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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2A_2_V
`define SKY130_FD_SC_HDLL__O2BB2A_2_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o2bb2a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o2bb2a_2 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o2bb2a_2 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2A_2_V
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_multi_mac_pcs_pma_gige.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac_pcs_pma_gige_phyip.v,v $
//
// $Revision: #2 $
// $Date: 2011/01/31 $
// Check in by : $Author: wyleong $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description :
//
// Top Level Triple Speed Ethernet(10/100/1000) MAC with MII/GMII
// interfaces, mdio module and register space (statistic, control and
// management)
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF;SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" } *)
module altera_tse_multi_mac_pcs_pma_gige_phyip
#(
parameter USE_SYNC_RESET = 0, // Use Synchronized Reset Inputs
parameter RESET_LEVEL = 1'b 1 , // Reset Active Level
parameter ENABLE_GMII_LOOPBACK = 1, // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1, // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter ENABLE_SUP_ADDR = 1, // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1, // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1, // STAT_CNT_ENA Enable Statistic Counters
parameter MDIO_CLK_DIV = 40 , // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3, // ALTERA Core Version
parameter CUST_VERSION = 1 , // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 0, // Enable the RGMII Interface
parameter ENABLE_MDIO = 1, // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1, // Enable magic packet detection
parameter ENABLE_PADDING = 1, // Enable padding operation.
parameter ENABLE_LGTH_CHECK = 1, // Enable frame length checking.
parameter GBIT_ONLY = 1, // Enable Gigabit only operation.
parameter MBIT_ONLY = 1, // Enable Megabit (10/100) only operation.
parameter REDUCED_CONTROL = 0, // Reduced control for MAC LITE
parameter CRC32DWIDTH = 4'b 1000, // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110, // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0, // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0, // false: merge enable
parameter ENABLE_SHIFT16 = 0, // Enable byte stuffing at packet header
parameter ENABLE_MAC_FLOW_CTRL = 1'b1, // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1, // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter PHY_IDENTIFIER = 32'h 00000000, // PHY Identifier
parameter DEV_VERSION = 16'h 0001 , // Customer Phy's Core Version
parameter ENABLE_SGMII = 1, // Enable SGMII logic for synthesis
parameter ENABLE_CLK_SHARING = 1, // Option to share clock for multiple channels (Clocks are rate-matched).
parameter ENABLE_REG_SHARING = 0, // Option to share register space. Uses certain hard-coded values from input.
parameter ENABLE_EXTENDED_STAT_REG = 0, // Enable a few extended statistic registers
parameter MAX_CHANNELS = 1, // The number of channels in Multi-TSE component
parameter ENABLE_PKT_CLASS = 1, // Enable Packet Classification Av-ST Interface
parameter ENABLE_RX_FIFO_STATUS = 1, // Enable Receive FIFO Almost Full status interface
parameter CHANNEL_WIDTH = 1, // The width of the channel interface
parameter EXPORT_PWRDN = 1'b0, // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX", // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b0, // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS IO
parameter ENABLE_ALT_RECONFIG = 0, // Option to expose the altreconfig ports
parameter SYNCHRONIZER_DEPTH = 3, // Number of synchronizer
// Internal parameters
parameter STARTING_CHANNEL_NUMBER = 0,
parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
(MAX_CHANNELS > 8)? 12 :
(MAX_CHANNELS > 4)? 11 :
(MAX_CHANNELS > 2)? 10 :
(MAX_CHANNELS > 1)? 9 : 8
)
// Port List
(
// RESET / MAC REG IF / MDIO
input wire reset, // Asynchronous Reset - clk Domain
input wire clk, // 25MHz Host Interface Clock
input wire read, // Register Read Strobe
input wire write, // Register Write Strobe
input wire [ADDR_WIDTH-1:0] address, // Register Address
input wire [31:0] writedata, // Write Data for Host Bus
output wire [31:0] readdata, // Read Data to Host Bus
output wire waitrequest, // Interface Busy
output wire mdc, // 2.5MHz Inteface
input wire mdio_in, // MDIO Input
output wire mdio_out, // MDIO Output
output wire mdio_oen, // MDIO Output Enable
// DEVICE SPECIFIC SIGNALS
input wire gxb_cal_blk_clk, // GXB Calibration Clock
input wire ref_clk, // Rference Clock
// SHARED CLK SIGNALS
output wire mac_rx_clk, // Av-ST Receive Clock
output wire mac_tx_clk, // Av-ST Transmit Clock
// SHARED RX STATUS
input wire rx_afull_clk, // Almost full clk
input wire [1:0] rx_afull_data, // Almost full data
input wire rx_afull_valid, // Almost full valid
input wire [CHANNEL_WIDTH-1:0] rx_afull_channel, // Almost full channel
// CHANNEL 0
// PCS SIGNALS TO PHY
input wire rxp_0, // Differential Receive Data
output wire txp_0, // Differential Transmit Data
output wire rx_recovclkout_0, // Receiver Recovered Clock
output wire led_crs_0, // Carrier Sense
output wire led_link_0, // Valid Link
output wire led_col_0, // Collision Indication
output wire led_an_0, // Auto-Negotiation Status
output wire led_char_err_0, // Character Error
output wire led_disp_err_0, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_0, // Av-ST Receive Clock
output wire mac_tx_clk_0, // Av-ST Transmit Clock
output wire data_rx_sop_0, // Start of Packet
output wire data_rx_eop_0, // End of Packet
output wire [7:0] data_rx_data_0, // Data from FIFO
output wire [4:0] data_rx_error_0, // Receive packet error
output wire data_rx_valid_0, // Data Receive FIFO Valid
input wire data_rx_ready_0, // Data Receive Ready
output wire [4:0] pkt_class_data_0, // Frame Type Indication
output wire pkt_class_valid_0, // Frame Type Indication Valid
input wire data_tx_error_0, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_0, // Data from FIFO transmit
input wire data_tx_valid_0, // Data FIFO transmit Empty
input wire data_tx_sop_0, // Start of Packet
input wire data_tx_eop_0, // END of Packet
output wire data_tx_ready_0, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_0, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_0, // Forward Current Frame with CRC from Application
input wire xoff_gen_0, // Xoff Pause frame generate
input wire xon_gen_0, // Xon Pause frame generate
input wire magic_sleep_n_0, // Enable Sleep Mode
output wire magic_wakeup_0, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_0, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_0, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_0, // address to PHYIP management interface
input wire phy_mgmt_read_0, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_0, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_0, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_0, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_0,// writedata to PHYIP management interface
// CHANNEL 1
// PCS SIGNALS TO PHY
input wire rxp_1, // Differential Receive Data
output wire txp_1, // Differential Transmit Data
output wire rx_recovclkout_1, // Receiver Recovered Clock
output wire led_crs_1, // Carrier Sense
output wire led_link_1, // Valid Link
output wire led_col_1, // Collision Indication
output wire led_an_1, // Auto-Negotiation Status
output wire led_char_err_1, // Character Error
output wire led_disp_err_1, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_1, // Av-ST Receive Clock
output wire mac_tx_clk_1, // Av-ST Transmit Clock
output wire data_rx_sop_1, // Start of Packet
output wire data_rx_eop_1, // End of Packet
output wire [7:0] data_rx_data_1, // Data from FIFO
output wire [4:0] data_rx_error_1, // Receive packet error
output wire data_rx_valid_1, // Data Receive FIFO Valid
input wire data_rx_ready_1, // Data Receive Ready
output wire [4:0] pkt_class_data_1, // Frame Type Indication
output wire pkt_class_valid_1, // Frame Type Indication Valid
input wire data_tx_error_1, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_1, // Data from FIFO transmit
input wire data_tx_valid_1, // Data FIFO transmit Empty
input wire data_tx_sop_1, // Start of Packet
input wire data_tx_eop_1, // END of Packet
output wire data_tx_ready_1, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_1, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_1, // Forward Current Frame with CRC from Application
input wire xoff_gen_1, // Xoff Pause frame generate
input wire xon_gen_1, // Xon Pause frame generate
input wire magic_sleep_n_1, // Enable Sleep Mode
output wire magic_wakeup_1, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_1, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_1, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_1, // address to PHYIP management interface
input wire phy_mgmt_read_1, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_1, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_1, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_1, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_1,// writedata to PHYIP management interface
// CHANNEL 2
// PCS SIGNALS TO PHY
input wire rxp_2, // Differential Receive Data
output wire txp_2, // Differential Transmit Data
output wire rx_recovclkout_2, // Receiver Recovered Clock
output wire led_crs_2, // Carrier Sense
output wire led_link_2, // Valid Link
output wire led_col_2, // Collision Indication
output wire led_an_2, // Auto-Negotiation Status
output wire led_char_err_2, // Character Error
output wire led_disp_err_2, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_2, // Av-ST Receive Clock
output wire mac_tx_clk_2, // Av-ST Transmit Clock
output wire data_rx_sop_2, // Start of Packet
output wire data_rx_eop_2, // End of Packet
output wire [7:0] data_rx_data_2, // Data from FIFO
output wire [4:0] data_rx_error_2, // Receive packet error
output wire data_rx_valid_2, // Data Receive FIFO Valid
input wire data_rx_ready_2, // Data Receive Ready
output wire [4:0] pkt_class_data_2, // Frame Type Indication
output wire pkt_class_valid_2, // Frame Type Indication Valid
input wire data_tx_error_2, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_2, // Data from FIFO transmit
input wire data_tx_valid_2, // Data FIFO transmit Empty
input wire data_tx_sop_2, // Start of Packet
input wire data_tx_eop_2, // END of Packet
output wire data_tx_ready_2, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_2, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_2, // Forward Current Frame with CRC from Application
input wire xoff_gen_2, // Xoff Pause frame generate
input wire xon_gen_2, // Xon Pause frame generate
input wire magic_sleep_n_2, // Enable Sleep Mode
output wire magic_wakeup_2, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_2, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_2, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_2, // address to PHYIP management interface
input wire phy_mgmt_read_2, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_2, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_2, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_2, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_2,// writedata to PHYIP management interface
// CHANNEL 3
// PCS SIGNALS TO PHY
input wire rxp_3, // Differential Receive Data
output wire txp_3, // Differential Transmit Data
output wire rx_recovclkout_3, // Receiver Recovered Clock
output wire led_crs_3, // Carrier Sense
output wire led_link_3, // Valid Link
output wire led_col_3, // Collision Indication
output wire led_an_3, // Auto-Negotiation Status
output wire led_char_err_3, // Character Error
output wire led_disp_err_3, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_3, // Av-ST Receive Clock
output wire mac_tx_clk_3, // Av-ST Transmit Clock
output wire data_rx_sop_3, // Start of Packet
output wire data_rx_eop_3, // End of Packet
output wire [7:0] data_rx_data_3, // Data from FIFO
output wire [4:0] data_rx_error_3, // Receive packet error
output wire data_rx_valid_3, // Data Receive FIFO Valid
input wire data_rx_ready_3, // Data Receive Ready
output wire [4:0] pkt_class_data_3, // Frame Type Indication
output wire pkt_class_valid_3, // Frame Type Indication Valid
input wire data_tx_error_3, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_3, // Data from FIFO transmit
input wire data_tx_valid_3, // Data FIFO transmit Empty
input wire data_tx_sop_3, // Start of Packet
input wire data_tx_eop_3, // END of Packet
output wire data_tx_ready_3, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_3, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_3, // Forward Current Frame with CRC from Application
input wire xoff_gen_3, // Xoff Pause frame generate
input wire xon_gen_3, // Xon Pause frame generate
input wire magic_sleep_n_3, // Enable Sleep Mode
output wire magic_wakeup_3, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_3, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_3, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_3, // address to PHYIP management interface
input wire phy_mgmt_read_3, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_3, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_3, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_3, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_3,// writedata to PHYIP management interface
// CHANNEL 4
// PCS SIGNALS TO PHY
input wire rxp_4, // Differential Receive Data
output wire txp_4, // Differential Transmit Data
output wire rx_recovclkout_4, // Receiver Recovered Clock
output wire led_crs_4, // Carrier Sense
output wire led_link_4, // Valid Link
output wire led_col_4, // Collision Indication
output wire led_an_4, // Auto-Negotiation Status
output wire led_char_err_4, // Character Error
output wire led_disp_err_4, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_4, // Av-ST Receive Clock
output wire mac_tx_clk_4, // Av-ST Transmit Clock
output wire data_rx_sop_4, // Start of Packet
output wire data_rx_eop_4, // End of Packet
output wire [7:0] data_rx_data_4, // Data from FIFO
output wire [4:0] data_rx_error_4, // Receive packet error
output wire data_rx_valid_4, // Data Receive FIFO Valid
input wire data_rx_ready_4, // Data Receive Ready
output wire [4:0] pkt_class_data_4, // Frame Type Indication
output wire pkt_class_valid_4, // Frame Type Indication Valid
input wire data_tx_error_4, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_4, // Data from FIFO transmit
input wire data_tx_valid_4, // Data FIFO transmit Empty
input wire data_tx_sop_4, // Start of Packet
input wire data_tx_eop_4, // END of Packet
output wire data_tx_ready_4, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_4, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_4, // Forward Current Frame with CRC from Application
input wire xoff_gen_4, // Xoff Pause frame generate
input wire xon_gen_4, // Xon Pause frame generate
input wire magic_sleep_n_4, // Enable Sleep Mode
output wire magic_wakeup_4, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_4, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_4, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_4, // address to PHYIP management interface
input wire phy_mgmt_read_4, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_4, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_4, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_4, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_4,// writedata to PHYIP management interface
// CHANNEL 5
// PCS SIGNALS TO PHY
input wire rxp_5, // Differential Receive Data
output wire txp_5, // Differential Transmit Data
output wire rx_recovclkout_5, // Receiver Recovered Clock
output wire led_crs_5, // Carrier Sense
output wire led_link_5, // Valid Link
output wire led_col_5, // Collision Indication
output wire led_an_5, // Auto-Negotiation Status
output wire led_char_err_5, // Character Error
output wire led_disp_err_5, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_5, // Av-ST Receive Clock
output wire mac_tx_clk_5, // Av-ST Transmit Clock
output wire data_rx_sop_5, // Start of Packet
output wire data_rx_eop_5, // End of Packet
output wire [7:0] data_rx_data_5, // Data from FIFO
output wire [4:0] data_rx_error_5, // Receive packet error
output wire data_rx_valid_5, // Data Receive FIFO Valid
input wire data_rx_ready_5, // Data Receive Ready
output wire [4:0] pkt_class_data_5, // Frame Type Indication
output wire pkt_class_valid_5, // Frame Type Indication Valid
input wire data_tx_error_5, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_5, // Data from FIFO transmit
input wire data_tx_valid_5, // Data FIFO transmit Empty
input wire data_tx_sop_5, // Start of Packet
input wire data_tx_eop_5, // END of Packet
output wire data_tx_ready_5, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_5, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_5, // Forward Current Frame with CRC from Application
input wire xoff_gen_5, // Xoff Pause frame generate
input wire xon_gen_5, // Xon Pause frame generate
input wire magic_sleep_n_5, // Enable Sleep Mode
output wire magic_wakeup_5, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_5, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_5, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_5, // address to PHYIP management interface
input wire phy_mgmt_read_5, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_5, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_5, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_5, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_5,// writedata to PHYIP management interface
// CHANNEL 6
// PCS SIGNALS TO PHY
input wire rxp_6, // Differential Receive Data
output wire txp_6, // Differential Transmit Data
output wire rx_recovclkout_6, // Receiver Recovered Clock
output wire led_crs_6, // Carrier Sense
output wire led_link_6, // Valid Link
output wire led_col_6, // Collision Indication
output wire led_an_6, // Auto-Negotiation Status
output wire led_char_err_6, // Character Error
output wire led_disp_err_6, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_6, // Av-ST Receive Clock
output wire mac_tx_clk_6, // Av-ST Transmit Clock
output wire data_rx_sop_6, // Start of Packet
output wire data_rx_eop_6, // End of Packet
output wire [7:0] data_rx_data_6, // Data from FIFO
output wire [4:0] data_rx_error_6, // Receive packet error
output wire data_rx_valid_6, // Data Receive FIFO Valid
input wire data_rx_ready_6, // Data Receive Ready
output wire [4:0] pkt_class_data_6, // Frame Type Indication
output wire pkt_class_valid_6, // Frame Type Indication Valid
input wire data_tx_error_6, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_6, // Data from FIFO transmit
input wire data_tx_valid_6, // Data FIFO transmit Empty
input wire data_tx_sop_6, // Start of Packet
input wire data_tx_eop_6, // END of Packet
output wire data_tx_ready_6, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_6, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_6, // Forward Current Frame with CRC from Application
input wire xoff_gen_6, // Xoff Pause frame generate
input wire xon_gen_6, // Xon Pause frame generate
input wire magic_sleep_n_6, // Enable Sleep Mode
output wire magic_wakeup_6, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_6, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_6, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_6, // address to PHYIP management interface
input wire phy_mgmt_read_6, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_6, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_6, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_6, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_6,// writedata to PHYIP management interface
// CHANNEL 7
// PCS SIGNALS TO PHY
input wire rxp_7, // Differential Receive Data
output wire txp_7, // Differential Transmit Data
output wire rx_recovclkout_7, // Receiver Recovered Clock
output wire led_crs_7, // Carrier Sense
output wire led_link_7, // Valid Link
output wire led_col_7, // Collision Indication
output wire led_an_7, // Auto-Negotiation Status
output wire led_char_err_7, // Character Error
output wire led_disp_err_7, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_7, // Av-ST Receive Clock
output wire mac_tx_clk_7, // Av-ST Transmit Clock
output wire data_rx_sop_7, // Start of Packet
output wire data_rx_eop_7, // End of Packet
output wire [7:0] data_rx_data_7, // Data from FIFO
output wire [4:0] data_rx_error_7, // Receive packet error
output wire data_rx_valid_7, // Data Receive FIFO Valid
input wire data_rx_ready_7, // Data Receive Ready
output wire [4:0] pkt_class_data_7, // Frame Type Indication
output wire pkt_class_valid_7, // Frame Type Indication Valid
input wire data_tx_error_7, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_7, // Data from FIFO transmit
input wire data_tx_valid_7, // Data FIFO transmit Empty
input wire data_tx_sop_7, // Start of Packet
input wire data_tx_eop_7, // END of Packet
output wire data_tx_ready_7, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_7, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_7, // Forward Current Frame with CRC from Application
input wire xoff_gen_7, // Xoff Pause frame generate
input wire xon_gen_7, // Xon Pause frame generate
input wire magic_sleep_n_7, // Enable Sleep Mode
output wire magic_wakeup_7, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_7, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_7, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_7, // address to PHYIP management interface
input wire phy_mgmt_read_7, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_7, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_7, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_7, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_7,// writedata to PHYIP management interface
// CHANNEL 8
// PCS SIGNALS TO PHY
input wire rxp_8, // Differential Receive Data
output wire txp_8, // Differential Transmit Data
output wire rx_recovclkout_8, // Receiver Recovered Clock
output wire led_crs_8, // Carrier Sense
output wire led_link_8, // Valid Link
output wire led_col_8, // Collision Indication
output wire led_an_8, // Auto-Negotiation Status
output wire led_char_err_8, // Character Error
output wire led_disp_err_8, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_8, // Av-ST Receive Clock
output wire mac_tx_clk_8, // Av-ST Transmit Clock
output wire data_rx_sop_8, // Start of Packet
output wire data_rx_eop_8, // End of Packet
output wire [7:0] data_rx_data_8, // Data from FIFO
output wire [4:0] data_rx_error_8, // Receive packet error
output wire data_rx_valid_8, // Data Receive FIFO Valid
input wire data_rx_ready_8, // Data Receive Ready
output wire [4:0] pkt_class_data_8, // Frame Type Indication
output wire pkt_class_valid_8, // Frame Type Indication Valid
input wire data_tx_error_8, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_8, // Data from FIFO transmit
input wire data_tx_valid_8, // Data FIFO transmit Empty
input wire data_tx_sop_8, // Start of Packet
input wire data_tx_eop_8, // END of Packet
output wire data_tx_ready_8, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_8, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_8, // Forward Current Frame with CRC from Application
input wire xoff_gen_8, // Xoff Pause frame generate
input wire xon_gen_8, // Xon Pause frame generate
input wire magic_sleep_n_8, // Enable Sleep Mode
output wire magic_wakeup_8, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_8, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_8, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_8, // address to PHYIP management interface
input wire phy_mgmt_read_8, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_8, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_8, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_8, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_8,// writedata to PHYIP management interface
// CHANNEL 9
// PCS SIGNALS TO PHY
input wire rxp_9, // Differential Receive Data
output wire txp_9, // Differential Transmit Data
output wire rx_recovclkout_9, // Receiver Recovered Clock
output wire led_crs_9, // Carrier Sense
output wire led_link_9, // Valid Link
output wire led_col_9, // Collision Indication
output wire led_an_9, // Auto-Negotiation Status
output wire led_char_err_9, // Character Error
output wire led_disp_err_9, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_9, // Av-ST Receive Clock
output wire mac_tx_clk_9, // Av-ST Transmit Clock
output wire data_rx_sop_9, // Start of Packet
output wire data_rx_eop_9, // End of Packet
output wire [7:0] data_rx_data_9, // Data from FIFO
output wire [4:0] data_rx_error_9, // Receive packet error
output wire data_rx_valid_9, // Data Receive FIFO Valid
input wire data_rx_ready_9, // Data Receive Ready
output wire [4:0] pkt_class_data_9, // Frame Type Indication
output wire pkt_class_valid_9, // Frame Type Indication Valid
input wire data_tx_error_9, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_9, // Data from FIFO transmit
input wire data_tx_valid_9, // Data FIFO transmit Empty
input wire data_tx_sop_9, // Start of Packet
input wire data_tx_eop_9, // END of Packet
output wire data_tx_ready_9, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_9, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_9, // Forward Current Frame with CRC from Application
input wire xoff_gen_9, // Xoff Pause frame generate
input wire xon_gen_9, // Xon Pause frame generate
input wire magic_sleep_n_9, // Enable Sleep Mode
output wire magic_wakeup_9, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_9, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_9, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_9, // address to PHYIP management interface
input wire phy_mgmt_read_9, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_9, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_9, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_9, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_9,// writedata to PHYIP management interface
// CHANNEL 10
// PCS SIGNALS TO PHY
input wire rxp_10, // Differential Receive Data
output wire txp_10, // Differential Transmit Data
output wire rx_recovclkout_10, // Receiver Recovered Clock
output wire led_crs_10, // Carrier Sense
output wire led_link_10, // Valid Link
output wire led_col_10, // Collision Indication
output wire led_an_10, // Auto-Negotiation Status
output wire led_char_err_10, // Character Error
output wire led_disp_err_10, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_10, // Av-ST Receive Clock
output wire mac_tx_clk_10, // Av-ST Transmit Clock
output wire data_rx_sop_10, // Start of Packet
output wire data_rx_eop_10, // End of Packet
output wire [7:0] data_rx_data_10, // Data from FIFO
output wire [4:0] data_rx_error_10, // Receive packet error
output wire data_rx_valid_10, // Data Receive FIFO Valid
input wire data_rx_ready_10, // Data Receive Ready
output wire [4:0] pkt_class_data_10, // Frame Type Indication
output wire pkt_class_valid_10, // Frame Type Indication Valid
input wire data_tx_error_10, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_10, // Data from FIFO transmit
input wire data_tx_valid_10, // Data FIFO transmit Empty
input wire data_tx_sop_10, // Start of Packet
input wire data_tx_eop_10, // END of Packet
output wire data_tx_ready_10, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_10, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_10, // Forward Current Frame with CRC from Application
input wire xoff_gen_10, // Xoff Pause frame generate
input wire xon_gen_10, // Xon Pause frame generate
input wire magic_sleep_n_10, // Enable Sleep Mode
output wire magic_wakeup_10, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_10, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_10, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_10, // address to PHYIP management interface
input wire phy_mgmt_read_10, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_10, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_10, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_10, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_10,// writedata to PHYIP management interface
// CHANNEL 11
// PCS SIGNALS TO PHY
input wire rxp_11, // Differential Receive Data
output wire txp_11, // Differential Transmit Data
output wire rx_recovclkout_11, // Receiver Recovered Clock
output wire led_crs_11, // Carrier Sense
output wire led_link_11, // Valid Link
output wire led_col_11, // Collision Indication
output wire led_an_11, // Auto-Negotiation Status
output wire led_char_err_11, // Character Error
output wire led_disp_err_11, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_11, // Av-ST Receive Clock
output wire mac_tx_clk_11, // Av-ST Transmit Clock
output wire data_rx_sop_11, // Start of Packet
output wire data_rx_eop_11, // End of Packet
output wire [7:0] data_rx_data_11, // Data from FIFO
output wire [4:0] data_rx_error_11, // Receive packet error
output wire data_rx_valid_11, // Data Receive FIFO Valid
input wire data_rx_ready_11, // Data Receive Ready
output wire [4:0] pkt_class_data_11, // Frame Type Indication
output wire pkt_class_valid_11, // Frame Type Indication Valid
input wire data_tx_error_11, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_11, // Data from FIFO transmit
input wire data_tx_valid_11, // Data FIFO transmit Empty
input wire data_tx_sop_11, // Start of Packet
input wire data_tx_eop_11, // END of Packet
output wire data_tx_ready_11, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_11, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_11, // Forward Current Frame with CRC from Application
input wire xoff_gen_11, // Xoff Pause frame generate
input wire xon_gen_11, // Xon Pause frame generate
input wire magic_sleep_n_11, // Enable Sleep Mode
output wire magic_wakeup_11, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_11, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_11, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_11, // address to PHYIP management interface
input wire phy_mgmt_read_11, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_11, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_11, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_11, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_11,// writedata to PHYIP management interface
// CHANNEL 12
// PCS SIGNALS TO PHY
input wire rxp_12, // Differential Receive Data
output wire txp_12, // Differential Transmit Data
output wire rx_recovclkout_12, // Receiver Recovered Clock
output wire led_crs_12, // Carrier Sense
output wire led_link_12, // Valid Link
output wire led_col_12, // Collision Indication
output wire led_an_12, // Auto-Negotiation Status
output wire led_char_err_12, // Character Error
output wire led_disp_err_12, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_12, // Av-ST Receive Clock
output wire mac_tx_clk_12, // Av-ST Transmit Clock
output wire data_rx_sop_12, // Start of Packet
output wire data_rx_eop_12, // End of Packet
output wire [7:0] data_rx_data_12, // Data from FIFO
output wire [4:0] data_rx_error_12, // Receive packet error
output wire data_rx_valid_12, // Data Receive FIFO Valid
input wire data_rx_ready_12, // Data Receive Ready
output wire [4:0] pkt_class_data_12, // Frame Type Indication
output wire pkt_class_valid_12, // Frame Type Indication Valid
input wire data_tx_error_12, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_12, // Data from FIFO transmit
input wire data_tx_valid_12, // Data FIFO transmit Empty
input wire data_tx_sop_12, // Start of Packet
input wire data_tx_eop_12, // END of Packet
output wire data_tx_ready_12, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_12, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_12, // Forward Current Frame with CRC from Application
input wire xoff_gen_12, // Xoff Pause frame generate
input wire xon_gen_12, // Xon Pause frame generate
input wire magic_sleep_n_12, // Enable Sleep Mode
output wire magic_wakeup_12, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_12, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_12, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_12, // address to PHYIP management interface
input wire phy_mgmt_read_12, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_12, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_12, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_12, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_12,// writedata to PHYIP management interface
// CHANNEL 13
// PCS SIGNALS TO PHY
input wire rxp_13, // Differential Receive Data
output wire txp_13, // Differential Transmit Data
output wire rx_recovclkout_13, // Receiver Recovered Clock
output wire led_crs_13, // Carrier Sense
output wire led_link_13, // Valid Link
output wire led_col_13, // Collision Indication
output wire led_an_13, // Auto-Negotiation Status
output wire led_char_err_13, // Character Error
output wire led_disp_err_13, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_13, // Av-ST Receive Clock
output wire mac_tx_clk_13, // Av-ST Transmit Clock
output wire data_rx_sop_13, // Start of Packet
output wire data_rx_eop_13, // End of Packet
output wire [7:0] data_rx_data_13, // Data from FIFO
output wire [4:0] data_rx_error_13, // Receive packet error
output wire data_rx_valid_13, // Data Receive FIFO Valid
input wire data_rx_ready_13, // Data Receive Ready
output wire [4:0] pkt_class_data_13, // Frame Type Indication
output wire pkt_class_valid_13, // Frame Type Indication Valid
input wire data_tx_error_13, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_13, // Data from FIFO transmit
input wire data_tx_valid_13, // Data FIFO transmit Empty
input wire data_tx_sop_13, // Start of Packet
input wire data_tx_eop_13, // END of Packet
output wire data_tx_ready_13, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_13, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_13, // Forward Current Frame with CRC from Application
input wire xoff_gen_13, // Xoff Pause frame generate
input wire xon_gen_13, // Xon Pause frame generate
input wire magic_sleep_n_13, // Enable Sleep Mode
output wire magic_wakeup_13, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_13, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_13, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_13, // address to PHYIP management interface
input wire phy_mgmt_read_13, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_13, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_13, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_13, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_13,// writedata to PHYIP management interface
// CHANNEL 14
// PCS SIGNALS TO PHY
input wire rxp_14, // Differential Receive Data
output wire txp_14, // Differential Transmit Data
output wire rx_recovclkout_14, // Receiver Recovered Clock
output wire led_crs_14, // Carrier Sense
output wire led_link_14, // Valid Link
output wire led_col_14, // Collision Indication
output wire led_an_14, // Auto-Negotiation Status
output wire led_char_err_14, // Character Error
output wire led_disp_err_14, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_14, // Av-ST Receive Clock
output wire mac_tx_clk_14, // Av-ST Transmit Clock
output wire data_rx_sop_14, // Start of Packet
output wire data_rx_eop_14, // End of Packet
output wire [7:0] data_rx_data_14, // Data from FIFO
output wire [4:0] data_rx_error_14, // Receive packet error
output wire data_rx_valid_14, // Data Receive FIFO Valid
input wire data_rx_ready_14, // Data Receive Ready
output wire [4:0] pkt_class_data_14, // Frame Type Indication
output wire pkt_class_valid_14, // Frame Type Indication Valid
input wire data_tx_error_14, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_14, // Data from FIFO transmit
input wire data_tx_valid_14, // Data FIFO transmit Empty
input wire data_tx_sop_14, // Start of Packet
input wire data_tx_eop_14, // END of Packet
output wire data_tx_ready_14, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_14, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_14, // Forward Current Frame with CRC from Application
input wire xoff_gen_14, // Xoff Pause frame generate
input wire xon_gen_14, // Xon Pause frame generate
input wire magic_sleep_n_14, // Enable Sleep Mode
output wire magic_wakeup_14, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_14, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_14, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_14, // address to PHYIP management interface
input wire phy_mgmt_read_14, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_14, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_14, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_14, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_14,// writedata to PHYIP management interface
// CHANNEL 15
// PCS SIGNALS TO PHY
input wire rxp_15, // Differential Receive Data
output wire txp_15, // Differential Transmit Data
output wire rx_recovclkout_15, // Receiver Recovered Clock
output wire led_crs_15, // Carrier Sense
output wire led_link_15, // Valid Link
output wire led_col_15, // Collision Indication
output wire led_an_15, // Auto-Negotiation Status
output wire led_char_err_15, // Character Error
output wire led_disp_err_15, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_15, // Av-ST Receive Clock
output wire mac_tx_clk_15, // Av-ST Transmit Clock
output wire data_rx_sop_15, // Start of Packet
output wire data_rx_eop_15, // End of Packet
output wire [7:0] data_rx_data_15, // Data from FIFO
output wire [4:0] data_rx_error_15, // Receive packet error
output wire data_rx_valid_15, // Data Receive FIFO Valid
input wire data_rx_ready_15, // Data Receive Ready
output wire [4:0] pkt_class_data_15, // Frame Type Indication
output wire pkt_class_valid_15, // Frame Type Indication Valid
input wire data_tx_error_15, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_15, // Data from FIFO transmit
input wire data_tx_valid_15, // Data FIFO transmit Empty
input wire data_tx_sop_15, // Start of Packet
input wire data_tx_eop_15, // END of Packet
output wire data_tx_ready_15, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_15, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_15, // Forward Current Frame with CRC from Application
input wire xoff_gen_15, // Xoff Pause frame generate
input wire xon_gen_15, // Xon Pause frame generate
input wire magic_sleep_n_15, // Enable Sleep Mode
output wire magic_wakeup_15, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_15, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_15, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_15, // address to PHYIP management interface
input wire phy_mgmt_read_15, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_15, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_15, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_15, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_15,// writedata to PHYIP management interface
// CHANNEL 16
// PCS SIGNALS TO PHY
input wire rxp_16, // Differential Receive Data
output wire txp_16, // Differential Transmit Data
output wire rx_recovclkout_16, // Receiver Recovered Clock
output wire led_crs_16, // Carrier Sense
output wire led_link_16, // Valid Link
output wire led_col_16, // Collision Indication
output wire led_an_16, // Auto-Negotiation Status
output wire led_char_err_16, // Character Error
output wire led_disp_err_16, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_16, // Av-ST Receive Clock
output wire mac_tx_clk_16, // Av-ST Transmit Clock
output wire data_rx_sop_16, // Start of Packet
output wire data_rx_eop_16, // End of Packet
output wire [7:0] data_rx_data_16, // Data from FIFO
output wire [4:0] data_rx_error_16, // Receive packet error
output wire data_rx_valid_16, // Data Receive FIFO Valid
input wire data_rx_ready_16, // Data Receive Ready
output wire [4:0] pkt_class_data_16, // Frame Type Indication
output wire pkt_class_valid_16, // Frame Type Indication Valid
input wire data_tx_error_16, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_16, // Data from FIFO transmit
input wire data_tx_valid_16, // Data FIFO transmit Empty
input wire data_tx_sop_16, // Start of Packet
input wire data_tx_eop_16, // END of Packet
output wire data_tx_ready_16, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_16, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_16, // Forward Current Frame with CRC from Application
input wire xoff_gen_16, // Xoff Pause frame generate
input wire xon_gen_16, // Xon Pause frame generate
input wire magic_sleep_n_16, // Enable Sleep Mode
output wire magic_wakeup_16, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_16, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_16, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_16, // address to PHYIP management interface
input wire phy_mgmt_read_16, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_16, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_16, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_16, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_16,// writedata to PHYIP management interface
// CHANNEL 17
// PCS SIGNALS TO PHY
input wire rxp_17, // Differential Receive Data
output wire txp_17, // Differential Transmit Data
output wire rx_recovclkout_17, // Receiver Recovered Clock
output wire led_crs_17, // Carrier Sense
output wire led_link_17, // Valid Link
output wire led_col_17, // Collision Indication
output wire led_an_17, // Auto-Negotiation Status
output wire led_char_err_17, // Character Error
output wire led_disp_err_17, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_17, // Av-ST Receive Clock
output wire mac_tx_clk_17, // Av-ST Transmit Clock
output wire data_rx_sop_17, // Start of Packet
output wire data_rx_eop_17, // End of Packet
output wire [7:0] data_rx_data_17, // Data from FIFO
output wire [4:0] data_rx_error_17, // Receive packet error
output wire data_rx_valid_17, // Data Receive FIFO Valid
input wire data_rx_ready_17, // Data Receive Ready
output wire [4:0] pkt_class_data_17, // Frame Type Indication
output wire pkt_class_valid_17, // Frame Type Indication Valid
input wire data_tx_error_17, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_17, // Data from FIFO transmit
input wire data_tx_valid_17, // Data FIFO transmit Empty
input wire data_tx_sop_17, // Start of Packet
input wire data_tx_eop_17, // END of Packet
output wire data_tx_ready_17, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_17, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_17, // Forward Current Frame with CRC from Application
input wire xoff_gen_17, // Xoff Pause frame generate
input wire xon_gen_17, // Xon Pause frame generate
input wire magic_sleep_n_17, // Enable Sleep Mode
output wire magic_wakeup_17, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_17, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_17, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_17, // address to PHYIP management interface
input wire phy_mgmt_read_17, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_17, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_17, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_17, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_17,// writedata to PHYIP management interface
// CHANNEL 18
// PCS SIGNALS TO PHY
input wire rxp_18, // Differential Receive Data
output wire txp_18, // Differential Transmit Data
output wire rx_recovclkout_18, // Receiver Recovered Clock
output wire led_crs_18, // Carrier Sense
output wire led_link_18, // Valid Link
output wire led_col_18, // Collision Indication
output wire led_an_18, // Auto-Negotiation Status
output wire led_char_err_18, // Character Error
output wire led_disp_err_18, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_18, // Av-ST Receive Clock
output wire mac_tx_clk_18, // Av-ST Transmit Clock
output wire data_rx_sop_18, // Start of Packet
output wire data_rx_eop_18, // End of Packet
output wire [7:0] data_rx_data_18, // Data from FIFO
output wire [4:0] data_rx_error_18, // Receive packet error
output wire data_rx_valid_18, // Data Receive FIFO Valid
input wire data_rx_ready_18, // Data Receive Ready
output wire [4:0] pkt_class_data_18, // Frame Type Indication
output wire pkt_class_valid_18, // Frame Type Indication Valid
input wire data_tx_error_18, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_18, // Data from FIFO transmit
input wire data_tx_valid_18, // Data FIFO transmit Empty
input wire data_tx_sop_18, // Start of Packet
input wire data_tx_eop_18, // END of Packet
output wire data_tx_ready_18, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_18, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_18, // Forward Current Frame with CRC from Application
input wire xoff_gen_18, // Xoff Pause frame generate
input wire xon_gen_18, // Xon Pause frame generate
input wire magic_sleep_n_18, // Enable Sleep Mode
output wire magic_wakeup_18, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_18, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_18, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_18, // address to PHYIP management interface
input wire phy_mgmt_read_18, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_18, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_18, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_18, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_18,// writedata to PHYIP management interface
// CHANNEL 19
// PCS SIGNALS TO PHY
input wire rxp_19, // Differential Receive Data
output wire txp_19, // Differential Transmit Data
output wire rx_recovclkout_19, // Receiver Recovered Clock
output wire led_crs_19, // Carrier Sense
output wire led_link_19, // Valid Link
output wire led_col_19, // Collision Indication
output wire led_an_19, // Auto-Negotiation Status
output wire led_char_err_19, // Character Error
output wire led_disp_err_19, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_19, // Av-ST Receive Clock
output wire mac_tx_clk_19, // Av-ST Transmit Clock
output wire data_rx_sop_19, // Start of Packet
output wire data_rx_eop_19, // End of Packet
output wire [7:0] data_rx_data_19, // Data from FIFO
output wire [4:0] data_rx_error_19, // Receive packet error
output wire data_rx_valid_19, // Data Receive FIFO Valid
input wire data_rx_ready_19, // Data Receive Ready
output wire [4:0] pkt_class_data_19, // Frame Type Indication
output wire pkt_class_valid_19, // Frame Type Indication Valid
input wire data_tx_error_19, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_19, // Data from FIFO transmit
input wire data_tx_valid_19, // Data FIFO transmit Empty
input wire data_tx_sop_19, // Start of Packet
input wire data_tx_eop_19, // END of Packet
output wire data_tx_ready_19, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_19, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_19, // Forward Current Frame with CRC from Application
input wire xoff_gen_19, // Xoff Pause frame generate
input wire xon_gen_19, // Xon Pause frame generate
input wire magic_sleep_n_19, // Enable Sleep Mode
output wire magic_wakeup_19, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_19, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_19, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_19, // address to PHYIP management interface
input wire phy_mgmt_read_19, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_19, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_19, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_19, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_19,// writedata to PHYIP management interface
// CHANNEL 20
// PCS SIGNALS TO PHY
input wire rxp_20, // Differential Receive Data
output wire txp_20, // Differential Transmit Data
output wire rx_recovclkout_20, // Receiver Recovered Clock
output wire led_crs_20, // Carrier Sense
output wire led_link_20, // Valid Link
output wire led_col_20, // Collision Indication
output wire led_an_20, // Auto-Negotiation Status
output wire led_char_err_20, // Character Error
output wire led_disp_err_20, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_20, // Av-ST Receive Clock
output wire mac_tx_clk_20, // Av-ST Transmit Clock
output wire data_rx_sop_20, // Start of Packet
output wire data_rx_eop_20, // End of Packet
output wire [7:0] data_rx_data_20, // Data from FIFO
output wire [4:0] data_rx_error_20, // Receive packet error
output wire data_rx_valid_20, // Data Receive FIFO Valid
input wire data_rx_ready_20, // Data Receive Ready
output wire [4:0] pkt_class_data_20, // Frame Type Indication
output wire pkt_class_valid_20, // Frame Type Indication Valid
input wire data_tx_error_20, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_20, // Data from FIFO transmit
input wire data_tx_valid_20, // Data FIFO transmit Empty
input wire data_tx_sop_20, // Start of Packet
input wire data_tx_eop_20, // END of Packet
output wire data_tx_ready_20, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_20, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_20, // Forward Current Frame with CRC from Application
input wire xoff_gen_20, // Xoff Pause frame generate
input wire xon_gen_20, // Xon Pause frame generate
input wire magic_sleep_n_20, // Enable Sleep Mode
output wire magic_wakeup_20, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_20, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_20, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_20, // address to PHYIP management interface
input wire phy_mgmt_read_20, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_20, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_20, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_20, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_20,// writedata to PHYIP management interface
// CHANNEL 21
// PCS SIGNALS TO PHY
input wire rxp_21, // Differential Receive Data
output wire txp_21, // Differential Transmit Data
output wire rx_recovclkout_21, // Receiver Recovered Clock
output wire led_crs_21, // Carrier Sense
output wire led_link_21, // Valid Link
output wire led_col_21, // Collision Indication
output wire led_an_21, // Auto-Negotiation Status
output wire led_char_err_21, // Character Error
output wire led_disp_err_21, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_21, // Av-ST Receive Clock
output wire mac_tx_clk_21, // Av-ST Transmit Clock
output wire data_rx_sop_21, // Start of Packet
output wire data_rx_eop_21, // End of Packet
output wire [7:0] data_rx_data_21, // Data from FIFO
output wire [4:0] data_rx_error_21, // Receive packet error
output wire data_rx_valid_21, // Data Receive FIFO Valid
input wire data_rx_ready_21, // Data Receive Ready
output wire [4:0] pkt_class_data_21, // Frame Type Indication
output wire pkt_class_valid_21, // Frame Type Indication Valid
input wire data_tx_error_21, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_21, // Data from FIFO transmit
input wire data_tx_valid_21, // Data FIFO transmit Empty
input wire data_tx_sop_21, // Start of Packet
input wire data_tx_eop_21, // END of Packet
output wire data_tx_ready_21, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_21, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_21, // Forward Current Frame with CRC from Application
input wire xoff_gen_21, // Xoff Pause frame generate
input wire xon_gen_21, // Xon Pause frame generate
input wire magic_sleep_n_21, // Enable Sleep Mode
output wire magic_wakeup_21, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_21, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_21, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_21, // address to PHYIP management interface
input wire phy_mgmt_read_21, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_21, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_21, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_21, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_21,// writedata to PHYIP management interface
// CHANNEL 22
// PCS SIGNALS TO PHY
input wire rxp_22, // Differential Receive Data
output wire txp_22, // Differential Transmit Data
output wire rx_recovclkout_22, // Receiver Recovered Clock
output wire led_crs_22, // Carrier Sense
output wire led_link_22, // Valid Link
output wire led_col_22, // Collision Indication
output wire led_an_22, // Auto-Negotiation Status
output wire led_char_err_22, // Character Error
output wire led_disp_err_22, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_22, // Av-ST Receive Clock
output wire mac_tx_clk_22, // Av-ST Transmit Clock
output wire data_rx_sop_22, // Start of Packet
output wire data_rx_eop_22, // End of Packet
output wire [7:0] data_rx_data_22, // Data from FIFO
output wire [4:0] data_rx_error_22, // Receive packet error
output wire data_rx_valid_22, // Data Receive FIFO Valid
input wire data_rx_ready_22, // Data Receive Ready
output wire [4:0] pkt_class_data_22, // Frame Type Indication
output wire pkt_class_valid_22, // Frame Type Indication Valid
input wire data_tx_error_22, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_22, // Data from FIFO transmit
input wire data_tx_valid_22, // Data FIFO transmit Empty
input wire data_tx_sop_22, // Start of Packet
input wire data_tx_eop_22, // END of Packet
output wire data_tx_ready_22, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_22, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_22, // Forward Current Frame with CRC from Application
input wire xoff_gen_22, // Xoff Pause frame generate
input wire xon_gen_22, // Xon Pause frame generate
input wire magic_sleep_n_22, // Enable Sleep Mode
output wire magic_wakeup_22, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_22, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_22, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_22, // address to PHYIP management interface
input wire phy_mgmt_read_22, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_22, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_22, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_22, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_22,// writedata to PHYIP management interface
// CHANNEL 23
// PCS SIGNALS TO PHY
input wire rxp_23, // Differential Receive Data
output wire txp_23, // Differential Transmit Data
output wire rx_recovclkout_23, // Receiver Recovered Clock
output wire led_crs_23, // Carrier Sense
output wire led_link_23, // Valid Link
output wire led_col_23, // Collision Indication
output wire led_an_23, // Auto-Negotiation Status
output wire led_char_err_23, // Character Error
output wire led_disp_err_23, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_23, // Av-ST Receive Clock
output wire mac_tx_clk_23, // Av-ST Transmit Clock
output wire data_rx_sop_23, // Start of Packet
output wire data_rx_eop_23, // End of Packet
output wire [7:0] data_rx_data_23, // Data from FIFO
output wire [4:0] data_rx_error_23, // Receive packet error
output wire data_rx_valid_23, // Data Receive FIFO Valid
input wire data_rx_ready_23, // Data Receive Ready
output wire [4:0] pkt_class_data_23, // Frame Type Indication
output wire pkt_class_valid_23, // Frame Type Indication Valid
input wire data_tx_error_23, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_23, // Data from FIFO transmit
input wire data_tx_valid_23, // Data FIFO transmit Empty
input wire data_tx_sop_23, // Start of Packet
input wire data_tx_eop_23, // END of Packet
output wire data_tx_ready_23, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_23, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_23, // Forward Current Frame with CRC from Application
input wire xoff_gen_23, // Xoff Pause frame generate
input wire xon_gen_23, // Xon Pause frame generate
input wire magic_sleep_n_23, // Enable Sleep Mode
output wire magic_wakeup_23, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_23, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_23, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_23, // address to PHYIP management interface
input wire phy_mgmt_read_23, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_23, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_23, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_23, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_23);// writedata to PHYIP management interface
wire MAC_PCS_reset;
wire [23:0] pcs_pwrdn_out_sig;
wire [23:0] gxb_pwrdn_in_sig;
wire gige_pma_reset;
wire [23:0] led_char_err_gx;
wire [23:0] link_status;
//wire [23:0] pcs_clk;
wire tx_pcs_clk_c0;
wire tx_pcs_clk_c1;
wire tx_pcs_clk_c2;
wire tx_pcs_clk_c3;
wire tx_pcs_clk_c4;
wire tx_pcs_clk_c5;
wire tx_pcs_clk_c6;
wire tx_pcs_clk_c7;
wire tx_pcs_clk_c8;
wire tx_pcs_clk_c9;
wire tx_pcs_clk_c10;
wire tx_pcs_clk_c11;
wire tx_pcs_clk_c12;
wire tx_pcs_clk_c13;
wire tx_pcs_clk_c14;
wire tx_pcs_clk_c15;
wire tx_pcs_clk_c16;
wire tx_pcs_clk_c17;
wire tx_pcs_clk_c18;
wire tx_pcs_clk_c19;
wire tx_pcs_clk_c20;
wire tx_pcs_clk_c21;
wire tx_pcs_clk_c22;
wire tx_pcs_clk_c23;
wire rx_pcs_clk_c0;
wire rx_pcs_clk_c1;
wire rx_pcs_clk_c2;
wire rx_pcs_clk_c3;
wire rx_pcs_clk_c4;
wire rx_pcs_clk_c5;
wire rx_pcs_clk_c6;
wire rx_pcs_clk_c7;
wire rx_pcs_clk_c8;
wire rx_pcs_clk_c9;
wire rx_pcs_clk_c10;
wire rx_pcs_clk_c11;
wire rx_pcs_clk_c12;
wire rx_pcs_clk_c13;
wire rx_pcs_clk_c14;
wire rx_pcs_clk_c15;
wire rx_pcs_clk_c16;
wire rx_pcs_clk_c17;
wire rx_pcs_clk_c18;
wire rx_pcs_clk_c19;
wire rx_pcs_clk_c20;
wire rx_pcs_clk_c21;
wire rx_pcs_clk_c22;
wire rx_pcs_clk_c23;
wire [23:0] rx_char_err_gx;
wire [23:0] rx_disp_err;
wire [23:0] rx_syncstatus;
wire [23:0] rx_runlengthviolation;
wire [23:0] rx_patterndetect;
wire [23:0] rx_runningdisp;
wire [23:0] rx_rmfifodatadeleted;
wire [23:0] rx_rmfifodatainserted;
wire [23:0] pcs_rx_rmfifodatadeleted;
wire [23:0] pcs_rx_rmfifodatainserted;
wire [23:0] pcs_rx_carrierdetected;
wire rx_kchar_0;
wire [7:0] rx_frame_0;
wire pcs_rx_kchar_0;
wire [7:0] pcs_rx_frame_0;
wire tx_kchar_0;
wire [7:0] tx_frame_0;
wire rx_kchar_1;
wire [7:0] rx_frame_1;
wire pcs_rx_kchar_1;
wire [7:0] pcs_rx_frame_1;
wire tx_kchar_1;
wire [7:0] tx_frame_1;
wire rx_kchar_2;
wire [7:0] rx_frame_2;
wire pcs_rx_kchar_2;
wire [7:0] pcs_rx_frame_2;
wire tx_kchar_2;
wire [7:0] tx_frame_2;
wire rx_kchar_3;
wire [7:0] rx_frame_3;
wire pcs_rx_kchar_3;
wire [7:0] pcs_rx_frame_3;
wire tx_kchar_3;
wire [7:0] tx_frame_3;
wire rx_kchar_4;
wire [7:0] rx_frame_4;
wire pcs_rx_kchar_4;
wire [7:0] pcs_rx_frame_4;
wire tx_kchar_4;
wire [7:0] tx_frame_4;
wire rx_kchar_5;
wire [7:0] rx_frame_5;
wire pcs_rx_kchar_5;
wire [7:0] pcs_rx_frame_5;
wire tx_kchar_5;
wire [7:0] tx_frame_5;
wire rx_kchar_6;
wire [7:0] rx_frame_6;
wire pcs_rx_kchar_6;
wire [7:0] pcs_rx_frame_6;
wire tx_kchar_6;
wire [7:0] tx_frame_6;
wire rx_kchar_7;
wire [7:0] rx_frame_7;
wire pcs_rx_kchar_7;
wire [7:0] pcs_rx_frame_7;
wire tx_kchar_7;
wire [7:0] tx_frame_7;
wire rx_kchar_8;
wire [7:0] rx_frame_8;
wire pcs_rx_kchar_8;
wire [7:0] pcs_rx_frame_8;
wire tx_kchar_8;
wire [7:0] tx_frame_8;
wire rx_kchar_9;
wire [7:0] rx_frame_9;
wire pcs_rx_kchar_9;
wire [7:0] pcs_rx_frame_9;
wire tx_kchar_9;
wire [7:0] tx_frame_9;
wire rx_kchar_10;
wire [7:0] rx_frame_10;
wire pcs_rx_kchar_10;
wire [7:0] pcs_rx_frame_10;
wire tx_kchar_10;
wire [7:0] tx_frame_10;
wire rx_kchar_11;
wire [7:0] rx_frame_11;
wire pcs_rx_kchar_11;
wire [7:0] pcs_rx_frame_11;
wire tx_kchar_11;
wire [7:0] tx_frame_11;
wire rx_kchar_12;
wire [7:0] rx_frame_12;
wire pcs_rx_kchar_12;
wire [7:0] pcs_rx_frame_12;
wire tx_kchar_12;
wire [7:0] tx_frame_12;
wire rx_kchar_13;
wire [7:0] rx_frame_13;
wire pcs_rx_kchar_13;
wire [7:0] pcs_rx_frame_13;
wire tx_kchar_13;
wire [7:0] tx_frame_13;
wire rx_kchar_14;
wire [7:0] rx_frame_14;
wire pcs_rx_kchar_14;
wire [7:0] pcs_rx_frame_14;
wire tx_kchar_14;
wire [7:0] tx_frame_14;
wire rx_kchar_15;
wire [7:0] rx_frame_15;
wire pcs_rx_kchar_15;
wire [7:0] pcs_rx_frame_15;
wire tx_kchar_15;
wire [7:0] tx_frame_15;
wire rx_kchar_16;
wire [7:0] rx_frame_16;
wire pcs_rx_kchar_16;
wire [7:0] pcs_rx_frame_16;
wire tx_kchar_16;
wire [7:0] tx_frame_16;
wire rx_kchar_17;
wire [7:0] rx_frame_17;
wire pcs_rx_kchar_17;
wire [7:0] pcs_rx_frame_17;
wire tx_kchar_17;
wire [7:0] tx_frame_17;
wire rx_kchar_18;
wire [7:0] rx_frame_18;
wire pcs_rx_kchar_18;
wire [7:0] pcs_rx_frame_18;
wire tx_kchar_18;
wire [7:0] tx_frame_18;
wire rx_kchar_19;
wire [7:0] rx_frame_19;
wire pcs_rx_kchar_19;
wire [7:0] pcs_rx_frame_19;
wire tx_kchar_19;
wire [7:0] tx_frame_19;
wire rx_kchar_20;
wire [7:0] rx_frame_20;
wire pcs_rx_kchar_20;
wire [7:0] pcs_rx_frame_20;
wire tx_kchar_20;
wire [7:0] tx_frame_20;
wire rx_kchar_21;
wire [7:0] rx_frame_21;
wire pcs_rx_kchar_21;
wire [7:0] pcs_rx_frame_21;
wire tx_kchar_21;
wire [7:0] tx_frame_21;
wire rx_kchar_22;
wire [7:0] rx_frame_22;
wire pcs_rx_kchar_22;
wire [7:0] pcs_rx_frame_22;
wire tx_kchar_22;
wire [7:0] tx_frame_22;
wire rx_kchar_23;
wire [7:0] rx_frame_23;
wire pcs_rx_kchar_23;
wire [7:0] pcs_rx_frame_23;
wire tx_kchar_23;
wire [7:0] tx_frame_23;
wire sd_loopback_0;
wire sd_loopback_1;
wire sd_loopback_2;
wire sd_loopback_3;
wire sd_loopback_4;
wire sd_loopback_5;
wire sd_loopback_6;
wire sd_loopback_7;
wire sd_loopback_8;
wire sd_loopback_9;
wire sd_loopback_10;
wire sd_loopback_11;
wire sd_loopback_12;
wire sd_loopback_13;
wire sd_loopback_14;
wire sd_loopback_15;
wire sd_loopback_16;
wire sd_loopback_17;
wire sd_loopback_18;
wire sd_loopback_19;
wire sd_loopback_20;
wire sd_loopback_21;
wire sd_loopback_22;
wire sd_loopback_23;
wire reset_rx_pcs_clk_c0_int;
wire reset_rx_pcs_clk_c1_int;
wire reset_rx_pcs_clk_c2_int;
wire reset_rx_pcs_clk_c3_int;
wire reset_rx_pcs_clk_c4_int;
wire reset_rx_pcs_clk_c5_int;
wire reset_rx_pcs_clk_c6_int;
wire reset_rx_pcs_clk_c7_int;
wire reset_rx_pcs_clk_c8_int;
wire reset_rx_pcs_clk_c9_int;
wire reset_rx_pcs_clk_c10_int;
wire reset_rx_pcs_clk_c11_int;
wire reset_rx_pcs_clk_c12_int;
wire reset_rx_pcs_clk_c13_int;
wire reset_rx_pcs_clk_c14_int;
wire reset_rx_pcs_clk_c15_int;
wire reset_rx_pcs_clk_c16_int;
wire reset_rx_pcs_clk_c17_int;
wire reset_rx_pcs_clk_c18_int;
wire reset_rx_pcs_clk_c19_int;
wire reset_rx_pcs_clk_c20_int;
wire reset_rx_pcs_clk_c21_int;
wire reset_rx_pcs_clk_c22_int;
wire reset_rx_pcs_clk_c23_int;
//assign pcs_clk = {pcs_clk_c23,pcs_clk_c22,pcs_clk_c21,pcs_clk_c20,pcs_clk_c19,pcs_clk_c18,pcs_clk_c17,pcs_clk_c16,pcs_clk_c15,pcs_clk_c14,pcs_clk_c13,pcs_clk_c12,pcs_clk_c11,pcs_clk_c10,pcs_clk_c9,pcs_clk_c8,pcs_clk_c7,pcs_clk_c6,pcs_clk_c5,pcs_clk_c4,pcs_clk_c3,pcs_clk_c2,pcs_clk_c1,pcs_clk_c0};
// Assign the character error and link status to top level leds
// ------------------------------------------------------------
assign led_char_err_0 = led_char_err_gx[0];
assign led_link_0 = link_status[0];
assign led_char_err_1 = led_char_err_gx[1];
assign led_link_1 = link_status[1];
assign led_char_err_2 = led_char_err_gx[2];
assign led_link_2 = link_status[2];
assign led_char_err_3 = led_char_err_gx[3];
assign led_link_3 = link_status[3];
assign led_char_err_4 = led_char_err_gx[4];
assign led_link_4 = link_status[4];
assign led_char_err_5 = led_char_err_gx[5];
assign led_link_5 = link_status[5];
assign led_char_err_6 = led_char_err_gx[6];
assign led_link_6 = link_status[6];
assign led_char_err_7 = led_char_err_gx[7];
assign led_link_7 = link_status[7];
assign led_char_err_8 = led_char_err_gx[8];
assign led_link_8 = link_status[8];
assign led_char_err_9 = led_char_err_gx[9];
assign led_link_9 = link_status[9];
assign led_char_err_10 = led_char_err_gx[10];
assign led_link_10 = link_status[10];
assign led_char_err_11 = led_char_err_gx[11];
assign led_link_11 = link_status[11];
assign led_char_err_12 = led_char_err_gx[12];
assign led_link_12 = link_status[12];
assign led_char_err_13 = led_char_err_gx[13];
assign led_link_13 = link_status[13];
assign led_char_err_14 = led_char_err_gx[14];
assign led_link_14 = link_status[14];
assign led_char_err_15 = led_char_err_gx[15];
assign led_link_15 = link_status[15];
assign led_char_err_16 = led_char_err_gx[16];
assign led_link_16 = link_status[16];
assign led_char_err_17 = led_char_err_gx[17];
assign led_link_17 = link_status[17];
assign led_char_err_18 = led_char_err_gx[18];
assign led_link_18 = link_status[18];
assign led_char_err_19 = led_char_err_gx[19];
assign led_link_19 = link_status[19];
assign led_char_err_20 = led_char_err_gx[20];
assign led_link_20 = link_status[20];
assign led_char_err_21 = led_char_err_gx[21];
assign led_link_21 = link_status[21];
assign led_char_err_22 = led_char_err_gx[22];
assign led_link_22 = link_status[22];
assign led_char_err_23 = led_char_err_gx[23];
assign led_link_23 = link_status[23];
// Instantiation of the MAC_PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_top_multi_mac_pcs_gige U_MULTI_MAC_PCS(
.reset(reset), //INPUT : ASYNCHRONOUS RESET - clk DOMAIN
.clk(clk), //INPUT : CLOCK
.read(read), //INPUT : REGISTER READ TRANSACTION
.ref_clk(ref_clk), //INPUT : REFERENCE CLOCK
.write(write), //INPUT : REGISTER WRITE TRANSACTION
.address(address), //INPUT : REGISTER ADDRESS
.writedata(writedata), //INPUT : REGISTER WRITE DATA
.readdata(readdata), //OUTPUT : REGISTER READ DATA
.waitrequest(waitrequest), //OUTPUT : TRANSACTION BUSY, ACTIVE LOW
.mdc(mdc), //OUTPUT : MDIO Clock
.mdio_out(mdio_out), //OUTPUT : Outgoing MDIO DATA
.mdio_in(mdio_in), //INPUT : Incoming MDIO DATA
.mdio_oen(mdio_oen), //OUTPUT : MDIO Output Enable
.mac_rx_clk(mac_rx_clk), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
.rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
.rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
.rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
.rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
// Channel 0
.rx_carrierdetected_0(pcs_rx_carrierdetected[0]),
.rx_rmfifodatadeleted_0(pcs_rx_rmfifodatadeleted[0]),
.rx_rmfifodatainserted_0(pcs_rx_rmfifodatainserted[0]),
.rx_clkout_0(rx_pcs_clk_c0), //INPUT : Receive Clock
.tx_clkout_0(tx_pcs_clk_c0), //INPUT : Transmit Clock
.rx_kchar_0(pcs_rx_kchar_0), //INPUT : Special Character Indication
.tx_kchar_0(tx_kchar_0), //OUTPUT : Special Character Indication
.rx_frame_0(pcs_rx_frame_0), //INPUT : Frame
.tx_frame_0(tx_frame_0), //OUTPUT : Frame
.sd_loopback_0(sd_loopback_0), //OUTPUT : SERDES Loopback Enable
.powerdown_0(pcs_pwrdn_out_sig[0]), //OUTPUT : Powerdown Enable
.led_col_0(led_col_0), //OUTPUT : Collision Indication
.led_an_0(led_an_0), //OUTPUT : Auto Negotiation Status
.led_char_err_0(led_char_err_gx[0]), //INPUT : Character error
.led_crs_0(led_crs_0), //OUTPUT : Carrier sense
.led_link_0(link_status[0]), //INPUT : Valid link
.mac_rx_clk_0(mac_rx_clk_0), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_0(mac_tx_clk_0), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_0(data_rx_sop_0), //OUTPUT : Start of Packet
.data_rx_eop_0(data_rx_eop_0), //OUTPUT : End of Packet
.data_rx_data_0(data_rx_data_0), //OUTPUT : Data from FIFO
.data_rx_error_0(data_rx_error_0), //OUTPUT : Receive packet error
.data_rx_valid_0(data_rx_valid_0), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_0(data_rx_ready_0), //OUTPUT : Data Receive Ready
.pkt_class_data_0(pkt_class_data_0), //OUTPUT : Frame Type Indication
.pkt_class_valid_0(pkt_class_valid_0), //OUTPUT : Frame Type Indication Valid
.data_tx_error_0(data_tx_error_0), //INPUT : Status
.data_tx_data_0(data_tx_data_0), //INPUT : Data from FIFO transmit
.data_tx_valid_0(data_tx_valid_0), //INPUT : Data FIFO transmit Empty
.data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
.data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
.data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 1
.rx_carrierdetected_1(pcs_rx_carrierdetected[1]),
.rx_rmfifodatadeleted_1(pcs_rx_rmfifodatadeleted[1]),
.rx_rmfifodatainserted_1(pcs_rx_rmfifodatainserted[1]),
.rx_clkout_1(rx_pcs_clk_c1), //INPUT : Receive Clock
.tx_clkout_1(tx_pcs_clk_c1), //INPUT : Transmit Clock
.rx_kchar_1(pcs_rx_kchar_1), //INPUT : Special Character Indication
.tx_kchar_1(tx_kchar_1), //OUTPUT : Special Character Indication
.rx_frame_1(pcs_rx_frame_1), //INPUT : Frame
.tx_frame_1(tx_frame_1), //OUTPUT : Frame
.sd_loopback_1(sd_loopback_1), //OUTPUT : SERDES Loopback Enable
.powerdown_1(pcs_pwrdn_out_sig[1]), //OUTPUT : Powerdown Enable
.led_col_1(led_col_1), //OUTPUT : Collision Indication
.led_an_1(led_an_1), //OUTPUT : Auto Negotiation Status
.led_char_err_1(led_char_err_gx[1]), //INPUT : Character error
.led_crs_1(led_crs_1), //OUTPUT : Carrier sense
.led_link_1(link_status[1]), //INPUT : Valid link
.mac_rx_clk_1(mac_rx_clk_1), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_1(mac_tx_clk_1), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_1(data_rx_sop_1), //OUTPUT : Start of Packet
.data_rx_eop_1(data_rx_eop_1), //OUTPUT : End of Packet
.data_rx_data_1(data_rx_data_1), //OUTPUT : Data from FIFO
.data_rx_error_1(data_rx_error_1), //OUTPUT : Receive packet error
.data_rx_valid_1(data_rx_valid_1), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_1(data_rx_ready_1), //OUTPUT : Data Receive Ready
.pkt_class_data_1(pkt_class_data_1), //OUTPUT : Frame Type Indication
.pkt_class_valid_1(pkt_class_valid_1), //OUTPUT : Frame Type Indication Valid
.data_tx_error_1(data_tx_error_1), //INPUT : Status
.data_tx_data_1(data_tx_data_1), //INPUT : Data from FIFO transmit
.data_tx_valid_1(data_tx_valid_1), //INPUT : Data FIFO transmit Empty
.data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
.data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
.data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 2
.rx_carrierdetected_2(pcs_rx_carrierdetected[2]),
.rx_rmfifodatadeleted_2(pcs_rx_rmfifodatadeleted[2]),
.rx_rmfifodatainserted_2(pcs_rx_rmfifodatainserted[2]),
.rx_clkout_2(rx_pcs_clk_c2), //INPUT : Receive Clock
.tx_clkout_2(tx_pcs_clk_c2), //INPUT : Transmit Clock
.rx_kchar_2(pcs_rx_kchar_2), //INPUT : Special Character Indication
.tx_kchar_2(tx_kchar_2), //OUTPUT : Special Character Indication
.rx_frame_2(pcs_rx_frame_2), //INPUT : Frame
.tx_frame_2(tx_frame_2), //OUTPUT : Frame
.sd_loopback_2(sd_loopback_2), //OUTPUT : SERDES Loopback Enable
.powerdown_2(pcs_pwrdn_out_sig[2]), //OUTPUT : Powerdown Enable
.led_col_2(led_col_2), //OUTPUT : Collision Indication
.led_an_2(led_an_2), //OUTPUT : Auto Negotiation Status
.led_char_err_2(led_char_err_gx[2]), //INPUT : Character error
.led_crs_2(led_crs_2), //OUTPUT : Carrier sense
.led_link_2(link_status[2]), //INPUT : Valid link
.mac_rx_clk_2(mac_rx_clk_2), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_2(mac_tx_clk_2), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_2(data_rx_sop_2), //OUTPUT : Start of Packet
.data_rx_eop_2(data_rx_eop_2), //OUTPUT : End of Packet
.data_rx_data_2(data_rx_data_2), //OUTPUT : Data from FIFO
.data_rx_error_2(data_rx_error_2), //OUTPUT : Receive packet error
.data_rx_valid_2(data_rx_valid_2), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_2(data_rx_ready_2), //OUTPUT : Data Receive Ready
.pkt_class_data_2(pkt_class_data_2), //OUTPUT : Frame Type Indication
.pkt_class_valid_2(pkt_class_valid_2), //OUTPUT : Frame Type Indication Valid
.data_tx_error_2(data_tx_error_2), //INPUT : Status
.data_tx_data_2(data_tx_data_2), //INPUT : Data from FIFO transmit
.data_tx_valid_2(data_tx_valid_2), //INPUT : Data FIFO transmit Empty
.data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
.data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
.data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 3
.rx_carrierdetected_3(pcs_rx_carrierdetected[3]),
.rx_rmfifodatadeleted_3(pcs_rx_rmfifodatadeleted[3]),
.rx_rmfifodatainserted_3(pcs_rx_rmfifodatainserted[3]),
.rx_clkout_3(rx_pcs_clk_c3), //INPUT : Receive Clock
.tx_clkout_3(tx_pcs_clk_c3), //INPUT : Transmit Clock
.rx_kchar_3(pcs_rx_kchar_3), //INPUT : Special Character Indication
.tx_kchar_3(tx_kchar_3), //OUTPUT : Special Character Indication
.rx_frame_3(pcs_rx_frame_3), //INPUT : Frame
.tx_frame_3(tx_frame_3), //OUTPUT : Frame
.sd_loopback_3(sd_loopback_3), //OUTPUT : SERDES Loopback Enable
.powerdown_3(pcs_pwrdn_out_sig[3]), //OUTPUT : Powerdown Enable
.led_col_3(led_col_3), //OUTPUT : Collision Indication
.led_an_3(led_an_3), //OUTPUT : Auto Negotiation Status
.led_char_err_3(led_char_err_gx[3]), //INPUT : Character error
.led_crs_3(led_crs_3), //OUTPUT : Carrier sense
.led_link_3(link_status[3]), //INPUT : Valid link
.mac_rx_clk_3(mac_rx_clk_3), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_3(mac_tx_clk_3), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_3(data_rx_sop_3), //OUTPUT : Start of Packet
.data_rx_eop_3(data_rx_eop_3), //OUTPUT : End of Packet
.data_rx_data_3(data_rx_data_3), //OUTPUT : Data from FIFO
.data_rx_error_3(data_rx_error_3), //OUTPUT : Receive packet error
.data_rx_valid_3(data_rx_valid_3), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_3(data_rx_ready_3), //OUTPUT : Data Receive Ready
.pkt_class_data_3(pkt_class_data_3), //OUTPUT : Frame Type Indication
.pkt_class_valid_3(pkt_class_valid_3), //OUTPUT : Frame Type Indication Valid
.data_tx_error_3(data_tx_error_3), //INPUT : Status
.data_tx_data_3(data_tx_data_3), //INPUT : Data from FIFO transmit
.data_tx_valid_3(data_tx_valid_3), //INPUT : Data FIFO transmit Empty
.data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
.data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
.data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 4
.rx_carrierdetected_4(pcs_rx_carrierdetected[4]),
.rx_rmfifodatadeleted_4(pcs_rx_rmfifodatadeleted[4]),
.rx_rmfifodatainserted_4(pcs_rx_rmfifodatainserted[4]),
.rx_clkout_4(rx_pcs_clk_c4), //INPUT : Receive Clock
.tx_clkout_4(tx_pcs_clk_c4), //INPUT : Transmit Clock
.rx_kchar_4(pcs_rx_kchar_4), //INPUT : Special Character Indication
.tx_kchar_4(tx_kchar_4), //OUTPUT : Special Character Indication
.rx_frame_4(pcs_rx_frame_4), //INPUT : Frame
.tx_frame_4(tx_frame_4), //OUTPUT : Frame
.sd_loopback_4(sd_loopback_4), //OUTPUT : SERDES Loopback Enable
.powerdown_4(pcs_pwrdn_out_sig[4]), //OUTPUT : Powerdown Enable
.led_col_4(led_col_4), //OUTPUT : Collision Indication
.led_an_4(led_an_4), //OUTPUT : Auto Negotiation Status
.led_char_err_4(led_char_err_gx[4]), //INPUT : Character error
.led_crs_4(led_crs_4), //OUTPUT : Carrier sense
.led_link_4(link_status[4]), //INPUT : Valid link
.mac_rx_clk_4(mac_rx_clk_4), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_4(mac_tx_clk_4), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_4(data_rx_sop_4), //OUTPUT : Start of Packet
.data_rx_eop_4(data_rx_eop_4), //OUTPUT : End of Packet
.data_rx_data_4(data_rx_data_4), //OUTPUT : Data from FIFO
.data_rx_error_4(data_rx_error_4), //OUTPUT : Receive packet error
.data_rx_valid_4(data_rx_valid_4), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_4(data_rx_ready_4), //OUTPUT : Data Receive Ready
.pkt_class_data_4(pkt_class_data_4), //OUTPUT : Frame Type Indication
.pkt_class_valid_4(pkt_class_valid_4), //OUTPUT : Frame Type Indication Valid
.data_tx_error_4(data_tx_error_4), //INPUT : Status
.data_tx_data_4(data_tx_data_4), //INPUT : Data from FIFO transmit
.data_tx_valid_4(data_tx_valid_4), //INPUT : Data FIFO transmit Empty
.data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
.data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
.data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 5
.rx_carrierdetected_5(pcs_rx_carrierdetected[5]),
.rx_rmfifodatadeleted_5(pcs_rx_rmfifodatadeleted[5]),
.rx_rmfifodatainserted_5(pcs_rx_rmfifodatainserted[5]),
.rx_clkout_5(rx_pcs_clk_c5), //INPUT : Receive Clock
.tx_clkout_5(tx_pcs_clk_c5), //INPUT : Transmit Clock
.rx_kchar_5(pcs_rx_kchar_5), //INPUT : Special Character Indication
.tx_kchar_5(tx_kchar_5), //OUTPUT : Special Character Indication
.rx_frame_5(pcs_rx_frame_5), //INPUT : Frame
.tx_frame_5(tx_frame_5), //OUTPUT : Frame
.sd_loopback_5(sd_loopback_5), //OUTPUT : SERDES Loopback Enable
.powerdown_5(pcs_pwrdn_out_sig[5]), //OUTPUT : Powerdown Enable
.led_col_5(led_col_5), //OUTPUT : Collision Indication
.led_an_5(led_an_5), //OUTPUT : Auto Negotiation Status
.led_char_err_5(led_char_err_gx[5]), //INPUT : Character error
.led_crs_5(led_crs_5), //OUTPUT : Carrier sense
.led_link_5(link_status[5]), //INPUT : Valid link
.mac_rx_clk_5(mac_rx_clk_5), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_5(mac_tx_clk_5), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_5(data_rx_sop_5), //OUTPUT : Start of Packet
.data_rx_eop_5(data_rx_eop_5), //OUTPUT : End of Packet
.data_rx_data_5(data_rx_data_5), //OUTPUT : Data from FIFO
.data_rx_error_5(data_rx_error_5), //OUTPUT : Receive packet error
.data_rx_valid_5(data_rx_valid_5), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_5(data_rx_ready_5), //OUTPUT : Data Receive Ready
.pkt_class_data_5(pkt_class_data_5), //OUTPUT : Frame Type Indication
.pkt_class_valid_5(pkt_class_valid_5), //OUTPUT : Frame Type Indication Valid
.data_tx_error_5(data_tx_error_5), //INPUT : Status
.data_tx_data_5(data_tx_data_5), //INPUT : Data from FIFO transmit
.data_tx_valid_5(data_tx_valid_5), //INPUT : Data FIFO transmit Empty
.data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
.data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
.data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 6
.rx_carrierdetected_6(pcs_rx_carrierdetected[6]),
.rx_rmfifodatadeleted_6(pcs_rx_rmfifodatadeleted[6]),
.rx_rmfifodatainserted_6(pcs_rx_rmfifodatainserted[6]),
.rx_clkout_6(rx_pcs_clk_c6), //INPUT : Receive Clock
.tx_clkout_6(tx_pcs_clk_c6), //INPUT : Transmit Clock
.rx_kchar_6(pcs_rx_kchar_6), //INPUT : Special Character Indication
.tx_kchar_6(tx_kchar_6), //OUTPUT : Special Character Indication
.rx_frame_6(pcs_rx_frame_6), //INPUT : Frame
.tx_frame_6(tx_frame_6), //OUTPUT : Frame
.sd_loopback_6(sd_loopback_6), //OUTPUT : SERDES Loopback Enable
.powerdown_6(pcs_pwrdn_out_sig[6]), //OUTPUT : Powerdown Enable
.led_col_6(led_col_6), //OUTPUT : Collision Indication
.led_an_6(led_an_6), //OUTPUT : Auto Negotiation Status
.led_char_err_6(led_char_err_gx[6]), //INPUT : Character error
.led_crs_6(led_crs_6), //OUTPUT : Carrier sense
.led_link_6(link_status[6]), //INPUT : Valid link
.mac_rx_clk_6(mac_rx_clk_6), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_6(mac_tx_clk_6), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_6(data_rx_sop_6), //OUTPUT : Start of Packet
.data_rx_eop_6(data_rx_eop_6), //OUTPUT : End of Packet
.data_rx_data_6(data_rx_data_6), //OUTPUT : Data from FIFO
.data_rx_error_6(data_rx_error_6), //OUTPUT : Receive packet error
.data_rx_valid_6(data_rx_valid_6), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_6(data_rx_ready_6), //OUTPUT : Data Receive Ready
.pkt_class_data_6(pkt_class_data_6), //OUTPUT : Frame Type Indication
.pkt_class_valid_6(pkt_class_valid_6), //OUTPUT : Frame Type Indication Valid
.data_tx_error_6(data_tx_error_6), //INPUT : Status
.data_tx_data_6(data_tx_data_6), //INPUT : Data from FIFO transmit
.data_tx_valid_6(data_tx_valid_6), //INPUT : Data FIFO transmit Empty
.data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
.data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
.data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 7
.rx_carrierdetected_7(pcs_rx_carrierdetected[7]),
.rx_rmfifodatadeleted_7(pcs_rx_rmfifodatadeleted[7]),
.rx_rmfifodatainserted_7(pcs_rx_rmfifodatainserted[7]),
.rx_clkout_7(rx_pcs_clk_c7), //INPUT : Receive Clock
.tx_clkout_7(tx_pcs_clk_c7), //INPUT : Transmit Clock
.rx_kchar_7(pcs_rx_kchar_7), //INPUT : Special Character Indication
.tx_kchar_7(tx_kchar_7), //OUTPUT : Special Character Indication
.rx_frame_7(pcs_rx_frame_7), //INPUT : Frame
.tx_frame_7(tx_frame_7), //OUTPUT : Frame
.sd_loopback_7(sd_loopback_7), //OUTPUT : SERDES Loopback Enable
.powerdown_7(pcs_pwrdn_out_sig[7]), //OUTPUT : Powerdown Enable
.led_col_7(led_col_7), //OUTPUT : Collision Indication
.led_an_7(led_an_7), //OUTPUT : Auto Negotiation Status
.led_char_err_7(led_char_err_gx[7]), //INPUT : Character error
.led_crs_7(led_crs_7), //OUTPUT : Carrier sense
.led_link_7(link_status[7]), //INPUT : Valid link
.mac_rx_clk_7(mac_rx_clk_7), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_7(mac_tx_clk_7), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_7(data_rx_sop_7), //OUTPUT : Start of Packet
.data_rx_eop_7(data_rx_eop_7), //OUTPUT : End of Packet
.data_rx_data_7(data_rx_data_7), //OUTPUT : Data from FIFO
.data_rx_error_7(data_rx_error_7), //OUTPUT : Receive packet error
.data_rx_valid_7(data_rx_valid_7), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_7(data_rx_ready_7), //OUTPUT : Data Receive Ready
.pkt_class_data_7(pkt_class_data_7), //OUTPUT : Frame Type Indication
.pkt_class_valid_7(pkt_class_valid_7), //OUTPUT : Frame Type Indication Valid
.data_tx_error_7(data_tx_error_7), //INPUT : Status
.data_tx_data_7(data_tx_data_7), //INPUT : Data from FIFO transmit
.data_tx_valid_7(data_tx_valid_7), //INPUT : Data FIFO transmit Empty
.data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
.data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
.data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 8
.rx_carrierdetected_8(pcs_rx_carrierdetected[8]),
.rx_rmfifodatadeleted_8(pcs_rx_rmfifodatadeleted[8]),
.rx_rmfifodatainserted_8(pcs_rx_rmfifodatainserted[8]),
.rx_clkout_8(rx_pcs_clk_c8), //INPUT : Receive Clock
.tx_clkout_8(tx_pcs_clk_c8), //INPUT : Transmit Clock
.rx_kchar_8(pcs_rx_kchar_8), //INPUT : Special Character Indication
.tx_kchar_8(tx_kchar_8), //OUTPUT : Special Character Indication
.rx_frame_8(pcs_rx_frame_8), //INPUT : Frame
.tx_frame_8(tx_frame_8), //OUTPUT : Frame
.sd_loopback_8(sd_loopback_8), //OUTPUT : SERDES Loopback Enable
.powerdown_8(pcs_pwrdn_out_sig[8]), //OUTPUT : Powerdown Enable
.led_col_8(led_col_8), //OUTPUT : Collision Indication
.led_an_8(led_an_8), //OUTPUT : Auto Negotiation Status
.led_char_err_8(led_char_err_gx[8]), //INPUT : Character error
.led_crs_8(led_crs_8), //OUTPUT : Carrier sense
.led_link_8(link_status[8]), //INPUT : Valid link
.mac_rx_clk_8(mac_rx_clk_8), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_8(mac_tx_clk_8), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_8(data_rx_sop_8), //OUTPUT : Start of Packet
.data_rx_eop_8(data_rx_eop_8), //OUTPUT : End of Packet
.data_rx_data_8(data_rx_data_8), //OUTPUT : Data from FIFO
.data_rx_error_8(data_rx_error_8), //OUTPUT : Receive packet error
.data_rx_valid_8(data_rx_valid_8), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_8(data_rx_ready_8), //OUTPUT : Data Receive Ready
.pkt_class_data_8(pkt_class_data_8), //OUTPUT : Frame Type Indication
.pkt_class_valid_8(pkt_class_valid_8), //OUTPUT : Frame Type Indication Valid
.data_tx_error_8(data_tx_error_8), //INPUT : Status
.data_tx_data_8(data_tx_data_8), //INPUT : Data from FIFO transmit
.data_tx_valid_8(data_tx_valid_8), //INPUT : Data FIFO transmit Empty
.data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
.data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
.data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 9
.rx_carrierdetected_9(pcs_rx_carrierdetected[9]),
.rx_rmfifodatadeleted_9(pcs_rx_rmfifodatadeleted[9]),
.rx_rmfifodatainserted_9(pcs_rx_rmfifodatainserted[9]),
.rx_clkout_9(rx_pcs_clk_c9), //INPUT : Receive Clock
.tx_clkout_9(tx_pcs_clk_c9), //INPUT : Transmit Clock
.rx_kchar_9(pcs_rx_kchar_9), //INPUT : Special Character Indication
.tx_kchar_9(tx_kchar_9), //OUTPUT : Special Character Indication
.rx_frame_9(pcs_rx_frame_9), //INPUT : Frame
.tx_frame_9(tx_frame_9), //OUTPUT : Frame
.sd_loopback_9(sd_loopback_9), //OUTPUT : SERDES Loopback Enable
.powerdown_9(pcs_pwrdn_out_sig[9]), //OUTPUT : Powerdown Enable
.led_col_9(led_col_9), //OUTPUT : Collision Indication
.led_an_9(led_an_9), //OUTPUT : Auto Negotiation Status
.led_char_err_9(led_char_err_gx[9]), //INPUT : Character error
.led_crs_9(led_crs_9), //OUTPUT : Carrier sense
.led_link_9(link_status[9]), //INPUT : Valid link
.mac_rx_clk_9(mac_rx_clk_9), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_9(mac_tx_clk_9), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_9(data_rx_sop_9), //OUTPUT : Start of Packet
.data_rx_eop_9(data_rx_eop_9), //OUTPUT : End of Packet
.data_rx_data_9(data_rx_data_9), //OUTPUT : Data from FIFO
.data_rx_error_9(data_rx_error_9), //OUTPUT : Receive packet error
.data_rx_valid_9(data_rx_valid_9), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_9(data_rx_ready_9), //OUTPUT : Data Receive Ready
.pkt_class_data_9(pkt_class_data_9), //OUTPUT : Frame Type Indication
.pkt_class_valid_9(pkt_class_valid_9), //OUTPUT : Frame Type Indication Valid
.data_tx_error_9(data_tx_error_9), //INPUT : Status
.data_tx_data_9(data_tx_data_9), //INPUT : Data from FIFO transmit
.data_tx_valid_9(data_tx_valid_9), //INPUT : Data FIFO transmit Empty
.data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
.data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
.data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 10
.rx_carrierdetected_10(pcs_rx_carrierdetected[10]),
.rx_rmfifodatadeleted_10(pcs_rx_rmfifodatadeleted[10]),
.rx_rmfifodatainserted_10(pcs_rx_rmfifodatainserted[10]),
.rx_clkout_10(rx_pcs_clk_c10), //INPUT : Receive Clock
.tx_clkout_10(tx_pcs_clk_c10), //INPUT : Transmit Clock
.rx_kchar_10(pcs_rx_kchar_10), //INPUT : Special Character Indication
.tx_kchar_10(tx_kchar_10), //OUTPUT : Special Character Indication
.rx_frame_10(pcs_rx_frame_10), //INPUT : Frame
.tx_frame_10(tx_frame_10), //OUTPUT : Frame
.sd_loopback_10(sd_loopback_10), //OUTPUT : SERDES Loopback Enable
.powerdown_10(pcs_pwrdn_out_sig[10]), //OUTPUT : Powerdown Enable
.led_col_10(led_col_10), //OUTPUT : Collision Indication
.led_an_10(led_an_10), //OUTPUT : Auto Negotiation Status
.led_char_err_10(led_char_err_gx[10]), //INPUT : Character error
.led_crs_10(led_crs_10), //OUTPUT : Carrier sense
.led_link_10(link_status[10]), //INPUT : Valid link
.mac_rx_clk_10(mac_rx_clk_10), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_10(mac_tx_clk_10), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_10(data_rx_sop_10), //OUTPUT : Start of Packet
.data_rx_eop_10(data_rx_eop_10), //OUTPUT : End of Packet
.data_rx_data_10(data_rx_data_10), //OUTPUT : Data from FIFO
.data_rx_error_10(data_rx_error_10), //OUTPUT : Receive packet error
.data_rx_valid_10(data_rx_valid_10), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_10(data_rx_ready_10), //OUTPUT : Data Receive Ready
.pkt_class_data_10(pkt_class_data_10), //OUTPUT : Frame Type Indication
.pkt_class_valid_10(pkt_class_valid_10), //OUTPUT : Frame Type Indication Valid
.data_tx_error_10(data_tx_error_10), //INPUT : Status
.data_tx_data_10(data_tx_data_10), //INPUT : Data from FIFO transmit
.data_tx_valid_10(data_tx_valid_10), //INPUT : Data FIFO transmit Empty
.data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
.data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
.data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 11
.rx_carrierdetected_11(pcs_rx_carrierdetected[11]),
.rx_rmfifodatadeleted_11(pcs_rx_rmfifodatadeleted[11]),
.rx_rmfifodatainserted_11(pcs_rx_rmfifodatainserted[11]),
.rx_clkout_11(rx_pcs_clk_c11), //INPUT : Receive Clock
.tx_clkout_11(tx_pcs_clk_c11), //INPUT : Transmit Clock
.rx_kchar_11(pcs_rx_kchar_11), //INPUT : Special Character Indication
.tx_kchar_11(tx_kchar_11), //OUTPUT : Special Character Indication
.rx_frame_11(pcs_rx_frame_11), //INPUT : Frame
.tx_frame_11(tx_frame_11), //OUTPUT : Frame
.sd_loopback_11(sd_loopback_11), //OUTPUT : SERDES Loopback Enable
.powerdown_11(pcs_pwrdn_out_sig[11]), //OUTPUT : Powerdown Enable
.led_col_11(led_col_11), //OUTPUT : Collision Indication
.led_an_11(led_an_11), //OUTPUT : Auto Negotiation Status
.led_char_err_11(led_char_err_gx[11]), //INPUT : Character error
.led_crs_11(led_crs_11), //OUTPUT : Carrier sense
.led_link_11(link_status[11]), //INPUT : Valid link
.mac_rx_clk_11(mac_rx_clk_11), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_11(mac_tx_clk_11), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_11(data_rx_sop_11), //OUTPUT : Start of Packet
.data_rx_eop_11(data_rx_eop_11), //OUTPUT : End of Packet
.data_rx_data_11(data_rx_data_11), //OUTPUT : Data from FIFO
.data_rx_error_11(data_rx_error_11), //OUTPUT : Receive packet error
.data_rx_valid_11(data_rx_valid_11), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_11(data_rx_ready_11), //OUTPUT : Data Receive Ready
.pkt_class_data_11(pkt_class_data_11), //OUTPUT : Frame Type Indication
.pkt_class_valid_11(pkt_class_valid_11), //OUTPUT : Frame Type Indication Valid
.data_tx_error_11(data_tx_error_11), //INPUT : Status
.data_tx_data_11(data_tx_data_11), //INPUT : Data from FIFO transmit
.data_tx_valid_11(data_tx_valid_11), //INPUT : Data FIFO transmit Empty
.data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
.data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
.data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 12
.rx_carrierdetected_12(pcs_rx_carrierdetected[12]),
.rx_rmfifodatadeleted_12(pcs_rx_rmfifodatadeleted[12]),
.rx_rmfifodatainserted_12(pcs_rx_rmfifodatainserted[12]),
.rx_clkout_12(rx_pcs_clk_c12), //INPUT : Receive Clock
.tx_clkout_12(tx_pcs_clk_c12), //INPUT : Transmit Clock
.rx_kchar_12(pcs_rx_kchar_12), //INPUT : Special Character Indication
.tx_kchar_12(tx_kchar_12), //OUTPUT : Special Character Indication
.rx_frame_12(pcs_rx_frame_12), //INPUT : Frame
.tx_frame_12(tx_frame_12), //OUTPUT : Frame
.sd_loopback_12(sd_loopback_12), //OUTPUT : SERDES Loopback Enable
.powerdown_12(pcs_pwrdn_out_sig[12]), //OUTPUT : Powerdown Enable
.led_col_12(led_col_12), //OUTPUT : Collision Indication
.led_an_12(led_an_12), //OUTPUT : Auto Negotiation Status
.led_char_err_12(led_char_err_gx[12]), //INPUT : Character error
.led_crs_12(led_crs_12), //OUTPUT : Carrier sense
.led_link_12(link_status[12]), //INPUT : Valid link
.mac_rx_clk_12(mac_rx_clk_12), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_12(mac_tx_clk_12), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_12(data_rx_sop_12), //OUTPUT : Start of Packet
.data_rx_eop_12(data_rx_eop_12), //OUTPUT : End of Packet
.data_rx_data_12(data_rx_data_12), //OUTPUT : Data from FIFO
.data_rx_error_12(data_rx_error_12), //OUTPUT : Receive packet error
.data_rx_valid_12(data_rx_valid_12), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_12(data_rx_ready_12), //OUTPUT : Data Receive Ready
.pkt_class_data_12(pkt_class_data_12), //OUTPUT : Frame Type Indication
.pkt_class_valid_12(pkt_class_valid_12), //OUTPUT : Frame Type Indication Valid
.data_tx_error_12(data_tx_error_12), //INPUT : Status
.data_tx_data_12(data_tx_data_12), //INPUT : Data from FIFO transmit
.data_tx_valid_12(data_tx_valid_12), //INPUT : Data FIFO transmit Empty
.data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
.data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
.data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 13
.rx_carrierdetected_13(pcs_rx_carrierdetected[13]),
.rx_rmfifodatadeleted_13(pcs_rx_rmfifodatadeleted[13]),
.rx_rmfifodatainserted_13(pcs_rx_rmfifodatainserted[13]),
.rx_clkout_13(rx_pcs_clk_c13), //INPUT : Receive Clock
.tx_clkout_13(tx_pcs_clk_c13), //INPUT : Transmit Clock
.rx_kchar_13(pcs_rx_kchar_13), //INPUT : Special Character Indication
.tx_kchar_13(tx_kchar_13), //OUTPUT : Special Character Indication
.rx_frame_13(pcs_rx_frame_13), //INPUT : Frame
.tx_frame_13(tx_frame_13), //OUTPUT : Frame
.sd_loopback_13(sd_loopback_13), //OUTPUT : SERDES Loopback Enable
.powerdown_13(pcs_pwrdn_out_sig[13]), //OUTPUT : Powerdown Enable
.led_col_13(led_col_13), //OUTPUT : Collision Indication
.led_an_13(led_an_13), //OUTPUT : Auto Negotiation Status
.led_char_err_13(led_char_err_gx[13]), //INPUT : Character error
.led_crs_13(led_crs_13), //OUTPUT : Carrier sense
.led_link_13(link_status[13]), //INPUT : Valid link
.mac_rx_clk_13(mac_rx_clk_13), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_13(mac_tx_clk_13), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_13(data_rx_sop_13), //OUTPUT : Start of Packet
.data_rx_eop_13(data_rx_eop_13), //OUTPUT : End of Packet
.data_rx_data_13(data_rx_data_13), //OUTPUT : Data from FIFO
.data_rx_error_13(data_rx_error_13), //OUTPUT : Receive packet error
.data_rx_valid_13(data_rx_valid_13), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_13(data_rx_ready_13), //OUTPUT : Data Receive Ready
.pkt_class_data_13(pkt_class_data_13), //OUTPUT : Frame Type Indication
.pkt_class_valid_13(pkt_class_valid_13), //OUTPUT : Frame Type Indication Valid
.data_tx_error_13(data_tx_error_13), //INPUT : Status
.data_tx_data_13(data_tx_data_13), //INPUT : Data from FIFO transmit
.data_tx_valid_13(data_tx_valid_13), //INPUT : Data FIFO transmit Empty
.data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
.data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
.data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 14
.rx_carrierdetected_14(pcs_rx_carrierdetected[14]),
.rx_rmfifodatadeleted_14(pcs_rx_rmfifodatadeleted[14]),
.rx_rmfifodatainserted_14(pcs_rx_rmfifodatainserted[14]),
.rx_clkout_14(rx_pcs_clk_c14), //INPUT : Receive Clock
.tx_clkout_14(tx_pcs_clk_c14), //INPUT : Transmit Clock
.rx_kchar_14(pcs_rx_kchar_14), //INPUT : Special Character Indication
.tx_kchar_14(tx_kchar_14), //OUTPUT : Special Character Indication
.rx_frame_14(pcs_rx_frame_14), //INPUT : Frame
.tx_frame_14(tx_frame_14), //OUTPUT : Frame
.sd_loopback_14(sd_loopback_14), //OUTPUT : SERDES Loopback Enable
.powerdown_14(pcs_pwrdn_out_sig[14]), //OUTPUT : Powerdown Enable
.led_col_14(led_col_14), //OUTPUT : Collision Indication
.led_an_14(led_an_14), //OUTPUT : Auto Negotiation Status
.led_char_err_14(led_char_err_gx[14]), //INPUT : Character error
.led_crs_14(led_crs_14), //OUTPUT : Carrier sense
.led_link_14(link_status[14]), //INPUT : Valid link
.mac_rx_clk_14(mac_rx_clk_14), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_14(mac_tx_clk_14), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_14(data_rx_sop_14), //OUTPUT : Start of Packet
.data_rx_eop_14(data_rx_eop_14), //OUTPUT : End of Packet
.data_rx_data_14(data_rx_data_14), //OUTPUT : Data from FIFO
.data_rx_error_14(data_rx_error_14), //OUTPUT : Receive packet error
.data_rx_valid_14(data_rx_valid_14), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_14(data_rx_ready_14), //OUTPUT : Data Receive Ready
.pkt_class_data_14(pkt_class_data_14), //OUTPUT : Frame Type Indication
.pkt_class_valid_14(pkt_class_valid_14), //OUTPUT : Frame Type Indication Valid
.data_tx_error_14(data_tx_error_14), //INPUT : Status
.data_tx_data_14(data_tx_data_14), //INPUT : Data from FIFO transmit
.data_tx_valid_14(data_tx_valid_14), //INPUT : Data FIFO transmit Empty
.data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
.data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
.data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 15
.rx_carrierdetected_15(pcs_rx_carrierdetected[15]),
.rx_rmfifodatadeleted_15(pcs_rx_rmfifodatadeleted[15]),
.rx_rmfifodatainserted_15(pcs_rx_rmfifodatainserted[15]),
.rx_clkout_15(rx_pcs_clk_c15), //INPUT : Receive Clock
.tx_clkout_15(tx_pcs_clk_c15), //INPUT : Transmit Clock
.rx_kchar_15(pcs_rx_kchar_15), //INPUT : Special Character Indication
.tx_kchar_15(tx_kchar_15), //OUTPUT : Special Character Indication
.rx_frame_15(pcs_rx_frame_15), //INPUT : Frame
.tx_frame_15(tx_frame_15), //OUTPUT : Frame
.sd_loopback_15(sd_loopback_15), //OUTPUT : SERDES Loopback Enable
.powerdown_15(pcs_pwrdn_out_sig[15]), //OUTPUT : Powerdown Enable
.led_col_15(led_col_15), //OUTPUT : Collision Indication
.led_an_15(led_an_15), //OUTPUT : Auto Negotiation Status
.led_char_err_15(led_char_err_gx[15]), //INPUT : Character error
.led_crs_15(led_crs_15), //OUTPUT : Carrier sense
.led_link_15(link_status[15]), //INPUT : Valid link
.mac_rx_clk_15(mac_rx_clk_15), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_15(mac_tx_clk_15), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_15(data_rx_sop_15), //OUTPUT : Start of Packet
.data_rx_eop_15(data_rx_eop_15), //OUTPUT : End of Packet
.data_rx_data_15(data_rx_data_15), //OUTPUT : Data from FIFO
.data_rx_error_15(data_rx_error_15), //OUTPUT : Receive packet error
.data_rx_valid_15(data_rx_valid_15), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_15(data_rx_ready_15), //OUTPUT : Data Receive Ready
.pkt_class_data_15(pkt_class_data_15), //OUTPUT : Frame Type Indication
.pkt_class_valid_15(pkt_class_valid_15), //OUTPUT : Frame Type Indication Valid
.data_tx_error_15(data_tx_error_15), //INPUT : Status
.data_tx_data_15(data_tx_data_15), //INPUT : Data from FIFO transmit
.data_tx_valid_15(data_tx_valid_15), //INPUT : Data FIFO transmit Empty
.data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
.data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
.data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 16
.rx_carrierdetected_16(pcs_rx_carrierdetected[16]),
.rx_rmfifodatadeleted_16(pcs_rx_rmfifodatadeleted[16]),
.rx_rmfifodatainserted_16(pcs_rx_rmfifodatainserted[16]),
.rx_clkout_16(rx_pcs_clk_c16), //INPUT : Receive Clock
.tx_clkout_16(tx_pcs_clk_c16), //INPUT : Transmit Clock
.rx_kchar_16(pcs_rx_kchar_16), //INPUT : Special Character Indication
.tx_kchar_16(tx_kchar_16), //OUTPUT : Special Character Indication
.rx_frame_16(pcs_rx_frame_16), //INPUT : Frame
.tx_frame_16(tx_frame_16), //OUTPUT : Frame
.sd_loopback_16(sd_loopback_16), //OUTPUT : SERDES Loopback Enable
.powerdown_16(pcs_pwrdn_out_sig[16]), //OUTPUT : Powerdown Enable
.led_col_16(led_col_16), //OUTPUT : Collision Indication
.led_an_16(led_an_16), //OUTPUT : Auto Negotiation Status
.led_char_err_16(led_char_err_gx[16]), //INPUT : Character error
.led_crs_16(led_crs_16), //OUTPUT : Carrier sense
.led_link_16(link_status[16]), //INPUT : Valid link
.mac_rx_clk_16(mac_rx_clk_16), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_16(mac_tx_clk_16), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_16(data_rx_sop_16), //OUTPUT : Start of Packet
.data_rx_eop_16(data_rx_eop_16), //OUTPUT : End of Packet
.data_rx_data_16(data_rx_data_16), //OUTPUT : Data from FIFO
.data_rx_error_16(data_rx_error_16), //OUTPUT : Receive packet error
.data_rx_valid_16(data_rx_valid_16), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_16(data_rx_ready_16), //OUTPUT : Data Receive Ready
.pkt_class_data_16(pkt_class_data_16), //OUTPUT : Frame Type Indication
.pkt_class_valid_16(pkt_class_valid_16), //OUTPUT : Frame Type Indication Valid
.data_tx_error_16(data_tx_error_16), //INPUT : Status
.data_tx_data_16(data_tx_data_16), //INPUT : Data from FIFO transmit
.data_tx_valid_16(data_tx_valid_16), //INPUT : Data FIFO transmit Empty
.data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
.data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
.data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 17
.rx_carrierdetected_17(pcs_rx_carrierdetected[17]),
.rx_rmfifodatadeleted_17(pcs_rx_rmfifodatadeleted[17]),
.rx_rmfifodatainserted_17(pcs_rx_rmfifodatainserted[17]),
.rx_clkout_17(rx_pcs_clk_c17), //INPUT : Receive Clock
.tx_clkout_17(tx_pcs_clk_c17), //INPUT : Transmit Clock
.rx_kchar_17(pcs_rx_kchar_17), //INPUT : Special Character Indication
.tx_kchar_17(tx_kchar_17), //OUTPUT : Special Character Indication
.rx_frame_17(pcs_rx_frame_17), //INPUT : Frame
.tx_frame_17(tx_frame_17), //OUTPUT : Frame
.sd_loopback_17(sd_loopback_17), //OUTPUT : SERDES Loopback Enable
.powerdown_17(pcs_pwrdn_out_sig[17]), //OUTPUT : Powerdown Enable
.led_col_17(led_col_17), //OUTPUT : Collision Indication
.led_an_17(led_an_17), //OUTPUT : Auto Negotiation Status
.led_char_err_17(led_char_err_gx[17]), //INPUT : Character error
.led_crs_17(led_crs_17), //OUTPUT : Carrier sense
.led_link_17(link_status[17]), //INPUT : Valid link
.mac_rx_clk_17(mac_rx_clk_17), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_17(mac_tx_clk_17), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_17(data_rx_sop_17), //OUTPUT : Start of Packet
.data_rx_eop_17(data_rx_eop_17), //OUTPUT : End of Packet
.data_rx_data_17(data_rx_data_17), //OUTPUT : Data from FIFO
.data_rx_error_17(data_rx_error_17), //OUTPUT : Receive packet error
.data_rx_valid_17(data_rx_valid_17), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_17(data_rx_ready_17), //OUTPUT : Data Receive Ready
.pkt_class_data_17(pkt_class_data_17), //OUTPUT : Frame Type Indication
.pkt_class_valid_17(pkt_class_valid_17), //OUTPUT : Frame Type Indication Valid
.data_tx_error_17(data_tx_error_17), //INPUT : Status
.data_tx_data_17(data_tx_data_17), //INPUT : Data from FIFO transmit
.data_tx_valid_17(data_tx_valid_17), //INPUT : Data FIFO transmit Empty
.data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
.data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
.data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 18
.rx_carrierdetected_18(pcs_rx_carrierdetected[18]),
.rx_rmfifodatadeleted_18(pcs_rx_rmfifodatadeleted[18]),
.rx_rmfifodatainserted_18(pcs_rx_rmfifodatainserted[18]),
.rx_clkout_18(rx_pcs_clk_c18), //INPUT : Receive Clock
.tx_clkout_18(tx_pcs_clk_c18), //INPUT : Transmit Clock
.rx_kchar_18(pcs_rx_kchar_18), //INPUT : Special Character Indication
.tx_kchar_18(tx_kchar_18), //OUTPUT : Special Character Indication
.rx_frame_18(pcs_rx_frame_18), //INPUT : Frame
.tx_frame_18(tx_frame_18), //OUTPUT : Frame
.sd_loopback_18(sd_loopback_18), //OUTPUT : SERDES Loopback Enable
.powerdown_18(pcs_pwrdn_out_sig[18]), //OUTPUT : Powerdown Enable
.led_col_18(led_col_18), //OUTPUT : Collision Indication
.led_an_18(led_an_18), //OUTPUT : Auto Negotiation Status
.led_char_err_18(led_char_err_gx[18]), //INPUT : Character error
.led_crs_18(led_crs_18), //OUTPUT : Carrier sense
.led_link_18(link_status[18]), //INPUT : Valid link
.mac_rx_clk_18(mac_rx_clk_18), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_18(mac_tx_clk_18), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_18(data_rx_sop_18), //OUTPUT : Start of Packet
.data_rx_eop_18(data_rx_eop_18), //OUTPUT : End of Packet
.data_rx_data_18(data_rx_data_18), //OUTPUT : Data from FIFO
.data_rx_error_18(data_rx_error_18), //OUTPUT : Receive packet error
.data_rx_valid_18(data_rx_valid_18), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_18(data_rx_ready_18), //OUTPUT : Data Receive Ready
.pkt_class_data_18(pkt_class_data_18), //OUTPUT : Frame Type Indication
.pkt_class_valid_18(pkt_class_valid_18), //OUTPUT : Frame Type Indication Valid
.data_tx_error_18(data_tx_error_18), //INPUT : Status
.data_tx_data_18(data_tx_data_18), //INPUT : Data from FIFO transmit
.data_tx_valid_18(data_tx_valid_18), //INPUT : Data FIFO transmit Empty
.data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
.data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
.data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 19
.rx_carrierdetected_19(pcs_rx_carrierdetected[19]),
.rx_rmfifodatadeleted_19(pcs_rx_rmfifodatadeleted[19]),
.rx_rmfifodatainserted_19(pcs_rx_rmfifodatainserted[19]),
.rx_clkout_19(rx_pcs_clk_c19), //INPUT : Receive Clock
.tx_clkout_19(tx_pcs_clk_c19), //INPUT : Transmit Clock
.rx_kchar_19(pcs_rx_kchar_19), //INPUT : Special Character Indication
.tx_kchar_19(tx_kchar_19), //OUTPUT : Special Character Indication
.rx_frame_19(pcs_rx_frame_19), //INPUT : Frame
.tx_frame_19(tx_frame_19), //OUTPUT : Frame
.sd_loopback_19(sd_loopback_19), //OUTPUT : SERDES Loopback Enable
.powerdown_19(pcs_pwrdn_out_sig[19]), //OUTPUT : Powerdown Enable
.led_col_19(led_col_19), //OUTPUT : Collision Indication
.led_an_19(led_an_19), //OUTPUT : Auto Negotiation Status
.led_char_err_19(led_char_err_gx[19]), //INPUT : Character error
.led_crs_19(led_crs_19), //OUTPUT : Carrier sense
.led_link_19(link_status[19]), //INPUT : Valid link
.mac_rx_clk_19(mac_rx_clk_19), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_19(mac_tx_clk_19), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_19(data_rx_sop_19), //OUTPUT : Start of Packet
.data_rx_eop_19(data_rx_eop_19), //OUTPUT : End of Packet
.data_rx_data_19(data_rx_data_19), //OUTPUT : Data from FIFO
.data_rx_error_19(data_rx_error_19), //OUTPUT : Receive packet error
.data_rx_valid_19(data_rx_valid_19), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_19(data_rx_ready_19), //OUTPUT : Data Receive Ready
.pkt_class_data_19(pkt_class_data_19), //OUTPUT : Frame Type Indication
.pkt_class_valid_19(pkt_class_valid_19), //OUTPUT : Frame Type Indication Valid
.data_tx_error_19(data_tx_error_19), //INPUT : Status
.data_tx_data_19(data_tx_data_19), //INPUT : Data from FIFO transmit
.data_tx_valid_19(data_tx_valid_19), //INPUT : Data FIFO transmit Empty
.data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
.data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
.data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 20
.rx_carrierdetected_20(pcs_rx_carrierdetected[20]),
.rx_rmfifodatadeleted_20(pcs_rx_rmfifodatadeleted[20]),
.rx_rmfifodatainserted_20(pcs_rx_rmfifodatainserted[20]),
.rx_clkout_20(rx_pcs_clk_c20), //INPUT : Receive Clock
.tx_clkout_20(tx_pcs_clk_c20), //INPUT : Transmit Clock
.rx_kchar_20(pcs_rx_kchar_20), //INPUT : Special Character Indication
.tx_kchar_20(tx_kchar_20), //OUTPUT : Special Character Indication
.rx_frame_20(pcs_rx_frame_20), //INPUT : Frame
.tx_frame_20(tx_frame_20), //OUTPUT : Frame
.sd_loopback_20(sd_loopback_20), //OUTPUT : SERDES Loopback Enable
.powerdown_20(pcs_pwrdn_out_sig[20]), //OUTPUT : Powerdown Enable
.led_col_20(led_col_20), //OUTPUT : Collision Indication
.led_an_20(led_an_20), //OUTPUT : Auto Negotiation Status
.led_char_err_20(led_char_err_gx[20]), //INPUT : Character error
.led_crs_20(led_crs_20), //OUTPUT : Carrier sense
.led_link_20(link_status[20]), //INPUT : Valid link
.mac_rx_clk_20(mac_rx_clk_20), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_20(mac_tx_clk_20), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_20(data_rx_sop_20), //OUTPUT : Start of Packet
.data_rx_eop_20(data_rx_eop_20), //OUTPUT : End of Packet
.data_rx_data_20(data_rx_data_20), //OUTPUT : Data from FIFO
.data_rx_error_20(data_rx_error_20), //OUTPUT : Receive packet error
.data_rx_valid_20(data_rx_valid_20), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_20(data_rx_ready_20), //OUTPUT : Data Receive Ready
.pkt_class_data_20(pkt_class_data_20), //OUTPUT : Frame Type Indication
.pkt_class_valid_20(pkt_class_valid_20), //OUTPUT : Frame Type Indication Valid
.data_tx_error_20(data_tx_error_20), //INPUT : Status
.data_tx_data_20(data_tx_data_20), //INPUT : Data from FIFO transmit
.data_tx_valid_20(data_tx_valid_20), //INPUT : Data FIFO transmit Empty
.data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
.data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
.data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 21
.rx_carrierdetected_21(pcs_rx_carrierdetected[21]),
.rx_rmfifodatadeleted_21(pcs_rx_rmfifodatadeleted[21]),
.rx_rmfifodatainserted_21(pcs_rx_rmfifodatainserted[21]),
.rx_clkout_21(rx_pcs_clk_c21), //INPUT : Receive Clock
.tx_clkout_21(tx_pcs_clk_c21), //INPUT : Transmit Clock
.rx_kchar_21(pcs_rx_kchar_21), //INPUT : Special Character Indication
.tx_kchar_21(tx_kchar_21), //OUTPUT : Special Character Indication
.rx_frame_21(pcs_rx_frame_21), //INPUT : Frame
.tx_frame_21(tx_frame_21), //OUTPUT : Frame
.sd_loopback_21(sd_loopback_21), //OUTPUT : SERDES Loopback Enable
.powerdown_21(pcs_pwrdn_out_sig[21]), //OUTPUT : Powerdown Enable
.led_col_21(led_col_21), //OUTPUT : Collision Indication
.led_an_21(led_an_21), //OUTPUT : Auto Negotiation Status
.led_char_err_21(led_char_err_gx[21]), //INPUT : Character error
.led_crs_21(led_crs_21), //OUTPUT : Carrier sense
.led_link_21(link_status[21]), //INPUT : Valid link
.mac_rx_clk_21(mac_rx_clk_21), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_21(mac_tx_clk_21), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_21(data_rx_sop_21), //OUTPUT : Start of Packet
.data_rx_eop_21(data_rx_eop_21), //OUTPUT : End of Packet
.data_rx_data_21(data_rx_data_21), //OUTPUT : Data from FIFO
.data_rx_error_21(data_rx_error_21), //OUTPUT : Receive packet error
.data_rx_valid_21(data_rx_valid_21), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_21(data_rx_ready_21), //OUTPUT : Data Receive Ready
.pkt_class_data_21(pkt_class_data_21), //OUTPUT : Frame Type Indication
.pkt_class_valid_21(pkt_class_valid_21), //OUTPUT : Frame Type Indication Valid
.data_tx_error_21(data_tx_error_21), //INPUT : Status
.data_tx_data_21(data_tx_data_21), //INPUT : Data from FIFO transmit
.data_tx_valid_21(data_tx_valid_21), //INPUT : Data FIFO transmit Empty
.data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
.data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
.data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 22
.rx_carrierdetected_22(pcs_rx_carrierdetected[22]),
.rx_rmfifodatadeleted_22(pcs_rx_rmfifodatadeleted[22]),
.rx_rmfifodatainserted_22(pcs_rx_rmfifodatainserted[22]),
.rx_clkout_22(rx_pcs_clk_c22), //INPUT : Receive Clock
.tx_clkout_22(tx_pcs_clk_c22), //INPUT : Transmit Clock
.rx_kchar_22(pcs_rx_kchar_22), //INPUT : Special Character Indication
.tx_kchar_22(tx_kchar_22), //OUTPUT : Special Character Indication
.rx_frame_22(pcs_rx_frame_22), //INPUT : Frame
.tx_frame_22(tx_frame_22), //OUTPUT : Frame
.sd_loopback_22(sd_loopback_22), //OUTPUT : SERDES Loopback Enable
.powerdown_22(pcs_pwrdn_out_sig[22]), //OUTPUT : Powerdown Enable
.led_col_22(led_col_22), //OUTPUT : Collision Indication
.led_an_22(led_an_22), //OUTPUT : Auto Negotiation Status
.led_char_err_22(led_char_err_gx[22]), //INPUT : Character error
.led_crs_22(led_crs_22), //OUTPUT : Carrier sense
.led_link_22(link_status[22]), //INPUT : Valid link
.mac_rx_clk_22(mac_rx_clk_22), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_22(mac_tx_clk_22), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_22(data_rx_sop_22), //OUTPUT : Start of Packet
.data_rx_eop_22(data_rx_eop_22), //OUTPUT : End of Packet
.data_rx_data_22(data_rx_data_22), //OUTPUT : Data from FIFO
.data_rx_error_22(data_rx_error_22), //OUTPUT : Receive packet error
.data_rx_valid_22(data_rx_valid_22), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_22(data_rx_ready_22), //OUTPUT : Data Receive Ready
.pkt_class_data_22(pkt_class_data_22), //OUTPUT : Frame Type Indication
.pkt_class_valid_22(pkt_class_valid_22), //OUTPUT : Frame Type Indication Valid
.data_tx_error_22(data_tx_error_22), //INPUT : Status
.data_tx_data_22(data_tx_data_22), //INPUT : Data from FIFO transmit
.data_tx_valid_22(data_tx_valid_22), //INPUT : Data FIFO transmit Empty
.data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
.data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
.data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 23
.rx_carrierdetected_23(pcs_rx_carrierdetected[23]),
.rx_rmfifodatadeleted_23(pcs_rx_rmfifodatadeleted[23]),
.rx_rmfifodatainserted_23(pcs_rx_rmfifodatainserted[23]),
.rx_clkout_23(rx_pcs_clk_c23), //INPUT : Receive Clock
.tx_clkout_23(tx_pcs_clk_c23), //INPUT : Transmit Clock
.rx_kchar_23(pcs_rx_kchar_23), //INPUT : Special Character Indication
.tx_kchar_23(tx_kchar_23), //OUTPUT : Special Character Indication
.rx_frame_23(pcs_rx_frame_23), //INPUT : Frame
.tx_frame_23(tx_frame_23), //OUTPUT : Frame
.sd_loopback_23(sd_loopback_23), //OUTPUT : SERDES Loopback Enable
.powerdown_23(pcs_pwrdn_out_sig[23]), //OUTPUT : Powerdown Enable
.led_col_23(led_col_23), //OUTPUT : Collision Indication
.led_an_23(led_an_23), //OUTPUT : Auto Negotiation Status
.led_char_err_23(led_char_err_gx[23]), //INPUT : Character error
.led_crs_23(led_crs_23), //OUTPUT : Carrier sense
.led_link_23(link_status[23]), //INPUT : Valid link
.mac_rx_clk_23(mac_rx_clk_23), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_23(mac_tx_clk_23), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_23(data_rx_sop_23), //OUTPUT : Start of Packet
.data_rx_eop_23(data_rx_eop_23), //OUTPUT : End of Packet
.data_rx_data_23(data_rx_data_23), //OUTPUT : Data from FIFO
.data_rx_error_23(data_rx_error_23), //OUTPUT : Receive packet error
.data_rx_valid_23(data_rx_valid_23), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_23(data_rx_ready_23), //OUTPUT : Data Receive Ready
.pkt_class_data_23(pkt_class_data_23), //OUTPUT : Frame Type Indication
.pkt_class_valid_23(pkt_class_valid_23), //OUTPUT : Frame Type Indication Valid
.data_tx_error_23(data_tx_error_23), //INPUT : Status
.data_tx_data_23(data_tx_data_23), //INPUT : Data from FIFO transmit
.data_tx_valid_23(data_tx_valid_23), //INPUT : Data FIFO transmit Empty
.data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
.data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
.data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_23(magic_wakeup_23)); //OUTPUT : MAC WAKE-UP INDICATION
defparam
U_MULTI_MAC_PCS.USE_SYNC_RESET = USE_SYNC_RESET,
U_MULTI_MAC_PCS.RESET_LEVEL = RESET_LEVEL,
U_MULTI_MAC_PCS.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
U_MULTI_MAC_PCS.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
U_MULTI_MAC_PCS.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
U_MULTI_MAC_PCS.ENA_HASH = ENA_HASH,
U_MULTI_MAC_PCS.STAT_CNT_ENA = STAT_CNT_ENA,
U_MULTI_MAC_PCS.CORE_VERSION = CORE_VERSION,
U_MULTI_MAC_PCS.CUST_VERSION = CUST_VERSION,
U_MULTI_MAC_PCS.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
U_MULTI_MAC_PCS.ENABLE_MDIO = ENABLE_MDIO,
U_MULTI_MAC_PCS.MDIO_CLK_DIV = MDIO_CLK_DIV,
U_MULTI_MAC_PCS.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
U_MULTI_MAC_PCS.ENABLE_PADDING = ENABLE_PADDING,
U_MULTI_MAC_PCS.ENABLE_LGTH_CHECK = ENABLE_LGTH_CHECK,
U_MULTI_MAC_PCS.GBIT_ONLY = GBIT_ONLY,
U_MULTI_MAC_PCS.MBIT_ONLY = MBIT_ONLY,
U_MULTI_MAC_PCS.REDUCED_CONTROL = REDUCED_CONTROL,
U_MULTI_MAC_PCS.CRC32DWIDTH = CRC32DWIDTH,
U_MULTI_MAC_PCS.CRC32GENDELAY = CRC32GENDELAY,
U_MULTI_MAC_PCS.CRC32CHECK16BIT = CRC32CHECK16BIT,
U_MULTI_MAC_PCS.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
U_MULTI_MAC_PCS.ENABLE_SHIFT16 = ENABLE_SHIFT16,
U_MULTI_MAC_PCS.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
U_MULTI_MAC_PCS.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
U_MULTI_MAC_PCS.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
U_MULTI_MAC_PCS.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN,
U_MULTI_MAC_PCS.PHY_IDENTIFIER = PHY_IDENTIFIER,
U_MULTI_MAC_PCS.DEV_VERSION = DEV_VERSION,
U_MULTI_MAC_PCS.ENABLE_SGMII = ENABLE_SGMII,
U_MULTI_MAC_PCS.MAX_CHANNELS = MAX_CHANNELS,
U_MULTI_MAC_PCS.CHANNEL_WIDTH = CHANNEL_WIDTH,
U_MULTI_MAC_PCS.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
U_MULTI_MAC_PCS.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
U_MULTI_MAC_PCS.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING,
U_MULTI_MAC_PCS.ENABLE_REG_SHARING = ENABLE_REG_SHARING;
// #######################################################################
// ############### CHANNEL 0 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 0)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch0_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c0_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_0
(
.clk(rx_pcs_clk_c0),
.reset(reset_rx_pcs_clk_c0_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_0),
.alt_sync(rx_syncstatus[0]),
.alt_disperr(rx_disp_err[0]),
.alt_ctrldetect(rx_kchar_0),
.alt_errdetect(rx_char_err_gx[0]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[0]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[0]),
.alt_runlengthviolation(rx_runlengthviolation[0]),
.alt_patterndetect(rx_patterndetect[0]),
.alt_runningdisp(rx_runningdisp[0]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_0),
.altpcs_sync(link_status[0]),
.altpcs_disperr(led_disp_err_0),
.altpcs_ctrldetect(pcs_rx_kchar_0),
.altpcs_errdetect(led_char_err_gx[0]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[0]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[0]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[0])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_0.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_0
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_0),
.phy_mgmt_read(phy_mgmt_read_0),
.phy_mgmt_readdata(phy_mgmt_readdata_0),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_0),
.phy_mgmt_write(phy_mgmt_write_0),
.phy_mgmt_writedata(phy_mgmt_writedata_0),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_0),
.rx_serial_data(rxp_0),
.rx_runningdisp(rx_runningdisp[0]),
.rx_disperr(rx_disp_err[0]),
.rx_errdetect(rx_char_err_gx[0]),
.rx_patterndetect(rx_patterndetect[0]),
.rx_syncstatus(rx_syncstatus[0]),
.tx_clkout(tx_pcs_clk_c0),
.rx_clkout(rx_pcs_clk_c0),
.tx_parallel_data(tx_frame_0),
.tx_datak(tx_kchar_0),
.rx_parallel_data(rx_frame_0),
.rx_datak(rx_kchar_0),
.rx_rlv(rx_runlengthviolation[0]),
.rx_recovclkout(rx_recovclkout_0),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[0]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[0]),
.reconfig_togxb(reconfig_togxb_0),
.reconfig_fromgxb(reconfig_fromgxb_0)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_0.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_0.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_0.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_0 = {92{1'b0}};
assign led_char_err_gx[0] = 1'b0;
assign link_status[0] = 1'b0;
assign led_disp_err_0 = 1'b0;
assign txp_0 = 1'b0;
assign rx_recovclkout_0= 1'b0;
assign phy_mgmt_readdata_0 = 32'b0;
assign phy_mgmt_waitrequest_0 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 1 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 1)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch1_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c1_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_1
(
.clk(rx_pcs_clk_c1),
.reset(reset_rx_pcs_clk_c1_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_1),
.alt_sync(rx_syncstatus[1]),
.alt_disperr(rx_disp_err[1]),
.alt_ctrldetect(rx_kchar_1),
.alt_errdetect(rx_char_err_gx[1]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[1]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[1]),
.alt_runlengthviolation(rx_runlengthviolation[1]),
.alt_patterndetect(rx_patterndetect[1]),
.alt_runningdisp(rx_runningdisp[1]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_1),
.altpcs_sync(link_status[1]),
.altpcs_disperr(led_disp_err_1),
.altpcs_ctrldetect(pcs_rx_kchar_1),
.altpcs_errdetect(led_char_err_gx[1]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[1]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[1]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[1])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_1.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_1
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_1),
.phy_mgmt_read(phy_mgmt_read_1),
.phy_mgmt_readdata(phy_mgmt_readdata_1),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_1),
.phy_mgmt_write(phy_mgmt_write_1),
.phy_mgmt_writedata(phy_mgmt_writedata_1),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_1),
.rx_serial_data(rxp_1),
.rx_runningdisp(rx_runningdisp[1]),
.rx_disperr(rx_disp_err[1]),
.rx_errdetect(rx_char_err_gx[1]),
.rx_patterndetect(rx_patterndetect[1]),
.rx_syncstatus(rx_syncstatus[1]),
.tx_clkout(tx_pcs_clk_c1),
.rx_clkout(rx_pcs_clk_c1),
.tx_parallel_data(tx_frame_1),
.tx_datak(tx_kchar_1),
.rx_parallel_data(rx_frame_1),
.rx_datak(rx_kchar_1),
.rx_rlv(rx_runlengthviolation[1]),
.rx_recovclkout(rx_recovclkout_1),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[1]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[1]),
.reconfig_togxb(reconfig_togxb_1),
.reconfig_fromgxb(reconfig_fromgxb_1)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_1.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_1.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_1.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_1 = {92{1'b0}};
assign led_char_err_gx[1] = 1'b0;
assign link_status[1] = 1'b0;
assign led_disp_err_1 = 1'b0;
assign txp_1 = 1'b0;
assign rx_recovclkout_1= 1'b0;
assign phy_mgmt_readdata_1 = 32'b0;
assign phy_mgmt_waitrequest_1 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 2 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 2)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch2_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c2_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_2
(
.clk(rx_pcs_clk_c2),
.reset(reset_rx_pcs_clk_c2_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_2),
.alt_sync(rx_syncstatus[2]),
.alt_disperr(rx_disp_err[2]),
.alt_ctrldetect(rx_kchar_2),
.alt_errdetect(rx_char_err_gx[2]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[2]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[2]),
.alt_runlengthviolation(rx_runlengthviolation[2]),
.alt_patterndetect(rx_patterndetect[2]),
.alt_runningdisp(rx_runningdisp[2]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_2),
.altpcs_sync(link_status[2]),
.altpcs_disperr(led_disp_err_2),
.altpcs_ctrldetect(pcs_rx_kchar_2),
.altpcs_errdetect(led_char_err_gx[2]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[2]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[2]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[2])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_2.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_2
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_2),
.phy_mgmt_read(phy_mgmt_read_2),
.phy_mgmt_readdata(phy_mgmt_readdata_2),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_2),
.phy_mgmt_write(phy_mgmt_write_2),
.phy_mgmt_writedata(phy_mgmt_writedata_2),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_2),
.rx_serial_data(rxp_2),
.rx_runningdisp(rx_runningdisp[2]),
.rx_disperr(rx_disp_err[2]),
.rx_errdetect(rx_char_err_gx[2]),
.rx_patterndetect(rx_patterndetect[2]),
.rx_syncstatus(rx_syncstatus[2]),
.tx_clkout(tx_pcs_clk_c2),
.rx_clkout(rx_pcs_clk_c2),
.tx_parallel_data(tx_frame_2),
.tx_datak(tx_kchar_2),
.rx_parallel_data(rx_frame_2),
.rx_datak(rx_kchar_2),
.rx_rlv(rx_runlengthviolation[2]),
.rx_recovclkout(rx_recovclkout_2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[2]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[2]),
.reconfig_togxb(reconfig_togxb_2),
.reconfig_fromgxb(reconfig_fromgxb_2)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_2.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_2.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_2.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_2 = {92{1'b0}};
assign led_char_err_gx[2] = 1'b0;
assign link_status[2] = 1'b0;
assign led_disp_err_2 = 1'b0;
assign txp_2 = 1'b0;
assign rx_recovclkout_2= 1'b0;
assign phy_mgmt_readdata_2 = 32'b0;
assign phy_mgmt_waitrequest_2 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 3 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 3)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch3_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c3_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_3
(
.clk(rx_pcs_clk_c3),
.reset(reset_rx_pcs_clk_c3_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_3),
.alt_sync(rx_syncstatus[3]),
.alt_disperr(rx_disp_err[3]),
.alt_ctrldetect(rx_kchar_3),
.alt_errdetect(rx_char_err_gx[3]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[3]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[3]),
.alt_runlengthviolation(rx_runlengthviolation[3]),
.alt_patterndetect(rx_patterndetect[3]),
.alt_runningdisp(rx_runningdisp[3]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_3),
.altpcs_sync(link_status[3]),
.altpcs_disperr(led_disp_err_3),
.altpcs_ctrldetect(pcs_rx_kchar_3),
.altpcs_errdetect(led_char_err_gx[3]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[3]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[3]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[3])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_3.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_3
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_3),
.phy_mgmt_read(phy_mgmt_read_3),
.phy_mgmt_readdata(phy_mgmt_readdata_3),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_3),
.phy_mgmt_write(phy_mgmt_write_3),
.phy_mgmt_writedata(phy_mgmt_writedata_3),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_3),
.rx_serial_data(rxp_3),
.rx_runningdisp(rx_runningdisp[3]),
.rx_disperr(rx_disp_err[3]),
.rx_errdetect(rx_char_err_gx[3]),
.rx_patterndetect(rx_patterndetect[3]),
.rx_syncstatus(rx_syncstatus[3]),
.tx_clkout(tx_pcs_clk_c3),
.rx_clkout(rx_pcs_clk_c3),
.tx_parallel_data(tx_frame_3),
.tx_datak(tx_kchar_3),
.rx_parallel_data(rx_frame_3),
.rx_datak(rx_kchar_3),
.rx_rlv(rx_runlengthviolation[3]),
.rx_recovclkout(rx_recovclkout_3),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[3]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[3]),
.reconfig_togxb(reconfig_togxb_3),
.reconfig_fromgxb(reconfig_fromgxb_3)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_3.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_3.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_3.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_3 = {92{1'b0}};
assign led_char_err_gx[3] = 1'b0;
assign link_status[3] = 1'b0;
assign led_disp_err_3 = 1'b0;
assign txp_3 = 1'b0;
assign rx_recovclkout_3= 1'b0;
assign phy_mgmt_readdata_3 = 32'b0;
assign phy_mgmt_waitrequest_3 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 4 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 4)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch4_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c4_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_4
(
.clk(rx_pcs_clk_c4),
.reset(reset_rx_pcs_clk_c4_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_4),
.alt_sync(rx_syncstatus[4]),
.alt_disperr(rx_disp_err[4]),
.alt_ctrldetect(rx_kchar_4),
.alt_errdetect(rx_char_err_gx[4]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[4]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[4]),
.alt_runlengthviolation(rx_runlengthviolation[4]),
.alt_patterndetect(rx_patterndetect[4]),
.alt_runningdisp(rx_runningdisp[4]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_4),
.altpcs_sync(link_status[4]),
.altpcs_disperr(led_disp_err_4),
.altpcs_ctrldetect(pcs_rx_kchar_4),
.altpcs_errdetect(led_char_err_gx[4]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[4]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[4]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[4])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_4.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_4
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_4),
.phy_mgmt_read(phy_mgmt_read_4),
.phy_mgmt_readdata(phy_mgmt_readdata_4),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_4),
.phy_mgmt_write(phy_mgmt_write_4),
.phy_mgmt_writedata(phy_mgmt_writedata_4),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_4),
.rx_serial_data(rxp_4),
.rx_runningdisp(rx_runningdisp[4]),
.rx_disperr(rx_disp_err[4]),
.rx_errdetect(rx_char_err_gx[4]),
.rx_patterndetect(rx_patterndetect[4]),
.rx_syncstatus(rx_syncstatus[4]),
.tx_clkout(tx_pcs_clk_c4),
.rx_clkout(rx_pcs_clk_c4),
.tx_parallel_data(tx_frame_4),
.tx_datak(tx_kchar_4),
.rx_parallel_data(rx_frame_4),
.rx_datak(rx_kchar_4),
.rx_rlv(rx_runlengthviolation[4]),
.rx_recovclkout(rx_recovclkout_4),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[4]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[4]),
.reconfig_togxb(reconfig_togxb_4),
.reconfig_fromgxb(reconfig_fromgxb_4)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_4.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_4.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_4.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_4 = {92{1'b0}};
assign led_char_err_gx[4] = 1'b0;
assign link_status[4] = 1'b0;
assign led_disp_err_4 = 1'b0;
assign txp_4 = 1'b0;
assign rx_recovclkout_4= 1'b0;
assign phy_mgmt_readdata_4 = 32'b0;
assign phy_mgmt_waitrequest_4 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 5 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 5)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch5_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c5_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_5
(
.clk(rx_pcs_clk_c5),
.reset(reset_rx_pcs_clk_c5_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_5),
.alt_sync(rx_syncstatus[5]),
.alt_disperr(rx_disp_err[5]),
.alt_ctrldetect(rx_kchar_5),
.alt_errdetect(rx_char_err_gx[5]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[5]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[5]),
.alt_runlengthviolation(rx_runlengthviolation[5]),
.alt_patterndetect(rx_patterndetect[5]),
.alt_runningdisp(rx_runningdisp[5]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_5),
.altpcs_sync(link_status[5]),
.altpcs_disperr(led_disp_err_5),
.altpcs_ctrldetect(pcs_rx_kchar_5),
.altpcs_errdetect(led_char_err_gx[5]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[5]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[5]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[5])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_5.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_5
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_5),
.phy_mgmt_read(phy_mgmt_read_5),
.phy_mgmt_readdata(phy_mgmt_readdata_5),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_5),
.phy_mgmt_write(phy_mgmt_write_5),
.phy_mgmt_writedata(phy_mgmt_writedata_5),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_5),
.rx_serial_data(rxp_5),
.rx_runningdisp(rx_runningdisp[5]),
.rx_disperr(rx_disp_err[5]),
.rx_errdetect(rx_char_err_gx[5]),
.rx_patterndetect(rx_patterndetect[5]),
.rx_syncstatus(rx_syncstatus[5]),
.tx_clkout(tx_pcs_clk_c5),
.rx_clkout(rx_pcs_clk_c5),
.tx_parallel_data(tx_frame_5),
.tx_datak(tx_kchar_5),
.rx_parallel_data(rx_frame_5),
.rx_datak(rx_kchar_5),
.rx_rlv(rx_runlengthviolation[5]),
.rx_recovclkout(rx_recovclkout_5),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[5]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[5]),
.reconfig_togxb(reconfig_togxb_5),
.reconfig_fromgxb(reconfig_fromgxb_5)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_5.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_5.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_5.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_5 = {92{1'b0}};
assign led_char_err_gx[5] = 1'b0;
assign link_status[5] = 1'b0;
assign led_disp_err_5 = 1'b0;
assign txp_5 = 1'b0;
assign rx_recovclkout_5= 1'b0;
assign phy_mgmt_readdata_5 = 32'b0;
assign phy_mgmt_waitrequest_5 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 6 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 6)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch6_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c6_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_6
(
.clk(rx_pcs_clk_c6),
.reset(reset_rx_pcs_clk_c6_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_6),
.alt_sync(rx_syncstatus[6]),
.alt_disperr(rx_disp_err[6]),
.alt_ctrldetect(rx_kchar_6),
.alt_errdetect(rx_char_err_gx[6]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[6]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[6]),
.alt_runlengthviolation(rx_runlengthviolation[6]),
.alt_patterndetect(rx_patterndetect[6]),
.alt_runningdisp(rx_runningdisp[6]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_6),
.altpcs_sync(link_status[6]),
.altpcs_disperr(led_disp_err_6),
.altpcs_ctrldetect(pcs_rx_kchar_6),
.altpcs_errdetect(led_char_err_gx[6]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[6]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[6]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[6])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_6.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_6
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_6),
.phy_mgmt_read(phy_mgmt_read_6),
.phy_mgmt_readdata(phy_mgmt_readdata_6),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_6),
.phy_mgmt_write(phy_mgmt_write_6),
.phy_mgmt_writedata(phy_mgmt_writedata_6),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_6),
.rx_serial_data(rxp_6),
.rx_runningdisp(rx_runningdisp[6]),
.rx_disperr(rx_disp_err[6]),
.rx_errdetect(rx_char_err_gx[6]),
.rx_patterndetect(rx_patterndetect[6]),
.rx_syncstatus(rx_syncstatus[6]),
.tx_clkout(tx_pcs_clk_c6),
.rx_clkout(rx_pcs_clk_c6),
.tx_parallel_data(tx_frame_6),
.tx_datak(tx_kchar_6),
.rx_parallel_data(rx_frame_6),
.rx_datak(rx_kchar_6),
.rx_rlv(rx_runlengthviolation[6]),
.rx_recovclkout(rx_recovclkout_6),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[6]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[6]),
.reconfig_togxb(reconfig_togxb_6),
.reconfig_fromgxb(reconfig_fromgxb_6)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_6.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_6.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_6.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_6 = {92{1'b0}};
assign led_char_err_gx[6] = 1'b0;
assign link_status[6] = 1'b0;
assign led_disp_err_6 = 1'b0;
assign txp_6 = 1'b0;
assign rx_recovclkout_6= 1'b0;
assign phy_mgmt_readdata_6 = 32'b0;
assign phy_mgmt_waitrequest_6 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 7 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 7)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch7_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c7_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_7
(
.clk(rx_pcs_clk_c7),
.reset(reset_rx_pcs_clk_c7_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_7),
.alt_sync(rx_syncstatus[7]),
.alt_disperr(rx_disp_err[7]),
.alt_ctrldetect(rx_kchar_7),
.alt_errdetect(rx_char_err_gx[7]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[7]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[7]),
.alt_runlengthviolation(rx_runlengthviolation[7]),
.alt_patterndetect(rx_patterndetect[7]),
.alt_runningdisp(rx_runningdisp[7]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_7),
.altpcs_sync(link_status[7]),
.altpcs_disperr(led_disp_err_7),
.altpcs_ctrldetect(pcs_rx_kchar_7),
.altpcs_errdetect(led_char_err_gx[7]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[7]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[7]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[7])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_7.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_7
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_7),
.phy_mgmt_read(phy_mgmt_read_7),
.phy_mgmt_readdata(phy_mgmt_readdata_7),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_7),
.phy_mgmt_write(phy_mgmt_write_7),
.phy_mgmt_writedata(phy_mgmt_writedata_7),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_7),
.rx_serial_data(rxp_7),
.rx_runningdisp(rx_runningdisp[7]),
.rx_disperr(rx_disp_err[7]),
.rx_errdetect(rx_char_err_gx[7]),
.rx_patterndetect(rx_patterndetect[7]),
.rx_syncstatus(rx_syncstatus[7]),
.tx_clkout(tx_pcs_clk_c7),
.rx_clkout(rx_pcs_clk_c7),
.tx_parallel_data(tx_frame_7),
.tx_datak(tx_kchar_7),
.rx_parallel_data(rx_frame_7),
.rx_datak(rx_kchar_7),
.rx_rlv(rx_runlengthviolation[7]),
.rx_recovclkout(rx_recovclkout_7),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[7]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[7]),
.reconfig_togxb(reconfig_togxb_7),
.reconfig_fromgxb(reconfig_fromgxb_7)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_7.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_7.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_7.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_7 = {92{1'b0}};
assign led_char_err_gx[7] = 1'b0;
assign link_status[7] = 1'b0;
assign led_disp_err_7 = 1'b0;
assign txp_7 = 1'b0;
assign rx_recovclkout_7= 1'b0;
assign phy_mgmt_readdata_7 = 32'b0;
assign phy_mgmt_waitrequest_7 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 8 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 8)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch8_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c8_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_8
(
.clk(rx_pcs_clk_c8),
.reset(reset_rx_pcs_clk_c8_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_8),
.alt_sync(rx_syncstatus[8]),
.alt_disperr(rx_disp_err[8]),
.alt_ctrldetect(rx_kchar_8),
.alt_errdetect(rx_char_err_gx[8]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[8]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[8]),
.alt_runlengthviolation(rx_runlengthviolation[8]),
.alt_patterndetect(rx_patterndetect[8]),
.alt_runningdisp(rx_runningdisp[8]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_8),
.altpcs_sync(link_status[8]),
.altpcs_disperr(led_disp_err_8),
.altpcs_ctrldetect(pcs_rx_kchar_8),
.altpcs_errdetect(led_char_err_gx[8]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[8]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[8]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[8])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_8.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_8
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_8),
.phy_mgmt_read(phy_mgmt_read_8),
.phy_mgmt_readdata(phy_mgmt_readdata_8),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_8),
.phy_mgmt_write(phy_mgmt_write_8),
.phy_mgmt_writedata(phy_mgmt_writedata_8),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_8),
.rx_serial_data(rxp_8),
.rx_runningdisp(rx_runningdisp[8]),
.rx_disperr(rx_disp_err[8]),
.rx_errdetect(rx_char_err_gx[8]),
.rx_patterndetect(rx_patterndetect[8]),
.rx_syncstatus(rx_syncstatus[8]),
.tx_clkout(tx_pcs_clk_c8),
.rx_clkout(rx_pcs_clk_c8),
.tx_parallel_data(tx_frame_8),
.tx_datak(tx_kchar_8),
.rx_parallel_data(rx_frame_8),
.rx_datak(rx_kchar_8),
.rx_rlv(rx_runlengthviolation[8]),
.rx_recovclkout(rx_recovclkout_8),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[8]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[8]),
.reconfig_togxb(reconfig_togxb_8),
.reconfig_fromgxb(reconfig_fromgxb_8)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_8.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_8.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_8.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_8 = {92{1'b0}};
assign led_char_err_gx[8] = 1'b0;
assign link_status[8] = 1'b0;
assign led_disp_err_8 = 1'b0;
assign txp_8 = 1'b0;
assign rx_recovclkout_8= 1'b0;
assign phy_mgmt_readdata_8 = 32'b0;
assign phy_mgmt_waitrequest_8 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 9 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 9)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch9_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c9_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_9
(
.clk(rx_pcs_clk_c9),
.reset(reset_rx_pcs_clk_c9_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_9),
.alt_sync(rx_syncstatus[9]),
.alt_disperr(rx_disp_err[9]),
.alt_ctrldetect(rx_kchar_9),
.alt_errdetect(rx_char_err_gx[9]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[9]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[9]),
.alt_runlengthviolation(rx_runlengthviolation[9]),
.alt_patterndetect(rx_patterndetect[9]),
.alt_runningdisp(rx_runningdisp[9]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_9),
.altpcs_sync(link_status[9]),
.altpcs_disperr(led_disp_err_9),
.altpcs_ctrldetect(pcs_rx_kchar_9),
.altpcs_errdetect(led_char_err_gx[9]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[9]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[9]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[9])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_9.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_9
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_9),
.phy_mgmt_read(phy_mgmt_read_9),
.phy_mgmt_readdata(phy_mgmt_readdata_9),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_9),
.phy_mgmt_write(phy_mgmt_write_9),
.phy_mgmt_writedata(phy_mgmt_writedata_9),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_9),
.rx_serial_data(rxp_9),
.rx_runningdisp(rx_runningdisp[9]),
.rx_disperr(rx_disp_err[9]),
.rx_errdetect(rx_char_err_gx[9]),
.rx_patterndetect(rx_patterndetect[9]),
.rx_syncstatus(rx_syncstatus[9]),
.tx_clkout(tx_pcs_clk_c9),
.rx_clkout(rx_pcs_clk_c9),
.tx_parallel_data(tx_frame_9),
.tx_datak(tx_kchar_9),
.rx_parallel_data(rx_frame_9),
.rx_datak(rx_kchar_9),
.rx_rlv(rx_runlengthviolation[9]),
.rx_recovclkout(rx_recovclkout_9),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[9]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[9]),
.reconfig_togxb(reconfig_togxb_9),
.reconfig_fromgxb(reconfig_fromgxb_9)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_9.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_9.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_9.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_9 = {92{1'b0}};
assign led_char_err_gx[9] = 1'b0;
assign link_status[9] = 1'b0;
assign led_disp_err_9 = 1'b0;
assign txp_9 = 1'b0;
assign rx_recovclkout_9= 1'b0;
assign phy_mgmt_readdata_9 = 32'b0;
assign phy_mgmt_waitrequest_9 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 10 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 10)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch10_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c10_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_10
(
.clk(rx_pcs_clk_c10),
.reset(reset_rx_pcs_clk_c10_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_10),
.alt_sync(rx_syncstatus[10]),
.alt_disperr(rx_disp_err[10]),
.alt_ctrldetect(rx_kchar_10),
.alt_errdetect(rx_char_err_gx[10]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[10]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[10]),
.alt_runlengthviolation(rx_runlengthviolation[10]),
.alt_patterndetect(rx_patterndetect[10]),
.alt_runningdisp(rx_runningdisp[10]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_10),
.altpcs_sync(link_status[10]),
.altpcs_disperr(led_disp_err_10),
.altpcs_ctrldetect(pcs_rx_kchar_10),
.altpcs_errdetect(led_char_err_gx[10]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[10]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[10]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[10])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_10.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_10
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_10),
.phy_mgmt_read(phy_mgmt_read_10),
.phy_mgmt_readdata(phy_mgmt_readdata_10),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_10),
.phy_mgmt_write(phy_mgmt_write_10),
.phy_mgmt_writedata(phy_mgmt_writedata_10),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_10),
.rx_serial_data(rxp_10),
.rx_runningdisp(rx_runningdisp[10]),
.rx_disperr(rx_disp_err[10]),
.rx_errdetect(rx_char_err_gx[10]),
.rx_patterndetect(rx_patterndetect[10]),
.rx_syncstatus(rx_syncstatus[10]),
.tx_clkout(tx_pcs_clk_c10),
.rx_clkout(rx_pcs_clk_c10),
.tx_parallel_data(tx_frame_10),
.tx_datak(tx_kchar_10),
.rx_parallel_data(rx_frame_10),
.rx_datak(rx_kchar_10),
.rx_rlv(rx_runlengthviolation[10]),
.rx_recovclkout(rx_recovclkout_10),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[10]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[10]),
.reconfig_togxb(reconfig_togxb_10),
.reconfig_fromgxb(reconfig_fromgxb_10)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_10.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_10.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_10.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_10 = {92{1'b0}};
assign led_char_err_gx[10] = 1'b0;
assign link_status[10] = 1'b0;
assign led_disp_err_10 = 1'b0;
assign txp_10 = 1'b0;
assign rx_recovclkout_10= 1'b0;
assign phy_mgmt_readdata_10 = 32'b0;
assign phy_mgmt_waitrequest_10 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 11 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 11)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch11_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c11_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_11
(
.clk(rx_pcs_clk_c11),
.reset(reset_rx_pcs_clk_c11_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_11),
.alt_sync(rx_syncstatus[11]),
.alt_disperr(rx_disp_err[11]),
.alt_ctrldetect(rx_kchar_11),
.alt_errdetect(rx_char_err_gx[11]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[11]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[11]),
.alt_runlengthviolation(rx_runlengthviolation[11]),
.alt_patterndetect(rx_patterndetect[11]),
.alt_runningdisp(rx_runningdisp[11]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_11),
.altpcs_sync(link_status[11]),
.altpcs_disperr(led_disp_err_11),
.altpcs_ctrldetect(pcs_rx_kchar_11),
.altpcs_errdetect(led_char_err_gx[11]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[11]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[11]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[11])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_11.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_11
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_11),
.phy_mgmt_read(phy_mgmt_read_11),
.phy_mgmt_readdata(phy_mgmt_readdata_11),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_11),
.phy_mgmt_write(phy_mgmt_write_11),
.phy_mgmt_writedata(phy_mgmt_writedata_11),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_11),
.rx_serial_data(rxp_11),
.rx_runningdisp(rx_runningdisp[11]),
.rx_disperr(rx_disp_err[11]),
.rx_errdetect(rx_char_err_gx[11]),
.rx_patterndetect(rx_patterndetect[11]),
.rx_syncstatus(rx_syncstatus[11]),
.tx_clkout(tx_pcs_clk_c11),
.rx_clkout(rx_pcs_clk_c11),
.tx_parallel_data(tx_frame_11),
.tx_datak(tx_kchar_11),
.rx_parallel_data(rx_frame_11),
.rx_datak(rx_kchar_11),
.rx_rlv(rx_runlengthviolation[11]),
.rx_recovclkout(rx_recovclkout_11),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[11]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[11]),
.reconfig_togxb(reconfig_togxb_11),
.reconfig_fromgxb(reconfig_fromgxb_11)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_11.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_11.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_11.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_11 = {92{1'b0}};
assign led_char_err_gx[11] = 1'b0;
assign link_status[11] = 1'b0;
assign led_disp_err_11 = 1'b0;
assign txp_11 = 1'b0;
assign rx_recovclkout_11= 1'b0;
assign phy_mgmt_readdata_11 = 32'b0;
assign phy_mgmt_waitrequest_11 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 12 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 12)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch12_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c12_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_12
(
.clk(rx_pcs_clk_c12),
.reset(reset_rx_pcs_clk_c12_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_12),
.alt_sync(rx_syncstatus[12]),
.alt_disperr(rx_disp_err[12]),
.alt_ctrldetect(rx_kchar_12),
.alt_errdetect(rx_char_err_gx[12]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[12]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[12]),
.alt_runlengthviolation(rx_runlengthviolation[12]),
.alt_patterndetect(rx_patterndetect[12]),
.alt_runningdisp(rx_runningdisp[12]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_12),
.altpcs_sync(link_status[12]),
.altpcs_disperr(led_disp_err_12),
.altpcs_ctrldetect(pcs_rx_kchar_12),
.altpcs_errdetect(led_char_err_gx[12]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[12]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[12]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[12])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_12.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_12
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_12),
.phy_mgmt_read(phy_mgmt_read_12),
.phy_mgmt_readdata(phy_mgmt_readdata_12),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_12),
.phy_mgmt_write(phy_mgmt_write_12),
.phy_mgmt_writedata(phy_mgmt_writedata_12),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_12),
.rx_serial_data(rxp_12),
.rx_runningdisp(rx_runningdisp[12]),
.rx_disperr(rx_disp_err[12]),
.rx_errdetect(rx_char_err_gx[12]),
.rx_patterndetect(rx_patterndetect[12]),
.rx_syncstatus(rx_syncstatus[12]),
.tx_clkout(tx_pcs_clk_c12),
.rx_clkout(rx_pcs_clk_c12),
.tx_parallel_data(tx_frame_12),
.tx_datak(tx_kchar_12),
.rx_parallel_data(rx_frame_12),
.rx_datak(rx_kchar_12),
.rx_rlv(rx_runlengthviolation[12]),
.rx_recovclkout(rx_recovclkout_12),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[12]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[12]),
.reconfig_togxb(reconfig_togxb_12),
.reconfig_fromgxb(reconfig_fromgxb_12)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_12.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_12.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_12.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_12 = {92{1'b0}};
assign led_char_err_gx[12] = 1'b0;
assign link_status[12] = 1'b0;
assign led_disp_err_12 = 1'b0;
assign txp_12 = 1'b0;
assign rx_recovclkout_12= 1'b0;
assign phy_mgmt_readdata_12 = 32'b0;
assign phy_mgmt_waitrequest_12 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 13 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 13)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch13_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c13_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_13
(
.clk(rx_pcs_clk_c13),
.reset(reset_rx_pcs_clk_c13_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_13),
.alt_sync(rx_syncstatus[13]),
.alt_disperr(rx_disp_err[13]),
.alt_ctrldetect(rx_kchar_13),
.alt_errdetect(rx_char_err_gx[13]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[13]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[13]),
.alt_runlengthviolation(rx_runlengthviolation[13]),
.alt_patterndetect(rx_patterndetect[13]),
.alt_runningdisp(rx_runningdisp[13]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_13),
.altpcs_sync(link_status[13]),
.altpcs_disperr(led_disp_err_13),
.altpcs_ctrldetect(pcs_rx_kchar_13),
.altpcs_errdetect(led_char_err_gx[13]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[13]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[13]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[13])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_13.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_13
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_13),
.phy_mgmt_read(phy_mgmt_read_13),
.phy_mgmt_readdata(phy_mgmt_readdata_13),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_13),
.phy_mgmt_write(phy_mgmt_write_13),
.phy_mgmt_writedata(phy_mgmt_writedata_13),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_13),
.rx_serial_data(rxp_13),
.rx_runningdisp(rx_runningdisp[13]),
.rx_disperr(rx_disp_err[13]),
.rx_errdetect(rx_char_err_gx[13]),
.rx_patterndetect(rx_patterndetect[13]),
.rx_syncstatus(rx_syncstatus[13]),
.tx_clkout(tx_pcs_clk_c13),
.rx_clkout(rx_pcs_clk_c13),
.tx_parallel_data(tx_frame_13),
.tx_datak(tx_kchar_13),
.rx_parallel_data(rx_frame_13),
.rx_datak(rx_kchar_13),
.rx_rlv(rx_runlengthviolation[13]),
.rx_recovclkout(rx_recovclkout_13),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[13]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[13]),
.reconfig_togxb(reconfig_togxb_13),
.reconfig_fromgxb(reconfig_fromgxb_13)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_13.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_13.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_13.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_13 = {92{1'b0}};
assign led_char_err_gx[13] = 1'b0;
assign link_status[13] = 1'b0;
assign led_disp_err_13 = 1'b0;
assign txp_13 = 1'b0;
assign rx_recovclkout_13= 1'b0;
assign phy_mgmt_readdata_13 = 32'b0;
assign phy_mgmt_waitrequest_13 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 14 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 14)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch14_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c14_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_14
(
.clk(rx_pcs_clk_c14),
.reset(reset_rx_pcs_clk_c14_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_14),
.alt_sync(rx_syncstatus[14]),
.alt_disperr(rx_disp_err[14]),
.alt_ctrldetect(rx_kchar_14),
.alt_errdetect(rx_char_err_gx[14]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[14]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[14]),
.alt_runlengthviolation(rx_runlengthviolation[14]),
.alt_patterndetect(rx_patterndetect[14]),
.alt_runningdisp(rx_runningdisp[14]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_14),
.altpcs_sync(link_status[14]),
.altpcs_disperr(led_disp_err_14),
.altpcs_ctrldetect(pcs_rx_kchar_14),
.altpcs_errdetect(led_char_err_gx[14]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[14]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[14]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[14])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_14.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_14
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_14),
.phy_mgmt_read(phy_mgmt_read_14),
.phy_mgmt_readdata(phy_mgmt_readdata_14),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_14),
.phy_mgmt_write(phy_mgmt_write_14),
.phy_mgmt_writedata(phy_mgmt_writedata_14),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_14),
.rx_serial_data(rxp_14),
.rx_runningdisp(rx_runningdisp[14]),
.rx_disperr(rx_disp_err[14]),
.rx_errdetect(rx_char_err_gx[14]),
.rx_patterndetect(rx_patterndetect[14]),
.rx_syncstatus(rx_syncstatus[14]),
.tx_clkout(tx_pcs_clk_c14),
.rx_clkout(rx_pcs_clk_c14),
.tx_parallel_data(tx_frame_14),
.tx_datak(tx_kchar_14),
.rx_parallel_data(rx_frame_14),
.rx_datak(rx_kchar_14),
.rx_rlv(rx_runlengthviolation[14]),
.rx_recovclkout(rx_recovclkout_14),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[14]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[14]),
.reconfig_togxb(reconfig_togxb_14),
.reconfig_fromgxb(reconfig_fromgxb_14)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_14.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_14.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_14.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_14 = {92{1'b0}};
assign led_char_err_gx[14] = 1'b0;
assign link_status[14] = 1'b0;
assign led_disp_err_14 = 1'b0;
assign txp_14 = 1'b0;
assign rx_recovclkout_14= 1'b0;
assign phy_mgmt_readdata_14 = 32'b0;
assign phy_mgmt_waitrequest_14 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 15 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 15)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch15_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c15_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_15
(
.clk(rx_pcs_clk_c15),
.reset(reset_rx_pcs_clk_c15_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_15),
.alt_sync(rx_syncstatus[15]),
.alt_disperr(rx_disp_err[15]),
.alt_ctrldetect(rx_kchar_15),
.alt_errdetect(rx_char_err_gx[15]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[15]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[15]),
.alt_runlengthviolation(rx_runlengthviolation[15]),
.alt_patterndetect(rx_patterndetect[15]),
.alt_runningdisp(rx_runningdisp[15]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_15),
.altpcs_sync(link_status[15]),
.altpcs_disperr(led_disp_err_15),
.altpcs_ctrldetect(pcs_rx_kchar_15),
.altpcs_errdetect(led_char_err_gx[15]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[15]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[15]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[15])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_15.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_15
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_15),
.phy_mgmt_read(phy_mgmt_read_15),
.phy_mgmt_readdata(phy_mgmt_readdata_15),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_15),
.phy_mgmt_write(phy_mgmt_write_15),
.phy_mgmt_writedata(phy_mgmt_writedata_15),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_15),
.rx_serial_data(rxp_15),
.rx_runningdisp(rx_runningdisp[15]),
.rx_disperr(rx_disp_err[15]),
.rx_errdetect(rx_char_err_gx[15]),
.rx_patterndetect(rx_patterndetect[15]),
.rx_syncstatus(rx_syncstatus[15]),
.tx_clkout(tx_pcs_clk_c15),
.rx_clkout(rx_pcs_clk_c15),
.tx_parallel_data(tx_frame_15),
.tx_datak(tx_kchar_15),
.rx_parallel_data(rx_frame_15),
.rx_datak(rx_kchar_15),
.rx_rlv(rx_runlengthviolation[15]),
.rx_recovclkout(rx_recovclkout_15),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[15]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[15]),
.reconfig_togxb(reconfig_togxb_15),
.reconfig_fromgxb(reconfig_fromgxb_15)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_15.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_15.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_15.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_15 = {92{1'b0}};
assign led_char_err_gx[15] = 1'b0;
assign link_status[15] = 1'b0;
assign led_disp_err_15 = 1'b0;
assign txp_15 = 1'b0;
assign rx_recovclkout_15= 1'b0;
assign phy_mgmt_readdata_15 = 32'b0;
assign phy_mgmt_waitrequest_15 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 16 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 16)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch16_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c16_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_16
(
.clk(rx_pcs_clk_c16),
.reset(reset_rx_pcs_clk_c16_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_16),
.alt_sync(rx_syncstatus[16]),
.alt_disperr(rx_disp_err[16]),
.alt_ctrldetect(rx_kchar_16),
.alt_errdetect(rx_char_err_gx[16]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[16]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[16]),
.alt_runlengthviolation(rx_runlengthviolation[16]),
.alt_patterndetect(rx_patterndetect[16]),
.alt_runningdisp(rx_runningdisp[16]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_16),
.altpcs_sync(link_status[16]),
.altpcs_disperr(led_disp_err_16),
.altpcs_ctrldetect(pcs_rx_kchar_16),
.altpcs_errdetect(led_char_err_gx[16]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[16]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[16]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[16])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_16.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_16
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_16),
.phy_mgmt_read(phy_mgmt_read_16),
.phy_mgmt_readdata(phy_mgmt_readdata_16),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_16),
.phy_mgmt_write(phy_mgmt_write_16),
.phy_mgmt_writedata(phy_mgmt_writedata_16),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_16),
.rx_serial_data(rxp_16),
.rx_runningdisp(rx_runningdisp[16]),
.rx_disperr(rx_disp_err[16]),
.rx_errdetect(rx_char_err_gx[16]),
.rx_patterndetect(rx_patterndetect[16]),
.rx_syncstatus(rx_syncstatus[16]),
.tx_clkout(tx_pcs_clk_c16),
.rx_clkout(rx_pcs_clk_c16),
.tx_parallel_data(tx_frame_16),
.tx_datak(tx_kchar_16),
.rx_parallel_data(rx_frame_16),
.rx_datak(rx_kchar_16),
.rx_rlv(rx_runlengthviolation[16]),
.rx_recovclkout(rx_recovclkout_16),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[16]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[16]),
.reconfig_togxb(reconfig_togxb_16),
.reconfig_fromgxb(reconfig_fromgxb_16)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_16.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_16.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_16.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_16 = {92{1'b0}};
assign led_char_err_gx[16] = 1'b0;
assign link_status[16] = 1'b0;
assign led_disp_err_16 = 1'b0;
assign txp_16 = 1'b0;
assign rx_recovclkout_16= 1'b0;
assign phy_mgmt_readdata_16 = 32'b0;
assign phy_mgmt_waitrequest_16 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 17 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 17)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch17_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c17_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_17
(
.clk(rx_pcs_clk_c17),
.reset(reset_rx_pcs_clk_c17_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_17),
.alt_sync(rx_syncstatus[17]),
.alt_disperr(rx_disp_err[17]),
.alt_ctrldetect(rx_kchar_17),
.alt_errdetect(rx_char_err_gx[17]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[17]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[17]),
.alt_runlengthviolation(rx_runlengthviolation[17]),
.alt_patterndetect(rx_patterndetect[17]),
.alt_runningdisp(rx_runningdisp[17]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_17),
.altpcs_sync(link_status[17]),
.altpcs_disperr(led_disp_err_17),
.altpcs_ctrldetect(pcs_rx_kchar_17),
.altpcs_errdetect(led_char_err_gx[17]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[17]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[17]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[17])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_17.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_17
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_17),
.phy_mgmt_read(phy_mgmt_read_17),
.phy_mgmt_readdata(phy_mgmt_readdata_17),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_17),
.phy_mgmt_write(phy_mgmt_write_17),
.phy_mgmt_writedata(phy_mgmt_writedata_17),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_17),
.rx_serial_data(rxp_17),
.rx_runningdisp(rx_runningdisp[17]),
.rx_disperr(rx_disp_err[17]),
.rx_errdetect(rx_char_err_gx[17]),
.rx_patterndetect(rx_patterndetect[17]),
.rx_syncstatus(rx_syncstatus[17]),
.tx_clkout(tx_pcs_clk_c17),
.rx_clkout(rx_pcs_clk_c17),
.tx_parallel_data(tx_frame_17),
.tx_datak(tx_kchar_17),
.rx_parallel_data(rx_frame_17),
.rx_datak(rx_kchar_17),
.rx_rlv(rx_runlengthviolation[17]),
.rx_recovclkout(rx_recovclkout_17),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[17]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[17]),
.reconfig_togxb(reconfig_togxb_17),
.reconfig_fromgxb(reconfig_fromgxb_17)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_17.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_17.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_17.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_17 = {92{1'b0}};
assign led_char_err_gx[17] = 1'b0;
assign link_status[17] = 1'b0;
assign led_disp_err_17 = 1'b0;
assign txp_17 = 1'b0;
assign rx_recovclkout_17= 1'b0;
assign phy_mgmt_readdata_17 = 32'b0;
assign phy_mgmt_waitrequest_17 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 18 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 18)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch18_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c18_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_18
(
.clk(rx_pcs_clk_c18),
.reset(reset_rx_pcs_clk_c18_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_18),
.alt_sync(rx_syncstatus[18]),
.alt_disperr(rx_disp_err[18]),
.alt_ctrldetect(rx_kchar_18),
.alt_errdetect(rx_char_err_gx[18]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[18]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[18]),
.alt_runlengthviolation(rx_runlengthviolation[18]),
.alt_patterndetect(rx_patterndetect[18]),
.alt_runningdisp(rx_runningdisp[18]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_18),
.altpcs_sync(link_status[18]),
.altpcs_disperr(led_disp_err_18),
.altpcs_ctrldetect(pcs_rx_kchar_18),
.altpcs_errdetect(led_char_err_gx[18]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[18]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[18]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[18])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_18.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_18
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_18),
.phy_mgmt_read(phy_mgmt_read_18),
.phy_mgmt_readdata(phy_mgmt_readdata_18),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_18),
.phy_mgmt_write(phy_mgmt_write_18),
.phy_mgmt_writedata(phy_mgmt_writedata_18),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_18),
.rx_serial_data(rxp_18),
.rx_runningdisp(rx_runningdisp[18]),
.rx_disperr(rx_disp_err[18]),
.rx_errdetect(rx_char_err_gx[18]),
.rx_patterndetect(rx_patterndetect[18]),
.rx_syncstatus(rx_syncstatus[18]),
.tx_clkout(tx_pcs_clk_c18),
.rx_clkout(rx_pcs_clk_c18),
.tx_parallel_data(tx_frame_18),
.tx_datak(tx_kchar_18),
.rx_parallel_data(rx_frame_18),
.rx_datak(rx_kchar_18),
.rx_rlv(rx_runlengthviolation[18]),
.rx_recovclkout(rx_recovclkout_18),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[18]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[18]),
.reconfig_togxb(reconfig_togxb_18),
.reconfig_fromgxb(reconfig_fromgxb_18)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_18.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_18.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_18.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_18 = {92{1'b0}};
assign led_char_err_gx[18] = 1'b0;
assign link_status[18] = 1'b0;
assign led_disp_err_18 = 1'b0;
assign txp_18 = 1'b0;
assign rx_recovclkout_18= 1'b0;
assign phy_mgmt_readdata_18 = 32'b0;
assign phy_mgmt_waitrequest_18 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 19 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 19)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch19_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c19_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_19
(
.clk(rx_pcs_clk_c19),
.reset(reset_rx_pcs_clk_c19_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_19),
.alt_sync(rx_syncstatus[19]),
.alt_disperr(rx_disp_err[19]),
.alt_ctrldetect(rx_kchar_19),
.alt_errdetect(rx_char_err_gx[19]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[19]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[19]),
.alt_runlengthviolation(rx_runlengthviolation[19]),
.alt_patterndetect(rx_patterndetect[19]),
.alt_runningdisp(rx_runningdisp[19]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_19),
.altpcs_sync(link_status[19]),
.altpcs_disperr(led_disp_err_19),
.altpcs_ctrldetect(pcs_rx_kchar_19),
.altpcs_errdetect(led_char_err_gx[19]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[19]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[19]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[19])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_19.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_19
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_19),
.phy_mgmt_read(phy_mgmt_read_19),
.phy_mgmt_readdata(phy_mgmt_readdata_19),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_19),
.phy_mgmt_write(phy_mgmt_write_19),
.phy_mgmt_writedata(phy_mgmt_writedata_19),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_19),
.rx_serial_data(rxp_19),
.rx_runningdisp(rx_runningdisp[19]),
.rx_disperr(rx_disp_err[19]),
.rx_errdetect(rx_char_err_gx[19]),
.rx_patterndetect(rx_patterndetect[19]),
.rx_syncstatus(rx_syncstatus[19]),
.tx_clkout(tx_pcs_clk_c19),
.rx_clkout(rx_pcs_clk_c19),
.tx_parallel_data(tx_frame_19),
.tx_datak(tx_kchar_19),
.rx_parallel_data(rx_frame_19),
.rx_datak(rx_kchar_19),
.rx_rlv(rx_runlengthviolation[19]),
.rx_recovclkout(rx_recovclkout_19),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[19]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[19]),
.reconfig_togxb(reconfig_togxb_19),
.reconfig_fromgxb(reconfig_fromgxb_19)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_19.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_19.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_19.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_19 = {92{1'b0}};
assign led_char_err_gx[19] = 1'b0;
assign link_status[19] = 1'b0;
assign led_disp_err_19 = 1'b0;
assign txp_19 = 1'b0;
assign rx_recovclkout_19= 1'b0;
assign phy_mgmt_readdata_19 = 32'b0;
assign phy_mgmt_waitrequest_19 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 20 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 20)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch20_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c20_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_20
(
.clk(rx_pcs_clk_c20),
.reset(reset_rx_pcs_clk_c20_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_20),
.alt_sync(rx_syncstatus[20]),
.alt_disperr(rx_disp_err[20]),
.alt_ctrldetect(rx_kchar_20),
.alt_errdetect(rx_char_err_gx[20]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[20]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[20]),
.alt_runlengthviolation(rx_runlengthviolation[20]),
.alt_patterndetect(rx_patterndetect[20]),
.alt_runningdisp(rx_runningdisp[20]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_20),
.altpcs_sync(link_status[20]),
.altpcs_disperr(led_disp_err_20),
.altpcs_ctrldetect(pcs_rx_kchar_20),
.altpcs_errdetect(led_char_err_gx[20]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[20]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[20]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[20])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_20.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_20
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_20),
.phy_mgmt_read(phy_mgmt_read_20),
.phy_mgmt_readdata(phy_mgmt_readdata_20),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_20),
.phy_mgmt_write(phy_mgmt_write_20),
.phy_mgmt_writedata(phy_mgmt_writedata_20),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_20),
.rx_serial_data(rxp_20),
.rx_runningdisp(rx_runningdisp[20]),
.rx_disperr(rx_disp_err[20]),
.rx_errdetect(rx_char_err_gx[20]),
.rx_patterndetect(rx_patterndetect[20]),
.rx_syncstatus(rx_syncstatus[20]),
.tx_clkout(tx_pcs_clk_c20),
.rx_clkout(rx_pcs_clk_c20),
.tx_parallel_data(tx_frame_20),
.tx_datak(tx_kchar_20),
.rx_parallel_data(rx_frame_20),
.rx_datak(rx_kchar_20),
.rx_rlv(rx_runlengthviolation[20]),
.rx_recovclkout(rx_recovclkout_20),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[20]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[20]),
.reconfig_togxb(reconfig_togxb_20),
.reconfig_fromgxb(reconfig_fromgxb_20)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_20.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_20.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_20.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_20 = {92{1'b0}};
assign led_char_err_gx[20] = 1'b0;
assign link_status[20] = 1'b0;
assign led_disp_err_20 = 1'b0;
assign txp_20 = 1'b0;
assign rx_recovclkout_20= 1'b0;
assign phy_mgmt_readdata_20 = 32'b0;
assign phy_mgmt_waitrequest_20 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 21 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 21)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch21_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c21_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_21
(
.clk(rx_pcs_clk_c21),
.reset(reset_rx_pcs_clk_c21_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_21),
.alt_sync(rx_syncstatus[21]),
.alt_disperr(rx_disp_err[21]),
.alt_ctrldetect(rx_kchar_21),
.alt_errdetect(rx_char_err_gx[21]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[21]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[21]),
.alt_runlengthviolation(rx_runlengthviolation[21]),
.alt_patterndetect(rx_patterndetect[21]),
.alt_runningdisp(rx_runningdisp[21]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_21),
.altpcs_sync(link_status[21]),
.altpcs_disperr(led_disp_err_21),
.altpcs_ctrldetect(pcs_rx_kchar_21),
.altpcs_errdetect(led_char_err_gx[21]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[21]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[21]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[21])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_21.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_21
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_21),
.phy_mgmt_read(phy_mgmt_read_21),
.phy_mgmt_readdata(phy_mgmt_readdata_21),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_21),
.phy_mgmt_write(phy_mgmt_write_21),
.phy_mgmt_writedata(phy_mgmt_writedata_21),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_21),
.rx_serial_data(rxp_21),
.rx_runningdisp(rx_runningdisp[21]),
.rx_disperr(rx_disp_err[21]),
.rx_errdetect(rx_char_err_gx[21]),
.rx_patterndetect(rx_patterndetect[21]),
.rx_syncstatus(rx_syncstatus[21]),
.tx_clkout(tx_pcs_clk_c21),
.rx_clkout(rx_pcs_clk_c21),
.tx_parallel_data(tx_frame_21),
.tx_datak(tx_kchar_21),
.rx_parallel_data(rx_frame_21),
.rx_datak(rx_kchar_21),
.rx_rlv(rx_runlengthviolation[21]),
.rx_recovclkout(rx_recovclkout_21),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[21]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[21]),
.reconfig_togxb(reconfig_togxb_21),
.reconfig_fromgxb(reconfig_fromgxb_21)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_21.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_21.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_21.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_21 = {92{1'b0}};
assign led_char_err_gx[21] = 1'b0;
assign link_status[21] = 1'b0;
assign led_disp_err_21 = 1'b0;
assign txp_21 = 1'b0;
assign rx_recovclkout_21= 1'b0;
assign phy_mgmt_readdata_21 = 32'b0;
assign phy_mgmt_waitrequest_21 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 22 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 22)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch22_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c22_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_22
(
.clk(rx_pcs_clk_c22),
.reset(reset_rx_pcs_clk_c22_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_22),
.alt_sync(rx_syncstatus[22]),
.alt_disperr(rx_disp_err[22]),
.alt_ctrldetect(rx_kchar_22),
.alt_errdetect(rx_char_err_gx[22]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[22]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[22]),
.alt_runlengthviolation(rx_runlengthviolation[22]),
.alt_patterndetect(rx_patterndetect[22]),
.alt_runningdisp(rx_runningdisp[22]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_22),
.altpcs_sync(link_status[22]),
.altpcs_disperr(led_disp_err_22),
.altpcs_ctrldetect(pcs_rx_kchar_22),
.altpcs_errdetect(led_char_err_gx[22]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[22]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[22]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[22])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_22.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_22
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_22),
.phy_mgmt_read(phy_mgmt_read_22),
.phy_mgmt_readdata(phy_mgmt_readdata_22),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_22),
.phy_mgmt_write(phy_mgmt_write_22),
.phy_mgmt_writedata(phy_mgmt_writedata_22),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_22),
.rx_serial_data(rxp_22),
.rx_runningdisp(rx_runningdisp[22]),
.rx_disperr(rx_disp_err[22]),
.rx_errdetect(rx_char_err_gx[22]),
.rx_patterndetect(rx_patterndetect[22]),
.rx_syncstatus(rx_syncstatus[22]),
.tx_clkout(tx_pcs_clk_c22),
.rx_clkout(rx_pcs_clk_c22),
.tx_parallel_data(tx_frame_22),
.tx_datak(tx_kchar_22),
.rx_parallel_data(rx_frame_22),
.rx_datak(rx_kchar_22),
.rx_rlv(rx_runlengthviolation[22]),
.rx_recovclkout(rx_recovclkout_22),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[22]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[22]),
.reconfig_togxb(reconfig_togxb_22),
.reconfig_fromgxb(reconfig_fromgxb_22)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_22.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_22.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_22.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_22 = {92{1'b0}};
assign led_char_err_gx[22] = 1'b0;
assign link_status[22] = 1'b0;
assign led_disp_err_22 = 1'b0;
assign txp_22 = 1'b0;
assign rx_recovclkout_22= 1'b0;
assign phy_mgmt_readdata_22 = 32'b0;
assign phy_mgmt_waitrequest_22 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 23 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 23)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch23_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c23_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_23
(
.clk(rx_pcs_clk_c23),
.reset(reset_rx_pcs_clk_c23_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_23),
.alt_sync(rx_syncstatus[23]),
.alt_disperr(rx_disp_err[23]),
.alt_ctrldetect(rx_kchar_23),
.alt_errdetect(rx_char_err_gx[23]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[23]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[23]),
.alt_runlengthviolation(rx_runlengthviolation[23]),
.alt_patterndetect(rx_patterndetect[23]),
.alt_runningdisp(rx_runningdisp[23]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_23),
.altpcs_sync(link_status[23]),
.altpcs_disperr(led_disp_err_23),
.altpcs_ctrldetect(pcs_rx_kchar_23),
.altpcs_errdetect(led_char_err_gx[23]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[23]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[23]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[23])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_23.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_23
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_23),
.phy_mgmt_read(phy_mgmt_read_23),
.phy_mgmt_readdata(phy_mgmt_readdata_23),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_23),
.phy_mgmt_write(phy_mgmt_write_23),
.phy_mgmt_writedata(phy_mgmt_writedata_23),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_23),
.rx_serial_data(rxp_23),
.rx_runningdisp(rx_runningdisp[23]),
.rx_disperr(rx_disp_err[23]),
.rx_errdetect(rx_char_err_gx[23]),
.rx_patterndetect(rx_patterndetect[23]),
.rx_syncstatus(rx_syncstatus[23]),
.tx_clkout(tx_pcs_clk_c23),
.rx_clkout(rx_pcs_clk_c23),
.tx_parallel_data(tx_frame_23),
.tx_datak(tx_kchar_23),
.rx_parallel_data(rx_frame_23),
.rx_datak(rx_kchar_23),
.rx_rlv(rx_runlengthviolation[23]),
.rx_recovclkout(rx_recovclkout_23),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[23]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[23]),
.reconfig_togxb(reconfig_togxb_23),
.reconfig_fromgxb(reconfig_fromgxb_23)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_23.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_23.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_23.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_23 = {92{1'b0}};
assign led_char_err_gx[23] = 1'b0;
assign link_status[23] = 1'b0;
assign led_disp_err_23 = 1'b0;
assign txp_23 = 1'b0;
assign rx_recovclkout_23= 1'b0;
assign phy_mgmt_readdata_23 = 32'b0;
assign phy_mgmt_waitrequest_23 = 1'b0;
end
endgenerate
endmodule // module altera_tse_multi_mac_pcs_pma_gige_phyip
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_PS_PP_PKG_SN_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_DFF_PS_PP_PKG_SN_BLACKBOX_V
/**
* udp_dff$PS_pp$PKG$sN: Positive edge triggered D flip-flop with
* active high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$PS_pp$PKG$sN (
Q ,
D ,
CLK ,
SET ,
SLEEP_B ,
NOTIFIER,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input CLK ;
input SET ;
input SLEEP_B ;
input NOTIFIER;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_PS_PP_PKG_SN_BLACKBOX_V
|
/*
VGA Demo 800x480 at 58Hz
The screen I'm using
http://www.amazon.co.uk/gp/product/B00IR5VRS4?psc=1&redirect=true&ref_=oh_aui_detailpage_o00_s01
http://www.adafruit.com/datasheets/KD50G21-40NT-A1.pdf
if these timings fail, try http://www.adafruit.com/datasheets/AT070TN94.pdf
Pixel Clock (MHz): 30.000
Horizontal (in Pixels)
Active Video: 800
Front Porch: 40
Sync Pulse: 48
Back Porch: 88
Total pixel clock ticks: 976
Vertical (in Lines)
Active Video: 480
Front Porch: 13
Sync Pulse: 3
Back Porch: 32
Total pixel clock ticks: 528
Total pixel clock ticks: 692,640
30,000,000 / 515,328 = 58.215350224 = 58Hz
1 pixel clock = 1/30Mhz = 33ns = 0.033us
*/
module vga_demo
(
CLOCK_PIXEL,
RESET,
VGA_RED,
VGA_GREEN,
VGA_BLUE,
VGA_HS,
VGA_VS
);
input CLOCK_PIXEL;
input RESET;
output VGA_RED;
output VGA_GREEN;
output VGA_BLUE;
output VGA_HS;
output VGA_VS;
/* Internal registers for horizontal signal timing */
reg [10:0] hor_reg; // to count up to 975
reg hor_sync;
wire hor_max = (hor_reg == 975); // to tell when a line is full
/* Internal registers for vertical signal timing */
reg [9:0] ver_reg; // to count up to 527
reg ver_sync;
reg red, green, blue;
wire ver_max = (ver_reg == 527); // to tell when a line is full
// Code
/* Running through line */
always @ (posedge CLOCK_PIXEL or posedge RESET) begin
if (RESET) begin
hor_reg <= 0;
ver_reg <= 0;
end
else if (hor_max) begin
hor_reg <= 0;
/* Running through frame */
if (ver_max)
ver_reg <= 0;
else
ver_reg <= ver_reg + 1;
end else
hor_reg <= hor_reg + 1;
end
always @ (posedge CLOCK_PIXEL or posedge RESET) begin
if (RESET) begin
hor_sync <= 0;
ver_sync <= 0;
red <= 0;
green <= 0;
blue <= 0;
end
else begin
/* Generating the horizontal sync signal */
if (hor_reg == 840) // video (800) + front porch (40)
hor_sync <= 1; // turn on horizontal sync pulse
else if (hor_reg == 928) // video (800) + front porch (40) + Sync Pulse (88)
hor_sync <= 0; // turn off horizontal sync pulse
/* Generating the vertical sync signal */
if (ver_reg == 493) // LINES: video (480) + front porch (13)
ver_sync <= 1; // turn on vertical sync pulse
else if (ver_reg == 496) // LINES: video (480) + front porch (13) + Sync Pulse (3)
ver_sync <= 0; // turn off vertical sync pulse
// black during the porches
if (ver_reg > 480 || hor_reg > 800) begin
red <= 0;
green <= 0;
blue <= 0;
end
else begin
// Draw a single square.
if (hor_reg >= 100 && hor_reg <= 200 && ver_reg >= 100 && ver_reg <= 200) begin
red <= 1;
green <= 1;
blue <= 1;
end
// top border
else if (ver_reg == 0 ) begin
red <= 0;
green <= 1;
blue <= 0;
end
// bottom border
else if (ver_reg == 478 ) begin // Not quite 480 visable
red <= 0;
green <= 1;
blue <= 0;
end
// left border
else if (hor_reg == 0 ) begin
red <= 1;
green <= 0;
blue <= 0;
end
// right border
else if (hor_reg == 780 ) begin // Not quite 800 visable
red <= 1;
green <= 0;
blue <= 0;
end
else begin
red <= 0;
green <= 0;
blue <= 1;
end
end
end
end
// Send the sync signals to the outputh.
// this doc says pulse is positive http://tinyvga.com/vga-timing/800x600@72Hz
assign VGA_HS = hor_sync;
assign VGA_VS = ver_sync;
assign VGA_RED = red;
assign VGA_GREEN = green;
assign VGA_BLUE = blue;
endmodule
|
module DataPath(input clk, reset, ir_write, B_write, pc_src, pc_write, mem_src, mem_write, stack_src, tos, push, pop, output reg z, output [2:0] inst_op);
//pc & inst Memory
reg [4:0] pc, next_pc;
reg [7:0] IR, B_reg;
assign inst_op = IR[7:5];
//data memory
reg [4:0] mem_addr;
reg [7:0] mem_write_data;
wire [7:0] mem_out_data;
//stack
reg [7:0] stack_in;
wire [7:0] stack_out;
//ALU
reg [7:0] alu_A, alu_B;
wire [7:0] alu_out;
reg [7:0] alu_reg;
//Modules
DataMem data_mem (clk, mem_write, mem_addr , mem_write_data, mem_out_data);
Stack stack(clk, tos, push,pop, stack_in, stack_out);
ALU alu(inst_op , alu_A, alu_B, alu_out);
always @(*) begin //calculate the new pc
//PC
case(pc_src)
1'b0: next_pc <= IR[4:0];
1'b1: next_pc <= pc + 1;
endcase
//Stack
case(stack_src)
1'b0: stack_in <= mem_out_data;
1'b1: stack_in <= alu_reg;
endcase
//z
if(stack_out == 8'b0)
z = 1'b1;
else z = 1'b0;
//ALU
alu_A <= stack_out;
alu_B <= B_reg;
//Data Memory
case(mem_src)
1'b0: mem_addr <= IR[4:0];
1'b1: mem_addr <= pc;
endcase
mem_write_data <= stack_out;
end
always @(posedge clk)begin //set new values to registers
if(reset == 1'b0)
begin
if(pc_write)
pc = next_pc;
if(ir_write)
IR <= mem_out_data;
B_reg <= stack_out;
alu_reg <= alu_out;
end
else begin
{pc,IR, B_reg} = 0;
alu_reg = 8'b0;
end
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3B_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__OR3B_PP_BLACKBOX_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3B_PP_BLACKBOX_V
|
/*
Pong clone for the Altera DE2.
Copyright (c) 2014 Felix Mo.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
----
INFO
----
There is a 3 second delay between each round.
The game ends when a player scores 10 points.
The scores are shown on the seven-segment displays (P1 - HEX6, P2 - HEX4).
The winner is displayed on HEX7 & HEX6.
When the game is over, use SW17 to restart the game.
--------
CONTROLS
--------
- Player 1 -
'W' - up
'S' - down
- Player 2 -
KEY3 - up
KEY0 - down
- Game -
SW17 - reset
---------------
ACKNOWLEDGMENTS
---------------
John Loomis (http://www.johnloomis.org/) for PS/2 keyboard input modules
Simon Moore (http://www.cl.cam.ac.uk/~swm11/) for VGA output module
*/
// VGA signal params
// horizontal and vertical sync parameters for 1280x1024 at 60Hz
// using 108MHz video_clock
// horizontal
`define ha 112 // duration of pulse to VGA_HSYNC signifying end of row of data
`define hb 248 // back porch
`define hc 1280 // horizontal screen size (px)
`define hd 48 // front porch
// vertical
`define va 3 // duration of pulse to VGA_HSYNC signifying end of row of data
`define vb 38 // back porch
`define vc 1024 // vertical screen size (px)
`define vd 1 // front porch
// Ball and bat size & speed parameters
`define ballsize 16
`define ballspeed 3
`define batwidth 16
`define batheight 128
`define batspeed 10
// Top level module
module pong(
CLOCK_27,
CLOCK_50,
KEY,
SW,
PS2_CLK,
PS2_DAT,
VGA_R,
VGA_G,
VGA_B,
VGA_CLK,
VGA_BLANK,
VGA_HS,
VGA_VS,
VGA_SYNC,
TD_RESET,
LEDR,
HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7
);
input CLOCK_27, CLOCK_50;
input PS2_CLK, PS2_DAT;
input [3:0] KEY;
input [17:0] SW;
output [9:0] VGA_R, VGA_G, VGA_B;
output VGA_CLK, VGA_BLANK, VGA_HS, VGA_VS, VGA_SYNC;
output TD_RESET;
output [17:0] LEDR;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
wire video_clock;
// convert CLOCK_27 to required clock speed
pll108MHz pll(.inclk0(CLOCK_27), .c0(video_clock));
assign VGA_CLK = video_clock;
assign VGA_SYNC = 0;
wire candraw;
wire start; // 1 = beginning of frame
wire ball_on;
// Location of pixel to draw
wire [10:0] x;
wire [10:0] y;
// Bats locations
wire [10:0] p1_y;
wire [10:0] p2_y;
// Ball location
wire [10:0] ball_x;
wire [10:0] ball_y;
// Scores
wire [3:0] p1_score;
wire [3:0] p2_score;
wire [1:0] winner; // 0 = none, 1 = P1, 2 = P2
assign LEDR[17] = (winner > 0); // light up LEDR-17 to alert user to reset game
// Keyboard input
wire [7:0] scan_code;
wire read, scan_ready;
reg [7:0] scan_history[1:2];
always @ (posedge scan_ready)
begin
scan_history[2] <= scan_history[1];
scan_history[1] <= scan_code;
end
assign TD_RESET = 1'b1;
// VGA output module
vga v(
.clk(video_clock),
.vsync(VGA_VS),
.hsync(VGA_HS),
.x(x),
.y(y),
.can_draw(candraw),
.start_of_frame(start)
);
// Module that renders graphics on-screen
graphics g(
.clk(video_clock),
.candraw(candraw),
.x(x),
.y(y),
.p1_y(p1_y),
.p2_y(p2_y),
.ball_on(ball_on),
.ball_x(ball_x),
.ball_y(ball_y),
.red(VGA_R),
.green(VGA_G),
.blue(VGA_B),
.vga_blank(VGA_BLANK)
);
// Game logic module
gamelogic gl(
.clock50(CLOCK_50),
.video_clock(video_clock),
.start(start),
.reset(SW[17]),
.p1_up((scan_history[1] == 'h1d) && (scan_history[2][7:4] != 'hF)), // 'W'
.p1_down((scan_history[1] == 'h1b) && (scan_history[2][7:4] != 'hF)), // 'S'
.p2_up(~KEY[3]),
.p2_down(~KEY[0]),
.p1_y(p1_y),
.p2_y(p2_y),
.ball_on(ball_on),
.ball_x(ball_x),
.ball_y(ball_y),
.p1_score(p1_score),
.p2_score(p2_score),
.winner(winner)
);
// PS/2 keyboard input module
// Credit: http://www.johnloomis.org/digitallab/ps2lab1/ps2lab1.html
keyboard keybd(
.keyboard_clk(PS2_CLK),
.keyboard_data(PS2_DAT),
.clock50(CLOCK_50),
.reset(0),
.read(read),
.scan_ready(scan_ready),
.scan_code(scan_code)
);
// Module to regulate keyboard input
// Credit: http://www.johnloomis.org/digitallab/ps2lab1/ps2lab1.html
oneshot pulser(
.pulse_out(read),
.trigger_in(scan_ready),
.clk(CLOCK_50)
);
// Module to output info to the seven-segment displays
sevenseg ss(
.seg0(HEX0),
.seg1(HEX1),
.seg2(HEX2),
.seg3(HEX3),
.seg4(HEX4),
.seg5(HEX5),
.seg6(HEX6),
.seg7(HEX7),
.score_p1(p1_score),
.score_p2(p2_score),
.winner(winner)
);
endmodule
// Module that renders graphics on-screen
// Draws objects pixel by pixel
module graphics(
clk,
candraw,
x,
y,
p1_y,
p2_y,
ball_on,
ball_x,
ball_y,
red,
green,
blue,
vga_blank
);
input clk;
input candraw;
input ball_on;
input [10:0] x, y, p1_y, p2_y, ball_x, ball_y;
output reg [9:0] red, green, blue;
output vga_blank;
reg n_vga_blank;
assign vga_blank = !n_vga_blank;
always @(posedge clk) begin
if (candraw) begin
n_vga_blank <= 1'b0;
// draw P1 (left) bat
if (x < `batwidth && y > p1_y && y < p1_y + `batheight) begin
// white bat
red <= 10'b1111111111;
green <= 10'b1111111111;
blue <= 10'b1111111111;
end
// draw P2 (right) bat
else if (x > `hc - `batwidth && y > p2_y && y < p2_y + `batheight) begin
// white bat
red <= 10'b1111111111;
green <= 10'b1111111111;
blue <= 10'b1111111111;
end
// draw ball
else if (ball_on && x > ball_x && x < ball_x + `ballsize && y > ball_y && y < ball_y + `ballsize) begin
// white ball
red <= 10'b1111111111;
green <= 10'b1111111111;
blue <= 10'b1111111111;
end
// black background
else begin
red <= 10'b0000000000;
green <= 10'b0000000000;
blue <= 10'b0000000000;
end
end else begin
// if we are not in the visible area, we must set the screen blank
n_vga_blank <= 1'b1;
end
end
endmodule
// VGA output module
// Controls the output parameters
// Credit: https://www.cl.cam.ac.uk/teaching/1011/ECAD+Arch/files/params.sv
module vga(
clk,
vsync,
hsync,
x,
y,
can_draw,
start_of_frame
);
input clk;
output vsync, hsync;
output [10:0] x, y;
output can_draw;
output start_of_frame;
assign x = h - `ha - `hb;
assign y = v - `va - `vb;
assign can_draw = (h >= (`ha + `hb)) && (h < (`ha + `hb + `hc))
&& (v >= (`va + `vb)) && (v < (`va + `vb + `vc));
assign vsync = vga_vsync;
assign hsync = vga_hsync;
assign start_of_frame = startframe;
// horizontal and vertical counts
reg [10:0] h;
reg [10:0] v;
reg vga_vsync;
reg vga_hsync;
reg startframe;
always @(posedge clk) begin
// if we are not at the end of a row, increment h
if (h < (`ha + `hb + `hc + `hd)) begin
h <= h + 11'd1;
// otherwise set h = 0 and increment v (unless we are at the bottom of the screen)
end else begin
h <= 11'd0;
v <= (v < (`va + `vb + `vc + `vd)) ? v + 11'd1 : 11'd0;
end
vga_hsync <= h > `ha;
vga_vsync <= v > `va;
startframe <= (h == 11'd0) && (v == 11'd0);
end
endmodule
// Counter for incrementing/decrementing bat position within bounds of screen
module batpos(
clk,
up,
down,
reset,
speed,
value
);
input clk;
input up, down; // signal for counting up/down
input [4:0] speed; // # of px to increment bats by
input reset;
output [10:0] value; // max value is 1024 (px), 11 bits wide
reg [10:0] value;
initial begin
value <= `vc / 2;
end
always @ (posedge clk or posedge reset) begin
if (reset) begin
// go back to the middle
value <= `vc / 2;
end
else begin
if (up) begin
// prevent bat from going beyond upper bound of the screen
if ((value - speed) > `va) begin
// move bat up the screen
value <= value - speed;
end
end
else if (down) begin
// prevent bat from going beyond lower bound of the screen
if ((value + speed) < (`vc - `batheight)) begin
// move bat down the screen
value <= value + speed;
end
end
end
end
endmodule
// Module with counters that determining the ball position
module ballpos(
clk,
reset,
speed,
dir_x, // 0 = LEFT, 1 = RIGHT
dir_y, // 0 = UP, 1 = DOWN
value_x,
value_y
);
input clk;
input [4:0] speed; // # of px to increment bat by
input reset;
input dir_x, dir_y;
output [10:0] value_x, value_y; // max value is 1024 (px), 11 bits wide
reg [10:0] value_x, value_y;
// the initial position of the ball is at the top of the screen, in the middle,
initial begin
value_x <= `hc / 2 - (`ballsize / 2);
value_y <= `va + 7;
end
always @ (posedge clk or posedge reset) begin
if (reset) begin
value_x <= `hc / 2 - (`ballsize / 2);
value_y <= `va + 7;
end
else begin
// increment x
if (dir_x) begin
// right
value_x <= value_x + speed;
end
else begin
// left
value_x <= value_x - speed;
end
// increment y
if (dir_y) begin
// down
value_y <= value_y + speed;
end
else begin
// up
value_y <= value_y - speed;
end
end
end
endmodule
// Ball collision detection module
// Detects collisions between the ball and the bats and walls and
// determines what direction the ball should go
module ballcollisions(
clk,
reset,
p1_y,
p2_y,
ball_x,
ball_y,
dir_x,
dir_y,
oob // whether ball is out of bounds
);
input clk, reset;
input [10:0] p1_y, p2_y, ball_x, ball_y;
output dir_x, dir_y, oob;
reg dir_x, dir_y, oob;
initial begin
dir_x <= 0;
dir_y <= 1;
oob <= 0;
end
always @ (posedge clk) begin
if (reset) begin
dir_x <= ~dir_x; // alternate starting direction every round
dir_y <= 1;
oob <= 0;
end
else begin
// out of bounds (i.e. one of the players missed the ball)
if (ball_x <= 0 || ball_x >= `hc) begin
oob = 1;
end
else begin
oob = 0;
end
// collision with top & bottom walls
if (ball_y <= `va + 5) begin
dir_y = 1;
end
if (ball_y >= `vc - `ballsize) begin
dir_y = 0;
end
// collision with P1 bat
if (ball_x <= `batwidth && ball_y + `ballsize >= p1_y && ball_y <= p1_y + `batheight) begin
dir_x = 1; // reverse direction
if (ball_y + `ballsize <= p1_y + (`batheight / 2)) begin
// collision with top half of p1 bat, go up
dir_y = 0;
end
else begin
// collision with bottom half of p1 bat, go down
dir_y = 1;
end
end
// collision with P2 bat
else if (ball_x >= `hc - `batwidth -`ballsize && ball_y + `ballsize <= p2_y + `batheight && ball_y >= p2_y) begin
dir_x = 0; // reverse direction
if (ball_y + `ballsize <= p2_y + (`batheight / 2)) begin
// collision with top half of p1 bat, go up
dir_y = 0;
end
else begin
// collision with bottom half of p1 bat, go down
dir_y = 1;
end
end
end
end
endmodule
// Game logic module
// Produces the data for output (VGA & HEX) given our inputs
module gamelogic(
clock50,
video_clock,
start,
reset,
p1_up,
p1_down,
p2_up,
p2_down,
p1_y,
p2_y,
ball_on,
ball_x,
ball_y,
p1_score,
p2_score,
winner
);
input clock50;
input reset;
input video_clock;
input start;
input p1_up, p1_down, p2_up, p2_down;
output [10:0] p1_y, p2_y;
output [10:0] ball_x, ball_y;
output ball_on;
output [3:0] p1_score, p2_score;
output [1:0] winner;
reg [3:0] p1_score, p2_score; // 0 - 10
initial begin
p1_score <= 4'b0;
p2_score <= 4'b0;
end
reg [1:0] winner; // 0 = none, 1 = P1, 2 = P2
initial begin
winner <= 0;
end
reg ball_on;
initial begin
ball_on <= 1;
end
wire dir_x; // 0 = LEFT, 1 = RIGHT
wire dir_y; // 0 = UP, 1 = DOWN
wire outofbounds;
reg newround;
reg [25:0] count_sec;
reg [1:0] count_secs;
always @ (posedge clock50) begin
if (outofbounds) begin
ball_on = 0;
// Second counter
if (count_sec == 26'd49_999_999) begin
// 50,000,000 clock cycles per second since we're using CLOCK_50 (50 MHz)
count_sec = 26'd0;
count_secs = count_secs + 1;
end
else begin
// Increment every clock cycle
count_sec = count_sec + 1;
end
// 3 secs after ball is out of bounds
if (count_secs == 3) begin
// Increment the score on the first clock cycle
// We need to check for this so the score is only incremented ONCE
if (count_sec == 26'd1) begin
if (dir_x) begin
// Out of bounds on the right
p1_score = p1_score + 1;
end
else begin
// Out of bounds on the left
p2_score = p2_score + 1;
end
end
// Check if someone has won
if (p1_score == 4'd10) begin
winner = 1;
end
else if (p2_score == 4'd10) begin
winner = 2;
end
// New round
ball_on = 1;
newround = 1;
end
end
else begin
if (newround) begin
newround = 0;
end
count_secs = 1'b0;
count_sec = 26'd0;
if (reset) begin
p1_score = 0;
p2_score = 0;
winner = 0;
end
end
end
// Module for controlling player 1's bat
batpos b1 (
.clk(video_clock && start),
.up(p1_up),
.down(p1_down),
.reset(reset),
.speed(`batspeed),
.value(p1_y)
);
// Module for controlling player 2's bat
batpos b2 (
.clk(video_clock && start),
.up(p2_up),
.down(p2_down),
.reset(reset),
.speed(`batspeed),
.value(p2_y)
);
// Ball collision detection module
ballcollisions bcs (
.clk(video_clock && start && ball_on),
.reset(reset || newround),
.p1_y(p1_y),
.p2_y(p2_y),
.ball_x(ball_x),
.ball_y(ball_y),
.dir_x(dir_x),
.dir_y(dir_y),
.oob(outofbounds)
);
// Module with counters that determining the ball position
ballpos bp (
.clk(video_clock && start && ball_on),
.reset(reset || newround || (winner > 0)),
.speed(`ballspeed),
.dir_x(dir_x),
.dir_y(dir_y),
.value_x(ball_x),
.value_y(ball_y)
);
endmodule
// Module to output info to the seven-segement displays
module sevenseg(seg0, seg1, seg2, seg3, seg4, seg5, seg6, seg7, score_p1, score_p2, winner);
input [3:0] score_p1, score_p2;
input [1:0] winner; // 0 = none, 1 = P1, 2 = P2
output [6:0] seg0, seg1, seg2, seg3, seg4, seg5, seg6, seg7;
reg [6:0] seg0, seg1, seg2, seg3, seg4, seg5, seg6, seg7;
always @ (score_p1 or winner) begin
if (winner > 0) begin
// Show the winner on HEX7 and HEX6 (i.e. P1 or P2)
seg7 = 7'b0001100; // P
case (winner)
2'h1: seg6 = 7'b1111001; // 1
2'h2: seg6 = 7'b0100100; // 2
default: seg6 = 7'b1111111;
endcase
end
else begin
seg7 = 7'b1111111;
case (score_p1)
4'h0: seg6 = 7'b1000000;
4'h1: seg6 = 7'b1111001;
4'h2: seg6 = 7'b0100100;
4'h3: seg6 = 7'b0110000;
4'h4: seg6 = 7'b0011001;
4'h5: seg6 = 7'b0010010;
4'h6: seg6 = 7'b0000010;
4'h7: seg6 = 7'b1111000;
4'h8: seg6 = 7'b0000000;
4'h9: seg6 = 7'b0011000;
default: seg6 = 7'b1111111;
endcase
end
end
always @ (score_p2 or winner) begin
if (winner > 0) begin
// Unused; blank out
seg5 = 7'b1111111;
seg4 = 7'b1111111;
end
else begin
seg5 = 7'b1111111;
case (score_p2)
4'h0: seg4 = 7'b1000000;
4'h1: seg4 = 7'b1111001;
4'h2: seg4 = 7'b0100100;
4'h3: seg4 = 7'b0110000;
4'h4: seg4 = 7'b0011001;
4'h5: seg4 = 7'b0010010;
4'h6: seg4 = 7'b0000010;
4'h7: seg4 = 7'b1111000;
4'h8: seg4 = 7'b0000000;
4'h9: seg4 = 7'b0011000;
default: seg4 = 7'b1111111;
endcase
end
end
// Blank out unused displays
always begin
seg3 = 7'b1111111;
seg2 = 7'b1111111;
seg1 = 7'b1111111;
seg0 = 7'b1111111;
end
endmodule |
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx2;
wire unxunused_resetxx3;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx2 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module gpac_adc_rx_core #(
parameter ABUSWIDTH = 16,
parameter [1:0] ADC_ID = 0,
parameter [0:0] HEADER_ID = 0
) (
input wire ADC_ENC,
input wire [13:0] ADC_IN,
input wire ADC_SYNC,
input wire ADC_TRIGGER,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
output wire LOST_ERROR
);
localparam VERSION = 1;
// 0 - soft reset
// 1 - start/status
//TODO:
// - external trigger /rising falling
wire SOFT_RST;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
reg [7:0] status_regs [15:0];
always @(posedge BUS_CLK) begin
if(RST) begin
status_regs[0] <= 0;
status_regs[1] <= 0;
status_regs[2] <= 8'b0000_0000; // CONF_START_WITH_SYNC = TRUE
status_regs[3] <= 0;
status_regs[4] <= 0;
status_regs[5] <= 0;
status_regs[6] <= 1;
status_regs[7] <= 0;
status_regs[8] <= 0;
end
else if(BUS_WR && BUS_ADD < 16)
status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN;
end
wire START;
assign START = (BUS_ADD==1 && BUS_WR);
wire CONF_START_WITH_SYNC;
assign CONF_START_WITH_SYNC = status_regs[2][0];
wire CONF_EN_EX_TRIGGER;
assign CONF_EN_EX_TRIGGER = status_regs[2][1];
wire CONF_SINGLE_DATA;
assign CONF_SINGLE_DATA = status_regs[2][2];
wire [23:0] CONF_DATA_CNT;
assign CONF_DATA_CNT = {status_regs[5], status_regs[4], status_regs[3]};
wire [7:0] CONF_SAMPLE_SKIP = status_regs[6];
wire [7:0] CONF_SAMPEL_DLY = status_regs[7];
reg [7:0] CONF_ERROR_LOST;
assign LOST_ERROR = CONF_ERROR_LOST != 0;
reg CONF_DONE;
wire [7:0] BUS_STATUS_OUT;
assign BUS_STATUS_OUT = status_regs[BUS_ADD[3:0]];
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT <= {7'b0, CONF_DONE};
else if(BUS_ADD == 8)
BUS_DATA_OUT <= CONF_ERROR_LOST;
else if(BUS_ADD < 16)
BUS_DATA_OUT <= BUS_STATUS_OUT;
end
end
wire rst_adc_sync;
cdc_reset_sync isync_rst (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(ADC_ENC), .pulse_out(rst_adc_sync));
wire start_adc_sync;
cdc_pulse_sync istart_rst (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(ADC_ENC), .pulse_out(start_adc_sync));
wire adc_sync_pulse;
pulse_gen_rising pulse_adc_sync (.clk_in(ADC_ENC), .in(ADC_SYNC), .out(adc_sync_pulse));
//long reset is needed
reg [7:0] sync_cnt;
always @(posedge BUS_CLK) begin
if(RST)
sync_cnt <= 120;
else if(sync_cnt != 100)
sync_cnt <= sync_cnt +1;
end
wire RST_LONG;
assign RST_LONG = sync_cnt[7];
/*
reg [7:0] align_cnt;
always @(posedge ADC_ENC) begin
if(adc_sync_pulse)
align_cnt <= 0;
else if(align_cnt == (CONF_SAMPLE_SKIP - 1))
align_cnt <= 0;
else
align_cnt <= align_cnt + 1;
end
*/
reg adc_sync_wait;
always @(posedge ADC_ENC) begin
if(rst_adc_sync)
adc_sync_wait <= 0;
else if(start_adc_sync)
adc_sync_wait <= 1;
else if (adc_sync_pulse)
adc_sync_wait <= 0;
end
wire start_data_count;
assign start_data_count = (CONF_START_WITH_SYNC ? (adc_sync_wait && adc_sync_pulse) : start_adc_sync) || ( CONF_EN_EX_TRIGGER && ADC_TRIGGER);
reg [23:0] rec_cnt;
always @(posedge ADC_ENC) begin
if(rst_adc_sync)
rec_cnt <= 0;
else if(start_data_count && (rec_cnt > CONF_DATA_CNT || rec_cnt == 0))
rec_cnt <= 1;
else if(rec_cnt != 24'hff_ffff && rec_cnt > 0 && CONF_DATA_CNT != 0)
rec_cnt <= rec_cnt + 1;
end
wire DONE;
assign DONE = rec_cnt > CONF_DATA_CNT;
reg cdc_fifo_write_single;
always @(*) begin
if(CONF_DATA_CNT==0 && rec_cnt>=1) //forever
cdc_fifo_write_single = 1;
else if(rec_cnt>=1 && rec_cnt <= CONF_DATA_CNT) //to CONF_DATA_CNT
cdc_fifo_write_single = 1;
else
cdc_fifo_write_single = 0;
end
reg [13:0] prev_data;
reg prev_sync;
reg prev_ready;
always @(posedge ADC_ENC) begin
if(rst_adc_sync || start_adc_sync)
prev_ready <= 0;
else
prev_ready <= !prev_ready;
end
//
reg [13:0] ADC_IN_DLY, adc_dly_mem;
reg [13:0] dly_mem [255:0];
reg [7:0] dly_addr_read, dly_addr_write;
always @(posedge ADC_ENC)
if(rst_adc_sync)
dly_addr_write <= 0;
else
dly_addr_write <= dly_addr_write + 1;
always @(posedge ADC_ENC)
dly_mem[dly_addr_write] <= ADC_IN;
always @(posedge ADC_ENC)
adc_dly_mem <= dly_mem[dly_addr_read];
always @(*) begin
dly_addr_read = dly_addr_write - CONF_SAMPEL_DLY;
ADC_IN_DLY = CONF_SAMPEL_DLY == 0 ? ADC_IN : adc_dly_mem;
end
//
always @(posedge ADC_ENC) begin
prev_data <= ADC_IN_DLY;
prev_sync <= ADC_SYNC;
end
wire fifo_full, cdc_fifo_empty, cdc_fifo_write_double;
assign cdc_fifo_write_double = cdc_fifo_write_single && prev_ready; //write every second
wire wfull;
reg cdc_fifo_write;
always @(posedge ADC_ENC) begin
if(rst_adc_sync)
CONF_ERROR_LOST <= 0;
else if (CONF_ERROR_LOST!=8'hff && wfull && cdc_fifo_write)
CONF_ERROR_LOST <= CONF_ERROR_LOST +1;
end
reg [31:0] data_to_fifo;
always @(*) begin
if(CONF_SINGLE_DATA)
data_to_fifo = {HEADER_ID, ADC_ID, CONF_EN_EX_TRIGGER ? rec_cnt == 1 : ADC_SYNC, 14'b0, ADC_IN_DLY};
else
data_to_fifo = {HEADER_ID, ADC_ID, prev_sync, prev_data, ADC_IN_DLY};
if(CONF_SINGLE_DATA)
cdc_fifo_write = cdc_fifo_write_single;
else
cdc_fifo_write = cdc_fifo_write_double;
end
wire [31:0] cdc_data_out;
cdc_syncfifo #(
.DSIZE(32),
.ASIZE(3)
) cdc_syncfifo_i (
.rdata(cdc_data_out),
.wfull(wfull),
.rempty(cdc_fifo_empty),
.wdata(data_to_fifo), //.wdata({ADC_SYNC,2'd0,ADC_SYNC,14'd0,adc_des}),
.winc(cdc_fifo_write),
.wclk(ADC_ENC),
.wrst(RST_LONG),
.rinc(!fifo_full),
.rclk(BUS_CLK),
.rrst(RST_LONG)
);
gerneric_fifo #(
.DATA_SIZE(32),
.DEPTH(1024)
) fifo_i (
.clk(BUS_CLK),
.reset(RST_LONG | BUS_RST),
.write(!cdc_fifo_empty),
.read(FIFO_READ),
.data_in(cdc_data_out),
.full(fifo_full),
.empty(FIFO_EMPTY),
.data_out(FIFO_DATA[31:0]),
.size()
);
//assign FIFO_DATA[31:30] = 0;
wire DONE_SYNC;
cdc_pulse_sync done_pulse_sync (.clk_in(ADC_ENC), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
always @(posedge BUS_CLK)
if(RST)
CONF_DONE <= 1;
else if(START)
CONF_DONE <= 0;
else if(DONE_SYNC)
CONF_DONE <= 1;
endmodule
|
`timescale 1ns / 1ps
module control_test();
reg power, start, weight_ch, mode_ch, clk;
wire [2:0]state, nextstate, weight_ch_light;
wire start_pause_light, water_in_light,
parameter TIME = 1000, DELAY = 10;
controler CONTROLER (
.power(power),
.start_pause(start),
.weight_ch(weight_ch),
.mode_ch(mode_ch),
.weight_ch(weight_ch),
.clk(clk),
.start_pause_light(start_pause_light),
.weight_ch_light(weight_ch_light),
.water_in_light(water_in_light),
.water_out_light(water_out_light),
.washing_light(washing_light),
.rinsing_light(rinsing_light),
.dewatering_light(dewatering_light),
.buzzer_lamp(dewatering_light),
.state(state),
.nextstate(nextstate)
);
initial begin
clk = 0; w_r_d_end = 0;
#TIME $finish;
end
always begin
power = 1; w_r_d = 1; reset = 0; start = 0;
#50 w_r_d = 2;
#50 w_r_d = 3;
#50 w_r_d = 4;
#50 w_r_d = 6;
#3 start = 1;
// #50 w_r_d = 7;
#100 w_r_d_end[2] = 1;
#100 w_r_d_end[1] = 1;
// #100 w_r_d_end[0] = 1;
#100 w_r_d_end = 0;
end
always begin
#DELAY clk = ~clk;
end
endmodule
|
module alu8b (input wire [7:0] A_in,
input wire [7:0] B_in,
input wire C_in,
input wire [2:0] Opcode_in,
output wire [7:0] Result_out,
output wire C_out);
reg [7:0] reg_result;
reg reg_cout;
wire [7:0] temp_sum;
wire temp_cout;
assign Result_out = reg_result;
assign C_out = reg_cout;
assign {temp_cout, temp_sum} = A_in + B_in + C_in;
always @ ( * ) begin
reg_cout = 1'b0; //default carry out
case (Opcode_in)
3'b000: // A+B+Cin
begin
reg_cout = temp_cout;
reg_result = temp_sum;
end
3'b001: // A-B
reg_result = A_in - B_in;
3'b010: // A & B
reg_result = A_in & B_in;
3'b011: // A|B
reg_result = A_in | B_in;
3'b100: // A % B
reg_result = A_in % B_in;
default:
reg_result = 8'b0;
endcase
end
endmodule // alu8b
|
// Issue-Execute Pipeline Register
module ex_pipe_reg
(
input wire clk,
input wire reset,
input wire clr,
input wire valid_ex_pipe_reg_i,
// Inputs from the instr decoder
input wire[2:0] funct3_ex_pipe_reg_i,
input wire[6:0] op_ex_pipe_reg_i,
input wire[4:0] rs1_ex_pipe_reg_i,
input wire[4:0] rs2_ex_pipe_reg_i,
input wire[4:0] rd_ex_pipe_reg_i,
input wire is_r_type_ex_pipe_reg_i,
input wire is_i_type_ex_pipe_reg_i,
input wire is_s_type_ex_pipe_reg_i,
input wire is_b_type_ex_pipe_reg_i,
input wire is_u_type_ex_pipe_reg_i,
input wire is_j_type_ex_pipe_reg_i,
// Inputs from the control unit
input wire[1:0] pc_sel_ex_pipe_reg_i,
input wire op1sel_ex_pipe_reg_i,
input wire[1:0] op2sel_ex_pipe_reg_i,
input wire[1:0] wb_sel_ex_pipe_reg_i,
input wire pc4_sel_ex_pipe_reg_i,
input wire mem_wr_ex_pipe_reg_i,
input wire cpr_en_ex_pipe_reg_i,
input wire wa_sel_ex_pipe_reg_i,
input wire rf_en_ex_pipe_reg_i,
input wire[5:0] alu_fun_ex_pipe_reg_i,
// PC related inputs from issue stage
input wire[31:0] next_seq_pc_ex_pipe_reg_i,
input wire[31:0] curr_pc_ex_pipe_reg_i,
input wire[31:0] next_brn_pc_ex_pipe_reg_i,
input wire[31:0] next_pred_pc_ex_pipe_reg_i,
// Inputs from sign extend units
input wire[31:0] sext_imm_ex_pipe_reg_i,
// Inputs from register file
input wire[31:0] r_data_p1_ex_pipe_reg_i,
input wire[31:0] r_data_p2_ex_pipe_reg_i,
// Inputs from the issue stage
input wire jump_ex_pipe_reg_i,
input wire brn_pred_ex_pipe_reg_i,
// Register outputs
output wire valid_ex_pipe_reg_o,
output wire[2:0] funct3_ex_pipe_reg_o,
output wire[6:0] op_ex_pipe_reg_o,
output wire[4:0] rs1_ex_pipe_reg_o,
output wire[4:0] rs2_ex_pipe_reg_o,
output wire[4:0] rd_ex_pipe_reg_o,
output wire is_r_type_ex_pipe_reg_o,
output wire is_i_type_ex_pipe_reg_o,
output wire is_s_type_ex_pipe_reg_o,
output wire is_b_type_ex_pipe_reg_o,
output wire is_u_type_ex_pipe_reg_o,
output wire is_j_type_ex_pipe_reg_o,
output wire[1:0] pc_sel_ex_pipe_reg_o,
output wire op1sel_ex_pipe_reg_o,
output wire[1:0] op2sel_ex_pipe_reg_o,
output wire[1:0] wb_sel_ex_pipe_reg_o,
output wire pc4_sel_ex_pipe_reg_o,
output wire mem_wr_ex_pipe_reg_o,
output wire cpr_en_ex_pipe_reg_o,
output wire wa_sel_ex_pipe_reg_o,
output wire rf_en_ex_pipe_reg_o,
output wire[5:0] alu_fun_ex_pipe_reg_o,
output wire[31:0] next_seq_pc_ex_pipe_reg_o,
output wire[31:0] curr_pc_ex_pipe_reg_o,
output wire[31:0] next_brn_pc_ex_pipe_reg_o,
output wire[31:0] next_pred_pc_ex_pipe_reg_o,
output wire[31:0] sext_imm_ex_pipe_reg_o,
output wire[31:0] r_data_p1_ex_pipe_reg_o,
output wire[31:0] r_data_p2_ex_pipe_reg_o,
output wire jump_ex_pipe_reg_o,
output wire brn_pred_ex_pipe_reg_o
);
reg valid_ex_pipe_reg;
reg[2:0] funct3_ex_pipe_reg;
reg[6:0] op_ex_pipe_reg;
reg[4:0] rs1_ex_pipe_reg;
reg[4:0] rs2_ex_pipe_reg;
reg[4:0] rd_ex_pipe_reg;
reg is_r_type_ex_pipe_reg;
reg is_i_type_ex_pipe_reg;
reg is_s_type_ex_pipe_reg;
reg is_b_type_ex_pipe_reg;
reg is_u_type_ex_pipe_reg;
reg is_j_type_ex_pipe_reg;
reg[1:0] pc_sel_ex_pipe_reg;
reg op1sel_ex_pipe_reg;
reg[1:0] op2sel_ex_pipe_reg;
reg[1:0] wb_sel_ex_pipe_reg;
reg pc4_sel_ex_pipe_reg;
reg mem_wr_ex_pipe_reg;
reg cpr_en_ex_pipe_reg;
reg wa_sel_ex_pipe_reg;
reg rf_en_ex_pipe_reg;
reg[5:0] alu_fun_ex_pipe_reg;
reg[31:0] next_seq_pc_ex_pipe_reg;
reg[31:0] curr_pc_ex_pipe_reg;
reg[31:0] next_brn_pc_ex_pipe_reg;
reg[31:0] next_pred_pc_ex_pipe_reg;
reg[31:0] sext_imm_ex_pipe_reg;
reg[31:0] r_data_p1_ex_pipe_reg;
reg[31:0] r_data_p2_ex_pipe_reg;
reg jump_ex_pipe_reg;
reg brn_pred_ex_pipe_reg;
assign valid_ex_pipe_reg_o = valid_ex_pipe_reg;
assign funct3_ex_pipe_reg_o = funct3_ex_pipe_reg;
assign op_ex_pipe_reg_o = op_ex_pipe_reg;
assign rs1_ex_pipe_reg_o = rs1_ex_pipe_reg;
assign rs2_ex_pipe_reg_o = rs2_ex_pipe_reg;
assign rd_ex_pipe_reg_o = rd_ex_pipe_reg;
assign is_r_type_ex_pipe_reg_o = is_r_type_ex_pipe_reg;
assign is_i_type_ex_pipe_reg_o = is_i_type_ex_pipe_reg;
assign is_s_type_ex_pipe_reg_o = is_s_type_ex_pipe_reg;
assign is_b_type_ex_pipe_reg_o = is_b_type_ex_pipe_reg;
assign is_u_type_ex_pipe_reg_o = is_u_type_ex_pipe_reg;
assign is_j_type_ex_pipe_reg_o = is_j_type_ex_pipe_reg;
assign pc_sel_ex_pipe_reg_o = pc_sel_ex_pipe_reg;
assign op1sel_ex_pipe_reg_o = op1sel_ex_pipe_reg;
assign op2sel_ex_pipe_reg_o = op2sel_ex_pipe_reg;
assign wb_sel_ex_pipe_reg_o = wb_sel_ex_pipe_reg;
assign pc4_sel_ex_pipe_reg_o = pc4_sel_ex_pipe_reg;
assign mem_wr_ex_pipe_reg_o = mem_wr_ex_pipe_reg;
assign cpr_en_ex_pipe_reg_o = cpr_en_ex_pipe_reg;
assign wa_sel_ex_pipe_reg_o = wa_sel_ex_pipe_reg;
assign rf_en_ex_pipe_reg_o = rf_en_ex_pipe_reg;
assign alu_fun_ex_pipe_reg_o = alu_fun_ex_pipe_reg;
assign next_seq_pc_ex_pipe_reg_o = next_seq_pc_ex_pipe_reg;
assign curr_pc_ex_pipe_reg_o = curr_pc_ex_pipe_reg;
assign next_brn_pc_ex_pipe_reg_o = next_brn_pc_ex_pipe_reg;
assign next_pred_pc_ex_pipe_reg_o = next_pred_pc_ex_pipe_reg;
assign sext_imm_ex_pipe_reg_o = sext_imm_ex_pipe_reg;
assign r_data_p1_ex_pipe_reg_o = r_data_p1_ex_pipe_reg;
assign r_data_p2_ex_pipe_reg_o = r_data_p2_ex_pipe_reg;
assign jump_ex_pipe_reg_o = jump_ex_pipe_reg;
assign brn_pred_ex_pipe_reg_o = brn_pred_ex_pipe_reg;
always @ (posedge clk)
if (reset | clr)
begin
valid_ex_pipe_reg <= 1'b0;
funct3_ex_pipe_reg <= 3'b0;
op_ex_pipe_reg <= 7'b0;
rs1_ex_pipe_reg <= 4'b0;
rs2_ex_pipe_reg <= 4'b0;
rd_ex_pipe_reg <= 4'b0;
is_r_type_ex_pipe_reg <= 1'b0;
is_i_type_ex_pipe_reg <= 1'b0;
is_s_type_ex_pipe_reg <= 1'b0;
is_b_type_ex_pipe_reg <= 1'b0;
is_u_type_ex_pipe_reg <= 1'b0;
is_j_type_ex_pipe_reg <= 1'b0;
pc_sel_ex_pipe_reg <= 2'b0;
op1sel_ex_pipe_reg <= 1'b0;
op2sel_ex_pipe_reg <= 2'b0;
wb_sel_ex_pipe_reg <= 2'b0;
pc4_sel_ex_pipe_reg <= 1'b0;
mem_wr_ex_pipe_reg <= 1'b0;
cpr_en_ex_pipe_reg <= 1'b0;
wa_sel_ex_pipe_reg <= 1'b0;
rf_en_ex_pipe_reg <= 1'b0;
alu_fun_ex_pipe_reg <= 6'b0;
next_seq_pc_ex_pipe_reg <= 31'b0;
curr_pc_ex_pipe_reg <= 31'b0;
next_brn_pc_ex_pipe_reg <= 31'b0;
next_pred_pc_ex_pipe_reg <= 31'b0;
sext_imm_ex_pipe_reg <= 31'b0;
r_data_p1_ex_pipe_reg <= 31'b0;
r_data_p2_ex_pipe_reg <= 31'b0;
jump_ex_pipe_reg <= 1'b0;
brn_pred_ex_pipe_reg <= 1'b0;
end
else
begin
valid_ex_pipe_reg <= valid_ex_pipe_reg_i;
funct3_ex_pipe_reg <= funct3_ex_pipe_reg_i;
op_ex_pipe_reg <= op_ex_pipe_reg_i;
rs1_ex_pipe_reg <= rs1_ex_pipe_reg_i;
rs2_ex_pipe_reg <= rs2_ex_pipe_reg_i;
rd_ex_pipe_reg <= rd_ex_pipe_reg_i;
is_r_type_ex_pipe_reg <= is_r_type_ex_pipe_reg_i;
is_i_type_ex_pipe_reg <= is_i_type_ex_pipe_reg_i;
is_s_type_ex_pipe_reg <= is_s_type_ex_pipe_reg_i;
is_b_type_ex_pipe_reg <= is_b_type_ex_pipe_reg_i;
is_u_type_ex_pipe_reg <= is_u_type_ex_pipe_reg_i;
is_j_type_ex_pipe_reg <= is_j_type_ex_pipe_reg_i;
pc_sel_ex_pipe_reg <= pc_sel_ex_pipe_reg_i;
op1sel_ex_pipe_reg <= op1sel_ex_pipe_reg_i;
op2sel_ex_pipe_reg <= op2sel_ex_pipe_reg_i;
wb_sel_ex_pipe_reg <= wb_sel_ex_pipe_reg_i;
pc4_sel_ex_pipe_reg <= pc4_sel_ex_pipe_reg_i;
mem_wr_ex_pipe_reg <= mem_wr_ex_pipe_reg_i;
cpr_en_ex_pipe_reg <= cpr_en_ex_pipe_reg_i;
wa_sel_ex_pipe_reg <= wa_sel_ex_pipe_reg_i;
rf_en_ex_pipe_reg <= rf_en_ex_pipe_reg_i;
alu_fun_ex_pipe_reg <= alu_fun_ex_pipe_reg_i;
next_seq_pc_ex_pipe_reg <= next_seq_pc_ex_pipe_reg_i;
curr_pc_ex_pipe_reg <= curr_pc_ex_pipe_reg_i;
next_brn_pc_ex_pipe_reg <= next_brn_pc_ex_pipe_reg_i;
next_pred_pc_ex_pipe_reg <= next_pred_pc_ex_pipe_reg_i;
sext_imm_ex_pipe_reg <= sext_imm_ex_pipe_reg_i;
r_data_p1_ex_pipe_reg <= r_data_p1_ex_pipe_reg_i;
r_data_p2_ex_pipe_reg <= r_data_p2_ex_pipe_reg_i;
jump_ex_pipe_reg <= jump_ex_pipe_reg_i;
brn_pred_ex_pipe_reg <= brn_pred_ex_pipe_reg_i;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:19:01 03/29/2015
// Design Name: regfileparam
// Module Name: C:/Users/Joseph/Documents/Xilinx/HW2/regfileparam_test.v
// Project Name: HW2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: regfileparam
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module regfileparam_test;
// Inputs
reg [3:0] ra;
reg [3:0] rb;
reg [3:0] rw;
reg [15:0] wdat;
reg wren;
reg clk;
reg rst;
// Outputs
wire [15:0] adat, adat2;
wire [15:0] bdat, bdat2;
wire [15:0] acompare;
wire [15:0] bcompare;
assign acompare = adat ^ adat2;
assign bcompare = bdat ^ bdat2;
// Instantiate the Unit Under Test (UUT)
regfileparam #(.BITSIZE(16), .ADDSIZE(4)) uut (
.adat(adat),
.bdat(bdat),
.ra(ra),
.rb(rb),
.rw(rw),
.wdat(wdat),
.wren(wren),
.clk(clk),
.rst(rst)
);
// Instantiate the Unit Under Test (UUT)
regfileparam_behav #(.BITSIZE(16), .ADDSIZE(4)) uut2 (
.adat(adat2),
.bdat(bdat2),
.ra(ra),
.rb(rb),
.rw(rw),
.wdat(wdat),
.wren(wren),
.clk(clk),
.rst(rst)
);
integer i;
always begin
clk = 1;
#10;
clk = 0;
#10;
end
initial begin
// Initialize Inputs
$display($time,,,"Simulation is started.");
ra = 0;
rb = 0;
rw = 0;
wdat = 0;
wren = 0;
rst = 0;
#10 rst = 1;
$display($time,,,"Reset is Asserted");
#15;
// First read from each location.
for(i=0; i<16; i=i+1) begin
ra = i; rb = i; wren = 0;
#20; // Progress time.
$display($time,,,"Port A: Read Address = %d, Read Value = %d \n\t Port B: Read Address = %d, Read Value = %d \n\t Compare Port A: %b, Compare Port B: %b", ra, adat, rb, bdat, acompare, bcompare);
end
$display($time,,,"Now we will write to each register location some random data.");
#20;
// Write to each location.
for(i=0; i<16; i=i+1) begin
rw = i; wren = 1; wdat = $random;
#20; // Progress time.
$display($time,,,"Write Address = %d, Written Value = %d", rw, wdat);
end
$display($time,,,"Now we will read from each register location the data that we have written from each port.");
#20;
// Now Read Again From Each Location.
for(i=0; i<16; i=i+1) begin
ra = i; rb = i; wren = 0;
#20; // Progress time.
$display($time,,,"Port A: Read Address = %d, Read Value = %d \n\t Port B: Read Address = %d, Read Value = %d \n\t Compare Port A: %b, Compare Port B: %b", ra, adat, rb, bdat, acompare, bcompare);
end
$display($time,,,"End of Simulation.");
#20;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_MUX_4TO2_TB_V
`define SKY130_FD_SC_HS__UDP_MUX_4TO2_TB_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_mux_4to2.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 A0 = 1'b1;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 S0 = 1'b1;
#240 S1 = 1'b1;
#260 A0 = 1'b0;
#280 A1 = 1'b0;
#300 A2 = 1'b0;
#320 A3 = 1'b0;
#340 S0 = 1'b0;
#360 S1 = 1'b0;
#380 S1 = 1'b1;
#400 S0 = 1'b1;
#420 A3 = 1'b1;
#440 A2 = 1'b1;
#460 A1 = 1'b1;
#480 A0 = 1'b1;
#500 S1 = 1'bx;
#520 S0 = 1'bx;
#540 A3 = 1'bx;
#560 A2 = 1'bx;
#580 A1 = 1'bx;
#600 A0 = 1'bx;
end
sky130_fd_sc_hs__udp_mux_4to2 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_MUX_4TO2_TB_V
|
//======================================================================
//
// blake2_G.v
// -----------
// Verilog 2001 implementation of the G function in the
// blake2 hash function core. This is pure combinational logic in a
// separade module to allow us to build versions with 1, 2, 4
// and even 8 parallel compression functions.
//
//
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blake2_G(
input wire [63 : 0] a,
input wire [63 : 0] b,
input wire [63 : 0] c,
input wire [63 : 0] d,
input wire [63 : 0] m0,
input wire [63 : 0] m1,
output wire [63 : 0] a_prim,
output wire [63 : 0] b_prim,
output wire [63 : 0] c_prim,
output wire [63 : 0] d_prim
);
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [63 : 0] internal_a_prim;
reg [63 : 0] internal_b_prim;
reg [63 : 0] internal_c_prim;
reg [63 : 0] internal_d_prim;
//----------------------------------------------------------------
// Concurrent connectivity for ports.
//----------------------------------------------------------------
assign a_prim = internal_a_prim;
assign b_prim = internal_b_prim;
assign c_prim = internal_c_prim;
assign d_prim = internal_d_prim;
//----------------------------------------------------------------
// G
//
// The actual G function.
//----------------------------------------------------------------
always @*
begin : G
reg [63 : 0] a0;
reg [63 : 0] a1;
reg [63 : 0] b0;
reg [63 : 0] b1;
reg [63 : 0] b2;
reg [63 : 0] b3;
reg [63 : 0] c0;
reg [63 : 0] c1;
reg [63 : 0] d0;
reg [63 : 0] d1;
reg [63 : 0] d2;
reg [63 : 0] d3;
a0 = a + b + m0;
d0 = d ^ a0;
d1 = {d0[31 : 0], d0[63 : 32]};
c0 = c + d1;
b0 = b ^ c0;
b1 = {b0[23 : 0], b0[63 : 24]};
a1 = a0 + b1 + m1;
d2 = d1 ^ a1;
d3 = {d2[15 : 0], d2[63 : 16]};
c1 = c0 + d3;
b2 = b1 ^ c1;
b3 = {b2[62 : 0], b2[63]};
internal_a_prim = a1;
internal_b_prim = b3;
internal_c_prim = c1;
internal_d_prim = d3;
end // G
endmodule // blake2_G
//======================================================================
// EOF blake2_G.v
//======================================================================
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:54:28 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_zybo_hdmi_0_0/system_zybo_hdmi_0_0_stub.v
// Design : system_zybo_hdmi_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "zybo_hdmi,Vivado 2016.4" *)
module system_zybo_hdmi_0_0(clk_125, clk_25, hsync, vsync, active, rgb, tmds,
tmdsb, hdmi_cec, hdmi_hpd, hdmi_out_en)
/* synthesis syn_black_box black_box_pad_pin="clk_125,clk_25,hsync,vsync,active,rgb[23:0],tmds[3:0],tmdsb[3:0],hdmi_cec,hdmi_hpd,hdmi_out_en" */;
input clk_125;
input clk_25;
input hsync;
input vsync;
input active;
input [23:0]rgb;
output [3:0]tmds;
output [3:0]tmdsb;
input hdmi_cec;
input hdmi_hpd;
output hdmi_out_en;
endmodule
|
// -----------------------------------------------------------------------
//
// Copyright 2004,2007,2008 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
`timescale 1ns/10ps
`include "asm.v"
`include "perfcounters.v"
module stage_X(input wire clock
,input wire restart // for synci
,input wire [31:0] restart_pc // for synci
,input wire d_valid
,input wire [31:0] d_instr
,input wire [31:0] d_pc
,input wire [31:0] d_npc
,input wire [ 5:0] d_opcode
,input wire [ 5:0] d_fn
,input wire [ 4:0] d_rd
,input wire [ 5:0] d_rs
,input wire [ 5:0] d_rt
,input wire [ 4:0] d_sa
,input wire [31:0] d_target
,input wire [ 5:0] d_wbr
,input wire d_has_delay_slot
,input wire [31:0] d_op1_val
,input wire [31:0] d_op2_val
,input wire [31:0] d_rt_val
,input wire [31:0] d_simm
,input wire d_restart
,input wire [31:0] d_restart_pc
,input wire d_load_use_hazard
,input wire m_valid
,input wire [ 5:0] m_wbr
,output reg x_valid = 0
,output reg [31:0] x_instr = 0 // XXX for debugging only
,output reg x_is_delay_slot = 0
,output reg [31:0] x_pc = 0
,output reg [ 5:0] x_opcode = 0
,output reg [31:0] x_op1_val = 0 // XXX
,output reg [ 5:0] x_rt = 0
,output reg [31:0] x_rt_val = 0 // for stores only
,output reg [ 5:0] x_wbr = 0
,output reg [31:0] x_res
,output reg x_synci = 0
,output reg [31:0] x_synci_a = 0
,output reg x_restart = 0
,output reg [31:0] x_restart_pc = 0
,output reg x_flush_D = 0
,output reg [31:0] perf_branch_hazard = 0
,input wire [31:0] perf_dcache_misses
,input wire [31:0] perf_delay_slot_bubble
,output reg [31:0] perf_div_hazard = 0
,input wire [31:0] perf_icache_misses
,input wire [31:0] perf_io_load_busy
,input wire [31:0] perf_io_store_busy
,input wire [31:0] perf_load_hit_store_hazard
,output reg [31:0] perf_load_use_hazard = 0
,output reg [31:0] perf_mult_hazard = 0
,input wire [47:0] perf_retired_inst
,input wire [31:0] perf_sb_full
);
parameter FREQ = 0;
parameter debug = 0;
`include "config.h"
reg [31:0] x_op2_val = 0;
reg [ 5:0] x_fn = 0;
reg [ 4:0] x_sa = 0;
wire [31:0] perf_frequency = FREQ / 1000; // Given in Hz, reported in kHz
wire d_ops_eq = d_op1_val == d_op2_val;
reg x_negate_op2 = 0;
always @(posedge clock)
x_negate_op2 <= d_opcode == `SLTI ||
d_opcode == `SLTIU ||
d_opcode == `REG && (d_fn == `SLT ||
d_fn == `SLTU ||
d_fn == `SUB ||
d_fn == `SUBU);
wire [31:0] x_sum;
wire x_carry_flag;
wire [31:0] x_op2_neg = {32{x_negate_op2}} ^ x_op2_val;
assign {x_carry_flag,x_sum} = x_op1_val + x_op2_neg + x_negate_op2;
wire x_sign_flag = x_sum[31];
wire x_overflow_flag = x_op1_val[31] == x_op2_neg[31] &&
x_op1_val[31] != x_sum[31];
wire [4:0] x_shift_dist = x_fn[2] ? x_op1_val[4:0] : x_sa;
// XXX BUG These architectural registers must live in ME or later
// as ME can flush the pipe rendering an update of state in EX
// premature. Of course this leads to headaches with forwarding and
// hazards on instruction depending on these... Sigh.
reg mult_busy = 0;
reg [63:0] mult_a = 0;
`ifdef MULT_RADIX_4
reg [63:0] mult_3a = 0;
`endif
reg [31:0] mult_b = 0;
reg mult_neg = 0;
reg [31:0] mult_lo = 0;
reg [31:0] mult_hi = 0;
reg div_busy = 0, div_neg_res, div_neg_rem;
reg [31:0] divisor = 0, div_hi = 0, div_lo = 0;
wire [64:0] div_shifted = {div_hi, div_lo, 1'd0};
wire [32:0] div_diff = div_shifted[64:32] - divisor;
reg [ 6:0] div_n = 0;
`ifdef LATER
reg [31:0] cp0_status = 0, // XXX -- " --
cp0_epc = 0,
cp0_errorepc = 0,
cp0_cause = 0;
`endif
reg x_has_delay_slot = 0;
reg [35:0] tsc = 0; // Free running counter
reg branch_event = 0;
reg [31:0] x_special = 0; // A value that can be precomputed
always @(posedge clock)
case (d_opcode)
`REG: x_special <= d_npc + 4;
`REGIMM: x_special <= d_npc + 4;
`JAL: x_special <= d_npc + 4;
`RDHWR:
case (d_rd)
0: x_special <= 0; // # of processors-1
1: x_special <= 4 << IC_WORD_INDEX_BITS;
2: x_special <= tsc[35:4]; // @40 MHz 28 min before rollover
3: x_special <= 1 << 4; // TSC scaling factor
4: x_special <= tsc[31:0]; // Unscaled, but truncated TSC (local hack)
endcase
`LUI: x_special <= {d_simm[15: 0], 16'd0};
`CP2:
case (d_rd)
`PERF_BRANCH_HAZARD: x_special <= perf_branch_hazard;
`PERF_DCACHE_MISSES: x_special <= perf_dcache_misses;
`PERF_DELAY_SLOT_BUBBLE: x_special <= perf_delay_slot_bubble;
`PERF_DIV_HAZARD: x_special <= perf_div_hazard;
`PERF_FREQUENCY: x_special <= perf_frequency;
`PERF_ICACHE_MISSES: x_special <= perf_icache_misses;
`PERF_IO_LOAD_BUSY: x_special <= perf_io_load_busy;
`PERF_IO_STORE_BUSY: x_special <= perf_io_store_busy;
`PERF_LOAD_HIT_STORE_HAZARD: x_special <= perf_load_hit_store_hazard;
`PERF_LOAD_USE_HAZARD: x_special <= perf_load_use_hazard;
`PERF_MULT_HAZARD: x_special <= perf_mult_hazard;
// Count 16 retired instructions. @40 MHz 1 CPI, it takes 28 min to roll over
`PERF_RETIRED_INST: x_special <= perf_retired_inst[35:4];
`PERF_SB_FULL: x_special <= perf_sb_full;
endcase
endcase
/*
* The ALU
*/
always @* begin
x_res = 32'hXXXXXXXX;
case (x_opcode)
`REG:
case (x_fn)
`SLL : x_res = x_op2_val << x_shift_dist;
`SRL : x_res = x_op2_val >> x_shift_dist;
`SRA : x_res = $signed(x_op2_val) >>> x_shift_dist;
`SLLV: x_res = x_op2_val << x_shift_dist;
`SRLV: x_res = x_op2_val >> x_shift_dist;
`SRAV: x_res = $signed(x_op2_val) >>> x_shift_dist;
`JALR: x_res = x_special;
// XXX BUG See the comment above with mult_lo and mult_hi
`MFHI: x_res = mult_hi;
`MFLO: x_res = mult_lo;
// XXX BUG Trap on overflow for ADD, ADDI and SUB
`ADD: x_res = x_sum;
`ADDU: x_res = x_sum;
`SUB: x_res = x_sum;
`SUBU: x_res = x_sum;
`AND: x_res = x_op1_val & x_op2_val;
`OR: x_res = x_op1_val | x_op2_val;
`XOR: x_res = x_op1_val ^ x_op2_val;
`NOR: x_res = ~(x_op1_val | x_op2_val);
`SLT: x_res = {{31{1'b0}}, x_sign_flag ^ x_overflow_flag};
`SLTU: x_res = {{31{1'b0}}, ~x_carry_flag};
default: x_res = 32'hXXXXXXXX;
endcase
`REGIMM: x_res = x_special;// BLTZ, BGEZ, BLTZAL, BGEZAL
`JAL: x_res = x_special;
`ADDI: x_res = x_sum;
`ADDIU: x_res = x_sum;
`SLTI: x_res = {{31{1'b0}}, x_sign_flag ^ x_overflow_flag};
`SLTIU: x_res = {{31{1'b0}}, ~x_carry_flag};
`ANDI: x_res = {16'b0, x_op1_val[15:0] & x_op2_val[15:0]};
`ORI: x_res = {x_op1_val[31:16], x_op1_val[15:0] | x_op2_val[15:0]};
`XORI: x_res = {x_op1_val[31:16], x_op1_val[15:0] ^ x_op2_val[15:0]};
`LUI: x_res = x_special;
//`CP1:
`RDHWR: x_res = x_special;
`CP2: x_res = x_special;
default: x_res = 32'hXXXXXXXX;
endcase
end
always @(posedge clock) begin
tsc <= tsc + 1;
x_valid <= d_valid;
x_instr <= d_instr;
x_pc <= d_pc;
x_opcode <= d_opcode;
x_fn <= d_fn;
x_sa <= d_sa;
x_op1_val <= d_op1_val;
x_op2_val <= d_op2_val;
x_rt <= d_rt;
x_rt_val <= d_rt_val;
x_wbr <= d_wbr;
x_has_delay_slot <= d_has_delay_slot & d_valid;
x_is_delay_slot <= x_has_delay_slot & x_valid;
x_restart <= 0;
x_restart_pc <= d_target;
x_flush_D <= 0;
x_synci <= 0;
/* Stat counts aren't critical, so I delay them to keep them out
of the critical path */
if (branch_event)
perf_branch_hazard <= perf_branch_hazard + 1;
branch_event <= 0;
//`define MULT_RADIX_4 1
`ifdef MULT_RADIX_4
// Radix-2 Multiplication Machine (this is not the best way to do this)
if (mult_busy) begin
$display("MULT[U] %x * %x + %x", mult_a, mult_b, {mult_hi,mult_lo});
case (mult_b[1:0])
1: {mult_hi,mult_lo} <= {mult_hi,mult_lo} + mult_a;
2: {mult_hi,mult_lo} <= {mult_hi,mult_lo} + (mult_a << 1);
3: {mult_hi,mult_lo} <= {mult_hi,mult_lo} + mult_3a;
endcase
mult_a <= mult_a << 2;
mult_3a <= mult_3a << 2;
mult_b <= mult_b >> 2;
if (mult_b == 0) begin
if (mult_neg) begin
{mult_hi,mult_lo} <= 64'd0 - {mult_hi,mult_lo};
mult_neg <= 0;
end else
mult_busy <= 0;
$display("MULT[U] = %x", mult_a + {mult_hi,mult_lo});
end
end
`else
// Radix-2 Multiplication Machine (this is not the best way to do this)
if (mult_busy) begin
$display("MULT[U] %x * %x + %x", mult_a, mult_b, {mult_hi,mult_lo});
if (mult_b[0])
{mult_hi,mult_lo} <= {mult_hi,mult_lo} + mult_a;
mult_a <= mult_a << 1;
mult_b <= mult_b >> 1;
if (mult_b == 0) begin
if (mult_neg) begin
{mult_hi,mult_lo} <= 64'd0 - {mult_hi,mult_lo};
mult_neg <= 0;
end else
mult_busy <= 0;
$display("MULT[U] = %x", mult_a + {mult_hi,mult_lo});
end
end
`endif
/*
* Division uses a simple algorithm:
* for 1 .. 32:
* divident = divident << 1
* if (divident >= (divisor << 32)):
* divident = divident - (divisor << 32) + 1
* result = divisor & 0xFFFF_FFFF
*/
if (!div_n[6]) begin
{div_hi,div_lo} <= div_shifted[63:0];
if (!div_diff[32]) begin
div_hi <= div_diff[31:0];
div_lo[0] <= 1'd1;
end
div_n <= div_n - 1'd1;
end else if (div_busy) begin
div_busy <= 0;
mult_lo <= div_neg_res ? -div_lo : div_lo; // result
mult_hi <= div_neg_rem ? -div_hi : div_hi; // remainder
$display("DIV = hi %d lo %d",
div_neg_rem ? -div_hi : div_hi,
div_neg_res ? -div_lo : div_lo);
end
case (d_opcode)
`REG:
case (d_fn)
`JALR:
if (d_valid) begin
$display("JAL: d_npc = %x", d_npc);
x_restart <= 1;
x_restart_pc <= d_op1_val;
branch_event <= 1;
end
`JR:
if (d_valid) begin
x_restart <= 1;
x_restart_pc <= d_op1_val;
branch_event <= 1;
end
// XXX BUG See the comment above with mult_lo and mult_hi
`MFHI:
if ((mult_busy | div_busy) && d_valid) begin
x_flush_D <= 1;
x_valid <= 0;
x_restart_pc <= d_pc - {x_has_delay_slot,2'd0};
x_restart <= 1;
if (mult_busy)
perf_mult_hazard <= perf_mult_hazard + 1;
else
perf_div_hazard <= perf_div_hazard + 1;
end
`MFLO:
if ((mult_busy | div_busy) && d_valid) begin
x_flush_D <= 1;
x_valid <= 0;
x_restart_pc <= d_pc - {x_has_delay_slot,2'd0};
x_restart <= 1;
if (mult_busy)
perf_mult_hazard <= perf_mult_hazard + 1;
else
perf_div_hazard <= perf_div_hazard + 1;
end
`MTHI:
if (d_valid) begin
if (mult_busy | div_busy) begin
x_flush_D <= 1;
x_valid <= 0;
x_restart_pc <= d_pc - {x_has_delay_slot,2'd0};
x_restart <= 1;
if (mult_busy)
perf_mult_hazard <= perf_mult_hazard + 1;
else
perf_div_hazard <= perf_div_hazard + 1;
end else
mult_hi <= d_op1_val;
end
`MTLO:
if (d_valid) begin
if (mult_busy | div_busy) begin
x_flush_D <= 1;
x_valid <= 0;
x_restart_pc <= d_pc - {x_has_delay_slot,2'd0};
x_restart <= 1;
if (mult_busy)
perf_mult_hazard <= perf_mult_hazard + 1;
else
perf_div_hazard <= perf_div_hazard + 1;
end else
mult_lo <= d_op1_val;
end
`DIV:
if (d_valid)
if (mult_busy | div_busy) begin
x_flush_D <= 1;
x_valid <= 0;
x_restart_pc <= d_pc - {x_has_delay_slot,2'd0};
x_restart <= 1;
if (mult_busy)
perf_mult_hazard <= perf_mult_hazard + 1;
else
perf_div_hazard <= perf_div_hazard + 1;
end else begin
div_busy <= 1;
div_hi <= 0;
div_lo <= d_op1_val[31] ? -d_op1_val : d_op1_val;
divisor <= d_op2_val[31] ? -d_op2_val : d_op2_val;
div_neg_res <= d_op1_val[31] ^ d_op2_val[31];
// res = a/b, rem = a - b*(a/b)
// thus the rem sign follows a only
div_neg_rem <= d_op1_val[31];
div_n <= 31;
$display("%05dc EX: %d / %d", $time, d_op1_val, d_op2_val);
end
`DIVU:
if (d_valid)
if (mult_busy | div_busy) begin
x_flush_D <= 1;
x_valid <= 0;
x_restart_pc <= d_pc - {x_has_delay_slot,2'd0};
x_restart <= 1;
if (mult_busy)
perf_mult_hazard <= perf_mult_hazard + 1;
else
perf_div_hazard <= perf_div_hazard + 1;
end else begin
div_busy <= 1;
div_hi <= 0;
div_lo <= d_op1_val;
divisor <= d_op2_val;
div_neg_res <= 0;
div_neg_rem <= 0;
div_n <= 31;
$display("%05dc EX: %d /U %d", $time, d_op1_val, d_op2_val);
end
`MULTU:
if (d_valid)
if (mult_busy | div_busy) begin
x_flush_D <= 1;
x_valid <= 0;
x_restart_pc <= d_pc - {x_has_delay_slot,2'd0};
x_restart <= 1;
if (mult_busy)
perf_mult_hazard <= perf_mult_hazard + 1;
else
perf_div_hazard <= perf_div_hazard + 1;
end else begin
$display("MULTU %x * %x", d_op1_val, d_op2_val);
mult_busy <= 1;
mult_hi <= 0;
mult_lo <= 0;
mult_a <= d_op1_val;
mult_b <= d_op2_val;
`ifdef MULT_RADIX_4
mult_3a <= 3 * d_op1_val;
`endif
mult_neg <= 0;
$display("%05dc EX: %dU * %dU", $time, d_op1_val, d_op2_val);
end
`MULT:
if (d_valid)
if (mult_busy | div_busy) begin
x_flush_D <= 1;
x_valid <= 0;
x_restart_pc <= d_pc - {x_has_delay_slot,2'd0};
x_restart <= 1;
if (mult_busy)
perf_mult_hazard <= perf_mult_hazard + 1;
else
perf_div_hazard <= perf_div_hazard + 1;
end else begin
$display("MULT %x * %x", d_op1_val, d_op2_val);
mult_busy <= 1;
mult_hi <= 0;
mult_lo <= 0;
mult_neg <= d_op1_val[31] ^ d_op2_val[31];
mult_a <= d_op1_val[31] ? {32'd0,32'd0 - d_op1_val} : d_op1_val;
`ifdef MULT_RADIX_4
mult_3a <= d_op1_val[31] ? 3 * {32'd0,32'd0-d_op1_val} : 3 * d_op1_val;
`endif
mult_b <= d_op2_val[31] ? 32'd0 - d_op2_val : d_op2_val;
$display("%05dc EX: %d * %d", $time, d_op1_val, d_op2_val);
end
`BREAK:
if (d_valid) begin
x_restart <= 1;
x_restart_pc <= 'hBFC00380;
x_flush_D <= 1;
`ifdef LATER
cp0_status[`CP0_STATUS_EXL] <= 1;
//cp0_cause.exc_code = EXC_BP;
cp0_cause <= 9 << 2;
// cp0_cause.bd = branch_delay_slot; // XXX DELAY SLOT HANDLING!
cp0_epc <= d_pc; // XXX DELAY SLOT HANDLING!
`endif
end
endcase
`REGIMM: // BLTZ, BGEZ, BLTZAL, BGEZAL
if (d_valid)
if (d_rt[4:0] == `SYNCI) begin
x_restart <= 1;
x_restart_pc <= x_restart ? restart_pc : d_npc;
x_flush_D <= 1;
$display("synci restart at %x (d_restart = %d, d_restart_pc = %x, d_npc = %x)",
d_restart ? d_restart_pc : d_npc,
d_restart, d_restart_pc, d_npc);
x_synci <= 1;
x_synci_a <= d_op1_val + d_simm;
end else begin
x_restart <= d_rt[0] ^ d_op1_val[31];
branch_event <= 1;
end
`JAL:
if (d_valid) begin
x_restart <= 1;
branch_event <= 1;
end
`J: if (d_valid) x_restart <= 1;
`BEQ:
if (d_valid) begin
x_restart <= d_ops_eq;
branch_event <= d_ops_eq;
$display("%05d BEQ %8x == %8x (%1d)", $time,
d_op1_val, d_op2_val, d_ops_eq);
end
`BNE:
if (d_valid) begin
x_restart <= ~d_ops_eq;
branch_event <= ~d_ops_eq;
$display("%05d BNE %8x != %8x (%1d) target %8x", $time,
d_op1_val, d_op2_val, !d_ops_eq, d_target);
end
`BLEZ:
if (d_valid) begin
x_restart <= d_op1_val[31] || d_op1_val == 0;
branch_event <= (d_op1_val[31] || d_op1_val == 0);
end
`BGTZ:
// XXX Share logic
if (d_valid) begin
x_restart <= !d_op1_val[31] && d_op1_val != 0;
branch_event <= (!d_op1_val[31] && d_op1_val != 0);
end
`CP2: begin
`ifdef SIMULATE_MAIN
if (d_valid && !d_rs[4] && 0) begin
if (mult_lo == 32'h87654321)
$display("TEST SUCCEEDED!");
else
$display("%05d TEST FAILED WITH %x (%1d:%8x:%8x)", $time, mult_lo,
d_valid, d_pc, d_instr);
$finish; // XXX do something more interesting for real hw.
end else
`endif
if (~d_rs[4])
if (d_rs[2])
$display("MTCP2 r%d <- %x (ignored)", d_rd, d_op2_val);
else
$display("MFCP2 r%d", d_rd);
end
/*
* XXX Comment out the CP0 handling for now. I want to handle
* that in a way that doesn't affect the performance of the
* regular instructions
*/
`ifdef LATER
`CP0: if (d_valid) begin
/* Two possible formats */
if (d_rs[4]) begin
if (d_fn == `C0_ERET) begin
/* Exception Return */
x_restart <= 1;
x_flush_D <= 1; // XXX BUG? Check that ERET doesn't have a delay slot!
if (cp0_status[`CP0_STATUS_ERL]) begin
x_restart_pc <= cp0_errorepc;
cp0_status[`CP0_STATUS_ERL] <= 0;
`ifdef SIMULATE_MAIN
$display("ERET ERROREPC %x", cp0_errorepc);
`endif
end else begin
x_restart_pc <= cp0_epc;
cp0_status[`CP0_STATUS_EXL] <= 0;
`ifdef SIMULATE_MAIN
$display("ERET EPC %x", cp0_epc);
`endif
end
end
`ifdef SIMULATE_MAIN
else
/* C1 format */
$display("Unhandled CP0 command %s\n",
d_fn == `C0_TLBR ? "tlbr" :
d_fn == `C0_TLBWI ? "tlbwi" :
d_fn == `C0_TLBWR ? "tlbwr" :
d_fn == `C0_TLBP ? "tlbp" :
d_fn == `C0_ERET ? "eret" :
d_fn == `C0_DERET ? "deret" :
d_fn == `C0_WAIT ? "wait" :
"???");
`endif
end else begin
`ifdef SIMULATE_MAIN
if (d_rs[2])
$display("MTCP0 r%d <- %x", d_rd, d_op2_val);
else
$display("MFCP0 r%d", d_rd);
if (d_fn != 0) $display("d_fn == %x", d_fn);
`endif
if (d_rs[2]) begin
x_wbr <= 0; // XXX BUG?
// cp0regs[i.r.rd] = t;
case (d_rd)
`CP0_STATUS:
begin
cp0_status <= d_op2_val;
$display("STATUS <= %x", d_op2_val);
end
`CP0_CAUSE:
begin
cp0_cause <= d_op2_val;
$display("CAUSE <= %x", d_op2_val);
end
`CP0_EPC:
begin
cp0_epc <= d_op2_val;
$display("EPC <= %x", d_op2_val);
end
`CP0_ERROREPC:
begin
cp0_errorepc <= d_op2_val;
$display("ERROREPC <= %x", d_op2_val);
end
/*
cp0_status.raw = t;
cp0_status.res1 = cp0_status.res2 = 0;
printf("Operating mode %s\n",
cp0_status.ksu == 0 ? "kernel" :
cp0_status.ksu == 1 ? "supervisor" :
cp0_status.ksu == 2 ? "user" : "??");
printf("Exception level %d\n", cp0_status.exl);
printf("Error level %d\n", cp0_status.erl);
printf("Interrupts %sabled\n", cp0_status.ie ? "en" : "dis");
break;
*/
default:
$display("Setting an unknown CP0 register %d", d_rd);
//case CP0_CAUSE:
endcase
end
end
end
`endif
endcase
if (d_load_use_hazard)
perf_load_use_hazard <= perf_load_use_hazard + 1;
end
endmodule
|
/****************************************
Branch
for MIST32 Processor
Takahiro Ito @cpu_labs
****************************************/
`include "core.h"
`default_nettype none
module execute_branch(
input wire [31:0] iDATA_0,
input wire [31:0] iDATA_1,
input wire [31:0] iPC,
input wire [4:0] iFLAG,
input wire [3:0] iCC,
input wire [4:0] iCMD,
output wire [31:0] oBRANCH_ADDR,
output wire oJUMP_VALID,
output wire oNOT_JUMP_VALID,
output wire oIB_VALID,
output wire oIDTS_VALID,
output wire oHALT_VALID
);
assign oBRANCH_ADDR = func_branch_addr(
iCMD,
iPC,
iDATA_1
);
function [31:0] func_branch_addr;
input [4:0] func_cmd;
input [31:0] func_pc;
input [31:0] func_source1;
begin
case(func_cmd)
`EXE_BRANCH_BUR:
begin
func_branch_addr = func_source1 + func_pc;
end
`EXE_BRANCH_BR:
begin
func_branch_addr = func_source1 + func_pc;
end
`EXE_BRANCH_B:
begin
func_branch_addr = func_source1;
end
`EXE_BRANCH_INTB:
begin
func_branch_addr = 32'h0;
end
`EXE_BRANCH_IDTS:
begin
func_branch_addr = func_pc + 32'h0000004;
end
default:
begin
func_branch_addr = 32'h0;
end
endcase
end
endfunction
assign oJUMP_VALID = (iCMD != `EXE_BRANCH_INTB && iCMD != `EXE_BRANCH_IDTS)? func_ex_branch_check(iCC, iFLAG) : 1'b0;
assign oNOT_JUMP_VALID = (iCMD != `EXE_BRANCH_INTB && iCMD != `EXE_BRANCH_IDTS)? !func_ex_branch_check(iCC, iFLAG) : 1'b0;
assign oIB_VALID = (iCMD == `EXE_BRANCH_INTB)? 1'b1 : 1'b0;
assign oIDTS_VALID = (iCMD == `EXE_BRANCH_IDTS)? 1'b1 : 1'b0;
assign oHALT_VALID = (iCMD == `EXE_BRANCH_HALT)? 1'b1 : 1'b0;
function func_ex_branch_check;
input [3:0] func_ex_branch_check_cc;
input [4:0] func_ex_branch_check_flag;
begin
case(func_ex_branch_check_cc)
`CC_AL : func_ex_branch_check = 1'b1;
`CC_EQ :
begin
if(func_ex_branch_check_flag[`FLAGS_ZF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_NEQ :
begin
if(!func_ex_branch_check_flag[`FLAGS_ZF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_MI :
begin
func_ex_branch_check = func_ex_branch_check_flag[`FLAGS_SF];
end
`CC_PL :
begin
func_ex_branch_check = !func_ex_branch_check_flag[`FLAGS_SF];
end
`CC_EN :
begin
if(!func_ex_branch_check_flag[`FLAGS_PF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_ON :
begin
if(func_ex_branch_check_flag[`FLAGS_PF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_OVF :
begin
if(func_ex_branch_check_flag[`FLAGS_OF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_UEO :
begin
func_ex_branch_check = func_ex_branch_check_flag[`FLAGS_CF];
end
`CC_UU :
begin
func_ex_branch_check = !func_ex_branch_check_flag[`FLAGS_CF];
end
`CC_UO :
begin
func_ex_branch_check = func_ex_branch_check_flag[`FLAGS_CF] && !func_ex_branch_check_flag[`FLAGS_ZF];
end
`CC_UEU :
begin
func_ex_branch_check = !func_ex_branch_check_flag[`FLAGS_CF] || func_ex_branch_check_flag[`FLAGS_ZF];
end
`CC_SEO :
begin
func_ex_branch_check = (func_ex_branch_check_flag[`FLAGS_SF] && func_ex_branch_check_flag[`FLAGS_OF]) || (!func_ex_branch_check_flag[`FLAGS_SF] && !func_ex_branch_check_flag[`FLAGS_OF]);
end
`CC_SU :
begin
func_ex_branch_check = (func_ex_branch_check_flag[`FLAGS_SF] && !func_ex_branch_check_flag[`FLAGS_OF]) || (!func_ex_branch_check_flag[`FLAGS_SF] && func_ex_branch_check_flag[`FLAGS_OF]);
end
`CC_SO :
begin
func_ex_branch_check = !((func_ex_branch_check_flag[`FLAGS_SF] ^ func_ex_branch_check_flag[`FLAGS_OF]) || func_ex_branch_check_flag[`FLAGS_ZF]);
end
`CC_SEU :
begin
func_ex_branch_check = (func_ex_branch_check_flag[`FLAGS_SF] ^ func_ex_branch_check_flag[`FLAGS_OF]) || func_ex_branch_check_flag[`FLAGS_ZF];
end
default : func_ex_branch_check = 1'b1;
endcase
end
endfunction
endmodule
`default_nettype wire
|
`include "Definition.v"
module ReadWrite#
(
parameter[ 3 : 0 ]ReadState = 0, // read raw data operation
parameter[ 3 : 0 ]ProcessState = 1, // color correction
parameter[ 3 : 0 ]WriteState = 2
)
(
input Clock,
input Reset,
input[ `size_char - 1 : 0 ]R,
input[ `size_char - 1 : 0 ]G,
input[ `size_char - 1 : 0 ]B,
output reg[ `size_char - 1 : 0 ]R_out,
output reg[ `size_char - 1 : 0 ]G_out,
output reg[ `size_char - 1 : 0 ]B_out
);
reg[ `size_int - 1 : 0 ]ScaleR[ 0 : `SumPixel - 1 ];
reg[ `size_int - 1 : 0 ]ScaleG[ 0 : `SumPixel - 1 ];
reg[ `size_int - 1 : 0 ]ScaleB[ 0 : `SumPixel - 1 ];
reg[ 3 : 0 ]StateNow;
reg[ 3 : 0 ]StateNext;
integer ReadIndex;
integer WriteIndex;
always@( posedge Clock )
begin
if( Reset == 1'b1 )
begin
ReadIndex = 0;
WriteIndex = 0;
StateNext = ReadState;
end
end
always@( StateNext )
StateNow = StateNext;
always@( posedge Clock )
begin
if( StateNow == ReadState )
begin
////////////////
// read raw data
ScaleR[ ReadIndex ] = R << `ScaleBit;
ScaleG[ ReadIndex ] = G << `ScaleBit;
ScaleB[ ReadIndex ] = B << `ScaleBit;
ReadIndex = ReadIndex + 1;
if( ReadIndex == `SumPixel )
StateNext = ProcessState;
end
else if( StateNow == WriteState )
begin
if( WriteIndex < `SumPixel )
begin
R_out = ScaleR[ WriteIndex ] >> `ScaleBit;
G_out = ScaleG[ WriteIndex ] >> `ScaleBit;
B_out = ScaleB[ WriteIndex ] >> `ScaleBit;
WriteIndex = WriteIndex + 1;
end
end
end
always@( StateNow )
begin
case( StateNow )
ProcessState:
begin
//
// work here
//
StateNext = WriteState;
end
endcase
end
endmodule
module ReadWrite_testbench;
// Signal declaration
reg Clock;
reg Reset;
reg[ `size_char - 1 : 0 ]R;
reg[ `size_char - 1 : 0 ]G;
reg[ `size_char - 1 : 0 ]B;
wire[ `size_char - 1 : 0 ]R_out;
wire[ `size_char - 1 : 0 ]G_out;
wire[ `size_char - 1 : 0 ]B_out;
reg[ `size_char - 1 : 0 ]RBlock[ 0 : `SumPixel - 1 ];
reg[ `size_char - 1 : 0 ]GBlock[ 0 : `SumPixel - 1 ];
reg[ `size_char - 1 : 0 ]BBlock[ 0 : `SumPixel - 1 ];
integer i;
integer RFile;
integer GFile;
integer BFile;
ReadWrite ReadWrite_test
(
Clock,
Reset,
R,
G,
B,
R_out,
G_out,
B_out
);
initial
begin
#2
begin
// open test data file
$readmemh( "data/IM000565_RAW_20x15R.dat", RBlock );
$readmemh( "data/IM000565_RAW_20x15G.dat", GBlock );
$readmemh( "data/IM000565_RAW_20x15B.dat", BBlock );
end
#2 Reset = 1'b1;
// Apply Stimulus
for( i = 0; i < `SumPixel; i = i + 1 )
begin
#2
begin
// initialization, start to read data into buffer
Reset = 1'b0;
R = RBlock[ i ];
G = GBlock[ i ];
B = BBlock[ i ];
end
end
#2
begin
RFile = $fopen( "data/R.dat" );
GFile = $fopen( "data/G.dat" );
BFile = $fopen( "data/B.dat" );
end
for( i = 0; i < `SumPixel; i = i + 1 )
begin
#2
begin
// display information on the screen
//$display( "R = %d, G = %d, B = %d\t\tR = %d, G = %d, B = %d",
// RBlock[ i ], GBlock[ i ], BBlock[ i ], R_out, G_out, B_out );
if( i % 16 == 0 )
begin
$fwrite( RFile, "\n" );
$fwrite( GFile, "\n" );
$fwrite( BFile, "\n" );
end
$fwrite( RFile, "%X ", R_out );
$fwrite( GFile, "%X ", G_out );
$fwrite( BFile, "%X ", B_out );
end
end
$fclose( RFile );
$fclose( GFile );
$fclose( BFile );
#100000 $stop;
#100000 $finish;
end
initial Clock = 0;
always #1 Clock = ~Clock; //Toggle Clock
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_button_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 1: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 1: 0] d1_data_in;
reg [ 1: 0] d2_data_in;
wire [ 1: 0] data_in;
reg [ 1: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 1: 0] edge_detect;
wire irq;
reg [ 1: 0] irq_mask;
wire [ 1: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({2 {(address == 0)}} & data_in) |
({2 {(address == 2)}} & irq_mask) |
({2 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[1 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0])
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1])
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
|
module testbench();
`include "bsg_noc_links.vh"
import bsg_noc_pkg::*;
// Sync with trace gen
localparam hdr_width_p = 32;
localparam cord_width_p = 2;
localparam len_width_p = 3;
localparam flit_width_p = 8;
localparam pr_data_width_p = 16;
localparam wh_hdr_width_p = cord_width_p + len_width_p;
localparam pr_hdr_width_p = hdr_width_p - wh_hdr_width_p;
localparam hdr_flits_p = hdr_width_p / flit_width_p;
localparam data_width_p = flit_width_p*(2**len_width_p-hdr_flits_p+1);
localparam data_flits_p = data_width_p / flit_width_p;
localparam ring_width_p = 1+`BSG_MAX(`BSG_MAX(hdr_width_p, pr_data_width_p), flit_width_p);
localparam rom_data_width_p = 4 + ring_width_p;
localparam rom_addr_width_p = 32;
logic clk;
bsg_nonsynth_clock_gen #(
.cycle_time_p(1000)
) clock_gen (
.o(clk)
);
logic reset;
bsg_nonsynth_reset_gen #(
.num_clocks_p(1)
,.reset_cycles_lo_p(4)
,.reset_cycles_hi_p(4)
) reset_gen (
.clk_i(clk)
,.async_reset_o(reset)
);
`declare_bsg_ready_and_link_sif_s(flit_width_p, bsg_ready_and_link_sif_s);
bsg_ready_and_link_sif_s link_lo, link_li;
bsg_ready_and_link_sif_s out_link_lo, out_link_li;
`declare_bsg_ready_and_link_sif_s(flit_width_p/4, bsg_narrow_link_sif_s);
bsg_narrow_link_sif_s narrow_link_li, narrow_link_lo;
logic [3:0] backpressure_cnt;
always_ff @(posedge clk)
if (reset)
backpressure_cnt <= '0;
else
backpressure_cnt <= backpressure_cnt + 1'b1;
wire backpressure = backpressure_cnt[0];
bsg_parallel_in_serial_out_passthrough
#(.width_p(flit_width_p/4), .els_p(4))
pisop
(.clk_i(clk)
,.reset_i(reset)
,.data_i(link_li.data)
,.v_i(link_li.v)
,.ready_and_o(link_lo.ready_and_rev)
,.data_o(narrow_link_lo.data)
,.v_o(narrow_link_lo.v)
,.ready_and_i(narrow_link_li.ready_and_rev & ~backpressure)
);
bsg_serial_in_parallel_out_passthrough
#(.width_p(flit_width_p/4), .els_p(4))
sipop
(.clk_i(clk)
,.reset_i(reset)
,.data_i(narrow_link_lo.data)
,.v_i(narrow_link_lo.v & ~backpressure)
,.ready_and_o(narrow_link_li.ready_and_rev)
,.data_o(out_link_li.data)
,.v_o(out_link_li.v)
,.ready_and_i(out_link_lo.ready_and_rev)
);
// TODO: Actually set
assign out_link_lo.ready_and_rev = 1'b1;
logic [63:0] counter;
always_ff @(posedge clk)
if (reset)
counter <= '0;
else
counter <= counter + 1'b1;
wire select_top = (counter % 68 == 0);
wire select_bot = (counter % 87 == 0);
wire select_left = (counter % 44 == 0);
wire select_right = (counter % 73 == 0);
logic [flit_width_p-1:0] left_data_li;
logic left_yumi_lo;
wire left_v_li = select_left;
initial
begin
left_data_li = '0;
for (integer i = 70; i < 170; i+=0)
begin
left_data_li = i << (cord_width_p);
@(left_yumi_lo);
@(negedge clk);
i += 1'b1;
end
end
logic [flit_width_p-1:0] right_data_li;
logic right_yumi_lo;
wire right_v_li = select_right;
initial
begin
right_data_li = '0;
for (integer i = 10; i < 110; i+=0)
begin
right_data_li = i << (cord_width_p);
@(right_yumi_lo);
@(negedge clk);
i += 1'b1;
end
end
logic [flit_width_p-1:0] top_data_li;
logic top_yumi_lo;
wire top_v_li = select_top;
initial
begin
top_data_li = '0;
for (integer i = 25; i < 125; i+=0)
begin
top_data_li = i << (cord_width_p);
@(top_yumi_lo);
@(negedge clk);
i += 1'b1;
end
end
logic [flit_width_p-1:0] bot_data_li;
logic bot_yumi_lo;
wire bot_v_li = select_bot;
initial
begin
bot_data_li = '0;
for (integer i = 50; i < 150; i+=0)
begin
bot_data_li = i << (cord_width_p);
@(bot_yumi_lo);
@(negedge clk);
i += 1'b1;
end
end
bsg_ready_and_link_sif_s [S:P] router_link_li, router_link_lo;
bsg_mesh_router_buffered
#(.width_p(flit_width_p)
,.x_cord_width_p(1)
,.y_cord_width_p(cord_width_p-1)
,.dirs_lp(5)
)
router
(.clk_i(clk)
,.reset_i(reset)
,.link_i(router_link_li)
,.link_o(router_link_lo)
,.my_x_i('0)
,.my_y_i('0)
);
assign router_link_li[S].data = bot_data_li;
assign router_link_li[N].data = top_data_li;
assign router_link_li[E].data = right_data_li;
assign router_link_li[W].data = left_data_li;
assign router_link_li[P].data = '0;
assign router_link_li[S].v = bot_v_li;
assign router_link_li[N].v = top_v_li;
assign router_link_li[E].v = right_v_li;
assign router_link_li[W].v = left_v_li;
assign router_link_li[P].v = '0;
assign router_link_li[S].ready_and_rev ='0;
assign router_link_li[N].ready_and_rev ='0;
assign router_link_li[E].ready_and_rev ='0;
assign router_link_li[W].ready_and_rev ='0;
assign router_link_li[P].ready_and_rev = link_lo.ready_and_rev;
assign bot_yumi_lo = router_link_lo[S].ready_and_rev & router_link_li[S].v;
assign top_yumi_lo = router_link_lo[N].ready_and_rev & router_link_li[N].v;
assign right_yumi_lo = router_link_lo[E].ready_and_rev & router_link_li[E].v;
assign left_yumi_lo = router_link_lo[W].ready_and_rev & router_link_li[W].v;
assign link_li.data = router_link_lo[P].data;
assign link_li.v = router_link_lo[P].v;
initial
begin
$assertoff();
@(posedge clk)
@(negedge reset)
$asserton();
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:26 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_led_controller_0_0_stub.v
// Design : ip_design_led_controller_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "led_controller_v1_0,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(LEDs_out, s00_axi_awaddr, s00_axi_awprot,
s00_axi_awvalid, s00_axi_awready, s00_axi_wdata, s00_axi_wstrb, s00_axi_wvalid,
s00_axi_wready, s00_axi_bresp, s00_axi_bvalid, s00_axi_bready, s00_axi_araddr,
s00_axi_arprot, s00_axi_arvalid, s00_axi_arready, s00_axi_rdata, s00_axi_rresp,
s00_axi_rvalid, s00_axi_rready, s00_axi_aclk, s00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */;
output [7:0]LEDs_out;
input [3:0]s00_axi_awaddr;
input [2:0]s00_axi_awprot;
input s00_axi_awvalid;
output s00_axi_awready;
input [31:0]s00_axi_wdata;
input [3:0]s00_axi_wstrb;
input s00_axi_wvalid;
output s00_axi_wready;
output [1:0]s00_axi_bresp;
output s00_axi_bvalid;
input s00_axi_bready;
input [3:0]s00_axi_araddr;
input [2:0]s00_axi_arprot;
input s00_axi_arvalid;
output s00_axi_arready;
output [31:0]s00_axi_rdata;
output [1:0]s00_axi_rresp;
output s00_axi_rvalid;
input s00_axi_rready;
input s00_axi_aclk;
input s00_axi_aresetn;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__EINVP_BEHAVIORAL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__einvp (
Z ,
A ,
TE
);
// Module ports
output Z ;
input A ;
input TE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
notif1 notif10 (Z , A, TE );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVP_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06:38:31 04/14/2015
// Design Name:
// Module Name: map
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module map_generator(clk_vga, reset, CurrentX, CurrentY, playerColor, mapData,
mapX, mapY
);
input [9:0]CurrentX;
input [8:0]CurrentY;
input [7:0]playerColor;
input [3:0]mapX;
input [3:0]mapY;
input clk_vga;
input reset;
output [7:0]mapData;
reg [7:0]mColor;
//Rooms
wire [7:0] startCastle;
wire [7:0] hallwayTop;
wire [7:0] hallwayRight;
wire [7:0] blackKeyRoom;
wire [7:0] hallwayLeft;
wire [7:0] centerMaze;
wire [7:0] eCenterMaze;
wire [7:0] nCenterMaze;
wire [7:0] sCenterMaze;
wire [7:0] swMaze;
wire [7:0] castle;
//Each map layout is split into its own module for readability
StartCastle StartCastle(
.clk_vga(clk_vga),
.CurrentX(CurrentX),
.CurrentY(CurrentY),
.mapData(startCastle),
.wall(playerColor)
);
HallwayTop HallwayTop(
.clk_vga(clk_vga),
.CurrentX(CurrentX),
.CurrentY(CurrentY),
.mapData(hallwayTop),
.wall(playerColor)
);
/*
HallwayRight HallwayRight(
.clk_vga(clk_vga),
.CurrentX(CurrentX),
.CurrentY(CurrentY),
.mapData(hallwayRight),
.wall(playerColor)
);
BlackKeyRoom BlackKeyRoom(
.clk_vga(clk_vga),
.CurrentX(CurrentX),
.CurrentY(CurrentY),
.mapData(blackKeyRoom),
.wall(playerColor)
);
*/
HallwayLeft HallwayLeft(
.clk_vga(clk_vga),
.CurrentX(CurrentX),
.CurrentY(CurrentY),
.mapData(hallwayLeft),
.wall(playerColor)
);
Castle Castle(
.clk_vga(clk_vga),
.CurrentX(CurrentX),
.CurrentY(CurrentY),
.mapData(castle),
.wall(playerColor)
);
CenterMaze CenterMaze(
.clk_vga(clk_vga),
.CurrentX(CurrentX),
.CurrentY(CurrentY),
.mapData(centerMaze),
.wall(playerColor)
);
ECenter ECenterMaze(
.clk_vga(clk_vga),
.CurrentX(CurrentX),
.CurrentY(CurrentY),
.mapData(eCenterMaze),
.wall(playerColor)
);
NCenterMaze NCenterMaze(
.clk_vga(clk_vga),
.CurrentX(CurrentX),
.CurrentY(CurrentY),
.mapData(nCenterMaze),
.wall(playerColor)
);
SCenterMaze SCenterMaze(
.clk_vga(clk_vga),
.CurrentX(CurrentX),
.CurrentY(CurrentY),
.mapData(sCenterMaze),
.wall(playerColor)
);
SWMaze SWMaze(
.clk_vga(clk_vga),
.CurrentX(CurrentX),
.CurrentY(CurrentY),
.mapData(swMaze),
.wall(playerColor)
);
//Draws the map based on the current mapX and mapY
//The idea is to have only one output from the map generator module
//And do all the heavy lifting in the top module
//The map generator acts as a datapath for the static objects in the game
always @(posedge clk_vga) begin
//Starting castle
if(mapX == 3 && mapY == 5)
mColor[7:0] <= startCastle[7:0];
//Central hallway
else if(mapX == 3 && mapY == 6)
mColor[7:0] <= hallwayTop[7:0];
//Right hallway
else if(mapX == 4 && mapY == 6)
mColor[7:0] <= hallwayRight[7:0];
//Black key room
else if(mapX == 4 && mapY == 7)
mColor[7:0] <= blackKeyRoom[7:0];
//Left hallway
else if(mapX == 2 && mapY == 6)
mColor[7:0] <= hallwayLeft;
//South Center Maze
else if(mapX == 1 && mapY == 6)
mColor[7:0] <= sCenterMaze;
//South West Maze
else if(mapX == 2 && mapY == 4)
mColor[7:0] <= swMaze;
//East Center Maze
else if(mapX == 2 && mapY == 5)
mColor[7:0] <= eCenterMaze;
//Center Maze
else if(mapX == 1 && mapY == 5)
mColor[7:0] <= centerMaze;
//North Center Maze
else if(mapX == 1 && mapY == 4)
mColor[7:0] <= nCenterMaze;
//Black Castle
else if(mapX == 1 && mapY == 3)
mColor[7:0] <= castle;
//Challice Room
else if(mapX == 1 && mapY == 2)
mColor[7:0] <= startCastle;
//No map found
else begin
mColor[7:0] <= 8'b00000000;
end
end
assign mapData[7:0] = mColor[7:0];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVN_8_V
`define SKY130_FD_SC_MS__EINVN_8_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__einvn_8 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__einvn_8 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVN_8_V
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module processing_system7_0 (
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
FCLK_CLK0,
FCLK_CLK3,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
input [47 : 0] GPIO_I;
output [47 : 0] GPIO_O;
output [47 : 0] GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1 : 0] USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11 : 0] M_AXI_GP1_ARID;
output [11 : 0] M_AXI_GP1_AWID;
output [11 : 0] M_AXI_GP1_WID;
output [1 : 0] M_AXI_GP1_ARBURST;
output [1 : 0] M_AXI_GP1_ARLOCK;
output [2 : 0] M_AXI_GP1_ARSIZE;
output [1 : 0] M_AXI_GP1_AWBURST;
output [1 : 0] M_AXI_GP1_AWLOCK;
output [2 : 0] M_AXI_GP1_AWSIZE;
output [2 : 0] M_AXI_GP1_ARPROT;
output [2 : 0] M_AXI_GP1_AWPROT;
output [31 : 0] M_AXI_GP1_ARADDR;
output [31 : 0] M_AXI_GP1_AWADDR;
output [31 : 0] M_AXI_GP1_WDATA;
output [3 : 0] M_AXI_GP1_ARCACHE;
output [3 : 0] M_AXI_GP1_ARLEN;
output [3 : 0] M_AXI_GP1_ARQOS;
output [3 : 0] M_AXI_GP1_AWCACHE;
output [3 : 0] M_AXI_GP1_AWLEN;
output [3 : 0] M_AXI_GP1_AWQOS;
output [3 : 0] M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11 : 0] M_AXI_GP1_BID;
input [11 : 0] M_AXI_GP1_RID;
input [1 : 0] M_AXI_GP1_BRESP;
input [1 : 0] M_AXI_GP1_RRESP;
input [31 : 0] M_AXI_GP1_RDATA;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1 : 0] S_AXI_HP1_BRESP;
output [1 : 0] S_AXI_HP1_RRESP;
output [5 : 0] S_AXI_HP1_BID;
output [5 : 0] S_AXI_HP1_RID;
output [63 : 0] S_AXI_HP1_RDATA;
output [7 : 0] S_AXI_HP1_RCOUNT;
output [7 : 0] S_AXI_HP1_WCOUNT;
output [2 : 0] S_AXI_HP1_RACOUNT;
output [5 : 0] S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1 : 0] S_AXI_HP1_ARBURST;
input [1 : 0] S_AXI_HP1_ARLOCK;
input [2 : 0] S_AXI_HP1_ARSIZE;
input [1 : 0] S_AXI_HP1_AWBURST;
input [1 : 0] S_AXI_HP1_AWLOCK;
input [2 : 0] S_AXI_HP1_AWSIZE;
input [2 : 0] S_AXI_HP1_ARPROT;
input [2 : 0] S_AXI_HP1_AWPROT;
input [31 : 0] S_AXI_HP1_ARADDR;
input [31 : 0] S_AXI_HP1_AWADDR;
input [3 : 0] S_AXI_HP1_ARCACHE;
input [3 : 0] S_AXI_HP1_ARLEN;
input [3 : 0] S_AXI_HP1_ARQOS;
input [3 : 0] S_AXI_HP1_AWCACHE;
input [3 : 0] S_AXI_HP1_AWLEN;
input [3 : 0] S_AXI_HP1_AWQOS;
input [5 : 0] S_AXI_HP1_ARID;
input [5 : 0] S_AXI_HP1_AWID;
input [5 : 0] S_AXI_HP1_WID;
input [63 : 0] S_AXI_HP1_WDATA;
input [7 : 0] S_AXI_HP1_WSTRB;
output FCLK_CLK0;
output FCLK_CLK3;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_processing_system7_bfm #(
.C_USE_M_AXI_GP0(0),
.C_USE_M_AXI_GP1(1),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(1),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(32),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(100),
.C_FCLK_CLK1_FREQ(200),
.C_FCLK_CLK2_FREQ(200),
.C_FCLK_CLK3_FREQ(40),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(),
.M_AXI_GP0_AWVALID(),
.M_AXI_GP0_BREADY(),
.M_AXI_GP0_RREADY(),
.M_AXI_GP0_WLAST(),
.M_AXI_GP0_WVALID(),
.M_AXI_GP0_ARID(),
.M_AXI_GP0_AWID(),
.M_AXI_GP0_WID(),
.M_AXI_GP0_ARBURST(),
.M_AXI_GP0_ARLOCK(),
.M_AXI_GP0_ARSIZE(),
.M_AXI_GP0_AWBURST(),
.M_AXI_GP0_AWLOCK(),
.M_AXI_GP0_AWSIZE(),
.M_AXI_GP0_ARPROT(),
.M_AXI_GP0_AWPROT(),
.M_AXI_GP0_ARADDR(),
.M_AXI_GP0_AWADDR(),
.M_AXI_GP0_WDATA(),
.M_AXI_GP0_ARCACHE(),
.M_AXI_GP0_ARLEN(),
.M_AXI_GP0_ARQOS(),
.M_AXI_GP0_AWCACHE(),
.M_AXI_GP0_AWLEN(),
.M_AXI_GP0_AWQOS(),
.M_AXI_GP0_WSTRB(),
.M_AXI_GP0_ACLK(1'B0),
.M_AXI_GP0_ARREADY(1'B0),
.M_AXI_GP0_AWREADY(1'B0),
.M_AXI_GP0_BVALID(1'B0),
.M_AXI_GP0_RLAST(1'B0),
.M_AXI_GP0_RVALID(1'B0),
.M_AXI_GP0_WREADY(1'B0),
.M_AXI_GP0_BID(12'B0),
.M_AXI_GP0_RID(12'B0),
.M_AXI_GP0_BRESP(2'B0),
.M_AXI_GP0_RRESP(2'B0),
.M_AXI_GP0_RDATA(32'B0),
.M_AXI_GP1_ARVALID(M_AXI_GP1_ARVALID),
.M_AXI_GP1_AWVALID(M_AXI_GP1_AWVALID),
.M_AXI_GP1_BREADY(M_AXI_GP1_BREADY),
.M_AXI_GP1_RREADY(M_AXI_GP1_RREADY),
.M_AXI_GP1_WLAST(M_AXI_GP1_WLAST),
.M_AXI_GP1_WVALID(M_AXI_GP1_WVALID),
.M_AXI_GP1_ARID(M_AXI_GP1_ARID),
.M_AXI_GP1_AWID(M_AXI_GP1_AWID),
.M_AXI_GP1_WID(M_AXI_GP1_WID),
.M_AXI_GP1_ARBURST(M_AXI_GP1_ARBURST),
.M_AXI_GP1_ARLOCK(M_AXI_GP1_ARLOCK),
.M_AXI_GP1_ARSIZE(M_AXI_GP1_ARSIZE),
.M_AXI_GP1_AWBURST(M_AXI_GP1_AWBURST),
.M_AXI_GP1_AWLOCK(M_AXI_GP1_AWLOCK),
.M_AXI_GP1_AWSIZE(M_AXI_GP1_AWSIZE),
.M_AXI_GP1_ARPROT(M_AXI_GP1_ARPROT),
.M_AXI_GP1_AWPROT(M_AXI_GP1_AWPROT),
.M_AXI_GP1_ARADDR(M_AXI_GP1_ARADDR),
.M_AXI_GP1_AWADDR(M_AXI_GP1_AWADDR),
.M_AXI_GP1_WDATA(M_AXI_GP1_WDATA),
.M_AXI_GP1_ARCACHE(M_AXI_GP1_ARCACHE),
.M_AXI_GP1_ARLEN(M_AXI_GP1_ARLEN),
.M_AXI_GP1_ARQOS(M_AXI_GP1_ARQOS),
.M_AXI_GP1_AWCACHE(M_AXI_GP1_AWCACHE),
.M_AXI_GP1_AWLEN(M_AXI_GP1_AWLEN),
.M_AXI_GP1_AWQOS(M_AXI_GP1_AWQOS),
.M_AXI_GP1_WSTRB(M_AXI_GP1_WSTRB),
.M_AXI_GP1_ACLK(M_AXI_GP1_ACLK),
.M_AXI_GP1_ARREADY(M_AXI_GP1_ARREADY),
.M_AXI_GP1_AWREADY(M_AXI_GP1_AWREADY),
.M_AXI_GP1_BVALID(M_AXI_GP1_BVALID),
.M_AXI_GP1_RLAST(M_AXI_GP1_RLAST),
.M_AXI_GP1_RVALID(M_AXI_GP1_RVALID),
.M_AXI_GP1_WREADY(M_AXI_GP1_WREADY),
.M_AXI_GP1_BID(M_AXI_GP1_BID),
.M_AXI_GP1_RID(M_AXI_GP1_RID),
.M_AXI_GP1_BRESP(M_AXI_GP1_BRESP),
.M_AXI_GP1_RRESP(M_AXI_GP1_RRESP),
.M_AXI_GP1_RDATA(M_AXI_GP1_RDATA),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(32'B0),
.S_AXI_HP0_WSTRB(4'B0),
.S_AXI_HP1_ARREADY(S_AXI_HP1_ARREADY),
.S_AXI_HP1_AWREADY(S_AXI_HP1_AWREADY),
.S_AXI_HP1_BVALID(S_AXI_HP1_BVALID),
.S_AXI_HP1_RLAST(S_AXI_HP1_RLAST),
.S_AXI_HP1_RVALID(S_AXI_HP1_RVALID),
.S_AXI_HP1_WREADY(S_AXI_HP1_WREADY),
.S_AXI_HP1_BRESP(S_AXI_HP1_BRESP),
.S_AXI_HP1_RRESP(S_AXI_HP1_RRESP),
.S_AXI_HP1_BID(S_AXI_HP1_BID),
.S_AXI_HP1_RID(S_AXI_HP1_RID),
.S_AXI_HP1_RDATA(S_AXI_HP1_RDATA),
.S_AXI_HP1_ACLK(S_AXI_HP1_ACLK),
.S_AXI_HP1_ARVALID(S_AXI_HP1_ARVALID),
.S_AXI_HP1_AWVALID(S_AXI_HP1_AWVALID),
.S_AXI_HP1_BREADY(S_AXI_HP1_BREADY),
.S_AXI_HP1_RREADY(S_AXI_HP1_RREADY),
.S_AXI_HP1_WLAST(S_AXI_HP1_WLAST),
.S_AXI_HP1_WVALID(S_AXI_HP1_WVALID),
.S_AXI_HP1_ARBURST(S_AXI_HP1_ARBURST),
.S_AXI_HP1_ARLOCK(S_AXI_HP1_ARLOCK),
.S_AXI_HP1_ARSIZE(S_AXI_HP1_ARSIZE),
.S_AXI_HP1_AWBURST(S_AXI_HP1_AWBURST),
.S_AXI_HP1_AWLOCK(S_AXI_HP1_AWLOCK),
.S_AXI_HP1_AWSIZE(S_AXI_HP1_AWSIZE),
.S_AXI_HP1_ARPROT(S_AXI_HP1_ARPROT),
.S_AXI_HP1_AWPROT(S_AXI_HP1_AWPROT),
.S_AXI_HP1_ARADDR(S_AXI_HP1_ARADDR),
.S_AXI_HP1_AWADDR(S_AXI_HP1_AWADDR),
.S_AXI_HP1_ARCACHE(S_AXI_HP1_ARCACHE),
.S_AXI_HP1_ARLEN(S_AXI_HP1_ARLEN),
.S_AXI_HP1_ARQOS(S_AXI_HP1_ARQOS),
.S_AXI_HP1_AWCACHE(S_AXI_HP1_AWCACHE),
.S_AXI_HP1_AWLEN(S_AXI_HP1_AWLEN),
.S_AXI_HP1_AWQOS(S_AXI_HP1_AWQOS),
.S_AXI_HP1_ARID(S_AXI_HP1_ARID),
.S_AXI_HP1_AWID(S_AXI_HP1_AWID),
.S_AXI_HP1_WID(S_AXI_HP1_WID),
.S_AXI_HP1_WDATA(S_AXI_HP1_WDATA),
.S_AXI_HP1_WSTRB(S_AXI_HP1_WSTRB),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(FCLK_CLK3),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:12.0
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_recv_fifo (
clk,
srst,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input wire clk;
input wire srst;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
input wire [255 : 0] din;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
input wire wr_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
input wire rd_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
output wire [255 : 0] dout;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
output wire full;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
output wire empty;
fifo_generator_v12_0 #(
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(8),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(256),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(256),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex7"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(0),
.C_HAS_SRST(1),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(127),
.C_PROG_FULL_THRESH_NEGATE_VAL(126),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(8),
.C_RD_DEPTH(128),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(7),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_PIPELINE_REG(0),
.C_POWER_SAVING_MODE(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(8),
.C_WR_DEPTH(128),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(7),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(2),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_HAS_AXI_ID(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(1),
.C_AXIS_TKEEP_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_PRIM_FIFO_TYPE_WACH("512x36"),
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
.C_PRIM_FIFO_TYPE_RACH("512x36"),
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'D0),
.backup_marker(1'D0),
.clk(clk),
.rst(1'D0),
.srst(srst),
.wr_clk(1'D0),
.wr_rst(1'D0),
.rd_clk(1'D0),
.rd_rst(1'D0),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(7'B0),
.prog_empty_thresh_assert(7'B0),
.prog_empty_thresh_negate(7'B0),
.prog_full_thresh(7'B0),
.prog_full_thresh_assert(7'B0),
.prog_full_thresh_negate(7'B0),
.int_clk(1'D0),
.injectdbiterr(1'D0),
.injectsbiterr(1'D0),
.sleep(1'D0),
.dout(dout),
.full(full),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.wr_rst_busy(),
.rd_rst_busy(),
.m_aclk(1'D0),
.s_aclk(1'D0),
.s_aresetn(1'D0),
.m_aclk_en(1'D0),
.s_aclk_en(1'D0),
.s_axi_awid(1'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(1'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wid(1'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'D0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'D0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'D0),
.m_axi_bid(1'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'D0),
.m_axi_bready(),
.s_axi_arid(1'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(1'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'D0),
.m_axi_rid(1'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'D0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'D0),
.m_axi_rready(),
.s_axis_tvalid(1'D0),
.s_axis_tready(),
.s_axis_tdata(8'B0),
.s_axis_tstrb(1'B0),
.s_axis_tkeep(1'B0),
.s_axis_tlast(1'D0),
.s_axis_tid(1'B0),
.s_axis_tdest(1'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'D0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'D0),
.axi_aw_injectdbiterr(1'D0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'D0),
.axi_w_injectdbiterr(1'D0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectsbiterr(1'D0),
.axi_b_injectdbiterr(1'D0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectsbiterr(1'D0),
.axi_ar_injectdbiterr(1'D0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'D0),
.axi_r_injectdbiterr(1'D0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectsbiterr(1'D0),
.axis_injectdbiterr(1'D0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule
|
module contadorprueba (
input [7:0] cantidad,
input entrada,
input ENABLE,
input clk,
input reset,
output [3:0] an,
output [6:0] seg,
output pulse
);
wire [7:0] count;
wire [3:0] centenas;
wire [3:0] decenas;
wire [3:0] unidades;
wire [1:0] mostrar;
wire [3:0] digito;
cantidadecho cantidadecho0 (
.cantidad ( cantidad ),
.entrada ( entrada ),
.CLKOUT ( CLKOUT ),
.reset ( reset ),
.ECHO ( ECHO )
);
contador contador0 (
.count ( count ),
.pulse ( pulse ),
.calculate ( calculate ),
.ECHO ( ECHO ),
.ENABLE ( ENABLE ),
.CLKOUT ( CLKOUT ),
.reset ( reset )
);
divisorfrec divisorfrec0 (
.clk ( clk ),
.CLKOUT ( CLKOUT )
);
anteconmutador anteconmutador0 (
.clk ( clk ),
.count ( count ),
.calculate ( calculate ),
.centenas ( centenas ),
.decenas ( decenas ),
.unidades ( unidades ),
.C ( C ),
.De ( De ),
.U ( U )
);
conmutacion conmutacion0 (
.centenas ( centenas ),
.decenas ( decenas ),
.unidades ( unidades ),
.C ( C ),
.De ( De ),
.U ( U ),
.CLKOUTseg ( CLKOUTseg ),
.mostrar ( mostrar ),
.digito ( digito )
);
display display0 (
.mostrar ( mostrar ),
.digito ( digito ),
.an ( an ),
.seg ( seg )
);
divisorfrecdisp divisorfrecdisp0 (
.clk ( clk ),
.CLKOUTseg ( CLKOUTseg )
);
endmodule
|
`timescale 1ns / 1ps
module Altera_UP_PS2_Data_In (
// Inputs
clk,
reset,
wait_for_incoming_data,
start_receiving_data,
ps2_clk_posedge,
ps2_clk_negedge,
ps2_data,
// Bidirectionals
// Outputs
received_data,
received_data_en // If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input wait_for_incoming_data;
input start_receiving_data;
input ps2_clk_posedge;
input ps2_clk_negedge;
input ps2_data;
// Bidirectionals
// Outputs
output reg [7:0] received_data;
output reg received_data_en;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_WAIT_FOR_DATA = 3'h1,
PS2_STATE_2_DATA_IN = 3'h2,
PS2_STATE_3_PARITY_IN = 3'h3,
PS2_STATE_4_STOP_IN = 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
reg [3:0] data_count;
reg [7:0] data_shift_reg;
// State Machine Registers
reg [2:0] ns_ps2_receiver;
reg [2:0] s_ps2_receiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
s_ps2_receiver <= PS2_STATE_0_IDLE;
else
s_ps2_receiver <= ns_ps2_receiver;
end
always @(*)
begin
// Defaults
ns_ps2_receiver = PS2_STATE_0_IDLE;
case (s_ps2_receiver)
PS2_STATE_0_IDLE:
begin
if ((wait_for_incoming_data == 1'b1) &&
(received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
else if ((start_receiving_data == 1'b1) &&
(received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_WAIT_FOR_DATA:
begin
if ((ps2_data == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else if (wait_for_incoming_data == 1'b0)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
end
PS2_STATE_2_DATA_IN:
begin
if ((data_count == 3'h7) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
else
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
end
PS2_STATE_3_PARITY_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
else
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
end
PS2_STATE_4_STOP_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
end
default:
begin
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
data_count <= 3'h0;
else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
(ps2_clk_posedge == 1'b1))
data_count <= data_count + 3'h1;
else if (s_ps2_receiver != PS2_STATE_2_DATA_IN)
data_count <= 3'h0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_shift_reg <= 8'h00;
else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
(ps2_clk_posedge == 1'b1))
data_shift_reg <= {ps2_data, data_shift_reg[7:1]};
end
always @(posedge clk)
begin
if (reset == 1'b1)
received_data <= 8'h00;
else if (s_ps2_receiver == PS2_STATE_4_STOP_IN)
received_data <= data_shift_reg;
end
always @(posedge clk)
begin
if (reset == 1'b1)
received_data_en <= 1'b0;
else if ((s_ps2_receiver == PS2_STATE_4_STOP_IN) &&
(ps2_clk_posedge == 1'b1))
received_data_en <= 1'b1;
else
received_data_en <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Wishbone RAM
*/
module wb_ram #
(
parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
parameter ADDR_WIDTH = 32, // width of address bus in bits
parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
)
(
input wire clk,
input wire [ADDR_WIDTH-1:0] adr_i, // ADR_I() address
input wire [DATA_WIDTH-1:0] dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] dat_o, // DAT_O() data out
input wire we_i, // WE_I write enable input
input wire [SELECT_WIDTH-1:0] sel_i, // SEL_I() select input
input wire stb_i, // STB_I strobe input
output wire ack_o, // ACK_O acknowledge output
input wire cyc_i // CYC_I cycle input
);
// for interfaces that are more than one word wide, disable address lines
parameter VALID_ADDR_WIDTH = ADDR_WIDTH - $clog2(SELECT_WIDTH);
// width of data port in words (1, 2, 4, or 8)
parameter WORD_WIDTH = SELECT_WIDTH;
// size of words (8, 16, 32, or 64 bits)
parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
reg [DATA_WIDTH-1:0] dat_o_reg = {DATA_WIDTH{1'b0}};
reg ack_o_reg = 1'b0;
// (* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH-1:0] mem[(2**VALID_ADDR_WIDTH)-1:0];
wire [VALID_ADDR_WIDTH-1:0] adr_i_valid = adr_i >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
assign dat_o = dat_o_reg;
assign ack_o = ack_o_reg;
integer i;
initial begin
for (i = 0; i < 2**VALID_ADDR_WIDTH; i = i + 1) begin
mem[i] = 0;
end
end
always @(posedge clk) begin
ack_o_reg <= 1'b0;
for (i = 0; i < WORD_WIDTH; i = i + 1) begin
if (cyc_i & stb_i & ~ack_o) begin
if (we_i & sel_i[i]) begin
mem[adr_i_valid][WORD_SIZE*i +: WORD_SIZE] <= dat_i[WORD_SIZE*i +: WORD_SIZE];
end
dat_o_reg[WORD_SIZE*i +: WORD_SIZE] <= mem[adr_i_valid][WORD_SIZE*i +: WORD_SIZE];
ack_o_reg <= 1'b1;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:05:56 02/23/2015
// Design Name:
// Module Name: mult_descale_pipeline
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mult_descale_pipeline(
input [31:0] a_multiplicand,
input [31:0] b_multiplier,
input [31:0] z_scale,
input [7:0] InsTagScaleOut,
input ScaleValid,
input NatLogFlagScaleOut,
input reset,
input clock,
output [31:0] FinalProduct,
output done,
output [7:0] InsTagDescale,
output [31:0] z_out
);
wire idle_Special, idle_Multiply, idle_NormaliseProd;
wire [32:0] aout_Special,bout_Special;
wire [32:0] zout_Special,zout_Multiply,zout_NormaliseProd;
wire [49:0] productout_Multiply, productout_NormaliseProd;
wire [7:0] InsTagSpecial,InsTagMultiply,InsTagNormaliseProd;
wire ScaleValidSpecial,ScaleValidMultiply,ScaleValidNormaliseProd;
wire [31:0] z_Special,z_Multiply,z_NormaliseProd;
SpecialMultDescale Mult1 (
.ain_Special(a_multiplicand),
.bin_Special(b_multiplier),
.InsTagScaleOut(InsTagScaleOut),
.ScaleValid(ScaleValid),
.NatLogFlagScaleOut(NatLogFlagScaleOut),
.z_scale(z_scale),
.reset(reset),
.clock(clock),
.idle_Special(idle_Special),
.aout_Special(aout_Special),
.bout_Special(bout_Special),
.zout_Special(zout_Special),
.InsTagSpecial(InsTagSpecial),
.ScaleValidSpecial(ScaleValidSpecial),
.z_Special(z_Special)
);
MultiplyMultDescale Mult2 (
.aout_Special(aout_Special),
.bout_Special(bout_Special),
.zout_Special(zout_Special),
.idle_Special(idle_Special),
.InsTagSpecial(InsTagSpecial),
.ScaleValidSpecial(ScaleValidSpecial),
.z_Special(z_Special),
.clock(clock),
.idle_Multiply(idle_Multiply),
.zout_Multiply(zout_Multiply),
.productout_Multiply(productout_Multiply),
.InsTagMultiply(InsTagMultiply),
.ScaleValidMultiply(ScaleValidMultiply),
.z_Multiply(z_Multiply)
);
NormaliseProdMultDescale Mult3 (
.zout_Multiply(zout_Multiply),
.productout_Multiply(productout_Multiply),
.InsTagMultiply(InsTagMultiply),
.ScaleValidMultiply(ScaleValidMultiply),
.z_Multiply(z_Multiply),
.clock(clock),
.idle_Multiply(idle_Multiply),
.idle_NormaliseProd(idle_NormaliseProd),
.zout_NormaliseProd(zout_NormaliseProd),
.productout_NormaliseProd(productout_NormaliseProd),
.InsTagNormaliseProd(InsTagNormaliseProd),
.ScaleValidNormaliseProd(ScaleValidNormaliseProd),
.z_NormaliseProd(z_NormaliseProd)
);
Pack_z_descale Mult4 (
.idle_NormaliseProd(idle_NormaliseProd),
.zout_NormaliseProd(zout_NormaliseProd),
.productout_NormaliseProd(productout_NormaliseProd),
.InsTagNormaliseProd(InsTagNormaliseProd),
.ScaleValidNormaliseProd(ScaleValidNormaliseProd),
.z_NormaliseProd(z_NormaliseProd),
.reset(reset),
.clock(clock),
.done(done),
.FinalProduct(FinalProduct),
.InsTagPack(InsTagDescale),
.z_Descale(z_out)
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Cal Poly Pomona
// Engineer: Byron Phung
//
// Create Date: 13:34:32 04/27/2016
// Design Name: Search_4Comparators
// Module Name: D:/Documents/College/CalPolyPomona/SeniorProject/hardware-accelerated-dna-matching-and-variation-detection/Hardware/Verilog/Search_4Comparators_tf.v
// Project Name: Verilog
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Search_4Comparators
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Search_4Comparators_tf;
// Inputs
reg clock;
reg reset;
reg [1023:0] data;
reg [63:0] key;
// Outputs
wire match;
// Instantiate the Unit Under Test (UUT)
Search_4Comparators uut (
.clock(clock),
.reset(reset),
.data(data),
.key(key),
.match(match)
);
// Alternate the clock every unit of time.
initial begin
clock = 0;
repeat (1_000_000)
#1 clock =~ clock;
end
initial begin
// Initialization
reset = 1;
data = 1024'b0100111010111010001100110010000010010111001110111010001010111000010111111100010011101110000010000010010100001010001111011010010010001101000100100001111100010111001110011110010001000111110010000001101100000000100100011000011100011110000110111011011000111011010000011010011011010000011111101100101100000101011101010011000010001110001110100111011000000100101000000100001010011010000011000100100000100011001101110000100011001111110001010011001100101011100100000000110000110000001010011010001000101101111000111100111100110000111100010000001000010000100110000000000011110011101000101100110011000011111000000001001001100100000000000000000001000010000010011001111000110001000010111111110101100000111110011001111000100000001100000011111111010110000010111100110111111110101110111110010001100001110010111001000110101011011110111000000100001101110000110000110010101000111001110001011100110101111100000001001100011000111011101000100000101011100000000110111010111101101001000100011110011010101110101111110111100100011100001111111110001011;
key = 64'b0100111010111010001100110010000010010111001110111010001010111000;
@(negedge clock);
// Turn off the reset and let the module be tested as is.
reset = 0;
end
endmodule
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_id_track.v
// Version : v1.0
// Description: To track the id received against the stored id.
// ARID and RID are tracked in case of read operations.
// AWID and BID are tracked in case of write operations.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_id_track
#(
parameter ID_WIDTH = 1
) (
input Clk ,
input rst_l ,
input [ID_WIDTH-1:0] in_push_id ,
input in_push ,
input [ID_WIDTH-1:0] in_search_id ,
input [3:0] in_clear_pos ,
input in_only_entry0,
output [3:0] out_push_pos ,
output [3:0] out_search_hit,
output [3:0] out_free
);
reg [ID_WIDTH:0] id_arr0_ff, id_arr1_ff, id_arr2_ff, id_arr3_ff;
reg [3:0] push_pos_ff, push_pos_2ff;
reg [3:0] in_clear_pos_ff;
wire [ID_WIDTH:0] push_id = { 1'b1, in_push_id[ID_WIDTH-1:0] };
wire [3:0] push_search = { (push_id[ID_WIDTH:0] == id_arr3_ff[ID_WIDTH:0]),
(push_id[ID_WIDTH:0] == id_arr2_ff[ID_WIDTH:0]),
(push_id[ID_WIDTH:0] == id_arr1_ff[ID_WIDTH:0]),
(push_id[ID_WIDTH:0] == id_arr0_ff[ID_WIDTH:0]) };
wire [3:0] free_pre = { ~id_arr3_ff[ID_WIDTH], ~id_arr2_ff[ID_WIDTH],
~id_arr1_ff[ID_WIDTH], ~id_arr0_ff[ID_WIDTH] };
wire [3:0] free = (in_only_entry0) ? { 3'b000, free_pre[0] } : free_pre[3:0];
wire [3:0] first_free = (free[0]) ? 4'h1 :
(free[1]) ? 4'h2 :
(free[2]) ? 4'h4 :
(free[3]) ? 4'h8 : 4'h0;
wire [3:0] push_pos = (in_push == 1'b0) ? 4'h0 :
(push_search[3:0] != 4'h0) ? push_search[3:0] :
first_free[3:0];
wire [ID_WIDTH:0] search_id = { 1'b1, in_search_id[ID_WIDTH-1:0] };
wire [3:0] search_pos = { (search_id[ID_WIDTH:0] == id_arr3_ff[ID_WIDTH:0]),
(search_id[ID_WIDTH:0] == id_arr2_ff[ID_WIDTH:0]),
(search_id[ID_WIDTH:0] == id_arr1_ff[ID_WIDTH:0]),
(search_id[ID_WIDTH:0] == id_arr0_ff[ID_WIDTH:0]) };
wire [3:0] do_clear = ~push_pos_ff[3:0] & ~push_pos_2ff[3:0] &
in_clear_pos_ff[3:0];
wire [ID_WIDTH:0] id_arr0 = (push_pos[0]) ? push_id[ID_WIDTH:0] :
{ (do_clear[0]) ? 1'b0:id_arr0_ff[ID_WIDTH], id_arr0_ff[ID_WIDTH-1:0] };
wire [ID_WIDTH:0] id_arr1 = (push_pos[1]) ? push_id[ID_WIDTH:0] :
{ (do_clear[1]) ? 1'b0:id_arr1_ff[ID_WIDTH], id_arr1_ff[ID_WIDTH-1:0] };
wire [ID_WIDTH:0] id_arr2 = (push_pos[2]) ? push_id[ID_WIDTH:0] :
{ (do_clear[2]) ? 1'b0:id_arr2_ff[ID_WIDTH], id_arr2_ff[ID_WIDTH-1:0] };
wire [ID_WIDTH:0] id_arr3 = (push_pos[3]) ? push_id[ID_WIDTH:0] :
{ (do_clear[3]) ? 1'b0:id_arr3_ff[ID_WIDTH], id_arr3_ff[ID_WIDTH-1:0] };
always @(posedge Clk) begin
id_arr0_ff[ID_WIDTH:0] <= (rst_l) ? id_arr0[ID_WIDTH:0] : 1'b0;
id_arr1_ff[ID_WIDTH:0] <= (rst_l) ? id_arr1[ID_WIDTH:0] : 1'b0;
id_arr2_ff[ID_WIDTH:0] <= (rst_l) ? id_arr2[ID_WIDTH:0] : 1'b0;
id_arr3_ff[ID_WIDTH:0] <= (rst_l) ? id_arr3[ID_WIDTH:0] : 1'b0;
push_pos_ff[3:0] <= (rst_l) ? push_pos[3:0] : 4'h0;
push_pos_2ff[3:0] <= (rst_l) ? push_pos_ff[3:0] : 4'h0;
in_clear_pos_ff[3:0] <= (rst_l) ? in_clear_pos[3:0] : 4'h0;
end
assign out_search_hit[3:0] = search_pos[3:0];
assign out_push_pos[3:0] = push_pos[3:0];
assign out_free[3:0] = free[3:0];
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.0
// \ \ Application: MIG
// / / Filename: ddr2_mem_if_top.v
// /___/ /\ Date Last Modified: $Date: 2009/01/15 14:22:14 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR/DDR2
//Purpose:
// Top-level for parameterizable (DDR or DDR2) memory interface
//Reference:
//Revision History:
// Rev 1.1 - Parameter USE_DM_PORT added. PK. 6/25/08
// Rev 1.2 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08
// Rev 1.3 - Parameter CS_BITS added. PK. 10/8/08
// Rev 1.4 - Parameter IODELAY_GRP added. PK. 11/27/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_mem_if_top #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module ddr2_mig module. Please refer to
// the ddr2_mig module for actual values.
parameter BANK_WIDTH = 2,
parameter CKE_WIDTH = 1,
parameter CLK_WIDTH = 1,
parameter COL_WIDTH = 10,
parameter CS_BITS = 0,
parameter CS_NUM = 1,
parameter CS_WIDTH = 1,
parameter USE_DM_PORT = 1,
parameter DM_WIDTH = 9,
parameter DQ_WIDTH = 72,
parameter DQ_BITS = 7,
parameter DQ_PER_DQS = 8,
parameter DQS_BITS = 4,
parameter DQS_WIDTH = 9,
parameter HIGH_PERFORMANCE_MODE = "TRUE",
parameter IODELAY_GRP = "IODELAY_MIG",
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 14,
parameter APPDATA_WIDTH = 144,
parameter ADDITIVE_LAT = 0,
parameter BURST_LEN = 4,
parameter BURST_TYPE = 0,
parameter CAS_LAT = 5,
parameter ECC_ENABLE = 0,
parameter MULTI_BANK_EN = 1,
parameter TWO_T_TIME_EN = 0,
parameter ODT_TYPE = 1,
parameter DDR_TYPE = 1,
parameter REDUCE_DRV = 0,
parameter REG_ENABLE = 1,
parameter TREFI_NS = 7800,
parameter TRAS = 40000,
parameter TRCD = 15000,
parameter TRFC = 105000,
parameter TRP = 15000,
parameter TRTP = 7500,
parameter TWR = 15000,
parameter TWTR = 10000,
parameter CLK_PERIOD = 3000,
parameter SIM_ONLY = 0,
parameter DEBUG_EN = 0,
parameter FPGA_SPEED_GRADE = 2
)
(
input clk0,
input usr_clk, // jb
input clk90,
input clkdiv0,
input rst0,
input rst90,
input rstdiv0,
input [2:0] app_af_cmd,
input [30:0] app_af_addr,
input app_af_wren,
input app_wdf_wren,
input [APPDATA_WIDTH-1:0] app_wdf_data,
input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
output [1:0] rd_ecc_error,
output app_af_afull,
output app_wdf_afull,
output rd_data_valid,
output [APPDATA_WIDTH-1:0] rd_data_fifo_out,
output phy_init_done,
output [CLK_WIDTH-1:0] ddr_ck,
output [CLK_WIDTH-1:0] ddr_ck_n,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_ras_n,
output ddr_cas_n,
output ddr_we_n,
output [CS_WIDTH-1:0] ddr_cs_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [ODT_WIDTH-1:0] ddr_odt,
output [DM_WIDTH-1:0] ddr_dm,
inout [DQS_WIDTH-1:0] ddr_dqs,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQ_WIDTH-1:0] ddr_dq,
// Debug signals (optional use)
input dbg_idel_up_all,
input dbg_idel_down_all,
input dbg_idel_up_dq,
input dbg_idel_down_dq,
input dbg_idel_up_dqs,
input dbg_idel_down_dqs,
input dbg_idel_up_gate,
input dbg_idel_down_gate,
input [DQ_BITS-1:0] dbg_sel_idel_dq,
input dbg_sel_all_idel_dq,
input [DQS_BITS:0] dbg_sel_idel_dqs,
input dbg_sel_all_idel_dqs,
input [DQS_BITS:0] dbg_sel_idel_gate,
input dbg_sel_all_idel_gate,
output [3:0] dbg_calib_done,
output [3:0] dbg_calib_err,
output [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt,
output [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt,
output [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt,
output [DQS_WIDTH-1:0] dbg_calib_rd_data_sel,
output [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly,
output [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly
, input sp_refresh_disable
);
wire [30:0] af_addr;
wire [2:0] af_cmd;
wire af_empty;
wire [ROW_WIDTH-1:0] ctrl_addr;
wire ctrl_af_rden;
wire [BANK_WIDTH-1:0] ctrl_ba;
wire ctrl_cas_n;
wire [CS_NUM-1:0] ctrl_cs_n;
wire ctrl_ras_n;
wire ctrl_rden;
wire ctrl_ref_flag;
wire ctrl_we_n;
wire ctrl_wren;
wire [DQS_WIDTH-1:0] phy_calib_rden;
wire [DQS_WIDTH-1:0] phy_calib_rden_sel;
wire [DQ_WIDTH-1:0] rd_data_fall;
wire [DQ_WIDTH-1:0] rd_data_rise;
wire [(2*DQ_WIDTH)-1:0] wdf_data;
wire [((2*DQ_WIDTH)/8)-1:0] wdf_mask_data;
wire wdf_rden;
//***************************************************************************
ddr2_phy_top #
(
.BANK_WIDTH (BANK_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.CLK_WIDTH (CLK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_BITS (CS_BITS),
.CS_NUM (CS_NUM),
.CS_WIDTH (CS_WIDTH),
.USE_DM_PORT (USE_DM_PORT),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQ_BITS (DQ_BITS),
.DQ_PER_DQS (DQ_PER_DQS),
.DQS_BITS (DQS_BITS),
.DQS_WIDTH (DQS_WIDTH),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.IODELAY_GRP (IODELAY_GRP),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.TWO_T_TIME_EN (TWO_T_TIME_EN),
.ADDITIVE_LAT (ADDITIVE_LAT),
.BURST_LEN (BURST_LEN),
.BURST_TYPE (BURST_TYPE),
.CAS_LAT (CAS_LAT),
.ECC_ENABLE (ECC_ENABLE),
.ODT_TYPE (ODT_TYPE),
.DDR_TYPE (DDR_TYPE),
.REDUCE_DRV (REDUCE_DRV),
.REG_ENABLE (REG_ENABLE),
.TWR (TWR),
.CLK_PERIOD (CLK_PERIOD),
.SIM_ONLY (SIM_ONLY),
.DEBUG_EN (DEBUG_EN),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE)
)
u_phy_top
(
.clk0 (clk0),
.clk90 (clk90),
.clkdiv0 (clkdiv0),
.rst0 (rst0),
.rst90 (rst90),
.rstdiv0 (rstdiv0),
.ctrl_wren (ctrl_wren),
.ctrl_addr (ctrl_addr),
.ctrl_ba (ctrl_ba),
.ctrl_ras_n (ctrl_ras_n),
.ctrl_cas_n (ctrl_cas_n),
.ctrl_we_n (ctrl_we_n),
.ctrl_cs_n (ctrl_cs_n),
.ctrl_rden (ctrl_rden),
.ctrl_ref_flag (ctrl_ref_flag),
.wdf_data (wdf_data),
.wdf_mask_data (wdf_mask_data),
.wdf_rden (wdf_rden),
.phy_init_done (phy_init_done),
.phy_calib_rden (phy_calib_rden),
.phy_calib_rden_sel (phy_calib_rden_sel),
.rd_data_rise (rd_data_rise),
.rd_data_fall (rd_data_fall),
.ddr_ck (ddr_ck),
.ddr_ck_n (ddr_ck_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_ras_n (ddr_ras_n),
.ddr_cas_n (ddr_cas_n),
.ddr_we_n (ddr_we_n),
.ddr_cs_n (ddr_cs_n),
.ddr_cke (ddr_cke),
.ddr_odt (ddr_odt),
.ddr_dm (ddr_dm),
.ddr_dqs (ddr_dqs),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dq (ddr_dq),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_dq (dbg_idel_up_dq),
.dbg_idel_down_dq (dbg_idel_down_dq),
.dbg_idel_up_dqs (dbg_idel_up_dqs),
.dbg_idel_down_dqs (dbg_idel_down_dqs),
.dbg_idel_up_gate (dbg_idel_up_gate),
.dbg_idel_down_gate (dbg_idel_down_gate),
.dbg_sel_idel_dq (dbg_sel_idel_dq),
.dbg_sel_all_idel_dq (dbg_sel_all_idel_dq),
.dbg_sel_idel_dqs (dbg_sel_idel_dqs),
.dbg_sel_all_idel_dqs (dbg_sel_all_idel_dqs),
.dbg_sel_idel_gate (dbg_sel_idel_gate),
.dbg_sel_all_idel_gate (dbg_sel_all_idel_gate),
.dbg_calib_done (dbg_calib_done),
.dbg_calib_err (dbg_calib_err),
.dbg_calib_dq_tap_cnt (dbg_calib_dq_tap_cnt),
.dbg_calib_dqs_tap_cnt (dbg_calib_dqs_tap_cnt),
.dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
.dbg_calib_rd_data_sel (dbg_calib_rd_data_sel),
.dbg_calib_rden_dly (dbg_calib_rden_dly),
.dbg_calib_gate_dly (dbg_calib_gate_dly)
);
ddr2_usr_top #
(
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_BITS (CS_BITS),
.DQ_WIDTH (DQ_WIDTH),
.DQ_PER_DQS (DQ_PER_DQS),
.DQS_WIDTH (DQS_WIDTH),
.APPDATA_WIDTH (APPDATA_WIDTH),
.ECC_ENABLE (ECC_ENABLE),
.ROW_WIDTH (ROW_WIDTH)
)
u_usr_top
(
.clk0 (clk0),
.usr_clk (usr_clk), //jb
.clk90 (clk90),
.rst0 (rst0),
.rd_data_in_rise (rd_data_rise),
.rd_data_in_fall (rd_data_fall),
.phy_calib_rden (phy_calib_rden),
.phy_calib_rden_sel(phy_calib_rden_sel),
.rd_data_valid (rd_data_valid),
.rd_ecc_error (rd_ecc_error),
.rd_data_fifo_out (rd_data_fifo_out),
.app_af_cmd (app_af_cmd),
.app_af_addr (app_af_addr),
.app_af_wren (app_af_wren),
.ctrl_af_rden (ctrl_af_rden),
.af_cmd (af_cmd),
.af_addr (af_addr),
.af_empty (af_empty),
.app_af_afull (app_af_afull),
.app_wdf_wren (app_wdf_wren),
.app_wdf_data (app_wdf_data),
.app_wdf_mask_data (app_wdf_mask_data),
.wdf_rden (wdf_rden),
.app_wdf_afull (app_wdf_afull),
.wdf_data (wdf_data),
.wdf_mask_data (wdf_mask_data)
);
ddr2_ctrl #
(
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_BITS (CS_BITS),
.CS_NUM (CS_NUM),
.ROW_WIDTH (ROW_WIDTH),
.ADDITIVE_LAT (ADDITIVE_LAT),
.BURST_LEN (BURST_LEN),
.CAS_LAT (CAS_LAT),
.ECC_ENABLE (ECC_ENABLE),
.REG_ENABLE (REG_ENABLE),
.MULTI_BANK_EN (MULTI_BANK_EN),
.TWO_T_TIME_EN (TWO_T_TIME_EN),
.TREFI_NS (TREFI_NS),
.TRAS (TRAS),
.TRCD (TRCD),
.TRFC (TRFC),
.TRP (TRP),
.TRTP (TRTP),
.TWR (TWR),
.TWTR (TWTR),
.CLK_PERIOD (CLK_PERIOD),
.DDR_TYPE (DDR_TYPE)
)
u_ctrl
(
.clk (clk0),
.rst (rst0),
.af_cmd (af_cmd),
.af_addr (af_addr),
.af_empty (af_empty),
.phy_init_done (phy_init_done),
.ctrl_ref_flag (ctrl_ref_flag),
.ctrl_af_rden (ctrl_af_rden),
.ctrl_wren (ctrl_wren),
.ctrl_rden (ctrl_rden),
.ctrl_addr (ctrl_addr),
.ctrl_ba (ctrl_ba),
.ctrl_ras_n (ctrl_ras_n),
.ctrl_cas_n (ctrl_cas_n),
.ctrl_we_n (ctrl_we_n),
.ctrl_cs_n (ctrl_cs_n)
, .sp_refresh_disable(sp_refresh_disable)
);
endmodule
|
`timescale 1ns / 1ns
`define MOD_OSRAM
module tb_ArtyA7;
reg sim_end;
reg RST_N;
reg CLK;
wire uart_txd_in;
wire uart_rxd_out;
wire [3:0] led;
initial begin
sim_end = 1'b0;
RST_N = 1'b0;
CLK = 1'b0;
force u_ArtyA7.u_fmrv32im_artya7_wrapper.fmrv32im_artya7_i.High_dout = 1'b0;
/*
`ifdef MOD_OSRAM
force u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.u_fmrv32im_cache.i_base = 32'h2000_0000;
force u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.u_fmrv32im_cache.d_base = 32'h2000_0000;
`endif
*/
#100;
@(posedge CLK);
RST_N = 1'b1;
force u_ArtyA7.u_fmrv32im_artya7_wrapper.fmrv32im_artya7_i.High_dout = 1'b1;
/*
`ifdef MOD_OSRAM
release u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.u_fmrv32im_cache.i_base;
release u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.u_fmrv32im_cache.d_base;
`endif
*/
$display("============================================================");
$display("Simulatin Start");
$display("============================================================");
end
// Clock
localparam CLK100M = 10;
always begin
#(CLK100M/2) CLK <= ~CLK;
end
reg [31:0] rslt;
/*
always @(posedge CLK) begin
if((u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_wstb == 4'hF))
begin
rslt <= u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_wdata;
end
end
*/
// Sinario
initial begin
wait(CLK);
@(posedge CLK);
$display("============================================================");
$display("Process Start");
$display("============================================================");
/*
wait((u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_wstb == 4'hF));
*/
#(2000000);
u_task_uart.write("e");
u_task_uart.write("c");
u_task_uart.write("h");
u_task_uart.write("o");
u_task_uart.write("b");
u_task_uart.write("a");
u_task_uart.write("c");
u_task_uart.write("k");
u_task_uart.write("\r");
u_task_uart.write("\n");
wait(led==4'hF);
repeat(10) @(posedge CLK);
sim_end = 1;
end
integer iena_count;
initial begin
wait(sim_end);
$display("============================================================");
$display("Simulatin Finish");
$display("============================================================");
$display("Result: %8x", rslt);
$display("Inst Count: %d", iena_count);
$finish();
end
// initial $readmemh("../../../../src/imem.hex", u_fmrv32im_core.u_fmrv32im_cache.imem);
// initial $readmemh("../../../../src/imem.hex", u_fmrv32im_core.u_fmrv32im_cache.dmem);
ArtyA7
#(
.MEM_FILE ("../../../../src/imem.hex")
)
u_ArtyA7
(
.CLK100MHZ (CLK),
.uart_txd_in (uart_txd_in),
.uart_rxd_out (uart_rxd_out),
.led (led)
);
/*
always @(posedge CLK) begin
if(!RST_N) begin
iena_count <= 0;
end else begin
if(u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.ibus_ena) begin
iena_count <= iena_count +1;
end
end
end
*/
task_uart u_task_uart(
.tx(uart_txd_in),
.rx(uart_rxd_out)
);
endmodule // tb_fmrv32im_core
`timescale 1ns / 1ps
module task_uart(
tx,
rx
);
output tx;
input rx;
reg tx;
reg clk, clk2;
reg [7:0] rdata;
reg rx_valid;
wire [7:0] rx_char;
initial begin
clk <= 1'b0;
clk2 <= 1'b0;
tx <= 1'b1;
end
always begin
#(1000000000/115200/2) clk <= ~clk;
end
always begin
#(1000000000/115200/2/2) clk2 <= ~clk2;
end
task write;
input [7:0] data;
begin
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b0;
@(posedge clk);
tx <= data[0];
@(posedge clk);
tx <= data[1];
@(posedge clk);
tx <= data[2];
@(posedge clk);
tx <= data[3];
@(posedge clk);
tx <= data[4];
@(posedge clk);
tx <= data[5];
@(posedge clk);
tx <= data[6];
@(posedge clk);
tx <= data[7];
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
end
endtask
// Receive
always begin
rx_valid <= 0;
@(posedge clk2);
if(rx == 1'b0) begin
repeat (2) @(posedge clk2);
rdata[0] <= rx;
repeat (2) @(posedge clk2);
rdata[1] <= rx;
repeat (2) @(posedge clk2);
rdata[2] <= rx;
repeat (2) @(posedge clk2);
rdata[3] <= rx;
repeat (2) @(posedge clk2);
rdata[4] <= rx;
repeat (2) @(posedge clk2);
rdata[5] <= rx;
repeat (2) @(posedge clk2);
rdata[6] <= rx;
repeat (2) @(posedge clk2);
rdata[7] <= rx;
repeat (2) @(posedge clk2);
if(rx == 1'b1) begin
// $display("%s", rdata[7:0]);
rx_valid <= 1;
$write("%s", rdata[7:0]);
end
repeat (2) @(posedge clk2);
end
end
assign rx_char = (rx_valid)?rdata:8'd0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_PP_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sedfxtp (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_PP_V |
module omega_network_ff_tb;
parameter WIDTH = 8;
parameter IN_PORTS = 8;
parameter OUT_PORTS = IN_PORTS;
parameter ADDR_WIDTH_PORTS = log2(OUT_PORTS-1);
reg clk;
reg [0:IN_PORTS-1] push;
reg [IN_PORTS*WIDTH-1:0] d_in;
wire [0:OUT_PORTS-1] valid;
wire [OUT_PORTS*WIDTH-1:0] d_out;
reg [ADDR_WIDTH_PORTS-1:0] control;
omega_network_ff dut(clk, push, d_in, valid, d_out, control);
initial begin
clk = 0;
forever #5 clk=~clk;
end
reg rst;
integer i, j;
integer si;
reg [WIDTH-1:0] d_in_2d [0:IN_PORTS];
reg [WIDTH-1:0] d_out_2d [0:IN_PORTS];
always @* begin
for(i = 0; i < IN_PORTS; i = i + 1) begin
d_in[(i+1)*WIDTH-1 -: WIDTH] = d_in_2d[i];
d_out_2d[i] = d_out[(i+1)*WIDTH-1 -: WIDTH];
end
end
reg count_rst;
reg [ADDR_WIDTH_PORTS-1:0] count[0:2*ADDR_WIDTH_PORTS];
initial begin
push = 0;
rst = 1;
for(i = 0; i < IN_PORTS; i = i + 1) begin
d_in_2d[i] = i;
end
count_rst = 1;
//TODO: wait correct amount of time
#101 rst = 0;
push = -1;
#10 push = 0;
#1000 count_rst = 0;
#10 push = -1;
for(si = 0; si < IN_PORTS; si = si + 1) begin
$display("here");
#10;
end
push = 0;
#1000 $display("NO ERRORS");
$finish;
end
always @(posedge clk) begin
for(j = 0; j < ADDR_WIDTH_PORTS; j = j + 1) begin
control[ADDR_WIDTH_PORTS-j-1] = count[j*2][j];
end
end
always @(posedge clk) begin
if(!rst) begin
for(i = 0; i < IN_PORTS; i = i + 1) begin
if(valid[i]) begin
$display("port: %d data: %d", i, d_out_2d[i]);
end
end
end
end
always @(posedge clk) begin
if(count_rst)
count[0] <= 0;
else
count[0] <= count[0] + 1;
for(i = 0; i < 2*ADDR_WIDTH_PORTS; i = i + 1)
count[i+1] <= count[i];
end
`include "log2.vh"
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10/02/2016
// Design Name:
// Module Name: vga_noise
// Project Name:
// Target Devices:
// Tool versions:
// Description: generate 8-bit VGA output with the following effects:
//
// Colour test: vertical colour bars
// Monochrome test: vertical monochrome bars
// Colour noise: 8bpp random noise
// Monochrome noise: monochrome random noise
//
// Both noise effects can be 'paused' by resetting the LFSR seed on each vsync
//
// Dependencies: noise_generator.v
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga_noise(clk, color, pause, vsync, hsync, style, test, audio_l, audio_r);
input clk;
output [7:0] color;
input pause;
input vsync, hsync;
input style;
input test;
output audio_l, audio_r;
reg [1:0] audio_data;
reg [7:0] latch;
reg [7:0] sr;
reg [12:0] divider;
wire noise_bit;
noise_generator gen (
.clk(clk),
.reset(pause&vsync),// reset the LFSR on vsync to give 'paused' noise effect
.random_bit(noise_bit)
);
// handy line-synchronised counter
always @(negedge clk)
begin
if(hsync)
divider <= 0;
else
divider <= divider + 1;
end
// divider[2] is a clock at pixel frequency
always @(posedge divider[2])
begin
latch <= sr;// latch shift register each complete byte (every 8 clock cycles)
end
// audio noise can be at a much lower rate
always @(posedge divider[12])
begin
if(!test && !pause)// turn off sound when noise is 'paused'
begin
audio_data <= sr[1:0];
end
end
always @(posedge clk)
begin
if(style)// colour
begin
if(test)
begin
// display test pattern (colour vertical stripes)
sr <= {divider[9],divider[9],divider[9],divider[8],divider[8],divider[8],divider[7],divider[7]};
end
else
begin
// add noise bits to shift register (8-bit 'colour' noise)
sr[7:1] <= sr[6:0];
sr[0] <= noise_bit;
end
end
else // monochrome
begin
if(test)
begin
// display test pattern (monochrome vertical stripes)
sr <= {divider[5],divider[5],divider[5],divider[5],divider[5],divider[5],divider[5],divider[5]};
end
else
begin
// load shift register with current noise bit value (monochrome noise)
sr <= {noise_bit,noise_bit,noise_bit,noise_bit,noise_bit,noise_bit,noise_bit,noise_bit};
end
end
end
assign color = latch;
// stereo noise!
assign audio_l = audio_data[0];
assign audio_r = audio_data[1];
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_AsyncResetRegVec_129(
input clock,
input reset,
input [19:0] io_d,
output [19:0] io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
wire reg_1_rst;
wire reg_1_clk;
wire reg_1_en;
wire reg_1_q;
wire reg_1_d;
wire reg_2_rst;
wire reg_2_clk;
wire reg_2_en;
wire reg_2_q;
wire reg_2_d;
wire reg_3_rst;
wire reg_3_clk;
wire reg_3_en;
wire reg_3_q;
wire reg_3_d;
wire reg_4_rst;
wire reg_4_clk;
wire reg_4_en;
wire reg_4_q;
wire reg_4_d;
wire reg_5_rst;
wire reg_5_clk;
wire reg_5_en;
wire reg_5_q;
wire reg_5_d;
wire reg_6_rst;
wire reg_6_clk;
wire reg_6_en;
wire reg_6_q;
wire reg_6_d;
wire reg_7_rst;
wire reg_7_clk;
wire reg_7_en;
wire reg_7_q;
wire reg_7_d;
wire reg_8_rst;
wire reg_8_clk;
wire reg_8_en;
wire reg_8_q;
wire reg_8_d;
wire reg_9_rst;
wire reg_9_clk;
wire reg_9_en;
wire reg_9_q;
wire reg_9_d;
wire reg_10_rst;
wire reg_10_clk;
wire reg_10_en;
wire reg_10_q;
wire reg_10_d;
wire reg_11_rst;
wire reg_11_clk;
wire reg_11_en;
wire reg_11_q;
wire reg_11_d;
wire reg_12_rst;
wire reg_12_clk;
wire reg_12_en;
wire reg_12_q;
wire reg_12_d;
wire reg_13_rst;
wire reg_13_clk;
wire reg_13_en;
wire reg_13_q;
wire reg_13_d;
wire reg_14_rst;
wire reg_14_clk;
wire reg_14_en;
wire reg_14_q;
wire reg_14_d;
wire reg_15_rst;
wire reg_15_clk;
wire reg_15_en;
wire reg_15_q;
wire reg_15_d;
wire reg_16_rst;
wire reg_16_clk;
wire reg_16_en;
wire reg_16_q;
wire reg_16_d;
wire reg_17_rst;
wire reg_17_clk;
wire reg_17_en;
wire reg_17_q;
wire reg_17_d;
wire reg_18_rst;
wire reg_18_clk;
wire reg_18_en;
wire reg_18_q;
wire reg_18_d;
wire reg_19_rst;
wire reg_19_clk;
wire reg_19_en;
wire reg_19_q;
wire reg_19_d;
wire T_8;
wire T_9;
wire T_10;
wire T_11;
wire T_12;
wire T_13;
wire T_14;
wire T_15;
wire T_16;
wire T_17;
wire T_18;
wire T_19;
wire T_20;
wire T_21;
wire T_22;
wire T_23;
wire T_24;
wire T_25;
wire T_26;
wire T_27;
wire [1:0] T_28;
wire [1:0] T_29;
wire [2:0] T_30;
wire [4:0] T_31;
wire [1:0] T_32;
wire [1:0] T_33;
wire [2:0] T_34;
wire [4:0] T_35;
wire [9:0] T_36;
wire [1:0] T_37;
wire [1:0] T_38;
wire [2:0] T_39;
wire [4:0] T_40;
wire [1:0] T_41;
wire [1:0] T_42;
wire [2:0] T_43;
wire [4:0] T_44;
wire [9:0] T_45;
wire [19:0] T_46;
sirv_AsyncResetReg reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en(reg_0_en),
.q(reg_0_q),
.d(reg_0_d)
);
sirv_AsyncResetReg reg_1 (
.rst(reg_1_rst),
.clk(reg_1_clk),
.en(reg_1_en),
.q(reg_1_q),
.d(reg_1_d)
);
sirv_AsyncResetReg reg_2 (
.rst(reg_2_rst),
.clk(reg_2_clk),
.en(reg_2_en),
.q(reg_2_q),
.d(reg_2_d)
);
sirv_AsyncResetReg reg_3 (
.rst(reg_3_rst),
.clk(reg_3_clk),
.en(reg_3_en),
.q(reg_3_q),
.d(reg_3_d)
);
sirv_AsyncResetReg reg_4 (
.rst(reg_4_rst),
.clk(reg_4_clk),
.en(reg_4_en),
.q(reg_4_q),
.d(reg_4_d)
);
sirv_AsyncResetReg reg_5 (
.rst(reg_5_rst),
.clk(reg_5_clk),
.en(reg_5_en),
.q(reg_5_q),
.d(reg_5_d)
);
sirv_AsyncResetReg reg_6 (
.rst(reg_6_rst),
.clk(reg_6_clk),
.en(reg_6_en),
.q(reg_6_q),
.d(reg_6_d)
);
sirv_AsyncResetReg reg_7 (
.rst(reg_7_rst),
.clk(reg_7_clk),
.en(reg_7_en),
.q(reg_7_q),
.d(reg_7_d)
);
sirv_AsyncResetReg reg_8 (
.rst(reg_8_rst),
.clk(reg_8_clk),
.en(reg_8_en),
.q(reg_8_q),
.d(reg_8_d)
);
sirv_AsyncResetReg reg_9 (
.rst(reg_9_rst),
.clk(reg_9_clk),
.en(reg_9_en),
.q(reg_9_q),
.d(reg_9_d)
);
sirv_AsyncResetReg reg_10 (
.rst(reg_10_rst),
.clk(reg_10_clk),
.en(reg_10_en),
.q(reg_10_q),
.d(reg_10_d)
);
sirv_AsyncResetReg reg_11 (
.rst(reg_11_rst),
.clk(reg_11_clk),
.en(reg_11_en),
.q(reg_11_q),
.d(reg_11_d)
);
sirv_AsyncResetReg reg_12 (
.rst(reg_12_rst),
.clk(reg_12_clk),
.en(reg_12_en),
.q(reg_12_q),
.d(reg_12_d)
);
sirv_AsyncResetReg reg_13 (
.rst(reg_13_rst),
.clk(reg_13_clk),
.en(reg_13_en),
.q(reg_13_q),
.d(reg_13_d)
);
sirv_AsyncResetReg reg_14 (
.rst(reg_14_rst),
.clk(reg_14_clk),
.en(reg_14_en),
.q(reg_14_q),
.d(reg_14_d)
);
sirv_AsyncResetReg reg_15 (
.rst(reg_15_rst),
.clk(reg_15_clk),
.en(reg_15_en),
.q(reg_15_q),
.d(reg_15_d)
);
sirv_AsyncResetReg reg_16 (
.rst(reg_16_rst),
.clk(reg_16_clk),
.en(reg_16_en),
.q(reg_16_q),
.d(reg_16_d)
);
sirv_AsyncResetReg reg_17 (
.rst(reg_17_rst),
.clk(reg_17_clk),
.en(reg_17_en),
.q(reg_17_q),
.d(reg_17_d)
);
sirv_AsyncResetReg reg_18 (
.rst(reg_18_rst),
.clk(reg_18_clk),
.en(reg_18_en),
.q(reg_18_q),
.d(reg_18_d)
);
sirv_AsyncResetReg reg_19 (
.rst(reg_19_rst),
.clk(reg_19_clk),
.en(reg_19_en),
.q(reg_19_q),
.d(reg_19_d)
);
assign io_q = T_46;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = io_en;
assign reg_0_d = T_8;
assign reg_1_rst = reset;
assign reg_1_clk = clock;
assign reg_1_en = io_en;
assign reg_1_d = T_9;
assign reg_2_rst = reset;
assign reg_2_clk = clock;
assign reg_2_en = io_en;
assign reg_2_d = T_10;
assign reg_3_rst = reset;
assign reg_3_clk = clock;
assign reg_3_en = io_en;
assign reg_3_d = T_11;
assign reg_4_rst = reset;
assign reg_4_clk = clock;
assign reg_4_en = io_en;
assign reg_4_d = T_12;
assign reg_5_rst = reset;
assign reg_5_clk = clock;
assign reg_5_en = io_en;
assign reg_5_d = T_13;
assign reg_6_rst = reset;
assign reg_6_clk = clock;
assign reg_6_en = io_en;
assign reg_6_d = T_14;
assign reg_7_rst = reset;
assign reg_7_clk = clock;
assign reg_7_en = io_en;
assign reg_7_d = T_15;
assign reg_8_rst = reset;
assign reg_8_clk = clock;
assign reg_8_en = io_en;
assign reg_8_d = T_16;
assign reg_9_rst = reset;
assign reg_9_clk = clock;
assign reg_9_en = io_en;
assign reg_9_d = T_17;
assign reg_10_rst = reset;
assign reg_10_clk = clock;
assign reg_10_en = io_en;
assign reg_10_d = T_18;
assign reg_11_rst = reset;
assign reg_11_clk = clock;
assign reg_11_en = io_en;
assign reg_11_d = T_19;
assign reg_12_rst = reset;
assign reg_12_clk = clock;
assign reg_12_en = io_en;
assign reg_12_d = T_20;
assign reg_13_rst = reset;
assign reg_13_clk = clock;
assign reg_13_en = io_en;
assign reg_13_d = T_21;
assign reg_14_rst = reset;
assign reg_14_clk = clock;
assign reg_14_en = io_en;
assign reg_14_d = T_22;
assign reg_15_rst = reset;
assign reg_15_clk = clock;
assign reg_15_en = io_en;
assign reg_15_d = T_23;
assign reg_16_rst = reset;
assign reg_16_clk = clock;
assign reg_16_en = io_en;
assign reg_16_d = T_24;
assign reg_17_rst = reset;
assign reg_17_clk = clock;
assign reg_17_en = io_en;
assign reg_17_d = T_25;
assign reg_18_rst = reset;
assign reg_18_clk = clock;
assign reg_18_en = io_en;
assign reg_18_d = T_26;
assign reg_19_rst = reset;
assign reg_19_clk = clock;
assign reg_19_en = io_en;
assign reg_19_d = T_27;
assign T_8 = io_d[0];
assign T_9 = io_d[1];
assign T_10 = io_d[2];
assign T_11 = io_d[3];
assign T_12 = io_d[4];
assign T_13 = io_d[5];
assign T_14 = io_d[6];
assign T_15 = io_d[7];
assign T_16 = io_d[8];
assign T_17 = io_d[9];
assign T_18 = io_d[10];
assign T_19 = io_d[11];
assign T_20 = io_d[12];
assign T_21 = io_d[13];
assign T_22 = io_d[14];
assign T_23 = io_d[15];
assign T_24 = io_d[16];
assign T_25 = io_d[17];
assign T_26 = io_d[18];
assign T_27 = io_d[19];
assign T_28 = {reg_1_q,reg_0_q};
assign T_29 = {reg_4_q,reg_3_q};
assign T_30 = {T_29,reg_2_q};
assign T_31 = {T_30,T_28};
assign T_32 = {reg_6_q,reg_5_q};
assign T_33 = {reg_9_q,reg_8_q};
assign T_34 = {T_33,reg_7_q};
assign T_35 = {T_34,T_32};
assign T_36 = {T_35,T_31};
assign T_37 = {reg_11_q,reg_10_q};
assign T_38 = {reg_14_q,reg_13_q};
assign T_39 = {T_38,reg_12_q};
assign T_40 = {T_39,T_37};
assign T_41 = {reg_16_q,reg_15_q};
assign T_42 = {reg_19_q,reg_18_q};
assign T_43 = {T_42,reg_17_q};
assign T_44 = {T_43,T_41};
assign T_45 = {T_44,T_40};
assign T_46 = {T_45,T_36};
endmodule
|
// SoC.v
// Generated using ACDS version 13.0sp1 232 at 2014.12.04.09:58:03
`timescale 1 ps / 1 ps
module SoC (
input wire clk_clk, // clk.clk
input wire reset_reset_n // reset.reset_n
);
wire nios_data_master_waitrequest; // NIOS_data_master_translator:av_waitrequest -> NIOS:d_waitrequest
wire [31:0] nios_data_master_writedata; // NIOS:d_writedata -> NIOS_data_master_translator:av_writedata
wire [18:0] nios_data_master_address; // NIOS:d_address -> NIOS_data_master_translator:av_address
wire nios_data_master_write; // NIOS:d_write -> NIOS_data_master_translator:av_write
wire nios_data_master_read; // NIOS:d_read -> NIOS_data_master_translator:av_read
wire [31:0] nios_data_master_readdata; // NIOS_data_master_translator:av_readdata -> NIOS:d_readdata
wire nios_data_master_debugaccess; // NIOS:jtag_debug_module_debugaccess_to_roms -> NIOS_data_master_translator:av_debugaccess
wire [3:0] nios_data_master_byteenable; // NIOS:d_byteenable -> NIOS_data_master_translator:av_byteenable
wire nios_instruction_master_waitrequest; // NIOS_instruction_master_translator:av_waitrequest -> NIOS:i_waitrequest
wire [18:0] nios_instruction_master_address; // NIOS:i_address -> NIOS_instruction_master_translator:av_address
wire nios_instruction_master_read; // NIOS:i_read -> NIOS_instruction_master_translator:av_read
wire [31:0] nios_instruction_master_readdata; // NIOS_instruction_master_translator:av_readdata -> NIOS:i_readdata
wire nios_instruction_master_readdatavalid; // NIOS_instruction_master_translator:av_readdatavalid -> NIOS:i_readdatavalid
wire [31:0] ram_s1_translator_avalon_anti_slave_0_writedata; // RAM_s1_translator:av_writedata -> RAM:writedata
wire [14:0] ram_s1_translator_avalon_anti_slave_0_address; // RAM_s1_translator:av_address -> RAM:address
wire ram_s1_translator_avalon_anti_slave_0_chipselect; // RAM_s1_translator:av_chipselect -> RAM:chipselect
wire ram_s1_translator_avalon_anti_slave_0_clken; // RAM_s1_translator:av_clken -> RAM:clken
wire ram_s1_translator_avalon_anti_slave_0_write; // RAM_s1_translator:av_write -> RAM:write
wire [31:0] ram_s1_translator_avalon_anti_slave_0_readdata; // RAM:readdata -> RAM_s1_translator:av_readdata
wire [3:0] ram_s1_translator_avalon_anti_slave_0_byteenable; // RAM_s1_translator:av_byteenable -> RAM:byteenable
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest; // jtag_uart_0:av_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator:av_waitrequest
wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata; // jtag_uart_0_avalon_jtag_slave_translator:av_writedata -> jtag_uart_0:av_writedata
wire [0:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address; // jtag_uart_0_avalon_jtag_slave_translator:av_address -> jtag_uart_0:av_address
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect; // jtag_uart_0_avalon_jtag_slave_translator:av_chipselect -> jtag_uart_0:av_chipselect
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write; // jtag_uart_0_avalon_jtag_slave_translator:av_write -> jtag_uart_0:av_write_n
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read; // jtag_uart_0_avalon_jtag_slave_translator:av_read -> jtag_uart_0:av_read_n
wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata; // jtag_uart_0:av_readdata -> jtag_uart_0_avalon_jtag_slave_translator:av_readdata
wire [0:0] sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address; // sysid_qsys_0_control_slave_translator:av_address -> sysid_qsys_0:address
wire [31:0] sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata; // sysid_qsys_0:readdata -> sysid_qsys_0_control_slave_translator:av_readdata
wire nios_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest; // NIOS:jtag_debug_module_waitrequest -> NIOS_jtag_debug_module_translator:av_waitrequest
wire [31:0] nios_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // NIOS_jtag_debug_module_translator:av_writedata -> NIOS:jtag_debug_module_writedata
wire [8:0] nios_jtag_debug_module_translator_avalon_anti_slave_0_address; // NIOS_jtag_debug_module_translator:av_address -> NIOS:jtag_debug_module_address
wire nios_jtag_debug_module_translator_avalon_anti_slave_0_write; // NIOS_jtag_debug_module_translator:av_write -> NIOS:jtag_debug_module_write
wire nios_jtag_debug_module_translator_avalon_anti_slave_0_read; // NIOS_jtag_debug_module_translator:av_read -> NIOS:jtag_debug_module_read
wire [31:0] nios_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // NIOS:jtag_debug_module_readdata -> NIOS_jtag_debug_module_translator:av_readdata
wire nios_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // NIOS_jtag_debug_module_translator:av_debugaccess -> NIOS:jtag_debug_module_debugaccess
wire [3:0] nios_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // NIOS_jtag_debug_module_translator:av_byteenable -> NIOS:jtag_debug_module_byteenable
wire [31:0] hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata; // hw_ann_0_avalon_slave_0_translator:av_writedata -> hw_ann_0:writedata
wire [8:0] hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_address; // hw_ann_0_avalon_slave_0_translator:av_address -> hw_ann_0:address
wire hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_write; // hw_ann_0_avalon_slave_0_translator:av_write -> hw_ann_0:write
wire hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_read; // hw_ann_0_avalon_slave_0_translator:av_read -> hw_ann_0:read
wire [31:0] hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata; // hw_ann_0:readdata -> hw_ann_0_avalon_slave_0_translator:av_readdata
wire lfsr_0_avalon_slave_0_translator_avalon_anti_slave_0_read; // lfsr_0_avalon_slave_0_translator:av_read -> lfsr_0:read
wire [31:0] lfsr_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata; // lfsr_0:read_data -> lfsr_0_avalon_slave_0_translator:av_readdata
wire nios_data_master_translator_avalon_universal_master_0_waitrequest; // NIOS_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> NIOS_data_master_translator:uav_waitrequest
wire [2:0] nios_data_master_translator_avalon_universal_master_0_burstcount; // NIOS_data_master_translator:uav_burstcount -> NIOS_data_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] nios_data_master_translator_avalon_universal_master_0_writedata; // NIOS_data_master_translator:uav_writedata -> NIOS_data_master_translator_avalon_universal_master_0_agent:av_writedata
wire [18:0] nios_data_master_translator_avalon_universal_master_0_address; // NIOS_data_master_translator:uav_address -> NIOS_data_master_translator_avalon_universal_master_0_agent:av_address
wire nios_data_master_translator_avalon_universal_master_0_lock; // NIOS_data_master_translator:uav_lock -> NIOS_data_master_translator_avalon_universal_master_0_agent:av_lock
wire nios_data_master_translator_avalon_universal_master_0_write; // NIOS_data_master_translator:uav_write -> NIOS_data_master_translator_avalon_universal_master_0_agent:av_write
wire nios_data_master_translator_avalon_universal_master_0_read; // NIOS_data_master_translator:uav_read -> NIOS_data_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] nios_data_master_translator_avalon_universal_master_0_readdata; // NIOS_data_master_translator_avalon_universal_master_0_agent:av_readdata -> NIOS_data_master_translator:uav_readdata
wire nios_data_master_translator_avalon_universal_master_0_debugaccess; // NIOS_data_master_translator:uav_debugaccess -> NIOS_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] nios_data_master_translator_avalon_universal_master_0_byteenable; // NIOS_data_master_translator:uav_byteenable -> NIOS_data_master_translator_avalon_universal_master_0_agent:av_byteenable
wire nios_data_master_translator_avalon_universal_master_0_readdatavalid; // NIOS_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> NIOS_data_master_translator:uav_readdatavalid
wire nios_instruction_master_translator_avalon_universal_master_0_waitrequest; // NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> NIOS_instruction_master_translator:uav_waitrequest
wire [2:0] nios_instruction_master_translator_avalon_universal_master_0_burstcount; // NIOS_instruction_master_translator:uav_burstcount -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] nios_instruction_master_translator_avalon_universal_master_0_writedata; // NIOS_instruction_master_translator:uav_writedata -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
wire [18:0] nios_instruction_master_translator_avalon_universal_master_0_address; // NIOS_instruction_master_translator:uav_address -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_address
wire nios_instruction_master_translator_avalon_universal_master_0_lock; // NIOS_instruction_master_translator:uav_lock -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_lock
wire nios_instruction_master_translator_avalon_universal_master_0_write; // NIOS_instruction_master_translator:uav_write -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_write
wire nios_instruction_master_translator_avalon_universal_master_0_read; // NIOS_instruction_master_translator:uav_read -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] nios_instruction_master_translator_avalon_universal_master_0_readdata; // NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> NIOS_instruction_master_translator:uav_readdata
wire nios_instruction_master_translator_avalon_universal_master_0_debugaccess; // NIOS_instruction_master_translator:uav_debugaccess -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] nios_instruction_master_translator_avalon_universal_master_0_byteenable; // NIOS_instruction_master_translator:uav_byteenable -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
wire nios_instruction_master_translator_avalon_universal_master_0_readdatavalid; // NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> NIOS_instruction_master_translator:uav_readdatavalid
wire ram_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // RAM_s1_translator:uav_waitrequest -> RAM_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] ram_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // RAM_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> RAM_s1_translator:uav_burstcount
wire [31:0] ram_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // RAM_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> RAM_s1_translator:uav_writedata
wire [18:0] ram_s1_translator_avalon_universal_slave_0_agent_m0_address; // RAM_s1_translator_avalon_universal_slave_0_agent:m0_address -> RAM_s1_translator:uav_address
wire ram_s1_translator_avalon_universal_slave_0_agent_m0_write; // RAM_s1_translator_avalon_universal_slave_0_agent:m0_write -> RAM_s1_translator:uav_write
wire ram_s1_translator_avalon_universal_slave_0_agent_m0_lock; // RAM_s1_translator_avalon_universal_slave_0_agent:m0_lock -> RAM_s1_translator:uav_lock
wire ram_s1_translator_avalon_universal_slave_0_agent_m0_read; // RAM_s1_translator_avalon_universal_slave_0_agent:m0_read -> RAM_s1_translator:uav_read
wire [31:0] ram_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // RAM_s1_translator:uav_readdata -> RAM_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire ram_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // RAM_s1_translator:uav_readdatavalid -> RAM_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire ram_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // RAM_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> RAM_s1_translator:uav_debugaccess
wire [3:0] ram_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // RAM_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> RAM_s1_translator:uav_byteenable
wire ram_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // RAM_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire ram_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // RAM_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire ram_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // RAM_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [92:0] ram_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // RAM_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire ram_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> RAM_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> RAM_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> RAM_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> RAM_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [92:0] ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> RAM_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // RAM_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // RAM_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> RAM_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // RAM_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> RAM_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // RAM_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> RAM_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // jtag_uart_0_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_0_avalon_jtag_slave_translator:uav_burstcount
wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_0_avalon_jtag_slave_translator:uav_writedata
wire [18:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_0_avalon_jtag_slave_translator:uav_address
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_0_avalon_jtag_slave_translator:uav_write
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_0_avalon_jtag_slave_translator:uav_lock
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_0_avalon_jtag_slave_translator:uav_read
wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_0_avalon_jtag_slave_translator:uav_debugaccess
wire [3:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_0_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [92:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [92:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sysid_qsys_0_control_slave_translator:uav_waitrequest -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sysid_qsys_0_control_slave_translator:uav_burstcount
wire [31:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sysid_qsys_0_control_slave_translator:uav_writedata
wire [18:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> sysid_qsys_0_control_slave_translator:uav_address
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> sysid_qsys_0_control_slave_translator:uav_write
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sysid_qsys_0_control_slave_translator:uav_lock
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> sysid_qsys_0_control_slave_translator:uav_read
wire [31:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // sysid_qsys_0_control_slave_translator:uav_readdata -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sysid_qsys_0_control_slave_translator:uav_readdatavalid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sysid_qsys_0_control_slave_translator:uav_debugaccess
wire [3:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sysid_qsys_0_control_slave_translator:uav_byteenable
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [92:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [92:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // NIOS_jtag_debug_module_translator:uav_waitrequest -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> NIOS_jtag_debug_module_translator:uav_burstcount
wire [31:0] nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> NIOS_jtag_debug_module_translator:uav_writedata
wire [18:0] nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> NIOS_jtag_debug_module_translator:uav_address
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> NIOS_jtag_debug_module_translator:uav_write
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> NIOS_jtag_debug_module_translator:uav_lock
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> NIOS_jtag_debug_module_translator:uav_read
wire [31:0] nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // NIOS_jtag_debug_module_translator:uav_readdata -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // NIOS_jtag_debug_module_translator:uav_readdatavalid -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> NIOS_jtag_debug_module_translator:uav_debugaccess
wire [3:0] nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> NIOS_jtag_debug_module_translator:uav_byteenable
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [92:0] nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [92:0] nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hw_ann_0_avalon_slave_0_translator:uav_waitrequest -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> hw_ann_0_avalon_slave_0_translator:uav_burstcount
wire [31:0] hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> hw_ann_0_avalon_slave_0_translator:uav_writedata
wire [18:0] hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> hw_ann_0_avalon_slave_0_translator:uav_address
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> hw_ann_0_avalon_slave_0_translator:uav_write
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> hw_ann_0_avalon_slave_0_translator:uav_lock
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> hw_ann_0_avalon_slave_0_translator:uav_read
wire [31:0] hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata; // hw_ann_0_avalon_slave_0_translator:uav_readdata -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hw_ann_0_avalon_slave_0_translator:uav_readdatavalid -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hw_ann_0_avalon_slave_0_translator:uav_debugaccess
wire [3:0] hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> hw_ann_0_avalon_slave_0_translator:uav_byteenable
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [92:0] hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [92:0] hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lfsr_0_avalon_slave_0_translator:uav_waitrequest -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> lfsr_0_avalon_slave_0_translator:uav_burstcount
wire [31:0] lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> lfsr_0_avalon_slave_0_translator:uav_writedata
wire [18:0] lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> lfsr_0_avalon_slave_0_translator:uav_address
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> lfsr_0_avalon_slave_0_translator:uav_write
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> lfsr_0_avalon_slave_0_translator:uav_lock
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> lfsr_0_avalon_slave_0_translator:uav_read
wire [31:0] lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata; // lfsr_0_avalon_slave_0_translator:uav_readdata -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lfsr_0_avalon_slave_0_translator:uav_readdatavalid -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lfsr_0_avalon_slave_0_translator:uav_debugaccess
wire [3:0] lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> lfsr_0_avalon_slave_0_translator:uav_byteenable
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [92:0] lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [92:0] lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire nios_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // NIOS_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
wire nios_data_master_translator_avalon_universal_master_0_agent_cp_valid; // NIOS_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
wire nios_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // NIOS_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
wire [91:0] nios_data_master_translator_avalon_universal_master_0_agent_cp_data; // NIOS_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
wire nios_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> NIOS_data_master_translator_avalon_universal_master_0_agent:cp_ready
wire nios_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // NIOS_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
wire nios_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // NIOS_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
wire nios_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // NIOS_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
wire [91:0] nios_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // NIOS_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
wire nios_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
wire ram_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // RAM_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire ram_s1_translator_avalon_universal_slave_0_agent_rp_valid; // RAM_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire ram_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // RAM_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [91:0] ram_s1_translator_avalon_universal_slave_0_agent_rp_data; // RAM_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire ram_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> RAM_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
wire [91:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
wire [91:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
wire [91:0] nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
wire [91:0] hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
wire [91:0] lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> limiter:cmd_sink_endofpacket
wire addr_router_001_src_valid; // addr_router_001:src_valid -> limiter:cmd_sink_valid
wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> limiter:cmd_sink_startofpacket
wire [91:0] addr_router_001_src_data; // addr_router_001:src_data -> limiter:cmd_sink_data
wire [5:0] addr_router_001_src_channel; // addr_router_001:src_channel -> limiter:cmd_sink_channel
wire addr_router_001_src_ready; // limiter:cmd_sink_ready -> addr_router_001:src_ready
wire limiter_rsp_src_endofpacket; // limiter:rsp_src_endofpacket -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire limiter_rsp_src_valid; // limiter:rsp_src_valid -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
wire limiter_rsp_src_startofpacket; // limiter:rsp_src_startofpacket -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [91:0] limiter_rsp_src_data; // limiter:rsp_src_data -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:rp_data
wire [5:0] limiter_rsp_src_channel; // limiter:rsp_src_channel -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
wire limiter_rsp_src_ready; // NIOS_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [NIOS:reset_n, NIOS_data_master_translator:reset, NIOS_data_master_translator_avalon_universal_master_0_agent:reset, NIOS_instruction_master_translator:reset, NIOS_instruction_master_translator_avalon_universal_master_0_agent:reset, NIOS_jtag_debug_module_translator:reset, NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, RAM:reset, RAM_s1_translator:reset, RAM_s1_translator_avalon_universal_slave_0_agent:reset, RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, addr_router:reset, addr_router_001:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_003:reset, cmd_xbar_mux_004:reset, cmd_xbar_mux_005:reset, hw_ann_0:MasterReset, hw_ann_0_avalon_slave_0_translator:reset, hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, irq_mapper:reset, jtag_uart_0:rst_n, jtag_uart_0_avalon_jtag_slave_translator:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lfsr_0:rst, lfsr_0_avalon_slave_0_translator:reset, lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, limiter:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, sysid_qsys_0:reset_n, sysid_qsys_0_control_slave_translator:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> RAM:reset_req
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
wire [91:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
wire [5:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [91:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src2_endofpacket; // cmd_xbar_demux:src2_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_src2_valid; // cmd_xbar_demux:src2_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_src2_startofpacket; // cmd_xbar_demux:src2_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [91:0] cmd_xbar_demux_src2_data; // cmd_xbar_demux:src2_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_demux_src2_channel; // cmd_xbar_demux:src2_channel -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src3_endofpacket; // cmd_xbar_demux:src3_endofpacket -> cmd_xbar_mux_003:sink0_endofpacket
wire cmd_xbar_demux_src3_valid; // cmd_xbar_demux:src3_valid -> cmd_xbar_mux_003:sink0_valid
wire cmd_xbar_demux_src3_startofpacket; // cmd_xbar_demux:src3_startofpacket -> cmd_xbar_mux_003:sink0_startofpacket
wire [91:0] cmd_xbar_demux_src3_data; // cmd_xbar_demux:src3_data -> cmd_xbar_mux_003:sink0_data
wire [5:0] cmd_xbar_demux_src3_channel; // cmd_xbar_demux:src3_channel -> cmd_xbar_mux_003:sink0_channel
wire cmd_xbar_demux_src3_ready; // cmd_xbar_mux_003:sink0_ready -> cmd_xbar_demux:src3_ready
wire cmd_xbar_demux_src4_endofpacket; // cmd_xbar_demux:src4_endofpacket -> cmd_xbar_mux_004:sink0_endofpacket
wire cmd_xbar_demux_src4_valid; // cmd_xbar_demux:src4_valid -> cmd_xbar_mux_004:sink0_valid
wire cmd_xbar_demux_src4_startofpacket; // cmd_xbar_demux:src4_startofpacket -> cmd_xbar_mux_004:sink0_startofpacket
wire [91:0] cmd_xbar_demux_src4_data; // cmd_xbar_demux:src4_data -> cmd_xbar_mux_004:sink0_data
wire [5:0] cmd_xbar_demux_src4_channel; // cmd_xbar_demux:src4_channel -> cmd_xbar_mux_004:sink0_channel
wire cmd_xbar_demux_src4_ready; // cmd_xbar_mux_004:sink0_ready -> cmd_xbar_demux:src4_ready
wire cmd_xbar_demux_src5_endofpacket; // cmd_xbar_demux:src5_endofpacket -> cmd_xbar_mux_005:sink0_endofpacket
wire cmd_xbar_demux_src5_valid; // cmd_xbar_demux:src5_valid -> cmd_xbar_mux_005:sink0_valid
wire cmd_xbar_demux_src5_startofpacket; // cmd_xbar_demux:src5_startofpacket -> cmd_xbar_mux_005:sink0_startofpacket
wire [91:0] cmd_xbar_demux_src5_data; // cmd_xbar_demux:src5_data -> cmd_xbar_mux_005:sink0_data
wire [5:0] cmd_xbar_demux_src5_channel; // cmd_xbar_demux:src5_channel -> cmd_xbar_mux_005:sink0_channel
wire cmd_xbar_demux_src5_ready; // cmd_xbar_mux_005:sink0_ready -> cmd_xbar_demux:src5_ready
wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
wire [91:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
wire [5:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_003:sink1_endofpacket
wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_003:sink1_valid
wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_003:sink1_startofpacket
wire [91:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_003:sink1_data
wire [5:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_003:sink1_channel
wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_003:sink1_ready -> cmd_xbar_demux_001:src1_ready
wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> cmd_xbar_mux_004:sink1_endofpacket
wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> cmd_xbar_mux_004:sink1_valid
wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> cmd_xbar_mux_004:sink1_startofpacket
wire [91:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> cmd_xbar_mux_004:sink1_data
wire [5:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> cmd_xbar_mux_004:sink1_channel
wire cmd_xbar_demux_001_src2_ready; // cmd_xbar_mux_004:sink1_ready -> cmd_xbar_demux_001:src2_ready
wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> cmd_xbar_mux_005:sink1_endofpacket
wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> cmd_xbar_mux_005:sink1_valid
wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> cmd_xbar_mux_005:sink1_startofpacket
wire [91:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> cmd_xbar_mux_005:sink1_data
wire [5:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> cmd_xbar_mux_005:sink1_channel
wire cmd_xbar_demux_001_src3_ready; // cmd_xbar_mux_005:sink1_ready -> cmd_xbar_demux_001:src3_ready
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [91:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
wire [5:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
wire [91:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
wire [5:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
wire [91:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
wire [5:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket
wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid
wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket
wire [91:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data
wire [5:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel
wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready
wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux:sink3_endofpacket
wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux:sink3_valid
wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux:sink3_startofpacket
wire [91:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux:sink3_data
wire [5:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux:sink3_channel
wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux:sink3_ready -> rsp_xbar_demux_003:src0_ready
wire rsp_xbar_demux_003_src1_endofpacket; // rsp_xbar_demux_003:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
wire rsp_xbar_demux_003_src1_valid; // rsp_xbar_demux_003:src1_valid -> rsp_xbar_mux_001:sink1_valid
wire rsp_xbar_demux_003_src1_startofpacket; // rsp_xbar_demux_003:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
wire [91:0] rsp_xbar_demux_003_src1_data; // rsp_xbar_demux_003:src1_data -> rsp_xbar_mux_001:sink1_data
wire [5:0] rsp_xbar_demux_003_src1_channel; // rsp_xbar_demux_003:src1_channel -> rsp_xbar_mux_001:sink1_channel
wire rsp_xbar_demux_003_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_003:src1_ready
wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux:sink4_endofpacket
wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux:sink4_valid
wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux:sink4_startofpacket
wire [91:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux:sink4_data
wire [5:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux:sink4_channel
wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux:sink4_ready -> rsp_xbar_demux_004:src0_ready
wire rsp_xbar_demux_004_src1_endofpacket; // rsp_xbar_demux_004:src1_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
wire rsp_xbar_demux_004_src1_valid; // rsp_xbar_demux_004:src1_valid -> rsp_xbar_mux_001:sink2_valid
wire rsp_xbar_demux_004_src1_startofpacket; // rsp_xbar_demux_004:src1_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
wire [91:0] rsp_xbar_demux_004_src1_data; // rsp_xbar_demux_004:src1_data -> rsp_xbar_mux_001:sink2_data
wire [5:0] rsp_xbar_demux_004_src1_channel; // rsp_xbar_demux_004:src1_channel -> rsp_xbar_mux_001:sink2_channel
wire rsp_xbar_demux_004_src1_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_004:src1_ready
wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux:sink5_endofpacket
wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux:sink5_valid
wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux:sink5_startofpacket
wire [91:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux:sink5_data
wire [5:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux:sink5_channel
wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux:sink5_ready -> rsp_xbar_demux_005:src0_ready
wire rsp_xbar_demux_005_src1_endofpacket; // rsp_xbar_demux_005:src1_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
wire rsp_xbar_demux_005_src1_valid; // rsp_xbar_demux_005:src1_valid -> rsp_xbar_mux_001:sink3_valid
wire rsp_xbar_demux_005_src1_startofpacket; // rsp_xbar_demux_005:src1_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
wire [91:0] rsp_xbar_demux_005_src1_data; // rsp_xbar_demux_005:src1_data -> rsp_xbar_mux_001:sink3_data
wire [5:0] rsp_xbar_demux_005_src1_channel; // rsp_xbar_demux_005:src1_channel -> rsp_xbar_mux_001:sink3_channel
wire rsp_xbar_demux_005_src1_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_005:src1_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> cmd_xbar_demux:sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [91:0] addr_router_src_data; // addr_router:src_data -> cmd_xbar_demux:sink_data
wire [5:0] addr_router_src_channel; // addr_router:src_channel -> cmd_xbar_demux:sink_channel
wire addr_router_src_ready; // cmd_xbar_demux:sink_ready -> addr_router:src_ready
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> NIOS_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> NIOS_data_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> NIOS_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [91:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> NIOS_data_master_translator_avalon_universal_master_0_agent:rp_data
wire [5:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> NIOS_data_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_mux_src_ready; // NIOS_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready
wire limiter_cmd_src_endofpacket; // limiter:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
wire limiter_cmd_src_startofpacket; // limiter:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
wire [91:0] limiter_cmd_src_data; // limiter:cmd_src_data -> cmd_xbar_demux_001:sink_data
wire [5:0] limiter_cmd_src_channel; // limiter:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
wire limiter_cmd_src_ready; // cmd_xbar_demux_001:sink_ready -> limiter:cmd_src_ready
wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> limiter:rsp_sink_endofpacket
wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> limiter:rsp_sink_valid
wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> limiter:rsp_sink_startofpacket
wire [91:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> limiter:rsp_sink_data
wire [5:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> limiter:rsp_sink_channel
wire rsp_xbar_mux_001_src_ready; // limiter:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> RAM_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> RAM_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> RAM_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [91:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> RAM_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> RAM_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_src_ready; // RAM_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [91:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data
wire [5:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel
wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready
wire cmd_xbar_demux_src1_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src1_ready
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
wire [91:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
wire [5:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
wire cmd_xbar_demux_src2_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src2_ready
wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
wire [91:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
wire [5:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
wire cmd_xbar_mux_003_src_endofpacket; // cmd_xbar_mux_003:src_endofpacket -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_003_src_valid; // cmd_xbar_mux_003:src_valid -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_003_src_startofpacket; // cmd_xbar_mux_003:src_startofpacket -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [91:0] cmd_xbar_mux_003_src_data; // cmd_xbar_mux_003:src_data -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_mux_003_src_channel; // cmd_xbar_mux_003:src_channel -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_003_src_ready; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_003:src_ready
wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
wire [91:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data
wire [5:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
wire cmd_xbar_mux_004_src_endofpacket; // cmd_xbar_mux_004:src_endofpacket -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_004_src_valid; // cmd_xbar_mux_004:src_valid -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_004_src_startofpacket; // cmd_xbar_mux_004:src_startofpacket -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [91:0] cmd_xbar_mux_004_src_data; // cmd_xbar_mux_004:src_data -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_mux_004_src_channel; // cmd_xbar_mux_004:src_channel -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_004_src_ready; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_004:src_ready
wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
wire [91:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
wire [5:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
wire cmd_xbar_mux_005_src_endofpacket; // cmd_xbar_mux_005:src_endofpacket -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_005_src_valid; // cmd_xbar_mux_005:src_valid -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_005_src_startofpacket; // cmd_xbar_mux_005:src_startofpacket -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [91:0] cmd_xbar_mux_005_src_data; // cmd_xbar_mux_005:src_data -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_mux_005_src_channel; // cmd_xbar_mux_005:src_channel -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_005_src_ready; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_005:src_ready
wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
wire [91:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
wire [5:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
wire [5:0] limiter_cmd_valid_data; // limiter:cmd_src_valid -> cmd_xbar_demux_001:sink_valid
wire irq_mapper_receiver0_irq; // jtag_uart_0:av_irq -> irq_mapper:receiver0_irq
wire [31:0] nios_d_irq_irq; // irq_mapper:sender_irq -> NIOS:d_irq
SoC_RAM ram (
.clk (clk_clk), // clk1.clk
.address (ram_s1_translator_avalon_anti_slave_0_address), // s1.address
.clken (ram_s1_translator_avalon_anti_slave_0_clken), // .clken
.chipselect (ram_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.write (ram_s1_translator_avalon_anti_slave_0_write), // .write
.readdata (ram_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.writedata (ram_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.byteenable (ram_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
SoC_jtag_uart_0 jtag_uart_0 (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // avalon_jtag_slave.chipselect
.av_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // .address
.av_read_n (~jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read_n
.av_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_write_n (~jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write_n
.av_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver0_irq) // irq.irq
);
SoC_sysid_qsys_0 sysid_qsys_0 (
.clock (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.readdata (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata), // control_slave.readdata
.address (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address) // .address
);
SoC_NIOS nios (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n
.d_address (nios_data_master_address), // data_master.address
.d_byteenable (nios_data_master_byteenable), // .byteenable
.d_read (nios_data_master_read), // .read
.d_readdata (nios_data_master_readdata), // .readdata
.d_waitrequest (nios_data_master_waitrequest), // .waitrequest
.d_write (nios_data_master_write), // .write
.d_writedata (nios_data_master_writedata), // .writedata
.jtag_debug_module_debugaccess_to_roms (nios_data_master_debugaccess), // .debugaccess
.i_address (nios_instruction_master_address), // instruction_master.address
.i_read (nios_instruction_master_read), // .read
.i_readdata (nios_instruction_master_readdata), // .readdata
.i_waitrequest (nios_instruction_master_waitrequest), // .waitrequest
.i_readdatavalid (nios_instruction_master_readdatavalid), // .readdatavalid
.d_irq (nios_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (), // jtag_debug_module_reset.reset
.jtag_debug_module_address (nios_jtag_debug_module_translator_avalon_anti_slave_0_address), // jtag_debug_module.address
.jtag_debug_module_byteenable (nios_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
.jtag_debug_module_debugaccess (nios_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.jtag_debug_module_read (nios_jtag_debug_module_translator_avalon_anti_slave_0_read), // .read
.jtag_debug_module_readdata (nios_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
.jtag_debug_module_waitrequest (nios_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.jtag_debug_module_write (nios_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
.jtag_debug_module_writedata (nios_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);
MainProyectoFinal #(
.Width (32),
.ConLimitador (0),
.Magnitud (7),
.Precision (24),
.Signo (1)
) hw_ann_0 (
.CLK (clk_clk), // clock.clk
.write (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_write), // avalon_slave_0.write
.read (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_read), // .read
.address (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_address), // .address
.writedata (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata), // .writedata
.readdata (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata), // .readdata
.MasterReset (~rst_controller_reset_out_reset) // reset_sink.reset_n
);
lfsr lfsr_0 (
.clk (clk_clk), // clock.clk
.read (lfsr_0_avalon_slave_0_translator_avalon_anti_slave_0_read), // avalon_slave_0.read
.read_data (lfsr_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata), // .readdata
.rst (rst_controller_reset_out_reset) // reset_sink.reset
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios_data_master_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (nios_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios_data_master_waitrequest), // .waitrequest
.av_byteenable (nios_data_master_byteenable), // .byteenable
.av_read (nios_data_master_read), // .read
.av_readdata (nios_data_master_readdata), // .readdata
.av_write (nios_data_master_write), // .write
.av_writedata (nios_data_master_writedata), // .writedata
.av_debugaccess (nios_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios_instruction_master_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (nios_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios_instruction_master_waitrequest), // .waitrequest
.av_read (nios_instruction_master_read), // .read
.av_readdata (nios_instruction_master_readdata), // .readdata
.av_readdatavalid (nios_instruction_master_readdatavalid), // .readdatavalid
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (15),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) ram_s1_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (ram_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (ram_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (ram_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (ram_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (ram_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (ram_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (ram_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (ram_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (ram_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (ram_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (ram_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (ram_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (ram_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (ram_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (ram_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (ram_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (ram_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_clken (ram_s1_translator_avalon_anti_slave_0_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_0_avalon_jtag_slave_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sysid_qsys_0_control_slave_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_readdata (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios_jtag_debug_module_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (nios_jtag_debug_module_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (nios_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
.av_read (nios_jtag_debug_module_translator_avalon_anti_slave_0_read), // .read
.av_readdata (nios_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (nios_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (nios_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_waitrequest (nios_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_debugaccess (nios_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hw_ann_0_avalon_slave_0_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_write), // .write
.av_read (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_read), // .read
.av_readdata (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) lfsr_0_avalon_slave_0_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_read (lfsr_0_avalon_slave_0_translator_avalon_anti_slave_0_read), // avalon_anti_slave_0.read
.av_readdata (lfsr_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata), // .readdata
.av_address (), // (terminated)
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (85),
.PKT_PROTECTION_L (83),
.PKT_BEGIN_BURST (74),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_BURST_TYPE_H (71),
.PKT_BURST_TYPE_L (70),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_TRANS_EXCLUSIVE (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (81),
.PKT_DEST_ID_L (79),
.PKT_THREAD_ID_H (82),
.PKT_THREAD_ID_L (82),
.PKT_CACHE_H (89),
.PKT_CACHE_L (86),
.PKT_DATA_SIDEBAND_H (73),
.PKT_DATA_SIDEBAND_L (73),
.PKT_QOS_H (75),
.PKT_QOS_L (75),
.PKT_ADDR_SIDEBAND_H (72),
.PKT_ADDR_SIDEBAND_L (72),
.PKT_RESPONSE_STATUS_H (91),
.PKT_RESPONSE_STATUS_L (90),
.ST_DATA_W (92),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios_data_master_translator_avalon_universal_master_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (nios_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (nios_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (nios_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_mux_src_valid), // rp.valid
.rp_data (rsp_xbar_mux_src_data), // .data
.rp_channel (rsp_xbar_mux_src_channel), // .channel
.rp_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (85),
.PKT_PROTECTION_L (83),
.PKT_BEGIN_BURST (74),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_BURST_TYPE_H (71),
.PKT_BURST_TYPE_L (70),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_TRANS_EXCLUSIVE (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (81),
.PKT_DEST_ID_L (79),
.PKT_THREAD_ID_H (82),
.PKT_THREAD_ID_L (82),
.PKT_CACHE_H (89),
.PKT_CACHE_L (86),
.PKT_DATA_SIDEBAND_H (73),
.PKT_DATA_SIDEBAND_L (73),
.PKT_QOS_H (75),
.PKT_QOS_L (75),
.PKT_ADDR_SIDEBAND_H (72),
.PKT_ADDR_SIDEBAND_L (72),
.PKT_RESPONSE_STATUS_H (91),
.PKT_RESPONSE_STATUS_L (90),
.ST_DATA_W (92),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios_instruction_master_translator_avalon_universal_master_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (nios_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (limiter_rsp_src_valid), // rp.valid
.rp_data (limiter_rsp_src_data), // .data
.rp_channel (limiter_rsp_src_channel), // .channel
.rp_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (74),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (81),
.PKT_DEST_ID_L (79),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_PROTECTION_H (85),
.PKT_PROTECTION_L (83),
.PKT_RESPONSE_STATUS_H (91),
.PKT_RESPONSE_STATUS_L (90),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.ST_CHANNEL_W (6),
.ST_DATA_W (92),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) ram_s1_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (ram_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (ram_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (ram_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (ram_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (ram_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (ram_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (ram_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (ram_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (ram_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (ram_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (ram_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (ram_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (ram_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (ram_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_src_valid), // .valid
.cp_data (cmd_xbar_mux_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_src_channel), // .channel
.rf_sink_ready (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (93),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (74),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (81),
.PKT_DEST_ID_L (79),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_PROTECTION_H (85),
.PKT_PROTECTION_L (83),
.PKT_RESPONSE_STATUS_H (91),
.PKT_RESPONSE_STATUS_L (90),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.ST_CHANNEL_W (6),
.ST_DATA_W (92),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_src1_ready), // cp.ready
.cp_valid (cmd_xbar_demux_src1_valid), // .valid
.cp_data (cmd_xbar_demux_src1_data), // .data
.cp_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_src1_channel), // .channel
.rf_sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (93),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (74),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (81),
.PKT_DEST_ID_L (79),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_PROTECTION_H (85),
.PKT_PROTECTION_L (83),
.PKT_RESPONSE_STATUS_H (91),
.PKT_RESPONSE_STATUS_L (90),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.ST_CHANNEL_W (6),
.ST_DATA_W (92),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_src2_ready), // cp.ready
.cp_valid (cmd_xbar_demux_src2_valid), // .valid
.cp_data (cmd_xbar_demux_src2_data), // .data
.cp_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_src2_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_src2_channel), // .channel
.rf_sink_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (93),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (74),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (81),
.PKT_DEST_ID_L (79),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_PROTECTION_H (85),
.PKT_PROTECTION_L (83),
.PKT_RESPONSE_STATUS_H (91),
.PKT_RESPONSE_STATUS_L (90),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.ST_CHANNEL_W (6),
.ST_DATA_W (92),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios_jtag_debug_module_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_003_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_003_src_valid), // .valid
.cp_data (cmd_xbar_mux_003_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_003_src_channel), // .channel
.rf_sink_ready (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (93),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (74),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (81),
.PKT_DEST_ID_L (79),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_PROTECTION_H (85),
.PKT_PROTECTION_L (83),
.PKT_RESPONSE_STATUS_H (91),
.PKT_RESPONSE_STATUS_L (90),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.ST_CHANNEL_W (6),
.ST_DATA_W (92),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_004_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_004_src_valid), // .valid
.cp_data (cmd_xbar_mux_004_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_004_src_channel), // .channel
.rf_sink_ready (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (93),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (74),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (81),
.PKT_DEST_ID_L (79),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_PROTECTION_H (85),
.PKT_PROTECTION_L (83),
.PKT_RESPONSE_STATUS_H (91),
.PKT_RESPONSE_STATUS_L (90),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.ST_CHANNEL_W (6),
.ST_DATA_W (92),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_005_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_005_src_valid), // .valid
.cp_data (cmd_xbar_mux_005_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_005_src_channel), // .channel
.rf_sink_ready (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (93),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
SoC_addr_router addr_router (
.sink_ready (nios_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (nios_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (nios_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (nios_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
SoC_addr_router_001 addr_router_001 (
.sink_ready (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_001_src_ready), // src.ready
.src_valid (addr_router_001_src_valid), // .valid
.src_data (addr_router_001_src_data), // .data
.src_channel (addr_router_001_src_channel), // .channel
.src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
);
SoC_id_router id_router (
.sink_ready (ram_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (ram_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (ram_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
SoC_id_router_001 id_router_001 (
.sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_001_src_ready), // src.ready
.src_valid (id_router_001_src_valid), // .valid
.src_data (id_router_001_src_data), // .data
.src_channel (id_router_001_src_channel), // .channel
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
);
SoC_id_router_001 id_router_002 (
.sink_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_002_src_ready), // src.ready
.src_valid (id_router_002_src_valid), // .valid
.src_data (id_router_002_src_data), // .data
.src_channel (id_router_002_src_channel), // .channel
.src_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_002_src_endofpacket) // .endofpacket
);
SoC_id_router id_router_003 (
.sink_ready (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_003_src_ready), // src.ready
.src_valid (id_router_003_src_valid), // .valid
.src_data (id_router_003_src_data), // .data
.src_channel (id_router_003_src_channel), // .channel
.src_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_003_src_endofpacket) // .endofpacket
);
SoC_id_router id_router_004 (
.sink_ready (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_004_src_ready), // src.ready
.src_valid (id_router_004_src_valid), // .valid
.src_data (id_router_004_src_data), // .data
.src_channel (id_router_004_src_channel), // .channel
.src_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_004_src_endofpacket) // .endofpacket
);
SoC_id_router id_router_005 (
.sink_ready (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_005_src_ready), // src.ready
.src_valid (id_router_005_src_valid), // .valid
.src_data (id_router_005_src_data), // .data
.src_channel (id_router_005_src_channel), // .channel
.src_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_005_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (81),
.PKT_DEST_ID_L (79),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.MAX_OUTSTANDING_RESPONSES (1),
.PIPELINED (0),
.ST_DATA_W (92),
.ST_CHANNEL_W (6),
.VALID_WIDTH (6),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32)
) limiter (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_001_src_valid), // .valid
.cmd_sink_data (addr_router_001_src_data), // .data
.cmd_sink_channel (addr_router_001_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_cmd_src_data), // .data
.cmd_src_channel (limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_rsp_src_valid), // .valid
.rsp_src_data (limiter_rsp_src_data), // .data
.rsp_src_channel (limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_cmd_valid_data) // cmd_valid.data
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
SoC_cmd_xbar_demux cmd_xbar_demux (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_src_ready), // sink.ready
.sink_channel (addr_router_src_channel), // .channel
.sink_data (addr_router_src_data), // .data
.sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.sink_valid (addr_router_src_valid), // .valid
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
.src1_data (cmd_xbar_demux_src1_data), // .data
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_src2_valid), // .valid
.src2_data (cmd_xbar_demux_src2_data), // .data
.src2_channel (cmd_xbar_demux_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_xbar_demux_src3_ready), // src3.ready
.src3_valid (cmd_xbar_demux_src3_valid), // .valid
.src3_data (cmd_xbar_demux_src3_data), // .data
.src3_channel (cmd_xbar_demux_src3_channel), // .channel
.src3_startofpacket (cmd_xbar_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_xbar_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_xbar_demux_src4_ready), // src4.ready
.src4_valid (cmd_xbar_demux_src4_valid), // .valid
.src4_data (cmd_xbar_demux_src4_data), // .data
.src4_channel (cmd_xbar_demux_src4_channel), // .channel
.src4_startofpacket (cmd_xbar_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_xbar_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_xbar_demux_src5_ready), // src5.ready
.src5_valid (cmd_xbar_demux_src5_valid), // .valid
.src5_data (cmd_xbar_demux_src5_data), // .data
.src5_channel (cmd_xbar_demux_src5_channel), // .channel
.src5_startofpacket (cmd_xbar_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_xbar_demux_src5_endofpacket) // .endofpacket
);
SoC_cmd_xbar_demux_001 cmd_xbar_demux_001 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (limiter_cmd_src_ready), // sink.ready
.sink_channel (limiter_cmd_src_channel), // .channel
.sink_data (limiter_cmd_src_data), // .data
.sink_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
.src0_data (cmd_xbar_demux_001_src0_data), // .data
.src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.src1_data (cmd_xbar_demux_001_src1_data), // .data
.src1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_001_src2_valid), // .valid
.src2_data (cmd_xbar_demux_001_src2_data), // .data
.src2_channel (cmd_xbar_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_xbar_demux_001_src3_valid), // .valid
.src3_data (cmd_xbar_demux_001_src3_data), // .data
.src3_channel (cmd_xbar_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket) // .endofpacket
);
SoC_cmd_xbar_mux cmd_xbar_mux (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_src_ready), // src.ready
.src_valid (cmd_xbar_mux_src_valid), // .valid
.src_data (cmd_xbar_mux_src_data), // .data
.src_channel (cmd_xbar_mux_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src0_valid), // .valid
.sink0_channel (cmd_xbar_demux_src0_channel), // .channel
.sink0_data (cmd_xbar_demux_src0_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket
);
SoC_cmd_xbar_mux cmd_xbar_mux_003 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_003_src_ready), // src.ready
.src_valid (cmd_xbar_mux_003_src_valid), // .valid
.src_data (cmd_xbar_mux_003_src_data), // .data
.src_channel (cmd_xbar_mux_003_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src3_valid), // .valid
.sink0_channel (cmd_xbar_demux_src3_channel), // .channel
.sink0_data (cmd_xbar_demux_src3_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src3_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket
);
SoC_cmd_xbar_mux cmd_xbar_mux_004 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_004_src_ready), // src.ready
.src_valid (cmd_xbar_mux_004_src_valid), // .valid
.src_data (cmd_xbar_mux_004_src_data), // .data
.src_channel (cmd_xbar_mux_004_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src4_valid), // .valid
.sink0_channel (cmd_xbar_demux_src4_channel), // .channel
.sink0_data (cmd_xbar_demux_src4_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src4_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src2_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src2_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src2_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src2_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src2_endofpacket) // .endofpacket
);
SoC_cmd_xbar_mux cmd_xbar_mux_005 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_005_src_ready), // src.ready
.src_valid (cmd_xbar_mux_005_src_valid), // .valid
.src_data (cmd_xbar_mux_005_src_data), // .data
.src_channel (cmd_xbar_mux_005_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src5_valid), // .valid
.sink0_channel (cmd_xbar_demux_src5_channel), // .channel
.sink0_data (cmd_xbar_demux_src5_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src5_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src3_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src3_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src3_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src3_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src3_endofpacket) // .endofpacket
);
SoC_rsp_xbar_demux rsp_xbar_demux (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_src_ready), // sink.ready
.sink_channel (id_router_src_channel), // .channel
.sink_data (id_router_src_data), // .data
.sink_startofpacket (id_router_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_src_endofpacket), // .endofpacket
.sink_valid (id_router_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_src1_valid), // .valid
.src1_data (rsp_xbar_demux_src1_data), // .data
.src1_channel (rsp_xbar_demux_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket
);
SoC_rsp_xbar_demux_001 rsp_xbar_demux_001 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_001_src_ready), // sink.ready
.sink_channel (id_router_001_src_channel), // .channel
.sink_data (id_router_001_src_data), // .data
.sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket
.sink_valid (id_router_001_src_valid), // .valid
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
.src0_data (rsp_xbar_demux_001_src0_data), // .data
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket
);
SoC_rsp_xbar_demux_001 rsp_xbar_demux_002 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_002_src_ready), // sink.ready
.sink_channel (id_router_002_src_channel), // .channel
.sink_data (id_router_002_src_data), // .data
.sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket
.sink_valid (id_router_002_src_valid), // .valid
.src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_002_src0_valid), // .valid
.src0_data (rsp_xbar_demux_002_src0_data), // .data
.src0_channel (rsp_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket
);
SoC_rsp_xbar_demux rsp_xbar_demux_003 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_003_src_ready), // sink.ready
.sink_channel (id_router_003_src_channel), // .channel
.sink_data (id_router_003_src_data), // .data
.sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket
.sink_valid (id_router_003_src_valid), // .valid
.src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_003_src0_valid), // .valid
.src0_data (rsp_xbar_demux_003_src0_data), // .data
.src0_channel (rsp_xbar_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_003_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_003_src1_valid), // .valid
.src1_data (rsp_xbar_demux_003_src1_data), // .data
.src1_channel (rsp_xbar_demux_003_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_003_src1_endofpacket) // .endofpacket
);
SoC_rsp_xbar_demux rsp_xbar_demux_004 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_004_src_ready), // sink.ready
.sink_channel (id_router_004_src_channel), // .channel
.sink_data (id_router_004_src_data), // .data
.sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket
.sink_valid (id_router_004_src_valid), // .valid
.src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_004_src0_valid), // .valid
.src0_data (rsp_xbar_demux_004_src0_data), // .data
.src0_channel (rsp_xbar_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_004_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_004_src1_valid), // .valid
.src1_data (rsp_xbar_demux_004_src1_data), // .data
.src1_channel (rsp_xbar_demux_004_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_004_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_004_src1_endofpacket) // .endofpacket
);
SoC_rsp_xbar_demux rsp_xbar_demux_005 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_005_src_ready), // sink.ready
.sink_channel (id_router_005_src_channel), // .channel
.sink_data (id_router_005_src_data), // .data
.sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket
.sink_valid (id_router_005_src_valid), // .valid
.src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_005_src0_valid), // .valid
.src0_data (rsp_xbar_demux_005_src0_data), // .data
.src0_channel (rsp_xbar_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_005_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_005_src1_valid), // .valid
.src1_data (rsp_xbar_demux_005_src1_data), // .data
.src1_channel (rsp_xbar_demux_005_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_005_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_005_src1_endofpacket) // .endofpacket
);
SoC_rsp_xbar_mux rsp_xbar_mux (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid
.sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel
.sink2_data (rsp_xbar_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid
.sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel
.sink3_data (rsp_xbar_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid
.sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel
.sink4_data (rsp_xbar_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid
.sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel
.sink5_data (rsp_xbar_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
);
SoC_rsp_xbar_mux_001 rsp_xbar_mux_001 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_001_src_ready), // src.ready
.src_valid (rsp_xbar_mux_001_src_valid), // .valid
.src_data (rsp_xbar_mux_001_src_data), // .data
.src_channel (rsp_xbar_mux_001_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src1_valid), // .valid
.sink0_channel (rsp_xbar_demux_src1_channel), // .channel
.sink0_data (rsp_xbar_demux_src1_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_003_src1_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_003_src1_valid), // .valid
.sink1_channel (rsp_xbar_demux_003_src1_channel), // .channel
.sink1_data (rsp_xbar_demux_003_src1_data), // .data
.sink1_startofpacket (rsp_xbar_demux_003_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_003_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_xbar_demux_004_src1_ready), // sink2.ready
.sink2_valid (rsp_xbar_demux_004_src1_valid), // .valid
.sink2_channel (rsp_xbar_demux_004_src1_channel), // .channel
.sink2_data (rsp_xbar_demux_004_src1_data), // .data
.sink2_startofpacket (rsp_xbar_demux_004_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_xbar_demux_004_src1_endofpacket), // .endofpacket
.sink3_ready (rsp_xbar_demux_005_src1_ready), // sink3.ready
.sink3_valid (rsp_xbar_demux_005_src1_valid), // .valid
.sink3_channel (rsp_xbar_demux_005_src1_channel), // .channel
.sink3_data (rsp_xbar_demux_005_src1_data), // .data
.sink3_startofpacket (rsp_xbar_demux_005_src1_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_xbar_demux_005_src1_endofpacket) // .endofpacket
);
SoC_irq_mapper irq_mapper (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (nios_d_irq_irq) // sender.irq
);
endmodule
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_reset O 1
// from_master_awready O 1 reg
// from_master_wready O 1 reg
// from_master_bvalid O 1 reg
// from_master_bid O 4 reg
// from_master_bresp O 2 reg
// from_master_arready O 1 reg
// from_master_rvalid O 1 reg
// from_master_rid O 4 reg
// from_master_rdata O 64 reg
// from_master_rresp O 2 reg
// from_master_rlast O 1 reg
// to_slave_awvalid O 1 reg
// to_slave_awid O 4 reg
// to_slave_awaddr O 64 reg
// to_slave_awlen O 8 reg
// to_slave_awsize O 3 reg
// to_slave_awburst O 2 reg
// to_slave_awlock O 1 reg
// to_slave_awcache O 4 reg
// to_slave_awprot O 3 reg
// to_slave_awqos O 4 reg
// to_slave_awregion O 4 reg
// to_slave_wvalid O 1 reg
// to_slave_wdata O 64 reg
// to_slave_wstrb O 8 reg
// to_slave_wlast O 1 reg
// to_slave_bready O 1 reg
// to_slave_arvalid O 1 reg
// to_slave_arid O 4 reg
// to_slave_araddr O 64 reg
// to_slave_arlen O 8 reg
// to_slave_arsize O 3 reg
// to_slave_arburst O 2 reg
// to_slave_arlock O 1 reg
// to_slave_arcache O 4 reg
// to_slave_arprot O 3 reg
// to_slave_arqos O 4 reg
// to_slave_arregion O 4 reg
// to_slave_rready O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// from_master_awvalid I 1
// from_master_awid I 4 reg
// from_master_awaddr I 64 reg
// from_master_awlen I 8 reg
// from_master_awsize I 3 reg
// from_master_awburst I 2 reg
// from_master_awlock I 1 reg
// from_master_awcache I 4 reg
// from_master_awprot I 3 reg
// from_master_awqos I 4 reg
// from_master_awregion I 4 reg
// from_master_wvalid I 1
// from_master_wdata I 64 reg
// from_master_wstrb I 8 reg
// from_master_wlast I 1 reg
// from_master_bready I 1
// from_master_arvalid I 1
// from_master_arid I 4 reg
// from_master_araddr I 64 reg
// from_master_arlen I 8 reg
// from_master_arsize I 3 reg
// from_master_arburst I 2 reg
// from_master_arlock I 1 reg
// from_master_arcache I 4 reg
// from_master_arprot I 3 reg
// from_master_arqos I 4 reg
// from_master_arregion I 4 reg
// from_master_rready I 1
// to_slave_awready I 1
// to_slave_wready I 1
// to_slave_bvalid I 1
// to_slave_bid I 4 reg
// to_slave_bresp I 2 reg
// to_slave_arready I 1
// to_slave_rvalid I 1
// to_slave_rid I 4 reg
// to_slave_rdata I 64 reg
// to_slave_rresp I 2 reg
// to_slave_rlast I 1 reg
// EN_reset I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkAXI4_Deburster_A(CLK,
RST_N,
EN_reset,
RDY_reset,
from_master_awvalid,
from_master_awid,
from_master_awaddr,
from_master_awlen,
from_master_awsize,
from_master_awburst,
from_master_awlock,
from_master_awcache,
from_master_awprot,
from_master_awqos,
from_master_awregion,
from_master_awready,
from_master_wvalid,
from_master_wdata,
from_master_wstrb,
from_master_wlast,
from_master_wready,
from_master_bvalid,
from_master_bid,
from_master_bresp,
from_master_bready,
from_master_arvalid,
from_master_arid,
from_master_araddr,
from_master_arlen,
from_master_arsize,
from_master_arburst,
from_master_arlock,
from_master_arcache,
from_master_arprot,
from_master_arqos,
from_master_arregion,
from_master_arready,
from_master_rvalid,
from_master_rid,
from_master_rdata,
from_master_rresp,
from_master_rlast,
from_master_rready,
to_slave_awvalid,
to_slave_awid,
to_slave_awaddr,
to_slave_awlen,
to_slave_awsize,
to_slave_awburst,
to_slave_awlock,
to_slave_awcache,
to_slave_awprot,
to_slave_awqos,
to_slave_awregion,
to_slave_awready,
to_slave_wvalid,
to_slave_wdata,
to_slave_wstrb,
to_slave_wlast,
to_slave_wready,
to_slave_bvalid,
to_slave_bid,
to_slave_bresp,
to_slave_bready,
to_slave_arvalid,
to_slave_arid,
to_slave_araddr,
to_slave_arlen,
to_slave_arsize,
to_slave_arburst,
to_slave_arlock,
to_slave_arcache,
to_slave_arprot,
to_slave_arqos,
to_slave_arregion,
to_slave_arready,
to_slave_rvalid,
to_slave_rid,
to_slave_rdata,
to_slave_rresp,
to_slave_rlast,
to_slave_rready);
input CLK;
input RST_N;
// action method reset
input EN_reset;
output RDY_reset;
// action method from_master_m_awvalid
input from_master_awvalid;
input [3 : 0] from_master_awid;
input [63 : 0] from_master_awaddr;
input [7 : 0] from_master_awlen;
input [2 : 0] from_master_awsize;
input [1 : 0] from_master_awburst;
input from_master_awlock;
input [3 : 0] from_master_awcache;
input [2 : 0] from_master_awprot;
input [3 : 0] from_master_awqos;
input [3 : 0] from_master_awregion;
// value method from_master_m_awready
output from_master_awready;
// action method from_master_m_wvalid
input from_master_wvalid;
input [63 : 0] from_master_wdata;
input [7 : 0] from_master_wstrb;
input from_master_wlast;
// value method from_master_m_wready
output from_master_wready;
// value method from_master_m_bvalid
output from_master_bvalid;
// value method from_master_m_bid
output [3 : 0] from_master_bid;
// value method from_master_m_bresp
output [1 : 0] from_master_bresp;
// value method from_master_m_buser
// action method from_master_m_bready
input from_master_bready;
// action method from_master_m_arvalid
input from_master_arvalid;
input [3 : 0] from_master_arid;
input [63 : 0] from_master_araddr;
input [7 : 0] from_master_arlen;
input [2 : 0] from_master_arsize;
input [1 : 0] from_master_arburst;
input from_master_arlock;
input [3 : 0] from_master_arcache;
input [2 : 0] from_master_arprot;
input [3 : 0] from_master_arqos;
input [3 : 0] from_master_arregion;
// value method from_master_m_arready
output from_master_arready;
// value method from_master_m_rvalid
output from_master_rvalid;
// value method from_master_m_rid
output [3 : 0] from_master_rid;
// value method from_master_m_rdata
output [63 : 0] from_master_rdata;
// value method from_master_m_rresp
output [1 : 0] from_master_rresp;
// value method from_master_m_rlast
output from_master_rlast;
// value method from_master_m_ruser
// action method from_master_m_rready
input from_master_rready;
// value method to_slave_m_awvalid
output to_slave_awvalid;
// value method to_slave_m_awid
output [3 : 0] to_slave_awid;
// value method to_slave_m_awaddr
output [63 : 0] to_slave_awaddr;
// value method to_slave_m_awlen
output [7 : 0] to_slave_awlen;
// value method to_slave_m_awsize
output [2 : 0] to_slave_awsize;
// value method to_slave_m_awburst
output [1 : 0] to_slave_awburst;
// value method to_slave_m_awlock
output to_slave_awlock;
// value method to_slave_m_awcache
output [3 : 0] to_slave_awcache;
// value method to_slave_m_awprot
output [2 : 0] to_slave_awprot;
// value method to_slave_m_awqos
output [3 : 0] to_slave_awqos;
// value method to_slave_m_awregion
output [3 : 0] to_slave_awregion;
// value method to_slave_m_awuser
// action method to_slave_m_awready
input to_slave_awready;
// value method to_slave_m_wvalid
output to_slave_wvalid;
// value method to_slave_m_wdata
output [63 : 0] to_slave_wdata;
// value method to_slave_m_wstrb
output [7 : 0] to_slave_wstrb;
// value method to_slave_m_wlast
output to_slave_wlast;
// value method to_slave_m_wuser
// action method to_slave_m_wready
input to_slave_wready;
// action method to_slave_m_bvalid
input to_slave_bvalid;
input [3 : 0] to_slave_bid;
input [1 : 0] to_slave_bresp;
// value method to_slave_m_bready
output to_slave_bready;
// value method to_slave_m_arvalid
output to_slave_arvalid;
// value method to_slave_m_arid
output [3 : 0] to_slave_arid;
// value method to_slave_m_araddr
output [63 : 0] to_slave_araddr;
// value method to_slave_m_arlen
output [7 : 0] to_slave_arlen;
// value method to_slave_m_arsize
output [2 : 0] to_slave_arsize;
// value method to_slave_m_arburst
output [1 : 0] to_slave_arburst;
// value method to_slave_m_arlock
output to_slave_arlock;
// value method to_slave_m_arcache
output [3 : 0] to_slave_arcache;
// value method to_slave_m_arprot
output [2 : 0] to_slave_arprot;
// value method to_slave_m_arqos
output [3 : 0] to_slave_arqos;
// value method to_slave_m_arregion
output [3 : 0] to_slave_arregion;
// value method to_slave_m_aruser
// action method to_slave_m_arready
input to_slave_arready;
// action method to_slave_m_rvalid
input to_slave_rvalid;
input [3 : 0] to_slave_rid;
input [63 : 0] to_slave_rdata;
input [1 : 0] to_slave_rresp;
input to_slave_rlast;
// value method to_slave_m_rready
output to_slave_rready;
// signals for module outputs
wire [63 : 0] from_master_rdata,
to_slave_araddr,
to_slave_awaddr,
to_slave_wdata;
wire [7 : 0] to_slave_arlen, to_slave_awlen, to_slave_wstrb;
wire [3 : 0] from_master_bid,
from_master_rid,
to_slave_arcache,
to_slave_arid,
to_slave_arqos,
to_slave_arregion,
to_slave_awcache,
to_slave_awid,
to_slave_awqos,
to_slave_awregion;
wire [2 : 0] to_slave_arprot,
to_slave_arsize,
to_slave_awprot,
to_slave_awsize;
wire [1 : 0] from_master_bresp,
from_master_rresp,
to_slave_arburst,
to_slave_awburst;
wire RDY_reset,
from_master_arready,
from_master_awready,
from_master_bvalid,
from_master_rlast,
from_master_rvalid,
from_master_wready,
to_slave_arlock,
to_slave_arvalid,
to_slave_awlock,
to_slave_awvalid,
to_slave_bready,
to_slave_rready,
to_slave_wlast,
to_slave_wvalid;
// register m_rg_ar_beat_count
reg [7 : 0] m_rg_ar_beat_count;
wire [7 : 0] m_rg_ar_beat_count$D_IN;
wire m_rg_ar_beat_count$EN;
// register m_rg_b_beat_count
reg [7 : 0] m_rg_b_beat_count;
wire [7 : 0] m_rg_b_beat_count$D_IN;
wire m_rg_b_beat_count$EN;
// register m_rg_b_resp
reg [1 : 0] m_rg_b_resp;
wire [1 : 0] m_rg_b_resp$D_IN;
wire m_rg_b_resp$EN;
// register m_rg_last_beat_raddr
reg [63 : 0] m_rg_last_beat_raddr;
wire [63 : 0] m_rg_last_beat_raddr$D_IN;
wire m_rg_last_beat_raddr$EN;
// register m_rg_last_beat_waddr
reg [63 : 0] m_rg_last_beat_waddr;
wire [63 : 0] m_rg_last_beat_waddr$D_IN;
wire m_rg_last_beat_waddr$EN;
// register m_rg_r_beat_count
reg [7 : 0] m_rg_r_beat_count;
wire [7 : 0] m_rg_r_beat_count$D_IN;
wire m_rg_r_beat_count$EN;
// register m_rg_reset
reg m_rg_reset;
wire m_rg_reset$D_IN, m_rg_reset$EN;
// register m_rg_w_beat_count
reg [7 : 0] m_rg_w_beat_count;
wire [7 : 0] m_rg_w_beat_count$D_IN;
wire m_rg_w_beat_count$EN;
// ports of submodule m_f_r_arlen
wire [7 : 0] m_f_r_arlen$D_IN, m_f_r_arlen$D_OUT;
wire m_f_r_arlen$CLR,
m_f_r_arlen$DEQ,
m_f_r_arlen$EMPTY_N,
m_f_r_arlen$ENQ,
m_f_r_arlen$FULL_N;
// ports of submodule m_f_w_awlen
wire [7 : 0] m_f_w_awlen$D_IN, m_f_w_awlen$D_OUT;
wire m_f_w_awlen$CLR,
m_f_w_awlen$DEQ,
m_f_w_awlen$EMPTY_N,
m_f_w_awlen$ENQ,
m_f_w_awlen$FULL_N;
// ports of submodule m_xactor_from_master_f_rd_addr
wire [96 : 0] m_xactor_from_master_f_rd_addr$D_IN,
m_xactor_from_master_f_rd_addr$D_OUT;
wire m_xactor_from_master_f_rd_addr$CLR,
m_xactor_from_master_f_rd_addr$DEQ,
m_xactor_from_master_f_rd_addr$EMPTY_N,
m_xactor_from_master_f_rd_addr$ENQ,
m_xactor_from_master_f_rd_addr$FULL_N;
// ports of submodule m_xactor_from_master_f_rd_data
wire [70 : 0] m_xactor_from_master_f_rd_data$D_IN,
m_xactor_from_master_f_rd_data$D_OUT;
wire m_xactor_from_master_f_rd_data$CLR,
m_xactor_from_master_f_rd_data$DEQ,
m_xactor_from_master_f_rd_data$EMPTY_N,
m_xactor_from_master_f_rd_data$ENQ,
m_xactor_from_master_f_rd_data$FULL_N;
// ports of submodule m_xactor_from_master_f_wr_addr
wire [96 : 0] m_xactor_from_master_f_wr_addr$D_IN,
m_xactor_from_master_f_wr_addr$D_OUT;
wire m_xactor_from_master_f_wr_addr$CLR,
m_xactor_from_master_f_wr_addr$DEQ,
m_xactor_from_master_f_wr_addr$EMPTY_N,
m_xactor_from_master_f_wr_addr$ENQ,
m_xactor_from_master_f_wr_addr$FULL_N;
// ports of submodule m_xactor_from_master_f_wr_data
wire [72 : 0] m_xactor_from_master_f_wr_data$D_IN,
m_xactor_from_master_f_wr_data$D_OUT;
wire m_xactor_from_master_f_wr_data$CLR,
m_xactor_from_master_f_wr_data$DEQ,
m_xactor_from_master_f_wr_data$EMPTY_N,
m_xactor_from_master_f_wr_data$ENQ,
m_xactor_from_master_f_wr_data$FULL_N;
// ports of submodule m_xactor_from_master_f_wr_resp
wire [5 : 0] m_xactor_from_master_f_wr_resp$D_IN,
m_xactor_from_master_f_wr_resp$D_OUT;
wire m_xactor_from_master_f_wr_resp$CLR,
m_xactor_from_master_f_wr_resp$DEQ,
m_xactor_from_master_f_wr_resp$EMPTY_N,
m_xactor_from_master_f_wr_resp$ENQ,
m_xactor_from_master_f_wr_resp$FULL_N;
// ports of submodule m_xactor_to_slave_f_rd_addr
wire [96 : 0] m_xactor_to_slave_f_rd_addr$D_IN,
m_xactor_to_slave_f_rd_addr$D_OUT;
wire m_xactor_to_slave_f_rd_addr$CLR,
m_xactor_to_slave_f_rd_addr$DEQ,
m_xactor_to_slave_f_rd_addr$EMPTY_N,
m_xactor_to_slave_f_rd_addr$ENQ,
m_xactor_to_slave_f_rd_addr$FULL_N;
// ports of submodule m_xactor_to_slave_f_rd_data
wire [70 : 0] m_xactor_to_slave_f_rd_data$D_IN,
m_xactor_to_slave_f_rd_data$D_OUT;
wire m_xactor_to_slave_f_rd_data$CLR,
m_xactor_to_slave_f_rd_data$DEQ,
m_xactor_to_slave_f_rd_data$EMPTY_N,
m_xactor_to_slave_f_rd_data$ENQ,
m_xactor_to_slave_f_rd_data$FULL_N;
// ports of submodule m_xactor_to_slave_f_wr_addr
wire [96 : 0] m_xactor_to_slave_f_wr_addr$D_IN,
m_xactor_to_slave_f_wr_addr$D_OUT;
wire m_xactor_to_slave_f_wr_addr$CLR,
m_xactor_to_slave_f_wr_addr$DEQ,
m_xactor_to_slave_f_wr_addr$EMPTY_N,
m_xactor_to_slave_f_wr_addr$ENQ,
m_xactor_to_slave_f_wr_addr$FULL_N;
// ports of submodule m_xactor_to_slave_f_wr_data
wire [72 : 0] m_xactor_to_slave_f_wr_data$D_IN,
m_xactor_to_slave_f_wr_data$D_OUT;
wire m_xactor_to_slave_f_wr_data$CLR,
m_xactor_to_slave_f_wr_data$DEQ,
m_xactor_to_slave_f_wr_data$EMPTY_N,
m_xactor_to_slave_f_wr_data$ENQ,
m_xactor_to_slave_f_wr_data$FULL_N;
// ports of submodule m_xactor_to_slave_f_wr_resp
wire [5 : 0] m_xactor_to_slave_f_wr_resp$D_IN,
m_xactor_to_slave_f_wr_resp$D_OUT;
wire m_xactor_to_slave_f_wr_resp$CLR,
m_xactor_to_slave_f_wr_resp$DEQ,
m_xactor_to_slave_f_wr_resp$EMPTY_N,
m_xactor_to_slave_f_wr_resp$ENQ,
m_xactor_to_slave_f_wr_resp$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_m_rl_rd_resp_slave_to_master,
CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave,
CAN_FIRE_RL_m_rl_reset,
CAN_FIRE_RL_m_rl_wr_resp_slave_to_master,
CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave,
CAN_FIRE_from_master_m_arvalid,
CAN_FIRE_from_master_m_awvalid,
CAN_FIRE_from_master_m_bready,
CAN_FIRE_from_master_m_rready,
CAN_FIRE_from_master_m_wvalid,
CAN_FIRE_reset,
CAN_FIRE_to_slave_m_arready,
CAN_FIRE_to_slave_m_awready,
CAN_FIRE_to_slave_m_bvalid,
CAN_FIRE_to_slave_m_rvalid,
CAN_FIRE_to_slave_m_wready,
WILL_FIRE_RL_m_rl_rd_resp_slave_to_master,
WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave,
WILL_FIRE_RL_m_rl_reset,
WILL_FIRE_RL_m_rl_wr_resp_slave_to_master,
WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave,
WILL_FIRE_from_master_m_arvalid,
WILL_FIRE_from_master_m_awvalid,
WILL_FIRE_from_master_m_bready,
WILL_FIRE_from_master_m_rready,
WILL_FIRE_from_master_m_wvalid,
WILL_FIRE_reset,
WILL_FIRE_to_slave_m_arready,
WILL_FIRE_to_slave_m_awready,
WILL_FIRE_to_slave_m_bvalid,
WILL_FIRE_to_slave_m_rvalid,
WILL_FIRE_to_slave_m_wready;
// inputs to muxes for submodule ports
wire [7 : 0] MUX_m_rg_ar_beat_count$write_1__VAL_2,
MUX_m_rg_b_beat_count$write_1__VAL_2,
MUX_m_rg_r_beat_count$write_1__VAL_2,
MUX_m_rg_w_beat_count$write_1__VAL_2;
wire [1 : 0] MUX_m_rg_b_resp$write_1__VAL_2;
wire MUX_m_rg_b_resp$write_1__SEL_2;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h2464;
reg [31 : 0] v__h2458;
// synopsys translate_on
// remaining internal signals
wire [63 : 0] a_out_araddr__h3025,
a_out_awaddr__h1941,
addr___1__h2035,
addr___1__h3119,
addr__h2023,
addr__h3107,
burst_len__h2024,
burst_len__h3108,
wrap_mask__h2025,
wrap_mask__h3109,
x__h2047,
x__h3131,
y__h2048,
y__h2049,
y__h3132,
y__h3133;
wire [7 : 0] x__h2322, x__h2829, x__h3316, x__h3535;
wire m_rg_ar_beat_count_9_ULT_m_xactor_from_master__ETC___d110,
m_rg_b_beat_count_5_ULT_m_f_w_awlen_first__6___d57,
m_rg_r_beat_count_19_ULT_m_f_r_arlen_first__20___d121,
m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42;
// action method reset
assign RDY_reset = !m_rg_reset ;
assign CAN_FIRE_reset = !m_rg_reset ;
assign WILL_FIRE_reset = EN_reset ;
// action method from_master_m_awvalid
assign CAN_FIRE_from_master_m_awvalid = 1'd1 ;
assign WILL_FIRE_from_master_m_awvalid = 1'd1 ;
// value method from_master_m_awready
assign from_master_awready = m_xactor_from_master_f_wr_addr$FULL_N ;
// action method from_master_m_wvalid
assign CAN_FIRE_from_master_m_wvalid = 1'd1 ;
assign WILL_FIRE_from_master_m_wvalid = 1'd1 ;
// value method from_master_m_wready
assign from_master_wready = m_xactor_from_master_f_wr_data$FULL_N ;
// value method from_master_m_bvalid
assign from_master_bvalid = m_xactor_from_master_f_wr_resp$EMPTY_N ;
// value method from_master_m_bid
assign from_master_bid = m_xactor_from_master_f_wr_resp$D_OUT[5:2] ;
// value method from_master_m_bresp
assign from_master_bresp = m_xactor_from_master_f_wr_resp$D_OUT[1:0] ;
// action method from_master_m_bready
assign CAN_FIRE_from_master_m_bready = 1'd1 ;
assign WILL_FIRE_from_master_m_bready = 1'd1 ;
// action method from_master_m_arvalid
assign CAN_FIRE_from_master_m_arvalid = 1'd1 ;
assign WILL_FIRE_from_master_m_arvalid = 1'd1 ;
// value method from_master_m_arready
assign from_master_arready = m_xactor_from_master_f_rd_addr$FULL_N ;
// value method from_master_m_rvalid
assign from_master_rvalid = m_xactor_from_master_f_rd_data$EMPTY_N ;
// value method from_master_m_rid
assign from_master_rid = m_xactor_from_master_f_rd_data$D_OUT[70:67] ;
// value method from_master_m_rdata
assign from_master_rdata = m_xactor_from_master_f_rd_data$D_OUT[66:3] ;
// value method from_master_m_rresp
assign from_master_rresp = m_xactor_from_master_f_rd_data$D_OUT[2:1] ;
// value method from_master_m_rlast
assign from_master_rlast = m_xactor_from_master_f_rd_data$D_OUT[0] ;
// action method from_master_m_rready
assign CAN_FIRE_from_master_m_rready = 1'd1 ;
assign WILL_FIRE_from_master_m_rready = 1'd1 ;
// value method to_slave_m_awvalid
assign to_slave_awvalid = m_xactor_to_slave_f_wr_addr$EMPTY_N ;
// value method to_slave_m_awid
assign to_slave_awid = m_xactor_to_slave_f_wr_addr$D_OUT[96:93] ;
// value method to_slave_m_awaddr
assign to_slave_awaddr = m_xactor_to_slave_f_wr_addr$D_OUT[92:29] ;
// value method to_slave_m_awlen
assign to_slave_awlen = m_xactor_to_slave_f_wr_addr$D_OUT[28:21] ;
// value method to_slave_m_awsize
assign to_slave_awsize = m_xactor_to_slave_f_wr_addr$D_OUT[20:18] ;
// value method to_slave_m_awburst
assign to_slave_awburst = m_xactor_to_slave_f_wr_addr$D_OUT[17:16] ;
// value method to_slave_m_awlock
assign to_slave_awlock = m_xactor_to_slave_f_wr_addr$D_OUT[15] ;
// value method to_slave_m_awcache
assign to_slave_awcache = m_xactor_to_slave_f_wr_addr$D_OUT[14:11] ;
// value method to_slave_m_awprot
assign to_slave_awprot = m_xactor_to_slave_f_wr_addr$D_OUT[10:8] ;
// value method to_slave_m_awqos
assign to_slave_awqos = m_xactor_to_slave_f_wr_addr$D_OUT[7:4] ;
// value method to_slave_m_awregion
assign to_slave_awregion = m_xactor_to_slave_f_wr_addr$D_OUT[3:0] ;
// action method to_slave_m_awready
assign CAN_FIRE_to_slave_m_awready = 1'd1 ;
assign WILL_FIRE_to_slave_m_awready = 1'd1 ;
// value method to_slave_m_wvalid
assign to_slave_wvalid = m_xactor_to_slave_f_wr_data$EMPTY_N ;
// value method to_slave_m_wdata
assign to_slave_wdata = m_xactor_to_slave_f_wr_data$D_OUT[72:9] ;
// value method to_slave_m_wstrb
assign to_slave_wstrb = m_xactor_to_slave_f_wr_data$D_OUT[8:1] ;
// value method to_slave_m_wlast
assign to_slave_wlast = m_xactor_to_slave_f_wr_data$D_OUT[0] ;
// action method to_slave_m_wready
assign CAN_FIRE_to_slave_m_wready = 1'd1 ;
assign WILL_FIRE_to_slave_m_wready = 1'd1 ;
// action method to_slave_m_bvalid
assign CAN_FIRE_to_slave_m_bvalid = 1'd1 ;
assign WILL_FIRE_to_slave_m_bvalid = 1'd1 ;
// value method to_slave_m_bready
assign to_slave_bready = m_xactor_to_slave_f_wr_resp$FULL_N ;
// value method to_slave_m_arvalid
assign to_slave_arvalid = m_xactor_to_slave_f_rd_addr$EMPTY_N ;
// value method to_slave_m_arid
assign to_slave_arid = m_xactor_to_slave_f_rd_addr$D_OUT[96:93] ;
// value method to_slave_m_araddr
assign to_slave_araddr = m_xactor_to_slave_f_rd_addr$D_OUT[92:29] ;
// value method to_slave_m_arlen
assign to_slave_arlen = m_xactor_to_slave_f_rd_addr$D_OUT[28:21] ;
// value method to_slave_m_arsize
assign to_slave_arsize = m_xactor_to_slave_f_rd_addr$D_OUT[20:18] ;
// value method to_slave_m_arburst
assign to_slave_arburst = m_xactor_to_slave_f_rd_addr$D_OUT[17:16] ;
// value method to_slave_m_arlock
assign to_slave_arlock = m_xactor_to_slave_f_rd_addr$D_OUT[15] ;
// value method to_slave_m_arcache
assign to_slave_arcache = m_xactor_to_slave_f_rd_addr$D_OUT[14:11] ;
// value method to_slave_m_arprot
assign to_slave_arprot = m_xactor_to_slave_f_rd_addr$D_OUT[10:8] ;
// value method to_slave_m_arqos
assign to_slave_arqos = m_xactor_to_slave_f_rd_addr$D_OUT[7:4] ;
// value method to_slave_m_arregion
assign to_slave_arregion = m_xactor_to_slave_f_rd_addr$D_OUT[3:0] ;
// action method to_slave_m_arready
assign CAN_FIRE_to_slave_m_arready = 1'd1 ;
assign WILL_FIRE_to_slave_m_arready = 1'd1 ;
// action method to_slave_m_rvalid
assign CAN_FIRE_to_slave_m_rvalid = 1'd1 ;
assign WILL_FIRE_to_slave_m_rvalid = 1'd1 ;
// value method to_slave_m_rready
assign to_slave_rready = m_xactor_to_slave_f_rd_data$FULL_N ;
// submodule m_f_r_arlen
SizedFIFO #(.p1width(32'd8),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(1'd1)) m_f_r_arlen(.RST(RST_N),
.CLK(CLK),
.D_IN(m_f_r_arlen$D_IN),
.ENQ(m_f_r_arlen$ENQ),
.DEQ(m_f_r_arlen$DEQ),
.CLR(m_f_r_arlen$CLR),
.D_OUT(m_f_r_arlen$D_OUT),
.FULL_N(m_f_r_arlen$FULL_N),
.EMPTY_N(m_f_r_arlen$EMPTY_N));
// submodule m_f_w_awlen
SizedFIFO #(.p1width(32'd8),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(1'd1)) m_f_w_awlen(.RST(RST_N),
.CLK(CLK),
.D_IN(m_f_w_awlen$D_IN),
.ENQ(m_f_w_awlen$ENQ),
.DEQ(m_f_w_awlen$DEQ),
.CLR(m_f_w_awlen$CLR),
.D_OUT(m_f_w_awlen$D_OUT),
.FULL_N(m_f_w_awlen$FULL_N),
.EMPTY_N(m_f_w_awlen$EMPTY_N));
// submodule m_xactor_from_master_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) m_xactor_from_master_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_from_master_f_rd_addr$D_IN),
.ENQ(m_xactor_from_master_f_rd_addr$ENQ),
.DEQ(m_xactor_from_master_f_rd_addr$DEQ),
.CLR(m_xactor_from_master_f_rd_addr$CLR),
.D_OUT(m_xactor_from_master_f_rd_addr$D_OUT),
.FULL_N(m_xactor_from_master_f_rd_addr$FULL_N),
.EMPTY_N(m_xactor_from_master_f_rd_addr$EMPTY_N));
// submodule m_xactor_from_master_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(1'd1)) m_xactor_from_master_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_from_master_f_rd_data$D_IN),
.ENQ(m_xactor_from_master_f_rd_data$ENQ),
.DEQ(m_xactor_from_master_f_rd_data$DEQ),
.CLR(m_xactor_from_master_f_rd_data$CLR),
.D_OUT(m_xactor_from_master_f_rd_data$D_OUT),
.FULL_N(m_xactor_from_master_f_rd_data$FULL_N),
.EMPTY_N(m_xactor_from_master_f_rd_data$EMPTY_N));
// submodule m_xactor_from_master_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) m_xactor_from_master_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_from_master_f_wr_addr$D_IN),
.ENQ(m_xactor_from_master_f_wr_addr$ENQ),
.DEQ(m_xactor_from_master_f_wr_addr$DEQ),
.CLR(m_xactor_from_master_f_wr_addr$CLR),
.D_OUT(m_xactor_from_master_f_wr_addr$D_OUT),
.FULL_N(m_xactor_from_master_f_wr_addr$FULL_N),
.EMPTY_N(m_xactor_from_master_f_wr_addr$EMPTY_N));
// submodule m_xactor_from_master_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) m_xactor_from_master_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_from_master_f_wr_data$D_IN),
.ENQ(m_xactor_from_master_f_wr_data$ENQ),
.DEQ(m_xactor_from_master_f_wr_data$DEQ),
.CLR(m_xactor_from_master_f_wr_data$CLR),
.D_OUT(m_xactor_from_master_f_wr_data$D_OUT),
.FULL_N(m_xactor_from_master_f_wr_data$FULL_N),
.EMPTY_N(m_xactor_from_master_f_wr_data$EMPTY_N));
// submodule m_xactor_from_master_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(1'd1)) m_xactor_from_master_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_from_master_f_wr_resp$D_IN),
.ENQ(m_xactor_from_master_f_wr_resp$ENQ),
.DEQ(m_xactor_from_master_f_wr_resp$DEQ),
.CLR(m_xactor_from_master_f_wr_resp$CLR),
.D_OUT(m_xactor_from_master_f_wr_resp$D_OUT),
.FULL_N(m_xactor_from_master_f_wr_resp$FULL_N),
.EMPTY_N(m_xactor_from_master_f_wr_resp$EMPTY_N));
// submodule m_xactor_to_slave_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) m_xactor_to_slave_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_to_slave_f_rd_addr$D_IN),
.ENQ(m_xactor_to_slave_f_rd_addr$ENQ),
.DEQ(m_xactor_to_slave_f_rd_addr$DEQ),
.CLR(m_xactor_to_slave_f_rd_addr$CLR),
.D_OUT(m_xactor_to_slave_f_rd_addr$D_OUT),
.FULL_N(m_xactor_to_slave_f_rd_addr$FULL_N),
.EMPTY_N(m_xactor_to_slave_f_rd_addr$EMPTY_N));
// submodule m_xactor_to_slave_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(1'd1)) m_xactor_to_slave_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_to_slave_f_rd_data$D_IN),
.ENQ(m_xactor_to_slave_f_rd_data$ENQ),
.DEQ(m_xactor_to_slave_f_rd_data$DEQ),
.CLR(m_xactor_to_slave_f_rd_data$CLR),
.D_OUT(m_xactor_to_slave_f_rd_data$D_OUT),
.FULL_N(m_xactor_to_slave_f_rd_data$FULL_N),
.EMPTY_N(m_xactor_to_slave_f_rd_data$EMPTY_N));
// submodule m_xactor_to_slave_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) m_xactor_to_slave_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_to_slave_f_wr_addr$D_IN),
.ENQ(m_xactor_to_slave_f_wr_addr$ENQ),
.DEQ(m_xactor_to_slave_f_wr_addr$DEQ),
.CLR(m_xactor_to_slave_f_wr_addr$CLR),
.D_OUT(m_xactor_to_slave_f_wr_addr$D_OUT),
.FULL_N(m_xactor_to_slave_f_wr_addr$FULL_N),
.EMPTY_N(m_xactor_to_slave_f_wr_addr$EMPTY_N));
// submodule m_xactor_to_slave_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) m_xactor_to_slave_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_to_slave_f_wr_data$D_IN),
.ENQ(m_xactor_to_slave_f_wr_data$ENQ),
.DEQ(m_xactor_to_slave_f_wr_data$DEQ),
.CLR(m_xactor_to_slave_f_wr_data$CLR),
.D_OUT(m_xactor_to_slave_f_wr_data$D_OUT),
.FULL_N(m_xactor_to_slave_f_wr_data$FULL_N),
.EMPTY_N(m_xactor_to_slave_f_wr_data$EMPTY_N));
// submodule m_xactor_to_slave_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(1'd1)) m_xactor_to_slave_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_to_slave_f_wr_resp$D_IN),
.ENQ(m_xactor_to_slave_f_wr_resp$ENQ),
.DEQ(m_xactor_to_slave_f_wr_resp$DEQ),
.CLR(m_xactor_to_slave_f_wr_resp$CLR),
.D_OUT(m_xactor_to_slave_f_wr_resp$D_OUT),
.FULL_N(m_xactor_to_slave_f_wr_resp$FULL_N),
.EMPTY_N(m_xactor_to_slave_f_wr_resp$EMPTY_N));
// rule RL_m_rl_wr_xaction_master_to_slave
assign CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave =
m_xactor_to_slave_f_wr_addr$FULL_N &&
m_xactor_from_master_f_wr_addr$EMPTY_N &&
m_xactor_to_slave_f_wr_data$FULL_N &&
m_xactor_from_master_f_wr_data$EMPTY_N &&
(m_rg_w_beat_count != 8'd0 || m_f_w_awlen$FULL_N) ;
assign WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave =
CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ;
// rule RL_m_rl_wr_resp_slave_to_master
assign CAN_FIRE_RL_m_rl_wr_resp_slave_to_master =
m_xactor_to_slave_f_wr_resp$EMPTY_N && m_f_w_awlen$EMPTY_N &&
(m_rg_b_beat_count_5_ULT_m_f_w_awlen_first__6___d57 ||
m_xactor_from_master_f_wr_resp$FULL_N) ;
assign WILL_FIRE_RL_m_rl_wr_resp_slave_to_master =
CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ;
// rule RL_m_rl_rd_xaction_master_to_slave
assign CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave =
m_xactor_to_slave_f_rd_addr$FULL_N &&
m_xactor_from_master_f_rd_addr$EMPTY_N &&
(m_rg_ar_beat_count != 8'd0 || m_f_r_arlen$FULL_N) ;
assign WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave =
CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ;
// rule RL_m_rl_rd_resp_slave_to_master
assign CAN_FIRE_RL_m_rl_rd_resp_slave_to_master =
m_xactor_to_slave_f_rd_data$EMPTY_N && m_f_r_arlen$EMPTY_N &&
m_xactor_from_master_f_rd_data$FULL_N ;
assign WILL_FIRE_RL_m_rl_rd_resp_slave_to_master =
CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ;
// rule RL_m_rl_reset
assign CAN_FIRE_RL_m_rl_reset = m_rg_reset ;
assign WILL_FIRE_RL_m_rl_reset = m_rg_reset ;
// inputs to muxes for submodule ports
assign MUX_m_rg_b_resp$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_wr_resp_slave_to_master &&
(m_rg_b_resp == 2'b0 &&
m_xactor_to_slave_f_wr_resp$D_OUT[1:0] != 2'b0 ||
!m_rg_b_beat_count_5_ULT_m_f_w_awlen_first__6___d57) ;
assign MUX_m_rg_ar_beat_count$write_1__VAL_2 =
m_rg_ar_beat_count_9_ULT_m_xactor_from_master__ETC___d110 ?
x__h3316 :
8'd0 ;
assign MUX_m_rg_b_beat_count$write_1__VAL_2 =
m_rg_b_beat_count_5_ULT_m_f_w_awlen_first__6___d57 ?
x__h2829 :
8'd0 ;
assign MUX_m_rg_b_resp$write_1__VAL_2 =
m_rg_b_beat_count_5_ULT_m_f_w_awlen_first__6___d57 ?
m_xactor_to_slave_f_wr_resp$D_OUT[1:0] :
2'b0 ;
assign MUX_m_rg_r_beat_count$write_1__VAL_2 =
m_rg_r_beat_count_19_ULT_m_f_r_arlen_first__20___d121 ?
x__h3535 :
8'd0 ;
assign MUX_m_rg_w_beat_count$write_1__VAL_2 =
m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 ?
x__h2322 :
8'd0 ;
// register m_rg_ar_beat_count
assign m_rg_ar_beat_count$D_IN =
m_rg_reset ? 8'd0 : MUX_m_rg_ar_beat_count$write_1__VAL_2 ;
assign m_rg_ar_beat_count$EN =
WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave || m_rg_reset ;
// register m_rg_b_beat_count
assign m_rg_b_beat_count$D_IN =
m_rg_reset ? 8'd0 : MUX_m_rg_b_beat_count$write_1__VAL_2 ;
assign m_rg_b_beat_count$EN =
WILL_FIRE_RL_m_rl_wr_resp_slave_to_master || m_rg_reset ;
// register m_rg_b_resp
assign m_rg_b_resp$D_IN =
m_rg_reset ? 2'b0 : MUX_m_rg_b_resp$write_1__VAL_2 ;
assign m_rg_b_resp$EN = MUX_m_rg_b_resp$write_1__SEL_2 || m_rg_reset ;
// register m_rg_last_beat_raddr
assign m_rg_last_beat_raddr$D_IN = a_out_araddr__h3025 ;
assign m_rg_last_beat_raddr$EN =
CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ;
// register m_rg_last_beat_waddr
assign m_rg_last_beat_waddr$D_IN = a_out_awaddr__h1941 ;
assign m_rg_last_beat_waddr$EN =
CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ;
// register m_rg_r_beat_count
assign m_rg_r_beat_count$D_IN =
m_rg_reset ? 8'd0 : MUX_m_rg_r_beat_count$write_1__VAL_2 ;
assign m_rg_r_beat_count$EN =
WILL_FIRE_RL_m_rl_rd_resp_slave_to_master || m_rg_reset ;
// register m_rg_reset
assign m_rg_reset$D_IN = !m_rg_reset ;
assign m_rg_reset$EN = m_rg_reset || EN_reset ;
// register m_rg_w_beat_count
assign m_rg_w_beat_count$D_IN =
m_rg_reset ? 8'd0 : MUX_m_rg_w_beat_count$write_1__VAL_2 ;
assign m_rg_w_beat_count$EN =
WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave || m_rg_reset ;
// submodule m_f_r_arlen
assign m_f_r_arlen$D_IN = m_xactor_from_master_f_rd_addr$D_OUT[28:21] ;
assign m_f_r_arlen$ENQ =
WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave &&
m_rg_ar_beat_count == 8'd0 ;
assign m_f_r_arlen$DEQ =
WILL_FIRE_RL_m_rl_rd_resp_slave_to_master &&
!m_rg_r_beat_count_19_ULT_m_f_r_arlen_first__20___d121 ;
assign m_f_r_arlen$CLR = m_rg_reset ;
// submodule m_f_w_awlen
assign m_f_w_awlen$D_IN = m_xactor_from_master_f_wr_addr$D_OUT[28:21] ;
assign m_f_w_awlen$ENQ =
WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
m_rg_w_beat_count == 8'd0 ;
assign m_f_w_awlen$DEQ =
WILL_FIRE_RL_m_rl_wr_resp_slave_to_master &&
!m_rg_b_beat_count_5_ULT_m_f_w_awlen_first__6___d57 ;
assign m_f_w_awlen$CLR = m_rg_reset ;
// submodule m_xactor_from_master_f_rd_addr
assign m_xactor_from_master_f_rd_addr$D_IN =
{ from_master_arid,
from_master_araddr,
from_master_arlen,
from_master_arsize,
from_master_arburst,
from_master_arlock,
from_master_arcache,
from_master_arprot,
from_master_arqos,
from_master_arregion } ;
assign m_xactor_from_master_f_rd_addr$ENQ =
from_master_arvalid && m_xactor_from_master_f_rd_addr$FULL_N ;
assign m_xactor_from_master_f_rd_addr$DEQ =
WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave &&
!m_rg_ar_beat_count_9_ULT_m_xactor_from_master__ETC___d110 ;
assign m_xactor_from_master_f_rd_addr$CLR = m_rg_reset ;
// submodule m_xactor_from_master_f_rd_data
assign m_xactor_from_master_f_rd_data$D_IN =
{ m_xactor_to_slave_f_rd_data$D_OUT[70:1],
!m_rg_r_beat_count_19_ULT_m_f_r_arlen_first__20___d121 } ;
assign m_xactor_from_master_f_rd_data$ENQ =
CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ;
assign m_xactor_from_master_f_rd_data$DEQ =
from_master_rready && m_xactor_from_master_f_rd_data$EMPTY_N ;
assign m_xactor_from_master_f_rd_data$CLR = m_rg_reset ;
// submodule m_xactor_from_master_f_wr_addr
assign m_xactor_from_master_f_wr_addr$D_IN =
{ from_master_awid,
from_master_awaddr,
from_master_awlen,
from_master_awsize,
from_master_awburst,
from_master_awlock,
from_master_awcache,
from_master_awprot,
from_master_awqos,
from_master_awregion } ;
assign m_xactor_from_master_f_wr_addr$ENQ =
from_master_awvalid && m_xactor_from_master_f_wr_addr$FULL_N ;
assign m_xactor_from_master_f_wr_addr$DEQ =
WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 ;
assign m_xactor_from_master_f_wr_addr$CLR = m_rg_reset ;
// submodule m_xactor_from_master_f_wr_data
assign m_xactor_from_master_f_wr_data$D_IN =
{ from_master_wdata, from_master_wstrb, from_master_wlast } ;
assign m_xactor_from_master_f_wr_data$ENQ =
from_master_wvalid && m_xactor_from_master_f_wr_data$FULL_N ;
assign m_xactor_from_master_f_wr_data$DEQ =
CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ;
assign m_xactor_from_master_f_wr_data$CLR = m_rg_reset ;
// submodule m_xactor_from_master_f_wr_resp
assign m_xactor_from_master_f_wr_resp$D_IN =
{ m_xactor_to_slave_f_wr_resp$D_OUT[5:2],
(m_rg_b_resp == 2'b0) ?
m_xactor_to_slave_f_wr_resp$D_OUT[1:0] :
m_rg_b_resp } ;
assign m_xactor_from_master_f_wr_resp$ENQ =
WILL_FIRE_RL_m_rl_wr_resp_slave_to_master &&
!m_rg_b_beat_count_5_ULT_m_f_w_awlen_first__6___d57 ;
assign m_xactor_from_master_f_wr_resp$DEQ =
from_master_bready && m_xactor_from_master_f_wr_resp$EMPTY_N ;
assign m_xactor_from_master_f_wr_resp$CLR = m_rg_reset ;
// submodule m_xactor_to_slave_f_rd_addr
assign m_xactor_to_slave_f_rd_addr$D_IN =
{ m_xactor_from_master_f_rd_addr$D_OUT[96:93],
a_out_araddr__h3025,
8'd0,
m_xactor_from_master_f_rd_addr$D_OUT[20:18],
2'b0,
m_xactor_from_master_f_rd_addr$D_OUT[15:0] } ;
assign m_xactor_to_slave_f_rd_addr$ENQ =
CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ;
assign m_xactor_to_slave_f_rd_addr$DEQ =
m_xactor_to_slave_f_rd_addr$EMPTY_N && to_slave_arready ;
assign m_xactor_to_slave_f_rd_addr$CLR = m_rg_reset ;
// submodule m_xactor_to_slave_f_rd_data
assign m_xactor_to_slave_f_rd_data$D_IN =
{ to_slave_rid,
to_slave_rdata,
to_slave_rresp,
to_slave_rlast } ;
assign m_xactor_to_slave_f_rd_data$ENQ =
to_slave_rvalid && m_xactor_to_slave_f_rd_data$FULL_N ;
assign m_xactor_to_slave_f_rd_data$DEQ =
CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ;
assign m_xactor_to_slave_f_rd_data$CLR = m_rg_reset ;
// submodule m_xactor_to_slave_f_wr_addr
assign m_xactor_to_slave_f_wr_addr$D_IN =
{ m_xactor_from_master_f_wr_addr$D_OUT[96:93],
a_out_awaddr__h1941,
8'd0,
m_xactor_from_master_f_wr_addr$D_OUT[20:18],
2'b0,
m_xactor_from_master_f_wr_addr$D_OUT[15:0] } ;
assign m_xactor_to_slave_f_wr_addr$ENQ =
CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ;
assign m_xactor_to_slave_f_wr_addr$DEQ =
m_xactor_to_slave_f_wr_addr$EMPTY_N && to_slave_awready ;
assign m_xactor_to_slave_f_wr_addr$CLR = m_rg_reset ;
// submodule m_xactor_to_slave_f_wr_data
assign m_xactor_to_slave_f_wr_data$D_IN =
{ m_xactor_from_master_f_wr_data$D_OUT[72:1], 1'd1 } ;
assign m_xactor_to_slave_f_wr_data$ENQ =
CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ;
assign m_xactor_to_slave_f_wr_data$DEQ =
m_xactor_to_slave_f_wr_data$EMPTY_N && to_slave_wready ;
assign m_xactor_to_slave_f_wr_data$CLR = m_rg_reset ;
// submodule m_xactor_to_slave_f_wr_resp
assign m_xactor_to_slave_f_wr_resp$D_IN = { to_slave_bid, to_slave_bresp } ;
assign m_xactor_to_slave_f_wr_resp$ENQ =
to_slave_bvalid && m_xactor_to_slave_f_wr_resp$FULL_N ;
assign m_xactor_to_slave_f_wr_resp$DEQ =
CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ;
assign m_xactor_to_slave_f_wr_resp$CLR = m_rg_reset ;
// remaining internal signals
assign a_out_araddr__h3025 =
(m_rg_ar_beat_count == 8'd0) ?
m_xactor_from_master_f_rd_addr$D_OUT[92:29] :
((m_xactor_from_master_f_rd_addr$D_OUT[17:16] == 2'b10) ?
addr___1__h3119 :
addr__h3107) ;
assign a_out_awaddr__h1941 =
(m_rg_w_beat_count == 8'd0) ?
m_xactor_from_master_f_wr_addr$D_OUT[92:29] :
((m_xactor_from_master_f_wr_addr$D_OUT[17:16] == 2'b10) ?
addr___1__h2035 :
addr__h2023) ;
assign addr___1__h2035 = x__h2047 | y__h2048 ;
assign addr___1__h3119 = x__h3131 | y__h3132 ;
assign addr__h2023 =
m_rg_last_beat_waddr +
(64'd1 << m_xactor_from_master_f_wr_addr$D_OUT[20:18]) ;
assign addr__h3107 =
m_rg_last_beat_raddr +
(64'd1 << m_xactor_from_master_f_rd_addr$D_OUT[20:18]) ;
assign burst_len__h2024 =
{ 56'd0, m_xactor_from_master_f_wr_addr$D_OUT[28:21] } + 64'd1 ;
assign burst_len__h3108 =
{ 56'd0, m_xactor_from_master_f_rd_addr$D_OUT[28:21] } + 64'd1 ;
assign m_rg_ar_beat_count_9_ULT_m_xactor_from_master__ETC___d110 =
m_rg_ar_beat_count <
m_xactor_from_master_f_rd_addr$D_OUT[28:21] ;
assign m_rg_b_beat_count_5_ULT_m_f_w_awlen_first__6___d57 =
m_rg_b_beat_count < m_f_w_awlen$D_OUT ;
assign m_rg_r_beat_count_19_ULT_m_f_r_arlen_first__20___d121 =
m_rg_r_beat_count < m_f_r_arlen$D_OUT ;
assign m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 =
m_rg_w_beat_count < m_xactor_from_master_f_wr_addr$D_OUT[28:21] ;
assign wrap_mask__h2025 =
(burst_len__h2024 <<
m_xactor_from_master_f_wr_addr$D_OUT[20:18]) -
64'd1 ;
assign wrap_mask__h3109 =
(burst_len__h3108 <<
m_xactor_from_master_f_rd_addr$D_OUT[20:18]) -
64'd1 ;
assign x__h2047 = m_rg_last_beat_waddr & y__h2049 ;
assign x__h2322 = m_rg_w_beat_count + 8'd1 ;
assign x__h2829 = m_rg_b_beat_count + 8'd1 ;
assign x__h3131 = m_rg_last_beat_raddr & y__h3133 ;
assign x__h3316 = m_rg_ar_beat_count + 8'd1 ;
assign x__h3535 = m_rg_r_beat_count + 8'd1 ;
assign y__h2048 = addr__h2023 & wrap_mask__h2025 ;
assign y__h2049 = ~wrap_mask__h2025 ;
assign y__h3132 = addr__h3107 & wrap_mask__h3109 ;
assign y__h3133 = ~wrap_mask__h3109 ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0;
m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0;
m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY 2'b0;
m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0;
m_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1;
m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (m_rg_ar_beat_count$EN)
m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_ar_beat_count$D_IN;
if (m_rg_b_beat_count$EN)
m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_b_beat_count$D_IN;
if (m_rg_b_resp$EN)
m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY m_rg_b_resp$D_IN;
if (m_rg_r_beat_count$EN)
m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_r_beat_count$D_IN;
if (m_rg_reset$EN)
m_rg_reset <= `BSV_ASSIGNMENT_DELAY m_rg_reset$D_IN;
if (m_rg_w_beat_count$EN)
m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_w_beat_count$D_IN;
end
if (m_rg_last_beat_raddr$EN)
m_rg_last_beat_raddr <= `BSV_ASSIGNMENT_DELAY m_rg_last_beat_raddr$D_IN;
if (m_rg_last_beat_waddr$EN)
m_rg_last_beat_waddr <= `BSV_ASSIGNMENT_DELAY m_rg_last_beat_waddr$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
m_rg_ar_beat_count = 8'hAA;
m_rg_b_beat_count = 8'hAA;
m_rg_b_resp = 2'h2;
m_rg_last_beat_raddr = 64'hAAAAAAAAAAAAAAAA;
m_rg_last_beat_waddr = 64'hAAAAAAAAAAAAAAAA;
m_rg_r_beat_count = 8'hAA;
m_rg_reset = 1'h0;
m_rg_w_beat_count = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
begin
v__h2464 = $stime;
#0;
end
v__h2458 = v__h2464 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$display("%0d: ERROR: %m::AXI4_Deburster.rl_wr_xaction_master_to_slave: m -> s",
v__h2458);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$display(" WLAST not set on last data beat (awlen = %0d)",
m_xactor_from_master_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write("\n");
end
// synopsys translate_on
endmodule // mkAXI4_Deburster_A
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_envelope_generator.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU length counter; building block used by several other APU components. Provides automatic
* duration control for the NES APU waveform channels. Once loaded with a value, it can optionally
* count down and silence the channel when it reaches zero.
***************************************************************************************************/
module apu_envelope_generator
(
input clk_in, // system clock signal
input rst_in, // reset signal
input eg_pulse_in, // 1 clk pulse for every env gen update
input [5:0] env_in, // envelope value (e.g., via $4000)
input env_wr_in, // envelope value write
input env_restart, // envelope restart
output [3:0] env_out // output volume
);
reg [5:0] q_reg;
wire [5:0] d_reg;
reg [3:0] q_cnt, d_cnt;
reg q_start_flag, d_start_flag;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_reg <= 6'h00;
q_cnt <= 4'h0;
q_start_flag <= 1'b0;
end
else
begin
q_reg <= d_reg;
q_cnt <= d_cnt;
q_start_flag <= d_start_flag;
end
end
reg divider_pulse_in;
reg divider_reload;
wire divider_pulse_out;
apu_div #(.PERIOD_BITS(4)) divider(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(divider_pulse_in),
.reload_in(divider_reload),
.period_in(q_reg[3:0]),
.pulse_out(divider_pulse_out)
);
always @*
begin
d_cnt = q_cnt;
d_start_flag = q_start_flag;
divider_pulse_in = 1'b0;
divider_reload = 1'b0;
// When the divider outputs a clock, one of two actions occurs: If the counter is non-zero, it
// is decremented, otherwise if the loop flag is set, the counter is loaded with 15.
if (divider_pulse_out)
begin
divider_reload = 1'b1;
if (q_cnt != 4'h0)
d_cnt = q_cnt - 4'h1;
else if (q_reg[5])
d_cnt = 4'hF;
end
// When clocked by the frame counter, one of two actions occurs: if the start flag is clear,
// the divider is clocked, otherwise the start flag is cleared, the counter is loaded with 15,
// and the divider's period is immediately reloaded.
if (eg_pulse_in)
begin
if (q_start_flag == 1'b0)
begin
divider_pulse_in = 1'b1;
end
else
begin
d_start_flag = 1'b0;
d_cnt = 4'hF;
end
end
if (env_restart)
d_start_flag = 1'b1;
end
assign d_reg = (env_wr_in) ? env_in : q_reg;
// The envelope unit's volume output depends on the constant volume flag: if set, the envelope
// parameter directly sets the volume, otherwise the counter's value is the current volume.
assign env_out = (q_reg[4]) ? q_reg[3:0] : q_cnt;
endmodule
|
//==================================================================================================
// Filename : subRecursiveKOA_1c.v
// Created On : 2016-10-27 23:29:04
// Last Modified : 2016-10-28 08:14:58
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`include "global.v"
module csubRecursiveKOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 8)
(
// input wire clk,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] Data_S_o
);
localparam integer STOP_CONT = `STOP_CONT;
generate
//assign i = Stop_I;
if (SW <= STOP_CONT) begin : GENSTOP
cmult #(.SW(SW))
inst_cmult (
// .clk(clk),
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.Data_S_o(Data_S_o)
);
end else begin : RECURSIVE
reg [2*SW-1:0] sgf_result_o;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
localparam half = SW/2;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
reg [SW-1:0] Q_left;
reg [SW-1:0] Q_right;
reg [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
always @* begin : EVEN11
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
sgf_result_o <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
csubRecursiveKOA #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
csubRecursiveKOA #(.SW(SW/2)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
csubRecursiveKOA #(.SW((SW/2)+1)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
assign Data_S_o = sgf_result_o;
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
always @* begin : ODD11
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
sgf_result_o<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
assign Data_S_o = sgf_result_o;
csubRecursiveKOA #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
csubRecursiveKOA #(.SW((SW/2)+1)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
csubRecursiveKOA #(.SW((SW/2)+2)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
end
endcase
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_TB_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_TB_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkdlybuf4s18.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__clkdlybuf4s18 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND2_SYMBOL_V
`define SKY130_FD_SC_LS__TAPVGND2_SYMBOL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND2_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 10:58:35 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/system_vga_hessian_0_0_sim_netlist.v
// Design : system_vga_hessian_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_hessian_0_0,vga_hessian,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_hessian,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_hessian_0_0
(clk_x16,
active,
rst,
x_addr,
y_addr,
g_in,
hessian_out);
input clk_x16;
input active;
(* x_interface_info = "xilinx.com:signal:reset:1.0 rst RST" *) input rst;
input [9:0]x_addr;
input [9:0]y_addr;
input [7:0]g_in;
output [31:0]hessian_out;
wire active;
wire clk_x16;
wire [7:0]g_in;
wire [31:0]hessian_out;
wire rst;
wire [9:0]x_addr;
wire [9:0]y_addr;
system_vga_hessian_0_0_vga_hessian U0
(.active(active),
.clk_x16(clk_x16),
.g_in(g_in),
.hessian_out(hessian_out),
.rst(rst),
.x_addr(x_addr),
.y_addr(y_addr));
endmodule
(* CHECK_LICENSE_TYPE = "blk_mem_gen_0,blk_mem_gen_v8_3_5,{}" *) (* ORIG_REF_NAME = "blk_mem_gen_0" *) (* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module system_vga_hessian_0_0_blk_mem_gen_0
(clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [13:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [15:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [15:0]douta;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input clkb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *) input enb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *) input [0:0]web;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [13:0]addrb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *) input [15:0]dinb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [15:0]doutb;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [13:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [13:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [15:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "14" *)
(* C_ADDRB_WIDTH = "14" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "7" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 22.1485 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "1" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "1" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "blk_mem_gen_0.mem" *)
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "0" *)
(* C_MEM_TYPE = "2" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "16384" *)
(* C_READ_DEPTH_B = "16384" *)
(* C_READ_WIDTH_A = "16" *)
(* C_READ_WIDTH_B = "16" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "16384" *)
(* C_WRITE_DEPTH_B = "16384" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "16" *)
(* C_WRITE_WIDTH_B = "16" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
system_vga_hessian_0_0_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.eccpipece(1'b0),
.ena(ena),
.enb(enb),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[13:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[13:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[15:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "vga_hessian" *)
module system_vga_hessian_0_0_vga_hessian
(hessian_out,
clk_x16,
rst,
active,
x_addr,
y_addr,
g_in);
output [31:0]hessian_out;
input clk_x16;
input rst;
input active;
input [9:0]x_addr;
input [9:0]y_addr;
input [7:0]g_in;
wire [15:0]A;
wire [15:0]B;
wire Lxx;
wire Lxx0_carry__0_i_1_n_0;
wire Lxx0_carry__0_i_2_n_0;
wire Lxx0_carry__0_i_3_n_0;
wire Lxx0_carry__0_i_4_n_0;
wire Lxx0_carry__0_i_5_n_0;
wire Lxx0_carry__0_i_6_n_0;
wire Lxx0_carry__0_i_7_n_0;
wire Lxx0_carry__0_i_8_n_0;
wire Lxx0_carry__0_n_0;
wire Lxx0_carry__0_n_1;
wire Lxx0_carry__0_n_2;
wire Lxx0_carry__0_n_3;
wire Lxx0_carry__1_i_1_n_0;
wire Lxx0_carry__1_i_2_n_0;
wire Lxx0_carry__1_i_3_n_0;
wire Lxx0_carry__1_i_4_n_0;
wire Lxx0_carry__1_i_5_n_0;
wire Lxx0_carry__1_i_6_n_0;
wire Lxx0_carry__1_i_7_n_0;
wire Lxx0_carry__1_i_8_n_0;
wire Lxx0_carry__1_n_0;
wire Lxx0_carry__1_n_1;
wire Lxx0_carry__1_n_2;
wire Lxx0_carry__1_n_3;
wire Lxx0_carry__2_i_1_n_0;
wire Lxx0_carry__2_i_2_n_0;
wire Lxx0_carry__2_i_3_n_0;
wire Lxx0_carry__2_i_4_n_0;
wire Lxx0_carry__2_i_5_n_0;
wire Lxx0_carry__2_i_6_n_0;
wire Lxx0_carry__2_i_7_n_0;
wire Lxx0_carry__2_n_1;
wire Lxx0_carry__2_n_2;
wire Lxx0_carry__2_n_3;
wire Lxx0_carry_i_1_n_0;
wire Lxx0_carry_i_2_n_0;
wire Lxx0_carry_i_3_n_0;
wire Lxx0_carry_i_4_n_0;
wire Lxx0_carry_i_5_n_0;
wire Lxx0_carry_i_6_n_0;
wire Lxx0_carry_n_0;
wire Lxx0_carry_n_1;
wire Lxx0_carry_n_2;
wire Lxx0_carry_n_3;
wire [15:0]Lxx_0;
wire [15:0]Lxx_00;
wire Lxx_00__1_carry__0_i_10_n_0;
wire Lxx_00__1_carry__0_i_11_n_0;
wire Lxx_00__1_carry__0_i_12_n_0;
wire Lxx_00__1_carry__0_i_1_n_0;
wire Lxx_00__1_carry__0_i_2_n_0;
wire Lxx_00__1_carry__0_i_3_n_0;
wire Lxx_00__1_carry__0_i_4_n_0;
wire Lxx_00__1_carry__0_i_5_n_0;
wire Lxx_00__1_carry__0_i_6_n_0;
wire Lxx_00__1_carry__0_i_7_n_0;
wire Lxx_00__1_carry__0_i_8_n_0;
wire Lxx_00__1_carry__0_i_9_n_0;
wire Lxx_00__1_carry__0_n_0;
wire Lxx_00__1_carry__0_n_1;
wire Lxx_00__1_carry__0_n_2;
wire Lxx_00__1_carry__0_n_3;
wire Lxx_00__1_carry__1_i_10_n_0;
wire Lxx_00__1_carry__1_i_11_n_0;
wire Lxx_00__1_carry__1_i_12_n_0;
wire Lxx_00__1_carry__1_i_1_n_0;
wire Lxx_00__1_carry__1_i_2_n_0;
wire Lxx_00__1_carry__1_i_3_n_0;
wire Lxx_00__1_carry__1_i_4_n_0;
wire Lxx_00__1_carry__1_i_5_n_0;
wire Lxx_00__1_carry__1_i_6_n_0;
wire Lxx_00__1_carry__1_i_7_n_0;
wire Lxx_00__1_carry__1_i_8_n_0;
wire Lxx_00__1_carry__1_i_9_n_0;
wire Lxx_00__1_carry__1_n_0;
wire Lxx_00__1_carry__1_n_1;
wire Lxx_00__1_carry__1_n_2;
wire Lxx_00__1_carry__1_n_3;
wire Lxx_00__1_carry__2_i_10_n_0;
wire Lxx_00__1_carry__2_i_11_n_0;
wire Lxx_00__1_carry__2_i_12_n_0;
wire Lxx_00__1_carry__2_i_1_n_0;
wire Lxx_00__1_carry__2_i_2_n_0;
wire Lxx_00__1_carry__2_i_3_n_0;
wire Lxx_00__1_carry__2_i_4_n_0;
wire Lxx_00__1_carry__2_i_5_n_0;
wire Lxx_00__1_carry__2_i_6_n_0;
wire Lxx_00__1_carry__2_i_7_n_0;
wire Lxx_00__1_carry__2_i_8_n_0;
wire Lxx_00__1_carry__2_i_9_n_0;
wire Lxx_00__1_carry__2_n_1;
wire Lxx_00__1_carry__2_n_2;
wire Lxx_00__1_carry__2_n_3;
wire Lxx_00__1_carry_i_1_n_0;
wire Lxx_00__1_carry_i_2_n_0;
wire Lxx_00__1_carry_i_3_n_0;
wire Lxx_00__1_carry_i_4_n_0;
wire Lxx_00__1_carry_i_5_n_0;
wire Lxx_00__1_carry_i_6_n_0;
wire Lxx_00__1_carry_i_7_n_0;
wire Lxx_00__1_carry_i_8_n_0;
wire Lxx_00__1_carry_i_9_n_0;
wire Lxx_00__1_carry_n_0;
wire Lxx_00__1_carry_n_1;
wire Lxx_00__1_carry_n_2;
wire Lxx_00__1_carry_n_3;
wire [15:1]Lxx_1;
wire [15:0]Lxx_11;
wire Lxx_11__1_carry__0_i_10_n_0;
wire Lxx_11__1_carry__0_i_11_n_0;
wire Lxx_11__1_carry__0_i_12_n_0;
wire Lxx_11__1_carry__0_i_1_n_0;
wire Lxx_11__1_carry__0_i_2_n_0;
wire Lxx_11__1_carry__0_i_3_n_0;
wire Lxx_11__1_carry__0_i_4_n_0;
wire Lxx_11__1_carry__0_i_5_n_0;
wire Lxx_11__1_carry__0_i_6_n_0;
wire Lxx_11__1_carry__0_i_7_n_0;
wire Lxx_11__1_carry__0_i_8_n_0;
wire Lxx_11__1_carry__0_i_9_n_0;
wire Lxx_11__1_carry__0_n_0;
wire Lxx_11__1_carry__0_n_1;
wire Lxx_11__1_carry__0_n_2;
wire Lxx_11__1_carry__0_n_3;
wire Lxx_11__1_carry__1_i_10_n_0;
wire Lxx_11__1_carry__1_i_11_n_0;
wire Lxx_11__1_carry__1_i_12_n_0;
wire Lxx_11__1_carry__1_i_1_n_0;
wire Lxx_11__1_carry__1_i_2_n_0;
wire Lxx_11__1_carry__1_i_3_n_0;
wire Lxx_11__1_carry__1_i_4_n_0;
wire Lxx_11__1_carry__1_i_5_n_0;
wire Lxx_11__1_carry__1_i_6_n_0;
wire Lxx_11__1_carry__1_i_7_n_0;
wire Lxx_11__1_carry__1_i_8_n_0;
wire Lxx_11__1_carry__1_i_9_n_0;
wire Lxx_11__1_carry__1_n_0;
wire Lxx_11__1_carry__1_n_1;
wire Lxx_11__1_carry__1_n_2;
wire Lxx_11__1_carry__1_n_3;
wire Lxx_11__1_carry__2_i_10_n_0;
wire Lxx_11__1_carry__2_i_11_n_0;
wire Lxx_11__1_carry__2_i_12_n_0;
wire Lxx_11__1_carry__2_i_1_n_0;
wire Lxx_11__1_carry__2_i_2_n_0;
wire Lxx_11__1_carry__2_i_3_n_0;
wire Lxx_11__1_carry__2_i_4_n_0;
wire Lxx_11__1_carry__2_i_5_n_0;
wire Lxx_11__1_carry__2_i_6_n_0;
wire Lxx_11__1_carry__2_i_7_n_0;
wire Lxx_11__1_carry__2_i_8_n_0;
wire Lxx_11__1_carry__2_i_9_n_0;
wire Lxx_11__1_carry__2_n_1;
wire Lxx_11__1_carry__2_n_2;
wire Lxx_11__1_carry__2_n_3;
wire Lxx_11__1_carry_i_1_n_0;
wire Lxx_11__1_carry_i_2_n_0;
wire Lxx_11__1_carry_i_3_n_0;
wire Lxx_11__1_carry_i_4_n_0;
wire Lxx_11__1_carry_i_5_n_0;
wire Lxx_11__1_carry_i_6_n_0;
wire Lxx_11__1_carry_i_7_n_0;
wire Lxx_11__1_carry_i_8_n_0;
wire Lxx_11__1_carry_i_9_n_0;
wire Lxx_11__1_carry_n_0;
wire Lxx_11__1_carry_n_1;
wire Lxx_11__1_carry_n_2;
wire Lxx_11__1_carry_n_3;
wire \Lxx_2[15]_i_1_n_0 ;
wire \Lxx_2_reg_n_0_[0] ;
wire \Lxx_2_reg_n_0_[10] ;
wire \Lxx_2_reg_n_0_[11] ;
wire \Lxx_2_reg_n_0_[12] ;
wire \Lxx_2_reg_n_0_[13] ;
wire \Lxx_2_reg_n_0_[14] ;
wire \Lxx_2_reg_n_0_[15] ;
wire \Lxx_2_reg_n_0_[1] ;
wire \Lxx_2_reg_n_0_[2] ;
wire \Lxx_2_reg_n_0_[3] ;
wire \Lxx_2_reg_n_0_[4] ;
wire \Lxx_2_reg_n_0_[5] ;
wire \Lxx_2_reg_n_0_[6] ;
wire \Lxx_2_reg_n_0_[7] ;
wire \Lxx_2_reg_n_0_[8] ;
wire \Lxx_2_reg_n_0_[9] ;
wire Lxy0__1_carry__0_i_10_n_0;
wire Lxy0__1_carry__0_i_11_n_0;
wire Lxy0__1_carry__0_i_12_n_0;
wire Lxy0__1_carry__0_i_1_n_0;
wire Lxy0__1_carry__0_i_2_n_0;
wire Lxy0__1_carry__0_i_3_n_0;
wire Lxy0__1_carry__0_i_4_n_0;
wire Lxy0__1_carry__0_i_5_n_0;
wire Lxy0__1_carry__0_i_6_n_0;
wire Lxy0__1_carry__0_i_7_n_0;
wire Lxy0__1_carry__0_i_8_n_0;
wire Lxy0__1_carry__0_i_9_n_0;
wire Lxy0__1_carry__0_n_0;
wire Lxy0__1_carry__0_n_1;
wire Lxy0__1_carry__0_n_2;
wire Lxy0__1_carry__0_n_3;
wire Lxy0__1_carry__0_n_4;
wire Lxy0__1_carry__0_n_5;
wire Lxy0__1_carry__0_n_6;
wire Lxy0__1_carry__0_n_7;
wire Lxy0__1_carry__1_i_10_n_0;
wire Lxy0__1_carry__1_i_11_n_0;
wire Lxy0__1_carry__1_i_12_n_0;
wire Lxy0__1_carry__1_i_1_n_0;
wire Lxy0__1_carry__1_i_2_n_0;
wire Lxy0__1_carry__1_i_3_n_0;
wire Lxy0__1_carry__1_i_4_n_0;
wire Lxy0__1_carry__1_i_5_n_0;
wire Lxy0__1_carry__1_i_6_n_0;
wire Lxy0__1_carry__1_i_7_n_0;
wire Lxy0__1_carry__1_i_8_n_0;
wire Lxy0__1_carry__1_i_9_n_0;
wire Lxy0__1_carry__1_n_0;
wire Lxy0__1_carry__1_n_1;
wire Lxy0__1_carry__1_n_2;
wire Lxy0__1_carry__1_n_3;
wire Lxy0__1_carry__1_n_4;
wire Lxy0__1_carry__1_n_5;
wire Lxy0__1_carry__1_n_6;
wire Lxy0__1_carry__1_n_7;
wire Lxy0__1_carry__2_i_10_n_0;
wire Lxy0__1_carry__2_i_11_n_0;
wire Lxy0__1_carry__2_i_12_n_0;
wire Lxy0__1_carry__2_i_1_n_0;
wire Lxy0__1_carry__2_i_2_n_0;
wire Lxy0__1_carry__2_i_3_n_0;
wire Lxy0__1_carry__2_i_4_n_0;
wire Lxy0__1_carry__2_i_5_n_0;
wire Lxy0__1_carry__2_i_6_n_0;
wire Lxy0__1_carry__2_i_7_n_0;
wire Lxy0__1_carry__2_i_8_n_0;
wire Lxy0__1_carry__2_i_9_n_0;
wire Lxy0__1_carry__2_n_1;
wire Lxy0__1_carry__2_n_2;
wire Lxy0__1_carry__2_n_3;
wire Lxy0__1_carry__2_n_4;
wire Lxy0__1_carry__2_n_5;
wire Lxy0__1_carry__2_n_6;
wire Lxy0__1_carry__2_n_7;
wire Lxy0__1_carry_i_10_n_0;
wire Lxy0__1_carry_i_1_n_0;
wire Lxy0__1_carry_i_2_n_0;
wire Lxy0__1_carry_i_3_n_0;
wire Lxy0__1_carry_i_4_n_0;
wire Lxy0__1_carry_i_5_n_0;
wire Lxy0__1_carry_i_6_n_0;
wire Lxy0__1_carry_i_7_n_0;
wire Lxy0__1_carry_i_8_n_0;
wire Lxy0__1_carry_i_9_n_0;
wire Lxy0__1_carry_n_0;
wire Lxy0__1_carry_n_1;
wire Lxy0__1_carry_n_2;
wire Lxy0__1_carry_n_3;
wire Lxy0__1_carry_n_4;
wire Lxy0__1_carry_n_5;
wire Lxy0__1_carry_n_6;
wire Lxy0__1_carry_n_7;
wire \Lxy_0[15]_i_1_n_0 ;
wire \Lxy_0_reg_n_0_[0] ;
wire \Lxy_0_reg_n_0_[10] ;
wire \Lxy_0_reg_n_0_[11] ;
wire \Lxy_0_reg_n_0_[12] ;
wire \Lxy_0_reg_n_0_[13] ;
wire \Lxy_0_reg_n_0_[14] ;
wire \Lxy_0_reg_n_0_[15] ;
wire \Lxy_0_reg_n_0_[1] ;
wire \Lxy_0_reg_n_0_[2] ;
wire \Lxy_0_reg_n_0_[3] ;
wire \Lxy_0_reg_n_0_[4] ;
wire \Lxy_0_reg_n_0_[5] ;
wire \Lxy_0_reg_n_0_[6] ;
wire \Lxy_0_reg_n_0_[7] ;
wire \Lxy_0_reg_n_0_[8] ;
wire \Lxy_0_reg_n_0_[9] ;
wire Lxy_1;
wire \Lxy_1_reg_n_0_[0] ;
wire \Lxy_1_reg_n_0_[10] ;
wire \Lxy_1_reg_n_0_[11] ;
wire \Lxy_1_reg_n_0_[12] ;
wire \Lxy_1_reg_n_0_[13] ;
wire \Lxy_1_reg_n_0_[14] ;
wire \Lxy_1_reg_n_0_[15] ;
wire \Lxy_1_reg_n_0_[1] ;
wire \Lxy_1_reg_n_0_[2] ;
wire \Lxy_1_reg_n_0_[3] ;
wire \Lxy_1_reg_n_0_[4] ;
wire \Lxy_1_reg_n_0_[5] ;
wire \Lxy_1_reg_n_0_[6] ;
wire \Lxy_1_reg_n_0_[7] ;
wire \Lxy_1_reg_n_0_[8] ;
wire \Lxy_1_reg_n_0_[9] ;
wire [15:0]Lxy_2;
wire [15:0]Lxy_3;
wire Lyy0_carry__0_i_1_n_0;
wire Lyy0_carry__0_i_2_n_0;
wire Lyy0_carry__0_i_3_n_0;
wire Lyy0_carry__0_i_4_n_0;
wire Lyy0_carry__0_i_5_n_0;
wire Lyy0_carry__0_i_6_n_0;
wire Lyy0_carry__0_i_7_n_0;
wire Lyy0_carry__0_i_8_n_0;
wire Lyy0_carry__0_n_0;
wire Lyy0_carry__0_n_1;
wire Lyy0_carry__0_n_2;
wire Lyy0_carry__0_n_3;
wire Lyy0_carry__1_i_1_n_0;
wire Lyy0_carry__1_i_2_n_0;
wire Lyy0_carry__1_i_3_n_0;
wire Lyy0_carry__1_i_4_n_0;
wire Lyy0_carry__1_i_5_n_0;
wire Lyy0_carry__1_i_6_n_0;
wire Lyy0_carry__1_i_7_n_0;
wire Lyy0_carry__1_i_8_n_0;
wire Lyy0_carry__1_n_0;
wire Lyy0_carry__1_n_1;
wire Lyy0_carry__1_n_2;
wire Lyy0_carry__1_n_3;
wire Lyy0_carry__2_i_1_n_0;
wire Lyy0_carry__2_i_2_n_0;
wire Lyy0_carry__2_i_3_n_0;
wire Lyy0_carry__2_i_4_n_0;
wire Lyy0_carry__2_i_5_n_0;
wire Lyy0_carry__2_i_6_n_0;
wire Lyy0_carry__2_i_7_n_0;
wire Lyy0_carry__2_n_1;
wire Lyy0_carry__2_n_2;
wire Lyy0_carry__2_n_3;
wire Lyy0_carry_i_1_n_0;
wire Lyy0_carry_i_2_n_0;
wire Lyy0_carry_i_3_n_0;
wire Lyy0_carry_i_4_n_0;
wire Lyy0_carry_i_5_n_0;
wire Lyy0_carry_i_6_n_0;
wire Lyy0_carry_n_0;
wire Lyy0_carry_n_1;
wire Lyy0_carry_n_2;
wire Lyy0_carry_n_3;
wire Lyy_0;
wire \Lyy_0_reg_n_0_[0] ;
wire \Lyy_0_reg_n_0_[10] ;
wire \Lyy_0_reg_n_0_[11] ;
wire \Lyy_0_reg_n_0_[12] ;
wire \Lyy_0_reg_n_0_[13] ;
wire \Lyy_0_reg_n_0_[14] ;
wire \Lyy_0_reg_n_0_[15] ;
wire \Lyy_0_reg_n_0_[1] ;
wire \Lyy_0_reg_n_0_[2] ;
wire \Lyy_0_reg_n_0_[3] ;
wire \Lyy_0_reg_n_0_[4] ;
wire \Lyy_0_reg_n_0_[5] ;
wire \Lyy_0_reg_n_0_[6] ;
wire \Lyy_0_reg_n_0_[7] ;
wire \Lyy_0_reg_n_0_[8] ;
wire \Lyy_0_reg_n_0_[9] ;
wire [15:1]Lyy_1;
wire [15:0]Lyy_20;
wire Lyy_20__1_carry__0_i_10_n_0;
wire Lyy_20__1_carry__0_i_11_n_0;
wire Lyy_20__1_carry__0_i_12_n_0;
wire Lyy_20__1_carry__0_i_1_n_0;
wire Lyy_20__1_carry__0_i_2_n_0;
wire Lyy_20__1_carry__0_i_3_n_0;
wire Lyy_20__1_carry__0_i_4_n_0;
wire Lyy_20__1_carry__0_i_5_n_0;
wire Lyy_20__1_carry__0_i_6_n_0;
wire Lyy_20__1_carry__0_i_7_n_0;
wire Lyy_20__1_carry__0_i_8_n_0;
wire Lyy_20__1_carry__0_i_9_n_0;
wire Lyy_20__1_carry__0_n_0;
wire Lyy_20__1_carry__0_n_1;
wire Lyy_20__1_carry__0_n_2;
wire Lyy_20__1_carry__0_n_3;
wire Lyy_20__1_carry__1_i_10_n_0;
wire Lyy_20__1_carry__1_i_11_n_0;
wire Lyy_20__1_carry__1_i_12_n_0;
wire Lyy_20__1_carry__1_i_1_n_0;
wire Lyy_20__1_carry__1_i_2_n_0;
wire Lyy_20__1_carry__1_i_3_n_0;
wire Lyy_20__1_carry__1_i_4_n_0;
wire Lyy_20__1_carry__1_i_5_n_0;
wire Lyy_20__1_carry__1_i_6_n_0;
wire Lyy_20__1_carry__1_i_7_n_0;
wire Lyy_20__1_carry__1_i_8_n_0;
wire Lyy_20__1_carry__1_i_9_n_0;
wire Lyy_20__1_carry__1_n_0;
wire Lyy_20__1_carry__1_n_1;
wire Lyy_20__1_carry__1_n_2;
wire Lyy_20__1_carry__1_n_3;
wire Lyy_20__1_carry__2_i_10_n_0;
wire Lyy_20__1_carry__2_i_11_n_0;
wire Lyy_20__1_carry__2_i_1_n_0;
wire Lyy_20__1_carry__2_i_2_n_0;
wire Lyy_20__1_carry__2_i_3_n_0;
wire Lyy_20__1_carry__2_i_4_n_0;
wire Lyy_20__1_carry__2_i_5_n_0;
wire Lyy_20__1_carry__2_i_6_n_0;
wire Lyy_20__1_carry__2_i_7_n_0;
wire Lyy_20__1_carry__2_i_8_n_0;
wire Lyy_20__1_carry__2_i_9_n_0;
wire Lyy_20__1_carry__2_n_1;
wire Lyy_20__1_carry__2_n_2;
wire Lyy_20__1_carry__2_n_3;
wire Lyy_20__1_carry_i_1_n_0;
wire Lyy_20__1_carry_i_2_n_0;
wire Lyy_20__1_carry_i_3_n_0;
wire Lyy_20__1_carry_i_4_n_0;
wire Lyy_20__1_carry_i_5_n_0;
wire Lyy_20__1_carry_i_6_n_0;
wire Lyy_20__1_carry_i_7_n_0;
wire Lyy_20__1_carry_i_8_n_0;
wire Lyy_20__1_carry_i_9_n_0;
wire Lyy_20__1_carry_n_0;
wire Lyy_20__1_carry_n_1;
wire Lyy_20__1_carry_n_2;
wire Lyy_20__1_carry_n_3;
wire \Lyy_2[15]_i_1_n_0 ;
wire [15:0]Lyy_2_bottom_left;
wire [15:0]Lyy_2_bottom_right;
wire [15:0]Lyy_2_bottom_right01_out;
wire Lyy_2_bottom_right0__0_carry__0_i_10_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_11_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_12_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_1_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_2_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_3_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_4_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_5_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_6_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_7_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_8_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_9_n_0;
wire Lyy_2_bottom_right0__0_carry__0_n_0;
wire Lyy_2_bottom_right0__0_carry__0_n_1;
wire Lyy_2_bottom_right0__0_carry__0_n_2;
wire Lyy_2_bottom_right0__0_carry__0_n_3;
wire Lyy_2_bottom_right0__0_carry__1_i_10_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_11_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_12_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_1_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_2_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_3_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_4_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_5_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_6_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_7_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_8_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_9_n_0;
wire Lyy_2_bottom_right0__0_carry__1_n_0;
wire Lyy_2_bottom_right0__0_carry__1_n_1;
wire Lyy_2_bottom_right0__0_carry__1_n_2;
wire Lyy_2_bottom_right0__0_carry__1_n_3;
wire Lyy_2_bottom_right0__0_carry__2_i_10_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_11_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_12_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_1_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_2_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_3_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_4_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_5_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_6_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_7_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_8_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_9_n_0;
wire Lyy_2_bottom_right0__0_carry__2_n_1;
wire Lyy_2_bottom_right0__0_carry__2_n_2;
wire Lyy_2_bottom_right0__0_carry__2_n_3;
wire Lyy_2_bottom_right0__0_carry_i_10_n_0;
wire Lyy_2_bottom_right0__0_carry_i_11_n_0;
wire Lyy_2_bottom_right0__0_carry_i_1_n_0;
wire Lyy_2_bottom_right0__0_carry_i_2_n_0;
wire Lyy_2_bottom_right0__0_carry_i_3_n_0;
wire Lyy_2_bottom_right0__0_carry_i_4_n_0;
wire Lyy_2_bottom_right0__0_carry_i_5_n_0;
wire Lyy_2_bottom_right0__0_carry_i_6_n_0;
wire Lyy_2_bottom_right0__0_carry_i_7_n_0;
wire Lyy_2_bottom_right0__0_carry_i_8_n_0;
wire Lyy_2_bottom_right0__0_carry_i_9_n_0;
wire Lyy_2_bottom_right0__0_carry_n_0;
wire Lyy_2_bottom_right0__0_carry_n_1;
wire Lyy_2_bottom_right0__0_carry_n_2;
wire Lyy_2_bottom_right0__0_carry_n_3;
wire \Lyy_2_reg_n_0_[0] ;
wire \Lyy_2_reg_n_0_[10] ;
wire \Lyy_2_reg_n_0_[11] ;
wire \Lyy_2_reg_n_0_[12] ;
wire \Lyy_2_reg_n_0_[13] ;
wire \Lyy_2_reg_n_0_[14] ;
wire \Lyy_2_reg_n_0_[15] ;
wire \Lyy_2_reg_n_0_[1] ;
wire \Lyy_2_reg_n_0_[2] ;
wire \Lyy_2_reg_n_0_[3] ;
wire \Lyy_2_reg_n_0_[4] ;
wire \Lyy_2_reg_n_0_[5] ;
wire \Lyy_2_reg_n_0_[6] ;
wire \Lyy_2_reg_n_0_[7] ;
wire \Lyy_2_reg_n_0_[8] ;
wire \Lyy_2_reg_n_0_[9] ;
wire [15:0]Lyy_2_top_left;
wire [15:0]Lyy_2_top_right;
wire active;
wire addr_0;
wire \addr_0[0]_i_1_n_0 ;
wire \addr_0[10]_i_1_n_0 ;
wire \addr_0[11]_i_1_n_0 ;
wire \addr_0[12]_i_1_n_0 ;
wire \addr_0[13]_i_2_n_0 ;
wire \addr_0[1]_i_1_n_0 ;
wire \addr_0[2]_i_1_n_0 ;
wire \addr_0[3]_i_1_n_0 ;
wire \addr_0[4]_i_1_n_0 ;
wire \addr_0[5]_i_1_n_0 ;
wire \addr_0[6]_i_1_n_0 ;
wire \addr_0[7]_i_1_n_0 ;
wire \addr_0[8]_i_1_n_0 ;
wire \addr_0[9]_i_1_n_0 ;
wire \addr_0_reg_n_0_[0] ;
wire \addr_0_reg_n_0_[10] ;
wire \addr_0_reg_n_0_[11] ;
wire \addr_0_reg_n_0_[12] ;
wire \addr_0_reg_n_0_[13] ;
wire \addr_0_reg_n_0_[1] ;
wire \addr_0_reg_n_0_[2] ;
wire \addr_0_reg_n_0_[3] ;
wire \addr_0_reg_n_0_[4] ;
wire \addr_0_reg_n_0_[5] ;
wire \addr_0_reg_n_0_[6] ;
wire \addr_0_reg_n_0_[7] ;
wire \addr_0_reg_n_0_[8] ;
wire \addr_0_reg_n_0_[9] ;
wire [13:0]addr_1;
wire \addr_1[0]_i_1_n_0 ;
wire \addr_1[10]_i_1_n_0 ;
wire \addr_1[11]_i_1_n_0 ;
wire \addr_1[12]_i_1_n_0 ;
wire \addr_1[13]_i_1_n_0 ;
wire \addr_1[1]_i_1_n_0 ;
wire \addr_1[2]_i_1_n_0 ;
wire \addr_1[3]_i_1_n_0 ;
wire \addr_1[4]_i_1_n_0 ;
wire \addr_1[5]_i_1_n_0 ;
wire \addr_1[6]_i_1_n_0 ;
wire \addr_1[7]_i_1_n_0 ;
wire \addr_1[8]_i_1_n_0 ;
wire \addr_1[9]_i_1_n_0 ;
wire bottom_left_0;
wire \bottom_left_0_reg_n_0_[0] ;
wire \bottom_left_0_reg_n_0_[10] ;
wire \bottom_left_0_reg_n_0_[11] ;
wire \bottom_left_0_reg_n_0_[12] ;
wire \bottom_left_0_reg_n_0_[13] ;
wire \bottom_left_0_reg_n_0_[14] ;
wire \bottom_left_0_reg_n_0_[15] ;
wire \bottom_left_0_reg_n_0_[1] ;
wire \bottom_left_0_reg_n_0_[2] ;
wire \bottom_left_0_reg_n_0_[3] ;
wire \bottom_left_0_reg_n_0_[4] ;
wire \bottom_left_0_reg_n_0_[5] ;
wire \bottom_left_0_reg_n_0_[6] ;
wire \bottom_left_0_reg_n_0_[7] ;
wire \bottom_left_0_reg_n_0_[8] ;
wire \bottom_left_0_reg_n_0_[9] ;
wire [15:0]bottom_left_1;
wire \bottom_right_0[0]_i_2_n_0 ;
wire \bottom_right_0[10]_i_2_n_0 ;
wire \bottom_right_0[11]_i_2_n_0 ;
wire \bottom_right_0[12]_i_2_n_0 ;
wire \bottom_right_0[13]_i_2_n_0 ;
wire \bottom_right_0[14]_i_2_n_0 ;
wire \bottom_right_0[15]_i_1_n_0 ;
wire \bottom_right_0[15]_i_3_n_0 ;
wire \bottom_right_0[15]_i_4_n_0 ;
wire \bottom_right_0[15]_i_5_n_0 ;
wire \bottom_right_0[1]_i_2_n_0 ;
wire \bottom_right_0[2]_i_2_n_0 ;
wire \bottom_right_0[3]_i_2_n_0 ;
wire \bottom_right_0[4]_i_2_n_0 ;
wire \bottom_right_0[5]_i_2_n_0 ;
wire \bottom_right_0[6]_i_2_n_0 ;
wire \bottom_right_0[7]_i_2_n_0 ;
wire \bottom_right_0[8]_i_2_n_0 ;
wire \bottom_right_0[9]_i_2_n_0 ;
wire \bottom_right_0_reg_n_0_[0] ;
wire \bottom_right_0_reg_n_0_[10] ;
wire \bottom_right_0_reg_n_0_[11] ;
wire \bottom_right_0_reg_n_0_[12] ;
wire \bottom_right_0_reg_n_0_[13] ;
wire \bottom_right_0_reg_n_0_[14] ;
wire \bottom_right_0_reg_n_0_[15] ;
wire \bottom_right_0_reg_n_0_[1] ;
wire \bottom_right_0_reg_n_0_[2] ;
wire \bottom_right_0_reg_n_0_[3] ;
wire \bottom_right_0_reg_n_0_[4] ;
wire \bottom_right_0_reg_n_0_[5] ;
wire \bottom_right_0_reg_n_0_[6] ;
wire \bottom_right_0_reg_n_0_[7] ;
wire \bottom_right_0_reg_n_0_[8] ;
wire \bottom_right_0_reg_n_0_[9] ;
wire bottom_right_1;
wire \bottom_right_1[0]_i_1_n_0 ;
wire \bottom_right_1[10]_i_1_n_0 ;
wire \bottom_right_1[11]_i_1_n_0 ;
wire \bottom_right_1[12]_i_1_n_0 ;
wire \bottom_right_1[13]_i_1_n_0 ;
wire \bottom_right_1[14]_i_1_n_0 ;
wire \bottom_right_1[15]_i_1_n_0 ;
wire \bottom_right_1[1]_i_1_n_0 ;
wire \bottom_right_1[2]_i_1_n_0 ;
wire \bottom_right_1[3]_i_1_n_0 ;
wire \bottom_right_1[4]_i_1_n_0 ;
wire \bottom_right_1[5]_i_1_n_0 ;
wire \bottom_right_1[6]_i_1_n_0 ;
wire \bottom_right_1[7]_i_1_n_0 ;
wire \bottom_right_1[8]_i_1_n_0 ;
wire \bottom_right_1[9]_i_1_n_0 ;
wire \bottom_right_1_reg_n_0_[0] ;
wire \bottom_right_1_reg_n_0_[10] ;
wire \bottom_right_1_reg_n_0_[11] ;
wire \bottom_right_1_reg_n_0_[12] ;
wire \bottom_right_1_reg_n_0_[13] ;
wire \bottom_right_1_reg_n_0_[14] ;
wire \bottom_right_1_reg_n_0_[15] ;
wire \bottom_right_1_reg_n_0_[1] ;
wire \bottom_right_1_reg_n_0_[2] ;
wire \bottom_right_1_reg_n_0_[3] ;
wire \bottom_right_1_reg_n_0_[4] ;
wire \bottom_right_1_reg_n_0_[5] ;
wire \bottom_right_1_reg_n_0_[6] ;
wire \bottom_right_1_reg_n_0_[7] ;
wire \bottom_right_1_reg_n_0_[8] ;
wire \bottom_right_1_reg_n_0_[9] ;
wire \cache[10]_5 ;
wire \cache[9][15]_i_1_n_0 ;
wire [15:0]\cache_reg[0]_4 ;
wire [15:0]\cache_reg[10]_3 ;
wire \cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[3][0]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][10]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][11]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][12]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][13]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][14]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][15]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][1]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][2]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][3]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][4]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][5]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][6]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][7]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][8]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][9]_U0_cache_reg_r_1_n_0 ;
wire [15:0]\cache_reg[4]_0 ;
wire \cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[7][0]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][10]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][11]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][12]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][13]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][14]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][15]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][1]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][2]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][3]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][4]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][5]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][6]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][7]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][8]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][9]_U0_cache_reg_r_1_n_0 ;
wire [15:0]\cache_reg[8]_1 ;
wire [15:0]\cache_reg[9]_2 ;
wire cache_reg_gate__0_n_0;
wire cache_reg_gate__10_n_0;
wire cache_reg_gate__11_n_0;
wire cache_reg_gate__12_n_0;
wire cache_reg_gate__13_n_0;
wire cache_reg_gate__14_n_0;
wire cache_reg_gate__15_n_0;
wire cache_reg_gate__16_n_0;
wire cache_reg_gate__17_n_0;
wire cache_reg_gate__18_n_0;
wire cache_reg_gate__19_n_0;
wire cache_reg_gate__1_n_0;
wire cache_reg_gate__20_n_0;
wire cache_reg_gate__21_n_0;
wire cache_reg_gate__22_n_0;
wire cache_reg_gate__23_n_0;
wire cache_reg_gate__24_n_0;
wire cache_reg_gate__25_n_0;
wire cache_reg_gate__26_n_0;
wire cache_reg_gate__27_n_0;
wire cache_reg_gate__28_n_0;
wire cache_reg_gate__29_n_0;
wire cache_reg_gate__2_n_0;
wire cache_reg_gate__30_n_0;
wire cache_reg_gate__3_n_0;
wire cache_reg_gate__4_n_0;
wire cache_reg_gate__5_n_0;
wire cache_reg_gate__6_n_0;
wire cache_reg_gate__7_n_0;
wire cache_reg_gate__8_n_0;
wire cache_reg_gate__9_n_0;
wire cache_reg_gate_n_0;
wire cache_reg_r_0_n_0;
wire cache_reg_r_1_n_0;
wire cache_reg_r_n_0;
wire clk_x16;
wire compute_addr_0;
wire \compute_addr_0[0]_i_1_n_0 ;
wire \compute_addr_0[10]_i_1_n_0 ;
wire \compute_addr_0[10]_i_2_n_0 ;
wire \compute_addr_0[11]_i_1_n_0 ;
wire \compute_addr_0[11]_i_2_n_0 ;
wire \compute_addr_0[11]_i_3_n_0 ;
wire \compute_addr_0[12]_i_1_n_0 ;
wire \compute_addr_0[12]_i_2_n_0 ;
wire \compute_addr_0[13]_i_2_n_0 ;
wire \compute_addr_0[13]_i_3_n_0 ;
wire \compute_addr_0[1]_i_1_n_0 ;
wire \compute_addr_0[2]_i_1_n_0 ;
wire \compute_addr_0[3]_i_1_n_0 ;
wire \compute_addr_0[4]_i_1_n_0 ;
wire \compute_addr_0[5]_i_1_n_0 ;
wire \compute_addr_0[6]_i_1_n_0 ;
wire \compute_addr_0[7]_i_1_n_0 ;
wire \compute_addr_0[8]_i_1_n_0 ;
wire \compute_addr_0[9]_i_1_n_0 ;
wire \compute_addr_0_reg_n_0_[0] ;
wire \compute_addr_0_reg_n_0_[10] ;
wire \compute_addr_0_reg_n_0_[11] ;
wire \compute_addr_0_reg_n_0_[12] ;
wire \compute_addr_0_reg_n_0_[13] ;
wire \compute_addr_0_reg_n_0_[1] ;
wire \compute_addr_0_reg_n_0_[2] ;
wire \compute_addr_0_reg_n_0_[3] ;
wire \compute_addr_0_reg_n_0_[4] ;
wire \compute_addr_0_reg_n_0_[5] ;
wire \compute_addr_0_reg_n_0_[6] ;
wire \compute_addr_0_reg_n_0_[7] ;
wire \compute_addr_0_reg_n_0_[8] ;
wire \compute_addr_0_reg_n_0_[9] ;
wire [13:0]compute_addr_1;
wire \compute_addr_1[0]_i_1_n_0 ;
wire \compute_addr_1[10]_i_1_n_0 ;
wire \compute_addr_1[10]_i_2_n_0 ;
wire \compute_addr_1[11]_i_1_n_0 ;
wire \compute_addr_1[11]_i_2_n_0 ;
wire \compute_addr_1[12]_i_1_n_0 ;
wire \compute_addr_1[12]_i_2_n_0 ;
wire \compute_addr_1[13]_i_1_n_0 ;
wire \compute_addr_1[13]_i_2_n_0 ;
wire \compute_addr_1[1]_i_1_n_0 ;
wire \compute_addr_1[2]_i_1_n_0 ;
wire \compute_addr_1[3]_i_1_n_0 ;
wire \compute_addr_1[4]_i_1_n_0 ;
wire \compute_addr_1[5]_i_1_n_0 ;
wire \compute_addr_1[6]_i_1_n_0 ;
wire \compute_addr_1[7]_i_1_n_0 ;
wire \compute_addr_1[8]_i_1_n_0 ;
wire \compute_addr_1[9]_i_1_n_0 ;
wire compute_addr_2;
wire \compute_addr_2[10]_i_1_n_0 ;
wire \compute_addr_2[10]_i_2_n_0 ;
wire \compute_addr_2[11]_i_1_n_0 ;
wire \compute_addr_2[11]_i_2_n_0 ;
wire \compute_addr_2[12]_i_1_n_0 ;
wire \compute_addr_2[12]_i_2_n_0 ;
wire \compute_addr_2[13]_i_2_n_0 ;
wire \compute_addr_2[13]_i_3_n_0 ;
wire \compute_addr_2[13]_i_4_n_0 ;
wire \compute_addr_2_reg_n_0_[0] ;
wire \compute_addr_2_reg_n_0_[10] ;
wire \compute_addr_2_reg_n_0_[11] ;
wire \compute_addr_2_reg_n_0_[12] ;
wire \compute_addr_2_reg_n_0_[13] ;
wire \compute_addr_2_reg_n_0_[1] ;
wire \compute_addr_2_reg_n_0_[2] ;
wire \compute_addr_2_reg_n_0_[3] ;
wire \compute_addr_2_reg_n_0_[4] ;
wire \compute_addr_2_reg_n_0_[5] ;
wire \compute_addr_2_reg_n_0_[6] ;
wire \compute_addr_2_reg_n_0_[7] ;
wire \compute_addr_2_reg_n_0_[8] ;
wire \compute_addr_2_reg_n_0_[9] ;
wire [13:0]compute_addr_3;
wire \compute_addr_3[0]_i_1_n_0 ;
wire \compute_addr_3[10]_i_1_n_0 ;
wire \compute_addr_3[10]_i_2_n_0 ;
wire \compute_addr_3[11]_i_1_n_0 ;
wire \compute_addr_3[11]_i_2_n_0 ;
wire \compute_addr_3[12]_i_1_n_0 ;
wire \compute_addr_3[12]_i_2_n_0 ;
wire \compute_addr_3[13]_i_1_n_0 ;
wire \compute_addr_3[13]_i_2_n_0 ;
wire \compute_addr_3[1]_i_1_n_0 ;
wire \compute_addr_3[2]_i_1_n_0 ;
wire \compute_addr_3[3]_i_1_n_0 ;
wire \compute_addr_3[4]_i_1_n_0 ;
wire \compute_addr_3[5]_i_1_n_0 ;
wire \compute_addr_3[6]_i_1_n_0 ;
wire \compute_addr_3[7]_i_1_n_0 ;
wire \compute_addr_3[8]_i_1_n_0 ;
wire \compute_addr_3[9]_i_1_n_0 ;
wire corner;
wire \corner_reg_n_0_[0] ;
wire \corner_reg_n_0_[10] ;
wire \corner_reg_n_0_[11] ;
wire \corner_reg_n_0_[12] ;
wire \corner_reg_n_0_[13] ;
wire \corner_reg_n_0_[14] ;
wire \corner_reg_n_0_[15] ;
wire \corner_reg_n_0_[1] ;
wire \corner_reg_n_0_[2] ;
wire \corner_reg_n_0_[3] ;
wire \corner_reg_n_0_[4] ;
wire \corner_reg_n_0_[5] ;
wire \corner_reg_n_0_[6] ;
wire \corner_reg_n_0_[7] ;
wire \corner_reg_n_0_[8] ;
wire \corner_reg_n_0_[9] ;
wire [3:0]cycle;
wire \cycle[0]_i_1_n_0 ;
wire \cycle[0]_rep_i_1_n_0 ;
wire \cycle[1]_i_1_n_0 ;
wire \cycle[1]_rep_i_1__0_n_0 ;
wire \cycle[1]_rep_i_1_n_0 ;
wire \cycle[2]_i_1_n_0 ;
wire \cycle[2]_rep_i_1_n_0 ;
wire \cycle[3]_i_1_n_0 ;
wire \cycle[3]_i_2_n_0 ;
wire \cycle_reg[0]_rep_n_0 ;
wire \cycle_reg[1]_rep__0_n_0 ;
wire \cycle_reg[1]_rep_n_0 ;
wire \cycle_reg[2]_rep_n_0 ;
wire [13:0]data1;
wire [13:0]data2;
wire [13:10]data5;
wire det_0;
wire det_0_reg_i_2_n_0;
wire det_0_reg_n_106;
wire det_0_reg_n_107;
wire det_0_reg_n_108;
wire det_0_reg_n_109;
wire det_0_reg_n_110;
wire det_0_reg_n_111;
wire det_0_reg_n_112;
wire det_0_reg_n_113;
wire det_0_reg_n_114;
wire det_0_reg_n_115;
wire det_0_reg_n_116;
wire det_0_reg_n_117;
wire det_0_reg_n_118;
wire det_0_reg_n_119;
wire det_0_reg_n_120;
wire det_0_reg_n_121;
wire det_0_reg_n_122;
wire det_0_reg_n_123;
wire det_0_reg_n_124;
wire det_0_reg_n_125;
wire det_0_reg_n_126;
wire det_0_reg_n_127;
wire det_0_reg_n_128;
wire det_0_reg_n_129;
wire det_0_reg_n_130;
wire det_0_reg_n_131;
wire det_0_reg_n_132;
wire det_0_reg_n_133;
wire det_0_reg_n_134;
wire det_0_reg_n_135;
wire det_0_reg_n_136;
wire det_0_reg_n_137;
wire det_0_reg_n_138;
wire det_0_reg_n_139;
wire det_0_reg_n_140;
wire det_0_reg_n_141;
wire det_0_reg_n_142;
wire det_0_reg_n_143;
wire det_0_reg_n_144;
wire det_0_reg_n_145;
wire det_0_reg_n_146;
wire det_0_reg_n_147;
wire det_0_reg_n_148;
wire det_0_reg_n_149;
wire det_0_reg_n_150;
wire det_0_reg_n_151;
wire det_0_reg_n_152;
wire det_0_reg_n_153;
wire [31:0]det_abs;
wire [31:1]det_abs0;
wire \det_abs[10]_i_1_n_0 ;
wire \det_abs[11]_i_1_n_0 ;
wire \det_abs[12]_i_1_n_0 ;
wire \det_abs[12]_i_3_n_0 ;
wire \det_abs[12]_i_4_n_0 ;
wire \det_abs[12]_i_5_n_0 ;
wire \det_abs[12]_i_6_n_0 ;
wire \det_abs[13]_i_1_n_0 ;
wire \det_abs[14]_i_1_n_0 ;
wire \det_abs[15]_i_1_n_0 ;
wire \det_abs[16]_i_1_n_0 ;
wire \det_abs[16]_i_3_n_0 ;
wire \det_abs[16]_i_4_n_0 ;
wire \det_abs[16]_i_5_n_0 ;
wire \det_abs[16]_i_6_n_0 ;
wire \det_abs[17]_i_1_n_0 ;
wire \det_abs[18]_i_1_n_0 ;
wire \det_abs[19]_i_1_n_0 ;
wire \det_abs[1]_i_1_n_0 ;
wire \det_abs[20]_i_1_n_0 ;
wire \det_abs[20]_i_3_n_0 ;
wire \det_abs[20]_i_4_n_0 ;
wire \det_abs[20]_i_5_n_0 ;
wire \det_abs[20]_i_6_n_0 ;
wire \det_abs[21]_i_1_n_0 ;
wire \det_abs[22]_i_1_n_0 ;
wire \det_abs[23]_i_1_n_0 ;
wire \det_abs[24]_i_1_n_0 ;
wire \det_abs[24]_i_3_n_0 ;
wire \det_abs[24]_i_4_n_0 ;
wire \det_abs[24]_i_5_n_0 ;
wire \det_abs[24]_i_6_n_0 ;
wire \det_abs[25]_i_1_n_0 ;
wire \det_abs[26]_i_1_n_0 ;
wire \det_abs[27]_i_1_n_0 ;
wire \det_abs[28]_i_1_n_0 ;
wire \det_abs[28]_i_3_n_0 ;
wire \det_abs[28]_i_4_n_0 ;
wire \det_abs[28]_i_5_n_0 ;
wire \det_abs[28]_i_6_n_0 ;
wire \det_abs[29]_i_1_n_0 ;
wire \det_abs[2]_i_1_n_0 ;
wire \det_abs[30]_i_1_n_0 ;
wire \det_abs[31]_i_1_n_0 ;
wire \det_abs[31]_i_3_n_0 ;
wire \det_abs[31]_i_4_n_0 ;
wire \det_abs[31]_i_5_n_0 ;
wire \det_abs[3]_i_1_n_0 ;
wire \det_abs[4]_i_1_n_0 ;
wire \det_abs[4]_i_3_n_0 ;
wire \det_abs[4]_i_4_n_0 ;
wire \det_abs[4]_i_5_n_0 ;
wire \det_abs[4]_i_6_n_0 ;
wire \det_abs[4]_i_7_n_0 ;
wire \det_abs[5]_i_1_n_0 ;
wire \det_abs[6]_i_1_n_0 ;
wire \det_abs[7]_i_1_n_0 ;
wire \det_abs[8]_i_1_n_0 ;
wire \det_abs[8]_i_3_n_0 ;
wire \det_abs[8]_i_4_n_0 ;
wire \det_abs[8]_i_5_n_0 ;
wire \det_abs[8]_i_6_n_0 ;
wire \det_abs[9]_i_1_n_0 ;
wire \det_abs_reg[12]_i_2_n_0 ;
wire \det_abs_reg[12]_i_2_n_1 ;
wire \det_abs_reg[12]_i_2_n_2 ;
wire \det_abs_reg[12]_i_2_n_3 ;
wire \det_abs_reg[16]_i_2_n_0 ;
wire \det_abs_reg[16]_i_2_n_1 ;
wire \det_abs_reg[16]_i_2_n_2 ;
wire \det_abs_reg[16]_i_2_n_3 ;
wire \det_abs_reg[20]_i_2_n_0 ;
wire \det_abs_reg[20]_i_2_n_1 ;
wire \det_abs_reg[20]_i_2_n_2 ;
wire \det_abs_reg[20]_i_2_n_3 ;
wire \det_abs_reg[24]_i_2_n_0 ;
wire \det_abs_reg[24]_i_2_n_1 ;
wire \det_abs_reg[24]_i_2_n_2 ;
wire \det_abs_reg[24]_i_2_n_3 ;
wire \det_abs_reg[28]_i_2_n_0 ;
wire \det_abs_reg[28]_i_2_n_1 ;
wire \det_abs_reg[28]_i_2_n_2 ;
wire \det_abs_reg[28]_i_2_n_3 ;
wire \det_abs_reg[31]_i_2_n_2 ;
wire \det_abs_reg[31]_i_2_n_3 ;
wire \det_abs_reg[4]_i_2_n_0 ;
wire \det_abs_reg[4]_i_2_n_1 ;
wire \det_abs_reg[4]_i_2_n_2 ;
wire \det_abs_reg[4]_i_2_n_3 ;
wire \det_abs_reg[8]_i_2_n_0 ;
wire \det_abs_reg[8]_i_2_n_1 ;
wire \det_abs_reg[8]_i_2_n_2 ;
wire \det_abs_reg[8]_i_2_n_3 ;
wire det_reg_n_100;
wire det_reg_n_101;
wire det_reg_n_102;
wire det_reg_n_103;
wire det_reg_n_104;
wire det_reg_n_105;
wire det_reg_n_74;
wire det_reg_n_75;
wire det_reg_n_76;
wire det_reg_n_77;
wire det_reg_n_78;
wire det_reg_n_79;
wire det_reg_n_80;
wire det_reg_n_81;
wire det_reg_n_82;
wire det_reg_n_83;
wire det_reg_n_84;
wire det_reg_n_85;
wire det_reg_n_86;
wire det_reg_n_87;
wire det_reg_n_88;
wire det_reg_n_89;
wire det_reg_n_90;
wire det_reg_n_91;
wire det_reg_n_92;
wire det_reg_n_93;
wire det_reg_n_94;
wire det_reg_n_95;
wire det_reg_n_96;
wire det_reg_n_97;
wire det_reg_n_98;
wire det_reg_n_99;
wire \din_reg_n_0_[0] ;
wire \din_reg_n_0_[10] ;
wire \din_reg_n_0_[11] ;
wire \din_reg_n_0_[12] ;
wire \din_reg_n_0_[13] ;
wire \din_reg_n_0_[14] ;
wire \din_reg_n_0_[15] ;
wire \din_reg_n_0_[1] ;
wire \din_reg_n_0_[2] ;
wire \din_reg_n_0_[3] ;
wire \din_reg_n_0_[4] ;
wire \din_reg_n_0_[5] ;
wire \din_reg_n_0_[6] ;
wire \din_reg_n_0_[7] ;
wire \din_reg_n_0_[8] ;
wire \din_reg_n_0_[9] ;
wire [15:0]dout_0;
wire [15:0]dout_1;
wire [7:0]g_in;
wire [31:0]hessian_out;
wire i__carry__0_i_1_n_0;
wire i__carry__0_i_2_n_0;
wire i__carry__0_i_3_n_0;
wire i__carry__0_i_4_n_0;
wire i__carry__0_i_5_n_0;
wire i__carry__1_i_1_n_0;
wire i__carry__1_i_2_n_0;
wire i__carry_i_1_n_0;
wire i__carry_i_2_n_0;
wire i__carry_i_3_n_0;
wire i__carry_i_4_n_0;
wire [7:0]last_value;
wire left;
wire \left[15]_i_2_n_0 ;
wire \left[15]_i_3_n_0 ;
wire \left_reg_n_0_[0] ;
wire \left_reg_n_0_[10] ;
wire \left_reg_n_0_[11] ;
wire \left_reg_n_0_[12] ;
wire \left_reg_n_0_[13] ;
wire \left_reg_n_0_[14] ;
wire \left_reg_n_0_[15] ;
wire \left_reg_n_0_[1] ;
wire \left_reg_n_0_[2] ;
wire \left_reg_n_0_[3] ;
wire \left_reg_n_0_[4] ;
wire \left_reg_n_0_[5] ;
wire \left_reg_n_0_[6] ;
wire \left_reg_n_0_[7] ;
wire \left_reg_n_0_[8] ;
wire \left_reg_n_0_[9] ;
wire [15:0]p_0_out;
wire \plusOp_inferred__0/i__carry__0_n_0 ;
wire \plusOp_inferred__0/i__carry__0_n_1 ;
wire \plusOp_inferred__0/i__carry__0_n_2 ;
wire \plusOp_inferred__0/i__carry__0_n_3 ;
wire \plusOp_inferred__0/i__carry__0_n_4 ;
wire \plusOp_inferred__0/i__carry__0_n_5 ;
wire \plusOp_inferred__0/i__carry__0_n_6 ;
wire \plusOp_inferred__0/i__carry__0_n_7 ;
wire \plusOp_inferred__0/i__carry__1_n_3 ;
wire \plusOp_inferred__0/i__carry__1_n_6 ;
wire \plusOp_inferred__0/i__carry__1_n_7 ;
wire \plusOp_inferred__0/i__carry_n_0 ;
wire \plusOp_inferred__0/i__carry_n_1 ;
wire \plusOp_inferred__0/i__carry_n_2 ;
wire \plusOp_inferred__0/i__carry_n_3 ;
wire \plusOp_inferred__0/i__carry_n_4 ;
wire \plusOp_inferred__0/i__carry_n_5 ;
wire \plusOp_inferred__0/i__carry_n_6 ;
wire \plusOp_inferred__0/i__carry_n_7 ;
wire rst;
wire top;
wire \top[15]_i_2_n_0 ;
wire top_left_0;
wire \top_left_0[0]_i_1_n_0 ;
wire \top_left_0[10]_i_1_n_0 ;
wire \top_left_0[11]_i_1_n_0 ;
wire \top_left_0[12]_i_1_n_0 ;
wire \top_left_0[13]_i_1_n_0 ;
wire \top_left_0[14]_i_1_n_0 ;
wire \top_left_0[15]_i_2_n_0 ;
wire \top_left_0[1]_i_1_n_0 ;
wire \top_left_0[2]_i_1_n_0 ;
wire \top_left_0[3]_i_1_n_0 ;
wire \top_left_0[4]_i_1_n_0 ;
wire \top_left_0[5]_i_1_n_0 ;
wire \top_left_0[6]_i_1_n_0 ;
wire \top_left_0[7]_i_1_n_0 ;
wire \top_left_0[8]_i_1_n_0 ;
wire \top_left_0[9]_i_1_n_0 ;
wire \top_left_0_reg_n_0_[0] ;
wire \top_left_0_reg_n_0_[10] ;
wire \top_left_0_reg_n_0_[11] ;
wire \top_left_0_reg_n_0_[12] ;
wire \top_left_0_reg_n_0_[13] ;
wire \top_left_0_reg_n_0_[14] ;
wire \top_left_0_reg_n_0_[15] ;
wire \top_left_0_reg_n_0_[1] ;
wire \top_left_0_reg_n_0_[2] ;
wire \top_left_0_reg_n_0_[3] ;
wire \top_left_0_reg_n_0_[4] ;
wire \top_left_0_reg_n_0_[5] ;
wire \top_left_0_reg_n_0_[6] ;
wire \top_left_0_reg_n_0_[7] ;
wire \top_left_0_reg_n_0_[8] ;
wire \top_left_0_reg_n_0_[9] ;
wire [15:0]top_left_1;
wire \top_left_1[0]_i_1_n_0 ;
wire \top_left_1[10]_i_1_n_0 ;
wire \top_left_1[11]_i_1_n_0 ;
wire \top_left_1[12]_i_1_n_0 ;
wire \top_left_1[13]_i_1_n_0 ;
wire \top_left_1[14]_i_1_n_0 ;
wire \top_left_1[15]_i_2_n_0 ;
wire \top_left_1[1]_i_1_n_0 ;
wire \top_left_1[2]_i_1_n_0 ;
wire \top_left_1[3]_i_1_n_0 ;
wire \top_left_1[4]_i_1_n_0 ;
wire \top_left_1[5]_i_1_n_0 ;
wire \top_left_1[6]_i_1_n_0 ;
wire \top_left_1[7]_i_1_n_0 ;
wire \top_left_1[8]_i_1_n_0 ;
wire \top_left_1[9]_i_1_n_0 ;
wire \top_reg_n_0_[0] ;
wire \top_reg_n_0_[10] ;
wire \top_reg_n_0_[11] ;
wire \top_reg_n_0_[12] ;
wire \top_reg_n_0_[13] ;
wire \top_reg_n_0_[14] ;
wire \top_reg_n_0_[15] ;
wire \top_reg_n_0_[1] ;
wire \top_reg_n_0_[2] ;
wire \top_reg_n_0_[3] ;
wire \top_reg_n_0_[4] ;
wire \top_reg_n_0_[5] ;
wire \top_reg_n_0_[6] ;
wire \top_reg_n_0_[7] ;
wire \top_reg_n_0_[8] ;
wire \top_reg_n_0_[9] ;
wire top_right_0;
wire \top_right_0[0]_i_1_n_0 ;
wire \top_right_0[10]_i_1_n_0 ;
wire \top_right_0[11]_i_1_n_0 ;
wire \top_right_0[12]_i_1_n_0 ;
wire \top_right_0[13]_i_1_n_0 ;
wire \top_right_0[14]_i_1_n_0 ;
wire \top_right_0[15]_i_2_n_0 ;
wire \top_right_0[1]_i_1_n_0 ;
wire \top_right_0[2]_i_1_n_0 ;
wire \top_right_0[3]_i_1_n_0 ;
wire \top_right_0[4]_i_1_n_0 ;
wire \top_right_0[5]_i_1_n_0 ;
wire \top_right_0[6]_i_1_n_0 ;
wire \top_right_0[7]_i_1_n_0 ;
wire \top_right_0[8]_i_1_n_0 ;
wire \top_right_0[9]_i_1_n_0 ;
wire \top_right_0_reg_n_0_[0] ;
wire \top_right_0_reg_n_0_[10] ;
wire \top_right_0_reg_n_0_[11] ;
wire \top_right_0_reg_n_0_[12] ;
wire \top_right_0_reg_n_0_[13] ;
wire \top_right_0_reg_n_0_[14] ;
wire \top_right_0_reg_n_0_[15] ;
wire \top_right_0_reg_n_0_[1] ;
wire \top_right_0_reg_n_0_[2] ;
wire \top_right_0_reg_n_0_[3] ;
wire \top_right_0_reg_n_0_[4] ;
wire \top_right_0_reg_n_0_[5] ;
wire \top_right_0_reg_n_0_[6] ;
wire \top_right_0_reg_n_0_[7] ;
wire \top_right_0_reg_n_0_[8] ;
wire \top_right_0_reg_n_0_[9] ;
wire top_right_1;
wire \top_right_1[0]_i_1_n_0 ;
wire \top_right_1[10]_i_1_n_0 ;
wire \top_right_1[11]_i_1_n_0 ;
wire \top_right_1[12]_i_1_n_0 ;
wire \top_right_1[13]_i_1_n_0 ;
wire \top_right_1[14]_i_1_n_0 ;
wire \top_right_1[15]_i_1_n_0 ;
wire \top_right_1[15]_i_2_n_0 ;
wire \top_right_1[1]_i_1_n_0 ;
wire \top_right_1[2]_i_1_n_0 ;
wire \top_right_1[3]_i_1_n_0 ;
wire \top_right_1[4]_i_1_n_0 ;
wire \top_right_1[5]_i_1_n_0 ;
wire \top_right_1[6]_i_1_n_0 ;
wire \top_right_1[7]_i_1_n_0 ;
wire \top_right_1[8]_i_1_n_0 ;
wire \top_right_1[9]_i_1_n_0 ;
wire \top_right_1_reg_n_0_[0] ;
wire \top_right_1_reg_n_0_[10] ;
wire \top_right_1_reg_n_0_[11] ;
wire \top_right_1_reg_n_0_[12] ;
wire \top_right_1_reg_n_0_[13] ;
wire \top_right_1_reg_n_0_[14] ;
wire \top_right_1_reg_n_0_[15] ;
wire \top_right_1_reg_n_0_[1] ;
wire \top_right_1_reg_n_0_[2] ;
wire \top_right_1_reg_n_0_[3] ;
wire \top_right_1_reg_n_0_[4] ;
wire \top_right_1_reg_n_0_[5] ;
wire \top_right_1_reg_n_0_[6] ;
wire \top_right_1_reg_n_0_[7] ;
wire \top_right_1_reg_n_0_[8] ;
wire \top_right_1_reg_n_0_[9] ;
wire \value_reg_n_0_[0] ;
wire \value_reg_n_0_[1] ;
wire \value_reg_n_0_[2] ;
wire \value_reg_n_0_[3] ;
wire \value_reg_n_0_[4] ;
wire \value_reg_n_0_[5] ;
wire \value_reg_n_0_[6] ;
wire \value_reg_n_0_[7] ;
wire wen_i_1_n_0;
wire wen_i_2_n_0;
wire wen_reg_n_0;
wire x;
wire \x0[0]_i_2_n_0 ;
wire \x0[0]_i_3_n_0 ;
wire \x0[1]_i_2_n_0 ;
wire \x0[1]_i_3_n_0 ;
wire \x0[1]_i_4_n_0 ;
wire \x0[2]_i_1_n_0 ;
wire \x0[2]_i_2_n_0 ;
wire \x0[2]_i_3_n_0 ;
wire \x0[2]_i_4_n_0 ;
wire \x0[2]_i_5_n_0 ;
wire \x0[3]_i_1_n_0 ;
wire \x0[3]_i_2_n_0 ;
wire \x0[3]_i_3_n_0 ;
wire \x0[3]_i_4_n_0 ;
wire \x0[3]_i_5_n_0 ;
wire \x0[3]_i_6_n_0 ;
wire \x0[4]_i_1_n_0 ;
wire \x0[4]_i_2_n_0 ;
wire \x0[4]_i_3_n_0 ;
wire \x0[4]_i_4_n_0 ;
wire \x0[4]_i_5_n_0 ;
wire \x0[5]_i_1_n_0 ;
wire \x0[5]_i_2_n_0 ;
wire \x0[5]_i_3_n_0 ;
wire \x0[5]_i_4_n_0 ;
wire \x0[5]_i_5_n_0 ;
wire \x0[6]_i_1_n_0 ;
wire \x0[6]_i_2_n_0 ;
wire \x0[6]_i_3_n_0 ;
wire \x0[6]_i_4_n_0 ;
wire \x0[6]_i_5_n_0 ;
wire \x0[7]_i_1_n_0 ;
wire \x0[7]_i_2_n_0 ;
wire \x0[7]_i_3_n_0 ;
wire \x0[7]_i_4_n_0 ;
wire \x0[7]_i_5_n_0 ;
wire \x0[7]_i_6_n_0 ;
wire \x0[7]_i_7_n_0 ;
wire \x0[8]_i_1_n_0 ;
wire \x0[8]_i_2_n_0 ;
wire \x0[8]_i_3_n_0 ;
wire \x0[8]_i_4_n_0 ;
wire \x0[8]_i_5_n_0 ;
wire \x0[8]_i_6_n_0 ;
wire \x0[8]_i_7_n_0 ;
wire \x0[9]_i_1_n_0 ;
wire \x0[9]_i_2_n_0 ;
wire \x0[9]_i_3_n_0 ;
wire \x0[9]_i_4_n_0 ;
wire \x0[9]_i_5_n_0 ;
wire \x0[9]_i_6_n_0 ;
wire \x0[9]_i_7_n_0 ;
wire \x0_reg[0]_i_1_n_0 ;
wire \x0_reg[1]_i_1_n_0 ;
wire x1;
wire \x1[0]_i_1_n_0 ;
wire \x1[1]_i_1_n_0 ;
wire \x1[2]_i_1_n_0 ;
wire \x1[2]_i_2_n_0 ;
wire \x1[2]_i_3_n_0 ;
wire \x1[3]_i_1_n_0 ;
wire \x1[3]_i_2_n_0 ;
wire \x1[3]_i_3_n_0 ;
wire \x1[3]_i_4_n_0 ;
wire \x1[4]_i_1_n_0 ;
wire \x1[4]_i_2_n_0 ;
wire \x1[4]_i_3_n_0 ;
wire \x1[4]_i_4_n_0 ;
wire \x1[4]_i_5_n_0 ;
wire \x1[5]_i_1_n_0 ;
wire \x1[5]_i_2_n_0 ;
wire \x1[5]_i_3_n_0 ;
wire \x1[5]_i_4_n_0 ;
wire \x1[5]_i_5_n_0 ;
wire \x1[6]_i_1_n_0 ;
wire \x1[6]_i_2_n_0 ;
wire \x1[6]_i_3_n_0 ;
wire \x1[6]_i_4_n_0 ;
wire \x1[6]_i_5_n_0 ;
wire \x1[6]_i_6_n_0 ;
wire \x1[6]_i_7_n_0 ;
wire \x1[6]_i_8_n_0 ;
wire \x1[7]_i_1_n_0 ;
wire \x1[7]_i_2_n_0 ;
wire \x1[7]_i_3_n_0 ;
wire \x1[7]_i_4_n_0 ;
wire \x1[7]_i_5_n_0 ;
wire \x1[8]_i_1_n_0 ;
wire \x1[8]_i_2_n_0 ;
wire \x1[8]_i_3_n_0 ;
wire \x1[8]_i_4_n_0 ;
wire \x1[8]_i_5_n_0 ;
wire \x1[8]_i_6_n_0 ;
wire \x1[9]_i_2_n_0 ;
wire \x1[9]_i_3_n_0 ;
wire \x1[9]_i_4_n_0 ;
wire \x1[9]_i_5_n_0 ;
wire \x1[9]_i_6_n_0 ;
wire \x1[9]_i_7_n_0 ;
wire \x1[9]_i_8_n_0 ;
wire [9:0]x_addr;
wire \x_reg_n_0_[0] ;
wire \x_reg_n_0_[1] ;
wire \x_reg_n_0_[2] ;
wire \x_reg_n_0_[3] ;
wire \x_reg_n_0_[4] ;
wire \x_reg_n_0_[5] ;
wire \x_reg_n_0_[6] ;
wire \x_reg_n_0_[7] ;
wire \x_reg_n_0_[8] ;
wire \x_reg_n_0_[9] ;
wire y1;
wire \y1[2]_i_1_n_0 ;
wire \y1[3]_i_1_n_0 ;
wire \y1_reg_n_0_[0] ;
wire \y1_reg_n_0_[1] ;
wire \y1_reg_n_0_[2] ;
wire \y1_reg_n_0_[3] ;
wire y2;
wire \y2[1]_i_1_n_0 ;
wire \y2[2]_i_1_n_0 ;
wire \y2[3]_i_1_n_0 ;
wire \y2_reg_n_0_[0] ;
wire \y2_reg_n_0_[1] ;
wire \y2_reg_n_0_[2] ;
wire \y2_reg_n_0_[3] ;
wire y3;
wire \y3[1]_i_1_n_0 ;
wire \y3[2]_i_1_n_0 ;
wire \y3[3]_i_1_n_0 ;
wire \y3_reg_n_0_[0] ;
wire \y3_reg_n_0_[1] ;
wire \y3_reg_n_0_[2] ;
wire \y3_reg_n_0_[3] ;
wire \y4[2]_i_1_n_0 ;
wire \y4[3]_i_1_n_0 ;
wire y5;
wire \y5[0]_i_1_n_0 ;
wire \y5[1]_i_1_n_0 ;
wire \y5[2]_i_1_n_0 ;
wire \y5[3]_i_1_n_0 ;
wire y6;
wire \y6[2]_i_1_n_0 ;
wire \y6[3]_i_1_n_0 ;
wire \y6_reg_n_0_[0] ;
wire \y6_reg_n_0_[1] ;
wire \y6_reg_n_0_[2] ;
wire \y6_reg_n_0_[3] ;
wire [3:0]y7;
wire \y7[2]_i_1_n_0 ;
wire \y7[3]_i_1_n_0 ;
wire [3:0]y8;
wire \y8[3]_i_1_n_0 ;
wire y9;
wire \y9[3]_i_1_n_0 ;
wire \y_actual_reg_n_0_[0] ;
wire \y_actual_reg_n_0_[1] ;
wire \y_actual_reg_n_0_[2] ;
wire \y_actual_reg_n_0_[3] ;
wire \y_actual_reg_n_0_[4] ;
wire \y_actual_reg_n_0_[5] ;
wire \y_actual_reg_n_0_[6] ;
wire \y_actual_reg_n_0_[7] ;
wire \y_actual_reg_n_0_[8] ;
wire \y_actual_reg_n_0_[9] ;
wire [9:0]y_addr;
wire [3:3]NLW_Lxx0_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_Lxx_00__1_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_Lxx_11__1_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_Lxy0__1_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_Lyy0_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_Lyy_20__1_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_Lyy_2_bottom_right0__0_carry__2_CO_UNCONNECTED;
wire NLW_det_0_reg_CARRYCASCOUT_UNCONNECTED;
wire NLW_det_0_reg_MULTSIGNOUT_UNCONNECTED;
wire NLW_det_0_reg_OVERFLOW_UNCONNECTED;
wire NLW_det_0_reg_PATTERNBDETECT_UNCONNECTED;
wire NLW_det_0_reg_PATTERNDETECT_UNCONNECTED;
wire NLW_det_0_reg_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_det_0_reg_ACOUT_UNCONNECTED;
wire [17:0]NLW_det_0_reg_BCOUT_UNCONNECTED;
wire [3:0]NLW_det_0_reg_CARRYOUT_UNCONNECTED;
wire [47:0]NLW_det_0_reg_P_UNCONNECTED;
wire [3:2]\NLW_det_abs_reg[31]_i_2_CO_UNCONNECTED ;
wire [3:3]\NLW_det_abs_reg[31]_i_2_O_UNCONNECTED ;
wire NLW_det_reg_CARRYCASCOUT_UNCONNECTED;
wire NLW_det_reg_MULTSIGNOUT_UNCONNECTED;
wire NLW_det_reg_OVERFLOW_UNCONNECTED;
wire NLW_det_reg_PATTERNBDETECT_UNCONNECTED;
wire NLW_det_reg_PATTERNDETECT_UNCONNECTED;
wire NLW_det_reg_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_det_reg_ACOUT_UNCONNECTED;
wire [17:0]NLW_det_reg_BCOUT_UNCONNECTED;
wire [3:0]NLW_det_reg_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_det_reg_P_UNCONNECTED;
wire [47:0]NLW_det_reg_PCOUT_UNCONNECTED;
wire [3:1]\NLW_plusOp_inferred__0/i__carry__1_CO_UNCONNECTED ;
wire [3:2]\NLW_plusOp_inferred__0/i__carry__1_O_UNCONNECTED ;
CARRY4 Lxx0_carry
(.CI(1'b0),
.CO({Lxx0_carry_n_0,Lxx0_carry_n_1,Lxx0_carry_n_2,Lxx0_carry_n_3}),
.CYINIT(1'b0),
.DI({Lxx0_carry_i_1_n_0,Lxx0_carry_i_2_n_0,1'b1,\Lxx_2_reg_n_0_[0] }),
.O(A[3:0]),
.S({Lxx0_carry_i_3_n_0,Lxx0_carry_i_4_n_0,Lxx0_carry_i_5_n_0,Lxx0_carry_i_6_n_0}));
CARRY4 Lxx0_carry__0
(.CI(Lxx0_carry_n_0),
.CO({Lxx0_carry__0_n_0,Lxx0_carry__0_n_1,Lxx0_carry__0_n_2,Lxx0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lxx0_carry__0_i_1_n_0,Lxx0_carry__0_i_2_n_0,Lxx0_carry__0_i_3_n_0,Lxx0_carry__0_i_4_n_0}),
.O(A[7:4]),
.S({Lxx0_carry__0_i_5_n_0,Lxx0_carry__0_i_6_n_0,Lxx0_carry__0_i_7_n_0,Lxx0_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair4" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__0_i_1
(.I0(Lxx_1[6]),
.I1(\Lxx_2_reg_n_0_[6] ),
.I2(Lxx_0[6]),
.O(Lxx0_carry__0_i_1_n_0));
(* HLUTNM = "lutpair3" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__0_i_2
(.I0(Lxx_1[5]),
.I1(\Lxx_2_reg_n_0_[5] ),
.I2(Lxx_0[5]),
.O(Lxx0_carry__0_i_2_n_0));
(* HLUTNM = "lutpair2" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__0_i_3
(.I0(Lxx_1[4]),
.I1(\Lxx_2_reg_n_0_[4] ),
.I2(Lxx_0[4]),
.O(Lxx0_carry__0_i_3_n_0));
(* HLUTNM = "lutpair1" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__0_i_4
(.I0(Lxx_1[3]),
.I1(\Lxx_2_reg_n_0_[3] ),
.I2(Lxx_0[3]),
.O(Lxx0_carry__0_i_4_n_0));
(* HLUTNM = "lutpair5" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__0_i_5
(.I0(Lxx_1[7]),
.I1(\Lxx_2_reg_n_0_[7] ),
.I2(Lxx_0[7]),
.I3(Lxx0_carry__0_i_1_n_0),
.O(Lxx0_carry__0_i_5_n_0));
(* HLUTNM = "lutpair4" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__0_i_6
(.I0(Lxx_1[6]),
.I1(\Lxx_2_reg_n_0_[6] ),
.I2(Lxx_0[6]),
.I3(Lxx0_carry__0_i_2_n_0),
.O(Lxx0_carry__0_i_6_n_0));
(* HLUTNM = "lutpair3" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__0_i_7
(.I0(Lxx_1[5]),
.I1(\Lxx_2_reg_n_0_[5] ),
.I2(Lxx_0[5]),
.I3(Lxx0_carry__0_i_3_n_0),
.O(Lxx0_carry__0_i_7_n_0));
(* HLUTNM = "lutpair2" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__0_i_8
(.I0(Lxx_1[4]),
.I1(\Lxx_2_reg_n_0_[4] ),
.I2(Lxx_0[4]),
.I3(Lxx0_carry__0_i_4_n_0),
.O(Lxx0_carry__0_i_8_n_0));
CARRY4 Lxx0_carry__1
(.CI(Lxx0_carry__0_n_0),
.CO({Lxx0_carry__1_n_0,Lxx0_carry__1_n_1,Lxx0_carry__1_n_2,Lxx0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lxx0_carry__1_i_1_n_0,Lxx0_carry__1_i_2_n_0,Lxx0_carry__1_i_3_n_0,Lxx0_carry__1_i_4_n_0}),
.O(A[11:8]),
.S({Lxx0_carry__1_i_5_n_0,Lxx0_carry__1_i_6_n_0,Lxx0_carry__1_i_7_n_0,Lxx0_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair8" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__1_i_1
(.I0(Lxx_1[10]),
.I1(\Lxx_2_reg_n_0_[10] ),
.I2(Lxx_0[10]),
.O(Lxx0_carry__1_i_1_n_0));
(* HLUTNM = "lutpair7" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__1_i_2
(.I0(Lxx_1[9]),
.I1(\Lxx_2_reg_n_0_[9] ),
.I2(Lxx_0[9]),
.O(Lxx0_carry__1_i_2_n_0));
(* HLUTNM = "lutpair6" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__1_i_3
(.I0(Lxx_1[8]),
.I1(\Lxx_2_reg_n_0_[8] ),
.I2(Lxx_0[8]),
.O(Lxx0_carry__1_i_3_n_0));
(* HLUTNM = "lutpair5" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__1_i_4
(.I0(Lxx_1[7]),
.I1(\Lxx_2_reg_n_0_[7] ),
.I2(Lxx_0[7]),
.O(Lxx0_carry__1_i_4_n_0));
(* HLUTNM = "lutpair9" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__1_i_5
(.I0(Lxx_1[11]),
.I1(\Lxx_2_reg_n_0_[11] ),
.I2(Lxx_0[11]),
.I3(Lxx0_carry__1_i_1_n_0),
.O(Lxx0_carry__1_i_5_n_0));
(* HLUTNM = "lutpair8" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__1_i_6
(.I0(Lxx_1[10]),
.I1(\Lxx_2_reg_n_0_[10] ),
.I2(Lxx_0[10]),
.I3(Lxx0_carry__1_i_2_n_0),
.O(Lxx0_carry__1_i_6_n_0));
(* HLUTNM = "lutpair7" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__1_i_7
(.I0(Lxx_1[9]),
.I1(\Lxx_2_reg_n_0_[9] ),
.I2(Lxx_0[9]),
.I3(Lxx0_carry__1_i_3_n_0),
.O(Lxx0_carry__1_i_7_n_0));
(* HLUTNM = "lutpair6" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__1_i_8
(.I0(Lxx_1[8]),
.I1(\Lxx_2_reg_n_0_[8] ),
.I2(Lxx_0[8]),
.I3(Lxx0_carry__1_i_4_n_0),
.O(Lxx0_carry__1_i_8_n_0));
CARRY4 Lxx0_carry__2
(.CI(Lxx0_carry__1_n_0),
.CO({NLW_Lxx0_carry__2_CO_UNCONNECTED[3],Lxx0_carry__2_n_1,Lxx0_carry__2_n_2,Lxx0_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lxx0_carry__2_i_1_n_0,Lxx0_carry__2_i_2_n_0,Lxx0_carry__2_i_3_n_0}),
.O(A[15:12]),
.S({Lxx0_carry__2_i_4_n_0,Lxx0_carry__2_i_5_n_0,Lxx0_carry__2_i_6_n_0,Lxx0_carry__2_i_7_n_0}));
(* HLUTNM = "lutpair11" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__2_i_1
(.I0(Lxx_1[13]),
.I1(\Lxx_2_reg_n_0_[13] ),
.I2(Lxx_0[13]),
.O(Lxx0_carry__2_i_1_n_0));
(* HLUTNM = "lutpair10" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__2_i_2
(.I0(Lxx_1[12]),
.I1(\Lxx_2_reg_n_0_[12] ),
.I2(Lxx_0[12]),
.O(Lxx0_carry__2_i_2_n_0));
(* HLUTNM = "lutpair9" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__2_i_3
(.I0(Lxx_1[11]),
.I1(\Lxx_2_reg_n_0_[11] ),
.I2(Lxx_0[11]),
.O(Lxx0_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h8E71718E718E8E71))
Lxx0_carry__2_i_4
(.I0(Lxx_0[14]),
.I1(\Lxx_2_reg_n_0_[14] ),
.I2(Lxx_1[14]),
.I3(\Lxx_2_reg_n_0_[15] ),
.I4(Lxx_1[15]),
.I5(Lxx_0[15]),
.O(Lxx0_carry__2_i_4_n_0));
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__2_i_5
(.I0(Lxx0_carry__2_i_1_n_0),
.I1(\Lxx_2_reg_n_0_[14] ),
.I2(Lxx_1[14]),
.I3(Lxx_0[14]),
.O(Lxx0_carry__2_i_5_n_0));
(* HLUTNM = "lutpair11" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__2_i_6
(.I0(Lxx_1[13]),
.I1(\Lxx_2_reg_n_0_[13] ),
.I2(Lxx_0[13]),
.I3(Lxx0_carry__2_i_2_n_0),
.O(Lxx0_carry__2_i_6_n_0));
(* HLUTNM = "lutpair10" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__2_i_7
(.I0(Lxx_1[12]),
.I1(\Lxx_2_reg_n_0_[12] ),
.I2(Lxx_0[12]),
.I3(Lxx0_carry__2_i_3_n_0),
.O(Lxx0_carry__2_i_7_n_0));
(* HLUTNM = "lutpair0" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry_i_1
(.I0(Lxx_1[2]),
.I1(\Lxx_2_reg_n_0_[2] ),
.I2(Lxx_0[2]),
.O(Lxx0_carry_i_1_n_0));
(* HLUTNM = "lutpair24" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry_i_2
(.I0(Lxx_1[1]),
.I1(\Lxx_2_reg_n_0_[1] ),
.I2(Lxx_0[1]),
.O(Lxx0_carry_i_2_n_0));
(* HLUTNM = "lutpair1" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry_i_3
(.I0(Lxx_1[3]),
.I1(\Lxx_2_reg_n_0_[3] ),
.I2(Lxx_0[3]),
.I3(Lxx0_carry_i_1_n_0),
.O(Lxx0_carry_i_3_n_0));
(* HLUTNM = "lutpair0" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry_i_4
(.I0(Lxx_1[2]),
.I1(\Lxx_2_reg_n_0_[2] ),
.I2(Lxx_0[2]),
.I3(Lxx0_carry_i_2_n_0),
.O(Lxx0_carry_i_4_n_0));
(* HLUTNM = "lutpair24" *)
LUT3 #(
.INIT(8'h96))
Lxx0_carry_i_5
(.I0(Lxx_1[1]),
.I1(\Lxx_2_reg_n_0_[1] ),
.I2(Lxx_0[1]),
.O(Lxx0_carry_i_5_n_0));
LUT2 #(
.INIT(4'h6))
Lxx0_carry_i_6
(.I0(\Lxx_2_reg_n_0_[0] ),
.I1(Lxx_0[0]),
.O(Lxx0_carry_i_6_n_0));
CARRY4 Lxx_00__1_carry
(.CI(1'b0),
.CO({Lxx_00__1_carry_n_0,Lxx_00__1_carry_n_1,Lxx_00__1_carry_n_2,Lxx_00__1_carry_n_3}),
.CYINIT(1'b0),
.DI({Lxx_00__1_carry_i_1_n_0,Lxx_00__1_carry_i_2_n_0,Lxx_00__1_carry_i_3_n_0,\bottom_right_0_reg_n_0_[0] }),
.O(Lxx_00[3:0]),
.S({Lxx_00__1_carry_i_4_n_0,Lxx_00__1_carry_i_5_n_0,Lxx_00__1_carry_i_6_n_0,Lxx_00__1_carry_i_7_n_0}));
CARRY4 Lxx_00__1_carry__0
(.CI(Lxx_00__1_carry_n_0),
.CO({Lxx_00__1_carry__0_n_0,Lxx_00__1_carry__0_n_1,Lxx_00__1_carry__0_n_2,Lxx_00__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lxx_00__1_carry__0_i_1_n_0,Lxx_00__1_carry__0_i_2_n_0,Lxx_00__1_carry__0_i_3_n_0,Lxx_00__1_carry__0_i_4_n_0}),
.O(Lxx_00[7:4]),
.S({Lxx_00__1_carry__0_i_5_n_0,Lxx_00__1_carry__0_i_6_n_0,Lxx_00__1_carry__0_i_7_n_0,Lxx_00__1_carry__0_i_8_n_0}));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__0_i_1
(.I0(\bottom_right_0_reg_n_0_[6] ),
.I1(Lxx_00__1_carry__0_i_9_n_0),
.I2(\top_left_0_reg_n_0_[5] ),
.I3(\top_right_0_reg_n_0_[5] ),
.I4(\bottom_left_0_reg_n_0_[5] ),
.O(Lxx_00__1_carry__0_i_1_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__0_i_10
(.I0(\bottom_left_0_reg_n_0_[5] ),
.I1(\top_right_0_reg_n_0_[5] ),
.I2(\top_left_0_reg_n_0_[5] ),
.O(Lxx_00__1_carry__0_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__0_i_11
(.I0(\bottom_left_0_reg_n_0_[4] ),
.I1(\top_right_0_reg_n_0_[4] ),
.I2(\top_left_0_reg_n_0_[4] ),
.O(Lxx_00__1_carry__0_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__0_i_12
(.I0(\bottom_left_0_reg_n_0_[7] ),
.I1(\top_right_0_reg_n_0_[7] ),
.I2(\top_left_0_reg_n_0_[7] ),
.O(Lxx_00__1_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__0_i_2
(.I0(\bottom_right_0_reg_n_0_[5] ),
.I1(Lxx_00__1_carry__0_i_10_n_0),
.I2(\top_left_0_reg_n_0_[4] ),
.I3(\top_right_0_reg_n_0_[4] ),
.I4(\bottom_left_0_reg_n_0_[4] ),
.O(Lxx_00__1_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__0_i_3
(.I0(\bottom_right_0_reg_n_0_[4] ),
.I1(Lxx_00__1_carry__0_i_11_n_0),
.I2(\top_left_0_reg_n_0_[3] ),
.I3(\top_right_0_reg_n_0_[3] ),
.I4(\bottom_left_0_reg_n_0_[3] ),
.O(Lxx_00__1_carry__0_i_3_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__0_i_4
(.I0(\bottom_right_0_reg_n_0_[3] ),
.I1(Lxx_00__1_carry_i_8_n_0),
.I2(\top_left_0_reg_n_0_[2] ),
.I3(\top_right_0_reg_n_0_[2] ),
.I4(\bottom_left_0_reg_n_0_[2] ),
.O(Lxx_00__1_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__0_i_5
(.I0(Lxx_00__1_carry__0_i_1_n_0),
.I1(\top_left_0_reg_n_0_[6] ),
.I2(\top_right_0_reg_n_0_[6] ),
.I3(\bottom_left_0_reg_n_0_[6] ),
.I4(\bottom_right_0_reg_n_0_[7] ),
.I5(Lxx_00__1_carry__0_i_12_n_0),
.O(Lxx_00__1_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__0_i_6
(.I0(Lxx_00__1_carry__0_i_2_n_0),
.I1(\top_left_0_reg_n_0_[5] ),
.I2(\top_right_0_reg_n_0_[5] ),
.I3(\bottom_left_0_reg_n_0_[5] ),
.I4(\bottom_right_0_reg_n_0_[6] ),
.I5(Lxx_00__1_carry__0_i_9_n_0),
.O(Lxx_00__1_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__0_i_7
(.I0(Lxx_00__1_carry__0_i_3_n_0),
.I1(\top_left_0_reg_n_0_[4] ),
.I2(\top_right_0_reg_n_0_[4] ),
.I3(\bottom_left_0_reg_n_0_[4] ),
.I4(\bottom_right_0_reg_n_0_[5] ),
.I5(Lxx_00__1_carry__0_i_10_n_0),
.O(Lxx_00__1_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__0_i_8
(.I0(Lxx_00__1_carry__0_i_4_n_0),
.I1(\top_left_0_reg_n_0_[3] ),
.I2(\top_right_0_reg_n_0_[3] ),
.I3(\bottom_left_0_reg_n_0_[3] ),
.I4(\bottom_right_0_reg_n_0_[4] ),
.I5(Lxx_00__1_carry__0_i_11_n_0),
.O(Lxx_00__1_carry__0_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__0_i_9
(.I0(\bottom_left_0_reg_n_0_[6] ),
.I1(\top_right_0_reg_n_0_[6] ),
.I2(\top_left_0_reg_n_0_[6] ),
.O(Lxx_00__1_carry__0_i_9_n_0));
CARRY4 Lxx_00__1_carry__1
(.CI(Lxx_00__1_carry__0_n_0),
.CO({Lxx_00__1_carry__1_n_0,Lxx_00__1_carry__1_n_1,Lxx_00__1_carry__1_n_2,Lxx_00__1_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lxx_00__1_carry__1_i_1_n_0,Lxx_00__1_carry__1_i_2_n_0,Lxx_00__1_carry__1_i_3_n_0,Lxx_00__1_carry__1_i_4_n_0}),
.O(Lxx_00[11:8]),
.S({Lxx_00__1_carry__1_i_5_n_0,Lxx_00__1_carry__1_i_6_n_0,Lxx_00__1_carry__1_i_7_n_0,Lxx_00__1_carry__1_i_8_n_0}));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__1_i_1
(.I0(\bottom_right_0_reg_n_0_[10] ),
.I1(Lxx_00__1_carry__1_i_9_n_0),
.I2(\top_left_0_reg_n_0_[9] ),
.I3(\top_right_0_reg_n_0_[9] ),
.I4(\bottom_left_0_reg_n_0_[9] ),
.O(Lxx_00__1_carry__1_i_1_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__1_i_10
(.I0(\bottom_left_0_reg_n_0_[9] ),
.I1(\top_right_0_reg_n_0_[9] ),
.I2(\top_left_0_reg_n_0_[9] ),
.O(Lxx_00__1_carry__1_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__1_i_11
(.I0(\bottom_left_0_reg_n_0_[8] ),
.I1(\top_right_0_reg_n_0_[8] ),
.I2(\top_left_0_reg_n_0_[8] ),
.O(Lxx_00__1_carry__1_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__1_i_12
(.I0(\bottom_left_0_reg_n_0_[11] ),
.I1(\top_right_0_reg_n_0_[11] ),
.I2(\top_left_0_reg_n_0_[11] ),
.O(Lxx_00__1_carry__1_i_12_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__1_i_2
(.I0(\bottom_right_0_reg_n_0_[9] ),
.I1(Lxx_00__1_carry__1_i_10_n_0),
.I2(\top_left_0_reg_n_0_[8] ),
.I3(\top_right_0_reg_n_0_[8] ),
.I4(\bottom_left_0_reg_n_0_[8] ),
.O(Lxx_00__1_carry__1_i_2_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__1_i_3
(.I0(\bottom_right_0_reg_n_0_[8] ),
.I1(Lxx_00__1_carry__1_i_11_n_0),
.I2(\top_left_0_reg_n_0_[7] ),
.I3(\top_right_0_reg_n_0_[7] ),
.I4(\bottom_left_0_reg_n_0_[7] ),
.O(Lxx_00__1_carry__1_i_3_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__1_i_4
(.I0(\bottom_right_0_reg_n_0_[7] ),
.I1(Lxx_00__1_carry__0_i_12_n_0),
.I2(\top_left_0_reg_n_0_[6] ),
.I3(\top_right_0_reg_n_0_[6] ),
.I4(\bottom_left_0_reg_n_0_[6] ),
.O(Lxx_00__1_carry__1_i_4_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__1_i_5
(.I0(Lxx_00__1_carry__1_i_1_n_0),
.I1(\top_left_0_reg_n_0_[10] ),
.I2(\top_right_0_reg_n_0_[10] ),
.I3(\bottom_left_0_reg_n_0_[10] ),
.I4(\bottom_right_0_reg_n_0_[11] ),
.I5(Lxx_00__1_carry__1_i_12_n_0),
.O(Lxx_00__1_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__1_i_6
(.I0(Lxx_00__1_carry__1_i_2_n_0),
.I1(\top_left_0_reg_n_0_[9] ),
.I2(\top_right_0_reg_n_0_[9] ),
.I3(\bottom_left_0_reg_n_0_[9] ),
.I4(\bottom_right_0_reg_n_0_[10] ),
.I5(Lxx_00__1_carry__1_i_9_n_0),
.O(Lxx_00__1_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__1_i_7
(.I0(Lxx_00__1_carry__1_i_3_n_0),
.I1(\top_left_0_reg_n_0_[8] ),
.I2(\top_right_0_reg_n_0_[8] ),
.I3(\bottom_left_0_reg_n_0_[8] ),
.I4(\bottom_right_0_reg_n_0_[9] ),
.I5(Lxx_00__1_carry__1_i_10_n_0),
.O(Lxx_00__1_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__1_i_8
(.I0(Lxx_00__1_carry__1_i_4_n_0),
.I1(\top_left_0_reg_n_0_[7] ),
.I2(\top_right_0_reg_n_0_[7] ),
.I3(\bottom_left_0_reg_n_0_[7] ),
.I4(\bottom_right_0_reg_n_0_[8] ),
.I5(Lxx_00__1_carry__1_i_11_n_0),
.O(Lxx_00__1_carry__1_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__1_i_9
(.I0(\bottom_left_0_reg_n_0_[10] ),
.I1(\top_right_0_reg_n_0_[10] ),
.I2(\top_left_0_reg_n_0_[10] ),
.O(Lxx_00__1_carry__1_i_9_n_0));
CARRY4 Lxx_00__1_carry__2
(.CI(Lxx_00__1_carry__1_n_0),
.CO({NLW_Lxx_00__1_carry__2_CO_UNCONNECTED[3],Lxx_00__1_carry__2_n_1,Lxx_00__1_carry__2_n_2,Lxx_00__1_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lxx_00__1_carry__2_i_1_n_0,Lxx_00__1_carry__2_i_2_n_0,Lxx_00__1_carry__2_i_3_n_0}),
.O(Lxx_00[15:12]),
.S({Lxx_00__1_carry__2_i_4_n_0,Lxx_00__1_carry__2_i_5_n_0,Lxx_00__1_carry__2_i_6_n_0,Lxx_00__1_carry__2_i_7_n_0}));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__2_i_1
(.I0(\bottom_right_0_reg_n_0_[13] ),
.I1(Lxx_00__1_carry__2_i_8_n_0),
.I2(\top_left_0_reg_n_0_[12] ),
.I3(\top_right_0_reg_n_0_[12] ),
.I4(\bottom_left_0_reg_n_0_[12] ),
.O(Lxx_00__1_carry__2_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'h2B))
Lxx_00__1_carry__2_i_10
(.I0(\top_left_0_reg_n_0_[13] ),
.I1(\top_right_0_reg_n_0_[13] ),
.I2(\bottom_left_0_reg_n_0_[13] ),
.O(Lxx_00__1_carry__2_i_10_n_0));
LUT4 #(
.INIT(16'h6996))
Lxx_00__1_carry__2_i_11
(.I0(\top_right_0_reg_n_0_[15] ),
.I1(\bottom_left_0_reg_n_0_[15] ),
.I2(\bottom_right_0_reg_n_0_[15] ),
.I3(\top_left_0_reg_n_0_[15] ),
.O(Lxx_00__1_carry__2_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__2_i_12
(.I0(\bottom_left_0_reg_n_0_[14] ),
.I1(\top_right_0_reg_n_0_[14] ),
.I2(\top_left_0_reg_n_0_[14] ),
.O(Lxx_00__1_carry__2_i_12_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__2_i_2
(.I0(\bottom_right_0_reg_n_0_[12] ),
.I1(Lxx_00__1_carry__2_i_9_n_0),
.I2(\top_left_0_reg_n_0_[11] ),
.I3(\top_right_0_reg_n_0_[11] ),
.I4(\bottom_left_0_reg_n_0_[11] ),
.O(Lxx_00__1_carry__2_i_2_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__2_i_3
(.I0(\bottom_right_0_reg_n_0_[11] ),
.I1(Lxx_00__1_carry__1_i_12_n_0),
.I2(\top_left_0_reg_n_0_[10] ),
.I3(\top_right_0_reg_n_0_[10] ),
.I4(\bottom_left_0_reg_n_0_[10] ),
.O(Lxx_00__1_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h178181E8E87E7E17))
Lxx_00__1_carry__2_i_4
(.I0(Lxx_00__1_carry__2_i_10_n_0),
.I1(\bottom_right_0_reg_n_0_[14] ),
.I2(\top_left_0_reg_n_0_[14] ),
.I3(\top_right_0_reg_n_0_[14] ),
.I4(\bottom_left_0_reg_n_0_[14] ),
.I5(Lxx_00__1_carry__2_i_11_n_0),
.O(Lxx_00__1_carry__2_i_4_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__2_i_5
(.I0(Lxx_00__1_carry__2_i_1_n_0),
.I1(\top_left_0_reg_n_0_[13] ),
.I2(\top_right_0_reg_n_0_[13] ),
.I3(\bottom_left_0_reg_n_0_[13] ),
.I4(\bottom_right_0_reg_n_0_[14] ),
.I5(Lxx_00__1_carry__2_i_12_n_0),
.O(Lxx_00__1_carry__2_i_5_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__2_i_6
(.I0(Lxx_00__1_carry__2_i_2_n_0),
.I1(\top_left_0_reg_n_0_[12] ),
.I2(\top_right_0_reg_n_0_[12] ),
.I3(\bottom_left_0_reg_n_0_[12] ),
.I4(\bottom_right_0_reg_n_0_[13] ),
.I5(Lxx_00__1_carry__2_i_8_n_0),
.O(Lxx_00__1_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__2_i_7
(.I0(Lxx_00__1_carry__2_i_3_n_0),
.I1(\top_left_0_reg_n_0_[11] ),
.I2(\top_right_0_reg_n_0_[11] ),
.I3(\bottom_left_0_reg_n_0_[11] ),
.I4(\bottom_right_0_reg_n_0_[12] ),
.I5(Lxx_00__1_carry__2_i_9_n_0),
.O(Lxx_00__1_carry__2_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__2_i_8
(.I0(\bottom_left_0_reg_n_0_[13] ),
.I1(\top_right_0_reg_n_0_[13] ),
.I2(\top_left_0_reg_n_0_[13] ),
.O(Lxx_00__1_carry__2_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__2_i_9
(.I0(\bottom_left_0_reg_n_0_[12] ),
.I1(\top_right_0_reg_n_0_[12] ),
.I2(\top_left_0_reg_n_0_[12] ),
.O(Lxx_00__1_carry__2_i_9_n_0));
LUT6 #(
.INIT(64'h8228EBBEEBBEEBBE))
Lxx_00__1_carry_i_1
(.I0(\bottom_right_0_reg_n_0_[2] ),
.I1(\top_left_0_reg_n_0_[2] ),
.I2(\top_right_0_reg_n_0_[2] ),
.I3(\bottom_left_0_reg_n_0_[2] ),
.I4(\bottom_left_0_reg_n_0_[1] ),
.I5(\top_right_0_reg_n_0_[1] ),
.O(Lxx_00__1_carry_i_1_n_0));
LUT4 #(
.INIT(16'hF990))
Lxx_00__1_carry_i_2
(.I0(\bottom_left_0_reg_n_0_[1] ),
.I1(\top_right_0_reg_n_0_[1] ),
.I2(\top_left_0_reg_n_0_[1] ),
.I3(\bottom_right_0_reg_n_0_[1] ),
.O(Lxx_00__1_carry_i_2_n_0));
LUT4 #(
.INIT(16'h9669))
Lxx_00__1_carry_i_3
(.I0(\top_right_0_reg_n_0_[1] ),
.I1(\bottom_left_0_reg_n_0_[1] ),
.I2(\bottom_right_0_reg_n_0_[1] ),
.I3(\top_left_0_reg_n_0_[1] ),
.O(Lxx_00__1_carry_i_3_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry_i_4
(.I0(Lxx_00__1_carry_i_1_n_0),
.I1(\top_left_0_reg_n_0_[2] ),
.I2(\top_right_0_reg_n_0_[2] ),
.I3(\bottom_left_0_reg_n_0_[2] ),
.I4(\bottom_right_0_reg_n_0_[3] ),
.I5(Lxx_00__1_carry_i_8_n_0),
.O(Lxx_00__1_carry_i_4_n_0));
LUT5 #(
.INIT(32'h96696969))
Lxx_00__1_carry_i_5
(.I0(Lxx_00__1_carry_i_2_n_0),
.I1(\bottom_right_0_reg_n_0_[2] ),
.I2(Lxx_00__1_carry_i_9_n_0),
.I3(\bottom_left_0_reg_n_0_[1] ),
.I4(\top_right_0_reg_n_0_[1] ),
.O(Lxx_00__1_carry_i_5_n_0));
LUT4 #(
.INIT(16'hA665))
Lxx_00__1_carry_i_6
(.I0(Lxx_00__1_carry_i_3_n_0),
.I1(\top_left_0_reg_n_0_[0] ),
.I2(\top_right_0_reg_n_0_[0] ),
.I3(\bottom_left_0_reg_n_0_[0] ),
.O(Lxx_00__1_carry_i_6_n_0));
LUT4 #(
.INIT(16'h6996))
Lxx_00__1_carry_i_7
(.I0(\bottom_left_0_reg_n_0_[0] ),
.I1(\top_right_0_reg_n_0_[0] ),
.I2(\top_left_0_reg_n_0_[0] ),
.I3(\bottom_right_0_reg_n_0_[0] ),
.O(Lxx_00__1_carry_i_7_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry_i_8
(.I0(\bottom_left_0_reg_n_0_[3] ),
.I1(\top_right_0_reg_n_0_[3] ),
.I2(\top_left_0_reg_n_0_[3] ),
.O(Lxx_00__1_carry_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry_i_9
(.I0(\bottom_left_0_reg_n_0_[2] ),
.I1(\top_right_0_reg_n_0_[2] ),
.I2(\top_left_0_reg_n_0_[2] ),
.O(Lxx_00__1_carry_i_9_n_0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[0]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[0]),
.Q(Lxx_0[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[10]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[10]),
.Q(Lxx_0[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[11]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[11]),
.Q(Lxx_0[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[12]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[12]),
.Q(Lxx_0[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[13]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[13]),
.Q(Lxx_0[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[14]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[14]),
.Q(Lxx_0[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[15]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[15]),
.Q(Lxx_0[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[1]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[1]),
.Q(Lxx_0[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[2]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[2]),
.Q(Lxx_0[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[3]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[3]),
.Q(Lxx_0[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[4]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[4]),
.Q(Lxx_0[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[5]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[5]),
.Q(Lxx_0[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[6]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[6]),
.Q(Lxx_0[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[7]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[7]),
.Q(Lxx_0[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[8]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[8]),
.Q(Lxx_0[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[9]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[9]),
.Q(Lxx_0[9]),
.R(1'b0));
CARRY4 Lxx_11__1_carry
(.CI(1'b0),
.CO({Lxx_11__1_carry_n_0,Lxx_11__1_carry_n_1,Lxx_11__1_carry_n_2,Lxx_11__1_carry_n_3}),
.CYINIT(1'b0),
.DI({Lxx_11__1_carry_i_1_n_0,Lxx_11__1_carry_i_2_n_0,Lxx_11__1_carry_i_3_n_0,\bottom_right_1_reg_n_0_[0] }),
.O(Lxx_11[3:0]),
.S({Lxx_11__1_carry_i_4_n_0,Lxx_11__1_carry_i_5_n_0,Lxx_11__1_carry_i_6_n_0,Lxx_11__1_carry_i_7_n_0}));
CARRY4 Lxx_11__1_carry__0
(.CI(Lxx_11__1_carry_n_0),
.CO({Lxx_11__1_carry__0_n_0,Lxx_11__1_carry__0_n_1,Lxx_11__1_carry__0_n_2,Lxx_11__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lxx_11__1_carry__0_i_1_n_0,Lxx_11__1_carry__0_i_2_n_0,Lxx_11__1_carry__0_i_3_n_0,Lxx_11__1_carry__0_i_4_n_0}),
.O(Lxx_11[7:4]),
.S({Lxx_11__1_carry__0_i_5_n_0,Lxx_11__1_carry__0_i_6_n_0,Lxx_11__1_carry__0_i_7_n_0,Lxx_11__1_carry__0_i_8_n_0}));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__0_i_1
(.I0(\bottom_right_1_reg_n_0_[6] ),
.I1(Lxx_11__1_carry__0_i_9_n_0),
.I2(top_left_1[5]),
.I3(\top_right_1_reg_n_0_[5] ),
.I4(bottom_left_1[5]),
.O(Lxx_11__1_carry__0_i_1_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__0_i_10
(.I0(bottom_left_1[5]),
.I1(\top_right_1_reg_n_0_[5] ),
.I2(top_left_1[5]),
.O(Lxx_11__1_carry__0_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__0_i_11
(.I0(bottom_left_1[4]),
.I1(\top_right_1_reg_n_0_[4] ),
.I2(top_left_1[4]),
.O(Lxx_11__1_carry__0_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__0_i_12
(.I0(bottom_left_1[7]),
.I1(\top_right_1_reg_n_0_[7] ),
.I2(top_left_1[7]),
.O(Lxx_11__1_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__0_i_2
(.I0(\bottom_right_1_reg_n_0_[5] ),
.I1(Lxx_11__1_carry__0_i_10_n_0),
.I2(top_left_1[4]),
.I3(\top_right_1_reg_n_0_[4] ),
.I4(bottom_left_1[4]),
.O(Lxx_11__1_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__0_i_3
(.I0(\bottom_right_1_reg_n_0_[4] ),
.I1(Lxx_11__1_carry__0_i_11_n_0),
.I2(top_left_1[3]),
.I3(\top_right_1_reg_n_0_[3] ),
.I4(bottom_left_1[3]),
.O(Lxx_11__1_carry__0_i_3_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__0_i_4
(.I0(\bottom_right_1_reg_n_0_[3] ),
.I1(Lxx_11__1_carry_i_8_n_0),
.I2(top_left_1[2]),
.I3(\top_right_1_reg_n_0_[2] ),
.I4(bottom_left_1[2]),
.O(Lxx_11__1_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__0_i_5
(.I0(Lxx_11__1_carry__0_i_1_n_0),
.I1(top_left_1[6]),
.I2(\top_right_1_reg_n_0_[6] ),
.I3(bottom_left_1[6]),
.I4(\bottom_right_1_reg_n_0_[7] ),
.I5(Lxx_11__1_carry__0_i_12_n_0),
.O(Lxx_11__1_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__0_i_6
(.I0(Lxx_11__1_carry__0_i_2_n_0),
.I1(top_left_1[5]),
.I2(\top_right_1_reg_n_0_[5] ),
.I3(bottom_left_1[5]),
.I4(\bottom_right_1_reg_n_0_[6] ),
.I5(Lxx_11__1_carry__0_i_9_n_0),
.O(Lxx_11__1_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__0_i_7
(.I0(Lxx_11__1_carry__0_i_3_n_0),
.I1(top_left_1[4]),
.I2(\top_right_1_reg_n_0_[4] ),
.I3(bottom_left_1[4]),
.I4(\bottom_right_1_reg_n_0_[5] ),
.I5(Lxx_11__1_carry__0_i_10_n_0),
.O(Lxx_11__1_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__0_i_8
(.I0(Lxx_11__1_carry__0_i_4_n_0),
.I1(top_left_1[3]),
.I2(\top_right_1_reg_n_0_[3] ),
.I3(bottom_left_1[3]),
.I4(\bottom_right_1_reg_n_0_[4] ),
.I5(Lxx_11__1_carry__0_i_11_n_0),
.O(Lxx_11__1_carry__0_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__0_i_9
(.I0(bottom_left_1[6]),
.I1(\top_right_1_reg_n_0_[6] ),
.I2(top_left_1[6]),
.O(Lxx_11__1_carry__0_i_9_n_0));
CARRY4 Lxx_11__1_carry__1
(.CI(Lxx_11__1_carry__0_n_0),
.CO({Lxx_11__1_carry__1_n_0,Lxx_11__1_carry__1_n_1,Lxx_11__1_carry__1_n_2,Lxx_11__1_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lxx_11__1_carry__1_i_1_n_0,Lxx_11__1_carry__1_i_2_n_0,Lxx_11__1_carry__1_i_3_n_0,Lxx_11__1_carry__1_i_4_n_0}),
.O(Lxx_11[11:8]),
.S({Lxx_11__1_carry__1_i_5_n_0,Lxx_11__1_carry__1_i_6_n_0,Lxx_11__1_carry__1_i_7_n_0,Lxx_11__1_carry__1_i_8_n_0}));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__1_i_1
(.I0(\bottom_right_1_reg_n_0_[10] ),
.I1(Lxx_11__1_carry__1_i_9_n_0),
.I2(top_left_1[9]),
.I3(\top_right_1_reg_n_0_[9] ),
.I4(bottom_left_1[9]),
.O(Lxx_11__1_carry__1_i_1_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__1_i_10
(.I0(bottom_left_1[9]),
.I1(\top_right_1_reg_n_0_[9] ),
.I2(top_left_1[9]),
.O(Lxx_11__1_carry__1_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__1_i_11
(.I0(bottom_left_1[8]),
.I1(\top_right_1_reg_n_0_[8] ),
.I2(top_left_1[8]),
.O(Lxx_11__1_carry__1_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__1_i_12
(.I0(bottom_left_1[11]),
.I1(\top_right_1_reg_n_0_[11] ),
.I2(top_left_1[11]),
.O(Lxx_11__1_carry__1_i_12_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__1_i_2
(.I0(\bottom_right_1_reg_n_0_[9] ),
.I1(Lxx_11__1_carry__1_i_10_n_0),
.I2(top_left_1[8]),
.I3(\top_right_1_reg_n_0_[8] ),
.I4(bottom_left_1[8]),
.O(Lxx_11__1_carry__1_i_2_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__1_i_3
(.I0(\bottom_right_1_reg_n_0_[8] ),
.I1(Lxx_11__1_carry__1_i_11_n_0),
.I2(top_left_1[7]),
.I3(\top_right_1_reg_n_0_[7] ),
.I4(bottom_left_1[7]),
.O(Lxx_11__1_carry__1_i_3_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__1_i_4
(.I0(\bottom_right_1_reg_n_0_[7] ),
.I1(Lxx_11__1_carry__0_i_12_n_0),
.I2(top_left_1[6]),
.I3(\top_right_1_reg_n_0_[6] ),
.I4(bottom_left_1[6]),
.O(Lxx_11__1_carry__1_i_4_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__1_i_5
(.I0(Lxx_11__1_carry__1_i_1_n_0),
.I1(top_left_1[10]),
.I2(\top_right_1_reg_n_0_[10] ),
.I3(bottom_left_1[10]),
.I4(\bottom_right_1_reg_n_0_[11] ),
.I5(Lxx_11__1_carry__1_i_12_n_0),
.O(Lxx_11__1_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__1_i_6
(.I0(Lxx_11__1_carry__1_i_2_n_0),
.I1(top_left_1[9]),
.I2(\top_right_1_reg_n_0_[9] ),
.I3(bottom_left_1[9]),
.I4(\bottom_right_1_reg_n_0_[10] ),
.I5(Lxx_11__1_carry__1_i_9_n_0),
.O(Lxx_11__1_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__1_i_7
(.I0(Lxx_11__1_carry__1_i_3_n_0),
.I1(top_left_1[8]),
.I2(\top_right_1_reg_n_0_[8] ),
.I3(bottom_left_1[8]),
.I4(\bottom_right_1_reg_n_0_[9] ),
.I5(Lxx_11__1_carry__1_i_10_n_0),
.O(Lxx_11__1_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__1_i_8
(.I0(Lxx_11__1_carry__1_i_4_n_0),
.I1(top_left_1[7]),
.I2(\top_right_1_reg_n_0_[7] ),
.I3(bottom_left_1[7]),
.I4(\bottom_right_1_reg_n_0_[8] ),
.I5(Lxx_11__1_carry__1_i_11_n_0),
.O(Lxx_11__1_carry__1_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__1_i_9
(.I0(bottom_left_1[10]),
.I1(\top_right_1_reg_n_0_[10] ),
.I2(top_left_1[10]),
.O(Lxx_11__1_carry__1_i_9_n_0));
CARRY4 Lxx_11__1_carry__2
(.CI(Lxx_11__1_carry__1_n_0),
.CO({NLW_Lxx_11__1_carry__2_CO_UNCONNECTED[3],Lxx_11__1_carry__2_n_1,Lxx_11__1_carry__2_n_2,Lxx_11__1_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lxx_11__1_carry__2_i_1_n_0,Lxx_11__1_carry__2_i_2_n_0,Lxx_11__1_carry__2_i_3_n_0}),
.O(Lxx_11[15:12]),
.S({Lxx_11__1_carry__2_i_4_n_0,Lxx_11__1_carry__2_i_5_n_0,Lxx_11__1_carry__2_i_6_n_0,Lxx_11__1_carry__2_i_7_n_0}));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__2_i_1
(.I0(\bottom_right_1_reg_n_0_[13] ),
.I1(Lxx_11__1_carry__2_i_8_n_0),
.I2(top_left_1[12]),
.I3(\top_right_1_reg_n_0_[12] ),
.I4(bottom_left_1[12]),
.O(Lxx_11__1_carry__2_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'h2B))
Lxx_11__1_carry__2_i_10
(.I0(top_left_1[13]),
.I1(\top_right_1_reg_n_0_[13] ),
.I2(bottom_left_1[13]),
.O(Lxx_11__1_carry__2_i_10_n_0));
LUT4 #(
.INIT(16'h6996))
Lxx_11__1_carry__2_i_11
(.I0(\top_right_1_reg_n_0_[15] ),
.I1(bottom_left_1[15]),
.I2(\bottom_right_1_reg_n_0_[15] ),
.I3(top_left_1[15]),
.O(Lxx_11__1_carry__2_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__2_i_12
(.I0(bottom_left_1[14]),
.I1(\top_right_1_reg_n_0_[14] ),
.I2(top_left_1[14]),
.O(Lxx_11__1_carry__2_i_12_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__2_i_2
(.I0(\bottom_right_1_reg_n_0_[12] ),
.I1(Lxx_11__1_carry__2_i_9_n_0),
.I2(top_left_1[11]),
.I3(\top_right_1_reg_n_0_[11] ),
.I4(bottom_left_1[11]),
.O(Lxx_11__1_carry__2_i_2_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__2_i_3
(.I0(\bottom_right_1_reg_n_0_[11] ),
.I1(Lxx_11__1_carry__1_i_12_n_0),
.I2(top_left_1[10]),
.I3(\top_right_1_reg_n_0_[10] ),
.I4(bottom_left_1[10]),
.O(Lxx_11__1_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h178181E8E87E7E17))
Lxx_11__1_carry__2_i_4
(.I0(Lxx_11__1_carry__2_i_10_n_0),
.I1(\bottom_right_1_reg_n_0_[14] ),
.I2(top_left_1[14]),
.I3(\top_right_1_reg_n_0_[14] ),
.I4(bottom_left_1[14]),
.I5(Lxx_11__1_carry__2_i_11_n_0),
.O(Lxx_11__1_carry__2_i_4_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__2_i_5
(.I0(Lxx_11__1_carry__2_i_1_n_0),
.I1(top_left_1[13]),
.I2(\top_right_1_reg_n_0_[13] ),
.I3(bottom_left_1[13]),
.I4(\bottom_right_1_reg_n_0_[14] ),
.I5(Lxx_11__1_carry__2_i_12_n_0),
.O(Lxx_11__1_carry__2_i_5_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__2_i_6
(.I0(Lxx_11__1_carry__2_i_2_n_0),
.I1(top_left_1[12]),
.I2(\top_right_1_reg_n_0_[12] ),
.I3(bottom_left_1[12]),
.I4(\bottom_right_1_reg_n_0_[13] ),
.I5(Lxx_11__1_carry__2_i_8_n_0),
.O(Lxx_11__1_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__2_i_7
(.I0(Lxx_11__1_carry__2_i_3_n_0),
.I1(top_left_1[11]),
.I2(\top_right_1_reg_n_0_[11] ),
.I3(bottom_left_1[11]),
.I4(\bottom_right_1_reg_n_0_[12] ),
.I5(Lxx_11__1_carry__2_i_9_n_0),
.O(Lxx_11__1_carry__2_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__2_i_8
(.I0(bottom_left_1[13]),
.I1(\top_right_1_reg_n_0_[13] ),
.I2(top_left_1[13]),
.O(Lxx_11__1_carry__2_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__2_i_9
(.I0(bottom_left_1[12]),
.I1(\top_right_1_reg_n_0_[12] ),
.I2(top_left_1[12]),
.O(Lxx_11__1_carry__2_i_9_n_0));
LUT6 #(
.INIT(64'h8228EBBEEBBEEBBE))
Lxx_11__1_carry_i_1
(.I0(\bottom_right_1_reg_n_0_[2] ),
.I1(top_left_1[2]),
.I2(\top_right_1_reg_n_0_[2] ),
.I3(bottom_left_1[2]),
.I4(bottom_left_1[1]),
.I5(\top_right_1_reg_n_0_[1] ),
.O(Lxx_11__1_carry_i_1_n_0));
LUT4 #(
.INIT(16'hF990))
Lxx_11__1_carry_i_2
(.I0(bottom_left_1[1]),
.I1(\top_right_1_reg_n_0_[1] ),
.I2(top_left_1[1]),
.I3(\bottom_right_1_reg_n_0_[1] ),
.O(Lxx_11__1_carry_i_2_n_0));
LUT4 #(
.INIT(16'h9669))
Lxx_11__1_carry_i_3
(.I0(\top_right_1_reg_n_0_[1] ),
.I1(bottom_left_1[1]),
.I2(\bottom_right_1_reg_n_0_[1] ),
.I3(top_left_1[1]),
.O(Lxx_11__1_carry_i_3_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry_i_4
(.I0(Lxx_11__1_carry_i_1_n_0),
.I1(top_left_1[2]),
.I2(\top_right_1_reg_n_0_[2] ),
.I3(bottom_left_1[2]),
.I4(\bottom_right_1_reg_n_0_[3] ),
.I5(Lxx_11__1_carry_i_8_n_0),
.O(Lxx_11__1_carry_i_4_n_0));
LUT5 #(
.INIT(32'h96696969))
Lxx_11__1_carry_i_5
(.I0(Lxx_11__1_carry_i_2_n_0),
.I1(\bottom_right_1_reg_n_0_[2] ),
.I2(Lxx_11__1_carry_i_9_n_0),
.I3(bottom_left_1[1]),
.I4(\top_right_1_reg_n_0_[1] ),
.O(Lxx_11__1_carry_i_5_n_0));
LUT4 #(
.INIT(16'hA665))
Lxx_11__1_carry_i_6
(.I0(Lxx_11__1_carry_i_3_n_0),
.I1(top_left_1[0]),
.I2(\top_right_1_reg_n_0_[0] ),
.I3(bottom_left_1[0]),
.O(Lxx_11__1_carry_i_6_n_0));
LUT4 #(
.INIT(16'h6996))
Lxx_11__1_carry_i_7
(.I0(bottom_left_1[0]),
.I1(\top_right_1_reg_n_0_[0] ),
.I2(top_left_1[0]),
.I3(\bottom_right_1_reg_n_0_[0] ),
.O(Lxx_11__1_carry_i_7_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry_i_8
(.I0(bottom_left_1[3]),
.I1(\top_right_1_reg_n_0_[3] ),
.I2(top_left_1[3]),
.O(Lxx_11__1_carry_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry_i_9
(.I0(bottom_left_1[2]),
.I1(\top_right_1_reg_n_0_[2] ),
.I2(top_left_1[2]),
.O(Lxx_11__1_carry_i_9_n_0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[10]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[9]),
.Q(Lxx_1[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[11]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[10]),
.Q(Lxx_1[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[12]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[11]),
.Q(Lxx_1[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[13]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[12]),
.Q(Lxx_1[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[14]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[13]),
.Q(Lxx_1[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[15]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[14]),
.Q(Lxx_1[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[1]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[0]),
.Q(Lxx_1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[2]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[1]),
.Q(Lxx_1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[3]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[2]),
.Q(Lxx_1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[4]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[3]),
.Q(Lxx_1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[5]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[4]),
.Q(Lxx_1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[6]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[5]),
.Q(Lxx_1[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[7]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[6]),
.Q(Lxx_1[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[8]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[7]),
.Q(Lxx_1[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[9]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[8]),
.Q(Lxx_1[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h0010000000000000))
\Lxx_2[15]_i_1
(.I0(cycle[3]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(cycle[2]),
.I4(rst),
.I5(active),
.O(\Lxx_2[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[0]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[0]),
.Q(\Lxx_2_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[10]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[10]),
.Q(\Lxx_2_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[11]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[11]),
.Q(\Lxx_2_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[12]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[12]),
.Q(\Lxx_2_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[13]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[13]),
.Q(\Lxx_2_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[14]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[14]),
.Q(\Lxx_2_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[15]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[15]),
.Q(\Lxx_2_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[1]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[1]),
.Q(\Lxx_2_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[2]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[2]),
.Q(\Lxx_2_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[3]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[3]),
.Q(\Lxx_2_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[4]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[4]),
.Q(\Lxx_2_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[5]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[5]),
.Q(\Lxx_2_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[6]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[6]),
.Q(\Lxx_2_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[7]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[7]),
.Q(\Lxx_2_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[8]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[8]),
.Q(\Lxx_2_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[9]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[9]),
.Q(\Lxx_2_reg_n_0_[9] ),
.R(1'b0));
CARRY4 Lxy0__1_carry
(.CI(1'b0),
.CO({Lxy0__1_carry_n_0,Lxy0__1_carry_n_1,Lxy0__1_carry_n_2,Lxy0__1_carry_n_3}),
.CYINIT(1'b0),
.DI({Lxy0__1_carry_i_1_n_0,Lxy0__1_carry_i_2_n_0,Lxy0__1_carry_i_3_n_0,\Lxy_0_reg_n_0_[0] }),
.O({Lxy0__1_carry_n_4,Lxy0__1_carry_n_5,Lxy0__1_carry_n_6,Lxy0__1_carry_n_7}),
.S({Lxy0__1_carry_i_4_n_0,Lxy0__1_carry_i_5_n_0,Lxy0__1_carry_i_6_n_0,Lxy0__1_carry_i_7_n_0}));
CARRY4 Lxy0__1_carry__0
(.CI(Lxy0__1_carry_n_0),
.CO({Lxy0__1_carry__0_n_0,Lxy0__1_carry__0_n_1,Lxy0__1_carry__0_n_2,Lxy0__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lxy0__1_carry__0_i_1_n_0,Lxy0__1_carry__0_i_2_n_0,Lxy0__1_carry__0_i_3_n_0,Lxy0__1_carry__0_i_4_n_0}),
.O({Lxy0__1_carry__0_n_4,Lxy0__1_carry__0_n_5,Lxy0__1_carry__0_n_6,Lxy0__1_carry__0_n_7}),
.S({Lxy0__1_carry__0_i_5_n_0,Lxy0__1_carry__0_i_6_n_0,Lxy0__1_carry__0_i_7_n_0,Lxy0__1_carry__0_i_8_n_0}));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__0_i_1
(.I0(\Lxy_0_reg_n_0_[6] ),
.I1(Lxy0__1_carry__0_i_9_n_0),
.I2(Lxy_3[5]),
.I3(Lxy_2[5]),
.I4(\Lxy_1_reg_n_0_[5] ),
.O(Lxy0__1_carry__0_i_1_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__0_i_10
(.I0(Lxy_3[5]),
.I1(\Lxy_1_reg_n_0_[5] ),
.I2(Lxy_2[5]),
.O(Lxy0__1_carry__0_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__0_i_11
(.I0(Lxy_3[4]),
.I1(\Lxy_1_reg_n_0_[4] ),
.I2(Lxy_2[4]),
.O(Lxy0__1_carry__0_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__0_i_12
(.I0(Lxy_3[7]),
.I1(\Lxy_1_reg_n_0_[7] ),
.I2(Lxy_2[7]),
.O(Lxy0__1_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__0_i_2
(.I0(\Lxy_0_reg_n_0_[5] ),
.I1(Lxy0__1_carry__0_i_10_n_0),
.I2(Lxy_3[4]),
.I3(Lxy_2[4]),
.I4(\Lxy_1_reg_n_0_[4] ),
.O(Lxy0__1_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__0_i_3
(.I0(\Lxy_0_reg_n_0_[4] ),
.I1(Lxy0__1_carry__0_i_11_n_0),
.I2(Lxy_3[3]),
.I3(Lxy_2[3]),
.I4(\Lxy_1_reg_n_0_[3] ),
.O(Lxy0__1_carry__0_i_3_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__0_i_4
(.I0(\Lxy_0_reg_n_0_[3] ),
.I1(Lxy0__1_carry_i_8_n_0),
.I2(Lxy_3[2]),
.I3(Lxy_2[2]),
.I4(\Lxy_1_reg_n_0_[2] ),
.O(Lxy0__1_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__0_i_5
(.I0(Lxy0__1_carry__0_i_1_n_0),
.I1(Lxy0__1_carry__0_i_12_n_0),
.I2(\Lxy_0_reg_n_0_[7] ),
.I3(\Lxy_1_reg_n_0_[6] ),
.I4(Lxy_2[6]),
.I5(Lxy_3[6]),
.O(Lxy0__1_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__0_i_6
(.I0(Lxy0__1_carry__0_i_2_n_0),
.I1(Lxy0__1_carry__0_i_9_n_0),
.I2(\Lxy_0_reg_n_0_[6] ),
.I3(\Lxy_1_reg_n_0_[5] ),
.I4(Lxy_2[5]),
.I5(Lxy_3[5]),
.O(Lxy0__1_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__0_i_7
(.I0(Lxy0__1_carry__0_i_3_n_0),
.I1(Lxy0__1_carry__0_i_10_n_0),
.I2(\Lxy_0_reg_n_0_[5] ),
.I3(\Lxy_1_reg_n_0_[4] ),
.I4(Lxy_2[4]),
.I5(Lxy_3[4]),
.O(Lxy0__1_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__0_i_8
(.I0(Lxy0__1_carry__0_i_4_n_0),
.I1(Lxy0__1_carry__0_i_11_n_0),
.I2(\Lxy_0_reg_n_0_[4] ),
.I3(\Lxy_1_reg_n_0_[3] ),
.I4(Lxy_2[3]),
.I5(Lxy_3[3]),
.O(Lxy0__1_carry__0_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__0_i_9
(.I0(Lxy_3[6]),
.I1(\Lxy_1_reg_n_0_[6] ),
.I2(Lxy_2[6]),
.O(Lxy0__1_carry__0_i_9_n_0));
CARRY4 Lxy0__1_carry__1
(.CI(Lxy0__1_carry__0_n_0),
.CO({Lxy0__1_carry__1_n_0,Lxy0__1_carry__1_n_1,Lxy0__1_carry__1_n_2,Lxy0__1_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lxy0__1_carry__1_i_1_n_0,Lxy0__1_carry__1_i_2_n_0,Lxy0__1_carry__1_i_3_n_0,Lxy0__1_carry__1_i_4_n_0}),
.O({Lxy0__1_carry__1_n_4,Lxy0__1_carry__1_n_5,Lxy0__1_carry__1_n_6,Lxy0__1_carry__1_n_7}),
.S({Lxy0__1_carry__1_i_5_n_0,Lxy0__1_carry__1_i_6_n_0,Lxy0__1_carry__1_i_7_n_0,Lxy0__1_carry__1_i_8_n_0}));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__1_i_1
(.I0(\Lxy_0_reg_n_0_[10] ),
.I1(Lxy0__1_carry__1_i_9_n_0),
.I2(Lxy_3[9]),
.I3(Lxy_2[9]),
.I4(\Lxy_1_reg_n_0_[9] ),
.O(Lxy0__1_carry__1_i_1_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__1_i_10
(.I0(Lxy_3[9]),
.I1(\Lxy_1_reg_n_0_[9] ),
.I2(Lxy_2[9]),
.O(Lxy0__1_carry__1_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__1_i_11
(.I0(Lxy_3[8]),
.I1(\Lxy_1_reg_n_0_[8] ),
.I2(Lxy_2[8]),
.O(Lxy0__1_carry__1_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__1_i_12
(.I0(Lxy_3[11]),
.I1(\Lxy_1_reg_n_0_[11] ),
.I2(Lxy_2[11]),
.O(Lxy0__1_carry__1_i_12_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__1_i_2
(.I0(\Lxy_0_reg_n_0_[9] ),
.I1(Lxy0__1_carry__1_i_10_n_0),
.I2(Lxy_3[8]),
.I3(Lxy_2[8]),
.I4(\Lxy_1_reg_n_0_[8] ),
.O(Lxy0__1_carry__1_i_2_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__1_i_3
(.I0(\Lxy_0_reg_n_0_[8] ),
.I1(Lxy0__1_carry__1_i_11_n_0),
.I2(Lxy_3[7]),
.I3(Lxy_2[7]),
.I4(\Lxy_1_reg_n_0_[7] ),
.O(Lxy0__1_carry__1_i_3_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__1_i_4
(.I0(\Lxy_0_reg_n_0_[7] ),
.I1(Lxy0__1_carry__0_i_12_n_0),
.I2(Lxy_3[6]),
.I3(Lxy_2[6]),
.I4(\Lxy_1_reg_n_0_[6] ),
.O(Lxy0__1_carry__1_i_4_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__1_i_5
(.I0(Lxy0__1_carry__1_i_1_n_0),
.I1(Lxy0__1_carry__1_i_12_n_0),
.I2(\Lxy_0_reg_n_0_[11] ),
.I3(\Lxy_1_reg_n_0_[10] ),
.I4(Lxy_2[10]),
.I5(Lxy_3[10]),
.O(Lxy0__1_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__1_i_6
(.I0(Lxy0__1_carry__1_i_2_n_0),
.I1(Lxy0__1_carry__1_i_9_n_0),
.I2(\Lxy_0_reg_n_0_[10] ),
.I3(\Lxy_1_reg_n_0_[9] ),
.I4(Lxy_2[9]),
.I5(Lxy_3[9]),
.O(Lxy0__1_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__1_i_7
(.I0(Lxy0__1_carry__1_i_3_n_0),
.I1(Lxy0__1_carry__1_i_10_n_0),
.I2(\Lxy_0_reg_n_0_[9] ),
.I3(\Lxy_1_reg_n_0_[8] ),
.I4(Lxy_2[8]),
.I5(Lxy_3[8]),
.O(Lxy0__1_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__1_i_8
(.I0(Lxy0__1_carry__1_i_4_n_0),
.I1(Lxy0__1_carry__1_i_11_n_0),
.I2(\Lxy_0_reg_n_0_[8] ),
.I3(\Lxy_1_reg_n_0_[7] ),
.I4(Lxy_2[7]),
.I5(Lxy_3[7]),
.O(Lxy0__1_carry__1_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__1_i_9
(.I0(Lxy_3[10]),
.I1(\Lxy_1_reg_n_0_[10] ),
.I2(Lxy_2[10]),
.O(Lxy0__1_carry__1_i_9_n_0));
CARRY4 Lxy0__1_carry__2
(.CI(Lxy0__1_carry__1_n_0),
.CO({NLW_Lxy0__1_carry__2_CO_UNCONNECTED[3],Lxy0__1_carry__2_n_1,Lxy0__1_carry__2_n_2,Lxy0__1_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lxy0__1_carry__2_i_1_n_0,Lxy0__1_carry__2_i_2_n_0,Lxy0__1_carry__2_i_3_n_0}),
.O({Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_5,Lxy0__1_carry__2_n_6,Lxy0__1_carry__2_n_7}),
.S({Lxy0__1_carry__2_i_4_n_0,Lxy0__1_carry__2_i_5_n_0,Lxy0__1_carry__2_i_6_n_0,Lxy0__1_carry__2_i_7_n_0}));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__2_i_1
(.I0(\Lxy_0_reg_n_0_[13] ),
.I1(Lxy0__1_carry__2_i_8_n_0),
.I2(Lxy_3[12]),
.I3(Lxy_2[12]),
.I4(\Lxy_1_reg_n_0_[12] ),
.O(Lxy0__1_carry__2_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h4D))
Lxy0__1_carry__2_i_10
(.I0(\Lxy_1_reg_n_0_[13] ),
.I1(Lxy_2[13]),
.I2(Lxy_3[13]),
.O(Lxy0__1_carry__2_i_10_n_0));
LUT4 #(
.INIT(16'h6996))
Lxy0__1_carry__2_i_11
(.I0(Lxy_2[15]),
.I1(\Lxy_1_reg_n_0_[15] ),
.I2(Lxy_3[15]),
.I3(\Lxy_0_reg_n_0_[15] ),
.O(Lxy0__1_carry__2_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__2_i_12
(.I0(Lxy_3[14]),
.I1(\Lxy_1_reg_n_0_[14] ),
.I2(Lxy_2[14]),
.O(Lxy0__1_carry__2_i_12_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__2_i_2
(.I0(\Lxy_0_reg_n_0_[12] ),
.I1(Lxy0__1_carry__2_i_9_n_0),
.I2(Lxy_3[11]),
.I3(Lxy_2[11]),
.I4(\Lxy_1_reg_n_0_[11] ),
.O(Lxy0__1_carry__2_i_2_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__2_i_3
(.I0(\Lxy_0_reg_n_0_[11] ),
.I1(Lxy0__1_carry__1_i_12_n_0),
.I2(Lxy_3[10]),
.I3(Lxy_2[10]),
.I4(\Lxy_1_reg_n_0_[10] ),
.O(Lxy0__1_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h1E87781E87E11E87))
Lxy0__1_carry__2_i_4
(.I0(Lxy0__1_carry__2_i_10_n_0),
.I1(\Lxy_0_reg_n_0_[14] ),
.I2(Lxy0__1_carry__2_i_11_n_0),
.I3(\Lxy_1_reg_n_0_[14] ),
.I4(Lxy_2[14]),
.I5(Lxy_3[14]),
.O(Lxy0__1_carry__2_i_4_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__2_i_5
(.I0(Lxy0__1_carry__2_i_1_n_0),
.I1(Lxy0__1_carry__2_i_12_n_0),
.I2(\Lxy_0_reg_n_0_[14] ),
.I3(\Lxy_1_reg_n_0_[13] ),
.I4(Lxy_2[13]),
.I5(Lxy_3[13]),
.O(Lxy0__1_carry__2_i_5_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__2_i_6
(.I0(Lxy0__1_carry__2_i_2_n_0),
.I1(Lxy0__1_carry__2_i_8_n_0),
.I2(\Lxy_0_reg_n_0_[13] ),
.I3(\Lxy_1_reg_n_0_[12] ),
.I4(Lxy_2[12]),
.I5(Lxy_3[12]),
.O(Lxy0__1_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__2_i_7
(.I0(Lxy0__1_carry__2_i_3_n_0),
.I1(Lxy0__1_carry__2_i_9_n_0),
.I2(\Lxy_0_reg_n_0_[12] ),
.I3(\Lxy_1_reg_n_0_[11] ),
.I4(Lxy_2[11]),
.I5(Lxy_3[11]),
.O(Lxy0__1_carry__2_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__2_i_8
(.I0(Lxy_3[13]),
.I1(\Lxy_1_reg_n_0_[13] ),
.I2(Lxy_2[13]),
.O(Lxy0__1_carry__2_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__2_i_9
(.I0(Lxy_3[12]),
.I1(\Lxy_1_reg_n_0_[12] ),
.I2(Lxy_2[12]),
.O(Lxy0__1_carry__2_i_9_n_0));
LUT6 #(
.INIT(64'hEBBEEBBE8228EBBE))
Lxy0__1_carry_i_1
(.I0(\Lxy_0_reg_n_0_[2] ),
.I1(Lxy_2[2]),
.I2(\Lxy_1_reg_n_0_[2] ),
.I3(Lxy_3[2]),
.I4(\Lxy_1_reg_n_0_[1] ),
.I5(Lxy_2[1]),
.O(Lxy0__1_carry_i_1_n_0));
LUT2 #(
.INIT(4'h9))
Lxy0__1_carry_i_10
(.I0(Lxy_2[1]),
.I1(\Lxy_1_reg_n_0_[1] ),
.O(Lxy0__1_carry_i_10_n_0));
LUT4 #(
.INIT(16'h4DD4))
Lxy0__1_carry_i_2
(.I0(Lxy_3[1]),
.I1(\Lxy_0_reg_n_0_[1] ),
.I2(\Lxy_1_reg_n_0_[1] ),
.I3(Lxy_2[1]),
.O(Lxy0__1_carry_i_2_n_0));
LUT4 #(
.INIT(16'h9669))
Lxy0__1_carry_i_3
(.I0(\Lxy_1_reg_n_0_[1] ),
.I1(Lxy_2[1]),
.I2(Lxy_3[1]),
.I3(\Lxy_0_reg_n_0_[1] ),
.O(Lxy0__1_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry_i_4
(.I0(Lxy0__1_carry_i_1_n_0),
.I1(Lxy0__1_carry_i_8_n_0),
.I2(\Lxy_0_reg_n_0_[3] ),
.I3(\Lxy_1_reg_n_0_[2] ),
.I4(Lxy_2[2]),
.I5(Lxy_3[2]),
.O(Lxy0__1_carry_i_4_n_0));
LUT5 #(
.INIT(32'h69966969))
Lxy0__1_carry_i_5
(.I0(Lxy0__1_carry_i_2_n_0),
.I1(Lxy0__1_carry_i_9_n_0),
.I2(\Lxy_0_reg_n_0_[2] ),
.I3(Lxy_2[1]),
.I4(\Lxy_1_reg_n_0_[1] ),
.O(Lxy0__1_carry_i_5_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry_i_6
(.I0(\Lxy_0_reg_n_0_[1] ),
.I1(Lxy_3[1]),
.I2(Lxy0__1_carry_i_10_n_0),
.I3(Lxy_3[0]),
.I4(Lxy_2[0]),
.I5(\Lxy_1_reg_n_0_[0] ),
.O(Lxy0__1_carry_i_6_n_0));
LUT4 #(
.INIT(16'h6996))
Lxy0__1_carry_i_7
(.I0(Lxy_2[0]),
.I1(\Lxy_1_reg_n_0_[0] ),
.I2(Lxy_3[0]),
.I3(\Lxy_0_reg_n_0_[0] ),
.O(Lxy0__1_carry_i_7_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry_i_8
(.I0(Lxy_3[3]),
.I1(\Lxy_1_reg_n_0_[3] ),
.I2(Lxy_2[3]),
.O(Lxy0__1_carry_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry_i_9
(.I0(Lxy_3[2]),
.I1(\Lxy_1_reg_n_0_[2] ),
.I2(Lxy_2[2]),
.O(Lxy0__1_carry_i_9_n_0));
LUT6 #(
.INIT(64'h0000000000004000))
\Lxy_0[15]_i_1
(.I0(\cycle_reg[0]_rep_n_0 ),
.I1(cycle[3]),
.I2(active),
.I3(rst),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(cycle[2]),
.O(\Lxy_0[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[0]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[0]),
.Q(\Lxy_0_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[10]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[10]),
.Q(\Lxy_0_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[11]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[11]),
.Q(\Lxy_0_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[12]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[12]),
.Q(\Lxy_0_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[13]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[13]),
.Q(\Lxy_0_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[14]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[14]),
.Q(\Lxy_0_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[15]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[15]),
.Q(\Lxy_0_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[1]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[1]),
.Q(\Lxy_0_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[2]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[2]),
.Q(\Lxy_0_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[3]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[3]),
.Q(\Lxy_0_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[4]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[4]),
.Q(\Lxy_0_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[5]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[5]),
.Q(\Lxy_0_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[6]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[6]),
.Q(\Lxy_0_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[7]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[7]),
.Q(\Lxy_0_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[8]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[8]),
.Q(\Lxy_0_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[9]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[9]),
.Q(\Lxy_0_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'h0000400000000000))
\Lxy_1[15]_i_1
(.I0(\cycle_reg[0]_rep_n_0 ),
.I1(cycle[3]),
.I2(active),
.I3(rst),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(Lxy_1));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[0]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[0]),
.Q(\Lxy_1_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[10]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[10]),
.Q(\Lxy_1_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[11]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[11]),
.Q(\Lxy_1_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[12]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[12]),
.Q(\Lxy_1_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[13]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[13]),
.Q(\Lxy_1_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[14]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[14]),
.Q(\Lxy_1_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[15]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[15]),
.Q(\Lxy_1_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[1]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[1]),
.Q(\Lxy_1_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[2]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[2]),
.Q(\Lxy_1_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[3]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[3]),
.Q(\Lxy_1_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[4]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[4]),
.Q(\Lxy_1_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[5]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[5]),
.Q(\Lxy_1_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[6]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[6]),
.Q(\Lxy_1_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[7]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[7]),
.Q(\Lxy_1_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[8]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[8]),
.Q(\Lxy_1_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[9]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[9]),
.Q(\Lxy_1_reg_n_0_[9] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[0]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[0]),
.Q(Lxy_2[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[10]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[10]),
.Q(Lxy_2[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[11]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[11]),
.Q(Lxy_2[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[12]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[12]),
.Q(Lxy_2[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[13]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[13]),
.Q(Lxy_2[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[14]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[14]),
.Q(Lxy_2[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[15]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[15]),
.Q(Lxy_2[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[1]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[1]),
.Q(Lxy_2[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[2]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[2]),
.Q(Lxy_2[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[3]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[3]),
.Q(Lxy_2[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[4]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[4]),
.Q(Lxy_2[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[5]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[5]),
.Q(Lxy_2[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[6]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[6]),
.Q(Lxy_2[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[7]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[7]),
.Q(Lxy_2[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[8]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[8]),
.Q(Lxy_2[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[9]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[9]),
.Q(Lxy_2[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h4000000000000000))
\Lxy_3[15]_i_1
(.I0(cycle[0]),
.I1(active),
.I2(rst),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(cycle[3]),
.O(y6));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[0]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[0]),
.Q(Lxy_3[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[10]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[10]),
.Q(Lxy_3[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[11]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[11]),
.Q(Lxy_3[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[12]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[12]),
.Q(Lxy_3[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[13]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[13]),
.Q(Lxy_3[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[14]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[14]),
.Q(Lxy_3[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[15]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[15]),
.Q(Lxy_3[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[1]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[1]),
.Q(Lxy_3[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[2]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[2]),
.Q(Lxy_3[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[3]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[3]),
.Q(Lxy_3[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[4]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[4]),
.Q(Lxy_3[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[5]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[5]),
.Q(Lxy_3[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[6]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[6]),
.Q(Lxy_3[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[7]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[7]),
.Q(Lxy_3[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[8]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[8]),
.Q(Lxy_3[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[9]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[9]),
.Q(Lxy_3[9]),
.R(1'b0));
CARRY4 Lyy0_carry
(.CI(1'b0),
.CO({Lyy0_carry_n_0,Lyy0_carry_n_1,Lyy0_carry_n_2,Lyy0_carry_n_3}),
.CYINIT(1'b0),
.DI({Lyy0_carry_i_1_n_0,Lyy0_carry_i_2_n_0,1'b1,\Lyy_2_reg_n_0_[0] }),
.O(B[3:0]),
.S({Lyy0_carry_i_3_n_0,Lyy0_carry_i_4_n_0,Lyy0_carry_i_5_n_0,Lyy0_carry_i_6_n_0}));
CARRY4 Lyy0_carry__0
(.CI(Lyy0_carry_n_0),
.CO({Lyy0_carry__0_n_0,Lyy0_carry__0_n_1,Lyy0_carry__0_n_2,Lyy0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lyy0_carry__0_i_1_n_0,Lyy0_carry__0_i_2_n_0,Lyy0_carry__0_i_3_n_0,Lyy0_carry__0_i_4_n_0}),
.O(B[7:4]),
.S({Lyy0_carry__0_i_5_n_0,Lyy0_carry__0_i_6_n_0,Lyy0_carry__0_i_7_n_0,Lyy0_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair16" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__0_i_1
(.I0(Lyy_1[6]),
.I1(\Lyy_2_reg_n_0_[6] ),
.I2(\Lyy_0_reg_n_0_[6] ),
.O(Lyy0_carry__0_i_1_n_0));
(* HLUTNM = "lutpair15" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__0_i_2
(.I0(Lyy_1[5]),
.I1(\Lyy_2_reg_n_0_[5] ),
.I2(\Lyy_0_reg_n_0_[5] ),
.O(Lyy0_carry__0_i_2_n_0));
(* HLUTNM = "lutpair14" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__0_i_3
(.I0(Lyy_1[4]),
.I1(\Lyy_2_reg_n_0_[4] ),
.I2(\Lyy_0_reg_n_0_[4] ),
.O(Lyy0_carry__0_i_3_n_0));
(* HLUTNM = "lutpair13" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__0_i_4
(.I0(Lyy_1[3]),
.I1(\Lyy_2_reg_n_0_[3] ),
.I2(\Lyy_0_reg_n_0_[3] ),
.O(Lyy0_carry__0_i_4_n_0));
(* HLUTNM = "lutpair17" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__0_i_5
(.I0(Lyy_1[7]),
.I1(\Lyy_2_reg_n_0_[7] ),
.I2(\Lyy_0_reg_n_0_[7] ),
.I3(Lyy0_carry__0_i_1_n_0),
.O(Lyy0_carry__0_i_5_n_0));
(* HLUTNM = "lutpair16" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__0_i_6
(.I0(Lyy_1[6]),
.I1(\Lyy_2_reg_n_0_[6] ),
.I2(\Lyy_0_reg_n_0_[6] ),
.I3(Lyy0_carry__0_i_2_n_0),
.O(Lyy0_carry__0_i_6_n_0));
(* HLUTNM = "lutpair15" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__0_i_7
(.I0(Lyy_1[5]),
.I1(\Lyy_2_reg_n_0_[5] ),
.I2(\Lyy_0_reg_n_0_[5] ),
.I3(Lyy0_carry__0_i_3_n_0),
.O(Lyy0_carry__0_i_7_n_0));
(* HLUTNM = "lutpair14" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__0_i_8
(.I0(Lyy_1[4]),
.I1(\Lyy_2_reg_n_0_[4] ),
.I2(\Lyy_0_reg_n_0_[4] ),
.I3(Lyy0_carry__0_i_4_n_0),
.O(Lyy0_carry__0_i_8_n_0));
CARRY4 Lyy0_carry__1
(.CI(Lyy0_carry__0_n_0),
.CO({Lyy0_carry__1_n_0,Lyy0_carry__1_n_1,Lyy0_carry__1_n_2,Lyy0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lyy0_carry__1_i_1_n_0,Lyy0_carry__1_i_2_n_0,Lyy0_carry__1_i_3_n_0,Lyy0_carry__1_i_4_n_0}),
.O(B[11:8]),
.S({Lyy0_carry__1_i_5_n_0,Lyy0_carry__1_i_6_n_0,Lyy0_carry__1_i_7_n_0,Lyy0_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair20" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__1_i_1
(.I0(Lyy_1[10]),
.I1(\Lyy_2_reg_n_0_[10] ),
.I2(\Lyy_0_reg_n_0_[10] ),
.O(Lyy0_carry__1_i_1_n_0));
(* HLUTNM = "lutpair19" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__1_i_2
(.I0(Lyy_1[9]),
.I1(\Lyy_2_reg_n_0_[9] ),
.I2(\Lyy_0_reg_n_0_[9] ),
.O(Lyy0_carry__1_i_2_n_0));
(* HLUTNM = "lutpair18" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__1_i_3
(.I0(Lyy_1[8]),
.I1(\Lyy_2_reg_n_0_[8] ),
.I2(\Lyy_0_reg_n_0_[8] ),
.O(Lyy0_carry__1_i_3_n_0));
(* HLUTNM = "lutpair17" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__1_i_4
(.I0(Lyy_1[7]),
.I1(\Lyy_2_reg_n_0_[7] ),
.I2(\Lyy_0_reg_n_0_[7] ),
.O(Lyy0_carry__1_i_4_n_0));
(* HLUTNM = "lutpair21" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__1_i_5
(.I0(Lyy_1[11]),
.I1(\Lyy_2_reg_n_0_[11] ),
.I2(\Lyy_0_reg_n_0_[11] ),
.I3(Lyy0_carry__1_i_1_n_0),
.O(Lyy0_carry__1_i_5_n_0));
(* HLUTNM = "lutpair20" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__1_i_6
(.I0(Lyy_1[10]),
.I1(\Lyy_2_reg_n_0_[10] ),
.I2(\Lyy_0_reg_n_0_[10] ),
.I3(Lyy0_carry__1_i_2_n_0),
.O(Lyy0_carry__1_i_6_n_0));
(* HLUTNM = "lutpair19" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__1_i_7
(.I0(Lyy_1[9]),
.I1(\Lyy_2_reg_n_0_[9] ),
.I2(\Lyy_0_reg_n_0_[9] ),
.I3(Lyy0_carry__1_i_3_n_0),
.O(Lyy0_carry__1_i_7_n_0));
(* HLUTNM = "lutpair18" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__1_i_8
(.I0(Lyy_1[8]),
.I1(\Lyy_2_reg_n_0_[8] ),
.I2(\Lyy_0_reg_n_0_[8] ),
.I3(Lyy0_carry__1_i_4_n_0),
.O(Lyy0_carry__1_i_8_n_0));
CARRY4 Lyy0_carry__2
(.CI(Lyy0_carry__1_n_0),
.CO({NLW_Lyy0_carry__2_CO_UNCONNECTED[3],Lyy0_carry__2_n_1,Lyy0_carry__2_n_2,Lyy0_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lyy0_carry__2_i_1_n_0,Lyy0_carry__2_i_2_n_0,Lyy0_carry__2_i_3_n_0}),
.O(B[15:12]),
.S({Lyy0_carry__2_i_4_n_0,Lyy0_carry__2_i_5_n_0,Lyy0_carry__2_i_6_n_0,Lyy0_carry__2_i_7_n_0}));
(* HLUTNM = "lutpair23" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__2_i_1
(.I0(Lyy_1[13]),
.I1(\Lyy_2_reg_n_0_[13] ),
.I2(\Lyy_0_reg_n_0_[13] ),
.O(Lyy0_carry__2_i_1_n_0));
(* HLUTNM = "lutpair22" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__2_i_2
(.I0(Lyy_1[12]),
.I1(\Lyy_2_reg_n_0_[12] ),
.I2(\Lyy_0_reg_n_0_[12] ),
.O(Lyy0_carry__2_i_2_n_0));
(* HLUTNM = "lutpair21" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__2_i_3
(.I0(Lyy_1[11]),
.I1(\Lyy_2_reg_n_0_[11] ),
.I2(\Lyy_0_reg_n_0_[11] ),
.O(Lyy0_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h8E71718E718E8E71))
Lyy0_carry__2_i_4
(.I0(\Lyy_0_reg_n_0_[14] ),
.I1(\Lyy_2_reg_n_0_[14] ),
.I2(Lyy_1[14]),
.I3(\Lyy_2_reg_n_0_[15] ),
.I4(Lyy_1[15]),
.I5(\Lyy_0_reg_n_0_[15] ),
.O(Lyy0_carry__2_i_4_n_0));
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__2_i_5
(.I0(Lyy0_carry__2_i_1_n_0),
.I1(\Lyy_2_reg_n_0_[14] ),
.I2(Lyy_1[14]),
.I3(\Lyy_0_reg_n_0_[14] ),
.O(Lyy0_carry__2_i_5_n_0));
(* HLUTNM = "lutpair23" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__2_i_6
(.I0(Lyy_1[13]),
.I1(\Lyy_2_reg_n_0_[13] ),
.I2(\Lyy_0_reg_n_0_[13] ),
.I3(Lyy0_carry__2_i_2_n_0),
.O(Lyy0_carry__2_i_6_n_0));
(* HLUTNM = "lutpair22" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__2_i_7
(.I0(Lyy_1[12]),
.I1(\Lyy_2_reg_n_0_[12] ),
.I2(\Lyy_0_reg_n_0_[12] ),
.I3(Lyy0_carry__2_i_3_n_0),
.O(Lyy0_carry__2_i_7_n_0));
(* HLUTNM = "lutpair12" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry_i_1
(.I0(Lyy_1[2]),
.I1(\Lyy_2_reg_n_0_[2] ),
.I2(\Lyy_0_reg_n_0_[2] ),
.O(Lyy0_carry_i_1_n_0));
(* HLUTNM = "lutpair25" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry_i_2
(.I0(Lyy_1[1]),
.I1(\Lyy_2_reg_n_0_[1] ),
.I2(\Lyy_0_reg_n_0_[1] ),
.O(Lyy0_carry_i_2_n_0));
(* HLUTNM = "lutpair13" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry_i_3
(.I0(Lyy_1[3]),
.I1(\Lyy_2_reg_n_0_[3] ),
.I2(\Lyy_0_reg_n_0_[3] ),
.I3(Lyy0_carry_i_1_n_0),
.O(Lyy0_carry_i_3_n_0));
(* HLUTNM = "lutpair12" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry_i_4
(.I0(Lyy_1[2]),
.I1(\Lyy_2_reg_n_0_[2] ),
.I2(\Lyy_0_reg_n_0_[2] ),
.I3(Lyy0_carry_i_2_n_0),
.O(Lyy0_carry_i_4_n_0));
(* HLUTNM = "lutpair25" *)
LUT3 #(
.INIT(8'h96))
Lyy0_carry_i_5
(.I0(Lyy_1[1]),
.I1(\Lyy_2_reg_n_0_[1] ),
.I2(\Lyy_0_reg_n_0_[1] ),
.O(Lyy0_carry_i_5_n_0));
LUT2 #(
.INIT(4'h6))
Lyy0_carry_i_6
(.I0(\Lyy_2_reg_n_0_[0] ),
.I1(\Lyy_0_reg_n_0_[0] ),
.O(Lyy0_carry_i_6_n_0));
LUT6 #(
.INIT(64'h0000000000000080))
\Lyy_0[15]_i_1
(.I0(rst),
.I1(active),
.I2(cycle[2]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[3]),
.I5(\cycle_reg[0]_rep_n_0 ),
.O(Lyy_0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[0]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[0]),
.Q(\Lyy_0_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[10]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[10]),
.Q(\Lyy_0_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[11]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[11]),
.Q(\Lyy_0_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[12]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[12]),
.Q(\Lyy_0_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[13]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[13]),
.Q(\Lyy_0_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[14]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[14]),
.Q(\Lyy_0_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[15]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[15]),
.Q(\Lyy_0_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[1]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[1]),
.Q(\Lyy_0_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[2]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[2]),
.Q(\Lyy_0_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[3]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[3]),
.Q(\Lyy_0_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[4]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[4]),
.Q(\Lyy_0_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[5]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[5]),
.Q(\Lyy_0_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[6]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[6]),
.Q(\Lyy_0_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[7]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[7]),
.Q(\Lyy_0_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[8]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[8]),
.Q(\Lyy_0_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[9]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[9]),
.Q(\Lyy_0_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000040000000))
\Lyy_1[15]_i_1
(.I0(cycle[3]),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(rst),
.I3(active),
.I4(cycle[0]),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(y1));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[10]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[9]),
.Q(Lyy_1[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[11]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[10]),
.Q(Lyy_1[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[12]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[11]),
.Q(Lyy_1[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[13]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[12]),
.Q(Lyy_1[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[14]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[13]),
.Q(Lyy_1[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[15]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[14]),
.Q(Lyy_1[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[1]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[0]),
.Q(Lyy_1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[2]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[1]),
.Q(Lyy_1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[3]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[2]),
.Q(Lyy_1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[4]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[3]),
.Q(Lyy_1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[5]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[4]),
.Q(Lyy_1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[6]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[5]),
.Q(Lyy_1[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[7]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[6]),
.Q(Lyy_1[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[8]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[7]),
.Q(Lyy_1[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[9]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[8]),
.Q(Lyy_1[9]),
.R(1'b0));
CARRY4 Lyy_20__1_carry
(.CI(1'b0),
.CO({Lyy_20__1_carry_n_0,Lyy_20__1_carry_n_1,Lyy_20__1_carry_n_2,Lyy_20__1_carry_n_3}),
.CYINIT(1'b0),
.DI({Lyy_20__1_carry_i_1_n_0,Lyy_20__1_carry_i_2_n_0,Lyy_20__1_carry_i_3_n_0,Lyy_2_bottom_right[0]}),
.O(Lyy_20[3:0]),
.S({Lyy_20__1_carry_i_4_n_0,Lyy_20__1_carry_i_5_n_0,Lyy_20__1_carry_i_6_n_0,Lyy_20__1_carry_i_7_n_0}));
CARRY4 Lyy_20__1_carry__0
(.CI(Lyy_20__1_carry_n_0),
.CO({Lyy_20__1_carry__0_n_0,Lyy_20__1_carry__0_n_1,Lyy_20__1_carry__0_n_2,Lyy_20__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lyy_20__1_carry__0_i_1_n_0,Lyy_20__1_carry__0_i_2_n_0,Lyy_20__1_carry__0_i_3_n_0,Lyy_20__1_carry__0_i_4_n_0}),
.O(Lyy_20[7:4]),
.S({Lyy_20__1_carry__0_i_5_n_0,Lyy_20__1_carry__0_i_6_n_0,Lyy_20__1_carry__0_i_7_n_0,Lyy_20__1_carry__0_i_8_n_0}));
LUT5 #(
.INIT(32'hFF969600))
Lyy_20__1_carry__0_i_1
(.I0(Lyy_2_top_left[6]),
.I1(Lyy_2_bottom_left[6]),
.I2(Lyy_2_top_right[6]),
.I3(Lyy_20__1_carry__0_i_9_n_0),
.I4(Lyy_2_bottom_right[6]),
.O(Lyy_20__1_carry__0_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry__0_i_10
(.I0(Lyy_2_top_left[5]),
.I1(Lyy_2_bottom_left[5]),
.I2(Lyy_2_top_right[5]),
.O(Lyy_20__1_carry__0_i_10_n_0));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'h4D))
Lyy_20__1_carry__0_i_11
(.I0(Lyy_2_top_right[3]),
.I1(Lyy_2_top_left[3]),
.I2(Lyy_2_bottom_left[3]),
.O(Lyy_20__1_carry__0_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry__0_i_12
(.I0(Lyy_2_top_left[7]),
.I1(Lyy_2_bottom_left[7]),
.I2(Lyy_2_top_right[7]),
.O(Lyy_20__1_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__0_i_2
(.I0(Lyy_2_bottom_right[5]),
.I1(Lyy_2_bottom_left[4]),
.I2(Lyy_2_top_left[4]),
.I3(Lyy_2_top_right[4]),
.I4(Lyy_20__1_carry__0_i_10_n_0),
.O(Lyy_20__1_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'hFF969600))
Lyy_20__1_carry__0_i_3
(.I0(Lyy_2_top_left[4]),
.I1(Lyy_2_bottom_left[4]),
.I2(Lyy_2_top_right[4]),
.I3(Lyy_20__1_carry__0_i_11_n_0),
.I4(Lyy_2_bottom_right[4]),
.O(Lyy_20__1_carry__0_i_3_n_0));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__0_i_4
(.I0(Lyy_2_bottom_right[3]),
.I1(Lyy_2_bottom_left[2]),
.I2(Lyy_2_top_left[2]),
.I3(Lyy_2_top_right[2]),
.I4(Lyy_20__1_carry_i_8_n_0),
.O(Lyy_20__1_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry__0_i_5
(.I0(Lyy_20__1_carry__0_i_1_n_0),
.I1(Lyy_20__1_carry__0_i_12_n_0),
.I2(Lyy_2_bottom_right[7]),
.I3(Lyy_2_top_right[6]),
.I4(Lyy_2_top_left[6]),
.I5(Lyy_2_bottom_left[6]),
.O(Lyy_20__1_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
Lyy_20__1_carry__0_i_6
(.I0(Lyy_20__1_carry__0_i_2_n_0),
.I1(Lyy_2_top_right[6]),
.I2(Lyy_2_bottom_left[6]),
.I3(Lyy_2_top_left[6]),
.I4(Lyy_2_bottom_right[6]),
.I5(Lyy_20__1_carry__0_i_9_n_0),
.O(Lyy_20__1_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry__0_i_7
(.I0(Lyy_20__1_carry__0_i_3_n_0),
.I1(Lyy_20__1_carry__0_i_10_n_0),
.I2(Lyy_2_bottom_right[5]),
.I3(Lyy_2_top_right[4]),
.I4(Lyy_2_top_left[4]),
.I5(Lyy_2_bottom_left[4]),
.O(Lyy_20__1_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
Lyy_20__1_carry__0_i_8
(.I0(Lyy_20__1_carry__0_i_4_n_0),
.I1(Lyy_2_top_right[4]),
.I2(Lyy_2_bottom_left[4]),
.I3(Lyy_2_top_left[4]),
.I4(Lyy_2_bottom_right[4]),
.I5(Lyy_20__1_carry__0_i_11_n_0),
.O(Lyy_20__1_carry__0_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'h4D))
Lyy_20__1_carry__0_i_9
(.I0(Lyy_2_top_right[5]),
.I1(Lyy_2_top_left[5]),
.I2(Lyy_2_bottom_left[5]),
.O(Lyy_20__1_carry__0_i_9_n_0));
CARRY4 Lyy_20__1_carry__1
(.CI(Lyy_20__1_carry__0_n_0),
.CO({Lyy_20__1_carry__1_n_0,Lyy_20__1_carry__1_n_1,Lyy_20__1_carry__1_n_2,Lyy_20__1_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lyy_20__1_carry__1_i_1_n_0,Lyy_20__1_carry__1_i_2_n_0,Lyy_20__1_carry__1_i_3_n_0,Lyy_20__1_carry__1_i_4_n_0}),
.O(Lyy_20[11:8]),
.S({Lyy_20__1_carry__1_i_5_n_0,Lyy_20__1_carry__1_i_6_n_0,Lyy_20__1_carry__1_i_7_n_0,Lyy_20__1_carry__1_i_8_n_0}));
LUT5 #(
.INIT(32'hFF969600))
Lyy_20__1_carry__1_i_1
(.I0(Lyy_2_top_left[10]),
.I1(Lyy_2_bottom_left[10]),
.I2(Lyy_2_top_right[10]),
.I3(Lyy_20__1_carry__1_i_9_n_0),
.I4(Lyy_2_bottom_right[10]),
.O(Lyy_20__1_carry__1_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry__1_i_10
(.I0(Lyy_2_top_left[9]),
.I1(Lyy_2_bottom_left[9]),
.I2(Lyy_2_top_right[9]),
.O(Lyy_20__1_carry__1_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry__1_i_11
(.I0(Lyy_2_top_left[8]),
.I1(Lyy_2_bottom_left[8]),
.I2(Lyy_2_top_right[8]),
.O(Lyy_20__1_carry__1_i_11_n_0));
LUT3 #(
.INIT(8'h4D))
Lyy_20__1_carry__1_i_12
(.I0(Lyy_2_top_right[10]),
.I1(Lyy_2_top_left[10]),
.I2(Lyy_2_bottom_left[10]),
.O(Lyy_20__1_carry__1_i_12_n_0));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__1_i_2
(.I0(Lyy_2_bottom_right[9]),
.I1(Lyy_2_bottom_left[8]),
.I2(Lyy_2_top_left[8]),
.I3(Lyy_2_top_right[8]),
.I4(Lyy_20__1_carry__1_i_10_n_0),
.O(Lyy_20__1_carry__1_i_2_n_0));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__1_i_3
(.I0(Lyy_2_bottom_right[8]),
.I1(Lyy_2_bottom_left[7]),
.I2(Lyy_2_top_left[7]),
.I3(Lyy_2_top_right[7]),
.I4(Lyy_20__1_carry__1_i_11_n_0),
.O(Lyy_20__1_carry__1_i_3_n_0));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__1_i_4
(.I0(Lyy_2_bottom_right[7]),
.I1(Lyy_2_bottom_left[6]),
.I2(Lyy_2_top_left[6]),
.I3(Lyy_2_top_right[6]),
.I4(Lyy_20__1_carry__0_i_12_n_0),
.O(Lyy_20__1_carry__1_i_4_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
Lyy_20__1_carry__1_i_5
(.I0(Lyy_20__1_carry__1_i_1_n_0),
.I1(Lyy_2_top_right[11]),
.I2(Lyy_2_bottom_left[11]),
.I3(Lyy_2_top_left[11]),
.I4(Lyy_2_bottom_right[11]),
.I5(Lyy_20__1_carry__1_i_12_n_0),
.O(Lyy_20__1_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
Lyy_20__1_carry__1_i_6
(.I0(Lyy_20__1_carry__1_i_2_n_0),
.I1(Lyy_2_top_right[10]),
.I2(Lyy_2_bottom_left[10]),
.I3(Lyy_2_top_left[10]),
.I4(Lyy_2_bottom_right[10]),
.I5(Lyy_20__1_carry__1_i_9_n_0),
.O(Lyy_20__1_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry__1_i_7
(.I0(Lyy_20__1_carry__1_i_3_n_0),
.I1(Lyy_20__1_carry__1_i_10_n_0),
.I2(Lyy_2_bottom_right[9]),
.I3(Lyy_2_top_right[8]),
.I4(Lyy_2_top_left[8]),
.I5(Lyy_2_bottom_left[8]),
.O(Lyy_20__1_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry__1_i_8
(.I0(Lyy_20__1_carry__1_i_4_n_0),
.I1(Lyy_20__1_carry__1_i_11_n_0),
.I2(Lyy_2_bottom_right[8]),
.I3(Lyy_2_top_right[7]),
.I4(Lyy_2_top_left[7]),
.I5(Lyy_2_bottom_left[7]),
.O(Lyy_20__1_carry__1_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'h4D))
Lyy_20__1_carry__1_i_9
(.I0(Lyy_2_top_right[9]),
.I1(Lyy_2_top_left[9]),
.I2(Lyy_2_bottom_left[9]),
.O(Lyy_20__1_carry__1_i_9_n_0));
CARRY4 Lyy_20__1_carry__2
(.CI(Lyy_20__1_carry__1_n_0),
.CO({NLW_Lyy_20__1_carry__2_CO_UNCONNECTED[3],Lyy_20__1_carry__2_n_1,Lyy_20__1_carry__2_n_2,Lyy_20__1_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lyy_20__1_carry__2_i_1_n_0,Lyy_20__1_carry__2_i_2_n_0,Lyy_20__1_carry__2_i_3_n_0}),
.O(Lyy_20[15:12]),
.S({Lyy_20__1_carry__2_i_4_n_0,Lyy_20__1_carry__2_i_5_n_0,Lyy_20__1_carry__2_i_6_n_0,Lyy_20__1_carry__2_i_7_n_0}));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__2_i_1
(.I0(Lyy_2_bottom_right[13]),
.I1(Lyy_2_top_right[12]),
.I2(Lyy_2_top_left[12]),
.I3(Lyy_2_bottom_left[12]),
.I4(Lyy_20__1_carry__2_i_8_n_0),
.O(Lyy_20__1_carry__2_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'h2B))
Lyy_20__1_carry__2_i_10
(.I0(Lyy_2_top_left[13]),
.I1(Lyy_2_bottom_left[13]),
.I2(Lyy_2_top_right[13]),
.O(Lyy_20__1_carry__2_i_10_n_0));
LUT4 #(
.INIT(16'h6996))
Lyy_20__1_carry__2_i_11
(.I0(Lyy_2_top_right[15]),
.I1(Lyy_2_bottom_left[15]),
.I2(Lyy_2_top_left[15]),
.I3(Lyy_2_bottom_right[15]),
.O(Lyy_20__1_carry__2_i_11_n_0));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__2_i_2
(.I0(Lyy_2_bottom_right[12]),
.I1(Lyy_2_bottom_left[11]),
.I2(Lyy_2_top_left[11]),
.I3(Lyy_2_top_right[11]),
.I4(Lyy_20__1_carry__2_i_9_n_0),
.O(Lyy_20__1_carry__2_i_2_n_0));
LUT5 #(
.INIT(32'hFF969600))
Lyy_20__1_carry__2_i_3
(.I0(Lyy_2_top_left[11]),
.I1(Lyy_2_bottom_left[11]),
.I2(Lyy_2_top_right[11]),
.I3(Lyy_20__1_carry__1_i_12_n_0),
.I4(Lyy_2_bottom_right[11]),
.O(Lyy_20__1_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h1E78871E871EE187))
Lyy_20__1_carry__2_i_4
(.I0(Lyy_2_bottom_right[14]),
.I1(Lyy_20__1_carry__2_i_10_n_0),
.I2(Lyy_20__1_carry__2_i_11_n_0),
.I3(Lyy_2_top_left[14]),
.I4(Lyy_2_bottom_left[14]),
.I5(Lyy_2_top_right[14]),
.O(Lyy_20__1_carry__2_i_4_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
Lyy_20__1_carry__2_i_5
(.I0(Lyy_20__1_carry__2_i_1_n_0),
.I1(Lyy_2_top_right[14]),
.I2(Lyy_2_bottom_left[14]),
.I3(Lyy_2_top_left[14]),
.I4(Lyy_2_bottom_right[14]),
.I5(Lyy_20__1_carry__2_i_10_n_0),
.O(Lyy_20__1_carry__2_i_5_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry__2_i_6
(.I0(Lyy_20__1_carry__2_i_2_n_0),
.I1(Lyy_20__1_carry__2_i_8_n_0),
.I2(Lyy_2_bottom_right[13]),
.I3(Lyy_2_bottom_left[12]),
.I4(Lyy_2_top_left[12]),
.I5(Lyy_2_top_right[12]),
.O(Lyy_20__1_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry__2_i_7
(.I0(Lyy_20__1_carry__2_i_3_n_0),
.I1(Lyy_20__1_carry__2_i_9_n_0),
.I2(Lyy_2_bottom_right[12]),
.I3(Lyy_2_top_right[11]),
.I4(Lyy_2_top_left[11]),
.I5(Lyy_2_bottom_left[11]),
.O(Lyy_20__1_carry__2_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry__2_i_8
(.I0(Lyy_2_top_left[13]),
.I1(Lyy_2_bottom_left[13]),
.I2(Lyy_2_top_right[13]),
.O(Lyy_20__1_carry__2_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry__2_i_9
(.I0(Lyy_2_top_left[12]),
.I1(Lyy_2_bottom_left[12]),
.I2(Lyy_2_top_right[12]),
.O(Lyy_20__1_carry__2_i_9_n_0));
LUT6 #(
.INIT(64'h96FFFFFF00969696))
Lyy_20__1_carry_i_1
(.I0(Lyy_2_top_left[2]),
.I1(Lyy_2_bottom_left[2]),
.I2(Lyy_2_top_right[2]),
.I3(Lyy_2_top_right[1]),
.I4(Lyy_2_bottom_left[1]),
.I5(Lyy_2_bottom_right[2]),
.O(Lyy_20__1_carry_i_1_n_0));
LUT4 #(
.INIT(16'hF990))
Lyy_20__1_carry_i_2
(.I0(Lyy_2_top_right[1]),
.I1(Lyy_2_bottom_left[1]),
.I2(Lyy_2_top_left[1]),
.I3(Lyy_2_bottom_right[1]),
.O(Lyy_20__1_carry_i_2_n_0));
LUT4 #(
.INIT(16'h9669))
Lyy_20__1_carry_i_3
(.I0(Lyy_2_bottom_left[1]),
.I1(Lyy_2_top_right[1]),
.I2(Lyy_2_top_left[1]),
.I3(Lyy_2_bottom_right[1]),
.O(Lyy_20__1_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry_i_4
(.I0(Lyy_20__1_carry_i_1_n_0),
.I1(Lyy_20__1_carry_i_8_n_0),
.I2(Lyy_2_bottom_right[3]),
.I3(Lyy_2_top_right[2]),
.I4(Lyy_2_top_left[2]),
.I5(Lyy_2_bottom_left[2]),
.O(Lyy_20__1_carry_i_4_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
Lyy_20__1_carry_i_5
(.I0(Lyy_20__1_carry_i_2_n_0),
.I1(Lyy_2_top_right[2]),
.I2(Lyy_2_bottom_left[2]),
.I3(Lyy_2_top_left[2]),
.I4(Lyy_2_bottom_right[2]),
.I5(Lyy_20__1_carry_i_9_n_0),
.O(Lyy_20__1_carry_i_5_n_0));
LUT4 #(
.INIT(16'h9A59))
Lyy_20__1_carry_i_6
(.I0(Lyy_20__1_carry_i_3_n_0),
.I1(Lyy_2_bottom_left[0]),
.I2(Lyy_2_top_left[0]),
.I3(Lyy_2_top_right[0]),
.O(Lyy_20__1_carry_i_6_n_0));
LUT4 #(
.INIT(16'h6996))
Lyy_20__1_carry_i_7
(.I0(Lyy_2_top_right[0]),
.I1(Lyy_2_bottom_left[0]),
.I2(Lyy_2_top_left[0]),
.I3(Lyy_2_bottom_right[0]),
.O(Lyy_20__1_carry_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry_i_8
(.I0(Lyy_2_top_left[3]),
.I1(Lyy_2_bottom_left[3]),
.I2(Lyy_2_top_right[3]),
.O(Lyy_20__1_carry_i_8_n_0));
LUT2 #(
.INIT(4'h7))
Lyy_20__1_carry_i_9
(.I0(Lyy_2_bottom_left[1]),
.I1(Lyy_2_top_right[1]),
.O(Lyy_20__1_carry_i_9_n_0));
LUT6 #(
.INIT(64'h0020000000000000))
\Lyy_2[15]_i_1
(.I0(\cycle_reg[1]_rep_n_0 ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(rst),
.I5(active),
.O(\Lyy_2[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[0]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [0]),
.Q(Lyy_2_bottom_left[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[10]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [10]),
.Q(Lyy_2_bottom_left[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[11]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [11]),
.Q(Lyy_2_bottom_left[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[12]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [12]),
.Q(Lyy_2_bottom_left[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[13]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [13]),
.Q(Lyy_2_bottom_left[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[14]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [14]),
.Q(Lyy_2_bottom_left[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[15]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [15]),
.Q(Lyy_2_bottom_left[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[1]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [1]),
.Q(Lyy_2_bottom_left[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[2]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [2]),
.Q(Lyy_2_bottom_left[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[3]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [3]),
.Q(Lyy_2_bottom_left[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[4]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [4]),
.Q(Lyy_2_bottom_left[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[5]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [5]),
.Q(Lyy_2_bottom_left[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[6]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [6]),
.Q(Lyy_2_bottom_left[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[7]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [7]),
.Q(Lyy_2_bottom_left[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[8]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [8]),
.Q(Lyy_2_bottom_left[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[9]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [9]),
.Q(Lyy_2_bottom_left[9]),
.R(1'b0));
CARRY4 Lyy_2_bottom_right0__0_carry
(.CI(1'b0),
.CO({Lyy_2_bottom_right0__0_carry_n_0,Lyy_2_bottom_right0__0_carry_n_1,Lyy_2_bottom_right0__0_carry_n_2,Lyy_2_bottom_right0__0_carry_n_3}),
.CYINIT(1'b0),
.DI({Lyy_2_bottom_right0__0_carry_i_1_n_0,Lyy_2_bottom_right0__0_carry_i_2_n_0,Lyy_2_bottom_right0__0_carry_i_3_n_0,Lyy_2_bottom_right0__0_carry_i_4_n_0}),
.O(Lyy_2_bottom_right01_out[3:0]),
.S({Lyy_2_bottom_right0__0_carry_i_5_n_0,Lyy_2_bottom_right0__0_carry_i_6_n_0,Lyy_2_bottom_right0__0_carry_i_7_n_0,Lyy_2_bottom_right0__0_carry_i_8_n_0}));
CARRY4 Lyy_2_bottom_right0__0_carry__0
(.CI(Lyy_2_bottom_right0__0_carry_n_0),
.CO({Lyy_2_bottom_right0__0_carry__0_n_0,Lyy_2_bottom_right0__0_carry__0_n_1,Lyy_2_bottom_right0__0_carry__0_n_2,Lyy_2_bottom_right0__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lyy_2_bottom_right0__0_carry__0_i_1_n_0,Lyy_2_bottom_right0__0_carry__0_i_2_n_0,Lyy_2_bottom_right0__0_carry__0_i_3_n_0,Lyy_2_bottom_right0__0_carry__0_i_4_n_0}),
.O(Lyy_2_bottom_right01_out[7:4]),
.S({Lyy_2_bottom_right0__0_carry__0_i_5_n_0,Lyy_2_bottom_right0__0_carry__0_i_6_n_0,Lyy_2_bottom_right0__0_carry__0_i_7_n_0,Lyy_2_bottom_right0__0_carry__0_i_8_n_0}));
LUT5 #(
.INIT(32'hEE8E8E88))
Lyy_2_bottom_right0__0_carry__0_i_1
(.I0(last_value[6]),
.I1(Lyy_2_bottom_right0__0_carry__0_i_9_n_0),
.I2(\corner_reg_n_0_[5] ),
.I3(\top_reg_n_0_[5] ),
.I4(\left_reg_n_0_[5] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_1_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__0_i_10
(.I0(\corner_reg_n_0_[5] ),
.I1(\left_reg_n_0_[5] ),
.I2(\top_reg_n_0_[5] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_10_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__0_i_11
(.I0(\corner_reg_n_0_[4] ),
.I1(\left_reg_n_0_[4] ),
.I2(\top_reg_n_0_[4] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_11_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__0_i_12
(.I0(\corner_reg_n_0_[7] ),
.I1(\left_reg_n_0_[7] ),
.I2(\top_reg_n_0_[7] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'hEE8E8E88))
Lyy_2_bottom_right0__0_carry__0_i_2
(.I0(last_value[5]),
.I1(Lyy_2_bottom_right0__0_carry__0_i_10_n_0),
.I2(\corner_reg_n_0_[4] ),
.I3(\top_reg_n_0_[4] ),
.I4(\left_reg_n_0_[4] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'hEE8E8E88))
Lyy_2_bottom_right0__0_carry__0_i_3
(.I0(last_value[4]),
.I1(Lyy_2_bottom_right0__0_carry__0_i_11_n_0),
.I2(\corner_reg_n_0_[3] ),
.I3(\top_reg_n_0_[3] ),
.I4(\left_reg_n_0_[3] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_3_n_0));
LUT5 #(
.INIT(32'hEE8E8E88))
Lyy_2_bottom_right0__0_carry__0_i_4
(.I0(last_value[3]),
.I1(Lyy_2_bottom_right0__0_carry_i_10_n_0),
.I2(\corner_reg_n_0_[2] ),
.I3(\top_reg_n_0_[2] ),
.I4(\left_reg_n_0_[2] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'h6996969669696996))
Lyy_2_bottom_right0__0_carry__0_i_5
(.I0(Lyy_2_bottom_right0__0_carry__0_i_1_n_0),
.I1(Lyy_2_bottom_right0__0_carry__0_i_12_n_0),
.I2(last_value[7]),
.I3(\left_reg_n_0_[6] ),
.I4(\top_reg_n_0_[6] ),
.I5(\corner_reg_n_0_[6] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'h6996969669696996))
Lyy_2_bottom_right0__0_carry__0_i_6
(.I0(Lyy_2_bottom_right0__0_carry__0_i_2_n_0),
.I1(Lyy_2_bottom_right0__0_carry__0_i_9_n_0),
.I2(last_value[6]),
.I3(\left_reg_n_0_[5] ),
.I4(\top_reg_n_0_[5] ),
.I5(\corner_reg_n_0_[5] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'h6996969669696996))
Lyy_2_bottom_right0__0_carry__0_i_7
(.I0(Lyy_2_bottom_right0__0_carry__0_i_3_n_0),
.I1(Lyy_2_bottom_right0__0_carry__0_i_10_n_0),
.I2(last_value[5]),
.I3(\left_reg_n_0_[4] ),
.I4(\top_reg_n_0_[4] ),
.I5(\corner_reg_n_0_[4] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'h6996969669696996))
Lyy_2_bottom_right0__0_carry__0_i_8
(.I0(Lyy_2_bottom_right0__0_carry__0_i_4_n_0),
.I1(Lyy_2_bottom_right0__0_carry__0_i_11_n_0),
.I2(last_value[4]),
.I3(\left_reg_n_0_[3] ),
.I4(\top_reg_n_0_[3] ),
.I5(\corner_reg_n_0_[3] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_8_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__0_i_9
(.I0(\corner_reg_n_0_[6] ),
.I1(\left_reg_n_0_[6] ),
.I2(\top_reg_n_0_[6] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_9_n_0));
CARRY4 Lyy_2_bottom_right0__0_carry__1
(.CI(Lyy_2_bottom_right0__0_carry__0_n_0),
.CO({Lyy_2_bottom_right0__0_carry__1_n_0,Lyy_2_bottom_right0__0_carry__1_n_1,Lyy_2_bottom_right0__0_carry__1_n_2,Lyy_2_bottom_right0__0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lyy_2_bottom_right0__0_carry__1_i_1_n_0,Lyy_2_bottom_right0__0_carry__1_i_2_n_0,Lyy_2_bottom_right0__0_carry__1_i_3_n_0,Lyy_2_bottom_right0__0_carry__1_i_4_n_0}),
.O(Lyy_2_bottom_right01_out[11:8]),
.S({Lyy_2_bottom_right0__0_carry__1_i_5_n_0,Lyy_2_bottom_right0__0_carry__1_i_6_n_0,Lyy_2_bottom_right0__0_carry__1_i_7_n_0,Lyy_2_bottom_right0__0_carry__1_i_8_n_0}));
LUT6 #(
.INIT(64'h6969006900690000))
Lyy_2_bottom_right0__0_carry__1_i_1
(.I0(\top_reg_n_0_[10] ),
.I1(\left_reg_n_0_[10] ),
.I2(\corner_reg_n_0_[10] ),
.I3(\corner_reg_n_0_[9] ),
.I4(\top_reg_n_0_[9] ),
.I5(\left_reg_n_0_[9] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_1_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__1_i_10
(.I0(\corner_reg_n_0_[10] ),
.I1(\left_reg_n_0_[10] ),
.I2(\top_reg_n_0_[10] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_10_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__1_i_11
(.I0(\corner_reg_n_0_[9] ),
.I1(\left_reg_n_0_[9] ),
.I2(\top_reg_n_0_[9] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_11_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__1_i_12
(.I0(\corner_reg_n_0_[8] ),
.I1(\left_reg_n_0_[8] ),
.I2(\top_reg_n_0_[8] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_12_n_0));
LUT6 #(
.INIT(64'h6969006900690000))
Lyy_2_bottom_right0__0_carry__1_i_2
(.I0(\top_reg_n_0_[9] ),
.I1(\left_reg_n_0_[9] ),
.I2(\corner_reg_n_0_[9] ),
.I3(\corner_reg_n_0_[8] ),
.I4(\top_reg_n_0_[8] ),
.I5(\left_reg_n_0_[8] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_2_n_0));
LUT6 #(
.INIT(64'h6969006900690000))
Lyy_2_bottom_right0__0_carry__1_i_3
(.I0(\top_reg_n_0_[8] ),
.I1(\left_reg_n_0_[8] ),
.I2(\corner_reg_n_0_[8] ),
.I3(\corner_reg_n_0_[7] ),
.I4(\top_reg_n_0_[7] ),
.I5(\left_reg_n_0_[7] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_3_n_0));
LUT5 #(
.INIT(32'hEE8E8E88))
Lyy_2_bottom_right0__0_carry__1_i_4
(.I0(last_value[7]),
.I1(Lyy_2_bottom_right0__0_carry__0_i_12_n_0),
.I2(\corner_reg_n_0_[6] ),
.I3(\top_reg_n_0_[6] ),
.I4(\left_reg_n_0_[6] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_4_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__1_i_5
(.I0(Lyy_2_bottom_right0__0_carry__1_i_1_n_0),
.I1(Lyy_2_bottom_right0__0_carry__1_i_9_n_0),
.I2(\left_reg_n_0_[10] ),
.I3(\top_reg_n_0_[10] ),
.I4(\corner_reg_n_0_[10] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_5_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__1_i_6
(.I0(Lyy_2_bottom_right0__0_carry__1_i_2_n_0),
.I1(Lyy_2_bottom_right0__0_carry__1_i_10_n_0),
.I2(\left_reg_n_0_[9] ),
.I3(\top_reg_n_0_[9] ),
.I4(\corner_reg_n_0_[9] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_6_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__1_i_7
(.I0(Lyy_2_bottom_right0__0_carry__1_i_3_n_0),
.I1(Lyy_2_bottom_right0__0_carry__1_i_11_n_0),
.I2(\left_reg_n_0_[8] ),
.I3(\top_reg_n_0_[8] ),
.I4(\corner_reg_n_0_[8] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_7_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__1_i_8
(.I0(Lyy_2_bottom_right0__0_carry__1_i_4_n_0),
.I1(Lyy_2_bottom_right0__0_carry__1_i_12_n_0),
.I2(\left_reg_n_0_[7] ),
.I3(\top_reg_n_0_[7] ),
.I4(\corner_reg_n_0_[7] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_8_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__1_i_9
(.I0(\corner_reg_n_0_[11] ),
.I1(\left_reg_n_0_[11] ),
.I2(\top_reg_n_0_[11] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_9_n_0));
CARRY4 Lyy_2_bottom_right0__0_carry__2
(.CI(Lyy_2_bottom_right0__0_carry__1_n_0),
.CO({NLW_Lyy_2_bottom_right0__0_carry__2_CO_UNCONNECTED[3],Lyy_2_bottom_right0__0_carry__2_n_1,Lyy_2_bottom_right0__0_carry__2_n_2,Lyy_2_bottom_right0__0_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lyy_2_bottom_right0__0_carry__2_i_1_n_0,Lyy_2_bottom_right0__0_carry__2_i_2_n_0,Lyy_2_bottom_right0__0_carry__2_i_3_n_0}),
.O(Lyy_2_bottom_right01_out[15:12]),
.S({Lyy_2_bottom_right0__0_carry__2_i_4_n_0,Lyy_2_bottom_right0__0_carry__2_i_5_n_0,Lyy_2_bottom_right0__0_carry__2_i_6_n_0,Lyy_2_bottom_right0__0_carry__2_i_7_n_0}));
LUT6 #(
.INIT(64'h6969006900690000))
Lyy_2_bottom_right0__0_carry__2_i_1
(.I0(\top_reg_n_0_[13] ),
.I1(\left_reg_n_0_[13] ),
.I2(\corner_reg_n_0_[13] ),
.I3(\corner_reg_n_0_[12] ),
.I4(\top_reg_n_0_[12] ),
.I5(\left_reg_n_0_[12] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_1_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__2_i_10
(.I0(\corner_reg_n_0_[14] ),
.I1(\left_reg_n_0_[14] ),
.I2(\top_reg_n_0_[14] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_10_n_0));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__2_i_11
(.I0(\corner_reg_n_0_[13] ),
.I1(\left_reg_n_0_[13] ),
.I2(\top_reg_n_0_[13] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_11_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__2_i_12
(.I0(\corner_reg_n_0_[12] ),
.I1(\left_reg_n_0_[12] ),
.I2(\top_reg_n_0_[12] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_12_n_0));
LUT6 #(
.INIT(64'h6969006900690000))
Lyy_2_bottom_right0__0_carry__2_i_2
(.I0(\top_reg_n_0_[12] ),
.I1(\left_reg_n_0_[12] ),
.I2(\corner_reg_n_0_[12] ),
.I3(\corner_reg_n_0_[11] ),
.I4(\top_reg_n_0_[11] ),
.I5(\left_reg_n_0_[11] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_2_n_0));
LUT6 #(
.INIT(64'h6969006900690000))
Lyy_2_bottom_right0__0_carry__2_i_3
(.I0(\top_reg_n_0_[11] ),
.I1(\left_reg_n_0_[11] ),
.I2(\corner_reg_n_0_[11] ),
.I3(\corner_reg_n_0_[10] ),
.I4(\top_reg_n_0_[10] ),
.I5(\left_reg_n_0_[10] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_3_n_0));
LUT5 #(
.INIT(32'hD77D2882))
Lyy_2_bottom_right0__0_carry__2_i_4
(.I0(Lyy_2_bottom_right0__0_carry__2_i_8_n_0),
.I1(\corner_reg_n_0_[14] ),
.I2(\left_reg_n_0_[14] ),
.I3(\top_reg_n_0_[14] ),
.I4(Lyy_2_bottom_right0__0_carry__2_i_9_n_0),
.O(Lyy_2_bottom_right0__0_carry__2_i_4_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__2_i_5
(.I0(Lyy_2_bottom_right0__0_carry__2_i_1_n_0),
.I1(Lyy_2_bottom_right0__0_carry__2_i_10_n_0),
.I2(\left_reg_n_0_[13] ),
.I3(\top_reg_n_0_[13] ),
.I4(\corner_reg_n_0_[13] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_5_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__2_i_6
(.I0(Lyy_2_bottom_right0__0_carry__2_i_2_n_0),
.I1(Lyy_2_bottom_right0__0_carry__2_i_11_n_0),
.I2(\left_reg_n_0_[12] ),
.I3(\top_reg_n_0_[12] ),
.I4(\corner_reg_n_0_[12] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_6_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__2_i_7
(.I0(Lyy_2_bottom_right0__0_carry__2_i_3_n_0),
.I1(Lyy_2_bottom_right0__0_carry__2_i_12_n_0),
.I2(\left_reg_n_0_[11] ),
.I3(\top_reg_n_0_[11] ),
.I4(\corner_reg_n_0_[11] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'h8E))
Lyy_2_bottom_right0__0_carry__2_i_8
(.I0(\left_reg_n_0_[13] ),
.I1(\top_reg_n_0_[13] ),
.I2(\corner_reg_n_0_[13] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_8_n_0));
LUT6 #(
.INIT(64'hD42B2BD42BD4D42B))
Lyy_2_bottom_right0__0_carry__2_i_9
(.I0(\corner_reg_n_0_[14] ),
.I1(\top_reg_n_0_[14] ),
.I2(\left_reg_n_0_[14] ),
.I3(\top_reg_n_0_[15] ),
.I4(\left_reg_n_0_[15] ),
.I5(\corner_reg_n_0_[15] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_9_n_0));
LUT5 #(
.INIT(32'hEE8E8E88))
Lyy_2_bottom_right0__0_carry_i_1
(.I0(last_value[2]),
.I1(Lyy_2_bottom_right0__0_carry_i_9_n_0),
.I2(\corner_reg_n_0_[1] ),
.I3(\top_reg_n_0_[1] ),
.I4(\left_reg_n_0_[1] ),
.O(Lyy_2_bottom_right0__0_carry_i_1_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry_i_10
(.I0(\corner_reg_n_0_[3] ),
.I1(\left_reg_n_0_[3] ),
.I2(\top_reg_n_0_[3] ),
.O(Lyy_2_bottom_right0__0_carry_i_10_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry_i_11
(.I0(\corner_reg_n_0_[1] ),
.I1(\left_reg_n_0_[1] ),
.I2(\top_reg_n_0_[1] ),
.O(Lyy_2_bottom_right0__0_carry_i_11_n_0));
LUT6 #(
.INIT(64'h20BABA20BA2020BA))
Lyy_2_bottom_right0__0_carry_i_2
(.I0(last_value[1]),
.I1(\corner_reg_n_0_[0] ),
.I2(last_value[0]),
.I3(\top_reg_n_0_[1] ),
.I4(\left_reg_n_0_[1] ),
.I5(\corner_reg_n_0_[1] ),
.O(Lyy_2_bottom_right0__0_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9669966969969669))
Lyy_2_bottom_right0__0_carry_i_3
(.I0(\top_reg_n_0_[1] ),
.I1(\left_reg_n_0_[1] ),
.I2(\corner_reg_n_0_[1] ),
.I3(last_value[1]),
.I4(last_value[0]),
.I5(\corner_reg_n_0_[0] ),
.O(Lyy_2_bottom_right0__0_carry_i_3_n_0));
LUT2 #(
.INIT(4'h9))
Lyy_2_bottom_right0__0_carry_i_4
(.I0(\left_reg_n_0_[0] ),
.I1(\top_reg_n_0_[0] ),
.O(Lyy_2_bottom_right0__0_carry_i_4_n_0));
LUT6 #(
.INIT(64'h6996969669696996))
Lyy_2_bottom_right0__0_carry_i_5
(.I0(Lyy_2_bottom_right0__0_carry_i_1_n_0),
.I1(Lyy_2_bottom_right0__0_carry_i_10_n_0),
.I2(last_value[3]),
.I3(\left_reg_n_0_[2] ),
.I4(\top_reg_n_0_[2] ),
.I5(\corner_reg_n_0_[2] ),
.O(Lyy_2_bottom_right0__0_carry_i_5_n_0));
LUT6 #(
.INIT(64'h6996969669696996))
Lyy_2_bottom_right0__0_carry_i_6
(.I0(Lyy_2_bottom_right0__0_carry_i_2_n_0),
.I1(Lyy_2_bottom_right0__0_carry_i_9_n_0),
.I2(last_value[2]),
.I3(\left_reg_n_0_[1] ),
.I4(\top_reg_n_0_[1] ),
.I5(\corner_reg_n_0_[1] ),
.O(Lyy_2_bottom_right0__0_carry_i_6_n_0));
LUT6 #(
.INIT(64'hB44BB44BB44B4BB4))
Lyy_2_bottom_right0__0_carry_i_7
(.I0(\corner_reg_n_0_[0] ),
.I1(last_value[0]),
.I2(last_value[1]),
.I3(Lyy_2_bottom_right0__0_carry_i_11_n_0),
.I4(\left_reg_n_0_[0] ),
.I5(\top_reg_n_0_[0] ),
.O(Lyy_2_bottom_right0__0_carry_i_7_n_0));
LUT4 #(
.INIT(16'h6996))
Lyy_2_bottom_right0__0_carry_i_8
(.I0(\left_reg_n_0_[0] ),
.I1(\top_reg_n_0_[0] ),
.I2(\corner_reg_n_0_[0] ),
.I3(last_value[0]),
.O(Lyy_2_bottom_right0__0_carry_i_8_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry_i_9
(.I0(\corner_reg_n_0_[2] ),
.I1(\left_reg_n_0_[2] ),
.I2(\top_reg_n_0_[2] ),
.O(Lyy_2_bottom_right0__0_carry_i_9_n_0));
LUT6 #(
.INIT(64'h0000000000000080))
\Lyy_2_bottom_right[15]_i_1
(.I0(cycle[0]),
.I1(active),
.I2(rst),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[3]),
.I5(cycle[2]),
.O(y5));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[0]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[0]),
.Q(Lyy_2_bottom_right[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[10]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[10]),
.Q(Lyy_2_bottom_right[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[11]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[11]),
.Q(Lyy_2_bottom_right[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[12]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[12]),
.Q(Lyy_2_bottom_right[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[13]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[13]),
.Q(Lyy_2_bottom_right[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[14]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[14]),
.Q(Lyy_2_bottom_right[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[15]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[15]),
.Q(Lyy_2_bottom_right[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[1]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[1]),
.Q(Lyy_2_bottom_right[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[2]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[2]),
.Q(Lyy_2_bottom_right[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[3]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[3]),
.Q(Lyy_2_bottom_right[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[4]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[4]),
.Q(Lyy_2_bottom_right[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[5]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[5]),
.Q(Lyy_2_bottom_right[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[6]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[6]),
.Q(Lyy_2_bottom_right[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[7]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[7]),
.Q(Lyy_2_bottom_right[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[8]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[8]),
.Q(Lyy_2_bottom_right[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[9]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[9]),
.Q(Lyy_2_bottom_right[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[0]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[0]),
.Q(\Lyy_2_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[10]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[10]),
.Q(\Lyy_2_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[11]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[11]),
.Q(\Lyy_2_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[12]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[12]),
.Q(\Lyy_2_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[13]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[13]),
.Q(\Lyy_2_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[14]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[14]),
.Q(\Lyy_2_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[15]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[15]),
.Q(\Lyy_2_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[1]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[1]),
.Q(\Lyy_2_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[2]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[2]),
.Q(\Lyy_2_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[3]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[3]),
.Q(\Lyy_2_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[4]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[4]),
.Q(\Lyy_2_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[5]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[5]),
.Q(\Lyy_2_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[6]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[6]),
.Q(\Lyy_2_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[7]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[7]),
.Q(\Lyy_2_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[8]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[8]),
.Q(\Lyy_2_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[9]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[9]),
.Q(\Lyy_2_reg_n_0_[9] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[0]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[0]),
.Q(Lyy_2_top_left[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[10]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[10]),
.Q(Lyy_2_top_left[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[11]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[11]),
.Q(Lyy_2_top_left[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[12]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[12]),
.Q(Lyy_2_top_left[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[13]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[13]),
.Q(Lyy_2_top_left[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[14]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[14]),
.Q(Lyy_2_top_left[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[15]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[15]),
.Q(Lyy_2_top_left[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[1]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[1]),
.Q(Lyy_2_top_left[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[2]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[2]),
.Q(Lyy_2_top_left[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[3]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[3]),
.Q(Lyy_2_top_left[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[4]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[4]),
.Q(Lyy_2_top_left[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[5]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[5]),
.Q(Lyy_2_top_left[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[6]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[6]),
.Q(Lyy_2_top_left[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[7]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[7]),
.Q(Lyy_2_top_left[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[8]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[8]),
.Q(Lyy_2_top_left[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[9]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[9]),
.Q(Lyy_2_top_left[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[0]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[0] ),
.Q(Lyy_2_top_right[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[10]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[10] ),
.Q(Lyy_2_top_right[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[11]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[11] ),
.Q(Lyy_2_top_right[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[12]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[12] ),
.Q(Lyy_2_top_right[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[13]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[13] ),
.Q(Lyy_2_top_right[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[14]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[14] ),
.Q(Lyy_2_top_right[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[15]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[15] ),
.Q(Lyy_2_top_right[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[1]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[1] ),
.Q(Lyy_2_top_right[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[2]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[2] ),
.Q(Lyy_2_top_right[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[3]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[3] ),
.Q(Lyy_2_top_right[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[4]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[4] ),
.Q(Lyy_2_top_right[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[5]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[5] ),
.Q(Lyy_2_top_right[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[6]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[6] ),
.Q(Lyy_2_top_right[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[7]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[7] ),
.Q(Lyy_2_top_right[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[8]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[8] ),
.Q(Lyy_2_top_right[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[9]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[9] ),
.Q(Lyy_2_top_right[9]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[0]_i_1
(.I0(\compute_addr_0_reg_n_0_[0] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[0] ),
.O(\addr_0[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[10]_i_1
(.I0(\compute_addr_0_reg_n_0_[10] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[10] ),
.O(\addr_0[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[11]_i_1
(.I0(\compute_addr_0_reg_n_0_[11] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[11] ),
.O(\addr_0[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[12]_i_1
(.I0(\compute_addr_0_reg_n_0_[12] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[12] ),
.O(\addr_0[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8888888888808888))
\addr_0[13]_i_1
(.I0(rst),
.I1(active),
.I2(cycle[3]),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(cycle[2]),
.O(addr_0));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[13]_i_2
(.I0(\compute_addr_0_reg_n_0_[13] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[13] ),
.O(\addr_0[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[1]_i_1
(.I0(\compute_addr_0_reg_n_0_[1] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[1] ),
.O(\addr_0[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[2]_i_1
(.I0(\compute_addr_0_reg_n_0_[2] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[2] ),
.O(\addr_0[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[3]_i_1
(.I0(\compute_addr_0_reg_n_0_[3] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[3] ),
.O(\addr_0[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[4]_i_1
(.I0(\compute_addr_0_reg_n_0_[4] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[4] ),
.O(\addr_0[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[5]_i_1
(.I0(\compute_addr_0_reg_n_0_[5] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[5] ),
.O(\addr_0[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[6]_i_1
(.I0(\compute_addr_0_reg_n_0_[6] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[6] ),
.O(\addr_0[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[7]_i_1
(.I0(\compute_addr_0_reg_n_0_[7] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[7] ),
.O(\addr_0[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[8]_i_1
(.I0(\compute_addr_0_reg_n_0_[8] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[8] ),
.O(\addr_0[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[9]_i_1
(.I0(\compute_addr_0_reg_n_0_[9] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[9] ),
.O(\addr_0[9]_i_1_n_0 ));
FDRE \addr_0_reg[0]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[0]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[0] ),
.R(1'b0));
FDRE \addr_0_reg[10]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[10]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[10] ),
.R(1'b0));
FDRE \addr_0_reg[11]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[11]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[11] ),
.R(1'b0));
FDRE \addr_0_reg[12]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[12]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[12] ),
.R(1'b0));
FDRE \addr_0_reg[13]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[13]_i_2_n_0 ),
.Q(\addr_0_reg_n_0_[13] ),
.R(1'b0));
FDRE \addr_0_reg[1]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[1]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[1] ),
.R(1'b0));
FDRE \addr_0_reg[2]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[2]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[2] ),
.R(1'b0));
FDRE \addr_0_reg[3]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[3]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[3] ),
.R(1'b0));
FDRE \addr_0_reg[4]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[4]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[4] ),
.R(1'b0));
FDRE \addr_0_reg[5]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[5]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[5] ),
.R(1'b0));
FDRE \addr_0_reg[6]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[6]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[6] ),
.R(1'b0));
FDRE \addr_0_reg[7]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[7]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[7] ),
.R(1'b0));
FDRE \addr_0_reg[8]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[8]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[8] ),
.R(1'b0));
FDRE \addr_0_reg[9]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[9]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[0]_i_1
(.I0(compute_addr_1[0]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[0]),
.O(\addr_1[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[10]_i_1
(.I0(compute_addr_1[10]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[10]),
.O(\addr_1[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[11]_i_1
(.I0(compute_addr_1[11]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[11]),
.O(\addr_1[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[12]_i_1
(.I0(compute_addr_1[12]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[12]),
.O(\addr_1[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[13]_i_1
(.I0(compute_addr_1[13]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[13]),
.O(\addr_1[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[1]_i_1
(.I0(compute_addr_1[1]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[1]),
.O(\addr_1[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[2]_i_1
(.I0(compute_addr_1[2]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[2]),
.O(\addr_1[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[3]_i_1
(.I0(compute_addr_1[3]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[3]),
.O(\addr_1[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[4]_i_1
(.I0(compute_addr_1[4]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[4]),
.O(\addr_1[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[5]_i_1
(.I0(compute_addr_1[5]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[5]),
.O(\addr_1[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[6]_i_1
(.I0(compute_addr_1[6]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[6]),
.O(\addr_1[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[7]_i_1
(.I0(compute_addr_1[7]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[7]),
.O(\addr_1[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[8]_i_1
(.I0(compute_addr_1[8]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[8]),
.O(\addr_1[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[9]_i_1
(.I0(compute_addr_1[9]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[9]),
.O(\addr_1[9]_i_1_n_0 ));
FDRE \addr_1_reg[0]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[0]_i_1_n_0 ),
.Q(addr_1[0]),
.R(1'b0));
FDRE \addr_1_reg[10]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[10]_i_1_n_0 ),
.Q(addr_1[10]),
.R(1'b0));
FDRE \addr_1_reg[11]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[11]_i_1_n_0 ),
.Q(addr_1[11]),
.R(1'b0));
FDRE \addr_1_reg[12]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[12]_i_1_n_0 ),
.Q(addr_1[12]),
.R(1'b0));
FDRE \addr_1_reg[13]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[13]_i_1_n_0 ),
.Q(addr_1[13]),
.R(1'b0));
FDRE \addr_1_reg[1]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[1]_i_1_n_0 ),
.Q(addr_1[1]),
.R(1'b0));
FDRE \addr_1_reg[2]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[2]_i_1_n_0 ),
.Q(addr_1[2]),
.R(1'b0));
FDRE \addr_1_reg[3]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[3]_i_1_n_0 ),
.Q(addr_1[3]),
.R(1'b0));
FDRE \addr_1_reg[4]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[4]_i_1_n_0 ),
.Q(addr_1[4]),
.R(1'b0));
FDRE \addr_1_reg[5]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[5]_i_1_n_0 ),
.Q(addr_1[5]),
.R(1'b0));
FDRE \addr_1_reg[6]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[6]_i_1_n_0 ),
.Q(addr_1[6]),
.R(1'b0));
FDRE \addr_1_reg[7]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[7]_i_1_n_0 ),
.Q(addr_1[7]),
.R(1'b0));
FDRE \addr_1_reg[8]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[8]_i_1_n_0 ),
.Q(addr_1[8]),
.R(1'b0));
FDRE \addr_1_reg[9]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[9]_i_1_n_0 ),
.Q(addr_1[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h8800880000000800))
\bottom_left_0[15]_i_1
(.I0(rst),
.I1(active),
.I2(cycle[2]),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(bottom_left_0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[0]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[0]),
.Q(\bottom_left_0_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[10]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[10]),
.Q(\bottom_left_0_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[11]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[11]),
.Q(\bottom_left_0_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[12]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[12]),
.Q(\bottom_left_0_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[13]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[13]),
.Q(\bottom_left_0_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[14]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[14]),
.Q(\bottom_left_0_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[15]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[15]),
.Q(\bottom_left_0_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[1]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[1]),
.Q(\bottom_left_0_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[2]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[2]),
.Q(\bottom_left_0_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[3]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[3]),
.Q(\bottom_left_0_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[4]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[4]),
.Q(\bottom_left_0_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[5]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[5]),
.Q(\bottom_left_0_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[6]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[6]),
.Q(\bottom_left_0_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[7]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[7]),
.Q(\bottom_left_0_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[8]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[8]),
.Q(\bottom_left_0_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[9]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[9]),
.Q(\bottom_left_0_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'h40000040))
\bottom_left_1[15]_i_1
(.I0(\cycle_reg[1]_rep_n_0 ),
.I1(active),
.I2(rst),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.O(top_right_1));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[0]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[0]),
.Q(bottom_left_1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[10]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[10]),
.Q(bottom_left_1[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[11]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[11]),
.Q(bottom_left_1[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[12]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[12]),
.Q(bottom_left_1[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[13]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[13]),
.Q(bottom_left_1[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[14]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[14]),
.Q(bottom_left_1[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[15]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[15]),
.Q(bottom_left_1[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[1]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[1]),
.Q(bottom_left_1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[2]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[2]),
.Q(bottom_left_1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[3]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[3]),
.Q(bottom_left_1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[4]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[4]),
.Q(bottom_left_1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[5]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[5]),
.Q(bottom_left_1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[6]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[6]),
.Q(bottom_left_1[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[7]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[7]),
.Q(bottom_left_1[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[8]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[8]),
.Q(bottom_left_1[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[9]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[9]),
.Q(bottom_left_1[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[0]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[0]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[0]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [0]),
.O(p_0_out[0]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[0]_i_2
(.I0(bottom_left_1[0]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[0]),
.I3(cycle[2]),
.I4(cycle[0]),
.O(\bottom_right_0[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[10]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[10]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[10]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [10]),
.O(p_0_out[10]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[10]_i_2
(.I0(bottom_left_1[10]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[10]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[11]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[11]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[11]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [11]),
.O(p_0_out[11]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[11]_i_2
(.I0(bottom_left_1[11]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[11]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[12]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[12]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[12]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [12]),
.O(p_0_out[12]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[12]_i_2
(.I0(bottom_left_1[12]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[12]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[13]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[13]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[13]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [13]),
.O(p_0_out[13]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[13]_i_2
(.I0(bottom_left_1[13]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[13]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[14]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[14]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[14]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [14]),
.O(p_0_out[14]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[14]_i_2
(.I0(bottom_left_1[14]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[14]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'h444A000000000000))
\bottom_right_0[15]_i_1
(.I0(cycle[0]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(rst),
.I5(active),
.O(\bottom_right_0[15]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[15]_i_2
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[15]_i_4_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[15]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [15]),
.O(p_0_out[15]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
\bottom_right_0[15]_i_3
(.I0(\cycle_reg[0]_rep_n_0 ),
.I1(cycle[2]),
.O(\bottom_right_0[15]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[15]_i_4
(.I0(bottom_left_1[15]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[15]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[15]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h04))
\bottom_right_0[15]_i_5
(.I0(cycle[2]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[0]),
.O(\bottom_right_0[15]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[1]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[1]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[1]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [1]),
.O(p_0_out[1]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[1]_i_2
(.I0(bottom_left_1[1]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[1]),
.I3(cycle[2]),
.I4(cycle[0]),
.O(\bottom_right_0[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[2]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[2]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[2]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [2]),
.O(p_0_out[2]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[2]_i_2
(.I0(bottom_left_1[2]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[2]),
.I3(cycle[2]),
.I4(cycle[0]),
.O(\bottom_right_0[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[3]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[3]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[3]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [3]),
.O(p_0_out[3]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[3]_i_2
(.I0(bottom_left_1[3]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[3]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[4]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[4]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[4]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [4]),
.O(p_0_out[4]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[4]_i_2
(.I0(bottom_left_1[4]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[4]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[5]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[5]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[5]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [5]),
.O(p_0_out[5]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[5]_i_2
(.I0(bottom_left_1[5]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[5]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[6]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[6]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[6]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [6]),
.O(p_0_out[6]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[6]_i_2
(.I0(bottom_left_1[6]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[6]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[7]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[7]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[7]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [7]),
.O(p_0_out[7]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[7]_i_2
(.I0(bottom_left_1[7]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[7]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[8]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[8]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[8]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [8]),
.O(p_0_out[8]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[8]_i_2
(.I0(bottom_left_1[8]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[8]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[9]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[9]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[9]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [9]),
.O(p_0_out[9]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[9]_i_2
(.I0(bottom_left_1[9]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[9]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[9]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[0]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[0]),
.Q(\bottom_right_0_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[10]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[10]),
.Q(\bottom_right_0_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[11]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[11]),
.Q(\bottom_right_0_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[12]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[12]),
.Q(\bottom_right_0_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[13]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[13]),
.Q(\bottom_right_0_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[14]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[14]),
.Q(\bottom_right_0_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[15]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[15]),
.Q(\bottom_right_0_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[1]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[1]),
.Q(\bottom_right_0_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[2]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[2]),
.Q(\bottom_right_0_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[3]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[3]),
.Q(\bottom_right_0_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[4]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[4]),
.Q(\bottom_right_0_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[5]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[5]),
.Q(\bottom_right_0_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[6]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[6]),
.Q(\bottom_right_0_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[7]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[7]),
.Q(\bottom_right_0_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[8]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[8]),
.Q(\bottom_right_0_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[9]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[9]),
.Q(\bottom_right_0_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[0]_i_1
(.I0(dout_0[0]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[0] ),
.O(\bottom_right_1[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[10]_i_1
(.I0(dout_0[10]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[10]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[10] ),
.O(\bottom_right_1[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[11]_i_1
(.I0(dout_0[11]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[11]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[11] ),
.O(\bottom_right_1[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[12]_i_1
(.I0(dout_0[12]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[12]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[12] ),
.O(\bottom_right_1[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[13]_i_1
(.I0(dout_0[13]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[13]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[13] ),
.O(\bottom_right_1[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[14]_i_1
(.I0(dout_0[14]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[14]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[14] ),
.O(\bottom_right_1[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[15]_i_1
(.I0(dout_0[15]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[15]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[15] ),
.O(\bottom_right_1[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[1]_i_1
(.I0(dout_0[1]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[1]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[1] ),
.O(\bottom_right_1[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[2]_i_1
(.I0(dout_0[2]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[2]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[2] ),
.O(\bottom_right_1[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[3]_i_1
(.I0(dout_0[3]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[3]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[3] ),
.O(\bottom_right_1[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[4]_i_1
(.I0(dout_0[4]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[4]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[4] ),
.O(\bottom_right_1[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[5]_i_1
(.I0(dout_0[5]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[5]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[5] ),
.O(\bottom_right_1[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[6]_i_1
(.I0(dout_0[6]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[6]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[6] ),
.O(\bottom_right_1[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[7]_i_1
(.I0(dout_0[7]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[7]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[7] ),
.O(\bottom_right_1[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[8]_i_1
(.I0(dout_0[8]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[8]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[8] ),
.O(\bottom_right_1[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[9]_i_1
(.I0(dout_0[9]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[9]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[9] ),
.O(\bottom_right_1[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[0]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[0]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[10]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[10]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[11]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[11]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[12]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[12]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[13]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[13]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[14]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[14]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[15]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[15]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[1]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[1]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[2]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[2]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[3]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[3]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[4]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[4]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[5]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[5]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[6]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[6]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[7]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[7]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[8]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[8]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[9]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[9]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[9] ),
.R(1'b0));
(* CHECK_LICENSE_TYPE = "blk_mem_gen_0,blk_mem_gen_v8_3_5,{}" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
system_vga_hessian_0_0_blk_mem_gen_0 bram_0
(.addra({\addr_0_reg_n_0_[13] ,\addr_0_reg_n_0_[12] ,\addr_0_reg_n_0_[11] ,\addr_0_reg_n_0_[10] ,\addr_0_reg_n_0_[9] ,\addr_0_reg_n_0_[8] ,\addr_0_reg_n_0_[7] ,\addr_0_reg_n_0_[6] ,\addr_0_reg_n_0_[5] ,\addr_0_reg_n_0_[4] ,\addr_0_reg_n_0_[3] ,\addr_0_reg_n_0_[2] ,\addr_0_reg_n_0_[1] ,\addr_0_reg_n_0_[0] }),
.addrb(addr_1),
.clka(clk_x16),
.clkb(clk_x16),
.dina({\din_reg_n_0_[15] ,\din_reg_n_0_[14] ,\din_reg_n_0_[13] ,\din_reg_n_0_[12] ,\din_reg_n_0_[11] ,\din_reg_n_0_[10] ,\din_reg_n_0_[9] ,\din_reg_n_0_[8] ,\din_reg_n_0_[7] ,\din_reg_n_0_[6] ,\din_reg_n_0_[5] ,\din_reg_n_0_[4] ,\din_reg_n_0_[3] ,\din_reg_n_0_[2] ,\din_reg_n_0_[1] ,\din_reg_n_0_[0] }),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(dout_0),
.doutb(dout_1),
.ena(1'b1),
.enb(1'b1),
.wea(wen_reg_n_0),
.web(1'b0));
LUT1 #(
.INIT(2'h1))
\cache[9][15]_i_1
(.I0(rst),
.O(\cache[9][15]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08000000))
\cache[9][15]_i_2
(.I0(active),
.I1(cycle[2]),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\cache[10]_5 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][0]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[0]),
.Q(\cache_reg[0]_4 [0]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][10]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[10]),
.Q(\cache_reg[0]_4 [10]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][11]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[11]),
.Q(\cache_reg[0]_4 [11]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][12]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[12]),
.Q(\cache_reg[0]_4 [12]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][13]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[13]),
.Q(\cache_reg[0]_4 [13]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][14]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[14]),
.Q(\cache_reg[0]_4 [14]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][15]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[15]),
.Q(\cache_reg[0]_4 [15]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][1]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[1]),
.Q(\cache_reg[0]_4 [1]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][2]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[2]),
.Q(\cache_reg[0]_4 [2]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][3]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[3]),
.Q(\cache_reg[0]_4 [3]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][4]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[4]),
.Q(\cache_reg[0]_4 [4]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][5]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[5]),
.Q(\cache_reg[0]_4 [5]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][6]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[6]),
.Q(\cache_reg[0]_4 [6]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][7]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[7]),
.Q(\cache_reg[0]_4 [7]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][8]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[8]),
.Q(\cache_reg[0]_4 [8]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][9]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[9]),
.Q(\cache_reg[0]_4 [9]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][0]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [0]),
.Q(\cache_reg[10]_3 [0]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][10]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [10]),
.Q(\cache_reg[10]_3 [10]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][11]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [11]),
.Q(\cache_reg[10]_3 [11]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][12]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [12]),
.Q(\cache_reg[10]_3 [12]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][13]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [13]),
.Q(\cache_reg[10]_3 [13]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][14]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [14]),
.Q(\cache_reg[10]_3 [14]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][15]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [15]),
.Q(\cache_reg[10]_3 [15]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][1]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [1]),
.Q(\cache_reg[10]_3 [1]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][2]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [2]),
.Q(\cache_reg[10]_3 [2]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][3]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [3]),
.Q(\cache_reg[10]_3 [3]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][4]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [4]),
.Q(\cache_reg[10]_3 [4]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][5]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [5]),
.Q(\cache_reg[10]_3 [5]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][6]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [6]),
.Q(\cache_reg[10]_3 [6]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][7]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [7]),
.Q(\cache_reg[10]_3 [7]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][8]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [8]),
.Q(\cache_reg[10]_3 [8]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][9]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [9]),
.Q(\cache_reg[10]_3 [9]),
.R(\cache[9][15]_i_1_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][0]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][0]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [0]),
.Q(\cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][10]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][10]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [10]),
.Q(\cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][11]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][11]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [11]),
.Q(\cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][12]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][12]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [12]),
.Q(\cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][13]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][13]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [13]),
.Q(\cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][14]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][14]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [14]),
.Q(\cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][15]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][15]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [15]),
.Q(\cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][1]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][1]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [1]),
.Q(\cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][2]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][2]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [2]),
.Q(\cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][3]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][3]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [3]),
.Q(\cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][4]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][4]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [4]),
.Q(\cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][5]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][5]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [5]),
.Q(\cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][6]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][6]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [6]),
.Q(\cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][7]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][7]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [7]),
.Q(\cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][8]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][8]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [8]),
.Q(\cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][9]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][9]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [9]),
.Q(\cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0 ));
FDRE \cache_reg[3][0]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][0]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][10]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][10]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][11]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][11]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][12]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][12]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][13]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][13]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][14]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][14]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][15]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][15]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][1]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][1]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][2]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][2]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][3]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][3]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][4]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][4]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][5]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][5]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][6]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][6]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][7]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][7]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][8]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][8]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][9]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][9]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[4][0]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__14_n_0),
.Q(\cache_reg[4]_0 [0]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][10]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__4_n_0),
.Q(\cache_reg[4]_0 [10]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][11]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__3_n_0),
.Q(\cache_reg[4]_0 [11]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][12]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__2_n_0),
.Q(\cache_reg[4]_0 [12]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][13]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__1_n_0),
.Q(\cache_reg[4]_0 [13]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][14]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__0_n_0),
.Q(\cache_reg[4]_0 [14]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][15]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate_n_0),
.Q(\cache_reg[4]_0 [15]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][1]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__13_n_0),
.Q(\cache_reg[4]_0 [1]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][2]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__12_n_0),
.Q(\cache_reg[4]_0 [2]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][3]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__11_n_0),
.Q(\cache_reg[4]_0 [3]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][4]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__10_n_0),
.Q(\cache_reg[4]_0 [4]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][5]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__9_n_0),
.Q(\cache_reg[4]_0 [5]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][6]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__8_n_0),
.Q(\cache_reg[4]_0 [6]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][7]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__7_n_0),
.Q(\cache_reg[4]_0 [7]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][8]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__6_n_0),
.Q(\cache_reg[4]_0 [8]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][9]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__5_n_0),
.Q(\cache_reg[4]_0 [9]),
.R(\cache[9][15]_i_1_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][0]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][0]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [0]),
.Q(\cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][10]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][10]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [10]),
.Q(\cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][11]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][11]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [11]),
.Q(\cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][12]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][12]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [12]),
.Q(\cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][13]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][13]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [13]),
.Q(\cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][14]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][14]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [14]),
.Q(\cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][15]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][15]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [15]),
.Q(\cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][1]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][1]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [1]),
.Q(\cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][2]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][2]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [2]),
.Q(\cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][3]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][3]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [3]),
.Q(\cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][4]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][4]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [4]),
.Q(\cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][5]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][5]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [5]),
.Q(\cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][6]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][6]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [6]),
.Q(\cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][7]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][7]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [7]),
.Q(\cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][8]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][8]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [8]),
.Q(\cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][9]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][9]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [9]),
.Q(\cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0 ));
FDRE \cache_reg[7][0]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][0]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][10]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][10]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][11]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][11]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][12]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][12]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][13]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][13]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][14]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][14]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][15]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][15]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][1]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][1]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][2]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][2]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][3]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][3]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][4]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][4]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][5]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][5]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][6]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][6]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][7]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][7]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][8]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][8]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][9]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][9]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[8][0]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__30_n_0),
.Q(\cache_reg[8]_1 [0]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][10]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__20_n_0),
.Q(\cache_reg[8]_1 [10]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][11]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__19_n_0),
.Q(\cache_reg[8]_1 [11]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][12]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__18_n_0),
.Q(\cache_reg[8]_1 [12]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][13]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__17_n_0),
.Q(\cache_reg[8]_1 [13]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][14]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__16_n_0),
.Q(\cache_reg[8]_1 [14]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][15]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__15_n_0),
.Q(\cache_reg[8]_1 [15]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][1]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__29_n_0),
.Q(\cache_reg[8]_1 [1]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][2]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__28_n_0),
.Q(\cache_reg[8]_1 [2]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][3]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__27_n_0),
.Q(\cache_reg[8]_1 [3]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][4]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__26_n_0),
.Q(\cache_reg[8]_1 [4]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][5]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__25_n_0),
.Q(\cache_reg[8]_1 [5]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][6]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__24_n_0),
.Q(\cache_reg[8]_1 [6]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][7]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__23_n_0),
.Q(\cache_reg[8]_1 [7]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][8]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__22_n_0),
.Q(\cache_reg[8]_1 [8]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][9]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__21_n_0),
.Q(\cache_reg[8]_1 [9]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][0]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [0]),
.Q(\cache_reg[9]_2 [0]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][10]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [10]),
.Q(\cache_reg[9]_2 [10]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][11]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [11]),
.Q(\cache_reg[9]_2 [11]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][12]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [12]),
.Q(\cache_reg[9]_2 [12]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][13]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [13]),
.Q(\cache_reg[9]_2 [13]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][14]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [14]),
.Q(\cache_reg[9]_2 [14]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][15]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [15]),
.Q(\cache_reg[9]_2 [15]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][1]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [1]),
.Q(\cache_reg[9]_2 [1]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][2]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [2]),
.Q(\cache_reg[9]_2 [2]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][3]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [3]),
.Q(\cache_reg[9]_2 [3]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][4]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [4]),
.Q(\cache_reg[9]_2 [4]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][5]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [5]),
.Q(\cache_reg[9]_2 [5]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][6]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [6]),
.Q(\cache_reg[9]_2 [6]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][7]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [7]),
.Q(\cache_reg[9]_2 [7]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][8]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [8]),
.Q(\cache_reg[9]_2 [8]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][9]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [9]),
.Q(\cache_reg[9]_2 [9]),
.R(\cache[9][15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate
(.I0(\cache_reg[3][15]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate_n_0));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__0
(.I0(\cache_reg[3][14]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__1
(.I0(\cache_reg[3][13]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__10
(.I0(\cache_reg[3][4]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__10_n_0));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__11
(.I0(\cache_reg[3][3]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__11_n_0));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__12
(.I0(\cache_reg[3][2]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__12_n_0));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__13
(.I0(\cache_reg[3][1]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__13_n_0));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__14
(.I0(\cache_reg[3][0]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__14_n_0));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__15
(.I0(\cache_reg[7][15]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__15_n_0));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__16
(.I0(\cache_reg[7][14]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__16_n_0));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__17
(.I0(\cache_reg[7][13]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__17_n_0));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__18
(.I0(\cache_reg[7][12]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__18_n_0));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__19
(.I0(\cache_reg[7][11]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__19_n_0));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__2
(.I0(\cache_reg[3][12]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__2_n_0));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__20
(.I0(\cache_reg[7][10]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__20_n_0));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__21
(.I0(\cache_reg[7][9]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__21_n_0));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__22
(.I0(\cache_reg[7][8]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__22_n_0));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__23
(.I0(\cache_reg[7][7]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__23_n_0));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__24
(.I0(\cache_reg[7][6]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__24_n_0));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__25
(.I0(\cache_reg[7][5]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__25_n_0));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__26
(.I0(\cache_reg[7][4]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__26_n_0));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__27
(.I0(\cache_reg[7][3]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__27_n_0));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__28
(.I0(\cache_reg[7][2]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__28_n_0));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__29
(.I0(\cache_reg[7][1]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__29_n_0));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__3
(.I0(\cache_reg[3][11]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__3_n_0));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__30
(.I0(\cache_reg[7][0]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__30_n_0));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__4
(.I0(\cache_reg[3][10]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__4_n_0));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__5
(.I0(\cache_reg[3][9]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__5_n_0));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__6
(.I0(\cache_reg[3][8]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__6_n_0));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__7
(.I0(\cache_reg[3][7]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__7_n_0));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__8
(.I0(\cache_reg[3][6]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__8_n_0));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__9
(.I0(\cache_reg[3][5]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__9_n_0));
FDRE cache_reg_r
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(1'b1),
.Q(cache_reg_r_n_0),
.R(\cache[9][15]_i_1_n_0 ));
FDRE cache_reg_r_0
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_r_n_0),
.Q(cache_reg_r_0_n_0),
.R(\cache[9][15]_i_1_n_0 ));
FDRE cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_r_0_n_0),
.Q(cache_reg_r_1_n_0),
.R(\cache[9][15]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[0]_i_1
(.I0(\x_reg_n_0_[0] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[0]),
.O(\compute_addr_0[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_0[10]_i_1
(.I0(data5[10]),
.I1(cycle[0]),
.I2(\compute_addr_2[10]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_0[10]_i_2_n_0 ),
.O(\compute_addr_0[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFC000000000FA0A))
\compute_addr_0[10]_i_2
(.I0(\y3_reg_n_0_[0] ),
.I1(data5[10]),
.I2(cycle[3]),
.I3(\y1_reg_n_0_[0] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_0[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hDDDDDDDDCDC88888))
\compute_addr_0[11]_i_1
(.I0(cycle[0]),
.I1(data5[11]),
.I2(cycle[3]),
.I3(\y1_reg_n_0_[1] ),
.I4(\compute_addr_0[11]_i_2_n_0 ),
.I5(\compute_addr_0[11]_i_3_n_0 ),
.O(\compute_addr_0[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\compute_addr_0[11]_i_2
(.I0(cycle[2]),
.I1(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_0[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000AAAAAAAACFC0))
\compute_addr_0[11]_i_3
(.I0(\compute_addr_2[11]_i_2_n_0 ),
.I1(\y1_reg_n_0_[1] ),
.I2(cycle[3]),
.I3(\y3_reg_n_0_[1] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_0[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_0[12]_i_1
(.I0(data5[12]),
.I1(cycle[0]),
.I2(\compute_addr_2[12]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_0[12]_i_2_n_0 ),
.O(\compute_addr_0[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFC000000000FA0A))
\compute_addr_0[12]_i_2
(.I0(\y3_reg_n_0_[2] ),
.I1(data5[12]),
.I2(cycle[3]),
.I3(\y1_reg_n_0_[2] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_0[12]_i_2_n_0 ));
LUT3 #(
.INIT(8'h08))
\compute_addr_0[13]_i_1
(.I0(rst),
.I1(active),
.I2(cycle[0]),
.O(compute_addr_0));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_0[13]_i_2
(.I0(data5[13]),
.I1(cycle[0]),
.I2(\compute_addr_2[13]_i_4_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_0[13]_i_3_n_0 ),
.O(\compute_addr_0[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hCFC000000000FA0A))
\compute_addr_0[13]_i_3
(.I0(\y3_reg_n_0_[3] ),
.I1(data5[13]),
.I2(cycle[3]),
.I3(\y1_reg_n_0_[3] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_0[13]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[1]_i_1
(.I0(\x_reg_n_0_[1] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[1]),
.O(\compute_addr_0[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[2]_i_1
(.I0(\x_reg_n_0_[2] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[2]),
.O(\compute_addr_0[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[3]_i_1
(.I0(\x_reg_n_0_[3] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[3]),
.O(\compute_addr_0[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[4]_i_1
(.I0(\x_reg_n_0_[4] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[4]),
.O(\compute_addr_0[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[5]_i_1
(.I0(\x_reg_n_0_[5] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[5]),
.O(\compute_addr_0[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[6]_i_1
(.I0(\x_reg_n_0_[6] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[6]),
.O(\compute_addr_0[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[7]_i_1
(.I0(\x_reg_n_0_[7] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[7]),
.O(\compute_addr_0[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[8]_i_1
(.I0(\x_reg_n_0_[8] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[8]),
.O(\compute_addr_0[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[9]_i_1
(.I0(\x_reg_n_0_[9] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(data1[9]),
.O(\compute_addr_0[9]_i_1_n_0 ));
FDRE \compute_addr_0_reg[0]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[0]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[0] ),
.R(1'b0));
FDRE \compute_addr_0_reg[10]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[10]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[10] ),
.R(1'b0));
FDRE \compute_addr_0_reg[11]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[11]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[11] ),
.R(1'b0));
FDRE \compute_addr_0_reg[12]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[12]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[12] ),
.R(1'b0));
FDRE \compute_addr_0_reg[13]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[13]_i_2_n_0 ),
.Q(\compute_addr_0_reg_n_0_[13] ),
.R(1'b0));
FDRE \compute_addr_0_reg[1]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[1]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[1] ),
.R(1'b0));
FDRE \compute_addr_0_reg[2]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[2]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[2] ),
.R(1'b0));
FDRE \compute_addr_0_reg[3]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[3]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[3] ),
.R(1'b0));
FDRE \compute_addr_0_reg[4]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[4]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[4] ),
.R(1'b0));
FDRE \compute_addr_0_reg[5]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[5]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[5] ),
.R(1'b0));
FDRE \compute_addr_0_reg[6]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[6]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[6] ),
.R(1'b0));
FDRE \compute_addr_0_reg[7]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[7]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[7] ),
.R(1'b0));
FDRE \compute_addr_0_reg[8]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[8]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[8] ),
.R(1'b0));
FDRE \compute_addr_0_reg[9]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[9]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[0]_i_1
(.I0(data1[0]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[0]),
.O(\compute_addr_1[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_1[10]_i_1
(.I0(data5[10]),
.I1(cycle[0]),
.I2(\compute_addr_3[10]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_1[10]_i_2_n_0 ),
.O(\compute_addr_1[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'hACAC00000000CFC0))
\compute_addr_1[10]_i_2
(.I0(data5[10]),
.I1(data2[10]),
.I2(cycle[3]),
.I3(\y3_reg_n_0_[0] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_1[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_1[11]_i_1
(.I0(data5[11]),
.I1(cycle[0]),
.I2(\compute_addr_3[11]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_1[11]_i_2_n_0 ),
.O(\compute_addr_1[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hACAC00000000CFC0))
\compute_addr_1[11]_i_2
(.I0(data5[11]),
.I1(data2[11]),
.I2(cycle[3]),
.I3(\y3_reg_n_0_[1] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_1[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_1[12]_i_1
(.I0(data5[12]),
.I1(cycle[0]),
.I2(\compute_addr_3[12]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_1[12]_i_2_n_0 ),
.O(\compute_addr_1[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hACAC00000000CFC0))
\compute_addr_1[12]_i_2
(.I0(data5[12]),
.I1(data2[12]),
.I2(cycle[3]),
.I3(\y3_reg_n_0_[2] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_1[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_1[13]_i_1
(.I0(data5[13]),
.I1(cycle[0]),
.I2(\compute_addr_3[13]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_1[13]_i_2_n_0 ),
.O(\compute_addr_1[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFC000000000FA0A))
\compute_addr_1[13]_i_2
(.I0(\y3_reg_n_0_[3] ),
.I1(data5[13]),
.I2(cycle[3]),
.I3(data2[13]),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_1[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[1]_i_1
(.I0(data1[1]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[1]),
.O(\compute_addr_1[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[2]_i_1
(.I0(data1[2]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[2]),
.O(\compute_addr_1[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[3]_i_1
(.I0(data1[3]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[3]),
.O(\compute_addr_1[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[4]_i_1
(.I0(data1[4]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[4]),
.O(\compute_addr_1[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[5]_i_1
(.I0(data1[5]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[5]),
.O(\compute_addr_1[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[6]_i_1
(.I0(data1[6]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[6]),
.O(\compute_addr_1[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[7]_i_1
(.I0(data1[7]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[7]),
.O(\compute_addr_1[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[8]_i_1
(.I0(data1[8]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[8]),
.O(\compute_addr_1[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[9]_i_1
(.I0(data1[9]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[9]),
.O(\compute_addr_1[9]_i_1_n_0 ));
FDRE \compute_addr_1_reg[0]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[0]_i_1_n_0 ),
.Q(compute_addr_1[0]),
.R(1'b0));
FDRE \compute_addr_1_reg[10]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[10]_i_1_n_0 ),
.Q(compute_addr_1[10]),
.R(1'b0));
FDRE \compute_addr_1_reg[11]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[11]_i_1_n_0 ),
.Q(compute_addr_1[11]),
.R(1'b0));
FDRE \compute_addr_1_reg[12]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[12]_i_1_n_0 ),
.Q(compute_addr_1[12]),
.R(1'b0));
FDRE \compute_addr_1_reg[13]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[13]_i_1_n_0 ),
.Q(compute_addr_1[13]),
.R(1'b0));
FDRE \compute_addr_1_reg[1]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[1]_i_1_n_0 ),
.Q(compute_addr_1[1]),
.R(1'b0));
FDRE \compute_addr_1_reg[2]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[2]_i_1_n_0 ),
.Q(compute_addr_1[2]),
.R(1'b0));
FDRE \compute_addr_1_reg[3]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[3]_i_1_n_0 ),
.Q(compute_addr_1[3]),
.R(1'b0));
FDRE \compute_addr_1_reg[4]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[4]_i_1_n_0 ),
.Q(compute_addr_1[4]),
.R(1'b0));
FDRE \compute_addr_1_reg[5]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[5]_i_1_n_0 ),
.Q(compute_addr_1[5]),
.R(1'b0));
FDRE \compute_addr_1_reg[6]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[6]_i_1_n_0 ),
.Q(compute_addr_1[6]),
.R(1'b0));
FDRE \compute_addr_1_reg[7]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[7]_i_1_n_0 ),
.Q(compute_addr_1[7]),
.R(1'b0));
FDRE \compute_addr_1_reg[8]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[8]_i_1_n_0 ),
.Q(compute_addr_1[8]),
.R(1'b0));
FDRE \compute_addr_1_reg[9]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[9]_i_1_n_0 ),
.Q(compute_addr_1[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_2[10]_i_1
(.I0(\y6_reg_n_0_[0] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_2[10]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\y1_reg_n_0_[0] ),
.O(\compute_addr_2[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_2[10]_i_2
(.I0(\y2_reg_n_0_[0] ),
.I1(cycle[3]),
.I2(data1[10]),
.O(\compute_addr_2[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_2[11]_i_1
(.I0(\y6_reg_n_0_[1] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_2[11]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\y1_reg_n_0_[1] ),
.O(\compute_addr_2[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_2[11]_i_2
(.I0(\y2_reg_n_0_[1] ),
.I1(cycle[3]),
.I2(data1[11]),
.O(\compute_addr_2[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_2[12]_i_1
(.I0(\y6_reg_n_0_[2] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_2[12]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\y1_reg_n_0_[2] ),
.O(\compute_addr_2[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_2[12]_i_2
(.I0(\y2_reg_n_0_[2] ),
.I1(cycle[3]),
.I2(data1[12]),
.O(\compute_addr_2[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'h8080808080808000))
\compute_addr_2[13]_i_1
(.I0(\cycle_reg[0]_rep_n_0 ),
.I1(active),
.I2(rst),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[3]),
.I5(cycle[2]),
.O(compute_addr_2));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_2[13]_i_2
(.I0(\y6_reg_n_0_[3] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_2[13]_i_4_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\y1_reg_n_0_[3] ),
.O(\compute_addr_2[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h81FF))
\compute_addr_2[13]_i_3
(.I0(cycle[3]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.O(\compute_addr_2[13]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_2[13]_i_4
(.I0(\y2_reg_n_0_[3] ),
.I1(cycle[3]),
.I2(data1[13]),
.O(\compute_addr_2[13]_i_4_n_0 ));
FDRE \compute_addr_2_reg[0]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[0]),
.Q(\compute_addr_2_reg_n_0_[0] ),
.R(1'b0));
FDRE \compute_addr_2_reg[10]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_2[10]_i_1_n_0 ),
.Q(\compute_addr_2_reg_n_0_[10] ),
.R(1'b0));
FDRE \compute_addr_2_reg[11]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_2[11]_i_1_n_0 ),
.Q(\compute_addr_2_reg_n_0_[11] ),
.R(1'b0));
FDRE \compute_addr_2_reg[12]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_2[12]_i_1_n_0 ),
.Q(\compute_addr_2_reg_n_0_[12] ),
.R(1'b0));
FDRE \compute_addr_2_reg[13]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_2[13]_i_2_n_0 ),
.Q(\compute_addr_2_reg_n_0_[13] ),
.R(1'b0));
FDRE \compute_addr_2_reg[1]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[1]),
.Q(\compute_addr_2_reg_n_0_[1] ),
.R(1'b0));
FDRE \compute_addr_2_reg[2]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[2]),
.Q(\compute_addr_2_reg_n_0_[2] ),
.R(1'b0));
FDRE \compute_addr_2_reg[3]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[3]),
.Q(\compute_addr_2_reg_n_0_[3] ),
.R(1'b0));
FDRE \compute_addr_2_reg[4]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[4]),
.Q(\compute_addr_2_reg_n_0_[4] ),
.R(1'b0));
FDRE \compute_addr_2_reg[5]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[5]),
.Q(\compute_addr_2_reg_n_0_[5] ),
.R(1'b0));
FDRE \compute_addr_2_reg[6]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[6]),
.Q(\compute_addr_2_reg_n_0_[6] ),
.R(1'b0));
FDRE \compute_addr_2_reg[7]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[7]),
.Q(\compute_addr_2_reg_n_0_[7] ),
.R(1'b0));
FDRE \compute_addr_2_reg[8]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[8]),
.Q(\compute_addr_2_reg_n_0_[8] ),
.R(1'b0));
FDRE \compute_addr_2_reg[9]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[9]),
.Q(\compute_addr_2_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[0]_i_1
(.I0(data1[0]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[0]),
.O(\compute_addr_3[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_3[10]_i_1
(.I0(\y6_reg_n_0_[0] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_3[10]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(data2[10]),
.O(\compute_addr_3[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_3[10]_i_2
(.I0(y7[0]),
.I1(cycle[3]),
.I2(y8[0]),
.O(\compute_addr_3[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_3[11]_i_1
(.I0(\y6_reg_n_0_[1] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_3[11]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(data2[11]),
.O(\compute_addr_3[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_3[11]_i_2
(.I0(y7[1]),
.I1(cycle[3]),
.I2(y8[1]),
.O(\compute_addr_3[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_3[12]_i_1
(.I0(\y6_reg_n_0_[2] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_3[12]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(data2[12]),
.O(\compute_addr_3[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_3[12]_i_2
(.I0(y7[2]),
.I1(cycle[3]),
.I2(y8[2]),
.O(\compute_addr_3[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_3[13]_i_1
(.I0(\y6_reg_n_0_[3] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_3[13]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(data2[13]),
.O(\compute_addr_3[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_3[13]_i_2
(.I0(y7[3]),
.I1(cycle[3]),
.I2(y8[3]),
.O(\compute_addr_3[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[1]_i_1
(.I0(data1[1]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[1]),
.O(\compute_addr_3[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[2]_i_1
(.I0(data1[2]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[2]),
.O(\compute_addr_3[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[3]_i_1
(.I0(data1[3]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[3]),
.O(\compute_addr_3[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[4]_i_1
(.I0(data1[4]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[4]),
.O(\compute_addr_3[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[5]_i_1
(.I0(data1[5]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[5]),
.O(\compute_addr_3[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[6]_i_1
(.I0(data1[6]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[6]),
.O(\compute_addr_3[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[7]_i_1
(.I0(data1[7]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[7]),
.O(\compute_addr_3[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[8]_i_1
(.I0(data1[8]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[8]),
.O(\compute_addr_3[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[9]_i_1
(.I0(data1[9]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[9]),
.O(\compute_addr_3[9]_i_1_n_0 ));
FDRE \compute_addr_3_reg[0]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[0]_i_1_n_0 ),
.Q(compute_addr_3[0]),
.R(1'b0));
FDRE \compute_addr_3_reg[10]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[10]_i_1_n_0 ),
.Q(compute_addr_3[10]),
.R(1'b0));
FDRE \compute_addr_3_reg[11]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[11]_i_1_n_0 ),
.Q(compute_addr_3[11]),
.R(1'b0));
FDRE \compute_addr_3_reg[12]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[12]_i_1_n_0 ),
.Q(compute_addr_3[12]),
.R(1'b0));
FDRE \compute_addr_3_reg[13]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[13]_i_1_n_0 ),
.Q(compute_addr_3[13]),
.R(1'b0));
FDRE \compute_addr_3_reg[1]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[1]_i_1_n_0 ),
.Q(compute_addr_3[1]),
.R(1'b0));
FDRE \compute_addr_3_reg[2]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[2]_i_1_n_0 ),
.Q(compute_addr_3[2]),
.R(1'b0));
FDRE \compute_addr_3_reg[3]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[3]_i_1_n_0 ),
.Q(compute_addr_3[3]),
.R(1'b0));
FDRE \compute_addr_3_reg[4]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[4]_i_1_n_0 ),
.Q(compute_addr_3[4]),
.R(1'b0));
FDRE \compute_addr_3_reg[5]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[5]_i_1_n_0 ),
.Q(compute_addr_3[5]),
.R(1'b0));
FDRE \compute_addr_3_reg[6]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[6]_i_1_n_0 ),
.Q(compute_addr_3[6]),
.R(1'b0));
FDRE \compute_addr_3_reg[7]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[7]_i_1_n_0 ),
.Q(compute_addr_3[7]),
.R(1'b0));
FDRE \compute_addr_3_reg[8]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[8]_i_1_n_0 ),
.Q(compute_addr_3[8]),
.R(1'b0));
FDRE \compute_addr_3_reg[9]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[9]_i_1_n_0 ),
.Q(compute_addr_3[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFFF00000008))
\corner[15]_i_1
(.I0(\left[15]_i_2_n_0 ),
.I1(x),
.I2(\x_reg_n_0_[0] ),
.I3(\x_reg_n_0_[9] ),
.I4(\x_reg_n_0_[8] ),
.I5(top),
.O(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[0]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [0]),
.Q(\corner_reg_n_0_[0] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[10]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [10]),
.Q(\corner_reg_n_0_[10] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[11]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [11]),
.Q(\corner_reg_n_0_[11] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[12]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [12]),
.Q(\corner_reg_n_0_[12] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[13]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [13]),
.Q(\corner_reg_n_0_[13] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[14]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [14]),
.Q(\corner_reg_n_0_[14] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[15]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [15]),
.Q(\corner_reg_n_0_[15] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[1]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [1]),
.Q(\corner_reg_n_0_[1] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[2]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [2]),
.Q(\corner_reg_n_0_[2] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[3]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [3]),
.Q(\corner_reg_n_0_[3] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[4]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [4]),
.Q(\corner_reg_n_0_[4] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[5]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [5]),
.Q(\corner_reg_n_0_[5] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[6]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [6]),
.Q(\corner_reg_n_0_[6] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[7]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [7]),
.Q(\corner_reg_n_0_[7] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[8]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [8]),
.Q(\corner_reg_n_0_[8] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[9]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [9]),
.Q(\corner_reg_n_0_[9] ),
.R(corner));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT1 #(
.INIT(2'h1))
\cycle[0]_i_1
(.I0(cycle[0]),
.O(\cycle[0]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\cycle[0]_rep_i_1
(.I0(cycle[0]),
.O(\cycle[0]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'h6))
\cycle[1]_i_1
(.I0(cycle[1]),
.I1(cycle[0]),
.O(\cycle[1]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\cycle[1]_rep_i_1
(.I0(cycle[1]),
.I1(cycle[0]),
.O(\cycle[1]_rep_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\cycle[1]_rep_i_1__0
(.I0(cycle[1]),
.I1(cycle[0]),
.O(\cycle[1]_rep_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'h78))
\cycle[2]_i_1
(.I0(cycle[1]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[2]),
.O(\cycle[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'h78))
\cycle[2]_rep_i_1
(.I0(\cycle_reg[1]_rep_n_0 ),
.I1(cycle[0]),
.I2(cycle[2]),
.O(\cycle[2]_rep_i_1_n_0 ));
LUT2 #(
.INIT(4'h7))
\cycle[3]_i_1
(.I0(rst),
.I1(active),
.O(\cycle[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h6AAA))
\cycle[3]_i_2
(.I0(cycle[3]),
.I1(cycle[2]),
.I2(cycle[1]),
.I3(\cycle_reg[0]_rep_n_0 ),
.O(\cycle[3]_i_2_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[0]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[0]
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[0]_i_1_n_0 ),
.Q(cycle[0]),
.R(\cycle[3]_i_1_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[0]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[0]_rep
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[0]_rep_i_1_n_0 ),
.Q(\cycle_reg[0]_rep_n_0 ),
.R(\cycle[3]_i_1_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[1]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[1]
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[1]_i_1_n_0 ),
.Q(cycle[1]),
.R(\cycle[3]_i_1_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[1]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[1]_rep
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[1]_rep_i_1_n_0 ),
.Q(\cycle_reg[1]_rep_n_0 ),
.R(\cycle[3]_i_1_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[1]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[1]_rep__0
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[1]_rep_i_1__0_n_0 ),
.Q(\cycle_reg[1]_rep__0_n_0 ),
.R(\cycle[3]_i_1_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[2]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[2]
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[2]_i_1_n_0 ),
.Q(cycle[2]),
.R(\cycle[3]_i_1_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[2]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[2]_rep
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[2]_rep_i_1_n_0 ),
.Q(\cycle_reg[2]_rep_n_0 ),
.R(\cycle[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cycle_reg[3]
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[3]_i_2_n_0 ),
.Q(cycle[3]),
.R(\cycle[3]_i_1_n_0 ));
DSP48E1 #(
.ACASCREG(1),
.ADREG(1),
.ALUMODEREG(0),
.AREG(1),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(1),
.BREG(1),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(1),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
det_0_reg
(.A({A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_det_0_reg_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({B[15],B[15],B}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_det_0_reg_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_det_0_reg_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_det_0_reg_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(Lxx),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(det_0_reg_i_2_n_0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(det_0),
.CEP(1'b0),
.CLK(clk_x16),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_det_0_reg_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_det_0_reg_OVERFLOW_UNCONNECTED),
.P(NLW_det_0_reg_P_UNCONNECTED[47:0]),
.PATTERNBDETECT(NLW_det_0_reg_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_det_0_reg_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT({det_0_reg_n_106,det_0_reg_n_107,det_0_reg_n_108,det_0_reg_n_109,det_0_reg_n_110,det_0_reg_n_111,det_0_reg_n_112,det_0_reg_n_113,det_0_reg_n_114,det_0_reg_n_115,det_0_reg_n_116,det_0_reg_n_117,det_0_reg_n_118,det_0_reg_n_119,det_0_reg_n_120,det_0_reg_n_121,det_0_reg_n_122,det_0_reg_n_123,det_0_reg_n_124,det_0_reg_n_125,det_0_reg_n_126,det_0_reg_n_127,det_0_reg_n_128,det_0_reg_n_129,det_0_reg_n_130,det_0_reg_n_131,det_0_reg_n_132,det_0_reg_n_133,det_0_reg_n_134,det_0_reg_n_135,det_0_reg_n_136,det_0_reg_n_137,det_0_reg_n_138,det_0_reg_n_139,det_0_reg_n_140,det_0_reg_n_141,det_0_reg_n_142,det_0_reg_n_143,det_0_reg_n_144,det_0_reg_n_145,det_0_reg_n_146,det_0_reg_n_147,det_0_reg_n_148,det_0_reg_n_149,det_0_reg_n_150,det_0_reg_n_151,det_0_reg_n_152,det_0_reg_n_153}),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_det_0_reg_UNDERFLOW_UNCONNECTED));
LUT6 #(
.INIT(64'h0000000000008000))
det_0_reg_i_1
(.I0(\cycle_reg[0]_rep_n_0 ),
.I1(active),
.I2(rst),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(cycle[3]),
.O(Lxx));
LUT6 #(
.INIT(64'h2000000000000000))
det_0_reg_i_2
(.I0(cycle[2]),
.I1(cycle[3]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(rst),
.I5(active),
.O(det_0_reg_i_2_n_0));
LUT6 #(
.INIT(64'h0000000008000000))
det_0_reg_i_3
(.I0(cycle[2]),
.I1(cycle[3]),
.I2(cycle[1]),
.I3(rst),
.I4(active),
.I5(\cycle_reg[0]_rep_n_0 ),
.O(det_0));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[10]_i_1
(.I0(det_abs0[10]),
.I1(det_reg_n_95),
.I2(det_reg_n_74),
.O(\det_abs[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[11]_i_1
(.I0(det_abs0[11]),
.I1(det_reg_n_94),
.I2(det_reg_n_74),
.O(\det_abs[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[12]_i_1
(.I0(det_abs0[12]),
.I1(det_reg_n_93),
.I2(det_reg_n_74),
.O(\det_abs[12]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[12]_i_3
(.I0(det_reg_n_93),
.O(\det_abs[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[12]_i_4
(.I0(det_reg_n_94),
.O(\det_abs[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[12]_i_5
(.I0(det_reg_n_95),
.O(\det_abs[12]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[12]_i_6
(.I0(det_reg_n_96),
.O(\det_abs[12]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[13]_i_1
(.I0(det_abs0[13]),
.I1(det_reg_n_92),
.I2(det_reg_n_74),
.O(\det_abs[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[14]_i_1
(.I0(det_abs0[14]),
.I1(det_reg_n_91),
.I2(det_reg_n_74),
.O(\det_abs[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[15]_i_1
(.I0(det_abs0[15]),
.I1(det_reg_n_90),
.I2(det_reg_n_74),
.O(\det_abs[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[16]_i_1
(.I0(det_abs0[16]),
.I1(det_reg_n_89),
.I2(det_reg_n_74),
.O(\det_abs[16]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[16]_i_3
(.I0(det_reg_n_89),
.O(\det_abs[16]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[16]_i_4
(.I0(det_reg_n_90),
.O(\det_abs[16]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[16]_i_5
(.I0(det_reg_n_91),
.O(\det_abs[16]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[16]_i_6
(.I0(det_reg_n_92),
.O(\det_abs[16]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[17]_i_1
(.I0(det_abs0[17]),
.I1(det_reg_n_88),
.I2(det_reg_n_74),
.O(\det_abs[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[18]_i_1
(.I0(det_abs0[18]),
.I1(det_reg_n_87),
.I2(det_reg_n_74),
.O(\det_abs[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[19]_i_1
(.I0(det_abs0[19]),
.I1(det_reg_n_86),
.I2(det_reg_n_74),
.O(\det_abs[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[1]_i_1
(.I0(det_abs0[1]),
.I1(det_reg_n_104),
.I2(det_reg_n_74),
.O(\det_abs[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[20]_i_1
(.I0(det_abs0[20]),
.I1(det_reg_n_85),
.I2(det_reg_n_74),
.O(\det_abs[20]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[20]_i_3
(.I0(det_reg_n_85),
.O(\det_abs[20]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[20]_i_4
(.I0(det_reg_n_86),
.O(\det_abs[20]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[20]_i_5
(.I0(det_reg_n_87),
.O(\det_abs[20]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[20]_i_6
(.I0(det_reg_n_88),
.O(\det_abs[20]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[21]_i_1
(.I0(det_abs0[21]),
.I1(det_reg_n_84),
.I2(det_reg_n_74),
.O(\det_abs[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[22]_i_1
(.I0(det_abs0[22]),
.I1(det_reg_n_83),
.I2(det_reg_n_74),
.O(\det_abs[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[23]_i_1
(.I0(det_abs0[23]),
.I1(det_reg_n_82),
.I2(det_reg_n_74),
.O(\det_abs[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[24]_i_1
(.I0(det_abs0[24]),
.I1(det_reg_n_81),
.I2(det_reg_n_74),
.O(\det_abs[24]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[24]_i_3
(.I0(det_reg_n_81),
.O(\det_abs[24]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[24]_i_4
(.I0(det_reg_n_82),
.O(\det_abs[24]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[24]_i_5
(.I0(det_reg_n_83),
.O(\det_abs[24]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[24]_i_6
(.I0(det_reg_n_84),
.O(\det_abs[24]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[25]_i_1
(.I0(det_abs0[25]),
.I1(det_reg_n_80),
.I2(det_reg_n_74),
.O(\det_abs[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[26]_i_1
(.I0(det_abs0[26]),
.I1(det_reg_n_79),
.I2(det_reg_n_74),
.O(\det_abs[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[27]_i_1
(.I0(det_abs0[27]),
.I1(det_reg_n_78),
.I2(det_reg_n_74),
.O(\det_abs[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[28]_i_1
(.I0(det_abs0[28]),
.I1(det_reg_n_77),
.I2(det_reg_n_74),
.O(\det_abs[28]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[28]_i_3
(.I0(det_reg_n_77),
.O(\det_abs[28]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[28]_i_4
(.I0(det_reg_n_78),
.O(\det_abs[28]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[28]_i_5
(.I0(det_reg_n_79),
.O(\det_abs[28]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[28]_i_6
(.I0(det_reg_n_80),
.O(\det_abs[28]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[29]_i_1
(.I0(det_abs0[29]),
.I1(det_reg_n_76),
.I2(det_reg_n_74),
.O(\det_abs[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[2]_i_1
(.I0(det_abs0[2]),
.I1(det_reg_n_103),
.I2(det_reg_n_74),
.O(\det_abs[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[30]_i_1
(.I0(det_abs0[30]),
.I1(det_reg_n_75),
.I2(det_reg_n_74),
.O(\det_abs[30]_i_1_n_0 ));
LUT2 #(
.INIT(4'h8))
\det_abs[31]_i_1
(.I0(det_abs0[31]),
.I1(det_reg_n_74),
.O(\det_abs[31]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[31]_i_3
(.I0(det_reg_n_74),
.O(\det_abs[31]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[31]_i_4
(.I0(det_reg_n_75),
.O(\det_abs[31]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[31]_i_5
(.I0(det_reg_n_76),
.O(\det_abs[31]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[3]_i_1
(.I0(det_abs0[3]),
.I1(det_reg_n_102),
.I2(det_reg_n_74),
.O(\det_abs[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[4]_i_1
(.I0(det_abs0[4]),
.I1(det_reg_n_101),
.I2(det_reg_n_74),
.O(\det_abs[4]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[4]_i_3
(.I0(det_reg_n_105),
.O(\det_abs[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[4]_i_4
(.I0(det_reg_n_101),
.O(\det_abs[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[4]_i_5
(.I0(det_reg_n_102),
.O(\det_abs[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[4]_i_6
(.I0(det_reg_n_103),
.O(\det_abs[4]_i_6_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[4]_i_7
(.I0(det_reg_n_104),
.O(\det_abs[4]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[5]_i_1
(.I0(det_abs0[5]),
.I1(det_reg_n_100),
.I2(det_reg_n_74),
.O(\det_abs[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[6]_i_1
(.I0(det_abs0[6]),
.I1(det_reg_n_99),
.I2(det_reg_n_74),
.O(\det_abs[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[7]_i_1
(.I0(det_abs0[7]),
.I1(det_reg_n_98),
.I2(det_reg_n_74),
.O(\det_abs[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[8]_i_1
(.I0(det_abs0[8]),
.I1(det_reg_n_97),
.I2(det_reg_n_74),
.O(\det_abs[8]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[8]_i_3
(.I0(det_reg_n_97),
.O(\det_abs[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[8]_i_4
(.I0(det_reg_n_98),
.O(\det_abs[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[8]_i_5
(.I0(det_reg_n_99),
.O(\det_abs[8]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[8]_i_6
(.I0(det_reg_n_100),
.O(\det_abs[8]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[9]_i_1
(.I0(det_abs0[9]),
.I1(det_reg_n_96),
.I2(det_reg_n_74),
.O(\det_abs[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\det_abs_reg[0]
(.C(clk_x16),
.CE(y6),
.D(det_reg_n_105),
.Q(det_abs[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[10]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[10]_i_1_n_0 ),
.Q(det_abs[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[11]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[11]_i_1_n_0 ),
.Q(det_abs[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[12]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[12]_i_1_n_0 ),
.Q(det_abs[12]),
.R(1'b0));
CARRY4 \det_abs_reg[12]_i_2
(.CI(\det_abs_reg[8]_i_2_n_0 ),
.CO({\det_abs_reg[12]_i_2_n_0 ,\det_abs_reg[12]_i_2_n_1 ,\det_abs_reg[12]_i_2_n_2 ,\det_abs_reg[12]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[12:9]),
.S({\det_abs[12]_i_3_n_0 ,\det_abs[12]_i_4_n_0 ,\det_abs[12]_i_5_n_0 ,\det_abs[12]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[13]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[13]_i_1_n_0 ),
.Q(det_abs[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[14]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[14]_i_1_n_0 ),
.Q(det_abs[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[15]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[15]_i_1_n_0 ),
.Q(det_abs[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[16]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[16]_i_1_n_0 ),
.Q(det_abs[16]),
.R(1'b0));
CARRY4 \det_abs_reg[16]_i_2
(.CI(\det_abs_reg[12]_i_2_n_0 ),
.CO({\det_abs_reg[16]_i_2_n_0 ,\det_abs_reg[16]_i_2_n_1 ,\det_abs_reg[16]_i_2_n_2 ,\det_abs_reg[16]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[16:13]),
.S({\det_abs[16]_i_3_n_0 ,\det_abs[16]_i_4_n_0 ,\det_abs[16]_i_5_n_0 ,\det_abs[16]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[17]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[17]_i_1_n_0 ),
.Q(det_abs[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[18]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[18]_i_1_n_0 ),
.Q(det_abs[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[19]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[19]_i_1_n_0 ),
.Q(det_abs[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[1]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[1]_i_1_n_0 ),
.Q(det_abs[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[20]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[20]_i_1_n_0 ),
.Q(det_abs[20]),
.R(1'b0));
CARRY4 \det_abs_reg[20]_i_2
(.CI(\det_abs_reg[16]_i_2_n_0 ),
.CO({\det_abs_reg[20]_i_2_n_0 ,\det_abs_reg[20]_i_2_n_1 ,\det_abs_reg[20]_i_2_n_2 ,\det_abs_reg[20]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[20:17]),
.S({\det_abs[20]_i_3_n_0 ,\det_abs[20]_i_4_n_0 ,\det_abs[20]_i_5_n_0 ,\det_abs[20]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[21]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[21]_i_1_n_0 ),
.Q(det_abs[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[22]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[22]_i_1_n_0 ),
.Q(det_abs[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[23]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[23]_i_1_n_0 ),
.Q(det_abs[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[24]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[24]_i_1_n_0 ),
.Q(det_abs[24]),
.R(1'b0));
CARRY4 \det_abs_reg[24]_i_2
(.CI(\det_abs_reg[20]_i_2_n_0 ),
.CO({\det_abs_reg[24]_i_2_n_0 ,\det_abs_reg[24]_i_2_n_1 ,\det_abs_reg[24]_i_2_n_2 ,\det_abs_reg[24]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[24:21]),
.S({\det_abs[24]_i_3_n_0 ,\det_abs[24]_i_4_n_0 ,\det_abs[24]_i_5_n_0 ,\det_abs[24]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[25]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[25]_i_1_n_0 ),
.Q(det_abs[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[26]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[26]_i_1_n_0 ),
.Q(det_abs[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[27]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[27]_i_1_n_0 ),
.Q(det_abs[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[28]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[28]_i_1_n_0 ),
.Q(det_abs[28]),
.R(1'b0));
CARRY4 \det_abs_reg[28]_i_2
(.CI(\det_abs_reg[24]_i_2_n_0 ),
.CO({\det_abs_reg[28]_i_2_n_0 ,\det_abs_reg[28]_i_2_n_1 ,\det_abs_reg[28]_i_2_n_2 ,\det_abs_reg[28]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[28:25]),
.S({\det_abs[28]_i_3_n_0 ,\det_abs[28]_i_4_n_0 ,\det_abs[28]_i_5_n_0 ,\det_abs[28]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[29]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[29]_i_1_n_0 ),
.Q(det_abs[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[2]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[2]_i_1_n_0 ),
.Q(det_abs[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[30]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[30]_i_1_n_0 ),
.Q(det_abs[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[31]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[31]_i_1_n_0 ),
.Q(det_abs[31]),
.R(1'b0));
CARRY4 \det_abs_reg[31]_i_2
(.CI(\det_abs_reg[28]_i_2_n_0 ),
.CO({\NLW_det_abs_reg[31]_i_2_CO_UNCONNECTED [3:2],\det_abs_reg[31]_i_2_n_2 ,\det_abs_reg[31]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_det_abs_reg[31]_i_2_O_UNCONNECTED [3],det_abs0[31:29]}),
.S({1'b0,\det_abs[31]_i_3_n_0 ,\det_abs[31]_i_4_n_0 ,\det_abs[31]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[3]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[3]_i_1_n_0 ),
.Q(det_abs[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[4]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[4]_i_1_n_0 ),
.Q(det_abs[4]),
.R(1'b0));
CARRY4 \det_abs_reg[4]_i_2
(.CI(1'b0),
.CO({\det_abs_reg[4]_i_2_n_0 ,\det_abs_reg[4]_i_2_n_1 ,\det_abs_reg[4]_i_2_n_2 ,\det_abs_reg[4]_i_2_n_3 }),
.CYINIT(\det_abs[4]_i_3_n_0 ),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[4:1]),
.S({\det_abs[4]_i_4_n_0 ,\det_abs[4]_i_5_n_0 ,\det_abs[4]_i_6_n_0 ,\det_abs[4]_i_7_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[5]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[5]_i_1_n_0 ),
.Q(det_abs[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[6]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[6]_i_1_n_0 ),
.Q(det_abs[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[7]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[7]_i_1_n_0 ),
.Q(det_abs[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[8]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[8]_i_1_n_0 ),
.Q(det_abs[8]),
.R(1'b0));
CARRY4 \det_abs_reg[8]_i_2
(.CI(\det_abs_reg[4]_i_2_n_0 ),
.CO({\det_abs_reg[8]_i_2_n_0 ,\det_abs_reg[8]_i_2_n_1 ,\det_abs_reg[8]_i_2_n_2 ,\det_abs_reg[8]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[8:5]),
.S({\det_abs[8]_i_3_n_0 ,\det_abs[8]_i_4_n_0 ,\det_abs[8]_i_5_n_0 ,\det_abs[8]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[9]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[9]_i_1_n_0 ),
.Q(det_abs[9]),
.R(1'b0));
DSP48E1 #(
.ACASCREG(1),
.ADREG(1),
.ALUMODEREG(0),
.AREG(1),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(1),
.BREG(1),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(1),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(1),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
det_reg
(.A({Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_5,Lxy0__1_carry__2_n_6,Lxy0__1_carry__2_n_7,Lxy0__1_carry__1_n_4,Lxy0__1_carry__1_n_5,Lxy0__1_carry__1_n_6,Lxy0__1_carry__1_n_7,Lxy0__1_carry__0_n_4,Lxy0__1_carry__0_n_5,Lxy0__1_carry__0_n_6,Lxy0__1_carry__0_n_7,Lxy0__1_carry_n_4,Lxy0__1_carry_n_5,Lxy0__1_carry_n_6,Lxy0__1_carry_n_7}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_det_reg_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b1,1'b1}),
.B({Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_5,Lxy0__1_carry__2_n_6,Lxy0__1_carry__2_n_7,Lxy0__1_carry__1_n_4,Lxy0__1_carry__1_n_5,Lxy0__1_carry__1_n_6,Lxy0__1_carry__1_n_7,Lxy0__1_carry__0_n_4,Lxy0__1_carry__0_n_5,Lxy0__1_carry__0_n_6,Lxy0__1_carry__0_n_7,Lxy0__1_carry_n_4,Lxy0__1_carry_n_5,Lxy0__1_carry_n_6,Lxy0__1_carry_n_7}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_det_reg_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_det_reg_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_det_reg_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(y3),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(y3),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(y2),
.CEP(y9),
.CLK(clk_x16),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_det_reg_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_det_reg_OVERFLOW_UNCONNECTED),
.P({NLW_det_reg_P_UNCONNECTED[47:32],det_reg_n_74,det_reg_n_75,det_reg_n_76,det_reg_n_77,det_reg_n_78,det_reg_n_79,det_reg_n_80,det_reg_n_81,det_reg_n_82,det_reg_n_83,det_reg_n_84,det_reg_n_85,det_reg_n_86,det_reg_n_87,det_reg_n_88,det_reg_n_89,det_reg_n_90,det_reg_n_91,det_reg_n_92,det_reg_n_93,det_reg_n_94,det_reg_n_95,det_reg_n_96,det_reg_n_97,det_reg_n_98,det_reg_n_99,det_reg_n_100,det_reg_n_101,det_reg_n_102,det_reg_n_103,det_reg_n_104,det_reg_n_105}),
.PATTERNBDETECT(NLW_det_reg_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_det_reg_PATTERNDETECT_UNCONNECTED),
.PCIN({det_0_reg_n_106,det_0_reg_n_107,det_0_reg_n_108,det_0_reg_n_109,det_0_reg_n_110,det_0_reg_n_111,det_0_reg_n_112,det_0_reg_n_113,det_0_reg_n_114,det_0_reg_n_115,det_0_reg_n_116,det_0_reg_n_117,det_0_reg_n_118,det_0_reg_n_119,det_0_reg_n_120,det_0_reg_n_121,det_0_reg_n_122,det_0_reg_n_123,det_0_reg_n_124,det_0_reg_n_125,det_0_reg_n_126,det_0_reg_n_127,det_0_reg_n_128,det_0_reg_n_129,det_0_reg_n_130,det_0_reg_n_131,det_0_reg_n_132,det_0_reg_n_133,det_0_reg_n_134,det_0_reg_n_135,det_0_reg_n_136,det_0_reg_n_137,det_0_reg_n_138,det_0_reg_n_139,det_0_reg_n_140,det_0_reg_n_141,det_0_reg_n_142,det_0_reg_n_143,det_0_reg_n_144,det_0_reg_n_145,det_0_reg_n_146,det_0_reg_n_147,det_0_reg_n_148,det_0_reg_n_149,det_0_reg_n_150,det_0_reg_n_151,det_0_reg_n_152,det_0_reg_n_153}),
.PCOUT(NLW_det_reg_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_det_reg_UNDERFLOW_UNCONNECTED));
LUT6 #(
.INIT(64'h0000000040000000))
det_reg_i_1
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(cycle[3]),
.I2(rst),
.I3(active),
.I4(\cycle_reg[0]_rep_n_0 ),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(y2));
LUT6 #(
.INIT(64'h0000000080000000))
det_reg_i_2
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(cycle[3]),
.I2(rst),
.I3(active),
.I4(\cycle_reg[0]_rep_n_0 ),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(y9));
FDRE #(
.INIT(1'b0))
\din_reg[0]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [0]),
.Q(\din_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[10]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [10]),
.Q(\din_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[11]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [11]),
.Q(\din_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[12]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [12]),
.Q(\din_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[13]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [13]),
.Q(\din_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[14]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [14]),
.Q(\din_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[15]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [15]),
.Q(\din_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[1]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [1]),
.Q(\din_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[2]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [2]),
.Q(\din_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[3]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [3]),
.Q(\din_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[4]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [4]),
.Q(\din_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[5]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [5]),
.Q(\din_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[6]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [6]),
.Q(\din_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[7]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [7]),
.Q(\din_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[8]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [8]),
.Q(\din_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[9]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [9]),
.Q(\din_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'h8000000000000000))
\hessian_out[31]_i_1
(.I0(rst),
.I1(active),
.I2(cycle[3]),
.I3(cycle[0]),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(y3));
FDRE \hessian_out_reg[0]
(.C(clk_x16),
.CE(y3),
.D(det_abs[0]),
.Q(hessian_out[0]),
.R(1'b0));
FDRE \hessian_out_reg[10]
(.C(clk_x16),
.CE(y3),
.D(det_abs[10]),
.Q(hessian_out[10]),
.R(1'b0));
FDRE \hessian_out_reg[11]
(.C(clk_x16),
.CE(y3),
.D(det_abs[11]),
.Q(hessian_out[11]),
.R(1'b0));
FDRE \hessian_out_reg[12]
(.C(clk_x16),
.CE(y3),
.D(det_abs[12]),
.Q(hessian_out[12]),
.R(1'b0));
FDRE \hessian_out_reg[13]
(.C(clk_x16),
.CE(y3),
.D(det_abs[13]),
.Q(hessian_out[13]),
.R(1'b0));
FDRE \hessian_out_reg[14]
(.C(clk_x16),
.CE(y3),
.D(det_abs[14]),
.Q(hessian_out[14]),
.R(1'b0));
FDRE \hessian_out_reg[15]
(.C(clk_x16),
.CE(y3),
.D(det_abs[15]),
.Q(hessian_out[15]),
.R(1'b0));
FDRE \hessian_out_reg[16]
(.C(clk_x16),
.CE(y3),
.D(det_abs[16]),
.Q(hessian_out[16]),
.R(1'b0));
FDRE \hessian_out_reg[17]
(.C(clk_x16),
.CE(y3),
.D(det_abs[17]),
.Q(hessian_out[17]),
.R(1'b0));
FDRE \hessian_out_reg[18]
(.C(clk_x16),
.CE(y3),
.D(det_abs[18]),
.Q(hessian_out[18]),
.R(1'b0));
FDRE \hessian_out_reg[19]
(.C(clk_x16),
.CE(y3),
.D(det_abs[19]),
.Q(hessian_out[19]),
.R(1'b0));
FDRE \hessian_out_reg[1]
(.C(clk_x16),
.CE(y3),
.D(det_abs[1]),
.Q(hessian_out[1]),
.R(1'b0));
FDRE \hessian_out_reg[20]
(.C(clk_x16),
.CE(y3),
.D(det_abs[20]),
.Q(hessian_out[20]),
.R(1'b0));
FDRE \hessian_out_reg[21]
(.C(clk_x16),
.CE(y3),
.D(det_abs[21]),
.Q(hessian_out[21]),
.R(1'b0));
FDRE \hessian_out_reg[22]
(.C(clk_x16),
.CE(y3),
.D(det_abs[22]),
.Q(hessian_out[22]),
.R(1'b0));
FDRE \hessian_out_reg[23]
(.C(clk_x16),
.CE(y3),
.D(det_abs[23]),
.Q(hessian_out[23]),
.R(1'b0));
FDRE \hessian_out_reg[24]
(.C(clk_x16),
.CE(y3),
.D(det_abs[24]),
.Q(hessian_out[24]),
.R(1'b0));
FDRE \hessian_out_reg[25]
(.C(clk_x16),
.CE(y3),
.D(det_abs[25]),
.Q(hessian_out[25]),
.R(1'b0));
FDRE \hessian_out_reg[26]
(.C(clk_x16),
.CE(y3),
.D(det_abs[26]),
.Q(hessian_out[26]),
.R(1'b0));
FDRE \hessian_out_reg[27]
(.C(clk_x16),
.CE(y3),
.D(det_abs[27]),
.Q(hessian_out[27]),
.R(1'b0));
FDRE \hessian_out_reg[28]
(.C(clk_x16),
.CE(y3),
.D(det_abs[28]),
.Q(hessian_out[28]),
.R(1'b0));
FDRE \hessian_out_reg[29]
(.C(clk_x16),
.CE(y3),
.D(det_abs[29]),
.Q(hessian_out[29]),
.R(1'b0));
FDRE \hessian_out_reg[2]
(.C(clk_x16),
.CE(y3),
.D(det_abs[2]),
.Q(hessian_out[2]),
.R(1'b0));
FDRE \hessian_out_reg[30]
(.C(clk_x16),
.CE(y3),
.D(det_abs[30]),
.Q(hessian_out[30]),
.R(1'b0));
FDRE \hessian_out_reg[31]
(.C(clk_x16),
.CE(y3),
.D(det_abs[31]),
.Q(hessian_out[31]),
.R(1'b0));
FDRE \hessian_out_reg[3]
(.C(clk_x16),
.CE(y3),
.D(det_abs[3]),
.Q(hessian_out[3]),
.R(1'b0));
FDRE \hessian_out_reg[4]
(.C(clk_x16),
.CE(y3),
.D(det_abs[4]),
.Q(hessian_out[4]),
.R(1'b0));
FDRE \hessian_out_reg[5]
(.C(clk_x16),
.CE(y3),
.D(det_abs[5]),
.Q(hessian_out[5]),
.R(1'b0));
FDRE \hessian_out_reg[6]
(.C(clk_x16),
.CE(y3),
.D(det_abs[6]),
.Q(hessian_out[6]),
.R(1'b0));
FDRE \hessian_out_reg[7]
(.C(clk_x16),
.CE(y3),
.D(det_abs[7]),
.Q(hessian_out[7]),
.R(1'b0));
FDRE \hessian_out_reg[8]
(.C(clk_x16),
.CE(y3),
.D(det_abs[8]),
.Q(hessian_out[8]),
.R(1'b0));
FDRE \hessian_out_reg[9]
(.C(clk_x16),
.CE(y3),
.D(det_abs[9]),
.Q(hessian_out[9]),
.R(1'b0));
LUT4 #(
.INIT(16'h0400))
i__carry__0_i_1
(.I0(\cycle_reg[1]_rep__0_n_0 ),
.I1(cycle[0]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[3]),
.O(i__carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h9))
i__carry__0_i_2
(.I0(\x_reg_n_0_[6] ),
.I1(\x_reg_n_0_[7] ),
.O(i__carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h9))
i__carry__0_i_3
(.I0(\x_reg_n_0_[5] ),
.I1(\x_reg_n_0_[6] ),
.O(i__carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h9))
i__carry__0_i_4
(.I0(\x_reg_n_0_[4] ),
.I1(\x_reg_n_0_[5] ),
.O(i__carry__0_i_4_n_0));
LUT5 #(
.INIT(32'h0020FFDF))
i__carry__0_i_5
(.I0(cycle[3]),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\x_reg_n_0_[4] ),
.O(i__carry__0_i_5_n_0));
LUT2 #(
.INIT(4'h9))
i__carry__1_i_1
(.I0(\x_reg_n_0_[8] ),
.I1(\x_reg_n_0_[9] ),
.O(i__carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h9))
i__carry__1_i_2
(.I0(\x_reg_n_0_[7] ),
.I1(\x_reg_n_0_[8] ),
.O(i__carry__1_i_2_n_0));
LUT5 #(
.INIT(32'h0020FFDF))
i__carry_i_1
(.I0(cycle[3]),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\x_reg_n_0_[3] ),
.O(i__carry_i_1_n_0));
LUT4 #(
.INIT(16'hAA6A))
i__carry_i_2
(.I0(\x_reg_n_0_[2] ),
.I1(cycle[3]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(\cycle_reg[2]_rep_n_0 ),
.O(i__carry_i_2_n_0));
LUT5 #(
.INIT(32'h55599555))
i__carry_i_3
(.I0(\x_reg_n_0_[1] ),
.I1(cycle[3]),
.I2(cycle[0]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\cycle_reg[2]_rep_n_0 ),
.O(i__carry_i_3_n_0));
LUT4 #(
.INIT(16'h5595))
i__carry_i_4
(.I0(\x_reg_n_0_[0] ),
.I1(cycle[3]),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.O(i__carry_i_4_n_0));
FDRE #(
.INIT(1'b0))
\last_value_reg[0]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[0] ),
.Q(last_value[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[1]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[1] ),
.Q(last_value[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[2]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[2] ),
.Q(last_value[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[3]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[3] ),
.Q(last_value[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[4]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[4] ),
.Q(last_value[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[5]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[5] ),
.Q(last_value[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[6]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[6] ),
.Q(last_value[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[7]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[7] ),
.Q(last_value[7]),
.R(1'b0));
LUT5 #(
.INIT(32'h00000008))
\left[15]_i_1
(.I0(\left[15]_i_2_n_0 ),
.I1(x),
.I2(\x_reg_n_0_[0] ),
.I3(\x_reg_n_0_[9] ),
.I4(\x_reg_n_0_[8] ),
.O(left));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h0001))
\left[15]_i_2
(.I0(\x_reg_n_0_[7] ),
.I1(\x_reg_n_0_[5] ),
.I2(\x_reg_n_0_[6] ),
.I3(\left[15]_i_3_n_0 ),
.O(\left[15]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hFFFE))
\left[15]_i_3
(.I0(\x_reg_n_0_[4] ),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[2] ),
.I3(\x_reg_n_0_[3] ),
.O(\left[15]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\left_reg[0]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [0]),
.Q(\left_reg_n_0_[0] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[10]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [10]),
.Q(\left_reg_n_0_[10] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[11]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [11]),
.Q(\left_reg_n_0_[11] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[12]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [12]),
.Q(\left_reg_n_0_[12] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[13]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [13]),
.Q(\left_reg_n_0_[13] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[14]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [14]),
.Q(\left_reg_n_0_[14] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[15]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [15]),
.Q(\left_reg_n_0_[15] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[1]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [1]),
.Q(\left_reg_n_0_[1] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[2]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [2]),
.Q(\left_reg_n_0_[2] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[3]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [3]),
.Q(\left_reg_n_0_[3] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[4]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [4]),
.Q(\left_reg_n_0_[4] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[5]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [5]),
.Q(\left_reg_n_0_[5] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[6]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [6]),
.Q(\left_reg_n_0_[6] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[7]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [7]),
.Q(\left_reg_n_0_[7] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[8]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [8]),
.Q(\left_reg_n_0_[8] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[9]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [9]),
.Q(\left_reg_n_0_[9] ),
.R(left));
CARRY4 \plusOp_inferred__0/i__carry
(.CI(1'b0),
.CO({\plusOp_inferred__0/i__carry_n_0 ,\plusOp_inferred__0/i__carry_n_1 ,\plusOp_inferred__0/i__carry_n_2 ,\plusOp_inferred__0/i__carry_n_3 }),
.CYINIT(1'b0),
.DI({\x_reg_n_0_[3] ,\x_reg_n_0_[2] ,\x_reg_n_0_[1] ,\x_reg_n_0_[0] }),
.O({\plusOp_inferred__0/i__carry_n_4 ,\plusOp_inferred__0/i__carry_n_5 ,\plusOp_inferred__0/i__carry_n_6 ,\plusOp_inferred__0/i__carry_n_7 }),
.S({i__carry_i_1_n_0,i__carry_i_2_n_0,i__carry_i_3_n_0,i__carry_i_4_n_0}));
CARRY4 \plusOp_inferred__0/i__carry__0
(.CI(\plusOp_inferred__0/i__carry_n_0 ),
.CO({\plusOp_inferred__0/i__carry__0_n_0 ,\plusOp_inferred__0/i__carry__0_n_1 ,\plusOp_inferred__0/i__carry__0_n_2 ,\plusOp_inferred__0/i__carry__0_n_3 }),
.CYINIT(1'b0),
.DI({\x_reg_n_0_[6] ,\x_reg_n_0_[5] ,\x_reg_n_0_[4] ,i__carry__0_i_1_n_0}),
.O({\plusOp_inferred__0/i__carry__0_n_4 ,\plusOp_inferred__0/i__carry__0_n_5 ,\plusOp_inferred__0/i__carry__0_n_6 ,\plusOp_inferred__0/i__carry__0_n_7 }),
.S({i__carry__0_i_2_n_0,i__carry__0_i_3_n_0,i__carry__0_i_4_n_0,i__carry__0_i_5_n_0}));
CARRY4 \plusOp_inferred__0/i__carry__1
(.CI(\plusOp_inferred__0/i__carry__0_n_0 ),
.CO({\NLW_plusOp_inferred__0/i__carry__1_CO_UNCONNECTED [3:1],\plusOp_inferred__0/i__carry__1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\x_reg_n_0_[7] }),
.O({\NLW_plusOp_inferred__0/i__carry__1_O_UNCONNECTED [3:2],\plusOp_inferred__0/i__carry__1_n_6 ,\plusOp_inferred__0/i__carry__1_n_7 }),
.S({1'b0,1'b0,i__carry__1_i_1_n_0,i__carry__1_i_2_n_0}));
LUT6 #(
.INIT(64'h0000000000000002))
\top[15]_i_1
(.I0(x),
.I1(\top[15]_i_2_n_0 ),
.I2(\y_actual_reg_n_0_[3] ),
.I3(\y_actual_reg_n_0_[0] ),
.I4(\y_actual_reg_n_0_[1] ),
.I5(\y_actual_reg_n_0_[2] ),
.O(top));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\top[15]_i_2
(.I0(\y_actual_reg_n_0_[8] ),
.I1(\y_actual_reg_n_0_[9] ),
.I2(\y_actual_reg_n_0_[6] ),
.I3(\y_actual_reg_n_0_[7] ),
.I4(\y_actual_reg_n_0_[4] ),
.I5(\y_actual_reg_n_0_[5] ),
.O(\top[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[0]_i_1
(.I0(dout_0[0]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[0]),
.O(\top_left_0[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[10]_i_1
(.I0(dout_0[10]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[10]),
.O(\top_left_0[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[11]_i_1
(.I0(dout_0[11]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[11]),
.O(\top_left_0[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[12]_i_1
(.I0(dout_0[12]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[12]),
.O(\top_left_0[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[13]_i_1
(.I0(dout_0[13]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[13]),
.O(\top_left_0[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[14]_i_1
(.I0(dout_0[14]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[14]),
.O(\top_left_0[14]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000700010000000))
\top_left_0[15]_i_1
(.I0(cycle[2]),
.I1(cycle[3]),
.I2(rst),
.I3(active),
.I4(\cycle_reg[0]_rep_n_0 ),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(top_left_0));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[15]_i_2
(.I0(dout_0[15]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[15]),
.O(\top_left_0[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[1]_i_1
(.I0(dout_0[1]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[1]),
.O(\top_left_0[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[2]_i_1
(.I0(dout_0[2]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[2]),
.O(\top_left_0[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[3]_i_1
(.I0(dout_0[3]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[3]),
.O(\top_left_0[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[4]_i_1
(.I0(dout_0[4]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[4]),
.O(\top_left_0[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[5]_i_1
(.I0(dout_0[5]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[5]),
.O(\top_left_0[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[6]_i_1
(.I0(dout_0[6]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[6]),
.O(\top_left_0[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[7]_i_1
(.I0(dout_0[7]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[7]),
.O(\top_left_0[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[8]_i_1
(.I0(dout_0[8]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[8]),
.O(\top_left_0[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[9]_i_1
(.I0(dout_0[9]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[9]),
.O(\top_left_0[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[0]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[0]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[10]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[10]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[11]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[11]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[12]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[12]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[13]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[13]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[14]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[14]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[15]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[15]_i_2_n_0 ),
.Q(\top_left_0_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[1]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[1]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[2]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[2]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[3]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[3]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[4]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[4]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[5]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[5]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[6]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[6]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[7]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[7]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[8]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[8]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[9]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[9]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[0]_i_1
(.I0(dout_1[0]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[0] ),
.O(\top_left_1[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[10]_i_1
(.I0(dout_1[10]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[10] ),
.O(\top_left_1[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[11]_i_1
(.I0(dout_1[11]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[11] ),
.O(\top_left_1[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[12]_i_1
(.I0(dout_1[12]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\bottom_left_0_reg_n_0_[12] ),
.O(\top_left_1[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[13]_i_1
(.I0(dout_1[13]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\bottom_left_0_reg_n_0_[13] ),
.O(\top_left_1[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[14]_i_1
(.I0(dout_1[14]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\bottom_left_0_reg_n_0_[14] ),
.O(\top_left_1[14]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0040))
\top_left_1[15]_i_1
(.I0(\cycle_reg[0]_rep_n_0 ),
.I1(active),
.I2(rst),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.O(bottom_right_1));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[15]_i_2
(.I0(dout_1[15]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\bottom_left_0_reg_n_0_[15] ),
.O(\top_left_1[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[1]_i_1
(.I0(dout_1[1]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[1] ),
.O(\top_left_1[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[2]_i_1
(.I0(dout_1[2]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[2] ),
.O(\top_left_1[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[3]_i_1
(.I0(dout_1[3]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[3] ),
.O(\top_left_1[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[4]_i_1
(.I0(dout_1[4]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[4] ),
.O(\top_left_1[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[5]_i_1
(.I0(dout_1[5]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[5] ),
.O(\top_left_1[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[6]_i_1
(.I0(dout_1[6]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[6] ),
.O(\top_left_1[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[7]_i_1
(.I0(dout_1[7]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[7] ),
.O(\top_left_1[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[8]_i_1
(.I0(dout_1[8]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[8] ),
.O(\top_left_1[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[9]_i_1
(.I0(dout_1[9]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[9] ),
.O(\top_left_1[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[0]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[0]_i_1_n_0 ),
.Q(top_left_1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[10]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[10]_i_1_n_0 ),
.Q(top_left_1[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[11]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[11]_i_1_n_0 ),
.Q(top_left_1[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[12]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[12]_i_1_n_0 ),
.Q(top_left_1[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[13]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[13]_i_1_n_0 ),
.Q(top_left_1[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[14]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[14]_i_1_n_0 ),
.Q(top_left_1[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[15]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[15]_i_2_n_0 ),
.Q(top_left_1[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[1]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[1]_i_1_n_0 ),
.Q(top_left_1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[2]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[2]_i_1_n_0 ),
.Q(top_left_1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[3]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[3]_i_1_n_0 ),
.Q(top_left_1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[4]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[4]_i_1_n_0 ),
.Q(top_left_1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[5]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[5]_i_1_n_0 ),
.Q(top_left_1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[6]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[6]_i_1_n_0 ),
.Q(top_left_1[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[7]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[7]_i_1_n_0 ),
.Q(top_left_1[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[8]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[8]_i_1_n_0 ),
.Q(top_left_1[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[9]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[9]_i_1_n_0 ),
.Q(top_left_1[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_reg[0]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [0]),
.Q(\top_reg_n_0_[0] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[10]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [10]),
.Q(\top_reg_n_0_[10] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[11]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [11]),
.Q(\top_reg_n_0_[11] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[12]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [12]),
.Q(\top_reg_n_0_[12] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[13]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [13]),
.Q(\top_reg_n_0_[13] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[14]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [14]),
.Q(\top_reg_n_0_[14] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[15]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [15]),
.Q(\top_reg_n_0_[15] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[1]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [1]),
.Q(\top_reg_n_0_[1] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[2]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [2]),
.Q(\top_reg_n_0_[2] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[3]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [3]),
.Q(\top_reg_n_0_[3] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[4]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [4]),
.Q(\top_reg_n_0_[4] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[5]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [5]),
.Q(\top_reg_n_0_[5] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[6]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [6]),
.Q(\top_reg_n_0_[6] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[7]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [7]),
.Q(\top_reg_n_0_[7] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[8]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [8]),
.Q(\top_reg_n_0_[8] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[9]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [9]),
.Q(\top_reg_n_0_[9] ),
.R(top));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[0]_i_1
(.I0(top_left_1[0]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[0]),
.O(\top_right_0[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[10]_i_1
(.I0(top_left_1[10]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[10]),
.O(\top_right_0[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[11]_i_1
(.I0(top_left_1[11]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[11]),
.O(\top_right_0[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[12]_i_1
(.I0(top_left_1[12]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[12]),
.O(\top_right_0[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[13]_i_1
(.I0(top_left_1[13]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[13]),
.O(\top_right_0[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[14]_i_1
(.I0(top_left_1[14]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[14]),
.O(\top_right_0[14]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0880000080080800))
\top_right_0[15]_i_1
(.I0(rst),
.I1(active),
.I2(cycle[3]),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\cycle_reg[2]_rep_n_0 ),
.O(top_right_0));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[15]_i_2
(.I0(top_left_1[15]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[15]),
.O(\top_right_0[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[1]_i_1
(.I0(top_left_1[1]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[1]),
.O(\top_right_0[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[2]_i_1
(.I0(top_left_1[2]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[2]),
.O(\top_right_0[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[3]_i_1
(.I0(top_left_1[3]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[3]),
.O(\top_right_0[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[4]_i_1
(.I0(top_left_1[4]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[4]),
.O(\top_right_0[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[5]_i_1
(.I0(top_left_1[5]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[5]),
.O(\top_right_0[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[6]_i_1
(.I0(top_left_1[6]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[6]),
.O(\top_right_0[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[7]_i_1
(.I0(top_left_1[7]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[7]),
.O(\top_right_0[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[8]_i_1
(.I0(top_left_1[8]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[8]),
.O(\top_right_0[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[9]_i_1
(.I0(top_left_1[9]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[9]),
.O(\top_right_0[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[0]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[0]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[10]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[10]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[11]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[11]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[12]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[12]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[13]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[13]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[14]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[14]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[15]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[15]_i_2_n_0 ),
.Q(\top_right_0_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[1]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[1]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[2]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[2]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[3]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[3]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[4]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[4]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[5]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[5]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[6]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[6]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[7]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[7]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[8]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[8]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[9]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[9]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[0]_i_1
(.I0(dout_1[0]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[0] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[0] ),
.O(\top_right_1[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[10]_i_1
(.I0(dout_1[10]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[10] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[10] ),
.O(\top_right_1[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[11]_i_1
(.I0(dout_1[11]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[11] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[11] ),
.O(\top_right_1[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[12]_i_1
(.I0(dout_1[12]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[12] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[12] ),
.O(\top_right_1[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[13]_i_1
(.I0(dout_1[13]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[13] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[13] ),
.O(\top_right_1[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[14]_i_1
(.I0(dout_1[14]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[14] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[14] ),
.O(\top_right_1[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[15]_i_1
(.I0(dout_1[15]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[15] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[15] ),
.O(\top_right_1[15]_i_1_n_0 ));
LUT3 #(
.INIT(8'hFE))
\top_right_1[15]_i_2
(.I0(cycle[3]),
.I1(cycle[0]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.O(\top_right_1[15]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[1]_i_1
(.I0(dout_1[1]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[1] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[1] ),
.O(\top_right_1[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[2]_i_1
(.I0(dout_1[2]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[2] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[2] ),
.O(\top_right_1[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[3]_i_1
(.I0(dout_1[3]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[3] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[3] ),
.O(\top_right_1[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[4]_i_1
(.I0(dout_1[4]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[4] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[4] ),
.O(\top_right_1[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[5]_i_1
(.I0(dout_1[5]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[5] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[5] ),
.O(\top_right_1[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[6]_i_1
(.I0(dout_1[6]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[6] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[6] ),
.O(\top_right_1[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[7]_i_1
(.I0(dout_1[7]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[7] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[7] ),
.O(\top_right_1[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[8]_i_1
(.I0(dout_1[8]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[8] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[8] ),
.O(\top_right_1[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[9]_i_1
(.I0(dout_1[9]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[9] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[9] ),
.O(\top_right_1[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[0]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[0]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[10]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[10]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[11]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[11]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[12]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[12]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[13]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[13]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[14]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[14]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[15]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[15]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[1]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[1]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[2]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[2]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[3]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[3]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[4]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[4]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[5]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[5]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[6]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[6]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[7]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[7]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[8]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[8]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[9]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[9]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[9] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[0]
(.C(clk_x16),
.CE(x),
.D(g_in[0]),
.Q(\value_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[1]
(.C(clk_x16),
.CE(x),
.D(g_in[1]),
.Q(\value_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[2]
(.C(clk_x16),
.CE(x),
.D(g_in[2]),
.Q(\value_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[3]
(.C(clk_x16),
.CE(x),
.D(g_in[3]),
.Q(\value_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[4]
(.C(clk_x16),
.CE(x),
.D(g_in[4]),
.Q(\value_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[5]
(.C(clk_x16),
.CE(x),
.D(g_in[5]),
.Q(\value_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[6]
(.C(clk_x16),
.CE(x),
.D(g_in[6]),
.Q(\value_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[7]
(.C(clk_x16),
.CE(x),
.D(g_in[7]),
.Q(\value_reg_n_0_[7] ),
.R(1'b0));
LUT6 #(
.INIT(64'hAAAAEAAAAAA2AAAA))
wen_i_1
(.I0(wen_reg_n_0),
.I1(wen_i_2_n_0),
.I2(\cycle_reg[0]_rep_n_0 ),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[3]),
.I5(cycle[2]),
.O(wen_i_1_n_0));
LUT2 #(
.INIT(4'h8))
wen_i_2
(.I0(active),
.I1(rst),
.O(wen_i_2_n_0));
FDRE #(
.INIT(1'b0))
wen_reg
(.C(clk_x16),
.CE(1'b1),
.D(wen_i_1_n_0),
.Q(wen_reg_n_0),
.R(1'b0));
LUT6 #(
.INIT(64'h3B01FFC53A00FEC4))
\x0[0]_i_2
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(cycle[0]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(data2[0]),
.I4(\x_reg_n_0_[0] ),
.I5(\plusOp_inferred__0/i__carry_n_7 ),
.O(\x0[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFE0002))
\x0[0]_i_3
(.I0(data2[0]),
.I1(cycle[0]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\plusOp_inferred__0/i__carry_n_7 ),
.O(\x0[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'hCCEECCEEEEEECCFC))
\x0[1]_i_2
(.I0(data2[1]),
.I1(\x0[1]_i_4_n_0 ),
.I2(\plusOp_inferred__0/i__carry_n_6 ),
.I3(cycle[0]),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(\x0[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFE0002))
\x0[1]_i_3
(.I0(data2[1]),
.I1(cycle[0]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\plusOp_inferred__0/i__carry_n_6 ),
.O(\x0[1]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h60600060))
\x0[1]_i_4
(.I0(\x_reg_n_0_[1] ),
.I1(\x_reg_n_0_[0] ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.O(\x0[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFBBBFBBBFFBBBBBB))
\x0[2]_i_1
(.I0(\x0[2]_i_2_n_0 ),
.I1(\x0[2]_i_3_n_0 ),
.I2(data2[2]),
.I3(cycle[3]),
.I4(\plusOp_inferred__0/i__carry_n_5 ),
.I5(\x1[5]_i_3_n_0 ),
.O(\x0[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h88AA22A0880022A0))
\x0[2]_i_2
(.I0(\x0[7]_i_4_n_0 ),
.I1(\x0[2]_i_4_n_0 ),
.I2(\plusOp_inferred__0/i__carry_n_5 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data2[2]),
.O(\x0[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h3FF3F3F377777777))
\x0[2]_i_3
(.I0(data2[2]),
.I1(\x0[2]_i_5_n_0 ),
.I2(\x_reg_n_0_[2] ),
.I3(\x_reg_n_0_[1] ),
.I4(\x_reg_n_0_[0] ),
.I5(\x1[6]_i_8_n_0 ),
.O(\x0[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'h6A))
\x0[2]_i_4
(.I0(\x_reg_n_0_[2] ),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[0] ),
.O(\x0[2]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h2))
\x0[2]_i_5
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(cycle[3]),
.O(\x0[2]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFF100F1))
\x0[3]_i_1
(.I0(\x0[3]_i_2_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(\x0[3]_i_3_n_0 ),
.I3(cycle[3]),
.I4(\x0[3]_i_4_n_0 ),
.O(\x0[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h660FFF00660FFFFF))
\x0[3]_i_2
(.I0(\x_reg_n_0_[3] ),
.I1(\x0[3]_i_5_n_0 ),
.I2(data2[3]),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\plusOp_inferred__0/i__carry_n_4 ),
.O(\x0[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h90F0F9F090000900))
\x0[3]_i_3
(.I0(\x_reg_n_0_[3] ),
.I1(\x0[3]_i_6_n_0 ),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data2[3]),
.O(\x0[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'hFFFE0002))
\x0[3]_i_4
(.I0(data2[3]),
.I1(cycle[0]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\plusOp_inferred__0/i__carry_n_4 ),
.O(\x0[3]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'h7F))
\x0[3]_i_5
(.I0(\x_reg_n_0_[2] ),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[0] ),
.O(\x0[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hEA))
\x0[3]_i_6
(.I0(\x_reg_n_0_[2] ),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[0] ),
.O(\x0[3]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFCDDFCDDFFDDCCDD))
\x0[4]_i_1
(.I0(\x0[4]_i_2_n_0 ),
.I1(\x0[4]_i_3_n_0 ),
.I2(data2[4]),
.I3(cycle[3]),
.I4(\plusOp_inferred__0/i__carry__0_n_7 ),
.I5(\x1[5]_i_3_n_0 ),
.O(\x0[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3C555555FFFF3CFF))
\x0[4]_i_2
(.I0(data2[4]),
.I1(\x_reg_n_0_[4] ),
.I2(\x0[4]_i_4_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\cycle_reg[2]_rep_n_0 ),
.O(\x0[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h008A0080A08AA080))
\x0[4]_i_3
(.I0(\x0[7]_i_4_n_0 ),
.I1(data2[4]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(cycle[0]),
.I4(\plusOp_inferred__0/i__carry__0_n_7 ),
.I5(\x0[4]_i_5_n_0 ),
.O(\x0[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hFFEA))
\x0[4]_i_4
(.I0(\x_reg_n_0_[3] ),
.I1(\x_reg_n_0_[0] ),
.I2(\x_reg_n_0_[1] ),
.I3(\x_reg_n_0_[2] ),
.O(\x0[4]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h95555555))
\x0[4]_i_5
(.I0(\x_reg_n_0_[4] ),
.I1(\x_reg_n_0_[3] ),
.I2(\x_reg_n_0_[2] ),
.I3(\x_reg_n_0_[1] ),
.I4(\x_reg_n_0_[0] ),
.O(\x0[4]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFCDDFCDDFFDDCCDD))
\x0[5]_i_1
(.I0(\x0[5]_i_2_n_0 ),
.I1(\x0[5]_i_3_n_0 ),
.I2(data2[5]),
.I3(cycle[3]),
.I4(\plusOp_inferred__0/i__carry__0_n_6 ),
.I5(\x1[5]_i_3_n_0 ),
.O(\x0[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3C555555FFFF3CFF))
\x0[5]_i_2
(.I0(data2[5]),
.I1(\x_reg_n_0_[5] ),
.I2(\x0[8]_i_7_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\cycle_reg[2]_rep_n_0 ),
.O(\x0[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00A80008AAAAAAAA))
\x0[5]_i_3
(.I0(\x0[7]_i_4_n_0 ),
.I1(\plusOp_inferred__0/i__carry__0_n_6 ),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(cycle[0]),
.I4(data2[5]),
.I5(\x0[5]_i_4_n_0 ),
.O(\x0[5]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h2DFFFFFF))
\x0[5]_i_4
(.I0(\x_reg_n_0_[4] ),
.I1(\x0[5]_i_5_n_0 ),
.I2(\x_reg_n_0_[5] ),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[0]),
.O(\x0[5]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'h7FFF))
\x0[5]_i_5
(.I0(\x_reg_n_0_[0] ),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[2] ),
.I3(\x_reg_n_0_[3] ),
.O(\x0[5]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFFF0507))
\x0[6]_i_1
(.I0(\x0[6]_i_2_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(cycle[3]),
.I3(\x0[6]_i_3_n_0 ),
.I4(\x0[6]_i_4_n_0 ),
.O(\x0[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0707077077777777))
\x0[6]_i_2
(.I0(\x1[9]_i_7_n_0 ),
.I1(data2[6]),
.I2(\x_reg_n_0_[6] ),
.I3(\x0[8]_i_7_n_0 ),
.I4(\x_reg_n_0_[5] ),
.I5(\x0[8]_i_5_n_0 ),
.O(\x0[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6600FF0F66FFFF0F))
\x0[6]_i_3
(.I0(\x_reg_n_0_[6] ),
.I1(\x0[6]_i_5_n_0 ),
.I2(\plusOp_inferred__0/i__carry__0_n_5 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data2[6]),
.O(\x0[6]_i_3_n_0 ));
LUT6 #(
.INIT(64'hC0C0C0C0C0C0C088))
\x0[6]_i_4
(.I0(data2[6]),
.I1(cycle[3]),
.I2(\plusOp_inferred__0/i__carry__0_n_5 ),
.I3(cycle[0]),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(\x0[6]_i_4_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\x0[6]_i_5
(.I0(\x_reg_n_0_[4] ),
.I1(\x_reg_n_0_[0] ),
.I2(\x_reg_n_0_[1] ),
.I3(\x_reg_n_0_[2] ),
.I4(\x_reg_n_0_[3] ),
.I5(\x_reg_n_0_[5] ),
.O(\x0[6]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFF020000))
\x0[7]_i_1
(.I0(cycle[0]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(\x0[7]_i_2_n_0 ),
.I3(\x0[7]_i_3_n_0 ),
.I4(\x0[7]_i_4_n_0 ),
.I5(\x0[7]_i_5_n_0 ),
.O(\x0[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h5556))
\x0[7]_i_2
(.I0(\x_reg_n_0_[7] ),
.I1(\x0[8]_i_7_n_0 ),
.I2(\x_reg_n_0_[5] ),
.I3(\x_reg_n_0_[6] ),
.O(\x0[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h99F000FF99F00000))
\x0[7]_i_3
(.I0(\x_reg_n_0_[7] ),
.I1(\x0[7]_i_6_n_0 ),
.I2(data2[7]),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\plusOp_inferred__0/i__carry__0_n_4 ),
.O(\x0[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h1))
\x0[7]_i_4
(.I0(cycle[3]),
.I1(\cycle_reg[2]_rep_n_0 ),
.O(\x0[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFF0FEECCF000EECC))
\x0[7]_i_5
(.I0(\x1[9]_i_7_n_0 ),
.I1(\x0[7]_i_7_n_0 ),
.I2(\x1[5]_i_3_n_0 ),
.I3(data2[7]),
.I4(cycle[3]),
.I5(\plusOp_inferred__0/i__carry__0_n_4 ),
.O(\x0[7]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\x0[7]_i_6
(.I0(\x0[6]_i_5_n_0 ),
.I1(\x_reg_n_0_[6] ),
.O(\x0[7]_i_6_n_0 ));
LUT6 #(
.INIT(64'h8888888000000008))
\x0[7]_i_7
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(\x1[6]_i_8_n_0 ),
.I2(\x_reg_n_0_[6] ),
.I3(\x_reg_n_0_[5] ),
.I4(\x0[8]_i_7_n_0 ),
.I5(\x_reg_n_0_[7] ),
.O(\x0[7]_i_7_n_0 ));
LUT6 #(
.INIT(64'hF0F0F0F0FFF1F1F1))
\x0[8]_i_1
(.I0(\x0[8]_i_2_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(\x0[8]_i_3_n_0 ),
.I3(\x0[8]_i_4_n_0 ),
.I4(\x0[8]_i_5_n_0 ),
.I5(cycle[3]),
.O(\x0[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'h990FFF00990FFFFF))
\x0[8]_i_2
(.I0(\x_reg_n_0_[8] ),
.I1(\x0[8]_i_6_n_0 ),
.I2(data2[8]),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\plusOp_inferred__0/i__carry__1_n_7 ),
.O(\x0[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'h8888B888B888B8C0))
\x0[8]_i_3
(.I0(\plusOp_inferred__0/i__carry__1_n_7 ),
.I1(cycle[3]),
.I2(data2[8]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[0]),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(\x0[8]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hAAAAAAA9))
\x0[8]_i_4
(.I0(\x_reg_n_0_[8] ),
.I1(\x_reg_n_0_[6] ),
.I2(\x_reg_n_0_[5] ),
.I3(\x0[8]_i_7_n_0 ),
.I4(\x_reg_n_0_[7] ),
.O(\x0[8]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h82))
\x0[8]_i_5
(.I0(cycle[0]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(\cycle_reg[2]_rep_n_0 ),
.O(\x0[8]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h08))
\x0[8]_i_6
(.I0(\x_reg_n_0_[7] ),
.I1(\x_reg_n_0_[6] ),
.I2(\x0[6]_i_5_n_0 ),
.O(\x0[8]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'hFFFFFEEE))
\x0[8]_i_7
(.I0(\x_reg_n_0_[4] ),
.I1(\x_reg_n_0_[2] ),
.I2(\x_reg_n_0_[1] ),
.I3(\x_reg_n_0_[0] ),
.I4(\x_reg_n_0_[3] ),
.O(\x0[8]_i_7_n_0 ));
LUT6 #(
.INIT(64'h77FE000000000000))
\x0[9]_i_1
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(cycle[3]),
.I2(cycle[0]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(active),
.I5(rst),
.O(\x0[9]_i_1_n_0 ));
LUT5 #(
.INIT(32'h01FF0101))
\x0[9]_i_2
(.I0(\x0[9]_i_3_n_0 ),
.I1(cycle[3]),
.I2(cycle[2]),
.I3(\x0[9]_i_4_n_0 ),
.I4(\x0[9]_i_5_n_0 ),
.O(\x0[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAF03AFF3A003A0F3))
\x0[9]_i_3
(.I0(\x0[9]_i_6_n_0 ),
.I1(\plusOp_inferred__0/i__carry__1_n_6 ),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(data2[9]),
.I5(\x0[9]_i_7_n_0 ),
.O(\x0[9]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0C0C0C0C0C0C0C44))
\x0[9]_i_4
(.I0(data2[9]),
.I1(cycle[3]),
.I2(\plusOp_inferred__0/i__carry__1_n_6 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\x0[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF5CCC0000))
\x0[9]_i_5
(.I0(\x0[9]_i_7_n_0 ),
.I1(data2[9]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[2]),
.I5(cycle[3]),
.O(\x0[9]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h55559555))
\x0[9]_i_6
(.I0(\x_reg_n_0_[9] ),
.I1(\x_reg_n_0_[8] ),
.I2(\x_reg_n_0_[7] ),
.I3(\x_reg_n_0_[6] ),
.I4(\x0[6]_i_5_n_0 ),
.O(\x0[9]_i_6_n_0 ));
LUT6 #(
.INIT(64'h5555555555555556))
\x0[9]_i_7
(.I0(\x_reg_n_0_[9] ),
.I1(\x_reg_n_0_[8] ),
.I2(\x_reg_n_0_[7] ),
.I3(\x0[8]_i_7_n_0 ),
.I4(\x_reg_n_0_[5] ),
.I5(\x_reg_n_0_[6] ),
.O(\x0[9]_i_7_n_0 ));
FDRE \x0_reg[0]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0_reg[0]_i_1_n_0 ),
.Q(data1[0]),
.R(1'b0));
MUXF7 \x0_reg[0]_i_1
(.I0(\x0[0]_i_2_n_0 ),
.I1(\x0[0]_i_3_n_0 ),
.O(\x0_reg[0]_i_1_n_0 ),
.S(cycle[3]));
FDRE \x0_reg[1]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0_reg[1]_i_1_n_0 ),
.Q(data1[1]),
.R(1'b0));
MUXF7 \x0_reg[1]_i_1
(.I0(\x0[1]_i_2_n_0 ),
.I1(\x0[1]_i_3_n_0 ),
.O(\x0_reg[1]_i_1_n_0 ),
.S(cycle[3]));
FDRE \x0_reg[2]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[2]_i_1_n_0 ),
.Q(data1[2]),
.R(1'b0));
FDRE \x0_reg[3]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[3]_i_1_n_0 ),
.Q(data1[3]),
.R(1'b0));
FDRE \x0_reg[4]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[4]_i_1_n_0 ),
.Q(data1[4]),
.R(1'b0));
FDRE \x0_reg[5]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[5]_i_1_n_0 ),
.Q(data1[5]),
.R(1'b0));
FDRE \x0_reg[6]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[6]_i_1_n_0 ),
.Q(data1[6]),
.R(1'b0));
FDRE \x0_reg[7]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[7]_i_1_n_0 ),
.Q(data1[7]),
.R(1'b0));
FDRE \x0_reg[8]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[8]_i_1_n_0 ),
.Q(data1[8]),
.R(1'b0));
FDRE \x0_reg[9]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[9]_i_2_n_0 ),
.Q(data1[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hFF01FF4EFE00B100))
\x1[0]_i_1
(.I0(\cycle_reg[1]_rep__0_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(cycle[0]),
.I3(\x_reg_n_0_[0] ),
.I4(cycle[3]),
.I5(data1[0]),
.O(\x1[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFEFAAA955565010))
\x1[1]_i_1
(.I0(cycle[3]),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(data1[1]),
.I5(\x_reg_n_0_[1] ),
.O(\x1[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFEFEFEAEAEAEFEAE))
\x1[2]_i_1
(.I0(\x1[2]_i_2_n_0 ),
.I1(\x1[2]_i_3_n_0 ),
.I2(cycle[3]),
.I3(\x_reg_n_0_[2] ),
.I4(\x1[5]_i_3_n_0 ),
.I5(data1[2]),
.O(\x1[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8A2A288880202888))
\x1[2]_i_2
(.I0(\x0[7]_i_4_n_0 ),
.I1(\x_reg_n_0_[2] ),
.I2(cycle[0]),
.I3(\x_reg_n_0_[1] ),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[2]),
.O(\x1[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h3CAAAAAA00000000))
\x1[2]_i_3
(.I0(data1[2]),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[2] ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\cycle_reg[2]_rep_n_0 ),
.O(\x1[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFCDDFCDDFFDDCCDD))
\x1[3]_i_1
(.I0(\x1[3]_i_2_n_0 ),
.I1(\x1[3]_i_3_n_0 ),
.I2(data1[3]),
.I3(cycle[3]),
.I4(\x_reg_n_0_[3] ),
.I5(\x1[5]_i_3_n_0 ),
.O(\x1[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0770707077777777))
\x1[3]_i_2
(.I0(\x1[9]_i_7_n_0 ),
.I1(data1[3]),
.I2(\x_reg_n_0_[3] ),
.I3(\x_reg_n_0_[2] ),
.I4(\x_reg_n_0_[1] ),
.I5(\x0[8]_i_5_n_0 ),
.O(\x1[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hA08A0080008AA080))
\x1[3]_i_3
(.I0(\x0[7]_i_4_n_0 ),
.I1(data1[3]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(cycle[0]),
.I4(\x_reg_n_0_[3] ),
.I5(\x1[3]_i_4_n_0 ),
.O(\x1[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT2 #(
.INIT(4'hE))
\x1[3]_i_4
(.I0(\x_reg_n_0_[1] ),
.I1(\x_reg_n_0_[2] ),
.O(\x1[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFCDDFCDDFFDDCCDD))
\x1[4]_i_1
(.I0(\x1[4]_i_2_n_0 ),
.I1(\x1[4]_i_3_n_0 ),
.I2(data1[4]),
.I3(cycle[3]),
.I4(\x_reg_n_0_[4] ),
.I5(\x1[5]_i_3_n_0 ),
.O(\x1[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3C555555FFFF3CFF))
\x1[4]_i_2
(.I0(data1[4]),
.I1(\x_reg_n_0_[4] ),
.I2(\x1[4]_i_4_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\cycle_reg[2]_rep_n_0 ),
.O(\x1[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hA08A0080008AA080))
\x1[4]_i_3
(.I0(\x0[7]_i_4_n_0 ),
.I1(data1[4]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(cycle[0]),
.I4(\x_reg_n_0_[4] ),
.I5(\x1[4]_i_5_n_0 ),
.O(\x1[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hEA))
\x1[4]_i_4
(.I0(\x_reg_n_0_[3] ),
.I1(\x_reg_n_0_[2] ),
.I2(\x_reg_n_0_[1] ),
.O(\x1[4]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hFE))
\x1[4]_i_5
(.I0(\x_reg_n_0_[3] ),
.I1(\x_reg_n_0_[2] ),
.I2(\x_reg_n_0_[1] ),
.O(\x1[4]_i_5_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\x1[5]_i_1
(.I0(\x1[5]_i_2_n_0 ),
.I1(data1[5]),
.I2(\x1[5]_i_3_n_0 ),
.I3(\x_reg_n_0_[5] ),
.I4(cycle[3]),
.O(\x1[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCDFDCDCDFDFDFDCD))
\x1[5]_i_2
(.I0(\x1[5]_i_4_n_0 ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\x1[6]_i_8_n_0 ),
.I4(data1[5]),
.I5(\x1[5]_i_5_n_0 ),
.O(\x1[5]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h01))
\x1[5]_i_3
(.I0(\cycle_reg[1]_rep__0_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(cycle[0]),
.O(\x1[5]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0530FA3FF5300A3F))
\x1[5]_i_4
(.I0(\x1[6]_i_7_n_0 ),
.I1(data1[5]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(cycle[0]),
.I4(\x_reg_n_0_[5] ),
.I5(\left[15]_i_3_n_0 ),
.O(\x1[5]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h55555666))
\x1[5]_i_5
(.I0(\x_reg_n_0_[5] ),
.I1(\x_reg_n_0_[3] ),
.I2(\x_reg_n_0_[2] ),
.I3(\x_reg_n_0_[1] ),
.I4(\x_reg_n_0_[4] ),
.O(\x1[5]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hFFF100F1))
\x1[6]_i_1
(.I0(\x1[6]_i_2_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(\x1[6]_i_3_n_0 ),
.I3(cycle[3]),
.I4(\x1[6]_i_4_n_0 ),
.O(\x1[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFC05050CFC05F5F))
\x1[6]_i_2
(.I0(data1[6]),
.I1(\x1[6]_i_5_n_0 ),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(\x1[6]_i_6_n_0 ),
.I4(cycle[0]),
.I5(\x_reg_n_0_[6] ),
.O(\x1[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'hA900FF00A9000000))
\x1[6]_i_3
(.I0(\x_reg_n_0_[6] ),
.I1(\x1[6]_i_7_n_0 ),
.I2(\x_reg_n_0_[5] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\x1[6]_i_8_n_0 ),
.I5(data1[6]),
.O(\x1[6]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hFFFE0002))
\x1[6]_i_4
(.I0(data1[6]),
.I1(cycle[0]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\x_reg_n_0_[6] ),
.O(\x1[6]_i_4_n_0 ));
LUT6 #(
.INIT(64'h5555555555555556))
\x1[6]_i_5
(.I0(\x_reg_n_0_[6] ),
.I1(\x_reg_n_0_[4] ),
.I2(\x_reg_n_0_[1] ),
.I3(\x_reg_n_0_[2] ),
.I4(\x_reg_n_0_[3] ),
.I5(\x_reg_n_0_[5] ),
.O(\x1[6]_i_5_n_0 ));
LUT6 #(
.INIT(64'h5555555555555666))
\x1[6]_i_6
(.I0(\x_reg_n_0_[6] ),
.I1(\x_reg_n_0_[4] ),
.I2(\x_reg_n_0_[1] ),
.I3(\x_reg_n_0_[2] ),
.I4(\x_reg_n_0_[3] ),
.I5(\x_reg_n_0_[5] ),
.O(\x1[6]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'hFFEA))
\x1[6]_i_7
(.I0(\x_reg_n_0_[4] ),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[2] ),
.I3(\x_reg_n_0_[3] ),
.O(\x1[6]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\x1[6]_i_8
(.I0(\cycle_reg[1]_rep__0_n_0 ),
.I1(cycle[0]),
.O(\x1[6]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'hFFF100F1))
\x1[7]_i_1
(.I0(\x1[7]_i_2_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(\x1[7]_i_3_n_0 ),
.I3(cycle[3]),
.I4(\x1[7]_i_4_n_0 ),
.O(\x1[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h303F5050CFC05F5F))
\x1[7]_i_2
(.I0(data1[7]),
.I1(\x1[7]_i_5_n_0 ),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(\x1[9]_i_6_n_0 ),
.I4(cycle[0]),
.I5(\x_reg_n_0_[7] ),
.O(\x1[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h90F0F0F090000000))
\x1[7]_i_3
(.I0(\x_reg_n_0_[7] ),
.I1(\x1[9]_i_6_n_0 ),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[7]),
.O(\x1[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'hFFFE0002))
\x1[7]_i_4
(.I0(data1[7]),
.I1(cycle[0]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\x_reg_n_0_[7] ),
.O(\x1[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\x1[7]_i_5
(.I0(\x_reg_n_0_[3] ),
.I1(\x_reg_n_0_[2] ),
.I2(\x_reg_n_0_[1] ),
.I3(\x_reg_n_0_[4] ),
.I4(\x_reg_n_0_[6] ),
.I5(\x_reg_n_0_[5] ),
.O(\x1[7]_i_5_n_0 ));
LUT4 #(
.INIT(16'hFF01))
\x1[8]_i_1
(.I0(\x1[8]_i_2_n_0 ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\x1[8]_i_3_n_0 ),
.O(\x1[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFA300A3F0A30FA3F))
\x1[8]_i_2
(.I0(\x1[8]_i_4_n_0 ),
.I1(data1[8]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(cycle[0]),
.I4(\x_reg_n_0_[8] ),
.I5(\left[15]_i_2_n_0 ),
.O(\x1[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFF0FEECCF000EECC))
\x1[8]_i_3
(.I0(\x1[9]_i_7_n_0 ),
.I1(\x1[8]_i_5_n_0 ),
.I2(\x1[5]_i_3_n_0 ),
.I3(data1[8]),
.I4(cycle[3]),
.I5(\x_reg_n_0_[8] ),
.O(\x1[8]_i_3_n_0 ));
LUT5 #(
.INIT(32'h55555556))
\x1[8]_i_4
(.I0(\x_reg_n_0_[8] ),
.I1(\x_reg_n_0_[6] ),
.I2(\x_reg_n_0_[5] ),
.I3(\x1[6]_i_7_n_0 ),
.I4(\x_reg_n_0_[7] ),
.O(\x1[8]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAA800000002))
\x1[8]_i_5
(.I0(\x1[8]_i_6_n_0 ),
.I1(\x_reg_n_0_[7] ),
.I2(\x1[6]_i_7_n_0 ),
.I3(\x_reg_n_0_[5] ),
.I4(\x_reg_n_0_[6] ),
.I5(\x_reg_n_0_[8] ),
.O(\x1[8]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h80))
\x1[8]_i_6
(.I0(cycle[0]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(\cycle_reg[2]_rep_n_0 ),
.O(\x1[8]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0088008880880880))
\x1[9]_i_1
(.I0(active),
.I1(rst),
.I2(cycle[0]),
.I3(cycle[3]),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(x1));
LUT6 #(
.INIT(64'hFFFFFFFF00000047))
\x1[9]_i_2
(.I0(\x1[9]_i_3_n_0 ),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(\x1[9]_i_4_n_0 ),
.I3(cycle[3]),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\x1[9]_i_5_n_0 ),
.O(\x1[9]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h3C335555))
\x1[9]_i_3
(.I0(data1[9]),
.I1(\x_reg_n_0_[9] ),
.I2(\x_reg_n_0_[8] ),
.I3(\left[15]_i_2_n_0 ),
.I4(cycle[0]),
.O(\x1[9]_i_3_n_0 ));
LUT5 #(
.INIT(32'h0100FEFF))
\x1[9]_i_4
(.I0(\x_reg_n_0_[8] ),
.I1(\x_reg_n_0_[7] ),
.I2(\x1[9]_i_6_n_0 ),
.I3(cycle[0]),
.I4(\x_reg_n_0_[9] ),
.O(\x1[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFF0FEECCF000EECC))
\x1[9]_i_5
(.I0(\x1[9]_i_7_n_0 ),
.I1(\x1[9]_i_8_n_0 ),
.I2(\x1[5]_i_3_n_0 ),
.I3(data1[9]),
.I4(cycle[3]),
.I5(\x_reg_n_0_[9] ),
.O(\x1[9]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFEFEFE))
\x1[9]_i_6
(.I0(\x_reg_n_0_[6] ),
.I1(\x_reg_n_0_[5] ),
.I2(\x_reg_n_0_[3] ),
.I3(\x_reg_n_0_[2] ),
.I4(\x_reg_n_0_[1] ),
.I5(\x_reg_n_0_[4] ),
.O(\x1[9]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h2A))
\x1[9]_i_7
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(cycle[0]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.O(\x1[9]_i_7_n_0 ));
LUT6 #(
.INIT(64'h8888888000000008))
\x1[9]_i_8
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(\x1[6]_i_8_n_0 ),
.I2(\x1[9]_i_6_n_0 ),
.I3(\x_reg_n_0_[7] ),
.I4(\x_reg_n_0_[8] ),
.I5(\x_reg_n_0_[9] ),
.O(\x1[9]_i_8_n_0 ));
FDRE \x1_reg[0]
(.C(clk_x16),
.CE(x1),
.D(\x1[0]_i_1_n_0 ),
.Q(data2[0]),
.R(1'b0));
FDRE \x1_reg[1]
(.C(clk_x16),
.CE(x1),
.D(\x1[1]_i_1_n_0 ),
.Q(data2[1]),
.R(1'b0));
FDRE \x1_reg[2]
(.C(clk_x16),
.CE(x1),
.D(\x1[2]_i_1_n_0 ),
.Q(data2[2]),
.R(1'b0));
FDRE \x1_reg[3]
(.C(clk_x16),
.CE(x1),
.D(\x1[3]_i_1_n_0 ),
.Q(data2[3]),
.R(1'b0));
FDRE \x1_reg[4]
(.C(clk_x16),
.CE(x1),
.D(\x1[4]_i_1_n_0 ),
.Q(data2[4]),
.R(1'b0));
FDRE \x1_reg[5]
(.C(clk_x16),
.CE(x1),
.D(\x1[5]_i_1_n_0 ),
.Q(data2[5]),
.R(1'b0));
FDRE \x1_reg[6]
(.C(clk_x16),
.CE(x1),
.D(\x1[6]_i_1_n_0 ),
.Q(data2[6]),
.R(1'b0));
FDRE \x1_reg[7]
(.C(clk_x16),
.CE(x1),
.D(\x1[7]_i_1_n_0 ),
.Q(data2[7]),
.R(1'b0));
FDRE \x1_reg[8]
(.C(clk_x16),
.CE(x1),
.D(\x1[8]_i_1_n_0 ),
.Q(data2[8]),
.R(1'b0));
FDRE \x1_reg[9]
(.C(clk_x16),
.CE(x1),
.D(\x1[9]_i_2_n_0 ),
.Q(data2[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000040))
\x[9]_i_1
(.I0(cycle[0]),
.I1(active),
.I2(rst),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[3]),
.I5(cycle[2]),
.O(x));
FDRE \x_reg[0]
(.C(clk_x16),
.CE(x),
.D(x_addr[0]),
.Q(\x_reg_n_0_[0] ),
.R(1'b0));
FDRE \x_reg[1]
(.C(clk_x16),
.CE(x),
.D(x_addr[1]),
.Q(\x_reg_n_0_[1] ),
.R(1'b0));
FDRE \x_reg[2]
(.C(clk_x16),
.CE(x),
.D(x_addr[2]),
.Q(\x_reg_n_0_[2] ),
.R(1'b0));
FDRE \x_reg[3]
(.C(clk_x16),
.CE(x),
.D(x_addr[3]),
.Q(\x_reg_n_0_[3] ),
.R(1'b0));
FDRE \x_reg[4]
(.C(clk_x16),
.CE(x),
.D(x_addr[4]),
.Q(\x_reg_n_0_[4] ),
.R(1'b0));
FDRE \x_reg[5]
(.C(clk_x16),
.CE(x),
.D(x_addr[5]),
.Q(\x_reg_n_0_[5] ),
.R(1'b0));
FDRE \x_reg[6]
(.C(clk_x16),
.CE(x),
.D(x_addr[6]),
.Q(\x_reg_n_0_[6] ),
.R(1'b0));
FDRE \x_reg[7]
(.C(clk_x16),
.CE(x),
.D(x_addr[7]),
.Q(\x_reg_n_0_[7] ),
.R(1'b0));
FDRE \x_reg[8]
(.C(clk_x16),
.CE(x),
.D(x_addr[8]),
.Q(\x_reg_n_0_[8] ),
.R(1'b0));
FDRE \x_reg[9]
(.C(clk_x16),
.CE(x),
.D(x_addr[9]),
.Q(\x_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hE1))
\y1[2]_i_1
(.I0(\y_actual_reg_n_0_[0] ),
.I1(\y_actual_reg_n_0_[1] ),
.I2(\y_actual_reg_n_0_[2] ),
.O(\y1[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'hFE01))
\y1[3]_i_1
(.I0(\y_actual_reg_n_0_[2] ),
.I1(\y_actual_reg_n_0_[1] ),
.I2(\y_actual_reg_n_0_[0] ),
.I3(\y_actual_reg_n_0_[3] ),
.O(\y1[3]_i_1_n_0 ));
FDRE \y1_reg[0]
(.C(clk_x16),
.CE(y1),
.D(\y5[0]_i_1_n_0 ),
.Q(\y1_reg_n_0_[0] ),
.R(1'b0));
FDRE \y1_reg[1]
(.C(clk_x16),
.CE(y1),
.D(\y5[1]_i_1_n_0 ),
.Q(\y1_reg_n_0_[1] ),
.R(1'b0));
FDRE \y1_reg[2]
(.C(clk_x16),
.CE(y1),
.D(\y1[2]_i_1_n_0 ),
.Q(\y1_reg_n_0_[2] ),
.R(1'b0));
FDRE \y1_reg[3]
(.C(clk_x16),
.CE(y1),
.D(\y1[3]_i_1_n_0 ),
.Q(\y1_reg_n_0_[3] ),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\y2[1]_i_1
(.I0(\y_actual_reg_n_0_[1] ),
.O(\y2[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h9))
\y2[2]_i_1
(.I0(\y_actual_reg_n_0_[2] ),
.I1(\y_actual_reg_n_0_[1] ),
.O(\y2[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hA9))
\y2[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[2] ),
.I2(\y_actual_reg_n_0_[1] ),
.O(\y2[3]_i_1_n_0 ));
FDRE \y2_reg[0]
(.C(clk_x16),
.CE(y2),
.D(\y_actual_reg_n_0_[0] ),
.Q(\y2_reg_n_0_[0] ),
.R(1'b0));
FDRE \y2_reg[1]
(.C(clk_x16),
.CE(y2),
.D(\y2[1]_i_1_n_0 ),
.Q(\y2_reg_n_0_[1] ),
.R(1'b0));
FDRE \y2_reg[2]
(.C(clk_x16),
.CE(y2),
.D(\y2[2]_i_1_n_0 ),
.Q(\y2_reg_n_0_[2] ),
.R(1'b0));
FDRE \y2_reg[3]
(.C(clk_x16),
.CE(y2),
.D(\y2[3]_i_1_n_0 ),
.Q(\y2_reg_n_0_[3] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT2 #(
.INIT(4'h6))
\y3[1]_i_1
(.I0(\y_actual_reg_n_0_[0] ),
.I1(\y_actual_reg_n_0_[1] ),
.O(\y3[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'h87))
\y3[2]_i_1
(.I0(\y_actual_reg_n_0_[0] ),
.I1(\y_actual_reg_n_0_[1] ),
.I2(\y_actual_reg_n_0_[2] ),
.O(\y3[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'hAA95))
\y3[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[0] ),
.I2(\y_actual_reg_n_0_[1] ),
.I3(\y_actual_reg_n_0_[2] ),
.O(\y3[3]_i_1_n_0 ));
FDRE \y3_reg[0]
(.C(clk_x16),
.CE(y3),
.D(\y5[0]_i_1_n_0 ),
.Q(\y3_reg_n_0_[0] ),
.R(1'b0));
FDRE \y3_reg[1]
(.C(clk_x16),
.CE(y3),
.D(\y3[1]_i_1_n_0 ),
.Q(\y3_reg_n_0_[1] ),
.R(1'b0));
FDRE \y3_reg[2]
(.C(clk_x16),
.CE(y3),
.D(\y3[2]_i_1_n_0 ),
.Q(\y3_reg_n_0_[2] ),
.R(1'b0));
FDRE \y3_reg[3]
(.C(clk_x16),
.CE(y3),
.D(\y3[3]_i_1_n_0 ),
.Q(\y3_reg_n_0_[3] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT1 #(
.INIT(2'h1))
\y4[2]_i_1
(.I0(\y_actual_reg_n_0_[2] ),
.O(\y4[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT2 #(
.INIT(4'h9))
\y4[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[2] ),
.O(\y4[3]_i_1_n_0 ));
FDRE \y4_reg[0]
(.C(clk_x16),
.CE(y1),
.D(\y_actual_reg_n_0_[0] ),
.Q(data2[10]),
.R(1'b0));
FDRE \y4_reg[1]
(.C(clk_x16),
.CE(y1),
.D(\y_actual_reg_n_0_[1] ),
.Q(data2[11]),
.R(1'b0));
FDRE \y4_reg[2]
(.C(clk_x16),
.CE(y1),
.D(\y4[2]_i_1_n_0 ),
.Q(data2[12]),
.R(1'b0));
FDRE \y4_reg[3]
(.C(clk_x16),
.CE(y1),
.D(\y4[3]_i_1_n_0 ),
.Q(data2[13]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT1 #(
.INIT(2'h1))
\y5[0]_i_1
(.I0(\y_actual_reg_n_0_[0] ),
.O(\y5[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h9))
\y5[1]_i_1
(.I0(\y_actual_reg_n_0_[1] ),
.I1(\y_actual_reg_n_0_[0] ),
.O(\y5[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h56))
\y5[2]_i_1
(.I0(\y_actual_reg_n_0_[2] ),
.I1(\y_actual_reg_n_0_[1] ),
.I2(\y_actual_reg_n_0_[0] ),
.O(\y5[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'hA955))
\y5[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[0] ),
.I2(\y_actual_reg_n_0_[1] ),
.I3(\y_actual_reg_n_0_[2] ),
.O(\y5[3]_i_1_n_0 ));
FDRE \y5_reg[0]
(.C(clk_x16),
.CE(y5),
.D(\y5[0]_i_1_n_0 ),
.Q(data1[10]),
.R(1'b0));
FDRE \y5_reg[1]
(.C(clk_x16),
.CE(y5),
.D(\y5[1]_i_1_n_0 ),
.Q(data1[11]),
.R(1'b0));
FDRE \y5_reg[2]
(.C(clk_x16),
.CE(y5),
.D(\y5[2]_i_1_n_0 ),
.Q(data1[12]),
.R(1'b0));
FDRE \y5_reg[3]
(.C(clk_x16),
.CE(y5),
.D(\y5[3]_i_1_n_0 ),
.Q(data1[13]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT2 #(
.INIT(4'h6))
\y6[2]_i_1
(.I0(\y_actual_reg_n_0_[1] ),
.I1(\y_actual_reg_n_0_[2] ),
.O(\y6[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'h95))
\y6[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[2] ),
.I2(\y_actual_reg_n_0_[1] ),
.O(\y6[3]_i_1_n_0 ));
FDRE \y6_reg[0]
(.C(clk_x16),
.CE(y6),
.D(\y_actual_reg_n_0_[0] ),
.Q(\y6_reg_n_0_[0] ),
.R(1'b0));
FDRE \y6_reg[1]
(.C(clk_x16),
.CE(y6),
.D(\y2[1]_i_1_n_0 ),
.Q(\y6_reg_n_0_[1] ),
.R(1'b0));
FDRE \y6_reg[2]
(.C(clk_x16),
.CE(y6),
.D(\y6[2]_i_1_n_0 ),
.Q(\y6_reg_n_0_[2] ),
.R(1'b0));
FDRE \y6_reg[3]
(.C(clk_x16),
.CE(y6),
.D(\y6[3]_i_1_n_0 ),
.Q(\y6_reg_n_0_[3] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'h6A))
\y7[2]_i_1
(.I0(\y_actual_reg_n_0_[2] ),
.I1(\y_actual_reg_n_0_[1] ),
.I2(\y_actual_reg_n_0_[0] ),
.O(\y7[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h9555))
\y7[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[0] ),
.I2(\y_actual_reg_n_0_[1] ),
.I3(\y_actual_reg_n_0_[2] ),
.O(\y7[3]_i_1_n_0 ));
FDRE \y7_reg[0]
(.C(clk_x16),
.CE(y2),
.D(\y5[0]_i_1_n_0 ),
.Q(y7[0]),
.R(1'b0));
FDRE \y7_reg[1]
(.C(clk_x16),
.CE(y2),
.D(\y3[1]_i_1_n_0 ),
.Q(y7[1]),
.R(1'b0));
FDRE \y7_reg[2]
(.C(clk_x16),
.CE(y2),
.D(\y7[2]_i_1_n_0 ),
.Q(y7[2]),
.R(1'b0));
FDRE \y7_reg[3]
(.C(clk_x16),
.CE(y2),
.D(\y7[3]_i_1_n_0 ),
.Q(y7[3]),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\y8[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.O(\y8[3]_i_1_n_0 ));
FDRE \y8_reg[0]
(.C(clk_x16),
.CE(y5),
.D(\y_actual_reg_n_0_[0] ),
.Q(y8[0]),
.R(1'b0));
FDRE \y8_reg[1]
(.C(clk_x16),
.CE(y5),
.D(\y_actual_reg_n_0_[1] ),
.Q(y8[1]),
.R(1'b0));
FDRE \y8_reg[2]
(.C(clk_x16),
.CE(y5),
.D(\y_actual_reg_n_0_[2] ),
.Q(y8[2]),
.R(1'b0));
FDRE \y8_reg[3]
(.C(clk_x16),
.CE(y5),
.D(\y8[3]_i_1_n_0 ),
.Q(y8[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h5556))
\y9[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[0] ),
.I2(\y_actual_reg_n_0_[1] ),
.I3(\y_actual_reg_n_0_[2] ),
.O(\y9[3]_i_1_n_0 ));
FDRE \y9_reg[0]
(.C(clk_x16),
.CE(y9),
.D(\y5[0]_i_1_n_0 ),
.Q(data5[10]),
.R(1'b0));
FDRE \y9_reg[1]
(.C(clk_x16),
.CE(y9),
.D(\y5[1]_i_1_n_0 ),
.Q(data5[11]),
.R(1'b0));
FDRE \y9_reg[2]
(.C(clk_x16),
.CE(y9),
.D(\y1[2]_i_1_n_0 ),
.Q(data5[12]),
.R(1'b0));
FDRE \y9_reg[3]
(.C(clk_x16),
.CE(y9),
.D(\y9[3]_i_1_n_0 ),
.Q(data5[13]),
.R(1'b0));
FDRE \y_actual_reg[0]
(.C(clk_x16),
.CE(x),
.D(y_addr[0]),
.Q(\y_actual_reg_n_0_[0] ),
.R(1'b0));
FDRE \y_actual_reg[1]
(.C(clk_x16),
.CE(x),
.D(y_addr[1]),
.Q(\y_actual_reg_n_0_[1] ),
.R(1'b0));
FDRE \y_actual_reg[2]
(.C(clk_x16),
.CE(x),
.D(y_addr[2]),
.Q(\y_actual_reg_n_0_[2] ),
.R(1'b0));
FDRE \y_actual_reg[3]
(.C(clk_x16),
.CE(x),
.D(y_addr[3]),
.Q(\y_actual_reg_n_0_[3] ),
.R(1'b0));
FDRE \y_actual_reg[4]
(.C(clk_x16),
.CE(x),
.D(y_addr[4]),
.Q(\y_actual_reg_n_0_[4] ),
.R(1'b0));
FDRE \y_actual_reg[5]
(.C(clk_x16),
.CE(x),
.D(y_addr[5]),
.Q(\y_actual_reg_n_0_[5] ),
.R(1'b0));
FDRE \y_actual_reg[6]
(.C(clk_x16),
.CE(x),
.D(y_addr[6]),
.Q(\y_actual_reg_n_0_[6] ),
.R(1'b0));
FDRE \y_actual_reg[7]
(.C(clk_x16),
.CE(x),
.D(y_addr[7]),
.Q(\y_actual_reg_n_0_[7] ),
.R(1'b0));
FDRE \y_actual_reg[8]
(.C(clk_x16),
.CE(x),
.D(y_addr[8]),
.Q(\y_actual_reg_n_0_[8] ),
.R(1'b0));
FDRE \y_actual_reg[9]
(.C(clk_x16),
.CE(x),
.D(y_addr[9]),
.Q(\y_actual_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "bindec" *)
module system_vga_hessian_0_0_bindec
(ena_array,
ena,
addra);
output [2:0]ena_array;
input ena;
input [1:0]addra;
wire [1:0]addra;
wire ena;
wire [2:0]ena_array;
LUT3 #(
.INIT(8'h02))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1
(.I0(ena),
.I1(addra[0]),
.I2(addra[1]),
.O(ena_array[0]));
LUT3 #(
.INIT(8'h40))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0
(.I0(addra[1]),
.I1(addra[0]),
.I2(ena),
.O(ena_array[1]));
LUT3 #(
.INIT(8'h40))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__1
(.I0(addra[0]),
.I1(ena),
.I2(addra[1]),
.O(ena_array[2]));
endmodule
(* ORIG_REF_NAME = "bindec" *)
module system_vga_hessian_0_0_bindec_0
(enb_array,
enb,
addrb);
output [2:0]enb_array;
input enb;
input [1:0]addrb;
wire [1:0]addrb;
wire enb;
wire [2:0]enb_array;
LUT3 #(
.INIT(8'h02))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2
(.I0(enb),
.I1(addrb[0]),
.I2(addrb[1]),
.O(enb_array[0]));
LUT3 #(
.INIT(8'h40))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0
(.I0(addrb[1]),
.I1(addrb[0]),
.I2(enb),
.O(enb_array[1]));
LUT3 #(
.INIT(8'h40))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__1
(.I0(addrb[0]),
.I1(enb),
.I2(addrb[1]),
.O(enb_array[2]));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module system_vga_hessian_0_0_blk_mem_gen_generic_cstr
(douta,
doutb,
addra,
ena,
addrb,
enb,
clka,
clkb,
dina,
dinb,
wea,
web);
output [15:0]douta;
output [15:0]doutb;
input [13:0]addra;
input ena;
input [13:0]addrb;
input enb;
input clka;
input clkb;
input [15:0]dina;
input [15:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire [2:0]ena_array;
wire enb;
wire [2:0]enb_array;
wire \ramloop[4].ram.r_n_0 ;
wire \ramloop[4].ram.r_n_1 ;
wire \ramloop[4].ram.r_n_10 ;
wire \ramloop[4].ram.r_n_11 ;
wire \ramloop[4].ram.r_n_12 ;
wire \ramloop[4].ram.r_n_13 ;
wire \ramloop[4].ram.r_n_14 ;
wire \ramloop[4].ram.r_n_15 ;
wire \ramloop[4].ram.r_n_16 ;
wire \ramloop[4].ram.r_n_17 ;
wire \ramloop[4].ram.r_n_2 ;
wire \ramloop[4].ram.r_n_3 ;
wire \ramloop[4].ram.r_n_4 ;
wire \ramloop[4].ram.r_n_5 ;
wire \ramloop[4].ram.r_n_6 ;
wire \ramloop[4].ram.r_n_7 ;
wire \ramloop[4].ram.r_n_8 ;
wire \ramloop[4].ram.r_n_9 ;
wire \ramloop[5].ram.r_n_0 ;
wire \ramloop[5].ram.r_n_1 ;
wire \ramloop[5].ram.r_n_10 ;
wire \ramloop[5].ram.r_n_11 ;
wire \ramloop[5].ram.r_n_12 ;
wire \ramloop[5].ram.r_n_13 ;
wire \ramloop[5].ram.r_n_14 ;
wire \ramloop[5].ram.r_n_15 ;
wire \ramloop[5].ram.r_n_16 ;
wire \ramloop[5].ram.r_n_17 ;
wire \ramloop[5].ram.r_n_2 ;
wire \ramloop[5].ram.r_n_3 ;
wire \ramloop[5].ram.r_n_4 ;
wire \ramloop[5].ram.r_n_5 ;
wire \ramloop[5].ram.r_n_6 ;
wire \ramloop[5].ram.r_n_7 ;
wire \ramloop[5].ram.r_n_8 ;
wire \ramloop[5].ram.r_n_9 ;
wire \ramloop[6].ram.r_n_0 ;
wire \ramloop[6].ram.r_n_1 ;
wire \ramloop[6].ram.r_n_10 ;
wire \ramloop[6].ram.r_n_11 ;
wire \ramloop[6].ram.r_n_12 ;
wire \ramloop[6].ram.r_n_13 ;
wire \ramloop[6].ram.r_n_14 ;
wire \ramloop[6].ram.r_n_15 ;
wire \ramloop[6].ram.r_n_16 ;
wire \ramloop[6].ram.r_n_17 ;
wire \ramloop[6].ram.r_n_2 ;
wire \ramloop[6].ram.r_n_3 ;
wire \ramloop[6].ram.r_n_4 ;
wire \ramloop[6].ram.r_n_5 ;
wire \ramloop[6].ram.r_n_6 ;
wire \ramloop[6].ram.r_n_7 ;
wire \ramloop[6].ram.r_n_8 ;
wire \ramloop[6].ram.r_n_9 ;
wire \ramloop[7].ram.r_n_0 ;
wire \ramloop[7].ram.r_n_1 ;
wire \ramloop[7].ram.r_n_10 ;
wire \ramloop[7].ram.r_n_11 ;
wire \ramloop[7].ram.r_n_12 ;
wire \ramloop[7].ram.r_n_13 ;
wire \ramloop[7].ram.r_n_14 ;
wire \ramloop[7].ram.r_n_15 ;
wire \ramloop[7].ram.r_n_16 ;
wire \ramloop[7].ram.r_n_17 ;
wire \ramloop[7].ram.r_n_2 ;
wire \ramloop[7].ram.r_n_3 ;
wire \ramloop[7].ram.r_n_4 ;
wire \ramloop[7].ram.r_n_5 ;
wire \ramloop[7].ram.r_n_6 ;
wire \ramloop[7].ram.r_n_7 ;
wire \ramloop[7].ram.r_n_8 ;
wire \ramloop[7].ram.r_n_9 ;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_bindec \bindec_a.bindec_inst_a
(.addra(addra[13:12]),
.ena(ena),
.ena_array(ena_array));
system_vga_hessian_0_0_bindec_0 \bindec_b.bindec_inst_b
(.addrb(addrb[13:12]),
.enb(enb),
.enb_array(enb_array));
system_vga_hessian_0_0_blk_mem_gen_mux \has_mux_a.A
(.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ({\ramloop[6].ram.r_n_0 ,\ramloop[6].ram.r_n_1 ,\ramloop[6].ram.r_n_2 ,\ramloop[6].ram.r_n_3 ,\ramloop[6].ram.r_n_4 ,\ramloop[6].ram.r_n_5 ,\ramloop[6].ram.r_n_6 ,\ramloop[6].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 (\ramloop[5].ram.r_n_16 ),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 (\ramloop[6].ram.r_n_16 ),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 (\ramloop[4].ram.r_n_16 ),
.DOADO({\ramloop[7].ram.r_n_0 ,\ramloop[7].ram.r_n_1 ,\ramloop[7].ram.r_n_2 ,\ramloop[7].ram.r_n_3 ,\ramloop[7].ram.r_n_4 ,\ramloop[7].ram.r_n_5 ,\ramloop[7].ram.r_n_6 ,\ramloop[7].ram.r_n_7 }),
.DOPADOP(\ramloop[7].ram.r_n_16 ),
.addra(addra[13:12]),
.clka(clka),
.douta(douta[15:7]),
.ena(ena));
system_vga_hessian_0_0_blk_mem_gen_mux__parameterized0 \has_mux_b.B
(.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ({\ramloop[5].ram.r_n_8 ,\ramloop[5].ram.r_n_9 ,\ramloop[5].ram.r_n_10 ,\ramloop[5].ram.r_n_11 ,\ramloop[5].ram.r_n_12 ,\ramloop[5].ram.r_n_13 ,\ramloop[5].ram.r_n_14 ,\ramloop[5].ram.r_n_15 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ({\ramloop[6].ram.r_n_8 ,\ramloop[6].ram.r_n_9 ,\ramloop[6].ram.r_n_10 ,\ramloop[6].ram.r_n_11 ,\ramloop[6].ram.r_n_12 ,\ramloop[6].ram.r_n_13 ,\ramloop[6].ram.r_n_14 ,\ramloop[6].ram.r_n_15 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ({\ramloop[4].ram.r_n_8 ,\ramloop[4].ram.r_n_9 ,\ramloop[4].ram.r_n_10 ,\ramloop[4].ram.r_n_11 ,\ramloop[4].ram.r_n_12 ,\ramloop[4].ram.r_n_13 ,\ramloop[4].ram.r_n_14 ,\ramloop[4].ram.r_n_15 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 (\ramloop[5].ram.r_n_17 ),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 (\ramloop[6].ram.r_n_17 ),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 (\ramloop[4].ram.r_n_17 ),
.DOBDO({\ramloop[7].ram.r_n_8 ,\ramloop[7].ram.r_n_9 ,\ramloop[7].ram.r_n_10 ,\ramloop[7].ram.r_n_11 ,\ramloop[7].ram.r_n_12 ,\ramloop[7].ram.r_n_13 ,\ramloop[7].ram.r_n_14 ,\ramloop[7].ram.r_n_15 }),
.DOPBDOP(\ramloop[7].ram.r_n_17 ),
.addrb(addrb[13:12]),
.clkb(clkb),
.doutb(doutb[15:7]),
.enb(enb));
system_vga_hessian_0_0_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[0]),
.dinb(dinb[0]),
.douta(douta[0]),
.doutb(doutb[0]),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[2:1]),
.dinb(dinb[2:1]),
.douta(douta[2:1]),
.doutb(doutb[2:1]),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[4:3]),
.dinb(dinb[4:3]),
.douta(douta[4:3]),
.doutb(doutb[4:3]),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[6:5]),
.dinb(dinb[6:5]),
.douta(douta[6:5]),
.doutb(doutb[6:5]),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r
(.addra(addra[11:0]),
.addrb(addrb[11:0]),
.\bottom_left_0_reg[14] ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }),
.\bottom_left_0_reg[15] (\ramloop[4].ram.r_n_16 ),
.clka(clka),
.clkb(clkb),
.dina(dina[15:7]),
.dinb(dinb[15:7]),
.ena(ena),
.ena_array(ena_array[0]),
.enb(enb),
.enb_array(enb_array[0]),
.\top_right_1_reg[14] ({\ramloop[4].ram.r_n_8 ,\ramloop[4].ram.r_n_9 ,\ramloop[4].ram.r_n_10 ,\ramloop[4].ram.r_n_11 ,\ramloop[4].ram.r_n_12 ,\ramloop[4].ram.r_n_13 ,\ramloop[4].ram.r_n_14 ,\ramloop[4].ram.r_n_15 }),
.\top_right_1_reg[15] (\ramloop[4].ram.r_n_17 ),
.wea(wea),
.web(web));
system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r
(.addra(addra[11:0]),
.addrb(addrb[11:0]),
.\bottom_left_0_reg[14] ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }),
.\bottom_left_0_reg[15] (\ramloop[5].ram.r_n_16 ),
.clka(clka),
.clkb(clkb),
.dina(dina[15:7]),
.dinb(dinb[15:7]),
.ena(ena),
.ena_array(ena_array[1]),
.enb(enb),
.enb_array(enb_array[1]),
.\top_right_1_reg[14] ({\ramloop[5].ram.r_n_8 ,\ramloop[5].ram.r_n_9 ,\ramloop[5].ram.r_n_10 ,\ramloop[5].ram.r_n_11 ,\ramloop[5].ram.r_n_12 ,\ramloop[5].ram.r_n_13 ,\ramloop[5].ram.r_n_14 ,\ramloop[5].ram.r_n_15 }),
.\top_right_1_reg[15] (\ramloop[5].ram.r_n_17 ),
.wea(wea),
.web(web));
system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r
(.addra(addra[11:0]),
.addrb(addrb[11:0]),
.\bottom_left_0_reg[14] ({\ramloop[6].ram.r_n_0 ,\ramloop[6].ram.r_n_1 ,\ramloop[6].ram.r_n_2 ,\ramloop[6].ram.r_n_3 ,\ramloop[6].ram.r_n_4 ,\ramloop[6].ram.r_n_5 ,\ramloop[6].ram.r_n_6 ,\ramloop[6].ram.r_n_7 }),
.\bottom_left_0_reg[15] (\ramloop[6].ram.r_n_16 ),
.clka(clka),
.clkb(clkb),
.dina(dina[15:7]),
.dinb(dinb[15:7]),
.ena(ena),
.ena_array(ena_array[2]),
.enb(enb),
.enb_array(enb_array[2]),
.\top_right_1_reg[14] ({\ramloop[6].ram.r_n_8 ,\ramloop[6].ram.r_n_9 ,\ramloop[6].ram.r_n_10 ,\ramloop[6].ram.r_n_11 ,\ramloop[6].ram.r_n_12 ,\ramloop[6].ram.r_n_13 ,\ramloop[6].ram.r_n_14 ,\ramloop[6].ram.r_n_15 }),
.\top_right_1_reg[15] (\ramloop[6].ram.r_n_17 ),
.wea(wea),
.web(web));
system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r
(.DOADO({\ramloop[7].ram.r_n_0 ,\ramloop[7].ram.r_n_1 ,\ramloop[7].ram.r_n_2 ,\ramloop[7].ram.r_n_3 ,\ramloop[7].ram.r_n_4 ,\ramloop[7].ram.r_n_5 ,\ramloop[7].ram.r_n_6 ,\ramloop[7].ram.r_n_7 }),
.DOBDO({\ramloop[7].ram.r_n_8 ,\ramloop[7].ram.r_n_9 ,\ramloop[7].ram.r_n_10 ,\ramloop[7].ram.r_n_11 ,\ramloop[7].ram.r_n_12 ,\ramloop[7].ram.r_n_13 ,\ramloop[7].ram.r_n_14 ,\ramloop[7].ram.r_n_15 }),
.DOPADOP(\ramloop[7].ram.r_n_16 ),
.DOPBDOP(\ramloop[7].ram.r_n_17 ),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[15:7]),
.dinb(dinb[15:7]),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_mux" *)
module system_vga_hessian_0_0_blk_mem_gen_mux
(douta,
ena,
addra,
clka,
DOADO,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ,
DOPADOP,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 );
output [8:0]douta;
input ena;
input [1:0]addra;
input clka;
input [7:0]DOADO;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ;
input [0:0]DOPADOP;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 ;
wire [7:0]DOADO;
wire [0:0]DOPADOP;
wire [1:0]addra;
wire clka;
wire [8:0]douta;
wire ena;
wire [1:0]sel_pipe;
wire [1:0]sel_pipe_d1;
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[10]_INST_0
(.I0(DOADO[3]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [3]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [3]),
.I5(sel_pipe_d1[0]),
.O(douta[3]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[11]_INST_0
(.I0(DOADO[4]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [4]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [4]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [4]),
.I5(sel_pipe_d1[0]),
.O(douta[4]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[12]_INST_0
(.I0(DOADO[5]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [5]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [5]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [5]),
.I5(sel_pipe_d1[0]),
.O(douta[5]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[13]_INST_0
(.I0(DOADO[6]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [6]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [6]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [6]),
.I5(sel_pipe_d1[0]),
.O(douta[6]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[14]_INST_0
(.I0(DOADO[7]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [7]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [7]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [7]),
.I5(sel_pipe_d1[0]),
.O(douta[7]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[15]_INST_0
(.I0(DOPADOP),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 ),
.I5(sel_pipe_d1[0]),
.O(douta[8]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[7]_INST_0
(.I0(DOADO[0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [0]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [0]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [0]),
.I5(sel_pipe_d1[0]),
.O(douta[0]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[8]_INST_0
(.I0(DOADO[1]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [1]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [1]),
.I5(sel_pipe_d1[0]),
.O(douta[1]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[9]_INST_0
(.I0(DOADO[2]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [2]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [2]),
.I5(sel_pipe_d1[0]),
.O(douta[2]));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]
(.C(clka),
.CE(ena),
.D(sel_pipe[0]),
.Q(sel_pipe_d1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]
(.C(clka),
.CE(ena),
.D(sel_pipe[1]),
.Q(sel_pipe_d1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]
(.C(clka),
.CE(ena),
.D(addra[0]),
.Q(sel_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]
(.C(clka),
.CE(ena),
.D(addra[1]),
.Q(sel_pipe[1]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_mux" *)
module system_vga_hessian_0_0_blk_mem_gen_mux__parameterized0
(doutb,
enb,
addrb,
clkb,
DOBDO,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ,
DOPBDOP,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 );
output [8:0]doutb;
input enb;
input [1:0]addrb;
input clkb;
input [7:0]DOBDO;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ;
input [0:0]DOPBDOP;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 ;
wire [7:0]DOBDO;
wire [0:0]DOPBDOP;
wire [1:0]addrb;
wire clkb;
wire [8:0]doutb;
wire enb;
wire \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ;
wire \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ;
wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0] ;
wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1] ;
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[10]_INST_0
(.I0(DOBDO[3]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [3]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [3]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[3]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[11]_INST_0
(.I0(DOBDO[4]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [4]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [4]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [4]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[4]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[12]_INST_0
(.I0(DOBDO[5]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [5]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [5]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [5]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[5]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[13]_INST_0
(.I0(DOBDO[6]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [6]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [6]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [6]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[6]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[14]_INST_0
(.I0(DOBDO[7]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [7]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [7]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [7]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[7]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[15]_INST_0
(.I0(DOPBDOP),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 ),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[8]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[7]_INST_0
(.I0(DOBDO[0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [0]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [0]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [0]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[0]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[8]_INST_0
(.I0(DOBDO[1]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [1]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [1]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[1]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[9]_INST_0
(.I0(DOBDO[2]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [2]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [2]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[2]));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]
(.C(clkb),
.CE(enb),
.D(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0] ),
.Q(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]
(.C(clkb),
.CE(enb),
.D(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1] ),
.Q(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]
(.C(clkb),
.CE(enb),
.D(addrb[0]),
.Q(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]
(.C(clkb),
.CE(enb),
.D(addrb[1]),
.Q(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module system_vga_hessian_0_0_blk_mem_gen_prim_width
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [0:0]douta;
output [0:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [0:0]dina;
input [0:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]dinb;
wire [0:0]douta;
wire [0:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized0
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized1
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized2
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized3
(\bottom_left_0_reg[14] ,
\top_right_1_reg[14] ,
\bottom_left_0_reg[15] ,
\top_right_1_reg[15] ,
clka,
clkb,
ena_array,
enb_array,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]\bottom_left_0_reg[14] ;
output [7:0]\top_right_1_reg[14] ;
output [0:0]\bottom_left_0_reg[15] ;
output [0:0]\top_right_1_reg[15] ;
input clka;
input clkb;
input [0:0]ena_array;
input [0:0]enb_array;
input ena;
input enb;
input [11:0]addra;
input [11:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [11:0]addra;
wire [11:0]addrb;
wire [7:0]\bottom_left_0_reg[14] ;
wire [0:0]\bottom_left_0_reg[15] ;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire [0:0]ena_array;
wire enb;
wire [0:0]enb_array;
wire [7:0]\top_right_1_reg[14] ;
wire [0:0]\top_right_1_reg[15] ;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.\bottom_left_0_reg[14] (\bottom_left_0_reg[14] ),
.\bottom_left_0_reg[15] (\bottom_left_0_reg[15] ),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.ena(ena),
.ena_array(ena_array),
.enb(enb),
.enb_array(enb_array),
.\top_right_1_reg[14] (\top_right_1_reg[14] ),
.\top_right_1_reg[15] (\top_right_1_reg[15] ),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized4
(\bottom_left_0_reg[14] ,
\top_right_1_reg[14] ,
\bottom_left_0_reg[15] ,
\top_right_1_reg[15] ,
clka,
clkb,
ena_array,
enb_array,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]\bottom_left_0_reg[14] ;
output [7:0]\top_right_1_reg[14] ;
output [0:0]\bottom_left_0_reg[15] ;
output [0:0]\top_right_1_reg[15] ;
input clka;
input clkb;
input [0:0]ena_array;
input [0:0]enb_array;
input ena;
input enb;
input [11:0]addra;
input [11:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [11:0]addra;
wire [11:0]addrb;
wire [7:0]\bottom_left_0_reg[14] ;
wire [0:0]\bottom_left_0_reg[15] ;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire [0:0]ena_array;
wire enb;
wire [0:0]enb_array;
wire [7:0]\top_right_1_reg[14] ;
wire [0:0]\top_right_1_reg[15] ;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.\bottom_left_0_reg[14] (\bottom_left_0_reg[14] ),
.\bottom_left_0_reg[15] (\bottom_left_0_reg[15] ),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.ena(ena),
.ena_array(ena_array),
.enb(enb),
.enb_array(enb_array),
.\top_right_1_reg[14] (\top_right_1_reg[14] ),
.\top_right_1_reg[15] (\top_right_1_reg[15] ),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized5
(\bottom_left_0_reg[14] ,
\top_right_1_reg[14] ,
\bottom_left_0_reg[15] ,
\top_right_1_reg[15] ,
clka,
clkb,
ena_array,
enb_array,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]\bottom_left_0_reg[14] ;
output [7:0]\top_right_1_reg[14] ;
output [0:0]\bottom_left_0_reg[15] ;
output [0:0]\top_right_1_reg[15] ;
input clka;
input clkb;
input [0:0]ena_array;
input [0:0]enb_array;
input ena;
input enb;
input [11:0]addra;
input [11:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [11:0]addra;
wire [11:0]addrb;
wire [7:0]\bottom_left_0_reg[14] ;
wire [0:0]\bottom_left_0_reg[15] ;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire [0:0]ena_array;
wire enb;
wire [0:0]enb_array;
wire [7:0]\top_right_1_reg[14] ;
wire [0:0]\top_right_1_reg[15] ;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.\bottom_left_0_reg[14] (\bottom_left_0_reg[14] ),
.\bottom_left_0_reg[15] (\bottom_left_0_reg[15] ),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.ena(ena),
.ena_array(ena_array),
.enb(enb),
.enb_array(enb_array),
.\top_right_1_reg[14] (\top_right_1_reg[14] ),
.\top_right_1_reg[15] (\top_right_1_reg[15] ),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized6
(DOADO,
DOBDO,
DOPADOP,
DOPBDOP,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]DOADO;
output [7:0]DOBDO;
output [0:0]DOPADOP;
output [0:0]DOPBDOP;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [7:0]DOADO;
wire [7:0]DOBDO;
wire [0:0]DOPADOP;
wire [0:0]DOPBDOP;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized6 \prim_noinit.ram
(.DOADO(DOADO),
.DOBDO(DOBDO),
.DOPADOP(DOPADOP),
.DOPBDOP(DOPBDOP),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module system_vga_hessian_0_0_blk_mem_gen_prim_wrapper
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [0:0]douta;
output [0:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [0:0]dina;
input [0:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]dinb;
wire [0:0]douta;
wire [0:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
wire [15:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(1),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:1],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:1],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized0
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized1
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized2
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized3
(\bottom_left_0_reg[14] ,
\top_right_1_reg[14] ,
\bottom_left_0_reg[15] ,
\top_right_1_reg[15] ,
clka,
clkb,
ena_array,
enb_array,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]\bottom_left_0_reg[14] ;
output [7:0]\top_right_1_reg[14] ;
output [0:0]\bottom_left_0_reg[15] ;
output [0:0]\top_right_1_reg[15] ;
input clka;
input clkb;
input [0:0]ena_array;
input [0:0]enb_array;
input ena;
input enb;
input [11:0]addra;
input [11:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [11:0]addra;
wire [11:0]addrb;
wire [7:0]\bottom_left_0_reg[14] ;
wire [0:0]\bottom_left_0_reg[15] ;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire [0:0]ena_array;
wire enb;
wire [0:0]enb_array;
wire [7:0]\top_right_1_reg[14] ;
wire [0:0]\top_right_1_reg[15] ;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb[7:0]}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,dinb[8]}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\bottom_left_0_reg[14] }),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\top_right_1_reg[14] }),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\bottom_left_0_reg[15] }),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\top_right_1_reg[15] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized4
(\bottom_left_0_reg[14] ,
\top_right_1_reg[14] ,
\bottom_left_0_reg[15] ,
\top_right_1_reg[15] ,
clka,
clkb,
ena_array,
enb_array,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]\bottom_left_0_reg[14] ;
output [7:0]\top_right_1_reg[14] ;
output [0:0]\bottom_left_0_reg[15] ;
output [0:0]\top_right_1_reg[15] ;
input clka;
input clkb;
input [0:0]ena_array;
input [0:0]enb_array;
input ena;
input enb;
input [11:0]addra;
input [11:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [11:0]addra;
wire [11:0]addrb;
wire [7:0]\bottom_left_0_reg[14] ;
wire [0:0]\bottom_left_0_reg[15] ;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire [0:0]ena_array;
wire enb;
wire [0:0]enb_array;
wire [7:0]\top_right_1_reg[14] ;
wire [0:0]\top_right_1_reg[15] ;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb[7:0]}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,dinb[8]}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\bottom_left_0_reg[14] }),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\top_right_1_reg[14] }),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\bottom_left_0_reg[15] }),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\top_right_1_reg[15] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized5
(\bottom_left_0_reg[14] ,
\top_right_1_reg[14] ,
\bottom_left_0_reg[15] ,
\top_right_1_reg[15] ,
clka,
clkb,
ena_array,
enb_array,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]\bottom_left_0_reg[14] ;
output [7:0]\top_right_1_reg[14] ;
output [0:0]\bottom_left_0_reg[15] ;
output [0:0]\top_right_1_reg[15] ;
input clka;
input clkb;
input [0:0]ena_array;
input [0:0]enb_array;
input ena;
input enb;
input [11:0]addra;
input [11:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [11:0]addra;
wire [11:0]addrb;
wire [7:0]\bottom_left_0_reg[14] ;
wire [0:0]\bottom_left_0_reg[15] ;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire [0:0]ena_array;
wire enb;
wire [0:0]enb_array;
wire [7:0]\top_right_1_reg[14] ;
wire [0:0]\top_right_1_reg[15] ;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb[7:0]}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,dinb[8]}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\bottom_left_0_reg[14] }),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\top_right_1_reg[14] }),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\bottom_left_0_reg[15] }),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\top_right_1_reg[15] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized6
(DOADO,
DOBDO,
DOPADOP,
DOPBDOP,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]DOADO;
output [7:0]DOBDO;
output [0:0]DOPADOP;
output [0:0]DOPBDOP;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0 ;
wire [7:0]DOADO;
wire [7:0]DOBDO;
wire [0:0]DOPADOP;
wire [0:0]DOPBDOP;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb[7:0]}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,dinb[8]}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],DOADO}),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],DOBDO}),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],DOPADOP}),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],DOPBDOP}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0 ),
.ENBWREN(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0 ),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
LUT3 #(
.INIT(8'h80))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1
(.I0(addra[13]),
.I1(addra[12]),
.I2(ena),
.O(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0 ));
LUT3 #(
.INIT(8'h80))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2
(.I0(addrb[13]),
.I1(addrb[12]),
.I2(enb),
.O(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0 ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module system_vga_hessian_0_0_blk_mem_gen_top
(douta,
doutb,
addra,
ena,
addrb,
enb,
clka,
clkb,
dina,
dinb,
wea,
web);
output [15:0]douta;
output [15:0]doutb;
input [13:0]addra;
input ena;
input [13:0]addrb;
input enb;
input clka;
input clkb;
input [15:0]dina;
input [15:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule
(* C_ADDRA_WIDTH = "14" *) (* C_ADDRB_WIDTH = "14" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "7" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 22.1485 mW" *)
(* C_FAMILY = "zynq" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "1" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "1" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "blk_mem_gen_0.mem" *)
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "0" *)
(* C_MEM_TYPE = "2" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "16384" *) (* C_READ_DEPTH_B = "16384" *) (* C_READ_WIDTH_A = "16" *)
(* C_READ_WIDTH_B = "16" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "16384" *) (* C_WRITE_DEPTH_B = "16384" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "16" *) (* C_WRITE_WIDTH_B = "16" *)
(* C_XDEVICEFAMILY = "zynq" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module system_vga_hessian_0_0_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [13:0]addra;
input [15:0]dina;
output [15:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [13:0]addrb;
input [15:0]dinb;
output [15:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [13:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [15:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [15:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [13:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
assign dbiterr = \<const0> ;
assign rdaddrecc[13] = \<const0> ;
assign rdaddrecc[12] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[13] = \<const0> ;
assign s_axi_rdaddrecc[12] = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
system_vga_hessian_0_0_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module system_vga_hessian_0_0_blk_mem_gen_v8_3_5_synth
(douta,
doutb,
addra,
ena,
addrb,
enb,
clka,
clkb,
dina,
dinb,
wea,
web);
output [15:0]douta;
output [15:0]doutb;
input [13:0]addra;
input ena;
input [13:0]addrb;
input enb;
input clka;
input clkb;
input [15:0]dina;
input [15:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ======================================================================
// Sensor_Node.v generated from TopDesign.cysch
// 12/19/2014 at 14:31
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_DIE_LEOPARD 1
`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
`define CYDEV_CHIP_REV_LEOPARD_ES3 3
`define CYDEV_CHIP_REV_LEOPARD_ES2 1
`define CYDEV_CHIP_REV_LEOPARD_ES1 0
`define CYDEV_CHIP_DIE_PSOC4A 2
`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17
`define CYDEV_CHIP_REV_PSOC4A_ES0 17
`define CYDEV_CHIP_DIE_PANTHER 3
`define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1
`define CYDEV_CHIP_REV_PANTHER_ES1 1
`define CYDEV_CHIP_REV_PANTHER_ES0 0
`define CYDEV_CHIP_DIE_PSOC5LP 4
`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0
`define CYDEV_CHIP_REV_PSOC5LP_ES0 0
`define CYDEV_CHIP_DIE_EXPECT 4
`define CYDEV_CHIP_REV_EXPECT 0
`define CYDEV_CHIP_DIE_ACTUAL 4
/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4A 2
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4D 3
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4D_ES0 0
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5A 4
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_MEMBER_5B 5
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_FAMILY_USED 3
`define CYDEV_CHIP_MEMBER_USED 5
`define CYDEV_CHIP_REVISION_USED 0
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// Component: B_UART_v2_30
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_UART_v2_30"
`include "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_UART_v2_30\B_UART_v2_30.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_UART_v2_30"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_UART_v2_30\B_UART_v2_30.v"
`endif
// UART_v2_30(Address1=0, Address2=0, BaudRate=1200, BreakBitsRX=13, BreakBitsTX=13, BreakDetect=false, CRCoutputsEn=false, CtrlModeReplacementString=SyncCtl, Enable_RX=1, Enable_RXIntInterrupt=0, Enable_TX=0, Enable_TXIntInterrupt=0, EnableHWAddress=0, EnIntRXInterrupt=false, EnIntTXInterrupt=false, FlowControl=0, HalfDuplexEn=false, HwTXEnSignal=true, InternalClock=true, InternalClockUsed=1, InterruptOnAddDetect=0, InterruptOnAddressMatch=0, InterruptOnBreak=0, InterruptOnByteRcvd=1, InterruptOnOverrunError=0, InterruptOnParityError=0, InterruptOnStopError=0, InterruptOnTXComplete=false, InterruptOnTXFifoEmpty=false, InterruptOnTXFifoFull=false, InterruptOnTXFifoNotFull=false, IntOnAddressDetect=false, IntOnAddressMatch=false, IntOnBreak=false, IntOnByteRcvd=true, IntOnOverrunError=false, IntOnParityError=false, IntOnStopError=false, NumDataBits=8, NumStopBits=1, OverSamplingRate=8, ParityType=0, ParityTypeSw=false, RequiredClock=9600, RXAddressMode=0, RXBufferSize=4, RxBuffRegSizeReplacementString=uint8, RXEnable=true, TXBitClkGenDP=true, TXBufferSize=4, TxBuffRegSizeReplacementString=uint8, TXEnable=false, Use23Polling=true, CY_COMPONENT_NAME=UART_v2_30, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=UART_SoilMoisture_Decagon, CY_INSTANCE_SHORT_NAME=UART_SoilMoisture_Decagon, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=30, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=UART_SoilMoisture_Decagon, )
module UART_v2_30_0 (
rx_clk,
rx_data,
tx_clk,
tx_data,
rx_interrupt,
tx_interrupt,
tx,
tx_en,
rts_n,
reset,
cts_n,
clock,
rx);
output rx_clk;
output rx_data;
output tx_clk;
output tx_data;
output rx_interrupt;
output tx_interrupt;
output tx;
output tx_en;
output rts_n;
input reset;
input cts_n;
input clock;
input rx;
parameter Address1 = 0;
parameter Address2 = 0;
parameter EnIntRXInterrupt = 0;
parameter EnIntTXInterrupt = 0;
parameter FlowControl = 0;
parameter HalfDuplexEn = 0;
parameter HwTXEnSignal = 1;
parameter NumDataBits = 8;
parameter NumStopBits = 1;
parameter ParityType = 0;
parameter RXEnable = 1;
parameter TXEnable = 0;
wire Net_289;
wire Net_61;
wire Net_9;
cy_clock_v1_0
#(.id("b0162966-0060-4af5-82d1-fcb491ad7619/be0a0e37-ad17-42ca-b5a1-1a654d736358"),
.source_clock_id(""),
.divisor(0),
.period("104166666666.667"),
.is_direct(0),
.is_digital(1))
IntClock
(.clock_out(Net_9));
// VirtualMux_1 (cy_virtualmux_v1_0)
assign Net_61 = Net_9;
B_UART_v2_30 BUART (
.cts_n(cts_n),
.tx(tx),
.rts_n(rts_n),
.tx_en(tx_en),
.clock(Net_61),
.reset(reset),
.rx(rx),
.tx_interrupt(tx_interrupt),
.rx_interrupt(rx_interrupt),
.tx_data(tx_data),
.tx_clk(tx_clk),
.rx_data(rx_data),
.rx_clk(rx_clk));
defparam BUART.Address1 = 0;
defparam BUART.Address2 = 0;
defparam BUART.BreakBitsRX = 13;
defparam BUART.BreakBitsTX = 13;
defparam BUART.BreakDetect = 0;
defparam BUART.CRCoutputsEn = 0;
defparam BUART.FlowControl = 0;
defparam BUART.HalfDuplexEn = 0;
defparam BUART.HwTXEnSignal = 1;
defparam BUART.NumDataBits = 8;
defparam BUART.NumStopBits = 1;
defparam BUART.OverSampleCount = 8;
defparam BUART.ParityType = 0;
defparam BUART.ParityTypeSw = 0;
defparam BUART.RXAddressMode = 0;
defparam BUART.RXEnable = 1;
defparam BUART.RXStatusIntEnable = 1;
defparam BUART.TXBitClkGenDP = 1;
defparam BUART.TXEnable = 0;
defparam BUART.Use23Polling = 1;
endmodule
// UART_v2_30(Address1=0, Address2=0, BaudRate=9600, BreakBitsRX=13, BreakBitsTX=13, BreakDetect=false, CRCoutputsEn=false, CtrlModeReplacementString=SyncCtl, Enable_RX=1, Enable_RXIntInterrupt=0, Enable_TX=0, Enable_TXIntInterrupt=0, EnableHWAddress=0, EnIntRXInterrupt=false, EnIntTXInterrupt=false, FlowControl=0, HalfDuplexEn=false, HwTXEnSignal=true, InternalClock=true, InternalClockUsed=1, InterruptOnAddDetect=0, InterruptOnAddressMatch=0, InterruptOnBreak=0, InterruptOnByteRcvd=1, InterruptOnOverrunError=0, InterruptOnParityError=0, InterruptOnStopError=0, InterruptOnTXComplete=false, InterruptOnTXFifoEmpty=false, InterruptOnTXFifoFull=false, InterruptOnTXFifoNotFull=false, IntOnAddressDetect=false, IntOnAddressMatch=false, IntOnBreak=false, IntOnByteRcvd=true, IntOnOverrunError=false, IntOnParityError=false, IntOnStopError=false, NumDataBits=8, NumStopBits=1, OverSamplingRate=8, ParityType=0, ParityTypeSw=false, RequiredClock=76800, RXAddressMode=0, RXBufferSize=4, RxBuffRegSizeReplacementString=uint8, RXEnable=true, TXBitClkGenDP=true, TXBufferSize=4, TxBuffRegSizeReplacementString=uint8, TXEnable=false, Use23Polling=true, CY_COMPONENT_NAME=UART_v2_30, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=UART_Ultrasonic_Maxbotix, CY_INSTANCE_SHORT_NAME=UART_Ultrasonic_Maxbotix, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=30, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=UART_Ultrasonic_Maxbotix, )
module UART_v2_30_1 (
rx_clk,
rx_data,
tx_clk,
tx_data,
rx_interrupt,
tx_interrupt,
tx,
tx_en,
rts_n,
reset,
cts_n,
clock,
rx);
output rx_clk;
output rx_data;
output tx_clk;
output tx_data;
output rx_interrupt;
output tx_interrupt;
output tx;
output tx_en;
output rts_n;
input reset;
input cts_n;
input clock;
input rx;
parameter Address1 = 0;
parameter Address2 = 0;
parameter EnIntRXInterrupt = 0;
parameter EnIntTXInterrupt = 0;
parameter FlowControl = 0;
parameter HalfDuplexEn = 0;
parameter HwTXEnSignal = 1;
parameter NumDataBits = 8;
parameter NumStopBits = 1;
parameter ParityType = 0;
parameter RXEnable = 1;
parameter TXEnable = 0;
wire Net_289;
wire Net_61;
wire Net_9;
cy_clock_v1_0
#(.id("cdcc95c5-960c-4c98-bdc1-3ae892f46451/be0a0e37-ad17-42ca-b5a1-1a654d736358"),
.source_clock_id(""),
.divisor(0),
.period("13020833333.3333"),
.is_direct(0),
.is_digital(1))
IntClock
(.clock_out(Net_9));
// VirtualMux_1 (cy_virtualmux_v1_0)
assign Net_61 = Net_9;
B_UART_v2_30 BUART (
.cts_n(cts_n),
.tx(tx),
.rts_n(rts_n),
.tx_en(tx_en),
.clock(Net_61),
.reset(reset),
.rx(rx),
.tx_interrupt(tx_interrupt),
.rx_interrupt(rx_interrupt),
.tx_data(tx_data),
.tx_clk(tx_clk),
.rx_data(rx_data),
.rx_clk(rx_clk));
defparam BUART.Address1 = 0;
defparam BUART.Address2 = 0;
defparam BUART.BreakBitsRX = 13;
defparam BUART.BreakBitsTX = 13;
defparam BUART.BreakDetect = 0;
defparam BUART.CRCoutputsEn = 0;
defparam BUART.FlowControl = 0;
defparam BUART.HalfDuplexEn = 0;
defparam BUART.HwTXEnSignal = 1;
defparam BUART.NumDataBits = 8;
defparam BUART.NumStopBits = 1;
defparam BUART.OverSampleCount = 8;
defparam BUART.ParityType = 0;
defparam BUART.ParityTypeSw = 0;
defparam BUART.RXAddressMode = 0;
defparam BUART.RXEnable = 1;
defparam BUART.RXStatusIntEnable = 1;
defparam BUART.TXBitClkGenDP = 1;
defparam BUART.TXEnable = 0;
defparam BUART.Use23Polling = 1;
endmodule
// UART_v2_30(Address1=0, Address2=0, BaudRate=115200, BreakBitsRX=13, BreakBitsTX=13, BreakDetect=false, CRCoutputsEn=false, CtrlModeReplacementString=SyncCtl, Enable_RX=1, Enable_RXIntInterrupt=0, Enable_TX=1, Enable_TXIntInterrupt=0, EnableHWAddress=0, EnIntRXInterrupt=false, EnIntTXInterrupt=false, FlowControl=0, HalfDuplexEn=false, HwTXEnSignal=false, InternalClock=true, InternalClockUsed=1, InterruptOnAddDetect=0, InterruptOnAddressMatch=0, InterruptOnBreak=0, InterruptOnByteRcvd=1, InterruptOnOverrunError=0, InterruptOnParityError=0, InterruptOnStopError=0, InterruptOnTXComplete=false, InterruptOnTXFifoEmpty=false, InterruptOnTXFifoFull=false, InterruptOnTXFifoNotFull=false, IntOnAddressDetect=false, IntOnAddressMatch=false, IntOnBreak=false, IntOnByteRcvd=true, IntOnOverrunError=false, IntOnParityError=false, IntOnStopError=false, NumDataBits=8, NumStopBits=1, OverSamplingRate=8, ParityType=0, ParityTypeSw=false, RequiredClock=921600, RXAddressMode=0, RXBufferSize=4, RxBuffRegSizeReplacementString=uint8, RXEnable=true, TXBitClkGenDP=true, TXBufferSize=4, TxBuffRegSizeReplacementString=uint8, TXEnable=true, Use23Polling=true, CY_COMPONENT_NAME=UART_v2_30, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=NEOMOTE_1:UART_MOTE, CY_INSTANCE_SHORT_NAME=UART_MOTE, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=30, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=NEOMOTE_1_UART_MOTE, )
module UART_v2_30_2 (
rx_clk,
rx_data,
tx_clk,
tx_data,
rx_interrupt,
tx_interrupt,
tx,
tx_en,
rts_n,
reset,
cts_n,
clock,
rx);
output rx_clk;
output rx_data;
output tx_clk;
output tx_data;
output rx_interrupt;
output tx_interrupt;
output tx;
output tx_en;
output rts_n;
input reset;
input cts_n;
input clock;
input rx;
parameter Address1 = 0;
parameter Address2 = 0;
parameter EnIntRXInterrupt = 0;
parameter EnIntTXInterrupt = 0;
parameter FlowControl = 0;
parameter HalfDuplexEn = 0;
parameter HwTXEnSignal = 0;
parameter NumDataBits = 8;
parameter NumStopBits = 1;
parameter ParityType = 0;
parameter RXEnable = 1;
parameter TXEnable = 1;
wire Net_289;
wire Net_61;
wire Net_9;
cy_clock_v1_0
#(.id("42a3c2ea-f0b8-4d0c-bf50-a43bc1e1db6a/b12b385d-9eab-45ad-ad40-c0cf3437ebe3/be0a0e37-ad17-42ca-b5a1-1a654d736358"),
.source_clock_id(""),
.divisor(0),
.period("1085069444.44444"),
.is_direct(0),
.is_digital(1))
IntClock
(.clock_out(Net_9));
// VirtualMux_1 (cy_virtualmux_v1_0)
assign Net_61 = Net_9;
B_UART_v2_30 BUART (
.cts_n(cts_n),
.tx(tx),
.rts_n(rts_n),
.tx_en(tx_en),
.clock(Net_61),
.reset(reset),
.rx(rx),
.tx_interrupt(tx_interrupt),
.rx_interrupt(rx_interrupt),
.tx_data(tx_data),
.tx_clk(tx_clk),
.rx_data(rx_data),
.rx_clk(rx_clk));
defparam BUART.Address1 = 0;
defparam BUART.Address2 = 0;
defparam BUART.BreakBitsRX = 13;
defparam BUART.BreakBitsTX = 13;
defparam BUART.BreakDetect = 0;
defparam BUART.CRCoutputsEn = 0;
defparam BUART.FlowControl = 0;
defparam BUART.HalfDuplexEn = 0;
defparam BUART.HwTXEnSignal = 0;
defparam BUART.NumDataBits = 8;
defparam BUART.NumStopBits = 1;
defparam BUART.OverSampleCount = 8;
defparam BUART.ParityType = 0;
defparam BUART.ParityTypeSw = 0;
defparam BUART.RXAddressMode = 0;
defparam BUART.RXEnable = 1;
defparam BUART.RXStatusIntEnable = 1;
defparam BUART.TXBitClkGenDP = 1;
defparam BUART.TXEnable = 1;
defparam BUART.Use23Polling = 1;
endmodule
// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif
// Component: OneTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v"
`endif
// Component: or_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`endif
// I2C_v3_30(Address_Decode=1, BusSpeed_kHz=100, ClockInputVisibility=false, CtlModeReplacementString=SyncCtl, EnableWakeup=false, ExternalBuffer=false, Externi2cIntrHandler=false, ExternTmoutIntrHandler=false, FF=true, Hex=false, I2C_Mode=2, I2cBusPort=0, Implementation=1, InternalUdbClockToleranceMinus=25, InternalUdbClockTolerancePlus=5, NotSlaveClockMinusTolerance=25, NotSlaveClockPlusTolerance=5, PrescalerEnabled=false, PrescalerPeriod=1, Psoc3ffSelected=false, Psoc5AffSelected=false, Psoc5lpffSelected=true, RemoveI2cff=false, RemoveI2cUdb=true, RemoveIntClock=true, RemoveTimeoutTimer=true, SclTimeoutEnabled=false, SdaTimeoutEnabled=false, Slave_Address=8, SlaveClockMinusTolerance=5, SlaveClockPlusTolerance=50, TimeoutEnabled=false, TimeoutImplementation=0, TimeOutms=25, TimeoutPeriodff=1563, TimeoutPeriodUdb=39999, UDB_MSTR=false, UDB_MULTI_MASTER_SLAVE=false, UDB_SLV=false, UdbInternalClock=false, UdbRequiredClock=1600, UdbSlaveFixedPlacementEnable=false, CY_COMPONENT_NAME=I2C_v3_30, CY_CONTROL_FILE=I2C_Slave_DefaultPlacement.ctl, CY_FITTER_NAME=NEOMOTE_1:I2C_0, CY_INSTANCE_SHORT_NAME=I2C_0, CY_MAJOR_VERSION=3, CY_MINOR_VERSION=30, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=NEOMOTE_1_I2C_0, )
module I2C_v3_30_3 (
sda_o,
scl_o,
sda_i,
scl_i,
iclk,
bclk,
reset,
clock,
scl,
sda,
itclk);
output sda_o;
output scl_o;
input sda_i;
input scl_i;
output iclk;
output bclk;
input reset;
input clock;
inout scl;
inout sda;
output itclk;
wire sda_x_wire;
wire sda_yfb;
wire udb_clk;
wire Net_975;
wire Net_974;
wire Net_973;
wire bus_clk;
wire Net_972;
wire Net_968;
wire scl_yfb;
wire Net_969;
wire Net_971;
wire Net_970;
wire timeout_clk;
wire Net_697;
wire Net_1045;
wire [1:0] Net_1109;
wire [5:0] Net_643;
wire scl_x_wire;
// Vmux_sda_out (cy_virtualmux_v1_0)
assign sda_x_wire = Net_643[1];
cy_isr_v1_0
#(.int_type(2'b00))
I2C_IRQ
(.int_signal(Net_697));
cy_psoc3_i2c_v1_0 I2C_FF (
.clock(bus_clk),
.scl_in(Net_1109[0]),
.sda_in(Net_1109[1]),
.scl_out(Net_643[0]),
.sda_out(Net_643[1]),
.interrupt(Net_643[2]));
defparam I2C_FF.use_wakeup = 0;
// Vmux_interrupt (cy_virtualmux_v1_0)
assign Net_697 = Net_643[2];
// Vmux_scl_out (cy_virtualmux_v1_0)
assign scl_x_wire = Net_643[0];
OneTerminal OneTerminal_1 (
.o(Net_969));
OneTerminal OneTerminal_2 (
.o(Net_968));
// Vmux_clock (cy_virtualmux_v1_0)
assign udb_clk = clock;
cy_clock_v1_0
#(.id("42a3c2ea-f0b8-4d0c-bf50-a43bc1e1db6a/966ec24e-f954-4ab8-95f3-fa8b01a2dc28/5ece924d-20ba-480e-9102-bc082dcdd926"),
.source_clock_id("75C2148C-3656-4d8a-846D-0CAE99AB6FF7"),
.divisor(0),
.period("0"),
.is_direct(1),
.is_digital(1))
BusClock
(.clock_out(bus_clk));
assign bclk = bus_clk | Net_973;
ZeroTerminal ZeroTerminal_1 (
.z(Net_973));
assign iclk = udb_clk | Net_974;
ZeroTerminal ZeroTerminal_2 (
.z(Net_974));
// Vmux_scl_in (cy_virtualmux_v1_0)
assign Net_1109[0] = scl_yfb;
// Vmux_sda_in (cy_virtualmux_v1_0)
assign Net_1109[1] = sda_yfb;
wire [0:0] tmpOE__Bufoe_scl_net;
cy_bufoe
Bufoe_scl
(.x(scl_x_wire),
.y(scl),
.oe(tmpOE__Bufoe_scl_net),
.yfb(scl_yfb));
assign tmpOE__Bufoe_scl_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{Net_969} : {Net_969};
wire [0:0] tmpOE__Bufoe_sda_net;
cy_bufoe
Bufoe_sda
(.x(sda_x_wire),
.y(sda),
.oe(tmpOE__Bufoe_sda_net),
.yfb(sda_yfb));
assign tmpOE__Bufoe_sda_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{Net_968} : {Net_968};
// Vmux_timeout_clock (cy_virtualmux_v1_0)
assign timeout_clk = clock;
assign itclk = timeout_clk | Net_975;
ZeroTerminal ZeroTerminal_3 (
.z(Net_975));
assign scl_o = scl_x_wire;
assign sda_o = sda_x_wire;
endmodule
// Counter_v2_40(CaptureMode=0, CaptureModeSoftware=0, ClockMode=3, CompareMode=1, CompareModeSoftware=0, CompareStatusEdgeSense=true, CompareValue=12, CONTROL3=1, ControlRegRemoved=0, CtlModeReplacementString=SyncCtl, CyGetRegReplacementString=CY_GET_REG16, CySetRegReplacementString=CY_SET_REG16, EnableMode=0, FF16=true, FF8=false, FixedFunction=true, FixedFunctionUsed=1, InitCounterValue=12000, InterruptOnCapture=false, InterruptOnCompare=false, InterruptOnOverUnderFlow=false, InterruptOnTC=true, Period=12000, RegDefReplacementString=reg16, RegSizeReplacementString=uint16, ReloadOnCapture=false, ReloadOnCompare=false, ReloadOnOverUnder=true, ReloadOnReset=true, Resolution=16, RstStatusReplacementString=sSTSReg_rstSts, RunMode=0, UDB16=false, UDB24=false, UDB32=false, UDB8=false, UDBControlReg=false, UseInterrupt=true, VerilogSectionReplacementString=sC16, CY_COMPONENT_NAME=Counter_v2_40, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=NEOMOTE_1:DELAY_COUNTER, CY_INSTANCE_SHORT_NAME=DELAY_COUNTER, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=40, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=NEOMOTE_1_DELAY_COUNTER, )
module Counter_v2_40_4 (
clock,
comp,
tc,
reset,
interrupt,
enable,
capture,
upCnt,
downCnt,
up_ndown,
count);
input clock;
output comp;
output tc;
input reset;
output interrupt;
input enable;
input capture;
input upCnt;
input downCnt;
input up_ndown;
input count;
parameter CaptureMode = 0;
parameter ClockMode = 3;
parameter CompareMode = 1;
parameter CompareStatusEdgeSense = 1;
parameter EnableMode = 0;
parameter ReloadOnCapture = 0;
parameter ReloadOnCompare = 0;
parameter ReloadOnOverUnder = 1;
parameter ReloadOnReset = 1;
parameter Resolution = 16;
parameter RunMode = 0;
parameter UseInterrupt = 1;
wire Net_47;
wire Net_102;
wire Net_95;
wire Net_82;
wire Net_91;
wire Net_89;
wire Net_49;
wire Net_48;
wire Net_42;
wire Net_43;
cy_psoc3_timer_v1_0 CounterHW (
.timer_reset(reset),
.capture(capture),
.enable(Net_91),
.kill(Net_82),
.clock(clock),
.tc(Net_48),
.compare(Net_47),
.interrupt(Net_42));
// int_vm (cy_virtualmux_v1_0)
assign interrupt = Net_42;
// TC_vm (cy_virtualmux_v1_0)
assign tc = Net_48;
ZeroTerminal ZeroTerminal_1 (
.z(Net_82));
// VirtualMux_1 (cy_virtualmux_v1_0)
assign Net_89 = Net_95;
ZeroTerminal ZeroTerminal_2 (
.z(Net_95));
// vmEnableMode (cy_virtualmux_v1_0)
assign Net_91 = enable;
OneTerminal OneTerminal_1 (
.o(Net_102));
endmodule
// Component: cy_constant_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`endif
// NEOMOTE(CY_COMPONENT_NAME=NEOMOTE, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=NEOMOTE_1, CY_INSTANCE_SHORT_NAME=NEOMOTE_1, CY_MAJOR_VERSION=0, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=NEOMOTE_1, )
module NEOMOTE_5 ;
wire Net_664;
wire Net_672;
wire Net_671;
wire Net_670;
wire Net_669;
wire Net_668;
wire Net_667;
wire Net_666;
wire Net_665;
wire Net_636;
wire Net_635;
wire Net_634;
wire Net_633;
wire Net_632;
wire Net_631;
wire Net_630;
wire Net_629;
wire Net_628;
wire Net_627;
wire Net_626;
wire Net_625;
wire Net_542;
wire Net_541;
wire Net_540;
wire Net_539;
wire Net_538;
wire Net_537;
wire Net_536;
wire Net_535;
wire Net_534;
wire Net_533;
wire Net_532;
wire Net_531;
wire Net_648;
wire Net_660;
wire Net_651;
wire Net_176;
wire Net_212;
UART_v2_30_2 UART_MOTE (
.cts_n(1'b0),
.tx(Net_176),
.rts_n(Net_532),
.tx_en(Net_533),
.clock(1'b0),
.reset(Net_535),
.rx(Net_212),
.tx_interrupt(Net_536),
.rx_interrupt(Net_537),
.tx_data(Net_538),
.tx_clk(Net_539),
.rx_data(Net_540),
.rx_clk(Net_541));
defparam UART_MOTE.Address1 = 0;
defparam UART_MOTE.Address2 = 0;
defparam UART_MOTE.EnIntRXInterrupt = 0;
defparam UART_MOTE.EnIntTXInterrupt = 0;
defparam UART_MOTE.FlowControl = 0;
defparam UART_MOTE.HalfDuplexEn = 0;
defparam UART_MOTE.HwTXEnSignal = 0;
defparam UART_MOTE.NumDataBits = 8;
defparam UART_MOTE.NumStopBits = 1;
defparam UART_MOTE.ParityType = 0;
defparam UART_MOTE.RXEnable = 1;
defparam UART_MOTE.TXEnable = 1;
wire [0:0] tmpOE__RX_Pin_net;
wire [0:0] tmpIO_0__RX_Pin_net;
wire [0:0] tmpINTERRUPT_0__RX_Pin_net;
electrical [0:0] tmpSIOVREF__RX_Pin_net;
cy_psoc3_pins_v1_10
#(.id("42a3c2ea-f0b8-4d0c-bf50-a43bc1e1db6a/483c8cff-b35d-4e9b-b782-7d15671bd8fc"),
.drive_mode(3'b010),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
RX_Pin
(.oe(tmpOE__RX_Pin_net),
.y({1'b0}),
.fb({Net_212}),
.io({tmpIO_0__RX_Pin_net[0:0]}),
.siovref(tmpSIOVREF__RX_Pin_net),
.interrupt({tmpINTERRUPT_0__RX_Pin_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__RX_Pin_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__TX_Pin_net;
wire [0:0] tmpFB_0__TX_Pin_net;
wire [0:0] tmpIO_0__TX_Pin_net;
wire [0:0] tmpINTERRUPT_0__TX_Pin_net;
electrical [0:0] tmpSIOVREF__TX_Pin_net;
cy_psoc3_pins_v1_10
#(.id("42a3c2ea-f0b8-4d0c-bf50-a43bc1e1db6a/ed092b9b-d398-4703-be89-cebf998501f6"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
TX_Pin
(.oe(tmpOE__TX_Pin_net),
.y({Net_176}),
.fb({tmpFB_0__TX_Pin_net[0:0]}),
.io({tmpIO_0__TX_Pin_net[0:0]}),
.siovref(tmpSIOVREF__TX_Pin_net),
.interrupt({tmpINTERRUPT_0__TX_Pin_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__TX_Pin_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
ZeroTerminal ZeroTerminal_2 (
.z(Net_535));
cy_isr_v1_0
#(.int_type(2'b10))
isr_RX
(.int_signal(Net_537));
wire [0:0] tmpOE__RX_RTS_n_net;
wire [0:0] tmpFB_0__RX_RTS_n_net;
wire [0:0] tmpIO_0__RX_RTS_n_net;
electrical [0:0] tmpSIOVREF__RX_RTS_n_net;
cy_psoc3_pins_v1_10
#(.id("42a3c2ea-f0b8-4d0c-bf50-a43bc1e1db6a/f497a9ab-60b4-4f16-b3f4-5d5c511256c1"),
.drive_mode(3'b010),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b11),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
RX_RTS_n
(.oe(tmpOE__RX_RTS_n_net),
.y({1'b0}),
.fb({tmpFB_0__RX_RTS_n_net[0:0]}),
.io({tmpIO_0__RX_RTS_n_net[0:0]}),
.siovref(tmpSIOVREF__RX_RTS_n_net),
.interrupt({Net_542}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__RX_RTS_n_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__RX_CTS_n_net;
wire [0:0] tmpFB_0__RX_CTS_n_net;
wire [0:0] tmpIO_0__RX_CTS_n_net;
wire [0:0] tmpINTERRUPT_0__RX_CTS_n_net;
electrical [0:0] tmpSIOVREF__RX_CTS_n_net;
cy_psoc3_pins_v1_10
#(.id("42a3c2ea-f0b8-4d0c-bf50-a43bc1e1db6a/aedfa372-ccbb-489a-9d67-d67b95d9adc7"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
RX_CTS_n
(.oe(tmpOE__RX_CTS_n_net),
.y({1'b0}),
.fb({tmpFB_0__RX_CTS_n_net[0:0]}),
.io({tmpIO_0__RX_CTS_n_net[0:0]}),
.siovref(tmpSIOVREF__RX_CTS_n_net),
.interrupt({tmpINTERRUPT_0__RX_CTS_n_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__RX_CTS_n_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__TX_RTS_n_net;
wire [0:0] tmpFB_0__TX_RTS_n_net;
wire [0:0] tmpIO_0__TX_RTS_n_net;
wire [0:0] tmpINTERRUPT_0__TX_RTS_n_net;
electrical [0:0] tmpSIOVREF__TX_RTS_n_net;
cy_psoc3_pins_v1_10
#(.id("42a3c2ea-f0b8-4d0c-bf50-a43bc1e1db6a/52d1081a-4b5a-4078-8e67-f4f9a3e0209d"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
TX_RTS_n
(.oe(tmpOE__TX_RTS_n_net),
.y({1'b0}),
.fb({tmpFB_0__TX_RTS_n_net[0:0]}),
.io({tmpIO_0__TX_RTS_n_net[0:0]}),
.siovref(tmpSIOVREF__TX_RTS_n_net),
.interrupt({tmpINTERRUPT_0__TX_RTS_n_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__TX_RTS_n_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__TX_CTS_n_net;
wire [0:0] tmpFB_0__TX_CTS_n_net;
wire [0:0] tmpIO_0__TX_CTS_n_net;
wire [0:0] tmpINTERRUPT_0__TX_CTS_n_net;
electrical [0:0] tmpSIOVREF__TX_CTS_n_net;
cy_psoc3_pins_v1_10
#(.id("42a3c2ea-f0b8-4d0c-bf50-a43bc1e1db6a/16e1e3e6-3865-4bb9-bb8c-3f92d51bf7af"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
TX_CTS_n
(.oe(tmpOE__TX_CTS_n_net),
.y({1'b0}),
.fb({tmpFB_0__TX_CTS_n_net[0:0]}),
.io({tmpIO_0__TX_CTS_n_net[0:0]}),
.siovref(tmpSIOVREF__TX_CTS_n_net),
.interrupt({tmpINTERRUPT_0__TX_CTS_n_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__TX_CTS_n_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__TimeN_net;
wire [0:0] tmpFB_0__TimeN_net;
wire [0:0] tmpIO_0__TimeN_net;
wire [0:0] tmpINTERRUPT_0__TimeN_net;
electrical [0:0] tmpSIOVREF__TimeN_net;
cy_psoc3_pins_v1_10
#(.id("42a3c2ea-f0b8-4d0c-bf50-a43bc1e1db6a/0818fd13-68e2-43ac-afc2-87e7ba6f6425"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
TimeN
(.oe(tmpOE__TimeN_net),
.y({1'b0}),
.fb({tmpFB_0__TimeN_net[0:0]}),
.io({tmpIO_0__TimeN_net[0:0]}),
.siovref(tmpSIOVREF__TimeN_net),
.interrupt({tmpINTERRUPT_0__TimeN_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__TimeN_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_isr_v1_0
#(.int_type(2'b10))
isr_RX_RTSn
(.int_signal(Net_542));
wire [0:0] tmpOE__External_VRef_net;
wire [0:0] tmpFB_0__External_VRef_net;
wire [0:0] tmpIO_0__External_VRef_net;
wire [0:0] tmpINTERRUPT_0__External_VRef_net;
electrical [0:0] tmpSIOVREF__External_VRef_net;
cy_psoc3_pins_v1_10
#(.id("42a3c2ea-f0b8-4d0c-bf50-a43bc1e1db6a/52f31aa9-2f0a-497d-9a1f-1424095e13e6"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
External_VRef
(.oe(tmpOE__External_VRef_net),
.y({1'b0}),
.fb({tmpFB_0__External_VRef_net[0:0]}),
.io({tmpIO_0__External_VRef_net[0:0]}),
.siovref(tmpSIOVREF__External_VRef_net),
.interrupt({tmpINTERRUPT_0__External_VRef_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__External_VRef_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
I2C_v3_30_3 I2C_0 (
.sda(Net_625),
.scl(Net_626),
.clock(1'b0),
.reset(1'b0),
.bclk(Net_629),
.iclk(Net_630),
.scl_i(1'b0),
.sda_i(1'b0),
.scl_o(Net_633),
.sda_o(Net_634),
.itclk(Net_635));
wire [0:0] tmpOE__I2C_0_SDA_net;
wire [0:0] tmpFB_0__I2C_0_SDA_net;
wire [0:0] tmpINTERRUPT_0__I2C_0_SDA_net;
electrical [0:0] tmpSIOVREF__I2C_0_SDA_net;
cy_psoc3_pins_v1_10
#(.id("42a3c2ea-f0b8-4d0c-bf50-a43bc1e1db6a/5c1decb5-69e3-4a8d-bb0c-281221d15217"),
.drive_mode(3'b100),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
I2C_0_SDA
(.oe(tmpOE__I2C_0_SDA_net),
.y({1'b0}),
.fb({tmpFB_0__I2C_0_SDA_net[0:0]}),
.io({Net_625}),
.siovref(tmpSIOVREF__I2C_0_SDA_net),
.interrupt({tmpINTERRUPT_0__I2C_0_SDA_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__I2C_0_SDA_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__I2C_0_SCL_net;
wire [0:0] tmpFB_0__I2C_0_SCL_net;
wire [0:0] tmpINTERRUPT_0__I2C_0_SCL_net;
electrical [0:0] tmpSIOVREF__I2C_0_SCL_net;
cy_psoc3_pins_v1_10
#(.id("42a3c2ea-f0b8-4d0c-bf50-a43bc1e1db6a/25518df9-7fe0-4da6-8dbf-d2a9e2ed11c1"),
.drive_mode(3'b100),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
I2C_0_SCL
(.oe(tmpOE__I2C_0_SCL_net),
.y({1'b0}),
.fb({tmpFB_0__I2C_0_SCL_net[0:0]}),
.io({Net_626}),
.siovref(tmpSIOVREF__I2C_0_SCL_net),
.interrupt({tmpINTERRUPT_0__I2C_0_SCL_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__I2C_0_SCL_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__NEO_RTC_INT1_net;
wire [0:0] tmpFB_0__NEO_RTC_INT1_net;
wire [0:0] tmpIO_0__NEO_RTC_INT1_net;
electrical [0:0] tmpSIOVREF__NEO_RTC_INT1_net;
cy_psoc3_pins_v1_10
#(.id("42a3c2ea-f0b8-4d0c-bf50-a43bc1e1db6a/94c29172-218c-472e-b77b-9668892b6f11"),
.drive_mode(3'b010),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b10),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
NEO_RTC_INT1
(.oe(tmpOE__NEO_RTC_INT1_net),
.y({1'b0}),
.fb({tmpFB_0__NEO_RTC_INT1_net[0:0]}),
.io({tmpIO_0__NEO_RTC_INT1_net[0:0]}),
.siovref(tmpSIOVREF__NEO_RTC_INT1_net),
.interrupt({Net_636}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__NEO_RTC_INT1_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_isr_v1_0
#(.int_type(2'b00))
isr_rtc_int1
(.int_signal(Net_636));
wire [0:0] tmpOE__SD_Card_Power_net;
wire [0:0] tmpFB_0__SD_Card_Power_net;
wire [0:0] tmpIO_0__SD_Card_Power_net;
wire [0:0] tmpINTERRUPT_0__SD_Card_Power_net;
electrical [0:0] tmpSIOVREF__SD_Card_Power_net;
cy_psoc3_pins_v1_10
#(.id("42a3c2ea-f0b8-4d0c-bf50-a43bc1e1db6a/37615ece-52ed-4b08-a3cb-e053c56b7928"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
SD_Card_Power
(.oe(tmpOE__SD_Card_Power_net),
.y({1'b0}),
.fb({tmpFB_0__SD_Card_Power_net[0:0]}),
.io({tmpIO_0__SD_Card_Power_net[0:0]}),
.siovref(tmpSIOVREF__SD_Card_Power_net),
.interrupt({tmpINTERRUPT_0__SD_Card_Power_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__SD_Card_Power_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
Counter_v2_40_4 DELAY_COUNTER (
.reset(Net_648),
.tc(Net_665),
.comp(Net_666),
.clock(Net_651),
.interrupt(Net_660),
.enable(1'b0),
.capture(1'b0),
.upCnt(1'b0),
.downCnt(1'b0),
.up_ndown(1'b1),
.count(1'b0));
defparam DELAY_COUNTER.CaptureMode = 0;
defparam DELAY_COUNTER.ClockMode = 3;
defparam DELAY_COUNTER.CompareMode = 1;
defparam DELAY_COUNTER.CompareStatusEdgeSense = 1;
defparam DELAY_COUNTER.EnableMode = 0;
defparam DELAY_COUNTER.ReloadOnCapture = 0;
defparam DELAY_COUNTER.ReloadOnCompare = 0;
defparam DELAY_COUNTER.ReloadOnOverUnder = 1;
defparam DELAY_COUNTER.ReloadOnReset = 1;
defparam DELAY_COUNTER.Resolution = 16;
defparam DELAY_COUNTER.RunMode = 0;
defparam DELAY_COUNTER.UseInterrupt = 1;
assign Net_648 = 1'h0;
cy_isr_v1_0
#(.int_type(2'b10))
isr_packet_delay
(.int_signal(Net_660));
cy_clock_v1_0
#(.id("42a3c2ea-f0b8-4d0c-bf50-a43bc1e1db6a/96bd6326-bc84-40d3-a080-adae5cf2aa35"),
.source_clock_id(""),
.divisor(0),
.period("83333333333.3333"),
.is_direct(0),
.is_digital(1))
Clock_1
(.clock_out(Net_651));
endmodule
// Component: B_SPI_Master_v2_40
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_40"
`include "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_40\B_SPI_Master_v2_40.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_40"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_40\B_SPI_Master_v2_40.v"
`endif
// SPI_Master_v2_40(BidirectMode=false, ClockInternal=false, CtlModeReplacementString=SyncCtl, CyGetRegReplacementString=CY_GET_REG8, CySetRegReplacementString=CY_SET_REG8, DesiredBitRate=1000000, HighSpeedMode=true, InternalClockUsed=0, InternalInterruptEnabled=0, InternalRxInterruptEnabled=0, InternalTxInterruptEnabled=0, InterruptOnByteComplete=false, InterruptOnRXFull=false, InterruptOnRXNotEmpty=false, InterruptOnRXOverrun=false, InterruptOnSPIDone=false, InterruptOnSPIIdle=false, InterruptOnTXEmpty=false, InterruptOnTXNotFull=false, IntOnByteComp=0, IntOnRXFull=0, IntOnRXNotEmpty=0, IntOnRXOver=0, IntOnSPIDone=0, IntOnSPIIdle=0, IntOnTXEmpty=0, IntOnTXNotFull=0, Mode=1, ModeUseZero=1, NumberOfDataBits=8, RegDefReplacementString=reg8, RegSizeReplacementString=uint8, RxBufferSize=4, ShiftDir=0, TxBufferSize=4, UseInternalInterrupt=false, UseRxInternalInterrupt=false, UseTxInternalInterrupt=false, VerilogSectionReplacementString=sR8, CY_COMPONENT_NAME=SPI_Master_v2_40, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=emFile_1:SPI0, CY_INSTANCE_SHORT_NAME=SPI0, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=40, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=emFile_1_SPI0, )
module SPI_Master_v2_40_6 (
clock,
reset,
miso,
sclk,
mosi,
ss,
rx_interrupt,
sdat,
tx_interrupt);
input clock;
input reset;
input miso;
output sclk;
output mosi;
output ss;
output rx_interrupt;
inout sdat;
output tx_interrupt;
parameter BidirectMode = 0;
parameter HighSpeedMode = 1;
parameter NumberOfDataBits = 8;
parameter ShiftDir = 0;
wire Net_257;
wire Net_273;
wire Net_274;
wire Net_244;
wire Net_239;
wire Net_253;
wire Net_161;
wire Net_276;
// VirtualMux_1 (cy_virtualmux_v1_0)
assign Net_276 = clock;
B_SPI_Master_v2_40 BSPIM (
.sclk(sclk),
.ss(ss),
.miso(Net_244),
.clock(Net_276),
.reset(Net_273),
.rx_interpt(rx_interrupt),
.tx_enable(Net_253),
.mosi(mosi),
.tx_interpt(tx_interrupt));
defparam BSPIM.BidirectMode = 0;
defparam BSPIM.HighSpeedMode = 1;
defparam BSPIM.ModeCPHA = 0;
defparam BSPIM.ModePOL = 0;
defparam BSPIM.NumberOfDataBits = 8;
defparam BSPIM.ShiftDir = 0;
// VirtualMux_2 (cy_virtualmux_v1_0)
assign Net_244 = miso;
// VirtualMux_3 (cy_virtualmux_v1_0)
assign Net_273 = Net_274;
ZeroTerminal ZeroTerminal_1 (
.z(Net_274));
endmodule
// emFile_v1_20(Max_SPI_Frequency=4000, NumberSDCards=1, WP0_En=false, WP1_En=false, WP2_En=false, WP3_En=false, CY_COMPONENT_NAME=emFile_v1_20, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=emFile_1, CY_INSTANCE_SHORT_NAME=emFile_1, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=20, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=emFile_1, )
module emFile_v1_20_7 ;
wire Net_31;
wire Net_30;
wire Net_29;
wire Net_28;
wire Net_27;
wire Net_26;
wire Net_24;
wire Net_23;
wire Net_21;
wire Net_20;
wire Net_18;
wire Net_17;
wire Net_14;
wire Net_13;
wire Net_12;
wire Net_11;
wire Net_9;
wire Net_8;
wire Net_6;
wire Net_5;
wire Net_4;
wire Net_3;
wire Net_2;
wire Net_1;
wire Net_58;
wire Net_57;
wire Net_55;
wire Net_54;
wire Net_43;
wire Net_42;
wire Net_40;
wire Net_39;
wire Net_83;
wire Net_81;
wire Net_80;
wire Net_66;
wire Net_19;
wire Net_16;
wire Net_22;
wire Net_10;
SPI_Master_v2_40_6 SPI0 (
.mosi(Net_10),
.sclk(Net_22),
.ss(Net_1),
.miso(Net_16),
.clock(Net_19),
.reset(Net_2),
.rx_interrupt(Net_3),
.sdat(Net_4),
.tx_interrupt(Net_5));
defparam SPI0.BidirectMode = 0;
defparam SPI0.HighSpeedMode = 1;
defparam SPI0.NumberOfDataBits = 8;
defparam SPI0.ShiftDir = 0;
wire [0:0] tmpOE__mosi0_net;
wire [0:0] tmpFB_0__mosi0_net;
wire [0:0] tmpIO_0__mosi0_net;
wire [0:0] tmpINTERRUPT_0__mosi0_net;
electrical [0:0] tmpSIOVREF__mosi0_net;
cy_psoc3_pins_v1_10
#(.id("62946763-63ac-47e7-8754-b206ba7765cc/ed092b9b-d398-4703-be89-cebf998501f6"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
mosi0
(.oe(tmpOE__mosi0_net),
.y({Net_10}),
.fb({tmpFB_0__mosi0_net[0:0]}),
.io({tmpIO_0__mosi0_net[0:0]}),
.siovref(tmpSIOVREF__mosi0_net),
.interrupt({tmpINTERRUPT_0__mosi0_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__mosi0_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_clock_v1_0
#(.id("62946763-63ac-47e7-8754-b206ba7765cc/5ed615c6-e1f0-40ed-8816-f906ef67d531"),
.source_clock_id("61737EF6-3B74-48f9-8B91-F7473A442AE7"),
.divisor(1),
.period("0"),
.is_direct(0),
.is_digital(1))
Clock_1
(.clock_out(Net_19));
wire [0:0] tmpOE__miso0_net;
wire [0:0] tmpIO_0__miso0_net;
wire [0:0] tmpINTERRUPT_0__miso0_net;
electrical [0:0] tmpSIOVREF__miso0_net;
cy_psoc3_pins_v1_10
#(.id("62946763-63ac-47e7-8754-b206ba7765cc/1425177d-0d0e-4468-8bcc-e638e5509a9b"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
miso0
(.oe(tmpOE__miso0_net),
.y({1'b0}),
.fb({Net_16}),
.io({tmpIO_0__miso0_net[0:0]}),
.siovref(tmpSIOVREF__miso0_net),
.interrupt({tmpINTERRUPT_0__miso0_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__miso0_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
ZeroTerminal ZeroTerminal_1 (
.z(Net_2));
wire [0:0] tmpOE__sclk0_net;
wire [0:0] tmpFB_0__sclk0_net;
wire [0:0] tmpIO_0__sclk0_net;
wire [0:0] tmpINTERRUPT_0__sclk0_net;
electrical [0:0] tmpSIOVREF__sclk0_net;
cy_psoc3_pins_v1_10
#(.id("62946763-63ac-47e7-8754-b206ba7765cc/ae249072-87dc-41aa-9405-888517aefa28"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
sclk0
(.oe(tmpOE__sclk0_net),
.y({Net_22}),
.fb({tmpFB_0__sclk0_net[0:0]}),
.io({tmpIO_0__sclk0_net[0:0]}),
.siovref(tmpSIOVREF__sclk0_net),
.interrupt({tmpINTERRUPT_0__sclk0_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__sclk0_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__SPI0_CS_net;
wire [0:0] tmpFB_0__SPI0_CS_net;
wire [0:0] tmpIO_0__SPI0_CS_net;
wire [0:0] tmpINTERRUPT_0__SPI0_CS_net;
electrical [0:0] tmpSIOVREF__SPI0_CS_net;
cy_psoc3_pins_v1_10
#(.id("62946763-63ac-47e7-8754-b206ba7765cc/6df85302-e45f-45fb-97de-4bdf3128e07b"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
SPI0_CS
(.oe(tmpOE__SPI0_CS_net),
.y({1'b0}),
.fb({tmpFB_0__SPI0_CS_net[0:0]}),
.io({tmpIO_0__SPI0_CS_net[0:0]}),
.siovref(tmpSIOVREF__SPI0_CS_net),
.interrupt({tmpINTERRUPT_0__SPI0_CS_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__SPI0_CS_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
endmodule
// Component: bI2C_v3_30
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\bI2C_v3_30"
`include "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\bI2C_v3_30\bI2C_v3_30.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\bI2C_v3_30"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\bI2C_v3_30\bI2C_v3_30.v"
`endif
// I2C_v3_30(Address_Decode=1, BusSpeed_kHz=100, ClockInputVisibility=false, CtlModeReplacementString=SyncCtl, EnableWakeup=false, ExternalBuffer=false, Externi2cIntrHandler=false, ExternTmoutIntrHandler=false, FF=false, Hex=false, I2C_Mode=2, I2cBusPort=0, Implementation=0, InternalUdbClockToleranceMinus=25, InternalUdbClockTolerancePlus=5, NotSlaveClockMinusTolerance=25, NotSlaveClockPlusTolerance=5, PrescalerEnabled=false, PrescalerPeriod=3, Psoc3ffSelected=false, Psoc5AffSelected=false, Psoc5lpffSelected=false, RemoveI2cff=true, RemoveI2cUdb=false, RemoveIntClock=false, RemoveTimeoutTimer=true, SclTimeoutEnabled=false, SdaTimeoutEnabled=false, Slave_Address=8, SlaveClockMinusTolerance=5, SlaveClockPlusTolerance=50, TimeoutEnabled=false, TimeoutImplementation=0, TimeOutms=25, TimeoutPeriodff=39999, TimeoutPeriodUdb=39999, UDB_MSTR=true, UDB_MULTI_MASTER_SLAVE=false, UDB_SLV=false, UdbInternalClock=true, UdbRequiredClock=1600, UdbSlaveFixedPlacementEnable=false, CY_COMPONENT_NAME=I2C_v3_30, CY_CONTROL_FILE=I2C_Slave_DefaultPlacement.ctl, CY_FITTER_NAME=I2C_1, CY_INSTANCE_SHORT_NAME=I2C_1, CY_MAJOR_VERSION=3, CY_MINOR_VERSION=30, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=I2C_1, )
module I2C_v3_30_8 (
sda_o,
scl_o,
sda_i,
scl_i,
iclk,
bclk,
reset,
clock,
scl,
sda,
itclk);
output sda_o;
output scl_o;
input sda_i;
input scl_i;
output iclk;
output bclk;
input reset;
input clock;
inout scl;
inout sda;
output itclk;
wire sda_x_wire;
wire sda_yfb;
wire udb_clk;
wire Net_975;
wire Net_974;
wire Net_973;
wire bus_clk;
wire Net_972;
wire Net_968;
wire scl_yfb;
wire Net_969;
wire Net_971;
wire Net_970;
wire timeout_clk;
wire Net_697;
wire Net_1045;
wire [1:0] Net_1109;
wire [5:0] Net_643;
wire scl_x_wire;
// Vmux_sda_out (cy_virtualmux_v1_0)
assign sda_x_wire = Net_643[4];
cy_isr_v1_0
#(.int_type(2'b00))
I2C_IRQ
(.int_signal(Net_697));
// Vmux_interrupt (cy_virtualmux_v1_0)
assign Net_697 = Net_643[5];
cy_clock_v1_0
#(.id("6f2d57bd-b6d0-4115-93da-ded3485bf4ed/be0a0e37-ad17-42ca-b5a1-1a654d736358"),
.source_clock_id(""),
.divisor(0),
.period("625000000"),
.is_direct(0),
.is_digital(1))
IntClock
(.clock_out(Net_970));
bI2C_v3_30 bI2C_UDB (
.clock(udb_clk),
.scl_in(Net_1109[0]),
.sda_in(Net_1109[1]),
.sda_out(Net_643[4]),
.scl_out(Net_643[3]),
.interrupt(Net_643[5]),
.reset(reset));
defparam bI2C_UDB.Mode = 2;
// Vmux_scl_out (cy_virtualmux_v1_0)
assign scl_x_wire = Net_643[3];
OneTerminal OneTerminal_1 (
.o(Net_969));
OneTerminal OneTerminal_2 (
.o(Net_968));
// Vmux_clock (cy_virtualmux_v1_0)
assign udb_clk = Net_970;
assign bclk = bus_clk | Net_973;
ZeroTerminal ZeroTerminal_1 (
.z(Net_973));
assign iclk = udb_clk | Net_974;
ZeroTerminal ZeroTerminal_2 (
.z(Net_974));
// Vmux_scl_in (cy_virtualmux_v1_0)
assign Net_1109[0] = scl_yfb;
// Vmux_sda_in (cy_virtualmux_v1_0)
assign Net_1109[1] = sda_yfb;
wire [0:0] tmpOE__Bufoe_scl_net;
cy_bufoe
Bufoe_scl
(.x(scl_x_wire),
.y(scl),
.oe(tmpOE__Bufoe_scl_net),
.yfb(scl_yfb));
assign tmpOE__Bufoe_scl_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{Net_969} : {Net_969};
wire [0:0] tmpOE__Bufoe_sda_net;
cy_bufoe
Bufoe_sda
(.x(sda_x_wire),
.y(sda),
.oe(tmpOE__Bufoe_sda_net),
.yfb(sda_yfb));
assign tmpOE__Bufoe_sda_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{Net_968} : {Net_968};
// Vmux_timeout_clock (cy_virtualmux_v1_0)
assign timeout_clk = udb_clk;
assign itclk = timeout_clk | Net_975;
ZeroTerminal ZeroTerminal_3 (
.z(Net_975));
assign scl_o = scl_x_wire;
assign sda_o = sda_x_wire;
endmodule
// top
module top ;
wire Net_147;
wire Net_146;
wire Net_145;
wire Net_144;
wire Net_143;
wire Net_142;
wire Net_141;
wire Net_140;
wire Net_139;
wire Net_129;
wire Net_128;
wire Net_113;
wire Net_112;
wire Net_111;
wire Net_110;
wire Net_109;
wire Net_44;
wire Net_108;
wire Net_107;
wire Net_106;
wire Net_105;
wire Net_104;
wire Net_103;
wire Net_66;
wire Net_65;
wire Net_64;
wire Net_63;
wire Net_62;
wire Net_61;
wire Net_60;
wire Net_59;
wire Net_58;
wire Net_57;
wire Net_56;
wire Net_97;
wire Net_7;
wire Net_35;
UART_v2_30_0 UART_SoilMoisture_Decagon (
.cts_n(1'b0),
.tx(Net_57),
.rts_n(Net_58),
.tx_en(Net_59),
.clock(1'b0),
.reset(1'b0),
.rx(Net_7),
.tx_interrupt(Net_62),
.rx_interrupt(Net_35),
.tx_data(Net_63),
.tx_clk(Net_64),
.rx_data(Net_65),
.rx_clk(Net_66));
defparam UART_SoilMoisture_Decagon.Address1 = 0;
defparam UART_SoilMoisture_Decagon.Address2 = 0;
defparam UART_SoilMoisture_Decagon.EnIntRXInterrupt = 0;
defparam UART_SoilMoisture_Decagon.EnIntTXInterrupt = 0;
defparam UART_SoilMoisture_Decagon.FlowControl = 0;
defparam UART_SoilMoisture_Decagon.HalfDuplexEn = 0;
defparam UART_SoilMoisture_Decagon.HwTXEnSignal = 1;
defparam UART_SoilMoisture_Decagon.NumDataBits = 8;
defparam UART_SoilMoisture_Decagon.NumStopBits = 1;
defparam UART_SoilMoisture_Decagon.ParityType = 0;
defparam UART_SoilMoisture_Decagon.RXEnable = 1;
defparam UART_SoilMoisture_Decagon.TXEnable = 0;
wire [0:0] tmpOE__Rx_SoilMoisture_Decagon_net;
wire [0:0] tmpIO_0__Rx_SoilMoisture_Decagon_net;
wire [0:0] tmpINTERRUPT_0__Rx_SoilMoisture_Decagon_net;
electrical [0:0] tmpSIOVREF__Rx_SoilMoisture_Decagon_net;
cy_psoc3_pins_v1_10
#(.id("1425177d-0d0e-4468-8bcc-e638e5509a9b"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
Rx_SoilMoisture_Decagon
(.oe(tmpOE__Rx_SoilMoisture_Decagon_net),
.y({1'b0}),
.fb({Net_7}),
.io({tmpIO_0__Rx_SoilMoisture_Decagon_net[0:0]}),
.siovref(tmpSIOVREF__Rx_SoilMoisture_Decagon_net),
.interrupt({tmpINTERRUPT_0__Rx_SoilMoisture_Decagon_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Rx_SoilMoisture_Decagon_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
UART_v2_30_1 UART_Ultrasonic_Maxbotix (
.cts_n(1'b0),
.tx(Net_104),
.rts_n(Net_105),
.tx_en(Net_106),
.clock(1'b0),
.reset(1'b0),
.rx(Net_44),
.tx_interrupt(Net_109),
.rx_interrupt(Net_97),
.tx_data(Net_110),
.tx_clk(Net_111),
.rx_data(Net_112),
.rx_clk(Net_113));
defparam UART_Ultrasonic_Maxbotix.Address1 = 0;
defparam UART_Ultrasonic_Maxbotix.Address2 = 0;
defparam UART_Ultrasonic_Maxbotix.EnIntRXInterrupt = 0;
defparam UART_Ultrasonic_Maxbotix.EnIntTXInterrupt = 0;
defparam UART_Ultrasonic_Maxbotix.FlowControl = 0;
defparam UART_Ultrasonic_Maxbotix.HalfDuplexEn = 0;
defparam UART_Ultrasonic_Maxbotix.HwTXEnSignal = 1;
defparam UART_Ultrasonic_Maxbotix.NumDataBits = 8;
defparam UART_Ultrasonic_Maxbotix.NumStopBits = 1;
defparam UART_Ultrasonic_Maxbotix.ParityType = 0;
defparam UART_Ultrasonic_Maxbotix.RXEnable = 1;
defparam UART_Ultrasonic_Maxbotix.TXEnable = 0;
wire [0:0] tmpOE__Rx_Depth_Maxbotix_net;
wire [0:0] tmpIO_0__Rx_Depth_Maxbotix_net;
wire [0:0] tmpINTERRUPT_0__Rx_Depth_Maxbotix_net;
electrical [0:0] tmpSIOVREF__Rx_Depth_Maxbotix_net;
cy_psoc3_pins_v1_10
#(.id("3e017343-901d-4f28-862c-3c6b5cdd94b9"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
Rx_Depth_Maxbotix
(.oe(tmpOE__Rx_Depth_Maxbotix_net),
.y({1'b0}),
.fb({Net_44}),
.io({tmpIO_0__Rx_Depth_Maxbotix_net[0:0]}),
.siovref(tmpSIOVREF__Rx_Depth_Maxbotix_net),
.interrupt({tmpINTERRUPT_0__Rx_Depth_Maxbotix_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Rx_Depth_Maxbotix_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_isr_v1_0
#(.int_type(2'b10))
isr_Ultrasonic_Maxbotix
(.int_signal(Net_97));
wire [0:0] tmpOE__Decagon_Sensor_Power_net;
wire [0:0] tmpFB_0__Decagon_Sensor_Power_net;
wire [0:0] tmpIO_0__Decagon_Sensor_Power_net;
wire [0:0] tmpINTERRUPT_0__Decagon_Sensor_Power_net;
electrical [0:0] tmpSIOVREF__Decagon_Sensor_Power_net;
cy_psoc3_pins_v1_10
#(.id("3dba336a-f6a5-43fb-aed3-de1e0b7bf362"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
Decagon_Sensor_Power
(.oe(tmpOE__Decagon_Sensor_Power_net),
.y({1'b0}),
.fb({tmpFB_0__Decagon_Sensor_Power_net[0:0]}),
.io({tmpIO_0__Decagon_Sensor_Power_net[0:0]}),
.siovref(tmpSIOVREF__Decagon_Sensor_Power_net),
.interrupt({tmpINTERRUPT_0__Decagon_Sensor_Power_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Decagon_Sensor_Power_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_isr_v1_0
#(.int_type(2'b10))
isr_SoilMoisture_Decagon
(.int_signal(Net_35));
NEOMOTE_5 NEOMOTE_1 ();
emFile_v1_20_7 emFile_1 ();
wire [0:0] tmpOE__SDA_1_net;
wire [0:0] tmpFB_0__SDA_1_net;
wire [0:0] tmpINTERRUPT_0__SDA_1_net;
electrical [0:0] tmpSIOVREF__SDA_1_net;
cy_psoc3_pins_v1_10
#(.id("22863ebe-a37b-476f-b252-6e49a8c00b12"),
.drive_mode(3'b100),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
SDA_1
(.oe(tmpOE__SDA_1_net),
.y({1'b0}),
.fb({tmpFB_0__SDA_1_net[0:0]}),
.io({Net_128}),
.siovref(tmpSIOVREF__SDA_1_net),
.interrupt({tmpINTERRUPT_0__SDA_1_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__SDA_1_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__SCL_1_net;
wire [0:0] tmpFB_0__SCL_1_net;
wire [0:0] tmpINTERRUPT_0__SCL_1_net;
electrical [0:0] tmpSIOVREF__SCL_1_net;
cy_psoc3_pins_v1_10
#(.id("02f2cf2c-2c7a-49df-9246-7a3435c21be3"),
.drive_mode(3'b100),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
SCL_1
(.oe(tmpOE__SCL_1_net),
.y({1'b0}),
.fb({tmpFB_0__SCL_1_net[0:0]}),
.io({Net_129}),
.siovref(tmpSIOVREF__SCL_1_net),
.interrupt({tmpINTERRUPT_0__SCL_1_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__SCL_1_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
I2C_v3_30_8 I2C_1 (
.sda(Net_128),
.scl(Net_129),
.clock(1'b0),
.reset(1'b0),
.bclk(Net_141),
.iclk(Net_142),
.scl_i(1'b0),
.sda_i(1'b0),
.scl_o(Net_145),
.sda_o(Net_146),
.itclk(Net_147));
wire [0:0] tmpOE__Digital_Sensor_Power_net;
wire [0:0] tmpFB_0__Digital_Sensor_Power_net;
wire [0:0] tmpIO_0__Digital_Sensor_Power_net;
wire [0:0] tmpINTERRUPT_0__Digital_Sensor_Power_net;
electrical [0:0] tmpSIOVREF__Digital_Sensor_Power_net;
cy_psoc3_pins_v1_10
#(.id("b4d82f45-d2ff-4880-ba26-f4781b7e5d27"),
.drive_mode(3'b010),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
Digital_Sensor_Power
(.oe(tmpOE__Digital_Sensor_Power_net),
.y({1'b0}),
.fb({tmpFB_0__Digital_Sensor_Power_net[0:0]}),
.io({tmpIO_0__Digital_Sensor_Power_net[0:0]}),
.siovref(tmpSIOVREF__Digital_Sensor_Power_net),
.interrupt({tmpINTERRUPT_0__Digital_Sensor_Power_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Digital_Sensor_Power_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
endmodule
|
(* We want a dependently typed recursive function. The output type is itself
described by a recursive function. *)
Fixpoint bool_nat_type (n:nat) : Set :=
match n with 0 => nat | 1 => bool | S (S n) => bool_nat_type n end.
(* The difficult point is to describe the computation at each
recursive step, knowing that sometimes this computation deals with
boolean values, while at other times it deals with integer
values. The trick is to discover that computations can actually
always be described by the same function as for the
pre-predecessor.
A dependently typed pattern-matching construct is need. *)
Require Import Bool.
Fixpoint bool_nat_fun_aux (n:nat) : bool_nat_type n -> bool_nat_type n :=
match n return bool_nat_type n -> bool_nat_type n with
0 => S | 1 => negb | S (S n) => bool_nat_fun_aux n
end.
(* The function is then easy to describe. We can use "Eval compute"
to check that its value is always as required. *)
Fixpoint bool_nat_fun (n:nat) : bool_nat_type n :=
match n return bool_nat_type n with
0 => 0
| 1 => true
| S (S n) => bool_nat_fun_aux n (bool_nat_fun n)
end.
Eval compute in (bool_nat_fun 6).
Eval compute in (bool_nat_fun 7).
Eval compute in (bool_nat_fun 9).
Eval compute in (bool_nat_fun 7 : bool).
Eval compute in (bool_nat_fun 6 : nat).
(* Defining a function of this form was fun, but will it ever be
useful? *)
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Test_Line.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Test_Line (
address,
clock,
q);
input [0:0] address;
input clock;
output [7:0] q;
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "Test_Line.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=line",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 1,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "line"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "Test_Line.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "1"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "Test_Line.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=line"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 1 0 INPUT NODEFVAL address[0..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: CONNECT: @address_a 0 0 1 0 address 0 0 1 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_Line.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_Line.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_Line.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_Line.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_Line_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_Line_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_Line_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_Line_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//======================================================================
//
// sha256_w_mem_regs.v
// -------------------
// The W memory. This version uses 16 32-bit registers as a sliding
// window to generate the 64 words.
//
//======================================================================
module sha256_w_mem(
input wire clk,
input wire reset_n,
input wire [511 : 0] block,
input wire init,
input wire next,
output wire [31 : 0] w
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter CTRL_IDLE = 0;
parameter CTRL_UPDATE = 1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] w_mem [0 : 15];
reg [31 : 0] w_mem00_new;
reg [31 : 0] w_mem01_new;
reg [31 : 0] w_mem02_new;
reg [31 : 0] w_mem03_new;
reg [31 : 0] w_mem04_new;
reg [31 : 0] w_mem05_new;
reg [31 : 0] w_mem06_new;
reg [31 : 0] w_mem07_new;
reg [31 : 0] w_mem08_new;
reg [31 : 0] w_mem09_new;
reg [31 : 0] w_mem10_new;
reg [31 : 0] w_mem11_new;
reg [31 : 0] w_mem12_new;
reg [31 : 0] w_mem13_new;
reg [31 : 0] w_mem14_new;
reg [31 : 0] w_mem15_new;
reg w_mem_we;
reg [5 : 0] w_ctr_reg;
reg [5 : 0] w_ctr_new;
reg w_ctr_we;
reg w_ctr_inc;
reg w_ctr_rst;
reg [1 : 0] sha256_w_mem_ctrl_reg;
reg [1 : 0] sha256_w_mem_ctrl_new;
reg sha256_w_mem_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] w_tmp;
reg [31 : 0] w_new;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign w = w_tmp;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
w_mem[00] <= 32'h0;
w_mem[01] <= 32'h0;
w_mem[02] <= 32'h0;
w_mem[03] <= 32'h0;
w_mem[04] <= 32'h0;
w_mem[05] <= 32'h0;
w_mem[06] <= 32'h0;
w_mem[07] <= 32'h0;
w_mem[08] <= 32'h0;
w_mem[09] <= 32'h0;
w_mem[10] <= 32'h0;
w_mem[11] <= 32'h0;
w_mem[12] <= 32'h0;
w_mem[13] <= 32'h0;
w_mem[14] <= 32'h0;
w_mem[15] <= 32'h0;
w_ctr_reg <= 6'h00;
sha256_w_mem_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (w_mem_we)
begin
w_mem[00] <= w_mem00_new;
w_mem[01] <= w_mem01_new;
w_mem[02] <= w_mem02_new;
w_mem[03] <= w_mem03_new;
w_mem[04] <= w_mem04_new;
w_mem[05] <= w_mem05_new;
w_mem[06] <= w_mem06_new;
w_mem[07] <= w_mem07_new;
w_mem[08] <= w_mem08_new;
w_mem[09] <= w_mem09_new;
w_mem[10] <= w_mem10_new;
w_mem[11] <= w_mem11_new;
w_mem[12] <= w_mem12_new;
w_mem[13] <= w_mem13_new;
w_mem[14] <= w_mem14_new;
w_mem[15] <= w_mem15_new;
end
if (w_ctr_we)
w_ctr_reg <= w_ctr_new;
if (sha256_w_mem_ctrl_we)
sha256_w_mem_ctrl_reg <= sha256_w_mem_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// select_w
//
// Mux for the external read operation. This is where we exract
// the W variable.
//----------------------------------------------------------------
always @*
begin : select_w
if (w_ctr_reg < 16)
begin
w_tmp = w_mem[w_ctr_reg[3 : 0]];
end
else
begin
w_tmp = w_new;
end
end // select_w
//----------------------------------------------------------------
// w_new_logic
//
// Logic that calculates the next value to be inserted into
// the sliding window of the memory.
//----------------------------------------------------------------
always @*
begin : w_mem_update_logic
reg [31 : 0] w_0;
reg [31 : 0] w_1;
reg [31 : 0] w_9;
reg [31 : 0] w_14;
reg [31 : 0] d0;
reg [31 : 0] d1;
w_mem00_new = 32'h0;
w_mem01_new = 32'h0;
w_mem02_new = 32'h0;
w_mem03_new = 32'h0;
w_mem04_new = 32'h0;
w_mem05_new = 32'h0;
w_mem06_new = 32'h0;
w_mem07_new = 32'h0;
w_mem08_new = 32'h0;
w_mem09_new = 32'h0;
w_mem10_new = 32'h0;
w_mem11_new = 32'h0;
w_mem12_new = 32'h0;
w_mem13_new = 32'h0;
w_mem14_new = 32'h0;
w_mem15_new = 32'h0;
w_mem_we = 0;
w_0 = w_mem[0];
w_1 = w_mem[1];
w_9 = w_mem[9];
w_14 = w_mem[14];
d0 = {w_1[6 : 0], w_1[31 : 7]} ^
{w_1[17 : 0], w_1[31 : 18]} ^
{3'b000, w_1[31 : 3]};
d1 = {w_14[16 : 0], w_14[31 : 17]} ^
{w_14[18 : 0], w_14[31 : 19]} ^
{10'b0000000000, w_14[31 : 10]};
w_new = d1 + w_9 + d0 + w_0;
if (init)
begin
w_mem00_new = block[511 : 480];
w_mem01_new = block[479 : 448];
w_mem02_new = block[447 : 416];
w_mem03_new = block[415 : 384];
w_mem04_new = block[383 : 352];
w_mem05_new = block[351 : 320];
w_mem06_new = block[319 : 288];
w_mem07_new = block[287 : 256];
w_mem08_new = block[255 : 224];
w_mem09_new = block[223 : 192];
w_mem10_new = block[191 : 160];
w_mem11_new = block[159 : 128];
w_mem12_new = block[127 : 96];
w_mem13_new = block[95 : 64];
w_mem14_new = block[63 : 32];
w_mem15_new = block[31 : 0];
w_mem_we = 1;
end
else if (w_ctr_reg > 15)
begin
w_mem00_new = w_mem[01];
w_mem01_new = w_mem[02];
w_mem02_new = w_mem[03];
w_mem03_new = w_mem[04];
w_mem04_new = w_mem[05];
w_mem05_new = w_mem[06];
w_mem06_new = w_mem[07];
w_mem07_new = w_mem[08];
w_mem08_new = w_mem[09];
w_mem09_new = w_mem[10];
w_mem10_new = w_mem[11];
w_mem11_new = w_mem[12];
w_mem12_new = w_mem[13];
w_mem13_new = w_mem[14];
w_mem14_new = w_mem[15];
w_mem15_new = w_new;
w_mem_we = 1;
end
end // w_mem_update_logic
//----------------------------------------------------------------
// w_ctr
// W schedule adress counter. Counts from 0x10 to 0x3f and
// is used to expand the block into words.
//----------------------------------------------------------------
always @*
begin : w_ctr
w_ctr_new = 0;
w_ctr_we = 0;
if (w_ctr_rst)
begin
w_ctr_new = 6'h00;
w_ctr_we = 1;
end
if (w_ctr_inc)
begin
w_ctr_new = w_ctr_reg + 6'h01;
w_ctr_we = 1;
end
end // w_ctr
//----------------------------------------------------------------
// sha256_w_mem_fsm
// Logic for the w shedule FSM.
//----------------------------------------------------------------
always @*
begin : sha256_w_mem_fsm
w_ctr_rst = 0;
w_ctr_inc = 0;
sha256_w_mem_ctrl_new = CTRL_IDLE;
sha256_w_mem_ctrl_we = 0;
case (sha256_w_mem_ctrl_reg)
CTRL_IDLE:
begin
if (init)
begin
w_ctr_rst = 1;
sha256_w_mem_ctrl_new = CTRL_UPDATE;
sha256_w_mem_ctrl_we = 1;
end
end
CTRL_UPDATE:
begin
if (next)
begin
w_ctr_inc = 1;
end
if (w_ctr_reg == 6'h3f)
begin
sha256_w_mem_ctrl_new = CTRL_IDLE;
sha256_w_mem_ctrl_we = 1;
end
end
endcase // case (sha256_ctrl_reg)
end // sha256_ctrl_fsm
endmodule // sha256_w_mem
//======================================================================
// sha256_mem.v
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_pixelq_op_img_rows_V_channel_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_pixelq_op_img_rows_V_channel (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_pixelq_op_img_rows_V_channel_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_pixelq_op_img_rows_V_channel_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_intr_wr_mem.v
*
* Date : 2012-11
*
* Description : Mimics interconnect for Writes between AFI and DDRC/OCM
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_intr_wr_mem(
sw_clk,
rstn,
full,
WR_DATA_ACK_OCM,
WR_DATA_ACK_DDR,
WR_ADDR,
WR_DATA,
WR_BYTES,
WR_QOS,
WR_DATA_VALID_OCM,
WR_DATA_VALID_DDR
);
`include "processing_system7_bfm_v2_0_local_params.v"
/* local parameters for interconnect wr fifo model */
input sw_clk, rstn;
output full;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output reg [max_burst_bits-1:0] WR_DATA;
output reg [addr_width-1:0] WR_ADDR;
output reg [max_burst_bytes_width:0] WR_BYTES;
output reg [axi_qos_width-1:0] WR_QOS;
reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0;
reg [wr_fifo_data_bits-1:0] wr_fifo [0:intr_max_outstanding-1];
wire empty;
assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0;
assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0;
parameter SEND_DATA = 0, WAIT_ACK = 1;
reg state;
task automatic write_mem;
input [wr_fifo_data_bits-1:0] data;
begin
wr_fifo[wr_ptr[intr_cnt_width-2:0]] = data;
if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
wr_ptr[intr_cnt_width-2:0] = 0;
else
wr_ptr = wr_ptr + 1;
end
endtask
always@(negedge rstn or posedge sw_clk)
begin
if(!rstn) begin
wr_ptr = 0;
rd_ptr = 0;
WR_DATA_VALID_DDR = 1'b0;
WR_DATA_VALID_OCM = 1'b0;
WR_QOS = 0;
state = SEND_DATA;
end else begin
case(state)
SEND_DATA :begin
state = SEND_DATA;
WR_DATA_VALID_OCM = 1'b0;
WR_DATA_VALID_DDR = 1'b0;
if(!empty) begin
WR_DATA = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_data_msb : wr_data_lsb];
WR_ADDR = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb];
WR_BYTES = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_bytes_msb : wr_bytes_lsb];
WR_QOS = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_qos_msb : wr_qos_lsb];
state = WAIT_ACK;
case(decode_address(wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb]))
OCM_MEM : WR_DATA_VALID_OCM = 1;
DDR_MEM : WR_DATA_VALID_DDR = 1;
default : state = SEND_DATA;
endcase
if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) begin
rd_ptr[intr_cnt_width-2:0] = 0;
end else begin
rd_ptr = rd_ptr+1;
end
end
end
WAIT_ACK :begin
state = WAIT_ACK;
if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin
WR_DATA_VALID_OCM = 1'b0;
WR_DATA_VALID_DDR = 1'b0;
state = SEND_DATA;
end
end
endcase
end
end
endmodule
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-03-2019
*/
module jt10_adpcm_drvB(
input rst_n,
input clk,
input cen, // 8MHz cen
input cen55, // clk & cen55 = 55 kHz
// Control
input acmd_on_b, // Control - Process start, Key On
input acmd_rep_b, // Control - Repeat
input acmd_rst_b, // Control - Reset
input acmd_up_b, // Control - New command received
input [ 1:0] alr_b, // Left / Right
input [15:0] astart_b, // Start address
input [15:0] aend_b, // End address
input [15:0] adeltan_b, // Delta-N
input [ 7:0] aeg_b, // Envelope Generator Control
output flag,
input clr_flag,
// memory
output [23:0] addr,
input [ 7:0] data,
output reg roe_n,
output reg signed [15:0] pcm55_l,
output reg signed [15:0] pcm55_r
);
wire nibble_sel;
wire adv; // advance to next reading
wire restart;
wire chon;
// `ifdef SIMULATION
// real fsample;
// always @(posedge acmd_on_b) begin
// fsample = adeltan_b;
// fsample = fsample/65536;
// fsample = fsample * 55.5;
// $display("\nINFO: ADPCM-B ON: %X delta N = %6d (%2.1f kHz)", astart_b, adeltan_b, fsample );
// end
// `endif
always @(posedge clk) roe_n <= ~(adv & cen55);
jt10_adpcmb_cnt u_cnt(
.rst_n ( rst_n ),
.clk ( clk ),
.cen ( cen55 ),
.delta_n ( adeltan_b ),
.acmd_up_b ( acmd_up_b ),
.clr ( acmd_rst_b ),
.on ( acmd_on_b ),
.astart ( astart_b ),
.aend ( aend_b ),
.arepeat ( acmd_rep_b ),
.addr ( addr ),
.nibble_sel ( nibble_sel ),
// Flag control
.chon ( chon ),
.clr_flag ( clr_flag ),
.flag ( flag ),
.restart ( restart ),
.adv ( adv )
);
reg [3:0] din;
always @(posedge clk) din <= !nibble_sel ? data[7:4] : data[3:0];
wire signed [15:0] pcmdec, pcminter, pcmgain;
jt10_adpcmb u_decoder(
.rst_n ( rst_n ),
.clk ( clk ),
.cen ( cen ),
.adv ( adv & cen55 ),
.data ( din ),
.chon ( chon ),
.clr ( flag | restart ),
.pcm ( pcmdec )
);
`ifndef NOBINTERPOL
jt10_adpcmb_interpol u_interpol(
.rst_n ( rst_n ),
.clk ( clk ),
.cen ( cen ),
.cen55 ( cen55 && chon ),
.adv ( adv ),
.pcmdec ( pcmdec ),
.pcmout ( pcminter )
);
`else
assign pcminter = pcmdec;
`endif
jt10_adpcmb_gain u_gain(
.rst_n ( rst_n ),
.clk ( clk ),
.cen55 ( cen55 ),
.tl ( aeg_b ),
.pcm_in ( pcminter ),
.pcm_out( pcmgain )
);
always @(posedge clk) if(cen55) begin
pcm55_l <= alr_b[1] ? pcmgain : 16'd0;
pcm55_r <= alr_b[0] ? pcmgain : 16'd0;
end
endmodule // jt10_adpcm_drvB
|
module IntegerDivision(
input [63:0] Dividend,
input [31:0] Divisor,
output[63:0] quotient,
output[31:0] remainder,
input start,
input clk
);
reg [8:0] count;
reg [96:0] tmp;
reg oldStart;
wire [33:0] nDivisor;
wire [33:0] pDivisor;
wire [63:0] result;
wire [33:0] addend;
initial begin
count <= 129;
tmp <= 0;
end
assign pDivisor[33] = 0,
pDivisor[32] = 0,
pDivisor[31:0] = Divisor;
assign nDivisor = -pDivisor;
assign addend = {34{tmp[96]}} & pDivisor | {34{!tmp[96]}} & nDivisor;
AdderAndSubber64 adder({30'b0,tmp[96:63]},{30'b0,addend},1'b0,result,SF,CF,OF,PF,ZF);
always @(posedge clk) begin
if (count <= 128) begin
if (count < 127) begin
if (count[0]) begin
tmp[96:1] <= tmp[95:0];
tmp[0] <= ~tmp[96];
end
else begin
tmp[96:63] <= result[33:0];
end
end
else if ( count == 127 ) begin
if ( tmp[96] ) begin
tmp[95:63] <= result[32:0];
end
end
else if ( count == 128 ) begin
tmp[96:1] <= tmp[95:0];
tmp[0] <= ~tmp[96];
end
count <= count + 1;
end
else if ( count > 128 && (start != oldStart)) begin
tmp[63:0] <= Dividend;
tmp[96:64] <= 0;
count <= 0;
end
else begin
tmp <= tmp;
count <= 129;
end
oldStart <= start;
end
assign quotient = tmp[63:0];
assign remainder = tmp[95:64];
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_example_if0_p0_write_datapath(
pll_afi_clk,
reset_n,
force_oct_off,
phy_ddio_oct_ena,
afi_dqs_en,
afi_wdata,
afi_wdata_valid,
afi_dm,
phy_ddio_dq,
phy_ddio_dqs_en,
phy_ddio_wrdata_en,
phy_ddio_wrdata_mask
);
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
parameter NUM_WRITE_PATH_FLOP_STAGES = "";
input pll_afi_clk;
input reset_n;
input [AFI_DQS_WIDTH-1:0] force_oct_off;
output [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena;
input [AFI_DQS_WIDTH-1:0] afi_dqs_en;
input [AFI_DATA_WIDTH-1:0] afi_wdata;
input [AFI_DQS_WIDTH-1:0] afi_wdata_valid;
input [AFI_DATA_MASK_WIDTH-1:0] afi_dm;
output [AFI_DATA_WIDTH-1:0] phy_ddio_dq;
output [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en;
output [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en;
output [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en_pre_shift;
wire [AFI_DATA_WIDTH-1:0] phy_ddio_dq_pre_shift;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en_pre_shift;
wire [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask_pre_shift;
generate
genvar stage;
if (NUM_WRITE_PATH_FLOP_STAGES == 0)
begin
assign phy_ddio_dq_pre_shift = afi_wdata;
assign phy_ddio_dqs_en_pre_shift = afi_dqs_en;
assign phy_ddio_wrdata_en_pre_shift = afi_wdata_valid;
assign phy_ddio_wrdata_mask_pre_shift = afi_dm;
end
else
begin
reg [AFI_DATA_WIDTH-1:0] afi_wdata_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
reg [AFI_DQS_WIDTH-1:0] afi_wdata_valid_r [NUM_WRITE_PATH_FLOP_STAGES-1:0] /* synthesis dont_merge */;
reg [AFI_DQS_WIDTH-1:0] afi_dqs_en_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
// phy_ddio_wrdata_mask is tied low during calibration
// the purpose of the assignment is to avoid Quartus from connecting the signal to the sclr pin of the flop
// sclr pin is very slow and causes timing failures
(* altera_attribute = {"-name ALLOW_SYNCH_CTRL_USAGE OFF"}*) reg [AFI_DATA_MASK_WIDTH-1:0] afi_dm_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
always @(posedge pll_afi_clk)
begin
afi_wdata_r[0] <= afi_wdata;
afi_dqs_en_r[0] <= afi_dqs_en;
afi_wdata_valid_r[0] <= afi_wdata_valid;
afi_dm_r[0] <= afi_dm;
end
for (stage = 1; stage < NUM_WRITE_PATH_FLOP_STAGES; stage = stage + 1)
begin : stage_gen
always @(posedge pll_afi_clk)
begin
afi_wdata_r[stage] <= afi_wdata_r[stage-1];
afi_dqs_en_r[stage] <= afi_dqs_en_r[stage-1];
afi_wdata_valid_r[stage] <= afi_wdata_valid_r[stage-1];
afi_dm_r[stage] <= afi_dm_r[stage-1];
end
end
assign phy_ddio_dq_pre_shift = afi_wdata_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_dqs_en_pre_shift = afi_dqs_en_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_wrdata_en_pre_shift = afi_wdata_valid_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_wrdata_mask_pre_shift = afi_dm_r[NUM_WRITE_PATH_FLOP_STAGES-1];
end
endgenerate
wire [AFI_DQS_WIDTH-1:0] oct_ena;
reg [MEM_WRITE_DQS_WIDTH-1:0] dqs_en_reg;
always @(posedge pll_afi_clk)
dqs_en_reg <= phy_ddio_dqs_en[AFI_DQS_WIDTH-1:MEM_WRITE_DQS_WIDTH];
assign oct_ena[AFI_DQS_WIDTH-1:MEM_WRITE_DQS_WIDTH] = ~phy_ddio_dqs_en[AFI_DQS_WIDTH-1:MEM_WRITE_DQS_WIDTH];
assign oct_ena[MEM_WRITE_DQS_WIDTH-1:0] = ~(phy_ddio_dqs_en[AFI_DQS_WIDTH-1:MEM_WRITE_DQS_WIDTH] | dqs_en_reg);
assign phy_ddio_oct_ena_pre_shift = oct_ena & ~force_oct_off;
assign phy_ddio_dq = phy_ddio_dq_pre_shift;
assign phy_ddio_wrdata_mask = phy_ddio_wrdata_mask_pre_shift;
assign phy_ddio_wrdata_en = phy_ddio_wrdata_en_pre_shift;
assign phy_ddio_dqs_en = phy_ddio_dqs_en_pre_shift;
assign phy_ddio_oct_ena = phy_ddio_oct_ena_pre_shift;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXTP_2_V
`define SKY130_FD_SC_HDLL__SDFXTP_2_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfxtp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfxtp_2 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXTP_2_V
|
`default_nettype none
/*******************************************
User Timer
Address
0x0 : UTIM64xMCFGR
0x1 : UTIM64xMCR_31-0
0x2 : UTIM64xMCR_63-32
0x3 : UTIM64xACC0R_31-0
0x4 : UTIM64xACC0R_63-32
0x5 : UTIM64xACC1R_31-0
0x6 : UTIM64xACC1R_63-32
0x7 : UTIM64xACC2R_31-0
0x8 : UTIM64xACC2R_63-32
0x9 : UTIM64xACC3R_31-0
0xA : UTIM64xACC3R_63-32
0xB : UTIM64xACC0CFRG
0xC : UTIM64xACC1CFRG
0xD : UTIM64xACC2CFRG
0xE : UTIM64xACC3CFRG
*******************************************/
`define UTIM6XAMCFGR 4'h0
`define UTIM6XAMCR63_32 4'h1
`define UTIM6XAMCR31_0 4'h2
`define UTIM64XACC0R63_32 4'h3
`define UTIM64XACC0R31_0 4'h4
`define UTIM64XACC1R63_32 4'h5
`define UTIM64XACC1R31_0 4'h6
`define UTIM64XACC2R63_32 4'h7
`define UTIM64XACC2R31_0 4'h8
`define UTIM64XACC3R63_32 4'h9
`define UTIM64XACC3R31_0 4'hA
`define UTIM64XACC0CFRG 4'hB
`define UTIM64XACC1CFRG 4'hC
`define UTIM64XACC2CFRG 4'hD
`define UTIM64XACC3CFRG 4'hE
module utim64(
//System
input wire iIF_CLOCK, //Global Clock
input wire iTIMER_CLOCK,
input wire inRESET,
//Counter
input wire iREQ_VALID,
output wire oREQ_BUSY,
input wire iREQ_RW,
input wire [3:0] iREQ_ADDR,
input wire [31:0] iREQ_DATA,
output wire oREQ_VALID,
output wire [31:0] oREQ_DATA,
//Interrupt
output wire [3:0] oIRQ_IRQ
);
wire req_fifo_full;
wire req_fifo_empty;
wire req_fifo_rw;
wire [31:0] req_fifo_data;
wire [3:0] req_fifo_addr;
wire req_fifo_read_condition;
mist1032sa_async_fifo #(37, 4, 2) FIFO_REQ(
//System
.inRESET(inRESET),
//Remove
.iREMOVE(1'b0),
//WR
.iWR_CLOCK(iIF_CLOCK),
.iWR_EN(iREQ_VALID),
.iWR_DATA({iREQ_RW, iREQ_ADDR, iREQ_DATA}),
.oWR_FULL(req_fifo_full),
//RD
.iRD_CLOCK(iTIMER_CLOCK),
.iRD_EN(req_fifo_read_condition),
.oRD_DATA({req_fifo_rw, req_fifo_addr, req_fifo_data}),
.oRD_EMPTY(req_fifo_empty)
);
wire write_condition = req_fifo_read_condition && req_fifo_rw;
wire read_condition = req_fifo_read_condition && !req_fifo_rw;
//Configlation Table
integer i;
reg [31:0] b_config_register_list[0:14];
always@(posedge iTIMER_CLOCK or negedge inRESET)begin
if(!inRESET)begin
for(i = 0; i < 15; i = i + 1)begin
b_config_register_list [i] <= 32'h0;
end
end
else begin
if(write_condition)begin
b_config_register_list [req_fifo_addr] <= req_fifo_data;
end
end
end
//Main Counter
wire main_config_write_cc = (req_fifo_addr == `UTIM6XAMCFGR)? write_condition : 1'b0;
wire main_counter_low_write_cc = (req_fifo_addr == `UTIM6XAMCR31_0)? write_condition : 1'b0;
wire main_counter_high_write_cc = (req_fifo_addr == `UTIM6XAMCR63_32)? write_condition : 1'b0;
wire [63:0] main_counter_write_data = (main_counter_high_write_cc)? {req_fifo_data, 32'h0} : {32'h0, req_fifo_data};
wire main_counter_working;
wire [63:0] main_counter;
main_counter MAIN_COUNTER(
.iCLOCK(iTIMER_CLOCK),
.inRESET(inRESET),
.iCONF_WRITE(main_config_write_cc),
.iCONF_ENA(req_fifo_data[0]),
.iCOUNT_WRITE(main_counter_high_write_cc || main_counter_low_write_cc),
.inCOUNT_DQM({!main_counter_high_write_cc, !main_counter_low_write_cc}),
.iCOUNT_COUNTER(main_counter_write_data),
.oWORKING(main_counter_working),
.oCOUNTER(main_counter)
);
//Comparator0
wire compare0_config_write_cc = (req_fifo_addr == `UTIM64XACC0CFRG)? write_condition : 1'b0;
wire compare0_counter_low_write_cc = (req_fifo_addr == `UTIM64XACC0R31_0)? write_condition : 1'b0;
wire compare0_counter_high_write_cc = (req_fifo_addr == `UTIM64XACC0R63_32)? write_condition : 1'b0;
wire [63:0] compare0_counter_write_data = (compare0_counter_high_write_cc)? {req_fifo_data, 32'h0} : {32'h0, req_fifo_data};//64'h00000000_000071af;
wire compare0_irq;
comparator_counter COMPARATOR0(
.iCLOCK(iTIMER_CLOCK),
.inRESET(inRESET),
.iMTIMER_WORKING(main_counter_working),
.iMTIMER_COUNT(main_counter),
.iCONF_WRITE(compare0_config_write_cc),
.iCONF_ENA(req_fifo_data[0]),
.iCONF_IRQENA(req_fifo_data[1]),
.iCONF_64MODE(req_fifo_data[2]),
.iCONF_PERIODIC(req_fifo_data[3]),
.iCOUNT_WRITE(compare0_counter_high_write_cc || compare0_counter_low_write_cc),
.inCOUNT_DQM({!compare0_counter_high_write_cc, !compare0_counter_low_write_cc}),
.iCOUNT_COUNTER(compare0_counter_write_data),
.oIRQ(compare0_irq)
);
//Comparator1
wire compare1_config_write_cc = (req_fifo_addr == `UTIM64XACC1CFRG)? write_condition : 1'b0;
wire compare1_counter_low_write_cc = (req_fifo_addr == `UTIM64XACC1R31_0)? write_condition : 1'b0;
wire compare1_counter_high_write_cc = (req_fifo_addr == `UTIM64XACC1R63_32)? write_condition : 1'b0;
wire [63:0] compare1_counter_write_data = (compare1_counter_high_write_cc)? {req_fifo_data, 32'h0} : {32'h0, req_fifo_data};
wire compare1_irq;
comparator_counter COMPARATOR1(
.iCLOCK(iTIMER_CLOCK),
.inRESET(inRESET),
.iMTIMER_WORKING(main_counter_working),
.iMTIMER_COUNT(main_counter),
.iCONF_WRITE(compare1_config_write_cc),
.iCONF_ENA(req_fifo_data[0]),
.iCONF_IRQENA(req_fifo_data[1]),
.iCONF_64MODE(req_fifo_data[2]),
.iCONF_PERIODIC(req_fifo_data[3]),
.iCOUNT_WRITE(compare1_counter_high_write_cc || compare1_counter_low_write_cc),
.inCOUNT_DQM({!compare1_counter_high_write_cc, !compare1_counter_low_write_cc}),
.iCOUNT_COUNTER(compare1_counter_write_data),
.oIRQ(compare1_irq)
);
//Comparator2
wire compare2_config_write_cc = (req_fifo_addr == `UTIM64XACC2CFRG)? write_condition : 1'b0;
wire compare2_counter_low_write_cc = (req_fifo_addr == `UTIM64XACC2R31_0)? write_condition : 1'b0;
wire compare2_counter_high_write_cc = (req_fifo_addr == `UTIM64XACC2R63_32)? write_condition : 1'b0;
wire [63:0] compare2_counter_write_data = (compare2_counter_high_write_cc)? {req_fifo_data, 32'h0} : {32'h0, req_fifo_data};
wire compare2_irq;
comparator_counter COMPARATOR2(
.iCLOCK(iTIMER_CLOCK),
.inRESET(inRESET),
.iMTIMER_WORKING(main_counter_working),
.iMTIMER_COUNT(main_counter),
.iCONF_WRITE(compare2_config_write_cc),
.iCONF_ENA(req_fifo_data[0]),
.iCONF_IRQENA(req_fifo_data[1]),
.iCONF_64MODE(req_fifo_data[2]),
.iCONF_PERIODIC(req_fifo_data[3]),
.iCOUNT_WRITE(compare2_counter_high_write_cc || compare2_counter_low_write_cc),
.inCOUNT_DQM({!compare2_counter_high_write_cc, !compare2_counter_low_write_cc}),
.iCOUNT_COUNTER(compare2_counter_write_data),
.oIRQ(compare2_irq)
);
//Comparator3
wire compare3_config_write_cc = (req_fifo_addr == `UTIM64XACC3CFRG)? write_condition : 1'b0;
wire compare3_counter_low_write_cc = (req_fifo_addr == `UTIM64XACC3R31_0)? write_condition : 1'b0;
wire compare3_counter_high_write_cc = (req_fifo_addr == `UTIM64XACC3R63_32)? write_condition : 1'b0;
wire [63:0] compare3_counter_write_data = (compare3_counter_high_write_cc)? {req_fifo_data, 32'h0} : {32'h0, req_fifo_data};
wire compare3_irq;
comparator_counter COMPARATOR3(
.iCLOCK(iTIMER_CLOCK),
.inRESET(inRESET),
.iMTIMER_WORKING(main_counter_working),
.iMTIMER_COUNT(main_counter),
.iCONF_WRITE(compare3_config_write_cc),
.iCONF_ENA(req_fifo_data[0]),
.iCONF_IRQENA(req_fifo_data[1]),
.iCONF_64MODE(req_fifo_data[2]),
.iCONF_PERIODIC(req_fifo_data[3]),
.iCOUNT_WRITE(compare3_counter_high_write_cc || compare3_counter_low_write_cc),
.inCOUNT_DQM({!compare3_counter_high_write_cc, !compare3_counter_low_write_cc}),
.iCOUNT_COUNTER(compare3_counter_write_data),
.oIRQ(compare3_irq)
);
//Output Buffer
wire out_fifo_full;
wire out_fifo_empty;
wire [31:0] out_fifo_data;
wire out_fifo_read_condition;
assign out_fifo_read_condition = !out_fifo_empty;
mist1032sa_async_fifo #(32, 4, 2) FIFO_OUT(
//System
.inRESET(inRESET),
//Remove
.iREMOVE(1'b0),
//WR
.iWR_CLOCK(iTIMER_CLOCK),
.iWR_EN(req_fifo_read_condition),
.iWR_DATA(b_config_register_list[req_fifo_addr]),
.oWR_FULL(out_fifo_full),
//RD
.iRD_CLOCK(iIF_CLOCK),
.iRD_EN(out_fifo_read_condition),
.oRD_DATA(out_fifo_data),
.oRD_EMPTY(out_fifo_empty)
);
assign req_fifo_read_condition = !req_fifo_empty && (req_fifo_rw || (!req_fifo_rw && !out_fifo_full));
assign oREQ_VALID = out_fifo_read_condition;
assign oREQ_DATA = out_fifo_data;
assign oREQ_BUSY = req_fifo_full;
assign oIRQ_IRQ = {compare3_irq, compare2_irq, compare1_irq, compare0_irq};
endmodule
`default_nettype wire
|
/*
* NAME
*
* cpu_tb.v - generic cpu test bench
*
* DESCRIPTION
*
* This generic cpu test bench can be used to run a program, which is in
* ASCII hex format, and output the results.
*
* Configuration is done by setting preprocessor defines at compile
* time. The result is an executable for that specific test.
*
* iverilog -DIM_DATA_FILE="\"t0001-no_hazard.hex\"" \
* -DNUM_IM_DATA=`wc -l t0001-no_hazard.hex | awk {'print $$1'}` \
* -DDUMP_FILE="\"t0001-no_hazard.vcd\"" \
* -I../ -g2005 \
* -o t0001-no_hazard \
* cpu_tb.v
*
* Then it can be run in the usual manner. $monitor variables will be
* output to STDOUT and a .vcd for use with Gtkwave will be output to
* 'DUMP_FILE'.
*
* ./t0001-no_hazard > t0001-no_hazard.out
*/
//`include "cpu.v"
module cpu_tb;
integer i = 0;
reg clk;
cpu #(.NMEM(12))
mips1(.clk(clk));
always begin
clk <= ~clk;
#5;
end
initial begin
// $dumpfile(`DUMP_FILE);
// $dumpvars(0, cpu_tb);
clk <= 1'b0;
/* cpu will $display output when `DEBUG_CPU_STAGES is on */
// Run all the lines, plus 5 extra to finish off the pipeline.
for (i = 0; i < 12 + 5; i = i + 1) begin
@(posedge clk);
end
$finish;
end
endmodule
|
/*
* @Author: tmh
* @Date: 2017-07-24 20:09:26
* @File Name: ALU.v
*/
`include "define.v"
module ALU (
input [ `ALU_DATA_WIDTH-1:0] wIn , // working register in
input [ `ALU_DATA_WIDTH-1:0] fIn , // general purpose register in
input [ `ALU_DATA_WIDTH-1:0] lIn , // literlal in
input [ `ALU_FUNC_WIDTH-1:0] funcIn , // alu function in
input [ 2:0] bitSel , // bit selection in
input cFlag , // carry flag in(for RRF, RLF instruction)
input [`ALU_STATUS_WIDTH-1:0] statusIn , // status in
output [`ALU_STATUS_WIDTH-1:0] aluStatusOut, // alu status out {zero, digit carry, carry}
output [ `ALU_DATA_WIDTH-1:0] aluResultOut // alu result out
);
// Arithmetic
reg C3;
reg carry;
reg [`ALU_DATA_WIDTH-1:0] result;
assign aluResultOut = result;
always @(*) begin
C3 = 1'b0;
carry = 1'b0;
case (funcIn)
`ALU_ADDWF: begin // ADD W and f
{C3,result[3:0]} = fIn[3:0] + wIn[3:0];
{carry,result[7:4]} = fIn [7:4] + wIn[7:4] + C3;
end
`ALU_SUBWF: begin // SUB w form f
{C3,result[3:0]} = fIn[3:0] - wIn[3:0];
{carry,result[7:4]} = fIn[7:4] - wIn[7:4] - C3;
end
`ALU_ANDWF: begin // AND w with f
result = wIn & fIn;
end
`ALU_COMF: begin // Complement f
result = ~ fIn;
end
`ALU_DECF: begin // Decrement f
result = fIn - 1'b1;
end
`ALU_INCF: begin // Incresement f
result = fIn + 1'b1;
end
`ALU_IORWF: begin // Inclusive OR W with f
result = fIn | wIn;
end
`ALU_RLF: begin // Rotate left f throngh Carry
{carry, result} = {fIn[`DATA_WIDTH-1:0], cFlag};
end
`ALU_RRF: begin // Rotate right f through Carry
{carry, result} = {fIn[0], cFlag, fIn[`DATA_WIDTH-1:1]};
end
`ALU_SWAPF: begin // Swap f
result = {fIn[3:0],fIn[7:4]};
end
`ALU_XORWF: begin // Exclusive OR W wtih f
result = fIn ^ wIn;
end
`ALU_BCF: begin // Bit Clear f
result = fIn & ~ (8'h01 << bitSel);
end
`ALU_BSF: begin // Bit Set f
result = fIn | (8'h1 << bitSel);
end
`ALU_ANDLW: begin // AND literal with W
result = wIn & lIn;
end
`ALU_IORLW: begin // Inclusive Or Literal in W
result = lIn | wIn;
end
`ALU_XORLW: begin
result = lIn ^ wIn;
end
`ALU_MOVF : begin
result = fIn;
end
`ALU_IDLE: begin
result = 8'hEF;
end
default: begin
result = 8'hEF;
end
endcase
end
// Status Affected
reg [`ALU_STATUS_WIDTH - 1:0] status;
assign aluStatusOut = status;
always@(*) begin
case (funcIn)
`ALU_ADDWF:begin
status = {(result == 8'b0), 1'b0, 1'b0} | {1'b0, C3, carry};
end
`ALU_SUBWF: begin
status = {(result == 8'b0), 1'b0, 1'b0} | {1'b0, ~C3, ~carry};
end
`ALU_RLF, `ALU_RRF: begin
status = statusIn | {1'b0, 1'b0, carry};
end
default: begin
status = {(result == 8'b0), statusIn[1:0]};
end
endcase
end
endmodule
|
`include "counter/simple_upcounter.v"
`include "counter/binary_upcounter.v"
`include "counter/simple_binary_upcounter.v"
`include "shift_reg/simple_shift_reg.v"
`include "shift_reg/shift_reg.v"
`include "majority/majority3.v"
/**
* Генератор частоты передачи данных.
* Параметр BAUD_RATE_BITS - число бит делителя.
* @param clk Вход тактирования.
* @param rst Вход сброса.
* @param ena Вход разрешения.
* @param baud_rate_div Значение делителя частоты.
* baud_rate_div = F_CLK / (16 * BAUD) - 1,
* где F_CLK - частота тактирования,
* BAUD - скорость обмена данными.
* @param out Выход генератора.
*/
module uart_baud_gen #(parameter BAUD_RATE_BITS=16)
(input wire clk, input wire rst, input wire ena,
input wire[BAUD_RATE_BITS-1:0] baud_rate_div, output wire out);
//
// Простой счётчик от 0 до top (от 0 до baud_rate_div).
simple_upcounter #(BAUD_RATE_BITS) cnt_baud(.clk(clk), .rst(rst), .ena(ena),
.top(baud_rate_div), .out(), .ovf(out));
//
endmodule
/**
* Передатчик UART.
* @param clk Вход тактирования.
* @param rst Вход сброса.
* @param ena Вход разрешения.
* @param baud_rate_clk Вход сигнала генератора частоты.
* @param parity_ena Разрешение контроля чётности.
* @param parity_type Тип контроля чётности.
* 0 - Even (Чётный),
* 1 - Odd (Не чётный).
* @param stop_size Размер стоп бита.
* 0 - 1 бит,
* 1 - 2 бита.
* @param data Данные для передачи.
* @param start Вход запуска передачи.
* @param busy Выход флага занятости передатчика.
* @param tx Выход передатчика.
*/
module uart_tx (input wire clk, input wire rst, input wire ena, input wire baud_rate_clk,
input wire parity_ena, input wire parity_type, input wire stop_size,
input wire[7:0] data, input wire start, output wire busy, output wire tx);
//
// Регистры.
//
// Состояние.
// Бит 3 - передача байта данных.
// Бит 2 - общий бит.
// Бит 1 - биты индекса в массиве специальных бит (передача бит старта, чётности, стопа).
// Бит 0 /
// 0 - IDLE.
reg[3:0] state;
//
// Общие провода.
//
// Флаг работы передатчика (state != 0).
wire running = |state;
// Флаг передачи байта данных (state[3] == 1).
wire transmit_data = state[3];
// Флаг синхронизации с генератором частоты.
wire baud_clk_sync = (~state[3] & state[2] & ~state[1] & ~state[0]);
// Специальные биты (idle, старт, чётность, стоп) для передачи.
wire[3:0] spec_bits = {1'b1, data_parity, 1'b0, 1'b1};
// Данные младшим битом вперёд для передачи.
wire[7:0] reversed_data;
//
// Генерация частоты передатчика.
//
// Сброс генератора частоты.
wire baud_gen_rst = rst & running & ~baud_clk_sync;
// Разрешение генератора частоты.
wire baud_gen_ena = ena & running & baud_rate_clk;
// Тик генератора частоты.
wire baud_tick;
//
// Сдвиговый регистр передаваемых данных.
//
// Флаг загрузки данных в регистр.
wire shift_reg_load = start & ~running;
// Флаг разрешения сдвига регистра.
wire shift_reg_ena = ena & baud_tick & transmit_data;
// Выход сдвигового регистра.
wire shift_reg_out;
// Выход данных сдвигового регистра.
wire[7:0] shift_reg_data_out;
//
// Чётность.
//
// Значение чётности данных по принципу "чётный".
wire data_parity_even = ^shift_reg_data_out;
// Значение чётности данных в зависимости от выбранного режима.
wire data_parity = (~parity_type & data_parity_even) | (parity_type & ~data_parity_even);
//
//
// Инициализация.
// Начальное состояние - 0 (IDLE).
initial begin
state <= 4'b0;
end
//
//
// Реверсирование данных.
genvar i;
generate
for(i = 0; i <= 7; i = i + 1) begin: gen_reverse
assign reversed_data[i] = data[7 - i];
end
endgenerate
//
// Выходные линии.
//
// Флаг занятости.
assign busy = running;
// Линия передачи.
assign tx = (transmit_data & shift_reg_out) | (~transmit_data & spec_bits[state[1:0]]);
//
//
// Модули.
//
// Сдвиговый регистр данных для передачи.
shift_reg #(8) sh_reg(.clk(clk), .rst(rst), .ena(shift_reg_ena),
.load(shift_reg_load), .load_data(reversed_data), .in(shift_reg_out),
.out_data(shift_reg_data_out), .out(shift_reg_out));
//
// Делитель входной частоты на 16.
// Синхронизируется по ближайшему тику генератора частоты после старта передачи.
simple_binary_upcounter #(4) baud_gen(.clk(clk), .rst(baud_gen_rst), .ena(baud_gen_ena),
.out(), .ovf(baud_tick));
//
//
always @(posedge clk or negedge rst) begin
if(!rst) begin
state <= 4'b0;
end else begin
case (state)
4'b0000: if(start) state <= 4'b0100; // idle
4'b0100: if(baud_rate_clk) state <= 4'b0001; // Ожидание синхронизации с генератором частоты.
4'b0001: if(baud_tick) state <= 4'b1000; // Стартовый бит.
4'b1000: if(baud_tick) state <= 4'b1001; // Бит 0
4'b1001: if(baud_tick) state <= 4'b1010; // Бит 1
4'b1010: if(baud_tick) state <= 4'b1011; // Бит 2
4'b1011: if(baud_tick) state <= 4'b1100; // Бит 3
4'b1100: if(baud_tick) state <= 4'b1101; // Бит 4
4'b1101: if(baud_tick) state <= 4'b1110; // Бит 5
4'b1110: if(baud_tick) state <= 4'b1111; // Бит 6
4'b1111: if(baud_tick) begin // Бит 7
// Если разрешена передача
// бита чётности.
if(parity_ena) begin
state <= 4'b0010; // -> Чётность.
end else begin
state <= 4'b0011; // -> Стоповый бит 1.
end
end
4'b0010: if(baud_tick) state <= 4'b0011; // Бит чётности.
4'b0011: if(baud_tick) begin // Стоповый бит 1.
// Если длина стопового бита
// равна двум.
if(stop_size) begin
state <= 4'b0111; // -> Стоповый бит 2.
end else begin
state <= 4'b0000; // -> idle
end
end
4'b0111: if(baud_tick) state <= 4'b0000; // Стоповый бит 2.
default: state <= 4'b0000; // -> idle.
endcase
end
end
//
endmodule
/**
* Приёмник UART.
* @param clk Вход тактирования.
* @param rst Вход сброса.
* @param ena Вход разрешения.
* @param baud_rate_clk Вход сигнала генератора частоты.
* @param parity_ena Разрешение контроля чётности.
* @param parity_type Тип контроля чётности.
* 0 - Even (Чётный),
* 1 - Odd (Не чётный).
* @param rx Вход приёмника.
* @param data Принятые данные.
* @param ready Флаг готовности принятых данных.
* @param parity_err Флаг ошибки чётности.
* @param frame_err Флаг ошибки кадра.
*/
module uart_rx (input wire clk, input wire rst, input wire ena,
input wire baud_rate_clk,
input wire parity_ena, input wire parity_type,
input wire rx, output wire[7:0] data, output wire ready,
output wire parity_err, output wire frame_err);
//
// Регистры.
//
// Состояние.
// Бит 3 - передача байта данных.
// Бит 2 \
// Бит 1 - Общие биты.
// Бит 0 /
// 0 - IDLE.
reg[3:0] state;
//
// Флаг ошибки чётности.
reg parity_err_flag;
// Флаг ошибки кадра.
reg frame_err_flag;
//
// Общие провода.
//
// Флаг работы передатчика (state != 0).
wire running = |state;
// Флаг приёма байта данных (state[3] == 1).
wire receive_data = state[3];
// Данные младшим битом вперёд для передачи.
wire[7:0] reversed_data;
// Значения линии приёма данных каждый тик генератора частоты.
wire[15:0] samples;
//
// Чётность.
//
// Значение чётности данных по принципу "чётный".
wire data_parity_even = ^data;
// Значение чётности данных в зависимости от выбранного режима.
wire data_parity = (~parity_type & data_parity_even) | (parity_type & ~data_parity_even);
//
// Поиск ниспадающего фронта.
//
// Выход мажоритарного элемента нахождения ниспадающего фронта.
wire falling_edge_detect_front;
// Мажоритарный элемент нахождения ниспадающего фронта.
majority3 falling_edge_detect_front_maj({samples[10], samples[8], samples[6]}, falling_edge_detect_front);
// Выход мажоритарного элемента нахождения центра стопового бита.
wire falling_edge_detect_center;
// Мажоритарный элемент нахождения центра стопового бита.
majority3 falling_edge_detect_center_maj(samples[5:3], falling_edge_detect_center);
// В выборке (samples) ищется последовательность 1110X|0X0X0|000.
wire falling_edge = &samples[15:13] & ~samples[12] & ~falling_edge_detect_front & ~falling_edge_detect_center;
// Флаг нахождения стартового бита.
wire start_bit = falling_edge & ~running;
//
// Полученный бит.
//
// Выход мажоритарного элемента цента выборки - полученный бит.
wire sampled_bit;
// Мажоритарный элемент цента выборки - полученный бит.
majority3 sampled_bit_maj(samples[8:6], sampled_bit);
//
// Сдвиговый регистр выборки.
//
// Разрешение сдвига выборки.
wire samples_sh_reg_ena = ena & baud_rate_clk;
//
// Генератор частоты следования бит (делитель частоты генератора на 16).
//
// Разрешения деления частоты.
wire baud_gen_ena = ena & running & baud_rate_clk;
// Выход генератора частоты следования бит.
wire baud_tick;
//
// Сдвиговый регистр получаемых данных.
//
// Разрешение сдвига данных.
wire data_sh_reg_ena = ena & receive_data & baud_tick;
//
//
// Инициализация.
// Начальное состояние - 0 (IDLE).
initial begin
state <= 4'b0;
parity_err_flag <= 1'b0;
frame_err_flag <= 1'b0;
end
//
//
// Реверсирование данных.
genvar i;
generate
for(i = 0; i <= 7; i = i + 1) begin: gen_reverse
assign data[i] = reversed_data[7 - i];
end
endgenerate
//
//
// Выходные линии.
//
// Флаг доступности данных.
assign ready = ~running;
// Флаг ошибки чётности.
assign parity_err = parity_err_flag;
// Флаг ошибки кадра.
assign frame_err = frame_err_flag;
//
//
// Модули.
//
// Сдвиговый регистр выборки.
simple_shift_reg #(16) samples_sh_reg(.clk(clk), .rst(rst), .ena(samples_sh_reg_ena),
.in(rx), .out_data(samples), .out());
//
// Генератор частоты следования бит (делитель на 16).
// Синхронизируется по текущей позиции при получении стартового бита.
binary_upcounter #(4) baud_gen(.clk(clk), .rst(rst), .ena(baud_gen_ena),
.value(4'hc), .load(start_bit), .out(), .ovf(baud_tick));
//
// Сдвиговй регистр бит данных.
simple_shift_reg #(8) data_sh_reg(.clk(clk), .rst(rst), .ena(data_sh_reg_ena),
.in(sampled_bit), .out_data(reversed_data), .out());
//
//
always @(posedge clk or negedge rst) begin
if(!rst) begin
state <= 4'b0;
parity_err_flag <= 1'b0;
frame_err_flag <= 1'b0;
end else begin
case (state)
4'b0000: if(start_bit) begin // idle
parity_err_flag <= 1'b0;
frame_err_flag <= 1'b0;
state <= 4'b0001; // -> Стартовый бит.
end
4'b0001: if(baud_tick) state <= 4'b1000; // Стартовый бит.
4'b1000: if(baud_tick) state <= 4'b1001; // Бит 0
4'b1001: if(baud_tick) state <= 4'b1010; // Бит 1
4'b1010: if(baud_tick) state <= 4'b1011; // Бит 2
4'b1011: if(baud_tick) state <= 4'b1100; // Бит 3
4'b1100: if(baud_tick) state <= 4'b1101; // Бит 4
4'b1101: if(baud_tick) state <= 4'b1110; // Бит 5
4'b1110: if(baud_tick) state <= 4'b1111; // Бит 6
4'b1111: if(baud_tick) begin // Бит 7
// Если разрешена передача
// бита чётности.
if(parity_ena) begin
state <= 4'b0010; // -> Чётность.
end else begin
state <= 4'b0011; // -> Стоповый бит.
end
end
4'b0010: if(baud_tick) begin // Бит чётности.
parity_err_flag <= parity_ena & (sampled_bit ^ data_parity);
state <= 4'b0011; // -> Стоповый бит.
end
4'b0011: if(baud_tick) begin // Стоповый бит.
// Если принятый стоповый бит
// имеет низкий логический уровень.
if(~sampled_bit) begin
// Установим ошибку кадра.
frame_err_flag <= 1'b1;
end
state <= 4'b0000; // -> idle.
end
default: state <= 4'b0000; // -> idle.
endcase
end
end
//
endmodule
/**
* Передатчик / приёмник UART.
* Параметр F_CLK - частота тактирования.
* Параметр BAUD - скорость передачи данных.
* @param clk Вход тактирования.
* @param rst Вход сброса.
* @param ena Вход разрешения.
* @param parity_ena Разрешение контроля чётности.
* @param parity_type Тип контроля чётности.
* 0 - Even (Чётный),
* 1 - Odd (Не чётный).
* @param stop_size Размер стоп бита.
* 0 - 1 бит,
* 1 - 2 бита.
* @param tx_data Данные для передачи.
* @param tx_start Вход запуска передачи.
* @param tx_busy Выход флага занятости передатчика.
* @param tx Выход передатчика.
* @param rx Вход приёмника.
* @param rx_data Принятые данные.
* @param rx_ready Флаг готовности принятых данных.
* @param parity_err Флаг ошибки чётности.
* @param frame_err Флаг ошибки кадра.
*/
module uart #(parameter F_CLK=50_000_000, parameter BAUD=9600)
(input wire clk, input wire rst, input wire ena,
input wire parity_ena, input wire parity_type, input wire stop_size,
input wire[7:0] tx_data, input wire tx_start, output wire tx_busy, output wire tx,
input wire rx, output wire[7:0] rx_data, output wire rx_ready,
output wire parity_err, output wire frame_err);
//
// Значение делителя частоты генератора.
localparam BAUD_GEN_DIV = F_CLK / (16 * BAUD) - 1;
localparam BAUD_GEN_DIV_BITS = $clog2(BAUD_GEN_DIV);
localparam BAUD_GEN_DIV_VAL = BAUD_GEN_DIV[BAUD_GEN_DIV_BITS-1:0];
//
// Провода.
//
// Выход генератора частоты.
wire baud_rate_clk;
//
// Модули.
//
// Генератор частоты.
uart_baud_gen #(BAUD_GEN_DIV_BITS) baud_gen(.clk(clk), .rst(rst), .ena(ena),
.baud_rate_div(BAUD_GEN_DIV_VAL), .out(baud_rate_clk));
// Передатчик.
uart_tx transmitter (.clk(clk), .rst(rst), .ena(rst), .baud_rate_clk(baud_rate_clk),
.parity_ena(parity_ena), .parity_type(parity_type), .stop_size(stop_size),
.data(tx_data), .start(tx_start), .busy(tx_busy), .tx(tx));
// Приёмник.
uart_rx receiver (.clk(clk), .rst(rst), .ena(ena), .baud_rate_clk(baud_rate_clk),
.parity_ena(parity_ena), .parity_type(parity_type),
.rx(rx), .data(rx_data), .ready(rx_ready),
.parity_err(parity_err), .frame_err(frame_err));
//
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:15:18 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_2048_0/bram_2048_0_sim_netlist.v
// Design : bram_2048_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "bram_2048_0,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module bram_2048_0
(clka,
ena,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [10:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [19:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [19:0]douta;
wire [10:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [19:0]NLW_U0_doutb_UNCONNECTED;
wire [10:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [10:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [19:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "11" *)
(* C_ADDRB_WIDTH = "11" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 3.9373 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "bram_2048_0.mem" *)
(* C_INIT_FILE_NAME = "bram_2048_0.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "2048" *)
(* C_READ_DEPTH_B = "2048" *)
(* C_READ_WIDTH_A = "20" *)
(* C_READ_WIDTH_B = "20" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "2048" *)
(* C_WRITE_DEPTH_B = "2048" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "20" *)
(* C_WRITE_WIDTH_B = "20" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
bram_2048_0_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[19:0]),
.eccpipece(1'b0),
.ena(ena),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[10:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[10:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[19:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module bram_2048_0_blk_mem_gen_generic_cstr
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [10:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_2048_0_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[8:0]),
.douta(douta[8:0]),
.ena(ena),
.wea(wea));
bram_2048_0_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[19:9]),
.douta(douta[19:9]),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bram_2048_0_blk_mem_gen_prim_width
(douta,
clka,
ena,
addra,
dina,
wea);
output [8:0]douta;
input clka;
input ena;
input [10:0]addra;
input [8:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [8:0]dina;
wire [8:0]douta;
wire ena;
wire [0:0]wea;
bram_2048_0_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bram_2048_0_blk_mem_gen_prim_width__parameterized0
(douta,
clka,
ena,
addra,
dina,
wea);
output [10:0]douta;
input clka;
input ena;
input [10:0]addra;
input [10:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [10:0]dina;
wire [10:0]douta;
wire ena;
wire [0:0]wea;
bram_2048_0_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bram_2048_0_blk_mem_gen_prim_wrapper_init
(douta,
clka,
ena,
addra,
dina,
wea);
output [8:0]douta;
input clka;
input ena;
input [10:0]addra;
input [8:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [8:0]dina;
wire [8:0]douta;
wire ena;
wire [0:0]wea;
wire [15:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h3F3D3B39373533312F2D2B29272523211F1D1B19171513110F0D0B0907050301),
.INIT_01(256'h7F7D7B79777573716F6D6B69676563615F5D5B59575553514F4D4B4947454341),
.INIT_02(256'hBFBDBBB9B7B5B3B1AFADABA9A7A5A3A19F9D9B99979593918F8D8B8987858381),
.INIT_03(256'hFFFDFBF9F7F5F3F1EFEDEBE9E7E5E3E1DFDDDBD9D7D5D3D1CFCDCBC9C7C5C3C1),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({addra,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:8],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(ena),
.ENBWREN(1'b0),
.REGCEAREGCE(ena),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bram_2048_0_blk_mem_gen_prim_wrapper_init__parameterized0
(douta,
clka,
ena,
addra,
dina,
wea);
output [10:0]douta;
input clka;
input ena;
input [10:0]addra;
input [10:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [10:0]addra;
wire clka;
wire [10:0]dina;
wire [10:0]douta;
wire ena;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[10:6],1'b0,1'b0,dina[5:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:16],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39 ,douta[10:6],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ,douta[5:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:2],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module bram_2048_0_blk_mem_gen_top
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [10:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_2048_0_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "11" *) (* C_ADDRB_WIDTH = "11" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "1" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 3.9373 mW" *)
(* C_FAMILY = "zynq" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "bram_2048_0.mem" *)
(* C_INIT_FILE_NAME = "bram_2048_0.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "2048" *) (* C_READ_DEPTH_B = "2048" *) (* C_READ_WIDTH_A = "20" *)
(* C_READ_WIDTH_B = "20" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "2048" *) (* C_WRITE_DEPTH_B = "2048" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "20" *) (* C_WRITE_WIDTH_B = "20" *)
(* C_XDEVICEFAMILY = "zynq" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module bram_2048_0_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [10:0]addra;
input [19:0]dina;
output [19:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [10:0]addrb;
input [19:0]dinb;
output [19:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [10:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [19:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [19:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [10:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [10:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[19] = \<const0> ;
assign doutb[18] = \<const0> ;
assign doutb[17] = \<const0> ;
assign doutb[16] = \<const0> ;
assign doutb[15] = \<const0> ;
assign doutb[14] = \<const0> ;
assign doutb[13] = \<const0> ;
assign doutb[12] = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
bram_2048_0_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module bram_2048_0_blk_mem_gen_v8_3_5_synth
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [10:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_2048_0_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
// Date : Fri Mar 04 11:10:30 2016
// Host : Dries007Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// d:/Xilinx/Projects/VGA/VGA.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_stub.v
// Design : clk_wiz_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_wiz_1(clk_in1, clk_out1)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1" */;
input clk_in1;
output clk_out1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAP_SYMBOL_V
`define SKY130_FD_SC_HD__TAP_SYMBOL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAP_SYMBOL_V
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_mem2x
#(
parameter DEPTH_WORDS=1,
parameter WIDTH=32,
parameter RDW_MODE="DONT_CARE",
parameter RAM_OPERATION_MODE = "BIDIR_DUAL_PORT", // altsyncram's OPERATION_MODE parameter
parameter RAM_BLOCK_TYPE = "AUTO", // altsyncram's RAM_BLOCK_TYPE parameter
parameter INTENDED_DEVICE_FAMILY = "Stratix IV", // altsyncram's INTENDED_DEVICE_FAMILY parameter
parameter ENABLED = 0, //use enable inputs
parameter PREFERRED_WIDTH = 160
)
(
input clk,
input clk2x,
input resetn,
input avs_port1_enable,
input avs_port2_enable,
input avs_port3_enable,
input avs_port4_enable,
input [WIDTH-1:0] avs_port1_writedata,
input [WIDTH-1:0] avs_port2_writedata,
input [WIDTH-1:0] avs_port3_writedata,
input [WIDTH-1:0] avs_port4_writedata,
input [WIDTH/8-1:0] avs_port1_byteenable,
input [WIDTH/8-1:0] avs_port2_byteenable,
input [WIDTH/8-1:0] avs_port3_byteenable,
input [WIDTH/8-1:0] avs_port4_byteenable,
input [$clog2(DEPTH_WORDS)-1:0] avs_port1_address,
input [$clog2(DEPTH_WORDS)-1:0] avs_port2_address,
input [$clog2(DEPTH_WORDS)-1:0] avs_port3_address,
input [$clog2(DEPTH_WORDS)-1:0] avs_port4_address,
input avs_port1_read,
input avs_port2_read,
input avs_port3_read,
input avs_port4_read,
input avs_port1_write,
input avs_port2_write,
input avs_port3_write,
input avs_port4_write,
output reg [WIDTH-1:0] avs_port1_readdata,
output reg [WIDTH-1:0] avs_port2_readdata,
output reg [WIDTH-1:0] avs_port3_readdata,
output reg [WIDTH-1:0] avs_port4_readdata,
output avs_port1_readdatavalid,
output avs_port2_readdatavalid,
output avs_port3_readdatavalid,
output avs_port4_readdatavalid,
output avs_port1_waitrequest,
output avs_port2_waitrequest,
output avs_port3_waitrequest,
output avs_port4_waitrequest
);
localparam LOG2DEPTH = $clog2( DEPTH_WORDS );
assign avs_port1_waitrequest=1'b0;
assign avs_port2_waitrequest=1'b0;
assign avs_port3_waitrequest=1'b0;
assign avs_port4_waitrequest=1'b0;
wire port1_enable;
wire port2_enable;
wire port3_enable;
wire port4_enable;
generate
if (ENABLED) begin
assign port1_enable = avs_port1_enable;
assign port2_enable = avs_port2_enable;
assign port3_enable = avs_port3_enable;
assign port4_enable = avs_port4_enable;
end else begin
assign port1_enable = 1'b1;
assign port2_enable = 1'b1;
assign port3_enable = 1'b1;
assign port4_enable = 1'b1;
end
endgenerate
wire [WIDTH-1:0] data_out_a_mem;
wire [WIDTH-1:0] data_out_b_mem;
wire [WIDTH-1:0] data_out_a_unreg;
wire [WIDTH-1:0] data_out_b_unreg;
reg [WIDTH-1:0] data_out_a_reg;
reg [WIDTH-1:0] data_out_b_reg;
reg [WIDTH-1:0] data_out_a_reg2;
reg [WIDTH-1:0] data_out_b_reg2;
_acl_mem2x_shiftreg readatavalid_1(.D(avs_port1_read), .clock(clk), .resetn(resetn), .enable(port1_enable), .Q(avs_port1_readdatavalid));
defparam readatavalid_1.WIDTH = 1;
defparam readatavalid_1.DEPTH = 4;
_acl_mem2x_shiftreg readatavalid_2(.D(avs_port2_read), .clock(clk), .resetn(resetn), .enable(port2_enable), .Q(avs_port2_readdatavalid));
defparam readatavalid_2.WIDTH = 1;
defparam readatavalid_2.DEPTH = 4;
_acl_mem2x_shiftreg readatavalid_3(.D(avs_port3_read), .clock(clk), .resetn(resetn), .enable(port3_enable), .Q(avs_port3_readdatavalid));
defparam readatavalid_3.WIDTH = 1;
defparam readatavalid_3.DEPTH = 4;
_acl_mem2x_shiftreg readatavalid_4(.D(avs_port4_read), .clock(clk), .resetn(resetn), .enable(port4_enable), .Q(avs_port4_readdatavalid));
defparam readatavalid_4.WIDTH = 1;
defparam readatavalid_4.DEPTH = 4;
localparam NUM_RAMS=((WIDTH+PREFERRED_WIDTH-1)/PREFERRED_WIDTH);
genvar n;
generate
for(n=0; n<NUM_RAMS; n++)
begin : block_n
localparam MY_WIDTH=( (n==NUM_RAMS-1) ? (WIDTH-(NUM_RAMS-1)*PREFERRED_WIDTH) : PREFERRED_WIDTH );
localparam MY_WIDTH_BYTES = MY_WIDTH / 8;
reg [LOG2DEPTH-1:0] addr_1_reg2x /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_2_reg2x /* synthesis dont_merge */;
reg write_1_reg2x /* synthesis dont_merge */;
reg write_2_reg2x /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_1_reg /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_2_reg /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_3_reg /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_4_reg /* synthesis dont_merge */;
reg write_1_reg, write_2_reg /* synthesis dont_merge */;
reg write_3_reg, write_4_reg /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_1_reg2x /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_2_reg2x /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_1_reg2x /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_2_reg2x /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_1_reg /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_2_reg /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_3_reg /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_4_reg /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_1_reg /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_2_reg /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_3_reg /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_4_reg /* synthesis dont_merge */;
reg clk_90deg, sel2x /* synthesis dont_merge */;
//Convert clock to data signal
always@(negedge clk2x)
clk_90deg<=clk;
always@(posedge clk2x)
sel2x<=clk_90deg; //This should give you exactly sel2x=~clk
always@(posedge clk2x)
begin
if (!resetn & ENABLED) begin
addr_1_reg2x <= {LOG2DEPTH{1'b0}};
addr_2_reg2x <= {LOG2DEPTH{1'b0}};
write_1_reg2x <= 1'b0;
write_2_reg2x <= 1'b0;
end else begin
if(!ENABLED | (port1_enable | port2_enable)) begin
addr_1_reg2x <= (!sel2x) ? addr_2_reg : addr_1_reg;
write_1_reg2x <= (!sel2x) ? write_2_reg : write_1_reg;
end
if(!ENABLED | (port3_enable | port4_enable)) begin
addr_2_reg2x <= (!sel2x) ? addr_4_reg : addr_3_reg;
write_2_reg2x <= (!sel2x) ? write_4_reg : write_3_reg;
end
end
end
always@(posedge clk)
begin
if (!resetn & ENABLED) begin
addr_1_reg <= {LOG2DEPTH{1'b0}};
addr_2_reg <= {LOG2DEPTH{1'b0}};
addr_3_reg <= {LOG2DEPTH{1'b0}};
addr_4_reg <= {LOG2DEPTH{1'b0}};
write_1_reg <= 1'b0;
write_2_reg <= 1'b0;
write_3_reg <= 1'b0;
write_4_reg <= 1'b0;
end else begin
if(!ENABLED | port1_enable) begin
addr_1_reg <= avs_port1_address;
write_1_reg <= avs_port1_write;
end
if(!ENABLED | port2_enable) begin
addr_2_reg <= avs_port2_address;
write_2_reg <= avs_port2_write;
end
if(!ENABLED | port3_enable) begin
addr_3_reg <= avs_port3_address;
write_3_reg <= avs_port3_write;
end
if(!ENABLED | port4_enable) begin
addr_4_reg <= avs_port4_address;
write_4_reg <= avs_port4_write;
end
end
end
//Register before double pumping
always@(posedge clk)
begin
if (!resetn & ENABLED) begin
data_1_reg <= {MY_WIDTH{1'b0}};
data_2_reg <= {MY_WIDTH{1'b0}};
data_3_reg <= {MY_WIDTH{1'b0}};
data_4_reg <= {MY_WIDTH{1'b0}};
byteen_1_reg <= {(MY_WIDTH/8){1'b1}};
byteen_2_reg <= {(MY_WIDTH/8){1'b1}};
byteen_3_reg <= {(MY_WIDTH/8){1'b1}};
byteen_4_reg <= {(MY_WIDTH/8){1'b1}};
end else begin
if(!ENABLED | port1_enable) begin
data_1_reg <= avs_port1_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
byteen_1_reg <= avs_port1_byteenable[n*(PREFERRED_WIDTH/8) +: (MY_WIDTH/8)];
end
if(!ENABLED | port2_enable) begin
data_2_reg <= avs_port2_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
byteen_2_reg <= avs_port2_byteenable[n*(PREFERRED_WIDTH/8) +: (MY_WIDTH/8)];
end
if(!ENABLED | port3_enable) begin
data_3_reg <= avs_port3_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
byteen_3_reg <= avs_port3_byteenable[n*(PREFERRED_WIDTH/8) +: (MY_WIDTH/8)];
end
if(!ENABLED | port4_enable) begin
data_4_reg <= avs_port4_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
byteen_4_reg <= avs_port4_byteenable[n*(PREFERRED_WIDTH/8) +: (MY_WIDTH/8)];
end
end
end
// Consider making only one port r/w and the rest read only
always@(posedge clk2x)
begin
if (!resetn & ENABLED) begin
data_1_reg2x <= {MY_WIDTH{1'b0}};
data_2_reg2x <= {MY_WIDTH{1'b0}};
byteen_1_reg2x <= {(MY_WIDTH/8){1'b1}};
byteen_2_reg2x <= {(MY_WIDTH/8){1'b1}};
end else begin
if(!ENABLED | (port1_enable | port2_enable)) begin
data_1_reg2x <= (!sel2x) ? data_2_reg : data_1_reg;
byteen_1_reg2x <= (!sel2x) ? byteen_2_reg : byteen_1_reg;
end
if(!ENABLED | (port3_enable | port4_enable)) begin
data_2_reg2x <= (!sel2x) ? data_4_reg : data_3_reg;
byteen_2_reg2x <= (!sel2x) ? byteen_4_reg : byteen_3_reg;
end
end
end
altsyncram altsyncram_component (
.clock0 (clk2x),
.wren_a (write_1_reg2x),
.wren_b (write_2_reg2x),
.address_a (addr_1_reg2x),
.address_b (addr_2_reg2x),
.data_a (data_1_reg2x),
.data_b (data_2_reg2x),
.q_a (data_out_a_mem[n*PREFERRED_WIDTH +: MY_WIDTH]),
.q_b (data_out_b_mem[n*PREFERRED_WIDTH +: MY_WIDTH]),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (ENABLED & (~port1_enable & ~port2_enable) ), //ports 1 and 2 must share the same enable source
.addressstall_b (ENABLED & (~port3_enable & ~port4_enable) ), //ports 3 and 4 must share the same enable source
.byteena_a (byteen_1_reg2x),
.byteena_b (byteen_2_reg2x),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.byteena_reg_b = "CLOCK0",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = INTENDED_DEVICE_FAMILY,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = DEPTH_WORDS,
altsyncram_component.numwords_b = DEPTH_WORDS,
altsyncram_component.operation_mode = RAM_OPERATION_MODE,
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = RDW_MODE,
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_b = "DONT_CARE",
altsyncram_component.widthad_a = LOG2DEPTH,
altsyncram_component.widthad_b = LOG2DEPTH,
altsyncram_component.width_a = MY_WIDTH,
altsyncram_component.width_b = MY_WIDTH,
altsyncram_component.width_byteena_a = MY_WIDTH_BYTES,
altsyncram_component.width_byteena_b = MY_WIDTH_BYTES,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.ram_block_type = RAM_BLOCK_TYPE;
if (ENABLED) begin
// catch read output data if disabled
// this should be synthesized away if enable is tied to 1
acl_mem_staging_reg #(
.WIDTH(MY_WIDTH)
) data_a_acl_mem_staging_reg (
.clk (clk2x),
.resetn (resetn),
.enable (port1_enable | port2_enable),
.rdata_in (data_out_a_mem[n*PREFERRED_WIDTH +: MY_WIDTH]),
.rdata_out(data_out_a_unreg[n*PREFERRED_WIDTH +: MY_WIDTH])
);
acl_mem_staging_reg #(
.WIDTH(MY_WIDTH)
) data_b_acl_mem_staging_reg (
.clk (clk2x),
.resetn (resetn),
.enable (port3_enable | port4_enable),
.rdata_in (data_out_b_mem[n*PREFERRED_WIDTH +: MY_WIDTH]),
.rdata_out(data_out_b_unreg[n*PREFERRED_WIDTH +: MY_WIDTH])
);
end else begin
assign data_out_a_unreg[n*PREFERRED_WIDTH +: MY_WIDTH] = data_out_a_mem[n*PREFERRED_WIDTH +: MY_WIDTH];
assign data_out_b_unreg[n*PREFERRED_WIDTH +: MY_WIDTH] = data_out_b_mem[n*PREFERRED_WIDTH +: MY_WIDTH];
end
end
endgenerate
always@(posedge clk2x)
begin
if (!ENABLED | (port1_enable | port2_enable)) begin
data_out_a_reg<=data_out_a_unreg;
data_out_a_reg2<=data_out_a_reg;
end
if (!ENABLED | (port3_enable | port4_enable)) begin
data_out_b_reg<=data_out_b_unreg;
data_out_b_reg2<=data_out_b_reg;
end
end
always@(posedge clk)
begin
if (!ENABLED | port1_enable) begin
avs_port1_readdata <= data_out_a_reg;
end
if (!ENABLED | port2_enable) begin
avs_port2_readdata <= data_out_a_reg2;
end
if (!ENABLED | port3_enable) begin
avs_port3_readdata <= data_out_b_reg;
end
if (!ENABLED | port4_enable) begin
avs_port4_readdata <= data_out_b_reg2;
end
end
endmodule
/*********************************************************************************
* Support components
*********************************************************************************/
module _acl_mem2x_shiftreg(D, clock, resetn, enable, Q);
parameter WIDTH = 32;
parameter DEPTH = 1;
input [WIDTH-1:0] D;
input clock, resetn, enable;
output [WIDTH-1:0] Q;
reg [DEPTH-1:0][WIDTH-1:0] local_ffs /* synthesis preserve */;
always @(posedge clock or negedge resetn)
if (!resetn)
local_ffs <= '0;
else if (enable)
local_ffs <= {local_ffs[DEPTH-2:0], D};
assign Q = local_ffs[DEPTH-1];
endmodule
// vim:set filetype=verilog:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211A_1_V
`define SKY130_FD_SC_LS__O211A_1_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o211a_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o211a_1 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211A_1_V
|
//
// .. hwt-autodoc::
//
module FullAdder (
input wire a,
input wire b,
input wire ci,
output reg co,
output reg s
);
always @(a, b, ci) begin: assig_process_co
co = a & b | (a & ci) | (b & ci);
end
always @(a, b, ci) begin: assig_process_s
s = a ^ b ^ ci;
end
endmodule
//
// .. hwt-autodoc::
//
module RippleAdder1 #(
parameter p_wordlength = 4
) (
input wire[3:0] a,
input wire[3:0] b,
input wire ci,
output reg co,
output reg[3:0] s
);
reg[4:0] c;
reg sig_fa_0_a;
reg sig_fa_0_b;
reg sig_fa_0_ci;
wire sig_fa_0_co;
wire sig_fa_0_s;
reg sig_fa_1_a;
reg sig_fa_1_b;
reg sig_fa_1_ci;
wire sig_fa_1_co;
wire sig_fa_1_s;
reg sig_fa_2_a;
reg sig_fa_2_b;
reg sig_fa_2_ci;
wire sig_fa_2_co;
wire sig_fa_2_s;
reg sig_fa_3_a;
reg sig_fa_3_b;
reg sig_fa_3_ci;
wire sig_fa_3_co;
wire sig_fa_3_s;
FullAdder fa_0_inst (
.a(sig_fa_0_a),
.b(sig_fa_0_b),
.ci(sig_fa_0_ci),
.co(sig_fa_0_co),
.s(sig_fa_0_s)
);
FullAdder fa_1_inst (
.a(sig_fa_1_a),
.b(sig_fa_1_b),
.ci(sig_fa_1_ci),
.co(sig_fa_1_co),
.s(sig_fa_1_s)
);
FullAdder fa_2_inst (
.a(sig_fa_2_a),
.b(sig_fa_2_b),
.ci(sig_fa_2_ci),
.co(sig_fa_2_co),
.s(sig_fa_2_s)
);
FullAdder fa_3_inst (
.a(sig_fa_3_a),
.b(sig_fa_3_b),
.ci(sig_fa_3_ci),
.co(sig_fa_3_co),
.s(sig_fa_3_s)
);
always @(ci, sig_fa_0_co, sig_fa_1_co, sig_fa_2_co, sig_fa_3_co) begin: assig_process_c
c = {{{{sig_fa_3_co, sig_fa_2_co}, sig_fa_1_co}, sig_fa_0_co}, ci};
end
always @(c) begin: assig_process_co
co = c[4];
end
always @(sig_fa_0_s, sig_fa_1_s, sig_fa_2_s, sig_fa_3_s) begin: assig_process_s
s = {{{sig_fa_3_s, sig_fa_2_s}, sig_fa_1_s}, sig_fa_0_s};
end
always @(a) begin: assig_process_sig_fa_0_a
sig_fa_0_a = a[0];
end
always @(b) begin: assig_process_sig_fa_0_b
sig_fa_0_b = b[0];
end
always @(c) begin: assig_process_sig_fa_0_ci
sig_fa_0_ci = c[0];
end
always @(a) begin: assig_process_sig_fa_1_a
sig_fa_1_a = a[1];
end
always @(b) begin: assig_process_sig_fa_1_b
sig_fa_1_b = b[1];
end
always @(c) begin: assig_process_sig_fa_1_ci
sig_fa_1_ci = c[1];
end
always @(a) begin: assig_process_sig_fa_2_a
sig_fa_2_a = a[2];
end
always @(b) begin: assig_process_sig_fa_2_b
sig_fa_2_b = b[2];
end
always @(c) begin: assig_process_sig_fa_2_ci
sig_fa_2_ci = c[2];
end
always @(a) begin: assig_process_sig_fa_3_a
sig_fa_3_a = a[3];
end
always @(b) begin: assig_process_sig_fa_3_b
sig_fa_3_b = b[3];
end
always @(c) begin: assig_process_sig_fa_3_ci
sig_fa_3_ci = c[3];
end
generate if (p_wordlength != 4)
$error("%m Generated only for this param value");
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2_12_V
`define SKY130_FD_SC_HDLL__MUX2_12_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 12 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__mux2_12 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__mux2_12 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2_12_V
|
// -----------------------------------------------------------------------------
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Filename: counter_f.v
//
// Description: Implements a parameterizable N-bit counter_f
// Up/Down Counter
// Count Enable
// Parallel Load
// Synchronous Reset
// The structural implementation has incremental cost
// of one LUT per bit.
// Precedence of operations when simultaneous:
// reset, load, count
//
// A default inferred-RTL implementation is provided and
// is used if the user explicitly specifies C_FAMILY=nofamily
// or ommits C_FAMILY (allowing it to default to nofamily).
// The default implementation is also used
// if needed primitives are not available in FPGAs of the
// type given by C_FAMILY.
//
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of axi_lite_ipif.
//
// --axi_lite_ipif.v
// --slave_attachment.v
// --address_decoder.v
// --pselect_f.v
// --counter_f.v
//-----------------------------------------------------------------------------
// Naming Conventions:
// active low signals: "*_n"
// clock signals: "clk", "clk_div#", "clk_#x"
// reset signals: "rst", "rst_n"
// generics: "C_*"
// user defined types: "*_TYPE"
// state machine next state: "*_ns"
// state machine current state: "*_cs"
// combinatorial signals: "*_com"
// pipelined or register delay signals: "*_d#"
// counter signals: "*cnt*"
// clock enable signals: "*_ce"
// internal version of output port "*_i"
// device pins: "*_pin"
// ports: - Names begin with Uppercase
// processes: "*_PROCESS"
// component instantiations: "<ENTITY_>I_<#|FUNC>
//-----------------------------------------------------------------------------
//---------------------------------------------------------------------------
// Entity section
//---------------------------------------------------------------------------
module counter_f (Clk, Rst, Load_In, Count_Enable, Count_Load, Count_Down,
Count_Out, Carry_Out);
parameter C_NUM_BITS = 9;
parameter C_FAMILY = "nofamily";
input Clk;
input Rst;
input[C_NUM_BITS - 1:0] Load_In;
input Count_Enable;
input Count_Load;
input Count_Down;
output[C_NUM_BITS - 1:0] Count_Out;
wire[C_NUM_BITS - 1:0] Count_Out;
output Carry_Out;
wire Carry_Out;
reg[C_NUM_BITS:0] icount_out;
wire[C_NUM_BITS:0] icount_out_x;
wire[C_NUM_BITS:0] load_in_x;
//-------------------------------------------------------------------
// Begin architecture
//-------------------------------------------------------------------
//-------------------------------------------------------------------
// Generate Inferred code
//-------------------------------------------------------------------
assign load_in_x = {1'b0, Load_In};
// Mask out carry position to retain legacy self-clear on next enable.
// icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
assign icount_out_x = {1'b0, icount_out[C_NUM_BITS - 1:0]};
//---------------------------------------------------------------
// Process to generate counter with - synchronous reset, load,
// counter enable, count down / up features.
//---------------------------------------------------------------
always @(posedge Clk)
begin : CNTR_PROC
if (Rst == 1'b1)
begin
icount_out <= {C_NUM_BITS-(0)+1{1'b0}} ;
end
else if (Count_Load == 1'b1)
begin
icount_out <= load_in_x ;
end
else if (Count_Down == 1'b1 & Count_Enable == 1'b1)
begin
icount_out <= icount_out_x - 1 ;
end
else if (Count_Enable == 1'b1)
begin
icount_out <= icount_out_x + 1 ;
end
end
assign Carry_Out = icount_out[C_NUM_BITS] ;
assign Count_Out = icount_out[C_NUM_BITS - 1:0];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBN_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DLXBN_BEHAVIORAL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_no_pg/sky130_fd_sc_hs__u_dl_p_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxbn (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
wire 1 ;
// Name Output Other arguments
not not0 (GATE , GATE_N_delayed );
sky130_fd_sc_hs__u_dl_p_no_pg u_dl_p_no_pg0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
assign awake = ( VPWR === 1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBN_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUFBUF_PP_SYMBOL_V
`define SKY130_FD_SC_LS__BUFBUF_PP_SYMBOL_V
/**
* bufbuf: Double buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__bufbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUFBUF_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGSBP_TB_V
`define SKY130_FD_SC_LP__SREGSBP_TB_V
/**
* sregsbp: ????.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sregsbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg ASYNC;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
ASYNC = 1'bX;
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 ASYNC = 1'b0;
#40 D = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 ASYNC = 1'b1;
#200 D = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 ASYNC = 1'b0;
#360 D = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 D = 1'b1;
#640 ASYNC = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 D = 1'bx;
#800 ASYNC = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__sregsbp dut (.D(D), .SCD(SCD), .SCE(SCE), .ASYNC(ASYNC), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGSBP_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DLXTP_FUNCTIONAL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_pg/sky130_fd_sc_hs__u_dl_p_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxtp (
VPWR,
VGND,
Q ,
D ,
GATE
);
// Module ports
input VPWR;
input VGND;
output Q ;
input D ;
input GATE;
// Local signals
wire buf_Q GATE_delayed;
wire buf_Q D_delayed ;
wire buf_Q ;
// Name Output Other arguments
sky130_fd_sc_hs__u_dl_p_pg u_dl_p_pg0 (buf_Q , D, GATE, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTP_FUNCTIONAL_V |
// daq_dma32_debug.v
`timescale 1 ns / 1 ps
/*
register set:
offset | bits | name |access| description
-------+------+-----------+------+--------------------------------
0 | 30:0 | mem_base | R/W |memory base byte address
4 | 25:0 | mem_size | R/W |memory size in words (16 bit)
8 | 25:0 | mem_read | R/W |memory read offset in words
12 | 25:0 | mem_write | R |memory write offset in words
16 | 0 | control | W | bit 0: enable
16 | 2:0 | status | R | {fifo_ovfl, ram_ovfl, running}
*/
module daq_dma32
(
input clk,
input reset,
// avalon mm data master
input avm_data_waitrq,
output avm_data_write,
output [31:0]avm_data_writedata,
output [31:0]avm_data_address,
output [3:0]avm_data_byteenable,
// avalon mm ctrl slave
input avs_ctrl_write,
input [31:0]avs_ctrl_writedata,
input avs_ctrl_read,
output reg [31:0]avs_ctrl_readdata,
input [2:0]avs_ctrl_address,
// conduit interface
input clk_daq,
input write,
input [15:0]din,
output reg running
);
wire fifo_read;
wire fifo_empty;
wire fifo_full;
wire dreg_clear;
wire dreg_write;
wire [15:0]data;
wire [1:0]be;
wire next;
// register
reg [15:0]dreg;
reg dreg_empty;
reg [30:1]mem_base;
reg [26:1]mem_size;
reg [26:1]mem_read;
reg [26:1]mem_write;
reg next2;
reg start;
reg fifo_ovfl;
reg ram_ovfl;
reg running_int;
// --- register write -----------------------------------------------------
wire write_ctrl = avs_ctrl_write && (avs_ctrl_address == 3'd4);
wire set_start = write_ctrl && avs_ctrl_writedata[0];
wire set_stop = write_ctrl && !avs_ctrl_writedata[0];
wire [26:1]inc_addr = mem_write + 26'd1;
wire carry = inc_addr == mem_size;
wire [26:1]next_addr = carry ? 26'd0 : inc_addr;
wire overflow = next_addr == mem_read;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
dreg <= 0;
dreg_empty <= 1;
next2 <= 0;
mem_base <= 0;
mem_size <= 0;
mem_write <= 0;
mem_read <= 0;
start <= 0;
running_int <= 0;
fifo_ovfl <= 0;
ram_ovfl <= 0;
end
else
begin
start <= set_start;
if (running_int)
begin
if (dreg_write) {dreg, dreg_empty} = {data, 1'b0};
else if (dreg_clear) dreg_empty = 1'b1;
if (overflow) ram_ovfl <= 1;
if (fifo_full) fifo_ovfl <= 1;
if (overflow || fifo_full || set_stop) running_int <= 0;
if (next || next2) mem_write <= next_addr;
if ((be == 3) && avm_data_write && !avm_data_waitrq) next2 <= 1;
else if (!next) next2 <= 0;
if (avs_ctrl_write && (avs_ctrl_address == 2))
mem_read <= avs_ctrl_writedata[25:0];
end
else if (start)
begin
dreg_empty <= 1;
next2 <= 0;
mem_write <= 0;
mem_read <= 0;
fifo_ovfl <= 0;
ram_ovfl <= 0;
running_int <= 1;
end
else
begin
if (avs_ctrl_write)
case (avs_ctrl_address)
0: mem_base <= avs_ctrl_writedata[30:1];
1: mem_size <= avs_ctrl_writedata[25:0];
2: mem_read <= avs_ctrl_writedata[25:0];
endcase
end
end
end
// --- register read ------------------------------------------------------
always @(*)
begin
case (avs_ctrl_address)
0: avs_ctrl_readdata <= {1'b0, mem_base, 1'b0};
1: avs_ctrl_readdata <= {6'b000000, mem_size };
2: avs_ctrl_readdata <= {6'b000000, mem_read };
3: avs_ctrl_readdata <= {6'b000000, mem_write };
default: avs_ctrl_readdata <= {29'b0, fifo_ovfl, ram_ovfl, running_int};
endcase
end
// --- DMA write controller -----------------------------------------------
wire [30:1]address = mem_base + {4'b0000, mem_write};
reg [6:0]sm_out;
always @(*)
begin
if (running_int)
case ({fifo_empty, dreg_empty, address[1], avm_data_waitrq})
4'b0000: sm_out <= 7'b1011111;
4'b0001: sm_out <= 7'b0001110;
4'b0010: sm_out <= 7'b1101101;
4'b0011: sm_out <= 7'b0001100;
4'b0100: sm_out <= 7'b1100110;
4'b0101: sm_out <= 7'b1100110;
4'b0110: sm_out <= 7'b1100100;
4'b0111: sm_out <= 7'b1100100;
4'b1000: sm_out <= 7'b0011011;
4'b1001: sm_out <= 7'b0001010;
4'b1010: sm_out <= 7'b0011101;
4'b1011: sm_out <= 7'b0001100;
4'b1100: sm_out <= 7'b0000010;
4'b1101: sm_out <= 7'b0000010;
4'b1110: sm_out <= 7'b0000100;
4'b1111: sm_out <= 7'b0000100;
endcase
else sm_out <= 7'b0000000;
end
assign {fifo_read, dreg_write, dreg_clear, avm_data_write, be, next} = sm_out;
assign avm_data_byteenable = { be[1], be[1], be[0], be[0] };
assign avm_data_address = {1'b0, address[30:2], 2'b00};
assign avm_data_writedata = be[0] ? {data, dreg} : {dreg, dreg};
daq_dma_fifo buffer
(
.aclr(reset || start),
.data(din),
.rdclk(clk),
.rdreq(fifo_read),
.wrclk(clk_daq),
.wrreq(write),
.q(data),
.rdempty(fifo_empty),
.rdfull(fifo_full)
);
// clock crossing: runnning_int -> running
reg running1;
always @(posedge clk_daq or posedge reset)
begin
if (reset)
begin
running1 <= 0;
running <= 0;
end
else
begin
running1 <= running_int;
running <= running1;
end
end
endmodule
|
module registerfile(
Q1,Q2.DI,clk,reset written,AD,A1,A2
);
output [31:0] Q1,Q2;
input [31:0] DI;
input clk,reset,written;
input [4:0] AD,A1,A2;
wire [31:0] decoderout,regen;
wire [31:0] q[31:0];
decoder dec_0(decoderout,AD);
assign regen[0] = decoderout[0]& written;
assign regen[1] = decoderout[1]& written;
//省略
assign regen[31] = decoderout[31]& written;
regesiter reg_0(q[0],DI,clk,reset,regen[0]);
regesiter reg_1(q[1],DI,clk,reset,regen[1]);
//省略
regesiter reg_31(q[31],DI,clk,reset,regen[31]);
mux_32 mux_1(Q1,q,A1);
mux_32 mux_2(Q2,q,A2);
endmodule
module dff(q,data,clk,reset,en)
output q;
input data,clk,reset,en;
reg q;
always@(posedge clk)
begin
if(reset) q<=0;
else if(en) q<=data;
else q<=q;
end
endmodule
module register(
q,data,clk,reset,en
);
output [31:0] q;
input [31:0]data;
input clk,reset,en;
dff u_0(q[0],data[0],clk,reset,en);
dff u_1(q[1],data[1],clk,reset,en);
// 省略
dff u_31(q[31],data[31],clk,reset,en);
endmodule
module mux_32(
output reg [31:0]q;
input [31:0]q[31:0];
input [4:0]raddr;
);
always@(raddr or q[31:0])
case(raddr)
5’d0: q<=q[0];
5’d1: q<=q[1];
// 省略
5’d31: q<=q[31];
default: q<= X;
endcase
endmodule
module decoder(
decoderout,waddr
);
output[31:0]decoderout;
input[4:0] waddr;
reg [31:0]decoderout;
always@(wadder)
case(wadder)
5’d0: decoderout<=32’b0000_00000_0000_0000_0000_0000_0000_0001;
5’d1: decoderout<=32’b0000_00000_0000_0000_0000_0000_0000_0010;
// 省略
5’d31: decoderout<=32’b1000_00000_0000_0000_0000_0000_0000_0000;
default: decoderout<= 32’bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
endcase
endmodule |
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Quartus II 11.0 Build 157 04/27/2011
`ifdef MODEL_TECH
`mti_v2k_int_delays_on
`endif
// ********** PRIMITIVE DEFINITIONS **********
`timescale 1 ps/1 ps
// ***** DFFE
primitive CYCLONEIVE_PRIM_DFFE (Q, ENA, D, CLK, CLRN, PRN, notifier);
input D;
input CLRN;
input PRN;
input CLK;
input ENA;
input notifier;
output Q; reg Q;
initial Q = 1'b0;
table
// ENA D CLK CLRN PRN notifier : Qt : Qt+1
(??) ? ? 1 1 ? : ? : -; // pessimism
x ? ? 1 1 ? : ? : -; // pessimism
1 1 (01) 1 1 ? : ? : 1; // clocked data
1 1 (01) 1 x ? : ? : 1; // pessimism
1 1 ? 1 x ? : 1 : 1; // pessimism
1 0 0 1 x ? : 1 : 1; // pessimism
1 0 x 1 (?x) ? : 1 : 1; // pessimism
1 0 1 1 (?x) ? : 1 : 1; // pessimism
1 x 0 1 x ? : 1 : 1; // pessimism
1 x x 1 (?x) ? : 1 : 1; // pessimism
1 x 1 1 (?x) ? : 1 : 1; // pessimism
1 0 (01) 1 1 ? : ? : 0; // clocked data
1 0 (01) x 1 ? : ? : 0; // pessimism
1 0 ? x 1 ? : 0 : 0; // pessimism
0 ? ? x 1 ? : ? : -;
1 1 0 x 1 ? : 0 : 0; // pessimism
1 1 x (?x) 1 ? : 0 : 0; // pessimism
1 1 1 (?x) 1 ? : 0 : 0; // pessimism
1 x 0 x 1 ? : 0 : 0; // pessimism
1 x x (?x) 1 ? : 0 : 0; // pessimism
1 x 1 (?x) 1 ? : 0 : 0; // pessimism
// 1 1 (x1) 1 1 ? : 1 : 1; // reducing pessimism
// 1 0 (x1) 1 1 ? : 0 : 0;
1 ? (x1) 1 1 ? : ? : -; // spr 80166-ignore
// x->1 edge
1 1 (0x) 1 1 ? : 1 : 1;
1 0 (0x) 1 1 ? : 0 : 0;
? ? ? 0 0 ? : ? : 0; // clear wins preset
? ? ? 0 1 ? : ? : 0; // asynch clear
? ? ? 1 0 ? : ? : 1; // asynch set
1 ? (?0) 1 1 ? : ? : -; // ignore falling clock
1 ? (1x) 1 1 ? : ? : -; // ignore falling clock
1 * ? ? ? ? : ? : -; // ignore data edges
1 ? ? (?1) ? ? : ? : -; // ignore edges on
1 ? ? ? (?1) ? : ? : -; // set and clear
0 ? ? 1 1 ? : ? : -; // set and clear
? ? ? 1 1 * : ? : x; // spr 36954 - at any
// notifier event,
// output 'x'
endtable
endprimitive
primitive CYCLONEIVE_PRIM_DFFEAS (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b0;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier: q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
primitive CYCLONEIVE_PRIM_DFFEAS_HIGH (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b1;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier : q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
module cycloneive_dffe ( Q, CLK, ENA, D, CLRN, PRN );
input D;
input CLK;
input CLRN;
input PRN;
input ENA;
output Q;
wire D_ipd;
wire ENA_ipd;
wire CLK_ipd;
wire PRN_ipd;
wire CLRN_ipd;
buf (D_ipd, D);
buf (ENA_ipd, ENA);
buf (CLK_ipd, CLK);
buf (PRN_ipd, PRN);
buf (CLRN_ipd, CLRN);
wire legal;
reg viol_notifier;
CYCLONEIVE_PRIM_DFFE ( Q, ENA_ipd, D_ipd, CLK_ipd, CLRN_ipd, PRN_ipd, viol_notifier );
and(legal, ENA_ipd, CLRN_ipd, PRN_ipd);
specify
specparam TREG = 0;
specparam TREN = 0;
specparam TRSU = 0;
specparam TRH = 0;
specparam TRPR = 0;
specparam TRCL = 0;
$setup ( D, posedge CLK &&& legal, TRSU, viol_notifier ) ;
$hold ( posedge CLK &&& legal, D, TRH, viol_notifier ) ;
$setup ( ENA, posedge CLK &&& legal, TREN, viol_notifier ) ;
$hold ( posedge CLK &&& legal, ENA, 0, viol_notifier ) ;
( negedge CLRN => (Q +: 1'b0)) = ( TRCL, TRCL) ;
( negedge PRN => (Q +: 1'b1)) = ( TRPR, TRPR) ;
( posedge CLK => (Q +: D)) = ( TREG, TREG) ;
endspecify
endmodule
// ***** cycloneive_mux21
module cycloneive_mux21 (MO, A, B, S);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf(A_in, A);
buf(B_in, B);
buf(S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1) ? B_in : A_in;
buf (MO, tmp_MO);
endmodule
// ***** cycloneive_mux41
module cycloneive_mux41 (MO, IN0, IN1, IN2, IN3, S);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf(IN0_in, IN0);
buf(IN1_in, IN1);
buf(IN2_in, IN2);
buf(IN3_in, IN3);
buf(S1_in, S[1]);
buf(S0_in, S[0]);
wire tmp_MO;
specify
(IN0 => MO) = (0, 0);
(IN1 => MO) = (0, 0);
(IN2 => MO) = (0, 0);
(IN3 => MO) = (0, 0);
(S[1] => MO) = (0, 0);
(S[0] => MO) = (0, 0);
endspecify
assign tmp_MO = S1_in ? (S0_in ? IN3_in : IN2_in) : (S0_in ? IN1_in : IN0_in);
buf (MO, tmp_MO);
endmodule
// ***** cycloneive_and1
module cycloneive_and1 (Y, IN1);
input IN1;
output Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y, IN1);
endmodule
// ***** cycloneive_and16
module cycloneive_and16 (Y, IN1);
input [15:0] IN1;
output [15:0] Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y[0], IN1[0]);
buf (Y[1], IN1[1]);
buf (Y[2], IN1[2]);
buf (Y[3], IN1[3]);
buf (Y[4], IN1[4]);
buf (Y[5], IN1[5]);
buf (Y[6], IN1[6]);
buf (Y[7], IN1[7]);
buf (Y[8], IN1[8]);
buf (Y[9], IN1[9]);
buf (Y[10], IN1[10]);
buf (Y[11], IN1[11]);
buf (Y[12], IN1[12]);
buf (Y[13], IN1[13]);
buf (Y[14], IN1[14]);
buf (Y[15], IN1[15]);
endmodule
// ***** cycloneive_bmux21
module cycloneive_bmux21 (MO, A, B, S);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** cycloneive_b17mux21
module cycloneive_b17mux21 (MO, A, B, S);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** cycloneive_nmux21
module cycloneive_nmux21 (MO, A, B, S);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
// ***** cycloneive_b5mux21
module cycloneive_b5mux21 (MO, A, B, S);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ********** END PRIMITIVE DEFINITIONS **********
// ********** PRIMITIVE DEFINITIONS **********
`timescale 1 ps/1 ps
// ***** cycloneive_latch
module cycloneive_latch(D, ENA, PRE, CLR, Q);
input D;
input ENA, PRE, CLR;
output Q;
reg q_out;
specify
$setup (D, negedge ENA, 0) ;
$hold (negedge ENA, D, 0) ;
(D => Q) = (0, 0);
(negedge ENA => (Q +: q_out)) = (0, 0);
(negedge PRE => (Q +: q_out)) = (0, 0);
(negedge CLR => (Q +: q_out)) = (0, 0);
endspecify
wire D_in;
wire ENA_in;
wire PRE_in;
wire CLR_in;
buf (D_in, D);
buf (ENA_in, ENA);
buf (PRE_in, PRE);
buf (CLR_in, CLR);
initial
begin
q_out <= 1'b0;
end
always @(D_in or ENA_in or PRE_in or CLR_in)
begin
if (PRE_in == 1'b0)
begin
// latch being preset, preset is active low
q_out <= 1'b1;
end
else if (CLR_in == 1'b0)
begin
// latch being cleared, clear is active low
q_out <= 1'b0;
end
else if (ENA_in == 1'b1)
begin
// latch is transparent
q_out <= D_in;
end
end
and (Q, q_out, 1'b1);
endmodule
// ********** END PRIMITIVE DEFINITIONS **********
//------------------------------------------------------------------
//
// Module Name : cycloneive_routing_wire
//
// Description : Simulation model for a simple routing wire
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cycloneive_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0) ;
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule // cycloneive_routing_wire
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneive_m_cntr
//
// Description : Timing simulation model for the M counter. This is the
// loop feedback counter for the CYCLONEIVE PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cycloneive_m_cntr ( clk,
reset,
cout,
initial_value,
modulus,
time_delay);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
cout_tmp <= tmp_cout;
end
else begin
if (clk_last_value !== clk)
begin
if (clk === 1'b1 && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
cout_tmp <= #(time_delay) tmp_cout;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
cout_tmp <= #(time_delay) tmp_cout;
end
end
end
end
clk_last_value = clk;
// cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // cycloneive_m_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneive_n_cntr
//
// Description : Timing simulation model for the N counter. This is the
// input clock divide counter for the CYCLONEIVE PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cycloneive_n_cntr ( clk,
reset,
cout,
modulus);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end
else begin
if (clk == 1 && clk_last_value !== clk && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
clk_last_value = clk;
end
assign cout = tmp_cout;
endmodule // cycloneive_n_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneive_scale_cntr
//
// Description : Timing simulation model for the output scale-down counters.
// This is a common model for the C0-C9
// output counters of the CYCLONEIVE PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cycloneive_scale_cntr ( clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg init;
integer count;
integer output_shift_count;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 0;
tmp_cout = 0;
output_shift_count = 1;
end
always @(clk or reset)
begin
if (init !== 1'b1)
begin
clk_last_value = 0;
init = 1'b1;
end
if (reset)
begin
count = 1;
output_shift_count = 1;
tmp_cout = 0;
first_rising_edge = 0;
end
else if (clk_last_value !== clk)
begin
if (mode == " off")
tmp_cout = 0;
else if (mode == "bypass")
begin
tmp_cout = clk;
first_rising_edge = 1;
end
else if (first_rising_edge == 0)
begin
if (clk == 1)
begin
if (output_shift_count == initial_value)
begin
tmp_cout = clk;
first_rising_edge = 1;
end
else
output_shift_count = output_shift_count + 1;
end
end
else if (output_shift_count < initial_value)
begin
if (clk == 1)
output_shift_count = output_shift_count + 1;
end
else
begin
count = count + 1;
if (mode == " even" && (count == (high*2) + 1))
tmp_cout = 0;
else if (mode == " odd" && (count == (high*2)))
tmp_cout = 0;
else if (count == (high + low)*2 + 1)
begin
tmp_cout = 1;
count = 1; // reset count
end
end
end
clk_last_value = clk;
cout_tmp <= tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // cycloneive_scale_cntr
//BEGIN MF PORTING DELETE
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneive_pll_reg
//
// Description : Simulation model for a simple DFF.
// This is required for the generation of the bit slip-signals.
// No timing, powers upto 0.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module cycloneive_pll_reg ( q,
clk,
ena,
d,
clrn,
prn);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q;
reg clk_last_value;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q = 0;
always @ (clk or negedge clrn or negedge prn )
begin
if (prn == 1'b0)
q <= 1;
else if (clrn == 1'b0)
q <= 0;
else if ((clk === 1'b1) && (clk_last_value === 1'b0) && (ena === 1'b1))
q <= d;
clk_last_value = clk;
end
endmodule // cycloneive_pll_reg
//END MF PORTING DELETE
//////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneive_pll
//
// Description : Timing simulation model for the Cycloneive PLL.
// In the functional mode, it is also the model for the altpll
// megafunction.
//
// Limitations : Does not support Spread Spectrum and Bandwidth.
//
// Outputs : Up to 10 output clocks, each defined by its own set of
// parameters. Locked output (active high) indicates when the
// PLL locks. clkbad and activeclock are used for
// clock switchover to indicate which input clock has gone
// bad, when the clock switchover initiates and which input
// clock is being used as the reference, respectively.
// scandataout is the data output of the serial scan chain.
//
// New Features : The list below outlines key new features in CYCLONEIVE:
// 1. Dynamic Phase Reconfiguration
// 2. Dynamic PLL Reconfiguration (different protocol)
// 3. More output counters
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`define WORD_LENGTH 18
module cycloneive_pll (inclk,
fbin,
fbout,
clkswitch,
areset,
pfdena,
scanclk,
scandata,
scanclkena,
configupdate,
clk,
phasecounterselect,
phaseupdown,
phasestep,
clkbad,
activeclock,
locked,
scandataout,
scandone,
phasedone,
vcooverrange,
vcounderrange
);
parameter operation_mode = "normal";
parameter pll_type = "auto"; // auto,fast(left_right),enhanced(top_bottom)
parameter compensate_clock = "clock0";
parameter inclk0_input_frequency = 0;
parameter inclk1_input_frequency = 0;
parameter self_reset_on_loss_lock = "off";
parameter switch_over_type = "auto";
parameter switch_over_counter = 1;
parameter enable_switch_over_counter = "off";
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter use_dc_coupling = "false";
parameter lock_high = 0; // 0 .. 4095
parameter lock_low = 0; // 0 .. 7
parameter lock_window_ui = "0.05"; // "0.05", "0.1", "0.15", "0.2"
parameter test_bypass_lock_detect = "off";
parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 0;
parameter clk0_divide_by = 0;
parameter clk0_phase_shift = "0";
parameter clk0_duty_cycle = 50;
parameter clk1_output_frequency = 0;
parameter clk1_multiply_by = 0;
parameter clk1_divide_by = 0;
parameter clk1_phase_shift = "0";
parameter clk1_duty_cycle = 50;
parameter clk2_output_frequency = 0;
parameter clk2_multiply_by = 0;
parameter clk2_divide_by = 0;
parameter clk2_phase_shift = "0";
parameter clk2_duty_cycle = 50;
parameter clk3_output_frequency = 0;
parameter clk3_multiply_by = 0;
parameter clk3_divide_by = 0;
parameter clk3_phase_shift = "0";
parameter clk3_duty_cycle = 50;
parameter clk4_output_frequency = 0;
parameter clk4_multiply_by = 0;
parameter clk4_divide_by = 0;
parameter clk4_phase_shift = "0";
parameter clk4_duty_cycle = 50;
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
// ADVANCED USE PARAMETERS
parameter m_initial = 1;
parameter m = 0;
parameter n = 1;
parameter c0_high = 1;
parameter c0_low = 1;
parameter c0_initial = 1;
parameter c0_mode = "bypass";
parameter c0_ph = 0;
parameter c1_high = 1;
parameter c1_low = 1;
parameter c1_initial = 1;
parameter c1_mode = "bypass";
parameter c1_ph = 0;
parameter c2_high = 1;
parameter c2_low = 1;
parameter c2_initial = 1;
parameter c2_mode = "bypass";
parameter c2_ph = 0;
parameter c3_high = 1;
parameter c3_low = 1;
parameter c3_initial = 1;
parameter c3_mode = "bypass";
parameter c3_ph = 0;
parameter c4_high = 1;
parameter c4_low = 1;
parameter c4_initial = 1;
parameter c4_mode = "bypass";
parameter c4_ph = 0;
parameter m_ph = 0;
parameter clk0_counter = "unused";
parameter clk1_counter = "unused";
parameter clk2_counter = "unused";
parameter clk3_counter = "unused";
parameter clk4_counter = "unused";
parameter c1_use_casc_in = "off";
parameter c2_use_casc_in = "off";
parameter c3_use_casc_in = "off";
parameter c4_use_casc_in = "off";
parameter m_test_source = -1;
parameter c0_test_source = -1;
parameter c1_test_source = -1;
parameter c2_test_source = -1;
parameter c3_test_source = -1;
parameter c4_test_source = -1;
parameter vco_multiply_by = 0;
parameter vco_divide_by = 0;
parameter vco_post_scale = 1; // 1 .. 2
parameter vco_frequency_control = "auto";
parameter vco_phase_shift_step = 0;
parameter charge_pump_current = 10;
parameter loop_filter_r = "1.0"; // "1.0", "2.0", "4.0", "6.0", "8.0", "12.0", "16.0", "20.0"
parameter loop_filter_c = 0; // 0 , 2 , 4
parameter pll_compensation_delay = 0;
parameter simulation_type = "functional";
parameter lpm_type = "cycloneive_pll";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter down_spread = "0.0";
parameter lock_c = 4;
parameter sim_gate_lock_device_behavior = "off";
parameter clk0_phase_shift_num = 0;
parameter clk1_phase_shift_num = 0;
parameter clk2_phase_shift_num = 0;
parameter clk3_phase_shift_num = 0;
parameter clk4_phase_shift_num = 0;
parameter family_name = "Cycloneive";
parameter clk0_use_even_counter_mode = "off";
parameter clk1_use_even_counter_mode = "off";
parameter clk2_use_even_counter_mode = "off";
parameter clk3_use_even_counter_mode = "off";
parameter clk4_use_even_counter_mode = "off";
parameter clk0_use_even_counter_value = "off";
parameter clk1_use_even_counter_value = "off";
parameter clk2_use_even_counter_value = "off";
parameter clk3_use_even_counter_value = "off";
parameter clk4_use_even_counter_value = "off";
// TEST ONLY
parameter init_block_reset_a_count = 1;
parameter init_block_reset_b_count = 1;
// SIMULATION_ONLY_PARAMETERS_END
// LOCAL_PARAMETERS_BEGIN
parameter phase_counter_select_width = 3;
parameter lock_window = 5;
parameter inclk0_freq = inclk0_input_frequency;
parameter inclk1_freq = inclk1_input_frequency;
parameter charge_pump_current_bits = 0;
parameter lock_window_ui_bits = 0;
parameter loop_filter_c_bits = 0;
parameter loop_filter_r_bits = 0;
parameter test_counter_c0_delay_chain_bits = 0;
parameter test_counter_c1_delay_chain_bits = 0;
parameter test_counter_c2_delay_chain_bits = 0;
parameter test_counter_c3_delay_chain_bits = 0;
parameter test_counter_c4_delay_chain_bits = 0;
parameter test_counter_c5_delay_chain_bits = 0;
parameter test_counter_m_delay_chain_bits = 0;
parameter test_counter_n_delay_chain_bits = 0;
parameter test_feedback_comp_delay_chain_bits = 0;
parameter test_input_comp_delay_chain_bits = 0;
parameter test_volt_reg_output_mode_bits = 0;
parameter test_volt_reg_output_voltage_bits = 0;
parameter test_volt_reg_test_mode = "false";
parameter vco_range_detector_high_bits = -1;
parameter vco_range_detector_low_bits = -1;
parameter scan_chain_mif_file = "";
parameter auto_settings = "true";
// LOCAL_PARAMETERS_END
// INPUT PORTS
input [1:0] inclk;
input fbin;
input clkswitch;
input areset;
input pfdena;
input [phase_counter_select_width - 1:0] phasecounterselect;
input phaseupdown;
input phasestep;
input scanclk;
input scanclkena;
input scandata;
input configupdate;
// OUTPUT PORTS
output [4:0] clk;
output [1:0] clkbad;
output activeclock;
output locked;
output scandataout;
output scandone;
output fbout;
output phasedone;
output vcooverrange;
output vcounderrange;
// TIMING CHECKS
specify
$setuphold(negedge scanclk, scandata, 0, 0);
$setuphold(negedge scanclk, scanclkena, 0, 0);
endspecify
// INTERNAL VARIABLES AND NETS
reg [8*6:1] clk_num[0:4];
integer scan_chain_length;
integer i;
integer j;
integer k;
integer x;
integer y;
integer l_index;
integer gate_count;
integer egpp_offset;
integer sched_time;
integer delay_chain;
integer low;
integer high;
integer initial_delay;
integer fbk_phase;
integer fbk_delay;
integer phase_shift[0:7];
integer last_phase_shift[0:7];
integer m_times_vco_period;
integer new_m_times_vco_period;
integer refclk_period;
integer fbclk_period;
integer high_time;
integer low_time;
integer my_rem;
integer tmp_rem;
integer rem;
integer tmp_vco_per;
integer vco_per;
integer offset;
integer temp_offset;
integer cycles_to_lock;
integer cycles_to_unlock;
integer loop_xplier;
integer loop_initial;
integer loop_ph;
integer cycle_to_adjust;
integer total_pull_back;
integer pull_back_M;
time fbclk_time;
time first_fbclk_time;
time refclk_time;
reg switch_clock;
reg [31:0] real_lock_high;
reg got_first_refclk;
reg got_second_refclk;
reg got_first_fbclk;
reg refclk_last_value;
reg fbclk_last_value;
reg inclk_last_value;
reg pll_is_locked;
reg locked_tmp;
reg areset_last_value;
reg pfdena_last_value;
reg inclk_out_of_range;
reg schedule_vco_last_value;
// Test bypass lock detect
reg pfd_locked;
integer cycles_pfd_low, cycles_pfd_high;
reg gate_out;
reg vco_val;
reg [31:0] m_initial_val;
reg [31:0] m_val[0:1];
reg [31:0] n_val[0:1];
reg [31:0] m_delay;
reg [8*6:1] m_mode_val[0:1];
reg [8*6:1] n_mode_val[0:1];
reg [31:0] c_high_val[0:9];
reg [31:0] c_low_val[0:9];
reg [8*6:1] c_mode_val[0:9];
reg [31:0] c_initial_val[0:9];
integer c_ph_val[0:9];
reg [31:0] c_val; // placeholder for c_high,c_low values
// VCO Frequency Range control
reg vco_over, vco_under;
// temporary registers for reprogramming
integer c_ph_val_tmp[0:9];
reg [31:0] c_high_val_tmp[0:9];
reg [31:0] c_hval[0:9];
reg [31:0] c_low_val_tmp[0:9];
reg [31:0] c_lval[0:9];
reg [8*6:1] c_mode_val_tmp[0:9];
// hold registers for reprogramming
integer c_ph_val_hold[0:9];
reg [31:0] c_high_val_hold[0:9];
reg [31:0] c_low_val_hold[0:9];
reg [8*6:1] c_mode_val_hold[0:9];
// old values
reg [31:0] m_val_old[0:1];
reg [31:0] m_val_tmp[0:1];
reg [31:0] n_val_old[0:1];
reg [8*6:1] m_mode_val_old[0:1];
reg [8*6:1] n_mode_val_old[0:1];
reg [31:0] c_high_val_old[0:9];
reg [31:0] c_low_val_old[0:9];
reg [8*6:1] c_mode_val_old[0:9];
integer c_ph_val_old[0:9];
integer m_ph_val_old;
integer m_ph_val_tmp;
integer cp_curr_old;
integer cp_curr_val;
integer lfc_old;
integer lfc_val;
integer vco_cur;
integer vco_old;
reg [9*8:1] lfr_val;
reg [9*8:1] lfr_old;
reg [1:2] lfc_val_bit_setting, lfc_val_old_bit_setting;
reg vco_val_bit_setting, vco_val_old_bit_setting;
reg [3:7] lfr_val_bit_setting, lfr_val_old_bit_setting;
reg [14:16] cp_curr_bit_setting, cp_curr_old_bit_setting;
// Setting on - display real values
// Setting off - display only bits
reg pll_reconfig_display_full_setting;
reg [7:0] m_hi;
reg [7:0] m_lo;
reg [7:0] n_hi;
reg [7:0] n_lo;
// ph tap orig values (POF)
integer c_ph_val_orig[0:9];
integer m_ph_val_orig;
reg schedule_vco;
reg stop_vco;
reg inclk_n;
reg inclk_man;
reg inclk_es;
reg [7:0] vco_out;
reg [7:0] vco_tap;
reg [7:0] vco_out_last_value;
reg [7:0] vco_tap_last_value;
wire inclk_c0;
wire inclk_c1;
wire inclk_c2;
wire inclk_c3;
wire inclk_c4;
wire inclk_c0_from_vco;
wire inclk_c1_from_vco;
wire inclk_c2_from_vco;
wire inclk_c3_from_vco;
wire inclk_c4_from_vco;
wire inclk_m_from_vco;
wire inclk_m;
wire pfdena_wire;
wire [4:0] clk_tmp, clk_out_pfd;
wire [4:0] clk_out;
wire c0_clk;
wire c1_clk;
wire c2_clk;
wire c3_clk;
wire c4_clk;
reg first_schedule;
reg vco_period_was_phase_adjusted;
reg phase_adjust_was_scheduled;
wire refclk;
wire fbclk;
wire pllena_reg;
wire test_mode_inclk;
// Self Reset
wire reset_self;
// Clock Switchover
reg clk0_is_bad;
reg clk1_is_bad;
reg inclk0_last_value;
reg inclk1_last_value;
reg other_clock_value;
reg other_clock_last_value;
reg primary_clk_is_bad;
reg current_clk_is_bad;
reg external_switch;
reg active_clock;
reg got_curr_clk_falling_edge_after_clkswitch;
integer clk0_count;
integer clk1_count;
integer switch_over_count;
wire scandataout_tmp;
reg scandata_in, scandata_out; // hold scan data in negative-edge triggered ff (on either side on chain)
reg scandone_tmp;
reg initiate_reconfig;
integer quiet_time;
integer slowest_clk_old;
integer slowest_clk_new;
reg reconfig_err;
reg error;
time scanclk_last_rising_edge;
time scanread_active_edge;
reg got_first_scanclk;
reg got_first_gated_scanclk;
reg gated_scanclk;
integer scanclk_period;
reg scanclk_last_value;
wire update_conf_latches;
reg update_conf_latches_reg;
reg [-1:142] scan_data;
reg scanclkena_reg; // register scanclkena on negative edge of scanclk
reg c0_rising_edge_transfer_done;
reg c1_rising_edge_transfer_done;
reg c2_rising_edge_transfer_done;
reg c3_rising_edge_transfer_done;
reg c4_rising_edge_transfer_done;
reg scanread_setup_violation;
integer index;
integer scanclk_cycles;
reg d_msg;
integer num_output_cntrs;
reg no_warn;
// Phase reconfig
reg [2:0] phasecounterselect_reg;
reg phaseupdown_reg;
reg phasestep_reg;
integer select_counter;
integer phasestep_high_count;
reg update_phase;
// LOCAL_PARAMETERS_BEGIN
parameter SCAN_CHAIN = 144;
parameter GPP_SCAN_CHAIN = 234;
parameter FAST_SCAN_CHAIN = 180;
// primary clk is always inclk0
parameter num_phase_taps = 8;
// LOCAL_PARAMETERS_END
// internal variables for scaling of multiply_by and divide_by values
integer i_clk0_mult_by;
integer i_clk0_div_by;
integer i_clk1_mult_by;
integer i_clk1_div_by;
integer i_clk2_mult_by;
integer i_clk2_div_by;
integer i_clk3_mult_by;
integer i_clk3_div_by;
integer i_clk4_mult_by;
integer i_clk4_div_by;
integer i_clk5_mult_by;
integer i_clk5_div_by;
integer i_clk6_mult_by;
integer i_clk6_div_by;
integer i_clk7_mult_by;
integer i_clk7_div_by;
integer i_clk8_mult_by;
integer i_clk8_div_by;
integer i_clk9_mult_by;
integer i_clk9_div_by;
integer max_d_value;
integer new_multiplier;
// internal variables for storing the phase shift number.(used in lvds mode only)
integer i_clk0_phase_shift;
integer i_clk1_phase_shift;
integer i_clk2_phase_shift;
integer i_clk3_phase_shift;
integer i_clk4_phase_shift;
// user to advanced internal signals
integer i_m_initial;
integer i_m;
integer i_n;
integer i_c_high[0:9];
integer i_c_low[0:9];
integer i_c_initial[0:9];
integer i_c_ph[0:9];
reg [8*6:1] i_c_mode[0:9];
integer i_vco_min;
integer i_vco_max;
integer i_vco_min_no_division;
integer i_vco_max_no_division;
integer i_vco_center;
integer i_pfd_min;
integer i_pfd_max;
integer i_m_ph;
integer m_ph_val;
reg [8*2:1] i_clk4_counter;
reg [8*2:1] i_clk3_counter;
reg [8*2:1] i_clk2_counter;
reg [8*2:1] i_clk1_counter;
reg [8*2:1] i_clk0_counter;
integer i_charge_pump_current;
integer i_loop_filter_r;
integer max_neg_abs;
integer output_count;
integer new_divisor;
integer loop_filter_c_arr[0:3];
integer fpll_loop_filter_c_arr[0:3];
integer charge_pump_curr_arr[0:15];
reg pll_in_test_mode;
reg pll_is_in_reset;
reg pll_has_just_been_reconfigured;
// uppercase to lowercase parameter values
reg [8*`WORD_LENGTH:1] l_operation_mode;
reg [8*`WORD_LENGTH:1] l_pll_type;
reg [8*`WORD_LENGTH:1] l_compensate_clock;
reg [8*`WORD_LENGTH:1] l_scan_chain;
reg [8*`WORD_LENGTH:1] l_switch_over_type;
reg [8*`WORD_LENGTH:1] l_bandwidth_type;
reg [8*`WORD_LENGTH:1] l_simulation_type;
reg [8*`WORD_LENGTH:1] l_sim_gate_lock_device_behavior;
reg [8*`WORD_LENGTH:1] l_vco_frequency_control;
reg [8*`WORD_LENGTH:1] l_enable_switch_over_counter;
reg [8*`WORD_LENGTH:1] l_self_reset_on_loss_lock;
integer current_clock;
integer current_clock_man;
reg is_fast_pll;
reg ic1_use_casc_in;
reg ic2_use_casc_in;
reg ic3_use_casc_in;
reg ic4_use_casc_in;
reg init;
reg tap0_is_active;
real inclk0_period, last_inclk0_period,inclk1_period, last_inclk1_period;
real last_inclk0_edge,last_inclk1_edge,diff_percent_period;
reg first_inclk0_edge_detect,first_inclk1_edge_detect;
specify
endspecify
// finds the closest integer fraction of a given pair of numerator and denominator.
task find_simple_integer_fraction;
input numerator;
input denominator;
input max_denom;
output fraction_num;
output fraction_div;
parameter max_iter = 20;
integer numerator;
integer denominator;
integer max_denom;
integer fraction_num;
integer fraction_div;
integer quotient_array[max_iter-1:0];
integer int_loop_iter;
integer int_quot;
integer m_value;
integer d_value;
integer old_m_value;
integer swap;
integer loop_iter;
integer num;
integer den;
integer i_max_iter;
begin
loop_iter = 0;
num = (numerator == 0) ? 1 : numerator;
den = (denominator == 0) ? 1 : denominator;
i_max_iter = max_iter;
while (loop_iter < i_max_iter)
begin
int_quot = num / den;
quotient_array[loop_iter] = int_quot;
num = num - (den*int_quot);
loop_iter=loop_iter+1;
if ((num == 0) || (max_denom != -1) || (loop_iter == i_max_iter))
begin
// calculate the numerator and denominator if there is a restriction on the
// max denom value or if the loop is ending
m_value = 0;
d_value = 1;
// get the rounded value at this stage for the remaining fraction
if (den != 0)
begin
m_value = (2*num/den);
end
// calculate the fraction numerator and denominator at this stage
for (int_loop_iter = loop_iter-1; int_loop_iter >= 0; int_loop_iter=int_loop_iter-1)
begin
if (m_value == 0)
begin
m_value = quotient_array[int_loop_iter];
d_value = 1;
end
else
begin
old_m_value = m_value;
m_value = quotient_array[int_loop_iter]*m_value + d_value;
d_value = old_m_value;
end
end
// if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) || (max_denom == -1))
begin
fraction_num = m_value;
fraction_div = d_value;
end
// end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) && (max_denom != -1)) || (num == 0))
begin
i_max_iter = loop_iter;
end
end
// swap the numerator and denominator for the next round
swap = den;
den = num;
num = swap;
end
end
endtask // find_simple_integer_fraction
// get the absolute value
function integer abs;
input value;
integer value;
begin
if (value < 0)
abs = value * -1;
else abs = value;
end
endfunction
// find twice the period of the slowest clock
function integer slowest_clk;
input C0, C0_mode, C1, C1_mode, C2, C2_mode, C3, C3_mode, C4, C4_mode, C5, C5_mode, C6, C6_mode, C7, C7_mode, C8, C8_mode, C9, C9_mode, refclk, m_mod;
integer C0, C1, C2, C3, C4, C5, C6, C7, C8, C9;
reg [8*6:1] C0_mode, C1_mode, C2_mode, C3_mode, C4_mode, C5_mode, C6_mode, C7_mode, C8_mode, C9_mode;
integer refclk;
reg [31:0] m_mod;
integer max_modulus;
begin
max_modulus = 1;
if (C0_mode != "bypass" && C0_mode != " off")
max_modulus = C0;
if (C1 > max_modulus && C1_mode != "bypass" && C1_mode != " off")
max_modulus = C1;
if (C2 > max_modulus && C2_mode != "bypass" && C2_mode != " off")
max_modulus = C2;
if (C3 > max_modulus && C3_mode != "bypass" && C3_mode != " off")
max_modulus = C3;
if (C4 > max_modulus && C4_mode != "bypass" && C4_mode != " off")
max_modulus = C4;
if (C5 > max_modulus && C5_mode != "bypass" && C5_mode != " off")
max_modulus = C5;
if (C6 > max_modulus && C6_mode != "bypass" && C6_mode != " off")
max_modulus = C6;
if (C7 > max_modulus && C7_mode != "bypass" && C7_mode != " off")
max_modulus = C7;
if (C8 > max_modulus && C8_mode != "bypass" && C8_mode != " off")
max_modulus = C8;
if (C9 > max_modulus && C9_mode != "bypass" && C9_mode != " off")
max_modulus = C9;
slowest_clk = (refclk * max_modulus *2 / m_mod);
end
endfunction
// count the number of digits in the given integer
function integer count_digit;
input X;
integer X;
integer count, result;
begin
count = 0;
result = X;
while (result != 0)
begin
result = (result / 10);
count = count + 1;
end
count_digit = count;
end
endfunction
// reduce the given huge number(X) to Y significant digits
function integer scale_num;
input X, Y;
integer X, Y;
integer count;
integer fac_ten, lc;
begin
fac_ten = 1;
count = count_digit(X);
for (lc = 0; lc < (count-Y); lc = lc + 1)
fac_ten = fac_ten * 10;
scale_num = (X / fac_ten);
end
endfunction
// find the greatest common denominator of X and Y
function integer gcd;
input X,Y;
integer X,Y;
integer L, S, R, G;
begin
if (X < Y) // find which is smaller.
begin
S = X;
L = Y;
end
else
begin
S = Y;
L = X;
end
R = S;
while ( R > 1)
begin
S = L;
L = R;
R = S % L; // divide bigger number by smaller.
// remainder becomes smaller number.
end
if (R == 0) // if evenly divisible then L is gcd else it is 1.
G = L;
else
G = R;
gcd = G;
end
endfunction
// find the least common multiple of A1 to A10
function integer lcm;
input A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer M1, M2, M3, M4, M5 , M6, M7, M8, M9, R;
begin
M1 = (A1 * A2)/gcd(A1, A2);
M2 = (M1 * A3)/gcd(M1, A3);
M3 = (M2 * A4)/gcd(M2, A4);
M4 = (M3 * A5)/gcd(M3, A5);
M5 = (M4 * A6)/gcd(M4, A6);
M6 = (M5 * A7)/gcd(M5, A7);
M7 = (M6 * A8)/gcd(M6, A8);
M8 = (M7 * A9)/gcd(M7, A9);
M9 = (M8 * A10)/gcd(M8, A10);
if (M9 < 3)
R = 10;
else if ((M9 <= 10) && (M9 >= 3))
R = 4 * M9;
else if (M9 > 1000)
R = scale_num(M9, 3);
else
R = M9;
lcm = R;
end
endfunction
// find the M and N values for Manual phase based on the following 5 criterias:
// 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
// 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
// 3. M is less than 512
// 4. N is less than 512
// 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
// of the desired vco-phase-shift-step
task find_m_and_n_4_manual_phase;
input inclock_period;
input vco_phase_shift_step;
input clk0_mult, clk1_mult, clk2_mult, clk3_mult, clk4_mult;
input clk5_mult, clk6_mult, clk7_mult, clk8_mult, clk9_mult;
input clk0_div, clk1_div, clk2_div, clk3_div, clk4_div;
input clk5_div, clk6_div, clk7_div, clk8_div, clk9_div;
input clk0_used, clk1_used, clk2_used, clk3_used, clk4_used;
input clk5_used, clk6_used, clk7_used, clk8_used, clk9_used;
output m;
output n;
parameter max_m = 511;
parameter max_n = 511;
parameter max_pfd = 720;
parameter min_pfd = 5;
parameter max_vco = 1600; // max vco frequency. (in mHz)
parameter min_vco = 300; // min vco frequency. (in mHz)
parameter max_offset = 0.004;
reg[160:1] clk0_used, clk1_used, clk2_used, clk3_used, clk4_used;
reg[160:1] clk5_used, clk6_used, clk7_used, clk8_used, clk9_used;
integer inclock_period;
integer vco_phase_shift_step;
integer clk0_mult, clk1_mult, clk2_mult, clk3_mult, clk4_mult;
integer clk5_mult, clk6_mult, clk7_mult, clk8_mult, clk9_mult;
integer clk0_div, clk1_div, clk2_div, clk3_div, clk4_div;
integer clk5_div, clk6_div, clk7_div, clk8_div, clk9_div;
integer m;
integer n;
integer pre_m;
integer pre_n;
integer m_out;
integer n_out;
integer closest_vco_step_value;
integer vco_period;
integer pfd_freq;
integer vco_freq;
integer vco_ps_step_value;
real clk0_div_factor_real;
real clk1_div_factor_real;
real clk2_div_factor_real;
real clk3_div_factor_real;
real clk4_div_factor_real;
real clk5_div_factor_real;
real clk6_div_factor_real;
real clk7_div_factor_real;
real clk8_div_factor_real;
real clk9_div_factor_real;
real clk0_div_factor_diff;
real clk1_div_factor_diff;
real clk2_div_factor_diff;
real clk3_div_factor_diff;
real clk4_div_factor_diff;
real clk5_div_factor_diff;
real clk6_div_factor_diff;
real clk7_div_factor_diff;
real clk8_div_factor_diff;
real clk9_div_factor_diff;
integer clk0_div_factor_int;
integer clk1_div_factor_int;
integer clk2_div_factor_int;
integer clk3_div_factor_int;
integer clk4_div_factor_int;
integer clk5_div_factor_int;
integer clk6_div_factor_int;
integer clk7_div_factor_int;
integer clk8_div_factor_int;
integer clk9_div_factor_int;
begin
vco_period = vco_phase_shift_step * 8;
pre_m = 0;
pre_n = 0;
closest_vco_step_value = 0;
begin : LOOP_1
for (n_out = 1; n_out < max_n; n_out = n_out +1)
begin
for (m_out = 1; m_out < max_m; m_out = m_out +1)
begin
clk0_div_factor_real = (clk0_div * m_out * 1.0 ) / (clk0_mult * n_out);
clk1_div_factor_real = (clk1_div * m_out * 1.0) / (clk1_mult * n_out);
clk2_div_factor_real = (clk2_div * m_out * 1.0) / (clk2_mult * n_out);
clk3_div_factor_real = (clk3_div * m_out * 1.0) / (clk3_mult * n_out);
clk4_div_factor_real = (clk4_div * m_out * 1.0) / (clk4_mult * n_out);
clk5_div_factor_real = (clk5_div * m_out * 1.0) / (clk5_mult * n_out);
clk6_div_factor_real = (clk6_div * m_out * 1.0) / (clk6_mult * n_out);
clk7_div_factor_real = (clk7_div * m_out * 1.0) / (clk7_mult * n_out);
clk8_div_factor_real = (clk8_div * m_out * 1.0) / (clk8_mult * n_out);
clk9_div_factor_real = (clk9_div * m_out * 1.0) / (clk9_mult * n_out);
clk0_div_factor_int = clk0_div_factor_real;
clk1_div_factor_int = clk1_div_factor_real;
clk2_div_factor_int = clk2_div_factor_real;
clk3_div_factor_int = clk3_div_factor_real;
clk4_div_factor_int = clk4_div_factor_real;
clk5_div_factor_int = clk5_div_factor_real;
clk6_div_factor_int = clk6_div_factor_real;
clk7_div_factor_int = clk7_div_factor_real;
clk8_div_factor_int = clk8_div_factor_real;
clk9_div_factor_int = clk9_div_factor_real;
clk0_div_factor_diff = (clk0_div_factor_real - clk0_div_factor_int < 0) ? (clk0_div_factor_real - clk0_div_factor_int) * -1.0 : clk0_div_factor_real - clk0_div_factor_int;
clk1_div_factor_diff = (clk1_div_factor_real - clk1_div_factor_int < 0) ? (clk1_div_factor_real - clk1_div_factor_int) * -1.0 : clk1_div_factor_real - clk1_div_factor_int;
clk2_div_factor_diff = (clk2_div_factor_real - clk2_div_factor_int < 0) ? (clk2_div_factor_real - clk2_div_factor_int) * -1.0 : clk2_div_factor_real - clk2_div_factor_int;
clk3_div_factor_diff = (clk3_div_factor_real - clk3_div_factor_int < 0) ? (clk3_div_factor_real - clk3_div_factor_int) * -1.0 : clk3_div_factor_real - clk3_div_factor_int;
clk4_div_factor_diff = (clk4_div_factor_real - clk4_div_factor_int < 0) ? (clk4_div_factor_real - clk4_div_factor_int) * -1.0 : clk4_div_factor_real - clk4_div_factor_int;
clk5_div_factor_diff = (clk5_div_factor_real - clk5_div_factor_int < 0) ? (clk5_div_factor_real - clk5_div_factor_int) * -1.0 : clk5_div_factor_real - clk5_div_factor_int;
clk6_div_factor_diff = (clk6_div_factor_real - clk6_div_factor_int < 0) ? (clk6_div_factor_real - clk6_div_factor_int) * -1.0 : clk6_div_factor_real - clk6_div_factor_int;
clk7_div_factor_diff = (clk7_div_factor_real - clk7_div_factor_int < 0) ? (clk7_div_factor_real - clk7_div_factor_int) * -1.0 : clk7_div_factor_real - clk7_div_factor_int;
clk8_div_factor_diff = (clk8_div_factor_real - clk8_div_factor_int < 0) ? (clk8_div_factor_real - clk8_div_factor_int) * -1.0 : clk8_div_factor_real - clk8_div_factor_int;
clk9_div_factor_diff = (clk9_div_factor_real - clk9_div_factor_int < 0) ? (clk9_div_factor_real - clk9_div_factor_int) * -1.0 : clk9_div_factor_real - clk9_div_factor_int;
if (((clk0_div_factor_diff < max_offset) || (clk0_used == "unused")) &&
((clk1_div_factor_diff < max_offset) || (clk1_used == "unused")) &&
((clk2_div_factor_diff < max_offset) || (clk2_used == "unused")) &&
((clk3_div_factor_diff < max_offset) || (clk3_used == "unused")) &&
((clk4_div_factor_diff < max_offset) || (clk4_used == "unused")) &&
((clk5_div_factor_diff < max_offset) || (clk5_used == "unused")) &&
((clk6_div_factor_diff < max_offset) || (clk6_used == "unused")) &&
((clk7_div_factor_diff < max_offset) || (clk7_used == "unused")) &&
((clk8_div_factor_diff < max_offset) || (clk8_used == "unused")) &&
((clk9_div_factor_diff < max_offset) || (clk9_used == "unused")) )
begin
if ((m_out != 0) && (n_out != 0))
begin
pfd_freq = 1000000 / (inclock_period * n_out);
vco_freq = (1000000 * m_out) / (inclock_period * n_out);
vco_ps_step_value = (inclock_period * n_out) / (8 * m_out);
if ( (m_out < max_m) && (n_out < max_n) && (pfd_freq >= min_pfd) && (pfd_freq <= max_pfd) &&
(vco_freq >= min_vco) && (vco_freq <= max_vco) )
begin
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
begin
pre_m = m_out;
pre_n = n_out;
disable LOOP_1;
end
else
begin
if ((closest_vco_step_value == 0) || (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
begin
pre_m = m_out;
pre_n = n_out;
closest_vco_step_value = vco_ps_step_value;
end
end
end
end
end
end
end
end
if ((pre_m != 0) && (pre_n != 0))
begin
find_simple_integer_fraction(pre_m, pre_n,
max_n, m, n);
end
else
begin
n = 1;
m = lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end
end
endtask // find_m_and_n_4_manual_phase
// find the factor of division of the output clock frequency
// compared to the VCO
function integer output_counter_value;
input clk_divide, clk_mult, M, N;
integer clk_divide, clk_mult, M, N;
real r;
integer r_int;
begin
r = (clk_divide * M * 1.0)/(clk_mult * N);
r_int = r;
output_counter_value = r_int;
end
endfunction
// find the mode of each of the PLL counters - bypass, even or odd
function [8*6:1] counter_mode;
input duty_cycle;
input output_counter_value;
integer duty_cycle;
integer output_counter_value;
integer half_cycle_high;
reg [8*6:1] R;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100.0;
if (output_counter_value == 1)
R = "bypass";
else if ((half_cycle_high % 2) == 0)
R = " even";
else
R = " odd";
counter_mode = R;
end
endfunction
// find the number of VCO clock cycles to hold the output clock high
function integer counter_high;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle;
integer half_cycle_high;
integer tmp_counter_high;
integer mode;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100.0;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_high = tmp_counter_high + !mode;
end
endfunction
// find the number of VCO clock cycles to hold the output clock low
function integer counter_low;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle, counter_h;
integer half_cycle_high;
integer mode;
integer tmp_counter_high;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100.0;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_h = tmp_counter_high + !mode;
counter_low = output_counter_value - counter_h;
end
endfunction
// find the smallest time delay amongst t1 to t10
function integer mintimedelay;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2)
m1 = t1;
else
m1 = t2;
if (m1 < t3)
m2 = m1;
else
m2 = t3;
if (m2 < t4)
m3 = m2;
else
m3 = t4;
if (m3 < t5)
m4 = m3;
else
m4 = t5;
if (m4 < t6)
m5 = m4;
else
m5 = t6;
if (m5 < t7)
m6 = m5;
else
m6 = t7;
if (m6 < t8)
m7 = m6;
else
m7 = t8;
if (m7 < t9)
m8 = m7;
else
m8 = t9;
if (m8 < t10)
m9 = m8;
else
m9 = t10;
if (m9 > 0)
mintimedelay = m9;
else
mintimedelay = 0;
end
endfunction
// find the numerically largest negative number, and return its absolute value
function integer maxnegabs;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2) m1 = t1; else m1 = t2;
if (m1 < t3) m2 = m1; else m2 = t3;
if (m2 < t4) m3 = m2; else m3 = t4;
if (m3 < t5) m4 = m3; else m4 = t5;
if (m4 < t6) m5 = m4; else m5 = t6;
if (m5 < t7) m6 = m5; else m6 = t7;
if (m6 < t8) m7 = m6; else m7 = t8;
if (m7 < t9) m8 = m7; else m8 = t9;
if (m8 < t10) m9 = m8; else m9 = t10;
maxnegabs = (m9 < 0) ? 0 - m9 : 0;
end
endfunction
// adjust the given tap_phase by adding the largest negative number (ph_base)
function integer ph_adjust;
input tap_phase, ph_base;
integer tap_phase, ph_base;
begin
ph_adjust = tap_phase + ph_base;
end
endfunction
// find the number of VCO clock cycles to wait initially before the first
// rising edge of the output clock
function integer counter_initial;
input tap_phase, m, n;
integer tap_phase, m, n, phase;
begin
if (tap_phase < 0) tap_phase = 0 - tap_phase;
// adding 0.5 for rounding correction (required in order to round
// to the nearest integer instead of truncating)
phase = ((tap_phase * m) / (360.0 * n)) + 0.6;
counter_initial = phase;
end
endfunction
// find which VCO phase tap to align the rising edge of the output clock to
function integer counter_ph;
input tap_phase;
input m,n;
integer m,n, phase;
integer tap_phase;
begin
// adding 0.5 for rounding correction
phase = (tap_phase * m / n) + 0.5;
counter_ph = (phase % 360) / 45.0;
if (counter_ph == 8)
counter_ph = 0;
end
endfunction
// convert the given string to length 6 by padding with spaces
function [8*6:1] translate_string;
input [8*6:1] mode;
reg [8*6:1] new_mode;
begin
if (mode == "bypass")
new_mode = "bypass";
else if (mode == "even")
new_mode = " even";
else if (mode == "odd")
new_mode = " odd";
translate_string = new_mode;
end
endfunction
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction
// this is for cycloneive lvds only
// convert phase delay to integer
function integer get_int_phase_shift;
input [8*16:1] s;
input i_phase_shift;
integer i_phase_shift;
begin
if (i_phase_shift != 0)
begin
get_int_phase_shift = i_phase_shift;
end
else
begin
get_int_phase_shift = str2int(s);
end
end
endfunction
// calculate the given phase shift (in ps) in terms of degrees
function integer get_phase_degree;
input phase_shift;
integer phase_shift, result;
begin
result = (phase_shift * 360) / inclk0_freq;
// this is to round up the calculation result
if ( result > 0 )
result = result + 1;
else if ( result < 0 )
result = result - 1;
else
result = 0;
// assign the rounded up result
get_phase_degree = result;
end
endfunction
// convert uppercase parameter values to lowercase
// assumes that the maximum character length of a parameter is 18
function [8*`WORD_LENGTH:1] alpha_tolower;
input [8*`WORD_LENGTH:1] given_string;
reg [8*`WORD_LENGTH:1] return_string;
reg [8*`WORD_LENGTH:1] reg_string;
reg [8:1] tmp;
reg [8:1] conv_char;
integer byte_count;
begin
return_string = " "; // initialise strings to spaces
conv_char = " ";
reg_string = given_string;
for (byte_count = `WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1)
begin
tmp = reg_string[8*`WORD_LENGTH:(8*(`WORD_LENGTH-1)+1)];
reg_string = reg_string << 8;
if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
begin
conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
return_string = {return_string, conv_char};
end
else
return_string = {return_string, tmp};
end
alpha_tolower = return_string;
end
endfunction
function integer display_msg;
input [8*2:1] cntr_name;
input msg_code;
integer msg_code;
begin
if (msg_code == 1)
$display ("Warning : %s counter switched from BYPASS mode to enabled. PLL may lose lock.", cntr_name);
else if (msg_code == 2)
$display ("Warning : Illegal 1 value for %s counter. Instead, the %s counter should be BYPASSED. Reconfiguration may not work.", cntr_name, cntr_name);
else if (msg_code == 3)
$display ("Warning : Illegal value for counter %s in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.", cntr_name);
else if (msg_code == 4)
$display ("Warning : %s counter switched from enabled to BYPASS mode. PLL may lose lock.", cntr_name);
$display ("Time: %0t Instance: %m", $time);
display_msg = 1;
end
endfunction
initial
begin
scandata_out = 1'b0;
first_inclk0_edge_detect = 1'b0;
first_inclk1_edge_detect = 1'b0;
pll_reconfig_display_full_setting = 1'b0;
initiate_reconfig = 1'b0;
switch_over_count = 0;
// convert string parameter values from uppercase to lowercase,
// as expected in this model
l_operation_mode = alpha_tolower(operation_mode);
l_pll_type = alpha_tolower(pll_type);
l_compensate_clock = alpha_tolower(compensate_clock);
l_switch_over_type = alpha_tolower(switch_over_type);
l_bandwidth_type = alpha_tolower(bandwidth_type);
l_simulation_type = alpha_tolower(simulation_type);
l_sim_gate_lock_device_behavior = alpha_tolower(sim_gate_lock_device_behavior);
l_vco_frequency_control = alpha_tolower(vco_frequency_control);
l_enable_switch_over_counter = alpha_tolower(enable_switch_over_counter);
l_self_reset_on_loss_lock = alpha_tolower(self_reset_on_loss_lock);
real_lock_high = (l_sim_gate_lock_device_behavior == "on") ? lock_high : 0;
// initialize charge_pump_current, and loop_filter tables
loop_filter_c_arr[0] = 0;
loop_filter_c_arr[1] = 0;
loop_filter_c_arr[2] = 0;
loop_filter_c_arr[3] = 0;
fpll_loop_filter_c_arr[0] = 0;
fpll_loop_filter_c_arr[1] = 0;
fpll_loop_filter_c_arr[2] = 0;
fpll_loop_filter_c_arr[3] = 0;
charge_pump_curr_arr[0] = 0;
charge_pump_curr_arr[1] = 0;
charge_pump_curr_arr[2] = 0;
charge_pump_curr_arr[3] = 0;
charge_pump_curr_arr[4] = 0;
charge_pump_curr_arr[5] = 0;
charge_pump_curr_arr[6] = 0;
charge_pump_curr_arr[7] = 0;
charge_pump_curr_arr[8] = 0;
charge_pump_curr_arr[9] = 0;
charge_pump_curr_arr[10] = 0;
charge_pump_curr_arr[11] = 0;
charge_pump_curr_arr[12] = 0;
charge_pump_curr_arr[13] = 0;
charge_pump_curr_arr[14] = 0;
charge_pump_curr_arr[15] = 0;
i_vco_max = vco_max;
i_vco_min = vco_min;
if(vco_post_scale == 1)
begin
i_vco_max_no_division = vco_max * 2;
i_vco_min_no_division = vco_min * 2;
end
else
begin
i_vco_max_no_division = vco_max;
i_vco_min_no_division = vco_min;
end
if (m == 0)
begin
i_clk4_counter = "c4" ;
i_clk3_counter = "c3" ;
i_clk2_counter = "c2" ;
i_clk1_counter = "c1" ;
i_clk0_counter = "c0" ;
end
else begin
i_clk4_counter = alpha_tolower(clk4_counter);
i_clk3_counter = alpha_tolower(clk3_counter);
i_clk2_counter = alpha_tolower(clk2_counter);
i_clk1_counter = alpha_tolower(clk1_counter);
i_clk0_counter = alpha_tolower(clk0_counter);
end
if (m == 0)
begin
// set the limit of the divide_by value that can be returned by
// the following function.
max_d_value = 500;
// scale down the multiply_by and divide_by values provided by the design
// before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
// convert user parameters to advanced
if (l_vco_frequency_control == "manual_phase")
begin
find_m_and_n_4_manual_phase(inclk0_freq, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,i_clk4_mult_by,
1, 1, 1, 1, 1,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,i_clk4_div_by,
1, 1, 1, 1, 1,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,clk4_counter,
"unused", "unused", "unused", "unused", "unused",
i_m, i_n);
end
else if (((l_pll_type == "fast") || (l_pll_type == "lvds") || (l_pll_type == "left_right")) && (vco_multiply_by != 0) && (vco_divide_by != 0))
begin
i_n = vco_divide_by;
i_m = vco_multiply_by;
end
else begin
i_n = 1;
if (((l_pll_type == "fast") || (l_pll_type == "left_right")) && (l_compensate_clock == "lvdsclk"))
i_m = i_clk0_mult_by;
else
i_m = lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,i_clk4_mult_by,
1, 1, 1, 1, 1,
inclk0_freq);
end
i_c_high[0] = counter_high (output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high[1] = counter_high (output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high[2] = counter_high (output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high[3] = counter_high (output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high[4] = counter_high (output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low[0] = counter_low (output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low[1] = counter_low (output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low[2] = counter_low (output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low[3] = counter_low (output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low[4] = counter_low (output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
if (l_pll_type == "flvds")
begin
// Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier = clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift = (clk0_phase_shift_num * new_multiplier);
i_clk1_phase_shift = (clk1_phase_shift_num * new_multiplier);
i_clk2_phase_shift = (clk2_phase_shift_num * new_multiplier);
i_clk3_phase_shift = 0;
i_clk4_phase_shift = 0;
end
else
begin
i_clk0_phase_shift = get_int_phase_shift(clk0_phase_shift, clk0_phase_shift_num);
i_clk1_phase_shift = get_int_phase_shift(clk1_phase_shift, clk1_phase_shift_num);
i_clk2_phase_shift = get_int_phase_shift(clk2_phase_shift, clk2_phase_shift_num);
i_clk3_phase_shift = get_int_phase_shift(clk3_phase_shift, clk3_phase_shift_num);
i_clk4_phase_shift = get_int_phase_shift(clk4_phase_shift, clk4_phase_shift_num);
end
max_neg_abs = maxnegabs ( i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
i_clk3_phase_shift,
i_clk4_phase_shift,
0,
0,
0,
0,
0
);
i_c_initial[0] = counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[1] = counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[2] = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[3] = counter_initial(get_phase_degree(ph_adjust(i_clk3_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[4] = counter_initial(get_phase_degree(ph_adjust(i_clk4_phase_shift, max_neg_abs)), i_m, i_n);
i_c_mode[0] = counter_mode(clk0_duty_cycle,output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode[1] = counter_mode(clk1_duty_cycle,output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode[2] = counter_mode(clk2_duty_cycle,output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode[3] = counter_mode(clk3_duty_cycle,output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode[4] = counter_mode(clk4_duty_cycle,output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_m_ph = counter_ph(get_phase_degree(max_neg_abs), i_m, i_n);
i_m_initial = counter_initial(get_phase_degree(max_neg_abs), i_m, i_n);
i_c_ph[0] = counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[1] = counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[2] = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[3] = counter_ph(get_phase_degree(ph_adjust(i_clk3_phase_shift,max_neg_abs)), i_m, i_n);
i_c_ph[4] = counter_ph(get_phase_degree(ph_adjust(i_clk4_phase_shift,max_neg_abs)), i_m, i_n);
end
else
begin // m != 0
i_n = n;
i_m = m;
i_c_high[0] = c0_high;
i_c_high[1] = c1_high;
i_c_high[2] = c2_high;
i_c_high[3] = c3_high;
i_c_high[4] = c4_high;
i_c_low[0] = c0_low;
i_c_low[1] = c1_low;
i_c_low[2] = c2_low;
i_c_low[3] = c3_low;
i_c_low[4] = c4_low;
i_c_initial[0] = c0_initial;
i_c_initial[1] = c1_initial;
i_c_initial[2] = c2_initial;
i_c_initial[3] = c3_initial;
i_c_initial[4] = c4_initial;
i_c_mode[0] = translate_string(alpha_tolower(c0_mode));
i_c_mode[1] = translate_string(alpha_tolower(c1_mode));
i_c_mode[2] = translate_string(alpha_tolower(c2_mode));
i_c_mode[3] = translate_string(alpha_tolower(c3_mode));
i_c_mode[4] = translate_string(alpha_tolower(c4_mode));
i_c_ph[0] = c0_ph;
i_c_ph[1] = c1_ph;
i_c_ph[2] = c2_ph;
i_c_ph[3] = c3_ph;
i_c_ph[4] = c4_ph;
i_m_ph = m_ph; // default
i_m_initial = m_initial;
end // user to advanced conversion
switch_clock = 1'b0;
refclk_period = inclk0_freq * i_n;
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
fbclk_period = 0;
high_time = 0;
low_time = 0;
schedule_vco = 0;
vco_out[7:0] = 8'b0;
vco_tap[7:0] = 8'b0;
fbclk_last_value = 0;
offset = 0;
temp_offset = 0;
got_first_refclk = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
refclk_time = 0;
first_schedule = 1;
sched_time = 0;
vco_val = 0;
gate_count = 0;
gate_out = 0;
initial_delay = 0;
fbk_phase = 0;
for (i = 0; i <= 7; i = i + 1)
begin
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
fbk_delay = 0;
inclk_n = 0;
inclk_es = 0;
inclk_man = 0;
cycle_to_adjust = 0;
m_delay = 0;
total_pull_back = 0;
pull_back_M = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
inclk_out_of_range = 0;
scandone_tmp = 1'b0;
schedule_vco_last_value = 0;
scan_chain_length = SCAN_CHAIN;
num_output_cntrs = 5;
phasestep_high_count = 0;
update_phase = 0;
// set initial values for counter parameters
m_initial_val = i_m_initial;
m_val[0] = i_m;
n_val[0] = i_n;
m_ph_val = i_m_ph;
m_ph_val_orig = i_m_ph;
m_ph_val_tmp = i_m_ph;
m_val_tmp[0] = i_m;
if (m_val[0] == 1)
m_mode_val[0] = "bypass";
else m_mode_val[0] = "";
if (m_val[1] == 1)
m_mode_val[1] = "bypass";
if (n_val[0] == 1)
n_mode_val[0] = "bypass";
if (n_val[1] == 1)
n_mode_val[1] = "bypass";
for (i = 0; i < 10; i=i+1)
begin
c_high_val[i] = i_c_high[i];
c_low_val[i] = i_c_low[i];
c_initial_val[i] = i_c_initial[i];
c_mode_val[i] = i_c_mode[i];
c_ph_val[i] = i_c_ph[i];
c_high_val_tmp[i] = i_c_high[i];
c_hval[i] = i_c_high[i];
c_low_val_tmp[i] = i_c_low[i];
c_lval[i] = i_c_low[i];
if (c_mode_val[i] == "bypass")
begin
if (l_pll_type == "fast" || l_pll_type == "lvds" || l_pll_type == "left_right")
begin
c_high_val[i] = 5'b10000;
c_low_val[i] = 5'b10000;
c_high_val_tmp[i] = 5'b10000;
c_low_val_tmp[i] = 5'b10000;
end
else begin
c_high_val[i] = 9'b100000000;
c_low_val[i] = 9'b100000000;
c_high_val_tmp[i] = 9'b100000000;
c_low_val_tmp[i] = 9'b100000000;
end
end
c_mode_val_tmp[i] = i_c_mode[i];
c_ph_val_tmp[i] = i_c_ph[i];
c_ph_val_orig[i] = i_c_ph[i];
c_high_val_hold[i] = i_c_high[i];
c_low_val_hold[i] = i_c_low[i];
c_mode_val_hold[i] = i_c_mode[i];
end
lfc_val = loop_filter_c;
lfr_val = loop_filter_r;
cp_curr_val = charge_pump_current;
vco_cur = vco_post_scale;
i = 0;
j = 0;
inclk_last_value = 0;
// initialize clkswitch variables
clk0_is_bad = 0;
clk1_is_bad = 0;
inclk0_last_value = 0;
inclk1_last_value = 0;
other_clock_value = 0;
other_clock_last_value = 0;
primary_clk_is_bad = 0;
current_clk_is_bad = 0;
external_switch = 0;
current_clock = 0;
current_clock_man = 0;
active_clock = 0; // primary_clk is always inclk0
if (l_pll_type == "fast" || (l_pll_type == "left_right"))
l_switch_over_type = "manual";
if (l_switch_over_type == "manual" && clkswitch === 1'b1)
begin
current_clock_man = 1;
active_clock = 1;
end
got_curr_clk_falling_edge_after_clkswitch = 0;
clk0_count = 0;
clk1_count = 0;
// initialize reconfiguration variables
// quiet_time
quiet_time = slowest_clk ( c_high_val[0]+c_low_val[0], c_mode_val[0],
c_high_val[1]+c_low_val[1], c_mode_val[1],
c_high_val[2]+c_low_val[2], c_mode_val[2],
c_high_val[3]+c_low_val[3], c_mode_val[3],
c_high_val[4]+c_low_val[4], c_mode_val[4],
c_high_val[5]+c_low_val[5], c_mode_val[5],
c_high_val[6]+c_low_val[6], c_mode_val[6],
c_high_val[7]+c_low_val[7], c_mode_val[7],
c_high_val[8]+c_low_val[8], c_mode_val[8],
c_high_val[9]+c_low_val[9], c_mode_val[9],
refclk_period, m_val[0]);
reconfig_err = 0;
error = 0;
c0_rising_edge_transfer_done = 0;
c1_rising_edge_transfer_done = 0;
c2_rising_edge_transfer_done = 0;
c3_rising_edge_transfer_done = 0;
c4_rising_edge_transfer_done = 0;
got_first_scanclk = 0;
got_first_gated_scanclk = 0;
gated_scanclk = 1;
scanread_setup_violation = 0;
index = 0;
vco_over = 1'b0;
vco_under = 1'b0;
// Initialize the scan chain
// LF unused : bit 1
scan_data[-1:0] = 2'b00;
// LF Capacitance : bits 1,2 : all values are legal
scan_data[1:2] = loop_filter_c_bits;
// LF Resistance : bits 3-7
scan_data[3:7] = loop_filter_r_bits;
// VCO post scale
if(vco_post_scale == 1)
begin
scan_data[8] = 1'b1;
vco_val_old_bit_setting = 1'b1;
end
else
begin
scan_data[8] = 1'b0;
vco_val_old_bit_setting = 1'b0;
end
scan_data[9:13] = 5'b00000;
// CP
// Bit 8 : CRBYPASS
// Bit 9-13 : unused
// Bits 14-16 : all values are legal
scan_data[14:16] = charge_pump_current_bits;
// store as old values
cp_curr_old_bit_setting = charge_pump_current_bits;
lfc_val_old_bit_setting = loop_filter_c_bits;
lfr_val_old_bit_setting = loop_filter_r_bits;
// C counters (start bit 53) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
for (i = 0; i < num_output_cntrs; i = i + 1)
begin
// 1. Mode - bypass
if (c_mode_val[i] == "bypass")
begin
scan_data[53 + i*18 + 0] = 1'b1;
if (c_mode_val[i] == " odd")
scan_data[53 + i*18 + 9] = 1'b1;
else
scan_data[53 + i*18 + 9] = 1'b0;
end
else
begin
scan_data[53 + i*18 + 0] = 1'b0;
// 3. Mode - odd/even
if (c_mode_val[i] == " odd")
scan_data[53 + i*18 + 9] = 1'b1;
else
scan_data[53 + i*18 + 9] = 1'b0;
end
// 2. Hi
c_val = c_high_val[i];
for (j = 1; j <= 8; j = j + 1)
scan_data[53 + i*18 + j] = c_val[8 - j];
// 4. Low
c_val = c_low_val[i];
for (j = 10; j <= 17; j = j + 1)
scan_data[53 + i*18 + j] = c_val[17 - j];
end
// M counter
// 1. Mode - bypass (bit 17)
if (m_mode_val[0] == "bypass")
scan_data[35] = 1'b1;
else
scan_data[35] = 1'b0;
// 2. High (bit 18-25)
// 3. Mode - odd/even (bit 26)
if (m_val[0] % 2 == 0)
begin
// M is an even no. : set M high = low,
// set odd/even bit to 0
scan_data[36:43]= m_val[0]/2;
scan_data[44] = 1'b0;
end
else
begin
// M is odd : M high = low + 1
scan_data[36:43] = m_val[0]/2 + 1;
scan_data[44] = 1'b1;
end
// 4. Low (bit 27-34)
scan_data[45:52] = m_val[0]/2;
// N counter
// 1. Mode - bypass (bit 35)
if (n_mode_val[0] == "bypass")
scan_data[17] = 1'b1;
else
scan_data[17] = 1'b0;
// 2. High (bit 36-43)
// 3. Mode - odd/even (bit 44)
if (n_val[0] % 2 == 0)
begin
// N is an even no. : set N high = low,
// set odd/even bit to 0
scan_data[18:25] = n_val[0]/2;
scan_data[26] = 1'b0;
end
else
begin // N is odd : N high = N low + 1
scan_data[18:25] = n_val[0]/2+ 1;
scan_data[26] = 1'b1;
end
// 4. Low (bit 45-52)
scan_data[27:34] = n_val[0]/2;
l_index = 1;
stop_vco = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
locked_tmp = 0;
pll_is_locked = 0;
no_warn = 1'b0;
pfd_locked = 1'b0;
cycles_pfd_high = 0;
cycles_pfd_low = 0;
// check if pll is in test mode
if (m_test_source != -1 || c0_test_source != -1 || c1_test_source != -1 || c2_test_source != -1 || c3_test_source != -1 || c4_test_source != -1)
pll_in_test_mode = 1'b1;
else
pll_in_test_mode = 1'b0;
pll_is_in_reset = 0;
pll_has_just_been_reconfigured = 0;
if (l_pll_type == "fast" || l_pll_type == "lvds" || l_pll_type == "left_right")
is_fast_pll = 1;
else is_fast_pll = 0;
if (c1_use_casc_in == "on")
ic1_use_casc_in = 1;
else
ic1_use_casc_in = 0;
if (c2_use_casc_in == "on")
ic2_use_casc_in = 1;
else
ic2_use_casc_in = 0;
if (c3_use_casc_in == "on")
ic3_use_casc_in = 1;
else
ic3_use_casc_in = 0;
if (c4_use_casc_in == "on")
ic4_use_casc_in = 1;
else
ic4_use_casc_in = 0;
tap0_is_active = 1;
// To display clock mapping
case( i_clk0_counter)
"c0" : clk_num[0] = " clk0";
"c1" : clk_num[0] = " clk1";
"c2" : clk_num[0] = " clk2";
"c3" : clk_num[0] = " clk3";
"c4" : clk_num[0] = " clk4";
default:clk_num[0] = "unused";
endcase
case( i_clk1_counter)
"c0" : clk_num[1] = " clk0";
"c1" : clk_num[1] = " clk1";
"c2" : clk_num[1] = " clk2";
"c3" : clk_num[1] = " clk3";
"c4" : clk_num[1] = " clk4";
default:clk_num[1] = "unused";
endcase
case( i_clk2_counter)
"c0" : clk_num[2] = " clk0";
"c1" : clk_num[2] = " clk1";
"c2" : clk_num[2] = " clk2";
"c3" : clk_num[2] = " clk3";
"c4" : clk_num[2] = " clk4";
default:clk_num[2] = "unused";
endcase
case( i_clk3_counter)
"c0" : clk_num[3] = " clk0";
"c1" : clk_num[3] = " clk1";
"c2" : clk_num[3] = " clk2";
"c3" : clk_num[3] = " clk3";
"c4" : clk_num[3] = " clk4";
default:clk_num[3] = "unused";
endcase
case( i_clk4_counter)
"c0" : clk_num[4] = " clk0";
"c1" : clk_num[4] = " clk1";
"c2" : clk_num[4] = " clk2";
"c3" : clk_num[4] = " clk3";
"c4" : clk_num[4] = " clk4";
default:clk_num[4] = "unused";
endcase
end
// Clock Switchover
always @(clkswitch)
begin
if (clkswitch === 1'b1 && l_switch_over_type == "auto")
external_switch = 1;
else if (l_switch_over_type == "manual")
begin
if(clkswitch === 1'b1)
switch_clock = 1'b1;
else
switch_clock = 1'b0;
end
end
always @(posedge inclk[0])
begin
// Determine the inclk0 frequency
if (first_inclk0_edge_detect == 1'b0)
begin
first_inclk0_edge_detect = 1'b1;
end
else
begin
last_inclk0_period = inclk0_period;
inclk0_period = $realtime - last_inclk0_edge;
end
last_inclk0_edge = $realtime;
end
always @(posedge inclk[1])
begin
// Determine the inclk1 frequency
if (first_inclk1_edge_detect == 1'b0)
begin
first_inclk1_edge_detect = 1'b1;
end
else
begin
last_inclk1_period = inclk1_period;
inclk1_period = $realtime - last_inclk1_edge;
end
last_inclk1_edge = $realtime;
end
always @(inclk[0] or inclk[1])
begin
if(switch_clock == 1'b1)
begin
if(current_clock_man == 0)
begin
current_clock_man = 1;
active_clock = 1;
end
else
begin
current_clock_man = 0;
active_clock = 0;
end
switch_clock = 1'b0;
end
if (current_clock_man == 0)
inclk_man = inclk[0];
else
inclk_man = inclk[1];
// save the inclk event value
if (inclk[0] !== inclk0_last_value)
begin
if (current_clock != 0)
other_clock_value = inclk[0];
end
if (inclk[1] !== inclk1_last_value)
begin
if (current_clock != 1)
other_clock_value = inclk[1];
end
// check if either input clk is bad
if (inclk[0] === 1'b1 && inclk[0] !== inclk0_last_value)
begin
clk0_count = clk0_count + 1;
clk0_is_bad = 0;
clk1_count = 0;
if (clk0_count > 2)
begin
// no event on other clk for 2 cycles
clk1_is_bad = 1;
if (current_clock == 1)
current_clk_is_bad = 1;
end
end
if (inclk[1] === 1'b1 && inclk[1] !== inclk1_last_value)
begin
clk1_count = clk1_count + 1;
clk1_is_bad = 0;
clk0_count = 0;
if (clk1_count > 2)
begin
// no event on other clk for 2 cycles
clk0_is_bad = 1;
if (current_clock == 0)
current_clk_is_bad = 1;
end
end
// check if the bad clk is the primary clock, which is always clk0
if (clk0_is_bad == 1'b1)
primary_clk_is_bad = 1;
else
primary_clk_is_bad = 0;
// actual switching -- manual switch
if ((inclk[0] !== inclk0_last_value) && current_clock == 0)
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk[0] === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_es = inclk[0];
end
end
else inclk_es = inclk[0];
end
if ((inclk[1] !== inclk1_last_value) && current_clock == 1)
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk[1] === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_es = inclk[1];
end
end
else inclk_es = inclk[1];
end
// actual switching -- automatic switch
if ((other_clock_value == 1'b1) && (other_clock_value != other_clock_last_value) && l_enable_switch_over_counter == "on" && primary_clk_is_bad)
switch_over_count = switch_over_count + 1;
if ((other_clock_value == 1'b0) && (other_clock_value != other_clock_last_value))
begin
if ((external_switch && (got_curr_clk_falling_edge_after_clkswitch || current_clk_is_bad)) || (primary_clk_is_bad && (clkswitch !== 1'b1) && ((l_enable_switch_over_counter == "off" || switch_over_count == switch_over_counter))))
begin
if (areset === 1'b0)
begin
if ((inclk0_period > inclk1_period) && (inclk1_period != 0))
diff_percent_period = (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
else if (inclk0_period != 0)
diff_percent_period = (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
if((diff_percent_period > 20)&& (l_switch_over_type == "auto"))
begin
$display ("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality.");
$display ("Time: %0t Instance: %m", $time);
end
end
got_curr_clk_falling_edge_after_clkswitch = 0;
if (current_clock == 0)
current_clock = 1;
else
current_clock = 0;
active_clock = ~active_clock;
switch_over_count = 0;
external_switch = 0;
current_clk_is_bad = 0;
end
else if(l_switch_over_type == "auto")
begin
if(current_clock == 0 && clk0_is_bad == 1'b1 && clk1_is_bad == 1'b0 )
begin
current_clock = 1;
active_clock = ~active_clock;
end
if(current_clock == 1 && clk1_is_bad == 1'b1 && clk0_is_bad == 1'b0 )
begin
current_clock = 0;
active_clock = ~active_clock;
end
end
end
if(l_switch_over_type == "manual")
inclk_n = inclk_man;
else
inclk_n = inclk_es;
inclk0_last_value = inclk[0];
inclk1_last_value = inclk[1];
other_clock_last_value = other_clock_value;
end
and (clkbad[0], clk0_is_bad, 1'b1);
and (clkbad[1], clk1_is_bad, 1'b1);
and (activeclock, active_clock, 1'b1);
assign inclk_m = (m_test_source == 0) ? fbclk : (m_test_source == 1) ? refclk : inclk_m_from_vco;
cycloneive_m_cntr m1 (.clk(inclk_m),
.reset(areset || stop_vco),
.cout(fbclk),
.initial_value(m_initial_val),
.modulus(m_val[0]),
.time_delay(m_delay));
cycloneive_n_cntr n1 (.clk(inclk_n),
.reset(areset),
.cout(refclk),
.modulus(n_val[0]));
// Update clock on /o counters from corresponding VCO tap
assign inclk_m_from_vco = vco_tap[m_ph_val];
assign inclk_c0_from_vco = vco_tap[c_ph_val[0]];
assign inclk_c1_from_vco = vco_tap[c_ph_val[1]];
assign inclk_c2_from_vco = vco_tap[c_ph_val[2]];
assign inclk_c3_from_vco = vco_tap[c_ph_val[3]];
assign inclk_c4_from_vco = vco_tap[c_ph_val[4]];
always @(vco_out)
begin
// check which VCO TAP has event
for (x = 0; x <= 7; x = x + 1)
begin
if (vco_out[x] !== vco_out_last_value[x])
begin
// TAP 'X' has event
if ((x == 0) && (!pll_is_in_reset) && (stop_vco !== 1'b1))
begin
if (vco_out[0] == 1'b1)
tap0_is_active = 1;
if (tap0_is_active == 1'b1)
vco_tap[0] <= vco_out[0];
end
else if (tap0_is_active == 1'b1)
vco_tap[x] <= vco_out[x];
if (stop_vco === 1'b1)
vco_out[x] <= 1'b0;
end
end
vco_out_last_value = vco_out;
end
always @(vco_tap)
begin
// Update phase taps for C/M counters on negative edge of VCO clock output
if (update_phase == 1'b1)
begin
for (x = 0; x <= 7; x = x + 1)
begin
if ((vco_tap[x] === 1'b0) && (vco_tap[x] !== vco_tap_last_value[x]))
begin
for (y = 0; y < 10; y = y + 1)
begin
if (c_ph_val_tmp[y] == x)
c_ph_val[y] = c_ph_val_tmp[y];
end
if (m_ph_val_tmp == x)
m_ph_val = m_ph_val_tmp;
end
end
update_phase <= #(0.5*scanclk_period) 1'b0;
end
// On reset, set all C/M counter phase taps to POF programmed values
if (areset === 1'b1)
begin
m_ph_val = m_ph_val_orig;
m_ph_val_tmp = m_ph_val_orig;
for (i=0; i<= 9; i=i+1)
begin
c_ph_val[i] = c_ph_val_orig[i];
c_ph_val_tmp[i] = c_ph_val_orig[i];
end
end
vco_tap_last_value = vco_tap;
end
assign inclk_c0 = (c0_test_source == 0) ? fbclk : (c0_test_source == 1) ? refclk : inclk_c0_from_vco;
cycloneive_scale_cntr c0 (.clk(inclk_c0),
.reset(areset || stop_vco),
.cout(c0_clk),
.high(c_high_val[0]),
.low(c_low_val[0]),
.initial_value(c_initial_val[0]),
.mode(c_mode_val[0]),
.ph_tap(c_ph_val[0]));
// Update /o counters mode and duty cycle immediately after configupdate is asserted
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[0] <= c_high_val_tmp[0];
c_mode_val[0] <= c_mode_val_tmp[0];
c0_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c0_rising_edge_transfer_done)
begin
c_low_val[0] <= c_low_val_tmp[0];
end
end
assign inclk_c1 = (c1_test_source == 0) ? fbclk : (c1_test_source == 1) ? refclk : (ic1_use_casc_in == 1) ? c0_clk : inclk_c1_from_vco;
cycloneive_scale_cntr c1 (.clk(inclk_c1),
.reset(areset || stop_vco),
.cout(c1_clk),
.high(c_high_val[1]),
.low(c_low_val[1]),
.initial_value(c_initial_val[1]),
.mode(c_mode_val[1]),
.ph_tap(c_ph_val[1]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[1] <= c_high_val_tmp[1];
c_mode_val[1] <= c_mode_val_tmp[1];
c1_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c1_rising_edge_transfer_done)
begin
c_low_val[1] <= c_low_val_tmp[1];
end
end
assign inclk_c2 = (c2_test_source == 0) ? fbclk : (c2_test_source == 1) ? refclk :(ic2_use_casc_in == 1) ? c1_clk : inclk_c2_from_vco;
cycloneive_scale_cntr c2 (.clk(inclk_c2),
.reset(areset || stop_vco),
.cout(c2_clk),
.high(c_high_val[2]),
.low(c_low_val[2]),
.initial_value(c_initial_val[2]),
.mode(c_mode_val[2]),
.ph_tap(c_ph_val[2]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[2] <= c_high_val_tmp[2];
c_mode_val[2] <= c_mode_val_tmp[2];
c2_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c2_rising_edge_transfer_done)
begin
c_low_val[2] <= c_low_val_tmp[2];
end
end
assign inclk_c3 = (c3_test_source == 0) ? fbclk : (c3_test_source == 1) ? refclk : (ic3_use_casc_in == 1) ? c2_clk : inclk_c3_from_vco;
cycloneive_scale_cntr c3 (.clk(inclk_c3),
.reset(areset || stop_vco),
.cout(c3_clk),
.high(c_high_val[3]),
.low(c_low_val[3]),
.initial_value(c_initial_val[3]),
.mode(c_mode_val[3]),
.ph_tap(c_ph_val[3]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[3] <= c_high_val_tmp[3];
c_mode_val[3] <= c_mode_val_tmp[3];
c3_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c3_rising_edge_transfer_done)
begin
c_low_val[3] <= c_low_val_tmp[3];
end
end
assign inclk_c4 = ((c4_test_source == 0) ? fbclk : (c4_test_source == 1) ? refclk : (ic4_use_casc_in == 1) ? c3_clk : inclk_c4_from_vco);
cycloneive_scale_cntr c4 (.clk(inclk_c4),
.reset(areset || stop_vco),
.cout(c4_clk),
.high(c_high_val[4]),
.low(c_low_val[4]),
.initial_value(c_initial_val[4]),
.mode(c_mode_val[4]),
.ph_tap(c_ph_val[4]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[4] <= c_high_val_tmp[4];
c_mode_val[4] <= c_mode_val_tmp[4];
c4_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c4_rising_edge_transfer_done)
begin
c_low_val[4] <= c_low_val_tmp[4];
end
end
assign locked = (test_bypass_lock_detect == "on") ? pfd_locked : locked_tmp;
// Register scanclk enable
always @(negedge scanclk)
scanclkena_reg <= scanclkena;
// Negative edge flip-flop in front of scan-chain
always @(negedge scanclk)
begin
if (scanclkena_reg)
begin
scandata_in <= scandata;
end
end
// Scan chain
always @(posedge scanclk)
begin
if (got_first_scanclk === 1'b0)
got_first_scanclk = 1'b1;
else
scanclk_period = $time - scanclk_last_rising_edge;
if (scanclkena_reg)
begin
for (j = scan_chain_length-2; j >= 0; j = j - 1)
scan_data[j] = scan_data[j - 1];
scan_data[-1] <= scandata_in;
end
scanclk_last_rising_edge = $realtime;
end
// Scan output
assign scandataout_tmp = scan_data[SCAN_CHAIN - 2];
// Negative edge flip-flop in rear of scan-chain
always @(negedge scanclk)
begin
if (scanclkena_reg)
begin
scandata_out <= scandataout_tmp;
end
end
// Scan complete
always @(negedge scandone_tmp)
begin
if (got_first_scanclk === 1'b1)
begin
if (reconfig_err == 1'b0)
begin
$display("NOTE : PLL Reprogramming completed with the following values (Values in parantheses are original values) : ");
$display ("Time: %0t Instance: %m", $time);
$display(" N modulus = %0d (%0d) ", n_val[0], n_val_old[0]);
$display(" M modulus = %0d (%0d) ", m_val[0], m_val_old[0]);
for (i = 0; i < num_output_cntrs; i=i+1)
begin
$display(" %s : C%0d high = %0d (%0d), C%0d low = %0d (%0d), C%0d mode = %s (%s)", clk_num[i],i, c_high_val[i], c_high_val_old[i], i, c_low_val_tmp[i], c_low_val_old[i], i, c_mode_val[i], c_mode_val_old[i]);
end
// display Charge pump and loop filter values
if (pll_reconfig_display_full_setting == 1'b1)
begin
$display (" Charge Pump Current (uA) = %0d (%0d) ", cp_curr_val, cp_curr_old);
$display (" Loop Filter Capacitor (pF) = %0d (%0d) ", lfc_val, lfc_old);
$display (" Loop Filter Resistor (Kohm) = %s (%s) ", lfr_val, lfr_old);
$display (" VCO_Post_Scale = %0d (%0d) ", vco_cur, vco_old);
end
else
begin
$display (" Charge Pump Current = %0d (%0d) ", cp_curr_bit_setting, cp_curr_old_bit_setting);
$display (" Loop Filter Capacitor = %0d (%0d) ", lfc_val_bit_setting, lfc_val_old_bit_setting);
$display (" Loop Filter Resistor = %0d (%0d) ", lfr_val_bit_setting, lfr_val_old_bit_setting);
$display (" VCO_Post_Scale = %b (%b) ", vco_val_bit_setting, vco_val_old_bit_setting);
end
cp_curr_old_bit_setting = cp_curr_bit_setting;
lfc_val_old_bit_setting = lfc_val_bit_setting;
lfr_val_old_bit_setting = lfr_val_bit_setting;
vco_val_old_bit_setting = vco_val_bit_setting;
end
else begin
$display("Warning : Errors were encountered during PLL reprogramming. Please refer to error/warning messages above.");
$display ("Time: %0t Instance: %m", $time);
end
end
end
// ************ PLL Phase Reconfiguration ************* //
// Latch updown,counter values at pos edge of scan clock
always @(posedge scanclk)
begin
if (phasestep_reg == 1'b1)
begin
if (phasestep_high_count == 1)
begin
phasecounterselect_reg <= phasecounterselect;
phaseupdown_reg <= phaseupdown;
// start reconfiguration
if (phasecounterselect < 3'b111) // no counters selected
begin
if (phasecounterselect == 0) // all output counters selected
begin
for (i = 0; i < num_output_cntrs; i = i + 1)
c_ph_val_tmp[i] = (phaseupdown == 1'b1) ?
(c_ph_val_tmp[i] + 1) % num_phase_taps :
(c_ph_val_tmp[i] == 0) ? num_phase_taps - 1 : (c_ph_val_tmp[i] - 1) % num_phase_taps ;
end
else if (phasecounterselect == 1) // select M counter
begin
m_ph_val_tmp = (phaseupdown == 1'b1) ?
(m_ph_val + 1) % num_phase_taps :
(m_ph_val == 0) ? num_phase_taps - 1 : (m_ph_val - 1) % num_phase_taps ;
end
else // select C counters
begin
select_counter = phasecounterselect - 2;
c_ph_val_tmp[select_counter] = (phaseupdown == 1'b1) ?
(c_ph_val_tmp[select_counter] + 1) % num_phase_taps :
(c_ph_val_tmp[select_counter] == 0) ? num_phase_taps - 1 : (c_ph_val_tmp[select_counter] - 1) % num_phase_taps ;
end
update_phase <= 1'b1;
end
end
phasestep_high_count = phasestep_high_count + 1;
end
end
// Latch phase enable (same as phasestep) on neg edge of scan clock
always @(negedge scanclk)
begin
phasestep_reg <= phasestep;
end
always @(posedge phasestep)
begin
if (update_phase == 1'b0) phasestep_high_count = 0; // phase adjustments must be 1 cycle apart
// if not, next phasestep cycle is skipped
end
// ************ PLL Full Reconfiguration ************* //
assign update_conf_latches = configupdate;
// reset counter transfer flags
always @(negedge scandone_tmp)
begin
c0_rising_edge_transfer_done = 0;
c1_rising_edge_transfer_done = 0;
c2_rising_edge_transfer_done = 0;
c3_rising_edge_transfer_done = 0;
c4_rising_edge_transfer_done = 0;
update_conf_latches_reg <= 1'b0;
end
always @(posedge update_conf_latches)
begin
initiate_reconfig <= 1'b1;
end
always @(posedge areset)
begin
if (scandone_tmp == 1'b1) scandone_tmp = 1'b0;
end
always @(posedge scanclk)
begin
if (initiate_reconfig == 1'b1)
begin
initiate_reconfig <= 1'b0;
$display ("NOTE : PLL Reprogramming initiated ....");
$display ("Time: %0t Instance: %m", $time);
scandone_tmp <= #(scanclk_period) 1'b1;
update_conf_latches_reg <= update_conf_latches;
error = 0;
reconfig_err = 0;
scanread_setup_violation = 0;
// save old values
cp_curr_old = cp_curr_val;
lfc_old = lfc_val;
lfr_old = lfr_val;
vco_old = vco_cur;
// save old values of bit settings
cp_curr_bit_setting = scan_data[14:16];
lfc_val_bit_setting = scan_data[1:2];
lfr_val_bit_setting = scan_data[3:7];
vco_val_bit_setting = scan_data[8];
// LF unused : bit 1
// LF Capacitance : bits 1,2 : all values are legal
if ((l_pll_type == "fast") || (l_pll_type == "lvds") || (l_pll_type == "left_right"))
lfc_val = fpll_loop_filter_c_arr[scan_data[1:2]];
else
lfc_val = loop_filter_c_arr[scan_data[1:2]];
// LF Resistance : bits 3-7
// valid values - 00000,00100,10000,10100,11000,11011,11100,11110
if (((scan_data[3:7] == 5'b00000) || (scan_data[3:7] == 5'b00100)) ||
((scan_data[3:7] == 5'b10000) || (scan_data[3:7] == 5'b10100)) ||
((scan_data[3:7] == 5'b11000) || (scan_data[3:7] == 5'b11011)) ||
((scan_data[3:7] == 5'b11100) || (scan_data[3:7] == 5'b11110))
)
begin
lfr_val = (scan_data[3:7] == 5'b00000) ? "20" :
(scan_data[3:7] == 5'b00100) ? "16" :
(scan_data[3:7] == 5'b10000) ? "12" :
(scan_data[3:7] == 5'b10100) ? "8" :
(scan_data[3:7] == 5'b11000) ? "6" :
(scan_data[3:7] == 5'b11011) ? "4" :
(scan_data[3:7] == 5'b11100) ? "2" : "1";
end
//VCO post scale value
if (scan_data[8] === 1'b1) // vco_post_scale = 1
begin
i_vco_max = i_vco_max_no_division/2;
i_vco_min = i_vco_min_no_division/2;
vco_cur = 1;
end
else
begin
i_vco_max = vco_max;
i_vco_min = vco_min;
vco_cur = 2;
end
// CP
// Bit 8 : CRBYPASS
// Bit 9-13 : unused
// Bits 14-16 : all values are legal
cp_curr_val = scan_data[14:16];
// save old values for display info.
for (i=0; i<=1; i=i+1)
begin
m_val_old[i] = m_val[i];
n_val_old[i] = n_val[i];
m_mode_val_old[i] = m_mode_val[i];
n_mode_val_old[i] = n_mode_val[i];
end
for (i=0; i< num_output_cntrs; i=i+1)
begin
c_high_val_old[i] = c_high_val[i];
c_low_val_old[i] = c_low_val[i];
c_mode_val_old[i] = c_mode_val[i];
end
// M counter
// 1. Mode - bypass (bit 17)
if (scan_data[17] == 1'b1)
n_mode_val[0] = "bypass";
// 3. Mode - odd/even (bit 26)
else if (scan_data[26] == 1'b1)
n_mode_val[0] = " odd";
else
n_mode_val[0] = " even";
// 2. High (bit 18-25)
n_hi = scan_data[18:25];
// 4. Low (bit 27-34)
n_lo = scan_data[27:34];
// N counter
// 1. Mode - bypass (bit 35)
if (scan_data[35] == 1'b1)
m_mode_val[0] = "bypass";
// 3. Mode - odd/even (bit 44)
else if (scan_data[44] == 1'b1)
m_mode_val[0] = " odd";
else
m_mode_val[0] = " even";
// 2. High (bit 36-43)
m_hi = scan_data[36:43];
// 4. Low (bit 45-52)
m_lo = scan_data[45:52];
//Update the current M and N counter values if the counters are NOT bypassed
if (m_mode_val[0] != "bypass")
m_val[0] = m_hi + m_lo;
if (n_mode_val[0] != "bypass")
n_val[0] = n_hi + n_lo;
// C counters (start bit 53) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
for (i = 0; i < num_output_cntrs; i = i + 1)
begin
// 1. Mode - bypass
if (scan_data[53 + i*18 + 0] == 1'b1)
c_mode_val_tmp[i] = "bypass";
// 3. Mode - odd/even
else if (scan_data[53 + i*18 + 9] == 1'b1)
c_mode_val_tmp[i] = " odd";
else
c_mode_val_tmp[i] = " even";
// 2. Hi
for (j = 1; j <= 8; j = j + 1)
c_val[8-j] = scan_data[53 + i*18 + j];
c_hval[i] = c_val[7:0];
if (c_hval[i] !== 32'h00000000)
c_high_val_tmp[i] = c_hval[i];
else
c_high_val_tmp[i] = 9'b100000000;
// 4. Low
for (j = 10; j <= 17; j = j + 1)
c_val[17 - j] = scan_data[53 + i*18 + j];
c_lval[i] = c_val[7:0];
if (c_lval[i] !== 32'h00000000)
c_low_val_tmp[i] = c_lval[i];
else
c_low_val_tmp[i] = 9'b100000000;
end
// Legality Checks
if (m_mode_val[0] != "bypass")
begin
if ((m_hi !== m_lo) && (m_mode_val[0] != " odd"))
begin
reconfig_err = 1;
$display ("Warning : The M counter of the %s Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work", family_name);
$display ("Time: %0t Instance: %m", $time);
end
else if (m_hi !== 8'b00000000)
begin
// counter value
m_val_tmp[0] = m_hi + m_lo;
end
else
m_val_tmp[0] = 9'b100000000;
end
else
m_val_tmp[0] = 8'b00000001;
if (n_mode_val[0] != "bypass")
begin
if ((n_hi !== n_lo) && (n_mode_val[0] != " odd"))
begin
reconfig_err = 1;
$display ("Warning : The N counter of the %s Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work", family_name);
$display ("Time: %0t Instance: %m", $time);
end
else if (n_hi !== 8'b00000000)
begin
// counter value
n_val[0] = n_hi + n_lo;
end
else
n_val[0] = 9'b100000000;
end
else
n_val[0] = 8'b00000001;
// TODO : Give warnings/errors in the following cases?
// 1. Illegal counter values (error)
// 2. Change of mode (warning)
// 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
end
end
// Self reset on loss of lock
assign reset_self = (l_self_reset_on_loss_lock == "on") ? ~pll_is_locked : 1'b0;
always @(posedge reset_self)
begin
$display (" Note : %s PLL self reset due to loss of lock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
// Phase shift on /o counters
always @(schedule_vco or areset)
begin
sched_time = 0;
for (i = 0; i <= 7; i=i+1)
last_phase_shift[i] = phase_shift[i];
cycle_to_adjust = 0;
l_index = 1;
m_times_vco_period = new_m_times_vco_period;
// give appropriate messages
// if areset was asserted
if (areset === 1'b1 && areset_last_value !== areset)
begin
$display (" Note : %s PLL was reset", family_name);
$display ("Time: %0t Instance: %m", $time);
// reset lock parameters
pll_is_locked = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
tap0_is_active = 0;
phase_adjust_was_scheduled = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
// illegal value on areset
if (areset === 1'bx && (areset_last_value === 1'b0 || areset_last_value === 1'b1))
begin
$display("Warning : Illegal value 'X' detected on ARESET input");
$display ("Time: %0t Instance: %m", $time);
end
if ((areset == 1'b1))
begin
pll_is_in_reset = 1;
got_first_refclk = 0;
got_second_refclk = 0;
end
if ((schedule_vco !== schedule_vco_last_value) && (areset == 1'b1 || stop_vco == 1'b1))
begin
// drop VCO taps to 0
for (i = 0; i <= 7; i=i+1)
begin
for (j = 0; j <= last_phase_shift[i] + 1; j=j+1)
vco_out[i] <= #(j) 1'b0;
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
// reset lock parameters
pll_is_locked = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
fbclk_period = 0;
first_schedule = 1;
vco_val = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
// reset all counter phase tap values to POF programmed values
m_ph_val = m_ph_val_orig;
for (i=0; i<= 5; i=i+1)
c_ph_val[i] = c_ph_val_orig[i];
end else if (areset === 1'b0 && stop_vco === 1'b0)
begin
// else note areset deassert time
// note it as refclk_time to prevent false triggering
// of stop_vco after areset
if (areset === 1'b0 && areset_last_value === 1'b1 && pll_is_in_reset === 1'b1)
begin
refclk_time = $time;
locked_tmp = 1'b0;
end
pll_is_in_reset = 0;
// calculate loop_xplier : this will be different from m_val in ext. fbk mode
loop_xplier = m_val[0];
loop_initial = i_m_initial - 1;
loop_ph = m_ph_val;
// convert initial value to delay
initial_delay = (loop_initial * m_times_vco_period)/loop_xplier;
// convert loop ph_tap to delay
rem = m_times_vco_period % loop_xplier;
vco_per = m_times_vco_period/loop_xplier;
if (rem != 0)
vco_per = vco_per + 1;
fbk_phase = (loop_ph * vco_per)/8;
pull_back_M = initial_delay + fbk_phase;
total_pull_back = pull_back_M;
if (l_simulation_type == "timing")
total_pull_back = total_pull_back + pll_compensation_delay;
while (total_pull_back > refclk_period)
total_pull_back = total_pull_back - refclk_period;
if (total_pull_back > 0)
offset = refclk_period - total_pull_back;
else
offset = 0;
fbk_delay = total_pull_back - fbk_phase;
if (fbk_delay < 0)
begin
offset = offset - fbk_phase;
fbk_delay = total_pull_back;
end
// assign m_delay
m_delay = fbk_delay;
for (i = 1; i <= loop_xplier; i=i+1)
begin
// adjust cycles
tmp_vco_per = m_times_vco_period/loop_xplier;
if (rem != 0 && l_index <= rem)
begin
tmp_rem = (loop_xplier * l_index) % rem;
cycle_to_adjust = (loop_xplier * l_index) / rem;
if (tmp_rem != 0)
cycle_to_adjust = cycle_to_adjust + 1;
end
if (cycle_to_adjust == i)
begin
tmp_vco_per = tmp_vco_per + 1;
l_index = l_index + 1;
end
// calculate high and low periods
high_time = tmp_vco_per/2;
if (tmp_vco_per % 2 != 0)
high_time = high_time + 1;
low_time = tmp_vco_per - high_time;
// schedule the rising and falling egdes
for (j=0; j<=1; j=j+1)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
// schedule taps with appropriate phase shifts
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
if (first_schedule)
vco_out[k] <= #(sched_time + phase_shift[k]) vco_val;
else
vco_out[k] <= #(sched_time + last_phase_shift[k]) vco_val;
end
end
end
if (first_schedule)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
vco_out[k] <= #(sched_time+phase_shift[k]) vco_val;
end
first_schedule = 0;
end
schedule_vco <= #(sched_time) ~schedule_vco;
if (vco_period_was_phase_adjusted)
begin
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 1;
tmp_vco_per = m_times_vco_period/loop_xplier;
for (k = 0; k <= 7; k=k+1)
phase_shift[k] = (k*tmp_vco_per)/8;
end
end
areset_last_value = areset;
schedule_vco_last_value = schedule_vco;
end
assign pfdena_wire = (pfdena === 1'b0) ? 1'b0 : 1'b1;
// PFD enable
always @(pfdena_wire)
begin
if (pfdena_wire === 1'b0)
begin
if (pll_is_locked)
locked_tmp = 1'bx;
pll_is_locked = 0;
cycles_to_lock = 0;
$display (" Note : PFDENA was deasserted");
$display ("Time: %0t Instance: %m", $time);
end
else if (pfdena_wire === 1'b1 && pfdena_last_value === 1'b0)
begin
// PFD was disabled, now enabled again
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = $time;
end
pfdena_last_value = pfdena_wire;
end
always @(negedge refclk or negedge fbclk)
begin
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
// Bypass lock detect
always @(posedge refclk)
begin
if (test_bypass_lock_detect == "on")
begin
if (pfdena_wire === 1'b1)
begin
cycles_pfd_low = 0;
if (pfd_locked == 1'b0)
begin
if (cycles_pfd_high == lock_high)
begin
$display ("Note : %s PLL locked in test mode on PFD enable assert", family_name);
$display ("Time: %0t Instance: %m", $time);
pfd_locked <= 1'b1;
end
cycles_pfd_high = cycles_pfd_high + 1;
end
end
if (pfdena_wire === 1'b0)
begin
cycles_pfd_high = 0;
if (pfd_locked == 1'b1)
begin
if (cycles_pfd_low == lock_low)
begin
$display ("Note : %s PLL lost lock in test mode on PFD enable deassert", family_name);
$display ("Time: %0t Instance: %m", $time);
pfd_locked <= 1'b0;
end
cycles_pfd_low = cycles_pfd_low + 1;
end
end
end
end
always @(posedge scandone_tmp or posedge locked_tmp)
begin
if(scandone_tmp == 1)
pll_has_just_been_reconfigured <= 1;
else
pll_has_just_been_reconfigured <= 0;
end
// VCO Frequency Range check
always @(posedge refclk or posedge fbclk)
begin
if (refclk == 1'b1 && refclk_last_value !== refclk && areset === 1'b0)
begin
if (! got_first_refclk)
begin
got_first_refclk = 1;
end else
begin
got_second_refclk = 1;
refclk_period = $time - refclk_time;
// check if incoming freq. will cause VCO range to be
// exceeded
if ((i_vco_max != 0 && i_vco_min != 0) && (pfdena_wire === 1'b1) &&
((refclk_period/loop_xplier > i_vco_max) ||
(refclk_period/loop_xplier < i_vco_min)) )
begin
if (pll_is_locked == 1'b1)
begin
if (refclk_period/loop_xplier > i_vco_max)
begin
$display ("Warning : Input clock freq. is over VCO range. %s PLL may lose lock", family_name);
vco_over = 1'b1;
end
if (refclk_period/loop_xplier < i_vco_min)
begin
$display ("Warning : Input clock freq. is under VCO range. %s PLL may lose lock", family_name);
vco_under = 1'b1;
end
$display ("Time: %0t Instance: %m", $time);
if (inclk_out_of_range === 1'b1)
begin
// unlock
pll_is_locked = 0;
locked_tmp = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
else begin
if (no_warn == 1'b0)
begin
if (refclk_period/loop_xplier > i_vco_max)
begin
$display ("Warning : Input clock freq. is over VCO range. %s PLL may lose lock", family_name);
vco_over = 1'b1;
end
if (refclk_period/loop_xplier < i_vco_min)
begin
$display ("Warning : Input clock freq. is under VCO range. %s PLL may lose lock", family_name);
vco_under = 1'b1;
end
$display ("Time: %0t Instance: %m", $time);
no_warn = 1'b1;
end
end
inclk_out_of_range = 1;
end
else begin
vco_over = 1'b0;
vco_under = 1'b0;
inclk_out_of_range = 0;
no_warn = 1'b0;
end
end
if (stop_vco == 1'b1)
begin
stop_vco = 0;
schedule_vco = ~schedule_vco;
end
refclk_time = $time;
end
// Update M counter value on feedback clock edge
if (fbclk == 1'b1 && fbclk_last_value !== fbclk)
begin
if (update_conf_latches === 1'b1)
begin
m_val[0] <= m_val_tmp[0];
m_val[1] <= m_val_tmp[1];
end
if (!got_first_fbclk)
begin
got_first_fbclk = 1;
first_fbclk_time = $time;
end
else
fbclk_period = $time - fbclk_time;
// need refclk_period here, so initialized to proper value above
if ( ( ($time - refclk_time > 1.5 * refclk_period) && pfdena_wire === 1'b1 && pll_is_locked === 1'b1) ||
( ($time - refclk_time > 5 * refclk_period) && (pfdena_wire === 1'b1) && (pll_has_just_been_reconfigured == 0) ) ||
( ($time - refclk_time > 50 * refclk_period) && (pfdena_wire === 1'b1) && (pll_has_just_been_reconfigured == 1) ) )
begin
stop_vco = 1;
// reset
got_first_refclk = 0;
got_first_fbclk = 0;
got_second_refclk = 0;
if (pll_is_locked == 1'b1)
begin
pll_is_locked = 0;
locked_tmp = 0;
$display ("Note : %s PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame.", family_name);
if ((i_vco_max == 0) && (i_vco_min == 0))
$display ("Note : Please run timing simulation to check whether the input clock is operating within the supported VCO range or not.");
$display ("Time: %0t Instance: %m", $time);
end
cycles_to_lock = 0;
cycles_to_unlock = 0;
first_schedule = 1;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
tap0_is_active = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
fbclk_time = $time;
end
// Core lock functionality
if (got_second_refclk && pfdena_wire === 1'b1 && (!inclk_out_of_range))
begin
// now we know actual incoming period
if (abs(fbclk_time - refclk_time) <= lock_window || (got_first_fbclk && abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window))
begin
// considered in phase
if (cycles_to_lock == real_lock_high)
begin
if (pll_is_locked === 1'b0)
begin
$display (" Note : %s PLL locked to incoming clock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
pll_is_locked = 1;
locked_tmp = 1;
cycles_to_unlock = 0;
end
// increment lock counter only if the second part of the above
// time check is not true
if (!(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window))
begin
cycles_to_lock = cycles_to_lock + 1;
end
// adjust m_times_vco_period
new_m_times_vco_period = refclk_period;
end else
begin
// if locked, begin unlock
if (pll_is_locked)
begin
cycles_to_unlock = cycles_to_unlock + 1;
if (cycles_to_unlock == lock_low)
begin
pll_is_locked = 0;
locked_tmp = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
got_first_refclk = 0;
got_first_fbclk = 0;
got_second_refclk = 0;
end
end
if (abs(refclk_period - fbclk_period) <= 2)
begin
// frequency is still good
if ($time == fbclk_time && (!phase_adjust_was_scheduled))
begin
if (abs(fbclk_time - refclk_time) > refclk_period/2)
begin
new_m_times_vco_period = abs(m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time)));
vco_period_was_phase_adjusted = 1;
end else
begin
new_m_times_vco_period = abs(m_times_vco_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted = 1;
end
end
end else
begin
new_m_times_vco_period = refclk_period;
phase_adjust_was_scheduled = 0;
end
end
end
if (reconfig_err == 1'b1)
begin
locked_tmp = 0;
end
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
assign clk_tmp[0] = i_clk0_counter == "c0" ? c0_clk : i_clk0_counter == "c1" ? c1_clk : i_clk0_counter == "c2" ? c2_clk : i_clk0_counter == "c3" ? c3_clk : i_clk0_counter == "c4" ? c4_clk : 1'b0;
assign clk_tmp[1] = i_clk1_counter == "c0" ? c0_clk : i_clk1_counter == "c1" ? c1_clk : i_clk1_counter == "c2" ? c2_clk : i_clk1_counter == "c3" ? c3_clk : i_clk1_counter == "c4" ? c4_clk : 1'b0;
assign clk_tmp[2] = i_clk2_counter == "c0" ? c0_clk : i_clk2_counter == "c1" ? c1_clk : i_clk2_counter == "c2" ? c2_clk : i_clk2_counter == "c3" ? c3_clk : i_clk2_counter == "c4" ? c4_clk : 1'b0;
assign clk_tmp[3] = i_clk3_counter == "c0" ? c0_clk : i_clk3_counter == "c1" ? c1_clk : i_clk3_counter == "c2" ? c2_clk : i_clk3_counter == "c3" ? c3_clk : i_clk3_counter == "c4" ? c4_clk : 1'b0;
assign clk_tmp[4] = i_clk4_counter == "c0" ? c0_clk : i_clk4_counter == "c1" ? c1_clk : i_clk4_counter == "c2" ? c2_clk : i_clk4_counter == "c3" ? c3_clk : i_clk4_counter == "c4" ? c4_clk : 1'b0;
assign clk_out_pfd[0] = (pfd_locked == 1'b1) ? clk_tmp[0] : 1'bx;
assign clk_out_pfd[1] = (pfd_locked == 1'b1) ? clk_tmp[1] : 1'bx;
assign clk_out_pfd[2] = (pfd_locked == 1'b1) ? clk_tmp[2] : 1'bx;
assign clk_out_pfd[3] = (pfd_locked == 1'b1) ? clk_tmp[3] : 1'bx;
assign clk_out_pfd[4] = (pfd_locked == 1'b1) ? clk_tmp[4] : 1'bx;
assign clk_out[0] = (test_bypass_lock_detect == "on") ? clk_out_pfd[0] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[0] : 1'bx);
assign clk_out[1] = (test_bypass_lock_detect == "on") ? clk_out_pfd[1] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[1] : 1'bx);
assign clk_out[2] = (test_bypass_lock_detect == "on") ? clk_out_pfd[2] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[2] : 1'bx);
assign clk_out[3] = (test_bypass_lock_detect == "on") ? clk_out_pfd[3] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[3] : 1'bx);
assign clk_out[4] = (test_bypass_lock_detect == "on") ? clk_out_pfd[4] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[4] : 1'bx);
// ACCELERATE OUTPUTS
and (clk[0], 1'b1, clk_out[0]);
and (clk[1], 1'b1, clk_out[1]);
and (clk[2], 1'b1, clk_out[2]);
and (clk[3], 1'b1, clk_out[3]);
and (clk[4], 1'b1, clk_out[4]);
and (scandataout, 1'b1, scandata_out);
and (scandone, 1'b1, scandone_tmp);
assign fbout = fbclk;
assign vcooverrange = (vco_range_detector_high_bits == -1) ? 1'bz : vco_over;
assign vcounderrange = (vco_range_detector_low_bits == -1) ? 1'bz :vco_under;
assign phasedone = ~update_phase;
endmodule // cycloneive_pll
//------------------------------------------------------------------
//
// Module Name : cycloneive_lcell_comb
//
// Description : Cyclone II LCELL_COMB Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneive_lcell_comb (
dataa,
datab,
datac,
datad,
cin,
combout,
cout
);
input dataa;
input datab;
input datac;
input datad;
input cin;
output combout;
output cout;
parameter lut_mask = 16'hFFFF;
parameter sum_lutc_input = "datac";
parameter dont_touch = "off";
parameter lpm_type = "cycloneive_lcell_comb";
reg cout_tmp;
reg combout_tmp;
reg [1:0] isum_lutc_input;
wire dataa_in;
wire datab_in;
wire datac_in;
wire datad_in;
wire cin_in;
buf (dataa_in, dataa);
buf (datab_in, datab);
buf (datac_in, datac);
buf (datad_in, datad);
buf (cin_in, cin);
specify
(dataa => combout) = (0, 0) ;
(datab => combout) = (0, 0) ;
(datac => combout) = (0, 0) ;
(datad => combout) = (0, 0) ;
(cin => combout) = (0, 0) ;
(dataa => cout) = (0, 0);
(datab => cout) = (0, 0);
(cin => cout) = (0, 0) ;
endspecify
// 4-input LUT function
function lut4;
input [15:0] mask;
input dataa;
input datab;
input datac;
input datad;
begin
lut4 = datad ? ( datac ? ( datab ? ( dataa ? mask[15] : mask[14])
: ( dataa ? mask[13] : mask[12]))
: ( datab ? ( dataa ? mask[11] : mask[10])
: ( dataa ? mask[ 9] : mask[ 8])))
: ( datac ? ( datab ? ( dataa ? mask[ 7] : mask[ 6])
: ( dataa ? mask[ 5] : mask[ 4]))
: ( datab ? ( dataa ? mask[ 3] : mask[ 2])
: ( dataa ? mask[ 1] : mask[ 0])));
end
endfunction
initial
begin
if (sum_lutc_input == "datac")
isum_lutc_input = 0;
else if (sum_lutc_input == "cin")
isum_lutc_input = 1;
else
begin
$display ("Error: Invalid sum_lutc_input specified\n");
$display ("Time: %0t Instance: %m", $time);
isum_lutc_input = 2;
end
end
always @(datad_in or datac_in or datab_in or dataa_in or cin_in)
begin
if (isum_lutc_input == 0) // datac
begin
combout_tmp = lut4(lut_mask, dataa_in, datab_in,
datac_in, datad_in);
end
else if (isum_lutc_input == 1) // cin
begin
combout_tmp = lut4(lut_mask, dataa_in, datab_in,
cin_in, datad_in);
end
cout_tmp = lut4(lut_mask, dataa_in, datab_in, cin_in, 'b0);
end
and (combout, combout_tmp, 1'b1) ;
and (cout, cout_tmp, 1'b1) ;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneive_ff
//
// Description : Cycloneive FF Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneive_ff (
d,
clk,
clrn,
aload,
sclr,
sload,
asdata,
ena,
devclrn,
devpor,
q
);
parameter power_up = "low";
parameter x_on_violation = "on";
parameter lpm_type = "cycloneive_ff";
input d;
input clk;
input clrn;
input aload;
input sclr;
input sload;
input asdata;
input ena;
input devclrn;
input devpor;
output q;
tri1 devclrn;
tri1 devpor;
reg q_tmp;
wire reset;
reg d_viol;
reg sclr_viol;
reg sload_viol;
reg asdata_viol;
reg ena_viol;
reg violation;
reg clk_last_value;
reg ix_on_violation;
wire d_in;
wire clk_in;
wire clrn_in;
wire aload_in;
wire sclr_in;
wire sload_in;
wire asdata_in;
wire ena_in;
wire nosloadsclr;
wire sloaddata;
buf (d_in, d);
buf (clk_in, clk);
buf (clrn_in, clrn);
buf (aload_in, aload);
buf (sclr_in, sclr);
buf (sload_in, sload);
buf (asdata_in, asdata);
buf (ena_in, ena);
assign reset = devpor && devclrn && clrn_in && ena_in;
assign nosloadsclr = reset && (!sload_in && !sclr_in);
assign sloaddata = reset && sload_in;
specify
$setuphold (posedge clk &&& nosloadsclr, d, 0, 0, d_viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, sclr_viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, sload_viol) ;
$setuphold (posedge clk &&& sloaddata, asdata, 0, 0, asdata_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
(posedge clrn => (q +: 1'b0)) = (0, 0) ;
(posedge aload => (q +: q_tmp)) = (0, 0) ;
(asdata => q) = (0, 0) ;
endspecify
initial
begin
violation = 'b0;
clk_last_value = 'b0;
if (power_up == "low")
q_tmp = 'b0;
else if (power_up == "high")
q_tmp = 'b1;
if (x_on_violation == "on")
ix_on_violation = 1;
else
ix_on_violation = 0;
end
always @ (d_viol or sclr_viol or sload_viol or ena_viol or asdata_viol)
begin
if (ix_on_violation == 1)
violation = 'b1;
end
always @ (asdata_in or clrn_in or posedge aload_in or
devclrn or devpor)
begin
if (devpor == 'b0)
q_tmp <= 'b0;
else if (devclrn == 'b0)
q_tmp <= 'b0;
else if (clrn_in == 'b0)
q_tmp <= 'b0;
else if (aload_in == 'b1)
q_tmp <= asdata_in;
end
always @ (clk_in or posedge clrn_in or posedge aload_in or
devclrn or devpor or posedge violation)
begin
if (violation == 1'b1)
begin
violation = 'b0;
q_tmp <= 'bX;
end
else
begin
if (devpor == 'b0 || devclrn == 'b0 || clrn_in === 'b0)
q_tmp <= 'b0;
else if (aload_in === 'b1)
q_tmp <= asdata_in;
else if (ena_in === 'b1 && clk_in === 'b1 && clk_last_value === 'b0)
begin
if (sclr_in === 'b1)
q_tmp <= 'b0 ;
else if (sload_in === 'b1)
q_tmp <= asdata_in;
else
q_tmp <= d_in;
end
end
clk_last_value = clk_in;
end
and (q, q_tmp, 1'b1);
endmodule
//--------------------------------------------------------------------------
// Module Name : cycloneive_ram_pulse_generator
// Description : Generate pulse to initiate memory read/write operations
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneive_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter delay_pulse = 1'b0;
parameter start_delay = (delay_pulse == 1'b0) ? 1 : 2; // delay write
reg state;
reg clk_prev;
wire clk_ipd;
specify
specparam t_decode = 0,t_access = 0;
(posedge clk => (pulse +: state)) = (t_decode,t_access);
endspecify
buf #(start_delay) (clk_ipd,clk);
wire pulse_opd;
buf buf_pulse (pulse,pulse_opd);
initial clk_prev = 1'bx;
always @(clk_ipd or posedge pulse)
begin
if (pulse) state <= 1'b0;
else if (ena && clk_ipd === 1'b1 && clk_prev === 1'b0) state <= 1'b1;
clk_prev = clk_ipd;
end
assign cycle = clk_ipd;
assign pulse_opd = state;
endmodule
//--------------------------------------------------------------------------
// Module Name : cycloneive_ram_register
// Description : Register module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneive_ram_register (
d,
clk,
aclr,
devclrn,
devpor,
stall,
ena,
q,
aclrout
);
parameter width = 1; // data width
parameter preset = 1'b0; // clear acts as preset
input [width - 1:0] d; // data
input clk; // clock
input aclr; // asynch clear
input devclrn,devpor; // device wide clear/reset
input stall; // address stall
input ena; // clock enable
output [width - 1:0] q; // register output
output aclrout; // delayed asynch clear
wire ena_ipd;
wire clk_ipd;
wire aclr_ipd;
wire [width - 1:0] d_ipd;
buf buf_ena (ena_ipd,ena);
buf buf_clk (clk_ipd,clk);
buf buf_aclr (aclr_ipd,aclr);
buf buf_d [width - 1:0] (d_ipd,d);
wire stall_ipd;
buf buf_stall (stall_ipd,stall);
wire [width - 1:0] q_opd;
buf buf_q [width - 1:0] (q,q_opd);
reg [width - 1:0] q_reg;
reg viol_notifier;
wire reset;
assign reset = devpor && devclrn && (!aclr_ipd) && (ena_ipd);
specify
$setup (d, posedge clk &&& reset, 0, viol_notifier);
$setup (aclr, posedge clk, 0, viol_notifier);
$setup (ena, posedge clk &&& reset, 0, viol_notifier );
$setup (stall, posedge clk &&& reset, 0, viol_notifier );
$hold (posedge clk &&& reset, d , 0, viol_notifier);
$hold (posedge clk, aclr, 0, viol_notifier);
$hold (posedge clk &&& reset, ena , 0, viol_notifier );
$hold (posedge clk &&& reset, stall, 0, viol_notifier );
(posedge clk => (q +: q_reg)) = (0,0);
(posedge aclr => (q +: q_reg)) = (0,0);
endspecify
initial q_reg <= (preset) ? {width{1'b1}} : 'b0;
always @(posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (aclr_ipd || ~devclrn || ~devpor)
q_reg <= (preset) ? {width{1'b1}} : 'b0;
else if (ena_ipd & !stall_ipd)
q_reg <= d_ipd;
end
assign aclrout = aclr_ipd;
assign q_opd = q_reg;
endmodule
`timescale 1 ps/1 ps
`define PRIME 1
`define SEC 0
//--------------------------------------------------------------------------
// Module Name : cycloneive_ram_block
// Description : Main RAM module
//--------------------------------------------------------------------------
module cycloneive_ram_block
(
portadatain,
portaaddr,
portawe,
portare,
portbdatain,
portbaddr,
portbwe,
portbre,
clk0, clk1,
ena0, ena1,
ena2, ena3,
clr0, clr1,
portabyteenamasks,
portbbyteenamasks,
portaaddrstall,
portbaddrstall,
devclrn,
devpor,
portadataout,
portbdataout
);
// -------- GLOBAL PARAMETERS ---------
parameter operation_mode = "single_port";
parameter mixed_port_feed_through_mode = "dont_care";
parameter ram_block_type = "auto";
parameter logical_ram_name = "ram_name";
parameter init_file = "init_file.hex";
parameter init_file_layout = "none";
parameter data_interleave_width_in_bits = 1;
parameter data_interleave_offset_in_bits = 1;
parameter port_a_logical_ram_depth = 0;
parameter port_a_logical_ram_width = 0;
parameter port_a_first_address = 0;
parameter port_a_last_address = 0;
parameter port_a_first_bit_number = 0;
parameter port_a_data_out_clear = "none";
parameter port_a_data_out_clock = "none";
parameter port_a_data_width = 1;
parameter port_a_address_width = 1;
parameter port_a_byte_enable_mask_width = 1;
parameter port_b_logical_ram_depth = 0;
parameter port_b_logical_ram_width = 0;
parameter port_b_first_address = 0;
parameter port_b_last_address = 0;
parameter port_b_first_bit_number = 0;
parameter port_b_address_clear = "none";
parameter port_b_data_out_clear = "none";
parameter port_b_data_in_clock = "clock1";
parameter port_b_address_clock = "clock1";
parameter port_b_write_enable_clock = "clock1";
parameter port_b_read_enable_clock = "clock1";
parameter port_b_byte_enable_clock = "clock1";
parameter port_b_data_out_clock = "none";
parameter port_b_data_width = 1;
parameter port_b_address_width = 1;
parameter port_b_byte_enable_mask_width = 1;
parameter port_a_read_during_write_mode = "new_data_no_nbe_read";
parameter port_b_read_during_write_mode = "new_data_no_nbe_read";
parameter power_up_uninitialized = "false";
parameter lpm_type = "cycloneive_ram_block";
parameter lpm_hint = "true";
parameter connectivity_checking = "off";
parameter mem_init0 = 2048'b0;
parameter mem_init1 = 2048'b0;
parameter mem_init2 = 2048'b0;
parameter mem_init3 = 2048'b0;
parameter mem_init4 = 2048'b0;
parameter port_a_byte_size = 0;
parameter port_b_byte_size = 0;
parameter safe_write = "err_on_2clk";
parameter init_file_restructured = "unused";
parameter clk0_input_clock_enable = "none"; // ena0,ena2,none
parameter clk0_core_clock_enable = "none"; // ena0,ena2,none
parameter clk0_output_clock_enable = "none"; // ena0,none
parameter clk1_input_clock_enable = "none"; // ena1,ena3,none
parameter clk1_core_clock_enable = "none"; // ena1,ena3,none
parameter clk1_output_clock_enable = "none"; // ena1,none
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter port_a_address_clear = "none";
parameter port_a_data_in_clock = "clock0";
parameter port_a_address_clock = "clock0";
parameter port_a_write_enable_clock = "clock0";
parameter port_a_byte_enable_clock = "clock0";
parameter port_a_read_enable_clock = "clock0";
// SIMULATION_ONLY_PARAMETERS_END
// LOCAL_PARAMETERS_BEGIN
parameter primary_port_is_a = (port_b_data_width <= port_a_data_width) ? 1'b1 : 1'b0;
parameter primary_port_is_b = ~primary_port_is_a;
parameter mode_is_rom_or_sp = ((operation_mode == "rom") || (operation_mode == "single_port")) ? 1'b1 : 1'b0;
parameter data_width = (primary_port_is_a) ? port_a_data_width : port_b_data_width;
parameter data_unit_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_data_width : port_b_data_width;
parameter address_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_address_width : port_b_address_width;
parameter address_unit_width = (mode_is_rom_or_sp | primary_port_is_a) ? port_a_address_width : port_b_address_width;
parameter wired_mode = ((port_a_address_width == 1) && (port_a_address_width == port_b_address_width)
&& (port_a_data_width != port_b_data_width));
parameter num_rows = 1 << address_unit_width;
parameter num_cols = (mode_is_rom_or_sp) ? 1 : ( wired_mode ? 2 :
( (primary_port_is_a) ?
1 << (port_b_address_width - port_a_address_width) :
1 << (port_a_address_width - port_b_address_width) ) ) ;
parameter mask_width_prime = (primary_port_is_a) ?
port_a_byte_enable_mask_width : port_b_byte_enable_mask_width;
parameter mask_width_sec = (primary_port_is_a) ?
port_b_byte_enable_mask_width : port_a_byte_enable_mask_width;
parameter byte_size_a = port_a_data_width/port_a_byte_enable_mask_width;
parameter byte_size_b = port_b_data_width/port_b_byte_enable_mask_width;
parameter mode_is_dp = (operation_mode == "dual_port") ? 1'b1 : 1'b0;
// Hardware write modes
parameter dual_clock = ((operation_mode == "dual_port") ||
(operation_mode == "bidir_dual_port")) &&
(port_b_address_clock == "clock1");
parameter both_new_data_same_port = (
((port_a_read_during_write_mode == "new_data_no_nbe_read") ||
(port_a_read_during_write_mode == "dont_care")) &&
((port_b_read_during_write_mode == "new_data_no_nbe_read") ||
(port_b_read_during_write_mode == "dont_care"))
) ? 1'b1 : 1'b0;
parameter hw_write_mode_a = (
((port_a_read_during_write_mode == "old_data") ||
(port_a_read_during_write_mode == "new_data_with_nbe_read"))
) ? "R+W" : (
dual_clock || (
mixed_port_feed_through_mode == "dont_care" &&
both_new_data_same_port
) ? "FW" : "DW"
);
parameter hw_write_mode_b = (
((port_b_read_during_write_mode == "old_data") ||
(port_b_read_during_write_mode == "new_data_with_nbe_read"))
) ? "R+W" : (
dual_clock || (
mixed_port_feed_through_mode == "dont_care" &&
both_new_data_same_port
) ? "FW" : "DW"
);
parameter delay_write_pulse_a = (hw_write_mode_a != "FW") ? 1'b1 : 1'b0;
parameter delay_write_pulse_b = (hw_write_mode_b != "FW") ? 1'b1 : 1'b0;
parameter be_mask_write_a = (port_a_read_during_write_mode == "new_data_with_nbe_read") ? 1'b1 : 1'b0;
parameter be_mask_write_b = (port_b_read_during_write_mode == "new_data_with_nbe_read") ? 1'b1 : 1'b0;
parameter old_data_write_a = (port_a_read_during_write_mode == "old_data") ? 1'b1 : 1'b0;
parameter old_data_write_b = (port_b_read_during_write_mode == "old_data") ? 1'b1 : 1'b0;
parameter read_before_write_a = (hw_write_mode_a == "R+W") ? 1'b1 : 1'b0;
parameter read_before_write_b = (hw_write_mode_b == "R+W") ? 1'b1 : 1'b0;
// LOCAL_PARAMETERS_END
// -------- PORT DECLARATIONS ---------
input portawe;
input portare;
input [port_a_data_width - 1:0] portadatain;
input [port_a_address_width - 1:0] portaaddr;
input [port_a_byte_enable_mask_width - 1:0] portabyteenamasks;
input portbwe, portbre;
input [port_b_data_width - 1:0] portbdatain;
input [port_b_address_width - 1:0] portbaddr;
input [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks;
input clr0,clr1;
input clk0,clk1;
input ena0,ena1;
input ena2,ena3;
input devclrn,devpor;
input portaaddrstall;
input portbaddrstall;
output [port_a_data_width - 1:0] portadataout;
output [port_b_data_width - 1:0] portbdataout;
tri0 portawe_int;
assign portawe_int = portawe;
tri1 portare_int;
assign portare_int = portare;
tri0 [port_a_data_width - 1:0] portadatain_int;
assign portadatain_int = portadatain;
tri0 [port_a_address_width - 1:0] portaaddr_int;
assign portaaddr_int = portaaddr;
tri1 [port_a_byte_enable_mask_width - 1:0] portabyteenamasks_int;
assign portabyteenamasks_int = portabyteenamasks;
tri0 portbwe_int;
assign portbwe_int = portbwe;
tri1 portbre_int;
assign portbre_int = portbre;
tri0 [port_b_data_width - 1:0] portbdatain_int;
assign portbdatain_int = portbdatain;
tri0 [port_b_address_width - 1:0] portbaddr_int;
assign portbaddr_int = portbaddr;
tri1 [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks_int;
assign portbbyteenamasks_int = portbbyteenamasks;
tri0 clr0_int,clr1_int;
assign clr0_int = clr0;
assign clr1_int = clr1;
tri0 clk0_int,clk1_int;
assign clk0_int = clk0;
assign clk1_int = clk1;
tri1 ena0_int,ena1_int;
assign ena0_int = ena0;
assign ena1_int = ena1;
tri1 ena2_int,ena3_int;
assign ena2_int = ena2;
assign ena3_int = ena3;
tri0 portaaddrstall_int;
assign portaaddrstall_int = portaaddrstall;
tri0 portbaddrstall_int;
assign portbaddrstall_int = portbaddrstall;
tri1 devclrn;
tri1 devpor;
// -------- INTERNAL signals ---------
// clock / clock enable
wire clk_a_in,clk_a_byteena,clk_a_out,clkena_a_out;
wire clk_a_rena, clk_a_wena;
wire clk_a_core;
wire clk_b_in,clk_b_byteena,clk_b_out,clkena_b_out;
wire clk_b_rena, clk_b_wena;
wire clk_b_core;
wire write_cycle_a,write_cycle_b;
// asynch clear
wire datain_a_clr,dataout_a_clr,datain_b_clr,dataout_b_clr;
wire dataout_a_clr_reg, dataout_b_clr_reg;
wire dataout_a_clr_reg_latch, dataout_b_clr_reg_latch;
wire addr_a_clr,addr_b_clr;
wire byteena_a_clr,byteena_b_clr;
wire we_a_clr, re_a_clr, we_b_clr, re_b_clr;
wire datain_a_clr_in,datain_b_clr_in;
wire addr_a_clr_in,addr_b_clr_in;
wire byteena_a_clr_in,byteena_b_clr_in;
wire we_a_clr_in, re_a_clr_in, we_b_clr_in, re_b_clr_in;
reg mem_invalidate;
wire [`PRIME:`SEC] clear_asserted_during_write;
reg clear_asserted_during_write_a,clear_asserted_during_write_b;
// port A registers
wire we_a_reg;
wire re_a_reg;
wire [port_a_address_width - 1:0] addr_a_reg;
wire [port_a_data_width - 1:0] datain_a_reg, dataout_a_reg;
reg [port_a_data_width - 1:0] dataout_a;
wire [port_a_byte_enable_mask_width - 1:0] byteena_a_reg;
reg out_a_is_reg;
// port B registers
wire we_b_reg, re_b_reg;
wire [port_b_address_width - 1:0] addr_b_reg;
wire [port_b_data_width - 1:0] datain_b_reg, dataout_b_reg;
reg [port_b_data_width - 1:0] dataout_b;
wire [port_b_byte_enable_mask_width - 1:0] byteena_b_reg;
reg out_b_is_reg;
// placeholders for read/written data
reg [data_width - 1:0] read_data_latch;
reg [data_width - 1:0] mem_data;
reg [data_width - 1:0] old_mem_data;
reg [data_unit_width - 1:0] read_unit_data_latch;
reg [data_width - 1:0] mem_unit_data;
// pulses for A/B ports
wire write_pulse_a,write_pulse_b;
wire read_pulse_a,read_pulse_b;
wire read_pulse_a_feedthru,read_pulse_b_feedthru;
wire rw_pulse_a, rw_pulse_b;
wire [address_unit_width - 1:0] addr_prime_reg; // registered address
wire [address_width - 1:0] addr_sec_reg;
wire [data_width - 1:0] datain_prime_reg; // registered data
wire [data_unit_width - 1:0] datain_sec_reg;
// pulses for primary/secondary ports
wire write_pulse_prime,write_pulse_sec;
wire read_pulse_prime,read_pulse_sec;
wire read_pulse_prime_feedthru,read_pulse_sec_feedthru;
wire rw_pulse_prime, rw_pulse_sec;
reg read_pulse_prime_last_value, read_pulse_sec_last_value;
reg rw_pulse_prime_last_value, rw_pulse_sec_last_value;
reg [`PRIME:`SEC] dual_write; // simultaneous write to same location
// (row,column) coordinates
reg [address_unit_width - 1:0] row_sec;
reg [address_width + data_unit_width - address_unit_width - 1:0] col_sec;
// memory core
reg [data_width - 1:0] mem [num_rows - 1:0];
// byte enable
wire [data_width - 1:0] mask_vector_prime, mask_vector_prime_int;
wire [data_unit_width - 1:0] mask_vector_sec, mask_vector_sec_int;
reg [data_unit_width - 1:0] mask_vector_common_int;
reg [port_a_data_width - 1:0] mask_vector_a, mask_vector_a_int;
reg [port_b_data_width - 1:0] mask_vector_b, mask_vector_b_int;
// memory initialization
integer i,j,k,l;
integer addr_range_init;
reg [data_width - 1:0] init_mem_word;
reg [(port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1:0] mem_init;
// port active for read/write
wire active_a_in, active_b_in;
wire active_a_core,active_a_core_in,active_b_core,active_b_core_in;
wire active_write_a,active_write_b,active_write_clear_a,active_write_clear_b;
reg mode_is_rom,mode_is_sp,mode_is_bdp; // ram mode
reg ram_type; // ram type eg. MRAM
initial
begin
`ifdef QUARTUS_MEMORY_PLI
$memory_connect(mem);
`endif
ram_type = 0;
mode_is_rom = (operation_mode == "rom");
mode_is_sp = (operation_mode == "single_port");
mode_is_bdp = (operation_mode == "bidir_dual_port");
out_a_is_reg = (port_a_data_out_clock == "none") ? 1'b0 : 1'b1;
out_b_is_reg = (port_b_data_out_clock == "none") ? 1'b0 : 1'b1;
// powerup output latches to 0
dataout_a = 'b0;
if (mode_is_dp || mode_is_bdp) dataout_b = 'b0;
if ((power_up_uninitialized == "false") && ~ram_type)
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'b0;
if ((init_file_layout == "port_a") || (init_file_layout == "port_b"))
begin
mem_init = {
mem_init4 , mem_init3 , mem_init2 ,
mem_init1 , mem_init0
};
addr_range_init = (primary_port_is_a) ?
port_a_last_address - port_a_first_address + 1 :
port_b_last_address - port_b_first_address + 1 ;
for (j = 0; j < addr_range_init; j = j + 1)
begin
for (k = 0; k < data_width; k = k + 1)
init_mem_word[k] = mem_init[j*data_width + k];
mem[j] = init_mem_word;
end
end
dual_write = 'b0;
end
assign clk_a_in = clk0_int;
assign clk_a_wena = (port_a_write_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_rena = (port_a_read_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_byteena = (port_a_byte_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_out = (port_a_data_out_clock == "none") ? 1'b0 : (
(port_a_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_in = (port_b_address_clock == "clock0") ? clk0_int : clk1_int;
assign clk_b_byteena = (port_b_byte_enable_clock == "none") ? 1'b0 : (
(port_b_byte_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_wena = (port_b_write_enable_clock == "none") ? 1'b0 : (
(port_b_write_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_rena = (port_b_read_enable_clock == "none") ? 1'b0 : (
(port_b_read_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_out = (port_b_data_out_clock == "none") ? 1'b0 : (
(port_b_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign addr_a_clr_in = (port_a_address_clear == "none") ? 1'b0 : clr0_int;
assign addr_b_clr_in = (port_b_address_clear == "none") ? 1'b0 : (
(port_b_address_clear == "clear0") ? clr0_int : clr1_int);
assign datain_a_clr_in = 1'b0;
assign dataout_a_clr = (port_a_data_out_clock == "none") ? (
(port_a_data_out_clear == "none") ? 1'b0 : (
(port_a_data_out_clear == "clear0") ? clr0_int : clr1_int)) : 1'b0;
assign dataout_a_clr_reg = (port_a_data_out_clear == "none") ? 1'b0 : (
(port_a_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign datain_b_clr_in = 1'b0;
assign dataout_b_clr = (port_b_data_out_clock == "none") ? (
(port_b_data_out_clear == "none") ? 1'b0 : (
(port_b_data_out_clear == "clear0") ? clr0_int : clr1_int)) : 1'b0;
assign dataout_b_clr_reg = (port_b_data_out_clear == "none") ? 1'b0 : (
(port_b_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign byteena_a_clr_in = 1'b0;
assign byteena_b_clr_in = 1'b0;
assign we_a_clr_in = 1'b0;
assign re_a_clr_in = 1'b0;
assign we_b_clr_in = 1'b0;
assign re_b_clr_in = 1'b0;
assign active_a_in = (clk0_input_clock_enable == "none") ? 1'b1 : (
(clk0_input_clock_enable == "ena0") ? ena0_int : ena2_int
);
assign active_a_core_in = (clk0_core_clock_enable == "none") ? 1'b1 : (
(clk0_core_clock_enable == "ena0") ? ena0_int : ena2_int
);
assign active_b_in = (port_b_address_clock == "clock0") ? (
(clk0_input_clock_enable == "none") ? 1'b1 : ((clk0_input_clock_enable == "ena0") ? ena0_int : ena2_int)
) : (
(clk1_input_clock_enable == "none") ? 1'b1 : ((clk1_input_clock_enable == "ena1") ? ena1_int : ena3_int)
);
assign active_b_core_in = (port_b_address_clock == "clock0") ? (
(clk0_core_clock_enable == "none") ? 1'b1 : ((clk0_core_clock_enable == "ena0") ? ena0_int : ena2_int)
) : (
(clk1_core_clock_enable == "none") ? 1'b1 : ((clk1_core_clock_enable == "ena1") ? ena1_int : ena3_int)
);
assign active_write_a = (byteena_a_reg !== 'b0);
assign active_write_b = (byteena_b_reg !== 'b0);
// Store core clock enable value for delayed write
// port A core active
cycloneive_ram_register active_core_port_a (
.d(active_a_core_in),
.clk(clk_a_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.stall(1'b0),
.ena(1'b1),
.q(active_a_core),.aclrout()
);
defparam active_core_port_a.width = 1;
// port B core active
cycloneive_ram_register active_core_port_b (
.d(active_b_core_in),
.clk(clk_b_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.stall(1'b0),
.ena(1'b1),
.q(active_b_core),.aclrout()
);
defparam active_core_port_b.width = 1;
// ------- A input registers -------
// write enable
cycloneive_ram_register we_a_register (
.d(mode_is_rom ? 1'b0 : portawe_int),
.clk(clk_a_wena),
.aclr(we_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(we_a_reg),
.aclrout(we_a_clr)
);
defparam we_a_register.width = 1;
// read enable
cycloneive_ram_register re_a_register (
.d(portare_int),
.clk(clk_a_rena),
.aclr(re_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(re_a_reg),
.aclrout(re_a_clr)
);
// address
cycloneive_ram_register addr_a_register (
.d(portaaddr_int),
.clk(clk_a_in),
.aclr(addr_a_clr_in),
.devclrn(devclrn),.devpor(devpor),
.stall(portaaddrstall_int),
.ena(active_a_in),
.q(addr_a_reg),
.aclrout(addr_a_clr)
);
defparam addr_a_register.width = port_a_address_width;
// data
cycloneive_ram_register datain_a_register (
.d(portadatain_int),
.clk(clk_a_in),
.aclr(datain_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(datain_a_reg),
.aclrout(datain_a_clr)
);
defparam datain_a_register.width = port_a_data_width;
// byte enable
cycloneive_ram_register byteena_a_register (
.d(portabyteenamasks_int),
.clk(clk_a_byteena),
.aclr(byteena_a_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_a_in),
.q(byteena_a_reg),
.aclrout(byteena_a_clr)
);
defparam byteena_a_register.width = port_a_byte_enable_mask_width;
defparam byteena_a_register.preset = 1'b1;
// ------- B input registers -------
// write enable
cycloneive_ram_register we_b_register (
.d(portbwe_int),
.clk(clk_b_wena),
.aclr(we_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(we_b_reg),
.aclrout(we_b_clr)
);
defparam we_b_register.width = 1;
defparam we_b_register.preset = 1'b0;
// read enable
cycloneive_ram_register re_b_register (
.d(portbre_int),
.clk(clk_b_rena),
.aclr(re_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(re_b_reg),
.aclrout(re_b_clr)
);
defparam re_b_register.width = 1;
defparam re_b_register.preset = 1'b0;
// address
cycloneive_ram_register addr_b_register (
.d(portbaddr_int),
.clk(clk_b_in),
.aclr(addr_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(portbaddrstall_int),
.ena(active_b_in),
.q(addr_b_reg),
.aclrout(addr_b_clr)
);
defparam addr_b_register.width = port_b_address_width;
// data
cycloneive_ram_register datain_b_register (
.d(portbdatain_int),
.clk(clk_b_in),
.aclr(datain_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_b_in),
.q(datain_b_reg),
.aclrout(datain_b_clr)
);
defparam datain_b_register.width = port_b_data_width;
// byte enable
cycloneive_ram_register byteena_b_register (
.d(portbbyteenamasks_int),
.clk(clk_b_byteena),
.aclr(byteena_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(byteena_b_reg),
.aclrout(byteena_b_clr)
);
defparam byteena_b_register.width = port_b_byte_enable_mask_width;
defparam byteena_b_register.preset = 1'b1;
assign datain_prime_reg = (primary_port_is_a) ? datain_a_reg : datain_b_reg;
assign addr_prime_reg = (primary_port_is_a) ? addr_a_reg : addr_b_reg;
assign datain_sec_reg = (primary_port_is_a) ? datain_b_reg : datain_a_reg;
assign addr_sec_reg = (primary_port_is_a) ? addr_b_reg : addr_a_reg;
assign mask_vector_prime = (primary_port_is_a) ? mask_vector_a : mask_vector_b;
assign mask_vector_prime_int = (primary_port_is_a) ? mask_vector_a_int : mask_vector_b_int;
assign mask_vector_sec = (primary_port_is_a) ? mask_vector_b : mask_vector_a;
assign mask_vector_sec_int = (primary_port_is_a) ? mask_vector_b_int : mask_vector_a_int;
// Hardware Write Modes
// CYCLONEIVE
// Write pulse generation
cycloneive_ram_pulse_generator wpgen_a (
.clk(clk_a_in),
.ena(active_a_core & active_write_a & we_a_reg),
.pulse(write_pulse_a),
.cycle(write_cycle_a)
);
defparam wpgen_a.delay_pulse = delay_write_pulse_a;
cycloneive_ram_pulse_generator wpgen_b (
.clk(clk_b_in),
.ena(active_b_core & active_write_b & mode_is_bdp & we_b_reg),
.pulse(write_pulse_b),
.cycle(write_cycle_b)
);
defparam wpgen_b.delay_pulse = delay_write_pulse_b;
// Read pulse generation
cycloneive_ram_pulse_generator rpgen_a (
.clk(clk_a_in),
.ena(active_a_core & re_a_reg & ~we_a_reg & ~dataout_a_clr),
.pulse(read_pulse_a),
.cycle(clk_a_core)
);
cycloneive_ram_pulse_generator rpgen_b (
.clk(clk_b_in),
.ena((mode_is_dp | mode_is_bdp) & active_b_core & re_b_reg & ~we_b_reg & ~dataout_b_clr),
.pulse(read_pulse_b),
.cycle(clk_b_core)
);
// Read during write pulse generation
cycloneive_ram_pulse_generator rwpgen_a (
.clk(clk_a_in),
.ena(active_a_core & re_a_reg & we_a_reg & read_before_write_a & ~dataout_a_clr),
.pulse(rw_pulse_a),.cycle()
);
cycloneive_ram_pulse_generator rwpgen_b (
.clk(clk_b_in),
.ena(active_b_core & mode_is_bdp & re_b_reg & we_b_reg & read_before_write_b & ~dataout_b_clr),
.pulse(rw_pulse_b),.cycle()
);
assign write_pulse_prime = (primary_port_is_a) ? write_pulse_a : write_pulse_b;
assign read_pulse_prime = (primary_port_is_a) ? read_pulse_a : read_pulse_b;
assign read_pulse_prime_feedthru = (primary_port_is_a) ? read_pulse_a_feedthru : read_pulse_b_feedthru;
assign rw_pulse_prime = (primary_port_is_a) ? rw_pulse_a : rw_pulse_b;
assign write_pulse_sec = (primary_port_is_a) ? write_pulse_b : write_pulse_a;
assign read_pulse_sec = (primary_port_is_a) ? read_pulse_b : read_pulse_a;
assign read_pulse_sec_feedthru = (primary_port_is_a) ? read_pulse_b_feedthru : read_pulse_a_feedthru;
assign rw_pulse_sec = (primary_port_is_a) ? rw_pulse_b : rw_pulse_a;
// Create internal masks for byte enable processing
always @(byteena_a_reg)
begin
for (i = 0; i < port_a_data_width; i = i + 1)
begin
mask_vector_a[i] = (byteena_a_reg[i/byte_size_a] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_a_int[i] = (byteena_a_reg[i/byte_size_a] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(byteena_b_reg)
begin
for (l = 0; l < port_b_data_width; l = l + 1)
begin
mask_vector_b[l] = (byteena_b_reg[l/byte_size_b] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_b_int[l] = (byteena_b_reg[l/byte_size_b] === 1'b0) ? 1'b0 : 1'bx;
end
end
// Latch Clear port A
always @(posedge dataout_a_clr)
begin
if (primary_port_is_a) begin read_data_latch = 'b0; dataout_a = 'b0; end
else begin read_unit_data_latch = 'b0; dataout_a = 'b0; end
end
// Latch Clear port B
always @(posedge dataout_b_clr)
begin
if (primary_port_is_b) begin read_data_latch = 'b0; dataout_b = 'b0; end
else begin read_unit_data_latch = 'b0; dataout_b = 'b0; end
end
always @(posedge write_pulse_prime or posedge write_pulse_sec or
posedge read_pulse_prime or posedge read_pulse_sec
or posedge rw_pulse_prime or posedge rw_pulse_sec
)
begin
// Read before Write stage 1 : read data from memory
if (rw_pulse_prime && (rw_pulse_prime !== rw_pulse_prime_last_value))
begin
read_data_latch = mem[addr_prime_reg];
rw_pulse_prime_last_value = rw_pulse_prime;
end
if (rw_pulse_sec && (rw_pulse_sec !== rw_pulse_sec_last_value))
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
rw_pulse_sec_last_value = rw_pulse_sec;
end
// Write stage 1 : write X to memory
if (write_pulse_prime)
begin
old_mem_data = mem[addr_prime_reg];
mem_data = mem[addr_prime_reg] ^ mask_vector_prime_int;
mem[addr_prime_reg] = mem_data;
if ((row_sec == addr_prime_reg) && (read_pulse_sec))
begin
mem_unit_data = (mixed_port_feed_through_mode == "dont_care") ? {data_width{1'bx}} : old_mem_data;
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
end
end
if (write_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = mem_unit_data[j] ^ mask_vector_sec_int[j - col_sec];
mem[row_sec] = mem_unit_data;
end
if ((addr_prime_reg == row_sec) && write_pulse_prime && write_pulse_sec) dual_write = 2'b11;
// Read stage 1 : read data from memory
if (read_pulse_prime && read_pulse_prime !== read_pulse_prime_last_value)
begin
read_data_latch = mem[addr_prime_reg];
read_pulse_prime_last_value = read_pulse_prime;
end
if (read_pulse_sec && read_pulse_sec !== read_pulse_sec_last_value)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
if ((row_sec == addr_prime_reg) && (write_pulse_prime))
mem_unit_data = (mixed_port_feed_through_mode == "dont_care") ? {data_width{1'bx}} : old_mem_data;
else
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
read_pulse_sec_last_value = read_pulse_sec;
end
end
// Simultaneous write to same/overlapping location by both ports
always @(dual_write)
begin
if (dual_write == 2'b11)
begin
for (i = 0; i < data_unit_width; i = i + 1)
mask_vector_common_int[i] = mask_vector_prime_int[col_sec + i] &
mask_vector_sec_int[i];
end
else if (dual_write == 2'b01) mem_unit_data = mem[row_sec];
else if (dual_write == 'b0)
begin
mem_data = mem[addr_prime_reg];
for (i = 0; i < data_unit_width; i = i + 1)
mem_data[col_sec + i] = mem_data[col_sec + i] ^ mask_vector_common_int[i];
mem[addr_prime_reg] = mem_data;
end
end
// Write stage 2 : Write actual data to memory
always @(negedge write_pulse_prime)
begin
if (clear_asserted_during_write[`PRIME] !== 1'b1)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0)
mem_data[i] = datain_prime_reg[i];
mem[addr_prime_reg] = mem_data;
end
dual_write[`PRIME] = 1'b0;
end
always @(negedge write_pulse_sec)
begin
if (clear_asserted_during_write[`SEC] !== 1'b1)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0)
mem_unit_data[col_sec + i] = datain_sec_reg[i];
mem[row_sec] = mem_unit_data;
end
dual_write[`SEC] = 1'b0;
end
always @(negedge read_pulse_prime) read_pulse_prime_last_value = 1'b0;
always @(negedge read_pulse_sec) read_pulse_sec_last_value = 1'b0;
always @(negedge rw_pulse_prime) rw_pulse_prime_last_value = 1'b0;
always @(negedge rw_pulse_sec) rw_pulse_sec_last_value = 1'b0;
// Read stage 2 : Send data to output
always @(negedge read_pulse_prime)
begin
if (primary_port_is_a)
dataout_a = read_data_latch;
else
dataout_b = read_data_latch;
end
always @(negedge read_pulse_sec)
begin
if (primary_port_is_b)
dataout_a = read_unit_data_latch;
else
dataout_b = read_unit_data_latch;
end
// Read during Write stage 2 : Send data to output
always @(negedge rw_pulse_prime)
begin
if (primary_port_is_a)
begin
// BE mask write
if (be_mask_write_a)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] === 1'bx) // disabled byte
dataout_a[i] = read_data_latch[i];
end
else
dataout_a = read_data_latch;
end
else
begin
// BE mask write
if (be_mask_write_b)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] === 1'bx) // disabled byte
dataout_b[i] = read_data_latch[i];
end
else
dataout_b = read_data_latch;
end
end
always @(negedge rw_pulse_sec)
begin
if (primary_port_is_b)
begin
// BE mask write
if (be_mask_write_a)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] === 1'bx) // disabled byte
dataout_a[i] = read_unit_data_latch[i];
end
else
dataout_a = read_unit_data_latch;
end
else
begin
// BE mask write
if (be_mask_write_b)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] === 1'bx) // disabled byte
dataout_b[i] = read_unit_data_latch[i];
end
else
dataout_b = read_unit_data_latch;
end
end
// Same port feed through
cycloneive_ram_pulse_generator ftpgen_a (
.clk(clk_a_in),
.ena(active_a_core & ~mode_is_dp & ~old_data_write_a & we_a_reg & re_a_reg & ~dataout_a_clr),
.pulse(read_pulse_a_feedthru),.cycle()
);
cycloneive_ram_pulse_generator ftpgen_b (
.clk(clk_b_in),
.ena(active_b_core & mode_is_bdp & ~old_data_write_b & we_b_reg & re_b_reg & ~dataout_b_clr),
.pulse(read_pulse_b_feedthru),.cycle()
);
always @(negedge read_pulse_prime_feedthru)
begin
if (primary_port_is_a)
begin
if (be_mask_write_a)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0) // enabled byte
dataout_a[i] = datain_prime_reg[i];
end
else
dataout_a = datain_prime_reg ^ mask_vector_prime;
end
else
begin
if (be_mask_write_b)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0) // enabled byte
dataout_b[i] = datain_prime_reg[i];
end
else
dataout_b = datain_prime_reg ^ mask_vector_prime;
end
end
always @(negedge read_pulse_sec_feedthru)
begin
if (primary_port_is_b)
begin
if (be_mask_write_a)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0) // enabled byte
dataout_a[i] = datain_sec_reg[i];
end
else
dataout_a = datain_sec_reg ^ mask_vector_sec;
end
else
begin
if (be_mask_write_b)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0) // enabled byte
dataout_b[i] = datain_sec_reg[i];
end
else
dataout_b = datain_sec_reg ^ mask_vector_sec;
end
end
// Input register clears
always @(posedge addr_a_clr or posedge datain_a_clr or posedge we_a_clr)
clear_asserted_during_write_a = write_pulse_a;
assign active_write_clear_a = active_write_a & write_cycle_a;
always @(posedge addr_a_clr)
begin
if (active_write_clear_a & we_a_reg)
mem_invalidate = 1'b1;
else if (active_a_core & re_a_reg & ~dataout_a_clr & ~dataout_a_clr_reg_latch)
begin
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_a = 'bx;
end
end
always @(posedge datain_a_clr or posedge we_a_clr)
begin
if (active_write_clear_a & we_a_reg)
begin
if (primary_port_is_a)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 1'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign active_write_clear_b = active_write_b & write_cycle_b;
always @(posedge addr_b_clr or posedge datain_b_clr or
posedge we_b_clr)
clear_asserted_during_write_b = write_pulse_b;
always @(posedge addr_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & we_b_reg)
mem_invalidate = 1'b1;
else if ((mode_is_dp | mode_is_bdp) & active_b_core & re_b_reg & ~dataout_b_clr & ~dataout_b_clr_reg_latch)
begin
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_b = 'bx;
end
end
always @(posedge datain_b_clr or posedge we_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & we_b_reg)
begin
if (primary_port_is_b)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign clear_asserted_during_write[primary_port_is_a] = clear_asserted_during_write_a;
assign clear_asserted_during_write[primary_port_is_b] = clear_asserted_during_write_b;
always @(posedge mem_invalidate)
begin
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'bx;
mem_invalidate = 1'b0;
end
// ------- Aclr mux registers (Latch Clear) --------
// port A
cycloneive_ram_register aclr__a__mux_register (
.d(dataout_a_clr),
.clk(clk_a_core),
.aclr(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(1'b1),
.q(dataout_a_clr_reg_latch),.aclrout()
);
// port B
cycloneive_ram_register aclr__b__mux_register (
.d(dataout_b_clr),
.clk(clk_b_core),
.aclr(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(1'b1),
.q(dataout_b_clr_reg_latch),.aclrout()
);
// ------- Output registers --------
assign clkena_a_out = (port_a_data_out_clock == "clock0") ?
((clk0_output_clock_enable == "none") ? 1'b1 : ena0_int) :
((clk1_output_clock_enable == "none") ? 1'b1 : ena1_int) ;
cycloneive_ram_register dataout_a_register (
.d(dataout_a),
.clk(clk_a_out),
.aclr(dataout_a_clr_reg),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(clkena_a_out),
.q(dataout_a_reg),.aclrout()
);
defparam dataout_a_register.width = port_a_data_width;
assign portadataout = (out_a_is_reg) ? dataout_a_reg : dataout_a;
assign clkena_b_out = (port_b_data_out_clock == "clock0") ?
((clk0_output_clock_enable == "none") ? 1'b1 : ena0_int) :
((clk1_output_clock_enable == "none") ? 1'b1 : ena1_int) ;
cycloneive_ram_register dataout_b_register (
.d( dataout_b ),
.clk(clk_b_out),
.aclr(dataout_b_clr_reg),
.devclrn(devclrn),.devpor(devpor),
.stall(1'b0),
.ena(clkena_b_out),
.q(dataout_b_reg),.aclrout()
);
defparam dataout_b_register.width = port_b_data_width;
assign portbdataout = (out_b_is_reg) ? dataout_b_reg : dataout_b;
endmodule // cycloneive_ram_block
//---------------------------------------------------------------------
//
// Module Name : cycloneive_mac_data_reg
//
// Description : Simulation model for the data input register of
// Cyclone II MAC_MULT
//
//---------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneive_mac_data_reg (clk,
data,
ena,
aclr,
dataout
);
parameter data_width = 18;
// INPUT PORTS
input clk;
input [17 : 0] data;
input ena;
input aclr;
// OUTPUT PORTS
output [17:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [17:0] dataout_tmp;
wire [17:0] dataout_wire;
// INTERNAL VARIABLES
wire [17:0] data_ipd;
wire enable;
wire no_clr;
reg d_viol;
reg ena_viol;
wire clk_ipd;
wire ena_ipd;
wire aclr_ipd;
// BUFFER INPUTS
buf (clk_ipd, clk);
buf (ena_ipd, ena);
buf (aclr_ipd, aclr);
buf (data_ipd[0], data[0]);
buf (data_ipd[1], data[1]);
buf (data_ipd[2], data[2]);
buf (data_ipd[3], data[3]);
buf (data_ipd[4], data[4]);
buf (data_ipd[5], data[5]);
buf (data_ipd[6], data[6]);
buf (data_ipd[7], data[7]);
buf (data_ipd[8], data[8]);
buf (data_ipd[9], data[9]);
buf (data_ipd[10], data[10]);
buf (data_ipd[11], data[11]);
buf (data_ipd[12], data[12]);
buf (data_ipd[13], data[13]);
buf (data_ipd[14], data[14]);
buf (data_ipd[15], data[15]);
buf (data_ipd[16], data[16]);
buf (data_ipd[17], data[17]);
assign enable = (!aclr_ipd) && (ena_ipd);
assign no_clr = (!aclr_ipd);
// TIMING PATHS
specify
$setuphold (posedge clk &&& enable, data, 0, 0, d_viol);
$setuphold (posedge clk &&& no_clr, ena, 0, 0, ena_viol);
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
(posedge aclr => (dataout +: 1'b0)) = (0, 0);
endspecify
initial
begin
clk_last_value <= 'b0;
dataout_tmp <= 18'b0;
end
always @(clk_ipd or aclr_ipd)
begin
if (d_viol == 1'b1 || ena_viol == 1'b1)
begin
dataout_tmp <= 'bX;
end
else if (aclr_ipd == 1'b1)
begin
dataout_tmp <= 'b0;
end
else
begin
if ((clk_ipd === 1'b1) && (clk_last_value == 1'b0))
if (ena_ipd === 1'b1)
dataout_tmp <= data_ipd;
end
clk_last_value <= clk_ipd;
end // always
assign dataout_wire = dataout_tmp;
and (dataout[0], dataout_wire[0], 1'b1);
and (dataout[1], dataout_wire[1], 1'b1);
and (dataout[2], dataout_wire[2], 1'b1);
and (dataout[3], dataout_wire[3], 1'b1);
and (dataout[4], dataout_wire[4], 1'b1);
and (dataout[5], dataout_wire[5], 1'b1);
and (dataout[6], dataout_wire[6], 1'b1);
and (dataout[7], dataout_wire[7], 1'b1);
and (dataout[8], dataout_wire[8], 1'b1);
and (dataout[9], dataout_wire[9], 1'b1);
and (dataout[10], dataout_wire[10], 1'b1);
and (dataout[11], dataout_wire[11], 1'b1);
and (dataout[12], dataout_wire[12], 1'b1);
and (dataout[13], dataout_wire[13], 1'b1);
and (dataout[14], dataout_wire[14], 1'b1);
and (dataout[15], dataout_wire[15], 1'b1);
and (dataout[16], dataout_wire[16], 1'b1);
and (dataout[17], dataout_wire[17], 1'b1);
endmodule //cycloneive_mac_data_reg
//------------------------------------------------------------------
//
// Module Name : cycloneive_mac_sign_reg
//
// Description : Simulation model for the sign input register of
// Cyclone II MAC_MULT
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cycloneive_mac_sign_reg (
clk,
d,
ena,
aclr,
q
);
// INPUT PORTS
input clk;
input d;
input ena;
input aclr;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg clk_last_value;
reg q_tmp;
reg ena_viol;
reg d_viol;
wire enable;
// DEFAULT VALUES THRO' PULLUPs
tri1 aclr, ena;
wire d_ipd;
wire clk_ipd;
wire ena_ipd;
wire aclr_ipd;
buf (d_ipd, d);
buf (clk_ipd, clk);
buf (ena_ipd, ena);
buf (aclr_ipd, aclr);
assign enable = (!aclr_ipd) && (ena_ipd);
specify
$setuphold (posedge clk &&& enable, d, 0, 0, d_viol) ;
$setuphold (posedge clk &&& enable, ena, 0, 0, ena_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
(posedge aclr => (q +: 1'b0)) = 0 ;
endspecify
initial
begin
clk_last_value <= 'b0;
q_tmp <= 'b0;
end
always @ (clk_ipd or aclr_ipd)
begin
if (d_viol == 1'b1 || ena_viol == 1'b1)
begin
q_tmp <= 'bX;
end
else
begin
if (aclr_ipd == 1'b1)
q_tmp <= 0;
else if ((clk_ipd == 1'b1) && (clk_last_value == 1'b0))
if (ena_ipd == 1'b1)
q_tmp <= d_ipd;
end
clk_last_value <= clk_ipd;
end
and (q, q_tmp, 'b1);
endmodule // cycloneive_mac_sign_reg
//------------------------------------------------------------------
//
// Module Name : cycloneive_mac_mult_internal
//
// Description : Cyclone II MAC_MULT_INTERNAL Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneive_mac_mult_internal
(
dataa,
datab,
signa,
signb,
dataout
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = dataa_width + datab_width;
// INPUT
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
// OUTPUT
output [dataout_width-1:0] dataout;
// Internal variables
wire [17:0] dataa_ipd;
wire [17:0] datab_ipd;
wire signa_ipd;
wire signb_ipd;
wire [dataout_width-1:0] dataout_tmp;
wire ia_is_positive;
wire ib_is_positive;
wire [17:0] iabsa; // absolute value (i.e. positive) form of dataa input
wire [17:0] iabsb; // absolute value (i.e. positive) form of datab input
wire [35:0] iabsresult; // absolute value (i.e. positive) form of product (a * b)
reg [17:0] i_ones; // padding with 1's for input negation
// Input buffers
buf (signa_ipd, signa);
buf (signb_ipd, signb);
buf dataa_buf [dataa_width-1:0] (dataa_ipd[dataa_width-1:0], dataa);
buf datab_buf [datab_width-1:0] (datab_ipd[datab_width-1:0], datab);
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(signa *> dataout) = (0, 0);
(signb *> dataout) = (0, 0);
endspecify
initial
begin
// 1's padding for 18-bit wide inputs
i_ones = ~0;
end
// get signs of a and b, and get absolute values since Verilog '*' operator
// is an unsigned multiplication
assign ia_is_positive = ~signa_ipd | ~dataa_ipd[dataa_width-1];
assign ib_is_positive = ~signb_ipd | ~datab_ipd[datab_width-1];
assign iabsa = ia_is_positive == 1 ? dataa_ipd[dataa_width-1:0] : -(dataa_ipd | (i_ones << dataa_width));
assign iabsb = ib_is_positive == 1 ? datab_ipd[datab_width-1:0] : -(datab_ipd | (i_ones << datab_width));
// multiply a * b
assign iabsresult = iabsa * iabsb;
assign dataout_tmp = (ia_is_positive ^ ib_is_positive) == 1 ? -iabsresult : iabsresult;
buf dataout_buf [dataout_width-1:0] (dataout, dataout_tmp);
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneive_mac_mult
//
// Description : Cyclone II MAC_MULT Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneive_mac_mult
(
dataa,
datab,
signa,
signb,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataa_clock = "none";
parameter datab_clock = "none";
parameter signa_clock = "none";
parameter signb_clock = "none";
parameter lpm_hint = "true";
parameter lpm_type = "cycloneive_mac_mult";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = dataa_width + datab_width;
// SIMULATION_ONLY_PARAMETERS_END
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
input clk;
input aclr;
input ena;
input devclrn;
input devpor;
output [dataout_width-1:0] dataout;
tri1 devclrn;
tri1 devpor;
wire [dataout_width-1:0] dataout_tmp;
wire [17:0] idataa_reg; // optional register for dataa input
wire [17:0] idatab_reg; // optional register for datab input
wire [17:0] dataa_pad; // padded dataa input
wire [17:0] datab_pad; // padded datab input
wire isigna_reg; // optional register for signa input
wire isignb_reg; // optional register for signb input
wire [17:0] idataa_int; // dataa as seen by the multiplier input
wire [17:0] idatab_int; // datab as seen by the multiplier input
wire isigna_int; // signa as seen by the multiplier input
wire isignb_int; // signb as seen by the multiplier input
wire ia_is_positive;
wire ib_is_positive;
wire [17:0] iabsa; // absolute value (i.e. positive) form of dataa input
wire [17:0] iabsb; // absolute value (i.e. positive) form of datab input
wire [35:0] iabsresult; // absolute value (i.e. positive) form of product (a * b)
wire dataa_use_reg; // equivalent to dataa_clock parameter
wire datab_use_reg; // equivalent to datab_clock parameter
wire signa_use_reg; // equivalent to signa_clock parameter
wire signb_use_reg; // equivalent to signb_clock parameter
reg [17:0] i_ones; // padding with 1's for input negation
wire reg_aclr;
assign reg_aclr = (!devpor) || (!devclrn) || (aclr);
// optional registering parameters
assign dataa_use_reg = (dataa_clock != "none") ? 1'b1 : 1'b0;
assign datab_use_reg = (datab_clock != "none") ? 1'b1 : 1'b0;
assign signa_use_reg = (signa_clock != "none") ? 1'b1 : 1'b0;
assign signb_use_reg = (signb_clock != "none") ? 1'b1 : 1'b0;
assign dataa_pad = ((18-dataa_width) == 0) ? dataa : {{(18-dataa_width){1'b0}},dataa};
assign datab_pad = ((18-datab_width) == 0) ? datab : {{(18-datab_width){1'b0}},datab};
initial
begin
// 1's padding for 18-bit wide inputs
i_ones = ~0;
end
// Optional input registers for dataa,b and signa,b
cycloneive_mac_data_reg dataa_reg (
.clk(clk),
.data(dataa_pad),
.ena(ena),
.aclr(reg_aclr),
.dataout(idataa_reg)
);
defparam dataa_reg.data_width = dataa_width;
cycloneive_mac_data_reg datab_reg (
.clk(clk),
.data(datab_pad),
.ena(ena),
.aclr(reg_aclr),
.dataout(idatab_reg)
);
defparam datab_reg.data_width = datab_width;
cycloneive_mac_sign_reg signa_reg (
.clk(clk),
.d(signa),
.ena(ena),
.aclr(reg_aclr),
.q(isigna_reg)
);
cycloneive_mac_sign_reg signb_reg (
.clk(clk),
.d(signb),
.ena(ena),
.aclr(reg_aclr),
.q(isignb_reg)
);
// mux input sources from direct inputs or optional registers
assign idataa_int = dataa_use_reg == 1'b1 ? idataa_reg : dataa;
assign idatab_int = datab_use_reg == 1'b1 ? idatab_reg : datab;
assign isigna_int = signa_use_reg == 1'b1 ? isigna_reg : signa;
assign isignb_int = signb_use_reg == 1'b1 ? isignb_reg : signb;
cycloneive_mac_mult_internal mac_multiply (
.dataa(idataa_int[dataa_width-1:0]),
.datab(idatab_int[datab_width-1:0]),
.signa(isigna_int),
.signb(isignb_int),
.dataout(dataout)
);
defparam mac_multiply.dataa_width = dataa_width;
defparam mac_multiply.datab_width = datab_width;
defparam mac_multiply.dataout_width = dataout_width;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneive_mac_out
//
// Description : Cyclone II MAC_OUT Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneive_mac_out
(
dataa,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
parameter dataa_width = 1;
parameter output_clock = "none";
parameter lpm_hint = "true";
parameter lpm_type = "cycloneive_mac_out";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = dataa_width;
// SIMULATION_ONLY_PARAMETERS_END
input [dataa_width-1:0] dataa;
input clk;
input aclr;
input ena;
input devclrn;
input devpor;
output [dataout_width-1:0] dataout;
tri1 devclrn;
tri1 devpor;
wire [dataa_width-1:0] dataa_ipd; // internal dataa
wire clk_ipd; // internal clk
wire aclr_ipd; // internal aclr
wire ena_ipd; // internal ena
// internal variable
wire [dataout_width-1:0] dataout_tmp;
reg [dataa_width-1:0] idataout_reg; // optional register for dataout output
wire use_reg; // equivalent to dataout_clock parameter
wire enable;
wire no_aclr;
// Input buffers
buf (clk_ipd, clk);
buf (aclr_ipd, aclr);
buf (ena_ipd, ena);
buf dataa_buf [dataa_width-1:0] (dataa_ipd, dataa);
// optional registering parameter
assign use_reg = (output_clock != "none") ? 1 : 0;
assign enable = (!aclr) && (ena) && use_reg;
assign no_aclr = (!aclr) && use_reg;
specify
if (use_reg)
(posedge clk => (dataout +: dataout_tmp)) = 0;
(posedge aclr => (dataout +: 1'b0)) = 0;
ifnone
(dataa *> dataout) = (0, 0);
$setuphold (posedge clk &&& enable, dataa, 0, 0);
$setuphold (posedge clk &&& no_aclr, ena, 0, 0);
endspecify
initial
begin
// initial values for optional register
idataout_reg = 0;
end
// Optional input registers for dataa,b and signa,b
always @ (posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (devclrn == 0 || devpor == 0 || aclr_ipd == 1)
begin
idataout_reg <= 0;
end
else if (ena_ipd == 1)
begin
idataout_reg <= dataa_ipd;
end
end
// mux input sources from direct inputs or optional registers
assign dataout_tmp = use_reg == 1 ? idataout_reg : dataa_ipd;
// accelerate outputs
buf dataout_buf [dataout_width-1:0] (dataout, dataout_tmp);
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: cycloneive_io_ibuf //
//Description: Simulation model for Cycloneive IO Input Buffer //
// //
//////////////////////////////////////////////////////////////////////////////////
module cycloneive_io_ibuf (
i,
ibar,
o
);
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter differential_mode = "false";
parameter bus_hold = "false";
parameter simulate_z_as = "Z";
parameter lpm_type = "cycloneive_io_ibuf";
// SIMULATION_ONLY_PARAMETERS_END
//Input Ports Declaration
input i;
input ibar;
//Output Ports Declaration
output o;
// Internal signals
reg out_tmp;
reg o_tmp;
wire out_val ;
reg prev_value;
specify
(i => o) = (0, 0);
(ibar => o) = (0, 0);
endspecify
initial
begin
prev_value = 1'b0;
end
always@(i or ibar)
begin
if(differential_mode == "false")
begin
if(i == 1'b1)
begin
o_tmp = 1'b1;
prev_value = 1'b1;
end
else if(i == 1'b0)
begin
o_tmp = 1'b0;
prev_value = 1'b0;
end
else if( i === 1'bz)
o_tmp = out_val;
else
o_tmp = i;
if( bus_hold == "true")
out_tmp = prev_value;
else
out_tmp = o_tmp;
end
else
begin
case({i,ibar})
2'b00: out_tmp = 1'bX;
2'b01: out_tmp = 1'b0;
2'b10: out_tmp = 1'b1;
2'b11: out_tmp = 1'bX;
default: out_tmp = 1'bX;
endcase
end
end
assign out_val = (simulate_z_as == "Z") ? 1'bz :
(simulate_z_as == "X") ? 1'bx :
(simulate_z_as == "vcc")? 1'b1 :
(simulate_z_as == "gnd") ? 1'b0 : 1'bz;
pmos (o, out_tmp, 1'b0);
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: cycloneive_io_obuf //
//Description: Simulation model for Cycloneive IO Output Buffer //
// //
//////////////////////////////////////////////////////////////////////////////////
module cycloneive_io_obuf (
i,
oe,
seriesterminationcontrol,
devoe,
o,
obar
);
//Parameter Declaration
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter lpm_type = "cycloneive_io_obuf";
//Input Ports Declaration
input i;
input oe;
input devoe;
input [15:0] seriesterminationcontrol;
//Outout Ports Declaration
output o;
output obar;
//INTERNAL Signals
reg out_tmp;
reg out_tmp_bar;
reg prev_value;
wire tmp;
wire tmp_bar;
wire tmp1;
wire tmp1_bar;
tri1 devoe;
specify
(i => o) = (0, 0);
(i => obar) = (0, 0);
(oe => o) = (0, 0);
(oe => obar) = (0, 0);
endspecify
initial
begin
prev_value = 'b0;
out_tmp = 'bz;
end
always@(i or oe)
begin
if(oe == 1'b1)
begin
if(open_drain_output == "true")
begin
if(i == 'b0)
begin
out_tmp = 'b0;
out_tmp_bar = 'b1;
prev_value = 'b0;
end
else
begin
out_tmp = 'bz;
out_tmp_bar = 'bz;
end
end
else
begin
if( i == 'b0)
begin
out_tmp = 'b0;
out_tmp_bar = 'b1;
prev_value = 'b0;
end
else if( i == 'b1)
begin
out_tmp = 'b1;
out_tmp_bar = 'b0;
prev_value = 'b1;
end
else
begin
out_tmp = i;
out_tmp_bar = i;
end
end
end
else if(oe == 1'b0)
begin
out_tmp = 'bz;
out_tmp_bar = 'bz;
end
else
begin
out_tmp = 'bx;
out_tmp_bar = 'bx;
end
end
assign tmp = (bus_hold == "true") ? prev_value : out_tmp;
assign tmp_bar = (bus_hold == "true") ? !prev_value : out_tmp_bar;
assign tmp1 = (devoe == 1'b1) ? tmp : 1'bz;
assign tmp1_bar = (devoe == 1'b1) ? tmp_bar : 1'bz;
pmos (o, tmp1, 1'b0);
pmos (obar, tmp1_bar, 1'b0);
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: cycloneive_ddio_out //
//Description: Simulation model for Cycloneive DDIO Output //
// //
//////////////////////////////////////////////////////////////////////////////////
module cycloneive_ddio_out (
datainlo,
datainhi,
clk,
clkhi,
clklo,
muxsel,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter use_new_clocking_model = "false";
parameter lpm_type = "cycloneive_ddio_out";
//Input Ports Declaration
input datainlo;
input datainhi;
input clk;
input clkhi;
input clklo;
input muxsel;
input ena;
input areset;
input sreset;
input devpor;
input devclrn;
//Output Ports Declaration
output dataout;
//Buried Ports Declaration
output dfflo;
output dffhi ;
tri1 devclrn;
tri1 devpor;
//Internal Signals
reg ddioreg_aclr;
reg ddioreg_adatasdata;
reg ddioreg_sclr;
reg ddioreg_sload;
reg ddioreg_prn;
reg viol_notifier;
wire dfflo_tmp;
wire dffhi_tmp;
wire mux_sel;
wire sel_mux_hi_in;
wire clk_hi;
wire clk_lo;
wire datainlo_tmp;
wire datainhi_tmp;
reg dinhi_tmp;
reg dinlo_tmp;
reg clk1;
reg clk2;
reg muxsel1;
reg muxsel2;
reg muxsel_tmp;
reg sel_mux_lo_in_tmp;
reg sel_mux_hi_in_tmp;
reg dffhi_tmp1;
wire muxsel3;
wire clk3;
wire sel_mux_lo_in;
initial
begin
ddioreg_aclr = 1'b1;
ddioreg_prn = 1'b1;
ddioreg_adatasdata = (sync_mode == "preset") ? 1'b1: 1'b0;
ddioreg_sclr = 1'b0;
ddioreg_sload = 1'b0;
end
assign dfflo = dfflo_tmp;
assign dffhi = dffhi_tmp;
always@(clk)
begin
clk1 = clk;
clk2 <= clk1;
end
always@(muxsel)
begin
muxsel1 = muxsel;
muxsel2 <= muxsel1;
end
always@(dfflo_tmp)
begin
sel_mux_lo_in_tmp <= dfflo_tmp;
end
always@(datainlo)
begin
dinlo_tmp <= datainlo;
end
always@(datainhi)
begin
dinhi_tmp <= datainhi;
end
always @(mux_sel) begin
muxsel_tmp <= mux_sel; //REM_SV
end
always@(dffhi_tmp)
begin
dffhi_tmp1 <= dffhi_tmp;
end
always@(dffhi_tmp1)
begin
sel_mux_hi_in_tmp <= dffhi_tmp1;
end
always@(areset)
begin
if(async_mode == "clear")
begin
ddioreg_aclr = !areset;
end
else if(async_mode == "preset")
begin
ddioreg_prn = !areset;
end
end
always@(sreset )
begin
if(sync_mode == "clear")
begin
ddioreg_sclr = sreset;
end
else if(sync_mode == "preset")
begin
ddioreg_sload = sreset;
end
end
//DDIO HIGH Register
cycloneive_latch ddioreg_hi(
.D(datainhi_tmp),
.ENA(!clk_hi & ena),
.PRE(ddioreg_prn),
.CLR(ddioreg_aclr),
.Q(dffhi_tmp)
);
assign clk_hi = (use_new_clocking_model == "true") ? clkhi : clk;
assign datainhi_tmp = (ddioreg_sclr == 1'b0 && ddioreg_sload == 1'b1)? 1'b1 : (ddioreg_sclr == 1'b1 && ddioreg_sload == 1'b0)? 1'b0: dinhi_tmp;
//DDIO Low Register
dffeas ddioreg_lo(
.d(datainlo_tmp),
.clk(clk_lo),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dfflo_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo.power_up = power_up;
assign clk_lo = (use_new_clocking_model == "true") ? clklo : clk;
assign datainlo_tmp = dinlo_tmp;
//DDIO High Register
//registered output selection
cycloneive_mux21 sel_mux(
.MO(dataout),
.A(sel_mux_hi_in),
.B(sel_mux_lo_in),
.S(!muxsel_tmp)
);
assign muxsel3 = muxsel2;
assign clk3 = clk2;
assign mux_sel = (use_new_clocking_model == "true")? muxsel3 : clk3;
assign sel_mux_lo_in = sel_mux_lo_in_tmp;
assign sel_mux_hi_in = sel_mux_hi_in_tmp;
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: cycloneive_ddio_oe //
//Description: Simulation model for Cycloneive DDIO OE //
// //
//////////////////////////////////////////////////////////////////////////////////
module cycloneive_ddio_oe (
oe,
clk,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter lpm_type = "cycloneive_ddio_oe";
//Input Ports Declaration
input oe;
input clk;
input ena;
input areset;
input sreset;
input devpor;
input devclrn;
//Output Ports Declaration
output dataout;
//Buried Ports Declaration
output dfflo;
output dffhi;
tri1 devclrn;
tri1 devpor;
//Internal Signals
reg ddioreg_aclr;
reg ddioreg_prn;
reg ddioreg_adatasdata;
reg ddioreg_sclr;
reg ddioreg_sload;
reg viol_notifier;
initial
begin
ddioreg_aclr = 1'b1;
ddioreg_prn = 1'b1;
ddioreg_adatasdata = 1'b0;
ddioreg_sclr = 1'b0;
ddioreg_sload = 1'b0;
end
wire dfflo_tmp;
wire dffhi_tmp;
always@(areset or sreset )
begin
if(async_mode == "clear")
begin
ddioreg_aclr = !areset;
ddioreg_prn = 1'b1;
end
else if(async_mode == "preset")
begin
ddioreg_aclr = 'b1;
ddioreg_prn = !areset;
end
else
begin
ddioreg_aclr = 'b1;
ddioreg_prn = 'b1;
end
if(sync_mode == "clear")
begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = sreset;
ddioreg_sload = 'b0;
end
else if(sync_mode == "preset")
begin
ddioreg_adatasdata = 'b1;
ddioreg_sclr = 'b0;
ddioreg_sload = sreset;
end
else
begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = 'b0;
ddioreg_sload = 'b0;
end
end
//DDIO OE Register
dffeas ddioreg_hi(
.d(oe),
.clk(clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dffhi_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_hi.power_up = power_up;
//DDIO Low Register
dffeas ddioreg_lo(
.d(dffhi_tmp),
.clk(!clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dfflo_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo.power_up = power_up;
//registered output
cycloneive_mux21 or_gate(
.MO(dataout),
.A(dffhi_tmp),
.B(dfflo_tmp),
.S(dfflo_tmp)
);
assign dfflo = dfflo_tmp;
assign dffhi = dffhi_tmp;
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: cycloneive_pseudo_diff_out //
//Description: Simulation model for Cycloneive Pseudo Differential //
// Output Buffer //
//////////////////////////////////////////////////////////////////////////////////
module cycloneive_pseudo_diff_out(
i,
o,
obar
);
parameter lpm_type = "cycloneive_pseudo_diff_out";
input i;
output o;
output obar;
reg o_tmp;
reg obar_tmp;
assign o = o_tmp;
assign obar = obar_tmp;
always@(i)
begin
if( i == 1'b1)
begin
o_tmp = 1'b1;
obar_tmp = 1'b0;
end
else if( i == 1'b0)
begin
o_tmp = 1'b0;
obar_tmp = 1'b1;
end
else
begin
o_tmp = i;
obar_tmp = i;
end
end
endmodule
//--------------------------------------------------------------------------
// Module Name : cycloneive_io_pad
// Description : Simulation model for cycloneive IO pad
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneive_io_pad (
padin,
padout
);
parameter lpm_type = "cycloneive_io_pad";
//INPUT PORTS
input padin; //Input Pad
//OUTPUT PORTS
output padout;//Output Pad
//INTERNAL SIGNALS
wire padin_ipd;
wire padout_opd;
//INPUT BUFFER INSERTION FOR VERILOG-XL
buf padin_buf (padin_ipd,padin);
assign padout_opd = padin_ipd;
//OUTPUT BUFFER INSERTION FOR VERILOG-XL
buf padout_buf (padout, padout_opd);
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneive_ena_reg
//
// Description : Simulation model for a simple DFF.
// This is used for the gated clock generation.
// Powers upto 1.
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cycloneive_ena_reg (
clk,
ena,
d,
clrn,
prn,
q
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q_tmp;
reg violation;
reg d_viol;
reg clk_last_value;
wire reset;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
wire d_in;
wire clk_in;
buf (d_in, d);
buf (clk_in, clk);
assign reset = (!clrn) && (ena);
specify
$setuphold (posedge clk &&& reset, d, 0, 0, d_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
endspecify
initial
begin
q_tmp = 'b1;
violation = 'b0;
clk_last_value = clk_in;
end
always @ (clk_in or negedge clrn or negedge prn )
begin
if (d_viol == 1'b1)
begin
violation = 1'b0;
q_tmp <= 'bX;
end
else
if (prn == 1'b0)
q_tmp <= 1;
else if (clrn == 1'b0)
q_tmp <= 0;
else if ((clk_last_value === 'b0) & (clk_in === 1'b1) & (ena == 1'b1))
q_tmp <= d_in;
clk_last_value = clk_in;
end
and (q, q_tmp, 'b1);
endmodule // cycloneive_ena_reg
//------------------------------------------------------------------
//
// Module Name : cycloneive_clkctrl
//
// Description : Cycloneiii CLKCTRL Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneive_clkctrl (
inclk,
clkselect,
ena,
devpor,
devclrn,
outclk
);
input [3:0] inclk;
input [1:0] clkselect;
input ena;
input devpor;
input devclrn;
output outclk;
tri1 devclrn;
tri1 devpor;
parameter clock_type = "auto";
parameter ena_register_mode = "falling edge";
parameter lpm_type = "cycloneive_clkctrl";
wire clkmux_out; // output of CLK mux
wire cereg1_out; // output of ENA register1
wire cereg2_out; // output of ENA register2
wire ena_out; // choice of registered ENA or none.
wire inclk3_ipd;
wire inclk2_ipd;
wire inclk1_ipd;
wire inclk0_ipd;
wire clkselect1_ipd;
wire clkselect0_ipd;
wire ena_ipd;
buf (inclk3_ipd, inclk[3]);
buf (inclk2_ipd, inclk[2]);
buf (inclk1_ipd, inclk[1]);
buf (inclk0_ipd, inclk[0]);
buf (clkselect1_ipd, clkselect[1]);
buf (clkselect0_ipd, clkselect[0]);
buf (ena_ipd, ena);
specify
(inclk *> outclk) = (0, 0) ;
endspecify
cycloneive_mux41 clk_mux (.MO(clkmux_out),
.IN0(inclk0_ipd),
.IN1(inclk1_ipd),
.IN2(inclk2_ipd),
.IN3(inclk3_ipd),
.S({clkselect1_ipd, clkselect0_ipd}));
cycloneive_ena_reg extena0_reg(
.clk(!clkmux_out),
.ena(1'b1),
.d(ena_ipd),
.clrn(1'b1),
.prn(devpor),
.q(cereg1_out)
);
cycloneive_ena_reg extena1_reg(
.clk(!clkmux_out),
.ena(1'b1),
.d(cereg1_out),
.clrn(1'b1),
.prn(devpor),
.q(cereg2_out)
);
assign ena_out = (ena_register_mode == "falling edge") ? cereg1_out :
((ena_register_mode == "none") ? ena_ipd : cereg2_out);
and (outclk, ena_out, clkmux_out);
endmodule
///////////////////////////////////////////////////////////////////////
//
// CYCLONEIVE RUBLOCK ATOM
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cycloneive_rublock
(
clk,
shiftnld,
captnupdt,
regin,
rsttimer,
rconfig,
regout
);
parameter sim_init_config = "factory";
parameter sim_init_watchdog_value = 0;
parameter sim_init_status = 0;
parameter lpm_type = "cycloneive_rublock";
input clk;
input shiftnld;
input captnupdt;
input regin;
input rsttimer;
input rconfig;
output regout;
endmodule
///////////////////////////////////////////////////////////////////////
//
// CYCLONEIVE_APFCONTROLLER ATOM
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cycloneive_apfcontroller
(
usermode,
nceout
);
parameter lpm_type = "cycloneive_apfcontroller";
output usermode;
output nceout;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneive_termination_ctrl_sub
//
// Description : Cycloneive Termination Ctrl Sub-block
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneive_termination_ctrl (
clkusr,
intosc,
nclrusr,
nfrzdrv,
rclkdiv,
rclrusrinv,
rdivsel,
roctusr,
rsellvrefdn,
rsellvrefup,
rtest,
vccnx,
vssn,
clken,
clkin,
maskbit,
nclr,
noctdoneuser,
octdone,
oregclk,
oregnclr,
vref,
vrefh,
vrefl);
input clkusr;
input intosc; // clk source in powerup mode
input nclrusr;
input nfrzdrv; // devclrn
input rclkdiv; // - 14
input rclrusrinv; // invert nclrusr signal - 13
input rdivsel; // 0 = /32; 1 = /4; - 16
input roctusr; // run_time_control - 15
input rsellvrefdn; // shift_vref_rdn - 26
input rsellvrefup; // shift_vref_rup - 25
input rtest; // test_mode - 2
input vccnx; // VCC voltage src
input vssn; // GND voltage src
output clken;
output clkin;
output [8:0] maskbit;
output nclr;
output noctdoneuser;
output octdone;
output oregclk;
output oregnclr;
output vref;
output vrefh;
output vrefl;
parameter REG_TCO_DLY = 0; // 1;
reg divby2;
reg divby4;
reg divby8;
reg divby16;
reg divby32;
reg oregclk;
reg oregclkclk;
reg intosc_div4;
reg intosc_div32;
reg clken;
reg octdoneuser;
reg startbit;
reg [8:0] maskbit;
reg octdone;
wire [8:0] maskbit_d;
wire intoscin;
wire clk_sel;
wire intosc_clk;
wire clkin;
wire oregnclr;
wire clr_invert;
wire nclr;
wire adcclk;
// data flow in user mode:
// oregnclr = 1 forever so clkin is clkusr
//
// deasserting nclrusr starts off USER calibration
// upon rising edge of nclrusr
// (1). at 1st neg edge of clkin, clken = 1
// (2). enable adcclk
// (3). Mask bits [8:0] shifts from MSB=1 into LSB=1
// (4). oregclkclk = bit[0] (=1); 7th cycle
// (5). oregclk = 1 (after falling edge of oregclkclk) 8th cycle
// (6). clken = 0 (!oregclk)
// (7). octdoneuser = 1 (falling edge of clken)
initial
begin
octdone = 1'b1; // from powerup stage
octdoneuser = 1'b0;
startbit = 1'b0;
maskbit = 9'b000000000;
oregclk = 1'b0;
oregclkclk = 1'b0;
clken = 1'b0;
divby2 = 1'b0;
divby4 = 1'b0;
divby8 = 1'b0;
divby16 = 1'b0;
divby32 = 1'b0;
intosc_div4 = 1'b0;
intosc_div32 = 1'b0;
end
assign noctdoneuser = ~octdoneuser;
// c7216 clkdiv
always @(posedge intosc or negedge nfrzdrv) begin
if (!nfrzdrv) divby2 <= #(REG_TCO_DLY) 1'b0;
else divby2 <= #(REG_TCO_DLY) ~divby2;
end
always @(posedge divby2 or negedge nfrzdrv) begin
if (!nfrzdrv) divby4 <= #(REG_TCO_DLY) 1'b0;
else divby4 <= #(REG_TCO_DLY) ~divby4;
end
always @(posedge divby4 or negedge nfrzdrv) begin
if (!nfrzdrv) divby8 <= #(REG_TCO_DLY) 1'b0;
else divby8 <= #(REG_TCO_DLY) ~divby8;
end
always @(posedge divby8 or negedge nfrzdrv) begin
if (!nfrzdrv) divby16 <= #(REG_TCO_DLY) 1'b0;
else divby16 <= #(REG_TCO_DLY) ~divby16;
end
always @(posedge divby16 or negedge nfrzdrv) begin
if (!nfrzdrv) divby32 <= #(REG_TCO_DLY) 1'b0;
else divby32 <= #(REG_TCO_DLY) ~divby32;
end
assign intoscin = rdivsel ? divby4 : divby32;
assign clk_sel = octdone & roctusr; // always 1
assign intosc_clk = rclkdiv ? intoscin : intosc;
assign clkin = clk_sel ? clkusr : intosc_clk;
assign oregnclr = rtest | nfrzdrv; // always 1
assign clr_invert = rclrusrinv ? ~nclrusr : nclrusr;
assign nclr = clk_sel ? clr_invert : nfrzdrv;
// c7206
always @(negedge clkin or negedge nclr) begin
if (!nclr) clken <= #(REG_TCO_DLY) 1'b0;
else clken <= #(REG_TCO_DLY) ~oregclk;
end
always @(negedge clken or negedge oregnclr) begin
if (!oregnclr) octdone <= #(REG_TCO_DLY) 1'b0;
else octdone <= #(REG_TCO_DLY) 1'b1;
end
assign adcclk = clkin & clken;
always @(posedge adcclk or negedge nclr) begin
if (!nclr)
startbit <= #(REG_TCO_DLY) 1'b0;
else
startbit <= #(REG_TCO_DLY) 1'b1;
end
assign maskbit_d = {~startbit, maskbit[8:1]};
always @(posedge adcclk or negedge nclr) begin
if (!nclr) begin
maskbit <= #(REG_TCO_DLY) 9'b0;
oregclkclk <= #(REG_TCO_DLY) 1'b0;
end
else begin
maskbit <= #(REG_TCO_DLY) maskbit_d;
oregclkclk <= #(REG_TCO_DLY) maskbit[0];
end
end
always @(negedge oregclkclk or negedge nclr) begin
if (~nclr) oregclk <= #(REG_TCO_DLY) 1'b0;
else oregclk <= #(REG_TCO_DLY) 1'b1;
end
always @(negedge clken or negedge nclr) begin
if (~nclr) octdoneuser <= #(REG_TCO_DLY) 1'b0;
else octdoneuser <= #(REG_TCO_DLY) 1'b1;
end
// OCT VREF c7207 xvref (
// Functional code
assign vrefh = 1'b1;
assign vref = 1'b1;
assign vrefl = 1'b0;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneive_termination_ctrl_sub
//
// Description : Cycloneive Termination Ctrl Sub-block
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneive_termination_rupdn (
clken,
clkin,
compout,
maskbit,
nclr,
octcal,
octpin,
octrpcd,
oregclk,
oregnclr,
radd,
rcompoutinv,
roctdone,
rpwrdn,
rshift,
rshiftvref,
rtest,
shiftedvref,
vccnx,
vref
);
input clken;
input clkin;
input [8:0] maskbit;
input nclr;
input octpin;
input oregclk;
input oregnclr;
input [7:0] radd;
input rcompoutinv;
input roctdone;
input rpwrdn;
input rshift;
input rshiftvref;
input rtest;
input shiftedvref;
input vccnx;
input vref;
output compout;
output [7:0] octcal; // to IO bank
output [7:0] octrpcd; // to the reference RUP/RDN
parameter is_rdn = "false";// initial value of octcal differ
parameter OCTCAL_DLY = 0; // 1;
parameter REG_TCO_DLY = 0; // 1;
//supply0 vss;
reg [7:0] comp_octrpcd;
reg [7:0] octcal_reg;
wire octref;
wire shftref_out;
wire compout_tmp;
wire nout;
wire nbias;
wire pbias;
wire [7:0] octrpcd;
wire [7:0] octcal_reg_in;
wire [7:0] reg_clk;
wire [7:0] srpcd;
wire [7:0] rpcdi;
wire [8:0] rpcdi_temp;
wire shift;
wire shftvrefhv;
wire compout;
wire clr;
wire reg_clkin;
wire reg_nclr;
wire shiftvref;
wire compadcen;
assign shift = rtest & ~clken;
assign compadcen = ~roctdone & clken;
assign shiftvref = ~(rshiftvref | maskbit[1]);
//c6419 xinverted_ls (
//vss, shiftvref, shftvrefhv, vccnx );
//c7223 xbias_ckt (
assign nbias = (compadcen === 1'b1) ? 1'b1 : 1'b0;
assign pbias = (compadcen === 1'b1) ? 1'b0 : 1'bz;
//c7202 xoct_comp (
assign compout_tmp = (compadcen === 1'b1) ? octpin : 1'b0;
assign shftvrefhv = shftref_out;
assign octref = shftvrefhv ? shiftedvref : vref;
assign compout = rcompoutinv ? compout_tmp : ~compout_tmp;
// c7208
assign reg_clk[7:0] = maskbit[7:0];
assign reg_nclr = (compadcen | ~rpwrdn) & nclr;
always @(posedge reg_clk[7] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[7] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[7] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[6] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[6] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[6] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[5] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[5] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[5] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[4] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[4] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[4] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[3] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[3] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[3] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[2] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[2] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[2] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[1] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[1] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[1] <= #(REG_TCO_DLY) compout;
end
always @(posedge reg_clk[0] or negedge reg_nclr) begin
if (!reg_nclr) comp_octrpcd[0] <= #(REG_TCO_DLY) 1'b0;
else comp_octrpcd[0] <= #(REG_TCO_DLY) compout;
end
// output sends to RUP/DN reference pins
assign octrpcd[7] = maskbit[8] ? 1'b1 : comp_octrpcd[7];
assign octrpcd[6] = maskbit[7] ? 1'b1 : comp_octrpcd[6];
// below: set octrpcd[5] and clear prior bit octrpcd[6] based on compout
assign octrpcd[5] = maskbit[6] ? 1'b1 : comp_octrpcd[5];
assign octrpcd[4] = maskbit[5] ? 1'b1 : comp_octrpcd[4];
assign octrpcd[3] = maskbit[4] ? 1'b1 : comp_octrpcd[3];
assign octrpcd[2] = maskbit[3] ? 1'b1 : comp_octrpcd[2];
assign octrpcd[1] = maskbit[2] ? 1'b1 : comp_octrpcd[1];
assign octrpcd[0] = maskbit[1] ? 1'b1 : comp_octrpcd[0];
// c7210 - leftshift
assign srpcd = rshift ? {octrpcd[6:0], 1'b0} : octrpcd;
// c7214 - Adder:
// overflow => max value 8'b1
// underflow => 0;
assign rpcdi_temp[8:0] = srpcd[7:0] + radd[7:0];
assign rpcdi[7:0] = {8{(~radd[7] & rpcdi_temp[8])}} | rpcdi_temp[7:0];
// left shift rotation in test mode - only when calibration is done (clken=0)
// calibration code (octcal) is 0 until calibration completed
// oregclk indicates 10th cycle since masket[8]=1 --> masket[0]=1 + one cycle
// clken is ~oregclk
assign reg_clkin = ~shift ? oregclk : clkin;
assign octcal_reg_in[7:0] = ~shift ? rpcdi[7:0] : ({octcal[6:0], octcal[7]});
initial begin
if (is_rdn == "true")
octcal_reg[7:0] = 8'hFF;
else
octcal_reg[7:0] = 8'h00;
end
// calibrated code cannot be cleared by user_clr
// it is only changed by code from calibration block which is
always @(posedge reg_clkin or negedge oregnclr) begin
if (!oregnclr) octcal_reg[7:0] <= #(REG_TCO_DLY) 8'h00;
else octcal_reg[7:0] <= #(REG_TCO_DLY) octcal_reg_in[7:0];
end
assign #(OCTCAL_DLY) octcal = octcal_reg;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneive_termination
//
// Description : Cycloneive Termination Atom Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneive_termination (
rup,
rdn,
terminationclock,
terminationclear,
devpor,
devclrn,
comparatorprobe,
terminationcontrolprobe,
calibrationdone,
terminationcontrol);
input rup;
input rdn;
input terminationclock;
input terminationclear;
input devpor;
input devclrn;
output comparatorprobe;
output terminationcontrolprobe;
output calibrationdone;
output [15:0] terminationcontrol;
parameter pullup_control_to_core = "false";
parameter power_down = "true";
parameter test_mode = "false";
parameter left_shift_termination_code = "false";
parameter pullup_adder = 0; // -128, 127
parameter pulldown_adder = 0; // -128, 127
parameter clock_divide_by = 32; // 1, 4, 32
parameter runtime_control = "false";
parameter shift_vref_rup = "true";
parameter shift_vref_rdn = "true";
parameter shifted_vref_control = "true";
parameter lpm_type = "cycloneive_termination";
tri1 devclrn;
tri1 devpor;
wire m_gnd;
wire m_vcc;
// interconnecting wires
// ctrl -----------------------------------------
wire xcbout_clken;
wire xcbout_clkin;
wire [8:0] xcbout_maskbit;
wire xcbout_nclr;
wire xcbout_noctdoneuser;
wire xcbout_octdone;
wire xcbout_oregclk;
wire xcbout_oregnclr;
wire xcbout_vref; // to run/dn comparator
wire xcbout_vrefh; // to rdn - shfitedvref
wire xcbout_vrefl; // to rup - shiftedvref
wire xcbin_clkusr;
wire xcbin_intosc; // clk source in powerup mode
wire xcbin_nclrusr;
wire xcbin_nfrzdrv; // devclrn
wire xcbin_rclkdiv; // - 14
wire xcbin_rclrusrinv; // invert nclrusr signal - 13
wire xcbin_rdivsel; // 0 = /32; 1 = /4; - 16
wire xcbin_roctusr; // run_time_control - 15
wire xcbin_rsellvrefdn; // shift_vref_rdn - 26
wire xcbin_rsellvrefup; // shift_vref_rup - 25
wire xcbin_rtest; // test_mode - 2
wire xcbin_vccnx; // VCC voltage src
wire xcbin_vssn; // GND voltage src
// rup and rdn ------------------------------------
// common
wire rshift_in;
wire rpwrdn_in;
wire rup_compout;
wire [7:0] rup_octrupn; // out from XRUP to rupref pin
wire [7:0] rup_octcalnout; // to the I/O bank
wire rupin;
reg [7:0] rup_radd;
wire rdn_compout;
wire [7:0] rdn_octrdnp; // out from XRDN to rdnref pin
wire [7:0] rdn_octcalpout; // to the I/O bank
wire rdnin;
reg [7:0] rdn_radd;
wire calout; // MSB of the calibration code
// primary input and outputs
assign rupin = rup;
assign rdnin = rdn;
// terminationclk and clear feeding into CTRL sub directly
assign calibrationdone = xcbout_octdone;
assign terminationcontrol = {rup_octcalnout, rdn_octcalpout};
assign comparatorprobe = (pullup_control_to_core == "true") ? rup_compout : rdn_compout;
assign calout = (pullup_control_to_core == "true") ? rup_octcalnout[7] : rdn_octcalpout[7];
assign terminationcontrolprobe = (test_mode == "true") ? calout : xcbout_noctdoneuser;
initial begin
rup_radd = pullup_adder;
rdn_radd = pulldown_adder;
end
// CTRL sub-block
assign xcbin_clkusr = terminationclock;
assign xcbin_intosc = 1'b0; // clk source in powerup mode
assign xcbin_nclrusr = (terminationclear === 1'b1) ? 1'b0 : 1'b1;
assign xcbin_nfrzdrv = (devclrn === 1'b0) ? 1'b0 : 1'b1;
assign xcbin_vccnx = 1'b1; // VCC voltage src
assign xcbin_vssn = 1'b0; // GND voltage src
assign xcbin_rclkdiv = (clock_divide_by != 1) ? 1'b1 : 1'b0; //- 14
assign xcbin_rclrusrinv = 1'b0; // invert nclrusr signal - 13
assign xcbin_rdivsel = (clock_divide_by == 32) ? 1'b0 : 1'b1; //- 16
assign xcbin_roctusr = (runtime_control == "true") ? 1'b1 : 1'b0; //- 15
assign xcbin_rsellvrefdn = (shift_vref_rdn == "true") ? 1'b1 : 1'b0; //- 26
assign xcbin_rsellvrefup = (shift_vref_rup == "true") ? 1'b1 : 1'b0; //- 25
assign xcbin_rtest = (test_mode == "true") ? 1'b1 : 1'b0; // - 2
cycloneive_termination_ctrl m_ctrl (
.clken (xcbout_clken ),
.clkin (xcbout_clkin ),
.maskbit (xcbout_maskbit ),
.nclr (xcbout_nclr ),
.noctdoneuser (xcbout_noctdoneuser ),
.octdone (xcbout_octdone ),
.oregclk (xcbout_oregclk ),
.oregnclr (xcbout_oregnclr ),
.vref (xcbout_vref ),
.vrefh (xcbout_vrefh ),
.vrefl (xcbout_vrefl ),
.clkusr (xcbin_clkusr ),
.intosc (xcbin_intosc ),
.nclrusr (xcbin_nclrusr ),
.nfrzdrv (xcbin_nfrzdrv ),
.vccnx (xcbin_vccnx ),
.vssn (xcbin_vssn ),
.rclkdiv (xcbin_rclkdiv ),
.rclrusrinv (xcbin_rclrusrinv ),
.rdivsel (xcbin_rdivsel ),
.roctusr (xcbin_roctusr ),
.rsellvrefdn (xcbin_rsellvrefdn ),
.rsellvrefup (xcbin_rsellvrefup ),
.rtest (xcbin_rtest )
);
assign m_vcc = 1'b1;
assign m_gnd = 1'b0;
assign rshift_in = (left_shift_termination_code == "true") ? 1'b1 : 1'b0;
assign rpwrdn_in = (power_down == "true") ? 1'b1 : 1'b0;
cycloneive_termination_rupdn m_rup (
.compout (rup_compout ),
.octrpcd (rup_octrupn ),
.octcal (rup_octcalnout ),
.octpin (rupin ),
.rcompoutinv (m_vcc ), // no inversion
.radd (rup_radd ),
.clken (xcbout_clken ),
.clkin (xcbout_clkin ),
.maskbit (xcbout_maskbit ),
.nclr (xcbout_nclr ),
.oregclk (xcbout_oregclk ),
.oregnclr (xcbout_oregnclr),
.shiftedvref (xcbout_vrefl ),
.vccnx (xcbin_vccnx ),
.vref (xcbout_vref ),
.roctdone (m_gnd ), // [12]
.rpwrdn (rpwrdn_in ), // [1]
.rshift (rshift_in ), // [3]
.rshiftvref (m_vcc ), // [27]
.rtest (xcbin_rtest )
);
defparam m_rup.is_rdn = "false";
cycloneive_termination_rupdn m_rdn (
.compout (rdn_compout ),
.octrpcd (rdn_octrdnp ),
.octcal (rdn_octcalpout ),
.octpin (rdnin ),
.rcompoutinv (m_gnd ), // invert compout
.radd (rdn_radd ),
.clken (xcbout_clken ),
.clkin (xcbout_clkin ),
.maskbit (xcbout_maskbit ),
.nclr (xcbout_nclr ),
.oregclk (xcbout_oregclk ),
.oregnclr (xcbout_oregnclr),
.shiftedvref (xcbout_vrefh ),
.vccnx (xcbin_vccnx ),
.vref (xcbout_vref ),
.roctdone (m_gnd ), // [12]
.rpwrdn (rpwrdn_in ), // [1]
.rshift (rshift_in ), // [3]
.rshiftvref (m_vcc ), // [27]
.rtest (xcbin_rtest )
);
defparam m_rdn.is_rdn = "true";
endmodule
//--------------------------------------------------------------------
//
// Module Name : cycloneive_jtag
//
// Description : Cycloneive JTAG Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneive_jtag (
tms,
tck,
tdi,
tdoutap,
tdouser,
tdo,
tmsutap,
tckutap,
tdiutap,
shiftuser,
clkdruser,
updateuser,
runidleuser,
usr1user);
input tms;
input tck;
input tdi;
input tdoutap;
input tdouser;
output tdo;
output tmsutap;
output tckutap;
output tdiutap;
output shiftuser;
output clkdruser;
output updateuser;
output runidleuser;
output usr1user;
parameter lpm_type = "cycloneive_jtag";
endmodule
//--------------------------------------------------------------------
//
// Module Name : cycloneive_crcblock
//
// Description : Cycloneive CRCBLOCK Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneive_crcblock (
clk,
shiftnld,
ldsrc,
crcerror,
regout);
input clk;
input shiftnld;
input ldsrc;
output crcerror;
output regout;
assign crcerror = 1'b0;
assign regout = 1'b0;
parameter oscillator_divider = 1;
parameter lpm_type = "cycloneive_crcblock";
endmodule
///////////////////////////////////////////////////////////////////////
//
// CYCLONEIVE OSCILLATOR ATOM
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cycloneive_oscillator
(
oscena,
clkout
);
parameter lpm_type = "cycloneive_oscillator";
input oscena;
output clkout;
// LOCAL_PARAMETERS_BEGIN
parameter OSC_PW = 6250; // fixed 80HZ running clock
// LOCAL_PARAMETERS_END
// INTERNAL wire
reg int_osc; // internal oscillator
specify
(posedge oscena => (clkout +: 1'b1)) = (0, 0);
endspecify
initial
int_osc = 1'b0;
always @(int_osc or oscena)
begin
if (oscena == 1'b1)
int_osc <= #OSC_PW ~int_osc;
end
and (clkout, int_osc, 1'b1);
endmodule
`ifdef MODEL_TECH
`mti_v2k_int_delays_off
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINVLP_SYMBOL_V
`define SKY130_FD_SC_HD__CLKINVLP_SYMBOL_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkinvlp (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINVLP_SYMBOL_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
adc_clk_in_p,
adc_clk_in_n,
adc_or_in_p,
adc_or_in_n,
adc_data_in_p,
adc_data_in_n,
spi_adf4351_csn,
spi_ad9652_csn,
spi_ad9517_csn,
spi_clk,
spi_sdio,
adf4351_ld);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input adc_clk_in_p;
input adc_clk_in_n;
input adc_or_in_p;
input adc_or_in_n;
input [15:0] adc_data_in_p;
input [15:0] adc_data_in_n;
output spi_adf4351_csn;
output spi_ad9652_csn;
output spi_ad9517_csn;
output spi_clk;
inout spi_sdio;
inout adf4351_ld;
// internal registers
reg adc_dwr = 'd0;
reg [31:0] adc_ddata = 'd0;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire adc_clk;
wire adc_valid_0;
wire adc_enable_0;
wire [15:0] adc_data_0;
wire adc_valid_1;
wire adc_enable_1;
wire [15:0] adc_data_1;
// pack-unpack place holder
always @(posedge adc_clk) begin
case ({adc_enable_1, adc_enable_0})
2'b10: begin
adc_dwr <= ~adc_dwr;
adc_ddata <= {adc_data_1, adc_ddata[31:16]};
end
2'b01: begin
adc_dwr <= ~adc_dwr;
adc_ddata <= {adc_data_0, adc_ddata[31:16]};
end
default: begin
adc_dwr <= 1'b1;
adc_ddata <= {adc_data_1, adc_data_0};
end
endcase
end
// spi
assign spi_clk = spi0_clk;
assign spi_ad9517_csn = spi0_csn[0];
assign spi_ad9652_csn = spi0_csn[1];
assign spi_adf4351_csn = spi0_csn[2];
// instantiations
fmcomms6_spi i_spi (
.spi_csn (spi0_csn),
.spi_clk (spi0_clk),
.spi_mosi (spi0_mosi),
.spi_miso (spi0_miso),
.spi_sdio (spi_sdio));
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf (
.dio_t (gpio_t[32]),
.dio_i (gpio_o[32]),
.dio_o (gpio_i[32]),
.dio_p (adf4351_ld));
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.adc_clk (adc_clk),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_ddata (adc_ddata),
.adc_dwr (adc_dwr),
.adc_enable_0 (adc_enable_0),
.adc_enable_1 (adc_enable_1),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_valid_0 (adc_valid_0),
.adc_valid_1 (adc_valid_1),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_12 (1'b0),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),
.spi0_csn_0_o (spi0_csn[0]),
.spi0_csn_1_o (spi0_csn[1]),
.spi0_csn_2_o (spi0_csn[2]),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi0_miso),
.spi0_sdo_i (spi0_mosi),
.spi0_sdo_o (spi0_mosi),
.spi1_clk_i (spi1_clk),
.spi1_clk_o (spi1_clk),
.spi1_csn_0_o (spi1_csn[0]),
.spi1_csn_1_o (spi1_csn[1]),
.spi1_csn_2_o (spi1_csn[2]),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b1),
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************
|
module lab5_top(CLK, SW, KEY, RESET_N, LEDR, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0);
input CLK;
input [9:0] SW;
input [3:0] KEY;
input RESET_N;
output [9:0] LEDR;
output [6:0] HEX5;
output [6:0] HEX4;
output [6:0] HEX3;
output [6:0] HEX2;
output [6:0] HEX1;
output [6:0] HEX0;
wire RESET;
wire EN_L;
wire [7:0] IOA;
wire [7:0] IOB;
wire [7:0] IOC;
wire [7:0] IOD;
wire [7:0] IOE;
wire [7:0] IOF;
wire [7:0] IOG;
assign RESET = ~RESET_N;
assign EN_L = KEY[2];
lab5 daCore(
.CLK(CLK),
.RESET(RESET),
.IOA(IOA),
.IOB(IOB),
.IOC(IOC),
.EN_L(EN_L),
.IOD(IOD),
.IOE(IOE),
.IOF(IOF),
.IOG(IOG)
);
dual_reg_in inputs(
.CLK(CLK),
.IN(SW[7:0]),
.SEL(SW[8]),
.WEN_L(KEY[3]),
.OUTA(IOA),
.OUTB(IOB)
);
// PUSHBUTTON INPUT LOGIC
assign IOC[7:2] = 6'b0;
assign IOC[1] = ~KEY[1];
assign IOC[0] = ~KEY[0];
// LED ARRAY LOGIC
assign LEDR[9] = CLK;
assign LEDR[8] = 1'b0;
assign LEDR[7:0] = IOD;
// SEVEN-SEGMENT DISPLAY DRIVERS
hex_to_seven_seg upperIOG(
.B(IOG[7:4]),
.SSEG_L(HEX5)
);
hex_to_seven_seg lowerIOG(
.B(IOG[3:0]),
.SSEG_L(HEX4)
);
hex_to_seven_seg upperIOF(
.B(IOF[7:4]),
.SSEG_L(HEX3)
);
hex_to_seven_seg lowerIOF(
.B(IOF[3:0]),
.SSEG_L(HEX2)
);
hex_to_seven_seg upperIOE(
.B(IOE[7:4]),
.SSEG_L(HEX1)
);
hex_to_seven_seg lowerIOE(
.B(IOE[3:0]),
.SSEG_L(HEX0)
);
endmodule
|
//
// Copyright (c) 2014 Jan Adelsbach <[email protected]>.
// All Rights Reserved.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`include "nova_defs.v"
module nova_ram(pclk, prst, mm_adr, mm_we, mm_din, mm_dout);
parameter addr_width = 16;
parameter mem_size = 1 << addr_width;
parameter mem_mask = mem_size-1;
input pclk;
input prst;
input [0:15] mm_adr;
input mm_we;
input [0:15] mm_din;
output [0:15] mm_dout;
reg [0:15] m_mem[0:mem_size];
wire [0:addr_width-1] w_adr_masked;
integer i;
assign w_adr_masked = mm_adr[0:addr_width-1];
assign mm_dout = (~mm_we) ? m_mem[w_adr_masked] : 16'h0000;
always @(posedge pclk) begin
if(prst) begin
for(i = 0; i < mem_size; i = i + 1)
m_mem[i] = 16'h0000;
// #9 $readmemh("rdos.hex", m_mem);
// Interrupt test
m_mem[1] = 16'b0000_0000_0000_0100; // @4
// IORST
m_mem[2][0:2] = 3'b011;
m_mem[2][`NOVA_IO_TRANSFER] = `NOVA_IO_TRANSFER_DIC;
m_mem[2][`NOVA_IO_CONTROL] = `NOVA_IO_CONTROL_CLR;
m_mem[2][`NOVA_IO_DEVICE] = 6'o77;
// JMP 2
m_mem[3][`NOVA_LS_DISPLACE] = 8'h2;
// HALT
m_mem[4][0:2] = 3'b011;
m_mem[4][`NOVA_IO_TRANSFER] = `NOVA_IO_TRANSFER_DOC;
m_mem[4][`NOVA_IO_CONTROL] = `NOVA_IO_CONTROL_CLR;
m_mem[4][`NOVA_IO_DEVICE] = 6'o77;
end
else begin
if(mm_we) begin
// $display("M[%h] = %h", mm_adr, mm_din);
m_mem[w_adr_masked] <= mm_din;
end
end
end
endmodule // nova_ram
|
/*
Copyright (c) 2014-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 125MHz LVDS
* Reset: Push button, active low
*/
input wire clk_125mhz_p,
input wire clk_125mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* I2C for board management
*/
inout wire i2c_scl,
inout wire i2c_sda,
/*
* Ethernet: QSFP28
*/
input wire qsfp_rx1_p,
input wire qsfp_rx1_n,
input wire qsfp_rx2_p,
input wire qsfp_rx2_n,
input wire qsfp_rx3_p,
input wire qsfp_rx3_n,
input wire qsfp_rx4_p,
input wire qsfp_rx4_n,
output wire qsfp_tx1_p,
output wire qsfp_tx1_n,
output wire qsfp_tx2_p,
output wire qsfp_tx2_n,
output wire qsfp_tx3_p,
output wire qsfp_tx3_n,
output wire qsfp_tx4_p,
output wire qsfp_tx4_n,
input wire qsfp_mgt_refclk_0_p,
input wire qsfp_mgt_refclk_0_n,
// input wire qsfp_mgt_refclk_1_p,
// input wire qsfp_mgt_refclk_1_n,
// output wire qsfp_recclk_p,
// output wire qsfp_recclk_n,
output wire qsfp_modsell,
output wire qsfp_resetl,
input wire qsfp_modprsl,
input wire qsfp_intl,
output wire qsfp_lpmode,
/*
* Ethernet: 1000BASE-T SGMII
*/
input wire phy_sgmii_rx_p,
input wire phy_sgmii_rx_n,
output wire phy_sgmii_tx_p,
output wire phy_sgmii_tx_n,
input wire phy_sgmii_clk_p,
input wire phy_sgmii_clk_n,
output wire phy_reset_n,
input wire phy_int_n,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// Clock and reset
wire clk_125mhz_ibufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_125mhz_ibufg_inst (
.O (clk_125mhz_ibufg),
.I (clk_125mhz_p),
.IB (clk_125mhz_n)
);
// MMCM instance
// 125 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 600 MHz to 1440 MHz
// M = 5, D = 1 sets Fvco = 625 MHz (in range)
// Divide by 5 to get output frequency of 125 MHz
MMCME3_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(5),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(5),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(8.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_125mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(4),
.RATE(156000)
)
debounce_switch_inst (
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_cts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_156mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
);
// SI570 I2C
wire i2c_scl_i;
wire i2c_scl_o = 1'b1;
wire i2c_scl_t = 1'b1;
wire i2c_sda_i;
wire i2c_sda_o = 1'b1;
wire i2c_sda_t = 1'b1;
assign i2c_scl_i = i2c_scl;
assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
assign i2c_sda_i = i2c_sda;
assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
// XGMII 10G PHY
assign qsfp_modsell = 1'b0;
assign qsfp_resetl = 1'b1;
assign qsfp_lpmode = 1'b0;
wire qsfp_tx_clk_1_int;
wire qsfp_tx_rst_1_int;
wire [63:0] qsfp_txd_1_int;
wire [7:0] qsfp_txc_1_int;
wire qsfp_rx_clk_1_int;
wire qsfp_rx_rst_1_int;
wire [63:0] qsfp_rxd_1_int;
wire [7:0] qsfp_rxc_1_int;
wire qsfp_tx_clk_2_int;
wire qsfp_tx_rst_2_int;
wire [63:0] qsfp_txd_2_int;
wire [7:0] qsfp_txc_2_int;
wire qsfp_rx_clk_2_int;
wire qsfp_rx_rst_2_int;
wire [63:0] qsfp_rxd_2_int;
wire [7:0] qsfp_rxc_2_int;
wire qsfp_tx_clk_3_int;
wire qsfp_tx_rst_3_int;
wire [63:0] qsfp_txd_3_int;
wire [7:0] qsfp_txc_3_int;
wire qsfp_rx_clk_3_int;
wire qsfp_rx_rst_3_int;
wire [63:0] qsfp_rxd_3_int;
wire [7:0] qsfp_rxc_3_int;
wire qsfp_tx_clk_4_int;
wire qsfp_tx_rst_4_int;
wire [63:0] qsfp_txd_4_int;
wire [7:0] qsfp_txc_4_int;
wire qsfp_rx_clk_4_int;
wire qsfp_rx_rst_4_int;
wire [63:0] qsfp_rxd_4_int;
wire [7:0] qsfp_rxc_4_int;
assign clk_156mhz_int = qsfp_tx_clk_1_int;
assign rst_156mhz_int = qsfp_tx_rst_1_int;
wire qsfp_rx_block_lock_1;
wire qsfp_rx_block_lock_2;
wire qsfp_rx_block_lock_3;
wire qsfp_rx_block_lock_4;
wire qsfp_mgt_refclk_0;
IBUFDS_GTE3 ibufds_gte3_qsfp_mgt_refclk_0_inst (
.I (qsfp_mgt_refclk_0_p),
.IB (qsfp_mgt_refclk_0_n),
.CEB (1'b0),
.O (qsfp_mgt_refclk_0),
.ODIV2 ()
);
wire qsfp_qpll0lock;
wire qsfp_qpll0outclk;
wire qsfp_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1)
)
qsfp_phy_1_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(qsfp_mgt_refclk_0),
.xcvr_qpll0lock_out(qsfp_qpll0lock),
.xcvr_qpll0outclk_out(qsfp_qpll0outclk),
.xcvr_qpll0outrefclk_out(qsfp_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(qsfp_tx1_p),
.xcvr_txn(qsfp_tx1_n),
.xcvr_rxp(qsfp_rx1_p),
.xcvr_rxn(qsfp_rx1_n),
// PHY connections
.phy_tx_clk(qsfp_tx_clk_1_int),
.phy_tx_rst(qsfp_tx_rst_1_int),
.phy_xgmii_txd(qsfp_txd_1_int),
.phy_xgmii_txc(qsfp_txc_1_int),
.phy_rx_clk(qsfp_rx_clk_1_int),
.phy_rx_rst(qsfp_rx_rst_1_int),
.phy_xgmii_rxd(qsfp_rxd_1_int),
.phy_xgmii_rxc(qsfp_rxc_1_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_phy_2_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_tx2_p),
.xcvr_txn(qsfp_tx2_n),
.xcvr_rxp(qsfp_rx2_p),
.xcvr_rxn(qsfp_rx2_n),
// PHY connections
.phy_tx_clk(qsfp_tx_clk_2_int),
.phy_tx_rst(qsfp_tx_rst_2_int),
.phy_xgmii_txd(qsfp_txd_2_int),
.phy_xgmii_txc(qsfp_txc_2_int),
.phy_rx_clk(qsfp_rx_clk_2_int),
.phy_rx_rst(qsfp_rx_rst_2_int),
.phy_xgmii_rxd(qsfp_rxd_2_int),
.phy_xgmii_rxc(qsfp_rxc_2_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_phy_3_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_tx3_p),
.xcvr_txn(qsfp_tx3_n),
.xcvr_rxp(qsfp_rx3_p),
.xcvr_rxn(qsfp_rx3_n),
// PHY connections
.phy_tx_clk(qsfp_tx_clk_3_int),
.phy_tx_rst(qsfp_tx_rst_3_int),
.phy_xgmii_txd(qsfp_txd_3_int),
.phy_xgmii_txc(qsfp_txc_3_int),
.phy_rx_clk(qsfp_rx_clk_3_int),
.phy_rx_rst(qsfp_rx_rst_3_int),
.phy_xgmii_rxd(qsfp_rxd_3_int),
.phy_xgmii_rxc(qsfp_rxc_3_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_phy_4_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_tx4_p),
.xcvr_txn(qsfp_tx4_n),
.xcvr_rxp(qsfp_rx4_p),
.xcvr_rxn(qsfp_rx4_n),
// PHY connections
.phy_tx_clk(qsfp_tx_clk_4_int),
.phy_tx_rst(qsfp_tx_rst_4_int),
.phy_xgmii_txd(qsfp_txd_4_int),
.phy_xgmii_txc(qsfp_txc_4_int),
.phy_rx_clk(qsfp_rx_clk_4_int),
.phy_rx_rst(qsfp_rx_rst_4_int),
.phy_xgmii_rxd(qsfp_rxd_4_int),
.phy_xgmii_rxc(qsfp_rxc_4_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
// SGMII interface to PHY
wire phy_gmii_clk_int;
wire phy_gmii_rst_int;
wire phy_gmii_clk_en_int;
wire [7:0] phy_gmii_txd_int;
wire phy_gmii_tx_en_int;
wire phy_gmii_tx_er_int;
wire [7:0] phy_gmii_rxd_int;
wire phy_gmii_rx_dv_int;
wire phy_gmii_rx_er_int;
wire [15:0] gig_eth_pcspma_status_vector;
wire gig_eth_pcspma_status_link_status = gig_eth_pcspma_status_vector[0];
wire gig_eth_pcspma_status_link_synchronization = gig_eth_pcspma_status_vector[1];
wire gig_eth_pcspma_status_rudi_c = gig_eth_pcspma_status_vector[2];
wire gig_eth_pcspma_status_rudi_i = gig_eth_pcspma_status_vector[3];
wire gig_eth_pcspma_status_rudi_invalid = gig_eth_pcspma_status_vector[4];
wire gig_eth_pcspma_status_rxdisperr = gig_eth_pcspma_status_vector[5];
wire gig_eth_pcspma_status_rxnotintable = gig_eth_pcspma_status_vector[6];
wire gig_eth_pcspma_status_phy_link_status = gig_eth_pcspma_status_vector[7];
wire [1:0] gig_eth_pcspma_status_remote_fault_encdg = gig_eth_pcspma_status_vector[9:8];
wire [1:0] gig_eth_pcspma_status_speed = gig_eth_pcspma_status_vector[11:10];
wire gig_eth_pcspma_status_duplex = gig_eth_pcspma_status_vector[12];
wire gig_eth_pcspma_status_remote_fault = gig_eth_pcspma_status_vector[13];
wire [1:0] gig_eth_pcspma_status_pause = gig_eth_pcspma_status_vector[15:14];
wire [4:0] gig_eth_pcspma_config_vector;
assign gig_eth_pcspma_config_vector[4] = 1'b1; // autonegotiation enable
assign gig_eth_pcspma_config_vector[3] = 1'b0; // isolate
assign gig_eth_pcspma_config_vector[2] = 1'b0; // power down
assign gig_eth_pcspma_config_vector[1] = 1'b0; // loopback enable
assign gig_eth_pcspma_config_vector[0] = 1'b0; // unidirectional enable
wire [15:0] gig_eth_pcspma_an_config_vector;
assign gig_eth_pcspma_an_config_vector[15] = 1'b1; // SGMII link status
assign gig_eth_pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge
assign gig_eth_pcspma_an_config_vector[13:12] = 2'b01; // full duplex
assign gig_eth_pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed
assign gig_eth_pcspma_an_config_vector[9] = 1'b0; // reserved
assign gig_eth_pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved
assign gig_eth_pcspma_an_config_vector[6] = 1'b0; // reserved
assign gig_eth_pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved
assign gig_eth_pcspma_an_config_vector[4:1] = 4'b0000; // reserved
assign gig_eth_pcspma_an_config_vector[0] = 1'b1; // SGMII
gig_ethernet_pcs_pma_0
gig_eth_pcspma (
// SGMII
.txp (phy_sgmii_tx_p),
.txn (phy_sgmii_tx_n),
.rxp (phy_sgmii_rx_p),
.rxn (phy_sgmii_rx_n),
// Ref clock from PHY
.refclk625_p (phy_sgmii_clk_p),
.refclk625_n (phy_sgmii_clk_n),
// async reset
.reset (rst_125mhz_int),
// clock and reset outputs
.clk125_out (phy_gmii_clk_int),
.clk625_out (),
.clk312_out (),
.rst_125_out (phy_gmii_rst_int),
.idelay_rdy_out (),
.mmcm_locked_out (),
// MAC clocking
.sgmii_clk_r (),
.sgmii_clk_f (),
.sgmii_clk_en (phy_gmii_clk_en_int),
// Speed control
.speed_is_10_100 (gig_eth_pcspma_status_speed != 2'b10),
.speed_is_100 (gig_eth_pcspma_status_speed == 2'b01),
// Internal GMII
.gmii_txd (phy_gmii_txd_int),
.gmii_tx_en (phy_gmii_tx_en_int),
.gmii_tx_er (phy_gmii_tx_er_int),
.gmii_rxd (phy_gmii_rxd_int),
.gmii_rx_dv (phy_gmii_rx_dv_int),
.gmii_rx_er (phy_gmii_rx_er_int),
.gmii_isolate (),
// Configuration
.configuration_vector (gig_eth_pcspma_config_vector),
.an_interrupt (),
.an_adv_config_vector (gig_eth_pcspma_an_config_vector),
.an_restart_config (1'b0),
// Status
.status_vector (gig_eth_pcspma_status_vector),
.signal_detect (1'b1)
);
wire [7:0] led_int;
assign led[0] = sw[0] ? qsfp_rx_block_lock_1 : led_int[0];
assign led[1] = sw[0] ? qsfp_rx_block_lock_2 : led_int[1];
assign led[2] = sw[0] ? qsfp_rx_block_lock_3 : led_int[2];
assign led[3] = sw[0] ? qsfp_rx_block_lock_4 : led_int[3];
assign led[4] = sw[0] ? 1'b0 : led_int[4];
assign led[5] = sw[0] ? 1'b0 : led_int[5];
assign led[6] = sw[0] ? 1'b0 : led_int[6];
assign led[7] = sw[0] ? 1'b0 : led_int[7];
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led_int),
/*
* Ethernet: QSFP28
*/
.qsfp_tx_clk_1(qsfp_tx_clk_1_int),
.qsfp_tx_rst_1(qsfp_tx_rst_1_int),
.qsfp_txd_1(qsfp_txd_1_int),
.qsfp_txc_1(qsfp_txc_1_int),
.qsfp_rx_clk_1(qsfp_rx_clk_1_int),
.qsfp_rx_rst_1(qsfp_rx_rst_1_int),
.qsfp_rxd_1(qsfp_rxd_1_int),
.qsfp_rxc_1(qsfp_rxc_1_int),
.qsfp_tx_clk_2(qsfp_tx_clk_2_int),
.qsfp_tx_rst_2(qsfp_tx_rst_2_int),
.qsfp_txd_2(qsfp_txd_2_int),
.qsfp_txc_2(qsfp_txc_2_int),
.qsfp_rx_clk_2(qsfp_rx_clk_2_int),
.qsfp_rx_rst_2(qsfp_rx_rst_2_int),
.qsfp_rxd_2(qsfp_rxd_2_int),
.qsfp_rxc_2(qsfp_rxc_2_int),
.qsfp_tx_clk_3(qsfp_tx_clk_3_int),
.qsfp_tx_rst_3(qsfp_tx_rst_3_int),
.qsfp_txd_3(qsfp_txd_3_int),
.qsfp_txc_3(qsfp_txc_3_int),
.qsfp_rx_clk_3(qsfp_rx_clk_3_int),
.qsfp_rx_rst_3(qsfp_rx_rst_3_int),
.qsfp_rxd_3(qsfp_rxd_3_int),
.qsfp_rxc_3(qsfp_rxc_3_int),
.qsfp_tx_clk_4(qsfp_tx_clk_4_int),
.qsfp_tx_rst_4(qsfp_tx_rst_4_int),
.qsfp_txd_4(qsfp_txd_4_int),
.qsfp_txc_4(qsfp_txc_4_int),
.qsfp_rx_clk_4(qsfp_rx_clk_4_int),
.qsfp_rx_rst_4(qsfp_rx_rst_4_int),
.qsfp_rxd_4(qsfp_rxd_4_int),
.qsfp_rxc_4(qsfp_rxc_4_int),
/*
* Ethernet: 1000BASE-T SGMII
*/
.phy_gmii_clk(phy_gmii_clk_int),
.phy_gmii_rst(phy_gmii_rst_int),
.phy_gmii_clk_en(phy_gmii_clk_en_int),
.phy_gmii_rxd(phy_gmii_rxd_int),
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
.phy_gmii_rx_er(phy_gmii_rx_er_int),
.phy_gmii_txd(phy_gmii_txd_int),
.phy_gmii_tx_en(phy_gmii_tx_en_int),
.phy_gmii_tx_er(phy_gmii_tx_er_int),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int)
);
endmodule
`resetall
|
//-----------------------------------------------------------------
// RISC-V Top
// V0.6
// Ultra-Embedded.com
// Copyright 2014-2019
//
// [email protected]
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module icache_data_ram
(
// Inputs
input clk_i
,input rst_i
,input [ 10:0] addr_i
,input [ 31:0] data_i
,input wr_i
// Outputs
,output [ 31:0] data_o
);
//-----------------------------------------------------------------
// Single Port RAM 8KB
// Mode: Read First
//-----------------------------------------------------------------
reg [31:0] ram [2047:0] /*verilator public*/;
reg [31:0] ram_read_q;
// Synchronous write
always @ (posedge clk_i)
begin
if (wr_i)
ram[addr_i] <= data_i;
ram_read_q <= ram[addr_i];
end
assign data_o = ram_read_q;
endmodule
|
/**
* bsg_cache_non_blocking_pkt_decode.v
*
* @author tommy
*
*/
`include "bsg_defines.v"
module bsg_cache_non_blocking_decode
import bsg_cache_non_blocking_pkg::*;
(
input bsg_cache_non_blocking_opcode_e opcode_i
, output bsg_cache_non_blocking_decode_s decode_o
);
always_comb begin
case (opcode_i)
LD, SD: decode_o.size_op = 2'b11;
LW, SW, LWU: decode_o.size_op = 2'b10;
LH, SH, LHU: decode_o.size_op = 2'b01;
LB, SB, LBU: decode_o.size_op = 2'b00;
default: decode_o.size_op = 2'b00;
endcase
end
assign decode_o.sigext_op = (opcode_i == LB)
| (opcode_i == LH)
| (opcode_i == LW)
| (opcode_i == LD);
assign decode_o.ld_op = (opcode_i == LB)
| (opcode_i == LH)
| (opcode_i == LW)
| (opcode_i == LD)
| (opcode_i == LBU)
| (opcode_i == LHU)
| (opcode_i == LWU);
assign decode_o.st_op = (opcode_i == SB)
| (opcode_i == SH)
| (opcode_i == SW)
| (opcode_i == SD)
| (opcode_i == SM);
assign decode_o.mask_op = (opcode_i == SM);
assign decode_o.block_ld_op = (opcode_i == BLOCK_LD);
assign decode_o.tagst_op = (opcode_i == TAGST);
assign decode_o.tagfl_op = (opcode_i == TAGFL);
assign decode_o.taglv_op = (opcode_i == TAGLV);
assign decode_o.tagla_op = (opcode_i == TAGLA);
assign decode_o.afl_op = (opcode_i == AFL);
assign decode_o.aflinv_op = (opcode_i == AFLINV);
assign decode_o.ainv_op = (opcode_i == AINV);
assign decode_o.alock_op = (opcode_i == ALOCK);
assign decode_o.aunlock_op = (opcode_i == AUNLOCK);
assign decode_o.mgmt_op = ~(decode_o.ld_op | decode_o.st_op | decode_o.block_ld_op);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S18_SYMBOL_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S18_SYMBOL_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkdlybuf4s18 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S18_SYMBOL_V
|
(*
Copyright © 2007-2008 Russell O’Connor
Permission is hereby granted, free of charge, to any person obtaining a copy of
this proof and associated documentation files (the "Proof"), to deal in
the Proof without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
the Proof, and to permit persons to whom the Proof is furnished to do so,
subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Proof.
THE PROOF IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE PROOF OR THE USE OR OTHER DEALINGS IN THE PROOF.
*)
Require Export CoRN.algebra.RSetoid.
Require Export CoRN.metric2.StepFunction.
Require Import CoRN.model.structures.OpenUnit.
Require Import CoRN.tactics.CornTac.
Require Import CoRN.tactics.Qauto.
Require Import CoRN.model.ordfields.Qordfield.
Require Import CoRN.algebra.COrdFields.
Set Implicit Arguments.
Set Automatic Introduction.
Local Open Scope Q_scope.
(**
** Step Functions over setoids
In this section we redevelop step functions over a setoid X.
The applicative functor StepF lifts equivalence relations (setoids).
When type X has an equivalence relation eqX, then StepF X inherits
an equivalence relation StepF_eq, by checking that the leaf values in X
are equivalent for each rational argument. Moreover, a morphism f : X --> Y
lifts to a morphism map StepF f : StepF X --> StepF Y.
In other words, StepF is an endofunctor of the category of setoids.
*)
Local Open Scope setoid_scope.
(** We lift ap to the setoid version. Map is a notation calling ap so
that all lemmas about ap automatically apply to Map. *)
Definition Ap (X Y : RSetoid) : (StepF (X --> Y))->(StepF X)->(StepF Y)
:= fun f x => (@Ap X Y (StepFunction.Map (@evalMorphism X Y) f) x).
Notation "f <@> x" := (Ap f x) (at level 15, left associativity) : sfstscope.
Notation "f ^@> x" := (Ap (constStepF f) x) (at level 15, left associativity) : sfstscope.
Notation "f <@^ x" := (Ap f (constStepF x)) (at level 15, left associativity) : sfstscope.
Local Open Scope sfstscope.
(** We lift lemmas about map, ap, mirror, and glue *)
Lemma MirrorGlue : forall (X : RSetoid) (o : OpenUnit) (al ar : StepF X),
Mirror (glue o al ar) = glue (OpenUnitDual o) (Mirror ar) (Mirror al).
Proof.
reflexivity.
Qed.
Lemma MapGlue : forall (X Y : RSetoid) (f : (X --> Y))
(o : OpenUnit) (al ar : StepF X),
f ^@> (glue o al ar) = glue o (f ^@> al) (f ^@> ar).
Proof.
reflexivity.
Qed.
Lemma ApGlue : forall (X Y : RSetoid) (fl fr : StepF (X --> Y))
(o : OpenUnit) (b : StepF X),
(glue o fl fr) <@> b = glue o (fl <@> (SplitL b o)) (fr <@> (SplitR b o)).
Proof.
intros X Y fl fr o b.
unfold Ap.
simpl (StepFunction.Map (@evalMorphism X Y) (glue o fl fr)).
rewrite ApGlue.
reflexivity.
Qed.
Lemma ApGlueGlue : forall (X Y : RSetoid) (fl fr : StepF (X --> Y)) (o : OpenUnit) (l r : StepF X),
(glue o fl fr) <@> (glue o l r) = glue o (fl <@> l) (fr <@> r).
Proof.
intros X Y fl fr o l r.
unfold Ap.
simpl (StepFunction.Map (@evalMorphism X Y) (glue o fl fr)).
rewrite ApGlueGlue.
reflexivity.
Qed.
Lemma SplitLMap : forall (X Y : RSetoid) (x : StepF X) (a : OpenUnit) (f : X --> Y),
SplitL (f ^@> x) a = f ^@> (SplitL x a).
Proof.
intros X Y x a f.
unfold Ap.
simpl.
rewrite SplitLMap.
reflexivity.
Qed.
Lemma SplitRMap : forall (X Y : RSetoid) (x : StepF X) (a : OpenUnit) (f : X --> Y),
SplitR (f ^@> x) a = f ^@> (SplitR x a).
Proof.
intros X Y x a f.
unfold Ap.
simpl.
rewrite SplitRMap.
reflexivity.
Qed.
Section EquivalenceA.
(** A step function over [Prop], a characteristic function, can be
folded into [Prop], which holds for the always true characteristic
function *)
Definition StepFfoldProp : StepF iffSetoid -> Prop := (StepFfold (X:=iffSetoid) (fun x => x ) (fun _ a b => a /\ b )).
Definition st_eqS0 {X : RSetoid} : X -> X --> iffSetoid.
Proof.
intros x.
exists (st_eq x).
abstract ( intros x1 x2 Hx; simpl; rewrite -> Hx; reflexivity).
Defined.
Definition st_eqS {X : RSetoid} : X --> X --> iffSetoid.
Proof.
exists (st_eqS0).
abstract ( intros x1 x2 Hx y; simpl; rewrite -> Hx; reflexivity).
Defined.
(**
** Equivalence
An equivalence relation on step functions is implemented by lifiting
the equivalence relation on the underlying setoid to step functions.
The results is a characteristic function saying where two step functions
are equivalent. The step functions are considered equivalent if this
characteristic function says they are equivalent everywhere.
*)
Definition StepF_eq {X : RSetoid} (f g:StepF X):Prop:=
(StepFfoldProp (st_eqS ^@> f <@> g)).
Notation "x === y" := (StepF_eq x y) (at level 70).
(** With equality defined we can complete the proof that split is the
opposite of glue *)
Lemma glue_StepF_eq :
forall {X : RSetoid} (s:StepF X) (s1 s2:StepF X),
forall a, s1 === (SplitL s a) -> s2 === (SplitR s a) -> (glue a s1 s2) === s.
Proof.
intros X s s1 s2 a H0 H1.
unfold StepF_eq.
rewrite MapGlue.
rewrite ApGlue.
split; assumption.
Qed.
Lemma glue_eq_ind : forall {X : RSetoid} (s1 s2 s:StepF X) a (P:Prop),
(s1 === SplitL s a -> s2 === SplitR s a -> P) -> (glue a s1 s2 === s) -> P.
Proof.
intros X s1 s2 s a P H H0.
unfold StepF_eq in *.
rewrite -> MapGlue in *.
rewrite ApGlue in H0.
destruct H0.
auto.
Qed.
(** The equivalence relation is reflexive *)
Lemma StepF_eq_refl : forall {X : RSetoid} (x : StepF X), x === x.
Proof.
intro X. induction x.
change (st_eq x x).
reflexivity.
apply glue_StepF_eq.
simpl; rewrite SplitLGlue; assumption.
simpl; rewrite SplitRGlue; assumption.
Qed.
(* begin hide *)
Hint Resolve StepF_eq_refl.
(* end hide *)
(** StepF_Qeq is a refinement of any setoid equality *)
Lemma StepF_Qeq_eq : forall {X : RSetoid} (s t:StepF X), (StepF_Qeq s t) -> s === t.
Proof.
intro X.
induction s; induction t; try contradiction; simpl.
intros H.
rewrite H.
auto with *.
intros [H [H0 H1]].
apply glue_StepF_eq.
apply IHs1.
apply SplitL_glue_ind; intros H2; try (elim (Qlt_not_le _ _ H2); rewrite -> H); auto with *.
apply IHs2.
apply SplitR_glue_ind; intros H2; try (elim (Qlt_not_le _ _ H2); rewrite -> H); auto with *.
Qed.
Lemma glueSplit : forall {X : RSetoid} (s : StepF X),
forall a, (glue a (SplitL s a) (SplitR s a)) === s.
Proof.
intros X s a.
apply glue_StepF_eq; auto with *.
Qed.
End EquivalenceA.
(* begin hide *)
Hint Resolve StepF_eq_refl : sfarith.
(* end hide *)
Notation "x == y" := (StepF_eq x y) (at level 70) : sfstscope.
Section EquivalenceB.
Variable X Y : RSetoid.
Lemma Map_resp_StepF_eq: forall f:X-->Y,
(forall x y, (st_eq x y)-> (st_eq (f x) (f y))) ->
forall s t:(StepF X), s == t -> (f ^@> s) == (f ^@> t).
Proof.
intros f H.
induction s. induction t.
unfold StepF_eq, Map2, StepFfoldProp ;simpl;auto with *.
unfold StepF_eq, Map2, StepFfoldProp. simpl; intuition.
intros t H0.
unfold StepF_eq, Map2 in H0.
rewrite MapGlue in H0.
rewrite ApGlue in H0.
unfold StepF_eq, Map2.
repeat rewrite MapGlue.
rewrite ApGlue.
rewrite SplitLMap.
rewrite SplitRMap.
destruct H0 as [H0l H0R].
split.
apply IHs1; auto.
apply IHs2; auto.
Qed.
End EquivalenceB.
Lemma StepFfoldPropglue:forall (y:StepF iffSetoid) o,
StepFfoldProp (glue o (SplitL y o) (SplitR y o)) <-> StepFfoldProp y.
Proof.
induction y.
unfold StepF_eq, StepFfoldProp.
simpl; tauto.
simpl.
intro o0.
apply SplitLR_glue_ind; intros H.
generalize (IHy1 (OpenUnitDiv o0 o H)).
unfold StepFfoldProp; simpl; tauto.
generalize (IHy2 (OpenUnitDualDiv o0 o H)).
unfold StepFfoldProp; simpl; tauto.
simpl.
reflexivity.
Qed.
Lemma StepFfoldProp_morphism:forall x y:(StepF iffSetoid),
(StepF_eq x y) ->
((StepFfoldProp x)<->(StepFfoldProp y)).
Proof.
induction x. induction y.
auto with *.
unfold StepF_eq. simpl. unfold StepFfoldProp;simpl;intuition.
intros y H0.
unfold StepF_eq, Map2 in H0.
rewrite MapGlue in H0.
rewrite ApGlue in H0.
destruct H0 as [H0l H0r].
change ((StepFfoldProp x1 /\ StepFfoldProp x2) <-> StepFfoldProp y).
rewrite -> (IHx1 (SplitL y o)); auto with *.
rewrite -> (IHx2 (SplitR y o)); auto with *.
apply: StepFfoldPropglue.
Qed.
Lemma StepFfoldPropSplitR
: forall (s : StepF iffSetoid) (a : OpenUnit),
StepFfoldProp s -> StepFfoldProp (SplitR s a).
Proof.
intros s a H.
rewrite <- (StepFfoldPropglue s a) in H.
destruct H; auto.
Qed.
Lemma StepFfoldPropSplitL
: forall (s : StepF iffSetoid) (a : OpenUnit),
StepFfoldProp s -> StepFfoldProp (SplitL s a).
Proof.
intros s a H.
rewrite <- (StepFfoldPropglue s a) in H.
destruct H; auto.
Qed.
Section EquivalenceC.
Variable X : RSetoid.
(* begin hide *)
Hint Resolve StepF_Qeq_eq StepF_Qeq_refl SplitL_resp_Qeq SplitR_resp_Qeq.
(* end hide *)
Lemma StepF_eq_resp_Qeq : forall (s t : StepF X) u v, (StepF_Qeq s t) -> (StepF_Qeq u v) -> s == u -> t == v.
Proof.
induction s; induction t; try contradiction.
intros u v Hst Huv Hsu.
simpl in Hst.
unfold StepF_eq in *.
rewrite <- Hst.
rewrite <- (StepFfoldProp_morphism ((st_eqS) ^@> constStepF x <@> u)); auto.
apply: (Map_resp_StepF_eq); auto with *.
intros a b Hab.
simpl.
rewrite -> Hab.
reflexivity.
intros u v [H [Hst0 Hst1]] Huv Hsu.
destruct Hsu as [Hsu1 Hsu2] using (glue_eq_ind s1).
apply glue_StepF_eq.
eapply IHs1.
assumption.
unfold SplitL; apply SplitL_resp_Qeq.
apply H.
apply Huv.
assumption.
eapply IHs2.
assumption.
unfold SplitR; apply SplitR_resp_Qeq.
apply H.
apply Huv.
assumption.
Qed.
Lemma Mirror_eq_Mirror : forall (s t : StepF X), Mirror s == Mirror t <-> s == t.
Proof.
induction s.
induction t; simpl.
reflexivity.
change (constStepF x == (Mirror t2) /\ constStepF x == (Mirror t1) <-> constStepF x == t1 /\ constStepF x == t2).
tauto.
intros t.
rewrite MirrorGlue.
split; apply (@glue_eq_ind X); intros H0 H1.
apply glue_StepF_eq.
rewrite <- IHs1.
eapply StepF_eq_resp_Qeq;[| |apply H1]; auto with *.
apply StepF_Qeq_sym.
apply MirrorSplitL_Qeq; auto with *.
rewrite <- IHs2.
eapply StepF_eq_resp_Qeq;[| |apply H0]; auto with *.
apply StepF_Qeq_sym.
apply MirrorSplitR_Qeq; auto with *.
apply glue_StepF_eq.
apply StepF_eq_resp_Qeq with (Mirror s2) (Mirror (SplitR t o)); auto.
apply MirrorSplitR_Qeq; apply Qeq_refl.
rewrite -> IHs2.
assumption.
apply StepF_eq_resp_Qeq with (Mirror s1) (Mirror (SplitL t o)); auto.
apply MirrorSplitL_Qeq; apply Qeq_refl.
rewrite -> IHs1.
assumption.
Qed.
Lemma SplitL_resp_Xeq : forall (s1 s2 : StepF X) a, s1 == s2 -> SplitL s1 a == SplitL s2 a.
Proof.
induction s1.
intros s2 a H.
unfold StepF_eq in *.
change (StepFfoldProp ((st_eqS x:X-->iffSetoid) ^@> SplitL s2 a)).
rewrite <- SplitLMap.
apply StepFfoldPropSplitL.
assumption.
intros s2 a H.
destruct H using (glue_eq_ind s1_1).
apply SplitL_glue_ind; intros Hao.
apply StepF_eq_resp_Qeq with (SplitL s1_1 (OpenUnitDiv a o Hao)) (SplitL (SplitL s2 o) (OpenUnitDiv a o Hao)); auto.
apply SplitLSplitL.
simpl; field; auto with *.
apply glue_StepF_eq.
apply StepF_eq_resp_Qeq with s1_1 (SplitL s2 o); auto.
apply StepF_Qeq_sym.
apply SplitLSplitL.
simpl; field; auto with *.
apply StepF_eq_resp_Qeq with (SplitL s1_2 (OpenUnitDualDiv a o Hao)) (SplitL (SplitR s2 o) (OpenUnitDualDiv a o Hao)); auto.
apply SplitLSplitR; simpl; field; auto with *.
apply StepF_eq_resp_Qeq with s1_1 (SplitL s2 o); auto with *.
Qed.
Lemma SplitR_resp_Xeq : forall (s1 s2:StepF X) a, s1 == s2 -> SplitR s1 a == SplitR s2 a.
Proof.
intros s1 s2 a H.
pose (b:=OpenUnitDual a).
apply StepF_eq_resp_Qeq with (Mirror (SplitL (Mirror s1) b)) (Mirror (SplitL (Mirror s2) b));
try (unfold Mirror, SplitR, SplitL, b;eapply StepF_Qeq_trans;[apply Mirror_resp_Qeq; apply StepF_Qeq_sym; apply MirrorSplitR_Qeq; reflexivity|apply MirrorMirror]).
rewrite -> Mirror_eq_Mirror.
apply SplitL_resp_Xeq.
rewrite -> Mirror_eq_Mirror.
assumption.
Qed.
(** equalitiy is transitive *)
Lemma StepF_eq_trans:forall x y z : StepF X, x == y -> y == z -> x == z.
Proof.
induction x. intros.
unfold StepF_eq in *.
set (A:=((st_eqS :X-->X-->iffSetoid) ^@> constStepF x)) in *.
rewrite <- (StepFfoldProp_morphism (A <@> y)); auto with *.
apply: (Map_resp_StepF_eq); auto with *.
intros a b Hab.
simpl.
rewrite -> Hab.
reflexivity.
intros.
destruct H using (glue_eq_ind x1).
apply glue_StepF_eq.
eapply IHx1.
apply H.
apply SplitL_resp_Xeq.
assumption.
eapply IHx2.
apply H1.
apply SplitR_resp_Xeq.
assumption.
Qed.
Lemma glue_resp_StepF_eq:forall (x x' y y':StepF X) o,
(x==x')->(y==y')->
(glue o x y)==(glue o x' y').
Proof.
intros.
unfold StepF_eq.
rewrite MapGlue.
rewrite ApGlueGlue.
split; assumption.
Qed.
(** equality is symmetric *)
Lemma StepF_eq_sym :forall x y: StepF X, x == y -> y == x.
Proof.
intros x y.
revert x.
induction y.
unfold StepF_eq. simpl. intro x0. induction x0.
unfold StepFfoldProp. simpl. intros. symmetry; assumption.
simpl. unfold StepFfoldProp; simpl; intuition; auto with *.
intros x H.
assert (H0:=(SplitL_resp_Xeq _ _ o H)).
rewrite SplitLGlue in H0.
assert (H1:=(SplitR_resp_Xeq _ _ o H)).
rewrite SplitRGlue in H1.
apply glue_StepF_eq;auto with *.
Qed.
End EquivalenceC.
(* begin hide *)
Add Parametric Relation (X : RSetoid) : (StepF X) (@StepF_eq X)
reflexivity proved by (@StepF_eq_refl X)
symmetry proved by (@StepF_eq_sym X)
transitivity proved by (@StepF_eq_trans X)
as StepF_SetoidTheory.
Hint Resolve StepF_eq_sym StepF_eq_trans.
Add Morphism (StepFfoldProp)
with signature (@StepF_eq iffSetoid) ==> iff
as StepFfoldProp_mor.
Proof.
exact StepFfoldProp_morphism.
Qed.
(* end hide *)
Lemma StepF_Sth (X : RSetoid) : (Setoid_Theory (StepF X) (@StepF_eq X)).
split; unfold Reflexive, Symmetric, Transitive; eauto with sfarith.
Qed.
(**
** Common subdivision view
This lemma allows to do induction over two step function as if the
functions had the same subdivisions.
*)
Lemma StepF_ind2 : forall (X Y : RSetoid) (P : StepF X -> StepF Y -> Prop),
(forall (s s0 : StepF X) (t t0 : StepF Y),
(s==s0) -> (t==t0) -> P s t -> P s0 t0) ->
(forall (x:X) (y:Y), P (constStepF x) (constStepF y)) ->
(forall (o : OpenUnit) (s s0 : StepF X) (t t0 : StepF Y),
P s t -> P s0 t0 -> P (glue o s s0) (glue o t t0)) ->
forall (s:StepF X) (t:StepF Y), P s t.
Proof.
intros X Y P wd c0 c1.
induction s.
induction t.
apply c0.
apply wd with (s:=(glue o (constStepF x) (constStepF x))) (t:=glue o t1 t2); try reflexivity.
apply (glueSplit (constStepF x) o).
apply c1; assumption.
intros t.
eapply wd.
reflexivity.
apply glueSplit with (a:=o).
apply c1; auto.
Qed.
Lemma glue_injl {X : RSetoid} :forall o (x y x1 y1:StepF X),
(glue o x y)==(glue o x1 y1) -> (x==x1).
Proof.
intros.
destruct H as [H _] using (glue_eq_ind x).
rewrite SplitLGlue in H.
assumption.
Qed.
Lemma glue_injr {X:RSetoid} :forall o (x y x1 y1:StepF X),
(glue o x y)==(glue o x1 y1) -> (y==y1).
Proof.
intros.
destruct H as [_ H] using (glue_eq_ind x).
rewrite SplitRGlue in H.
assumption.
Qed.
(** Decompose an equality over glue into two parts *)
Lemma eq_glue_ind {X : RSetoid} : forall (s1 s2 s : StepF X) (a : OpenUnit) (P : Prop),
((SplitL s a) == s1 -> (SplitR s a) == s2 -> P) ->
s == (glue a s1 s2) -> P.
Proof.
intros s1 s2 s a P H H0.
symmetry in H0.
destruct H0 as [H0l H0r] using (glue_eq_ind s1).
symmetry in H0l, H0r.
auto.
Qed.
Lemma MirrorSplitR {X : RSetoid} : forall (s : StepF X) (a b : OpenUnit),
(b == OpenUnitDual a)%Q ->
(Mirror (SplitR s a)) == (SplitL (Mirror s) b).
Proof.
intros.
apply StepF_Qeq_eq; auto with *.
apply MirrorSplitR_Qeq; auto with *.
Qed.
Lemma MirrorSplitL {X : RSetoid} : forall (s : StepF X) (a b : OpenUnit),
(b == OpenUnitDual a)%Q ->
(Mirror (SplitL s a)) == (SplitR (Mirror s) b).
Proof.
intros.
apply StepF_Qeq_eq; auto with *.
apply MirrorSplitL_Qeq; auto with *.
Qed.
(** Lift the distribution lemmas between ap and split to work over step
functions *)
Lemma SplitRAp :forall (X Y : RSetoid) (f : StepF (Y --> X)) (s : StepF Y) (o : OpenUnit),
(SplitR (f <@> s) o) == (SplitR f o <@> SplitR s o).
Proof.
intros X Y f s o.
apply StepF_Qeq_eq; auto with *.
unfold Ap.
rewrite <- StepFunction.SplitRMap.
apply SplitRAp_Qeq.
Qed.
Lemma SplitLAp :forall (X Y : RSetoid) (f : StepF (Y --> X)) (s : StepF Y) (o : OpenUnit),
(SplitL (f <@> s) o) == (SplitL f o <@> SplitL s o).
Proof.
intros X Y f s o.
apply StepF_Qeq_eq; auto with *.
unfold Ap.
rewrite <- StepFunction.SplitLMap.
apply SplitLAp_Qeq.
Qed.
(* begin hide *)
Add Parametric Morphism s : (@constStepF s) with signature (@st_eq s) ==> (@StepF_eq s) as constStepF_wd.
Proof.
auto.
Qed.
Add Parametric Morphism s : (@glue s) with signature ou_eq ==> (@StepF_eq s) ==> (@StepF_eq s) ==> (@StepF_eq s) as glue_wd.
Proof.
intros o1 o2 Ho x1 x2 Hx y1 y2 Hy.
transitivity (glue o1 x2 y2).
apply glue_resp_StepF_eq; auto.
apply StepF_Qeq_eq.
repeat split; auto; reflexivity.
Qed.
Add Parametric Morphism X : (@SplitL X) with signature (@StepF_eq X) ==> ou_eq ==> (@StepF_eq X) as SplitL_wd.
Proof.
intros x1 x2 Hx o1 o2 Ho.
transitivity (SplitL x2 o1).
apply SplitL_resp_Xeq; auto.
apply StepF_Qeq_eq.
apply SplitL_resp_Qeq; auto; reflexivity.
Qed.
Add Parametric Morphism X : (@SplitR X) with signature (@StepF_eq X) ==> ou_eq ==> (@StepF_eq X) as SplitR_wd.
Proof.
intros x1 x2 Hx o1 o2 Ho.
transitivity (SplitR x2 o1).
apply SplitR_resp_Xeq; auto.
apply StepF_Qeq_eq.
apply SplitR_resp_Qeq; auto; reflexivity.
Qed.
Add Parametric Morphism X Y : (@Ap X Y) with signature (@StepF_eq (extSetoid X Y)) ==> (@StepF_eq X) ==> (@StepF_eq Y) as Ap_wd.
Proof.
intros f.
induction f; intros g Hfg.
induction g; intros x1.
simpl.
induction x1; intros x2.
induction x2.
intros H.
transitivity (x ^@> (constStepF x2)).
destruct x as [x Hx].
clear Hfg. apply: Hx ; assumption.
apply: Hfg.
intros H.
rewrite MapGlue.
symmetry.
symmetry in H.
destruct H as [Hl Hr] using (glue_eq_ind x2_1).
apply glue_StepF_eq.
symmetry.
symmetry in Hl.
apply IHx2_1.
assumption.
symmetry.
symmetry in Hr.
apply IHx2_2.
assumption.
intros H.
rewrite MapGlue.
destruct H as [Hl Hr] using (glue_eq_ind x1_1).
apply glue_StepF_eq.
rewrite SplitLMap.
apply IHx1_1; auto.
rewrite SplitRMap.
apply IHx1_2; auto.
symmetry.
rewrite ApGlue.
destruct Hfg as [Hfg0 Hfg1] using (eq_glue_ind g1).
apply glue_StepF_eq; symmetry.
rewrite SplitLMap.
apply IHg1; try rewrite -> H0; auto with *.
rewrite SplitRMap.
apply IHg2; try rewrite -> H0; auto with *.
intros s s' Hs.
destruct Hfg as [Hfg0 Hfg1] using (glue_eq_ind f1).
rewrite ApGlue.
apply glue_StepF_eq; auto with *.
rewrite -> SplitLAp.
apply IHf1; try rewrite -> Hs; auto with *.
rewrite -> SplitRAp.
apply IHf2; try rewrite -> Hs; auto with *.
Qed.
(* end hide *)
Lemma GlueAp : forall (X Y : RSetoid) (f : StepF (X --> Y)) (o : OpenUnit) (l r : StepF X),
f <@> (glue o l r) == glue o ((SplitL f o) <@> l) ((SplitR f o) <@> r).
Proof.
intros X Y f o l r.
set (A:= ((SplitL f o)<@>l)).
set (B:= ((SplitR f o)<@>r)).
rewrite <- (glueSplit f o).
rewrite ApGlueGlue.
reflexivity.
Qed.
(**
** Applicative Functor
Here we prove the axioms of an applicative functor.
*)
Lemma Map_homomorphism (X Y : RSetoid) : forall (f:X-->Y) (a:X),
(f ^@> constStepF a) == (constStepF (f a)).
Proof.
reflexivity.
Qed.
Lemma Map_identity (X : RSetoid) : forall (a:StepF X),
(@id X) ^@> a == a.
Proof.
intros a.
now rewrite <-(Map_identity a) at 2.
Qed.
Lemma Map_composition (X Y Z : RSetoid) : forall (a:StepF (Y-->Z)) (b:StepF (X-->Y)) (c:StepF X),
((@compose X Y Z) ^@> a <@> b <@> c) == (a <@> (b <@> c)).
Proof.
induction a.
simpl.
apply (StepF_ind2 (X --> Y) X); auto with *.
intros s s0 t t0 Hs Ht.
rewrite -> Hs, Ht.
auto.
intros o s s0 t t0 H H0.
rewrite -> Map_homomorphism.
rewrite ApGlueGlue.
do 2 rewrite MapGlue.
rewrite ApGlueGlue.
rewrite <- H.
rewrite <- H0.
reflexivity.
intros b c.
rewrite MapGlue.
repeat rewrite ApGlue.
apply glue_resp_StepF_eq.
rewrite -> IHa1.
rewrite -> SplitLAp.
reflexivity.
rewrite -> IHa2.
rewrite -> SplitRAp.
reflexivity.
Qed.
(** Here we show that the rest of the BCKW combinators lift to
step functions. Hence all of the lambda calculus lifts to operate
over step functions. Step functions form about a nice of an
applicative functor as is possible. *)
Lemma Map_discardable (X Y : RSetoid) : forall (a:StepF X) (b:StepF Y),
((@const _ _) ^@> a <@> b == a).
Proof.
apply StepF_ind2; auto with *.
intros s s0 t t0 Hs Ht.
rewrite -> Hs, Ht; auto.
intros o s s0 t t0 H0 H1.
rewrite MapGlue.
rewrite ApGlueGlue.
rewrite -> H0, H1;reflexivity.
Qed.
Lemma Map_commutative W X Y : forall (f:StepF (W --> X --> Y)) (x:StepF X) (w:StepF W),
((@flip _ _ _) ^@> f <@> x <@> w) == (f <@> w <@> x).
Proof.
induction f.
simpl.
apply StepF_ind2; auto with *.
intros s s0 t t0 Hs Ht.
rewrite -> Hs, Ht;auto.
intros o s s0 t t0 H0 H1.
rewrite -> Map_homomorphism.
do 2 rewrite MapGlue.
do 2 rewrite ApGlueGlue.
rewrite -> H0, H1; reflexivity.
intros x w.
rewrite MapGlue.
do 4 rewrite ApGlue.
apply glue_resp_StepF_eq; auto.
Qed.
Lemma Map_copyable X Y : forall (f:StepF (X --> X --> Y)) (x:StepF X),
((@join _ _) ^@> f <@> x) == (f <@> x <@> x).
Proof.
apply StepF_ind2; auto with *.
intros s s0 t t0 Hs Ht.
rewrite -> Hs, Ht; auto.
intros o s s0 t t0 H0 H1.
rewrite MapGlue.
do 3 rewrite ApGlueGlue.
rewrite -> H0, H1;reflexivity.
Qed.
(* begin hide *)
Hint Rewrite
ApGlueGlue ApGlue GlueAp SplitRAp SplitLAp SplitLGlue SplitRGlue
Map_homomorphism : StepF_rew.
Hint Rewrite
Map_composition
Map_discardable
Map_commutative
Map_identity
Map_copyable : StepF_eval.
(* end hide *)
(** This tactic is usefully for symbolically evaluating functions written
in (BCKWI) combinator form that are ap'ed to step functions *)
Ltac evalStepF := progress
(repeat rewrite <- Map_homomorphism; autorewrite with StepF_eval).
Lemma Ap_interchange (X Y : RSetoid) : forall (f:StepF (X-->Y)) (a:X),
(f <@^ a) == (flip id a) ^@> f.
Proof.
intros f a.
evalStepF.
reflexivity.
Qed.
(** Map'ing the S combinator (which is also called ap) *)
Lemma Map_ap X Y Z : forall (f:StepF (X --> Y --> Z)) (x:StepF (X --> Y)) (a:StepF X),
((@ap _ _ _) ^@> f <@> x <@> a) == (f <@> a <@> (x <@> a)).
Proof.
intros f x a.
unfold ap.
evalStepF.
reflexivity.
Qed.
(* begin hide *)
Hint Rewrite Map_ap : StepF_eval.
(* end hide *)
Ltac rewriteStepF := autorewrite with StepF_rew.
Lemma StepFfoldPropForall_Ap :
forall X (f:StepF (X --> iffSetoid)) (x:StepF X), (forall y, StepFfoldProp (f <@> constStepF y)) -> StepFfoldProp (f <@> x).
Proof.
intros X f x H.
revert f H.
induction x.
intros f H.
apply H.
intros f H.
rewrite <- (glueSplit f o).
rewrite ApGlueGlue.
split.
apply IHx1.
intros y.
assert (H0:=H y).
rewrite <- (glueSplit f o) in H0.
rewrite ApGlue in H0.
destruct H0 as [H0 _].
assumption.
apply IHx2.
intros y.
assert (H0:=H y).
rewrite <- (glueSplit f o) in H0.
rewrite ApGlue in H0.
destruct H0 as [_ H0].
assumption.
Qed.
(** A common case that we will encounter is that a predicate holds for
all step functions when it is define via map (or map2 or map3) and the
underlying function holds for all X. *)
Lemma StepFfoldPropForall_Map :
forall X (f:X --> iffSetoid) (x:StepF X), (forall a, f a) -> StepFfoldProp (f ^@> x).
Proof.
intros X f x H.
apply StepFfoldPropForall_Ap.
assumption.
Qed.
Lemma StepFfoldPropForall_Map2 :
forall X Y (f:X --> Y --> iffSetoid) x y, (forall a b, f a b) -> StepFfoldProp (f ^@> x <@> y).
Proof.
intros X Y f x y H.
apply StepFfoldPropForall_Ap.
intros b.
rewrite <- (Map_commutative (constStepF f) (constStepF b)).
rewriteStepF.
apply StepFfoldPropForall_Map.
intros a.
apply: H.
Qed.
Lemma StepFfoldPropForall_Map3 :
forall X Y Z (f:X --> Y --> Z --> iffSetoid) x y z, (forall a b c, f a b c) -> StepFfoldProp (f ^@> x <@> y <@> z).
Proof.
intros X Y Z f x y z H.
apply StepFfoldPropForall_Ap.
intros c.
rewrite <- (Map_commutative ((constStepF f) <@> x) (constStepF c)).
rewrite <- Map_composition.
rewriteStepF.
rewrite <- (Map_commutative (constStepF (compose flip f)) (constStepF c)).
rewriteStepF.
apply StepFfoldPropForall_Map2.
intros a b.
apply: H.
Qed.
(** The implication operation can be lifted to work on characteristic
functions *)
Definition imp0:Prop->iffSetoid-->iffSetoid.
Proof.
intro A.
exists (fun B:Prop=>(A->B)).
simpl. unfold canonical_names.equiv. intuition.
Defined.
Definition imp:iffSetoid-->iffSetoid-->iffSetoid.
Proof.
exists imp0.
simpl. unfold canonical_names.equiv, extEq. intuition.
simpl. intuition.
Defined.
Definition StepF_imp (f g:StepF iffSetoid):Prop:=
(StepFfoldProp (imp ^@> f <@> g)).
Lemma StepFfoldPropglue_rew:(forall o x y, (StepFfoldProp (glue o x y))<->((StepFfoldProp x)/\StepFfoldProp y)).
Proof.
auto with *.
Qed.
(* begin hide *)
Hint Rewrite StepFfoldPropglue_rew:StepF_rew.
(* end hide *)
Lemma StepF_imp_imp:forall x y:(StepF iffSetoid),
(StepF_imp x y) ->
((StepFfoldProp x)->(StepFfoldProp y)).
Proof.
induction x. induction y.
auto with *.
unfold StepF_imp. unfold StepFfoldProp;simpl;intuition.
intros y.
unfold StepF_imp, Map2.
rewriteStepF.
intros.
rewrite <- (StepFfoldPropglue y o).
rewriteStepF.
intuition.
Qed.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__SDFBBP_BEHAVIORAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_notify_pg/sky130_fd_sc_hs__u_dfb_setdom_notify_pg.v"
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`celldefine
module sky130_fd_sc_hs__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_dfb_setdom_notify_pg u_dfb_setdom_notify_pg0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBP_BEHAVIORAL_V |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module nfa_accept_sample (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address,
nfa_initials_buckets_datain,
nfa_initials_buckets_dataout,
nfa_initials_buckets_size,
nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address,
nfa_finals_buckets_datain,
nfa_finals_buckets_dataout,
nfa_finals_buckets_size,
nfa_forward_buckets_req_din,
nfa_forward_buckets_req_full_n,
nfa_forward_buckets_req_write,
nfa_forward_buckets_rsp_empty_n,
nfa_forward_buckets_rsp_read,
nfa_forward_buckets_address,
nfa_forward_buckets_datain,
nfa_forward_buckets_dataout,
nfa_forward_buckets_size,
nfa_symbols,
sample_req_din,
sample_req_full_n,
sample_req_write,
sample_rsp_empty_n,
sample_rsp_read,
sample_address,
sample_datain,
sample_dataout,
sample_size,
empty,
length_r,
ap_return
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output nfa_initials_buckets_req_din;
input nfa_initials_buckets_req_full_n;
output nfa_initials_buckets_req_write;
input nfa_initials_buckets_rsp_empty_n;
output nfa_initials_buckets_rsp_read;
output [31:0] nfa_initials_buckets_address;
input [31:0] nfa_initials_buckets_datain;
output [31:0] nfa_initials_buckets_dataout;
output [31:0] nfa_initials_buckets_size;
output nfa_finals_buckets_req_din;
input nfa_finals_buckets_req_full_n;
output nfa_finals_buckets_req_write;
input nfa_finals_buckets_rsp_empty_n;
output nfa_finals_buckets_rsp_read;
output [31:0] nfa_finals_buckets_address;
input [31:0] nfa_finals_buckets_datain;
output [31:0] nfa_finals_buckets_dataout;
output [31:0] nfa_finals_buckets_size;
output nfa_forward_buckets_req_din;
input nfa_forward_buckets_req_full_n;
output nfa_forward_buckets_req_write;
input nfa_forward_buckets_rsp_empty_n;
output nfa_forward_buckets_rsp_read;
output [31:0] nfa_forward_buckets_address;
input [31:0] nfa_forward_buckets_datain;
output [31:0] nfa_forward_buckets_dataout;
output [31:0] nfa_forward_buckets_size;
input [7:0] nfa_symbols;
output sample_req_din;
input sample_req_full_n;
output sample_req_write;
input sample_rsp_empty_n;
output sample_rsp_read;
output [31:0] sample_address;
input [7:0] sample_datain;
output [7:0] sample_dataout;
output [31:0] sample_size;
input [31:0] empty;
input [15:0] length_r;
output [0:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg nfa_forward_buckets_req_write;
reg nfa_forward_buckets_rsp_read;
reg[31:0] nfa_forward_buckets_address;
reg sample_req_write;
reg sample_rsp_read;
reg[0:0] ap_return;
reg [5:0] ap_CS_fsm = 6'b000000;
reg [31:0] reg_374;
reg [31:0] current_buckets_0_reg_577;
reg [31:0] current_buckets_1_reg_582;
wire [0:0] tmp_s_fu_397_p2;
reg [0:0] tmp_s_reg_597;
wire [15:0] grp_fu_402_p2;
reg [15:0] i_1_reg_601;
reg [31:0] sample_addr_1_reg_606;
wire [0:0] tmp_17_i_fu_420_p2;
reg [0:0] tmp_17_i_reg_612;
wire [31:0] grp_fu_414_p2;
reg [31:0] p_rec_reg_616;
reg [7:0] sym_reg_621;
wire [0:0] tmp_17_1_i_fu_426_p2;
reg [0:0] tmp_17_1_i_reg_626;
wire [4:0] grp_p_bsf32_hw_fu_368_ap_return;
reg [4:0] r_bit_reg_630;
wire [1:0] agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1;
wire [7:0] j_bucket_index1_ph_cast_fu_436_p1;
wire [7:0] j_bit1_ph_cast_fu_440_p1;
wire [13:0] tmp_7_i_cast_fu_444_p1;
reg [13:0] tmp_7_i_cast_reg_650;
wire [0:0] j_end_phi_fu_312_p4;
wire [5:0] grp_fu_463_p2;
reg [5:0] state_reg_665;
wire [13:0] grp_fu_476_p2;
reg [13:0] tmp_6_i_reg_680;
reg [7:0] j_bit_reg_685;
reg [7:0] j_bucket_index_reg_690;
reg [31:0] j_bucket_reg_695;
reg [0:0] p_s_reg_700;
wire [13:0] grp_fu_482_p2;
reg [13:0] offset_i_reg_705;
wire [31:0] next_buckets_0_1_fu_538_p2;
reg [31:0] next_buckets_0_1_reg_721;
wire [31:0] next_buckets_1_1_fu_544_p2;
reg [31:0] tmp_buckets_0_reg_731;
reg [31:0] tmp_buckets_1_reg_736;
wire [31:0] current_buckets_0_1_fu_558_p2;
reg [31:0] current_buckets_0_1_reg_741;
wire [31:0] current_buckets_1_1_fu_563_p2;
reg [31:0] current_buckets_1_1_reg_746;
wire [31:0] tmp_1_fu_568_p2;
reg [31:0] tmp_1_reg_751;
wire [0:0] tmp_2_fu_572_p2;
reg [0:0] tmp_2_reg_756;
wire [31:0] grp_bitset_next_fu_344_p_read;
wire [7:0] grp_bitset_next_fu_344_r_bit;
wire [7:0] grp_bitset_next_fu_344_r_bucket_index;
wire [31:0] grp_bitset_next_fu_344_r_bucket;
wire [7:0] grp_bitset_next_fu_344_ap_return_0;
wire [7:0] grp_bitset_next_fu_344_ap_return_1;
wire [31:0] grp_bitset_next_fu_344_ap_return_2;
wire [0:0] grp_bitset_next_fu_344_ap_return_3;
reg grp_bitset_next_fu_344_ap_ce;
reg grp_nfa_get_initials_fu_356_ap_start;
wire grp_nfa_get_initials_fu_356_ap_done;
wire grp_nfa_get_initials_fu_356_ap_idle;
wire grp_nfa_get_initials_fu_356_ap_ready;
wire grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din;
wire grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n;
wire grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write;
wire grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n;
wire grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read;
wire [31:0] grp_nfa_get_initials_fu_356_nfa_initials_buckets_address;
wire [31:0] grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain;
wire [31:0] grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout;
wire [31:0] grp_nfa_get_initials_fu_356_nfa_initials_buckets_size;
wire grp_nfa_get_initials_fu_356_ap_ce;
wire [31:0] grp_nfa_get_initials_fu_356_ap_return_0;
wire [31:0] grp_nfa_get_initials_fu_356_ap_return_1;
wire grp_nfa_get_finals_fu_362_ap_start;
wire grp_nfa_get_finals_fu_362_ap_done;
wire grp_nfa_get_finals_fu_362_ap_idle;
wire grp_nfa_get_finals_fu_362_ap_ready;
wire grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din;
wire grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n;
wire grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write;
wire grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n;
wire grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read;
wire [31:0] grp_nfa_get_finals_fu_362_nfa_finals_buckets_address;
wire [31:0] grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain;
wire [31:0] grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout;
wire [31:0] grp_nfa_get_finals_fu_362_nfa_finals_buckets_size;
wire grp_nfa_get_finals_fu_362_ap_ce;
wire [31:0] grp_nfa_get_finals_fu_362_ap_return_0;
wire [31:0] grp_nfa_get_finals_fu_362_ap_return_1;
wire [31:0] grp_p_bsf32_hw_fu_368_bus_r;
reg grp_p_bsf32_hw_fu_368_ap_ce;
reg [15:0] i_reg_134;
wire [0:0] any_phi_fu_324_p4;
reg [31:0] p_01_rec_reg_146;
reg [31:0] next_buckets_1_reg_158;
reg [31:0] next_buckets_0_reg_168;
reg [31:0] bus_assign_reg_178;
reg [0:0] agg_result_bucket_index_0_lcssa4_i_reg_190;
reg [31:0] j_bucket1_ph_reg_203;
reg [1:0] j_bucket_index1_ph_reg_216;
reg [4:0] j_bit1_ph_reg_227;
reg [0:0] j_end_ph_reg_238;
reg [31:0] tmp_buckets_1_3_reg_252;
reg [31:0] tmp_buckets_0_3_reg_265;
reg [31:0] j_bucket1_reg_278;
reg [7:0] j_bucket_index1_reg_289;
reg [7:0] j_bit1_reg_299;
reg [0:0] j_end_reg_309;
reg [0:0] any_reg_319;
reg [0:0] p_0_reg_332;
reg [5:0] ap_NS_fsm;
reg grp_nfa_get_finals_fu_362_ap_start_ap_start_reg = 1'b0;
wire [31:0] grp_fu_392_p2;
wire [31:0] tmp_4_i_cast_fu_509_p1;
wire [31:0] tmp_8_i_cast_fu_527_p1;
wire [31:0] grp_fu_392_p0;
wire [31:0] grp_fu_392_p1;
wire [15:0] grp_fu_402_p0;
wire [15:0] grp_fu_402_p1;
wire [31:0] grp_fu_414_p0;
wire [31:0] grp_fu_414_p1;
wire [0:0] tmp_5_fu_447_p1;
wire [5:0] grp_fu_463_p0;
wire [5:0] grp_fu_463_p1;
wire [7:0] grp_fu_476_p0;
wire [5:0] grp_fu_476_p1;
wire [13:0] grp_fu_482_p0;
wire [13:0] grp_fu_482_p1;
wire [14:0] tmp_4_i_fu_502_p3;
wire [14:0] tmp_8_i_fu_520_p3;
wire grp_fu_392_ce;
wire grp_fu_402_ce;
reg grp_fu_414_ce;
wire grp_fu_463_ce;
wire grp_fu_476_ce;
wire grp_fu_482_ce;
reg [0:0] ap_return_preg = 1'b0;
wire [13:0] grp_fu_476_p00;
wire [13:0] grp_fu_476_p10;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 6'b000000;
parameter ap_ST_st2_fsm_1 = 6'b1;
parameter ap_ST_st3_fsm_2 = 6'b10;
parameter ap_ST_st4_fsm_3 = 6'b11;
parameter ap_ST_st5_fsm_4 = 6'b100;
parameter ap_ST_st6_fsm_5 = 6'b101;
parameter ap_ST_st7_fsm_6 = 6'b110;
parameter ap_ST_st8_fsm_7 = 6'b111;
parameter ap_ST_st9_fsm_8 = 6'b1000;
parameter ap_ST_st10_fsm_9 = 6'b1001;
parameter ap_ST_st11_fsm_10 = 6'b1010;
parameter ap_ST_st12_fsm_11 = 6'b1011;
parameter ap_ST_st13_fsm_12 = 6'b1100;
parameter ap_ST_st14_fsm_13 = 6'b1101;
parameter ap_ST_st15_fsm_14 = 6'b1110;
parameter ap_ST_st16_fsm_15 = 6'b1111;
parameter ap_ST_st17_fsm_16 = 6'b10000;
parameter ap_ST_st18_fsm_17 = 6'b10001;
parameter ap_ST_st19_fsm_18 = 6'b10010;
parameter ap_ST_st20_fsm_19 = 6'b10011;
parameter ap_ST_st21_fsm_20 = 6'b10100;
parameter ap_ST_st22_fsm_21 = 6'b10101;
parameter ap_ST_st23_fsm_22 = 6'b10110;
parameter ap_ST_st24_fsm_23 = 6'b10111;
parameter ap_ST_st25_fsm_24 = 6'b11000;
parameter ap_ST_st26_fsm_25 = 6'b11001;
parameter ap_ST_st27_fsm_26 = 6'b11010;
parameter ap_ST_st28_fsm_27 = 6'b11011;
parameter ap_ST_st29_fsm_28 = 6'b11100;
parameter ap_ST_st30_fsm_29 = 6'b11101;
parameter ap_ST_st31_fsm_30 = 6'b11110;
parameter ap_ST_st32_fsm_31 = 6'b11111;
parameter ap_ST_st33_fsm_32 = 6'b100000;
parameter ap_ST_st34_fsm_33 = 6'b100001;
parameter ap_ST_st35_fsm_34 = 6'b100010;
parameter ap_ST_st36_fsm_35 = 6'b100011;
parameter ap_ST_st37_fsm_36 = 6'b100100;
parameter ap_ST_st38_fsm_37 = 6'b100101;
parameter ap_ST_st39_fsm_38 = 6'b100110;
parameter ap_ST_st40_fsm_39 = 6'b100111;
parameter ap_ST_st41_fsm_40 = 6'b101000;
parameter ap_ST_st42_fsm_41 = 6'b101001;
parameter ap_ST_st43_fsm_42 = 6'b101010;
parameter ap_ST_st44_fsm_43 = 6'b101011;
parameter ap_ST_st45_fsm_44 = 6'b101100;
parameter ap_ST_st46_fsm_45 = 6'b101101;
parameter ap_ST_st47_fsm_46 = 6'b101110;
parameter ap_ST_st48_fsm_47 = 6'b101111;
parameter ap_ST_st49_fsm_48 = 6'b110000;
parameter ap_ST_st50_fsm_49 = 6'b110001;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv16_0 = 16'b0000000000000000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv2_2 = 2'b10;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv16_1 = 16'b1;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_true = 1'b1;
bitset_next grp_bitset_next_fu_344(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p_read( grp_bitset_next_fu_344_p_read ),
.r_bit( grp_bitset_next_fu_344_r_bit ),
.r_bucket_index( grp_bitset_next_fu_344_r_bucket_index ),
.r_bucket( grp_bitset_next_fu_344_r_bucket ),
.ap_return_0( grp_bitset_next_fu_344_ap_return_0 ),
.ap_return_1( grp_bitset_next_fu_344_ap_return_1 ),
.ap_return_2( grp_bitset_next_fu_344_ap_return_2 ),
.ap_return_3( grp_bitset_next_fu_344_ap_return_3 ),
.ap_ce( grp_bitset_next_fu_344_ap_ce )
);
nfa_get_initials grp_nfa_get_initials_fu_356(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_nfa_get_initials_fu_356_ap_start ),
.ap_done( grp_nfa_get_initials_fu_356_ap_done ),
.ap_idle( grp_nfa_get_initials_fu_356_ap_idle ),
.ap_ready( grp_nfa_get_initials_fu_356_ap_ready ),
.nfa_initials_buckets_req_din( grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din ),
.nfa_initials_buckets_req_full_n( grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n ),
.nfa_initials_buckets_req_write( grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write ),
.nfa_initials_buckets_rsp_empty_n( grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n ),
.nfa_initials_buckets_rsp_read( grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read ),
.nfa_initials_buckets_address( grp_nfa_get_initials_fu_356_nfa_initials_buckets_address ),
.nfa_initials_buckets_datain( grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain ),
.nfa_initials_buckets_dataout( grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout ),
.nfa_initials_buckets_size( grp_nfa_get_initials_fu_356_nfa_initials_buckets_size ),
.ap_ce( grp_nfa_get_initials_fu_356_ap_ce ),
.ap_return_0( grp_nfa_get_initials_fu_356_ap_return_0 ),
.ap_return_1( grp_nfa_get_initials_fu_356_ap_return_1 )
);
nfa_get_finals grp_nfa_get_finals_fu_362(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_nfa_get_finals_fu_362_ap_start ),
.ap_done( grp_nfa_get_finals_fu_362_ap_done ),
.ap_idle( grp_nfa_get_finals_fu_362_ap_idle ),
.ap_ready( grp_nfa_get_finals_fu_362_ap_ready ),
.nfa_finals_buckets_req_din( grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din ),
.nfa_finals_buckets_req_full_n( grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n ),
.nfa_finals_buckets_req_write( grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write ),
.nfa_finals_buckets_rsp_empty_n( grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n ),
.nfa_finals_buckets_rsp_read( grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read ),
.nfa_finals_buckets_address( grp_nfa_get_finals_fu_362_nfa_finals_buckets_address ),
.nfa_finals_buckets_datain( grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain ),
.nfa_finals_buckets_dataout( grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout ),
.nfa_finals_buckets_size( grp_nfa_get_finals_fu_362_nfa_finals_buckets_size ),
.ap_ce( grp_nfa_get_finals_fu_362_ap_ce ),
.ap_return_0( grp_nfa_get_finals_fu_362_ap_return_0 ),
.ap_return_1( grp_nfa_get_finals_fu_362_ap_return_1 )
);
p_bsf32_hw grp_p_bsf32_hw_fu_368(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.bus_r( grp_p_bsf32_hw_fu_368_bus_r ),
.ap_return( grp_p_bsf32_hw_fu_368_ap_return ),
.ap_ce( grp_p_bsf32_hw_fu_368_ap_ce )
);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 #(
.ID( 17 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U17(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_392_p0 ),
.din1( grp_fu_392_p1 ),
.ce( grp_fu_392_ce ),
.dout( grp_fu_392_p2 )
);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 #(
.ID( 18 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 16 ),
.din1_WIDTH( 16 ),
.dout_WIDTH( 16 ))
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U18(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_402_p0 ),
.din1( grp_fu_402_p1 ),
.ce( grp_fu_402_ce ),
.dout( grp_fu_402_p2 )
);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 #(
.ID( 19 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U19(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_414_p0 ),
.din1( grp_fu_414_p1 ),
.ce( grp_fu_414_ce ),
.dout( grp_fu_414_p2 )
);
nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 #(
.ID( 20 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 6 ),
.din1_WIDTH( 6 ),
.dout_WIDTH( 6 ))
nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_U20(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_463_p0 ),
.din1( grp_fu_463_p1 ),
.ce( grp_fu_463_ce ),
.dout( grp_fu_463_p2 )
);
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9 #(
.ID( 21 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 6 ),
.dout_WIDTH( 14 ))
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_U21(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_476_p0 ),
.din1( grp_fu_476_p1 ),
.ce( grp_fu_476_ce ),
.dout( grp_fu_476_p2 )
);
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 #(
.ID( 22 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 14 ),
.din1_WIDTH( 14 ),
.dout_WIDTH( 14 ))
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_U22(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_482_p0 ),
.din1( grp_fu_482_p1 ),
.ce( grp_fu_482_ce ),
.dout( grp_fu_482_p2 )
);
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_return_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_preg
if (ap_rst == 1'b1) begin
ap_return_preg <= ap_const_lv1_0;
end else begin
if ((ap_ST_st50_fsm_49 == ap_CS_fsm)) begin
ap_return_preg <= p_0_reg_332;
end
end
end
/// grp_nfa_get_finals_fu_362_ap_start_ap_start_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_grp_nfa_get_finals_fu_362_ap_start_ap_start_reg
if (ap_rst == 1'b1) begin
grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_0;
end else begin
if (((ap_ST_st12_fsm_11 == ap_NS_fsm) & (ap_ST_st11_fsm_10 == ap_CS_fsm) & (tmp_s_reg_597 == ap_const_lv1_0))) begin
grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_1;
end else if ((ap_const_logic_1 == grp_nfa_get_finals_fu_362_ap_ready)) begin
grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st20_fsm_19 == ap_CS_fsm) & (tmp_17_1_i_reg_626 == ap_const_lv1_0))) begin
agg_result_bucket_index_0_lcssa4_i_reg_190 <= ap_const_lv1_1;
end else if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0) & (tmp_17_i_reg_612 == ap_const_lv1_0))) begin
agg_result_bucket_index_0_lcssa4_i_reg_190 <= ap_const_lv1_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
any_reg_319 <= ap_const_lv1_0;
end else if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
any_reg_319 <= ap_const_lv1_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st20_fsm_19 == ap_CS_fsm) & (tmp_17_1_i_reg_626 == ap_const_lv1_0))) begin
bus_assign_reg_178 <= next_buckets_1_reg_158;
end else if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0) & (tmp_17_i_reg_612 == ap_const_lv1_0))) begin
bus_assign_reg_178 <= next_buckets_0_reg_168;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st25_fsm_24 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & ~(ap_const_lv1_0 == any_phi_fu_324_p4))) begin
i_reg_134 <= i_1_reg_601;
end else if ((ap_ST_st4_fsm_3 == ap_CS_fsm)) begin
i_reg_134 <= ap_const_lv16_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
j_bit1_reg_299 <= j_bit1_ph_cast_fu_440_p1;
end else if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
j_bit1_reg_299 <= j_bit_reg_685;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
j_bucket1_ph_reg_203 <= bus_assign_reg_178;
end else if (((ap_ST_st20_fsm_19 == ap_CS_fsm) & ~(tmp_17_1_i_reg_626 == ap_const_lv1_0))) begin
j_bucket1_ph_reg_203 <= ap_const_lv32_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
j_bucket1_reg_278 <= j_bucket1_ph_reg_203;
end else if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
j_bucket1_reg_278 <= j_bucket_reg_695;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
j_bucket_index1_ph_reg_216 <= agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1;
end else if (((ap_ST_st20_fsm_19 == ap_CS_fsm) & ~(tmp_17_1_i_reg_626 == ap_const_lv1_0))) begin
j_bucket_index1_ph_reg_216 <= ap_const_lv2_2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
j_bucket_index1_reg_289 <= j_bucket_index1_ph_cast_fu_436_p1;
end else if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
j_bucket_index1_reg_289 <= j_bucket_index_reg_690;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
j_end_ph_reg_238 <= ap_const_lv1_0;
end else if (((ap_ST_st20_fsm_19 == ap_CS_fsm) & ~(tmp_17_1_i_reg_626 == ap_const_lv1_0))) begin
j_end_ph_reg_238 <= ap_const_lv1_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
j_end_reg_309 <= j_end_ph_reg_238;
end else if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
j_end_reg_309 <= p_s_reg_700;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st25_fsm_24 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & ~(ap_const_lv1_0 == any_phi_fu_324_p4))) begin
next_buckets_0_reg_168 <= tmp_buckets_0_3_reg_265;
end else if ((ap_ST_st4_fsm_3 == ap_CS_fsm)) begin
next_buckets_0_reg_168 <= current_buckets_0_reg_577;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st25_fsm_24 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & ~(ap_const_lv1_0 == any_phi_fu_324_p4))) begin
next_buckets_1_reg_158 <= tmp_buckets_1_3_reg_252;
end else if ((ap_ST_st4_fsm_3 == ap_CS_fsm)) begin
next_buckets_1_reg_158 <= current_buckets_1_reg_582;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st25_fsm_24 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & ~(ap_const_lv1_0 == any_phi_fu_324_p4))) begin
p_01_rec_reg_146 <= p_rec_reg_616;
end else if ((ap_ST_st4_fsm_3 == ap_CS_fsm)) begin
p_01_rec_reg_146 <= ap_const_lv32_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st25_fsm_24 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & (ap_const_lv1_0 == any_phi_fu_324_p4))) begin
p_0_reg_332 <= ap_const_lv1_0;
end else if ((ap_ST_st49_fsm_48 == ap_CS_fsm)) begin
p_0_reg_332 <= tmp_2_reg_756;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
tmp_buckets_0_3_reg_265 <= ap_const_lv32_0;
end else if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
tmp_buckets_0_3_reg_265 <= next_buckets_0_1_reg_721;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
tmp_buckets_1_3_reg_252 <= ap_const_lv32_0;
end else if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
tmp_buckets_1_3_reg_252 <= next_buckets_1_1_fu_544_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st46_fsm_45 == ap_CS_fsm)) begin
current_buckets_0_1_reg_741 <= current_buckets_0_1_fu_558_p2;
current_buckets_1_1_reg_746 <= current_buckets_1_1_fu_563_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st3_fsm_2 == ap_CS_fsm)) begin
current_buckets_0_reg_577 <= grp_nfa_get_initials_fu_356_ap_return_0;
current_buckets_1_reg_582 <= grp_nfa_get_initials_fu_356_ap_return_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st8_fsm_7 == ap_CS_fsm)) begin
i_1_reg_601 <= grp_fu_402_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
j_bit1_ph_reg_227 <= r_bit_reg_630;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st36_fsm_35 == ap_CS_fsm)) begin
j_bit_reg_685 <= grp_bitset_next_fu_344_ap_return_0;
j_bucket_index_reg_690 <= grp_bitset_next_fu_344_ap_return_1;
j_bucket_reg_695 <= grp_bitset_next_fu_344_ap_return_2;
p_s_reg_700 <= grp_bitset_next_fu_344_ap_return_3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0) & (ap_ST_st42_fsm_41 == ap_CS_fsm))) begin
next_buckets_0_1_reg_721 <= next_buckets_0_1_fu_538_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st39_fsm_38 == ap_CS_fsm)) begin
offset_i_reg_705 <= grp_fu_482_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0))) begin
p_rec_reg_616 <= grp_fu_414_p2;
sym_reg_621 <= sample_datain;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st22_fsm_21 == ap_CS_fsm)) begin
r_bit_reg_630 <= grp_p_bsf32_hw_fu_368_ap_return;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((ap_ST_st41_fsm_40 == ap_CS_fsm) & ~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) | (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0) & (ap_ST_st42_fsm_41 == ap_CS_fsm)))) begin
reg_374 <= nfa_forward_buckets_datain;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st12_fsm_11 == ap_CS_fsm)) begin
sample_addr_1_reg_606 <= grp_fu_392_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st26_fsm_25 == ap_CS_fsm)) begin
state_reg_665 <= grp_fu_463_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0) & ~(tmp_17_i_reg_612 == ap_const_lv1_0))) begin
tmp_17_1_i_reg_626 <= tmp_17_1_i_fu_426_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
tmp_17_i_reg_612 <= tmp_17_i_fu_420_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st47_fsm_46 == ap_CS_fsm)) begin
tmp_1_reg_751 <= tmp_1_fu_568_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st48_fsm_47 == ap_CS_fsm)) begin
tmp_2_reg_756 <= tmp_2_fu_572_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st35_fsm_34 == ap_CS_fsm)) begin
tmp_6_i_reg_680 <= grp_fu_476_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
tmp_7_i_cast_reg_650[0] <= tmp_7_i_cast_fu_444_p1[0];
tmp_7_i_cast_reg_650[1] <= tmp_7_i_cast_fu_444_p1[1];
tmp_7_i_cast_reg_650[2] <= tmp_7_i_cast_fu_444_p1[2];
tmp_7_i_cast_reg_650[3] <= tmp_7_i_cast_fu_444_p1[3];
tmp_7_i_cast_reg_650[4] <= tmp_7_i_cast_fu_444_p1[4];
tmp_7_i_cast_reg_650[5] <= tmp_7_i_cast_fu_444_p1[5];
tmp_7_i_cast_reg_650[6] <= tmp_7_i_cast_fu_444_p1[6];
tmp_7_i_cast_reg_650[7] <= tmp_7_i_cast_fu_444_p1[7];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st45_fsm_44 == ap_CS_fsm)) begin
tmp_buckets_0_reg_731 <= grp_nfa_get_finals_fu_362_ap_return_0;
tmp_buckets_1_reg_736 <= grp_nfa_get_finals_fu_362_ap_return_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st5_fsm_4 == ap_CS_fsm)) begin
tmp_s_reg_597 <= tmp_s_fu_397_p2;
end
end
/// ap_done assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if (((~(ap_const_logic_1 == ap_start) & (ap_ST_st1_fsm_0 == ap_CS_fsm)) | (ap_ST_st50_fsm_49 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st1_fsm_0 == ap_CS_fsm))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st50_fsm_49 == ap_CS_fsm)) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_return assign process. ///
always @ (ap_CS_fsm or p_0_reg_332 or ap_return_preg)
begin
if ((ap_ST_st50_fsm_49 == ap_CS_fsm)) begin
ap_return = p_0_reg_332;
end else begin
ap_return = ap_return_preg;
end
end
/// grp_bitset_next_fu_344_ap_ce assign process. ///
always @ (ap_CS_fsm or j_end_phi_fu_312_p4)
begin
if ((((ap_ST_st25_fsm_24 == ap_CS_fsm) & (ap_const_lv1_0 == j_end_phi_fu_312_p4)) | (ap_ST_st26_fsm_25 == ap_CS_fsm) | (ap_ST_st27_fsm_26 == ap_CS_fsm) | (ap_ST_st35_fsm_34 == ap_CS_fsm) | (ap_ST_st36_fsm_35 == ap_CS_fsm) | (ap_ST_st28_fsm_27 == ap_CS_fsm) | (ap_ST_st29_fsm_28 == ap_CS_fsm) | (ap_ST_st30_fsm_29 == ap_CS_fsm) | (ap_ST_st31_fsm_30 == ap_CS_fsm) | (ap_ST_st32_fsm_31 == ap_CS_fsm) | (ap_ST_st33_fsm_32 == ap_CS_fsm) | (ap_ST_st34_fsm_33 == ap_CS_fsm))) begin
grp_bitset_next_fu_344_ap_ce = ap_const_logic_1;
end else begin
grp_bitset_next_fu_344_ap_ce = ap_const_logic_0;
end
end
/// grp_fu_414_ce assign process. ///
always @ (ap_CS_fsm or sample_rsp_empty_n or tmp_s_reg_597)
begin
if (((ap_ST_st18_fsm_17 == ap_CS_fsm) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0)) | ((ap_ST_st12_fsm_11 == ap_CS_fsm) & ~(tmp_s_reg_597 == ap_const_lv1_0)) | (ap_ST_st13_fsm_12 == ap_CS_fsm) | (ap_ST_st14_fsm_13 == ap_CS_fsm) | (ap_ST_st15_fsm_14 == ap_CS_fsm) | (ap_ST_st16_fsm_15 == ap_CS_fsm) | (ap_ST_st17_fsm_16 == ap_CS_fsm))) begin
grp_fu_414_ce = ap_const_logic_1;
end else begin
grp_fu_414_ce = ap_const_logic_0;
end
end
/// grp_nfa_get_initials_fu_356_ap_start assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if (((ap_ST_st1_fsm_0 == ap_CS_fsm) & ~(ap_start == ap_const_logic_0))) begin
grp_nfa_get_initials_fu_356_ap_start = ap_const_logic_1;
end else begin
grp_nfa_get_initials_fu_356_ap_start = ap_const_logic_0;
end
end
/// grp_p_bsf32_hw_fu_368_ap_ce assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st22_fsm_21 == ap_CS_fsm) | (ap_ST_st21_fsm_20 == ap_CS_fsm))) begin
grp_p_bsf32_hw_fu_368_ap_ce = ap_const_logic_1;
end else begin
grp_p_bsf32_hw_fu_368_ap_ce = ap_const_logic_0;
end
end
/// nfa_forward_buckets_address assign process. ///
always @ (ap_CS_fsm or nfa_forward_buckets_rsp_empty_n or tmp_4_i_cast_fu_509_p1 or tmp_8_i_cast_fu_527_p1)
begin
if (((ap_ST_st41_fsm_40 == ap_CS_fsm) & ~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0))) begin
nfa_forward_buckets_address = tmp_8_i_cast_fu_527_p1;
end else if ((ap_ST_st40_fsm_39 == ap_CS_fsm)) begin
nfa_forward_buckets_address = tmp_4_i_cast_fu_509_p1;
end else begin
nfa_forward_buckets_address = 'bx;
end
end
/// nfa_forward_buckets_req_write assign process. ///
always @ (ap_CS_fsm or nfa_forward_buckets_rsp_empty_n)
begin
if ((((ap_ST_st41_fsm_40 == ap_CS_fsm) & ~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) | (ap_ST_st40_fsm_39 == ap_CS_fsm))) begin
nfa_forward_buckets_req_write = ap_const_logic_1;
end else begin
nfa_forward_buckets_req_write = ap_const_logic_0;
end
end
/// nfa_forward_buckets_rsp_read assign process. ///
always @ (ap_CS_fsm or nfa_forward_buckets_rsp_empty_n)
begin
if ((((ap_ST_st41_fsm_40 == ap_CS_fsm) & ~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) | (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0) & (ap_ST_st42_fsm_41 == ap_CS_fsm)))) begin
nfa_forward_buckets_rsp_read = ap_const_logic_1;
end else begin
nfa_forward_buckets_rsp_read = ap_const_logic_0;
end
end
/// sample_req_write assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sample_req_write = ap_const_logic_1;
end else begin
sample_req_write = ap_const_logic_0;
end
end
/// sample_rsp_read assign process. ///
always @ (ap_CS_fsm or sample_rsp_empty_n)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0))) begin
sample_rsp_read = ap_const_logic_1;
end else begin
sample_rsp_read = ap_const_logic_0;
end
end
always @ (ap_start or ap_CS_fsm or nfa_forward_buckets_rsp_empty_n or sample_rsp_empty_n or tmp_s_reg_597 or tmp_17_i_reg_612 or tmp_17_1_i_reg_626 or j_end_phi_fu_312_p4 or any_phi_fu_324_p4)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
if (~(ap_start == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
ap_ST_st2_fsm_1 :
ap_NS_fsm = ap_ST_st3_fsm_2;
ap_ST_st3_fsm_2 :
ap_NS_fsm = ap_ST_st4_fsm_3;
ap_ST_st4_fsm_3 :
ap_NS_fsm = ap_ST_st5_fsm_4;
ap_ST_st5_fsm_4 :
ap_NS_fsm = ap_ST_st6_fsm_5;
ap_ST_st6_fsm_5 :
ap_NS_fsm = ap_ST_st7_fsm_6;
ap_ST_st7_fsm_6 :
ap_NS_fsm = ap_ST_st8_fsm_7;
ap_ST_st8_fsm_7 :
ap_NS_fsm = ap_ST_st9_fsm_8;
ap_ST_st9_fsm_8 :
ap_NS_fsm = ap_ST_st10_fsm_9;
ap_ST_st10_fsm_9 :
ap_NS_fsm = ap_ST_st11_fsm_10;
ap_ST_st11_fsm_10 :
ap_NS_fsm = ap_ST_st12_fsm_11;
ap_ST_st12_fsm_11 :
if ((tmp_s_reg_597 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st44_fsm_43;
end else begin
ap_NS_fsm = ap_ST_st13_fsm_12;
end
ap_ST_st13_fsm_12 :
ap_NS_fsm = ap_ST_st14_fsm_13;
ap_ST_st14_fsm_13 :
ap_NS_fsm = ap_ST_st15_fsm_14;
ap_ST_st15_fsm_14 :
ap_NS_fsm = ap_ST_st16_fsm_15;
ap_ST_st16_fsm_15 :
ap_NS_fsm = ap_ST_st17_fsm_16;
ap_ST_st17_fsm_16 :
ap_NS_fsm = ap_ST_st18_fsm_17;
ap_ST_st18_fsm_17 :
ap_NS_fsm = ap_ST_st19_fsm_18;
ap_ST_st19_fsm_18 :
if ((~(sample_rsp_empty_n == ap_const_logic_0) & (tmp_17_i_reg_612 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_st21_fsm_20;
end else if ((~(sample_rsp_empty_n == ap_const_logic_0) & ~(tmp_17_i_reg_612 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_st20_fsm_19;
end else begin
ap_NS_fsm = ap_ST_st19_fsm_18;
end
ap_ST_st20_fsm_19 :
if (~(tmp_17_1_i_reg_626 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st24_fsm_23;
end else begin
ap_NS_fsm = ap_ST_st21_fsm_20;
end
ap_ST_st21_fsm_20 :
ap_NS_fsm = ap_ST_st22_fsm_21;
ap_ST_st22_fsm_21 :
ap_NS_fsm = ap_ST_st23_fsm_22;
ap_ST_st23_fsm_22 :
ap_NS_fsm = ap_ST_st24_fsm_23;
ap_ST_st24_fsm_23 :
ap_NS_fsm = ap_ST_st25_fsm_24;
ap_ST_st25_fsm_24 :
if ((~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & ~(ap_const_lv1_0 == any_phi_fu_324_p4))) begin
ap_NS_fsm = ap_ST_st5_fsm_4;
end else if ((~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & (ap_const_lv1_0 == any_phi_fu_324_p4))) begin
ap_NS_fsm = ap_ST_st50_fsm_49;
end else begin
ap_NS_fsm = ap_ST_st26_fsm_25;
end
ap_ST_st26_fsm_25 :
ap_NS_fsm = ap_ST_st27_fsm_26;
ap_ST_st27_fsm_26 :
ap_NS_fsm = ap_ST_st28_fsm_27;
ap_ST_st28_fsm_27 :
ap_NS_fsm = ap_ST_st29_fsm_28;
ap_ST_st29_fsm_28 :
ap_NS_fsm = ap_ST_st30_fsm_29;
ap_ST_st30_fsm_29 :
ap_NS_fsm = ap_ST_st31_fsm_30;
ap_ST_st31_fsm_30 :
ap_NS_fsm = ap_ST_st32_fsm_31;
ap_ST_st32_fsm_31 :
ap_NS_fsm = ap_ST_st33_fsm_32;
ap_ST_st33_fsm_32 :
ap_NS_fsm = ap_ST_st34_fsm_33;
ap_ST_st34_fsm_33 :
ap_NS_fsm = ap_ST_st35_fsm_34;
ap_ST_st35_fsm_34 :
ap_NS_fsm = ap_ST_st36_fsm_35;
ap_ST_st36_fsm_35 :
ap_NS_fsm = ap_ST_st37_fsm_36;
ap_ST_st37_fsm_36 :
ap_NS_fsm = ap_ST_st38_fsm_37;
ap_ST_st38_fsm_37 :
ap_NS_fsm = ap_ST_st39_fsm_38;
ap_ST_st39_fsm_38 :
ap_NS_fsm = ap_ST_st40_fsm_39;
ap_ST_st40_fsm_39 :
ap_NS_fsm = ap_ST_st41_fsm_40;
ap_ST_st41_fsm_40 :
if (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st42_fsm_41;
end else begin
ap_NS_fsm = ap_ST_st41_fsm_40;
end
ap_ST_st42_fsm_41 :
if (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st43_fsm_42;
end else begin
ap_NS_fsm = ap_ST_st42_fsm_41;
end
ap_ST_st43_fsm_42 :
ap_NS_fsm = ap_ST_st25_fsm_24;
ap_ST_st44_fsm_43 :
ap_NS_fsm = ap_ST_st45_fsm_44;
ap_ST_st45_fsm_44 :
ap_NS_fsm = ap_ST_st46_fsm_45;
ap_ST_st46_fsm_45 :
ap_NS_fsm = ap_ST_st47_fsm_46;
ap_ST_st47_fsm_46 :
ap_NS_fsm = ap_ST_st48_fsm_47;
ap_ST_st48_fsm_47 :
ap_NS_fsm = ap_ST_st49_fsm_48;
ap_ST_st49_fsm_48 :
ap_NS_fsm = ap_ST_st50_fsm_49;
ap_ST_st50_fsm_49 :
ap_NS_fsm = ap_ST_st1_fsm_0;
default :
ap_NS_fsm = 'bx;
endcase
end
assign agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1 = $unsigned(agg_result_bucket_index_0_lcssa4_i_reg_190);
assign any_phi_fu_324_p4 = any_reg_319;
assign current_buckets_0_1_fu_558_p2 = (next_buckets_0_reg_168 & tmp_buckets_0_reg_731);
assign current_buckets_1_1_fu_563_p2 = (next_buckets_1_reg_158 & tmp_buckets_1_reg_736);
assign grp_bitset_next_fu_344_p_read = next_buckets_1_reg_158;
assign grp_bitset_next_fu_344_r_bit = j_bit1_reg_299;
assign grp_bitset_next_fu_344_r_bucket = j_bucket1_reg_278;
assign grp_bitset_next_fu_344_r_bucket_index = j_bucket_index1_reg_289;
assign grp_fu_392_ce = ap_const_logic_1;
assign grp_fu_392_p0 = p_01_rec_reg_146;
assign grp_fu_392_p1 = empty;
assign grp_fu_402_ce = ap_const_logic_1;
assign grp_fu_402_p0 = i_reg_134;
assign grp_fu_402_p1 = ap_const_lv16_1;
assign grp_fu_414_p0 = p_01_rec_reg_146;
assign grp_fu_414_p1 = ap_const_lv32_1;
assign grp_fu_463_ce = ap_const_logic_1;
assign grp_fu_463_p0 = {{tmp_5_fu_447_p1}, {ap_const_lv5_0}};
assign grp_fu_463_p1 = j_bit1_reg_299[5:0];
assign grp_fu_476_ce = ap_const_logic_1;
assign grp_fu_476_p0 = grp_fu_476_p00;
assign grp_fu_476_p00 = $unsigned(nfa_symbols);
assign grp_fu_476_p1 = grp_fu_476_p10;
assign grp_fu_476_p10 = $unsigned(state_reg_665);
assign grp_fu_482_ce = ap_const_logic_1;
assign grp_fu_482_p0 = tmp_6_i_reg_680;
assign grp_fu_482_p1 = tmp_7_i_cast_reg_650;
assign grp_nfa_get_finals_fu_362_ap_ce = ap_const_logic_1;
assign grp_nfa_get_finals_fu_362_ap_start = grp_nfa_get_finals_fu_362_ap_start_ap_start_reg;
assign grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain = nfa_finals_buckets_datain;
assign grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n = nfa_finals_buckets_req_full_n;
assign grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n = nfa_finals_buckets_rsp_empty_n;
assign grp_nfa_get_initials_fu_356_ap_ce = ap_const_logic_1;
assign grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain = nfa_initials_buckets_datain;
assign grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n = nfa_initials_buckets_req_full_n;
assign grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n = nfa_initials_buckets_rsp_empty_n;
assign grp_p_bsf32_hw_fu_368_bus_r = bus_assign_reg_178;
assign j_bit1_ph_cast_fu_440_p1 = $unsigned(j_bit1_ph_reg_227);
assign j_bucket_index1_ph_cast_fu_436_p1 = $unsigned(j_bucket_index1_ph_reg_216);
assign j_end_phi_fu_312_p4 = j_end_reg_309;
assign next_buckets_0_1_fu_538_p2 = (tmp_buckets_0_3_reg_265 | reg_374);
assign next_buckets_1_1_fu_544_p2 = (tmp_buckets_1_3_reg_252 | reg_374);
assign nfa_finals_buckets_address = grp_nfa_get_finals_fu_362_nfa_finals_buckets_address;
assign nfa_finals_buckets_dataout = grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout;
assign nfa_finals_buckets_req_din = grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din;
assign nfa_finals_buckets_req_write = grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write;
assign nfa_finals_buckets_rsp_read = grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read;
assign nfa_finals_buckets_size = grp_nfa_get_finals_fu_362_nfa_finals_buckets_size;
assign nfa_forward_buckets_dataout = ap_const_lv32_0;
assign nfa_forward_buckets_req_din = ap_const_logic_0;
assign nfa_forward_buckets_size = ap_const_lv32_1;
assign nfa_initials_buckets_address = grp_nfa_get_initials_fu_356_nfa_initials_buckets_address;
assign nfa_initials_buckets_dataout = grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout;
assign nfa_initials_buckets_req_din = grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din;
assign nfa_initials_buckets_req_write = grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write;
assign nfa_initials_buckets_rsp_read = grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read;
assign nfa_initials_buckets_size = grp_nfa_get_initials_fu_356_nfa_initials_buckets_size;
assign sample_address = sample_addr_1_reg_606;
assign sample_dataout = ap_const_lv8_0;
assign sample_req_din = ap_const_logic_0;
assign sample_size = ap_const_lv32_1;
assign tmp_17_1_i_fu_426_p2 = (next_buckets_1_reg_158 == ap_const_lv32_0? 1'b1: 1'b0);
assign tmp_17_i_fu_420_p2 = (next_buckets_0_reg_168 == ap_const_lv32_0? 1'b1: 1'b0);
assign tmp_1_fu_568_p2 = (current_buckets_1_1_reg_746 | current_buckets_0_1_reg_741);
assign tmp_2_fu_572_p2 = (tmp_1_reg_751 != ap_const_lv32_0? 1'b1: 1'b0);
assign tmp_4_i_cast_fu_509_p1 = $unsigned(tmp_4_i_fu_502_p3);
assign tmp_4_i_fu_502_p3 = {{offset_i_reg_705}, {ap_const_lv1_0}};
assign tmp_5_fu_447_p1 = j_bucket_index1_reg_289[0:0];
assign tmp_7_i_cast_fu_444_p1 = $unsigned(sym_reg_621);
assign tmp_8_i_cast_fu_527_p1 = $unsigned(tmp_8_i_fu_520_p3);
assign tmp_8_i_fu_520_p3 = {{offset_i_reg_705}, {ap_const_lv1_1}};
assign tmp_s_fu_397_p2 = (i_reg_134 < length_r? 1'b1: 1'b0);
always @ (posedge ap_clk)
begin
tmp_7_i_cast_reg_650[13:8] <= 6'b000000;
end
endmodule //nfa_accept_sample
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DECAP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__DECAP_FUNCTIONAL_PP_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__decap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DECAP_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A22O_BEHAVIORAL_PP_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22O_BEHAVIORAL_PP_V |
module ARM_CU_ALU_TestBench2;
parameter sim_time = 750*2; // Num of Cycles * 2
reg MFC , Reset , Clk , MEMSTORE,MEMLOAD;
reg [31:0] MEMDAT;
wire MFA,READ_WRITE,WORD_BYTE;
wire [7:0] MEMADD;
//module ARM_CU_ALU( input MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, output MEMADD, MFA,READ_WRITE,WORD_BYTE);
ARM_CU_ALU CPU( MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT,MEMADD, MFA,READ_WRITE,WORD_BYTE);
initial fork
Reset =1; Clk = 0; MEMSTORE=0;MEMLOAD=0;MEMDAT=0;MFC=0;
#1 Reset = 0;
join
always@(posedge MFA)begin
case(MEMADD)
8'h00:begin
#1 MEMDAT = 32'b11100010_00000001_00000000_00000000 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h01:begin
#1 MEMDAT = 32'b11100011_10000000_00010000_00101000 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h02:begin
#1 MEMDAT = 32'b11100111_11010001_00100000_00000000 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h03:begin
#1 MEMDAT = 32'b11100101_11010001_00110000_00000010 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h04:begin
#1 MEMDAT = 32'b11100000_10000000_01010000_00000000 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h05:begin
#1 MEMDAT = 32'b11100000_10000010_01010000_00000101; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h06:begin
#1 MEMDAT = 32'b11100010_01010011_00110000_00000001 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h07:begin
#1 MEMDAT = 32'b00011010_11111111_11111111_11111101 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h08:begin
#1 MEMDAT = 32'b11100101_11000001_01010000_00000011 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h09:begin
#1 MEMDAT = 32'b11101010_00000000_00000000_00000001 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h0A:begin
#1 MEMDAT = 32'b00001011_00000101_00000111_00000100 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h0B:begin
#1 MEMDAT = 32'b11101010_11111111_11111111_11111111 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
default:begin
#1 MEMDAT = 32'h00000000 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
endcase
end
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("ARM_CU_ALU_TestBench2.vcd");
$dumpvars(0,ARM_CU_ALU_TestBench2);
$display(" Test Results" );
$monitor("input MFC =%d, Reset =%d, Clk =%d, MEMSTORE=%d,MEMLOAD=%d,MEMDAT=%d, output MEMADD=%d, MFA=%d,READ_WRITE=%d,WORD_BYTE=%d,",MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, MEMADD, MFA,READ_WRITE,WORD_BYTE);
end
endmodule
//iverilog ARM_ALU.v ARM_CU_ALU.v BarrelShifter.v Buffer32_32.v controlunit3.v Decoder4x16.v Multiplexer2x1_32b.v Register.v Register2.v RegisterFile.v Register2Buff.v ARM_CU_ALU_TestBench2.v |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_V
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_V
/**
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_clkinvkapwr (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__O2111AI_BEHAVIORAL_PP_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2111ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
// Local signals
wire C1 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, B1, D1, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111AI_BEHAVIORAL_PP_V |
module SortX16 # (
parameter DSIZE = 18,
parameter OFFSET = 8
)(
input [DSIZE-1:0] a0,
input [DSIZE-1:0] a1,
input [DSIZE-1:0] a2,
input [DSIZE-1:0] a3,
input [DSIZE-1:0] a4,
input [DSIZE-1:0] a5,
input [DSIZE-1:0] a6,
input [DSIZE-1:0] a7,
input [DSIZE-1:0] a8,
input [DSIZE-1:0] a9,
input [DSIZE-1:0] a10,
input [DSIZE-1:0] a11,
input [DSIZE-1:0] a12,
input [DSIZE-1:0] a13,
input [DSIZE-1:0] a14,
input [DSIZE-1:0] a15,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1,
output wire [DSIZE-1:0] sort2,
output wire [DSIZE-1:0] sort3,
output wire [DSIZE-1:0] sort4,
output wire [DSIZE-1:0] sort5,
output wire [DSIZE-1:0] sort6,
output wire [DSIZE-1:0] sort7,
output wire [DSIZE-1:0] sort8,
output wire [DSIZE-1:0] sort9,
output wire [DSIZE-1:0] sort10,
output wire [DSIZE-1:0] sort11,
output wire [DSIZE-1:0] sort12,
output wire [DSIZE-1:0] sort13,
output wire [DSIZE-1:0] sort14,
output wire [DSIZE-1:0] sort15
);
wire [DSIZE-1:0] sortX8_0_0;
wire [DSIZE-1:0] sortX8_0_1;
wire [DSIZE-1:0] sortX8_0_2;
wire [DSIZE-1:0] sortX8_0_3;
wire [DSIZE-1:0] sortX8_0_4;
wire [DSIZE-1:0] sortX8_0_5;
wire [DSIZE-1:0] sortX8_0_6;
wire [DSIZE-1:0] sortX8_0_7;
wire [DSIZE-1:0] sortX8_1_0;
wire [DSIZE-1:0] sortX8_1_1;
wire [DSIZE-1:0] sortX8_1_2;
wire [DSIZE-1:0] sortX8_1_3;
wire [DSIZE-1:0] sortX8_1_4;
wire [DSIZE-1:0] sortX8_1_5;
wire [DSIZE-1:0] sortX8_1_6;
wire [DSIZE-1:0] sortX8_1_7;
wire [DSIZE-1:0] sort0_0;
wire [DSIZE-1:0] sort0_1;
wire [DSIZE-1:0] sort1_0;
wire [DSIZE-1:0] sort1_1;
wire [DSIZE-1:0] sort2_0;
wire [DSIZE-1:0] sort2_1;
wire [DSIZE-1:0] sort3_0;
wire [DSIZE-1:0] sort3_1;
wire [DSIZE-1:0] sort4_0;
wire [DSIZE-1:0] sort4_1;
wire [DSIZE-1:0] sort5_0;
wire [DSIZE-1:0] sort5_1;
wire [DSIZE-1:0] sort6_0;
wire [DSIZE-1:0] sort6_1;
wire [DSIZE-1:0] sort7_0;
wire [DSIZE-1:0] sort7_1;
// divide sort
SortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sortX8_inst0 (
.a0 (a0),
.a1 (a1),
.a2 (a2),
.a3 (a3),
.a4 (a4),
.a5 (a5),
.a6 (a6),
.a7 (a7),
.sort0 (sortX8_0_0),
.sort1 (sortX8_0_1),
.sort2 (sortX8_0_2),
.sort3 (sortX8_0_3),
.sort4 (sortX8_0_4),
.sort5 (sortX8_0_5),
.sort6 (sortX8_0_6),
.sort7 (sortX8_0_7)
);
SortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sortX8_inst1 (
.a0 (a8),
.a1 (a9),
.a2 (a10),
.a3 (a11),
.a4 (a12),
.a5 (a13),
.a6 (a14),
.a7 (a15),
.sort0 (sortX8_1_0),
.sort1 (sortX8_1_1),
.sort2 (sortX8_1_2),
.sort3 (sortX8_1_3),
.sort4 (sortX8_1_4),
.sort5 (sortX8_1_5),
.sort6 (sortX8_1_6),
.sort7 (sortX8_1_7)
);
// merge
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst0 (
.a(sortX8_0_0),
.b(sortX8_1_7),
.sort0(sort0_0),
.sort1(sort0_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst1 (
.a(sortX8_0_1),
.b(sortX8_1_6),
.sort0(sort1_0),
.sort1(sort1_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst2 (
.a(sortX8_0_2),
.b(sortX8_1_5),
.sort0(sort2_0),
.sort1(sort2_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst3 (
.a(sortX8_0_3),
.b(sortX8_1_4),
.sort0(sort3_0),
.sort1(sort3_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst4 (
.a(sortX8_0_4),
.b(sortX8_1_3),
.sort0(sort4_0),
.sort1(sort4_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst5 (
.a(sortX8_0_5),
.b(sortX8_1_2),
.sort0(sort5_0),
.sort1(sort5_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst6 (
.a(sortX8_0_6),
.b(sortX8_1_1),
.sort0(sort6_0),
.sort1(sort6_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst7 (
.a(sortX8_0_7),
.b(sortX8_1_0),
.sort0(sort7_0),
.sort1(sort7_1)
);
// bitonic
BitonicSortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) bitonicsortx8_inst0 (
.a0 (sort0_0),
.a1 (sort1_0),
.a2 (sort2_0),
.a3 (sort3_0),
.a4 (sort4_0),
.a5 (sort5_0),
.a6 (sort6_0),
.a7 (sort7_0),
.sort0 (sort0),
.sort1 (sort1),
.sort2 (sort2),
.sort3 (sort3),
.sort4 (sort4),
.sort5 (sort5),
.sort6 (sort6),
.sort7 (sort7)
);
BitonicSortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) bitonicsortx8_inst1 (
.a0 (sort7_1),
.a1 (sort6_1),
.a2 (sort5_1),
.a3 (sort4_1),
.a4 (sort3_1),
.a5 (sort2_1),
.a6 (sort1_1),
.a7 (sort0_1),
.sort0 (sort8),
.sort1 (sort9),
.sort2 (sort10),
.sort3 (sort11),
.sort4 (sort12),
.sort5 (sort13),
.sort6 (sort14),
.sort7 (sort15)
);
endmodule
|
`timescale 1ns /1ps
module add4 ( o, a, b );
output [15:0] o;
input [15:0] a;
input [15:0] b;
wire n1, n2, n3, n4, n5, n6, n7,
n8, n9, n10, n11, n12, n13,
n14, n15, n16, n17, n18, n19,
n20, n21, n22, n23, n24, n25,
n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37,
n38, n39, n40, n41, n42, n43,
n44, n45, n46, n47, n48, n49,
n50, n51, n52, n53, n54, n55,
n56, n57, n58, n59, n60, n61,
n62, n63, n64, n65, n66, n67,
n68, n69, n70, n71, n72, n73,
n74, n75, n76, n77, n78, n79,
n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91,
n92, n93, n94, n95, n96, n97,
n98, n99, n100, n101, n102, n103,
n104, n105, n106, n107, n108,
n109, n110, n111, n112, n113,
n114, n115, n116, n117, n118,
n119, n120, n121, n122, n123,
n124, n125, n126, n127, n128,
n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138,
n139, n140, n141, n142, n143,
n144, n145, n146, n147, n148,
n149, n150, n151, n152, n153,
n154, n155, n156, n157, n158,
n159, n160, n161, n162, n163,
n164;
wire a0,a1, a2, a3, a4, a5, a6, a7,
a8, a9, a10, a11, a12, a13,
a14, a15;
wire b0,b1, b2, b3, b4, b5, b6, b7,
b8, b9, b10, b11, b12, b13,
b14, b15;
wire o0,o1, o2, o3, o4, o5, o6, o7,
o8, o9, o10, o11, o12, o13,
o14, o15;
buf #(0.716) G0 ( a0, a[0]);
buf #(0.716) G1 ( a1, a[0]);
buf #(0.716) G2 ( a2, a[1]);
buf #(0.716) G3 ( a3, a[1]);
buf #(0.716) G4 ( a4, a[2]);
buf #(0.716) G5 ( a5, a[2]);
buf #(0.716) G6 ( a6, a[3]);
buf #(0.716) G7 ( a7, a[3]);
buf #(0.716) G8 ( a8, a[4]);
buf #(0.716) G9 ( a9, a[4]);
buf #(0.716) G10 ( a10, a[5]);
buf #(0.716) G11 ( a11, a[5]);
buf #(0.716) G12 ( a12, a[6]);
buf #(0.716) G13 ( a13, a[6]);
buf #(0.716) G14 ( a14, a[7]);
buf #(0.716) G15 ( a15, a[7]);
buf #(0.716) H0 ( b0, b[0]);
buf #(0.716) H1 ( b1, b[0]);
buf #(0.716) H2 ( b2, b[1]);
buf #(0.716) H3 ( b3, b[1]);
buf #(0.716) H4 ( b4, b[2]);
buf #(0.716) H5 ( b5, b[2]);
buf #(0.716) H6 ( b6, b[3]);
buf #(0.716) H7 ( b7, b[3]);
buf #(0.716) H8 ( b8, b[4]);
buf #(0.716) H9 ( b9, b[4]);
buf #(0.716) H10 ( b10, b[5]);
buf #(0.716) H11 ( b11, b[5]);
buf #(0.716) H12 ( b12, b[6]);
buf #(0.716) H13 ( b13, b[6]);
buf #(0.716) H14 ( b14, b[7]);
buf #(0.716) H15 ( b15, b[7]);
nand #(0.716) K0 ( o[0],o0,o1,o2,o3);
nand #(0.716) K1 ( o[1],o4,o5,o6,o7);
nand #(0.716) K2 ( o[2],o8,o9,o10,o11);
nand #(0.716) K3 ( o[3],o12,o13,o14,o15);
not #(1.000) U4 ( n60, n160 );
nor #(1.000) U5 ( n160, n161, n162 );
not #(1.000) U6 ( n52, n156 );
not #(1.000) U7 ( n45, n152 );
not #(1.000) U8 ( n38, n148 );
not #(1.000) U9 ( n31, n144 );
not #(1.000) U10 ( n24, n140 );
not #(1.000) U11 ( n17, n136 );
not #(1.000) U12 ( n10, n132 );
not #(1.000) U13 ( n109, n107 );
not #(1.000) U14 ( n98, n96 );
not #(1.000) U15 ( n87, n85 );
not #(1.000) U16 ( n73, n71 );
not #(1.000) U17 ( n120, n118 );
nor #(1.000) U18 ( o2, n50, n51 );
and #(1.000) U19 ( n51, n52, n53 );
nor #(1.000) U20 ( n50, n52, n53 );
nand #(1.000) U21 ( n53, n54, n55 );
nor #(1.000) U22 ( o3, n43, n44 );
and #(1.000) U23 ( n44, n45, n46 );
nor #(1.000) U24 ( n43, n45, n46 );
nand #(1.000) U25 ( n46, n47, n48 );
nor #(1.000) U26 ( o4, n36, n37 );
and #(1.000) U27 ( n37, n38, n39 );
nor #(1.000) U28 ( n36, n38, n39 );
nand #(1.000) U29 ( n39, n40, n41 );
nor #(1.000) U30 ( o5, n29, n30 );
and #(1.000) U31 ( n30, n31, n32 );
nor #(1.000) U32 ( n29, n31, n32 );
nand #(1.000) U33 ( n32, n33, n34 );
nor #(1.000) U34 ( o6, n22, n23 );
and #(1.000) U35 ( n23, n24, n25 );
nor #(1.000) U36 ( n22, n24, n25 );
nand #(1.000) U37 ( n25, n26, n27 );
nor #(1.000) U38 ( o7, n15, n16 );
and #(1.000) U39 ( n16, n17, n18 );
nor #(1.000) U40 ( n15, n17, n18 );
nand #(1.000) U41 ( n18, n19, n20 );
nor #(1.000) U42 ( o8, n8, n9 );
and #(1.000) U43 ( n9, n10, n11 );
nor #(1.000) U44 ( n8, n10, n11 );
nand #(1.000) U45 ( n11, n12, n13 );
nor #(1.000) U46 ( o9, n1, n2 );
and #(1.000) U47 ( n2, n3, n4 );
nor #(1.000) U48 ( n1, n3, n4 );
nand #(1.000) U49 ( n4, n5, n6 );
nor #(1.000) U50 ( o10, n121, n122 );
and #(1.000) U51 ( n122, n120, n123 );
nor #(1.000) U52 ( n121, n120, n123 );
nand #(1.000) U53 ( n123, n124, n125 );
nor #(1.000) U54 ( o11, n110, n111 );
and #(1.000) U55 ( n111, n109, n112 );
nor #(1.000) U56 ( n110, n109, n112 );
nand #(1.000) U57 ( n112, n113, n114 );
nor #(1.000) U58 ( o12, n99, n100 );
and #(1.000) U59 ( n100, n98, n101 );
nor #(1.000) U60 ( n99, n98, n101 );
nand #(1.000) U61 ( n101, n102, n103 );
nor #(1.000) U62 ( o13, n88, n89 );
and #(1.000) U63 ( n89, n87, n90 );
nor #(1.000) U64 ( n88, n87, n90 );
nand #(1.000) U65 ( n90, n91, n92 );
nor #(1.000) U66 ( o14, n77, n78 );
and #(1.000) U67 ( n78, n73, n79 );
nor #(1.000) U68 ( n77, n73, n79 );
nand #(1.000) U69 ( n79, n80, n81 );
nor #(1.000) U70 ( o15, n64, n65 );
and #(1.000) U71 ( n65, n66, n67 );
nor #(1.000) U72 ( n64, n67, n66 );
nand #(1.000) U73 ( n66, n68, n69 );
nand #(1.000) U74 ( o1, n57, n58 );
or #(1.000) U75 ( n58, n59, n60 );
nand #(1.000) U76 ( n57, n59, n60 );
nand #(1.000) U77 ( n59, n61, n62 );
nand #(1.000) U78 ( n3, n129, n130 );
nand #(1.000) U79 ( n129, a8, n10 );
nand #(1.000) U80 ( n130, b8, n131 );
nand #(1.000) U81 ( n131, n132, n14 );
and #(1.000) U82 ( n156, n157, n158 );
nand #(1.000) U83 ( n158, b1, n159 );
nand #(1.000) U84 ( n157, a1, n160 );
nand #(1.000) U85 ( n159, n63, n60 );
and #(1.000) U86 ( n152, n153, n154 );
nand #(1.000) U87 ( n153, a2, n52 );
nand #(1.000) U88 ( n154, b2, n155 );
nand #(1.000) U89 ( n155, n156, n56 );
and #(1.000) U90 ( n148, n149, n150 );
nand #(1.000) U91 ( n149, a3, n45 );
nand #(1.000) U92 ( n150, b3, n151 );
nand #(1.000) U93 ( n151, n152, n49 );
and #(1.000) U94 ( n144, n145, n146 );
nand #(1.000) U95 ( n145, a4, n38 );
nand #(1.000) U96 ( n146, b4, n147 );
nand #(1.000) U97 ( n147, n148, n42 );
and #(1.000) U98 ( n107, n115, n116 );
nand #(1.000) U99 ( n115, a10, n120 );
nand #(1.000) U100 ( n116, b10, n117 );
nand #(1.000) U101 ( n117, n118, n119 );
and #(1.000) U102 ( n140, n141, n142 );
nand #(1.000) U103 ( n141, a5, n31 );
nand #(1.000) U104 ( n142, b5, n143 );
nand #(1.000) U105 ( n143, n144, n35 );
and #(1.000) U106 ( n96, n104, n105 );
nand #(1.000) U107 ( n104, a11, n109 );
nand #(1.000) U108 ( n105, b11, n106 );
nand #(1.000) U109 ( n106, n107, n108 );
and #(1.000) U110 ( n136, n137, n138 );
nand #(1.000) U111 ( n137, a6, n24 );
nand #(1.000) U112 ( n138, b6, n139 );
nand #(1.000) U113 ( n139, n140, n28 );
and #(1.000) U114 ( n85, n93, n94 );
nand #(1.000) U115 ( n93, a12, n98 );
nand #(1.000) U116 ( n94, b12, n95 );
nand #(1.000) U117 ( n95, n96, n97 );
and #(1.000) U118 ( n132, n133, n134 );
nand #(1.000) U119 ( n133, a7, n17 );
nand #(1.000) U120 ( n134, b7, n135 );
nand #(1.000) U121 ( n135, n136, n21 );
and #(1.000) U122 ( n71, n82, n83 );
nand #(1.000) U123 ( n82, a13, n87 );
nand #(1.000) U124 ( n83, b13, n84 );
nand #(1.000) U125 ( n84, n85, n86 );
and #(1.000) U126 ( n118, n126, n127 );
nand #(1.000) U127 ( n127, b9, n128 );
nand #(1.000) U128 ( n126, a9, n3 );
or #(1.000) U129 ( n128, n3, a9 );
nand #(1.000) U130 ( n67, n74, n75 );
or #(1.000) U131 ( n74, n76, b15 );
nand #(1.000) U132 ( n75, b15, n76 );
not #(1.000) U133 ( n76, a15 );
nand #(1.000) U134 ( n55, b2, n56 );
nand #(1.000) U135 ( n48, b3, n49 );
nand #(1.000) U136 ( n41, b4, n42 );
nand #(1.000) U137 ( n34, b5, n35 );
nand #(1.000) U138 ( n27, b6, n28 );
nand #(1.000) U139 ( n20, b7, n21 );
nand #(1.000) U140 ( n13, b8, n14 );
nand #(1.000) U141 ( n125, b10, n119 );
nand #(1.000) U142 ( n114, b11, n108 );
nand #(1.000) U143 ( n103, b12, n97 );
nand #(1.000) U144 ( n92, b13, n86 );
nand #(1.000) U145 ( n81, b14, n72 );
nand #(1.000) U146 ( n62, b1, n63 );
nand #(1.000) U147 ( n69, b14, n70 );
nand #(1.000) U148 ( n70, n71, n72 );
nand #(1.000) U149 ( n68, a14, n73 );
not #(1.000) U150 ( n56, a2 );
not #(1.000) U151 ( n49, a3 );
not #(1.000) U152 ( n42, a4 );
not #(1.000) U153 ( n35, a5 );
not #(1.000) U154 ( n28, a6 );
not #(1.000) U155 ( n21, a7 );
not #(1.000) U156 ( n14, a8 );
not #(1.000) U157 ( n119, a10 );
not #(1.000) U158 ( n108, a11 );
not #(1.000) U159 ( n97, a12 );
not #(1.000) U160 ( n86, a13 );
not #(1.000) U161 ( n72, a14 );
nand #(1.000) U162 ( n6, b9, n7 );
not #(1.000) U163 ( n63, a1 );
not #(1.000) U164 ( n161, b0 );
not #(1.000) U165 ( n162, a0 );
nand #(1.000) U166 ( o0, n163, n164 );
nand #(1.000) U167 ( n163, a0, n161 );
nand #(1.000) U168 ( n164, b0, n162 );
or #(1.000) U169 ( n61, n63, b1 );
or #(1.000) U170 ( n54, n56, b2 );
or #(1.000) U171 ( n47, n49, b3 );
or #(1.000) U172 ( n40, n42, b4 );
or #(1.000) U173 ( n33, n35, b5 );
or #(1.000) U174 ( n26, n28, b6 );
or #(1.000) U175 ( n19, n21, b7 );
or #(1.000) U176 ( n12, n14, b8 );
or #(1.000) U177 ( n5, n7, b9 );
or #(1.000) U178 ( n124, n119, b10 );
or #(1.000) U179 ( n113, n108, b11 );
or #(1.000) U180 ( n102, n97, b12 );
or #(1.000) U181 ( n91, n86, b13 );
or #(1.000) U182 ( n80, n72, b14 );
not #(1.000) U183 ( n7, a9 );
wire d1, d2, d3, d4, d5, d6, d7,
d8, d9, d10, d11, d12, d13,
d14, d15, d16, d17, d18, d19,
d20, d21, d22, d23, d24, d25,
d26, d27, d28, d29, d30, d31,
d32, d33, d34, d35, d36, d37,
d38, d39, d40, d41, d42, d43,
d44, d45, d46, d47, d48, d49,
d50, d51, d52, d53, d54, d55,
d56, d57, d58, d59, d60, d61,
d62, d63, d64, d65, d66, d67,
d68, d69, d70, d71, d72, d73,
d74, d75, d76, d77, d78, d79,
d80, d81, d82, d83, d84, d85,
d86, d87, d88, d89, d90, d91,
d92, d93, d94, d95, d96, d97,
d98, d99, d100, d101, d102, d103,
d104, d105, d106, d107, d108,
d109, d110, d111, d112, d113,
d114, d115, d116, d117, d118,
d119, d120, d121, d122, d123,
d124, d125, d126, d127, d128,
d129, d130, d131, d132, d133,
d134, d135, d136, d137, d138,
d139, d140, d141, d142, d143,
d144, d145, d146, d147, d148,
d149, d150, d151, d152, d153,
d154, d155, d156, d157, d158,
d159, d160, d161, d162, d163,
d164;
wire c0,c1, c2, c3, c4, c5, c6, c7,
c8, c9, c10, c11, c12, c13,
c14, c15;
wire e0,e1, e2, e3, e4, e5, e6, e7,
e8, e9, e10, e11, e12, e13,
e14, e15;
wire f0,f1, f2, f3, f4, f5, f6, f7,
f8, f9, f10, f11, f12, f13,
f14, f15;
buf #(0.716) GW0 ( c0, a[0]);
buf #(0.716) GW1 ( c1, a[0]);
buf #(0.716) GW2 ( c2, a[1]);
buf #(0.716) GW3 ( c3, a[1]);
buf #(0.716) GW4 ( c4, a[2]);
buf #(0.716) GW5 ( c5, a[2]);
buf #(0.716) GW6 ( c6, a[3]);
buf #(0.716) GW7 ( c7, a[3]);
buf #(0.716) GW8 ( c8, a[4]);
buf #(0.716) GW9 ( c9, a[4]);
buf #(0.716) GW10 ( c10, a[5]);
buf #(0.716) GW11 ( c11, a[5]);
buf #(0.716) GW12 ( c12, a[6]);
buf #(0.716) GW13 ( c13, a[6]);
buf #(0.716) GW14 ( c14, a[7]);
buf #(0.716) GW15 ( c15, a[7]);
buf #(0.716) HW0 ( e0, b[0]);
buf #(0.716) HW1 ( e1, b[0]);
buf #(0.716) HW2 ( e2, b[1]);
buf #(0.716) HW3 ( e3, b[1]);
buf #(0.716) HW4 ( e4, b[2]);
buf #(0.716) HW5 ( e5, b[2]);
buf #(0.716) HW6 ( e6, b[3]);
buf #(0.716) HW7 ( e7, b[3]);
buf #(0.716) HW8 ( e8, b[4]);
buf #(0.716) HW9 ( e9, b[4]);
buf #(0.716) HW10 ( e10, b[5]);
buf #(0.716) HW11 ( e11, b[5]);
buf #(0.716) HW12 ( e12, b[6]);
buf #(0.716) HW13 ( e13, b[6]);
buf #(0.716) HW14 ( e14, b[7]);
buf #(0.716) HW15 ( e15, b[7]);
nand #(0.716) KW0 ( o[4],f0,f1,f2,f3);
nand #(0.716) KW1 ( o[5],f4,f5,f6,f7);
nand #(0.716) KW2 ( o[6],f8,f9,f10,f11);
nand #(0.716) KW3 ( o[7],f12,f13,f14,f15);
not #(1.000) UW4 ( d60, d160 );
nor #(1.000) UW5 ( d160, d161, d162 );
not #(1.000) UW6 ( d52, d156 );
not #(1.000) UW7 ( d45, d152 );
not #(1.000) UW8 ( d38, d148 );
not #(1.000) UW9 ( d31, d144 );
not #(1.000) UW10 ( d24, d140 );
not #(1.000) UW11 ( d17, d136 );
not #(1.000) UW12 ( d10, d132 );
not #(1.000) UW13 ( d109, d107 );
not #(1.000) UW14 ( d98, d96 );
not #(1.000) UW15 ( d87, d85 );
not #(1.000) UW16 ( d73, d71 );
not #(1.000) UW17 ( d120, d118 );
nor #(1.000) UW18 ( f2, d50, d51 );
and #(1.000) UW19 ( d51, d52, d53 );
nor #(1.000) UW20 ( d50, d52, d53 );
nand #(1.000) UW21 ( d53, d54, d55 );
nor #(1.000) UW22 ( f3, d43, d44 );
and #(1.000) UW23 ( d44, d45, d46 );
nor #(1.000) UW24 ( d43, d45, d46 );
nand #(1.000) UW25 ( d46, d47, d48 );
nor #(1.000) UW26 ( f4, d36, d37 );
and #(1.000) UW27 ( d37, d38, d39 );
nor #(1.000) UW28 ( d36, d38, d39 );
nand #(1.000) UW29 ( d39, d40, d41 );
nor #(1.000) UW30 ( f5, d29, d30 );
and #(1.000) UW31 ( d30, d31, d32 );
nor #(1.000) UW32 ( d29, d31, d32 );
nand #(1.000) UW33 ( d32, d33, d34 );
nor #(1.000) UW34 ( f6, d22, d23 );
and #(1.000) UW35 ( d23, d24, d25 );
nor #(1.000) UW36 ( d22, d24, d25 );
nand #(1.000) UW37 ( d25, d26, d27 );
nor #(1.000) UW38 ( f7, d15, d16 );
and #(1.000) UW39 ( d16, d17, d18 );
nor #(1.000) UW40 ( d15, d17, d18 );
nand #(1.000) UW41 ( d18, d19, d20 );
nor #(1.000) UW42 ( f8, d8, d9 );
and #(1.000) UW43 ( d9, d10, d11 );
nor #(1.000) UW44 ( d8, d10, d11 );
nand #(1.000) UW45 ( d11, d12, d13 );
nor #(1.000) UW46 ( f9, d1, d2 );
and #(1.000) UW47 ( d2, d3, d4 );
nor #(1.000) UW48 ( d1, d3, d4 );
nand #(1.000) UW49 ( d4, d5, d6 );
nor #(1.000) UW50 ( f10, d121, d122 );
and #(1.000) UW51 ( d122, d120, d123 );
nor #(1.000) UW52 ( d121, d120, d123 );
nand #(1.000) UW53 ( d123, d124, d125 );
nor #(1.000) UW54 ( f11, d110, d111 );
and #(1.000) UW55 ( d111, d109, d112 );
nor #(1.000) UW56 ( d110, d109, d112 );
nand #(1.000) UW57 ( d112, d113, d114 );
nor #(1.000) UW58 ( f12, d99, d100 );
and #(1.000) UW59 ( d100, d98, d101 );
nor #(1.000) UW60 ( d99, d98, d101 );
nand #(1.000) UW61 ( d101, d102, d103 );
nor #(1.000) UW62 ( f13, d88, d89 );
and #(1.000) UW63 ( d89, d87, d90 );
nor #(1.000) UW64 ( d88, d87, d90 );
nand #(1.000) UW65 ( d90, d91, d92 );
nor #(1.000) UW66 ( f14, d77, d78 );
and #(1.000) UW67 ( d78, d73, d79 );
nor #(1.000) UW68 ( d77, d73, d79 );
nand #(1.000) UW69 ( d79, d80, d81 );
nor #(1.000) UW70 ( f15, d64, d65 );
and #(1.000) UW71 ( d65, d66, d67 );
nor #(1.000) UW72 ( d64, d67, d66 );
nand #(1.000) UW73 ( d66, d68, d69 );
nand #(1.000) UW74 ( f1, d57, d58 );
or #(1.000) UW75 ( d58, d59, d60 );
nand #(1.000) UW76 ( d57, d59, d60 );
nand #(1.000) UW77 ( d59, d61, d62 );
nand #(1.000) UW78 ( d3, d129, d130 );
nand #(1.000) UW79 ( d129, c8, d10 );
nand #(1.000) UW80 ( d130, e8, d131 );
nand #(1.000) UW81 ( d131, d132, d14 );
and #(1.000) UW82 ( d156, d157, d158 );
nand #(1.000) UW83 ( d158, e1, d159 );
nand #(1.000) UW84 ( d157, c1, d160 );
nand #(1.000) UW85 ( d159, d63, d60 );
and #(1.000) UW86 ( d152, d153, d154 );
nand #(1.000) UW87 ( d153, c2, d52 );
nand #(1.000) UW88 ( d154, e2, d155 );
nand #(1.000) UW89 ( d155, d156, d56 );
and #(1.000) UW90 ( d148, d149, d150 );
nand #(1.000) UW91 ( d149, c3, d45 );
nand #(1.000) UW92 ( d150, e3, d151 );
nand #(1.000) UW93 ( d151, d152, d49 );
and #(1.000) UW94 ( d144, d145, d146 );
nand #(1.000) UW95 ( d145, c4, d38 );
nand #(1.000) UW96 ( d146, e4, d147 );
nand #(1.000) UW97 ( d147, d148, d42 );
and #(1.000) UW98 ( d107, d115, d116 );
nand #(1.000) UW99 ( d115, c10, d120 );
nand #(1.000) UW100 ( d116, e10, d117 );
nand #(1.000) UW101 ( d117, d118, d119 );
and #(1.000) UW102 ( d140, d141, d142 );
nand #(1.000) UW103 ( d141, c5, d31 );
nand #(1.000) UW104 ( d142, e5, d143 );
nand #(1.000) UW105 ( d143, d144, d35 );
and #(1.000) UW106 ( d96, d104, d105 );
nand #(1.000) UW107 ( d104, c11, d109 );
nand #(1.000) UW108 ( d105, e11, d106 );
nand #(1.000) UW109 ( d106, d107, d108 );
and #(1.000) UW110 ( d136, d137, d138 );
nand #(1.000) UW111 ( d137, c6, d24 );
nand #(1.000) UW112 ( d138, e6, d139 );
nand #(1.000) UW113 ( d139, d140, d28 );
and #(1.000) UW114 ( d85, d93, d94 );
nand #(1.000) UW115 ( d93, c12, d98 );
nand #(1.000) UW116 ( d94, e12, d95 );
nand #(1.000) UW117 ( d95, d96, d97 );
and #(1.000) UW118 ( d132, d133, d134 );
nand #(1.000) UW119 ( d133, c7, d17 );
nand #(1.000) UW120 ( d134, e7, d135 );
nand #(1.000) UW121 ( d135, d136, d21 );
and #(1.000) UW122 ( d71, d82, d83 );
nand #(1.000) UW123 ( d82, c13, d87 );
nand #(1.000) UW124 ( d83, e13, d84 );
nand #(1.000) UW125 ( d84, d85, d86 );
and #(1.000) UW126 ( d118, d126, d127 );
nand #(1.000) UW127 ( d127, e9, d128 );
nand #(1.000) UW128 ( d126, c9, d3 );
or #(1.000) UW129 ( d128, d3, c9 );
nand #(1.000) UW130 ( d67, d74, d75 );
or #(1.000) UW131 ( d74, d76, e15 );
nand #(1.000) UW132 ( d75, e15, d76 );
not #(1.000) UW133 ( d76, c15 );
nand #(1.000) UW134 ( d55, e2, d56 );
nand #(1.000) UW135 ( d48, e3, d49 );
nand #(1.000) UW136 ( d41, e4, d42 );
nand #(1.000) UW137 ( d34, e5, d35 );
nand #(1.000) UW138 ( d27, e6, d28 );
nand #(1.000) UW139 ( d20, e7, d21 );
nand #(1.000) UW140 ( d13, e8, d14 );
nand #(1.000) UW141 ( d125, e10, d119 );
nand #(1.000) UW142 ( d114, e11, d108 );
nand #(1.000) UW143 ( d103, e12, d97 );
nand #(1.000) UW144 ( d92, e13, d86 );
nand #(1.000) UW145 ( d81, e14, d72 );
nand #(1.000) UW146 ( d62, e1, d63 );
nand #(1.000) UW147 ( d69, e14, d70 );
nand #(1.000) UW148 ( d70, d71, d72 );
nand #(1.000) UW149 ( d68, c14, d73 );
not #(1.000) UW150 ( d56, c2 );
not #(1.000) UW151 ( d49, c3 );
not #(1.000) UW152 ( d42, c4 );
not #(1.000) UW153 ( d35, c5 );
not #(1.000) UW154 ( d28, c6 );
not #(1.000) UW155 ( d21, c7 );
not #(1.000) UW156 ( d14, c8 );
not #(1.000) UW157 ( d119, c10 );
not #(1.000) UW158 ( d108, c11 );
not #(1.000) UW159 ( d97, c12 );
not #(1.000) UW160 ( d86, c13 );
not #(1.000) UW161 ( d72, c14 );
nand #(1.000) UW162 ( d6, e9, d7 );
not #(1.000) UW163 ( d63, c1 );
not #(1.000) UW164 ( d161, e0 );
not #(1.000) UW165 ( d162, c0 );
nand #(1.000) UW166 ( f0, d163, d164 );
nand #(1.000) UW167 ( d163, c0, d161 );
nand #(1.000) UW168 ( d164, e0, d162 );
or #(1.000) UW169 ( d61, d63, e1 );
or #(1.000) UW170 ( d54, d56, e2 );
or #(1.000) UW171 ( d47, d49, e3 );
or #(1.000) UW172 ( d40, d42, e4 );
or #(1.000) UW173 ( d33, d35, e5 );
or #(1.000) UW174 ( d26, d28, e6 );
or #(1.000) UW175 ( d19, d21, e7 );
or #(1.000) UW176 ( d12, d14, e8 );
or #(1.000) UW177 ( d5, d7, e9 );
or #(1.000) UW178 ( d124, d119, e10 );
or #(1.000) UW179 ( d113, d108, e11 );
or #(1.000) UW180 ( d102, d97, e12 );
or #(1.000) UW181 ( d91, d86, e13 );
or #(1.000) UW182 ( d80, d72, e14 );
not #(1.000) UW183 ( d7, c9 );
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : PIO_64_RX_ENGINE.v
// Version : 2.4
//--
//-- Description: 64 bit Local-Link Receive Unit.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module PIO_64_RX_ENGINE #(
parameter TCQ = 1,
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
input clk,
input rst_n,
// AXI-S
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output reg m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
/*
* Memory Read data handshake with Completion
* transmit unit. Transmit unit reponds to
* req_compl assertion and responds with compl_done
* assertion when a Completion w/ data is transmitted.
*/
output reg req_compl_o,
output reg req_compl_wd_o,
input compl_done_i,
output reg [2:0] req_tc_o, // Memory Read TC
output reg req_td_o, // Memory Read TD
output reg req_ep_o, // Memory Read EP
output reg [1:0] req_attr_o, // Memory Read Attribute
output reg [9:0] req_len_o, // Memory Read Length (1DW)
output reg [15:0] req_rid_o, // Memory Read Requestor ID
output reg [7:0] req_tag_o, // Memory Read Tag
output reg [7:0] req_be_o, // Memory Read Byte Enables
output reg [12:0] req_addr_o, // Memory Read Address
/*
* Memory interface used to save 1 DW data received
* on Memory Write 32 TLP. Data extracted from
* inbound TLP is presented to the Endpoint memory
* unit. Endpoint memory unit reacts to wr_en_o
* assertion and asserts wr_busy_i when it is
* processing written information.
*/
output reg [10:0] wr_addr_o, // Memory Write Address
output reg [7:0] wr_be_o, // Memory Write Byte Enable
output reg [31:0] wr_data_o, // Memory Write Data
output reg wr_en_o, // Memory Write Enable
input wr_busy_i // Memory Write Busy
);
localparam PIO_64_RX_MEM_RD32_FMT_TYPE = 7'b00_00000;
localparam PIO_64_RX_MEM_WR32_FMT_TYPE = 7'b10_00000;
localparam PIO_64_RX_MEM_RD64_FMT_TYPE = 7'b01_00000;
localparam PIO_64_RX_MEM_WR64_FMT_TYPE = 7'b11_00000;
localparam PIO_64_RX_IO_RD32_FMT_TYPE = 7'b00_00010;
localparam PIO_64_RX_IO_WR32_FMT_TYPE = 7'b10_00010;
localparam PIO_64_RX_RST_STATE = 8'b00000000;
localparam PIO_64_RX_MEM_RD32_DW1DW2 = 8'b00000001;
localparam PIO_64_RX_MEM_WR32_DW1DW2 = 8'b00000010;
localparam PIO_64_RX_MEM_RD64_DW1DW2 = 8'b00000100;
localparam PIO_64_RX_MEM_WR64_DW1DW2 = 8'b00001000;
localparam PIO_64_RX_MEM_WR64_DW3 = 8'b00010000;
localparam PIO_64_RX_WAIT_STATE = 8'b00100000;
localparam PIO_64_RX_IO_WR_DW1DW2 = 8'b01000000;
localparam PIO_64_RX_IO_MEM_WR_WAIT_STATE = 8'b10000000;
// Local Registers
reg [7:0] state;
reg [7:0] tlp_type;
wire io_bar_hit_n;
wire mem32_bar_hit_n;
wire mem64_bar_hit_n;
wire erom_bar_hit_n;
reg [1:0] region_select;
wire sop; // Start of packet
reg in_packet_q;
// Generate a signal that indicates if we are currently receiving a packet.
// This value is one clock cycle delayed from what is actually on the AXIS
// data bus.
always@(posedge clk)
begin
if(!rst_n)
in_packet_q <= # TCQ 1'b0;
else if (m_axis_rx_tvalid && m_axis_rx_tready && m_axis_rx_tlast)
in_packet_q <= # TCQ 1'b0;
else if (sop && m_axis_rx_tready)
in_packet_q <= # TCQ 1'b1;
end
assign sop = !in_packet_q && m_axis_rx_tvalid;
always @ ( posedge clk ) begin
if (!rst_n ) begin
m_axis_rx_tready <= #TCQ 1'b0;
req_compl_o <= #TCQ 1'b0;
req_compl_wd_o <= #TCQ 1'b1;
req_tc_o <= #TCQ 3'b0;
req_td_o <= #TCQ 1'b0;
req_ep_o <= #TCQ 1'b0;
req_attr_o <= #TCQ 2'b0;
req_len_o <= #TCQ 10'b0;
req_rid_o <= #TCQ 16'b0;
req_tag_o <= #TCQ 8'b0;
req_be_o <= #TCQ 8'b0;
req_addr_o <= #TCQ 13'b0;
wr_be_o <= #TCQ 8'b0;
wr_addr_o <= #TCQ 11'b0;
wr_data_o <= #TCQ 32'b0;
wr_en_o <= #TCQ 1'b0;
state <= #TCQ PIO_64_RX_RST_STATE;
tlp_type <= #TCQ 8'b0;
end else begin
wr_en_o <= #TCQ 1'b0;
req_compl_o <= #TCQ 1'b0;
case (state)
PIO_64_RX_RST_STATE : begin
m_axis_rx_tready <= #TCQ 1'b1;
req_compl_wd_o <= #TCQ 1'b1;
if (sop) begin
case (m_axis_rx_tdata[30:24])
PIO_64_RX_MEM_RD32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1) begin
req_tc_o <= #TCQ m_axis_rx_tdata[22:20];
req_td_o <= #TCQ m_axis_rx_tdata[15];
req_ep_o <= #TCQ m_axis_rx_tdata[14];
req_attr_o <= #TCQ m_axis_rx_tdata[13:12];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
req_rid_o <= #TCQ m_axis_rx_tdata[63:48];
req_tag_o <= #TCQ m_axis_rx_tdata[47:40];
req_be_o <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_64_RX_MEM_RD32_DW1DW2;
end else begin
state <= #TCQ PIO_64_RX_RST_STATE;
end
end
PIO_64_RX_MEM_WR32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1) begin
wr_be_o <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_64_RX_MEM_WR32_DW1DW2;
end else begin
state <= #TCQ PIO_64_RX_RST_STATE;
end
end
PIO_64_RX_MEM_RD64_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1) begin
req_tc_o <= #TCQ m_axis_rx_tdata[22:20];
req_td_o <= #TCQ m_axis_rx_tdata[15];
req_ep_o <= #TCQ m_axis_rx_tdata[14];
req_attr_o <= #TCQ m_axis_rx_tdata[13:12];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
req_rid_o <= #TCQ m_axis_rx_tdata[63:48];
req_tag_o <= #TCQ m_axis_rx_tdata[47:40];
req_be_o <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_64_RX_MEM_RD64_DW1DW2;
end else begin
state <= #TCQ PIO_64_RX_RST_STATE;
end
end
PIO_64_RX_MEM_WR64_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
if (m_axis_rx_tdata[9:0] == 10'b1) begin
wr_be_o <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_64_RX_MEM_WR64_DW1DW2;
end else begin
state <= #TCQ PIO_64_RX_RST_STATE;
end
end
PIO_64_RX_IO_RD32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1) begin
req_tc_o <= #TCQ m_axis_rx_tdata[22:20];
req_td_o <= #TCQ m_axis_rx_tdata[15];
req_ep_o <= #TCQ m_axis_rx_tdata[14];
req_attr_o <= #TCQ m_axis_rx_tdata[13:12];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
req_rid_o <= #TCQ m_axis_rx_tdata[63:48];
req_tag_o <= #TCQ m_axis_rx_tdata[47:40];
req_be_o <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_64_RX_MEM_RD32_DW1DW2;
end else begin
state <= #TCQ PIO_64_RX_RST_STATE;
end
end
PIO_64_RX_IO_WR32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1) begin
req_tc_o <= #TCQ m_axis_rx_tdata[22:20];
req_td_o <= #TCQ m_axis_rx_tdata[15];
req_ep_o <= #TCQ m_axis_rx_tdata[14];
req_attr_o <= #TCQ m_axis_rx_tdata[13:12];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
req_rid_o <= #TCQ m_axis_rx_tdata[63:48];
req_tag_o <= #TCQ m_axis_rx_tdata[47:40];
req_be_o <= #TCQ m_axis_rx_tdata[39:32];
wr_be_o <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_64_RX_IO_WR_DW1DW2;
end else begin
state <= #TCQ PIO_64_RX_RST_STATE;
end
end
default : begin // other TLPs
state <= #TCQ PIO_64_RX_RST_STATE;
end
endcase
end else
state <= #TCQ PIO_64_RX_RST_STATE;
end
PIO_64_RX_MEM_RD32_DW1DW2 : begin
if (m_axis_rx_tvalid) begin
m_axis_rx_tready <= #TCQ 1'b0;
req_addr_o <= #TCQ {region_select[1:0],m_axis_rx_tdata[10:2], 2'b00};
req_compl_o <= #TCQ 1'b1;
req_compl_wd_o <= #TCQ 1'b1;
state <= #TCQ PIO_64_RX_WAIT_STATE;
end else
state <= #TCQ PIO_64_RX_MEM_RD32_DW1DW2;
end
PIO_64_RX_MEM_WR32_DW1DW2 : begin
if (m_axis_rx_tvalid) begin
wr_data_o <= #TCQ m_axis_rx_tdata[63:32];
wr_en_o <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr_o <= #TCQ {region_select[1:0],m_axis_rx_tdata[10:2]};
state <= #TCQ PIO_64_RX_WAIT_STATE;
end else
state <= #TCQ PIO_64_RX_MEM_WR32_DW1DW2;
end
PIO_64_RX_MEM_RD64_DW1DW2 : begin
if (m_axis_rx_tvalid) begin
req_addr_o <= #TCQ {region_select[1:0],m_axis_rx_tdata[42:34], 2'b00};
req_compl_o <= #TCQ 1'b1;
req_compl_wd_o <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
state <= #TCQ PIO_64_RX_WAIT_STATE;
end else
state <= #TCQ PIO_64_RX_MEM_RD64_DW1DW2;
end
PIO_64_RX_MEM_WR64_DW1DW2 : begin
if (m_axis_rx_tvalid) begin
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr_o <= #TCQ {region_select[1:0],m_axis_rx_tdata[42:34]};
state <= #TCQ PIO_64_RX_MEM_WR64_DW3;
end else
state <= #TCQ PIO_64_RX_MEM_WR64_DW1DW2;
end
PIO_64_RX_MEM_WR64_DW3 : begin
if (m_axis_rx_tvalid) begin
wr_data_o <= #TCQ m_axis_rx_tdata[31:0];
wr_en_o <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
state <= #TCQ PIO_64_RX_WAIT_STATE;
end else
state <= #TCQ PIO_64_RX_MEM_WR64_DW3;
end
PIO_64_RX_IO_WR_DW1DW2 : begin
if (m_axis_rx_tvalid) begin
wr_data_o <= #TCQ m_axis_rx_tdata[63:32];
wr_en_o <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr_o <= #TCQ {region_select[1:0],m_axis_rx_tdata[10:2]};
req_compl_o <= #TCQ 1'b1;
req_compl_wd_o <= #TCQ 1'b0;
state <= #TCQ PIO_64_RX_WAIT_STATE;
end else
state <= #TCQ PIO_64_RX_IO_WR_DW1DW2;
end
PIO_64_RX_WAIT_STATE : begin
wr_en_o <= #TCQ 1'b0;
req_compl_o <= #TCQ 1'b0;
if ((tlp_type == PIO_64_RX_MEM_WR32_FMT_TYPE) &&
(!wr_busy_i)) begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_64_RX_RST_STATE;
end else if ((tlp_type == PIO_64_RX_IO_WR32_FMT_TYPE) &&
(!wr_busy_i)) begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_64_RX_RST_STATE;
end else if ((tlp_type == PIO_64_RX_MEM_WR64_FMT_TYPE) &&
(!wr_busy_i)) begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_64_RX_RST_STATE;
end else if ((tlp_type == PIO_64_RX_MEM_RD32_FMT_TYPE) &&
(compl_done_i)) begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_64_RX_RST_STATE;
end else if ((tlp_type == PIO_64_RX_IO_RD32_FMT_TYPE) &&
(compl_done_i)) begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_64_RX_RST_STATE;
end else if ((tlp_type == PIO_64_RX_MEM_RD64_FMT_TYPE) &&
(compl_done_i)) begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_64_RX_RST_STATE;
end else
state <= #TCQ PIO_64_RX_WAIT_STATE;
end
endcase
end
end
assign mem64_bar_hit_n = ~m_axis_rx_tuser[2];
assign io_bar_hit_n = ~m_axis_rx_tuser[5];
assign mem32_bar_hit_n = ~m_axis_rx_tuser[4];
assign erom_bar_hit_n = !m_axis_rx_tuser[8];
always @*
begin
case ({io_bar_hit_n, mem32_bar_hit_n, mem64_bar_hit_n, erom_bar_hit_n})
4'b0111 : begin
region_select <= #TCQ 2'b00; // Select IO region
end
4'b1011 : begin
region_select <= #TCQ 2'b01; // Select Mem32 region
end
4'b1101 : begin
region_select <= #TCQ 2'b10; // Select Mem64 region
end
4'b1110 : begin
region_select <= #TCQ 2'b11; // Select EROM region
end
default : begin
region_select <= #TCQ 2'b00; // Error selection will select IO region
end
endcase
end
// synthesis translate_off
reg [8*20:1] state_ascii;
always @(state)
begin
case (state)
PIO_64_RX_RST_STATE : state_ascii <= #TCQ "RX_RST_STATE";
PIO_64_RX_MEM_RD32_DW1DW2 : state_ascii <= #TCQ "RX_MEM_RD32_DW1DW2";
PIO_64_RX_MEM_WR32_DW1DW2 : state_ascii <= #TCQ "RX_MEM_WR32_DW1DW2";
PIO_64_RX_MEM_RD64_DW1DW2 : state_ascii <= #TCQ "RX_MEM_RD64_DW1DW2";
PIO_64_RX_MEM_WR64_DW1DW2 : state_ascii <= #TCQ "RX_MEM_WR64_DW1DW2";
PIO_64_RX_MEM_WR64_DW3 : state_ascii <= #TCQ "RX_MEM_WR64_DW3";
PIO_64_RX_WAIT_STATE : state_ascii <= #TCQ "RX_WAIT_STATE";
PIO_64_RX_IO_WR_DW1DW2 : state_ascii <= #TCQ "PIO_64_RX_IO_WR_DW1DW2";
PIO_64_RX_IO_MEM_WR_WAIT_STATE : state_ascii <= #TCQ "PIO_64_RX_IO_MEM_WR_WAIT_STATE";
default : state_ascii <= #TCQ "PIO 64 STATE ERR";
endcase
end
// synthesis translate_on
endmodule // PIO_64_RX_ENGINE
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_sfr.v
//
// *Module Description:
// Processor Special function register
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 34 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Di, 29 Dez 2009) $
//----------------------------------------------------------------------------
`include "timescale.v"
`include "openMSP430_defines.v"
module omsp_sfr (
// OUTPUTs
nmie, // Non-maskable interrupt enable
per_dout, // Peripheral data output
wdt_irq, // Watchdog-timer interrupt
wdt_reset, // Watchdog-timer reset
wdtie, // Watchdog-timer interrupt enable
// INPUTs
mclk, // Main system clock
nmi_acc, // Non-Maskable interrupt request accepted
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_wen, // Peripheral write enable (high active)
por, // Power-on reset
puc, // Main system reset
wdtifg_clr, // Clear Watchdog-timer interrupt flag
wdtifg_set, // Set Watchdog-timer interrupt flag
wdtpw_error, // Watchdog-timer password error
wdttmsel // Watchdog-timer mode select
);
// OUTPUTs
//=========
output nmie; // Non-maskable interrupt enable
output [15:0] per_dout; // Peripheral data output
output wdt_irq; // Watchdog-timer interrupt
output wdt_reset; // Watchdog-timer reset
output wdtie; // Watchdog-timer interrupt enable
// INPUTs
//=========
input mclk; // Main system clock
input nmi_acc; // Non-Maskable interrupt request accepted
input [7:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_wen; // Peripheral write enable (high active)
input por; // Power-on reset
input puc; // Main system reset
input wdtifg_clr; // Clear Watchdog-timer interrupt flag
input wdtifg_set; // Set Watchdog-timer interrupt flag
input wdtpw_error; // Watchdog-timer password error
input wdttmsel; // Watchdog-timer mode select
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Register addresses
parameter IE1 = 9'h000;
parameter IFG1 = 9'h002;
// Register one-hot decoder
parameter IE1_D = (256'h1 << (IE1 /2));
parameter IFG1_D = (256'h1 << (IFG1 /2));
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Register address decode
reg [255:0] reg_dec;
always @(per_addr)
case (per_addr)
(IE1 /2): reg_dec = IE1_D;
(IFG1 /2): reg_dec = IFG1_D;
default : reg_dec = {256{1'b0}};
endcase
// Read/Write probes
wire reg_lo_write = per_wen[0] & per_en;
wire reg_hi_write = per_wen[1] & per_en;
wire reg_read = ~|per_wen & per_en;
// Read/Write vectors
wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}};
wire [255:0] reg_rd = reg_dec & {256{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// IE1 Register
//--------------
wire [7:0] ie1;
wire ie1_wr = IE1[0] ? reg_hi_wr[IE1/2] : reg_lo_wr[IE1/2];
wire [7:0] ie1_nxt = IE1[0] ? per_din[15:8] : per_din[7:0];
reg nmie;
always @ (posedge mclk or posedge puc)
if (puc) nmie <= 1'b0;
else if (nmi_acc) nmie <= 1'b0;
else if (ie1_wr) nmie <= ie1_nxt[4];
reg wdtie;
always @ (posedge mclk or posedge puc)
if (puc) wdtie <= 1'b0;
else if (ie1_wr) wdtie <= ie1_nxt[0];
assign ie1 = {3'b000, nmie, 3'b000, wdtie};
// IFG1 Register
//---------------
wire [7:0] ifg1;
wire ifg1_wr = IFG1[0] ? reg_hi_wr[IFG1/2] : reg_lo_wr[IFG1/2];
wire [7:0] ifg1_nxt = IFG1[0] ? per_din[15:8] : per_din[7:0];
reg nmiifg;
always @ (posedge mclk or posedge puc)
if (puc) nmiifg <= 1'b0;
else if (nmi_acc) nmiifg <= 1'b1;
else if (ifg1_wr) nmiifg <= ifg1_nxt[4];
reg wdtifg;
always @ (posedge mclk or posedge por)
if (por) wdtifg <= 1'b0;
else if (wdtifg_set) wdtifg <= 1'b1;
else if (wdttmsel & wdtifg_clr) wdtifg <= 1'b0;
else if (ifg1_wr) wdtifg <= ifg1_nxt[0];
assign ifg1 = {3'b000, nmiifg, 3'b000, wdtifg};
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] ie1_rd = (ie1 & {8{reg_rd[IE1/2]}}) << (8 & {4{IE1[0]}});
wire [15:0] ifg1_rd = (ifg1 & {8{reg_rd[IFG1/2]}}) << (8 & {4{IFG1[0]}});
wire [15:0] per_dout = ie1_rd |
ifg1_rd;
//=============================================================================
// 5) WATCHDOG INTERRUPT & RESET
//=============================================================================
// Watchdog interrupt generation
//---------------------------------
wire wdt_irq = wdttmsel & wdtifg & wdtie;
// Watchdog reset generation
//-----------------------------
reg wdt_reset;
always @ (posedge mclk or posedge por)
if (por) wdt_reset <= 1'b0;
else wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);
endmodule // omsp_sfr
`include "openMSP430_undefines.v"
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:13:36 09/03/2013
// Design Name:
// Module Name: clock_divider
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clock_divider(input clk, input rst, output reg clk_out);
//Lleva la cuenta de los ciclos de reloj transcurridos
reg [25:0] counter;
initial
begin
counter <= 26'd0;
clk_out <= 1'b1;
end
always @(posedge clk or posedge rst)
begin
if(rst)
begin
counter <= 26'd0;
clk_out <= ~clk_out;
end
else
if(counter == 26'd25000000) //va convertir un clk de 50MHz a 1Hz
begin
counter <= 26'd0;
clk_out <= ~clk_out;
end
else
begin
counter <= counter+1;
end
end
endmodule
|
module score (
input wire clk,
input wire [10:0] PIXEL_H, PIXEL_V,
input wire [7:0] PLAYER_ONE, PLAYER_TWO,
output reg [2:0] PIXEL
);
// signal declaration
wire [10:0] rom_addr;
reg [6:0] char_addr;
reg [3:0] row_addr;
reg [2:0] bit_addr;
wire [7:0] font_word;
wire font_bit;
wire p1, p2;
// instantiate font ROM
font_rom font_unit
(.clk(clk), .addr(rom_addr), .data(font_word));
// Location on the screen of the player one score.
reg [10:0] p1_v_start = 11'd10;
reg [10:0] p1_h_start = 11'd280;
// Location on the screen of the player two score.
reg [10:0] p2_v_start = 11'd10;
reg [10:0] p2_h_start = 11'd470;
// Check we are within the part of the screen that holds the player one score.
assign p1 = (
PIXEL_H >= p1_h_start && PIXEL_H <= p1_h_start + (8'd7 << 2)
&& PIXEL_V >= p1_v_start && PIXEL_V <= p1_v_start + (8'd15 << 2)
);
// Check we are within the part of the screen that holds the player two score.
assign p2 = (
PIXEL_H >= p2_h_start && PIXEL_H <= p2_h_start + (8'd7 << 2)
&& PIXEL_V >= p2_v_start && PIXEL_V <= p2_v_start + (8'd15 << 2)
);
// Mux for font ROM addresses and rgb
always @* begin
PIXEL = 3'b000;
if (p1) begin
// @todo Scores larger than 9!!!
char_addr = 7'h30 + PLAYER_ONE;
row_addr = (PIXEL_V - p1_v_start) >> 2;
bit_addr = (PIXEL_H - p1_h_start) >> 2;
if (font_bit)
PIXEL = 3'b111;
end else if (p2) begin
// @todo Scores larger than 9!!!
char_addr = 7'h30 + PLAYER_TWO;
row_addr = (PIXEL_V - p2_v_start) >> 2;
bit_addr = (PIXEL_H - p2_h_start) >> 2;
if (font_bit)
PIXEL = 3'b111;
end else begin
char_addr = 0;
row_addr = 0;
bit_addr = 0;
end
end
// Build the rom address of the current pixel.
assign rom_addr = {char_addr, row_addr};
// Get the on/off value of the bit at the current pixel from the rom.
assign font_bit = font_word[~bit_addr];
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
// Date : Mon Dec 01 03:09:56 2014
// Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// c:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_stub.v
// Design : clk_wiz_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_wiz_1(clk_in1, clk_out1, reset, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,reset,locked" */;
input clk_in1;
output clk_out1;
input reset;
output locked;
endmodule
|
`include "assert.vh"
`include "stack.vh"
module Stack_tb();
parameter WIDTH = 8;
parameter DEPTH = 1; // frames (exponential)
localparam MAX_STACK = (1 << DEPTH+1) - 1;
reg clk = 0;
reg reset;
reg [ 1:0] op;
reg [WIDTH-1:0] data;
wire [WIDTH-1:0] tos;
wire [1:0] status;
wire [1:0] error;
stack #(
.WIDTH(WIDTH),
.DEPTH(DEPTH)
)
dut(
.clk(clk),
.reset(reset),
.op(op),
.data(data),
.tos(tos),
.status(status),
.error(error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("stack_tb.vcd");
$dumpvars(0, Stack_tb);
// `status` is `empty` by default
`assert(status, `EMPTY);
// Underflow
op <= `POP;
data <= 0;
#2
`assert(error, `UNDERFLOW);
// Push
op <= `PUSH;
data <= 0;
#2
`assert(status, `NONE);
`assert(tos , 8'h00);
op <= `PUSH;
data <= 1;
#2
`assert(status, `NONE);
`assert(tos , 8'h01);
op <= `PUSH;
data <= 2;
#2
`assert(status, `FULL);
`assert(tos , 8'h02);
// Top of Stack
op <= `NONE;
#2
`assert(status, `FULL);
`assert(tos , 8'h02);
// Overflow
op <= `PUSH;
data <= 3;
#2
`assert(error, `OVERFLOW);
`assert(tos , 8'h02);
// Pop
op <= `POP;
data <= 0;
#2
`assert(status, `NONE);
`assert(tos , 8'h01);
op <= `POP;
data <= 0;
#2
`assert(status, `NONE);
`assert(tos , 8'h00);
op <= `POP;
data <= 0;
#2
`assert(status, `EMPTY);
// Replace
op <= `REPLACE;
data <= 4;
#2
`assert(error, `UNDERFLOW);
op <= `PUSH;
data <= 5;
#2
`assert(status, `NONE);
`assert(tos , 8'h05);
op <= `REPLACE;
data <= 6;
#2
`assert(status, `NONE);
`assert(tos , 8'h06);
op <= `NONE;
#2
`assert(status, `NONE);
`assert(tos , 8'h06);
// Reset
reset <= 1;
#2
reset <= 0;
`assert(status, `EMPTY);
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_2_V
`define SKY130_FD_SC_LS__FILL_2_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_2_V
|
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