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/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* XGMII control/data interleave
*/
module xgmii_interleave
(
input wire [63:0] input_xgmii_d,
input wire [7:0] input_xgmii_c,
output wire [72:0] output_xgmii_dc
);
assign output_xgmii_dc[7:0] = input_xgmii_d[7:0];
assign output_xgmii_dc[8] = input_xgmii_c[0];
assign output_xgmii_dc[16:9] = input_xgmii_d[15:8];
assign output_xgmii_dc[17] = input_xgmii_c[1];
assign output_xgmii_dc[25:18] = input_xgmii_d[23:16];
assign output_xgmii_dc[26] = input_xgmii_c[2];
assign output_xgmii_dc[34:27] = input_xgmii_d[31:24];
assign output_xgmii_dc[35] = input_xgmii_c[3];
assign output_xgmii_dc[43:36] = input_xgmii_d[39:32];
assign output_xgmii_dc[44] = input_xgmii_c[4];
assign output_xgmii_dc[52:45] = input_xgmii_d[47:40];
assign output_xgmii_dc[53] = input_xgmii_c[5];
assign output_xgmii_dc[61:54] = input_xgmii_d[55:48];
assign output_xgmii_dc[62] = input_xgmii_c[6];
assign output_xgmii_dc[70:63] = input_xgmii_d[63:56];
assign output_xgmii_dc[71] = input_xgmii_c[7];
endmodule
`resetall
|
module testbench (
CLOCK_50, // 50 MHz
//////////////////// LCD Module 16X2 ////////////////
LCD_ON, // LCD Power ON/OFF
LCD_BLON, // LCD Back Light ON/OFF
LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
LCD_EN, // LCD Enable
LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
LCD_DATA, // LCD Data bus 8 bits
debug_sw
);
input CLOCK_50; // 50 MHz
inout [7:0] LCD_DATA; // LCD Data bus 8 bits
output LCD_ON; // LCD Power ON/OFF
output LCD_BLON; // LCD Back Light ON/OFF
output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN; // LCD Enable
output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
input debug_sw;
wire DLY_RST;
wire [4:0] wire_lcd_ctrl;
reset_gen r0 (
.clock (CLOCK_50),
.reset (DLY_RST)
);
lcd_bridge u5 (
.clock (CLOCK_50),
.reset (DLY_RST),
.insert (debug_sw),
.new_record ({4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8}),
// LCD Side
.lcd_data (LCD_DATA),
.lcd_ctrl (wire_lcd_ctrl)
);
assign {LCD_RW, LCD_EN, LCD_RS, LCD_ON, LCD_BLON} = wire_lcd_ctrl;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O41A_FUNCTIONAL_PP_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41A_FUNCTIONAL_PP_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_clgen.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "spi_defines.v"
`include "timescale.v"
module spi_flash_clgen (clk_in, rst, go, enable, last_clk, clk_out, pos_edge, neg_edge);
parameter divider_len = 2;
parameter divider = 1;
parameter Tp = 1;
input clk_in; // input clock (system clock)
input rst; // reset
input enable; // clock enable
input go; // start transfer
input last_clk; // last clock
//input [spi_divider_len-1:0] divider; // clock divider (output clock is divided by this value)
output clk_out; // output clock
output pos_edge; // pulse marking positive edge of clk_out
output neg_edge; // pulse marking negative edge of clk_out
reg clk_out;
reg pos_edge;
reg neg_edge;
reg [divider_len-1:0] cnt; // clock counter
wire cnt_zero; // conter is equal to zero
wire cnt_one; // conter is equal to one
assign cnt_zero = cnt == {divider_len{1'b0}};
assign cnt_one = cnt == {{divider_len-1{1'b0}}, 1'b1};
// Counter counts half period
always @(posedge clk_in or posedge rst)
begin
if(rst)
cnt <= #Tp {divider_len{1'b1}};
else
begin
if(!enable || cnt_zero)
cnt <= #Tp divider;
else
cnt <= #Tp cnt - {{divider_len-1{1'b0}}, 1'b1};
end
end
// clk_out is asserted every other half period
always @(posedge clk_in or posedge rst)
begin
if(rst)
clk_out <= #Tp 1'b0;
else
clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
end
// Pos and neg edge signals
always @(posedge clk_in or posedge rst)
begin
if(rst)
begin
pos_edge <= #Tp 1'b0;
neg_edge <= #Tp 1'b0;
end
else
begin
pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
end
end
endmodule
|
// nios_dut_mm_interconnect_0_avalon_st_adapter_012.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_dut_mm_interconnect_0_avalon_st_adapter_012 #(
parameter inBitsPerSymbol = 130,
parameter inUsePackets = 0,
parameter inDataWidth = 130,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 130,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [129:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [129:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_dut_mm_interconnect_0_avalon_st_adapter_012_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_P_PP_PKG_SN_TB_V
`define SKY130_FD_SC_LP__UDP_DFF_P_PP_PKG_SN_TB_V
/**
* udp_dff$P_pp$PKG$sN: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_dff_p_pp_pkg_sn.v"
module top();
// Inputs are registered
reg D;
reg SLEEP_B;
reg NOTIFIER;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
NOTIFIER = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 NOTIFIER = 1'b0;
#80 SLEEP_B = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 KAPWR = 1'b1;
#180 NOTIFIER = 1'b1;
#200 SLEEP_B = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 KAPWR = 1'b0;
#300 NOTIFIER = 1'b0;
#320 SLEEP_B = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SLEEP_B = 1'b1;
#440 NOTIFIER = 1'b1;
#460 KAPWR = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SLEEP_B = 1'bx;
#560 NOTIFIER = 1'bx;
#580 KAPWR = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__udp_dff$P_pp$PKG$sN dut (.D(D), .SLEEP_B(SLEEP_B), .NOTIFIER(NOTIFIER), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_P_PP_PKG_SN_TB_V
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("return.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("return_tb.vcd");
$dumpvars(0, cpu_tb);
if(USE_64B) begin
#12
`assert(result, 42);
`assert(result_type, `i64);
`assert(result_empty, 0);
end
else begin
#12
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
/* Data read from RAM and displayed on one LED while others are a
* binary counter
*/
module top (
input clk,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5
);
parameter LOG2RAMDELAY = 20;
localparam BITS = 4;
localparam LOG2DELAY = LOG2RAMDELAY + 7;
reg [BITS+LOG2DELAY-1:0] counter = 0;
reg [BITS-1:0] outcnt;
wire bout;
reg enable = 0;
always @(posedge clk) begin
counter <= counter + 1;
outcnt <= counter >> LOG2DELAY;
enable <= counter[LOG2RAMDELAY];
end
memory m1 (clk, enable, bout);
assign LED1 = bout;
assign {LED2, LED3, LED4, LED5} = outcnt;
endmodule
module memory (
input clk,
input inc,
output bout
);
localparam DEPTH = 6;
localparam LEN = 1<<(DEPTH-1);
wire [15:0] data;
reg [DEPTH-1:0] cnt = 0;
// Morse code for "hello"
SB_RAM40_4K #(
.INIT_0(256'h0000000100000000000000010000000000000001000000010000000100000001),
.INIT_1(256'h0000000100010001000000010000000000000001000000010000000100010001),
.INIT_2(256'h0001000100000001000100010000000100010001000000000000000100000001),
.INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000001),
.INIT_4(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_5(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_6(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_7(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_8(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_9(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_A(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_B(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_C(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_D(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_E(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_F(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.READ_MODE(2'b01),
.WRITE_MODE(2'b01)
)
mem
(
.RADDR({ 5'b0, cnt}),
.RCLK(clk),
.RCLKE(1'b1),
.RDATA(data),
.RE(1'b1),
.WCLK(clk),
.WCLKE(1'b0)
);
always @(posedge inc) begin
cnt <= cnt + 1;
end
assign bout = data[0];
endmodule // memory
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXBP_SYMBOL_V
`define SKY130_FD_SC_HVL__DFXBP_SYMBOL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXBP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A311OI_FUNCTIONAL_PP_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311OI_FUNCTIONAL_PP_V |
/*
** -----------------------------------------------------------------------------**
** lens_flat.v
**
** Correction of lens+sensor vignetting. Initially it is just a quadratic function
** that can be improved later by a piece-linear table function T() of the calculated
** f(x,y)=p*(x-x0)^2 + q(y-yo)^2 + c.
** T(f(x,y)) can be used to approximate cos^4). or other vignetting functions
**
** This function - f(x,y) or T(f(x,y)) here deal with full sensor data before
** gamma-tables are applied and the data is compressed to 8 bits
**
** Copyright (C) 2008 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X333
** X333 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
/*
F2(x,y)=p*(x-x0)^2 + q(y-yo)^2 + c=
p*x^2 - (2*p*x0) * x + p* (x0*x0) + q*y^2 - (2*q*y0) * y + q* (y0*y0) + c=
p* x^2 - (2*p*x0) * x + q* y^2 -(2*q)* y + (p* (x0*x0)+q* (y0*y0) + c)
Final:
F2(X,Y)=p* x^2 - (2*p*x0) * x + q* y^2 -(2*q)* y + (p* (x0*x0)+q* (y0*y0) + c):
Ax(Y)= p
Bx(Y)=-(2*p)
F(0,Y)= q*y^2 - (2*q*y0) * y + (q* (y0*y0) + c + p* (x0*x0))
C= (q* (y0*y0) + c + p* (x0*x0));
BY= - (2*q*y0)
AY= q
AX= p
BX= -2*p*x0
*/
`timescale 1ns / 1ps
module lens_flat (sclk, /// system clock @negedge
wen, /// write LSW from di
di, /// [15:0] data in
pclk, /// pixel clock (@pclk)
fstart, // frame start - single clock (will have frame latency as coefficients are written after the fstart)
newline, // start of scan line - ahead of linerun
linerun, // active pixel output - latency will be = 4 clocks
bayer,
pixdi, // pixel data in, 16 bit unsigned
pixdo // pixel data out, 16 bit unsigned
);
input sclk;
input wen;
input [15:0] di;
input pclk;
input fstart;
input newline;
input linerun;
input [1:0] bayer;
input [15:0] pixdi;
output[15:0] pixdo;
// output [18:0] lens_corr;
reg [ 1:0] wen_d;
reg [23:0] did;
reg [23:0] didd;
// reg we_AA,we_AB,we_AC,we_BA,we_BB,we_BC,we_CA,we_CB,we_CC;
reg we_AX,we_BX,we_AY,we_BY,we_C;
reg we_scales;/// write additional individual per-color scales (17 bits each)
reg we_fatzero_in,we_fatzero_out; ///
reg we_post_scale;
//F(x,y)=Ax*x^2+Bx*x+Ay*y^2+By*y+C
reg [18:0] AX; /// Ax
reg [18:0] AY; /// Ax
reg [20:0] BX; /// Bx
reg [20:0] BY; /// By
reg [18:0] C; /// C
reg [16:0] scales[0:3]; // per-color coefficients
///AF: reg [16:0] scales_r;
reg [15:0] fatzero_in; /// zero level to subtract before multiplication
reg [15:0] fatzero_out; /// zero level to add after multiplication
reg [ 3:0] post_scale; /// shift product after first multiplier - maybe needed when using decimation
wire [18:0] FY; /// F(0,y)
wire [23:0] ERR_Y; /// running error for the first column
wire [18:0] FXY; /// F(x,y)
///AF: reg [18:0] FXY_sat;
reg [ 4:0] lens_corr_out; /// lens correction out valid (first clock from column0 )
/// copied form sensorpix353.v
reg bayer_nset;
reg bayer0_latched;
reg [1:0] color;
wire [35:0] mult_first_res;
reg [17:0] mult_first_scaled; /// scaled multiplication result (to use with decimation to make parabola 'sharper')
wire [35:0] mult_second_res;
reg [15:0] pixdo; /// output pixel data, 16 bits, saturated at positive
wire [20:0] pre_pixdo_with_zero= mult_second_res[35:15] + {{5{fatzero_out[15]}},fatzero_out[15:0]};
wire sync_bayer=linerun && ~lens_corr_out[0];
wire [17:0] pix_zero = {2'b0,pixdi[15:0]}-{{2{fatzero_in [15]}},fatzero_in [15:0]};
always @ (negedge sclk) begin
wen_d[1:0] <= {wen_d[0],wen};
if (wen) did[15: 0] <= di[15:0];
if (wen_d[0]) did[23:16] <= di[ 7:0];
didd[23:0] <= did[23:0];
we_AX <= wen_d[1] && (did[23:19]==5'h00); /// 00000
we_AY <= wen_d[1] && (did[23:19]==5'h01); /// 00001
we_C <= wen_d[1] && (did[23:19]==5'h02); /// 00010
we_BX <= wen_d[1] && (did[23:21]==3'h1 ); /// 001
we_BY <= wen_d[1] && (did[23:21]==3'h2 ); /// 010
we_scales <= wen_d[1] && (did[23:19]==5'h0c); /// 01100NN
we_fatzero_in <= wen_d[1] && (did[23:16]==8'h68); /// 01101000
we_fatzero_out <= wen_d[1] && (did[23:16]==8'h69); /// 01101001
we_post_scale <= wen_d[1] && (did[23:16]==8'h6a); /// 01101010
if (we_AX) AX[18:0] <= didd[18:0];
if (we_AY) AY[18:0] <= didd[18:0];
if (we_BX) BX[20:0] <= didd[20:0];
if (we_BY) BY[20:0] <= didd[20:0];
if (we_C) C[18:0] <= didd[18:0];
if (we_scales) scales[didd[18:17]] <= didd[16:0];
if (we_fatzero_in) fatzero_in [15:0] <= didd[15:0];
if (we_fatzero_out) fatzero_out[15:0] <= didd[15:0];
if (we_post_scale) post_scale [ 3:0] <= didd[ 3:0];
end
//reg color[1:0]
always @ (posedge pclk) begin
lens_corr_out[4:0]<={lens_corr_out[3:0],linerun};
bayer_nset <= !fstart && (bayer_nset || linerun);
bayer0_latched<= bayer_nset? bayer0_latched:bayer[0];
color[1:0] <= { bayer_nset? (sync_bayer ^ color[1]):bayer[1] ,
(bayer_nset &&(~sync_bayer))?~color[0]:bayer0_latched };
/// now scale the result (normally post_scale[2:0] ==1)
case (post_scale [2:0])
3'h0:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:33]) ? 18'h1ffff:mult_first_res[33:16]; /// only limit positive overflow
3'h1:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:32]) ? 18'h1ffff:mult_first_res[32:15];
3'h2:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:31]) ? 18'h1ffff:mult_first_res[31:14];
3'h3:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:30]) ? 18'h1ffff:mult_first_res[30:13];
3'h4:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:29]) ? 18'h1ffff:mult_first_res[29:12];
3'h5:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:28]) ? 18'h1ffff:mult_first_res[28:11];
3'h6:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:27]) ? 18'h1ffff:mult_first_res[27:10];
3'h7:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:26]) ? 18'h1ffff:mult_first_res[26: 9];
endcase
if (lens_corr_out[4]) pixdo[15:0] <= pre_pixdo_with_zero[20]? 16'h0: /// negative - use 0
((|pre_pixdo_with_zero[19:16])?16'hffff: ///>0xffff - limit by 0xffff
pre_pixdo_with_zero[15:0]);
end
MULT18X18SIO #(
.AREG(1), // Enable the input registers on the A port (1=on, 0=off)
.BREG(1), // Enable the input registers on the B port (1=on, 0=off)
.B_INPUT("DIRECT"), // B cascade input "DIRECT" or "CASCADE"
.PREG(1) // Enable the input registers on the P port (1=on, 0=off)
) i_mult_first (
.BCOUT(), // 18-bit cascade output
.P(mult_first_res[35:0]), // 36-bit multiplier output
// .A(FXY[17]?18'h1ffff:FXY[17:0]), // 18-bit multiplier input
.A((FXY[18]==FXY[17])?FXY[17:0]:(FXY[18]?18'h20000:18'h1ffff)), // 18-bit multiplier input
.B({1'b0,scales[~color[1:0]]}), // 18-bit multiplier input
.BCIN(18'b0), // 18-bit cascade input
.CEA(lens_corr_out[0]), // Clock enable input for the A port
.CEB(lens_corr_out[0]), // Clock enable input for the B port
.CEP(lens_corr_out[1]), // Clock enable input for the P port
.CLK(pclk), // Clock input
.RSTA(1'b0), // Synchronous reset input for the A port
.RSTB(1'b0), // Synchronous reset input for the B port
.RSTP(1'b0) // Synchronous reset input for the P port
);
MULT18X18SIO #(
.AREG(1), // Enable the input registers on the A port (1=on, 0=off)
.BREG(0), // Enable the input registers on the B port (1=on, 0=off)
.B_INPUT("DIRECT"), // B cascade input "DIRECT" or "CASCADE"
.PREG(1) // Enable the input registers on the P port (1=on, 0=off)
) i_mult_second (
.BCOUT(), // 18-bit cascade output
.P(mult_second_res[35:0]), // 36-bit multiplier output
.A(pix_zero[17:0]), // 18-bit multiplier input
.B(mult_first_scaled[17:0]), // 18-bit multiplier input - always positive
.BCIN(18'b0), // 18-bit cascade input
.CEA(lens_corr_out[2]), // Clock enable input for the A port
.CEB(lens_corr_out[0]), // Clock enable input for the B port
.CEP(lens_corr_out[3]), // Clock enable input for the P port
.CLK(pclk), // Clock input
.RSTA(1'b0), // Synchronous reset input for the A port
.RSTB(1'b0), // Synchronous reset input for the B port
.RSTP(1'b0) // Synchronous reset input for the P port
);
lens_flat_line #(.F_WIDTH(19), /// number of bits in the output result (signed)
.F_SHIFT(22), /// shift ~2*log2(width/2), for 4K width
.B_SHIFT(12), ///(<=F_SHIFT) shift b- coeff (12 is 2^12 - good for lines <4096, 1 output count per width)
.A_WIDTH(19), /// number of bits in a-coefficient (signed). Just to match the caller - MSBs will be anyway discarded
.B_WIDTH(21)) /// number of bits in b-coefficient (signed).
i_fy( .pclk(pclk), /// pixel clock
.first(fstart), /// initialize running parameters from the inputs (first column). Should be at least 1-cycle gap between "first" and first "next"
.next(newline), /// calcualte next pixel
.F0(C[18:0]), /// value of the output in the first column (before saturation), 18 bit, unsigned
.ERR0(24'b0), /// initial value of the running error (-2.0<err<+2.0), scaled by 2^22, so 24 bits
.A0(AY[18:0]), /// Ay
.B0(BY[20:0]), /// By, signed
.F(FY[18:0]),
.ERR(ERR_Y[23:0]));
lens_flat_line #(.F_WIDTH(19), /// number of bits in the output result
.F_SHIFT(22), /// shift ~2*log2(width/2), for 4K width
.B_SHIFT(12), ///(<=F_SHIFT) shift b- coeff (12 is 2^12 - good for lines <4096, 1 output count per width)
.A_WIDTH(19), /// number of bits in a-coefficient (unsigned). Just to match the caller - MSBs will be anyway discarded
.B_WIDTH(21)) /// number of bits in b-coefficient (signed).
i_fxy( .pclk(pclk), /// pixel clock
.first(newline), /// initialize running parameters from the inputs (first column). Should be at least 1-cycle gap between "first" and first "next"
.next(linerun), /// calcualte next pixel
.F0(FY[18:0]), /// value of the output in the first column (before saturation), 18 bit, unsigned
.ERR0(ERR_Y[23:0]), /// initial value of the running error (-2.0<err<+2.0), scaled by 2^22, so 24 bits
.A0(AX[18:0]), /// Ax(Y), signed
.B0(BX[20:0]), /// Bx(Y), signed
.F(FXY[18:0]),
.ERR());
endmodule
module lens_flat_line(
pclk, /// pixel clock
first, /// initialize running parameters from the inputs (first column). Should be at least 1-cycle gap between "first" and first "next"
next, /// calcualte next pixel
F0, /// value of the output in the first column (before saturation), 18 bit, unsigned
ERR0, /// initial value of the running error (-2.0<err<+2.0), scaled by 2^22, so 24 bits
A0, /// a - fixed for negative values
B0,
F,
ERR); // output - 18 bits, unsigned (not saturated)
parameter F_WIDTH= 18; /// number of bits in the output result
parameter F_SHIFT=22; /// shift ~2*log2(width/2), for 4K width
parameter B_SHIFT=12; ///(<=F_SHIFT) shift b- coeff (12 is 2^12 - good for lines <4096, 1 output count per width)
parameter A_WIDTH=18; /// number of bits in a-coefficient (unsigned). Just to match the caller - MSBs will be anyway discarded
parameter B_WIDTH=21; // number of bits in b-coefficient (signed).
parameter DF_WIDTH=B_WIDTH-F_SHIFT+B_SHIFT; //21-22+12 11; /// number of bits in step of F between (df/dx), signed
input pclk;
input first;
input next;
input [F_WIDTH-1:0] F0;
input [F_SHIFT+1:0] ERR0;
input [A_WIDTH-1:0] A0;
input [B_WIDTH-1:0] B0;
output [F_WIDTH-1:0] F;
output [F_SHIFT+1:0] ERR;
reg [F_SHIFT+1:0] ERR; /// running difference between ax^2+bx+c and y, scaled by 2^22, signed, should never overflow
reg [F_SHIFT+1:0] ApB; /// a+b, scaled by 2 ^22, high bits ignored (not really needed - can use ApB0
reg [F_SHIFT+1:1] A2X; /// running value for 2*a*x, scaled by 2^22, high bits ignored
reg [(DF_WIDTH)-1:0] dF; /// or [9:0] - anyway only lower bits will be used in comparison operations
reg [F_WIDTH-1:0] F; /// Running value of the output
reg next_d, first_d; // delayed by 1 cycle
reg [F_WIDTH-1:0] F1;
reg [A_WIDTH-1:0] A;
wire [F_SHIFT+1:0] preERR={A2X[F_SHIFT+1:1],1'b0}+ApB[F_SHIFT+1:0]-{dF[1:0],{F_SHIFT{1'b0}}};
/// Increment can be 0 or +/-1, depending on the required correction
/// It relies on the facts that:
/// - the output F(x) is integer
/// - dF/dx does not chnage by more than +/-1 when x is incremented (abs (d2f/dx2)<1), so the algorithm to get
/// y=round(F(x)) is simple :
/// At each step x, try to chnage y by the same amount as was done at the previous step, adding/subtracting 1 if needed
/// and updating the new running error (difference between the current (integer) value of y and the precise value of F(x)
/// This error is calculated here with the 22 binary digits after the point.
///f=ax^2+bx+c
///
///1) f <= f+ df +1
/// df <= df+1;
/// err+= (2ax+a+b-df) -1
///2) f <= f+ df
/// err+= (2ax+a+b-df)
///3) f <= f+ df -1
/// df <= df-1;
/// err+= (2ax+a+b-df) +1
///preERR->inc:
/// 100 -> 11
/// 101 -> 11
/// 110 -> 11
/// 111 -> 00
/// 000 -> 00
/// 001 -> 01
/// 010 -> 01
/// 011 -> 01
wire [1:0] inc= {preERR[F_SHIFT+1] & (~preERR[F_SHIFT] | ~preERR[F_SHIFT-1]),
(preERR[F_SHIFT+1:F_SHIFT-1] != 3'h0) &
(preERR[F_SHIFT+1:F_SHIFT-1] != 3'h7)};
always @(posedge pclk) begin
first_d <=first;
next_d <=next;
if (first) begin
F1 [F_WIDTH-1:0] <= F0[ F_WIDTH-1:0];
dF[(DF_WIDTH)-1:0] <= B0[B_WIDTH-1: (F_SHIFT-B_SHIFT)];
ERR[F_SHIFT+1:0] <= ERR0[F_SHIFT+1:0];
ApB[F_SHIFT+1:0] <= {{F_SHIFT+2-A_WIDTH{A0[A_WIDTH-1]}},A0[A_WIDTH-1:0]}+{B0[B_WIDTH-1:0],{F_SHIFT-B_SHIFT{1'b0}}}; /// high bits from B will be discarded
A [A_WIDTH-1:0] <= A0[A_WIDTH-1:0];
end else if (next) begin
dF[(DF_WIDTH)-1:0] <= dF[(DF_WIDTH)-1:0]+{{((DF_WIDTH)-1){inc[1]}},inc[1:0]};
ERR[F_SHIFT-1:0]<= preERR[F_SHIFT-1:0];
ERR[F_SHIFT+1:F_SHIFT]<= preERR[F_SHIFT+1:F_SHIFT]-inc[1:0];
end
if (first_d) F[F_WIDTH-1:0] <= F1[ F_WIDTH-1:0];
else if (next_d) F[F_WIDTH-1:0] <= F[F_WIDTH-1:0]+{{(F_WIDTH-(DF_WIDTH)){dF[(DF_WIDTH)-1]}},dF[(DF_WIDTH)-1:0]};
if (first_d) A2X[F_SHIFT+1:1] <= {{F_SHIFT+2-A_WIDTH{A[A_WIDTH-1]}},A[A_WIDTH-1:0]};
else if (next) A2X[F_SHIFT+1:1] <= A2X[F_SHIFT+1:1] + {{F_SHIFT+2-A_WIDTH{A[A_WIDTH-1]}},A[A_WIDTH-1:0]};
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Name: Andrew Camps, Jason Tran
// Create Date: 09/17/2017 05:35:13 PM
// Module Name: CIRCUIT1
//////////////////////////////////////////////////////////////////////////////////
module CIRCUIT6(a, b, c, d, e, f, g, h, num, Clk, Rst, avg);
input Clk, Rst;
input [15:0] a, b, c, d, e, f, g, h, num;
output [15:0] avg;
reg [15:0] r1, r2, r3, r4, r5, r6, r7;
wire [15:0] avgwire;
wire [31:0] t1, t2, t3, t4, t5, t6, t7;
ADD #(16) add1(a, b, t1);
ADD #(16) add2(r1, c, t2);
ADD #(16) add3(r2, d, t3);
ADD #(16) add4(r3, e, t4);
ADD #(16) add5(r4, f, t5);
ADD #(16) add6(r5, g, t6);
ADD #(16) add7(r6, h, t7);
DIV #(16) div1(r7, num, avgwire);
REG #(16) reg8(avgwire, Clk, Rst, avg);
always @(r1, r2, r3, r4, r5, r6, r7) begin
r1 <= t1;
r2 <= t2;
r3 <= t3;
r4 <= t4;
r5 <= t5;
r6 <= t6;
r7 <= t7;
end
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:26:17 04/26/2015
// Design Name:
// Module Name: videosyncs
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module videosyncs (
input wire clk,
input wire [2:0] rin,
input wire [2:0] gin,
input wire [1:0] bin,
output reg [2:0] rout,
output reg [2:0] gout,
output reg [1:0] bout,
output reg hs,
output reg vs,
output wire [10:0] hc,
output wire [10:0] vc
);
/* http://www.abramovbenjamin.net/calc.html */
// VGA 640x480@60Hz,25MHz
parameter htotal = 800;
parameter vtotal = 524;
parameter hactive = 640;
parameter vactive = 480;
parameter hfrontporch = 16;
parameter hsyncpulse = 96;
parameter vfrontporch = 11;
parameter vsyncpulse = 2;
parameter hsyncpolarity = 0;
parameter vsyncpolarity = 0;
reg [10:0] hcont = 0;
reg [10:0] vcont = 0;
reg active_area;
assign hc = hcont;
assign vc = vcont;
always @(posedge clk) begin
if (hcont == htotal-1) begin
hcont <= 0;
if (vcont == vtotal-1) begin
vcont <= 0;
end
else begin
vcont <= vcont + 1;
end
end
else begin
hcont <= hcont + 1;
end
end
always @* begin
if (hcont>=0 && hcont<hactive && vcont>=0 && vcont<vactive)
active_area = 1'b1;
else
active_area = 1'b0;
if (hcont>=(hactive+hfrontporch) && hcont<(hactive+hfrontporch+hsyncpulse))
hs = hsyncpolarity;
else
hs = ~hsyncpolarity;
if (vcont>=(vactive+vfrontporch) && vcont<(vactive+vfrontporch+vsyncpulse))
vs = vsyncpolarity;
else
vs = ~vsyncpolarity;
end
always @* begin
if (active_area) begin
gout = gin;
rout = rin;
bout = bin;
end
else begin
gout = 3'h00;
rout = 3'h00;
bout = 2'h00;
end
end
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:37:23 10/06/2014
// Design Name:
// Module Name: uart
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart_rx(clk, reset, wren, rden, din, dout, rxin, addr);
input clk, reset, wren, rden;
input [7:0] din;
output [8:0] dout;
input rxin; //serial data in
input [2:0] addr;
reg [8:0] dout, frame_error;
reg [9:0] shift;
reg [7:0] control;
reg wr_baud, rd_baud, wr_fifo, rd_fifo, wr_control;
reg ld_shift, stop, count, finish, rd_shift, bittime;
reg [3:0] bittimer, bitcounter;
reg [2:0] nstate, pstate;
reg in_one, in_two, hold, frame_ready, loaded, load, clr_load;
`define period 3'b100
`define rx_reg 3'b101
`define control 3'b111
`define RXEN control[0]
`define DATARDY control[1]
`define OVERRUN control[2]
`define ERROR frame_error[8]
`define STOP shift[9]
`define START shift[0]
`define HOLD 3'b000
`define WAIT 3'b001
`define SHIFT1 3'b010
`define SHIFT2 3'b011
`define LD_FIFO 3'b100
`define RX_NOT_READY 3'b101
wire [7:0] dout_baud;
wire [8:0] dout_fifo;
wire baud, full, empty;
parameter PERIOD = 8'h1A; //must have this initial value
//baud generator
//module baudgen(wren, rden, reset, din, clk, sclr, baud, dout);
//input wren, rden, reset, clk, sclr;
//input [7:0] din;
//output baud;
//output [7:0] dout;
baudgen #(.PERIOD(PERIOD)) baud1(
.wren (wr_baud),
.rden (rd_baud),
.reset (reset),
.din (din),
.clk (clk),
.stop (stop),
.baud (baud),
.dout (dout_baud)
);
//fifo ipcore
//input clk;
//input srst;
//input [8 : 0] din;
//input wr_en;
//input rd_en;
//output [8 : 0] dout;
//output full;
//output empty;
fifo_rx fifo1(
.clk (clk),
.srst (hold),
.din (frame_error),
.wr_en (wr_fifo),
.rd_en (rd_fifo),
.dout (dout_fifo),
.full (full),
.empty (empty)
);
// input flip flops
always @(posedge clk) begin
//first flip flop
in_one <= rxin;
//second flip flop
in_two <= in_one;
end
// shift register
always @(posedge clk or posedge reset) begin
if(reset) begin
shift <= 10'b1111111111;
load = 0;
end
else begin
if(ld_shift) begin
shift <= {in_two, shift[9:1]};
load = 1;
end
else
load = 0;
end
end
// loaded flag
always @(negedge clk or posedge reset) begin
if(reset) begin
loaded = 0;
end
else begin
if(load)
loaded = 1;
if(clr_load)
loaded = 0;
end
end
// frame check
always @(posedge clk or posedge reset) begin
if(reset) begin
frame_error <= 8'b00000000;
frame_ready <= 0;
end
else begin
if(rd_shift)begin
frame_error[7:0] <= shift[8:1];
if(`START | ~`STOP)
`ERROR <= 1;
else
`ERROR <= 0;
frame_ready <= 1;
end
else
frame_ready <= 0;
end
end
//address write
always @* begin
wr_baud = 0;
wr_control = 0;
case(addr)
`period: begin
if(wren)
wr_baud = 1;
end
`control: begin
if(wren)
wr_control = 1;
end
endcase
end
//address read
always @* begin
rd_baud = 0;
rd_fifo = 0;
dout = 9'b000000000;
case(addr)
`period: begin
if(rden)
rd_baud = 1;
dout = dout_baud;
end
`rx_reg: begin
if(rden)
rd_fifo = 1;
dout = dout_fifo;
end
`control: begin
if(rden)
dout = control;
end
endcase
end
// control register
always @(posedge clk or posedge reset) begin
if(reset)
control[7:0] <= 8'b00000000;
else begin
`DATARDY <= ~empty;
if(wr_control)
control[0] <= din[0];
if(frame_ready & full)
`OVERRUN <= 1;
if(~`RXEN) begin
`DATARDY <= 0;
`OVERRUN <= 0;
end
end
end
// bittimer
always @(posedge baud or posedge reset) begin
if(reset)
bittimer <= 4'b0000;
else begin
if(bittime)
bittimer <= bittimer + 1;
end
end
// bitcounter
always @(posedge clk or posedge reset) begin
if(reset)begin
bitcounter <= 4'b0000;
end
else begin
if(count)
bitcounter <= bitcounter + 1;
if(finish)
bitcounter <= 4'b0000;
end
end
// set state during startup.
always @(posedge clk or posedge reset) begin
if (reset)
pstate <= `HOLD;
else begin
pstate <= nstate;
if(`OVERRUN)
pstate <= `RX_NOT_READY;
end
end
//fsm
always @* begin
hold = 0;
ld_shift = 0; clr_load = 0;
stop = 0; count = 0; finish = 0;
bittime = 0; rd_shift = 0; wr_fifo = 0;
nstate = pstate;
case (pstate)
`HOLD: begin
hold = 1;
stop = 1;
if(`RXEN == 1)
nstate = `WAIT;
end
`WAIT: begin
stop = 1;
if(~rxin) begin
stop = 0;
nstate = `SHIFT1;
end
end
`SHIFT1: begin
if(bitcounter == 4'b1010) begin
nstate = `LD_FIFO;
finish = 1;
rd_shift = 1;
end
else begin
if(baud)
nstate = `SHIFT2;
bittime = 1;
end
end
`SHIFT2: begin
bittime = 1;
if(bittimer == 4'b1000 & ~loaded)
ld_shift = 1;
if(~baud & (bittimer == 4'b0000)) begin
count = 1;
clr_load = 1;
nstate = `SHIFT1;
end
end
`LD_FIFO: begin
wr_fifo = 1;
nstate = `WAIT;
end
`RX_NOT_READY: begin
if(~`OVERRUN)
nstate = `HOLD;
end
endcase
end
endmodule
|
// hub_mem
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
// Andy Silverman 20140903 Provide fully standard Propeller configuration including video rom and full math tables, 32K RAM
//
// Magnus Karlsson 20140818 RAM is now 64KB
//
// RR20140816 ROM to use new unscrambled code and preset with $readmemh
// ROM is now 4KB ($F000..$FFFF) and preset with interpreter/booter/runner
// RAM may be expanded to fill available space up to 60KB
// RR20140816 Bigger Hub RAM & No ROM
// RAM is 48KB and remaps 48-64KB to 32-48KB
module hub_mem
(
input clk_cog,
input ena_bus,
input w,
input [3:0] wb,
input [13:0] a,
input [31:0] d,
output [31:0] q
);
// 8192 x 32 ram with byte-write enables ($0000..$7FFF)
reg [7:0] ram3 [8191:0];
reg [7:0] ram2 [8191:0];
reg [7:0] ram1 [8191:0];
reg [7:0] ram0 [8191:0];
reg [7:0] ram_q3;
reg [7:0] ram_q2;
reg [7:0] ram_q1;
reg [7:0] ram_q0;
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[3])
ram3[a[12:0]] <= d[31:24];
if (ena_bus && !a[13])
ram_q3 <= ram3[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[2])
ram2[a[12:0]] <= d[23:16];
if (ena_bus && !a[13])
ram_q2 <= ram2[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[1])
ram1[a[12:0]] <= d[15:8];
if (ena_bus && !a[13])
ram_q1 <= ram1[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[0])
ram0[a[12:0]] <= d[7:0];
if (ena_bus && !a[13])
ram_q0 <= ram0[a[12:0]];
end
// 4096 x 32 rom containing character definitions ($8000..$BFFF)
reg [31:0] rom_low [4095:0];
reg [31:0] rom_low_q;
// 4096 x 32 rom containing sin table, log table, booter, and interpreter ($C000..$FFFF)
reg [31:0] rom_high [4095:0];
reg [31:0] rom_high_q;
// pre-load ROM
initial
begin
$readmemh ("P8X32A_ROM_FONT.spin", rom_low);
$readmemh ("ROM_$C000-$FFFF_UNSCRAMBLED.spin", rom_high);
end
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b10)
rom_low_q <= rom_low[a[11:0]];
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b11)
rom_high_q <= rom_high[a[11:0]];
// memory output mux
reg [1:0] mem;
always @(posedge clk_cog)
if (ena_bus)
mem <= a[13:12];
assign q = !mem[1] ? {ram_q3, ram_q2, ram_q1, ram_q0}
: !mem[0] ? rom_low_q // comment out this line for DE0-Nano (sacrifices character rom to fit device)
: rom_high_q;
endmodule
|
module register_file
(
input clk, rst, w_en,
input [3:0] addr_a, addr_b, addr_c, addr_d,
input [15:0] data_c,
output reg [15:0] data_a, data_b, data_d
);
//`define addr_size 4
wire w_en0, w_en1, w_en2, w_en3, w_en4, w_en5, w_en6, w_en7, w_en8, w_en9, w_enA, w_enB, w_enC, w_enD, w_enE, w_enF;
wire [15:0] data0, data1, data2, data3, data4, data5, data6, data7, data8, data9, dataA, dataB, dataC, dataD, dataE, dataF;
register register0(clk, rst ,w_en0, data_c, data0);
register register1(clk, rst ,w_en1, data_c, data1);
register register2(clk, rst ,w_en2, data_c, data2);
register register3(clk, rst ,w_en3, data_c, data3);
register register4(clk, rst ,w_en4, data_c, data4);
register register5(clk, rst ,w_en5, data_c, data5);
register register6(clk, rst ,w_en6, data_c, data6);
register register7(clk, rst ,w_en7, data_c, data7);
register register8(clk, rst ,w_en8, data_c, data8);
register register9(clk, rst ,w_en9, data_c, data9);
register register10(clk, rst ,w_enA, data_c, dataA);
register register11(clk, rst ,w_enB, data_c, dataB);
register register12(clk, rst ,w_enC, data_c, dataC);
register register13(clk, rst ,w_enD, data_c, dataD);
register register14(clk, rst ,w_enE, data_c, dataE);
register register15(clk, rst ,w_enF, data_c, dataF);
assign w_en0 = (addr_c == 4'h0) & w_en ? 1'b1 : 1'b0;
assign w_en1 = (addr_c == 4'h1) & w_en ? 1'b1 : 1'b0;
assign w_en2 = (addr_c == 4'h2) & w_en ? 1'b1 : 1'b0;
assign w_en3 = (addr_c == 4'h3) & w_en ? 1'b1 : 1'b0;
assign w_en4 = (addr_c == 4'h4) & w_en ? 1'b1 : 1'b0;
assign w_en5 = (addr_c == 4'h5) & w_en ? 1'b1 : 1'b0;
assign w_en6 = (addr_c == 4'h6) & w_en ? 1'b1 : 1'b0;
assign w_en7 = (addr_c == 4'h7) & w_en ? 1'b1 : 1'b0;
assign w_en8 = (addr_c == 4'h8) & w_en ? 1'b1 : 1'b0;
assign w_en9 = (addr_c == 4'h9) & w_en ? 1'b1 : 1'b0;
assign w_enA = (addr_c == 4'ha) & w_en ? 1'b1 : 1'b0;
assign w_enB = (addr_c == 4'hb) & w_en ? 1'b1 : 1'b0;
assign w_enC = (addr_c == 4'hc) & w_en ? 1'b1 : 1'b0;
assign w_enD = (addr_c == 4'hd) & w_en ? 1'b1 : 1'b0;
assign w_enE = (addr_c == 4'he) & w_en ? 1'b1 : 1'b0;
assign w_enF = (addr_c == 4'hf) & w_en ? 1'b1 : 1'b0;
always@(*) begin
case(addr_a)
4'h0:
data_a = data0;
4'h1:
data_a = data1;
4'h2:
data_a = data2;
4'h3:
data_a = data3;
4'h4:
data_a = data4;
4'h5:
data_a = data5;
4'h6:
data_a = data6;
4'h7:
data_a = data7;
4'h8:
data_a = data8;
4'h9:
data_a = data9;
4'ha:
data_a = dataA;
4'hb:
data_a = dataB;
4'hc:
data_a = dataC;
4'hd:
data_a = dataD;
4'he:
data_a = dataE;
4'hf:
data_a = dataF;
endcase
case(addr_b)
4'h0:
data_b = data0;
4'h1:
data_b = data1;
4'h2:
data_b = data2;
4'h3:
data_b = data3;
4'h4:
data_b = data4;
4'h5:
data_b = data5;
4'h6:
data_b = data6;
4'h7:
data_b = data7;
4'h8:
data_b = data8;
4'h9:
data_b = data9;
4'ha:
data_b = dataA;
4'hb:
data_b = dataB;
4'hc:
data_b = dataC;
4'hd:
data_b = dataD;
4'he:
data_b = dataE;
4'hf:
data_b = dataF;
endcase
case(addr_d)
4'h0:
data_d = data0;
4'h1:
data_d = data1;
4'h2:
data_d = data2;
4'h3:
data_d = data3;
4'h4:
data_d = data4;
4'h5:
data_d = data5;
4'h6:
data_d = data6;
4'h7:
data_d = data7;
4'h8:
data_d = data8;
4'h9:
data_d = data9;
4'ha:
data_d = dataA;
4'hb:
data_d = dataB;
4'hc:
data_d = dataC;
4'hd:
data_d = dataD;
4'he:
data_d = dataE;
4'hf:
data_d = dataF;
endcase
end
endmodule
|
/*
Copyright (c) 2014-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "XILINX"
)
(
/*
* Clock: 156.25MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* Ethernet: QSFP28
*/
input wire qsfp0_tx_clk_1,
input wire qsfp0_tx_rst_1,
output wire [63:0] qsfp0_txd_1,
output wire [7:0] qsfp0_txc_1,
input wire qsfp0_rx_clk_1,
input wire qsfp0_rx_rst_1,
input wire [63:0] qsfp0_rxd_1,
input wire [7:0] qsfp0_rxc_1,
input wire qsfp0_tx_clk_2,
input wire qsfp0_tx_rst_2,
output wire [63:0] qsfp0_txd_2,
output wire [7:0] qsfp0_txc_2,
input wire qsfp0_rx_clk_2,
input wire qsfp0_rx_rst_2,
input wire [63:0] qsfp0_rxd_2,
input wire [7:0] qsfp0_rxc_2,
input wire qsfp0_tx_clk_3,
input wire qsfp0_tx_rst_3,
output wire [63:0] qsfp0_txd_3,
output wire [7:0] qsfp0_txc_3,
input wire qsfp0_rx_clk_3,
input wire qsfp0_rx_rst_3,
input wire [63:0] qsfp0_rxd_3,
input wire [7:0] qsfp0_rxc_3,
input wire qsfp0_tx_clk_4,
input wire qsfp0_tx_rst_4,
output wire [63:0] qsfp0_txd_4,
output wire [7:0] qsfp0_txc_4,
input wire qsfp0_rx_clk_4,
input wire qsfp0_rx_rst_4,
input wire [63:0] qsfp0_rxd_4,
input wire [7:0] qsfp0_rxc_4,
input wire qsfp1_tx_clk_1,
input wire qsfp1_tx_rst_1,
output wire [63:0] qsfp1_txd_1,
output wire [7:0] qsfp1_txc_1,
input wire qsfp1_rx_clk_1,
input wire qsfp1_rx_rst_1,
input wire [63:0] qsfp1_rxd_1,
input wire [7:0] qsfp1_rxc_1,
input wire qsfp1_tx_clk_2,
input wire qsfp1_tx_rst_2,
output wire [63:0] qsfp1_txd_2,
output wire [7:0] qsfp1_txc_2,
input wire qsfp1_rx_clk_2,
input wire qsfp1_rx_rst_2,
input wire [63:0] qsfp1_rxd_2,
input wire [7:0] qsfp1_rxc_2,
input wire qsfp1_tx_clk_3,
input wire qsfp1_tx_rst_3,
output wire [63:0] qsfp1_txd_3,
output wire [7:0] qsfp1_txc_3,
input wire qsfp1_rx_clk_3,
input wire qsfp1_rx_rst_3,
input wire [63:0] qsfp1_rxd_3,
input wire [7:0] qsfp1_rxc_3,
input wire qsfp1_tx_clk_4,
input wire qsfp1_tx_rst_4,
output wire [63:0] qsfp1_txd_4,
output wire [7:0] qsfp1_txc_4,
input wire qsfp1_rx_clk_4,
input wire qsfp1_rx_rst_4,
input wire [63:0] qsfp1_rxd_4,
input wire [7:0] qsfp1_rxc_4
);
// AXI between MAC and Ethernet modules
wire [63:0] rx_axis_tdata;
wire [7:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [63:0] tx_axis_tdata;
wire [7:0] tx_axis_tkeep;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [63:0] rx_eth_payload_axis_tdata;
wire [7:0] rx_eth_payload_axis_tkeep;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [63:0] tx_eth_payload_axis_tdata;
wire [7:0] tx_eth_payload_axis_tkeep;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [63:0] rx_ip_payload_axis_tdata;
wire [7:0] rx_ip_payload_axis_tkeep;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [63:0] tx_ip_payload_axis_tdata;
wire [7:0] tx_ip_payload_axis_tkeep;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [63:0] rx_udp_payload_axis_tdata;
wire [7:0] rx_udp_payload_axis_tkeep;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [63:0] tx_udp_payload_axis_tdata;
wire [7:0] tx_udp_payload_axis_tkeep;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [63:0] rx_fifo_udp_payload_axis_tdata;
wire [7:0] rx_fifo_udp_payload_axis_tkeep;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [63:0] tx_fifo_udp_payload_axis_tdata;
wire [7:0] tx_fifo_udp_payload_axis_tkeep;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tkeep = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
valid_last <= tx_udp_payload_axis_tvalid;
if (tx_udp_payload_axis_tvalid && !valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
end
end
end
assign qsfp0_txd_2 = 64'h0707070707070707;
assign qsfp0_txc_2 = 8'hff;
assign qsfp0_txd_3 = 64'h0707070707070707;
assign qsfp0_txc_3 = 8'hff;
assign qsfp0_txd_4 = 64'h0707070707070707;
assign qsfp0_txc_4 = 8'hff;
assign qsfp1_txd_1 = 64'h0707070707070707;
assign qsfp1_txc_1 = 8'hff;
assign qsfp1_txd_2 = 64'h0707070707070707;
assign qsfp1_txc_2 = 8'hff;
assign qsfp1_txd_3 = 64'h0707070707070707;
assign qsfp1_txc_3 = 8'hff;
assign qsfp1_txd_4 = 64'h0707070707070707;
assign qsfp1_txc_4 = 8'hff;
eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(qsfp0_rx_clk_1),
.rx_rst(qsfp0_rx_rst_1),
.tx_clk(qsfp0_tx_clk_1),
.tx_rst(qsfp0_tx_rst_1),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.xgmii_rxd(qsfp0_rxd_1),
.xgmii_rxc(qsfp0_rxc_1),
.xgmii_txd(qsfp0_txd_1),
.xgmii_txc(qsfp0_txc_1),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
);
eth_axis_rx #(
.DATA_WIDTH(64)
)
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx #(
.DATA_WIDTH(64)
)
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tkeep(tx_axis_tkeep),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete_64
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(1'b0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
`resetall
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file sdp_ram_10x14_11x7.v when simulating
// the core, sdp_ram_10x14_11x7. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module sdp_ram_10x14_11x7(
clka,
dina,
addra,
wea,
clkb,
addrb,
doutb);
input clka;
input [13 : 0] dina;
input [9 : 0] addra;
input [0 : 0] wea;
input clkb;
input [10 : 0] addrb;
output [6 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V2_8 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex5"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_SSRA(0),
.C_HAS_SSRB(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(14),
.C_READ_WIDTH_B(7),
.C_SIM_COLLISION_CHECK("ALL"),
.C_SINITA_VAL("0"),
.C_SINITB_VAL("0"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_RAMB16BWER_RST_BHV(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(14),
.C_WRITE_WIDTH_B(7),
.C_XDEVICEFAMILY("virtex5"))
inst (
.CLKA(clka),
.DINA(dina),
.ADDRA(addra),
.WEA(wea),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.ENA(),
.REGCEA(),
.SSRA(),
.DOUTA(),
.DINB(),
.ENB(),
.REGCEB(),
.WEB(),
.SSRB(),
.DBITERR(),
.SBITERR());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of sdp_ram_10x14_11x7 is "black_box"
endmodule
|
// nios_system_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 186 at 2016.05.04.10:35:24
`timescale 1 ps / 1 ps
module nios_system_mm_interconnect_0 (
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire nios2_qsys_0_reset_reset_bridge_in_reset_reset, // nios2_qsys_0_reset_reset_bridge_in_reset.reset
input wire [18:0] nios2_qsys_0_data_master_address, // nios2_qsys_0_data_master.address
output wire nios2_qsys_0_data_master_waitrequest, // .waitrequest
input wire [3:0] nios2_qsys_0_data_master_byteenable, // .byteenable
input wire nios2_qsys_0_data_master_read, // .read
output wire [31:0] nios2_qsys_0_data_master_readdata, // .readdata
input wire nios2_qsys_0_data_master_write, // .write
input wire [31:0] nios2_qsys_0_data_master_writedata, // .writedata
input wire nios2_qsys_0_data_master_debugaccess, // .debugaccess
input wire [18:0] nios2_qsys_0_instruction_master_address, // nios2_qsys_0_instruction_master.address
output wire nios2_qsys_0_instruction_master_waitrequest, // .waitrequest
input wire nios2_qsys_0_instruction_master_read, // .read
output wire [31:0] nios2_qsys_0_instruction_master_readdata, // .readdata
output wire [1:0] alu_a_s1_address, // alu_a_s1.address
output wire alu_a_s1_write, // .write
input wire [31:0] alu_a_s1_readdata, // .readdata
output wire [31:0] alu_a_s1_writedata, // .writedata
output wire alu_a_s1_chipselect, // .chipselect
output wire [1:0] alu_b_s1_address, // alu_b_s1.address
output wire alu_b_s1_write, // .write
input wire [31:0] alu_b_s1_readdata, // .readdata
output wire [31:0] alu_b_s1_writedata, // .writedata
output wire alu_b_s1_chipselect, // .chipselect
output wire [1:0] alu_carry_out_s1_address, // alu_carry_out_s1.address
input wire [31:0] alu_carry_out_s1_readdata, // .readdata
output wire [1:0] alu_control_s1_address, // alu_control_s1.address
output wire alu_control_s1_write, // .write
input wire [31:0] alu_control_s1_readdata, // .readdata
output wire [31:0] alu_control_s1_writedata, // .writedata
output wire alu_control_s1_chipselect, // .chipselect
output wire [1:0] alu_negative_s1_address, // alu_negative_s1.address
input wire [31:0] alu_negative_s1_readdata, // .readdata
output wire [1:0] alu_out_s1_address, // alu_out_s1.address
input wire [31:0] alu_out_s1_readdata, // .readdata
output wire [1:0] alu_overflow_s1_address, // alu_overflow_s1.address
input wire [31:0] alu_overflow_s1_readdata, // .readdata
output wire [1:0] alu_zero_s1_address, // alu_zero_s1.address
input wire [31:0] alu_zero_s1_readdata, // .readdata
output wire [1:0] hex_0_s1_address, // hex_0_s1.address
output wire hex_0_s1_write, // .write
input wire [31:0] hex_0_s1_readdata, // .readdata
output wire [31:0] hex_0_s1_writedata, // .writedata
output wire hex_0_s1_chipselect, // .chipselect
output wire [1:0] hex_1_s1_address, // hex_1_s1.address
output wire hex_1_s1_write, // .write
input wire [31:0] hex_1_s1_readdata, // .readdata
output wire [31:0] hex_1_s1_writedata, // .writedata
output wire hex_1_s1_chipselect, // .chipselect
output wire [1:0] hex_2_s1_address, // hex_2_s1.address
output wire hex_2_s1_write, // .write
input wire [31:0] hex_2_s1_readdata, // .readdata
output wire [31:0] hex_2_s1_writedata, // .writedata
output wire hex_2_s1_chipselect, // .chipselect
output wire [1:0] hex_3_s1_address, // hex_3_s1.address
output wire hex_3_s1_write, // .write
input wire [31:0] hex_3_s1_readdata, // .readdata
output wire [31:0] hex_3_s1_writedata, // .writedata
output wire hex_3_s1_chipselect, // .chipselect
output wire [1:0] hex_4_s1_address, // hex_4_s1.address
output wire hex_4_s1_write, // .write
input wire [31:0] hex_4_s1_readdata, // .readdata
output wire [31:0] hex_4_s1_writedata, // .writedata
output wire hex_4_s1_chipselect, // .chipselect
output wire [1:0] hex_5_s1_address, // hex_5_s1.address
output wire hex_5_s1_write, // .write
input wire [31:0] hex_5_s1_readdata, // .readdata
output wire [31:0] hex_5_s1_writedata, // .writedata
output wire hex_5_s1_chipselect, // .chipselect
output wire [0:0] jtag_uart_0_avalon_jtag_slave_address, // jtag_uart_0_avalon_jtag_slave.address
output wire jtag_uart_0_avalon_jtag_slave_write, // .write
output wire jtag_uart_0_avalon_jtag_slave_read, // .read
input wire [31:0] jtag_uart_0_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] jtag_uart_0_avalon_jtag_slave_writedata, // .writedata
input wire jtag_uart_0_avalon_jtag_slave_waitrequest, // .waitrequest
output wire jtag_uart_0_avalon_jtag_slave_chipselect, // .chipselect
output wire [1:0] keys_s1_address, // keys_s1.address
input wire [31:0] keys_s1_readdata, // .readdata
output wire [1:0] LEDs_s1_address, // LEDs_s1.address
output wire LEDs_s1_write, // .write
input wire [31:0] LEDs_s1_readdata, // .readdata
output wire [31:0] LEDs_s1_writedata, // .writedata
output wire LEDs_s1_chipselect, // .chipselect
output wire [8:0] nios2_qsys_0_debug_mem_slave_address, // nios2_qsys_0_debug_mem_slave.address
output wire nios2_qsys_0_debug_mem_slave_write, // .write
output wire nios2_qsys_0_debug_mem_slave_read, // .read
input wire [31:0] nios2_qsys_0_debug_mem_slave_readdata, // .readdata
output wire [31:0] nios2_qsys_0_debug_mem_slave_writedata, // .writedata
output wire [3:0] nios2_qsys_0_debug_mem_slave_byteenable, // .byteenable
input wire nios2_qsys_0_debug_mem_slave_waitrequest, // .waitrequest
output wire nios2_qsys_0_debug_mem_slave_debugaccess, // .debugaccess
output wire [14:0] onchip_memory2_0_s1_address, // onchip_memory2_0_s1.address
output wire onchip_memory2_0_s1_write, // .write
input wire [31:0] onchip_memory2_0_s1_readdata, // .readdata
output wire [31:0] onchip_memory2_0_s1_writedata, // .writedata
output wire [3:0] onchip_memory2_0_s1_byteenable, // .byteenable
output wire onchip_memory2_0_s1_chipselect, // .chipselect
output wire onchip_memory2_0_s1_clken, // .clken
output wire [1:0] regfile_data_s1_address, // regfile_data_s1.address
output wire regfile_data_s1_write, // .write
input wire [31:0] regfile_data_s1_readdata, // .readdata
output wire [31:0] regfile_data_s1_writedata, // .writedata
output wire regfile_data_s1_chipselect, // .chipselect
output wire [1:0] regfile_r1sel_s1_address, // regfile_r1sel_s1.address
output wire regfile_r1sel_s1_write, // .write
input wire [31:0] regfile_r1sel_s1_readdata, // .readdata
output wire [31:0] regfile_r1sel_s1_writedata, // .writedata
output wire regfile_r1sel_s1_chipselect, // .chipselect
output wire [1:0] regfile_r2sel_s1_address, // regfile_r2sel_s1.address
output wire regfile_r2sel_s1_write, // .write
input wire [31:0] regfile_r2sel_s1_readdata, // .readdata
output wire [31:0] regfile_r2sel_s1_writedata, // .writedata
output wire regfile_r2sel_s1_chipselect, // .chipselect
output wire [1:0] regfile_reg1_s1_address, // regfile_reg1_s1.address
input wire [31:0] regfile_reg1_s1_readdata, // .readdata
output wire [1:0] regfile_reg2_s1_address, // regfile_reg2_s1.address
input wire [31:0] regfile_reg2_s1_readdata, // .readdata
output wire [1:0] regfile_we_s1_address, // regfile_we_s1.address
output wire regfile_we_s1_write, // .write
input wire [31:0] regfile_we_s1_readdata, // .readdata
output wire [31:0] regfile_we_s1_writedata, // .writedata
output wire regfile_we_s1_chipselect, // .chipselect
output wire [1:0] regfile_wsel_s1_address, // regfile_wsel_s1.address
output wire regfile_wsel_s1_write, // .write
input wire [31:0] regfile_wsel_s1_readdata, // .readdata
output wire [31:0] regfile_wsel_s1_writedata, // .writedata
output wire regfile_wsel_s1_chipselect, // .chipselect
output wire [1:0] sram_addr_s1_address, // sram_addr_s1.address
output wire sram_addr_s1_write, // .write
input wire [31:0] sram_addr_s1_readdata, // .readdata
output wire [31:0] sram_addr_s1_writedata, // .writedata
output wire sram_addr_s1_chipselect, // .chipselect
output wire [1:0] sram_cs_s1_address, // sram_cs_s1.address
output wire sram_cs_s1_write, // .write
input wire [31:0] sram_cs_s1_readdata, // .readdata
output wire [31:0] sram_cs_s1_writedata, // .writedata
output wire sram_cs_s1_chipselect, // .chipselect
output wire [1:0] sram_data_s1_address, // sram_data_s1.address
output wire sram_data_s1_write, // .write
input wire [31:0] sram_data_s1_readdata, // .readdata
output wire [31:0] sram_data_s1_writedata, // .writedata
output wire sram_data_s1_chipselect, // .chipselect
output wire [1:0] sram_oe_s1_address, // sram_oe_s1.address
output wire sram_oe_s1_write, // .write
input wire [31:0] sram_oe_s1_readdata, // .readdata
output wire [31:0] sram_oe_s1_writedata, // .writedata
output wire sram_oe_s1_chipselect, // .chipselect
output wire [1:0] sram_read_write_s1_address, // sram_read_write_s1.address
output wire sram_read_write_s1_write, // .write
input wire [31:0] sram_read_write_s1_readdata, // .readdata
output wire [31:0] sram_read_write_s1_writedata, // .writedata
output wire sram_read_write_s1_chipselect, // .chipselect
output wire [1:0] switches_s1_address, // switches_s1.address
input wire [31:0] switches_s1_readdata // .readdata
);
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_0_data_master_agent:av_waitrequest -> nios2_qsys_0_data_master_translator:uav_waitrequest
wire [31:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_0_data_master_agent:av_readdata -> nios2_qsys_0_data_master_translator:uav_readdata
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_0_data_master_translator:uav_debugaccess -> nios2_qsys_0_data_master_agent:av_debugaccess
wire [18:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_address; // nios2_qsys_0_data_master_translator:uav_address -> nios2_qsys_0_data_master_agent:av_address
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_read; // nios2_qsys_0_data_master_translator:uav_read -> nios2_qsys_0_data_master_agent:av_read
wire [3:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_0_data_master_translator:uav_byteenable -> nios2_qsys_0_data_master_agent:av_byteenable
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_0_data_master_agent:av_readdatavalid -> nios2_qsys_0_data_master_translator:uav_readdatavalid
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock; // nios2_qsys_0_data_master_translator:uav_lock -> nios2_qsys_0_data_master_agent:av_lock
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_write; // nios2_qsys_0_data_master_translator:uav_write -> nios2_qsys_0_data_master_agent:av_write
wire [31:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_0_data_master_translator:uav_writedata -> nios2_qsys_0_data_master_agent:av_writedata
wire [2:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_0_data_master_translator:uav_burstcount -> nios2_qsys_0_data_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> nios2_qsys_0_data_master_agent:rp_valid
wire [98:0] rsp_mux_src_data; // rsp_mux:src_data -> nios2_qsys_0_data_master_agent:rp_data
wire rsp_mux_src_ready; // nios2_qsys_0_data_master_agent:rp_ready -> rsp_mux:src_ready
wire [31:0] rsp_mux_src_channel; // rsp_mux:src_channel -> nios2_qsys_0_data_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> nios2_qsys_0_data_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> nios2_qsys_0_data_master_agent:rp_endofpacket
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_0_instruction_master_agent:av_waitrequest -> nios2_qsys_0_instruction_master_translator:uav_waitrequest
wire [31:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_0_instruction_master_agent:av_readdata -> nios2_qsys_0_instruction_master_translator:uav_readdata
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_0_instruction_master_translator:uav_debugaccess -> nios2_qsys_0_instruction_master_agent:av_debugaccess
wire [18:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address; // nios2_qsys_0_instruction_master_translator:uav_address -> nios2_qsys_0_instruction_master_agent:av_address
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read; // nios2_qsys_0_instruction_master_translator:uav_read -> nios2_qsys_0_instruction_master_agent:av_read
wire [3:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_0_instruction_master_translator:uav_byteenable -> nios2_qsys_0_instruction_master_agent:av_byteenable
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_0_instruction_master_agent:av_readdatavalid -> nios2_qsys_0_instruction_master_translator:uav_readdatavalid
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock; // nios2_qsys_0_instruction_master_translator:uav_lock -> nios2_qsys_0_instruction_master_agent:av_lock
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write; // nios2_qsys_0_instruction_master_translator:uav_write -> nios2_qsys_0_instruction_master_agent:av_write
wire [31:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_0_instruction_master_translator:uav_writedata -> nios2_qsys_0_instruction_master_agent:av_writedata
wire [2:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_0_instruction_master_translator:uav_burstcount -> nios2_qsys_0_instruction_master_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> nios2_qsys_0_instruction_master_agent:rp_valid
wire [98:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> nios2_qsys_0_instruction_master_agent:rp_data
wire rsp_mux_001_src_ready; // nios2_qsys_0_instruction_master_agent:rp_ready -> rsp_mux_001:src_ready
wire [31:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> nios2_qsys_0_instruction_master_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> nios2_qsys_0_instruction_master_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> nios2_qsys_0_instruction_master_agent:rp_endofpacket
wire [31:0] jtag_uart_0_avalon_jtag_slave_agent_m0_readdata; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_0_avalon_jtag_slave_agent:m0_readdata
wire jtag_uart_0_avalon_jtag_slave_agent_m0_waitrequest; // jtag_uart_0_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_0_avalon_jtag_slave_agent:m0_waitrequest
wire jtag_uart_0_avalon_jtag_slave_agent_m0_debugaccess; // jtag_uart_0_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_0_avalon_jtag_slave_translator:uav_debugaccess
wire [18:0] jtag_uart_0_avalon_jtag_slave_agent_m0_address; // jtag_uart_0_avalon_jtag_slave_agent:m0_address -> jtag_uart_0_avalon_jtag_slave_translator:uav_address
wire [3:0] jtag_uart_0_avalon_jtag_slave_agent_m0_byteenable; // jtag_uart_0_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_0_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_0_avalon_jtag_slave_agent_m0_read; // jtag_uart_0_avalon_jtag_slave_agent:m0_read -> jtag_uart_0_avalon_jtag_slave_translator:uav_read
wire jtag_uart_0_avalon_jtag_slave_agent_m0_readdatavalid; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_0_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_uart_0_avalon_jtag_slave_agent_m0_lock; // jtag_uart_0_avalon_jtag_slave_agent:m0_lock -> jtag_uart_0_avalon_jtag_slave_translator:uav_lock
wire [31:0] jtag_uart_0_avalon_jtag_slave_agent_m0_writedata; // jtag_uart_0_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_0_avalon_jtag_slave_translator:uav_writedata
wire jtag_uart_0_avalon_jtag_slave_agent_m0_write; // jtag_uart_0_avalon_jtag_slave_agent:m0_write -> jtag_uart_0_avalon_jtag_slave_translator:uav_write
wire [2:0] jtag_uart_0_avalon_jtag_slave_agent_m0_burstcount; // jtag_uart_0_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_0_avalon_jtag_slave_translator:uav_burstcount
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_valid; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire [99:0] jtag_uart_0_avalon_jtag_slave_agent_rf_source_data; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_ready; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_0_avalon_jtag_slave_agent:rf_source_ready
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_startofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_endofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_valid; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_valid
wire [99:0] jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_data; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_data
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_ready; // jtag_uart_0_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_startofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_endofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_valid; // jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_src_valid -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_data; // jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_src_data -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_ready; // jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire cmd_mux_src_valid; // cmd_mux:src_valid -> jtag_uart_0_avalon_jtag_slave_agent:cp_valid
wire [98:0] cmd_mux_src_data; // cmd_mux:src_data -> jtag_uart_0_avalon_jtag_slave_agent:cp_data
wire cmd_mux_src_ready; // jtag_uart_0_avalon_jtag_slave_agent:cp_ready -> cmd_mux:src_ready
wire [31:0] cmd_mux_src_channel; // cmd_mux:src_channel -> jtag_uart_0_avalon_jtag_slave_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> jtag_uart_0_avalon_jtag_slave_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> jtag_uart_0_avalon_jtag_slave_agent:cp_endofpacket
wire [31:0] nios2_qsys_0_debug_mem_slave_agent_m0_readdata; // nios2_qsys_0_debug_mem_slave_translator:uav_readdata -> nios2_qsys_0_debug_mem_slave_agent:m0_readdata
wire nios2_qsys_0_debug_mem_slave_agent_m0_waitrequest; // nios2_qsys_0_debug_mem_slave_translator:uav_waitrequest -> nios2_qsys_0_debug_mem_slave_agent:m0_waitrequest
wire nios2_qsys_0_debug_mem_slave_agent_m0_debugaccess; // nios2_qsys_0_debug_mem_slave_agent:m0_debugaccess -> nios2_qsys_0_debug_mem_slave_translator:uav_debugaccess
wire [18:0] nios2_qsys_0_debug_mem_slave_agent_m0_address; // nios2_qsys_0_debug_mem_slave_agent:m0_address -> nios2_qsys_0_debug_mem_slave_translator:uav_address
wire [3:0] nios2_qsys_0_debug_mem_slave_agent_m0_byteenable; // nios2_qsys_0_debug_mem_slave_agent:m0_byteenable -> nios2_qsys_0_debug_mem_slave_translator:uav_byteenable
wire nios2_qsys_0_debug_mem_slave_agent_m0_read; // nios2_qsys_0_debug_mem_slave_agent:m0_read -> nios2_qsys_0_debug_mem_slave_translator:uav_read
wire nios2_qsys_0_debug_mem_slave_agent_m0_readdatavalid; // nios2_qsys_0_debug_mem_slave_translator:uav_readdatavalid -> nios2_qsys_0_debug_mem_slave_agent:m0_readdatavalid
wire nios2_qsys_0_debug_mem_slave_agent_m0_lock; // nios2_qsys_0_debug_mem_slave_agent:m0_lock -> nios2_qsys_0_debug_mem_slave_translator:uav_lock
wire [31:0] nios2_qsys_0_debug_mem_slave_agent_m0_writedata; // nios2_qsys_0_debug_mem_slave_agent:m0_writedata -> nios2_qsys_0_debug_mem_slave_translator:uav_writedata
wire nios2_qsys_0_debug_mem_slave_agent_m0_write; // nios2_qsys_0_debug_mem_slave_agent:m0_write -> nios2_qsys_0_debug_mem_slave_translator:uav_write
wire [2:0] nios2_qsys_0_debug_mem_slave_agent_m0_burstcount; // nios2_qsys_0_debug_mem_slave_agent:m0_burstcount -> nios2_qsys_0_debug_mem_slave_translator:uav_burstcount
wire nios2_qsys_0_debug_mem_slave_agent_rf_source_valid; // nios2_qsys_0_debug_mem_slave_agent:rf_source_valid -> nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:in_valid
wire [99:0] nios2_qsys_0_debug_mem_slave_agent_rf_source_data; // nios2_qsys_0_debug_mem_slave_agent:rf_source_data -> nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:in_data
wire nios2_qsys_0_debug_mem_slave_agent_rf_source_ready; // nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:in_ready -> nios2_qsys_0_debug_mem_slave_agent:rf_source_ready
wire nios2_qsys_0_debug_mem_slave_agent_rf_source_startofpacket; // nios2_qsys_0_debug_mem_slave_agent:rf_source_startofpacket -> nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:in_startofpacket
wire nios2_qsys_0_debug_mem_slave_agent_rf_source_endofpacket; // nios2_qsys_0_debug_mem_slave_agent:rf_source_endofpacket -> nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:in_endofpacket
wire nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_valid; // nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:out_valid -> nios2_qsys_0_debug_mem_slave_agent:rf_sink_valid
wire [99:0] nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_data; // nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:out_data -> nios2_qsys_0_debug_mem_slave_agent:rf_sink_data
wire nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_ready; // nios2_qsys_0_debug_mem_slave_agent:rf_sink_ready -> nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:out_ready
wire nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket; // nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> nios2_qsys_0_debug_mem_slave_agent:rf_sink_startofpacket
wire nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket; // nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> nios2_qsys_0_debug_mem_slave_agent:rf_sink_endofpacket
wire nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_valid; // nios2_qsys_0_debug_mem_slave_agent:rdata_fifo_src_valid -> nios2_qsys_0_debug_mem_slave_agent:rdata_fifo_sink_valid
wire [33:0] nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_data; // nios2_qsys_0_debug_mem_slave_agent:rdata_fifo_src_data -> nios2_qsys_0_debug_mem_slave_agent:rdata_fifo_sink_data
wire nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_ready; // nios2_qsys_0_debug_mem_slave_agent:rdata_fifo_sink_ready -> nios2_qsys_0_debug_mem_slave_agent:rdata_fifo_src_ready
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> nios2_qsys_0_debug_mem_slave_agent:cp_valid
wire [98:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> nios2_qsys_0_debug_mem_slave_agent:cp_data
wire cmd_mux_001_src_ready; // nios2_qsys_0_debug_mem_slave_agent:cp_ready -> cmd_mux_001:src_ready
wire [31:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> nios2_qsys_0_debug_mem_slave_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> nios2_qsys_0_debug_mem_slave_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> nios2_qsys_0_debug_mem_slave_agent:cp_endofpacket
wire [31:0] onchip_memory2_0_s1_agent_m0_readdata; // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_agent:m0_readdata
wire onchip_memory2_0_s1_agent_m0_waitrequest; // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_agent:m0_waitrequest
wire onchip_memory2_0_s1_agent_m0_debugaccess; // onchip_memory2_0_s1_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
wire [18:0] onchip_memory2_0_s1_agent_m0_address; // onchip_memory2_0_s1_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
wire [3:0] onchip_memory2_0_s1_agent_m0_byteenable; // onchip_memory2_0_s1_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
wire onchip_memory2_0_s1_agent_m0_read; // onchip_memory2_0_s1_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
wire onchip_memory2_0_s1_agent_m0_readdatavalid; // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_agent:m0_readdatavalid
wire onchip_memory2_0_s1_agent_m0_lock; // onchip_memory2_0_s1_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
wire [31:0] onchip_memory2_0_s1_agent_m0_writedata; // onchip_memory2_0_s1_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
wire onchip_memory2_0_s1_agent_m0_write; // onchip_memory2_0_s1_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
wire [2:0] onchip_memory2_0_s1_agent_m0_burstcount; // onchip_memory2_0_s1_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
wire onchip_memory2_0_s1_agent_rf_source_valid; // onchip_memory2_0_s1_agent:rf_source_valid -> onchip_memory2_0_s1_agent_rsp_fifo:in_valid
wire [99:0] onchip_memory2_0_s1_agent_rf_source_data; // onchip_memory2_0_s1_agent:rf_source_data -> onchip_memory2_0_s1_agent_rsp_fifo:in_data
wire onchip_memory2_0_s1_agent_rf_source_ready; // onchip_memory2_0_s1_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_agent:rf_source_ready
wire onchip_memory2_0_s1_agent_rf_source_startofpacket; // onchip_memory2_0_s1_agent:rf_source_startofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_startofpacket
wire onchip_memory2_0_s1_agent_rf_source_endofpacket; // onchip_memory2_0_s1_agent:rf_source_endofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_valid; // onchip_memory2_0_s1_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_agent:rf_sink_valid
wire [99:0] onchip_memory2_0_s1_agent_rsp_fifo_out_data; // onchip_memory2_0_s1_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_agent:rf_sink_data
wire onchip_memory2_0_s1_agent_rsp_fifo_out_ready; // onchip_memory2_0_s1_agent:rf_sink_ready -> onchip_memory2_0_s1_agent_rsp_fifo:out_ready
wire onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_agent:rf_sink_startofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_agent:rf_sink_endofpacket
wire onchip_memory2_0_s1_agent_rdata_fifo_src_valid; // onchip_memory2_0_s1_agent:rdata_fifo_src_valid -> onchip_memory2_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] onchip_memory2_0_s1_agent_rdata_fifo_src_data; // onchip_memory2_0_s1_agent:rdata_fifo_src_data -> onchip_memory2_0_s1_agent:rdata_fifo_sink_data
wire onchip_memory2_0_s1_agent_rdata_fifo_src_ready; // onchip_memory2_0_s1_agent:rdata_fifo_sink_ready -> onchip_memory2_0_s1_agent:rdata_fifo_src_ready
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> onchip_memory2_0_s1_agent:cp_valid
wire [98:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> onchip_memory2_0_s1_agent:cp_data
wire cmd_mux_002_src_ready; // onchip_memory2_0_s1_agent:cp_ready -> cmd_mux_002:src_ready
wire [31:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> onchip_memory2_0_s1_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> onchip_memory2_0_s1_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> onchip_memory2_0_s1_agent:cp_endofpacket
wire [31:0] leds_s1_agent_m0_readdata; // LEDs_s1_translator:uav_readdata -> LEDs_s1_agent:m0_readdata
wire leds_s1_agent_m0_waitrequest; // LEDs_s1_translator:uav_waitrequest -> LEDs_s1_agent:m0_waitrequest
wire leds_s1_agent_m0_debugaccess; // LEDs_s1_agent:m0_debugaccess -> LEDs_s1_translator:uav_debugaccess
wire [18:0] leds_s1_agent_m0_address; // LEDs_s1_agent:m0_address -> LEDs_s1_translator:uav_address
wire [3:0] leds_s1_agent_m0_byteenable; // LEDs_s1_agent:m0_byteenable -> LEDs_s1_translator:uav_byteenable
wire leds_s1_agent_m0_read; // LEDs_s1_agent:m0_read -> LEDs_s1_translator:uav_read
wire leds_s1_agent_m0_readdatavalid; // LEDs_s1_translator:uav_readdatavalid -> LEDs_s1_agent:m0_readdatavalid
wire leds_s1_agent_m0_lock; // LEDs_s1_agent:m0_lock -> LEDs_s1_translator:uav_lock
wire [31:0] leds_s1_agent_m0_writedata; // LEDs_s1_agent:m0_writedata -> LEDs_s1_translator:uav_writedata
wire leds_s1_agent_m0_write; // LEDs_s1_agent:m0_write -> LEDs_s1_translator:uav_write
wire [2:0] leds_s1_agent_m0_burstcount; // LEDs_s1_agent:m0_burstcount -> LEDs_s1_translator:uav_burstcount
wire leds_s1_agent_rf_source_valid; // LEDs_s1_agent:rf_source_valid -> LEDs_s1_agent_rsp_fifo:in_valid
wire [99:0] leds_s1_agent_rf_source_data; // LEDs_s1_agent:rf_source_data -> LEDs_s1_agent_rsp_fifo:in_data
wire leds_s1_agent_rf_source_ready; // LEDs_s1_agent_rsp_fifo:in_ready -> LEDs_s1_agent:rf_source_ready
wire leds_s1_agent_rf_source_startofpacket; // LEDs_s1_agent:rf_source_startofpacket -> LEDs_s1_agent_rsp_fifo:in_startofpacket
wire leds_s1_agent_rf_source_endofpacket; // LEDs_s1_agent:rf_source_endofpacket -> LEDs_s1_agent_rsp_fifo:in_endofpacket
wire leds_s1_agent_rsp_fifo_out_valid; // LEDs_s1_agent_rsp_fifo:out_valid -> LEDs_s1_agent:rf_sink_valid
wire [99:0] leds_s1_agent_rsp_fifo_out_data; // LEDs_s1_agent_rsp_fifo:out_data -> LEDs_s1_agent:rf_sink_data
wire leds_s1_agent_rsp_fifo_out_ready; // LEDs_s1_agent:rf_sink_ready -> LEDs_s1_agent_rsp_fifo:out_ready
wire leds_s1_agent_rsp_fifo_out_startofpacket; // LEDs_s1_agent_rsp_fifo:out_startofpacket -> LEDs_s1_agent:rf_sink_startofpacket
wire leds_s1_agent_rsp_fifo_out_endofpacket; // LEDs_s1_agent_rsp_fifo:out_endofpacket -> LEDs_s1_agent:rf_sink_endofpacket
wire leds_s1_agent_rdata_fifo_src_valid; // LEDs_s1_agent:rdata_fifo_src_valid -> LEDs_s1_agent:rdata_fifo_sink_valid
wire [33:0] leds_s1_agent_rdata_fifo_src_data; // LEDs_s1_agent:rdata_fifo_src_data -> LEDs_s1_agent:rdata_fifo_sink_data
wire leds_s1_agent_rdata_fifo_src_ready; // LEDs_s1_agent:rdata_fifo_sink_ready -> LEDs_s1_agent:rdata_fifo_src_ready
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> LEDs_s1_agent:cp_valid
wire [98:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> LEDs_s1_agent:cp_data
wire cmd_mux_003_src_ready; // LEDs_s1_agent:cp_ready -> cmd_mux_003:src_ready
wire [31:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> LEDs_s1_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> LEDs_s1_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> LEDs_s1_agent:cp_endofpacket
wire [31:0] switches_s1_agent_m0_readdata; // switches_s1_translator:uav_readdata -> switches_s1_agent:m0_readdata
wire switches_s1_agent_m0_waitrequest; // switches_s1_translator:uav_waitrequest -> switches_s1_agent:m0_waitrequest
wire switches_s1_agent_m0_debugaccess; // switches_s1_agent:m0_debugaccess -> switches_s1_translator:uav_debugaccess
wire [18:0] switches_s1_agent_m0_address; // switches_s1_agent:m0_address -> switches_s1_translator:uav_address
wire [3:0] switches_s1_agent_m0_byteenable; // switches_s1_agent:m0_byteenable -> switches_s1_translator:uav_byteenable
wire switches_s1_agent_m0_read; // switches_s1_agent:m0_read -> switches_s1_translator:uav_read
wire switches_s1_agent_m0_readdatavalid; // switches_s1_translator:uav_readdatavalid -> switches_s1_agent:m0_readdatavalid
wire switches_s1_agent_m0_lock; // switches_s1_agent:m0_lock -> switches_s1_translator:uav_lock
wire [31:0] switches_s1_agent_m0_writedata; // switches_s1_agent:m0_writedata -> switches_s1_translator:uav_writedata
wire switches_s1_agent_m0_write; // switches_s1_agent:m0_write -> switches_s1_translator:uav_write
wire [2:0] switches_s1_agent_m0_burstcount; // switches_s1_agent:m0_burstcount -> switches_s1_translator:uav_burstcount
wire switches_s1_agent_rf_source_valid; // switches_s1_agent:rf_source_valid -> switches_s1_agent_rsp_fifo:in_valid
wire [99:0] switches_s1_agent_rf_source_data; // switches_s1_agent:rf_source_data -> switches_s1_agent_rsp_fifo:in_data
wire switches_s1_agent_rf_source_ready; // switches_s1_agent_rsp_fifo:in_ready -> switches_s1_agent:rf_source_ready
wire switches_s1_agent_rf_source_startofpacket; // switches_s1_agent:rf_source_startofpacket -> switches_s1_agent_rsp_fifo:in_startofpacket
wire switches_s1_agent_rf_source_endofpacket; // switches_s1_agent:rf_source_endofpacket -> switches_s1_agent_rsp_fifo:in_endofpacket
wire switches_s1_agent_rsp_fifo_out_valid; // switches_s1_agent_rsp_fifo:out_valid -> switches_s1_agent:rf_sink_valid
wire [99:0] switches_s1_agent_rsp_fifo_out_data; // switches_s1_agent_rsp_fifo:out_data -> switches_s1_agent:rf_sink_data
wire switches_s1_agent_rsp_fifo_out_ready; // switches_s1_agent:rf_sink_ready -> switches_s1_agent_rsp_fifo:out_ready
wire switches_s1_agent_rsp_fifo_out_startofpacket; // switches_s1_agent_rsp_fifo:out_startofpacket -> switches_s1_agent:rf_sink_startofpacket
wire switches_s1_agent_rsp_fifo_out_endofpacket; // switches_s1_agent_rsp_fifo:out_endofpacket -> switches_s1_agent:rf_sink_endofpacket
wire switches_s1_agent_rdata_fifo_src_valid; // switches_s1_agent:rdata_fifo_src_valid -> switches_s1_agent:rdata_fifo_sink_valid
wire [33:0] switches_s1_agent_rdata_fifo_src_data; // switches_s1_agent:rdata_fifo_src_data -> switches_s1_agent:rdata_fifo_sink_data
wire switches_s1_agent_rdata_fifo_src_ready; // switches_s1_agent:rdata_fifo_sink_ready -> switches_s1_agent:rdata_fifo_src_ready
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> switches_s1_agent:cp_valid
wire [98:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> switches_s1_agent:cp_data
wire cmd_mux_004_src_ready; // switches_s1_agent:cp_ready -> cmd_mux_004:src_ready
wire [31:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> switches_s1_agent:cp_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> switches_s1_agent:cp_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> switches_s1_agent:cp_endofpacket
wire [31:0] sram_data_s1_agent_m0_readdata; // sram_data_s1_translator:uav_readdata -> sram_data_s1_agent:m0_readdata
wire sram_data_s1_agent_m0_waitrequest; // sram_data_s1_translator:uav_waitrequest -> sram_data_s1_agent:m0_waitrequest
wire sram_data_s1_agent_m0_debugaccess; // sram_data_s1_agent:m0_debugaccess -> sram_data_s1_translator:uav_debugaccess
wire [18:0] sram_data_s1_agent_m0_address; // sram_data_s1_agent:m0_address -> sram_data_s1_translator:uav_address
wire [3:0] sram_data_s1_agent_m0_byteenable; // sram_data_s1_agent:m0_byteenable -> sram_data_s1_translator:uav_byteenable
wire sram_data_s1_agent_m0_read; // sram_data_s1_agent:m0_read -> sram_data_s1_translator:uav_read
wire sram_data_s1_agent_m0_readdatavalid; // sram_data_s1_translator:uav_readdatavalid -> sram_data_s1_agent:m0_readdatavalid
wire sram_data_s1_agent_m0_lock; // sram_data_s1_agent:m0_lock -> sram_data_s1_translator:uav_lock
wire [31:0] sram_data_s1_agent_m0_writedata; // sram_data_s1_agent:m0_writedata -> sram_data_s1_translator:uav_writedata
wire sram_data_s1_agent_m0_write; // sram_data_s1_agent:m0_write -> sram_data_s1_translator:uav_write
wire [2:0] sram_data_s1_agent_m0_burstcount; // sram_data_s1_agent:m0_burstcount -> sram_data_s1_translator:uav_burstcount
wire sram_data_s1_agent_rf_source_valid; // sram_data_s1_agent:rf_source_valid -> sram_data_s1_agent_rsp_fifo:in_valid
wire [99:0] sram_data_s1_agent_rf_source_data; // sram_data_s1_agent:rf_source_data -> sram_data_s1_agent_rsp_fifo:in_data
wire sram_data_s1_agent_rf_source_ready; // sram_data_s1_agent_rsp_fifo:in_ready -> sram_data_s1_agent:rf_source_ready
wire sram_data_s1_agent_rf_source_startofpacket; // sram_data_s1_agent:rf_source_startofpacket -> sram_data_s1_agent_rsp_fifo:in_startofpacket
wire sram_data_s1_agent_rf_source_endofpacket; // sram_data_s1_agent:rf_source_endofpacket -> sram_data_s1_agent_rsp_fifo:in_endofpacket
wire sram_data_s1_agent_rsp_fifo_out_valid; // sram_data_s1_agent_rsp_fifo:out_valid -> sram_data_s1_agent:rf_sink_valid
wire [99:0] sram_data_s1_agent_rsp_fifo_out_data; // sram_data_s1_agent_rsp_fifo:out_data -> sram_data_s1_agent:rf_sink_data
wire sram_data_s1_agent_rsp_fifo_out_ready; // sram_data_s1_agent:rf_sink_ready -> sram_data_s1_agent_rsp_fifo:out_ready
wire sram_data_s1_agent_rsp_fifo_out_startofpacket; // sram_data_s1_agent_rsp_fifo:out_startofpacket -> sram_data_s1_agent:rf_sink_startofpacket
wire sram_data_s1_agent_rsp_fifo_out_endofpacket; // sram_data_s1_agent_rsp_fifo:out_endofpacket -> sram_data_s1_agent:rf_sink_endofpacket
wire sram_data_s1_agent_rdata_fifo_src_valid; // sram_data_s1_agent:rdata_fifo_src_valid -> sram_data_s1_agent:rdata_fifo_sink_valid
wire [33:0] sram_data_s1_agent_rdata_fifo_src_data; // sram_data_s1_agent:rdata_fifo_src_data -> sram_data_s1_agent:rdata_fifo_sink_data
wire sram_data_s1_agent_rdata_fifo_src_ready; // sram_data_s1_agent:rdata_fifo_sink_ready -> sram_data_s1_agent:rdata_fifo_src_ready
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> sram_data_s1_agent:cp_valid
wire [98:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> sram_data_s1_agent:cp_data
wire cmd_mux_005_src_ready; // sram_data_s1_agent:cp_ready -> cmd_mux_005:src_ready
wire [31:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> sram_data_s1_agent:cp_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> sram_data_s1_agent:cp_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> sram_data_s1_agent:cp_endofpacket
wire [31:0] sram_addr_s1_agent_m0_readdata; // sram_addr_s1_translator:uav_readdata -> sram_addr_s1_agent:m0_readdata
wire sram_addr_s1_agent_m0_waitrequest; // sram_addr_s1_translator:uav_waitrequest -> sram_addr_s1_agent:m0_waitrequest
wire sram_addr_s1_agent_m0_debugaccess; // sram_addr_s1_agent:m0_debugaccess -> sram_addr_s1_translator:uav_debugaccess
wire [18:0] sram_addr_s1_agent_m0_address; // sram_addr_s1_agent:m0_address -> sram_addr_s1_translator:uav_address
wire [3:0] sram_addr_s1_agent_m0_byteenable; // sram_addr_s1_agent:m0_byteenable -> sram_addr_s1_translator:uav_byteenable
wire sram_addr_s1_agent_m0_read; // sram_addr_s1_agent:m0_read -> sram_addr_s1_translator:uav_read
wire sram_addr_s1_agent_m0_readdatavalid; // sram_addr_s1_translator:uav_readdatavalid -> sram_addr_s1_agent:m0_readdatavalid
wire sram_addr_s1_agent_m0_lock; // sram_addr_s1_agent:m0_lock -> sram_addr_s1_translator:uav_lock
wire [31:0] sram_addr_s1_agent_m0_writedata; // sram_addr_s1_agent:m0_writedata -> sram_addr_s1_translator:uav_writedata
wire sram_addr_s1_agent_m0_write; // sram_addr_s1_agent:m0_write -> sram_addr_s1_translator:uav_write
wire [2:0] sram_addr_s1_agent_m0_burstcount; // sram_addr_s1_agent:m0_burstcount -> sram_addr_s1_translator:uav_burstcount
wire sram_addr_s1_agent_rf_source_valid; // sram_addr_s1_agent:rf_source_valid -> sram_addr_s1_agent_rsp_fifo:in_valid
wire [99:0] sram_addr_s1_agent_rf_source_data; // sram_addr_s1_agent:rf_source_data -> sram_addr_s1_agent_rsp_fifo:in_data
wire sram_addr_s1_agent_rf_source_ready; // sram_addr_s1_agent_rsp_fifo:in_ready -> sram_addr_s1_agent:rf_source_ready
wire sram_addr_s1_agent_rf_source_startofpacket; // sram_addr_s1_agent:rf_source_startofpacket -> sram_addr_s1_agent_rsp_fifo:in_startofpacket
wire sram_addr_s1_agent_rf_source_endofpacket; // sram_addr_s1_agent:rf_source_endofpacket -> sram_addr_s1_agent_rsp_fifo:in_endofpacket
wire sram_addr_s1_agent_rsp_fifo_out_valid; // sram_addr_s1_agent_rsp_fifo:out_valid -> sram_addr_s1_agent:rf_sink_valid
wire [99:0] sram_addr_s1_agent_rsp_fifo_out_data; // sram_addr_s1_agent_rsp_fifo:out_data -> sram_addr_s1_agent:rf_sink_data
wire sram_addr_s1_agent_rsp_fifo_out_ready; // sram_addr_s1_agent:rf_sink_ready -> sram_addr_s1_agent_rsp_fifo:out_ready
wire sram_addr_s1_agent_rsp_fifo_out_startofpacket; // sram_addr_s1_agent_rsp_fifo:out_startofpacket -> sram_addr_s1_agent:rf_sink_startofpacket
wire sram_addr_s1_agent_rsp_fifo_out_endofpacket; // sram_addr_s1_agent_rsp_fifo:out_endofpacket -> sram_addr_s1_agent:rf_sink_endofpacket
wire sram_addr_s1_agent_rdata_fifo_src_valid; // sram_addr_s1_agent:rdata_fifo_src_valid -> sram_addr_s1_agent:rdata_fifo_sink_valid
wire [33:0] sram_addr_s1_agent_rdata_fifo_src_data; // sram_addr_s1_agent:rdata_fifo_src_data -> sram_addr_s1_agent:rdata_fifo_sink_data
wire sram_addr_s1_agent_rdata_fifo_src_ready; // sram_addr_s1_agent:rdata_fifo_sink_ready -> sram_addr_s1_agent:rdata_fifo_src_ready
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> sram_addr_s1_agent:cp_valid
wire [98:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> sram_addr_s1_agent:cp_data
wire cmd_mux_006_src_ready; // sram_addr_s1_agent:cp_ready -> cmd_mux_006:src_ready
wire [31:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> sram_addr_s1_agent:cp_channel
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> sram_addr_s1_agent:cp_startofpacket
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> sram_addr_s1_agent:cp_endofpacket
wire [31:0] sram_read_write_s1_agent_m0_readdata; // sram_read_write_s1_translator:uav_readdata -> sram_read_write_s1_agent:m0_readdata
wire sram_read_write_s1_agent_m0_waitrequest; // sram_read_write_s1_translator:uav_waitrequest -> sram_read_write_s1_agent:m0_waitrequest
wire sram_read_write_s1_agent_m0_debugaccess; // sram_read_write_s1_agent:m0_debugaccess -> sram_read_write_s1_translator:uav_debugaccess
wire [18:0] sram_read_write_s1_agent_m0_address; // sram_read_write_s1_agent:m0_address -> sram_read_write_s1_translator:uav_address
wire [3:0] sram_read_write_s1_agent_m0_byteenable; // sram_read_write_s1_agent:m0_byteenable -> sram_read_write_s1_translator:uav_byteenable
wire sram_read_write_s1_agent_m0_read; // sram_read_write_s1_agent:m0_read -> sram_read_write_s1_translator:uav_read
wire sram_read_write_s1_agent_m0_readdatavalid; // sram_read_write_s1_translator:uav_readdatavalid -> sram_read_write_s1_agent:m0_readdatavalid
wire sram_read_write_s1_agent_m0_lock; // sram_read_write_s1_agent:m0_lock -> sram_read_write_s1_translator:uav_lock
wire [31:0] sram_read_write_s1_agent_m0_writedata; // sram_read_write_s1_agent:m0_writedata -> sram_read_write_s1_translator:uav_writedata
wire sram_read_write_s1_agent_m0_write; // sram_read_write_s1_agent:m0_write -> sram_read_write_s1_translator:uav_write
wire [2:0] sram_read_write_s1_agent_m0_burstcount; // sram_read_write_s1_agent:m0_burstcount -> sram_read_write_s1_translator:uav_burstcount
wire sram_read_write_s1_agent_rf_source_valid; // sram_read_write_s1_agent:rf_source_valid -> sram_read_write_s1_agent_rsp_fifo:in_valid
wire [99:0] sram_read_write_s1_agent_rf_source_data; // sram_read_write_s1_agent:rf_source_data -> sram_read_write_s1_agent_rsp_fifo:in_data
wire sram_read_write_s1_agent_rf_source_ready; // sram_read_write_s1_agent_rsp_fifo:in_ready -> sram_read_write_s1_agent:rf_source_ready
wire sram_read_write_s1_agent_rf_source_startofpacket; // sram_read_write_s1_agent:rf_source_startofpacket -> sram_read_write_s1_agent_rsp_fifo:in_startofpacket
wire sram_read_write_s1_agent_rf_source_endofpacket; // sram_read_write_s1_agent:rf_source_endofpacket -> sram_read_write_s1_agent_rsp_fifo:in_endofpacket
wire sram_read_write_s1_agent_rsp_fifo_out_valid; // sram_read_write_s1_agent_rsp_fifo:out_valid -> sram_read_write_s1_agent:rf_sink_valid
wire [99:0] sram_read_write_s1_agent_rsp_fifo_out_data; // sram_read_write_s1_agent_rsp_fifo:out_data -> sram_read_write_s1_agent:rf_sink_data
wire sram_read_write_s1_agent_rsp_fifo_out_ready; // sram_read_write_s1_agent:rf_sink_ready -> sram_read_write_s1_agent_rsp_fifo:out_ready
wire sram_read_write_s1_agent_rsp_fifo_out_startofpacket; // sram_read_write_s1_agent_rsp_fifo:out_startofpacket -> sram_read_write_s1_agent:rf_sink_startofpacket
wire sram_read_write_s1_agent_rsp_fifo_out_endofpacket; // sram_read_write_s1_agent_rsp_fifo:out_endofpacket -> sram_read_write_s1_agent:rf_sink_endofpacket
wire sram_read_write_s1_agent_rdata_fifo_src_valid; // sram_read_write_s1_agent:rdata_fifo_src_valid -> sram_read_write_s1_agent:rdata_fifo_sink_valid
wire [33:0] sram_read_write_s1_agent_rdata_fifo_src_data; // sram_read_write_s1_agent:rdata_fifo_src_data -> sram_read_write_s1_agent:rdata_fifo_sink_data
wire sram_read_write_s1_agent_rdata_fifo_src_ready; // sram_read_write_s1_agent:rdata_fifo_sink_ready -> sram_read_write_s1_agent:rdata_fifo_src_ready
wire cmd_mux_007_src_valid; // cmd_mux_007:src_valid -> sram_read_write_s1_agent:cp_valid
wire [98:0] cmd_mux_007_src_data; // cmd_mux_007:src_data -> sram_read_write_s1_agent:cp_data
wire cmd_mux_007_src_ready; // sram_read_write_s1_agent:cp_ready -> cmd_mux_007:src_ready
wire [31:0] cmd_mux_007_src_channel; // cmd_mux_007:src_channel -> sram_read_write_s1_agent:cp_channel
wire cmd_mux_007_src_startofpacket; // cmd_mux_007:src_startofpacket -> sram_read_write_s1_agent:cp_startofpacket
wire cmd_mux_007_src_endofpacket; // cmd_mux_007:src_endofpacket -> sram_read_write_s1_agent:cp_endofpacket
wire [31:0] sram_cs_s1_agent_m0_readdata; // sram_cs_s1_translator:uav_readdata -> sram_cs_s1_agent:m0_readdata
wire sram_cs_s1_agent_m0_waitrequest; // sram_cs_s1_translator:uav_waitrequest -> sram_cs_s1_agent:m0_waitrequest
wire sram_cs_s1_agent_m0_debugaccess; // sram_cs_s1_agent:m0_debugaccess -> sram_cs_s1_translator:uav_debugaccess
wire [18:0] sram_cs_s1_agent_m0_address; // sram_cs_s1_agent:m0_address -> sram_cs_s1_translator:uav_address
wire [3:0] sram_cs_s1_agent_m0_byteenable; // sram_cs_s1_agent:m0_byteenable -> sram_cs_s1_translator:uav_byteenable
wire sram_cs_s1_agent_m0_read; // sram_cs_s1_agent:m0_read -> sram_cs_s1_translator:uav_read
wire sram_cs_s1_agent_m0_readdatavalid; // sram_cs_s1_translator:uav_readdatavalid -> sram_cs_s1_agent:m0_readdatavalid
wire sram_cs_s1_agent_m0_lock; // sram_cs_s1_agent:m0_lock -> sram_cs_s1_translator:uav_lock
wire [31:0] sram_cs_s1_agent_m0_writedata; // sram_cs_s1_agent:m0_writedata -> sram_cs_s1_translator:uav_writedata
wire sram_cs_s1_agent_m0_write; // sram_cs_s1_agent:m0_write -> sram_cs_s1_translator:uav_write
wire [2:0] sram_cs_s1_agent_m0_burstcount; // sram_cs_s1_agent:m0_burstcount -> sram_cs_s1_translator:uav_burstcount
wire sram_cs_s1_agent_rf_source_valid; // sram_cs_s1_agent:rf_source_valid -> sram_cs_s1_agent_rsp_fifo:in_valid
wire [99:0] sram_cs_s1_agent_rf_source_data; // sram_cs_s1_agent:rf_source_data -> sram_cs_s1_agent_rsp_fifo:in_data
wire sram_cs_s1_agent_rf_source_ready; // sram_cs_s1_agent_rsp_fifo:in_ready -> sram_cs_s1_agent:rf_source_ready
wire sram_cs_s1_agent_rf_source_startofpacket; // sram_cs_s1_agent:rf_source_startofpacket -> sram_cs_s1_agent_rsp_fifo:in_startofpacket
wire sram_cs_s1_agent_rf_source_endofpacket; // sram_cs_s1_agent:rf_source_endofpacket -> sram_cs_s1_agent_rsp_fifo:in_endofpacket
wire sram_cs_s1_agent_rsp_fifo_out_valid; // sram_cs_s1_agent_rsp_fifo:out_valid -> sram_cs_s1_agent:rf_sink_valid
wire [99:0] sram_cs_s1_agent_rsp_fifo_out_data; // sram_cs_s1_agent_rsp_fifo:out_data -> sram_cs_s1_agent:rf_sink_data
wire sram_cs_s1_agent_rsp_fifo_out_ready; // sram_cs_s1_agent:rf_sink_ready -> sram_cs_s1_agent_rsp_fifo:out_ready
wire sram_cs_s1_agent_rsp_fifo_out_startofpacket; // sram_cs_s1_agent_rsp_fifo:out_startofpacket -> sram_cs_s1_agent:rf_sink_startofpacket
wire sram_cs_s1_agent_rsp_fifo_out_endofpacket; // sram_cs_s1_agent_rsp_fifo:out_endofpacket -> sram_cs_s1_agent:rf_sink_endofpacket
wire sram_cs_s1_agent_rdata_fifo_src_valid; // sram_cs_s1_agent:rdata_fifo_src_valid -> sram_cs_s1_agent:rdata_fifo_sink_valid
wire [33:0] sram_cs_s1_agent_rdata_fifo_src_data; // sram_cs_s1_agent:rdata_fifo_src_data -> sram_cs_s1_agent:rdata_fifo_sink_data
wire sram_cs_s1_agent_rdata_fifo_src_ready; // sram_cs_s1_agent:rdata_fifo_sink_ready -> sram_cs_s1_agent:rdata_fifo_src_ready
wire cmd_mux_008_src_valid; // cmd_mux_008:src_valid -> sram_cs_s1_agent:cp_valid
wire [98:0] cmd_mux_008_src_data; // cmd_mux_008:src_data -> sram_cs_s1_agent:cp_data
wire cmd_mux_008_src_ready; // sram_cs_s1_agent:cp_ready -> cmd_mux_008:src_ready
wire [31:0] cmd_mux_008_src_channel; // cmd_mux_008:src_channel -> sram_cs_s1_agent:cp_channel
wire cmd_mux_008_src_startofpacket; // cmd_mux_008:src_startofpacket -> sram_cs_s1_agent:cp_startofpacket
wire cmd_mux_008_src_endofpacket; // cmd_mux_008:src_endofpacket -> sram_cs_s1_agent:cp_endofpacket
wire [31:0] sram_oe_s1_agent_m0_readdata; // sram_oe_s1_translator:uav_readdata -> sram_oe_s1_agent:m0_readdata
wire sram_oe_s1_agent_m0_waitrequest; // sram_oe_s1_translator:uav_waitrequest -> sram_oe_s1_agent:m0_waitrequest
wire sram_oe_s1_agent_m0_debugaccess; // sram_oe_s1_agent:m0_debugaccess -> sram_oe_s1_translator:uav_debugaccess
wire [18:0] sram_oe_s1_agent_m0_address; // sram_oe_s1_agent:m0_address -> sram_oe_s1_translator:uav_address
wire [3:0] sram_oe_s1_agent_m0_byteenable; // sram_oe_s1_agent:m0_byteenable -> sram_oe_s1_translator:uav_byteenable
wire sram_oe_s1_agent_m0_read; // sram_oe_s1_agent:m0_read -> sram_oe_s1_translator:uav_read
wire sram_oe_s1_agent_m0_readdatavalid; // sram_oe_s1_translator:uav_readdatavalid -> sram_oe_s1_agent:m0_readdatavalid
wire sram_oe_s1_agent_m0_lock; // sram_oe_s1_agent:m0_lock -> sram_oe_s1_translator:uav_lock
wire [31:0] sram_oe_s1_agent_m0_writedata; // sram_oe_s1_agent:m0_writedata -> sram_oe_s1_translator:uav_writedata
wire sram_oe_s1_agent_m0_write; // sram_oe_s1_agent:m0_write -> sram_oe_s1_translator:uav_write
wire [2:0] sram_oe_s1_agent_m0_burstcount; // sram_oe_s1_agent:m0_burstcount -> sram_oe_s1_translator:uav_burstcount
wire sram_oe_s1_agent_rf_source_valid; // sram_oe_s1_agent:rf_source_valid -> sram_oe_s1_agent_rsp_fifo:in_valid
wire [99:0] sram_oe_s1_agent_rf_source_data; // sram_oe_s1_agent:rf_source_data -> sram_oe_s1_agent_rsp_fifo:in_data
wire sram_oe_s1_agent_rf_source_ready; // sram_oe_s1_agent_rsp_fifo:in_ready -> sram_oe_s1_agent:rf_source_ready
wire sram_oe_s1_agent_rf_source_startofpacket; // sram_oe_s1_agent:rf_source_startofpacket -> sram_oe_s1_agent_rsp_fifo:in_startofpacket
wire sram_oe_s1_agent_rf_source_endofpacket; // sram_oe_s1_agent:rf_source_endofpacket -> sram_oe_s1_agent_rsp_fifo:in_endofpacket
wire sram_oe_s1_agent_rsp_fifo_out_valid; // sram_oe_s1_agent_rsp_fifo:out_valid -> sram_oe_s1_agent:rf_sink_valid
wire [99:0] sram_oe_s1_agent_rsp_fifo_out_data; // sram_oe_s1_agent_rsp_fifo:out_data -> sram_oe_s1_agent:rf_sink_data
wire sram_oe_s1_agent_rsp_fifo_out_ready; // sram_oe_s1_agent:rf_sink_ready -> sram_oe_s1_agent_rsp_fifo:out_ready
wire sram_oe_s1_agent_rsp_fifo_out_startofpacket; // sram_oe_s1_agent_rsp_fifo:out_startofpacket -> sram_oe_s1_agent:rf_sink_startofpacket
wire sram_oe_s1_agent_rsp_fifo_out_endofpacket; // sram_oe_s1_agent_rsp_fifo:out_endofpacket -> sram_oe_s1_agent:rf_sink_endofpacket
wire sram_oe_s1_agent_rdata_fifo_src_valid; // sram_oe_s1_agent:rdata_fifo_src_valid -> sram_oe_s1_agent:rdata_fifo_sink_valid
wire [33:0] sram_oe_s1_agent_rdata_fifo_src_data; // sram_oe_s1_agent:rdata_fifo_src_data -> sram_oe_s1_agent:rdata_fifo_sink_data
wire sram_oe_s1_agent_rdata_fifo_src_ready; // sram_oe_s1_agent:rdata_fifo_sink_ready -> sram_oe_s1_agent:rdata_fifo_src_ready
wire cmd_mux_009_src_valid; // cmd_mux_009:src_valid -> sram_oe_s1_agent:cp_valid
wire [98:0] cmd_mux_009_src_data; // cmd_mux_009:src_data -> sram_oe_s1_agent:cp_data
wire cmd_mux_009_src_ready; // sram_oe_s1_agent:cp_ready -> cmd_mux_009:src_ready
wire [31:0] cmd_mux_009_src_channel; // cmd_mux_009:src_channel -> sram_oe_s1_agent:cp_channel
wire cmd_mux_009_src_startofpacket; // cmd_mux_009:src_startofpacket -> sram_oe_s1_agent:cp_startofpacket
wire cmd_mux_009_src_endofpacket; // cmd_mux_009:src_endofpacket -> sram_oe_s1_agent:cp_endofpacket
wire [31:0] regfile_data_s1_agent_m0_readdata; // regfile_data_s1_translator:uav_readdata -> regfile_data_s1_agent:m0_readdata
wire regfile_data_s1_agent_m0_waitrequest; // regfile_data_s1_translator:uav_waitrequest -> regfile_data_s1_agent:m0_waitrequest
wire regfile_data_s1_agent_m0_debugaccess; // regfile_data_s1_agent:m0_debugaccess -> regfile_data_s1_translator:uav_debugaccess
wire [18:0] regfile_data_s1_agent_m0_address; // regfile_data_s1_agent:m0_address -> regfile_data_s1_translator:uav_address
wire [3:0] regfile_data_s1_agent_m0_byteenable; // regfile_data_s1_agent:m0_byteenable -> regfile_data_s1_translator:uav_byteenable
wire regfile_data_s1_agent_m0_read; // regfile_data_s1_agent:m0_read -> regfile_data_s1_translator:uav_read
wire regfile_data_s1_agent_m0_readdatavalid; // regfile_data_s1_translator:uav_readdatavalid -> regfile_data_s1_agent:m0_readdatavalid
wire regfile_data_s1_agent_m0_lock; // regfile_data_s1_agent:m0_lock -> regfile_data_s1_translator:uav_lock
wire [31:0] regfile_data_s1_agent_m0_writedata; // regfile_data_s1_agent:m0_writedata -> regfile_data_s1_translator:uav_writedata
wire regfile_data_s1_agent_m0_write; // regfile_data_s1_agent:m0_write -> regfile_data_s1_translator:uav_write
wire [2:0] regfile_data_s1_agent_m0_burstcount; // regfile_data_s1_agent:m0_burstcount -> regfile_data_s1_translator:uav_burstcount
wire regfile_data_s1_agent_rf_source_valid; // regfile_data_s1_agent:rf_source_valid -> regfile_data_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_data_s1_agent_rf_source_data; // regfile_data_s1_agent:rf_source_data -> regfile_data_s1_agent_rsp_fifo:in_data
wire regfile_data_s1_agent_rf_source_ready; // regfile_data_s1_agent_rsp_fifo:in_ready -> regfile_data_s1_agent:rf_source_ready
wire regfile_data_s1_agent_rf_source_startofpacket; // regfile_data_s1_agent:rf_source_startofpacket -> regfile_data_s1_agent_rsp_fifo:in_startofpacket
wire regfile_data_s1_agent_rf_source_endofpacket; // regfile_data_s1_agent:rf_source_endofpacket -> regfile_data_s1_agent_rsp_fifo:in_endofpacket
wire regfile_data_s1_agent_rsp_fifo_out_valid; // regfile_data_s1_agent_rsp_fifo:out_valid -> regfile_data_s1_agent:rf_sink_valid
wire [99:0] regfile_data_s1_agent_rsp_fifo_out_data; // regfile_data_s1_agent_rsp_fifo:out_data -> regfile_data_s1_agent:rf_sink_data
wire regfile_data_s1_agent_rsp_fifo_out_ready; // regfile_data_s1_agent:rf_sink_ready -> regfile_data_s1_agent_rsp_fifo:out_ready
wire regfile_data_s1_agent_rsp_fifo_out_startofpacket; // regfile_data_s1_agent_rsp_fifo:out_startofpacket -> regfile_data_s1_agent:rf_sink_startofpacket
wire regfile_data_s1_agent_rsp_fifo_out_endofpacket; // regfile_data_s1_agent_rsp_fifo:out_endofpacket -> regfile_data_s1_agent:rf_sink_endofpacket
wire regfile_data_s1_agent_rdata_fifo_src_valid; // regfile_data_s1_agent:rdata_fifo_src_valid -> regfile_data_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_data_s1_agent_rdata_fifo_src_data; // regfile_data_s1_agent:rdata_fifo_src_data -> regfile_data_s1_agent:rdata_fifo_sink_data
wire regfile_data_s1_agent_rdata_fifo_src_ready; // regfile_data_s1_agent:rdata_fifo_sink_ready -> regfile_data_s1_agent:rdata_fifo_src_ready
wire cmd_mux_010_src_valid; // cmd_mux_010:src_valid -> regfile_data_s1_agent:cp_valid
wire [98:0] cmd_mux_010_src_data; // cmd_mux_010:src_data -> regfile_data_s1_agent:cp_data
wire cmd_mux_010_src_ready; // regfile_data_s1_agent:cp_ready -> cmd_mux_010:src_ready
wire [31:0] cmd_mux_010_src_channel; // cmd_mux_010:src_channel -> regfile_data_s1_agent:cp_channel
wire cmd_mux_010_src_startofpacket; // cmd_mux_010:src_startofpacket -> regfile_data_s1_agent:cp_startofpacket
wire cmd_mux_010_src_endofpacket; // cmd_mux_010:src_endofpacket -> regfile_data_s1_agent:cp_endofpacket
wire [31:0] regfile_reg1_s1_agent_m0_readdata; // regfile_reg1_s1_translator:uav_readdata -> regfile_reg1_s1_agent:m0_readdata
wire regfile_reg1_s1_agent_m0_waitrequest; // regfile_reg1_s1_translator:uav_waitrequest -> regfile_reg1_s1_agent:m0_waitrequest
wire regfile_reg1_s1_agent_m0_debugaccess; // regfile_reg1_s1_agent:m0_debugaccess -> regfile_reg1_s1_translator:uav_debugaccess
wire [18:0] regfile_reg1_s1_agent_m0_address; // regfile_reg1_s1_agent:m0_address -> regfile_reg1_s1_translator:uav_address
wire [3:0] regfile_reg1_s1_agent_m0_byteenable; // regfile_reg1_s1_agent:m0_byteenable -> regfile_reg1_s1_translator:uav_byteenable
wire regfile_reg1_s1_agent_m0_read; // regfile_reg1_s1_agent:m0_read -> regfile_reg1_s1_translator:uav_read
wire regfile_reg1_s1_agent_m0_readdatavalid; // regfile_reg1_s1_translator:uav_readdatavalid -> regfile_reg1_s1_agent:m0_readdatavalid
wire regfile_reg1_s1_agent_m0_lock; // regfile_reg1_s1_agent:m0_lock -> regfile_reg1_s1_translator:uav_lock
wire [31:0] regfile_reg1_s1_agent_m0_writedata; // regfile_reg1_s1_agent:m0_writedata -> regfile_reg1_s1_translator:uav_writedata
wire regfile_reg1_s1_agent_m0_write; // regfile_reg1_s1_agent:m0_write -> regfile_reg1_s1_translator:uav_write
wire [2:0] regfile_reg1_s1_agent_m0_burstcount; // regfile_reg1_s1_agent:m0_burstcount -> regfile_reg1_s1_translator:uav_burstcount
wire regfile_reg1_s1_agent_rf_source_valid; // regfile_reg1_s1_agent:rf_source_valid -> regfile_reg1_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_reg1_s1_agent_rf_source_data; // regfile_reg1_s1_agent:rf_source_data -> regfile_reg1_s1_agent_rsp_fifo:in_data
wire regfile_reg1_s1_agent_rf_source_ready; // regfile_reg1_s1_agent_rsp_fifo:in_ready -> regfile_reg1_s1_agent:rf_source_ready
wire regfile_reg1_s1_agent_rf_source_startofpacket; // regfile_reg1_s1_agent:rf_source_startofpacket -> regfile_reg1_s1_agent_rsp_fifo:in_startofpacket
wire regfile_reg1_s1_agent_rf_source_endofpacket; // regfile_reg1_s1_agent:rf_source_endofpacket -> regfile_reg1_s1_agent_rsp_fifo:in_endofpacket
wire regfile_reg1_s1_agent_rsp_fifo_out_valid; // regfile_reg1_s1_agent_rsp_fifo:out_valid -> regfile_reg1_s1_agent:rf_sink_valid
wire [99:0] regfile_reg1_s1_agent_rsp_fifo_out_data; // regfile_reg1_s1_agent_rsp_fifo:out_data -> regfile_reg1_s1_agent:rf_sink_data
wire regfile_reg1_s1_agent_rsp_fifo_out_ready; // regfile_reg1_s1_agent:rf_sink_ready -> regfile_reg1_s1_agent_rsp_fifo:out_ready
wire regfile_reg1_s1_agent_rsp_fifo_out_startofpacket; // regfile_reg1_s1_agent_rsp_fifo:out_startofpacket -> regfile_reg1_s1_agent:rf_sink_startofpacket
wire regfile_reg1_s1_agent_rsp_fifo_out_endofpacket; // regfile_reg1_s1_agent_rsp_fifo:out_endofpacket -> regfile_reg1_s1_agent:rf_sink_endofpacket
wire regfile_reg1_s1_agent_rdata_fifo_src_valid; // regfile_reg1_s1_agent:rdata_fifo_src_valid -> regfile_reg1_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_reg1_s1_agent_rdata_fifo_src_data; // regfile_reg1_s1_agent:rdata_fifo_src_data -> regfile_reg1_s1_agent:rdata_fifo_sink_data
wire regfile_reg1_s1_agent_rdata_fifo_src_ready; // regfile_reg1_s1_agent:rdata_fifo_sink_ready -> regfile_reg1_s1_agent:rdata_fifo_src_ready
wire cmd_mux_011_src_valid; // cmd_mux_011:src_valid -> regfile_reg1_s1_agent:cp_valid
wire [98:0] cmd_mux_011_src_data; // cmd_mux_011:src_data -> regfile_reg1_s1_agent:cp_data
wire cmd_mux_011_src_ready; // regfile_reg1_s1_agent:cp_ready -> cmd_mux_011:src_ready
wire [31:0] cmd_mux_011_src_channel; // cmd_mux_011:src_channel -> regfile_reg1_s1_agent:cp_channel
wire cmd_mux_011_src_startofpacket; // cmd_mux_011:src_startofpacket -> regfile_reg1_s1_agent:cp_startofpacket
wire cmd_mux_011_src_endofpacket; // cmd_mux_011:src_endofpacket -> regfile_reg1_s1_agent:cp_endofpacket
wire [31:0] regfile_reg2_s1_agent_m0_readdata; // regfile_reg2_s1_translator:uav_readdata -> regfile_reg2_s1_agent:m0_readdata
wire regfile_reg2_s1_agent_m0_waitrequest; // regfile_reg2_s1_translator:uav_waitrequest -> regfile_reg2_s1_agent:m0_waitrequest
wire regfile_reg2_s1_agent_m0_debugaccess; // regfile_reg2_s1_agent:m0_debugaccess -> regfile_reg2_s1_translator:uav_debugaccess
wire [18:0] regfile_reg2_s1_agent_m0_address; // regfile_reg2_s1_agent:m0_address -> regfile_reg2_s1_translator:uav_address
wire [3:0] regfile_reg2_s1_agent_m0_byteenable; // regfile_reg2_s1_agent:m0_byteenable -> regfile_reg2_s1_translator:uav_byteenable
wire regfile_reg2_s1_agent_m0_read; // regfile_reg2_s1_agent:m0_read -> regfile_reg2_s1_translator:uav_read
wire regfile_reg2_s1_agent_m0_readdatavalid; // regfile_reg2_s1_translator:uav_readdatavalid -> regfile_reg2_s1_agent:m0_readdatavalid
wire regfile_reg2_s1_agent_m0_lock; // regfile_reg2_s1_agent:m0_lock -> regfile_reg2_s1_translator:uav_lock
wire [31:0] regfile_reg2_s1_agent_m0_writedata; // regfile_reg2_s1_agent:m0_writedata -> regfile_reg2_s1_translator:uav_writedata
wire regfile_reg2_s1_agent_m0_write; // regfile_reg2_s1_agent:m0_write -> regfile_reg2_s1_translator:uav_write
wire [2:0] regfile_reg2_s1_agent_m0_burstcount; // regfile_reg2_s1_agent:m0_burstcount -> regfile_reg2_s1_translator:uav_burstcount
wire regfile_reg2_s1_agent_rf_source_valid; // regfile_reg2_s1_agent:rf_source_valid -> regfile_reg2_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_reg2_s1_agent_rf_source_data; // regfile_reg2_s1_agent:rf_source_data -> regfile_reg2_s1_agent_rsp_fifo:in_data
wire regfile_reg2_s1_agent_rf_source_ready; // regfile_reg2_s1_agent_rsp_fifo:in_ready -> regfile_reg2_s1_agent:rf_source_ready
wire regfile_reg2_s1_agent_rf_source_startofpacket; // regfile_reg2_s1_agent:rf_source_startofpacket -> regfile_reg2_s1_agent_rsp_fifo:in_startofpacket
wire regfile_reg2_s1_agent_rf_source_endofpacket; // regfile_reg2_s1_agent:rf_source_endofpacket -> regfile_reg2_s1_agent_rsp_fifo:in_endofpacket
wire regfile_reg2_s1_agent_rsp_fifo_out_valid; // regfile_reg2_s1_agent_rsp_fifo:out_valid -> regfile_reg2_s1_agent:rf_sink_valid
wire [99:0] regfile_reg2_s1_agent_rsp_fifo_out_data; // regfile_reg2_s1_agent_rsp_fifo:out_data -> regfile_reg2_s1_agent:rf_sink_data
wire regfile_reg2_s1_agent_rsp_fifo_out_ready; // regfile_reg2_s1_agent:rf_sink_ready -> regfile_reg2_s1_agent_rsp_fifo:out_ready
wire regfile_reg2_s1_agent_rsp_fifo_out_startofpacket; // regfile_reg2_s1_agent_rsp_fifo:out_startofpacket -> regfile_reg2_s1_agent:rf_sink_startofpacket
wire regfile_reg2_s1_agent_rsp_fifo_out_endofpacket; // regfile_reg2_s1_agent_rsp_fifo:out_endofpacket -> regfile_reg2_s1_agent:rf_sink_endofpacket
wire regfile_reg2_s1_agent_rdata_fifo_src_valid; // regfile_reg2_s1_agent:rdata_fifo_src_valid -> regfile_reg2_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_reg2_s1_agent_rdata_fifo_src_data; // regfile_reg2_s1_agent:rdata_fifo_src_data -> regfile_reg2_s1_agent:rdata_fifo_sink_data
wire regfile_reg2_s1_agent_rdata_fifo_src_ready; // regfile_reg2_s1_agent:rdata_fifo_sink_ready -> regfile_reg2_s1_agent:rdata_fifo_src_ready
wire cmd_mux_012_src_valid; // cmd_mux_012:src_valid -> regfile_reg2_s1_agent:cp_valid
wire [98:0] cmd_mux_012_src_data; // cmd_mux_012:src_data -> regfile_reg2_s1_agent:cp_data
wire cmd_mux_012_src_ready; // regfile_reg2_s1_agent:cp_ready -> cmd_mux_012:src_ready
wire [31:0] cmd_mux_012_src_channel; // cmd_mux_012:src_channel -> regfile_reg2_s1_agent:cp_channel
wire cmd_mux_012_src_startofpacket; // cmd_mux_012:src_startofpacket -> regfile_reg2_s1_agent:cp_startofpacket
wire cmd_mux_012_src_endofpacket; // cmd_mux_012:src_endofpacket -> regfile_reg2_s1_agent:cp_endofpacket
wire [31:0] regfile_r1sel_s1_agent_m0_readdata; // regfile_r1sel_s1_translator:uav_readdata -> regfile_r1sel_s1_agent:m0_readdata
wire regfile_r1sel_s1_agent_m0_waitrequest; // regfile_r1sel_s1_translator:uav_waitrequest -> regfile_r1sel_s1_agent:m0_waitrequest
wire regfile_r1sel_s1_agent_m0_debugaccess; // regfile_r1sel_s1_agent:m0_debugaccess -> regfile_r1sel_s1_translator:uav_debugaccess
wire [18:0] regfile_r1sel_s1_agent_m0_address; // regfile_r1sel_s1_agent:m0_address -> regfile_r1sel_s1_translator:uav_address
wire [3:0] regfile_r1sel_s1_agent_m0_byteenable; // regfile_r1sel_s1_agent:m0_byteenable -> regfile_r1sel_s1_translator:uav_byteenable
wire regfile_r1sel_s1_agent_m0_read; // regfile_r1sel_s1_agent:m0_read -> regfile_r1sel_s1_translator:uav_read
wire regfile_r1sel_s1_agent_m0_readdatavalid; // regfile_r1sel_s1_translator:uav_readdatavalid -> regfile_r1sel_s1_agent:m0_readdatavalid
wire regfile_r1sel_s1_agent_m0_lock; // regfile_r1sel_s1_agent:m0_lock -> regfile_r1sel_s1_translator:uav_lock
wire [31:0] regfile_r1sel_s1_agent_m0_writedata; // regfile_r1sel_s1_agent:m0_writedata -> regfile_r1sel_s1_translator:uav_writedata
wire regfile_r1sel_s1_agent_m0_write; // regfile_r1sel_s1_agent:m0_write -> regfile_r1sel_s1_translator:uav_write
wire [2:0] regfile_r1sel_s1_agent_m0_burstcount; // regfile_r1sel_s1_agent:m0_burstcount -> regfile_r1sel_s1_translator:uav_burstcount
wire regfile_r1sel_s1_agent_rf_source_valid; // regfile_r1sel_s1_agent:rf_source_valid -> regfile_r1sel_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_r1sel_s1_agent_rf_source_data; // regfile_r1sel_s1_agent:rf_source_data -> regfile_r1sel_s1_agent_rsp_fifo:in_data
wire regfile_r1sel_s1_agent_rf_source_ready; // regfile_r1sel_s1_agent_rsp_fifo:in_ready -> regfile_r1sel_s1_agent:rf_source_ready
wire regfile_r1sel_s1_agent_rf_source_startofpacket; // regfile_r1sel_s1_agent:rf_source_startofpacket -> regfile_r1sel_s1_agent_rsp_fifo:in_startofpacket
wire regfile_r1sel_s1_agent_rf_source_endofpacket; // regfile_r1sel_s1_agent:rf_source_endofpacket -> regfile_r1sel_s1_agent_rsp_fifo:in_endofpacket
wire regfile_r1sel_s1_agent_rsp_fifo_out_valid; // regfile_r1sel_s1_agent_rsp_fifo:out_valid -> regfile_r1sel_s1_agent:rf_sink_valid
wire [99:0] regfile_r1sel_s1_agent_rsp_fifo_out_data; // regfile_r1sel_s1_agent_rsp_fifo:out_data -> regfile_r1sel_s1_agent:rf_sink_data
wire regfile_r1sel_s1_agent_rsp_fifo_out_ready; // regfile_r1sel_s1_agent:rf_sink_ready -> regfile_r1sel_s1_agent_rsp_fifo:out_ready
wire regfile_r1sel_s1_agent_rsp_fifo_out_startofpacket; // regfile_r1sel_s1_agent_rsp_fifo:out_startofpacket -> regfile_r1sel_s1_agent:rf_sink_startofpacket
wire regfile_r1sel_s1_agent_rsp_fifo_out_endofpacket; // regfile_r1sel_s1_agent_rsp_fifo:out_endofpacket -> regfile_r1sel_s1_agent:rf_sink_endofpacket
wire regfile_r1sel_s1_agent_rdata_fifo_src_valid; // regfile_r1sel_s1_agent:rdata_fifo_src_valid -> regfile_r1sel_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_r1sel_s1_agent_rdata_fifo_src_data; // regfile_r1sel_s1_agent:rdata_fifo_src_data -> regfile_r1sel_s1_agent:rdata_fifo_sink_data
wire regfile_r1sel_s1_agent_rdata_fifo_src_ready; // regfile_r1sel_s1_agent:rdata_fifo_sink_ready -> regfile_r1sel_s1_agent:rdata_fifo_src_ready
wire cmd_mux_013_src_valid; // cmd_mux_013:src_valid -> regfile_r1sel_s1_agent:cp_valid
wire [98:0] cmd_mux_013_src_data; // cmd_mux_013:src_data -> regfile_r1sel_s1_agent:cp_data
wire cmd_mux_013_src_ready; // regfile_r1sel_s1_agent:cp_ready -> cmd_mux_013:src_ready
wire [31:0] cmd_mux_013_src_channel; // cmd_mux_013:src_channel -> regfile_r1sel_s1_agent:cp_channel
wire cmd_mux_013_src_startofpacket; // cmd_mux_013:src_startofpacket -> regfile_r1sel_s1_agent:cp_startofpacket
wire cmd_mux_013_src_endofpacket; // cmd_mux_013:src_endofpacket -> regfile_r1sel_s1_agent:cp_endofpacket
wire [31:0] regfile_r2sel_s1_agent_m0_readdata; // regfile_r2sel_s1_translator:uav_readdata -> regfile_r2sel_s1_agent:m0_readdata
wire regfile_r2sel_s1_agent_m0_waitrequest; // regfile_r2sel_s1_translator:uav_waitrequest -> regfile_r2sel_s1_agent:m0_waitrequest
wire regfile_r2sel_s1_agent_m0_debugaccess; // regfile_r2sel_s1_agent:m0_debugaccess -> regfile_r2sel_s1_translator:uav_debugaccess
wire [18:0] regfile_r2sel_s1_agent_m0_address; // regfile_r2sel_s1_agent:m0_address -> regfile_r2sel_s1_translator:uav_address
wire [3:0] regfile_r2sel_s1_agent_m0_byteenable; // regfile_r2sel_s1_agent:m0_byteenable -> regfile_r2sel_s1_translator:uav_byteenable
wire regfile_r2sel_s1_agent_m0_read; // regfile_r2sel_s1_agent:m0_read -> regfile_r2sel_s1_translator:uav_read
wire regfile_r2sel_s1_agent_m0_readdatavalid; // regfile_r2sel_s1_translator:uav_readdatavalid -> regfile_r2sel_s1_agent:m0_readdatavalid
wire regfile_r2sel_s1_agent_m0_lock; // regfile_r2sel_s1_agent:m0_lock -> regfile_r2sel_s1_translator:uav_lock
wire [31:0] regfile_r2sel_s1_agent_m0_writedata; // regfile_r2sel_s1_agent:m0_writedata -> regfile_r2sel_s1_translator:uav_writedata
wire regfile_r2sel_s1_agent_m0_write; // regfile_r2sel_s1_agent:m0_write -> regfile_r2sel_s1_translator:uav_write
wire [2:0] regfile_r2sel_s1_agent_m0_burstcount; // regfile_r2sel_s1_agent:m0_burstcount -> regfile_r2sel_s1_translator:uav_burstcount
wire regfile_r2sel_s1_agent_rf_source_valid; // regfile_r2sel_s1_agent:rf_source_valid -> regfile_r2sel_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_r2sel_s1_agent_rf_source_data; // regfile_r2sel_s1_agent:rf_source_data -> regfile_r2sel_s1_agent_rsp_fifo:in_data
wire regfile_r2sel_s1_agent_rf_source_ready; // regfile_r2sel_s1_agent_rsp_fifo:in_ready -> regfile_r2sel_s1_agent:rf_source_ready
wire regfile_r2sel_s1_agent_rf_source_startofpacket; // regfile_r2sel_s1_agent:rf_source_startofpacket -> regfile_r2sel_s1_agent_rsp_fifo:in_startofpacket
wire regfile_r2sel_s1_agent_rf_source_endofpacket; // regfile_r2sel_s1_agent:rf_source_endofpacket -> regfile_r2sel_s1_agent_rsp_fifo:in_endofpacket
wire regfile_r2sel_s1_agent_rsp_fifo_out_valid; // regfile_r2sel_s1_agent_rsp_fifo:out_valid -> regfile_r2sel_s1_agent:rf_sink_valid
wire [99:0] regfile_r2sel_s1_agent_rsp_fifo_out_data; // regfile_r2sel_s1_agent_rsp_fifo:out_data -> regfile_r2sel_s1_agent:rf_sink_data
wire regfile_r2sel_s1_agent_rsp_fifo_out_ready; // regfile_r2sel_s1_agent:rf_sink_ready -> regfile_r2sel_s1_agent_rsp_fifo:out_ready
wire regfile_r2sel_s1_agent_rsp_fifo_out_startofpacket; // regfile_r2sel_s1_agent_rsp_fifo:out_startofpacket -> regfile_r2sel_s1_agent:rf_sink_startofpacket
wire regfile_r2sel_s1_agent_rsp_fifo_out_endofpacket; // regfile_r2sel_s1_agent_rsp_fifo:out_endofpacket -> regfile_r2sel_s1_agent:rf_sink_endofpacket
wire regfile_r2sel_s1_agent_rdata_fifo_src_valid; // regfile_r2sel_s1_agent:rdata_fifo_src_valid -> regfile_r2sel_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_r2sel_s1_agent_rdata_fifo_src_data; // regfile_r2sel_s1_agent:rdata_fifo_src_data -> regfile_r2sel_s1_agent:rdata_fifo_sink_data
wire regfile_r2sel_s1_agent_rdata_fifo_src_ready; // regfile_r2sel_s1_agent:rdata_fifo_sink_ready -> regfile_r2sel_s1_agent:rdata_fifo_src_ready
wire cmd_mux_014_src_valid; // cmd_mux_014:src_valid -> regfile_r2sel_s1_agent:cp_valid
wire [98:0] cmd_mux_014_src_data; // cmd_mux_014:src_data -> regfile_r2sel_s1_agent:cp_data
wire cmd_mux_014_src_ready; // regfile_r2sel_s1_agent:cp_ready -> cmd_mux_014:src_ready
wire [31:0] cmd_mux_014_src_channel; // cmd_mux_014:src_channel -> regfile_r2sel_s1_agent:cp_channel
wire cmd_mux_014_src_startofpacket; // cmd_mux_014:src_startofpacket -> regfile_r2sel_s1_agent:cp_startofpacket
wire cmd_mux_014_src_endofpacket; // cmd_mux_014:src_endofpacket -> regfile_r2sel_s1_agent:cp_endofpacket
wire [31:0] regfile_wsel_s1_agent_m0_readdata; // regfile_wsel_s1_translator:uav_readdata -> regfile_wsel_s1_agent:m0_readdata
wire regfile_wsel_s1_agent_m0_waitrequest; // regfile_wsel_s1_translator:uav_waitrequest -> regfile_wsel_s1_agent:m0_waitrequest
wire regfile_wsel_s1_agent_m0_debugaccess; // regfile_wsel_s1_agent:m0_debugaccess -> regfile_wsel_s1_translator:uav_debugaccess
wire [18:0] regfile_wsel_s1_agent_m0_address; // regfile_wsel_s1_agent:m0_address -> regfile_wsel_s1_translator:uav_address
wire [3:0] regfile_wsel_s1_agent_m0_byteenable; // regfile_wsel_s1_agent:m0_byteenable -> regfile_wsel_s1_translator:uav_byteenable
wire regfile_wsel_s1_agent_m0_read; // regfile_wsel_s1_agent:m0_read -> regfile_wsel_s1_translator:uav_read
wire regfile_wsel_s1_agent_m0_readdatavalid; // regfile_wsel_s1_translator:uav_readdatavalid -> regfile_wsel_s1_agent:m0_readdatavalid
wire regfile_wsel_s1_agent_m0_lock; // regfile_wsel_s1_agent:m0_lock -> regfile_wsel_s1_translator:uav_lock
wire [31:0] regfile_wsel_s1_agent_m0_writedata; // regfile_wsel_s1_agent:m0_writedata -> regfile_wsel_s1_translator:uav_writedata
wire regfile_wsel_s1_agent_m0_write; // regfile_wsel_s1_agent:m0_write -> regfile_wsel_s1_translator:uav_write
wire [2:0] regfile_wsel_s1_agent_m0_burstcount; // regfile_wsel_s1_agent:m0_burstcount -> regfile_wsel_s1_translator:uav_burstcount
wire regfile_wsel_s1_agent_rf_source_valid; // regfile_wsel_s1_agent:rf_source_valid -> regfile_wsel_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_wsel_s1_agent_rf_source_data; // regfile_wsel_s1_agent:rf_source_data -> regfile_wsel_s1_agent_rsp_fifo:in_data
wire regfile_wsel_s1_agent_rf_source_ready; // regfile_wsel_s1_agent_rsp_fifo:in_ready -> regfile_wsel_s1_agent:rf_source_ready
wire regfile_wsel_s1_agent_rf_source_startofpacket; // regfile_wsel_s1_agent:rf_source_startofpacket -> regfile_wsel_s1_agent_rsp_fifo:in_startofpacket
wire regfile_wsel_s1_agent_rf_source_endofpacket; // regfile_wsel_s1_agent:rf_source_endofpacket -> regfile_wsel_s1_agent_rsp_fifo:in_endofpacket
wire regfile_wsel_s1_agent_rsp_fifo_out_valid; // regfile_wsel_s1_agent_rsp_fifo:out_valid -> regfile_wsel_s1_agent:rf_sink_valid
wire [99:0] regfile_wsel_s1_agent_rsp_fifo_out_data; // regfile_wsel_s1_agent_rsp_fifo:out_data -> regfile_wsel_s1_agent:rf_sink_data
wire regfile_wsel_s1_agent_rsp_fifo_out_ready; // regfile_wsel_s1_agent:rf_sink_ready -> regfile_wsel_s1_agent_rsp_fifo:out_ready
wire regfile_wsel_s1_agent_rsp_fifo_out_startofpacket; // regfile_wsel_s1_agent_rsp_fifo:out_startofpacket -> regfile_wsel_s1_agent:rf_sink_startofpacket
wire regfile_wsel_s1_agent_rsp_fifo_out_endofpacket; // regfile_wsel_s1_agent_rsp_fifo:out_endofpacket -> regfile_wsel_s1_agent:rf_sink_endofpacket
wire regfile_wsel_s1_agent_rdata_fifo_src_valid; // regfile_wsel_s1_agent:rdata_fifo_src_valid -> regfile_wsel_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_wsel_s1_agent_rdata_fifo_src_data; // regfile_wsel_s1_agent:rdata_fifo_src_data -> regfile_wsel_s1_agent:rdata_fifo_sink_data
wire regfile_wsel_s1_agent_rdata_fifo_src_ready; // regfile_wsel_s1_agent:rdata_fifo_sink_ready -> regfile_wsel_s1_agent:rdata_fifo_src_ready
wire cmd_mux_015_src_valid; // cmd_mux_015:src_valid -> regfile_wsel_s1_agent:cp_valid
wire [98:0] cmd_mux_015_src_data; // cmd_mux_015:src_data -> regfile_wsel_s1_agent:cp_data
wire cmd_mux_015_src_ready; // regfile_wsel_s1_agent:cp_ready -> cmd_mux_015:src_ready
wire [31:0] cmd_mux_015_src_channel; // cmd_mux_015:src_channel -> regfile_wsel_s1_agent:cp_channel
wire cmd_mux_015_src_startofpacket; // cmd_mux_015:src_startofpacket -> regfile_wsel_s1_agent:cp_startofpacket
wire cmd_mux_015_src_endofpacket; // cmd_mux_015:src_endofpacket -> regfile_wsel_s1_agent:cp_endofpacket
wire [31:0] regfile_we_s1_agent_m0_readdata; // regfile_we_s1_translator:uav_readdata -> regfile_we_s1_agent:m0_readdata
wire regfile_we_s1_agent_m0_waitrequest; // regfile_we_s1_translator:uav_waitrequest -> regfile_we_s1_agent:m0_waitrequest
wire regfile_we_s1_agent_m0_debugaccess; // regfile_we_s1_agent:m0_debugaccess -> regfile_we_s1_translator:uav_debugaccess
wire [18:0] regfile_we_s1_agent_m0_address; // regfile_we_s1_agent:m0_address -> regfile_we_s1_translator:uav_address
wire [3:0] regfile_we_s1_agent_m0_byteenable; // regfile_we_s1_agent:m0_byteenable -> regfile_we_s1_translator:uav_byteenable
wire regfile_we_s1_agent_m0_read; // regfile_we_s1_agent:m0_read -> regfile_we_s1_translator:uav_read
wire regfile_we_s1_agent_m0_readdatavalid; // regfile_we_s1_translator:uav_readdatavalid -> regfile_we_s1_agent:m0_readdatavalid
wire regfile_we_s1_agent_m0_lock; // regfile_we_s1_agent:m0_lock -> regfile_we_s1_translator:uav_lock
wire [31:0] regfile_we_s1_agent_m0_writedata; // regfile_we_s1_agent:m0_writedata -> regfile_we_s1_translator:uav_writedata
wire regfile_we_s1_agent_m0_write; // regfile_we_s1_agent:m0_write -> regfile_we_s1_translator:uav_write
wire [2:0] regfile_we_s1_agent_m0_burstcount; // regfile_we_s1_agent:m0_burstcount -> regfile_we_s1_translator:uav_burstcount
wire regfile_we_s1_agent_rf_source_valid; // regfile_we_s1_agent:rf_source_valid -> regfile_we_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_we_s1_agent_rf_source_data; // regfile_we_s1_agent:rf_source_data -> regfile_we_s1_agent_rsp_fifo:in_data
wire regfile_we_s1_agent_rf_source_ready; // regfile_we_s1_agent_rsp_fifo:in_ready -> regfile_we_s1_agent:rf_source_ready
wire regfile_we_s1_agent_rf_source_startofpacket; // regfile_we_s1_agent:rf_source_startofpacket -> regfile_we_s1_agent_rsp_fifo:in_startofpacket
wire regfile_we_s1_agent_rf_source_endofpacket; // regfile_we_s1_agent:rf_source_endofpacket -> regfile_we_s1_agent_rsp_fifo:in_endofpacket
wire regfile_we_s1_agent_rsp_fifo_out_valid; // regfile_we_s1_agent_rsp_fifo:out_valid -> regfile_we_s1_agent:rf_sink_valid
wire [99:0] regfile_we_s1_agent_rsp_fifo_out_data; // regfile_we_s1_agent_rsp_fifo:out_data -> regfile_we_s1_agent:rf_sink_data
wire regfile_we_s1_agent_rsp_fifo_out_ready; // regfile_we_s1_agent:rf_sink_ready -> regfile_we_s1_agent_rsp_fifo:out_ready
wire regfile_we_s1_agent_rsp_fifo_out_startofpacket; // regfile_we_s1_agent_rsp_fifo:out_startofpacket -> regfile_we_s1_agent:rf_sink_startofpacket
wire regfile_we_s1_agent_rsp_fifo_out_endofpacket; // regfile_we_s1_agent_rsp_fifo:out_endofpacket -> regfile_we_s1_agent:rf_sink_endofpacket
wire regfile_we_s1_agent_rdata_fifo_src_valid; // regfile_we_s1_agent:rdata_fifo_src_valid -> regfile_we_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_we_s1_agent_rdata_fifo_src_data; // regfile_we_s1_agent:rdata_fifo_src_data -> regfile_we_s1_agent:rdata_fifo_sink_data
wire regfile_we_s1_agent_rdata_fifo_src_ready; // regfile_we_s1_agent:rdata_fifo_sink_ready -> regfile_we_s1_agent:rdata_fifo_src_ready
wire cmd_mux_016_src_valid; // cmd_mux_016:src_valid -> regfile_we_s1_agent:cp_valid
wire [98:0] cmd_mux_016_src_data; // cmd_mux_016:src_data -> regfile_we_s1_agent:cp_data
wire cmd_mux_016_src_ready; // regfile_we_s1_agent:cp_ready -> cmd_mux_016:src_ready
wire [31:0] cmd_mux_016_src_channel; // cmd_mux_016:src_channel -> regfile_we_s1_agent:cp_channel
wire cmd_mux_016_src_startofpacket; // cmd_mux_016:src_startofpacket -> regfile_we_s1_agent:cp_startofpacket
wire cmd_mux_016_src_endofpacket; // cmd_mux_016:src_endofpacket -> regfile_we_s1_agent:cp_endofpacket
wire [31:0] hex_0_s1_agent_m0_readdata; // hex_0_s1_translator:uav_readdata -> hex_0_s1_agent:m0_readdata
wire hex_0_s1_agent_m0_waitrequest; // hex_0_s1_translator:uav_waitrequest -> hex_0_s1_agent:m0_waitrequest
wire hex_0_s1_agent_m0_debugaccess; // hex_0_s1_agent:m0_debugaccess -> hex_0_s1_translator:uav_debugaccess
wire [18:0] hex_0_s1_agent_m0_address; // hex_0_s1_agent:m0_address -> hex_0_s1_translator:uav_address
wire [3:0] hex_0_s1_agent_m0_byteenable; // hex_0_s1_agent:m0_byteenable -> hex_0_s1_translator:uav_byteenable
wire hex_0_s1_agent_m0_read; // hex_0_s1_agent:m0_read -> hex_0_s1_translator:uav_read
wire hex_0_s1_agent_m0_readdatavalid; // hex_0_s1_translator:uav_readdatavalid -> hex_0_s1_agent:m0_readdatavalid
wire hex_0_s1_agent_m0_lock; // hex_0_s1_agent:m0_lock -> hex_0_s1_translator:uav_lock
wire [31:0] hex_0_s1_agent_m0_writedata; // hex_0_s1_agent:m0_writedata -> hex_0_s1_translator:uav_writedata
wire hex_0_s1_agent_m0_write; // hex_0_s1_agent:m0_write -> hex_0_s1_translator:uav_write
wire [2:0] hex_0_s1_agent_m0_burstcount; // hex_0_s1_agent:m0_burstcount -> hex_0_s1_translator:uav_burstcount
wire hex_0_s1_agent_rf_source_valid; // hex_0_s1_agent:rf_source_valid -> hex_0_s1_agent_rsp_fifo:in_valid
wire [99:0] hex_0_s1_agent_rf_source_data; // hex_0_s1_agent:rf_source_data -> hex_0_s1_agent_rsp_fifo:in_data
wire hex_0_s1_agent_rf_source_ready; // hex_0_s1_agent_rsp_fifo:in_ready -> hex_0_s1_agent:rf_source_ready
wire hex_0_s1_agent_rf_source_startofpacket; // hex_0_s1_agent:rf_source_startofpacket -> hex_0_s1_agent_rsp_fifo:in_startofpacket
wire hex_0_s1_agent_rf_source_endofpacket; // hex_0_s1_agent:rf_source_endofpacket -> hex_0_s1_agent_rsp_fifo:in_endofpacket
wire hex_0_s1_agent_rsp_fifo_out_valid; // hex_0_s1_agent_rsp_fifo:out_valid -> hex_0_s1_agent:rf_sink_valid
wire [99:0] hex_0_s1_agent_rsp_fifo_out_data; // hex_0_s1_agent_rsp_fifo:out_data -> hex_0_s1_agent:rf_sink_data
wire hex_0_s1_agent_rsp_fifo_out_ready; // hex_0_s1_agent:rf_sink_ready -> hex_0_s1_agent_rsp_fifo:out_ready
wire hex_0_s1_agent_rsp_fifo_out_startofpacket; // hex_0_s1_agent_rsp_fifo:out_startofpacket -> hex_0_s1_agent:rf_sink_startofpacket
wire hex_0_s1_agent_rsp_fifo_out_endofpacket; // hex_0_s1_agent_rsp_fifo:out_endofpacket -> hex_0_s1_agent:rf_sink_endofpacket
wire hex_0_s1_agent_rdata_fifo_src_valid; // hex_0_s1_agent:rdata_fifo_src_valid -> hex_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] hex_0_s1_agent_rdata_fifo_src_data; // hex_0_s1_agent:rdata_fifo_src_data -> hex_0_s1_agent:rdata_fifo_sink_data
wire hex_0_s1_agent_rdata_fifo_src_ready; // hex_0_s1_agent:rdata_fifo_sink_ready -> hex_0_s1_agent:rdata_fifo_src_ready
wire cmd_mux_017_src_valid; // cmd_mux_017:src_valid -> hex_0_s1_agent:cp_valid
wire [98:0] cmd_mux_017_src_data; // cmd_mux_017:src_data -> hex_0_s1_agent:cp_data
wire cmd_mux_017_src_ready; // hex_0_s1_agent:cp_ready -> cmd_mux_017:src_ready
wire [31:0] cmd_mux_017_src_channel; // cmd_mux_017:src_channel -> hex_0_s1_agent:cp_channel
wire cmd_mux_017_src_startofpacket; // cmd_mux_017:src_startofpacket -> hex_0_s1_agent:cp_startofpacket
wire cmd_mux_017_src_endofpacket; // cmd_mux_017:src_endofpacket -> hex_0_s1_agent:cp_endofpacket
wire [31:0] hex_1_s1_agent_m0_readdata; // hex_1_s1_translator:uav_readdata -> hex_1_s1_agent:m0_readdata
wire hex_1_s1_agent_m0_waitrequest; // hex_1_s1_translator:uav_waitrequest -> hex_1_s1_agent:m0_waitrequest
wire hex_1_s1_agent_m0_debugaccess; // hex_1_s1_agent:m0_debugaccess -> hex_1_s1_translator:uav_debugaccess
wire [18:0] hex_1_s1_agent_m0_address; // hex_1_s1_agent:m0_address -> hex_1_s1_translator:uav_address
wire [3:0] hex_1_s1_agent_m0_byteenable; // hex_1_s1_agent:m0_byteenable -> hex_1_s1_translator:uav_byteenable
wire hex_1_s1_agent_m0_read; // hex_1_s1_agent:m0_read -> hex_1_s1_translator:uav_read
wire hex_1_s1_agent_m0_readdatavalid; // hex_1_s1_translator:uav_readdatavalid -> hex_1_s1_agent:m0_readdatavalid
wire hex_1_s1_agent_m0_lock; // hex_1_s1_agent:m0_lock -> hex_1_s1_translator:uav_lock
wire [31:0] hex_1_s1_agent_m0_writedata; // hex_1_s1_agent:m0_writedata -> hex_1_s1_translator:uav_writedata
wire hex_1_s1_agent_m0_write; // hex_1_s1_agent:m0_write -> hex_1_s1_translator:uav_write
wire [2:0] hex_1_s1_agent_m0_burstcount; // hex_1_s1_agent:m0_burstcount -> hex_1_s1_translator:uav_burstcount
wire hex_1_s1_agent_rf_source_valid; // hex_1_s1_agent:rf_source_valid -> hex_1_s1_agent_rsp_fifo:in_valid
wire [99:0] hex_1_s1_agent_rf_source_data; // hex_1_s1_agent:rf_source_data -> hex_1_s1_agent_rsp_fifo:in_data
wire hex_1_s1_agent_rf_source_ready; // hex_1_s1_agent_rsp_fifo:in_ready -> hex_1_s1_agent:rf_source_ready
wire hex_1_s1_agent_rf_source_startofpacket; // hex_1_s1_agent:rf_source_startofpacket -> hex_1_s1_agent_rsp_fifo:in_startofpacket
wire hex_1_s1_agent_rf_source_endofpacket; // hex_1_s1_agent:rf_source_endofpacket -> hex_1_s1_agent_rsp_fifo:in_endofpacket
wire hex_1_s1_agent_rsp_fifo_out_valid; // hex_1_s1_agent_rsp_fifo:out_valid -> hex_1_s1_agent:rf_sink_valid
wire [99:0] hex_1_s1_agent_rsp_fifo_out_data; // hex_1_s1_agent_rsp_fifo:out_data -> hex_1_s1_agent:rf_sink_data
wire hex_1_s1_agent_rsp_fifo_out_ready; // hex_1_s1_agent:rf_sink_ready -> hex_1_s1_agent_rsp_fifo:out_ready
wire hex_1_s1_agent_rsp_fifo_out_startofpacket; // hex_1_s1_agent_rsp_fifo:out_startofpacket -> hex_1_s1_agent:rf_sink_startofpacket
wire hex_1_s1_agent_rsp_fifo_out_endofpacket; // hex_1_s1_agent_rsp_fifo:out_endofpacket -> hex_1_s1_agent:rf_sink_endofpacket
wire hex_1_s1_agent_rdata_fifo_src_valid; // hex_1_s1_agent:rdata_fifo_src_valid -> hex_1_s1_agent:rdata_fifo_sink_valid
wire [33:0] hex_1_s1_agent_rdata_fifo_src_data; // hex_1_s1_agent:rdata_fifo_src_data -> hex_1_s1_agent:rdata_fifo_sink_data
wire hex_1_s1_agent_rdata_fifo_src_ready; // hex_1_s1_agent:rdata_fifo_sink_ready -> hex_1_s1_agent:rdata_fifo_src_ready
wire cmd_mux_018_src_valid; // cmd_mux_018:src_valid -> hex_1_s1_agent:cp_valid
wire [98:0] cmd_mux_018_src_data; // cmd_mux_018:src_data -> hex_1_s1_agent:cp_data
wire cmd_mux_018_src_ready; // hex_1_s1_agent:cp_ready -> cmd_mux_018:src_ready
wire [31:0] cmd_mux_018_src_channel; // cmd_mux_018:src_channel -> hex_1_s1_agent:cp_channel
wire cmd_mux_018_src_startofpacket; // cmd_mux_018:src_startofpacket -> hex_1_s1_agent:cp_startofpacket
wire cmd_mux_018_src_endofpacket; // cmd_mux_018:src_endofpacket -> hex_1_s1_agent:cp_endofpacket
wire [31:0] hex_2_s1_agent_m0_readdata; // hex_2_s1_translator:uav_readdata -> hex_2_s1_agent:m0_readdata
wire hex_2_s1_agent_m0_waitrequest; // hex_2_s1_translator:uav_waitrequest -> hex_2_s1_agent:m0_waitrequest
wire hex_2_s1_agent_m0_debugaccess; // hex_2_s1_agent:m0_debugaccess -> hex_2_s1_translator:uav_debugaccess
wire [18:0] hex_2_s1_agent_m0_address; // hex_2_s1_agent:m0_address -> hex_2_s1_translator:uav_address
wire [3:0] hex_2_s1_agent_m0_byteenable; // hex_2_s1_agent:m0_byteenable -> hex_2_s1_translator:uav_byteenable
wire hex_2_s1_agent_m0_read; // hex_2_s1_agent:m0_read -> hex_2_s1_translator:uav_read
wire hex_2_s1_agent_m0_readdatavalid; // hex_2_s1_translator:uav_readdatavalid -> hex_2_s1_agent:m0_readdatavalid
wire hex_2_s1_agent_m0_lock; // hex_2_s1_agent:m0_lock -> hex_2_s1_translator:uav_lock
wire [31:0] hex_2_s1_agent_m0_writedata; // hex_2_s1_agent:m0_writedata -> hex_2_s1_translator:uav_writedata
wire hex_2_s1_agent_m0_write; // hex_2_s1_agent:m0_write -> hex_2_s1_translator:uav_write
wire [2:0] hex_2_s1_agent_m0_burstcount; // hex_2_s1_agent:m0_burstcount -> hex_2_s1_translator:uav_burstcount
wire hex_2_s1_agent_rf_source_valid; // hex_2_s1_agent:rf_source_valid -> hex_2_s1_agent_rsp_fifo:in_valid
wire [99:0] hex_2_s1_agent_rf_source_data; // hex_2_s1_agent:rf_source_data -> hex_2_s1_agent_rsp_fifo:in_data
wire hex_2_s1_agent_rf_source_ready; // hex_2_s1_agent_rsp_fifo:in_ready -> hex_2_s1_agent:rf_source_ready
wire hex_2_s1_agent_rf_source_startofpacket; // hex_2_s1_agent:rf_source_startofpacket -> hex_2_s1_agent_rsp_fifo:in_startofpacket
wire hex_2_s1_agent_rf_source_endofpacket; // hex_2_s1_agent:rf_source_endofpacket -> hex_2_s1_agent_rsp_fifo:in_endofpacket
wire hex_2_s1_agent_rsp_fifo_out_valid; // hex_2_s1_agent_rsp_fifo:out_valid -> hex_2_s1_agent:rf_sink_valid
wire [99:0] hex_2_s1_agent_rsp_fifo_out_data; // hex_2_s1_agent_rsp_fifo:out_data -> hex_2_s1_agent:rf_sink_data
wire hex_2_s1_agent_rsp_fifo_out_ready; // hex_2_s1_agent:rf_sink_ready -> hex_2_s1_agent_rsp_fifo:out_ready
wire hex_2_s1_agent_rsp_fifo_out_startofpacket; // hex_2_s1_agent_rsp_fifo:out_startofpacket -> hex_2_s1_agent:rf_sink_startofpacket
wire hex_2_s1_agent_rsp_fifo_out_endofpacket; // hex_2_s1_agent_rsp_fifo:out_endofpacket -> hex_2_s1_agent:rf_sink_endofpacket
wire hex_2_s1_agent_rdata_fifo_src_valid; // hex_2_s1_agent:rdata_fifo_src_valid -> hex_2_s1_agent:rdata_fifo_sink_valid
wire [33:0] hex_2_s1_agent_rdata_fifo_src_data; // hex_2_s1_agent:rdata_fifo_src_data -> hex_2_s1_agent:rdata_fifo_sink_data
wire hex_2_s1_agent_rdata_fifo_src_ready; // hex_2_s1_agent:rdata_fifo_sink_ready -> hex_2_s1_agent:rdata_fifo_src_ready
wire cmd_mux_019_src_valid; // cmd_mux_019:src_valid -> hex_2_s1_agent:cp_valid
wire [98:0] cmd_mux_019_src_data; // cmd_mux_019:src_data -> hex_2_s1_agent:cp_data
wire cmd_mux_019_src_ready; // hex_2_s1_agent:cp_ready -> cmd_mux_019:src_ready
wire [31:0] cmd_mux_019_src_channel; // cmd_mux_019:src_channel -> hex_2_s1_agent:cp_channel
wire cmd_mux_019_src_startofpacket; // cmd_mux_019:src_startofpacket -> hex_2_s1_agent:cp_startofpacket
wire cmd_mux_019_src_endofpacket; // cmd_mux_019:src_endofpacket -> hex_2_s1_agent:cp_endofpacket
wire [31:0] hex_3_s1_agent_m0_readdata; // hex_3_s1_translator:uav_readdata -> hex_3_s1_agent:m0_readdata
wire hex_3_s1_agent_m0_waitrequest; // hex_3_s1_translator:uav_waitrequest -> hex_3_s1_agent:m0_waitrequest
wire hex_3_s1_agent_m0_debugaccess; // hex_3_s1_agent:m0_debugaccess -> hex_3_s1_translator:uav_debugaccess
wire [18:0] hex_3_s1_agent_m0_address; // hex_3_s1_agent:m0_address -> hex_3_s1_translator:uav_address
wire [3:0] hex_3_s1_agent_m0_byteenable; // hex_3_s1_agent:m0_byteenable -> hex_3_s1_translator:uav_byteenable
wire hex_3_s1_agent_m0_read; // hex_3_s1_agent:m0_read -> hex_3_s1_translator:uav_read
wire hex_3_s1_agent_m0_readdatavalid; // hex_3_s1_translator:uav_readdatavalid -> hex_3_s1_agent:m0_readdatavalid
wire hex_3_s1_agent_m0_lock; // hex_3_s1_agent:m0_lock -> hex_3_s1_translator:uav_lock
wire [31:0] hex_3_s1_agent_m0_writedata; // hex_3_s1_agent:m0_writedata -> hex_3_s1_translator:uav_writedata
wire hex_3_s1_agent_m0_write; // hex_3_s1_agent:m0_write -> hex_3_s1_translator:uav_write
wire [2:0] hex_3_s1_agent_m0_burstcount; // hex_3_s1_agent:m0_burstcount -> hex_3_s1_translator:uav_burstcount
wire hex_3_s1_agent_rf_source_valid; // hex_3_s1_agent:rf_source_valid -> hex_3_s1_agent_rsp_fifo:in_valid
wire [99:0] hex_3_s1_agent_rf_source_data; // hex_3_s1_agent:rf_source_data -> hex_3_s1_agent_rsp_fifo:in_data
wire hex_3_s1_agent_rf_source_ready; // hex_3_s1_agent_rsp_fifo:in_ready -> hex_3_s1_agent:rf_source_ready
wire hex_3_s1_agent_rf_source_startofpacket; // hex_3_s1_agent:rf_source_startofpacket -> hex_3_s1_agent_rsp_fifo:in_startofpacket
wire hex_3_s1_agent_rf_source_endofpacket; // hex_3_s1_agent:rf_source_endofpacket -> hex_3_s1_agent_rsp_fifo:in_endofpacket
wire hex_3_s1_agent_rsp_fifo_out_valid; // hex_3_s1_agent_rsp_fifo:out_valid -> hex_3_s1_agent:rf_sink_valid
wire [99:0] hex_3_s1_agent_rsp_fifo_out_data; // hex_3_s1_agent_rsp_fifo:out_data -> hex_3_s1_agent:rf_sink_data
wire hex_3_s1_agent_rsp_fifo_out_ready; // hex_3_s1_agent:rf_sink_ready -> hex_3_s1_agent_rsp_fifo:out_ready
wire hex_3_s1_agent_rsp_fifo_out_startofpacket; // hex_3_s1_agent_rsp_fifo:out_startofpacket -> hex_3_s1_agent:rf_sink_startofpacket
wire hex_3_s1_agent_rsp_fifo_out_endofpacket; // hex_3_s1_agent_rsp_fifo:out_endofpacket -> hex_3_s1_agent:rf_sink_endofpacket
wire hex_3_s1_agent_rdata_fifo_src_valid; // hex_3_s1_agent:rdata_fifo_src_valid -> hex_3_s1_agent:rdata_fifo_sink_valid
wire [33:0] hex_3_s1_agent_rdata_fifo_src_data; // hex_3_s1_agent:rdata_fifo_src_data -> hex_3_s1_agent:rdata_fifo_sink_data
wire hex_3_s1_agent_rdata_fifo_src_ready; // hex_3_s1_agent:rdata_fifo_sink_ready -> hex_3_s1_agent:rdata_fifo_src_ready
wire cmd_mux_020_src_valid; // cmd_mux_020:src_valid -> hex_3_s1_agent:cp_valid
wire [98:0] cmd_mux_020_src_data; // cmd_mux_020:src_data -> hex_3_s1_agent:cp_data
wire cmd_mux_020_src_ready; // hex_3_s1_agent:cp_ready -> cmd_mux_020:src_ready
wire [31:0] cmd_mux_020_src_channel; // cmd_mux_020:src_channel -> hex_3_s1_agent:cp_channel
wire cmd_mux_020_src_startofpacket; // cmd_mux_020:src_startofpacket -> hex_3_s1_agent:cp_startofpacket
wire cmd_mux_020_src_endofpacket; // cmd_mux_020:src_endofpacket -> hex_3_s1_agent:cp_endofpacket
wire [31:0] hex_4_s1_agent_m0_readdata; // hex_4_s1_translator:uav_readdata -> hex_4_s1_agent:m0_readdata
wire hex_4_s1_agent_m0_waitrequest; // hex_4_s1_translator:uav_waitrequest -> hex_4_s1_agent:m0_waitrequest
wire hex_4_s1_agent_m0_debugaccess; // hex_4_s1_agent:m0_debugaccess -> hex_4_s1_translator:uav_debugaccess
wire [18:0] hex_4_s1_agent_m0_address; // hex_4_s1_agent:m0_address -> hex_4_s1_translator:uav_address
wire [3:0] hex_4_s1_agent_m0_byteenable; // hex_4_s1_agent:m0_byteenable -> hex_4_s1_translator:uav_byteenable
wire hex_4_s1_agent_m0_read; // hex_4_s1_agent:m0_read -> hex_4_s1_translator:uav_read
wire hex_4_s1_agent_m0_readdatavalid; // hex_4_s1_translator:uav_readdatavalid -> hex_4_s1_agent:m0_readdatavalid
wire hex_4_s1_agent_m0_lock; // hex_4_s1_agent:m0_lock -> hex_4_s1_translator:uav_lock
wire [31:0] hex_4_s1_agent_m0_writedata; // hex_4_s1_agent:m0_writedata -> hex_4_s1_translator:uav_writedata
wire hex_4_s1_agent_m0_write; // hex_4_s1_agent:m0_write -> hex_4_s1_translator:uav_write
wire [2:0] hex_4_s1_agent_m0_burstcount; // hex_4_s1_agent:m0_burstcount -> hex_4_s1_translator:uav_burstcount
wire hex_4_s1_agent_rf_source_valid; // hex_4_s1_agent:rf_source_valid -> hex_4_s1_agent_rsp_fifo:in_valid
wire [99:0] hex_4_s1_agent_rf_source_data; // hex_4_s1_agent:rf_source_data -> hex_4_s1_agent_rsp_fifo:in_data
wire hex_4_s1_agent_rf_source_ready; // hex_4_s1_agent_rsp_fifo:in_ready -> hex_4_s1_agent:rf_source_ready
wire hex_4_s1_agent_rf_source_startofpacket; // hex_4_s1_agent:rf_source_startofpacket -> hex_4_s1_agent_rsp_fifo:in_startofpacket
wire hex_4_s1_agent_rf_source_endofpacket; // hex_4_s1_agent:rf_source_endofpacket -> hex_4_s1_agent_rsp_fifo:in_endofpacket
wire hex_4_s1_agent_rsp_fifo_out_valid; // hex_4_s1_agent_rsp_fifo:out_valid -> hex_4_s1_agent:rf_sink_valid
wire [99:0] hex_4_s1_agent_rsp_fifo_out_data; // hex_4_s1_agent_rsp_fifo:out_data -> hex_4_s1_agent:rf_sink_data
wire hex_4_s1_agent_rsp_fifo_out_ready; // hex_4_s1_agent:rf_sink_ready -> hex_4_s1_agent_rsp_fifo:out_ready
wire hex_4_s1_agent_rsp_fifo_out_startofpacket; // hex_4_s1_agent_rsp_fifo:out_startofpacket -> hex_4_s1_agent:rf_sink_startofpacket
wire hex_4_s1_agent_rsp_fifo_out_endofpacket; // hex_4_s1_agent_rsp_fifo:out_endofpacket -> hex_4_s1_agent:rf_sink_endofpacket
wire hex_4_s1_agent_rdata_fifo_src_valid; // hex_4_s1_agent:rdata_fifo_src_valid -> hex_4_s1_agent:rdata_fifo_sink_valid
wire [33:0] hex_4_s1_agent_rdata_fifo_src_data; // hex_4_s1_agent:rdata_fifo_src_data -> hex_4_s1_agent:rdata_fifo_sink_data
wire hex_4_s1_agent_rdata_fifo_src_ready; // hex_4_s1_agent:rdata_fifo_sink_ready -> hex_4_s1_agent:rdata_fifo_src_ready
wire cmd_mux_021_src_valid; // cmd_mux_021:src_valid -> hex_4_s1_agent:cp_valid
wire [98:0] cmd_mux_021_src_data; // cmd_mux_021:src_data -> hex_4_s1_agent:cp_data
wire cmd_mux_021_src_ready; // hex_4_s1_agent:cp_ready -> cmd_mux_021:src_ready
wire [31:0] cmd_mux_021_src_channel; // cmd_mux_021:src_channel -> hex_4_s1_agent:cp_channel
wire cmd_mux_021_src_startofpacket; // cmd_mux_021:src_startofpacket -> hex_4_s1_agent:cp_startofpacket
wire cmd_mux_021_src_endofpacket; // cmd_mux_021:src_endofpacket -> hex_4_s1_agent:cp_endofpacket
wire [31:0] hex_5_s1_agent_m0_readdata; // hex_5_s1_translator:uav_readdata -> hex_5_s1_agent:m0_readdata
wire hex_5_s1_agent_m0_waitrequest; // hex_5_s1_translator:uav_waitrequest -> hex_5_s1_agent:m0_waitrequest
wire hex_5_s1_agent_m0_debugaccess; // hex_5_s1_agent:m0_debugaccess -> hex_5_s1_translator:uav_debugaccess
wire [18:0] hex_5_s1_agent_m0_address; // hex_5_s1_agent:m0_address -> hex_5_s1_translator:uav_address
wire [3:0] hex_5_s1_agent_m0_byteenable; // hex_5_s1_agent:m0_byteenable -> hex_5_s1_translator:uav_byteenable
wire hex_5_s1_agent_m0_read; // hex_5_s1_agent:m0_read -> hex_5_s1_translator:uav_read
wire hex_5_s1_agent_m0_readdatavalid; // hex_5_s1_translator:uav_readdatavalid -> hex_5_s1_agent:m0_readdatavalid
wire hex_5_s1_agent_m0_lock; // hex_5_s1_agent:m0_lock -> hex_5_s1_translator:uav_lock
wire [31:0] hex_5_s1_agent_m0_writedata; // hex_5_s1_agent:m0_writedata -> hex_5_s1_translator:uav_writedata
wire hex_5_s1_agent_m0_write; // hex_5_s1_agent:m0_write -> hex_5_s1_translator:uav_write
wire [2:0] hex_5_s1_agent_m0_burstcount; // hex_5_s1_agent:m0_burstcount -> hex_5_s1_translator:uav_burstcount
wire hex_5_s1_agent_rf_source_valid; // hex_5_s1_agent:rf_source_valid -> hex_5_s1_agent_rsp_fifo:in_valid
wire [99:0] hex_5_s1_agent_rf_source_data; // hex_5_s1_agent:rf_source_data -> hex_5_s1_agent_rsp_fifo:in_data
wire hex_5_s1_agent_rf_source_ready; // hex_5_s1_agent_rsp_fifo:in_ready -> hex_5_s1_agent:rf_source_ready
wire hex_5_s1_agent_rf_source_startofpacket; // hex_5_s1_agent:rf_source_startofpacket -> hex_5_s1_agent_rsp_fifo:in_startofpacket
wire hex_5_s1_agent_rf_source_endofpacket; // hex_5_s1_agent:rf_source_endofpacket -> hex_5_s1_agent_rsp_fifo:in_endofpacket
wire hex_5_s1_agent_rsp_fifo_out_valid; // hex_5_s1_agent_rsp_fifo:out_valid -> hex_5_s1_agent:rf_sink_valid
wire [99:0] hex_5_s1_agent_rsp_fifo_out_data; // hex_5_s1_agent_rsp_fifo:out_data -> hex_5_s1_agent:rf_sink_data
wire hex_5_s1_agent_rsp_fifo_out_ready; // hex_5_s1_agent:rf_sink_ready -> hex_5_s1_agent_rsp_fifo:out_ready
wire hex_5_s1_agent_rsp_fifo_out_startofpacket; // hex_5_s1_agent_rsp_fifo:out_startofpacket -> hex_5_s1_agent:rf_sink_startofpacket
wire hex_5_s1_agent_rsp_fifo_out_endofpacket; // hex_5_s1_agent_rsp_fifo:out_endofpacket -> hex_5_s1_agent:rf_sink_endofpacket
wire hex_5_s1_agent_rdata_fifo_src_valid; // hex_5_s1_agent:rdata_fifo_src_valid -> hex_5_s1_agent:rdata_fifo_sink_valid
wire [33:0] hex_5_s1_agent_rdata_fifo_src_data; // hex_5_s1_agent:rdata_fifo_src_data -> hex_5_s1_agent:rdata_fifo_sink_data
wire hex_5_s1_agent_rdata_fifo_src_ready; // hex_5_s1_agent:rdata_fifo_sink_ready -> hex_5_s1_agent:rdata_fifo_src_ready
wire cmd_mux_022_src_valid; // cmd_mux_022:src_valid -> hex_5_s1_agent:cp_valid
wire [98:0] cmd_mux_022_src_data; // cmd_mux_022:src_data -> hex_5_s1_agent:cp_data
wire cmd_mux_022_src_ready; // hex_5_s1_agent:cp_ready -> cmd_mux_022:src_ready
wire [31:0] cmd_mux_022_src_channel; // cmd_mux_022:src_channel -> hex_5_s1_agent:cp_channel
wire cmd_mux_022_src_startofpacket; // cmd_mux_022:src_startofpacket -> hex_5_s1_agent:cp_startofpacket
wire cmd_mux_022_src_endofpacket; // cmd_mux_022:src_endofpacket -> hex_5_s1_agent:cp_endofpacket
wire [31:0] alu_a_s1_agent_m0_readdata; // alu_a_s1_translator:uav_readdata -> alu_a_s1_agent:m0_readdata
wire alu_a_s1_agent_m0_waitrequest; // alu_a_s1_translator:uav_waitrequest -> alu_a_s1_agent:m0_waitrequest
wire alu_a_s1_agent_m0_debugaccess; // alu_a_s1_agent:m0_debugaccess -> alu_a_s1_translator:uav_debugaccess
wire [18:0] alu_a_s1_agent_m0_address; // alu_a_s1_agent:m0_address -> alu_a_s1_translator:uav_address
wire [3:0] alu_a_s1_agent_m0_byteenable; // alu_a_s1_agent:m0_byteenable -> alu_a_s1_translator:uav_byteenable
wire alu_a_s1_agent_m0_read; // alu_a_s1_agent:m0_read -> alu_a_s1_translator:uav_read
wire alu_a_s1_agent_m0_readdatavalid; // alu_a_s1_translator:uav_readdatavalid -> alu_a_s1_agent:m0_readdatavalid
wire alu_a_s1_agent_m0_lock; // alu_a_s1_agent:m0_lock -> alu_a_s1_translator:uav_lock
wire [31:0] alu_a_s1_agent_m0_writedata; // alu_a_s1_agent:m0_writedata -> alu_a_s1_translator:uav_writedata
wire alu_a_s1_agent_m0_write; // alu_a_s1_agent:m0_write -> alu_a_s1_translator:uav_write
wire [2:0] alu_a_s1_agent_m0_burstcount; // alu_a_s1_agent:m0_burstcount -> alu_a_s1_translator:uav_burstcount
wire alu_a_s1_agent_rf_source_valid; // alu_a_s1_agent:rf_source_valid -> alu_a_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_a_s1_agent_rf_source_data; // alu_a_s1_agent:rf_source_data -> alu_a_s1_agent_rsp_fifo:in_data
wire alu_a_s1_agent_rf_source_ready; // alu_a_s1_agent_rsp_fifo:in_ready -> alu_a_s1_agent:rf_source_ready
wire alu_a_s1_agent_rf_source_startofpacket; // alu_a_s1_agent:rf_source_startofpacket -> alu_a_s1_agent_rsp_fifo:in_startofpacket
wire alu_a_s1_agent_rf_source_endofpacket; // alu_a_s1_agent:rf_source_endofpacket -> alu_a_s1_agent_rsp_fifo:in_endofpacket
wire alu_a_s1_agent_rsp_fifo_out_valid; // alu_a_s1_agent_rsp_fifo:out_valid -> alu_a_s1_agent:rf_sink_valid
wire [99:0] alu_a_s1_agent_rsp_fifo_out_data; // alu_a_s1_agent_rsp_fifo:out_data -> alu_a_s1_agent:rf_sink_data
wire alu_a_s1_agent_rsp_fifo_out_ready; // alu_a_s1_agent:rf_sink_ready -> alu_a_s1_agent_rsp_fifo:out_ready
wire alu_a_s1_agent_rsp_fifo_out_startofpacket; // alu_a_s1_agent_rsp_fifo:out_startofpacket -> alu_a_s1_agent:rf_sink_startofpacket
wire alu_a_s1_agent_rsp_fifo_out_endofpacket; // alu_a_s1_agent_rsp_fifo:out_endofpacket -> alu_a_s1_agent:rf_sink_endofpacket
wire alu_a_s1_agent_rdata_fifo_src_valid; // alu_a_s1_agent:rdata_fifo_src_valid -> alu_a_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_a_s1_agent_rdata_fifo_src_data; // alu_a_s1_agent:rdata_fifo_src_data -> alu_a_s1_agent:rdata_fifo_sink_data
wire alu_a_s1_agent_rdata_fifo_src_ready; // alu_a_s1_agent:rdata_fifo_sink_ready -> alu_a_s1_agent:rdata_fifo_src_ready
wire cmd_mux_023_src_valid; // cmd_mux_023:src_valid -> alu_a_s1_agent:cp_valid
wire [98:0] cmd_mux_023_src_data; // cmd_mux_023:src_data -> alu_a_s1_agent:cp_data
wire cmd_mux_023_src_ready; // alu_a_s1_agent:cp_ready -> cmd_mux_023:src_ready
wire [31:0] cmd_mux_023_src_channel; // cmd_mux_023:src_channel -> alu_a_s1_agent:cp_channel
wire cmd_mux_023_src_startofpacket; // cmd_mux_023:src_startofpacket -> alu_a_s1_agent:cp_startofpacket
wire cmd_mux_023_src_endofpacket; // cmd_mux_023:src_endofpacket -> alu_a_s1_agent:cp_endofpacket
wire [31:0] alu_b_s1_agent_m0_readdata; // alu_b_s1_translator:uav_readdata -> alu_b_s1_agent:m0_readdata
wire alu_b_s1_agent_m0_waitrequest; // alu_b_s1_translator:uav_waitrequest -> alu_b_s1_agent:m0_waitrequest
wire alu_b_s1_agent_m0_debugaccess; // alu_b_s1_agent:m0_debugaccess -> alu_b_s1_translator:uav_debugaccess
wire [18:0] alu_b_s1_agent_m0_address; // alu_b_s1_agent:m0_address -> alu_b_s1_translator:uav_address
wire [3:0] alu_b_s1_agent_m0_byteenable; // alu_b_s1_agent:m0_byteenable -> alu_b_s1_translator:uav_byteenable
wire alu_b_s1_agent_m0_read; // alu_b_s1_agent:m0_read -> alu_b_s1_translator:uav_read
wire alu_b_s1_agent_m0_readdatavalid; // alu_b_s1_translator:uav_readdatavalid -> alu_b_s1_agent:m0_readdatavalid
wire alu_b_s1_agent_m0_lock; // alu_b_s1_agent:m0_lock -> alu_b_s1_translator:uav_lock
wire [31:0] alu_b_s1_agent_m0_writedata; // alu_b_s1_agent:m0_writedata -> alu_b_s1_translator:uav_writedata
wire alu_b_s1_agent_m0_write; // alu_b_s1_agent:m0_write -> alu_b_s1_translator:uav_write
wire [2:0] alu_b_s1_agent_m0_burstcount; // alu_b_s1_agent:m0_burstcount -> alu_b_s1_translator:uav_burstcount
wire alu_b_s1_agent_rf_source_valid; // alu_b_s1_agent:rf_source_valid -> alu_b_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_b_s1_agent_rf_source_data; // alu_b_s1_agent:rf_source_data -> alu_b_s1_agent_rsp_fifo:in_data
wire alu_b_s1_agent_rf_source_ready; // alu_b_s1_agent_rsp_fifo:in_ready -> alu_b_s1_agent:rf_source_ready
wire alu_b_s1_agent_rf_source_startofpacket; // alu_b_s1_agent:rf_source_startofpacket -> alu_b_s1_agent_rsp_fifo:in_startofpacket
wire alu_b_s1_agent_rf_source_endofpacket; // alu_b_s1_agent:rf_source_endofpacket -> alu_b_s1_agent_rsp_fifo:in_endofpacket
wire alu_b_s1_agent_rsp_fifo_out_valid; // alu_b_s1_agent_rsp_fifo:out_valid -> alu_b_s1_agent:rf_sink_valid
wire [99:0] alu_b_s1_agent_rsp_fifo_out_data; // alu_b_s1_agent_rsp_fifo:out_data -> alu_b_s1_agent:rf_sink_data
wire alu_b_s1_agent_rsp_fifo_out_ready; // alu_b_s1_agent:rf_sink_ready -> alu_b_s1_agent_rsp_fifo:out_ready
wire alu_b_s1_agent_rsp_fifo_out_startofpacket; // alu_b_s1_agent_rsp_fifo:out_startofpacket -> alu_b_s1_agent:rf_sink_startofpacket
wire alu_b_s1_agent_rsp_fifo_out_endofpacket; // alu_b_s1_agent_rsp_fifo:out_endofpacket -> alu_b_s1_agent:rf_sink_endofpacket
wire alu_b_s1_agent_rdata_fifo_src_valid; // alu_b_s1_agent:rdata_fifo_src_valid -> alu_b_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_b_s1_agent_rdata_fifo_src_data; // alu_b_s1_agent:rdata_fifo_src_data -> alu_b_s1_agent:rdata_fifo_sink_data
wire alu_b_s1_agent_rdata_fifo_src_ready; // alu_b_s1_agent:rdata_fifo_sink_ready -> alu_b_s1_agent:rdata_fifo_src_ready
wire cmd_mux_024_src_valid; // cmd_mux_024:src_valid -> alu_b_s1_agent:cp_valid
wire [98:0] cmd_mux_024_src_data; // cmd_mux_024:src_data -> alu_b_s1_agent:cp_data
wire cmd_mux_024_src_ready; // alu_b_s1_agent:cp_ready -> cmd_mux_024:src_ready
wire [31:0] cmd_mux_024_src_channel; // cmd_mux_024:src_channel -> alu_b_s1_agent:cp_channel
wire cmd_mux_024_src_startofpacket; // cmd_mux_024:src_startofpacket -> alu_b_s1_agent:cp_startofpacket
wire cmd_mux_024_src_endofpacket; // cmd_mux_024:src_endofpacket -> alu_b_s1_agent:cp_endofpacket
wire [31:0] alu_control_s1_agent_m0_readdata; // alu_control_s1_translator:uav_readdata -> alu_control_s1_agent:m0_readdata
wire alu_control_s1_agent_m0_waitrequest; // alu_control_s1_translator:uav_waitrequest -> alu_control_s1_agent:m0_waitrequest
wire alu_control_s1_agent_m0_debugaccess; // alu_control_s1_agent:m0_debugaccess -> alu_control_s1_translator:uav_debugaccess
wire [18:0] alu_control_s1_agent_m0_address; // alu_control_s1_agent:m0_address -> alu_control_s1_translator:uav_address
wire [3:0] alu_control_s1_agent_m0_byteenable; // alu_control_s1_agent:m0_byteenable -> alu_control_s1_translator:uav_byteenable
wire alu_control_s1_agent_m0_read; // alu_control_s1_agent:m0_read -> alu_control_s1_translator:uav_read
wire alu_control_s1_agent_m0_readdatavalid; // alu_control_s1_translator:uav_readdatavalid -> alu_control_s1_agent:m0_readdatavalid
wire alu_control_s1_agent_m0_lock; // alu_control_s1_agent:m0_lock -> alu_control_s1_translator:uav_lock
wire [31:0] alu_control_s1_agent_m0_writedata; // alu_control_s1_agent:m0_writedata -> alu_control_s1_translator:uav_writedata
wire alu_control_s1_agent_m0_write; // alu_control_s1_agent:m0_write -> alu_control_s1_translator:uav_write
wire [2:0] alu_control_s1_agent_m0_burstcount; // alu_control_s1_agent:m0_burstcount -> alu_control_s1_translator:uav_burstcount
wire alu_control_s1_agent_rf_source_valid; // alu_control_s1_agent:rf_source_valid -> alu_control_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_control_s1_agent_rf_source_data; // alu_control_s1_agent:rf_source_data -> alu_control_s1_agent_rsp_fifo:in_data
wire alu_control_s1_agent_rf_source_ready; // alu_control_s1_agent_rsp_fifo:in_ready -> alu_control_s1_agent:rf_source_ready
wire alu_control_s1_agent_rf_source_startofpacket; // alu_control_s1_agent:rf_source_startofpacket -> alu_control_s1_agent_rsp_fifo:in_startofpacket
wire alu_control_s1_agent_rf_source_endofpacket; // alu_control_s1_agent:rf_source_endofpacket -> alu_control_s1_agent_rsp_fifo:in_endofpacket
wire alu_control_s1_agent_rsp_fifo_out_valid; // alu_control_s1_agent_rsp_fifo:out_valid -> alu_control_s1_agent:rf_sink_valid
wire [99:0] alu_control_s1_agent_rsp_fifo_out_data; // alu_control_s1_agent_rsp_fifo:out_data -> alu_control_s1_agent:rf_sink_data
wire alu_control_s1_agent_rsp_fifo_out_ready; // alu_control_s1_agent:rf_sink_ready -> alu_control_s1_agent_rsp_fifo:out_ready
wire alu_control_s1_agent_rsp_fifo_out_startofpacket; // alu_control_s1_agent_rsp_fifo:out_startofpacket -> alu_control_s1_agent:rf_sink_startofpacket
wire alu_control_s1_agent_rsp_fifo_out_endofpacket; // alu_control_s1_agent_rsp_fifo:out_endofpacket -> alu_control_s1_agent:rf_sink_endofpacket
wire alu_control_s1_agent_rdata_fifo_src_valid; // alu_control_s1_agent:rdata_fifo_src_valid -> alu_control_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_control_s1_agent_rdata_fifo_src_data; // alu_control_s1_agent:rdata_fifo_src_data -> alu_control_s1_agent:rdata_fifo_sink_data
wire alu_control_s1_agent_rdata_fifo_src_ready; // alu_control_s1_agent:rdata_fifo_sink_ready -> alu_control_s1_agent:rdata_fifo_src_ready
wire cmd_mux_025_src_valid; // cmd_mux_025:src_valid -> alu_control_s1_agent:cp_valid
wire [98:0] cmd_mux_025_src_data; // cmd_mux_025:src_data -> alu_control_s1_agent:cp_data
wire cmd_mux_025_src_ready; // alu_control_s1_agent:cp_ready -> cmd_mux_025:src_ready
wire [31:0] cmd_mux_025_src_channel; // cmd_mux_025:src_channel -> alu_control_s1_agent:cp_channel
wire cmd_mux_025_src_startofpacket; // cmd_mux_025:src_startofpacket -> alu_control_s1_agent:cp_startofpacket
wire cmd_mux_025_src_endofpacket; // cmd_mux_025:src_endofpacket -> alu_control_s1_agent:cp_endofpacket
wire [31:0] alu_out_s1_agent_m0_readdata; // alu_out_s1_translator:uav_readdata -> alu_out_s1_agent:m0_readdata
wire alu_out_s1_agent_m0_waitrequest; // alu_out_s1_translator:uav_waitrequest -> alu_out_s1_agent:m0_waitrequest
wire alu_out_s1_agent_m0_debugaccess; // alu_out_s1_agent:m0_debugaccess -> alu_out_s1_translator:uav_debugaccess
wire [18:0] alu_out_s1_agent_m0_address; // alu_out_s1_agent:m0_address -> alu_out_s1_translator:uav_address
wire [3:0] alu_out_s1_agent_m0_byteenable; // alu_out_s1_agent:m0_byteenable -> alu_out_s1_translator:uav_byteenable
wire alu_out_s1_agent_m0_read; // alu_out_s1_agent:m0_read -> alu_out_s1_translator:uav_read
wire alu_out_s1_agent_m0_readdatavalid; // alu_out_s1_translator:uav_readdatavalid -> alu_out_s1_agent:m0_readdatavalid
wire alu_out_s1_agent_m0_lock; // alu_out_s1_agent:m0_lock -> alu_out_s1_translator:uav_lock
wire [31:0] alu_out_s1_agent_m0_writedata; // alu_out_s1_agent:m0_writedata -> alu_out_s1_translator:uav_writedata
wire alu_out_s1_agent_m0_write; // alu_out_s1_agent:m0_write -> alu_out_s1_translator:uav_write
wire [2:0] alu_out_s1_agent_m0_burstcount; // alu_out_s1_agent:m0_burstcount -> alu_out_s1_translator:uav_burstcount
wire alu_out_s1_agent_rf_source_valid; // alu_out_s1_agent:rf_source_valid -> alu_out_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_out_s1_agent_rf_source_data; // alu_out_s1_agent:rf_source_data -> alu_out_s1_agent_rsp_fifo:in_data
wire alu_out_s1_agent_rf_source_ready; // alu_out_s1_agent_rsp_fifo:in_ready -> alu_out_s1_agent:rf_source_ready
wire alu_out_s1_agent_rf_source_startofpacket; // alu_out_s1_agent:rf_source_startofpacket -> alu_out_s1_agent_rsp_fifo:in_startofpacket
wire alu_out_s1_agent_rf_source_endofpacket; // alu_out_s1_agent:rf_source_endofpacket -> alu_out_s1_agent_rsp_fifo:in_endofpacket
wire alu_out_s1_agent_rsp_fifo_out_valid; // alu_out_s1_agent_rsp_fifo:out_valid -> alu_out_s1_agent:rf_sink_valid
wire [99:0] alu_out_s1_agent_rsp_fifo_out_data; // alu_out_s1_agent_rsp_fifo:out_data -> alu_out_s1_agent:rf_sink_data
wire alu_out_s1_agent_rsp_fifo_out_ready; // alu_out_s1_agent:rf_sink_ready -> alu_out_s1_agent_rsp_fifo:out_ready
wire alu_out_s1_agent_rsp_fifo_out_startofpacket; // alu_out_s1_agent_rsp_fifo:out_startofpacket -> alu_out_s1_agent:rf_sink_startofpacket
wire alu_out_s1_agent_rsp_fifo_out_endofpacket; // alu_out_s1_agent_rsp_fifo:out_endofpacket -> alu_out_s1_agent:rf_sink_endofpacket
wire alu_out_s1_agent_rdata_fifo_src_valid; // alu_out_s1_agent:rdata_fifo_src_valid -> alu_out_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_out_s1_agent_rdata_fifo_src_data; // alu_out_s1_agent:rdata_fifo_src_data -> alu_out_s1_agent:rdata_fifo_sink_data
wire alu_out_s1_agent_rdata_fifo_src_ready; // alu_out_s1_agent:rdata_fifo_sink_ready -> alu_out_s1_agent:rdata_fifo_src_ready
wire cmd_mux_026_src_valid; // cmd_mux_026:src_valid -> alu_out_s1_agent:cp_valid
wire [98:0] cmd_mux_026_src_data; // cmd_mux_026:src_data -> alu_out_s1_agent:cp_data
wire cmd_mux_026_src_ready; // alu_out_s1_agent:cp_ready -> cmd_mux_026:src_ready
wire [31:0] cmd_mux_026_src_channel; // cmd_mux_026:src_channel -> alu_out_s1_agent:cp_channel
wire cmd_mux_026_src_startofpacket; // cmd_mux_026:src_startofpacket -> alu_out_s1_agent:cp_startofpacket
wire cmd_mux_026_src_endofpacket; // cmd_mux_026:src_endofpacket -> alu_out_s1_agent:cp_endofpacket
wire [31:0] alu_zero_s1_agent_m0_readdata; // alu_zero_s1_translator:uav_readdata -> alu_zero_s1_agent:m0_readdata
wire alu_zero_s1_agent_m0_waitrequest; // alu_zero_s1_translator:uav_waitrequest -> alu_zero_s1_agent:m0_waitrequest
wire alu_zero_s1_agent_m0_debugaccess; // alu_zero_s1_agent:m0_debugaccess -> alu_zero_s1_translator:uav_debugaccess
wire [18:0] alu_zero_s1_agent_m0_address; // alu_zero_s1_agent:m0_address -> alu_zero_s1_translator:uav_address
wire [3:0] alu_zero_s1_agent_m0_byteenable; // alu_zero_s1_agent:m0_byteenable -> alu_zero_s1_translator:uav_byteenable
wire alu_zero_s1_agent_m0_read; // alu_zero_s1_agent:m0_read -> alu_zero_s1_translator:uav_read
wire alu_zero_s1_agent_m0_readdatavalid; // alu_zero_s1_translator:uav_readdatavalid -> alu_zero_s1_agent:m0_readdatavalid
wire alu_zero_s1_agent_m0_lock; // alu_zero_s1_agent:m0_lock -> alu_zero_s1_translator:uav_lock
wire [31:0] alu_zero_s1_agent_m0_writedata; // alu_zero_s1_agent:m0_writedata -> alu_zero_s1_translator:uav_writedata
wire alu_zero_s1_agent_m0_write; // alu_zero_s1_agent:m0_write -> alu_zero_s1_translator:uav_write
wire [2:0] alu_zero_s1_agent_m0_burstcount; // alu_zero_s1_agent:m0_burstcount -> alu_zero_s1_translator:uav_burstcount
wire alu_zero_s1_agent_rf_source_valid; // alu_zero_s1_agent:rf_source_valid -> alu_zero_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_zero_s1_agent_rf_source_data; // alu_zero_s1_agent:rf_source_data -> alu_zero_s1_agent_rsp_fifo:in_data
wire alu_zero_s1_agent_rf_source_ready; // alu_zero_s1_agent_rsp_fifo:in_ready -> alu_zero_s1_agent:rf_source_ready
wire alu_zero_s1_agent_rf_source_startofpacket; // alu_zero_s1_agent:rf_source_startofpacket -> alu_zero_s1_agent_rsp_fifo:in_startofpacket
wire alu_zero_s1_agent_rf_source_endofpacket; // alu_zero_s1_agent:rf_source_endofpacket -> alu_zero_s1_agent_rsp_fifo:in_endofpacket
wire alu_zero_s1_agent_rsp_fifo_out_valid; // alu_zero_s1_agent_rsp_fifo:out_valid -> alu_zero_s1_agent:rf_sink_valid
wire [99:0] alu_zero_s1_agent_rsp_fifo_out_data; // alu_zero_s1_agent_rsp_fifo:out_data -> alu_zero_s1_agent:rf_sink_data
wire alu_zero_s1_agent_rsp_fifo_out_ready; // alu_zero_s1_agent:rf_sink_ready -> alu_zero_s1_agent_rsp_fifo:out_ready
wire alu_zero_s1_agent_rsp_fifo_out_startofpacket; // alu_zero_s1_agent_rsp_fifo:out_startofpacket -> alu_zero_s1_agent:rf_sink_startofpacket
wire alu_zero_s1_agent_rsp_fifo_out_endofpacket; // alu_zero_s1_agent_rsp_fifo:out_endofpacket -> alu_zero_s1_agent:rf_sink_endofpacket
wire alu_zero_s1_agent_rdata_fifo_src_valid; // alu_zero_s1_agent:rdata_fifo_src_valid -> alu_zero_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_zero_s1_agent_rdata_fifo_src_data; // alu_zero_s1_agent:rdata_fifo_src_data -> alu_zero_s1_agent:rdata_fifo_sink_data
wire alu_zero_s1_agent_rdata_fifo_src_ready; // alu_zero_s1_agent:rdata_fifo_sink_ready -> alu_zero_s1_agent:rdata_fifo_src_ready
wire cmd_mux_027_src_valid; // cmd_mux_027:src_valid -> alu_zero_s1_agent:cp_valid
wire [98:0] cmd_mux_027_src_data; // cmd_mux_027:src_data -> alu_zero_s1_agent:cp_data
wire cmd_mux_027_src_ready; // alu_zero_s1_agent:cp_ready -> cmd_mux_027:src_ready
wire [31:0] cmd_mux_027_src_channel; // cmd_mux_027:src_channel -> alu_zero_s1_agent:cp_channel
wire cmd_mux_027_src_startofpacket; // cmd_mux_027:src_startofpacket -> alu_zero_s1_agent:cp_startofpacket
wire cmd_mux_027_src_endofpacket; // cmd_mux_027:src_endofpacket -> alu_zero_s1_agent:cp_endofpacket
wire [31:0] alu_overflow_s1_agent_m0_readdata; // alu_overflow_s1_translator:uav_readdata -> alu_overflow_s1_agent:m0_readdata
wire alu_overflow_s1_agent_m0_waitrequest; // alu_overflow_s1_translator:uav_waitrequest -> alu_overflow_s1_agent:m0_waitrequest
wire alu_overflow_s1_agent_m0_debugaccess; // alu_overflow_s1_agent:m0_debugaccess -> alu_overflow_s1_translator:uav_debugaccess
wire [18:0] alu_overflow_s1_agent_m0_address; // alu_overflow_s1_agent:m0_address -> alu_overflow_s1_translator:uav_address
wire [3:0] alu_overflow_s1_agent_m0_byteenable; // alu_overflow_s1_agent:m0_byteenable -> alu_overflow_s1_translator:uav_byteenable
wire alu_overflow_s1_agent_m0_read; // alu_overflow_s1_agent:m0_read -> alu_overflow_s1_translator:uav_read
wire alu_overflow_s1_agent_m0_readdatavalid; // alu_overflow_s1_translator:uav_readdatavalid -> alu_overflow_s1_agent:m0_readdatavalid
wire alu_overflow_s1_agent_m0_lock; // alu_overflow_s1_agent:m0_lock -> alu_overflow_s1_translator:uav_lock
wire [31:0] alu_overflow_s1_agent_m0_writedata; // alu_overflow_s1_agent:m0_writedata -> alu_overflow_s1_translator:uav_writedata
wire alu_overflow_s1_agent_m0_write; // alu_overflow_s1_agent:m0_write -> alu_overflow_s1_translator:uav_write
wire [2:0] alu_overflow_s1_agent_m0_burstcount; // alu_overflow_s1_agent:m0_burstcount -> alu_overflow_s1_translator:uav_burstcount
wire alu_overflow_s1_agent_rf_source_valid; // alu_overflow_s1_agent:rf_source_valid -> alu_overflow_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_overflow_s1_agent_rf_source_data; // alu_overflow_s1_agent:rf_source_data -> alu_overflow_s1_agent_rsp_fifo:in_data
wire alu_overflow_s1_agent_rf_source_ready; // alu_overflow_s1_agent_rsp_fifo:in_ready -> alu_overflow_s1_agent:rf_source_ready
wire alu_overflow_s1_agent_rf_source_startofpacket; // alu_overflow_s1_agent:rf_source_startofpacket -> alu_overflow_s1_agent_rsp_fifo:in_startofpacket
wire alu_overflow_s1_agent_rf_source_endofpacket; // alu_overflow_s1_agent:rf_source_endofpacket -> alu_overflow_s1_agent_rsp_fifo:in_endofpacket
wire alu_overflow_s1_agent_rsp_fifo_out_valid; // alu_overflow_s1_agent_rsp_fifo:out_valid -> alu_overflow_s1_agent:rf_sink_valid
wire [99:0] alu_overflow_s1_agent_rsp_fifo_out_data; // alu_overflow_s1_agent_rsp_fifo:out_data -> alu_overflow_s1_agent:rf_sink_data
wire alu_overflow_s1_agent_rsp_fifo_out_ready; // alu_overflow_s1_agent:rf_sink_ready -> alu_overflow_s1_agent_rsp_fifo:out_ready
wire alu_overflow_s1_agent_rsp_fifo_out_startofpacket; // alu_overflow_s1_agent_rsp_fifo:out_startofpacket -> alu_overflow_s1_agent:rf_sink_startofpacket
wire alu_overflow_s1_agent_rsp_fifo_out_endofpacket; // alu_overflow_s1_agent_rsp_fifo:out_endofpacket -> alu_overflow_s1_agent:rf_sink_endofpacket
wire alu_overflow_s1_agent_rdata_fifo_src_valid; // alu_overflow_s1_agent:rdata_fifo_src_valid -> alu_overflow_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_overflow_s1_agent_rdata_fifo_src_data; // alu_overflow_s1_agent:rdata_fifo_src_data -> alu_overflow_s1_agent:rdata_fifo_sink_data
wire alu_overflow_s1_agent_rdata_fifo_src_ready; // alu_overflow_s1_agent:rdata_fifo_sink_ready -> alu_overflow_s1_agent:rdata_fifo_src_ready
wire cmd_mux_028_src_valid; // cmd_mux_028:src_valid -> alu_overflow_s1_agent:cp_valid
wire [98:0] cmd_mux_028_src_data; // cmd_mux_028:src_data -> alu_overflow_s1_agent:cp_data
wire cmd_mux_028_src_ready; // alu_overflow_s1_agent:cp_ready -> cmd_mux_028:src_ready
wire [31:0] cmd_mux_028_src_channel; // cmd_mux_028:src_channel -> alu_overflow_s1_agent:cp_channel
wire cmd_mux_028_src_startofpacket; // cmd_mux_028:src_startofpacket -> alu_overflow_s1_agent:cp_startofpacket
wire cmd_mux_028_src_endofpacket; // cmd_mux_028:src_endofpacket -> alu_overflow_s1_agent:cp_endofpacket
wire [31:0] alu_carry_out_s1_agent_m0_readdata; // alu_carry_out_s1_translator:uav_readdata -> alu_carry_out_s1_agent:m0_readdata
wire alu_carry_out_s1_agent_m0_waitrequest; // alu_carry_out_s1_translator:uav_waitrequest -> alu_carry_out_s1_agent:m0_waitrequest
wire alu_carry_out_s1_agent_m0_debugaccess; // alu_carry_out_s1_agent:m0_debugaccess -> alu_carry_out_s1_translator:uav_debugaccess
wire [18:0] alu_carry_out_s1_agent_m0_address; // alu_carry_out_s1_agent:m0_address -> alu_carry_out_s1_translator:uav_address
wire [3:0] alu_carry_out_s1_agent_m0_byteenable; // alu_carry_out_s1_agent:m0_byteenable -> alu_carry_out_s1_translator:uav_byteenable
wire alu_carry_out_s1_agent_m0_read; // alu_carry_out_s1_agent:m0_read -> alu_carry_out_s1_translator:uav_read
wire alu_carry_out_s1_agent_m0_readdatavalid; // alu_carry_out_s1_translator:uav_readdatavalid -> alu_carry_out_s1_agent:m0_readdatavalid
wire alu_carry_out_s1_agent_m0_lock; // alu_carry_out_s1_agent:m0_lock -> alu_carry_out_s1_translator:uav_lock
wire [31:0] alu_carry_out_s1_agent_m0_writedata; // alu_carry_out_s1_agent:m0_writedata -> alu_carry_out_s1_translator:uav_writedata
wire alu_carry_out_s1_agent_m0_write; // alu_carry_out_s1_agent:m0_write -> alu_carry_out_s1_translator:uav_write
wire [2:0] alu_carry_out_s1_agent_m0_burstcount; // alu_carry_out_s1_agent:m0_burstcount -> alu_carry_out_s1_translator:uav_burstcount
wire alu_carry_out_s1_agent_rf_source_valid; // alu_carry_out_s1_agent:rf_source_valid -> alu_carry_out_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_carry_out_s1_agent_rf_source_data; // alu_carry_out_s1_agent:rf_source_data -> alu_carry_out_s1_agent_rsp_fifo:in_data
wire alu_carry_out_s1_agent_rf_source_ready; // alu_carry_out_s1_agent_rsp_fifo:in_ready -> alu_carry_out_s1_agent:rf_source_ready
wire alu_carry_out_s1_agent_rf_source_startofpacket; // alu_carry_out_s1_agent:rf_source_startofpacket -> alu_carry_out_s1_agent_rsp_fifo:in_startofpacket
wire alu_carry_out_s1_agent_rf_source_endofpacket; // alu_carry_out_s1_agent:rf_source_endofpacket -> alu_carry_out_s1_agent_rsp_fifo:in_endofpacket
wire alu_carry_out_s1_agent_rsp_fifo_out_valid; // alu_carry_out_s1_agent_rsp_fifo:out_valid -> alu_carry_out_s1_agent:rf_sink_valid
wire [99:0] alu_carry_out_s1_agent_rsp_fifo_out_data; // alu_carry_out_s1_agent_rsp_fifo:out_data -> alu_carry_out_s1_agent:rf_sink_data
wire alu_carry_out_s1_agent_rsp_fifo_out_ready; // alu_carry_out_s1_agent:rf_sink_ready -> alu_carry_out_s1_agent_rsp_fifo:out_ready
wire alu_carry_out_s1_agent_rsp_fifo_out_startofpacket; // alu_carry_out_s1_agent_rsp_fifo:out_startofpacket -> alu_carry_out_s1_agent:rf_sink_startofpacket
wire alu_carry_out_s1_agent_rsp_fifo_out_endofpacket; // alu_carry_out_s1_agent_rsp_fifo:out_endofpacket -> alu_carry_out_s1_agent:rf_sink_endofpacket
wire alu_carry_out_s1_agent_rdata_fifo_src_valid; // alu_carry_out_s1_agent:rdata_fifo_src_valid -> alu_carry_out_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_carry_out_s1_agent_rdata_fifo_src_data; // alu_carry_out_s1_agent:rdata_fifo_src_data -> alu_carry_out_s1_agent:rdata_fifo_sink_data
wire alu_carry_out_s1_agent_rdata_fifo_src_ready; // alu_carry_out_s1_agent:rdata_fifo_sink_ready -> alu_carry_out_s1_agent:rdata_fifo_src_ready
wire cmd_mux_029_src_valid; // cmd_mux_029:src_valid -> alu_carry_out_s1_agent:cp_valid
wire [98:0] cmd_mux_029_src_data; // cmd_mux_029:src_data -> alu_carry_out_s1_agent:cp_data
wire cmd_mux_029_src_ready; // alu_carry_out_s1_agent:cp_ready -> cmd_mux_029:src_ready
wire [31:0] cmd_mux_029_src_channel; // cmd_mux_029:src_channel -> alu_carry_out_s1_agent:cp_channel
wire cmd_mux_029_src_startofpacket; // cmd_mux_029:src_startofpacket -> alu_carry_out_s1_agent:cp_startofpacket
wire cmd_mux_029_src_endofpacket; // cmd_mux_029:src_endofpacket -> alu_carry_out_s1_agent:cp_endofpacket
wire [31:0] alu_negative_s1_agent_m0_readdata; // alu_negative_s1_translator:uav_readdata -> alu_negative_s1_agent:m0_readdata
wire alu_negative_s1_agent_m0_waitrequest; // alu_negative_s1_translator:uav_waitrequest -> alu_negative_s1_agent:m0_waitrequest
wire alu_negative_s1_agent_m0_debugaccess; // alu_negative_s1_agent:m0_debugaccess -> alu_negative_s1_translator:uav_debugaccess
wire [18:0] alu_negative_s1_agent_m0_address; // alu_negative_s1_agent:m0_address -> alu_negative_s1_translator:uav_address
wire [3:0] alu_negative_s1_agent_m0_byteenable; // alu_negative_s1_agent:m0_byteenable -> alu_negative_s1_translator:uav_byteenable
wire alu_negative_s1_agent_m0_read; // alu_negative_s1_agent:m0_read -> alu_negative_s1_translator:uav_read
wire alu_negative_s1_agent_m0_readdatavalid; // alu_negative_s1_translator:uav_readdatavalid -> alu_negative_s1_agent:m0_readdatavalid
wire alu_negative_s1_agent_m0_lock; // alu_negative_s1_agent:m0_lock -> alu_negative_s1_translator:uav_lock
wire [31:0] alu_negative_s1_agent_m0_writedata; // alu_negative_s1_agent:m0_writedata -> alu_negative_s1_translator:uav_writedata
wire alu_negative_s1_agent_m0_write; // alu_negative_s1_agent:m0_write -> alu_negative_s1_translator:uav_write
wire [2:0] alu_negative_s1_agent_m0_burstcount; // alu_negative_s1_agent:m0_burstcount -> alu_negative_s1_translator:uav_burstcount
wire alu_negative_s1_agent_rf_source_valid; // alu_negative_s1_agent:rf_source_valid -> alu_negative_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_negative_s1_agent_rf_source_data; // alu_negative_s1_agent:rf_source_data -> alu_negative_s1_agent_rsp_fifo:in_data
wire alu_negative_s1_agent_rf_source_ready; // alu_negative_s1_agent_rsp_fifo:in_ready -> alu_negative_s1_agent:rf_source_ready
wire alu_negative_s1_agent_rf_source_startofpacket; // alu_negative_s1_agent:rf_source_startofpacket -> alu_negative_s1_agent_rsp_fifo:in_startofpacket
wire alu_negative_s1_agent_rf_source_endofpacket; // alu_negative_s1_agent:rf_source_endofpacket -> alu_negative_s1_agent_rsp_fifo:in_endofpacket
wire alu_negative_s1_agent_rsp_fifo_out_valid; // alu_negative_s1_agent_rsp_fifo:out_valid -> alu_negative_s1_agent:rf_sink_valid
wire [99:0] alu_negative_s1_agent_rsp_fifo_out_data; // alu_negative_s1_agent_rsp_fifo:out_data -> alu_negative_s1_agent:rf_sink_data
wire alu_negative_s1_agent_rsp_fifo_out_ready; // alu_negative_s1_agent:rf_sink_ready -> alu_negative_s1_agent_rsp_fifo:out_ready
wire alu_negative_s1_agent_rsp_fifo_out_startofpacket; // alu_negative_s1_agent_rsp_fifo:out_startofpacket -> alu_negative_s1_agent:rf_sink_startofpacket
wire alu_negative_s1_agent_rsp_fifo_out_endofpacket; // alu_negative_s1_agent_rsp_fifo:out_endofpacket -> alu_negative_s1_agent:rf_sink_endofpacket
wire alu_negative_s1_agent_rdata_fifo_src_valid; // alu_negative_s1_agent:rdata_fifo_src_valid -> alu_negative_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_negative_s1_agent_rdata_fifo_src_data; // alu_negative_s1_agent:rdata_fifo_src_data -> alu_negative_s1_agent:rdata_fifo_sink_data
wire alu_negative_s1_agent_rdata_fifo_src_ready; // alu_negative_s1_agent:rdata_fifo_sink_ready -> alu_negative_s1_agent:rdata_fifo_src_ready
wire cmd_mux_030_src_valid; // cmd_mux_030:src_valid -> alu_negative_s1_agent:cp_valid
wire [98:0] cmd_mux_030_src_data; // cmd_mux_030:src_data -> alu_negative_s1_agent:cp_data
wire cmd_mux_030_src_ready; // alu_negative_s1_agent:cp_ready -> cmd_mux_030:src_ready
wire [31:0] cmd_mux_030_src_channel; // cmd_mux_030:src_channel -> alu_negative_s1_agent:cp_channel
wire cmd_mux_030_src_startofpacket; // cmd_mux_030:src_startofpacket -> alu_negative_s1_agent:cp_startofpacket
wire cmd_mux_030_src_endofpacket; // cmd_mux_030:src_endofpacket -> alu_negative_s1_agent:cp_endofpacket
wire [31:0] keys_s1_agent_m0_readdata; // keys_s1_translator:uav_readdata -> keys_s1_agent:m0_readdata
wire keys_s1_agent_m0_waitrequest; // keys_s1_translator:uav_waitrequest -> keys_s1_agent:m0_waitrequest
wire keys_s1_agent_m0_debugaccess; // keys_s1_agent:m0_debugaccess -> keys_s1_translator:uav_debugaccess
wire [18:0] keys_s1_agent_m0_address; // keys_s1_agent:m0_address -> keys_s1_translator:uav_address
wire [3:0] keys_s1_agent_m0_byteenable; // keys_s1_agent:m0_byteenable -> keys_s1_translator:uav_byteenable
wire keys_s1_agent_m0_read; // keys_s1_agent:m0_read -> keys_s1_translator:uav_read
wire keys_s1_agent_m0_readdatavalid; // keys_s1_translator:uav_readdatavalid -> keys_s1_agent:m0_readdatavalid
wire keys_s1_agent_m0_lock; // keys_s1_agent:m0_lock -> keys_s1_translator:uav_lock
wire [31:0] keys_s1_agent_m0_writedata; // keys_s1_agent:m0_writedata -> keys_s1_translator:uav_writedata
wire keys_s1_agent_m0_write; // keys_s1_agent:m0_write -> keys_s1_translator:uav_write
wire [2:0] keys_s1_agent_m0_burstcount; // keys_s1_agent:m0_burstcount -> keys_s1_translator:uav_burstcount
wire keys_s1_agent_rf_source_valid; // keys_s1_agent:rf_source_valid -> keys_s1_agent_rsp_fifo:in_valid
wire [99:0] keys_s1_agent_rf_source_data; // keys_s1_agent:rf_source_data -> keys_s1_agent_rsp_fifo:in_data
wire keys_s1_agent_rf_source_ready; // keys_s1_agent_rsp_fifo:in_ready -> keys_s1_agent:rf_source_ready
wire keys_s1_agent_rf_source_startofpacket; // keys_s1_agent:rf_source_startofpacket -> keys_s1_agent_rsp_fifo:in_startofpacket
wire keys_s1_agent_rf_source_endofpacket; // keys_s1_agent:rf_source_endofpacket -> keys_s1_agent_rsp_fifo:in_endofpacket
wire keys_s1_agent_rsp_fifo_out_valid; // keys_s1_agent_rsp_fifo:out_valid -> keys_s1_agent:rf_sink_valid
wire [99:0] keys_s1_agent_rsp_fifo_out_data; // keys_s1_agent_rsp_fifo:out_data -> keys_s1_agent:rf_sink_data
wire keys_s1_agent_rsp_fifo_out_ready; // keys_s1_agent:rf_sink_ready -> keys_s1_agent_rsp_fifo:out_ready
wire keys_s1_agent_rsp_fifo_out_startofpacket; // keys_s1_agent_rsp_fifo:out_startofpacket -> keys_s1_agent:rf_sink_startofpacket
wire keys_s1_agent_rsp_fifo_out_endofpacket; // keys_s1_agent_rsp_fifo:out_endofpacket -> keys_s1_agent:rf_sink_endofpacket
wire keys_s1_agent_rdata_fifo_src_valid; // keys_s1_agent:rdata_fifo_src_valid -> keys_s1_agent:rdata_fifo_sink_valid
wire [33:0] keys_s1_agent_rdata_fifo_src_data; // keys_s1_agent:rdata_fifo_src_data -> keys_s1_agent:rdata_fifo_sink_data
wire keys_s1_agent_rdata_fifo_src_ready; // keys_s1_agent:rdata_fifo_sink_ready -> keys_s1_agent:rdata_fifo_src_ready
wire cmd_mux_031_src_valid; // cmd_mux_031:src_valid -> keys_s1_agent:cp_valid
wire [98:0] cmd_mux_031_src_data; // cmd_mux_031:src_data -> keys_s1_agent:cp_data
wire cmd_mux_031_src_ready; // keys_s1_agent:cp_ready -> cmd_mux_031:src_ready
wire [31:0] cmd_mux_031_src_channel; // cmd_mux_031:src_channel -> keys_s1_agent:cp_channel
wire cmd_mux_031_src_startofpacket; // cmd_mux_031:src_startofpacket -> keys_s1_agent:cp_startofpacket
wire cmd_mux_031_src_endofpacket; // cmd_mux_031:src_endofpacket -> keys_s1_agent:cp_endofpacket
wire nios2_qsys_0_data_master_agent_cp_valid; // nios2_qsys_0_data_master_agent:cp_valid -> router:sink_valid
wire [98:0] nios2_qsys_0_data_master_agent_cp_data; // nios2_qsys_0_data_master_agent:cp_data -> router:sink_data
wire nios2_qsys_0_data_master_agent_cp_ready; // router:sink_ready -> nios2_qsys_0_data_master_agent:cp_ready
wire nios2_qsys_0_data_master_agent_cp_startofpacket; // nios2_qsys_0_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire nios2_qsys_0_data_master_agent_cp_endofpacket; // nios2_qsys_0_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [98:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [31:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire nios2_qsys_0_instruction_master_agent_cp_valid; // nios2_qsys_0_instruction_master_agent:cp_valid -> router_001:sink_valid
wire [98:0] nios2_qsys_0_instruction_master_agent_cp_data; // nios2_qsys_0_instruction_master_agent:cp_data -> router_001:sink_data
wire nios2_qsys_0_instruction_master_agent_cp_ready; // router_001:sink_ready -> nios2_qsys_0_instruction_master_agent:cp_ready
wire nios2_qsys_0_instruction_master_agent_cp_startofpacket; // nios2_qsys_0_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire nios2_qsys_0_instruction_master_agent_cp_endofpacket; // nios2_qsys_0_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [98:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [31:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rp_valid; // jtag_uart_0_avalon_jtag_slave_agent:rp_valid -> router_002:sink_valid
wire [98:0] jtag_uart_0_avalon_jtag_slave_agent_rp_data; // jtag_uart_0_avalon_jtag_slave_agent:rp_data -> router_002:sink_data
wire jtag_uart_0_avalon_jtag_slave_agent_rp_ready; // router_002:sink_ready -> jtag_uart_0_avalon_jtag_slave_agent:rp_ready
wire jtag_uart_0_avalon_jtag_slave_agent_rp_startofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rp_startofpacket -> router_002:sink_startofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rp_endofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [98:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [31:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire nios2_qsys_0_debug_mem_slave_agent_rp_valid; // nios2_qsys_0_debug_mem_slave_agent:rp_valid -> router_003:sink_valid
wire [98:0] nios2_qsys_0_debug_mem_slave_agent_rp_data; // nios2_qsys_0_debug_mem_slave_agent:rp_data -> router_003:sink_data
wire nios2_qsys_0_debug_mem_slave_agent_rp_ready; // router_003:sink_ready -> nios2_qsys_0_debug_mem_slave_agent:rp_ready
wire nios2_qsys_0_debug_mem_slave_agent_rp_startofpacket; // nios2_qsys_0_debug_mem_slave_agent:rp_startofpacket -> router_003:sink_startofpacket
wire nios2_qsys_0_debug_mem_slave_agent_rp_endofpacket; // nios2_qsys_0_debug_mem_slave_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire [98:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire [31:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire onchip_memory2_0_s1_agent_rp_valid; // onchip_memory2_0_s1_agent:rp_valid -> router_004:sink_valid
wire [98:0] onchip_memory2_0_s1_agent_rp_data; // onchip_memory2_0_s1_agent:rp_data -> router_004:sink_data
wire onchip_memory2_0_s1_agent_rp_ready; // router_004:sink_ready -> onchip_memory2_0_s1_agent:rp_ready
wire onchip_memory2_0_s1_agent_rp_startofpacket; // onchip_memory2_0_s1_agent:rp_startofpacket -> router_004:sink_startofpacket
wire onchip_memory2_0_s1_agent_rp_endofpacket; // onchip_memory2_0_s1_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire [98:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire [31:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire leds_s1_agent_rp_valid; // LEDs_s1_agent:rp_valid -> router_005:sink_valid
wire [98:0] leds_s1_agent_rp_data; // LEDs_s1_agent:rp_data -> router_005:sink_data
wire leds_s1_agent_rp_ready; // router_005:sink_ready -> LEDs_s1_agent:rp_ready
wire leds_s1_agent_rp_startofpacket; // LEDs_s1_agent:rp_startofpacket -> router_005:sink_startofpacket
wire leds_s1_agent_rp_endofpacket; // LEDs_s1_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire [98:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire [31:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire switches_s1_agent_rp_valid; // switches_s1_agent:rp_valid -> router_006:sink_valid
wire [98:0] switches_s1_agent_rp_data; // switches_s1_agent:rp_data -> router_006:sink_data
wire switches_s1_agent_rp_ready; // router_006:sink_ready -> switches_s1_agent:rp_ready
wire switches_s1_agent_rp_startofpacket; // switches_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
wire switches_s1_agent_rp_endofpacket; // switches_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_004:sink_valid
wire [98:0] router_006_src_data; // router_006:src_data -> rsp_demux_004:sink_data
wire router_006_src_ready; // rsp_demux_004:sink_ready -> router_006:src_ready
wire [31:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire sram_data_s1_agent_rp_valid; // sram_data_s1_agent:rp_valid -> router_007:sink_valid
wire [98:0] sram_data_s1_agent_rp_data; // sram_data_s1_agent:rp_data -> router_007:sink_data
wire sram_data_s1_agent_rp_ready; // router_007:sink_ready -> sram_data_s1_agent:rp_ready
wire sram_data_s1_agent_rp_startofpacket; // sram_data_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
wire sram_data_s1_agent_rp_endofpacket; // sram_data_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid
wire [98:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data
wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready
wire [31:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire sram_addr_s1_agent_rp_valid; // sram_addr_s1_agent:rp_valid -> router_008:sink_valid
wire [98:0] sram_addr_s1_agent_rp_data; // sram_addr_s1_agent:rp_data -> router_008:sink_data
wire sram_addr_s1_agent_rp_ready; // router_008:sink_ready -> sram_addr_s1_agent:rp_ready
wire sram_addr_s1_agent_rp_startofpacket; // sram_addr_s1_agent:rp_startofpacket -> router_008:sink_startofpacket
wire sram_addr_s1_agent_rp_endofpacket; // sram_addr_s1_agent:rp_endofpacket -> router_008:sink_endofpacket
wire router_008_src_valid; // router_008:src_valid -> rsp_demux_006:sink_valid
wire [98:0] router_008_src_data; // router_008:src_data -> rsp_demux_006:sink_data
wire router_008_src_ready; // rsp_demux_006:sink_ready -> router_008:src_ready
wire [31:0] router_008_src_channel; // router_008:src_channel -> rsp_demux_006:sink_channel
wire router_008_src_startofpacket; // router_008:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire router_008_src_endofpacket; // router_008:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire sram_read_write_s1_agent_rp_valid; // sram_read_write_s1_agent:rp_valid -> router_009:sink_valid
wire [98:0] sram_read_write_s1_agent_rp_data; // sram_read_write_s1_agent:rp_data -> router_009:sink_data
wire sram_read_write_s1_agent_rp_ready; // router_009:sink_ready -> sram_read_write_s1_agent:rp_ready
wire sram_read_write_s1_agent_rp_startofpacket; // sram_read_write_s1_agent:rp_startofpacket -> router_009:sink_startofpacket
wire sram_read_write_s1_agent_rp_endofpacket; // sram_read_write_s1_agent:rp_endofpacket -> router_009:sink_endofpacket
wire router_009_src_valid; // router_009:src_valid -> rsp_demux_007:sink_valid
wire [98:0] router_009_src_data; // router_009:src_data -> rsp_demux_007:sink_data
wire router_009_src_ready; // rsp_demux_007:sink_ready -> router_009:src_ready
wire [31:0] router_009_src_channel; // router_009:src_channel -> rsp_demux_007:sink_channel
wire router_009_src_startofpacket; // router_009:src_startofpacket -> rsp_demux_007:sink_startofpacket
wire router_009_src_endofpacket; // router_009:src_endofpacket -> rsp_demux_007:sink_endofpacket
wire sram_cs_s1_agent_rp_valid; // sram_cs_s1_agent:rp_valid -> router_010:sink_valid
wire [98:0] sram_cs_s1_agent_rp_data; // sram_cs_s1_agent:rp_data -> router_010:sink_data
wire sram_cs_s1_agent_rp_ready; // router_010:sink_ready -> sram_cs_s1_agent:rp_ready
wire sram_cs_s1_agent_rp_startofpacket; // sram_cs_s1_agent:rp_startofpacket -> router_010:sink_startofpacket
wire sram_cs_s1_agent_rp_endofpacket; // sram_cs_s1_agent:rp_endofpacket -> router_010:sink_endofpacket
wire router_010_src_valid; // router_010:src_valid -> rsp_demux_008:sink_valid
wire [98:0] router_010_src_data; // router_010:src_data -> rsp_demux_008:sink_data
wire router_010_src_ready; // rsp_demux_008:sink_ready -> router_010:src_ready
wire [31:0] router_010_src_channel; // router_010:src_channel -> rsp_demux_008:sink_channel
wire router_010_src_startofpacket; // router_010:src_startofpacket -> rsp_demux_008:sink_startofpacket
wire router_010_src_endofpacket; // router_010:src_endofpacket -> rsp_demux_008:sink_endofpacket
wire sram_oe_s1_agent_rp_valid; // sram_oe_s1_agent:rp_valid -> router_011:sink_valid
wire [98:0] sram_oe_s1_agent_rp_data; // sram_oe_s1_agent:rp_data -> router_011:sink_data
wire sram_oe_s1_agent_rp_ready; // router_011:sink_ready -> sram_oe_s1_agent:rp_ready
wire sram_oe_s1_agent_rp_startofpacket; // sram_oe_s1_agent:rp_startofpacket -> router_011:sink_startofpacket
wire sram_oe_s1_agent_rp_endofpacket; // sram_oe_s1_agent:rp_endofpacket -> router_011:sink_endofpacket
wire router_011_src_valid; // router_011:src_valid -> rsp_demux_009:sink_valid
wire [98:0] router_011_src_data; // router_011:src_data -> rsp_demux_009:sink_data
wire router_011_src_ready; // rsp_demux_009:sink_ready -> router_011:src_ready
wire [31:0] router_011_src_channel; // router_011:src_channel -> rsp_demux_009:sink_channel
wire router_011_src_startofpacket; // router_011:src_startofpacket -> rsp_demux_009:sink_startofpacket
wire router_011_src_endofpacket; // router_011:src_endofpacket -> rsp_demux_009:sink_endofpacket
wire regfile_data_s1_agent_rp_valid; // regfile_data_s1_agent:rp_valid -> router_012:sink_valid
wire [98:0] regfile_data_s1_agent_rp_data; // regfile_data_s1_agent:rp_data -> router_012:sink_data
wire regfile_data_s1_agent_rp_ready; // router_012:sink_ready -> regfile_data_s1_agent:rp_ready
wire regfile_data_s1_agent_rp_startofpacket; // regfile_data_s1_agent:rp_startofpacket -> router_012:sink_startofpacket
wire regfile_data_s1_agent_rp_endofpacket; // regfile_data_s1_agent:rp_endofpacket -> router_012:sink_endofpacket
wire router_012_src_valid; // router_012:src_valid -> rsp_demux_010:sink_valid
wire [98:0] router_012_src_data; // router_012:src_data -> rsp_demux_010:sink_data
wire router_012_src_ready; // rsp_demux_010:sink_ready -> router_012:src_ready
wire [31:0] router_012_src_channel; // router_012:src_channel -> rsp_demux_010:sink_channel
wire router_012_src_startofpacket; // router_012:src_startofpacket -> rsp_demux_010:sink_startofpacket
wire router_012_src_endofpacket; // router_012:src_endofpacket -> rsp_demux_010:sink_endofpacket
wire regfile_reg1_s1_agent_rp_valid; // regfile_reg1_s1_agent:rp_valid -> router_013:sink_valid
wire [98:0] regfile_reg1_s1_agent_rp_data; // regfile_reg1_s1_agent:rp_data -> router_013:sink_data
wire regfile_reg1_s1_agent_rp_ready; // router_013:sink_ready -> regfile_reg1_s1_agent:rp_ready
wire regfile_reg1_s1_agent_rp_startofpacket; // regfile_reg1_s1_agent:rp_startofpacket -> router_013:sink_startofpacket
wire regfile_reg1_s1_agent_rp_endofpacket; // regfile_reg1_s1_agent:rp_endofpacket -> router_013:sink_endofpacket
wire router_013_src_valid; // router_013:src_valid -> rsp_demux_011:sink_valid
wire [98:0] router_013_src_data; // router_013:src_data -> rsp_demux_011:sink_data
wire router_013_src_ready; // rsp_demux_011:sink_ready -> router_013:src_ready
wire [31:0] router_013_src_channel; // router_013:src_channel -> rsp_demux_011:sink_channel
wire router_013_src_startofpacket; // router_013:src_startofpacket -> rsp_demux_011:sink_startofpacket
wire router_013_src_endofpacket; // router_013:src_endofpacket -> rsp_demux_011:sink_endofpacket
wire regfile_reg2_s1_agent_rp_valid; // regfile_reg2_s1_agent:rp_valid -> router_014:sink_valid
wire [98:0] regfile_reg2_s1_agent_rp_data; // regfile_reg2_s1_agent:rp_data -> router_014:sink_data
wire regfile_reg2_s1_agent_rp_ready; // router_014:sink_ready -> regfile_reg2_s1_agent:rp_ready
wire regfile_reg2_s1_agent_rp_startofpacket; // regfile_reg2_s1_agent:rp_startofpacket -> router_014:sink_startofpacket
wire regfile_reg2_s1_agent_rp_endofpacket; // regfile_reg2_s1_agent:rp_endofpacket -> router_014:sink_endofpacket
wire router_014_src_valid; // router_014:src_valid -> rsp_demux_012:sink_valid
wire [98:0] router_014_src_data; // router_014:src_data -> rsp_demux_012:sink_data
wire router_014_src_ready; // rsp_demux_012:sink_ready -> router_014:src_ready
wire [31:0] router_014_src_channel; // router_014:src_channel -> rsp_demux_012:sink_channel
wire router_014_src_startofpacket; // router_014:src_startofpacket -> rsp_demux_012:sink_startofpacket
wire router_014_src_endofpacket; // router_014:src_endofpacket -> rsp_demux_012:sink_endofpacket
wire regfile_r1sel_s1_agent_rp_valid; // regfile_r1sel_s1_agent:rp_valid -> router_015:sink_valid
wire [98:0] regfile_r1sel_s1_agent_rp_data; // regfile_r1sel_s1_agent:rp_data -> router_015:sink_data
wire regfile_r1sel_s1_agent_rp_ready; // router_015:sink_ready -> regfile_r1sel_s1_agent:rp_ready
wire regfile_r1sel_s1_agent_rp_startofpacket; // regfile_r1sel_s1_agent:rp_startofpacket -> router_015:sink_startofpacket
wire regfile_r1sel_s1_agent_rp_endofpacket; // regfile_r1sel_s1_agent:rp_endofpacket -> router_015:sink_endofpacket
wire router_015_src_valid; // router_015:src_valid -> rsp_demux_013:sink_valid
wire [98:0] router_015_src_data; // router_015:src_data -> rsp_demux_013:sink_data
wire router_015_src_ready; // rsp_demux_013:sink_ready -> router_015:src_ready
wire [31:0] router_015_src_channel; // router_015:src_channel -> rsp_demux_013:sink_channel
wire router_015_src_startofpacket; // router_015:src_startofpacket -> rsp_demux_013:sink_startofpacket
wire router_015_src_endofpacket; // router_015:src_endofpacket -> rsp_demux_013:sink_endofpacket
wire regfile_r2sel_s1_agent_rp_valid; // regfile_r2sel_s1_agent:rp_valid -> router_016:sink_valid
wire [98:0] regfile_r2sel_s1_agent_rp_data; // regfile_r2sel_s1_agent:rp_data -> router_016:sink_data
wire regfile_r2sel_s1_agent_rp_ready; // router_016:sink_ready -> regfile_r2sel_s1_agent:rp_ready
wire regfile_r2sel_s1_agent_rp_startofpacket; // regfile_r2sel_s1_agent:rp_startofpacket -> router_016:sink_startofpacket
wire regfile_r2sel_s1_agent_rp_endofpacket; // regfile_r2sel_s1_agent:rp_endofpacket -> router_016:sink_endofpacket
wire router_016_src_valid; // router_016:src_valid -> rsp_demux_014:sink_valid
wire [98:0] router_016_src_data; // router_016:src_data -> rsp_demux_014:sink_data
wire router_016_src_ready; // rsp_demux_014:sink_ready -> router_016:src_ready
wire [31:0] router_016_src_channel; // router_016:src_channel -> rsp_demux_014:sink_channel
wire router_016_src_startofpacket; // router_016:src_startofpacket -> rsp_demux_014:sink_startofpacket
wire router_016_src_endofpacket; // router_016:src_endofpacket -> rsp_demux_014:sink_endofpacket
wire regfile_wsel_s1_agent_rp_valid; // regfile_wsel_s1_agent:rp_valid -> router_017:sink_valid
wire [98:0] regfile_wsel_s1_agent_rp_data; // regfile_wsel_s1_agent:rp_data -> router_017:sink_data
wire regfile_wsel_s1_agent_rp_ready; // router_017:sink_ready -> regfile_wsel_s1_agent:rp_ready
wire regfile_wsel_s1_agent_rp_startofpacket; // regfile_wsel_s1_agent:rp_startofpacket -> router_017:sink_startofpacket
wire regfile_wsel_s1_agent_rp_endofpacket; // regfile_wsel_s1_agent:rp_endofpacket -> router_017:sink_endofpacket
wire router_017_src_valid; // router_017:src_valid -> rsp_demux_015:sink_valid
wire [98:0] router_017_src_data; // router_017:src_data -> rsp_demux_015:sink_data
wire router_017_src_ready; // rsp_demux_015:sink_ready -> router_017:src_ready
wire [31:0] router_017_src_channel; // router_017:src_channel -> rsp_demux_015:sink_channel
wire router_017_src_startofpacket; // router_017:src_startofpacket -> rsp_demux_015:sink_startofpacket
wire router_017_src_endofpacket; // router_017:src_endofpacket -> rsp_demux_015:sink_endofpacket
wire regfile_we_s1_agent_rp_valid; // regfile_we_s1_agent:rp_valid -> router_018:sink_valid
wire [98:0] regfile_we_s1_agent_rp_data; // regfile_we_s1_agent:rp_data -> router_018:sink_data
wire regfile_we_s1_agent_rp_ready; // router_018:sink_ready -> regfile_we_s1_agent:rp_ready
wire regfile_we_s1_agent_rp_startofpacket; // regfile_we_s1_agent:rp_startofpacket -> router_018:sink_startofpacket
wire regfile_we_s1_agent_rp_endofpacket; // regfile_we_s1_agent:rp_endofpacket -> router_018:sink_endofpacket
wire router_018_src_valid; // router_018:src_valid -> rsp_demux_016:sink_valid
wire [98:0] router_018_src_data; // router_018:src_data -> rsp_demux_016:sink_data
wire router_018_src_ready; // rsp_demux_016:sink_ready -> router_018:src_ready
wire [31:0] router_018_src_channel; // router_018:src_channel -> rsp_demux_016:sink_channel
wire router_018_src_startofpacket; // router_018:src_startofpacket -> rsp_demux_016:sink_startofpacket
wire router_018_src_endofpacket; // router_018:src_endofpacket -> rsp_demux_016:sink_endofpacket
wire hex_0_s1_agent_rp_valid; // hex_0_s1_agent:rp_valid -> router_019:sink_valid
wire [98:0] hex_0_s1_agent_rp_data; // hex_0_s1_agent:rp_data -> router_019:sink_data
wire hex_0_s1_agent_rp_ready; // router_019:sink_ready -> hex_0_s1_agent:rp_ready
wire hex_0_s1_agent_rp_startofpacket; // hex_0_s1_agent:rp_startofpacket -> router_019:sink_startofpacket
wire hex_0_s1_agent_rp_endofpacket; // hex_0_s1_agent:rp_endofpacket -> router_019:sink_endofpacket
wire router_019_src_valid; // router_019:src_valid -> rsp_demux_017:sink_valid
wire [98:0] router_019_src_data; // router_019:src_data -> rsp_demux_017:sink_data
wire router_019_src_ready; // rsp_demux_017:sink_ready -> router_019:src_ready
wire [31:0] router_019_src_channel; // router_019:src_channel -> rsp_demux_017:sink_channel
wire router_019_src_startofpacket; // router_019:src_startofpacket -> rsp_demux_017:sink_startofpacket
wire router_019_src_endofpacket; // router_019:src_endofpacket -> rsp_demux_017:sink_endofpacket
wire hex_1_s1_agent_rp_valid; // hex_1_s1_agent:rp_valid -> router_020:sink_valid
wire [98:0] hex_1_s1_agent_rp_data; // hex_1_s1_agent:rp_data -> router_020:sink_data
wire hex_1_s1_agent_rp_ready; // router_020:sink_ready -> hex_1_s1_agent:rp_ready
wire hex_1_s1_agent_rp_startofpacket; // hex_1_s1_agent:rp_startofpacket -> router_020:sink_startofpacket
wire hex_1_s1_agent_rp_endofpacket; // hex_1_s1_agent:rp_endofpacket -> router_020:sink_endofpacket
wire router_020_src_valid; // router_020:src_valid -> rsp_demux_018:sink_valid
wire [98:0] router_020_src_data; // router_020:src_data -> rsp_demux_018:sink_data
wire router_020_src_ready; // rsp_demux_018:sink_ready -> router_020:src_ready
wire [31:0] router_020_src_channel; // router_020:src_channel -> rsp_demux_018:sink_channel
wire router_020_src_startofpacket; // router_020:src_startofpacket -> rsp_demux_018:sink_startofpacket
wire router_020_src_endofpacket; // router_020:src_endofpacket -> rsp_demux_018:sink_endofpacket
wire hex_2_s1_agent_rp_valid; // hex_2_s1_agent:rp_valid -> router_021:sink_valid
wire [98:0] hex_2_s1_agent_rp_data; // hex_2_s1_agent:rp_data -> router_021:sink_data
wire hex_2_s1_agent_rp_ready; // router_021:sink_ready -> hex_2_s1_agent:rp_ready
wire hex_2_s1_agent_rp_startofpacket; // hex_2_s1_agent:rp_startofpacket -> router_021:sink_startofpacket
wire hex_2_s1_agent_rp_endofpacket; // hex_2_s1_agent:rp_endofpacket -> router_021:sink_endofpacket
wire router_021_src_valid; // router_021:src_valid -> rsp_demux_019:sink_valid
wire [98:0] router_021_src_data; // router_021:src_data -> rsp_demux_019:sink_data
wire router_021_src_ready; // rsp_demux_019:sink_ready -> router_021:src_ready
wire [31:0] router_021_src_channel; // router_021:src_channel -> rsp_demux_019:sink_channel
wire router_021_src_startofpacket; // router_021:src_startofpacket -> rsp_demux_019:sink_startofpacket
wire router_021_src_endofpacket; // router_021:src_endofpacket -> rsp_demux_019:sink_endofpacket
wire hex_3_s1_agent_rp_valid; // hex_3_s1_agent:rp_valid -> router_022:sink_valid
wire [98:0] hex_3_s1_agent_rp_data; // hex_3_s1_agent:rp_data -> router_022:sink_data
wire hex_3_s1_agent_rp_ready; // router_022:sink_ready -> hex_3_s1_agent:rp_ready
wire hex_3_s1_agent_rp_startofpacket; // hex_3_s1_agent:rp_startofpacket -> router_022:sink_startofpacket
wire hex_3_s1_agent_rp_endofpacket; // hex_3_s1_agent:rp_endofpacket -> router_022:sink_endofpacket
wire router_022_src_valid; // router_022:src_valid -> rsp_demux_020:sink_valid
wire [98:0] router_022_src_data; // router_022:src_data -> rsp_demux_020:sink_data
wire router_022_src_ready; // rsp_demux_020:sink_ready -> router_022:src_ready
wire [31:0] router_022_src_channel; // router_022:src_channel -> rsp_demux_020:sink_channel
wire router_022_src_startofpacket; // router_022:src_startofpacket -> rsp_demux_020:sink_startofpacket
wire router_022_src_endofpacket; // router_022:src_endofpacket -> rsp_demux_020:sink_endofpacket
wire hex_4_s1_agent_rp_valid; // hex_4_s1_agent:rp_valid -> router_023:sink_valid
wire [98:0] hex_4_s1_agent_rp_data; // hex_4_s1_agent:rp_data -> router_023:sink_data
wire hex_4_s1_agent_rp_ready; // router_023:sink_ready -> hex_4_s1_agent:rp_ready
wire hex_4_s1_agent_rp_startofpacket; // hex_4_s1_agent:rp_startofpacket -> router_023:sink_startofpacket
wire hex_4_s1_agent_rp_endofpacket; // hex_4_s1_agent:rp_endofpacket -> router_023:sink_endofpacket
wire router_023_src_valid; // router_023:src_valid -> rsp_demux_021:sink_valid
wire [98:0] router_023_src_data; // router_023:src_data -> rsp_demux_021:sink_data
wire router_023_src_ready; // rsp_demux_021:sink_ready -> router_023:src_ready
wire [31:0] router_023_src_channel; // router_023:src_channel -> rsp_demux_021:sink_channel
wire router_023_src_startofpacket; // router_023:src_startofpacket -> rsp_demux_021:sink_startofpacket
wire router_023_src_endofpacket; // router_023:src_endofpacket -> rsp_demux_021:sink_endofpacket
wire hex_5_s1_agent_rp_valid; // hex_5_s1_agent:rp_valid -> router_024:sink_valid
wire [98:0] hex_5_s1_agent_rp_data; // hex_5_s1_agent:rp_data -> router_024:sink_data
wire hex_5_s1_agent_rp_ready; // router_024:sink_ready -> hex_5_s1_agent:rp_ready
wire hex_5_s1_agent_rp_startofpacket; // hex_5_s1_agent:rp_startofpacket -> router_024:sink_startofpacket
wire hex_5_s1_agent_rp_endofpacket; // hex_5_s1_agent:rp_endofpacket -> router_024:sink_endofpacket
wire router_024_src_valid; // router_024:src_valid -> rsp_demux_022:sink_valid
wire [98:0] router_024_src_data; // router_024:src_data -> rsp_demux_022:sink_data
wire router_024_src_ready; // rsp_demux_022:sink_ready -> router_024:src_ready
wire [31:0] router_024_src_channel; // router_024:src_channel -> rsp_demux_022:sink_channel
wire router_024_src_startofpacket; // router_024:src_startofpacket -> rsp_demux_022:sink_startofpacket
wire router_024_src_endofpacket; // router_024:src_endofpacket -> rsp_demux_022:sink_endofpacket
wire alu_a_s1_agent_rp_valid; // alu_a_s1_agent:rp_valid -> router_025:sink_valid
wire [98:0] alu_a_s1_agent_rp_data; // alu_a_s1_agent:rp_data -> router_025:sink_data
wire alu_a_s1_agent_rp_ready; // router_025:sink_ready -> alu_a_s1_agent:rp_ready
wire alu_a_s1_agent_rp_startofpacket; // alu_a_s1_agent:rp_startofpacket -> router_025:sink_startofpacket
wire alu_a_s1_agent_rp_endofpacket; // alu_a_s1_agent:rp_endofpacket -> router_025:sink_endofpacket
wire router_025_src_valid; // router_025:src_valid -> rsp_demux_023:sink_valid
wire [98:0] router_025_src_data; // router_025:src_data -> rsp_demux_023:sink_data
wire router_025_src_ready; // rsp_demux_023:sink_ready -> router_025:src_ready
wire [31:0] router_025_src_channel; // router_025:src_channel -> rsp_demux_023:sink_channel
wire router_025_src_startofpacket; // router_025:src_startofpacket -> rsp_demux_023:sink_startofpacket
wire router_025_src_endofpacket; // router_025:src_endofpacket -> rsp_demux_023:sink_endofpacket
wire alu_b_s1_agent_rp_valid; // alu_b_s1_agent:rp_valid -> router_026:sink_valid
wire [98:0] alu_b_s1_agent_rp_data; // alu_b_s1_agent:rp_data -> router_026:sink_data
wire alu_b_s1_agent_rp_ready; // router_026:sink_ready -> alu_b_s1_agent:rp_ready
wire alu_b_s1_agent_rp_startofpacket; // alu_b_s1_agent:rp_startofpacket -> router_026:sink_startofpacket
wire alu_b_s1_agent_rp_endofpacket; // alu_b_s1_agent:rp_endofpacket -> router_026:sink_endofpacket
wire router_026_src_valid; // router_026:src_valid -> rsp_demux_024:sink_valid
wire [98:0] router_026_src_data; // router_026:src_data -> rsp_demux_024:sink_data
wire router_026_src_ready; // rsp_demux_024:sink_ready -> router_026:src_ready
wire [31:0] router_026_src_channel; // router_026:src_channel -> rsp_demux_024:sink_channel
wire router_026_src_startofpacket; // router_026:src_startofpacket -> rsp_demux_024:sink_startofpacket
wire router_026_src_endofpacket; // router_026:src_endofpacket -> rsp_demux_024:sink_endofpacket
wire alu_control_s1_agent_rp_valid; // alu_control_s1_agent:rp_valid -> router_027:sink_valid
wire [98:0] alu_control_s1_agent_rp_data; // alu_control_s1_agent:rp_data -> router_027:sink_data
wire alu_control_s1_agent_rp_ready; // router_027:sink_ready -> alu_control_s1_agent:rp_ready
wire alu_control_s1_agent_rp_startofpacket; // alu_control_s1_agent:rp_startofpacket -> router_027:sink_startofpacket
wire alu_control_s1_agent_rp_endofpacket; // alu_control_s1_agent:rp_endofpacket -> router_027:sink_endofpacket
wire router_027_src_valid; // router_027:src_valid -> rsp_demux_025:sink_valid
wire [98:0] router_027_src_data; // router_027:src_data -> rsp_demux_025:sink_data
wire router_027_src_ready; // rsp_demux_025:sink_ready -> router_027:src_ready
wire [31:0] router_027_src_channel; // router_027:src_channel -> rsp_demux_025:sink_channel
wire router_027_src_startofpacket; // router_027:src_startofpacket -> rsp_demux_025:sink_startofpacket
wire router_027_src_endofpacket; // router_027:src_endofpacket -> rsp_demux_025:sink_endofpacket
wire alu_out_s1_agent_rp_valid; // alu_out_s1_agent:rp_valid -> router_028:sink_valid
wire [98:0] alu_out_s1_agent_rp_data; // alu_out_s1_agent:rp_data -> router_028:sink_data
wire alu_out_s1_agent_rp_ready; // router_028:sink_ready -> alu_out_s1_agent:rp_ready
wire alu_out_s1_agent_rp_startofpacket; // alu_out_s1_agent:rp_startofpacket -> router_028:sink_startofpacket
wire alu_out_s1_agent_rp_endofpacket; // alu_out_s1_agent:rp_endofpacket -> router_028:sink_endofpacket
wire router_028_src_valid; // router_028:src_valid -> rsp_demux_026:sink_valid
wire [98:0] router_028_src_data; // router_028:src_data -> rsp_demux_026:sink_data
wire router_028_src_ready; // rsp_demux_026:sink_ready -> router_028:src_ready
wire [31:0] router_028_src_channel; // router_028:src_channel -> rsp_demux_026:sink_channel
wire router_028_src_startofpacket; // router_028:src_startofpacket -> rsp_demux_026:sink_startofpacket
wire router_028_src_endofpacket; // router_028:src_endofpacket -> rsp_demux_026:sink_endofpacket
wire alu_zero_s1_agent_rp_valid; // alu_zero_s1_agent:rp_valid -> router_029:sink_valid
wire [98:0] alu_zero_s1_agent_rp_data; // alu_zero_s1_agent:rp_data -> router_029:sink_data
wire alu_zero_s1_agent_rp_ready; // router_029:sink_ready -> alu_zero_s1_agent:rp_ready
wire alu_zero_s1_agent_rp_startofpacket; // alu_zero_s1_agent:rp_startofpacket -> router_029:sink_startofpacket
wire alu_zero_s1_agent_rp_endofpacket; // alu_zero_s1_agent:rp_endofpacket -> router_029:sink_endofpacket
wire router_029_src_valid; // router_029:src_valid -> rsp_demux_027:sink_valid
wire [98:0] router_029_src_data; // router_029:src_data -> rsp_demux_027:sink_data
wire router_029_src_ready; // rsp_demux_027:sink_ready -> router_029:src_ready
wire [31:0] router_029_src_channel; // router_029:src_channel -> rsp_demux_027:sink_channel
wire router_029_src_startofpacket; // router_029:src_startofpacket -> rsp_demux_027:sink_startofpacket
wire router_029_src_endofpacket; // router_029:src_endofpacket -> rsp_demux_027:sink_endofpacket
wire alu_overflow_s1_agent_rp_valid; // alu_overflow_s1_agent:rp_valid -> router_030:sink_valid
wire [98:0] alu_overflow_s1_agent_rp_data; // alu_overflow_s1_agent:rp_data -> router_030:sink_data
wire alu_overflow_s1_agent_rp_ready; // router_030:sink_ready -> alu_overflow_s1_agent:rp_ready
wire alu_overflow_s1_agent_rp_startofpacket; // alu_overflow_s1_agent:rp_startofpacket -> router_030:sink_startofpacket
wire alu_overflow_s1_agent_rp_endofpacket; // alu_overflow_s1_agent:rp_endofpacket -> router_030:sink_endofpacket
wire router_030_src_valid; // router_030:src_valid -> rsp_demux_028:sink_valid
wire [98:0] router_030_src_data; // router_030:src_data -> rsp_demux_028:sink_data
wire router_030_src_ready; // rsp_demux_028:sink_ready -> router_030:src_ready
wire [31:0] router_030_src_channel; // router_030:src_channel -> rsp_demux_028:sink_channel
wire router_030_src_startofpacket; // router_030:src_startofpacket -> rsp_demux_028:sink_startofpacket
wire router_030_src_endofpacket; // router_030:src_endofpacket -> rsp_demux_028:sink_endofpacket
wire alu_carry_out_s1_agent_rp_valid; // alu_carry_out_s1_agent:rp_valid -> router_031:sink_valid
wire [98:0] alu_carry_out_s1_agent_rp_data; // alu_carry_out_s1_agent:rp_data -> router_031:sink_data
wire alu_carry_out_s1_agent_rp_ready; // router_031:sink_ready -> alu_carry_out_s1_agent:rp_ready
wire alu_carry_out_s1_agent_rp_startofpacket; // alu_carry_out_s1_agent:rp_startofpacket -> router_031:sink_startofpacket
wire alu_carry_out_s1_agent_rp_endofpacket; // alu_carry_out_s1_agent:rp_endofpacket -> router_031:sink_endofpacket
wire router_031_src_valid; // router_031:src_valid -> rsp_demux_029:sink_valid
wire [98:0] router_031_src_data; // router_031:src_data -> rsp_demux_029:sink_data
wire router_031_src_ready; // rsp_demux_029:sink_ready -> router_031:src_ready
wire [31:0] router_031_src_channel; // router_031:src_channel -> rsp_demux_029:sink_channel
wire router_031_src_startofpacket; // router_031:src_startofpacket -> rsp_demux_029:sink_startofpacket
wire router_031_src_endofpacket; // router_031:src_endofpacket -> rsp_demux_029:sink_endofpacket
wire alu_negative_s1_agent_rp_valid; // alu_negative_s1_agent:rp_valid -> router_032:sink_valid
wire [98:0] alu_negative_s1_agent_rp_data; // alu_negative_s1_agent:rp_data -> router_032:sink_data
wire alu_negative_s1_agent_rp_ready; // router_032:sink_ready -> alu_negative_s1_agent:rp_ready
wire alu_negative_s1_agent_rp_startofpacket; // alu_negative_s1_agent:rp_startofpacket -> router_032:sink_startofpacket
wire alu_negative_s1_agent_rp_endofpacket; // alu_negative_s1_agent:rp_endofpacket -> router_032:sink_endofpacket
wire router_032_src_valid; // router_032:src_valid -> rsp_demux_030:sink_valid
wire [98:0] router_032_src_data; // router_032:src_data -> rsp_demux_030:sink_data
wire router_032_src_ready; // rsp_demux_030:sink_ready -> router_032:src_ready
wire [31:0] router_032_src_channel; // router_032:src_channel -> rsp_demux_030:sink_channel
wire router_032_src_startofpacket; // router_032:src_startofpacket -> rsp_demux_030:sink_startofpacket
wire router_032_src_endofpacket; // router_032:src_endofpacket -> rsp_demux_030:sink_endofpacket
wire keys_s1_agent_rp_valid; // keys_s1_agent:rp_valid -> router_033:sink_valid
wire [98:0] keys_s1_agent_rp_data; // keys_s1_agent:rp_data -> router_033:sink_data
wire keys_s1_agent_rp_ready; // router_033:sink_ready -> keys_s1_agent:rp_ready
wire keys_s1_agent_rp_startofpacket; // keys_s1_agent:rp_startofpacket -> router_033:sink_startofpacket
wire keys_s1_agent_rp_endofpacket; // keys_s1_agent:rp_endofpacket -> router_033:sink_endofpacket
wire router_033_src_valid; // router_033:src_valid -> rsp_demux_031:sink_valid
wire [98:0] router_033_src_data; // router_033:src_data -> rsp_demux_031:sink_data
wire router_033_src_ready; // rsp_demux_031:sink_ready -> router_033:src_ready
wire [31:0] router_033_src_channel; // router_033:src_channel -> rsp_demux_031:sink_channel
wire router_033_src_startofpacket; // router_033:src_startofpacket -> rsp_demux_031:sink_startofpacket
wire router_033_src_endofpacket; // router_033:src_endofpacket -> rsp_demux_031:sink_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [98:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [31:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [98:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [31:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [98:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [31:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [98:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [31:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire [98:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire [31:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire [98:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire [31:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
wire [98:0] cmd_demux_src6_data; // cmd_demux:src6_data -> cmd_mux_006:sink0_data
wire cmd_demux_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
wire [31:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
wire cmd_demux_src7_valid; // cmd_demux:src7_valid -> cmd_mux_007:sink0_valid
wire [98:0] cmd_demux_src7_data; // cmd_demux:src7_data -> cmd_mux_007:sink0_data
wire cmd_demux_src7_ready; // cmd_mux_007:sink0_ready -> cmd_demux:src7_ready
wire [31:0] cmd_demux_src7_channel; // cmd_demux:src7_channel -> cmd_mux_007:sink0_channel
wire cmd_demux_src7_startofpacket; // cmd_demux:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
wire cmd_demux_src7_endofpacket; // cmd_demux:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
wire cmd_demux_src8_valid; // cmd_demux:src8_valid -> cmd_mux_008:sink0_valid
wire [98:0] cmd_demux_src8_data; // cmd_demux:src8_data -> cmd_mux_008:sink0_data
wire cmd_demux_src8_ready; // cmd_mux_008:sink0_ready -> cmd_demux:src8_ready
wire [31:0] cmd_demux_src8_channel; // cmd_demux:src8_channel -> cmd_mux_008:sink0_channel
wire cmd_demux_src8_startofpacket; // cmd_demux:src8_startofpacket -> cmd_mux_008:sink0_startofpacket
wire cmd_demux_src8_endofpacket; // cmd_demux:src8_endofpacket -> cmd_mux_008:sink0_endofpacket
wire cmd_demux_src9_valid; // cmd_demux:src9_valid -> cmd_mux_009:sink0_valid
wire [98:0] cmd_demux_src9_data; // cmd_demux:src9_data -> cmd_mux_009:sink0_data
wire cmd_demux_src9_ready; // cmd_mux_009:sink0_ready -> cmd_demux:src9_ready
wire [31:0] cmd_demux_src9_channel; // cmd_demux:src9_channel -> cmd_mux_009:sink0_channel
wire cmd_demux_src9_startofpacket; // cmd_demux:src9_startofpacket -> cmd_mux_009:sink0_startofpacket
wire cmd_demux_src9_endofpacket; // cmd_demux:src9_endofpacket -> cmd_mux_009:sink0_endofpacket
wire cmd_demux_src10_valid; // cmd_demux:src10_valid -> cmd_mux_010:sink0_valid
wire [98:0] cmd_demux_src10_data; // cmd_demux:src10_data -> cmd_mux_010:sink0_data
wire cmd_demux_src10_ready; // cmd_mux_010:sink0_ready -> cmd_demux:src10_ready
wire [31:0] cmd_demux_src10_channel; // cmd_demux:src10_channel -> cmd_mux_010:sink0_channel
wire cmd_demux_src10_startofpacket; // cmd_demux:src10_startofpacket -> cmd_mux_010:sink0_startofpacket
wire cmd_demux_src10_endofpacket; // cmd_demux:src10_endofpacket -> cmd_mux_010:sink0_endofpacket
wire cmd_demux_src11_valid; // cmd_demux:src11_valid -> cmd_mux_011:sink0_valid
wire [98:0] cmd_demux_src11_data; // cmd_demux:src11_data -> cmd_mux_011:sink0_data
wire cmd_demux_src11_ready; // cmd_mux_011:sink0_ready -> cmd_demux:src11_ready
wire [31:0] cmd_demux_src11_channel; // cmd_demux:src11_channel -> cmd_mux_011:sink0_channel
wire cmd_demux_src11_startofpacket; // cmd_demux:src11_startofpacket -> cmd_mux_011:sink0_startofpacket
wire cmd_demux_src11_endofpacket; // cmd_demux:src11_endofpacket -> cmd_mux_011:sink0_endofpacket
wire cmd_demux_src12_valid; // cmd_demux:src12_valid -> cmd_mux_012:sink0_valid
wire [98:0] cmd_demux_src12_data; // cmd_demux:src12_data -> cmd_mux_012:sink0_data
wire cmd_demux_src12_ready; // cmd_mux_012:sink0_ready -> cmd_demux:src12_ready
wire [31:0] cmd_demux_src12_channel; // cmd_demux:src12_channel -> cmd_mux_012:sink0_channel
wire cmd_demux_src12_startofpacket; // cmd_demux:src12_startofpacket -> cmd_mux_012:sink0_startofpacket
wire cmd_demux_src12_endofpacket; // cmd_demux:src12_endofpacket -> cmd_mux_012:sink0_endofpacket
wire cmd_demux_src13_valid; // cmd_demux:src13_valid -> cmd_mux_013:sink0_valid
wire [98:0] cmd_demux_src13_data; // cmd_demux:src13_data -> cmd_mux_013:sink0_data
wire cmd_demux_src13_ready; // cmd_mux_013:sink0_ready -> cmd_demux:src13_ready
wire [31:0] cmd_demux_src13_channel; // cmd_demux:src13_channel -> cmd_mux_013:sink0_channel
wire cmd_demux_src13_startofpacket; // cmd_demux:src13_startofpacket -> cmd_mux_013:sink0_startofpacket
wire cmd_demux_src13_endofpacket; // cmd_demux:src13_endofpacket -> cmd_mux_013:sink0_endofpacket
wire cmd_demux_src14_valid; // cmd_demux:src14_valid -> cmd_mux_014:sink0_valid
wire [98:0] cmd_demux_src14_data; // cmd_demux:src14_data -> cmd_mux_014:sink0_data
wire cmd_demux_src14_ready; // cmd_mux_014:sink0_ready -> cmd_demux:src14_ready
wire [31:0] cmd_demux_src14_channel; // cmd_demux:src14_channel -> cmd_mux_014:sink0_channel
wire cmd_demux_src14_startofpacket; // cmd_demux:src14_startofpacket -> cmd_mux_014:sink0_startofpacket
wire cmd_demux_src14_endofpacket; // cmd_demux:src14_endofpacket -> cmd_mux_014:sink0_endofpacket
wire cmd_demux_src15_valid; // cmd_demux:src15_valid -> cmd_mux_015:sink0_valid
wire [98:0] cmd_demux_src15_data; // cmd_demux:src15_data -> cmd_mux_015:sink0_data
wire cmd_demux_src15_ready; // cmd_mux_015:sink0_ready -> cmd_demux:src15_ready
wire [31:0] cmd_demux_src15_channel; // cmd_demux:src15_channel -> cmd_mux_015:sink0_channel
wire cmd_demux_src15_startofpacket; // cmd_demux:src15_startofpacket -> cmd_mux_015:sink0_startofpacket
wire cmd_demux_src15_endofpacket; // cmd_demux:src15_endofpacket -> cmd_mux_015:sink0_endofpacket
wire cmd_demux_src16_valid; // cmd_demux:src16_valid -> cmd_mux_016:sink0_valid
wire [98:0] cmd_demux_src16_data; // cmd_demux:src16_data -> cmd_mux_016:sink0_data
wire cmd_demux_src16_ready; // cmd_mux_016:sink0_ready -> cmd_demux:src16_ready
wire [31:0] cmd_demux_src16_channel; // cmd_demux:src16_channel -> cmd_mux_016:sink0_channel
wire cmd_demux_src16_startofpacket; // cmd_demux:src16_startofpacket -> cmd_mux_016:sink0_startofpacket
wire cmd_demux_src16_endofpacket; // cmd_demux:src16_endofpacket -> cmd_mux_016:sink0_endofpacket
wire cmd_demux_src17_valid; // cmd_demux:src17_valid -> cmd_mux_017:sink0_valid
wire [98:0] cmd_demux_src17_data; // cmd_demux:src17_data -> cmd_mux_017:sink0_data
wire cmd_demux_src17_ready; // cmd_mux_017:sink0_ready -> cmd_demux:src17_ready
wire [31:0] cmd_demux_src17_channel; // cmd_demux:src17_channel -> cmd_mux_017:sink0_channel
wire cmd_demux_src17_startofpacket; // cmd_demux:src17_startofpacket -> cmd_mux_017:sink0_startofpacket
wire cmd_demux_src17_endofpacket; // cmd_demux:src17_endofpacket -> cmd_mux_017:sink0_endofpacket
wire cmd_demux_src18_valid; // cmd_demux:src18_valid -> cmd_mux_018:sink0_valid
wire [98:0] cmd_demux_src18_data; // cmd_demux:src18_data -> cmd_mux_018:sink0_data
wire cmd_demux_src18_ready; // cmd_mux_018:sink0_ready -> cmd_demux:src18_ready
wire [31:0] cmd_demux_src18_channel; // cmd_demux:src18_channel -> cmd_mux_018:sink0_channel
wire cmd_demux_src18_startofpacket; // cmd_demux:src18_startofpacket -> cmd_mux_018:sink0_startofpacket
wire cmd_demux_src18_endofpacket; // cmd_demux:src18_endofpacket -> cmd_mux_018:sink0_endofpacket
wire cmd_demux_src19_valid; // cmd_demux:src19_valid -> cmd_mux_019:sink0_valid
wire [98:0] cmd_demux_src19_data; // cmd_demux:src19_data -> cmd_mux_019:sink0_data
wire cmd_demux_src19_ready; // cmd_mux_019:sink0_ready -> cmd_demux:src19_ready
wire [31:0] cmd_demux_src19_channel; // cmd_demux:src19_channel -> cmd_mux_019:sink0_channel
wire cmd_demux_src19_startofpacket; // cmd_demux:src19_startofpacket -> cmd_mux_019:sink0_startofpacket
wire cmd_demux_src19_endofpacket; // cmd_demux:src19_endofpacket -> cmd_mux_019:sink0_endofpacket
wire cmd_demux_src20_valid; // cmd_demux:src20_valid -> cmd_mux_020:sink0_valid
wire [98:0] cmd_demux_src20_data; // cmd_demux:src20_data -> cmd_mux_020:sink0_data
wire cmd_demux_src20_ready; // cmd_mux_020:sink0_ready -> cmd_demux:src20_ready
wire [31:0] cmd_demux_src20_channel; // cmd_demux:src20_channel -> cmd_mux_020:sink0_channel
wire cmd_demux_src20_startofpacket; // cmd_demux:src20_startofpacket -> cmd_mux_020:sink0_startofpacket
wire cmd_demux_src20_endofpacket; // cmd_demux:src20_endofpacket -> cmd_mux_020:sink0_endofpacket
wire cmd_demux_src21_valid; // cmd_demux:src21_valid -> cmd_mux_021:sink0_valid
wire [98:0] cmd_demux_src21_data; // cmd_demux:src21_data -> cmd_mux_021:sink0_data
wire cmd_demux_src21_ready; // cmd_mux_021:sink0_ready -> cmd_demux:src21_ready
wire [31:0] cmd_demux_src21_channel; // cmd_demux:src21_channel -> cmd_mux_021:sink0_channel
wire cmd_demux_src21_startofpacket; // cmd_demux:src21_startofpacket -> cmd_mux_021:sink0_startofpacket
wire cmd_demux_src21_endofpacket; // cmd_demux:src21_endofpacket -> cmd_mux_021:sink0_endofpacket
wire cmd_demux_src22_valid; // cmd_demux:src22_valid -> cmd_mux_022:sink0_valid
wire [98:0] cmd_demux_src22_data; // cmd_demux:src22_data -> cmd_mux_022:sink0_data
wire cmd_demux_src22_ready; // cmd_mux_022:sink0_ready -> cmd_demux:src22_ready
wire [31:0] cmd_demux_src22_channel; // cmd_demux:src22_channel -> cmd_mux_022:sink0_channel
wire cmd_demux_src22_startofpacket; // cmd_demux:src22_startofpacket -> cmd_mux_022:sink0_startofpacket
wire cmd_demux_src22_endofpacket; // cmd_demux:src22_endofpacket -> cmd_mux_022:sink0_endofpacket
wire cmd_demux_src23_valid; // cmd_demux:src23_valid -> cmd_mux_023:sink0_valid
wire [98:0] cmd_demux_src23_data; // cmd_demux:src23_data -> cmd_mux_023:sink0_data
wire cmd_demux_src23_ready; // cmd_mux_023:sink0_ready -> cmd_demux:src23_ready
wire [31:0] cmd_demux_src23_channel; // cmd_demux:src23_channel -> cmd_mux_023:sink0_channel
wire cmd_demux_src23_startofpacket; // cmd_demux:src23_startofpacket -> cmd_mux_023:sink0_startofpacket
wire cmd_demux_src23_endofpacket; // cmd_demux:src23_endofpacket -> cmd_mux_023:sink0_endofpacket
wire cmd_demux_src24_valid; // cmd_demux:src24_valid -> cmd_mux_024:sink0_valid
wire [98:0] cmd_demux_src24_data; // cmd_demux:src24_data -> cmd_mux_024:sink0_data
wire cmd_demux_src24_ready; // cmd_mux_024:sink0_ready -> cmd_demux:src24_ready
wire [31:0] cmd_demux_src24_channel; // cmd_demux:src24_channel -> cmd_mux_024:sink0_channel
wire cmd_demux_src24_startofpacket; // cmd_demux:src24_startofpacket -> cmd_mux_024:sink0_startofpacket
wire cmd_demux_src24_endofpacket; // cmd_demux:src24_endofpacket -> cmd_mux_024:sink0_endofpacket
wire cmd_demux_src25_valid; // cmd_demux:src25_valid -> cmd_mux_025:sink0_valid
wire [98:0] cmd_demux_src25_data; // cmd_demux:src25_data -> cmd_mux_025:sink0_data
wire cmd_demux_src25_ready; // cmd_mux_025:sink0_ready -> cmd_demux:src25_ready
wire [31:0] cmd_demux_src25_channel; // cmd_demux:src25_channel -> cmd_mux_025:sink0_channel
wire cmd_demux_src25_startofpacket; // cmd_demux:src25_startofpacket -> cmd_mux_025:sink0_startofpacket
wire cmd_demux_src25_endofpacket; // cmd_demux:src25_endofpacket -> cmd_mux_025:sink0_endofpacket
wire cmd_demux_src26_valid; // cmd_demux:src26_valid -> cmd_mux_026:sink0_valid
wire [98:0] cmd_demux_src26_data; // cmd_demux:src26_data -> cmd_mux_026:sink0_data
wire cmd_demux_src26_ready; // cmd_mux_026:sink0_ready -> cmd_demux:src26_ready
wire [31:0] cmd_demux_src26_channel; // cmd_demux:src26_channel -> cmd_mux_026:sink0_channel
wire cmd_demux_src26_startofpacket; // cmd_demux:src26_startofpacket -> cmd_mux_026:sink0_startofpacket
wire cmd_demux_src26_endofpacket; // cmd_demux:src26_endofpacket -> cmd_mux_026:sink0_endofpacket
wire cmd_demux_src27_valid; // cmd_demux:src27_valid -> cmd_mux_027:sink0_valid
wire [98:0] cmd_demux_src27_data; // cmd_demux:src27_data -> cmd_mux_027:sink0_data
wire cmd_demux_src27_ready; // cmd_mux_027:sink0_ready -> cmd_demux:src27_ready
wire [31:0] cmd_demux_src27_channel; // cmd_demux:src27_channel -> cmd_mux_027:sink0_channel
wire cmd_demux_src27_startofpacket; // cmd_demux:src27_startofpacket -> cmd_mux_027:sink0_startofpacket
wire cmd_demux_src27_endofpacket; // cmd_demux:src27_endofpacket -> cmd_mux_027:sink0_endofpacket
wire cmd_demux_src28_valid; // cmd_demux:src28_valid -> cmd_mux_028:sink0_valid
wire [98:0] cmd_demux_src28_data; // cmd_demux:src28_data -> cmd_mux_028:sink0_data
wire cmd_demux_src28_ready; // cmd_mux_028:sink0_ready -> cmd_demux:src28_ready
wire [31:0] cmd_demux_src28_channel; // cmd_demux:src28_channel -> cmd_mux_028:sink0_channel
wire cmd_demux_src28_startofpacket; // cmd_demux:src28_startofpacket -> cmd_mux_028:sink0_startofpacket
wire cmd_demux_src28_endofpacket; // cmd_demux:src28_endofpacket -> cmd_mux_028:sink0_endofpacket
wire cmd_demux_src29_valid; // cmd_demux:src29_valid -> cmd_mux_029:sink0_valid
wire [98:0] cmd_demux_src29_data; // cmd_demux:src29_data -> cmd_mux_029:sink0_data
wire cmd_demux_src29_ready; // cmd_mux_029:sink0_ready -> cmd_demux:src29_ready
wire [31:0] cmd_demux_src29_channel; // cmd_demux:src29_channel -> cmd_mux_029:sink0_channel
wire cmd_demux_src29_startofpacket; // cmd_demux:src29_startofpacket -> cmd_mux_029:sink0_startofpacket
wire cmd_demux_src29_endofpacket; // cmd_demux:src29_endofpacket -> cmd_mux_029:sink0_endofpacket
wire cmd_demux_src30_valid; // cmd_demux:src30_valid -> cmd_mux_030:sink0_valid
wire [98:0] cmd_demux_src30_data; // cmd_demux:src30_data -> cmd_mux_030:sink0_data
wire cmd_demux_src30_ready; // cmd_mux_030:sink0_ready -> cmd_demux:src30_ready
wire [31:0] cmd_demux_src30_channel; // cmd_demux:src30_channel -> cmd_mux_030:sink0_channel
wire cmd_demux_src30_startofpacket; // cmd_demux:src30_startofpacket -> cmd_mux_030:sink0_startofpacket
wire cmd_demux_src30_endofpacket; // cmd_demux:src30_endofpacket -> cmd_mux_030:sink0_endofpacket
wire cmd_demux_src31_valid; // cmd_demux:src31_valid -> cmd_mux_031:sink0_valid
wire [98:0] cmd_demux_src31_data; // cmd_demux:src31_data -> cmd_mux_031:sink0_data
wire cmd_demux_src31_ready; // cmd_mux_031:sink0_ready -> cmd_demux:src31_ready
wire [31:0] cmd_demux_src31_channel; // cmd_demux:src31_channel -> cmd_mux_031:sink0_channel
wire cmd_demux_src31_startofpacket; // cmd_demux:src31_startofpacket -> cmd_mux_031:sink0_startofpacket
wire cmd_demux_src31_endofpacket; // cmd_demux:src31_endofpacket -> cmd_mux_031:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux_001:sink1_valid
wire [98:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux_001:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src0_ready
wire [31:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_002:sink1_valid
wire [98:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_002:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src1_ready
wire [31:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_002:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_002:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [98:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [31:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [98:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [31:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink0_valid
wire [98:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux_001:src1_ready
wire [31:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [98:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [31:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink1_valid
wire [98:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_002_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_002:src1_ready
wire [31:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [98:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [31:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire [98:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire [31:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire [98:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire [31:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
wire [98:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux:sink6_data
wire rsp_demux_006_src0_ready; // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
wire [31:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
wire rsp_demux_007_src0_valid; // rsp_demux_007:src0_valid -> rsp_mux:sink7_valid
wire [98:0] rsp_demux_007_src0_data; // rsp_demux_007:src0_data -> rsp_mux:sink7_data
wire rsp_demux_007_src0_ready; // rsp_mux:sink7_ready -> rsp_demux_007:src0_ready
wire [31:0] rsp_demux_007_src0_channel; // rsp_demux_007:src0_channel -> rsp_mux:sink7_channel
wire rsp_demux_007_src0_startofpacket; // rsp_demux_007:src0_startofpacket -> rsp_mux:sink7_startofpacket
wire rsp_demux_007_src0_endofpacket; // rsp_demux_007:src0_endofpacket -> rsp_mux:sink7_endofpacket
wire rsp_demux_008_src0_valid; // rsp_demux_008:src0_valid -> rsp_mux:sink8_valid
wire [98:0] rsp_demux_008_src0_data; // rsp_demux_008:src0_data -> rsp_mux:sink8_data
wire rsp_demux_008_src0_ready; // rsp_mux:sink8_ready -> rsp_demux_008:src0_ready
wire [31:0] rsp_demux_008_src0_channel; // rsp_demux_008:src0_channel -> rsp_mux:sink8_channel
wire rsp_demux_008_src0_startofpacket; // rsp_demux_008:src0_startofpacket -> rsp_mux:sink8_startofpacket
wire rsp_demux_008_src0_endofpacket; // rsp_demux_008:src0_endofpacket -> rsp_mux:sink8_endofpacket
wire rsp_demux_009_src0_valid; // rsp_demux_009:src0_valid -> rsp_mux:sink9_valid
wire [98:0] rsp_demux_009_src0_data; // rsp_demux_009:src0_data -> rsp_mux:sink9_data
wire rsp_demux_009_src0_ready; // rsp_mux:sink9_ready -> rsp_demux_009:src0_ready
wire [31:0] rsp_demux_009_src0_channel; // rsp_demux_009:src0_channel -> rsp_mux:sink9_channel
wire rsp_demux_009_src0_startofpacket; // rsp_demux_009:src0_startofpacket -> rsp_mux:sink9_startofpacket
wire rsp_demux_009_src0_endofpacket; // rsp_demux_009:src0_endofpacket -> rsp_mux:sink9_endofpacket
wire rsp_demux_010_src0_valid; // rsp_demux_010:src0_valid -> rsp_mux:sink10_valid
wire [98:0] rsp_demux_010_src0_data; // rsp_demux_010:src0_data -> rsp_mux:sink10_data
wire rsp_demux_010_src0_ready; // rsp_mux:sink10_ready -> rsp_demux_010:src0_ready
wire [31:0] rsp_demux_010_src0_channel; // rsp_demux_010:src0_channel -> rsp_mux:sink10_channel
wire rsp_demux_010_src0_startofpacket; // rsp_demux_010:src0_startofpacket -> rsp_mux:sink10_startofpacket
wire rsp_demux_010_src0_endofpacket; // rsp_demux_010:src0_endofpacket -> rsp_mux:sink10_endofpacket
wire rsp_demux_011_src0_valid; // rsp_demux_011:src0_valid -> rsp_mux:sink11_valid
wire [98:0] rsp_demux_011_src0_data; // rsp_demux_011:src0_data -> rsp_mux:sink11_data
wire rsp_demux_011_src0_ready; // rsp_mux:sink11_ready -> rsp_demux_011:src0_ready
wire [31:0] rsp_demux_011_src0_channel; // rsp_demux_011:src0_channel -> rsp_mux:sink11_channel
wire rsp_demux_011_src0_startofpacket; // rsp_demux_011:src0_startofpacket -> rsp_mux:sink11_startofpacket
wire rsp_demux_011_src0_endofpacket; // rsp_demux_011:src0_endofpacket -> rsp_mux:sink11_endofpacket
wire rsp_demux_012_src0_valid; // rsp_demux_012:src0_valid -> rsp_mux:sink12_valid
wire [98:0] rsp_demux_012_src0_data; // rsp_demux_012:src0_data -> rsp_mux:sink12_data
wire rsp_demux_012_src0_ready; // rsp_mux:sink12_ready -> rsp_demux_012:src0_ready
wire [31:0] rsp_demux_012_src0_channel; // rsp_demux_012:src0_channel -> rsp_mux:sink12_channel
wire rsp_demux_012_src0_startofpacket; // rsp_demux_012:src0_startofpacket -> rsp_mux:sink12_startofpacket
wire rsp_demux_012_src0_endofpacket; // rsp_demux_012:src0_endofpacket -> rsp_mux:sink12_endofpacket
wire rsp_demux_013_src0_valid; // rsp_demux_013:src0_valid -> rsp_mux:sink13_valid
wire [98:0] rsp_demux_013_src0_data; // rsp_demux_013:src0_data -> rsp_mux:sink13_data
wire rsp_demux_013_src0_ready; // rsp_mux:sink13_ready -> rsp_demux_013:src0_ready
wire [31:0] rsp_demux_013_src0_channel; // rsp_demux_013:src0_channel -> rsp_mux:sink13_channel
wire rsp_demux_013_src0_startofpacket; // rsp_demux_013:src0_startofpacket -> rsp_mux:sink13_startofpacket
wire rsp_demux_013_src0_endofpacket; // rsp_demux_013:src0_endofpacket -> rsp_mux:sink13_endofpacket
wire rsp_demux_014_src0_valid; // rsp_demux_014:src0_valid -> rsp_mux:sink14_valid
wire [98:0] rsp_demux_014_src0_data; // rsp_demux_014:src0_data -> rsp_mux:sink14_data
wire rsp_demux_014_src0_ready; // rsp_mux:sink14_ready -> rsp_demux_014:src0_ready
wire [31:0] rsp_demux_014_src0_channel; // rsp_demux_014:src0_channel -> rsp_mux:sink14_channel
wire rsp_demux_014_src0_startofpacket; // rsp_demux_014:src0_startofpacket -> rsp_mux:sink14_startofpacket
wire rsp_demux_014_src0_endofpacket; // rsp_demux_014:src0_endofpacket -> rsp_mux:sink14_endofpacket
wire rsp_demux_015_src0_valid; // rsp_demux_015:src0_valid -> rsp_mux:sink15_valid
wire [98:0] rsp_demux_015_src0_data; // rsp_demux_015:src0_data -> rsp_mux:sink15_data
wire rsp_demux_015_src0_ready; // rsp_mux:sink15_ready -> rsp_demux_015:src0_ready
wire [31:0] rsp_demux_015_src0_channel; // rsp_demux_015:src0_channel -> rsp_mux:sink15_channel
wire rsp_demux_015_src0_startofpacket; // rsp_demux_015:src0_startofpacket -> rsp_mux:sink15_startofpacket
wire rsp_demux_015_src0_endofpacket; // rsp_demux_015:src0_endofpacket -> rsp_mux:sink15_endofpacket
wire rsp_demux_016_src0_valid; // rsp_demux_016:src0_valid -> rsp_mux:sink16_valid
wire [98:0] rsp_demux_016_src0_data; // rsp_demux_016:src0_data -> rsp_mux:sink16_data
wire rsp_demux_016_src0_ready; // rsp_mux:sink16_ready -> rsp_demux_016:src0_ready
wire [31:0] rsp_demux_016_src0_channel; // rsp_demux_016:src0_channel -> rsp_mux:sink16_channel
wire rsp_demux_016_src0_startofpacket; // rsp_demux_016:src0_startofpacket -> rsp_mux:sink16_startofpacket
wire rsp_demux_016_src0_endofpacket; // rsp_demux_016:src0_endofpacket -> rsp_mux:sink16_endofpacket
wire rsp_demux_017_src0_valid; // rsp_demux_017:src0_valid -> rsp_mux:sink17_valid
wire [98:0] rsp_demux_017_src0_data; // rsp_demux_017:src0_data -> rsp_mux:sink17_data
wire rsp_demux_017_src0_ready; // rsp_mux:sink17_ready -> rsp_demux_017:src0_ready
wire [31:0] rsp_demux_017_src0_channel; // rsp_demux_017:src0_channel -> rsp_mux:sink17_channel
wire rsp_demux_017_src0_startofpacket; // rsp_demux_017:src0_startofpacket -> rsp_mux:sink17_startofpacket
wire rsp_demux_017_src0_endofpacket; // rsp_demux_017:src0_endofpacket -> rsp_mux:sink17_endofpacket
wire rsp_demux_018_src0_valid; // rsp_demux_018:src0_valid -> rsp_mux:sink18_valid
wire [98:0] rsp_demux_018_src0_data; // rsp_demux_018:src0_data -> rsp_mux:sink18_data
wire rsp_demux_018_src0_ready; // rsp_mux:sink18_ready -> rsp_demux_018:src0_ready
wire [31:0] rsp_demux_018_src0_channel; // rsp_demux_018:src0_channel -> rsp_mux:sink18_channel
wire rsp_demux_018_src0_startofpacket; // rsp_demux_018:src0_startofpacket -> rsp_mux:sink18_startofpacket
wire rsp_demux_018_src0_endofpacket; // rsp_demux_018:src0_endofpacket -> rsp_mux:sink18_endofpacket
wire rsp_demux_019_src0_valid; // rsp_demux_019:src0_valid -> rsp_mux:sink19_valid
wire [98:0] rsp_demux_019_src0_data; // rsp_demux_019:src0_data -> rsp_mux:sink19_data
wire rsp_demux_019_src0_ready; // rsp_mux:sink19_ready -> rsp_demux_019:src0_ready
wire [31:0] rsp_demux_019_src0_channel; // rsp_demux_019:src0_channel -> rsp_mux:sink19_channel
wire rsp_demux_019_src0_startofpacket; // rsp_demux_019:src0_startofpacket -> rsp_mux:sink19_startofpacket
wire rsp_demux_019_src0_endofpacket; // rsp_demux_019:src0_endofpacket -> rsp_mux:sink19_endofpacket
wire rsp_demux_020_src0_valid; // rsp_demux_020:src0_valid -> rsp_mux:sink20_valid
wire [98:0] rsp_demux_020_src0_data; // rsp_demux_020:src0_data -> rsp_mux:sink20_data
wire rsp_demux_020_src0_ready; // rsp_mux:sink20_ready -> rsp_demux_020:src0_ready
wire [31:0] rsp_demux_020_src0_channel; // rsp_demux_020:src0_channel -> rsp_mux:sink20_channel
wire rsp_demux_020_src0_startofpacket; // rsp_demux_020:src0_startofpacket -> rsp_mux:sink20_startofpacket
wire rsp_demux_020_src0_endofpacket; // rsp_demux_020:src0_endofpacket -> rsp_mux:sink20_endofpacket
wire rsp_demux_021_src0_valid; // rsp_demux_021:src0_valid -> rsp_mux:sink21_valid
wire [98:0] rsp_demux_021_src0_data; // rsp_demux_021:src0_data -> rsp_mux:sink21_data
wire rsp_demux_021_src0_ready; // rsp_mux:sink21_ready -> rsp_demux_021:src0_ready
wire [31:0] rsp_demux_021_src0_channel; // rsp_demux_021:src0_channel -> rsp_mux:sink21_channel
wire rsp_demux_021_src0_startofpacket; // rsp_demux_021:src0_startofpacket -> rsp_mux:sink21_startofpacket
wire rsp_demux_021_src0_endofpacket; // rsp_demux_021:src0_endofpacket -> rsp_mux:sink21_endofpacket
wire rsp_demux_022_src0_valid; // rsp_demux_022:src0_valid -> rsp_mux:sink22_valid
wire [98:0] rsp_demux_022_src0_data; // rsp_demux_022:src0_data -> rsp_mux:sink22_data
wire rsp_demux_022_src0_ready; // rsp_mux:sink22_ready -> rsp_demux_022:src0_ready
wire [31:0] rsp_demux_022_src0_channel; // rsp_demux_022:src0_channel -> rsp_mux:sink22_channel
wire rsp_demux_022_src0_startofpacket; // rsp_demux_022:src0_startofpacket -> rsp_mux:sink22_startofpacket
wire rsp_demux_022_src0_endofpacket; // rsp_demux_022:src0_endofpacket -> rsp_mux:sink22_endofpacket
wire rsp_demux_023_src0_valid; // rsp_demux_023:src0_valid -> rsp_mux:sink23_valid
wire [98:0] rsp_demux_023_src0_data; // rsp_demux_023:src0_data -> rsp_mux:sink23_data
wire rsp_demux_023_src0_ready; // rsp_mux:sink23_ready -> rsp_demux_023:src0_ready
wire [31:0] rsp_demux_023_src0_channel; // rsp_demux_023:src0_channel -> rsp_mux:sink23_channel
wire rsp_demux_023_src0_startofpacket; // rsp_demux_023:src0_startofpacket -> rsp_mux:sink23_startofpacket
wire rsp_demux_023_src0_endofpacket; // rsp_demux_023:src0_endofpacket -> rsp_mux:sink23_endofpacket
wire rsp_demux_024_src0_valid; // rsp_demux_024:src0_valid -> rsp_mux:sink24_valid
wire [98:0] rsp_demux_024_src0_data; // rsp_demux_024:src0_data -> rsp_mux:sink24_data
wire rsp_demux_024_src0_ready; // rsp_mux:sink24_ready -> rsp_demux_024:src0_ready
wire [31:0] rsp_demux_024_src0_channel; // rsp_demux_024:src0_channel -> rsp_mux:sink24_channel
wire rsp_demux_024_src0_startofpacket; // rsp_demux_024:src0_startofpacket -> rsp_mux:sink24_startofpacket
wire rsp_demux_024_src0_endofpacket; // rsp_demux_024:src0_endofpacket -> rsp_mux:sink24_endofpacket
wire rsp_demux_025_src0_valid; // rsp_demux_025:src0_valid -> rsp_mux:sink25_valid
wire [98:0] rsp_demux_025_src0_data; // rsp_demux_025:src0_data -> rsp_mux:sink25_data
wire rsp_demux_025_src0_ready; // rsp_mux:sink25_ready -> rsp_demux_025:src0_ready
wire [31:0] rsp_demux_025_src0_channel; // rsp_demux_025:src0_channel -> rsp_mux:sink25_channel
wire rsp_demux_025_src0_startofpacket; // rsp_demux_025:src0_startofpacket -> rsp_mux:sink25_startofpacket
wire rsp_demux_025_src0_endofpacket; // rsp_demux_025:src0_endofpacket -> rsp_mux:sink25_endofpacket
wire rsp_demux_026_src0_valid; // rsp_demux_026:src0_valid -> rsp_mux:sink26_valid
wire [98:0] rsp_demux_026_src0_data; // rsp_demux_026:src0_data -> rsp_mux:sink26_data
wire rsp_demux_026_src0_ready; // rsp_mux:sink26_ready -> rsp_demux_026:src0_ready
wire [31:0] rsp_demux_026_src0_channel; // rsp_demux_026:src0_channel -> rsp_mux:sink26_channel
wire rsp_demux_026_src0_startofpacket; // rsp_demux_026:src0_startofpacket -> rsp_mux:sink26_startofpacket
wire rsp_demux_026_src0_endofpacket; // rsp_demux_026:src0_endofpacket -> rsp_mux:sink26_endofpacket
wire rsp_demux_027_src0_valid; // rsp_demux_027:src0_valid -> rsp_mux:sink27_valid
wire [98:0] rsp_demux_027_src0_data; // rsp_demux_027:src0_data -> rsp_mux:sink27_data
wire rsp_demux_027_src0_ready; // rsp_mux:sink27_ready -> rsp_demux_027:src0_ready
wire [31:0] rsp_demux_027_src0_channel; // rsp_demux_027:src0_channel -> rsp_mux:sink27_channel
wire rsp_demux_027_src0_startofpacket; // rsp_demux_027:src0_startofpacket -> rsp_mux:sink27_startofpacket
wire rsp_demux_027_src0_endofpacket; // rsp_demux_027:src0_endofpacket -> rsp_mux:sink27_endofpacket
wire rsp_demux_028_src0_valid; // rsp_demux_028:src0_valid -> rsp_mux:sink28_valid
wire [98:0] rsp_demux_028_src0_data; // rsp_demux_028:src0_data -> rsp_mux:sink28_data
wire rsp_demux_028_src0_ready; // rsp_mux:sink28_ready -> rsp_demux_028:src0_ready
wire [31:0] rsp_demux_028_src0_channel; // rsp_demux_028:src0_channel -> rsp_mux:sink28_channel
wire rsp_demux_028_src0_startofpacket; // rsp_demux_028:src0_startofpacket -> rsp_mux:sink28_startofpacket
wire rsp_demux_028_src0_endofpacket; // rsp_demux_028:src0_endofpacket -> rsp_mux:sink28_endofpacket
wire rsp_demux_029_src0_valid; // rsp_demux_029:src0_valid -> rsp_mux:sink29_valid
wire [98:0] rsp_demux_029_src0_data; // rsp_demux_029:src0_data -> rsp_mux:sink29_data
wire rsp_demux_029_src0_ready; // rsp_mux:sink29_ready -> rsp_demux_029:src0_ready
wire [31:0] rsp_demux_029_src0_channel; // rsp_demux_029:src0_channel -> rsp_mux:sink29_channel
wire rsp_demux_029_src0_startofpacket; // rsp_demux_029:src0_startofpacket -> rsp_mux:sink29_startofpacket
wire rsp_demux_029_src0_endofpacket; // rsp_demux_029:src0_endofpacket -> rsp_mux:sink29_endofpacket
wire rsp_demux_030_src0_valid; // rsp_demux_030:src0_valid -> rsp_mux:sink30_valid
wire [98:0] rsp_demux_030_src0_data; // rsp_demux_030:src0_data -> rsp_mux:sink30_data
wire rsp_demux_030_src0_ready; // rsp_mux:sink30_ready -> rsp_demux_030:src0_ready
wire [31:0] rsp_demux_030_src0_channel; // rsp_demux_030:src0_channel -> rsp_mux:sink30_channel
wire rsp_demux_030_src0_startofpacket; // rsp_demux_030:src0_startofpacket -> rsp_mux:sink30_startofpacket
wire rsp_demux_030_src0_endofpacket; // rsp_demux_030:src0_endofpacket -> rsp_mux:sink30_endofpacket
wire rsp_demux_031_src0_valid; // rsp_demux_031:src0_valid -> rsp_mux:sink31_valid
wire [98:0] rsp_demux_031_src0_data; // rsp_demux_031:src0_data -> rsp_mux:sink31_data
wire rsp_demux_031_src0_ready; // rsp_mux:sink31_ready -> rsp_demux_031:src0_ready
wire [31:0] rsp_demux_031_src0_channel; // rsp_demux_031:src0_channel -> rsp_mux:sink31_channel
wire rsp_demux_031_src0_startofpacket; // rsp_demux_031:src0_startofpacket -> rsp_mux:sink31_startofpacket
wire rsp_demux_031_src0_endofpacket; // rsp_demux_031:src0_endofpacket -> rsp_mux:sink31_endofpacket
altera_merlin_master_translator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) nios2_qsys_0_data_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_qsys_0_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_qsys_0_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_qsys_0_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_qsys_0_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_qsys_0_data_master_waitrequest), // .waitrequest
.av_byteenable (nios2_qsys_0_data_master_byteenable), // .byteenable
.av_read (nios2_qsys_0_data_master_read), // .read
.av_readdata (nios2_qsys_0_data_master_readdata), // .readdata
.av_write (nios2_qsys_0_data_master_write), // .write
.av_writedata (nios2_qsys_0_data_master_writedata), // .writedata
.av_debugaccess (nios2_qsys_0_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_qsys_0_instruction_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_qsys_0_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_qsys_0_instruction_master_waitrequest), // .waitrequest
.av_read (nios2_qsys_0_instruction_master_read), // .read
.av_readdata (nios2_qsys_0_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_0_avalon_jtag_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_uart_0_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_0_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_0_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_uart_0_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_0_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_0_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_0_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_0_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_0_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_0_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_0_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_0_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_0_avalon_jtag_slave_write), // .write
.av_read (jtag_uart_0_avalon_jtag_slave_read), // .read
.av_readdata (jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.av_writedata (jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_0_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios2_qsys_0_debug_mem_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_qsys_0_debug_mem_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios2_qsys_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.uav_read (nios2_qsys_0_debug_mem_slave_agent_m0_read), // .read
.uav_write (nios2_qsys_0_debug_mem_slave_agent_m0_write), // .write
.uav_waitrequest (nios2_qsys_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_0_debug_mem_slave_agent_m0_readdata), // .readdata
.uav_writedata (nios2_qsys_0_debug_mem_slave_agent_m0_writedata), // .writedata
.uav_lock (nios2_qsys_0_debug_mem_slave_agent_m0_lock), // .lock
.uav_debugaccess (nios2_qsys_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.av_address (nios2_qsys_0_debug_mem_slave_address), // avalon_anti_slave_0.address
.av_write (nios2_qsys_0_debug_mem_slave_write), // .write
.av_read (nios2_qsys_0_debug_mem_slave_read), // .read
.av_readdata (nios2_qsys_0_debug_mem_slave_readdata), // .readdata
.av_writedata (nios2_qsys_0_debug_mem_slave_writedata), // .writedata
.av_byteenable (nios2_qsys_0_debug_mem_slave_byteenable), // .byteenable
.av_waitrequest (nios2_qsys_0_debug_mem_slave_waitrequest), // .waitrequest
.av_debugaccess (nios2_qsys_0_debug_mem_slave_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (15),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_0_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_memory2_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_0_s1_agent_m0_read), // .read
.uav_write (onchip_memory2_0_s1_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_0_s1_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_0_s1_write), // .write
.av_readdata (onchip_memory2_0_s1_readdata), // .readdata
.av_writedata (onchip_memory2_0_s1_writedata), // .writedata
.av_byteenable (onchip_memory2_0_s1_byteenable), // .byteenable
.av_chipselect (onchip_memory2_0_s1_chipselect), // .chipselect
.av_clken (onchip_memory2_0_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) leds_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (leds_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (leds_s1_agent_m0_burstcount), // .burstcount
.uav_read (leds_s1_agent_m0_read), // .read
.uav_write (leds_s1_agent_m0_write), // .write
.uav_waitrequest (leds_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (leds_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (leds_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (leds_s1_agent_m0_readdata), // .readdata
.uav_writedata (leds_s1_agent_m0_writedata), // .writedata
.uav_lock (leds_s1_agent_m0_lock), // .lock
.uav_debugaccess (leds_s1_agent_m0_debugaccess), // .debugaccess
.av_address (LEDs_s1_address), // avalon_anti_slave_0.address
.av_write (LEDs_s1_write), // .write
.av_readdata (LEDs_s1_readdata), // .readdata
.av_writedata (LEDs_s1_writedata), // .writedata
.av_chipselect (LEDs_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) switches_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (switches_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (switches_s1_agent_m0_burstcount), // .burstcount
.uav_read (switches_s1_agent_m0_read), // .read
.uav_write (switches_s1_agent_m0_write), // .write
.uav_waitrequest (switches_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (switches_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (switches_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (switches_s1_agent_m0_readdata), // .readdata
.uav_writedata (switches_s1_agent_m0_writedata), // .writedata
.uav_lock (switches_s1_agent_m0_lock), // .lock
.uav_debugaccess (switches_s1_agent_m0_debugaccess), // .debugaccess
.av_address (switches_s1_address), // avalon_anti_slave_0.address
.av_readdata (switches_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_data_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sram_data_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_data_s1_agent_m0_burstcount), // .burstcount
.uav_read (sram_data_s1_agent_m0_read), // .read
.uav_write (sram_data_s1_agent_m0_write), // .write
.uav_waitrequest (sram_data_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_data_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_data_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_data_s1_agent_m0_readdata), // .readdata
.uav_writedata (sram_data_s1_agent_m0_writedata), // .writedata
.uav_lock (sram_data_s1_agent_m0_lock), // .lock
.uav_debugaccess (sram_data_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sram_data_s1_address), // avalon_anti_slave_0.address
.av_write (sram_data_s1_write), // .write
.av_readdata (sram_data_s1_readdata), // .readdata
.av_writedata (sram_data_s1_writedata), // .writedata
.av_chipselect (sram_data_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_addr_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sram_addr_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_addr_s1_agent_m0_burstcount), // .burstcount
.uav_read (sram_addr_s1_agent_m0_read), // .read
.uav_write (sram_addr_s1_agent_m0_write), // .write
.uav_waitrequest (sram_addr_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_addr_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_addr_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_addr_s1_agent_m0_readdata), // .readdata
.uav_writedata (sram_addr_s1_agent_m0_writedata), // .writedata
.uav_lock (sram_addr_s1_agent_m0_lock), // .lock
.uav_debugaccess (sram_addr_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sram_addr_s1_address), // avalon_anti_slave_0.address
.av_write (sram_addr_s1_write), // .write
.av_readdata (sram_addr_s1_readdata), // .readdata
.av_writedata (sram_addr_s1_writedata), // .writedata
.av_chipselect (sram_addr_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_read_write_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sram_read_write_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_read_write_s1_agent_m0_burstcount), // .burstcount
.uav_read (sram_read_write_s1_agent_m0_read), // .read
.uav_write (sram_read_write_s1_agent_m0_write), // .write
.uav_waitrequest (sram_read_write_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_read_write_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_read_write_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_read_write_s1_agent_m0_readdata), // .readdata
.uav_writedata (sram_read_write_s1_agent_m0_writedata), // .writedata
.uav_lock (sram_read_write_s1_agent_m0_lock), // .lock
.uav_debugaccess (sram_read_write_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sram_read_write_s1_address), // avalon_anti_slave_0.address
.av_write (sram_read_write_s1_write), // .write
.av_readdata (sram_read_write_s1_readdata), // .readdata
.av_writedata (sram_read_write_s1_writedata), // .writedata
.av_chipselect (sram_read_write_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_cs_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sram_cs_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_cs_s1_agent_m0_burstcount), // .burstcount
.uav_read (sram_cs_s1_agent_m0_read), // .read
.uav_write (sram_cs_s1_agent_m0_write), // .write
.uav_waitrequest (sram_cs_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_cs_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_cs_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_cs_s1_agent_m0_readdata), // .readdata
.uav_writedata (sram_cs_s1_agent_m0_writedata), // .writedata
.uav_lock (sram_cs_s1_agent_m0_lock), // .lock
.uav_debugaccess (sram_cs_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sram_cs_s1_address), // avalon_anti_slave_0.address
.av_write (sram_cs_s1_write), // .write
.av_readdata (sram_cs_s1_readdata), // .readdata
.av_writedata (sram_cs_s1_writedata), // .writedata
.av_chipselect (sram_cs_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_oe_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sram_oe_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_oe_s1_agent_m0_burstcount), // .burstcount
.uav_read (sram_oe_s1_agent_m0_read), // .read
.uav_write (sram_oe_s1_agent_m0_write), // .write
.uav_waitrequest (sram_oe_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_oe_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_oe_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_oe_s1_agent_m0_readdata), // .readdata
.uav_writedata (sram_oe_s1_agent_m0_writedata), // .writedata
.uav_lock (sram_oe_s1_agent_m0_lock), // .lock
.uav_debugaccess (sram_oe_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sram_oe_s1_address), // avalon_anti_slave_0.address
.av_write (sram_oe_s1_write), // .write
.av_readdata (sram_oe_s1_readdata), // .readdata
.av_writedata (sram_oe_s1_writedata), // .writedata
.av_chipselect (sram_oe_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_data_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_data_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_data_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_data_s1_agent_m0_read), // .read
.uav_write (regfile_data_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_data_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_data_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_data_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_data_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_data_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_data_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_data_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_data_s1_address), // avalon_anti_slave_0.address
.av_write (regfile_data_s1_write), // .write
.av_readdata (regfile_data_s1_readdata), // .readdata
.av_writedata (regfile_data_s1_writedata), // .writedata
.av_chipselect (regfile_data_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_reg1_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_reg1_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_reg1_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_reg1_s1_agent_m0_read), // .read
.uav_write (regfile_reg1_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_reg1_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_reg1_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_reg1_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_reg1_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_reg1_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_reg1_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_reg1_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_reg1_s1_address), // avalon_anti_slave_0.address
.av_readdata (regfile_reg1_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_reg2_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_reg2_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_reg2_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_reg2_s1_agent_m0_read), // .read
.uav_write (regfile_reg2_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_reg2_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_reg2_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_reg2_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_reg2_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_reg2_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_reg2_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_reg2_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_reg2_s1_address), // avalon_anti_slave_0.address
.av_readdata (regfile_reg2_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_r1sel_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_r1sel_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_r1sel_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_r1sel_s1_agent_m0_read), // .read
.uav_write (regfile_r1sel_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_r1sel_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_r1sel_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_r1sel_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_r1sel_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_r1sel_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_r1sel_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_r1sel_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_r1sel_s1_address), // avalon_anti_slave_0.address
.av_write (regfile_r1sel_s1_write), // .write
.av_readdata (regfile_r1sel_s1_readdata), // .readdata
.av_writedata (regfile_r1sel_s1_writedata), // .writedata
.av_chipselect (regfile_r1sel_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_r2sel_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_r2sel_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_r2sel_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_r2sel_s1_agent_m0_read), // .read
.uav_write (regfile_r2sel_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_r2sel_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_r2sel_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_r2sel_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_r2sel_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_r2sel_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_r2sel_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_r2sel_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_r2sel_s1_address), // avalon_anti_slave_0.address
.av_write (regfile_r2sel_s1_write), // .write
.av_readdata (regfile_r2sel_s1_readdata), // .readdata
.av_writedata (regfile_r2sel_s1_writedata), // .writedata
.av_chipselect (regfile_r2sel_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_wsel_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_wsel_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_wsel_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_wsel_s1_agent_m0_read), // .read
.uav_write (regfile_wsel_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_wsel_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_wsel_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_wsel_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_wsel_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_wsel_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_wsel_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_wsel_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_wsel_s1_address), // avalon_anti_slave_0.address
.av_write (regfile_wsel_s1_write), // .write
.av_readdata (regfile_wsel_s1_readdata), // .readdata
.av_writedata (regfile_wsel_s1_writedata), // .writedata
.av_chipselect (regfile_wsel_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_we_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_we_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_we_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_we_s1_agent_m0_read), // .read
.uav_write (regfile_we_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_we_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_we_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_we_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_we_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_we_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_we_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_we_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_we_s1_address), // avalon_anti_slave_0.address
.av_write (regfile_we_s1_write), // .write
.av_readdata (regfile_we_s1_readdata), // .readdata
.av_writedata (regfile_we_s1_writedata), // .writedata
.av_chipselect (regfile_we_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex_0_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex_0_s1_agent_m0_read), // .read
.uav_write (hex_0_s1_agent_m0_write), // .write
.uav_waitrequest (hex_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex_0_s1_agent_m0_writedata), // .writedata
.uav_lock (hex_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex_0_s1_address), // avalon_anti_slave_0.address
.av_write (hex_0_s1_write), // .write
.av_readdata (hex_0_s1_readdata), // .readdata
.av_writedata (hex_0_s1_writedata), // .writedata
.av_chipselect (hex_0_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex_1_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex_1_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex_1_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex_1_s1_agent_m0_read), // .read
.uav_write (hex_1_s1_agent_m0_write), // .write
.uav_waitrequest (hex_1_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex_1_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex_1_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex_1_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex_1_s1_agent_m0_writedata), // .writedata
.uav_lock (hex_1_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex_1_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex_1_s1_address), // avalon_anti_slave_0.address
.av_write (hex_1_s1_write), // .write
.av_readdata (hex_1_s1_readdata), // .readdata
.av_writedata (hex_1_s1_writedata), // .writedata
.av_chipselect (hex_1_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex_2_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex_2_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex_2_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex_2_s1_agent_m0_read), // .read
.uav_write (hex_2_s1_agent_m0_write), // .write
.uav_waitrequest (hex_2_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex_2_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex_2_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex_2_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex_2_s1_agent_m0_writedata), // .writedata
.uav_lock (hex_2_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex_2_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex_2_s1_address), // avalon_anti_slave_0.address
.av_write (hex_2_s1_write), // .write
.av_readdata (hex_2_s1_readdata), // .readdata
.av_writedata (hex_2_s1_writedata), // .writedata
.av_chipselect (hex_2_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex_3_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex_3_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex_3_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex_3_s1_agent_m0_read), // .read
.uav_write (hex_3_s1_agent_m0_write), // .write
.uav_waitrequest (hex_3_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex_3_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex_3_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex_3_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex_3_s1_agent_m0_writedata), // .writedata
.uav_lock (hex_3_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex_3_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex_3_s1_address), // avalon_anti_slave_0.address
.av_write (hex_3_s1_write), // .write
.av_readdata (hex_3_s1_readdata), // .readdata
.av_writedata (hex_3_s1_writedata), // .writedata
.av_chipselect (hex_3_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex_4_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex_4_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex_4_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex_4_s1_agent_m0_read), // .read
.uav_write (hex_4_s1_agent_m0_write), // .write
.uav_waitrequest (hex_4_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex_4_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex_4_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex_4_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex_4_s1_agent_m0_writedata), // .writedata
.uav_lock (hex_4_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex_4_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex_4_s1_address), // avalon_anti_slave_0.address
.av_write (hex_4_s1_write), // .write
.av_readdata (hex_4_s1_readdata), // .readdata
.av_writedata (hex_4_s1_writedata), // .writedata
.av_chipselect (hex_4_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex_5_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex_5_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex_5_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex_5_s1_agent_m0_read), // .read
.uav_write (hex_5_s1_agent_m0_write), // .write
.uav_waitrequest (hex_5_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex_5_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex_5_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex_5_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex_5_s1_agent_m0_writedata), // .writedata
.uav_lock (hex_5_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex_5_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex_5_s1_address), // avalon_anti_slave_0.address
.av_write (hex_5_s1_write), // .write
.av_readdata (hex_5_s1_readdata), // .readdata
.av_writedata (hex_5_s1_writedata), // .writedata
.av_chipselect (hex_5_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_a_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_a_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_a_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_a_s1_agent_m0_read), // .read
.uav_write (alu_a_s1_agent_m0_write), // .write
.uav_waitrequest (alu_a_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_a_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_a_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_a_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_a_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_a_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_a_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_a_s1_address), // avalon_anti_slave_0.address
.av_write (alu_a_s1_write), // .write
.av_readdata (alu_a_s1_readdata), // .readdata
.av_writedata (alu_a_s1_writedata), // .writedata
.av_chipselect (alu_a_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_b_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_b_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_b_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_b_s1_agent_m0_read), // .read
.uav_write (alu_b_s1_agent_m0_write), // .write
.uav_waitrequest (alu_b_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_b_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_b_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_b_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_b_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_b_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_b_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_b_s1_address), // avalon_anti_slave_0.address
.av_write (alu_b_s1_write), // .write
.av_readdata (alu_b_s1_readdata), // .readdata
.av_writedata (alu_b_s1_writedata), // .writedata
.av_chipselect (alu_b_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_control_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_control_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_control_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_control_s1_agent_m0_read), // .read
.uav_write (alu_control_s1_agent_m0_write), // .write
.uav_waitrequest (alu_control_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_control_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_control_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_control_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_control_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_control_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_control_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_control_s1_address), // avalon_anti_slave_0.address
.av_write (alu_control_s1_write), // .write
.av_readdata (alu_control_s1_readdata), // .readdata
.av_writedata (alu_control_s1_writedata), // .writedata
.av_chipselect (alu_control_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_out_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_out_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_out_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_out_s1_agent_m0_read), // .read
.uav_write (alu_out_s1_agent_m0_write), // .write
.uav_waitrequest (alu_out_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_out_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_out_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_out_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_out_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_out_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_out_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_out_s1_address), // avalon_anti_slave_0.address
.av_readdata (alu_out_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_zero_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_zero_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_zero_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_zero_s1_agent_m0_read), // .read
.uav_write (alu_zero_s1_agent_m0_write), // .write
.uav_waitrequest (alu_zero_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_zero_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_zero_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_zero_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_zero_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_zero_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_zero_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_zero_s1_address), // avalon_anti_slave_0.address
.av_readdata (alu_zero_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_overflow_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_overflow_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_overflow_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_overflow_s1_agent_m0_read), // .read
.uav_write (alu_overflow_s1_agent_m0_write), // .write
.uav_waitrequest (alu_overflow_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_overflow_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_overflow_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_overflow_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_overflow_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_overflow_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_overflow_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_overflow_s1_address), // avalon_anti_slave_0.address
.av_readdata (alu_overflow_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_carry_out_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_carry_out_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_carry_out_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_carry_out_s1_agent_m0_read), // .read
.uav_write (alu_carry_out_s1_agent_m0_write), // .write
.uav_waitrequest (alu_carry_out_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_carry_out_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_carry_out_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_carry_out_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_carry_out_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_carry_out_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_carry_out_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_carry_out_s1_address), // avalon_anti_slave_0.address
.av_readdata (alu_carry_out_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_negative_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_negative_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_negative_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_negative_s1_agent_m0_read), // .read
.uav_write (alu_negative_s1_agent_m0_write), // .write
.uav_waitrequest (alu_negative_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_negative_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_negative_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_negative_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_negative_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_negative_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_negative_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_negative_s1_address), // avalon_anti_slave_0.address
.av_readdata (alu_negative_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) keys_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (keys_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (keys_s1_agent_m0_burstcount), // .burstcount
.uav_read (keys_s1_agent_m0_read), // .read
.uav_write (keys_s1_agent_m0_write), // .write
.uav_waitrequest (keys_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (keys_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (keys_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (keys_s1_agent_m0_readdata), // .readdata
.uav_writedata (keys_s1_agent_m0_writedata), // .writedata
.uav_lock (keys_s1_agent_m0_lock), // .lock
.uav_debugaccess (keys_s1_agent_m0_debugaccess), // .debugaccess
.av_address (keys_s1_address), // avalon_anti_slave_0.address
.av_readdata (keys_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_QOS_H (75),
.PKT_QOS_L (75),
.PKT_DATA_SIDEBAND_H (73),
.PKT_DATA_SIDEBAND_L (73),
.PKT_ADDR_SIDEBAND_H (72),
.PKT_ADDR_SIDEBAND_L (72),
.PKT_BURST_TYPE_H (71),
.PKT_BURST_TYPE_L (70),
.PKT_CACHE_H (93),
.PKT_CACHE_L (90),
.PKT_THREAD_ID_H (86),
.PKT_THREAD_ID_L (86),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_EXCLUSIVE (60),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.ST_DATA_W (99),
.ST_CHANNEL_W (32),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_0_data_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_qsys_0_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_qsys_0_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_qsys_0_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_qsys_0_data_master_agent_cp_valid), // cp.valid
.cp_data (nios2_qsys_0_data_master_agent_cp_data), // .data
.cp_startofpacket (nios2_qsys_0_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_qsys_0_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_qsys_0_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_QOS_H (75),
.PKT_QOS_L (75),
.PKT_DATA_SIDEBAND_H (73),
.PKT_DATA_SIDEBAND_L (73),
.PKT_ADDR_SIDEBAND_H (72),
.PKT_ADDR_SIDEBAND_L (72),
.PKT_BURST_TYPE_H (71),
.PKT_BURST_TYPE_L (70),
.PKT_CACHE_H (93),
.PKT_CACHE_L (90),
.PKT_THREAD_ID_H (86),
.PKT_THREAD_ID_L (86),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_EXCLUSIVE (60),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.ST_DATA_W (99),
.ST_CHANNEL_W (32),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_0_instruction_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_qsys_0_instruction_master_agent_cp_valid), // cp.valid
.cp_data (nios2_qsys_0_instruction_master_agent_cp_data), // .data
.cp_startofpacket (nios2_qsys_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_qsys_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_qsys_0_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) jtag_uart_0_avalon_jtag_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_uart_0_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_0_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_0_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_0_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_0_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_0_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_0_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_0_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_0_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_0_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_0_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_0_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_uart_0_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_uart_0_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_0_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_0_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_0_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_uart_0_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_uart_0_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_0_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_0_debug_mem_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (nios2_qsys_0_debug_mem_slave_agent_m0_address), // m0.address
.m0_burstcount (nios2_qsys_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios2_qsys_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios2_qsys_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios2_qsys_0_debug_mem_slave_agent_m0_lock), // .lock
.m0_readdata (nios2_qsys_0_debug_mem_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios2_qsys_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios2_qsys_0_debug_mem_slave_agent_m0_read), // .read
.m0_waitrequest (nios2_qsys_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios2_qsys_0_debug_mem_slave_agent_m0_writedata), // .writedata
.m0_write (nios2_qsys_0_debug_mem_slave_agent_m0_write), // .write
.rp_endofpacket (nios2_qsys_0_debug_mem_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios2_qsys_0_debug_mem_slave_agent_rp_ready), // .ready
.rp_valid (nios2_qsys_0_debug_mem_slave_agent_rp_valid), // .valid
.rp_data (nios2_qsys_0_debug_mem_slave_agent_rp_data), // .data
.rp_startofpacket (nios2_qsys_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios2_qsys_0_debug_mem_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios2_qsys_0_debug_mem_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios2_qsys_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios2_qsys_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios2_qsys_0_debug_mem_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios2_qsys_0_debug_mem_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (nios2_qsys_0_debug_mem_slave_agent_rf_source_data), // in.data
.in_valid (nios2_qsys_0_debug_mem_slave_agent_rf_source_valid), // .valid
.in_ready (nios2_qsys_0_debug_mem_slave_agent_rf_source_ready), // .ready
.in_startofpacket (nios2_qsys_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios2_qsys_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) onchip_memory2_0_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_memory2_0_s1_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_0_s1_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_0_s1_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_0_s1_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.rp_data (onchip_memory2_0_s1_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_0_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_0_s1_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) leds_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (leds_s1_agent_m0_address), // m0.address
.m0_burstcount (leds_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (leds_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (leds_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (leds_s1_agent_m0_lock), // .lock
.m0_readdata (leds_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (leds_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (leds_s1_agent_m0_read), // .read
.m0_waitrequest (leds_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (leds_s1_agent_m0_writedata), // .writedata
.m0_write (leds_s1_agent_m0_write), // .write
.rp_endofpacket (leds_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (leds_s1_agent_rp_ready), // .ready
.rp_valid (leds_s1_agent_rp_valid), // .valid
.rp_data (leds_s1_agent_rp_data), // .data
.rp_startofpacket (leds_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (leds_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (leds_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (leds_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (leds_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (leds_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (leds_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (leds_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (leds_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (leds_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (leds_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (leds_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (leds_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (leds_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (leds_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (leds_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (leds_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) leds_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (leds_s1_agent_rf_source_data), // in.data
.in_valid (leds_s1_agent_rf_source_valid), // .valid
.in_ready (leds_s1_agent_rf_source_ready), // .ready
.in_startofpacket (leds_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (leds_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (leds_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (leds_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (leds_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (leds_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (leds_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) switches_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (switches_s1_agent_m0_address), // m0.address
.m0_burstcount (switches_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (switches_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (switches_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (switches_s1_agent_m0_lock), // .lock
.m0_readdata (switches_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (switches_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (switches_s1_agent_m0_read), // .read
.m0_waitrequest (switches_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (switches_s1_agent_m0_writedata), // .writedata
.m0_write (switches_s1_agent_m0_write), // .write
.rp_endofpacket (switches_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (switches_s1_agent_rp_ready), // .ready
.rp_valid (switches_s1_agent_rp_valid), // .valid
.rp_data (switches_s1_agent_rp_data), // .data
.rp_startofpacket (switches_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (switches_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (switches_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (switches_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (switches_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (switches_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (switches_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (switches_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (switches_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (switches_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (switches_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (switches_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (switches_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (switches_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (switches_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (switches_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (switches_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) switches_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (switches_s1_agent_rf_source_data), // in.data
.in_valid (switches_s1_agent_rf_source_valid), // .valid
.in_ready (switches_s1_agent_rf_source_ready), // .ready
.in_startofpacket (switches_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (switches_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (switches_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (switches_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (switches_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (switches_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (switches_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sram_data_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sram_data_s1_agent_m0_address), // m0.address
.m0_burstcount (sram_data_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_data_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_data_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_data_s1_agent_m0_lock), // .lock
.m0_readdata (sram_data_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_data_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_data_s1_agent_m0_read), // .read
.m0_waitrequest (sram_data_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_data_s1_agent_m0_writedata), // .writedata
.m0_write (sram_data_s1_agent_m0_write), // .write
.rp_endofpacket (sram_data_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_data_s1_agent_rp_ready), // .ready
.rp_valid (sram_data_s1_agent_rp_valid), // .valid
.rp_data (sram_data_s1_agent_rp_data), // .data
.rp_startofpacket (sram_data_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (sram_data_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_data_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_data_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_data_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_data_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_data_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_data_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_data_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_data_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_data_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sram_data_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sram_data_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sram_data_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sram_data_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_data_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_data_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_data_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_data_s1_agent_rf_source_data), // in.data
.in_valid (sram_data_s1_agent_rf_source_valid), // .valid
.in_ready (sram_data_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sram_data_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_data_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_data_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_data_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_data_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_data_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_data_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sram_addr_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sram_addr_s1_agent_m0_address), // m0.address
.m0_burstcount (sram_addr_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_addr_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_addr_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_addr_s1_agent_m0_lock), // .lock
.m0_readdata (sram_addr_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_addr_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_addr_s1_agent_m0_read), // .read
.m0_waitrequest (sram_addr_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_addr_s1_agent_m0_writedata), // .writedata
.m0_write (sram_addr_s1_agent_m0_write), // .write
.rp_endofpacket (sram_addr_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_addr_s1_agent_rp_ready), // .ready
.rp_valid (sram_addr_s1_agent_rp_valid), // .valid
.rp_data (sram_addr_s1_agent_rp_data), // .data
.rp_startofpacket (sram_addr_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_006_src_ready), // cp.ready
.cp_valid (cmd_mux_006_src_valid), // .valid
.cp_data (cmd_mux_006_src_data), // .data
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_006_src_channel), // .channel
.rf_sink_ready (sram_addr_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_addr_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_addr_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_addr_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_addr_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_addr_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_addr_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_addr_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_addr_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_addr_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sram_addr_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sram_addr_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sram_addr_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sram_addr_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_addr_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_addr_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_addr_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_addr_s1_agent_rf_source_data), // in.data
.in_valid (sram_addr_s1_agent_rf_source_valid), // .valid
.in_ready (sram_addr_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sram_addr_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_addr_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_addr_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_addr_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_addr_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_addr_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_addr_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sram_read_write_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sram_read_write_s1_agent_m0_address), // m0.address
.m0_burstcount (sram_read_write_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_read_write_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_read_write_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_read_write_s1_agent_m0_lock), // .lock
.m0_readdata (sram_read_write_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_read_write_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_read_write_s1_agent_m0_read), // .read
.m0_waitrequest (sram_read_write_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_read_write_s1_agent_m0_writedata), // .writedata
.m0_write (sram_read_write_s1_agent_m0_write), // .write
.rp_endofpacket (sram_read_write_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_read_write_s1_agent_rp_ready), // .ready
.rp_valid (sram_read_write_s1_agent_rp_valid), // .valid
.rp_data (sram_read_write_s1_agent_rp_data), // .data
.rp_startofpacket (sram_read_write_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_007_src_ready), // cp.ready
.cp_valid (cmd_mux_007_src_valid), // .valid
.cp_data (cmd_mux_007_src_data), // .data
.cp_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_007_src_channel), // .channel
.rf_sink_ready (sram_read_write_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_read_write_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_read_write_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_read_write_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_read_write_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_read_write_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_read_write_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_read_write_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_read_write_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_read_write_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sram_read_write_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sram_read_write_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sram_read_write_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sram_read_write_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_read_write_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_read_write_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_read_write_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_read_write_s1_agent_rf_source_data), // in.data
.in_valid (sram_read_write_s1_agent_rf_source_valid), // .valid
.in_ready (sram_read_write_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sram_read_write_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_read_write_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_read_write_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_read_write_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_read_write_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_read_write_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_read_write_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sram_cs_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sram_cs_s1_agent_m0_address), // m0.address
.m0_burstcount (sram_cs_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_cs_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_cs_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_cs_s1_agent_m0_lock), // .lock
.m0_readdata (sram_cs_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_cs_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_cs_s1_agent_m0_read), // .read
.m0_waitrequest (sram_cs_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_cs_s1_agent_m0_writedata), // .writedata
.m0_write (sram_cs_s1_agent_m0_write), // .write
.rp_endofpacket (sram_cs_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_cs_s1_agent_rp_ready), // .ready
.rp_valid (sram_cs_s1_agent_rp_valid), // .valid
.rp_data (sram_cs_s1_agent_rp_data), // .data
.rp_startofpacket (sram_cs_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_008_src_ready), // cp.ready
.cp_valid (cmd_mux_008_src_valid), // .valid
.cp_data (cmd_mux_008_src_data), // .data
.cp_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_008_src_channel), // .channel
.rf_sink_ready (sram_cs_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_cs_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_cs_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_cs_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_cs_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_cs_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_cs_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_cs_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_cs_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_cs_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sram_cs_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sram_cs_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sram_cs_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sram_cs_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_cs_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_cs_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_cs_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_cs_s1_agent_rf_source_data), // in.data
.in_valid (sram_cs_s1_agent_rf_source_valid), // .valid
.in_ready (sram_cs_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sram_cs_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_cs_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_cs_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_cs_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_cs_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_cs_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_cs_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sram_oe_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sram_oe_s1_agent_m0_address), // m0.address
.m0_burstcount (sram_oe_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_oe_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_oe_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_oe_s1_agent_m0_lock), // .lock
.m0_readdata (sram_oe_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_oe_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_oe_s1_agent_m0_read), // .read
.m0_waitrequest (sram_oe_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_oe_s1_agent_m0_writedata), // .writedata
.m0_write (sram_oe_s1_agent_m0_write), // .write
.rp_endofpacket (sram_oe_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_oe_s1_agent_rp_ready), // .ready
.rp_valid (sram_oe_s1_agent_rp_valid), // .valid
.rp_data (sram_oe_s1_agent_rp_data), // .data
.rp_startofpacket (sram_oe_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_009_src_ready), // cp.ready
.cp_valid (cmd_mux_009_src_valid), // .valid
.cp_data (cmd_mux_009_src_data), // .data
.cp_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_009_src_channel), // .channel
.rf_sink_ready (sram_oe_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_oe_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_oe_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_oe_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_oe_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_oe_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_oe_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_oe_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_oe_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_oe_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sram_oe_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sram_oe_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sram_oe_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sram_oe_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_oe_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_oe_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_oe_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_oe_s1_agent_rf_source_data), // in.data
.in_valid (sram_oe_s1_agent_rf_source_valid), // .valid
.in_ready (sram_oe_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sram_oe_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_oe_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_oe_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_oe_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_oe_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_oe_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_oe_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_data_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_data_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_data_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_data_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_data_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_data_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_data_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_data_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_data_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_data_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_data_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_data_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_data_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_data_s1_agent_rp_ready), // .ready
.rp_valid (regfile_data_s1_agent_rp_valid), // .valid
.rp_data (regfile_data_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_data_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_010_src_ready), // cp.ready
.cp_valid (cmd_mux_010_src_valid), // .valid
.cp_data (cmd_mux_010_src_data), // .data
.cp_startofpacket (cmd_mux_010_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_010_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_010_src_channel), // .channel
.rf_sink_ready (regfile_data_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_data_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_data_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_data_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_data_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_data_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_data_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_data_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_data_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_data_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_data_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_data_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_data_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_data_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_data_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_data_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_data_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_data_s1_agent_rf_source_data), // in.data
.in_valid (regfile_data_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_data_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_data_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_data_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_data_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_data_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_data_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_data_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_data_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_reg1_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_reg1_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_reg1_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_reg1_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_reg1_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_reg1_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_reg1_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_reg1_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_reg1_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_reg1_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_reg1_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_reg1_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_reg1_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_reg1_s1_agent_rp_ready), // .ready
.rp_valid (regfile_reg1_s1_agent_rp_valid), // .valid
.rp_data (regfile_reg1_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_reg1_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_011_src_ready), // cp.ready
.cp_valid (cmd_mux_011_src_valid), // .valid
.cp_data (cmd_mux_011_src_data), // .data
.cp_startofpacket (cmd_mux_011_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_011_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_011_src_channel), // .channel
.rf_sink_ready (regfile_reg1_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_reg1_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_reg1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_reg1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_reg1_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_reg1_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_reg1_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_reg1_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_reg1_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_reg1_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_reg1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_reg1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_reg1_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_reg1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_reg1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_reg1_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_reg1_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_reg1_s1_agent_rf_source_data), // in.data
.in_valid (regfile_reg1_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_reg1_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_reg1_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_reg1_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_reg1_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_reg1_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_reg1_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_reg1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_reg1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_reg2_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_reg2_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_reg2_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_reg2_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_reg2_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_reg2_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_reg2_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_reg2_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_reg2_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_reg2_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_reg2_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_reg2_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_reg2_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_reg2_s1_agent_rp_ready), // .ready
.rp_valid (regfile_reg2_s1_agent_rp_valid), // .valid
.rp_data (regfile_reg2_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_reg2_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_012_src_ready), // cp.ready
.cp_valid (cmd_mux_012_src_valid), // .valid
.cp_data (cmd_mux_012_src_data), // .data
.cp_startofpacket (cmd_mux_012_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_012_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_012_src_channel), // .channel
.rf_sink_ready (regfile_reg2_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_reg2_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_reg2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_reg2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_reg2_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_reg2_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_reg2_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_reg2_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_reg2_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_reg2_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_reg2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_reg2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_reg2_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_reg2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_reg2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_reg2_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_reg2_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_reg2_s1_agent_rf_source_data), // in.data
.in_valid (regfile_reg2_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_reg2_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_reg2_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_reg2_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_reg2_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_reg2_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_reg2_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_reg2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_reg2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_r1sel_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_r1sel_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_r1sel_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_r1sel_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_r1sel_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_r1sel_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_r1sel_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_r1sel_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_r1sel_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_r1sel_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_r1sel_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_r1sel_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_r1sel_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_r1sel_s1_agent_rp_ready), // .ready
.rp_valid (regfile_r1sel_s1_agent_rp_valid), // .valid
.rp_data (regfile_r1sel_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_r1sel_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_013_src_ready), // cp.ready
.cp_valid (cmd_mux_013_src_valid), // .valid
.cp_data (cmd_mux_013_src_data), // .data
.cp_startofpacket (cmd_mux_013_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_013_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_013_src_channel), // .channel
.rf_sink_ready (regfile_r1sel_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_r1sel_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_r1sel_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_r1sel_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_r1sel_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_r1sel_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_r1sel_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_r1sel_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_r1sel_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_r1sel_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_r1sel_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_r1sel_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_r1sel_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_r1sel_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_r1sel_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_r1sel_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_r1sel_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_r1sel_s1_agent_rf_source_data), // in.data
.in_valid (regfile_r1sel_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_r1sel_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_r1sel_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_r1sel_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_r1sel_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_r1sel_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_r1sel_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_r1sel_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_r1sel_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_r2sel_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_r2sel_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_r2sel_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_r2sel_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_r2sel_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_r2sel_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_r2sel_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_r2sel_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_r2sel_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_r2sel_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_r2sel_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_r2sel_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_r2sel_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_r2sel_s1_agent_rp_ready), // .ready
.rp_valid (regfile_r2sel_s1_agent_rp_valid), // .valid
.rp_data (regfile_r2sel_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_r2sel_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_014_src_ready), // cp.ready
.cp_valid (cmd_mux_014_src_valid), // .valid
.cp_data (cmd_mux_014_src_data), // .data
.cp_startofpacket (cmd_mux_014_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_014_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_014_src_channel), // .channel
.rf_sink_ready (regfile_r2sel_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_r2sel_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_r2sel_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_r2sel_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_r2sel_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_r2sel_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_r2sel_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_r2sel_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_r2sel_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_r2sel_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_r2sel_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_r2sel_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_r2sel_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_r2sel_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_r2sel_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_r2sel_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_r2sel_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_r2sel_s1_agent_rf_source_data), // in.data
.in_valid (regfile_r2sel_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_r2sel_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_r2sel_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_r2sel_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_r2sel_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_r2sel_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_r2sel_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_r2sel_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_r2sel_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_wsel_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_wsel_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_wsel_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_wsel_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_wsel_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_wsel_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_wsel_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_wsel_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_wsel_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_wsel_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_wsel_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_wsel_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_wsel_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_wsel_s1_agent_rp_ready), // .ready
.rp_valid (regfile_wsel_s1_agent_rp_valid), // .valid
.rp_data (regfile_wsel_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_wsel_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_015_src_ready), // cp.ready
.cp_valid (cmd_mux_015_src_valid), // .valid
.cp_data (cmd_mux_015_src_data), // .data
.cp_startofpacket (cmd_mux_015_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_015_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_015_src_channel), // .channel
.rf_sink_ready (regfile_wsel_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_wsel_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_wsel_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_wsel_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_wsel_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_wsel_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_wsel_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_wsel_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_wsel_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_wsel_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_wsel_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_wsel_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_wsel_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_wsel_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_wsel_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_wsel_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_wsel_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_wsel_s1_agent_rf_source_data), // in.data
.in_valid (regfile_wsel_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_wsel_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_wsel_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_wsel_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_wsel_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_wsel_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_wsel_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_wsel_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_wsel_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_we_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_we_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_we_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_we_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_we_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_we_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_we_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_we_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_we_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_we_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_we_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_we_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_we_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_we_s1_agent_rp_ready), // .ready
.rp_valid (regfile_we_s1_agent_rp_valid), // .valid
.rp_data (regfile_we_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_we_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_016_src_ready), // cp.ready
.cp_valid (cmd_mux_016_src_valid), // .valid
.cp_data (cmd_mux_016_src_data), // .data
.cp_startofpacket (cmd_mux_016_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_016_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_016_src_channel), // .channel
.rf_sink_ready (regfile_we_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_we_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_we_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_we_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_we_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_we_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_we_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_we_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_we_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_we_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_we_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_we_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_we_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_we_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_we_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_we_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_we_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_we_s1_agent_rf_source_data), // in.data
.in_valid (regfile_we_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_we_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_we_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_we_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_we_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_we_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_we_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_we_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_we_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hex_0_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex_0_s1_agent_m0_address), // m0.address
.m0_burstcount (hex_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex_0_s1_agent_m0_lock), // .lock
.m0_readdata (hex_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex_0_s1_agent_m0_read), // .read
.m0_waitrequest (hex_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex_0_s1_agent_m0_writedata), // .writedata
.m0_write (hex_0_s1_agent_m0_write), // .write
.rp_endofpacket (hex_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex_0_s1_agent_rp_ready), // .ready
.rp_valid (hex_0_s1_agent_rp_valid), // .valid
.rp_data (hex_0_s1_agent_rp_data), // .data
.rp_startofpacket (hex_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_017_src_ready), // cp.ready
.cp_valid (cmd_mux_017_src_valid), // .valid
.cp_data (cmd_mux_017_src_data), // .data
.cp_startofpacket (cmd_mux_017_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_017_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_017_src_channel), // .channel
.rf_sink_ready (hex_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hex_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hex_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hex_0_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hex_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex_0_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex_0_s1_agent_rf_source_data), // in.data
.in_valid (hex_0_s1_agent_rf_source_valid), // .valid
.in_ready (hex_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hex_1_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex_1_s1_agent_m0_address), // m0.address
.m0_burstcount (hex_1_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex_1_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex_1_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex_1_s1_agent_m0_lock), // .lock
.m0_readdata (hex_1_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex_1_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex_1_s1_agent_m0_read), // .read
.m0_waitrequest (hex_1_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex_1_s1_agent_m0_writedata), // .writedata
.m0_write (hex_1_s1_agent_m0_write), // .write
.rp_endofpacket (hex_1_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex_1_s1_agent_rp_ready), // .ready
.rp_valid (hex_1_s1_agent_rp_valid), // .valid
.rp_data (hex_1_s1_agent_rp_data), // .data
.rp_startofpacket (hex_1_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_018_src_ready), // cp.ready
.cp_valid (cmd_mux_018_src_valid), // .valid
.cp_data (cmd_mux_018_src_data), // .data
.cp_startofpacket (cmd_mux_018_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_018_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_018_src_channel), // .channel
.rf_sink_ready (hex_1_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex_1_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex_1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex_1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex_1_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex_1_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex_1_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex_1_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex_1_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex_1_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hex_1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hex_1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hex_1_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hex_1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex_1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex_1_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex_1_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex_1_s1_agent_rf_source_data), // in.data
.in_valid (hex_1_s1_agent_rf_source_valid), // .valid
.in_ready (hex_1_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex_1_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex_1_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex_1_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex_1_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex_1_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex_1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex_1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hex_2_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex_2_s1_agent_m0_address), // m0.address
.m0_burstcount (hex_2_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex_2_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex_2_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex_2_s1_agent_m0_lock), // .lock
.m0_readdata (hex_2_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex_2_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex_2_s1_agent_m0_read), // .read
.m0_waitrequest (hex_2_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex_2_s1_agent_m0_writedata), // .writedata
.m0_write (hex_2_s1_agent_m0_write), // .write
.rp_endofpacket (hex_2_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex_2_s1_agent_rp_ready), // .ready
.rp_valid (hex_2_s1_agent_rp_valid), // .valid
.rp_data (hex_2_s1_agent_rp_data), // .data
.rp_startofpacket (hex_2_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_019_src_ready), // cp.ready
.cp_valid (cmd_mux_019_src_valid), // .valid
.cp_data (cmd_mux_019_src_data), // .data
.cp_startofpacket (cmd_mux_019_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_019_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_019_src_channel), // .channel
.rf_sink_ready (hex_2_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex_2_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex_2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex_2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex_2_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex_2_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex_2_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex_2_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex_2_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex_2_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hex_2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hex_2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hex_2_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hex_2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex_2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex_2_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex_2_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex_2_s1_agent_rf_source_data), // in.data
.in_valid (hex_2_s1_agent_rf_source_valid), // .valid
.in_ready (hex_2_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex_2_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex_2_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex_2_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex_2_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex_2_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex_2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex_2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hex_3_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex_3_s1_agent_m0_address), // m0.address
.m0_burstcount (hex_3_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex_3_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex_3_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex_3_s1_agent_m0_lock), // .lock
.m0_readdata (hex_3_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex_3_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex_3_s1_agent_m0_read), // .read
.m0_waitrequest (hex_3_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex_3_s1_agent_m0_writedata), // .writedata
.m0_write (hex_3_s1_agent_m0_write), // .write
.rp_endofpacket (hex_3_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex_3_s1_agent_rp_ready), // .ready
.rp_valid (hex_3_s1_agent_rp_valid), // .valid
.rp_data (hex_3_s1_agent_rp_data), // .data
.rp_startofpacket (hex_3_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_020_src_ready), // cp.ready
.cp_valid (cmd_mux_020_src_valid), // .valid
.cp_data (cmd_mux_020_src_data), // .data
.cp_startofpacket (cmd_mux_020_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_020_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_020_src_channel), // .channel
.rf_sink_ready (hex_3_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex_3_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex_3_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex_3_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex_3_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex_3_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex_3_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex_3_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex_3_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex_3_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hex_3_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hex_3_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hex_3_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hex_3_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex_3_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex_3_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex_3_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex_3_s1_agent_rf_source_data), // in.data
.in_valid (hex_3_s1_agent_rf_source_valid), // .valid
.in_ready (hex_3_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex_3_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex_3_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex_3_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex_3_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex_3_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex_3_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex_3_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hex_4_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex_4_s1_agent_m0_address), // m0.address
.m0_burstcount (hex_4_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex_4_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex_4_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex_4_s1_agent_m0_lock), // .lock
.m0_readdata (hex_4_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex_4_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex_4_s1_agent_m0_read), // .read
.m0_waitrequest (hex_4_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex_4_s1_agent_m0_writedata), // .writedata
.m0_write (hex_4_s1_agent_m0_write), // .write
.rp_endofpacket (hex_4_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex_4_s1_agent_rp_ready), // .ready
.rp_valid (hex_4_s1_agent_rp_valid), // .valid
.rp_data (hex_4_s1_agent_rp_data), // .data
.rp_startofpacket (hex_4_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_021_src_ready), // cp.ready
.cp_valid (cmd_mux_021_src_valid), // .valid
.cp_data (cmd_mux_021_src_data), // .data
.cp_startofpacket (cmd_mux_021_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_021_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_021_src_channel), // .channel
.rf_sink_ready (hex_4_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex_4_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex_4_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex_4_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex_4_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex_4_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex_4_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex_4_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex_4_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex_4_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hex_4_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hex_4_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hex_4_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hex_4_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex_4_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex_4_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex_4_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex_4_s1_agent_rf_source_data), // in.data
.in_valid (hex_4_s1_agent_rf_source_valid), // .valid
.in_ready (hex_4_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex_4_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex_4_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex_4_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex_4_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex_4_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex_4_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex_4_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hex_5_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex_5_s1_agent_m0_address), // m0.address
.m0_burstcount (hex_5_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex_5_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex_5_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex_5_s1_agent_m0_lock), // .lock
.m0_readdata (hex_5_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex_5_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex_5_s1_agent_m0_read), // .read
.m0_waitrequest (hex_5_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex_5_s1_agent_m0_writedata), // .writedata
.m0_write (hex_5_s1_agent_m0_write), // .write
.rp_endofpacket (hex_5_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex_5_s1_agent_rp_ready), // .ready
.rp_valid (hex_5_s1_agent_rp_valid), // .valid
.rp_data (hex_5_s1_agent_rp_data), // .data
.rp_startofpacket (hex_5_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_022_src_ready), // cp.ready
.cp_valid (cmd_mux_022_src_valid), // .valid
.cp_data (cmd_mux_022_src_data), // .data
.cp_startofpacket (cmd_mux_022_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_022_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_022_src_channel), // .channel
.rf_sink_ready (hex_5_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex_5_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex_5_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex_5_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex_5_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex_5_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex_5_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex_5_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex_5_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex_5_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hex_5_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hex_5_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hex_5_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hex_5_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex_5_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex_5_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex_5_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex_5_s1_agent_rf_source_data), // in.data
.in_valid (hex_5_s1_agent_rf_source_valid), // .valid
.in_ready (hex_5_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex_5_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex_5_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex_5_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex_5_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex_5_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex_5_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex_5_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_a_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_a_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_a_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_a_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_a_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_a_s1_agent_m0_lock), // .lock
.m0_readdata (alu_a_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_a_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_a_s1_agent_m0_read), // .read
.m0_waitrequest (alu_a_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_a_s1_agent_m0_writedata), // .writedata
.m0_write (alu_a_s1_agent_m0_write), // .write
.rp_endofpacket (alu_a_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_a_s1_agent_rp_ready), // .ready
.rp_valid (alu_a_s1_agent_rp_valid), // .valid
.rp_data (alu_a_s1_agent_rp_data), // .data
.rp_startofpacket (alu_a_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_023_src_ready), // cp.ready
.cp_valid (cmd_mux_023_src_valid), // .valid
.cp_data (cmd_mux_023_src_data), // .data
.cp_startofpacket (cmd_mux_023_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_023_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_023_src_channel), // .channel
.rf_sink_ready (alu_a_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_a_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_a_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_a_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_a_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_a_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_a_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_a_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_a_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_a_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_a_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_a_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_a_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_a_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_a_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_a_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_a_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_a_s1_agent_rf_source_data), // in.data
.in_valid (alu_a_s1_agent_rf_source_valid), // .valid
.in_ready (alu_a_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_a_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_a_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_a_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_a_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_a_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_a_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_a_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_b_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_b_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_b_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_b_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_b_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_b_s1_agent_m0_lock), // .lock
.m0_readdata (alu_b_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_b_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_b_s1_agent_m0_read), // .read
.m0_waitrequest (alu_b_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_b_s1_agent_m0_writedata), // .writedata
.m0_write (alu_b_s1_agent_m0_write), // .write
.rp_endofpacket (alu_b_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_b_s1_agent_rp_ready), // .ready
.rp_valid (alu_b_s1_agent_rp_valid), // .valid
.rp_data (alu_b_s1_agent_rp_data), // .data
.rp_startofpacket (alu_b_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_024_src_ready), // cp.ready
.cp_valid (cmd_mux_024_src_valid), // .valid
.cp_data (cmd_mux_024_src_data), // .data
.cp_startofpacket (cmd_mux_024_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_024_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_024_src_channel), // .channel
.rf_sink_ready (alu_b_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_b_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_b_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_b_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_b_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_b_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_b_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_b_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_b_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_b_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_b_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_b_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_b_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_b_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_b_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_b_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_b_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_b_s1_agent_rf_source_data), // in.data
.in_valid (alu_b_s1_agent_rf_source_valid), // .valid
.in_ready (alu_b_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_b_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_b_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_b_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_b_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_b_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_b_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_b_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_control_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_control_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_control_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_control_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_control_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_control_s1_agent_m0_lock), // .lock
.m0_readdata (alu_control_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_control_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_control_s1_agent_m0_read), // .read
.m0_waitrequest (alu_control_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_control_s1_agent_m0_writedata), // .writedata
.m0_write (alu_control_s1_agent_m0_write), // .write
.rp_endofpacket (alu_control_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_control_s1_agent_rp_ready), // .ready
.rp_valid (alu_control_s1_agent_rp_valid), // .valid
.rp_data (alu_control_s1_agent_rp_data), // .data
.rp_startofpacket (alu_control_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_025_src_ready), // cp.ready
.cp_valid (cmd_mux_025_src_valid), // .valid
.cp_data (cmd_mux_025_src_data), // .data
.cp_startofpacket (cmd_mux_025_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_025_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_025_src_channel), // .channel
.rf_sink_ready (alu_control_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_control_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_control_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_control_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_control_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_control_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_control_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_control_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_control_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_control_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_control_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_control_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_control_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_control_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_control_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_control_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_control_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_control_s1_agent_rf_source_data), // in.data
.in_valid (alu_control_s1_agent_rf_source_valid), // .valid
.in_ready (alu_control_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_control_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_control_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_control_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_control_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_control_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_control_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_control_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_out_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_out_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_out_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_out_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_out_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_out_s1_agent_m0_lock), // .lock
.m0_readdata (alu_out_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_out_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_out_s1_agent_m0_read), // .read
.m0_waitrequest (alu_out_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_out_s1_agent_m0_writedata), // .writedata
.m0_write (alu_out_s1_agent_m0_write), // .write
.rp_endofpacket (alu_out_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_out_s1_agent_rp_ready), // .ready
.rp_valid (alu_out_s1_agent_rp_valid), // .valid
.rp_data (alu_out_s1_agent_rp_data), // .data
.rp_startofpacket (alu_out_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_026_src_ready), // cp.ready
.cp_valid (cmd_mux_026_src_valid), // .valid
.cp_data (cmd_mux_026_src_data), // .data
.cp_startofpacket (cmd_mux_026_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_026_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_026_src_channel), // .channel
.rf_sink_ready (alu_out_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_out_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_out_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_out_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_out_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_out_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_out_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_out_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_out_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_out_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_out_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_out_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_out_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_out_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_out_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_out_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_out_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_out_s1_agent_rf_source_data), // in.data
.in_valid (alu_out_s1_agent_rf_source_valid), // .valid
.in_ready (alu_out_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_out_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_out_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_out_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_out_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_out_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_out_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_out_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_zero_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_zero_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_zero_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_zero_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_zero_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_zero_s1_agent_m0_lock), // .lock
.m0_readdata (alu_zero_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_zero_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_zero_s1_agent_m0_read), // .read
.m0_waitrequest (alu_zero_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_zero_s1_agent_m0_writedata), // .writedata
.m0_write (alu_zero_s1_agent_m0_write), // .write
.rp_endofpacket (alu_zero_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_zero_s1_agent_rp_ready), // .ready
.rp_valid (alu_zero_s1_agent_rp_valid), // .valid
.rp_data (alu_zero_s1_agent_rp_data), // .data
.rp_startofpacket (alu_zero_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_027_src_ready), // cp.ready
.cp_valid (cmd_mux_027_src_valid), // .valid
.cp_data (cmd_mux_027_src_data), // .data
.cp_startofpacket (cmd_mux_027_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_027_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_027_src_channel), // .channel
.rf_sink_ready (alu_zero_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_zero_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_zero_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_zero_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_zero_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_zero_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_zero_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_zero_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_zero_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_zero_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_zero_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_zero_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_zero_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_zero_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_zero_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_zero_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_zero_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_zero_s1_agent_rf_source_data), // in.data
.in_valid (alu_zero_s1_agent_rf_source_valid), // .valid
.in_ready (alu_zero_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_zero_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_zero_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_zero_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_zero_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_zero_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_zero_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_zero_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_overflow_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_overflow_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_overflow_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_overflow_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_overflow_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_overflow_s1_agent_m0_lock), // .lock
.m0_readdata (alu_overflow_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_overflow_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_overflow_s1_agent_m0_read), // .read
.m0_waitrequest (alu_overflow_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_overflow_s1_agent_m0_writedata), // .writedata
.m0_write (alu_overflow_s1_agent_m0_write), // .write
.rp_endofpacket (alu_overflow_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_overflow_s1_agent_rp_ready), // .ready
.rp_valid (alu_overflow_s1_agent_rp_valid), // .valid
.rp_data (alu_overflow_s1_agent_rp_data), // .data
.rp_startofpacket (alu_overflow_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_028_src_ready), // cp.ready
.cp_valid (cmd_mux_028_src_valid), // .valid
.cp_data (cmd_mux_028_src_data), // .data
.cp_startofpacket (cmd_mux_028_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_028_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_028_src_channel), // .channel
.rf_sink_ready (alu_overflow_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_overflow_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_overflow_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_overflow_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_overflow_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_overflow_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_overflow_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_overflow_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_overflow_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_overflow_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_overflow_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_overflow_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_overflow_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_overflow_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_overflow_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_overflow_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_overflow_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_overflow_s1_agent_rf_source_data), // in.data
.in_valid (alu_overflow_s1_agent_rf_source_valid), // .valid
.in_ready (alu_overflow_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_overflow_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_overflow_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_overflow_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_overflow_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_overflow_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_overflow_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_overflow_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_carry_out_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_carry_out_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_carry_out_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_carry_out_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_carry_out_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_carry_out_s1_agent_m0_lock), // .lock
.m0_readdata (alu_carry_out_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_carry_out_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_carry_out_s1_agent_m0_read), // .read
.m0_waitrequest (alu_carry_out_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_carry_out_s1_agent_m0_writedata), // .writedata
.m0_write (alu_carry_out_s1_agent_m0_write), // .write
.rp_endofpacket (alu_carry_out_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_carry_out_s1_agent_rp_ready), // .ready
.rp_valid (alu_carry_out_s1_agent_rp_valid), // .valid
.rp_data (alu_carry_out_s1_agent_rp_data), // .data
.rp_startofpacket (alu_carry_out_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_029_src_ready), // cp.ready
.cp_valid (cmd_mux_029_src_valid), // .valid
.cp_data (cmd_mux_029_src_data), // .data
.cp_startofpacket (cmd_mux_029_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_029_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_029_src_channel), // .channel
.rf_sink_ready (alu_carry_out_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_carry_out_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_carry_out_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_carry_out_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_carry_out_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_carry_out_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_carry_out_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_carry_out_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_carry_out_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_carry_out_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_carry_out_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_carry_out_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_carry_out_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_carry_out_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_carry_out_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_carry_out_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_carry_out_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_carry_out_s1_agent_rf_source_data), // in.data
.in_valid (alu_carry_out_s1_agent_rf_source_valid), // .valid
.in_ready (alu_carry_out_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_carry_out_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_carry_out_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_carry_out_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_carry_out_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_carry_out_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_carry_out_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_carry_out_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_negative_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_negative_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_negative_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_negative_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_negative_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_negative_s1_agent_m0_lock), // .lock
.m0_readdata (alu_negative_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_negative_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_negative_s1_agent_m0_read), // .read
.m0_waitrequest (alu_negative_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_negative_s1_agent_m0_writedata), // .writedata
.m0_write (alu_negative_s1_agent_m0_write), // .write
.rp_endofpacket (alu_negative_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_negative_s1_agent_rp_ready), // .ready
.rp_valid (alu_negative_s1_agent_rp_valid), // .valid
.rp_data (alu_negative_s1_agent_rp_data), // .data
.rp_startofpacket (alu_negative_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_030_src_ready), // cp.ready
.cp_valid (cmd_mux_030_src_valid), // .valid
.cp_data (cmd_mux_030_src_data), // .data
.cp_startofpacket (cmd_mux_030_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_030_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_030_src_channel), // .channel
.rf_sink_ready (alu_negative_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_negative_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_negative_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_negative_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_negative_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_negative_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_negative_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_negative_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_negative_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_negative_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_negative_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_negative_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_negative_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_negative_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_negative_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_negative_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_negative_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_negative_s1_agent_rf_source_data), // in.data
.in_valid (alu_negative_s1_agent_rf_source_valid), // .valid
.in_ready (alu_negative_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_negative_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_negative_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_negative_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_negative_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_negative_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_negative_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_negative_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) keys_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (keys_s1_agent_m0_address), // m0.address
.m0_burstcount (keys_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (keys_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (keys_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (keys_s1_agent_m0_lock), // .lock
.m0_readdata (keys_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (keys_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (keys_s1_agent_m0_read), // .read
.m0_waitrequest (keys_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (keys_s1_agent_m0_writedata), // .writedata
.m0_write (keys_s1_agent_m0_write), // .write
.rp_endofpacket (keys_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (keys_s1_agent_rp_ready), // .ready
.rp_valid (keys_s1_agent_rp_valid), // .valid
.rp_data (keys_s1_agent_rp_data), // .data
.rp_startofpacket (keys_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_031_src_ready), // cp.ready
.cp_valid (cmd_mux_031_src_valid), // .valid
.cp_data (cmd_mux_031_src_data), // .data
.cp_startofpacket (cmd_mux_031_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_031_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_031_src_channel), // .channel
.rf_sink_ready (keys_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (keys_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (keys_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (keys_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (keys_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (keys_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (keys_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (keys_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (keys_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (keys_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (keys_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (keys_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (keys_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (keys_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (keys_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (keys_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) keys_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (keys_s1_agent_rf_source_data), // in.data
.in_valid (keys_s1_agent_rf_source_valid), // .valid
.in_ready (keys_s1_agent_rf_source_ready), // .ready
.in_startofpacket (keys_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (keys_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (keys_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (keys_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (keys_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (keys_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (keys_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
nios_system_mm_interconnect_0_router router (
.sink_ready (nios2_qsys_0_data_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_qsys_0_data_master_agent_cp_valid), // .valid
.sink_data (nios2_qsys_0_data_master_agent_cp_data), // .data
.sink_startofpacket (nios2_qsys_0_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_0_data_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_001 router_001 (
.sink_ready (nios2_qsys_0_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_qsys_0_instruction_master_agent_cp_valid), // .valid
.sink_data (nios2_qsys_0_instruction_master_agent_cp_data), // .data
.sink_startofpacket (nios2_qsys_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_002 (
.sink_ready (jtag_uart_0_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_0_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_uart_0_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_003 router_003 (
.sink_ready (nios2_qsys_0_debug_mem_slave_agent_rp_ready), // sink.ready
.sink_valid (nios2_qsys_0_debug_mem_slave_agent_rp_valid), // .valid
.sink_data (nios2_qsys_0_debug_mem_slave_agent_rp_data), // .data
.sink_startofpacket (nios2_qsys_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_0_debug_mem_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_003 router_004 (
.sink_ready (onchip_memory2_0_s1_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.sink_data (onchip_memory2_0_s1_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_005 (
.sink_ready (leds_s1_agent_rp_ready), // sink.ready
.sink_valid (leds_s1_agent_rp_valid), // .valid
.sink_data (leds_s1_agent_rp_data), // .data
.sink_startofpacket (leds_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (leds_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_006 (
.sink_ready (switches_s1_agent_rp_ready), // sink.ready
.sink_valid (switches_s1_agent_rp_valid), // .valid
.sink_data (switches_s1_agent_rp_data), // .data
.sink_startofpacket (switches_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (switches_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_007 (
.sink_ready (sram_data_s1_agent_rp_ready), // sink.ready
.sink_valid (sram_data_s1_agent_rp_valid), // .valid
.sink_data (sram_data_s1_agent_rp_data), // .data
.sink_startofpacket (sram_data_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_data_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_008 (
.sink_ready (sram_addr_s1_agent_rp_ready), // sink.ready
.sink_valid (sram_addr_s1_agent_rp_valid), // .valid
.sink_data (sram_addr_s1_agent_rp_data), // .data
.sink_startofpacket (sram_addr_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_addr_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_008_src_ready), // src.ready
.src_valid (router_008_src_valid), // .valid
.src_data (router_008_src_data), // .data
.src_channel (router_008_src_channel), // .channel
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_009 (
.sink_ready (sram_read_write_s1_agent_rp_ready), // sink.ready
.sink_valid (sram_read_write_s1_agent_rp_valid), // .valid
.sink_data (sram_read_write_s1_agent_rp_data), // .data
.sink_startofpacket (sram_read_write_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_read_write_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_009_src_ready), // src.ready
.src_valid (router_009_src_valid), // .valid
.src_data (router_009_src_data), // .data
.src_channel (router_009_src_channel), // .channel
.src_startofpacket (router_009_src_startofpacket), // .startofpacket
.src_endofpacket (router_009_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_010 (
.sink_ready (sram_cs_s1_agent_rp_ready), // sink.ready
.sink_valid (sram_cs_s1_agent_rp_valid), // .valid
.sink_data (sram_cs_s1_agent_rp_data), // .data
.sink_startofpacket (sram_cs_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_cs_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_010_src_ready), // src.ready
.src_valid (router_010_src_valid), // .valid
.src_data (router_010_src_data), // .data
.src_channel (router_010_src_channel), // .channel
.src_startofpacket (router_010_src_startofpacket), // .startofpacket
.src_endofpacket (router_010_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_011 (
.sink_ready (sram_oe_s1_agent_rp_ready), // sink.ready
.sink_valid (sram_oe_s1_agent_rp_valid), // .valid
.sink_data (sram_oe_s1_agent_rp_data), // .data
.sink_startofpacket (sram_oe_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_oe_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_011_src_ready), // src.ready
.src_valid (router_011_src_valid), // .valid
.src_data (router_011_src_data), // .data
.src_channel (router_011_src_channel), // .channel
.src_startofpacket (router_011_src_startofpacket), // .startofpacket
.src_endofpacket (router_011_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_012 (
.sink_ready (regfile_data_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_data_s1_agent_rp_valid), // .valid
.sink_data (regfile_data_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_data_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_data_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_012_src_ready), // src.ready
.src_valid (router_012_src_valid), // .valid
.src_data (router_012_src_data), // .data
.src_channel (router_012_src_channel), // .channel
.src_startofpacket (router_012_src_startofpacket), // .startofpacket
.src_endofpacket (router_012_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_013 (
.sink_ready (regfile_reg1_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_reg1_s1_agent_rp_valid), // .valid
.sink_data (regfile_reg1_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_reg1_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_reg1_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_013_src_ready), // src.ready
.src_valid (router_013_src_valid), // .valid
.src_data (router_013_src_data), // .data
.src_channel (router_013_src_channel), // .channel
.src_startofpacket (router_013_src_startofpacket), // .startofpacket
.src_endofpacket (router_013_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_014 (
.sink_ready (regfile_reg2_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_reg2_s1_agent_rp_valid), // .valid
.sink_data (regfile_reg2_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_reg2_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_reg2_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_014_src_ready), // src.ready
.src_valid (router_014_src_valid), // .valid
.src_data (router_014_src_data), // .data
.src_channel (router_014_src_channel), // .channel
.src_startofpacket (router_014_src_startofpacket), // .startofpacket
.src_endofpacket (router_014_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_015 (
.sink_ready (regfile_r1sel_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_r1sel_s1_agent_rp_valid), // .valid
.sink_data (regfile_r1sel_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_r1sel_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_r1sel_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_015_src_ready), // src.ready
.src_valid (router_015_src_valid), // .valid
.src_data (router_015_src_data), // .data
.src_channel (router_015_src_channel), // .channel
.src_startofpacket (router_015_src_startofpacket), // .startofpacket
.src_endofpacket (router_015_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_016 (
.sink_ready (regfile_r2sel_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_r2sel_s1_agent_rp_valid), // .valid
.sink_data (regfile_r2sel_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_r2sel_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_r2sel_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_016_src_ready), // src.ready
.src_valid (router_016_src_valid), // .valid
.src_data (router_016_src_data), // .data
.src_channel (router_016_src_channel), // .channel
.src_startofpacket (router_016_src_startofpacket), // .startofpacket
.src_endofpacket (router_016_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_017 (
.sink_ready (regfile_wsel_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_wsel_s1_agent_rp_valid), // .valid
.sink_data (regfile_wsel_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_wsel_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_wsel_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_017_src_ready), // src.ready
.src_valid (router_017_src_valid), // .valid
.src_data (router_017_src_data), // .data
.src_channel (router_017_src_channel), // .channel
.src_startofpacket (router_017_src_startofpacket), // .startofpacket
.src_endofpacket (router_017_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_018 (
.sink_ready (regfile_we_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_we_s1_agent_rp_valid), // .valid
.sink_data (regfile_we_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_we_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_we_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_018_src_ready), // src.ready
.src_valid (router_018_src_valid), // .valid
.src_data (router_018_src_data), // .data
.src_channel (router_018_src_channel), // .channel
.src_startofpacket (router_018_src_startofpacket), // .startofpacket
.src_endofpacket (router_018_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_019 (
.sink_ready (hex_0_s1_agent_rp_ready), // sink.ready
.sink_valid (hex_0_s1_agent_rp_valid), // .valid
.sink_data (hex_0_s1_agent_rp_data), // .data
.sink_startofpacket (hex_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_019_src_ready), // src.ready
.src_valid (router_019_src_valid), // .valid
.src_data (router_019_src_data), // .data
.src_channel (router_019_src_channel), // .channel
.src_startofpacket (router_019_src_startofpacket), // .startofpacket
.src_endofpacket (router_019_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_020 (
.sink_ready (hex_1_s1_agent_rp_ready), // sink.ready
.sink_valid (hex_1_s1_agent_rp_valid), // .valid
.sink_data (hex_1_s1_agent_rp_data), // .data
.sink_startofpacket (hex_1_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex_1_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_020_src_ready), // src.ready
.src_valid (router_020_src_valid), // .valid
.src_data (router_020_src_data), // .data
.src_channel (router_020_src_channel), // .channel
.src_startofpacket (router_020_src_startofpacket), // .startofpacket
.src_endofpacket (router_020_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_021 (
.sink_ready (hex_2_s1_agent_rp_ready), // sink.ready
.sink_valid (hex_2_s1_agent_rp_valid), // .valid
.sink_data (hex_2_s1_agent_rp_data), // .data
.sink_startofpacket (hex_2_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex_2_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_021_src_ready), // src.ready
.src_valid (router_021_src_valid), // .valid
.src_data (router_021_src_data), // .data
.src_channel (router_021_src_channel), // .channel
.src_startofpacket (router_021_src_startofpacket), // .startofpacket
.src_endofpacket (router_021_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_022 (
.sink_ready (hex_3_s1_agent_rp_ready), // sink.ready
.sink_valid (hex_3_s1_agent_rp_valid), // .valid
.sink_data (hex_3_s1_agent_rp_data), // .data
.sink_startofpacket (hex_3_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex_3_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_022_src_ready), // src.ready
.src_valid (router_022_src_valid), // .valid
.src_data (router_022_src_data), // .data
.src_channel (router_022_src_channel), // .channel
.src_startofpacket (router_022_src_startofpacket), // .startofpacket
.src_endofpacket (router_022_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_023 (
.sink_ready (hex_4_s1_agent_rp_ready), // sink.ready
.sink_valid (hex_4_s1_agent_rp_valid), // .valid
.sink_data (hex_4_s1_agent_rp_data), // .data
.sink_startofpacket (hex_4_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex_4_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_023_src_ready), // src.ready
.src_valid (router_023_src_valid), // .valid
.src_data (router_023_src_data), // .data
.src_channel (router_023_src_channel), // .channel
.src_startofpacket (router_023_src_startofpacket), // .startofpacket
.src_endofpacket (router_023_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_024 (
.sink_ready (hex_5_s1_agent_rp_ready), // sink.ready
.sink_valid (hex_5_s1_agent_rp_valid), // .valid
.sink_data (hex_5_s1_agent_rp_data), // .data
.sink_startofpacket (hex_5_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex_5_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_024_src_ready), // src.ready
.src_valid (router_024_src_valid), // .valid
.src_data (router_024_src_data), // .data
.src_channel (router_024_src_channel), // .channel
.src_startofpacket (router_024_src_startofpacket), // .startofpacket
.src_endofpacket (router_024_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_025 (
.sink_ready (alu_a_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_a_s1_agent_rp_valid), // .valid
.sink_data (alu_a_s1_agent_rp_data), // .data
.sink_startofpacket (alu_a_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_a_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_025_src_ready), // src.ready
.src_valid (router_025_src_valid), // .valid
.src_data (router_025_src_data), // .data
.src_channel (router_025_src_channel), // .channel
.src_startofpacket (router_025_src_startofpacket), // .startofpacket
.src_endofpacket (router_025_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_026 (
.sink_ready (alu_b_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_b_s1_agent_rp_valid), // .valid
.sink_data (alu_b_s1_agent_rp_data), // .data
.sink_startofpacket (alu_b_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_b_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_026_src_ready), // src.ready
.src_valid (router_026_src_valid), // .valid
.src_data (router_026_src_data), // .data
.src_channel (router_026_src_channel), // .channel
.src_startofpacket (router_026_src_startofpacket), // .startofpacket
.src_endofpacket (router_026_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_027 (
.sink_ready (alu_control_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_control_s1_agent_rp_valid), // .valid
.sink_data (alu_control_s1_agent_rp_data), // .data
.sink_startofpacket (alu_control_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_control_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_027_src_ready), // src.ready
.src_valid (router_027_src_valid), // .valid
.src_data (router_027_src_data), // .data
.src_channel (router_027_src_channel), // .channel
.src_startofpacket (router_027_src_startofpacket), // .startofpacket
.src_endofpacket (router_027_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_028 (
.sink_ready (alu_out_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_out_s1_agent_rp_valid), // .valid
.sink_data (alu_out_s1_agent_rp_data), // .data
.sink_startofpacket (alu_out_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_out_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_028_src_ready), // src.ready
.src_valid (router_028_src_valid), // .valid
.src_data (router_028_src_data), // .data
.src_channel (router_028_src_channel), // .channel
.src_startofpacket (router_028_src_startofpacket), // .startofpacket
.src_endofpacket (router_028_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_029 (
.sink_ready (alu_zero_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_zero_s1_agent_rp_valid), // .valid
.sink_data (alu_zero_s1_agent_rp_data), // .data
.sink_startofpacket (alu_zero_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_zero_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_029_src_ready), // src.ready
.src_valid (router_029_src_valid), // .valid
.src_data (router_029_src_data), // .data
.src_channel (router_029_src_channel), // .channel
.src_startofpacket (router_029_src_startofpacket), // .startofpacket
.src_endofpacket (router_029_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_030 (
.sink_ready (alu_overflow_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_overflow_s1_agent_rp_valid), // .valid
.sink_data (alu_overflow_s1_agent_rp_data), // .data
.sink_startofpacket (alu_overflow_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_overflow_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_030_src_ready), // src.ready
.src_valid (router_030_src_valid), // .valid
.src_data (router_030_src_data), // .data
.src_channel (router_030_src_channel), // .channel
.src_startofpacket (router_030_src_startofpacket), // .startofpacket
.src_endofpacket (router_030_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_031 (
.sink_ready (alu_carry_out_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_carry_out_s1_agent_rp_valid), // .valid
.sink_data (alu_carry_out_s1_agent_rp_data), // .data
.sink_startofpacket (alu_carry_out_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_carry_out_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_031_src_ready), // src.ready
.src_valid (router_031_src_valid), // .valid
.src_data (router_031_src_data), // .data
.src_channel (router_031_src_channel), // .channel
.src_startofpacket (router_031_src_startofpacket), // .startofpacket
.src_endofpacket (router_031_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_032 (
.sink_ready (alu_negative_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_negative_s1_agent_rp_valid), // .valid
.sink_data (alu_negative_s1_agent_rp_data), // .data
.sink_startofpacket (alu_negative_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_negative_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_032_src_ready), // src.ready
.src_valid (router_032_src_valid), // .valid
.src_data (router_032_src_data), // .data
.src_channel (router_032_src_channel), // .channel
.src_startofpacket (router_032_src_startofpacket), // .startofpacket
.src_endofpacket (router_032_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_033 (
.sink_ready (keys_s1_agent_rp_ready), // sink.ready
.sink_valid (keys_s1_agent_rp_valid), // .valid
.sink_data (keys_s1_agent_rp_data), // .data
.sink_startofpacket (keys_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (keys_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_033_src_ready), // src.ready
.src_valid (router_033_src_valid), // .valid
.src_data (router_033_src_data), // .data
.src_channel (router_033_src_channel), // .channel
.src_startofpacket (router_033_src_startofpacket), // .startofpacket
.src_endofpacket (router_033_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_demux cmd_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_src6_ready), // src6.ready
.src6_valid (cmd_demux_src6_valid), // .valid
.src6_data (cmd_demux_src6_data), // .data
.src6_channel (cmd_demux_src6_channel), // .channel
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
.src7_ready (cmd_demux_src7_ready), // src7.ready
.src7_valid (cmd_demux_src7_valid), // .valid
.src7_data (cmd_demux_src7_data), // .data
.src7_channel (cmd_demux_src7_channel), // .channel
.src7_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_demux_src7_endofpacket), // .endofpacket
.src8_ready (cmd_demux_src8_ready), // src8.ready
.src8_valid (cmd_demux_src8_valid), // .valid
.src8_data (cmd_demux_src8_data), // .data
.src8_channel (cmd_demux_src8_channel), // .channel
.src8_startofpacket (cmd_demux_src8_startofpacket), // .startofpacket
.src8_endofpacket (cmd_demux_src8_endofpacket), // .endofpacket
.src9_ready (cmd_demux_src9_ready), // src9.ready
.src9_valid (cmd_demux_src9_valid), // .valid
.src9_data (cmd_demux_src9_data), // .data
.src9_channel (cmd_demux_src9_channel), // .channel
.src9_startofpacket (cmd_demux_src9_startofpacket), // .startofpacket
.src9_endofpacket (cmd_demux_src9_endofpacket), // .endofpacket
.src10_ready (cmd_demux_src10_ready), // src10.ready
.src10_valid (cmd_demux_src10_valid), // .valid
.src10_data (cmd_demux_src10_data), // .data
.src10_channel (cmd_demux_src10_channel), // .channel
.src10_startofpacket (cmd_demux_src10_startofpacket), // .startofpacket
.src10_endofpacket (cmd_demux_src10_endofpacket), // .endofpacket
.src11_ready (cmd_demux_src11_ready), // src11.ready
.src11_valid (cmd_demux_src11_valid), // .valid
.src11_data (cmd_demux_src11_data), // .data
.src11_channel (cmd_demux_src11_channel), // .channel
.src11_startofpacket (cmd_demux_src11_startofpacket), // .startofpacket
.src11_endofpacket (cmd_demux_src11_endofpacket), // .endofpacket
.src12_ready (cmd_demux_src12_ready), // src12.ready
.src12_valid (cmd_demux_src12_valid), // .valid
.src12_data (cmd_demux_src12_data), // .data
.src12_channel (cmd_demux_src12_channel), // .channel
.src12_startofpacket (cmd_demux_src12_startofpacket), // .startofpacket
.src12_endofpacket (cmd_demux_src12_endofpacket), // .endofpacket
.src13_ready (cmd_demux_src13_ready), // src13.ready
.src13_valid (cmd_demux_src13_valid), // .valid
.src13_data (cmd_demux_src13_data), // .data
.src13_channel (cmd_demux_src13_channel), // .channel
.src13_startofpacket (cmd_demux_src13_startofpacket), // .startofpacket
.src13_endofpacket (cmd_demux_src13_endofpacket), // .endofpacket
.src14_ready (cmd_demux_src14_ready), // src14.ready
.src14_valid (cmd_demux_src14_valid), // .valid
.src14_data (cmd_demux_src14_data), // .data
.src14_channel (cmd_demux_src14_channel), // .channel
.src14_startofpacket (cmd_demux_src14_startofpacket), // .startofpacket
.src14_endofpacket (cmd_demux_src14_endofpacket), // .endofpacket
.src15_ready (cmd_demux_src15_ready), // src15.ready
.src15_valid (cmd_demux_src15_valid), // .valid
.src15_data (cmd_demux_src15_data), // .data
.src15_channel (cmd_demux_src15_channel), // .channel
.src15_startofpacket (cmd_demux_src15_startofpacket), // .startofpacket
.src15_endofpacket (cmd_demux_src15_endofpacket), // .endofpacket
.src16_ready (cmd_demux_src16_ready), // src16.ready
.src16_valid (cmd_demux_src16_valid), // .valid
.src16_data (cmd_demux_src16_data), // .data
.src16_channel (cmd_demux_src16_channel), // .channel
.src16_startofpacket (cmd_demux_src16_startofpacket), // .startofpacket
.src16_endofpacket (cmd_demux_src16_endofpacket), // .endofpacket
.src17_ready (cmd_demux_src17_ready), // src17.ready
.src17_valid (cmd_demux_src17_valid), // .valid
.src17_data (cmd_demux_src17_data), // .data
.src17_channel (cmd_demux_src17_channel), // .channel
.src17_startofpacket (cmd_demux_src17_startofpacket), // .startofpacket
.src17_endofpacket (cmd_demux_src17_endofpacket), // .endofpacket
.src18_ready (cmd_demux_src18_ready), // src18.ready
.src18_valid (cmd_demux_src18_valid), // .valid
.src18_data (cmd_demux_src18_data), // .data
.src18_channel (cmd_demux_src18_channel), // .channel
.src18_startofpacket (cmd_demux_src18_startofpacket), // .startofpacket
.src18_endofpacket (cmd_demux_src18_endofpacket), // .endofpacket
.src19_ready (cmd_demux_src19_ready), // src19.ready
.src19_valid (cmd_demux_src19_valid), // .valid
.src19_data (cmd_demux_src19_data), // .data
.src19_channel (cmd_demux_src19_channel), // .channel
.src19_startofpacket (cmd_demux_src19_startofpacket), // .startofpacket
.src19_endofpacket (cmd_demux_src19_endofpacket), // .endofpacket
.src20_ready (cmd_demux_src20_ready), // src20.ready
.src20_valid (cmd_demux_src20_valid), // .valid
.src20_data (cmd_demux_src20_data), // .data
.src20_channel (cmd_demux_src20_channel), // .channel
.src20_startofpacket (cmd_demux_src20_startofpacket), // .startofpacket
.src20_endofpacket (cmd_demux_src20_endofpacket), // .endofpacket
.src21_ready (cmd_demux_src21_ready), // src21.ready
.src21_valid (cmd_demux_src21_valid), // .valid
.src21_data (cmd_demux_src21_data), // .data
.src21_channel (cmd_demux_src21_channel), // .channel
.src21_startofpacket (cmd_demux_src21_startofpacket), // .startofpacket
.src21_endofpacket (cmd_demux_src21_endofpacket), // .endofpacket
.src22_ready (cmd_demux_src22_ready), // src22.ready
.src22_valid (cmd_demux_src22_valid), // .valid
.src22_data (cmd_demux_src22_data), // .data
.src22_channel (cmd_demux_src22_channel), // .channel
.src22_startofpacket (cmd_demux_src22_startofpacket), // .startofpacket
.src22_endofpacket (cmd_demux_src22_endofpacket), // .endofpacket
.src23_ready (cmd_demux_src23_ready), // src23.ready
.src23_valid (cmd_demux_src23_valid), // .valid
.src23_data (cmd_demux_src23_data), // .data
.src23_channel (cmd_demux_src23_channel), // .channel
.src23_startofpacket (cmd_demux_src23_startofpacket), // .startofpacket
.src23_endofpacket (cmd_demux_src23_endofpacket), // .endofpacket
.src24_ready (cmd_demux_src24_ready), // src24.ready
.src24_valid (cmd_demux_src24_valid), // .valid
.src24_data (cmd_demux_src24_data), // .data
.src24_channel (cmd_demux_src24_channel), // .channel
.src24_startofpacket (cmd_demux_src24_startofpacket), // .startofpacket
.src24_endofpacket (cmd_demux_src24_endofpacket), // .endofpacket
.src25_ready (cmd_demux_src25_ready), // src25.ready
.src25_valid (cmd_demux_src25_valid), // .valid
.src25_data (cmd_demux_src25_data), // .data
.src25_channel (cmd_demux_src25_channel), // .channel
.src25_startofpacket (cmd_demux_src25_startofpacket), // .startofpacket
.src25_endofpacket (cmd_demux_src25_endofpacket), // .endofpacket
.src26_ready (cmd_demux_src26_ready), // src26.ready
.src26_valid (cmd_demux_src26_valid), // .valid
.src26_data (cmd_demux_src26_data), // .data
.src26_channel (cmd_demux_src26_channel), // .channel
.src26_startofpacket (cmd_demux_src26_startofpacket), // .startofpacket
.src26_endofpacket (cmd_demux_src26_endofpacket), // .endofpacket
.src27_ready (cmd_demux_src27_ready), // src27.ready
.src27_valid (cmd_demux_src27_valid), // .valid
.src27_data (cmd_demux_src27_data), // .data
.src27_channel (cmd_demux_src27_channel), // .channel
.src27_startofpacket (cmd_demux_src27_startofpacket), // .startofpacket
.src27_endofpacket (cmd_demux_src27_endofpacket), // .endofpacket
.src28_ready (cmd_demux_src28_ready), // src28.ready
.src28_valid (cmd_demux_src28_valid), // .valid
.src28_data (cmd_demux_src28_data), // .data
.src28_channel (cmd_demux_src28_channel), // .channel
.src28_startofpacket (cmd_demux_src28_startofpacket), // .startofpacket
.src28_endofpacket (cmd_demux_src28_endofpacket), // .endofpacket
.src29_ready (cmd_demux_src29_ready), // src29.ready
.src29_valid (cmd_demux_src29_valid), // .valid
.src29_data (cmd_demux_src29_data), // .data
.src29_channel (cmd_demux_src29_channel), // .channel
.src29_startofpacket (cmd_demux_src29_startofpacket), // .startofpacket
.src29_endofpacket (cmd_demux_src29_endofpacket), // .endofpacket
.src30_ready (cmd_demux_src30_ready), // src30.ready
.src30_valid (cmd_demux_src30_valid), // .valid
.src30_data (cmd_demux_src30_data), // .data
.src30_channel (cmd_demux_src30_channel), // .channel
.src30_startofpacket (cmd_demux_src30_startofpacket), // .startofpacket
.src30_endofpacket (cmd_demux_src30_endofpacket), // .endofpacket
.src31_ready (cmd_demux_src31_ready), // src31.ready
.src31_valid (cmd_demux_src31_valid), // .valid
.src31_data (cmd_demux_src31_data), // .data
.src31_channel (cmd_demux_src31_channel), // .channel
.src31_startofpacket (cmd_demux_src31_startofpacket), // .startofpacket
.src31_endofpacket (cmd_demux_src31_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux_001 cmd_mux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_005 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_006 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src6_ready), // sink0.ready
.sink0_valid (cmd_demux_src6_valid), // .valid
.sink0_channel (cmd_demux_src6_channel), // .channel
.sink0_data (cmd_demux_src6_data), // .data
.sink0_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_007 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_007_src_ready), // src.ready
.src_valid (cmd_mux_007_src_valid), // .valid
.src_data (cmd_mux_007_src_data), // .data
.src_channel (cmd_mux_007_src_channel), // .channel
.src_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src7_ready), // sink0.ready
.sink0_valid (cmd_demux_src7_valid), // .valid
.sink0_channel (cmd_demux_src7_channel), // .channel
.sink0_data (cmd_demux_src7_data), // .data
.sink0_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src7_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_008 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_008_src_ready), // src.ready
.src_valid (cmd_mux_008_src_valid), // .valid
.src_data (cmd_mux_008_src_data), // .data
.src_channel (cmd_mux_008_src_channel), // .channel
.src_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src8_ready), // sink0.ready
.sink0_valid (cmd_demux_src8_valid), // .valid
.sink0_channel (cmd_demux_src8_channel), // .channel
.sink0_data (cmd_demux_src8_data), // .data
.sink0_startofpacket (cmd_demux_src8_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src8_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_009 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_009_src_ready), // src.ready
.src_valid (cmd_mux_009_src_valid), // .valid
.src_data (cmd_mux_009_src_data), // .data
.src_channel (cmd_mux_009_src_channel), // .channel
.src_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src9_ready), // sink0.ready
.sink0_valid (cmd_demux_src9_valid), // .valid
.sink0_channel (cmd_demux_src9_channel), // .channel
.sink0_data (cmd_demux_src9_data), // .data
.sink0_startofpacket (cmd_demux_src9_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src9_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_010 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_010_src_ready), // src.ready
.src_valid (cmd_mux_010_src_valid), // .valid
.src_data (cmd_mux_010_src_data), // .data
.src_channel (cmd_mux_010_src_channel), // .channel
.src_startofpacket (cmd_mux_010_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_010_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src10_ready), // sink0.ready
.sink0_valid (cmd_demux_src10_valid), // .valid
.sink0_channel (cmd_demux_src10_channel), // .channel
.sink0_data (cmd_demux_src10_data), // .data
.sink0_startofpacket (cmd_demux_src10_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src10_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_011 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_011_src_ready), // src.ready
.src_valid (cmd_mux_011_src_valid), // .valid
.src_data (cmd_mux_011_src_data), // .data
.src_channel (cmd_mux_011_src_channel), // .channel
.src_startofpacket (cmd_mux_011_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_011_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src11_ready), // sink0.ready
.sink0_valid (cmd_demux_src11_valid), // .valid
.sink0_channel (cmd_demux_src11_channel), // .channel
.sink0_data (cmd_demux_src11_data), // .data
.sink0_startofpacket (cmd_demux_src11_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src11_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_012 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_012_src_ready), // src.ready
.src_valid (cmd_mux_012_src_valid), // .valid
.src_data (cmd_mux_012_src_data), // .data
.src_channel (cmd_mux_012_src_channel), // .channel
.src_startofpacket (cmd_mux_012_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_012_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src12_ready), // sink0.ready
.sink0_valid (cmd_demux_src12_valid), // .valid
.sink0_channel (cmd_demux_src12_channel), // .channel
.sink0_data (cmd_demux_src12_data), // .data
.sink0_startofpacket (cmd_demux_src12_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src12_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_013 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_013_src_ready), // src.ready
.src_valid (cmd_mux_013_src_valid), // .valid
.src_data (cmd_mux_013_src_data), // .data
.src_channel (cmd_mux_013_src_channel), // .channel
.src_startofpacket (cmd_mux_013_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_013_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src13_ready), // sink0.ready
.sink0_valid (cmd_demux_src13_valid), // .valid
.sink0_channel (cmd_demux_src13_channel), // .channel
.sink0_data (cmd_demux_src13_data), // .data
.sink0_startofpacket (cmd_demux_src13_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src13_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_014 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_014_src_ready), // src.ready
.src_valid (cmd_mux_014_src_valid), // .valid
.src_data (cmd_mux_014_src_data), // .data
.src_channel (cmd_mux_014_src_channel), // .channel
.src_startofpacket (cmd_mux_014_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_014_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src14_ready), // sink0.ready
.sink0_valid (cmd_demux_src14_valid), // .valid
.sink0_channel (cmd_demux_src14_channel), // .channel
.sink0_data (cmd_demux_src14_data), // .data
.sink0_startofpacket (cmd_demux_src14_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src14_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_015 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_015_src_ready), // src.ready
.src_valid (cmd_mux_015_src_valid), // .valid
.src_data (cmd_mux_015_src_data), // .data
.src_channel (cmd_mux_015_src_channel), // .channel
.src_startofpacket (cmd_mux_015_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_015_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src15_ready), // sink0.ready
.sink0_valid (cmd_demux_src15_valid), // .valid
.sink0_channel (cmd_demux_src15_channel), // .channel
.sink0_data (cmd_demux_src15_data), // .data
.sink0_startofpacket (cmd_demux_src15_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src15_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_016 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_016_src_ready), // src.ready
.src_valid (cmd_mux_016_src_valid), // .valid
.src_data (cmd_mux_016_src_data), // .data
.src_channel (cmd_mux_016_src_channel), // .channel
.src_startofpacket (cmd_mux_016_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_016_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src16_ready), // sink0.ready
.sink0_valid (cmd_demux_src16_valid), // .valid
.sink0_channel (cmd_demux_src16_channel), // .channel
.sink0_data (cmd_demux_src16_data), // .data
.sink0_startofpacket (cmd_demux_src16_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src16_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_017 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_017_src_ready), // src.ready
.src_valid (cmd_mux_017_src_valid), // .valid
.src_data (cmd_mux_017_src_data), // .data
.src_channel (cmd_mux_017_src_channel), // .channel
.src_startofpacket (cmd_mux_017_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_017_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src17_ready), // sink0.ready
.sink0_valid (cmd_demux_src17_valid), // .valid
.sink0_channel (cmd_demux_src17_channel), // .channel
.sink0_data (cmd_demux_src17_data), // .data
.sink0_startofpacket (cmd_demux_src17_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src17_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_018 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_018_src_ready), // src.ready
.src_valid (cmd_mux_018_src_valid), // .valid
.src_data (cmd_mux_018_src_data), // .data
.src_channel (cmd_mux_018_src_channel), // .channel
.src_startofpacket (cmd_mux_018_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_018_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src18_ready), // sink0.ready
.sink0_valid (cmd_demux_src18_valid), // .valid
.sink0_channel (cmd_demux_src18_channel), // .channel
.sink0_data (cmd_demux_src18_data), // .data
.sink0_startofpacket (cmd_demux_src18_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src18_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_019 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_019_src_ready), // src.ready
.src_valid (cmd_mux_019_src_valid), // .valid
.src_data (cmd_mux_019_src_data), // .data
.src_channel (cmd_mux_019_src_channel), // .channel
.src_startofpacket (cmd_mux_019_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_019_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src19_ready), // sink0.ready
.sink0_valid (cmd_demux_src19_valid), // .valid
.sink0_channel (cmd_demux_src19_channel), // .channel
.sink0_data (cmd_demux_src19_data), // .data
.sink0_startofpacket (cmd_demux_src19_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src19_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_020 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_020_src_ready), // src.ready
.src_valid (cmd_mux_020_src_valid), // .valid
.src_data (cmd_mux_020_src_data), // .data
.src_channel (cmd_mux_020_src_channel), // .channel
.src_startofpacket (cmd_mux_020_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_020_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src20_ready), // sink0.ready
.sink0_valid (cmd_demux_src20_valid), // .valid
.sink0_channel (cmd_demux_src20_channel), // .channel
.sink0_data (cmd_demux_src20_data), // .data
.sink0_startofpacket (cmd_demux_src20_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src20_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_021 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_021_src_ready), // src.ready
.src_valid (cmd_mux_021_src_valid), // .valid
.src_data (cmd_mux_021_src_data), // .data
.src_channel (cmd_mux_021_src_channel), // .channel
.src_startofpacket (cmd_mux_021_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_021_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src21_ready), // sink0.ready
.sink0_valid (cmd_demux_src21_valid), // .valid
.sink0_channel (cmd_demux_src21_channel), // .channel
.sink0_data (cmd_demux_src21_data), // .data
.sink0_startofpacket (cmd_demux_src21_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src21_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_022 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_022_src_ready), // src.ready
.src_valid (cmd_mux_022_src_valid), // .valid
.src_data (cmd_mux_022_src_data), // .data
.src_channel (cmd_mux_022_src_channel), // .channel
.src_startofpacket (cmd_mux_022_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_022_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src22_ready), // sink0.ready
.sink0_valid (cmd_demux_src22_valid), // .valid
.sink0_channel (cmd_demux_src22_channel), // .channel
.sink0_data (cmd_demux_src22_data), // .data
.sink0_startofpacket (cmd_demux_src22_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src22_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_023 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_023_src_ready), // src.ready
.src_valid (cmd_mux_023_src_valid), // .valid
.src_data (cmd_mux_023_src_data), // .data
.src_channel (cmd_mux_023_src_channel), // .channel
.src_startofpacket (cmd_mux_023_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_023_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src23_ready), // sink0.ready
.sink0_valid (cmd_demux_src23_valid), // .valid
.sink0_channel (cmd_demux_src23_channel), // .channel
.sink0_data (cmd_demux_src23_data), // .data
.sink0_startofpacket (cmd_demux_src23_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src23_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_024 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_024_src_ready), // src.ready
.src_valid (cmd_mux_024_src_valid), // .valid
.src_data (cmd_mux_024_src_data), // .data
.src_channel (cmd_mux_024_src_channel), // .channel
.src_startofpacket (cmd_mux_024_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_024_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src24_ready), // sink0.ready
.sink0_valid (cmd_demux_src24_valid), // .valid
.sink0_channel (cmd_demux_src24_channel), // .channel
.sink0_data (cmd_demux_src24_data), // .data
.sink0_startofpacket (cmd_demux_src24_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src24_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_025 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_025_src_ready), // src.ready
.src_valid (cmd_mux_025_src_valid), // .valid
.src_data (cmd_mux_025_src_data), // .data
.src_channel (cmd_mux_025_src_channel), // .channel
.src_startofpacket (cmd_mux_025_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_025_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src25_ready), // sink0.ready
.sink0_valid (cmd_demux_src25_valid), // .valid
.sink0_channel (cmd_demux_src25_channel), // .channel
.sink0_data (cmd_demux_src25_data), // .data
.sink0_startofpacket (cmd_demux_src25_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src25_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_026 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_026_src_ready), // src.ready
.src_valid (cmd_mux_026_src_valid), // .valid
.src_data (cmd_mux_026_src_data), // .data
.src_channel (cmd_mux_026_src_channel), // .channel
.src_startofpacket (cmd_mux_026_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_026_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src26_ready), // sink0.ready
.sink0_valid (cmd_demux_src26_valid), // .valid
.sink0_channel (cmd_demux_src26_channel), // .channel
.sink0_data (cmd_demux_src26_data), // .data
.sink0_startofpacket (cmd_demux_src26_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src26_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_027 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_027_src_ready), // src.ready
.src_valid (cmd_mux_027_src_valid), // .valid
.src_data (cmd_mux_027_src_data), // .data
.src_channel (cmd_mux_027_src_channel), // .channel
.src_startofpacket (cmd_mux_027_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_027_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src27_ready), // sink0.ready
.sink0_valid (cmd_demux_src27_valid), // .valid
.sink0_channel (cmd_demux_src27_channel), // .channel
.sink0_data (cmd_demux_src27_data), // .data
.sink0_startofpacket (cmd_demux_src27_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src27_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_028 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_028_src_ready), // src.ready
.src_valid (cmd_mux_028_src_valid), // .valid
.src_data (cmd_mux_028_src_data), // .data
.src_channel (cmd_mux_028_src_channel), // .channel
.src_startofpacket (cmd_mux_028_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_028_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src28_ready), // sink0.ready
.sink0_valid (cmd_demux_src28_valid), // .valid
.sink0_channel (cmd_demux_src28_channel), // .channel
.sink0_data (cmd_demux_src28_data), // .data
.sink0_startofpacket (cmd_demux_src28_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src28_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_029 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_029_src_ready), // src.ready
.src_valid (cmd_mux_029_src_valid), // .valid
.src_data (cmd_mux_029_src_data), // .data
.src_channel (cmd_mux_029_src_channel), // .channel
.src_startofpacket (cmd_mux_029_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_029_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src29_ready), // sink0.ready
.sink0_valid (cmd_demux_src29_valid), // .valid
.sink0_channel (cmd_demux_src29_channel), // .channel
.sink0_data (cmd_demux_src29_data), // .data
.sink0_startofpacket (cmd_demux_src29_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src29_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_030 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_030_src_ready), // src.ready
.src_valid (cmd_mux_030_src_valid), // .valid
.src_data (cmd_mux_030_src_data), // .data
.src_channel (cmd_mux_030_src_channel), // .channel
.src_startofpacket (cmd_mux_030_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_030_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src30_ready), // sink0.ready
.sink0_valid (cmd_demux_src30_valid), // .valid
.sink0_channel (cmd_demux_src30_channel), // .channel
.sink0_data (cmd_demux_src30_data), // .data
.sink0_startofpacket (cmd_demux_src30_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src30_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_031 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_031_src_ready), // src.ready
.src_valid (cmd_mux_031_src_valid), // .valid
.src_data (cmd_mux_031_src_data), // .data
.src_channel (cmd_mux_031_src_channel), // .channel
.src_startofpacket (cmd_mux_031_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_031_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src31_ready), // sink0.ready
.sink0_valid (cmd_demux_src31_valid), // .valid
.sink0_channel (cmd_demux_src31_channel), // .channel
.sink0_data (cmd_demux_src31_data), // .data
.sink0_startofpacket (cmd_demux_src31_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src31_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_demux_001 rsp_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_demux_001 rsp_demux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_005 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_006 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_008_src_ready), // sink.ready
.sink_channel (router_008_src_channel), // .channel
.sink_data (router_008_src_data), // .data
.sink_startofpacket (router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (router_008_src_endofpacket), // .endofpacket
.sink_valid (router_008_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_007 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_009_src_ready), // sink.ready
.sink_channel (router_009_src_channel), // .channel
.sink_data (router_009_src_data), // .data
.sink_startofpacket (router_009_src_startofpacket), // .startofpacket
.sink_endofpacket (router_009_src_endofpacket), // .endofpacket
.sink_valid (router_009_src_valid), // .valid
.src0_ready (rsp_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_demux_007_src0_valid), // .valid
.src0_data (rsp_demux_007_src0_data), // .data
.src0_channel (rsp_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_007_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_008 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_010_src_ready), // sink.ready
.sink_channel (router_010_src_channel), // .channel
.sink_data (router_010_src_data), // .data
.sink_startofpacket (router_010_src_startofpacket), // .startofpacket
.sink_endofpacket (router_010_src_endofpacket), // .endofpacket
.sink_valid (router_010_src_valid), // .valid
.src0_ready (rsp_demux_008_src0_ready), // src0.ready
.src0_valid (rsp_demux_008_src0_valid), // .valid
.src0_data (rsp_demux_008_src0_data), // .data
.src0_channel (rsp_demux_008_src0_channel), // .channel
.src0_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_008_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_009 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_011_src_ready), // sink.ready
.sink_channel (router_011_src_channel), // .channel
.sink_data (router_011_src_data), // .data
.sink_startofpacket (router_011_src_startofpacket), // .startofpacket
.sink_endofpacket (router_011_src_endofpacket), // .endofpacket
.sink_valid (router_011_src_valid), // .valid
.src0_ready (rsp_demux_009_src0_ready), // src0.ready
.src0_valid (rsp_demux_009_src0_valid), // .valid
.src0_data (rsp_demux_009_src0_data), // .data
.src0_channel (rsp_demux_009_src0_channel), // .channel
.src0_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_009_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_010 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_012_src_ready), // sink.ready
.sink_channel (router_012_src_channel), // .channel
.sink_data (router_012_src_data), // .data
.sink_startofpacket (router_012_src_startofpacket), // .startofpacket
.sink_endofpacket (router_012_src_endofpacket), // .endofpacket
.sink_valid (router_012_src_valid), // .valid
.src0_ready (rsp_demux_010_src0_ready), // src0.ready
.src0_valid (rsp_demux_010_src0_valid), // .valid
.src0_data (rsp_demux_010_src0_data), // .data
.src0_channel (rsp_demux_010_src0_channel), // .channel
.src0_startofpacket (rsp_demux_010_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_010_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_011 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_013_src_ready), // sink.ready
.sink_channel (router_013_src_channel), // .channel
.sink_data (router_013_src_data), // .data
.sink_startofpacket (router_013_src_startofpacket), // .startofpacket
.sink_endofpacket (router_013_src_endofpacket), // .endofpacket
.sink_valid (router_013_src_valid), // .valid
.src0_ready (rsp_demux_011_src0_ready), // src0.ready
.src0_valid (rsp_demux_011_src0_valid), // .valid
.src0_data (rsp_demux_011_src0_data), // .data
.src0_channel (rsp_demux_011_src0_channel), // .channel
.src0_startofpacket (rsp_demux_011_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_011_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_012 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_014_src_ready), // sink.ready
.sink_channel (router_014_src_channel), // .channel
.sink_data (router_014_src_data), // .data
.sink_startofpacket (router_014_src_startofpacket), // .startofpacket
.sink_endofpacket (router_014_src_endofpacket), // .endofpacket
.sink_valid (router_014_src_valid), // .valid
.src0_ready (rsp_demux_012_src0_ready), // src0.ready
.src0_valid (rsp_demux_012_src0_valid), // .valid
.src0_data (rsp_demux_012_src0_data), // .data
.src0_channel (rsp_demux_012_src0_channel), // .channel
.src0_startofpacket (rsp_demux_012_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_012_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_013 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_015_src_ready), // sink.ready
.sink_channel (router_015_src_channel), // .channel
.sink_data (router_015_src_data), // .data
.sink_startofpacket (router_015_src_startofpacket), // .startofpacket
.sink_endofpacket (router_015_src_endofpacket), // .endofpacket
.sink_valid (router_015_src_valid), // .valid
.src0_ready (rsp_demux_013_src0_ready), // src0.ready
.src0_valid (rsp_demux_013_src0_valid), // .valid
.src0_data (rsp_demux_013_src0_data), // .data
.src0_channel (rsp_demux_013_src0_channel), // .channel
.src0_startofpacket (rsp_demux_013_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_013_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_014 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_016_src_ready), // sink.ready
.sink_channel (router_016_src_channel), // .channel
.sink_data (router_016_src_data), // .data
.sink_startofpacket (router_016_src_startofpacket), // .startofpacket
.sink_endofpacket (router_016_src_endofpacket), // .endofpacket
.sink_valid (router_016_src_valid), // .valid
.src0_ready (rsp_demux_014_src0_ready), // src0.ready
.src0_valid (rsp_demux_014_src0_valid), // .valid
.src0_data (rsp_demux_014_src0_data), // .data
.src0_channel (rsp_demux_014_src0_channel), // .channel
.src0_startofpacket (rsp_demux_014_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_014_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_015 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_017_src_ready), // sink.ready
.sink_channel (router_017_src_channel), // .channel
.sink_data (router_017_src_data), // .data
.sink_startofpacket (router_017_src_startofpacket), // .startofpacket
.sink_endofpacket (router_017_src_endofpacket), // .endofpacket
.sink_valid (router_017_src_valid), // .valid
.src0_ready (rsp_demux_015_src0_ready), // src0.ready
.src0_valid (rsp_demux_015_src0_valid), // .valid
.src0_data (rsp_demux_015_src0_data), // .data
.src0_channel (rsp_demux_015_src0_channel), // .channel
.src0_startofpacket (rsp_demux_015_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_015_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_016 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_018_src_ready), // sink.ready
.sink_channel (router_018_src_channel), // .channel
.sink_data (router_018_src_data), // .data
.sink_startofpacket (router_018_src_startofpacket), // .startofpacket
.sink_endofpacket (router_018_src_endofpacket), // .endofpacket
.sink_valid (router_018_src_valid), // .valid
.src0_ready (rsp_demux_016_src0_ready), // src0.ready
.src0_valid (rsp_demux_016_src0_valid), // .valid
.src0_data (rsp_demux_016_src0_data), // .data
.src0_channel (rsp_demux_016_src0_channel), // .channel
.src0_startofpacket (rsp_demux_016_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_016_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_017 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_019_src_ready), // sink.ready
.sink_channel (router_019_src_channel), // .channel
.sink_data (router_019_src_data), // .data
.sink_startofpacket (router_019_src_startofpacket), // .startofpacket
.sink_endofpacket (router_019_src_endofpacket), // .endofpacket
.sink_valid (router_019_src_valid), // .valid
.src0_ready (rsp_demux_017_src0_ready), // src0.ready
.src0_valid (rsp_demux_017_src0_valid), // .valid
.src0_data (rsp_demux_017_src0_data), // .data
.src0_channel (rsp_demux_017_src0_channel), // .channel
.src0_startofpacket (rsp_demux_017_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_017_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_018 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_020_src_ready), // sink.ready
.sink_channel (router_020_src_channel), // .channel
.sink_data (router_020_src_data), // .data
.sink_startofpacket (router_020_src_startofpacket), // .startofpacket
.sink_endofpacket (router_020_src_endofpacket), // .endofpacket
.sink_valid (router_020_src_valid), // .valid
.src0_ready (rsp_demux_018_src0_ready), // src0.ready
.src0_valid (rsp_demux_018_src0_valid), // .valid
.src0_data (rsp_demux_018_src0_data), // .data
.src0_channel (rsp_demux_018_src0_channel), // .channel
.src0_startofpacket (rsp_demux_018_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_018_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_019 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_021_src_ready), // sink.ready
.sink_channel (router_021_src_channel), // .channel
.sink_data (router_021_src_data), // .data
.sink_startofpacket (router_021_src_startofpacket), // .startofpacket
.sink_endofpacket (router_021_src_endofpacket), // .endofpacket
.sink_valid (router_021_src_valid), // .valid
.src0_ready (rsp_demux_019_src0_ready), // src0.ready
.src0_valid (rsp_demux_019_src0_valid), // .valid
.src0_data (rsp_demux_019_src0_data), // .data
.src0_channel (rsp_demux_019_src0_channel), // .channel
.src0_startofpacket (rsp_demux_019_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_019_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_020 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_022_src_ready), // sink.ready
.sink_channel (router_022_src_channel), // .channel
.sink_data (router_022_src_data), // .data
.sink_startofpacket (router_022_src_startofpacket), // .startofpacket
.sink_endofpacket (router_022_src_endofpacket), // .endofpacket
.sink_valid (router_022_src_valid), // .valid
.src0_ready (rsp_demux_020_src0_ready), // src0.ready
.src0_valid (rsp_demux_020_src0_valid), // .valid
.src0_data (rsp_demux_020_src0_data), // .data
.src0_channel (rsp_demux_020_src0_channel), // .channel
.src0_startofpacket (rsp_demux_020_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_020_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_021 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_023_src_ready), // sink.ready
.sink_channel (router_023_src_channel), // .channel
.sink_data (router_023_src_data), // .data
.sink_startofpacket (router_023_src_startofpacket), // .startofpacket
.sink_endofpacket (router_023_src_endofpacket), // .endofpacket
.sink_valid (router_023_src_valid), // .valid
.src0_ready (rsp_demux_021_src0_ready), // src0.ready
.src0_valid (rsp_demux_021_src0_valid), // .valid
.src0_data (rsp_demux_021_src0_data), // .data
.src0_channel (rsp_demux_021_src0_channel), // .channel
.src0_startofpacket (rsp_demux_021_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_021_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_022 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_024_src_ready), // sink.ready
.sink_channel (router_024_src_channel), // .channel
.sink_data (router_024_src_data), // .data
.sink_startofpacket (router_024_src_startofpacket), // .startofpacket
.sink_endofpacket (router_024_src_endofpacket), // .endofpacket
.sink_valid (router_024_src_valid), // .valid
.src0_ready (rsp_demux_022_src0_ready), // src0.ready
.src0_valid (rsp_demux_022_src0_valid), // .valid
.src0_data (rsp_demux_022_src0_data), // .data
.src0_channel (rsp_demux_022_src0_channel), // .channel
.src0_startofpacket (rsp_demux_022_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_022_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_023 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_025_src_ready), // sink.ready
.sink_channel (router_025_src_channel), // .channel
.sink_data (router_025_src_data), // .data
.sink_startofpacket (router_025_src_startofpacket), // .startofpacket
.sink_endofpacket (router_025_src_endofpacket), // .endofpacket
.sink_valid (router_025_src_valid), // .valid
.src0_ready (rsp_demux_023_src0_ready), // src0.ready
.src0_valid (rsp_demux_023_src0_valid), // .valid
.src0_data (rsp_demux_023_src0_data), // .data
.src0_channel (rsp_demux_023_src0_channel), // .channel
.src0_startofpacket (rsp_demux_023_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_023_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_024 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_026_src_ready), // sink.ready
.sink_channel (router_026_src_channel), // .channel
.sink_data (router_026_src_data), // .data
.sink_startofpacket (router_026_src_startofpacket), // .startofpacket
.sink_endofpacket (router_026_src_endofpacket), // .endofpacket
.sink_valid (router_026_src_valid), // .valid
.src0_ready (rsp_demux_024_src0_ready), // src0.ready
.src0_valid (rsp_demux_024_src0_valid), // .valid
.src0_data (rsp_demux_024_src0_data), // .data
.src0_channel (rsp_demux_024_src0_channel), // .channel
.src0_startofpacket (rsp_demux_024_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_024_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_025 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_027_src_ready), // sink.ready
.sink_channel (router_027_src_channel), // .channel
.sink_data (router_027_src_data), // .data
.sink_startofpacket (router_027_src_startofpacket), // .startofpacket
.sink_endofpacket (router_027_src_endofpacket), // .endofpacket
.sink_valid (router_027_src_valid), // .valid
.src0_ready (rsp_demux_025_src0_ready), // src0.ready
.src0_valid (rsp_demux_025_src0_valid), // .valid
.src0_data (rsp_demux_025_src0_data), // .data
.src0_channel (rsp_demux_025_src0_channel), // .channel
.src0_startofpacket (rsp_demux_025_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_025_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_026 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_028_src_ready), // sink.ready
.sink_channel (router_028_src_channel), // .channel
.sink_data (router_028_src_data), // .data
.sink_startofpacket (router_028_src_startofpacket), // .startofpacket
.sink_endofpacket (router_028_src_endofpacket), // .endofpacket
.sink_valid (router_028_src_valid), // .valid
.src0_ready (rsp_demux_026_src0_ready), // src0.ready
.src0_valid (rsp_demux_026_src0_valid), // .valid
.src0_data (rsp_demux_026_src0_data), // .data
.src0_channel (rsp_demux_026_src0_channel), // .channel
.src0_startofpacket (rsp_demux_026_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_026_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_027 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_029_src_ready), // sink.ready
.sink_channel (router_029_src_channel), // .channel
.sink_data (router_029_src_data), // .data
.sink_startofpacket (router_029_src_startofpacket), // .startofpacket
.sink_endofpacket (router_029_src_endofpacket), // .endofpacket
.sink_valid (router_029_src_valid), // .valid
.src0_ready (rsp_demux_027_src0_ready), // src0.ready
.src0_valid (rsp_demux_027_src0_valid), // .valid
.src0_data (rsp_demux_027_src0_data), // .data
.src0_channel (rsp_demux_027_src0_channel), // .channel
.src0_startofpacket (rsp_demux_027_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_027_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_028 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_030_src_ready), // sink.ready
.sink_channel (router_030_src_channel), // .channel
.sink_data (router_030_src_data), // .data
.sink_startofpacket (router_030_src_startofpacket), // .startofpacket
.sink_endofpacket (router_030_src_endofpacket), // .endofpacket
.sink_valid (router_030_src_valid), // .valid
.src0_ready (rsp_demux_028_src0_ready), // src0.ready
.src0_valid (rsp_demux_028_src0_valid), // .valid
.src0_data (rsp_demux_028_src0_data), // .data
.src0_channel (rsp_demux_028_src0_channel), // .channel
.src0_startofpacket (rsp_demux_028_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_028_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_029 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_031_src_ready), // sink.ready
.sink_channel (router_031_src_channel), // .channel
.sink_data (router_031_src_data), // .data
.sink_startofpacket (router_031_src_startofpacket), // .startofpacket
.sink_endofpacket (router_031_src_endofpacket), // .endofpacket
.sink_valid (router_031_src_valid), // .valid
.src0_ready (rsp_demux_029_src0_ready), // src0.ready
.src0_valid (rsp_demux_029_src0_valid), // .valid
.src0_data (rsp_demux_029_src0_data), // .data
.src0_channel (rsp_demux_029_src0_channel), // .channel
.src0_startofpacket (rsp_demux_029_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_029_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_030 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_032_src_ready), // sink.ready
.sink_channel (router_032_src_channel), // .channel
.sink_data (router_032_src_data), // .data
.sink_startofpacket (router_032_src_startofpacket), // .startofpacket
.sink_endofpacket (router_032_src_endofpacket), // .endofpacket
.sink_valid (router_032_src_valid), // .valid
.src0_ready (rsp_demux_030_src0_ready), // src0.ready
.src0_valid (rsp_demux_030_src0_valid), // .valid
.src0_data (rsp_demux_030_src0_data), // .data
.src0_channel (rsp_demux_030_src0_channel), // .channel
.src0_startofpacket (rsp_demux_030_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_030_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_031 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_033_src_ready), // sink.ready
.sink_channel (router_033_src_channel), // .channel
.sink_data (router_033_src_data), // .data
.sink_startofpacket (router_033_src_startofpacket), // .startofpacket
.sink_endofpacket (router_033_src_endofpacket), // .endofpacket
.sink_valid (router_033_src_valid), // .valid
.src0_ready (rsp_demux_031_src0_ready), // src0.ready
.src0_valid (rsp_demux_031_src0_valid), // .valid
.src0_data (rsp_demux_031_src0_data), // .data
.src0_channel (rsp_demux_031_src0_channel), // .channel
.src0_startofpacket (rsp_demux_031_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_031_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_mux rsp_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src0_valid), // .valid
.sink6_channel (rsp_demux_006_src0_channel), // .channel
.sink6_data (rsp_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
.sink7_ready (rsp_demux_007_src0_ready), // sink7.ready
.sink7_valid (rsp_demux_007_src0_valid), // .valid
.sink7_channel (rsp_demux_007_src0_channel), // .channel
.sink7_data (rsp_demux_007_src0_data), // .data
.sink7_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
.sink8_ready (rsp_demux_008_src0_ready), // sink8.ready
.sink8_valid (rsp_demux_008_src0_valid), // .valid
.sink8_channel (rsp_demux_008_src0_channel), // .channel
.sink8_data (rsp_demux_008_src0_data), // .data
.sink8_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.sink8_endofpacket (rsp_demux_008_src0_endofpacket), // .endofpacket
.sink9_ready (rsp_demux_009_src0_ready), // sink9.ready
.sink9_valid (rsp_demux_009_src0_valid), // .valid
.sink9_channel (rsp_demux_009_src0_channel), // .channel
.sink9_data (rsp_demux_009_src0_data), // .data
.sink9_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
.sink9_endofpacket (rsp_demux_009_src0_endofpacket), // .endofpacket
.sink10_ready (rsp_demux_010_src0_ready), // sink10.ready
.sink10_valid (rsp_demux_010_src0_valid), // .valid
.sink10_channel (rsp_demux_010_src0_channel), // .channel
.sink10_data (rsp_demux_010_src0_data), // .data
.sink10_startofpacket (rsp_demux_010_src0_startofpacket), // .startofpacket
.sink10_endofpacket (rsp_demux_010_src0_endofpacket), // .endofpacket
.sink11_ready (rsp_demux_011_src0_ready), // sink11.ready
.sink11_valid (rsp_demux_011_src0_valid), // .valid
.sink11_channel (rsp_demux_011_src0_channel), // .channel
.sink11_data (rsp_demux_011_src0_data), // .data
.sink11_startofpacket (rsp_demux_011_src0_startofpacket), // .startofpacket
.sink11_endofpacket (rsp_demux_011_src0_endofpacket), // .endofpacket
.sink12_ready (rsp_demux_012_src0_ready), // sink12.ready
.sink12_valid (rsp_demux_012_src0_valid), // .valid
.sink12_channel (rsp_demux_012_src0_channel), // .channel
.sink12_data (rsp_demux_012_src0_data), // .data
.sink12_startofpacket (rsp_demux_012_src0_startofpacket), // .startofpacket
.sink12_endofpacket (rsp_demux_012_src0_endofpacket), // .endofpacket
.sink13_ready (rsp_demux_013_src0_ready), // sink13.ready
.sink13_valid (rsp_demux_013_src0_valid), // .valid
.sink13_channel (rsp_demux_013_src0_channel), // .channel
.sink13_data (rsp_demux_013_src0_data), // .data
.sink13_startofpacket (rsp_demux_013_src0_startofpacket), // .startofpacket
.sink13_endofpacket (rsp_demux_013_src0_endofpacket), // .endofpacket
.sink14_ready (rsp_demux_014_src0_ready), // sink14.ready
.sink14_valid (rsp_demux_014_src0_valid), // .valid
.sink14_channel (rsp_demux_014_src0_channel), // .channel
.sink14_data (rsp_demux_014_src0_data), // .data
.sink14_startofpacket (rsp_demux_014_src0_startofpacket), // .startofpacket
.sink14_endofpacket (rsp_demux_014_src0_endofpacket), // .endofpacket
.sink15_ready (rsp_demux_015_src0_ready), // sink15.ready
.sink15_valid (rsp_demux_015_src0_valid), // .valid
.sink15_channel (rsp_demux_015_src0_channel), // .channel
.sink15_data (rsp_demux_015_src0_data), // .data
.sink15_startofpacket (rsp_demux_015_src0_startofpacket), // .startofpacket
.sink15_endofpacket (rsp_demux_015_src0_endofpacket), // .endofpacket
.sink16_ready (rsp_demux_016_src0_ready), // sink16.ready
.sink16_valid (rsp_demux_016_src0_valid), // .valid
.sink16_channel (rsp_demux_016_src0_channel), // .channel
.sink16_data (rsp_demux_016_src0_data), // .data
.sink16_startofpacket (rsp_demux_016_src0_startofpacket), // .startofpacket
.sink16_endofpacket (rsp_demux_016_src0_endofpacket), // .endofpacket
.sink17_ready (rsp_demux_017_src0_ready), // sink17.ready
.sink17_valid (rsp_demux_017_src0_valid), // .valid
.sink17_channel (rsp_demux_017_src0_channel), // .channel
.sink17_data (rsp_demux_017_src0_data), // .data
.sink17_startofpacket (rsp_demux_017_src0_startofpacket), // .startofpacket
.sink17_endofpacket (rsp_demux_017_src0_endofpacket), // .endofpacket
.sink18_ready (rsp_demux_018_src0_ready), // sink18.ready
.sink18_valid (rsp_demux_018_src0_valid), // .valid
.sink18_channel (rsp_demux_018_src0_channel), // .channel
.sink18_data (rsp_demux_018_src0_data), // .data
.sink18_startofpacket (rsp_demux_018_src0_startofpacket), // .startofpacket
.sink18_endofpacket (rsp_demux_018_src0_endofpacket), // .endofpacket
.sink19_ready (rsp_demux_019_src0_ready), // sink19.ready
.sink19_valid (rsp_demux_019_src0_valid), // .valid
.sink19_channel (rsp_demux_019_src0_channel), // .channel
.sink19_data (rsp_demux_019_src0_data), // .data
.sink19_startofpacket (rsp_demux_019_src0_startofpacket), // .startofpacket
.sink19_endofpacket (rsp_demux_019_src0_endofpacket), // .endofpacket
.sink20_ready (rsp_demux_020_src0_ready), // sink20.ready
.sink20_valid (rsp_demux_020_src0_valid), // .valid
.sink20_channel (rsp_demux_020_src0_channel), // .channel
.sink20_data (rsp_demux_020_src0_data), // .data
.sink20_startofpacket (rsp_demux_020_src0_startofpacket), // .startofpacket
.sink20_endofpacket (rsp_demux_020_src0_endofpacket), // .endofpacket
.sink21_ready (rsp_demux_021_src0_ready), // sink21.ready
.sink21_valid (rsp_demux_021_src0_valid), // .valid
.sink21_channel (rsp_demux_021_src0_channel), // .channel
.sink21_data (rsp_demux_021_src0_data), // .data
.sink21_startofpacket (rsp_demux_021_src0_startofpacket), // .startofpacket
.sink21_endofpacket (rsp_demux_021_src0_endofpacket), // .endofpacket
.sink22_ready (rsp_demux_022_src0_ready), // sink22.ready
.sink22_valid (rsp_demux_022_src0_valid), // .valid
.sink22_channel (rsp_demux_022_src0_channel), // .channel
.sink22_data (rsp_demux_022_src0_data), // .data
.sink22_startofpacket (rsp_demux_022_src0_startofpacket), // .startofpacket
.sink22_endofpacket (rsp_demux_022_src0_endofpacket), // .endofpacket
.sink23_ready (rsp_demux_023_src0_ready), // sink23.ready
.sink23_valid (rsp_demux_023_src0_valid), // .valid
.sink23_channel (rsp_demux_023_src0_channel), // .channel
.sink23_data (rsp_demux_023_src0_data), // .data
.sink23_startofpacket (rsp_demux_023_src0_startofpacket), // .startofpacket
.sink23_endofpacket (rsp_demux_023_src0_endofpacket), // .endofpacket
.sink24_ready (rsp_demux_024_src0_ready), // sink24.ready
.sink24_valid (rsp_demux_024_src0_valid), // .valid
.sink24_channel (rsp_demux_024_src0_channel), // .channel
.sink24_data (rsp_demux_024_src0_data), // .data
.sink24_startofpacket (rsp_demux_024_src0_startofpacket), // .startofpacket
.sink24_endofpacket (rsp_demux_024_src0_endofpacket), // .endofpacket
.sink25_ready (rsp_demux_025_src0_ready), // sink25.ready
.sink25_valid (rsp_demux_025_src0_valid), // .valid
.sink25_channel (rsp_demux_025_src0_channel), // .channel
.sink25_data (rsp_demux_025_src0_data), // .data
.sink25_startofpacket (rsp_demux_025_src0_startofpacket), // .startofpacket
.sink25_endofpacket (rsp_demux_025_src0_endofpacket), // .endofpacket
.sink26_ready (rsp_demux_026_src0_ready), // sink26.ready
.sink26_valid (rsp_demux_026_src0_valid), // .valid
.sink26_channel (rsp_demux_026_src0_channel), // .channel
.sink26_data (rsp_demux_026_src0_data), // .data
.sink26_startofpacket (rsp_demux_026_src0_startofpacket), // .startofpacket
.sink26_endofpacket (rsp_demux_026_src0_endofpacket), // .endofpacket
.sink27_ready (rsp_demux_027_src0_ready), // sink27.ready
.sink27_valid (rsp_demux_027_src0_valid), // .valid
.sink27_channel (rsp_demux_027_src0_channel), // .channel
.sink27_data (rsp_demux_027_src0_data), // .data
.sink27_startofpacket (rsp_demux_027_src0_startofpacket), // .startofpacket
.sink27_endofpacket (rsp_demux_027_src0_endofpacket), // .endofpacket
.sink28_ready (rsp_demux_028_src0_ready), // sink28.ready
.sink28_valid (rsp_demux_028_src0_valid), // .valid
.sink28_channel (rsp_demux_028_src0_channel), // .channel
.sink28_data (rsp_demux_028_src0_data), // .data
.sink28_startofpacket (rsp_demux_028_src0_startofpacket), // .startofpacket
.sink28_endofpacket (rsp_demux_028_src0_endofpacket), // .endofpacket
.sink29_ready (rsp_demux_029_src0_ready), // sink29.ready
.sink29_valid (rsp_demux_029_src0_valid), // .valid
.sink29_channel (rsp_demux_029_src0_channel), // .channel
.sink29_data (rsp_demux_029_src0_data), // .data
.sink29_startofpacket (rsp_demux_029_src0_startofpacket), // .startofpacket
.sink29_endofpacket (rsp_demux_029_src0_endofpacket), // .endofpacket
.sink30_ready (rsp_demux_030_src0_ready), // sink30.ready
.sink30_valid (rsp_demux_030_src0_valid), // .valid
.sink30_channel (rsp_demux_030_src0_channel), // .channel
.sink30_data (rsp_demux_030_src0_data), // .data
.sink30_startofpacket (rsp_demux_030_src0_startofpacket), // .startofpacket
.sink30_endofpacket (rsp_demux_030_src0_endofpacket), // .endofpacket
.sink31_ready (rsp_demux_031_src0_ready), // sink31.ready
.sink31_valid (rsp_demux_031_src0_valid), // .valid
.sink31_channel (rsp_demux_031_src0_channel), // .channel
.sink31_data (rsp_demux_031_src0_data), // .data
.sink31_startofpacket (rsp_demux_031_src0_startofpacket), // .startofpacket
.sink31_endofpacket (rsp_demux_031_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_001_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_001_src1_valid), // .valid
.sink0_channel (rsp_demux_001_src1_channel), // .channel
.sink0_data (rsp_demux_001_src1_data), // .data
.sink0_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_002_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_002_src1_valid), // .valid
.sink1_channel (rsp_demux_002_src1_channel), // .channel
.sink1_data (rsp_demux_002_src1_data), // .data
.sink1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
endmodule
|
//-----------------------------------------------------------------------------------------
//-- txstr: Uart_tx example 2
//-- Transmission of string
//-- The reset signal is connected to the dtr signal (in file txstr.pcf)
//-- Fot this example to work is necessary to open a serial terminal (gtkterm for example)
//-- and deactivate DTR. Every time a reset is done, a string appears on the terminal
//-- Fixed BAUDRATE: 115200
//-----------------------------------------------------------------------------------------
//-- (C) BQ. December 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//-----------------------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
//-- Top entity
module txstr #(
parameter BAUDRATE = `B115200
)(
input wire clk, //-- System clock
input wire rstn, //-- Reset (active low)
output wire tx //-- Serial data output
);
//-- Serial Unit instantation
uart_tx #(
.BAUDRATE(BAUDRATE) //-- Set the baudrate
) TX0 (
.clk(clk),
.rstn(rstn),
.data(data),
.start(start),
.tx(tx),
.ready(ready)
);
//-- Connecting wires
wire ready;
reg start = 0;
reg [7:0] data;
//-- Multiplexer with the 8-character string to transmit
always @*
case (char_count)
8'd0: data <= "H";
8'd1: data <= "e";
8'd2: data <= "l";
8'd3: data <= "l";
8'd4: data <= "o";
8'd5: data <= "!";
8'd6: data <= ".";
8'd7: data <= ".";
default: data <= ".";
endcase
//-- Characters counter
//-- It only counts when the cena control signal is enabled
reg [2:0] char_count;
reg cena; //-- Counter enable
always @(posedge clk)
if (!rstn)
char_count = 0;
else if (cena)
char_count = char_count + 1;
//--------------------- CONTROLLER
localparam INI = 0;
localparam TXCAR = 1;
localparam NEXTCAR = 2;
localparam STOP = 3;
//-- fsm state
reg [1:0] state;
reg [1:0] next_state;
//-- Transition between states
always @(posedge clk) begin
if (!rstn)
state <= INI;
else
state <= next_state;
end
//-- Control signal generation and next states
always @(*) begin
next_state = state;
start = 0;
cena = 0;
case (state)
//-- Initial state. Start the trasmission
INI: begin
start = 1;
next_state = TXCAR;
end
//-- Wait until one car is transmitted
TXCAR: begin
if (ready)
next_state = NEXTCAR;
end
//-- Increment the character counter
//-- Finish when it is the last character
NEXTCAR: begin
cena = 1;
if (char_count == 7)
next_state = STOP;
else
next_state = INI;
end
endcase
end
endmodule
|
(** * Imp: Simple Imperative Programs *)
(** In this chapter, we begin a new direction that will continue for
the rest of the course. Up to now most of our attention has been
focused on various aspects of Coq itself, while from now on we'll
mostly be using Coq to formalize other things. (We'll continue to
pause from time to time to introduce a few additional aspects of
Coq.)
Our first case study is a _simple imperative programming language_
called Imp, embodying a tiny core fragment of conventional
mainstream languages such as C and Java. Here is a familiar
mathematical function written in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
*)
(** This chapter looks at how to define the _syntax_ and _semantics_
of Imp; the chapters that follow develop a theory of _program
equivalence_ and introduce _Hoare Logic_, a widely used logic for
reasoning about imperative programs. *)
(* ####################################################### *)
(** *** Sflib *)
(** A minor technical point: Instead of asking Coq to import our
earlier definitions from chapter [Logic], we import a small library
called [Sflib.v], containing just a few definitions and theorems
from earlier chapters that we'll actually use in the rest of the
course. This change should be nearly invisible, since most of what's
missing from Sflib has identical definitions in the Coq standard
library. The main reason for doing it is to tidy the global Coq
environment so that, for example, it is easier to search for
relevant theorems. *)
Require Export SfLib.
(* ####################################################### *)
(** * Arithmetic and Boolean Expressions *)
(** We'll present Imp in three parts: first a core language of
_arithmetic and boolean expressions_, then an extension of these
expressions with _variables_, and finally a language of _commands_
including assignment, conditions, sequencing, and loops. *)
(* ####################################################### *)
(** ** Syntax *)
Module AExp.
(** These two definitions specify the _abstract syntax_ of
arithmetic and boolean expressions. *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
(** In this chapter, we'll elide the translation from the
concrete syntax that a programmer would actually write to these
abstract syntax trees -- the process that, for example, would
translate the string ["1+2*3"] to the AST [APlus (ANum
1) (AMult (ANum 2) (ANum 3))]. The optional chapter [ImpParser]
develops a simple implementation of a lexical analyzer and parser
that can perform this translation. You do _not_ need to
understand that file to understand this one, but if you haven't
taken a course where these techniques are covered (e.g., a
compilers course) you may want to skim it. *)
(** *** *)
(** For comparison, here's a conventional BNF (Backus-Naur Form)
grammar defining the same abstract syntax:
a ::= nat
| a + a
| a - a
| a * a
b ::= true
| false
| a = a
| a <= a
| not b
| b and b
*)
(** Compared to the Coq version above...
- The BNF is more informal -- for example, it gives some
suggestions about the surface syntax of expressions (like the
fact that the addition operation is written [+] and is an
infix symbol) while leaving other aspects of lexical analysis
and parsing (like the relative precedence of [+], [-], and
[*]) unspecified. Some additional information -- and human
intelligence -- would be required to turn this description
into a formal definition (when implementing a compiler, for
example).
The Coq version consistently omits all this information and
concentrates on the abstract syntax only.
- On the other hand, the BNF version is lighter and
easier to read. Its informality makes it flexible, which is
a huge advantage in situations like discussions at the
blackboard, where conveying general ideas is more important
than getting every detail nailed down precisely.
Indeed, there are dozens of BNF-like notations and people
switch freely among them, usually without bothering to say which
form of BNF they're using because there is no need to: a
rough-and-ready informal understanding is all that's
needed. *)
(** It's good to be comfortable with both sorts of notations:
informal ones for communicating between humans and formal ones for
carrying out implementations and proofs. *)
(* ####################################################### *)
(** ** Evaluation *)
(** _Evaluating_ an arithmetic expression produces a number. *)
Fixpoint aeval (a : aexp) : nat :=
match a with
| ANum n => n
| APlus a1 a2 => (aeval a1) + (aeval a2)
| AMinus a1 a2 => (aeval a1) - (aeval a2)
| AMult a1 a2 => (aeval a1) * (aeval a2)
end.
Example test_aeval1:
aeval (APlus (ANum 2) (ANum 2)) = 4.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, evaluating a boolean expression yields a boolean. *)
Fixpoint beval (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval a1) (aeval a2)
| BLe a1 a2 => ble_nat (aeval a1) (aeval a2)
| BNot b1 => negb (beval b1)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
(* ####################################################### *)
(** ** Optimization *)
(** We haven't defined very much yet, but we can already get
some mileage out of the definitions. Suppose we define a function
that takes an arithmetic expression and slightly simplifies it,
changing every occurrence of [0+e] (i.e., [(APlus (ANum 0) e])
into just [e]. *)
Fixpoint optimize_0plus (a:aexp) : aexp :=
match a with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
(** To make sure our optimization is doing the right thing we
can test it on some examples and see if the output looks OK. *)
Example test_optimize_0plus:
optimize_0plus (APlus (ANum 2)
(APlus (ANum 0)
(APlus (ANum 0) (ANum 1))))
= APlus (ANum 2) (ANum 1).
Proof.
simpl. reflexivity.
Qed.
(** But if we want to be sure the optimization is correct --
i.e., that evaluating an optimized expression gives the same
result as the original -- we should prove it. *)
Theorem optimize_0plus_sound: forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a. induction a.
Case "ANum". simpl. reflexivity.
Case "APlus". destruct a1.
SCase "a1 = ANum". destruct n.
SSCase "n=0". simpl. assumption.
SSCase "n<>0". simpl. rewrite -> IHa2. reflexivity.
SCase "a1 = APlus a1_1 a1_2".
simpl. simpl in IHa1. rewrite -> IHa1. rewrite -> IHa2. reflexivity.
SCase "a1 = AMinus a1_1 a1_2".
simpl. simpl in IHa1. rewrite -> IHa1. rewrite -> IHa2. reflexivity.
SCase "a1 = AMult a1_1 a1_2".
simpl. simpl in IHa1. rewrite -> IHa1. rewrite -> IHa2. reflexivity.
SCase "AMinus". simpl. rewrite -> IHa1. rewrite -> IHa2. reflexivity.
SCase "AMult". simpl. rewrite -> IHa1. rewrite -> IHa2. reflexivity.
Qed.
(* ####################################################### *)
(** * Coq Automation *)
(** The repetition in this last proof is starting to be a little
annoying. If either the language of arithmetic expressions or the
optimization being proved sound were significantly more complex,
it would begin to be a real problem.
So far, we've been doing all our proofs using just a small handful
of Coq's tactics and completely ignoring its powerful facilities
for constructing parts of proofs automatically. This section
introduces some of these facilities, and we will see more over the
next several chapters. Getting used to them will take some
energy -- Coq's automation is a power tool -- but it will allow us
to scale up our efforts to more complex definitions and more
interesting properties without becoming overwhelmed by boring,
repetitive, low-level details. *)
(* ####################################################### *)
(** ** Tacticals *)
(** _Tacticals_ is Coq's term for tactics that take other tactics as
arguments -- "higher-order tactics," if you will. *)
(* ####################################################### *)
(** *** The [repeat] Tactical *)
(** The [repeat] tactical takes another tactic and keeps applying
this tactic until the tactic fails. Here is an example showing
that [100] is even using repeat. *)
Theorem ev100 : ev 100.
Proof.
repeat (apply ev_SS). apply ev_0.
Qed.
(** The [repeat T] tactic never fails; if the tactic [T] doesn't apply
to the original goal, then repeat still succeeds without changing
the original goal (it repeats zero times). *)
Theorem ev100' : ev 100.
Proof.
repeat (apply ev_0). repeat (apply ev_SS). repeat (apply ev_0).
Qed.
(** The [repeat T] tactic does not have any bound on the number of
times it applies [T]. If [T] is a tactic that always succeeds then
repeat [T] will loop forever (e.g. [repeat simpl] loops forever
since [simpl] always succeeds). While Coq's term language is
guaranteed to terminate, Coq's tactic language is not! *)
(* ####################################################### *)
(** *** The [try] Tactical *)
(** If [T] is a tactic, then [try T] is a tactic that is just like [T]
except that, if [T] fails, [try T] _successfully_ does nothing at
all (instead of failing). *)
Theorem silly1 : forall ae, aeval ae = aeval ae.
Proof.
try reflexivity.
Qed.
Theorem silly2 : forall (P : Prop), P -> P.
Proof.
intros.
try reflexivity.
assumption.
Qed.
(** Using [try] in a completely manual proof is a bit silly, but
we'll see below that [try] is very useful for doing automated
proofs in conjunction with the [;] tactical. *)
(* ####################################################### *)
(** *** The [;] Tactical (Simple Form) *)
(** In its most commonly used form, the [;] tactical takes two tactics
as argument: [T;T'] first performs the tactic [T] and then
performs the tactic [T'] on _each subgoal_ generated by [T]. *)
(** For example, consider the following trivial lemma: *)
Lemma foo : forall n, ble_nat 0 n = true.
Proof.
intros. destruct n.
Case "n=0". reflexivity.
Case "n<>0". reflexivity.
Qed.
(** We can simplify this proof using the [;] tactical: *)
Lemma foo' : forall n, ble_nat 0 n = true.
Proof.
(* intros. destruct n; simpl; reflexivity. *)
intros.
destruct n; (* [destruct] the current goal *)
simpl; (* then [simpl] each resulting subgoal *)
reflexivity. (* and do [reflexivity] on each resulting subgoal *)
Qed.
(** Using [try] and [;] together, we can get rid of the repetition in
the proof that was bothering us a little while ago. *)
Theorem optimize_0plus_sound': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
(* The remaining cases -- ANum and APlus -- are different *)
Case "ANum". reflexivity.
Case "APlus".
destruct a1;
(* Again, most cases follow directly by the IH *)
try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
(* The interesting case, on which the [try...] does nothing,
is when [e1 = ANum n]. In this case, we have to destruct
[n] (to see whether the optimization applies) and rewrite
with the induction hypothesis. *)
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity.
Qed.
(** Coq experts often use this "[...; try... ]" idiom after a tactic
like [induction] to take care of many similar cases all at once.
Naturally, this practice has an analog in informal proofs.
Here is an informal proof of this theorem that matches the
structure of the formal one:
_Theorem_: For all arithmetic expressions [a],
aeval (optimize_0plus a) = aeval a.
_Proof_: By induction on [a]. The [AMinus] and [AMult] cases
follow directly from the IH. The remaining cases are as follows:
- Suppose [a = ANum n] for some [n]. We must show
aeval (optimize_0plus (ANum n)) = aeval (ANum n).
This is immediate from the definition of [optimize_0plus].
- Suppose [a = APlus a1 a2] for some [a1] and [a2]. We
must show
aeval (optimize_0plus (APlus a1 a2))
= aeval (APlus a1 a2).
Consider the possible forms of [a1]. For most of them,
[optimize_0plus] simply calls itself recursively for the
subexpressions and rebuilds a new expression of the same form
as [a1]; in these cases, the result follows directly from the
IH.
The interesting case is when [a1 = ANum n] for some [n].
If [n = ANum 0], then
optimize_0plus (APlus a1 a2) = optimize_0plus a2
and the IH for [a2] is exactly what we need. On the other
hand, if [n = S n'] for some [n'], then again [optimize_0plus]
simply calls itself recursively, and the result follows from
the IH. [] *)
(** This proof can still be improved: the first case (for [a = ANum
n]) is very trivial -- even more trivial than the cases that we
said simply followed from the IH -- yet we have chosen to write it
out in full. It would be better and clearer to drop it and just
say, at the top, "Most cases are either immediate or direct from
the IH. The only interesting case is the one for [APlus]..." We
can make the same improvement in our formal proof too. Here's how
it looks: *)
Theorem optimize_0plus_sound'': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
(* ... or are immediate by definition *)
try reflexivity.
(* The interesting case is when a = APlus a1 a2. *)
Case "APlus".
destruct a1; try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(* ####################################################### *)
(** *** The [;] Tactical (General Form) *)
(** The [;] tactical has a more general than the simple [T;T'] we've
seen above, which is sometimes also useful. If [T], [T1], ...,
[Tn] are tactics, then
T; [T1 | T2 | ... | Tn]
is a tactic that first performs [T] and then performs [T1] on the
first subgoal generated by [T], performs [T2] on the second
subgoal, etc.
So [T;T'] is just special notation for the case when all of the
[Ti]'s are the same tactic; i.e. [T;T'] is just a shorthand for:
T; [T' | T' | ... | T']
*)
(* ####################################################### *)
(** ** Defining New Tactic Notations *)
(** Coq also provides several ways of "programming" tactic scripts.
- The [Tactic Notation] idiom illustrated below gives a handy
way to define "shorthand tactics" that bundle several tactics
into a single command.
- For more sophisticated programming, Coq offers a small
built-in programming language called [Ltac] with primitives
that can examine and modify the proof state. The details are
a bit too complicated to get into here (and it is generally
agreed that [Ltac] is not the most beautiful part of Coq's
design!), but they can be found in the reference manual, and
there are many examples of [Ltac] definitions in the Coq
standard library that you can use as examples.
- There is also an OCaml API, which can be used to build tactics
that access Coq's internal structures at a lower level, but
this is seldom worth the trouble for ordinary Coq users.
The [Tactic Notation] mechanism is the easiest to come to grips with,
and it offers plenty of power for many purposes. Here's an example.
*)
Tactic Notation "simpl_and_try" tactic(c) :=
simpl;
try c.
(** This defines a new tactical called [simpl_and_try] which
takes one tactic [c] as an argument, and is defined to be
equivalent to the tactic [simpl; try c]. For example, writing
"[simpl_and_try reflexivity.]" in a proof would be the same as
writing "[simpl; try reflexivity.]" *)
(** The next subsection gives a more sophisticated use of this
feature... *)
(* ####################################################### *)
(** *** Bulletproofing Case Analyses *)
(** Being able to deal with most of the cases of an [induction]
or [destruct] all at the same time is very convenient, but it can
also be a little confusing. One problem that often comes up is
that _maintaining_ proofs written in this style can be difficult.
For example, suppose that, later, we extended the definition of
[aexp] with another constructor that also required a special
argument. The above proof might break because Coq generated the
subgoals for this constructor before the one for [APlus], so that,
at the point when we start working on the [APlus] case, Coq is
actually expecting the argument for a completely different
constructor. What we'd like is to get a sensible error message
saying "I was expecting the [AFoo] case at this point, but the
proof script is talking about [APlus]." Here's a nice trick (due
to Aaron Bohannon) that smoothly achieves this. *)
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** ([Case_aux] implements the common functionality of [Case],
[SCase], [SSCase], etc. For example, [Case "foo"] is defined as
[Case_aux Case "foo".) *)
(** For example, if [a] is a variable of type [aexp], then doing
aexp_cases (induction a) Case
will perform an induction on [a] (the same as if we had just typed
[induction a]) and _also_ add a [Case] tag to each subgoal
generated by the [induction], labeling which constructor it comes
from. For example, here is yet another proof of
[optimize_0plus_sound], using [aexp_cases]: *)
Theorem optimize_0plus_sound''': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
aexp_cases (induction a) Case;
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
try reflexivity.
(* At this point, there is already an ["APlus"] case name
in the context. The [Case "APlus"] here in the proof
text has the effect of a sanity check: if the "Case"
string in the context is anything _other_ than ["APlus"]
(for example, because we added a clause to the definition
of [aexp] and forgot to change the proof) we'll get a
helpful error at this point telling us that this is now
the wrong case. *)
Case "APlus".
aexp_cases (destruct a1) SCase;
try (simpl; simpl in IHa1;
rewrite IHa1; rewrite IHa2; reflexivity).
SCase "ANum". destruct n;
simpl; rewrite IHa2; reflexivity.
Qed.
(** **** Exercise: 3 stars (optimize_0plus_b) *)
(** Since the [optimize_0plus] tranformation doesn't change the value
of [aexp]s, we should be able to apply it to all the [aexp]s that
appear in a [bexp] without changing the [bexp]'s value. Write a
function which performs that transformation on [bexp]s, and prove
it is sound. Use the tacticals we've just seen to make the proof
as elegant as possible. *)
Fixpoint optimize_0plus_b (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 => BEq (optimize_0plus a1) (optimize_0plus a2)
| BLe a1 a2 => BLe (optimize_0plus a1) (optimize_0plus a2)
| BNot b1 => BNot (optimize_0plus_b b1)
| BAnd b1 b2 => BAnd (optimize_0plus_b b1) (optimize_0plus_b b2)
end.
Theorem optimize_0plus_b_sound_test : forall b,
beval (optimize_0plus_b b) = beval b.
Proof.
intros b. induction b.
Case "b=BTrue". reflexivity.
Case "b=BFalse". reflexivity.
Case "b=BEq a a0". simpl. rewrite -> optimize_0plus_sound. rewrite -> optimize_0plus_sound. reflexivity.
Case "b=Ble a a0". simpl. rewrite -> optimize_0plus_sound. rewrite -> optimize_0plus_sound. reflexivity.
Case "b=BNot b". simpl. rewrite -> IHb. reflexivity.
Case "BAnd b1 b2". simpl. rewrite -> IHb1. rewrite -> IHb2. reflexivity.
Qed.
Theorem optimize_0plus_b_sound : forall b,
beval (optimize_0plus_b b) = beval b.
Proof.
intros b.
induction b;
try reflexivity;
try (simpl; rewrite optimize_0plus_sound; rewrite optimize_0plus_sound; reflexivity).
simpl; rewrite -> IHb; reflexivity.
simpl; rewrite -> IHb1; rewrite -> IHb2; reflexivity.
Qed.
(** **** Exercise: 4 stars, optional (optimizer) *)
(** _Design exercise_: The optimization implemented by our
[optimize_0plus] function is only one of many imaginable
optimizations on arithmetic and boolean expressions. Write a more
sophisticated optimizer and prove it correct.
*)
Fixpoint optimize_amore (a:aexp) : aexp :=
match a with
| ANum n => ANum n
| APlus (ANum 0) e2 => optimize_amore e2
| APlus e1 (ANum 0) => optimize_amore e1
| APlus e1 e2 => APlus (optimize_amore e1) (optimize_amore e2)
| AMinus e1 e2 => AMinus (optimize_amore e1) (optimize_amore e2)
| AMult e1 e2 => AMult (optimize_amore e1) (optimize_amore e2)
end.
(* ####################################################### *)
(** ** The [omega] Tactic *)
(** The [omega] tactic implements a decision procedure for a subset of
first-order logic called _Presburger arithmetic_. It is based on
the Omega algorithm invented in 1992 by William Pugh.
If the goal is a universally quantified formula made out of
- numeric constants, addition ([+] and [S]), subtraction ([-]
and [pred]), and multiplication by constants (this is what
makes it Presburger arithmetic),
- equality ([=] and [<>]) and inequality ([<=]), and
- the logical connectives [/\], [\/], [~], and [->],
then invoking [omega] will either solve the goal or tell you that
it is actually false. *)
Example silly_presburger_example : forall m n o p,
m + n <= n + o /\ o + 3 = p + 3 ->
m <= p.
Proof.
intros. omega.
Qed.
(** Leibniz wrote, "It is unworthy of excellent men to lose
hours like slaves in the labor of calculation which could be
relegated to anyone else if machines were used." We recommend
using the omega tactic whenever possible. *)
(* ####################################################### *)
(** ** A Few More Handy Tactics *)
(** Finally, here are some miscellaneous tactics that you may find
convenient.
- [clear H]: Delete hypothesis [H] from the context.
- [subst x]: Find an assumption [x = e] or [e = x] in the
context, replace [x] with [e] throughout the context and
current goal, and clear the assumption.
- [subst]: Substitute away _all_ assumptions of the form [x = e]
or [e = x].
- [rename... into...]: Change the name of a hypothesis in the
proof context. For example, if the context includes a variable
named [x], then [rename x into y] will change all occurrences
of [x] to [y].
- [assumption]: Try to find a hypothesis [H] in the context that
exactly matches the goal; if one is found, behave just like
[apply H].
- [contradiction]: Try to find a hypothesis [H] in the current
context that is logically equivalent to [False]. If one is
found, solve the goal.
- [constructor]: Try to find a constructor [c] (from some
[Inductive] definition in the current environment) that can be
applied to solve the current goal. If one is found, behave
like [apply c]. *)
(** We'll see many examples of these in the proofs below. *)
(* ####################################################### *)
(** * Evaluation as a Relation *)
(** We have presented [aeval] and [beval] as functions defined by
[Fixpoints]. Another way to think about evaluation -- one that we
will see is often more flexible -- is as a _relation_ between
expressions and their values. This leads naturally to [Inductive]
definitions like the following one for arithmetic
expressions... *)
Module aevalR_first_try.
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n: nat),
aevalR (ANum n) n
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus: forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMult e1 e2) (n1 * n2).
(** As is often the case with relations, we'll find it
convenient to define infix notation for [aevalR]. We'll write [e
|| n] to mean that arithmetic expression [e] evaluates to value
[n]. (This notation is one place where the limitation to ASCII
symbols becomes a little bothersome. The standard notation for
the evaluation relation is a double down-arrow. We'll typeset it
like this in the HTML version of the notes and use a double
vertical bar as the closest approximation in [.v] files.) *)
Notation "e '||' n" := (aevalR e n) : type_scope.
End aevalR_first_try.
(** In fact, Coq provides a way to use this notation in the definition
of [aevalR] itself. This avoids situations where we're working on
a proof involving statements in the form [e || n] but we have to
refer back to a definition written using the form [aevalR e n].
We do this by first "reserving" the notation, then giving the
definition together with a declaration of what the notation
means. *)
Reserved Notation "e '||' n" (at level 50, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (APlus e1 e2) || (n1 + n2)
| E_AMinus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMinus e1 e2) || (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMult e1 e2) || (n1 * n2)
where "e '||' n" := (aevalR e n) : type_scope.
Tactic Notation "aevalR_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_ANum" | Case_aux c "E_APlus"
| Case_aux c "E_AMinus" | Case_aux c "E_AMult" ].
(* ####################################################### *)
(** ** Inference Rule Notation *)
(** In informal discussions, it is convenient to write the rules for
[aevalR] and similar relations in the more readable graphical form
of _inference rules_, where the premises above the line justify
the conclusion below the line (we have already seen them in the
Prop chapter). *)
(** For example, the constructor [E_APlus]...
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
...would be written like this as an inference rule:
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
*)
(** Formally, there is nothing very deep about inference rules:
they are just implications. You can read the rule name on the
right as the name of the constructor and read each of the
linebreaks between the premises above the line and the line itself
as [->]. All the variables mentioned in the rule ([e1], [n1],
etc.) are implicitly bound by universal quantifiers at the
beginning. (Such variables are often called _metavariables_ to
distinguish them from the variables of the language we are
defining. At the moment, our arithmetic expressions don't include
variables, but we'll soon be adding them.) The whole collection
of rules is understood as being wrapped in an [Inductive]
declaration (informally, this is either elided or else indicated
by saying something like "Let [aevalR] be the smallest relation
closed under the following rules..."). *)
(** For example, [||] is the smallest relation closed under these
rules:
----------- (E_ANum)
ANum n || n
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
e1 || n1
e2 || n2
--------------------- (E_AMinus)
AMinus e1 e2 || n1-n2
e1 || n1
e2 || n2
-------------------- (E_AMult)
AMult e1 e2 || n1*n2
*)
(* ####################################################### *)
(** ** Equivalence of the Definitions *)
(** It is straightforward to prove that the relational and functional
definitions of evaluation agree on all possible arithmetic
expressions... *)
Theorem aeval_iff_aevalR : forall a n,
(a || n) <-> aeval a = n.
Proof.
split.
Case "=>". intros H.
aexp_cases (induction H) SCases; try simpl.
SCase "a = ANum n". reflexivity.
SCase "a = APlus e1 e2". rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "a = AMinus e1 e2". rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "a = AMult e1 e2". rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
Case "<=". intros H.
aexp_cases (induction a) SCases; try simpl.
SCase "a = ANum n0". simpl.
split.
Case "->".
intros H.
aevalR_cases (induction H) SCase; simpl.
SCase "E_ANum".
reflexivity.
SCase "E_APlus".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "E_AMinus".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "E_AMult".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
Case "<-".
generalize dependent n.
aexp_cases (induction a) SCase; simpl; intros; subst.
SCase "ANum".
apply E_ANum.
SCase "APlus".
apply E_APlus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
SCase "AMinus".
apply E_AMinus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
SCase "AMult".
apply E_AMult.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
Qed.
(** Note: if you're reading the HTML file, you'll see an empty square box instead
of a proof for this theorem.
You can click on this box to "unfold" the text to see the proof.
Click on the unfolded to text to "fold" it back up to a box. We'll be using
this style frequently from now on to help keep the HTML easier to read.
The full proofs always appear in the .v files. *)
(** We can make the proof quite a bit shorter by making more
use of tacticals... *)
Theorem aeval_iff_aevalR' : forall a n,
(a || n) <-> aeval a = n.
Proof.
(* WORKED IN CLASS *)
split.
Case "->".
intros H; induction H; subst; reflexivity.
Case "<-".
generalize dependent n.
induction a; simpl; intros; subst; constructor;
try apply IHa1; try apply IHa2; reflexivity.
Qed.
(** **** Exercise: 3 stars (bevalR) *)
(** Write a relation [bevalR] in the same style as
[aevalR], and prove that it is equivalent to [beval].*)
(*
Inductive bevalR:
(* FILL IN HERE *)
*)
(** [] *)
End AExp.
(* ####################################################### *)
(** ** Computational vs. Relational Definitions *)
(** For the definitions of evaluation for arithmetic and boolean
expressions, the choice of whether to use functional or relational
definitions is mainly a matter of taste. In general, Coq has
somewhat better support for working with relations. On the other
hand, in some sense function definitions carry more information,
because functions are necessarily deterministic and defined on all
arguments; for a relation we have to show these properties
explicitly if we need them. Functions also take advantage of Coq's
computations mechanism.
However, there are circumstances where relational definitions of
evaluation are preferable to functional ones. *)
Module aevalR_division.
(** For example, suppose that we wanted to extend the arithmetic
operations by considering also a division operation:*)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp
| ADiv : aexp -> aexp -> aexp. (* <--- new *)
(** Extending the definition of [aeval] to handle this new operation
would not be straightforward (what should we return as the result
of [ADiv (ANum 5) (ANum 0)]?). But extending [aevalR] is
straightforward. *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
| E_ADiv : forall (a1 a2: aexp) (n1 n2 n3: nat),
(a1 || n1) -> (a2 || n2) -> (mult n2 n3 = n1) -> (ADiv a1 a2) || n3
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_division.
Module aevalR_extended.
(** Suppose, instead, that we want to extend the arithmetic operations
by a nondeterministic number generator [any]:*)
Inductive aexp : Type :=
| AAny : aexp (* <--- NEW *)
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
(** Again, extending [aeval] would be tricky (because evaluation is
_not_ a deterministic function from expressions to numbers), but
extending [aevalR] is no problem: *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_Any : forall (n:nat),
AAny || n (* <--- new *)
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_extended.
(** * Expressions With Variables *)
(** Let's turn our attention back to defining Imp. The next thing we
need to do is to enrich our arithmetic and boolean expressions
with variables. To keep things simple, we'll assume that all
variables are global and that they only hold numbers. *)
(* ##################################################### *)
(** ** Identifiers *)
(** To begin, we'll need to formalize _identifiers_ such as program
variables. We could use strings for this -- or, in a real
compiler, fancier structures like pointers into a symbol table.
But for simplicity let's just use natural numbers as identifiers. *)
(** (We hide this section in a module because these definitions are
actually in [SfLib], but we want to repeat them here so that we
can explain them.) *)
Module Id.
(** We define a new inductive datatype [Id] so that we won't confuse
identifiers and numbers. We use [sumbool] to define a computable
equality operator on [Id]. *)
Inductive id : Type :=
Id : nat -> id.
Theorem eq_id_dec : forall id1 id2 : id, {id1 = id2} + {id1 <> id2}.
Proof.
intros id1 id2.
destruct id1 as [n1]. destruct id2 as [n2].
destruct (eq_nat_dec n1 n2) as [Heq | Hneq].
Case "n1 = n2".
left. rewrite Heq. reflexivity.
Case "n1 <> n2".
right. intros contra. inversion contra. apply Hneq. apply H0.
Defined.
(** The following lemmas will be useful for rewriting terms involving [eq_id_dec]. *)
Lemma eq_id : forall (T:Type) x (p q:T),
(if eq_id_dec x x then p else q) = p.
Proof.
intros.
destruct (eq_id_dec x x).
Case "x = x".
reflexivity.
Case "x <> x (impossible)".
apply ex_falso_quodlibet; apply n; reflexivity. Qed.
(** **** Exercise: 1 star, optional (neq_id) *)
Lemma neq_id : forall (T:Type) x y (p q:T), x <> y ->
(if eq_id_dec x y then p else q) = q.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Id.
(* ####################################################### *)
(** ** States *)
(** A _state_ represents the current values of _all_ the variables at
some point in the execution of a program. *)
(** For simplicity (to avoid dealing with partial functions), we
let the state be defined for _all_ variables, even though any
given program is only going to mention a finite number of them.
The state captures all of the information stored in memory. For Imp
programs, because each variable stores only a natural number, we
can represent the state as a mapping from identifiers to [nat].
For more complex programming languages, the state might have more
structure.
*)
Definition state := id -> nat.
Definition empty_state : state :=
fun _ => 0.
Definition update (st : state) (x : id) (n : nat) : state :=
fun x' => if eq_id_dec x x' then n else st x'.
(** For proofs involving states, we'll need several simple properties
of [update]. *)
(** **** Exercise: 1 star (update_eq) *)
Theorem update_eq : forall n x st,
(update st x n) x = n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (update_neq) *)
Theorem update_neq : forall x2 x1 n st,
x2 <> x1 ->
(update st x2 n) x1 = (st x1).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (update_example) *)
(** Before starting to play with tactics, make sure you understand
exactly what the theorem is saying! *)
Theorem update_example : forall (n:nat),
(update empty_state (Id 2) n) (Id 3) = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (update_shadow) *)
Theorem update_shadow : forall n1 n2 x1 x2 (st : state),
(update (update st x2 n1) x2 n2) x1 = (update st x2 n2) x1.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (update_same) *)
Theorem update_same : forall n1 x1 x2 (st : state),
st x1 = n1 ->
(update st x1 n1) x2 = st x2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (update_permute) *)
Theorem update_permute : forall n1 n2 x1 x2 x3 st,
x2 <> x1 ->
(update (update st x2 n1) x1 n2) x3 = (update (update st x1 n2) x2 n1) x3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################### *)
(** ** Syntax *)
(** We can add variables to the arithmetic expressions we had before by
simply adding one more constructor: *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| AId : id -> aexp (* <----- NEW *)
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "AId" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** Defining a few variable names as notational shorthands will make
examples easier to read: *)
Definition X : id := Id 0.
Definition Y : id := Id 1.
Definition Z : id := Id 2.
(** (This convention for naming program variables ([X], [Y],
[Z]) clashes a bit with our earlier use of uppercase letters for
types. Since we're not using polymorphism heavily in this part of
the course, this overloading should not cause confusion.) *)
(** The definition of [bexp]s is the same as before (using the new
[aexp]s): *)
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
Tactic Notation "bexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "BTrue" | Case_aux c "BFalse" | Case_aux c "BEq"
| Case_aux c "BLe" | Case_aux c "BNot" | Case_aux c "BAnd" ].
(* ################################################### *)
(** ** Evaluation *)
(** The arith and boolean evaluators can be extended to handle
variables in the obvious way: *)
Fixpoint aeval (st : state) (a : aexp) : nat :=
match a with
| ANum n => n
| AId x => st x (* <----- NEW *)
| APlus a1 a2 => (aeval st a1) + (aeval st a2)
| AMinus a1 a2 => (aeval st a1) - (aeval st a2)
| AMult a1 a2 => (aeval st a1) * (aeval st a2)
end.
Fixpoint beval (st : state) (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval st a1) (aeval st a2)
| BLe a1 a2 => ble_nat (aeval st a1) (aeval st a2)
| BNot b1 => negb (beval st b1)
| BAnd b1 b2 => andb (beval st b1) (beval st b2)
end.
Example aexp1 :
aeval (update empty_state X 5)
(APlus (ANum 3) (AMult (AId X) (ANum 2)))
= 13.
Proof. reflexivity. Qed.
Example bexp1 :
beval (update empty_state X 5)
(BAnd BTrue (BNot (BLe (AId X) (ANum 4))))
= true.
Proof. reflexivity. Qed.
(* ####################################################### *)
(** * Commands *)
(** Now we are ready define the syntax and behavior of Imp
_commands_ (often called _statements_). *)
(* ################################################### *)
(** ** Syntax *)
(** Informally, commands [c] are described by the following BNF
grammar:
c ::= SKIP
| x ::= a
| c ;; c
| WHILE b DO c END
| IFB b THEN c ELSE c FI
]]
*)
(**
For example, here's the factorial function in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
When this command terminates, the variable [Y] will contain the
factorial of the initial value of [X].
*)
(** Here is the formal definition of the syntax of commands: *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";;"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
(** As usual, we can use a few [Notation] declarations to make things
more readable. We need to be a bit careful to avoid conflicts
with Coq's built-in notations, so we'll keep this light -- in
particular, we won't introduce any notations for [aexps] and
[bexps] to avoid confusion with the numerical and boolean
operators we've already defined. We use the keyword [IFB] for
conditionals instead of [IF], for similar reasons. *)
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** For example, here is the factorial function again, written as a
formal definition to Coq: *)
Definition fact_in_coq : com :=
Z ::= AId X;;
Y ::= ANum 1;;
WHILE BNot (BEq (AId Z) (ANum 0)) DO
Y ::= AMult (AId Y) (AId Z);;
Z ::= AMinus (AId Z) (ANum 1)
END.
(* ####################################################### *)
(** ** Examples *)
(** Assignment: *)
Definition plus2 : com :=
X ::= (APlus (AId X) (ANum 2)).
Definition XtimesYinZ : com :=
Z ::= (AMult (AId X) (AId Y)).
Definition subtract_slowly_body : com :=
Z ::= AMinus (AId Z) (ANum 1) ;;
X ::= AMinus (AId X) (ANum 1).
(** *** Loops *)
Definition subtract_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
subtract_slowly_body
END.
Definition subtract_3_from_5_slowly : com :=
X ::= ANum 3 ;;
Z ::= ANum 5 ;;
subtract_slowly.
(** *** An infinite loop: *)
Definition loop : com :=
WHILE BTrue DO
SKIP
END.
(* ################################################################ *)
(** * Evaluation *)
(** Next we need to define what it means to evaluate an Imp command.
The fact that [WHILE] loops don't necessarily terminate makes defining
an evaluation function tricky... *)
(* #################################### *)
(** ** Evaluation as a Function (Failed Attempt) *)
(** Here's an attempt at defining an evaluation function for commands,
omitting the [WHILE] case. *)
Fixpoint ceval_fun_no_while (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| x ::= a1 =>
update st x (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_fun_no_while st c1 in
ceval_fun_no_while st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_fun_no_while st c1
else ceval_fun_no_while st c2
| WHILE b DO c END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the [WHILE] case as follows:
<<
Fixpoint ceval_fun (st : state) (c : com) : state :=
match c with
...
| WHILE b DO c END =>
if (beval st b1)
then ceval_fun st (c1; WHILE b DO c END)
else st
end.
>>
Coq doesn't accept such a definition ("Error: Cannot guess
decreasing argument of fix") because the function we want to
define is not guaranteed to terminate. Indeed, it doesn't always
terminate: for example, the full version of the [ceval_fun]
function applied to the [loop] program above would never
terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is
an (invalid!) Coq program showing what would go wrong if Coq
allowed non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become provable
(e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_fun] cannot be written in Coq -- at least not without
additional tricks (see chapter [ImpCEvalFun] if curious). *)
(* #################################### *)
(** ** Evaluation as a Relation *)
(** Here's a better way: we define [ceval] as a _relation_ rather than
a _function_ -- i.e., we define it in [Prop] instead of [Type], as
we did for [aevalR] above. *)
(** This is an important change. Besides freeing us from the awkward
workarounds that would be needed to define evaluation as a
function, it gives us a lot more flexibility in the definition.
For example, if we added concurrency features to the language,
we'd want the definition of evaluation to be non-deterministic --
i.e., not only would it not be total, it would not even be a
partial function! *)
(** We'll use the notation [c / st || st'] for our [ceval] relation:
[c / st || st'] means that executing program [c] in a starting
state [st] results in an ending state [st']. This can be
pronounced "[c] takes state [st] to [st']".
*)
(** *** Operational Semantics
---------------- (E_Skip)
SKIP / st || st
aeval st a1 = n
-------------------------------- (E_Ass)
x := a1 / st || (update st x n)
c1 / st || st'
c2 / st' || st''
------------------- (E_Seq)
c1;;c2 / st || st''
beval st b1 = true
c1 / st || st'
------------------------------------- (E_IfTrue)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
c2 / st || st'
------------------------------------- (E_IfFalse)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
------------------------------ (E_WhileEnd)
WHILE b DO c END / st || st
beval st b1 = true
c / st || st'
WHILE b DO c END / st' || st''
--------------------------------- (E_WhileLoop)
WHILE b DO c END / st || st''
*)
(** Here is the formal definition. (Make sure you understand
how it corresponds to the inference rules.) *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
SKIP / st || st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
(x ::= a1) / st || (update st x n)
| E_Seq : forall c1 c2 st st' st'',
c1 / st || st' ->
c2 / st' || st'' ->
(c1 ;; c2) / st || st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
c1 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
c2 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall b st c,
beval st b = false ->
(WHILE b DO c END) / st || st
| E_WhileLoop : forall st st' st'' b c,
beval st b = true ->
c / st || st' ->
(WHILE b DO c END) / st' || st'' ->
(WHILE b DO c END) / st || st''
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop" ].
(** *** *)
(** The cost of defining evaluation as a relation instead of a
function is that we now need to construct _proofs_ that some
program evaluates to some result state, rather than just letting
Coq's computation mechanism do it for us. *)
Example ceval_example1:
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)
/ empty_state
|| (update (update empty_state X 2) Z 4).
Proof.
(* We must supply the intermediate state *)
apply E_Seq with (update empty_state X 2).
Case "assignment command".
apply E_Ass. reflexivity.
Case "if command".
apply E_IfFalse.
reflexivity.
apply E_Ass. reflexivity. Qed.
(** **** Exercise: 2 stars (ceval_example2) *)
Example ceval_example2:
(X ::= ANum 0;; Y ::= ANum 1;; Z ::= ANum 2) / empty_state ||
(update (update (update empty_state X 0) Y 1) Z 2).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y].
Prove that this program executes as intended for X = 2
(this latter part is trickier than you might expect). *)
Definition pup_to_n : com :=
(* FILL IN HERE *) admit.
Theorem pup_to_2_ceval :
pup_to_n / (update empty_state X 2) ||
update (update (update (update (update (update empty_state
X 2) Y 0) Y 2) X 1) Y 3) X 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** ** Determinism of Evaluation *)
(** Changing from a computational to a relational definition of
evaluation is a good move because it allows us to escape from the
artificial requirement (imposed by Coq's restrictions on
[Fixpoint] definitions) that evaluation should be a total
function. But it also raises a question: Is the second definition
of evaluation actually a partial function? That is, is it
possible that, beginning from the same state [st], we could
evaluate some command [c] in different ways to reach two different
output states [st'] and [st'']?
In fact, this cannot happen: [ceval] is a partial function.
Here's the proof: *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
ceval_cases (induction E1) Case;
intros st2 E2; inversion E2; subst.
Case "E_Skip". reflexivity.
Case "E_Ass". reflexivity.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Case "E_IfTrue".
SCase "b1 evaluates to true".
apply IHE1. assumption.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
SCase "b1 evaluates to false".
apply IHE1. assumption.
Case "E_WhileEnd".
SCase "b1 evaluates to false".
reflexivity.
SCase "b1 evaluates to true (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b1 evaluates to false (contradiction)".
rewrite H in H4. inversion H4.
SCase "b1 evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption. Qed.
(* ####################################################### *)
(** * Reasoning About Imp Programs *)
(** We'll get much deeper into systematic techniques for reasoning
about Imp programs in the following chapters, but we can do quite
a bit just working with the bare definitions. *)
(* This section explores some examples. *)
Theorem plus2_spec : forall st n st',
st X = n ->
plus2 / st || st' ->
st' X = n + 2.
Proof.
intros st n st' HX Heval.
(* Inverting Heval essentially forces Coq to expand one
step of the ceval computation - in this case revealing
that st' must be st extended with the new value of X,
since plus2 is an assignment *)
inversion Heval. subst. clear Heval. simpl.
apply update_eq. Qed.
(** **** Exercise: 3 stars (XtimesYinZ_spec) *)
(** State and prove a specification of [XtimesYinZ]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (loop_never_stops) *)
Theorem loop_never_stops : forall st st',
~(loop / st || st').
Proof.
intros st st' contra. unfold loop in contra.
remember (WHILE BTrue DO SKIP END) as loopdef eqn:Heqloopdef.
(* Proceed by induction on the assumed derivation showing that
[loopdef] terminates. Most of the cases are immediately
contradictory (and so can be solved in one step with
[inversion]). *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (no_whilesR) *)
(** Consider the definition of the [no_whiles] property below: *)
Fixpoint no_whiles (c : com) : bool :=
match c with
| SKIP => true
| _ ::= _ => true
| c1 ;; c2 => andb (no_whiles c1) (no_whiles c2)
| IFB _ THEN ct ELSE cf FI => andb (no_whiles ct) (no_whiles cf)
| WHILE _ DO _ END => false
end.
(** This property yields [true] just on programs that
have no while loops. Using [Inductive], write a property
[no_whilesR] such that [no_whilesR c] is provable exactly when [c]
is a program with no while loops. Then prove its equivalence
with [no_whiles]. *)
Inductive no_whilesR: com -> Prop :=
(* FILL IN HERE *)
.
Theorem no_whiles_eqv:
forall c, no_whiles c = true <-> no_whilesR c.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars (no_whiles_terminating) *)
(** Imp programs that don't involve while loops always terminate.
State and prove a theorem [no_whiles_terminating] that says this. *)
(** (Use either [no_whiles] or [no_whilesR], as you prefer.) *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (stack_compiler) *)
(** HP Calculators, programming languages like Forth and Postscript,
and abstract machines like the Java Virtual Machine all evaluate
arithmetic expressions using a stack. For instance, the expression
<<
(2*3)+(3*(4-2))
>>
would be entered as
<<
2 3 * 3 4 2 - * +
>>
and evaluated like this:
<<
[] | 2 3 * 3 4 2 - * +
[2] | 3 * 3 4 2 - * +
[3, 2] | * 3 4 2 - * +
[6] | 3 4 2 - * +
[3, 6] | 4 2 - * +
[4, 3, 6] | 2 - * +
[2, 4, 3, 6] | - * +
[2, 3, 6] | * +
[6, 6] | +
[12] |
>>
The task of this exercise is to write a small compiler that
translates [aexp]s into stack machine instructions.
The instruction set for our stack language will consist of the
following instructions:
- [SPush n]: Push the number [n] on the stack.
- [SLoad x]: Load the identifier [x] from the store and push it
on the stack
- [SPlus]: Pop the two top numbers from the stack, add them, and
push the result onto the stack.
- [SMinus]: Similar, but subtract.
- [SMult]: Similar, but multiply. *)
Inductive sinstr : Type :=
| SPush : nat -> sinstr
| SLoad : id -> sinstr
| SPlus : sinstr
| SMinus : sinstr
| SMult : sinstr.
(** Write a function to evaluate programs in the stack language. It
takes as input a state, a stack represented as a list of
numbers (top stack item is the head of the list), and a program
represented as a list of instructions, and returns the stack after
executing the program. Test your function on the examples below.
Note that the specification leaves unspecified what to do when
encountering an [SPlus], [SMinus], or [SMult] instruction if the
stack contains less than two elements. In a sense, it is
immaterial what we do, since our compiler will never emit such a
malformed program. *)
Fixpoint s_execute (st : state) (stack : list nat)
(prog : list sinstr)
: list nat :=
(* FILL IN HERE *) admit.
Example s_execute1 :
s_execute empty_state []
[SPush 5; SPush 3; SPush 1; SMinus]
= [2; 5].
(* FILL IN HERE *) Admitted.
Example s_execute2 :
s_execute (update empty_state X 3) [3;4]
[SPush 4; SLoad X; SMult; SPlus]
= [15; 4].
(* FILL IN HERE *) Admitted.
(** Next, write a function which compiles an [aexp] into a stack
machine program. The effect of running the program should be the
same as pushing the value of the expression on the stack. *)
Fixpoint s_compile (e : aexp) : list sinstr :=
(* FILL IN HERE *) admit.
(** After you've defined [s_compile], prove the following to test
that it works. *)
Example s_compile1 :
s_compile (AMinus (AId X) (AMult (ANum 2) (AId Y)))
= [SLoad X; SPush 2; SLoad Y; SMult; SMinus].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (stack_compiler_correct) *)
(** The task of this exercise is to prove the correctness of the
compiler implemented in the previous exercise. Remember that
the specification left unspecified what to do when encountering an
[SPlus], [SMinus], or [SMult] instruction if the stack contains
less than two elements. (In order to make your correctness proof
easier you may find it useful to go back and change your
implementation!)
Prove the following theorem, stating that the [compile] function
behaves correctly. You will need to start by stating a more
general lemma to get a usable induction hypothesis; the main
theorem will then be a simple corollary of this lemma. *)
Theorem s_compile_correct : forall (st : state) (e : aexp),
s_execute st [] (s_compile e) = [ aeval st e ].
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 5 stars, advanced (break_imp) *)
Module BreakImp.
(** Imperative languages such as C or Java often have a [break] or
similar statement for interrupting the execution of loops. In this
exercise we will consider how to add [break] to Imp.
First, we need to enrich the language of commands with an
additional case. *)
Inductive com : Type :=
| CSkip : com
| CBreak : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "BREAK" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
Notation "'SKIP'" :=
CSkip.
Notation "'BREAK'" :=
CBreak.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** Next, we need to define the behavior of [BREAK]. Informally,
whenever [BREAK] is executed in a sequence of commands, it stops
the execution of that sequence and signals that the innermost
enclosing loop (if any) should terminate. If there aren't any
enclosing loops, then the whole program simply terminates. The
final state should be the same as the one in which the [BREAK]
statement was executed.
One important point is what to do when there are multiple loops
enclosing a given [BREAK]. In those cases, [BREAK] should only
terminate the _innermost_ loop where it occurs. Thus, after
executing the following piece of code...
X ::= 0;;
Y ::= 1;;
WHILE 0 <> Y DO
WHILE TRUE DO
BREAK
END;;
X ::= 1;;
Y ::= Y - 1
END
... the value of [X] should be [1], and not [0].
One way of expressing this behavior is to add another parameter to
the evaluation relation that specifies whether evaluation of a
command executes a [BREAK] statement: *)
Inductive status : Type :=
| SContinue : status
| SBreak : status.
Reserved Notation "c1 '/' st '||' s '/' st'"
(at level 40, st, s at level 39).
(** Intuitively, [c / st || s / st'] means that, if [c] is started in
state [st], then it terminates in state [st'] and either signals
that any surrounding loop (or the whole program) should exit
immediately ([s = SBreak]) or that execution should continue
normally ([s = SContinue]).
The definition of the "[c / st || s / st']" relation is very
similar to the one we gave above for the regular evaluation
relation ([c / st || s / st']) -- we just need to handle the
termination signals appropriately:
- If the command is [SKIP], then the state doesn't change, and
execution of any enclosing loop can continue normally.
- If the command is [BREAK], the state stays unchanged, but we
signal a [SBreak].
- If the command is an assignment, then we update the binding for
that variable in the state accordingly and signal that execution
can continue normally.
- If the command is of the form [IF b THEN c1 ELSE c2 FI], then
the state is updated as in the original semantics of Imp, except
that we also propagate the signal from the execution of
whichever branch was taken.
- If the command is a sequence [c1 ; c2], we first execute
[c1]. If this yields a [SBreak], we skip the execution of [c2]
and propagate the [SBreak] signal to the surrounding context;
the resulting state should be the same as the one obtained by
executing [c1] alone. Otherwise, we execute [c2] on the state
obtained after executing [c1], and propagate the signal that was
generated there.
- Finally, for a loop of the form [WHILE b DO c END], the
semantics is almost the same as before. The only difference is
that, when [b] evaluates to true, we execute [c] and check the
signal that it raises. If that signal is [SContinue], then the
execution proceeds as in the original semantics. Otherwise, we
stop the execution of the loop, and the resulting state is the
same as the one resulting from the execution of the current
iteration. In either case, since [BREAK] only terminates the
innermost loop, [WHILE] signals [SContinue]. *)
(** Based on the above description, complete the definition of the
[ceval] relation. *)
Inductive ceval : com -> state -> status -> state -> Prop :=
| E_Skip : forall st,
CSkip / st || SContinue / st
(* FILL IN HERE *)
where "c1 '/' st '||' s '/' st'" := (ceval c1 st s st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip"
(* FILL IN HERE *)
].
(** Now the following properties of your definition of [ceval]: *)
Theorem break_ignore : forall c st st' s,
(BREAK;; c) / st || s / st' ->
st = st'.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_continue : forall b c st st' s,
(WHILE b DO c END) / st || s / st' ->
s = SContinue.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_stops_on_break : forall b c st st',
beval st b = true ->
c / st || SBreak / st' ->
(WHILE b DO c END) / st || SContinue / st'.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 3 stars, advanced, optional (while_break_true) *)
Theorem while_break_true : forall b c st st',
(WHILE b DO c END) / st || SContinue / st' ->
beval st' b = true ->
exists st'', c / st'' || SBreak / st'.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 4 stars, advanced, optional (ceval_deterministic) *)
Theorem ceval_deterministic: forall (c:com) st st1 st2 s1 s2,
c / st || s1 / st1 ->
c / st || s2 / st2 ->
st1 = st2 /\ s1 = s2.
Proof.
(* FILL IN HERE *) Admitted.
End BreakImp.
(** [] *)
(** **** Exercise: 3 stars, optional (short_circuit) *)
(** Most modern programming languages use a "short-circuit" evaluation
rule for boolean [and]: to evaluate [BAnd b1 b2], first evaluate
[b1]. If it evaluates to [false], then the entire [BAnd]
expression evaluates to [false] immediately, without evaluating
[b2]. Otherwise, [b2] is evaluated to determine the result of the
[BAnd] expression.
Write an alternate version of [beval] that performs short-circuit
evaluation of [BAnd] in this manner, and prove that it is
equivalent to [beval]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, optional (add_for_loop) *)
(** Add C-style [for] loops to the language of commands, update the
[ceval] definition to define the semantics of [for] loops, and add
cases for [for] loops as needed so that all the proofs in this file
are accepted by Coq.
A [for] loop should be parameterized by (a) a statement executed
initially, (b) a test that is run on each iteration of the loop to
determine whether the loop should continue, (c) a statement
executed at the end of each loop iteration, and (d) a statement
that makes up the body of the loop. (You don't need to worry
about making up a concrete Notation for [for] loops, but feel free
to play with this too if you like.) *)
(* FILL IN HERE *)
(** [] *)
(* <$Date: 2014-12-26 15:20:26 -0500 (Fri, 26 Dec 2014) $ *)
|
//
// Copyright (c) 1999 Thomas Coonan ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module idec (
inst,
aluasel,
alubsel,
aluop,
wwe,
fwe,
zwe,
cwe,
bdpol,
option,
tris
);
input [11:0] inst;
output [1:0] aluasel;
output [1:0] alubsel;
output [3:0] aluop;
output wwe;
output fwe;
output zwe;
output cwe;
output bdpol;
output option;
output tris;
reg [14:0] decodes;
// For reference, the ALU Op codes are:
//
// ADD 0000
// SUB 1000
// AND 0001
// OR 0010
// XOR 0011
// COM 0100
// ROR 0101
// ROL 0110
// SWAP 0111
assign { aluasel, // Select source for ALU A input. 00=W, 01=SBUS, 10=K, 11=BD
alubsel, // Select source for ALU B input. 00=W, 01=SBUS, 10=K, 11="1"
aluop, // ALU Operation (see comments above for these codes)
wwe, // W register Write Enable
fwe, // File Register Write Enable
zwe, // Status register Z bit update
cwe, // Status register Z bit update
bdpol, // Polarity on bit decode vector (0=no inversion, 1=invert)
tris, // Instruction is an TRIS instruction
option // Instruction is an OPTION instruction
} = decodes;
// This is a large combinatorial decoder.
// I use the casex statement.
always @(inst) begin
casex (inst) // synopsys parallel_case
// *** Byte-Oriented File Register Operations
//
// A A ALU W F Z C B T O
// L L O W W W W D R P
// U U P E E E E P I T
// A B O S
// L
12'b0000_0000_0000: decodes = 15'b00_00_0000_0_0_0_0_0_0_0; // NOP
12'b0000_001X_XXXX: decodes = 15'b00_00_0010_0_1_0_0_0_0_0; // MOVWF
12'b0000_0100_0000: decodes = 15'b00_00_0011_1_0_1_0_0_0_0; // CLRW
12'b0000_011X_XXXX: decodes = 15'b00_00_0011_0_1_1_0_0_0_0; // CLRF
12'b0000_100X_XXXX: decodes = 15'b01_00_1000_1_0_1_1_0_0_0; // SUBWF (d=0)
12'b0000_101X_XXXX: decodes = 15'b01_00_1000_0_1_1_1_0_0_0; // SUBWF (d=1)
12'b0000_110X_XXXX: decodes = 15'b01_11_1000_1_0_1_0_0_0_0; // DECF (d=0)
12'b0000_111X_XXXX: decodes = 15'b01_11_1000_0_1_1_0_0_0_0; // DECF (d=1)
12'b0001_000X_XXXX: decodes = 15'b00_01_0010_1_0_1_0_0_0_0; // IORWF (d=0)
12'b0001_001X_XXXX: decodes = 15'b00_01_0010_0_1_1_0_0_0_0; // IORWF (d=1)
12'b0001_010X_XXXX: decodes = 15'b00_01_0001_1_0_1_0_0_0_0; // ANDWF (d=0)
12'b0001_011X_XXXX: decodes = 15'b00_01_0001_0_1_1_0_0_0_0; // ANDWF (d=1)
12'b0001_100X_XXXX: decodes = 15'b00_01_0011_1_0_1_0_0_0_0; // XORWF (d=0)
12'b0001_101X_XXXX: decodes = 15'b00_01_0011_0_1_1_0_0_0_0; // XORWF (d=1)
12'b0001_110X_XXXX: decodes = 15'b00_01_0000_1_0_1_1_0_0_0; // ADDWF (d=0)
12'b0001_111X_XXXX: decodes = 15'b00_01_0000_0_1_1_1_0_0_0; // ADDWF (d=1)
12'b0010_000X_XXXX: decodes = 15'b01_01_0010_1_0_1_0_0_0_0; // MOVF (d=0)
12'b0010_001X_XXXX: decodes = 15'b01_01_0010_0_1_1_0_0_0_0; // MOVF (d=1)
12'b0010_010X_XXXX: decodes = 15'b01_01_0100_1_0_1_0_0_0_0; // COMF (d=0)
12'b0010_011X_XXXX: decodes = 15'b01_01_0100_0_1_1_0_0_0_0; // COMF (d=1)
12'b0010_100X_XXXX: decodes = 15'b01_11_0000_1_0_1_0_0_0_0; // INCF (d=0)
12'b0010_101X_XXXX: decodes = 15'b01_11_0000_0_1_1_0_0_0_0; // INCF (d=1)
12'b0010_110X_XXXX: decodes = 15'b01_11_1000_1_0_0_0_0_0_0; // DECFSZ(d=0)
12'b0010_111X_XXXX: decodes = 15'b01_11_1000_0_1_0_0_0_0_0; // DECFSZ(d=1)
12'b0011_000X_XXXX: decodes = 15'b01_01_0101_1_0_0_1_0_0_0; // RRF (d=0)
12'b0011_001X_XXXX: decodes = 15'b01_01_0101_0_1_0_1_0_0_0; // RRF (d=1)
12'b0011_010X_XXXX: decodes = 15'b01_01_0110_1_0_0_1_0_0_0; // RLF (d=0)
12'b0011_011X_XXXX: decodes = 15'b01_01_0110_0_1_0_1_0_0_0; // RLF (d=1)
12'b0011_100X_XXXX: decodes = 15'b01_01_0111_1_0_0_0_0_0_0; // SWAPF (d=0)
12'b0011_101X_XXXX: decodes = 15'b01_01_0111_0_1_0_0_0_0_0; // SWAPF (d=1)
12'b0011_110X_XXXX: decodes = 15'b01_11_0000_1_0_0_0_0_0_0; // INCFSZ(d=0)
12'b0011_111X_XXXX: decodes = 15'b01_11_0000_0_1_0_0_0_0_0; // INCFSZ(d=1)
// *** Bit-Oriented File Register Operations
//
// A A ALU W F Z C B T O
// L L O W W W W D R P
// U U P E E E E P I T
// A B O S
// L
12'b0100_XXXX_XXXX: decodes = 15'b11_01_0001_0_1_0_0_1_0_0; // BCF
12'b0101_XXXX_XXXX: decodes = 15'b11_01_0010_0_1_0_0_0_0_0; // BSF
12'b0110_XXXX_XXXX: decodes = 15'b11_01_0001_0_0_0_0_0_0_0; // BTFSC
12'b0111_XXXX_XXXX: decodes = 15'b11_01_0001_0_0_0_0_0_0_0; // BTFSS
// *** Literal and Control Operations
//
// A A ALU W F Z C B T O
// L L O W W W W D R P
// U U P E E E E P I T
// A B O S
// L
12'b0000_0000_0010: decodes = 15'b00_00_0010_0_1_0_0_0_0_1; // OPTION
12'b0000_0000_0011: decodes = 15'b00_00_0000_0_0_0_0_0_0_0; // SLEEP
12'b0000_0000_0100: decodes = 15'b00_00_0000_0_0_0_0_0_0_0; // CLRWDT
12'b0000_0000_0101: decodes = 15'b00_00_0000_0_1_0_0_0_1_0; // TRIS 5
12'b0000_0000_0110: decodes = 15'b00_00_0010_0_1_0_0_0_1_0; // TRIS 6
12'b0000_0000_0111: decodes = 15'b00_00_0010_0_1_0_0_0_1_0; // TRIS 7
//
// A A ALU W F Z C B T O
// L L O W W W W D R P
// U U P E E E E P I T
// A B O S
// L
12'b1000_XXXX_XXXX: decodes = 15'b10_10_0010_1_0_0_0_0_0_0; // RETLW
12'b1001_XXXX_XXXX: decodes = 15'b10_10_0010_0_0_0_0_0_0_0; // CALL
12'b101X_XXXX_XXXX: decodes = 15'b10_10_0010_0_0_0_0_0_0_0; // GOTO
12'b1100_XXXX_XXXX: decodes = 15'b10_10_0010_1_0_0_0_0_0_0; // MOVLW
12'b1101_XXXX_XXXX: decodes = 15'b00_10_0010_1_0_1_0_0_0_0; // IORLW
12'b1110_XXXX_XXXX: decodes = 15'b00_10_0001_1_0_1_0_0_0_0; // ANDLW
12'b1111_XXXX_XXXX: decodes = 15'b00_10_0011_1_0_1_0_0_0_0; // XORLW
default:
decodes = 15'b00_00_0000_0_0_0_0_0_0_0;
endcase
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_ddr_pad_txrx_zctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_ddr_pad_txrx_zctl(/*AUTOARG*/
// Outputs
out,
// Inouts
pad,
// Inputs
vrefcode, vdd_h, cbu, cbd, data, oe, odt_enable
);
// INPUTS
input [7:0] vrefcode; // impedence control bits
input odt_enable; // ODT control
input vdd_h; // IO power
input [8:1] cbu; // Impedence Control bits for Pullup driver
input [8:1] cbd; // Impedence Control bits for Pulldn driver
input data; // Data input to Driver
input oe; // Output tristate control (active high)
// INOUTS
inout pad; // Output/Input pad of Driver/Receiver
// OUTPUTS
output out; // Receiver output
//////////////////////////
// CODE
//////////////////////////
assign pad = oe ? data : 1'bz;
assign out = pad;
// FIX FOR MAKING INPUT DQS WEAK 0/1 WHEN BUS IS IN "Z" STATE.
//wire pad_in;
//pulldown p1(pad_in); // pulldown by default if no driver
//assign out = (pad === 1'bz) ? pad_in : pad;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O221AI_BLACKBOX_V
`define SKY130_FD_SC_MS__O221AI_BLACKBOX_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o221ai (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O221AI_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVGND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__TAPVGND2_FUNCTIONAL_PP_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapvgnd2 (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVGND2_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21BOI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A21BOI_BEHAVIORAL_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, b, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21BOI_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211A_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O211A_BEHAVIORAL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o211a (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211A_BEHAVIORAL_V |
/*
* Copyright (c) 2015, Arch Labolatory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
module GEN( input wire CLK_IN,
input wire RST_X_IN,
output wire CLK_OUT,
output wire VGA_CLK_OUT,
output wire RST_X_OUT
);
wire LOCKED, VLOCKED, CLK_IBUF;
wire RST_X_BUF;
clk_wiz_0 clkgen(CLK_IN, CLK_OUT, VGA_CLK_OUT, LOCKED);
RSTGEN rstgen(CLK_OUT, (RST_X_IN & LOCKED), RST_X_OUT);
endmodule
module RSTGEN(CLK, RST_X_I, RST_X_O);
input CLK, RST_X_I;
output RST_X_O;
reg [7:0] cnt;
assign RST_X_O = cnt[7];
always @(posedge CLK or negedge RST_X_I) begin
if (!RST_X_I) cnt <= 0;
else if (~RST_X_O) cnt <= (cnt + 1'b1);
end
endmodule
|
// Copyright 2020 The XLS Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Sends a single byte (if TEST_SINGLE_BYTE) or two bytes to the UART
// receiver and checks it is properly received / obeying its interface
// protocol.
`include "xls/uncore_rtl/ice40/uart_receiver.v"
module uart_receiver_test;
localparam TicksPerClock = 2;
localparam ClocksPerBaud = 8;
integer i;
reg clk;
reg rst_n;
reg rx;
reg rx_byte_done;
wire [7:0] rx_byte;
wire rx_byte_valid;
wire clear_to_send;
integer stop_bit_begin_time;
integer stop_bit_done = 0;
uart_receiver #(
.ClocksPerBaud(ClocksPerBaud)
) receiver (
.clk (clk),
.rst_n (rst_n),
.rx (rx),
.clear_to_send_out(clear_to_send),
.rx_byte_out (rx_byte),
.rx_byte_valid_out(rx_byte_valid),
.rx_byte_done (rx_byte_done)
);
initial begin
#1 clk = 0;
forever #1 clk = !clk;
end
`include "xls/uncore_rtl/ice40/xls_assertions.inc"
// Make sure we finish after some reasonable amount of time.
initial begin
#1024 begin
$display("ERROR: timeout, simulation ran too long");
$finish;
end
end
initial begin
//$dumpfile("/tmp/uart_receiver_test.vcd");
//$dumpvars(0, clk, rst_n, rx_byte, rx_byte_valid, rx, rx_byte_done,
// clear_to_send, receiver.state, receiver.state_next,
// receiver.rx_countdown, receiver.samples, receiver.sample_count,
// receiver.data_bitno, receiver.rx_byte_valid_next);
$display("Starting...\n");
$monitor("%t rx: %b rx_byte_valid: %b", $time, rx, rx_byte_valid);
rst_n <= 0;
rx <= 1;
rx_byte_done <= 0;
// Come out of reset after a few cycles.
#4 rst_n <= 1;
#TicksPerClock;
xls_assert(receiver.state, 0, "receiver state should be idle");
xls_assert(clear_to_send, 1, "should be clear to send when idle");
// Start bit.
rx <= 0;
#(TicksPerClock*ClocksPerBaud);
// Send toggling bits, starting with 'b1 to make 'h55.
for (i = 0; i < 8; i = i + 1) begin
xls_assert(clear_to_send, 0, "transmitting from testbench");
rx <= (i % 2 == 0);
#(TicksPerClock*ClocksPerBaud);
end
stop_bit_begin_time = $time;
// Stop bit / idle.
rx <= 1;
#TicksPerClock;
// Byte should be valid before we receive the stop bit.
#1;
xls_assert(1, rx_byte_valid, "valid during stop bit");
xls_assert_int_eq(8'h55, rx_byte, "byte payload during stop bit");
`ifdef TEST_SINGLE_BYTE
// Wait to transition back to idle.
wait (receiver.state == 'd0);
// Byte should be valid and the same after we're idle.
xls_assert(1, rx_byte_valid, "valid when idle");
xls_assert_int_eq(8'h55, rx_byte, "byte payload when idle");
xls_assert(clear_to_send, 0, "byte is valid, should not be clear to send");
`else
// Discard the byte immediately now that we've checked it.
rx_byte_done <= 1;
// Check that subsequently we say it's ok to send.
#TicksPerClock;
xls_assert(1, clear_to_send, "clear to send once byte is done");
// Only note that the RX byte is done for a single cycle.
rx_byte_done <= 0;
// Wait until we've sent the stop bit for a full baud of time.
#(TicksPerClock*ClocksPerBaud-($time-stop_bit_begin_time));
$display("Starting second byte.");
// Then send a start bit and the next byte.
rx <= 0;
#(ClocksPerBaud*TicksPerClock);
for (i = 0; i < 8; i = i + 1) begin
rx <= (8'h01 >> i) & 1'b1;
#(ClocksPerBaud*TicksPerClock);
end
// Stop bit / idle.
rx <= 1;
#TicksPerClock;
// Byte should be valid before we receive the stop bit.
#1;
xls_assert(1, rx_byte_valid, "valid during stop bit");
xls_assert_int_eq(8'h01, rx_byte, "byte payload during stop bit");
`endif
// Pad a little time before end of sim.
#(8*TicksPerClock);
$finish;
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file Mem_B.v when simulating
// the core, Mem_B. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module Mem_B(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("Mem_B.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The system memory bus and the ROM instance
//
// ====================================================================
`include "e203_defines.v"
module e203_subsys_mems(
input mem_icb_cmd_valid,
output mem_icb_cmd_ready,
input [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr,
input mem_icb_cmd_read,
input [`E203_XLEN-1:0] mem_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] mem_icb_cmd_wmask,
//
output mem_icb_rsp_valid,
input mem_icb_rsp_ready,
output mem_icb_rsp_err,
output [`E203_XLEN-1:0] mem_icb_rsp_rdata,
//////////////////////////////////////////////////////////
output sysmem_icb_cmd_valid,
input sysmem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] sysmem_icb_cmd_addr,
output sysmem_icb_cmd_read,
output [`E203_XLEN-1:0] sysmem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] sysmem_icb_cmd_wmask,
//
input sysmem_icb_rsp_valid,
output sysmem_icb_rsp_ready,
input sysmem_icb_rsp_err,
input [`E203_XLEN-1:0] sysmem_icb_rsp_rdata,
//////////////////////////////////////////////////////////
output qspi0_ro_icb_cmd_valid,
input qspi0_ro_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] qspi0_ro_icb_cmd_addr,
output qspi0_ro_icb_cmd_read,
output [`E203_XLEN-1:0] qspi0_ro_icb_cmd_wdata,
//
input qspi0_ro_icb_rsp_valid,
output qspi0_ro_icb_rsp_ready,
input qspi0_ro_icb_rsp_err,
input [`E203_XLEN-1:0] qspi0_ro_icb_rsp_rdata,
//////////////////////////////////////////////////////////
output otp_ro_icb_cmd_valid,
input otp_ro_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] otp_ro_icb_cmd_addr,
output otp_ro_icb_cmd_read,
output [`E203_XLEN-1:0] otp_ro_icb_cmd_wdata,
//
input otp_ro_icb_rsp_valid,
output otp_ro_icb_rsp_ready,
input otp_ro_icb_rsp_err,
input [`E203_XLEN-1:0] otp_ro_icb_rsp_rdata,
//////////////////////////////////////////////////////////
output dm_icb_cmd_valid,
input dm_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] dm_icb_cmd_addr,
output dm_icb_cmd_read,
output [`E203_XLEN-1:0] dm_icb_cmd_wdata,
//
input dm_icb_rsp_valid,
output dm_icb_rsp_ready,
input [`E203_XLEN-1:0] dm_icb_rsp_rdata,
input clk,
input bus_rst_n,
input rst_n
);
wire mrom_icb_cmd_valid;
wire mrom_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] mrom_icb_cmd_addr;
wire mrom_icb_cmd_read;
wire mrom_icb_rsp_valid;
wire mrom_icb_rsp_ready;
wire mrom_icb_rsp_err ;
wire [`E203_XLEN-1:0] mrom_icb_rsp_rdata;
wire expl_axi_icb_cmd_valid;
wire expl_axi_icb_cmd_ready;
wire [32-1:0] expl_axi_icb_cmd_addr;
wire expl_axi_icb_cmd_read;
wire [32-1:0] expl_axi_icb_cmd_wdata;
wire [4 -1:0] expl_axi_icb_cmd_wmask;
wire expl_axi_icb_rsp_valid;
wire expl_axi_icb_rsp_ready;
wire [32-1:0] expl_axi_icb_rsp_rdata;
wire expl_axi_icb_rsp_err;
localparam MROM_AW = 12 ;
localparam MROM_DP = 1024;
// There are several slaves for Mem bus, including:
// * DM : 0x0000 0000 -- 0x0000 0FFF
// * MROM : 0x0000 1000 -- 0x0000 1FFF
// * OTP-RO : 0x0002 0000 -- 0x0003 FFFF
// * QSPI0-RO : 0x2000 0000 -- 0x3FFF FFFF
// * SysMem : 0x8000 0000 -- 0xFFFF FFFF
sirv_icb1to8_bus # (
.ICB_FIFO_DP (2),// We add a ping-pong buffer here to cut down the timing path
.ICB_FIFO_CUT_READY (1),// We configure it to cut down the back-pressure ready signal
.AW (32),
.DW (`E203_XLEN),
.SPLT_FIFO_OUTS_NUM (1),// The Mem only allow 1 oustanding
.SPLT_FIFO_CUT_READY (1),// The Mem always cut ready
// * DM : 0x0000 0000 -- 0x0000 0FFF
.O0_BASE_ADDR (32'h0000_0000),
.O0_BASE_REGION_LSB (12),
// * MROM : 0x0000 1000 -- 0x0000 1FFF
.O1_BASE_ADDR (32'h0000_1000),
.O1_BASE_REGION_LSB (12),
// * OTP-RO : 0x0002 0000 -- 0x0003 FFFF
.O2_BASE_ADDR (32'h0002_0000),
.O2_BASE_REGION_LSB (17),
// * QSPI0-RO : 0x2000 0000 -- 0x3FFF FFFF
.O3_BASE_ADDR (32'h2000_0000),
.O3_BASE_REGION_LSB (29),
// * SysMem : 0x8000 0000 -- 0xFFFF FFFF
// Actually since the 0xFxxx xxxx have been occupied by FIO,
// sysmem have no chance to access it
.O4_BASE_ADDR (32'h8000_0000),
.O4_BASE_REGION_LSB (31),
// * Here is an example AXI Peripheral
.O5_BASE_ADDR (32'h4000_0000),
.O5_BASE_REGION_LSB (28),
// Not used
.O6_BASE_ADDR (32'h0000_0000),
.O6_BASE_REGION_LSB (0),
// Not used
.O7_BASE_ADDR (32'h0000_0000),
.O7_BASE_REGION_LSB (0)
)u_sirv_mem_fab(
.i_icb_cmd_valid (mem_icb_cmd_valid),
.i_icb_cmd_ready (mem_icb_cmd_ready),
.i_icb_cmd_addr (mem_icb_cmd_addr ),
.i_icb_cmd_read (mem_icb_cmd_read ),
.i_icb_cmd_wdata (mem_icb_cmd_wdata),
.i_icb_cmd_wmask (mem_icb_cmd_wmask),
.i_icb_cmd_lock (1'b0 ),
.i_icb_cmd_excl (1'b0 ),
.i_icb_cmd_size (2'b0 ),
.i_icb_cmd_burst (2'b0),
.i_icb_cmd_beat (2'b0 ),
.i_icb_rsp_valid (mem_icb_rsp_valid),
.i_icb_rsp_ready (mem_icb_rsp_ready),
.i_icb_rsp_err (mem_icb_rsp_err ),
.i_icb_rsp_excl_ok(),
.i_icb_rsp_rdata (mem_icb_rsp_rdata),
// * DM
.o0_icb_enable (1'b1),
.o0_icb_cmd_valid (dm_icb_cmd_valid),
.o0_icb_cmd_ready (dm_icb_cmd_ready),
.o0_icb_cmd_addr (dm_icb_cmd_addr ),
.o0_icb_cmd_read (dm_icb_cmd_read ),
.o0_icb_cmd_wdata (dm_icb_cmd_wdata),
.o0_icb_cmd_wmask (),
.o0_icb_cmd_lock (),
.o0_icb_cmd_excl (),
.o0_icb_cmd_size (),
.o0_icb_cmd_burst (),
.o0_icb_cmd_beat (),
.o0_icb_rsp_valid (dm_icb_rsp_valid),
.o0_icb_rsp_ready (dm_icb_rsp_ready),
.o0_icb_rsp_err (1'b0),
.o0_icb_rsp_excl_ok(1'b0),
.o0_icb_rsp_rdata (dm_icb_rsp_rdata),
// * MROM
.o1_icb_enable (1'b1),
.o1_icb_cmd_valid (mrom_icb_cmd_valid),
.o1_icb_cmd_ready (mrom_icb_cmd_ready),
.o1_icb_cmd_addr (mrom_icb_cmd_addr ),
.o1_icb_cmd_read (mrom_icb_cmd_read ),
.o1_icb_cmd_wdata (),
.o1_icb_cmd_wmask (),
.o1_icb_cmd_lock (),
.o1_icb_cmd_excl (),
.o1_icb_cmd_size (),
.o1_icb_cmd_burst (),
.o1_icb_cmd_beat (),
.o1_icb_rsp_valid (mrom_icb_rsp_valid),
.o1_icb_rsp_ready (mrom_icb_rsp_ready),
.o1_icb_rsp_err (mrom_icb_rsp_err),
.o1_icb_rsp_excl_ok(1'b0 ),
.o1_icb_rsp_rdata (mrom_icb_rsp_rdata),
// * OTP-RO
.o2_icb_enable (1'b1),
.o2_icb_cmd_valid (otp_ro_icb_cmd_valid),
.o2_icb_cmd_ready (otp_ro_icb_cmd_ready),
.o2_icb_cmd_addr (otp_ro_icb_cmd_addr ),
.o2_icb_cmd_read (otp_ro_icb_cmd_read ),
.o2_icb_cmd_wdata (otp_ro_icb_cmd_wdata),
.o2_icb_cmd_wmask (),
.o2_icb_cmd_lock (),
.o2_icb_cmd_excl (),
.o2_icb_cmd_size (),
.o2_icb_cmd_burst (),
.o2_icb_cmd_beat (),
.o2_icb_rsp_valid (otp_ro_icb_rsp_valid),
.o2_icb_rsp_ready (otp_ro_icb_rsp_ready),
.o2_icb_rsp_err (otp_ro_icb_rsp_err),
.o2_icb_rsp_excl_ok(1'b0 ),
.o2_icb_rsp_rdata (otp_ro_icb_rsp_rdata),
// * QSPI0-RO
.o3_icb_enable (1'b1),
.o3_icb_cmd_valid (qspi0_ro_icb_cmd_valid),
.o3_icb_cmd_ready (qspi0_ro_icb_cmd_ready),
.o3_icb_cmd_addr (qspi0_ro_icb_cmd_addr ),
.o3_icb_cmd_read (qspi0_ro_icb_cmd_read ),
.o3_icb_cmd_wdata (qspi0_ro_icb_cmd_wdata),
.o3_icb_cmd_wmask (),
.o3_icb_cmd_lock (),
.o3_icb_cmd_excl (),
.o3_icb_cmd_size (),
.o3_icb_cmd_burst (),
.o3_icb_cmd_beat (),
.o3_icb_rsp_valid (qspi0_ro_icb_rsp_valid),
.o3_icb_rsp_ready (qspi0_ro_icb_rsp_ready),
.o3_icb_rsp_err (qspi0_ro_icb_rsp_err),
.o3_icb_rsp_excl_ok(1'b0 ),
.o3_icb_rsp_rdata (qspi0_ro_icb_rsp_rdata),
// * SysMem
.o4_icb_enable (1'b1),
.o4_icb_cmd_valid (sysmem_icb_cmd_valid),
.o4_icb_cmd_ready (sysmem_icb_cmd_ready),
.o4_icb_cmd_addr (sysmem_icb_cmd_addr ),
.o4_icb_cmd_read (sysmem_icb_cmd_read ),
.o4_icb_cmd_wdata (sysmem_icb_cmd_wdata),
.o4_icb_cmd_wmask (sysmem_icb_cmd_wmask),
.o4_icb_cmd_lock (),
.o4_icb_cmd_excl (),
.o4_icb_cmd_size (),
.o4_icb_cmd_burst (),
.o4_icb_cmd_beat (),
.o4_icb_rsp_valid (sysmem_icb_rsp_valid),
.o4_icb_rsp_ready (sysmem_icb_rsp_ready),
.o4_icb_rsp_err (sysmem_icb_rsp_err ),
.o4_icb_rsp_excl_ok(1'b0),
.o4_icb_rsp_rdata (sysmem_icb_rsp_rdata),
// * Example AXI
.o5_icb_enable (1'b1),
.o5_icb_cmd_valid (expl_axi_icb_cmd_valid),
.o5_icb_cmd_ready (expl_axi_icb_cmd_ready),
.o5_icb_cmd_addr (expl_axi_icb_cmd_addr ),
.o5_icb_cmd_read (expl_axi_icb_cmd_read ),
.o5_icb_cmd_wdata (expl_axi_icb_cmd_wdata),
.o5_icb_cmd_wmask (expl_axi_icb_cmd_wmask),
.o5_icb_cmd_lock (),
.o5_icb_cmd_excl (),
.o5_icb_cmd_size (),
.o5_icb_cmd_burst (),
.o5_icb_cmd_beat (),
.o5_icb_rsp_valid (expl_axi_icb_rsp_valid),
.o5_icb_rsp_ready (expl_axi_icb_rsp_ready),
.o5_icb_rsp_err (expl_axi_icb_rsp_err),
.o5_icb_rsp_excl_ok(1'b0 ),
.o5_icb_rsp_rdata (expl_axi_icb_rsp_rdata),
// * Not used
.o6_icb_enable (1'b0),
.o6_icb_cmd_valid (),
.o6_icb_cmd_ready (1'b0),
.o6_icb_cmd_addr (),
.o6_icb_cmd_read (),
.o6_icb_cmd_wdata (),
.o6_icb_cmd_wmask (),
.o6_icb_cmd_lock (),
.o6_icb_cmd_excl (),
.o6_icb_cmd_size (),
.o6_icb_cmd_burst (),
.o6_icb_cmd_beat (),
.o6_icb_rsp_valid (1'b0),
.o6_icb_rsp_ready (),
.o6_icb_rsp_err (1'b0 ),
.o6_icb_rsp_excl_ok(1'b0 ),
.o6_icb_rsp_rdata (`E203_XLEN'b0),
// * Not used
.o7_icb_enable (1'b0),
.o7_icb_cmd_valid (),
.o7_icb_cmd_ready (1'b0),
.o7_icb_cmd_addr (),
.o7_icb_cmd_read (),
.o7_icb_cmd_wdata (),
.o7_icb_cmd_wmask (),
.o7_icb_cmd_lock (),
.o7_icb_cmd_excl (),
.o7_icb_cmd_size (),
.o7_icb_cmd_burst (),
.o7_icb_cmd_beat (),
.o7_icb_rsp_valid (1'b0),
.o7_icb_rsp_ready (),
.o7_icb_rsp_err (1'b0 ),
.o7_icb_rsp_excl_ok(1'b0 ),
.o7_icb_rsp_rdata (`E203_XLEN'b0),
.clk (clk ),
.rst_n (bus_rst_n)
);
sirv_mrom_top #(
.AW(MROM_AW),
.DW(32),
.DP(MROM_DP)
)u_sirv_mrom_top(
.rom_icb_cmd_valid (mrom_icb_cmd_valid),
.rom_icb_cmd_ready (mrom_icb_cmd_ready),
.rom_icb_cmd_addr (mrom_icb_cmd_addr [MROM_AW-1:0]),
.rom_icb_cmd_read (mrom_icb_cmd_read ),
.rom_icb_rsp_valid (mrom_icb_rsp_valid),
.rom_icb_rsp_ready (mrom_icb_rsp_ready),
.rom_icb_rsp_err (mrom_icb_rsp_err ),
.rom_icb_rsp_rdata (mrom_icb_rsp_rdata),
.clk (clk ),
.rst_n (rst_n)
);
// * Here is an example AXI Peripheral
wire expl_axi_arvalid;
wire expl_axi_arready;
wire [`E203_ADDR_SIZE-1:0] expl_axi_araddr;
wire [3:0] expl_axi_arcache;
wire [2:0] expl_axi_arprot;
wire [1:0] expl_axi_arlock;
wire [1:0] expl_axi_arburst;
wire [3:0] expl_axi_arlen;
wire [2:0] expl_axi_arsize;
wire expl_axi_awvalid;
wire expl_axi_awready;
wire [`E203_ADDR_SIZE-1:0] expl_axi_awaddr;
wire [3:0] expl_axi_awcache;
wire [2:0] expl_axi_awprot;
wire [1:0] expl_axi_awlock;
wire [1:0] expl_axi_awburst;
wire [3:0] expl_axi_awlen;
wire [2:0] expl_axi_awsize;
wire expl_axi_rvalid;
wire expl_axi_rready;
wire [`E203_XLEN-1:0] expl_axi_rdata;
wire [1:0] expl_axi_rresp;
wire expl_axi_rlast;
wire expl_axi_wvalid;
wire expl_axi_wready;
wire [`E203_XLEN-1:0] expl_axi_wdata;
wire [(`E203_XLEN/8)-1:0] expl_axi_wstrb;
wire expl_axi_wlast;
wire expl_axi_bvalid;
wire expl_axi_bready;
wire [1:0] expl_axi_bresp;
sirv_gnrl_icb2axi # (
.AXI_FIFO_DP (2), // We just add ping-pong buffer here to avoid any potential timing loops
// User can change it to 0 if dont care
.AXI_FIFO_CUT_READY (1), // This is to cut the back-pressure signal if you set as 1
.AW (32),
.FIFO_OUTS_NUM (4),// We only allow 4 oustandings at most for mem, user can configure it to any value
.FIFO_CUT_READY(1),
.DW (`E203_XLEN)
) u_expl_axi_icb2axi(
.i_icb_cmd_valid (expl_axi_icb_cmd_valid),
.i_icb_cmd_ready (expl_axi_icb_cmd_ready),
.i_icb_cmd_addr (expl_axi_icb_cmd_addr ),
.i_icb_cmd_read (expl_axi_icb_cmd_read ),
.i_icb_cmd_wdata (expl_axi_icb_cmd_wdata),
.i_icb_cmd_wmask (expl_axi_icb_cmd_wmask),
.i_icb_cmd_size (),
.i_icb_rsp_valid (expl_axi_icb_rsp_valid),
.i_icb_rsp_ready (expl_axi_icb_rsp_ready),
.i_icb_rsp_rdata (expl_axi_icb_rsp_rdata),
.i_icb_rsp_err (expl_axi_icb_rsp_err),
.o_axi_arvalid (expl_axi_arvalid),
.o_axi_arready (expl_axi_arready),
.o_axi_araddr (expl_axi_araddr ),
.o_axi_arcache (expl_axi_arcache),
.o_axi_arprot (expl_axi_arprot ),
.o_axi_arlock (expl_axi_arlock ),
.o_axi_arburst (expl_axi_arburst),
.o_axi_arlen (expl_axi_arlen ),
.o_axi_arsize (expl_axi_arsize ),
.o_axi_awvalid (expl_axi_awvalid),
.o_axi_awready (expl_axi_awready),
.o_axi_awaddr (expl_axi_awaddr ),
.o_axi_awcache (expl_axi_awcache),
.o_axi_awprot (expl_axi_awprot ),
.o_axi_awlock (expl_axi_awlock ),
.o_axi_awburst (expl_axi_awburst),
.o_axi_awlen (expl_axi_awlen ),
.o_axi_awsize (expl_axi_awsize ),
.o_axi_rvalid (expl_axi_rvalid ),
.o_axi_rready (expl_axi_rready ),
.o_axi_rdata (expl_axi_rdata ),
.o_axi_rresp (expl_axi_rresp ),
.o_axi_rlast (expl_axi_rlast ),
.o_axi_wvalid (expl_axi_wvalid ),
.o_axi_wready (expl_axi_wready ),
.o_axi_wdata (expl_axi_wdata ),
.o_axi_wstrb (expl_axi_wstrb ),
.o_axi_wlast (expl_axi_wlast ),
.o_axi_bvalid (expl_axi_bvalid ),
.o_axi_bready (expl_axi_bready ),
.o_axi_bresp (expl_axi_bresp ),
.clk (clk ),
.rst_n (bus_rst_n)
);
sirv_expl_axi_slv # (
.AW (32),
.DW (`E203_XLEN)
) u_perips_expl_axi_slv (
.axi_arvalid (expl_axi_arvalid),
.axi_arready (expl_axi_arready),
.axi_araddr (expl_axi_araddr ),
.axi_arcache (expl_axi_arcache),
.axi_arprot (expl_axi_arprot ),
.axi_arlock (expl_axi_arlock ),
.axi_arburst (expl_axi_arburst),
.axi_arlen (expl_axi_arlen ),
.axi_arsize (expl_axi_arsize ),
.axi_awvalid (expl_axi_awvalid),
.axi_awready (expl_axi_awready),
.axi_awaddr (expl_axi_awaddr ),
.axi_awcache (expl_axi_awcache),
.axi_awprot (expl_axi_awprot ),
.axi_awlock (expl_axi_awlock ),
.axi_awburst (expl_axi_awburst),
.axi_awlen (expl_axi_awlen ),
.axi_awsize (expl_axi_awsize ),
.axi_rvalid (expl_axi_rvalid ),
.axi_rready (expl_axi_rready ),
.axi_rdata (expl_axi_rdata ),
.axi_rresp (expl_axi_rresp ),
.axi_rlast (expl_axi_rlast ),
.axi_wvalid (expl_axi_wvalid ),
.axi_wready (expl_axi_wready ),
.axi_wdata (expl_axi_wdata ),
.axi_wstrb (expl_axi_wstrb ),
.axi_wlast (expl_axi_wlast ),
.axi_bvalid (expl_axi_bvalid ),
.axi_bready (expl_axi_bready ),
.axi_bresp (expl_axi_bresp ),
.clk (clk ),
.rst_n (rst_n)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFSTP_BLACKBOX_V
`define SKY130_FD_SC_LS__DFSTP_BLACKBOX_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfstp (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFSTP_BLACKBOX_V
|
// Pixel RAM. LCD pixel -> RAM -> LED pixel.
// Copyright (c) 2013 Jared Boone, ShareBrained Technology, Inc.
//
// This file is part of the Medusa project.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; see the file COPYING. If not, write to
// the Free Software Foundation, Inc., 51 Franklin Street,
// Boston, MA 02110-1301, USA.
//
module pixel_ram
#(parameter DATA_WIDTH=24, parameter ADDR_WIDTH=9)
(
input [(DATA_WIDTH-1):0] data_a,
input [(ADDR_WIDTH-1):0] addr_a, addr_b,
input we_a, clk_a, clk_b,
output reg [(DATA_WIDTH-1):0] q_b
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @ (posedge clk_a)
begin
if (we_a)
ram[addr_a] <= data_a;
end
always @ (posedge clk_b)
begin
q_b <= ram[addr_b];
end
endmodule
|
`default_nettype none
`timescale 1ns / 1ps
/***********************************************************************************************************************
* *
* ANTIKERNEL v0.1 *
* *
* Copyright (c) 2012-2017 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/
/**
@file
@author Andrew D. Zonenberg
@brief Receiver for RPC network, protocol version 3
Network-side interface is standard RPCv3
Router-side interface is a FIFO.
space_available Asserted by router if it has at least one *packet* worth of buffer space.
packet_start Asserted by transceiver for one clock at start of message.
Asserted before first assertion of data_valid.
data_valid Asserted by transceiver if data should be processed.
Will be asserted for one clock every (OUT_DATA_WIDTH / IN_DATA_WIDTH) clocks.
data One word of message data.
packet_done Asserted by transceiver for one clock at end of message.
Concurrent with last assertion of data_valid.
RESOURCE USAGE (XST A7 rough estimate)
Width FF LUT Slice
16 -> 16 22 7 7
16 -> 32 38 12 14
16 -> 64 70 10 21
16 -> 128 133 5 37
32 -> 16 40 76 43
32 -> 32 37 5 10
32 -> 64 69 4 20
32 -> 128 132 48 24
64 -> 16 72 154 73
64 -> 32 71 89 39
64 -> 64 68 3 20
64 -> 128 131 27 30
128 -> 16 136 104 36
128 -> 32 134 102 49
128 -> 64 132 164 68
128 -> 128 131 30 28
*/
module RPCv3RouterReceiver
#(
parameter OUT_DATA_WIDTH = 32,
parameter IN_DATA_WIDTH = 16
)
(
//Interface clock
input wire clk,
//Network interface, inbound side
input wire rpc_rx_en,
input wire[IN_DATA_WIDTH-1:0] rpc_rx_data,
output wire rpc_rx_ready,
//Router interface, outbound side
input wire rpc_fab_rx_space_available,
output wire rpc_fab_rx_packet_start,
output wire rpc_fab_rx_data_valid,
output wire[OUT_DATA_WIDTH-1:0] rpc_fab_rx_data,
output wire rpc_fab_rx_packet_done
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Create the right receiver depending on link widths
localparam EXPANDING = (IN_DATA_WIDTH < OUT_DATA_WIDTH);
localparam COLLAPSING = (IN_DATA_WIDTH > OUT_DATA_WIDTH);
localparam BUFFERING = (IN_DATA_WIDTH == OUT_DATA_WIDTH);
generate
if(EXPANDING) begin
RPCv3RouterReceiver_expanding #(
.IN_DATA_WIDTH(IN_DATA_WIDTH),
.OUT_DATA_WIDTH(OUT_DATA_WIDTH)
) rxvr (
.clk(clk),
.rpc_rx_en(rpc_rx_en),
.rpc_rx_data(rpc_rx_data),
.rpc_rx_ready(rpc_rx_ready),
.rpc_fab_rx_space_available(rpc_fab_rx_space_available),
.rpc_fab_rx_packet_start(rpc_fab_rx_packet_start),
.rpc_fab_rx_data_valid(rpc_fab_rx_data_valid),
.rpc_fab_rx_data(rpc_fab_rx_data),
.rpc_fab_rx_packet_done(rpc_fab_rx_packet_done)
);
end
else if(COLLAPSING) begin
RPCv3RouterReceiver_collapsing #(
.IN_DATA_WIDTH(IN_DATA_WIDTH),
.OUT_DATA_WIDTH(OUT_DATA_WIDTH)
) rxvr (
.clk(clk),
.rpc_rx_en(rpc_rx_en),
.rpc_rx_data(rpc_rx_data),
.rpc_rx_ready(rpc_rx_ready),
.rpc_fab_rx_space_available(rpc_fab_rx_space_available),
.rpc_fab_rx_packet_start(rpc_fab_rx_packet_start),
.rpc_fab_rx_data_valid(rpc_fab_rx_data_valid),
.rpc_fab_rx_data(rpc_fab_rx_data),
.rpc_fab_rx_packet_done(rpc_fab_rx_packet_done)
);
end
else begin
RPCv3RouterReceiver_buffering #(
.IN_DATA_WIDTH(IN_DATA_WIDTH),
.OUT_DATA_WIDTH(OUT_DATA_WIDTH)
) rxvr (
.clk(clk),
.rpc_rx_en(rpc_rx_en),
.rpc_rx_data(rpc_rx_data),
.rpc_rx_ready(rpc_rx_ready),
.rpc_fab_rx_space_available(rpc_fab_rx_space_available),
.rpc_fab_rx_packet_start(rpc_fab_rx_packet_start),
.rpc_fab_rx_data_valid(rpc_fab_rx_data_valid),
.rpc_fab_rx_data(rpc_fab_rx_data),
.rpc_fab_rx_packet_done(rpc_fab_rx_packet_done)
);
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:45:25 12/01/2014
// Design Name:
// Module Name: RegistroWithMuxInputBorrar
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RegistroWithMuxInput#(parameter Width = 4)
(CLK,EnableRegisterIn,reset,SELCoeffX,SELCoeffY,Coeff00,Coeff01,Coeff02,Coeff03,Coeff04,Coeff05,Coeff06,Coeff07,Coeff08,Coeff09,
Coeff10,Coeff11,Coeff12,Coeff13,Coeff14,Coeff15,Coeff16,Coeff17,Coeff18,Coeff19,OffsetIn,OutCoeffX,OutCoeffY,OffsetOut);
input signed [Width-1:0] Coeff00,Coeff01,Coeff02,Coeff03,Coeff04,Coeff05,Coeff06,Coeff07,Coeff08,
Coeff09,Coeff10,Coeff11,Coeff12,Coeff13,Coeff14,Coeff15,Coeff16,Coeff17,Coeff18,Coeff19,OffsetIn;
input CLK,EnableRegisterIn,reset;
input [3:0] SELCoeffX,SELCoeffY;
output reg signed [Width-1:0] OutCoeffX = 0;
output reg signed [Width-1:0] OutCoeffY = 0; //OffsetOut
output signed [Width-1:0] OffsetOut;
reg signed [Width-1:0] AuxCoeff00,AuxCoeff01,AuxCoeff02,AuxCoeff03,AuxCoeff04,AuxCoeff05,AuxCoeff06,
AuxCoeff07,AuxCoeff08,AuxCoeff09,AuxCoeff10,AuxCoeff11,AuxCoeff12,AuxCoeff13,AuxCoeff14,AuxCoeff15,AuxCoeff16,
AuxCoeff17,AuxCoeff18,AuxCoeff19,AuxCoeff20;
always @(posedge CLK)
if (reset) begin
AuxCoeff00 <= 0;
AuxCoeff01 <= 0;
AuxCoeff02 <= 0;
AuxCoeff03 <= 0;
AuxCoeff04 <= 0;
AuxCoeff05 <= 0;
AuxCoeff06 <= 0;
AuxCoeff07 <= 0;
AuxCoeff08 <= 0;
AuxCoeff09 <= 0;
AuxCoeff10 <= 0;
AuxCoeff11 <= 0;
AuxCoeff12 <= 0;
AuxCoeff13 <= 0;
AuxCoeff14 <= 0;
AuxCoeff15 <= 0;
AuxCoeff16 <= 0;
AuxCoeff17 <= 0;
AuxCoeff18 <= 0;
AuxCoeff19 <= 0;
AuxCoeff20 <= 0;
end else if (EnableRegisterIn) begin
AuxCoeff00 <= Coeff00;
AuxCoeff01 <= Coeff01;
AuxCoeff02 <= Coeff02;
AuxCoeff03 <= Coeff03;
AuxCoeff04 <= Coeff04;
AuxCoeff05 <= Coeff05;
AuxCoeff06 <= Coeff06;
AuxCoeff07 <= Coeff07;
AuxCoeff08 <= Coeff08;
AuxCoeff09 <= Coeff09;
AuxCoeff10 <= Coeff10;
AuxCoeff11 <= Coeff11;
AuxCoeff12 <= Coeff12;
AuxCoeff13 <= Coeff13;
AuxCoeff14 <= Coeff14;
AuxCoeff15 <= Coeff15;
AuxCoeff16 <= Coeff16;
AuxCoeff17 <= Coeff17;
AuxCoeff18 <= Coeff18;
AuxCoeff19 <= Coeff19;
AuxCoeff20 <= OffsetIn;
end
assign OffsetOut = AuxCoeff20;
always @(SELCoeffX, AuxCoeff00,AuxCoeff01,AuxCoeff02,AuxCoeff03,AuxCoeff04,AuxCoeff05,AuxCoeff06,
AuxCoeff07,AuxCoeff08,AuxCoeff09)
case (SELCoeffX)
5'd00: OutCoeffX <= AuxCoeff00;
5'd01: OutCoeffX <= AuxCoeff01;
5'd02: OutCoeffX <= AuxCoeff02;
5'd03: OutCoeffX <= AuxCoeff03;
5'd04: OutCoeffX <= AuxCoeff04;
5'd05: OutCoeffX <= AuxCoeff05;
5'd06: OutCoeffX <= AuxCoeff06;
5'd07: OutCoeffX <= AuxCoeff07;
5'd08: OutCoeffX <= AuxCoeff08;
5'd09: OutCoeffX <= AuxCoeff09;
default : OutCoeffX <= 0;
endcase
always @(SELCoeffY,AuxCoeff10,AuxCoeff11,AuxCoeff12,AuxCoeff13,AuxCoeff14,AuxCoeff15,AuxCoeff16,
AuxCoeff17,AuxCoeff18,AuxCoeff19)
case (SELCoeffY)
5'd00: OutCoeffY <= AuxCoeff10;
5'd01: OutCoeffY <= AuxCoeff11;
5'd02: OutCoeffY <= AuxCoeff12;
5'd03: OutCoeffY <= AuxCoeff13;
5'd04: OutCoeffY <= AuxCoeff14;
5'd05: OutCoeffY <= AuxCoeff15;
5'd06: OutCoeffY <= AuxCoeff16;
5'd07: OutCoeffY <= AuxCoeff17;
5'd08: OutCoeffY <= AuxCoeff18;
5'd09: OutCoeffY <= AuxCoeff19;
default : OutCoeffY <= 0;
endcase
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_PP_V
/**
* lpflow_inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso0n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, SLEEP_B );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , and0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_PP_V |
module ascii (
input clk,
input scan_ready,
input [7:0] scan_code,
output [7:0] ascii
);
reg [7:0] r_ascii;
reg [1:0] scan_ready_edge_detect = 2'b00;
assign ascii = r_ascii;
//reg keyup = 0;
reg extended = 0;
reg shift = 0;
reg [1:0] caps = 2'b00;
wire caps_lock;
reg [7:0] code;
reg [7:0] key_code [2:0];
reg [1:0] key_mem_index = 2'b00;
reg [1:0] key_current_index = 2'b00;
reg key_clear = 0;
reg [7:0] current_code;
reg [7:0] break_code;
reg [7:0] state_code;
reg [2:0] state_reg = 2'b00;
// state machine parameters
parameter st_idle = 3'b000;
parameter st_code_1 = 3'b001;
parameter st_code_2 = 3'b010;
parameter st_code_3 = 3'b011;
parameter st_break = 3'b100;
parameter st_extended = 3'b101;
parameter st_ready = 3'b110;
assign caps_lock = caps[0]; // odd number of presses
// posedge of the ps2 clock
always @(posedge clk) begin
scan_ready_edge_detect <= {scan_ready_edge_detect[0], scan_ready};
end
always @(posedge clk) begin
case (state_reg)
st_idle:
begin
if (scan_ready_edge_detect == 2'b01) begin
current_code <= scan_code;
state_reg <= st_code_1;
end
end
st_code_1:
begin
state_code <= current_code;
state_reg <= st_code_2;
end
st_code_2:
begin
// break code
if (state_code == 8'hf0) begin
state_reg <= st_break;
end else begin
state_reg <= st_code_3;
end
end
st_code_3:
begin
state_reg <= st_ready;
end
st_break:
begin
// key up
code <= 8'h00;
if (scan_ready_edge_detect == 2'b01) begin
state_reg <= st_idle;
break_code <= scan_code;
end
end
st_extended:
begin
end
st_ready:
begin
code <= state_code;
state_reg <= st_idle;
end
default:
begin
end
endcase
end
// Caps lock
always @(posedge clk) begin
if (scan_ready_edge_detect == 2'b01 && code == 8'h58) begin
caps <= caps + 2'b1;
end
end
// LEFT SHIFT || RIGHT SHIFT
always @(posedge clk) begin
if (code == 8'h12 || code == 8'h59) begin
shift <= 1;
end else if (break_code == 8'h12 || break_code == 8'h59) begin
shift <= 0;
end
end
/*
// Store char codes & remove then when their break code arrives.
always @(posedge clk) begin
if (scan_ready_edge_detect == 2'b01) begin
// LEFT SHIFT || RIGHT SHIFT
if (scan_code == 8'h12 || scan_code == 8'h59) begin
if (key_clear) begin
shift <= 0;
end else begin
shift <= 1;
end
end else if (scan_code == 8'hf0) begin // break code
// Clear the next scan code from the key_code memory.
key_clear <= 1'b1;
end else if (key_clear) begin
// Find the key code in the memory & clear it.
key_clear <= 1'b0;
extended <= 1'b0;
if (key_code[0] == scan_code) begin
key_code[0] <= 8'h00;
// if (key_current_index == 2'b0) begin
// key_current_index <= 2'b10;
// end else begin
// key_current_index <= key_current_index - 1'b1;
// end
end
else if (key_code[1] == scan_code) begin
key_code[1] <= 8'h00;
// if (key_current_index == 2'b0) begin
// key_current_index <= 2'b10;
// end else begin
// key_current_index <= key_current_index - 1'b1;
// end
end
else if (key_code[2] == scan_code) begin
key_code[2] <= 8'h00;
// if (key_current_index == 2'b0) begin
// key_current_index <= 2'b10;
// end else begin
// key_current_index <= key_current_index - 1'b1;
// end
end
end else begin
// Store the key code.
key_current_index <= key_mem_index;
if (key_mem_index == 2'b10) begin
key_mem_index <= 2'b00;
end else begin
key_mem_index <= key_mem_index + 2'b01;
end
key_code[key_mem_index] <= scan_code;
end
if (scan_code == 8'he0) begin
// extended make codes
extended <= 1'b1;
end
// Caps lock
if (code == 8'h58) begin
caps = caps + 2'b01;
end
end
end
always @(posedge clk) begin
code <= key_code[key_current_index];
end
*/
always @(posedge clk) begin
if (extended) begin
//extended <= 0;
case (code)
// nand2tetris special codes
8'h6b: r_ascii <= 8'd130; // L ARROW
8'h75: r_ascii <= 8'd131; // UP ARROW
8'h74: r_ascii <= 8'd132; // R ARROW
8'h72: r_ascii <= 8'd133; // DOWN ARROW
8'h6c: r_ascii <= 8'd134; // HOME
8'h69: r_ascii <= 8'd135; // END
8'h7d: r_ascii <= 8'd136; // PAGE UP
8'h7a: r_ascii <= 8'd137; // PAGE DOWN
8'h70: r_ascii <= 8'd138; // INSERT
8'h71: r_ascii <= 8'd139; // DELETE
default: r_ascii <= 8'd0; // null
endcase
end else
if ((shift && !caps_lock) || (caps_lock && !shift)) begin
case (code)
8'h29: r_ascii <= 8'd32; // [space]
8'h16: r_ascii <= 8'd33; // !
8'h52: r_ascii <= 8'd34; // "
8'h26: r_ascii <= 8'd35; // #
8'h25: r_ascii <= 8'd36; // $
8'h2e: r_ascii <= 8'd37; // %
8'h3d: r_ascii <= 8'd38; // &
8'h46: r_ascii <= 8'd40; // (
8'h45: r_ascii <= 8'd41; // )
8'h3e: r_ascii <= 8'd42; // *
8'h55: r_ascii <= 8'd43; // +
8'h4c: r_ascii <= 8'd58; // :
8'h41: r_ascii <= 8'd60; // <
8'h49: r_ascii <= 8'd62; // >
8'h4a: r_ascii <= 8'd63; // ?
8'h1e: r_ascii <= 8'd64; // @
8'h1c: r_ascii <= 8'd65; // A
8'h32: r_ascii <= 8'd66; // B
8'h21: r_ascii <= 8'd67; // C
8'h23: r_ascii <= 8'd68; // D
8'h24: r_ascii <= 8'd69; // E
8'h2b: r_ascii <= 8'd70; // F
8'h34: r_ascii <= 8'd71; // G
8'h33: r_ascii <= 8'd72; // H
8'h43: r_ascii <= 8'd73; // I
8'h3b: r_ascii <= 8'd74; // J
8'h42: r_ascii <= 8'd75; // K
8'h4b: r_ascii <= 8'd76; // L
8'h3a: r_ascii <= 8'd77; // M
8'h31: r_ascii <= 8'd78; // N
8'h44: r_ascii <= 8'd79; // O
8'h4d: r_ascii <= 8'd80; // P
8'h15: r_ascii <= 8'd81; // Q
8'h2d: r_ascii <= 8'd82; // R
8'h1b: r_ascii <= 8'd83; // S
8'h2c: r_ascii <= 8'd84; // T
8'h3c: r_ascii <= 8'd85; // U
8'h2a: r_ascii <= 8'd86; // V
8'h1d: r_ascii <= 8'd87; // W
8'h22: r_ascii <= 8'd88; // X
8'h35: r_ascii <= 8'd89; // Y
8'h1a: r_ascii <= 8'd90; // Z
8'h36: r_ascii <= 8'd94; // ^
8'h4e: r_ascii <= 8'd95; // _
8'h54: r_ascii <= 8'd123; // {
8'h5d: r_ascii <= 8'd124; // |
8'h5b: r_ascii <= 8'd125; // }
8'h0e: r_ascii <= 8'd126; // ~
default: r_ascii <= 8'd0; // null
endcase
end else begin
case (code)
8'h0d: r_ascii <= 8'd9; // [tab]
//8'h14: r_ascii <= L CTRL
//8'h11: r_ascii <= L ALT
//8'h7e: r_ascii <= SCROLL
//8'h77: r_ascii <= NUM
8'h29: r_ascii <= 8'd32; // [space]
8'h52: r_ascii <= 8'd39; // '
8'h7c: r_ascii <= 8'd42; // KP *
8'h79: r_ascii <= 8'd43; // KP +
8'h41: r_ascii <= 8'd44; // ,
8'h49: r_ascii <= 8'd46; // .
8'h71: r_ascii <= 8'd46; // KP .
8'h4e: r_ascii <= 8'd45; // -
8'h7b: r_ascii <= 8'd45; // KP -
8'h4a: r_ascii <= 8'd47; // /
8'h45: r_ascii <= 8'd48; // 0
8'h70: r_ascii <= 8'd48; // KP 0
8'h16: r_ascii <= 8'd49; // 1
8'h69: r_ascii <= 8'd49; // KP 1
8'h1e: r_ascii <= 8'd50; // 2
8'h72: r_ascii <= 8'd50; // KP 2
8'h26: r_ascii <= 8'd51; // 3
8'h7a: r_ascii <= 8'd51; // KP 3
8'h25: r_ascii <= 8'd52; // 4
8'h6b: r_ascii <= 8'd52; // KP 4
8'h2e: r_ascii <= 8'd53; // 5
8'h73: r_ascii <= 8'd53; // KP 5
8'h36: r_ascii <= 8'd54; // 6
8'h74: r_ascii <= 8'd54; // KP 6
8'h3d: r_ascii <= 8'd55; // 7
8'h6c: r_ascii <= 8'd55; // KP 7
8'h3e: r_ascii <= 8'd56; // 8
8'h75: r_ascii <= 8'd56; // KP 8
8'h46: r_ascii <= 8'd57; // 9
8'h7d: r_ascii <= 8'd57; // KP 9
8'h4c: r_ascii <= 8'd59; // ;
8'h55: r_ascii <= 8'd61; // =
8'h54: r_ascii <= 8'd91; // [
8'h5d: r_ascii <= 8'd92; // \
8'h5b: r_ascii <= 8'd93; // ]
8'h0e: r_ascii <= 8'd96; // `
8'h1c: r_ascii <= 8'd97; // a
8'h32: r_ascii <= 8'd98; // b
8'h21: r_ascii <= 8'd99; // c
8'h23: r_ascii <= 8'd100; // d
8'h24: r_ascii <= 8'd101; // e
8'h2b: r_ascii <= 8'd102; // f
8'h34: r_ascii <= 8'd103; // g
8'h33: r_ascii <= 8'd104; // h
8'h43: r_ascii <= 8'd105; // i
8'h3b: r_ascii <= 8'd106; // j
8'h42: r_ascii <= 8'd107; // k
8'h4b: r_ascii <= 8'd108; // l
8'h3a: r_ascii <= 8'd109; // m
8'h31: r_ascii <= 8'd110; // n
8'h44: r_ascii <= 8'd111; // o
8'h4d: r_ascii <= 8'd112; // p
8'h15: r_ascii <= 8'd113; // q
8'h2d: r_ascii <= 8'd114; // r
8'h1b: r_ascii <= 8'd115; // s
8'h2c: r_ascii <= 8'd116; // t
8'h3c: r_ascii <= 8'd117; // u
8'h2a: r_ascii <= 8'd118; // v
8'h1d: r_ascii <= 8'd119; // w
8'h22: r_ascii <= 8'd120; // x
8'h35: r_ascii <= 8'd121; // y
8'h1a: r_ascii <= 8'd122; // z
// nand2tetris special codes
8'h5a: r_ascii <= 8'd128; // [enter]
8'h66: r_ascii <= 8'd129; // [back space]
8'h76: r_ascii <= 8'd140; // ESCAPE
8'h05: r_ascii <= 8'd141; // F1
8'h06: r_ascii <= 8'd142; // F2
8'h04: r_ascii <= 8'd143; // F3
8'h0c: r_ascii <= 8'd144; // F4
8'h03: r_ascii <= 8'd145; // F5
8'h0b: r_ascii <= 8'd146; // F6
8'h83: r_ascii <= 8'd147; // F7
8'h0a: r_ascii <= 8'd148; // F8
8'h01: r_ascii <= 8'd149; // F9
8'h09: r_ascii <= 8'd150; // F10
8'h78: r_ascii <= 8'd151; // F11
8'h07: r_ascii <= 8'd152; // F12
default: r_ascii <= 8'd0; // null
endcase
end
end
endmodule
|
module s27_path (
G1,
G2,
clk_net,
reset_net,
G3,
G0,
G17);
// Start PIs
input G1;
input G2;
input clk_net;
input reset_net;
input G3;
input G0;
// Start POs
output G17;
// Start wires
wire G1;
wire net_5;
wire net_15;
wire net_27;
wire G17;
wire reset_net;
wire net_14;
wire G3;
wire net_26;
wire clk_net;
wire net_13;
wire G2;
wire net_19;
wire net_3;
wire net_22;
wire net_16;
wire net_6;
wire net_24;
wire net_11;
wire net_1;
wire net_23;
wire net_18;
wire net_12;
wire net_2;
wire net_10;
wire net_8;
wire net_9;
wire net_25;
wire net_21;
wire net_7;
wire net_20;
wire G0;
wire net_4;
wire net_17;
// Start cells
CLKBUF_X2 inst_19 ( .A(net_17), .Z(net_18) );
DFFR_X2 inst_14 ( .RN(net_12), .D(net_10), .QN(net_3), .CK(net_27) );
INV_X1 inst_12 ( .A(net_16), .ZN(G17) );
INV_X4 inst_8 ( .ZN(net_5), .A(net_1) );
NOR2_X4 inst_2 ( .ZN(net_11), .A2(net_9), .A1(net_6) );
NOR2_X4 inst_1 ( .A1(net_14), .ZN(net_8), .A2(G3) );
CLKBUF_X2 inst_21 ( .A(net_19), .Z(net_20) );
CLKBUF_X2 inst_25 ( .A(net_23), .Z(net_24) );
NAND2_X2 inst_7 ( .ZN(net_7), .A1(net_4), .A2(net_3) );
CLKBUF_X2 inst_20 ( .A(net_18), .Z(net_19) );
INV_X1 inst_13 ( .ZN(net_12), .A(reset_net) );
CLKBUF_X2 inst_27 ( .A(net_25), .Z(net_26) );
CLKBUF_X2 inst_26 ( .A(net_17), .Z(net_25) );
NOR3_X4 inst_0 ( .ZN(net_16), .A1(net_11), .A3(net_8), .A2(net_5) );
CLKBUF_X2 inst_18 ( .A(clk_net), .Z(net_17) );
DFFR_X2 inst_15 ( .D(net_16), .RN(net_12), .QN(net_2), .CK(net_19) );
DFFR_X2 inst_16 ( .D(net_13), .RN(net_12), .QN(net_1), .CK(net_24) );
CLKBUF_X2 inst_24 ( .A(net_22), .Z(net_23) );
NOR2_X2 inst_3 ( .ZN(net_14), .A1(net_2), .A2(G0) );
NOR2_X2 inst_6 ( .A1(net_16), .A2(net_15), .ZN(net_13) );
INV_X4 inst_9 ( .ZN(net_9), .A(net_7) );
NOR2_X2 inst_5 ( .ZN(net_10), .A2(net_9), .A1(G2) );
INV_X2 inst_10 ( .ZN(net_4), .A(G1) );
NOR2_X2 inst_4 ( .ZN(net_6), .A1(net_2), .A2(G0) );
CLKBUF_X2 inst_23 ( .A(net_21), .Z(net_22) );
INV_X2 inst_11 ( .ZN(net_15), .A(G0) );
CLKBUF_X2 inst_28 ( .A(net_26), .Z(net_27) );
CLKBUF_X2 inst_22 ( .A(net_20), .Z(net_21) );
endmodule
|
// DUT based on oh/elink/dv/dut_axi_elink.v
//
`include "elink_regmap.vh"
module dut(/*AUTOARG*/
// Outputs
clkout, dut_active, wait_out, access_out, packet_out,
// Inputs
clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
);
//##########################################################################
//# INTERFACE
//##########################################################################
parameter AW = 32;
parameter ID = 12'h810;
parameter S_IDW = 12;
parameter S2_IDW = 12;
parameter M_IDW = 6;
parameter M2_IDW = 6;
parameter PW = 2*AW + 40;
parameter N = 1;
parameter RETURN_ADDR = {ID,
`EGROUP_RR,
16'b0}; // axi return addr
//clock,reset
input clk1;
input clk2;
output clkout;
input nreset;
input [N*N-1:0] vdd;
input vss;
output dut_active;
//Stimulus Driven Transaction
input [N-1:0] access_in;
input [N*PW-1:0] packet_in;
output [N-1:0] wait_out;
//DUT driven transaction
output [N-1:0] access_out;
output [N*PW-1:0] packet_out;
input [N-1:0] wait_in;
//##########################################################################
//#BODY
//##########################################################################
wire mem_rd_wait;
wire mem_wr_wait;
wire mem_access;
wire [PW-1:0] mem_packet;
/*AUTOINPUT*/
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire elink0_cclk_n; // From elink0 of axi_elink.v
wire elink0_cclk_p; // From elink0 of axi_elink.v
wire elink0_chip_nreset; // From elink0 of axi_elink.v
wire [11:0] elink0_chipid; // From elink0 of axi_elink.v
wire [31:0] elink0_m_axi_araddr; // From elink0 of axi_elink.v
wire [1:0] elink0_m_axi_arburst; // From elink0 of axi_elink.v
wire [3:0] elink0_m_axi_arcache; // From elink0 of axi_elink.v
wire [M_IDW-1:0] elink0_m_axi_arid; // From elink0 of axi_elink.v
wire [7:0] elink0_m_axi_arlen; // From elink0 of axi_elink.v
wire elink0_m_axi_arlock; // From elink0 of axi_elink.v
wire [2:0] elink0_m_axi_arprot; // From elink0 of axi_elink.v
wire [3:0] elink0_m_axi_arqos; // From elink0 of axi_elink.v
wire elink0_m_axi_arready; // From axislave_stub of axislave_stub.v
wire [2:0] elink0_m_axi_arsize; // From elink0 of axi_elink.v
wire elink0_m_axi_arvalid; // From elink0 of axi_elink.v
wire [31:0] elink0_m_axi_awaddr; // From elink0 of axi_elink.v
wire [1:0] elink0_m_axi_awburst; // From elink0 of axi_elink.v
wire [3:0] elink0_m_axi_awcache; // From elink0 of axi_elink.v
wire [M_IDW-1:0] elink0_m_axi_awid; // From elink0 of axi_elink.v
wire [7:0] elink0_m_axi_awlen; // From elink0 of axi_elink.v
wire elink0_m_axi_awlock; // From elink0 of axi_elink.v
wire [2:0] elink0_m_axi_awprot; // From elink0 of axi_elink.v
wire [3:0] elink0_m_axi_awqos; // From elink0 of axi_elink.v
wire elink0_m_axi_awready; // From axislave_stub of axislave_stub.v
wire [2:0] elink0_m_axi_awsize; // From elink0 of axi_elink.v
wire elink0_m_axi_awvalid; // From elink0 of axi_elink.v
wire [S_IDW-1:0] elink0_m_axi_bid; // From axislave_stub of axislave_stub.v
wire elink0_m_axi_bready; // From elink0 of axi_elink.v
wire [1:0] elink0_m_axi_bresp; // From axislave_stub of axislave_stub.v
wire elink0_m_axi_bvalid; // From axislave_stub of axislave_stub.v
wire [31:0] elink0_m_axi_rdata; // From axislave_stub of axislave_stub.v
wire [S_IDW-1:0] elink0_m_axi_rid; // From axislave_stub of axislave_stub.v
wire elink0_m_axi_rlast; // From axislave_stub of axislave_stub.v
wire elink0_m_axi_rready; // From elink0 of axi_elink.v
wire [1:0] elink0_m_axi_rresp; // From axislave_stub of axislave_stub.v
wire elink0_m_axi_rvalid; // From axislave_stub of axislave_stub.v
wire [63:0] elink0_m_axi_wdata; // From elink0 of axi_elink.v
wire [M_IDW-1:0] elink0_m_axi_wid; // From elink0 of axi_elink.v
wire elink0_m_axi_wlast; // From elink0 of axi_elink.v
wire elink0_m_axi_wready; // From axislave_stub of axislave_stub.v
wire [7:0] elink0_m_axi_wstrb; // From elink0 of axi_elink.v
wire elink0_m_axi_wvalid; // From elink0 of axi_elink.v
wire elink0_mailbox_irq; // From elink0 of axi_elink.v
wire elink0_rxo_rd_wait_n; // From elink0 of axi_elink.v
wire elink0_rxo_rd_wait_p; // From elink0 of axi_elink.v
wire elink0_rxo_wr_wait_n; // From elink0 of axi_elink.v
wire elink0_rxo_wr_wait_p; // From elink0 of axi_elink.v
wire [7:0] elink0_txo_data_n; // From elink0 of axi_elink.v
wire [7:0] elink0_txo_data_p; // From elink0 of axi_elink.v
wire elink0_txo_frame_n; // From elink0 of axi_elink.v
wire elink0_txo_frame_p; // From elink0 of axi_elink.v
wire elink0_txo_lclk_n; // From elink0 of axi_elink.v
wire elink0_txo_lclk_p; // From elink0 of axi_elink.v
wire elink1_cclk_n; // From elink1 of axi_elink.v
wire elink1_cclk_p; // From elink1 of axi_elink.v
wire elink1_chip_nreset; // From elink1 of axi_elink.v
wire [11:0] elink1_chipid; // From elink1 of axi_elink.v
wire elink1_elink_active; // From elink1 of axi_elink.v
wire elink1_mailbox_irq; // From elink1 of axi_elink.v
wire elink1_rxo_rd_wait_n; // From elink1 of axi_elink.v
wire elink1_rxo_rd_wait_p; // From elink1 of axi_elink.v
wire elink1_rxo_wr_wait_n; // From elink1 of axi_elink.v
wire elink1_rxo_wr_wait_p; // From elink1 of axi_elink.v
wire [7:0] elink1_txo_data_n; // From elink1 of axi_elink.v
wire [7:0] elink1_txo_data_p; // From elink1 of axi_elink.v
wire elink1_txo_frame_n; // From elink1 of axi_elink.v
wire elink1_txo_frame_p; // From elink1 of axi_elink.v
wire elink1_txo_lclk_n; // From elink1 of axi_elink.v
wire elink1_txo_lclk_p; // From elink1 of axi_elink.v
wire [31:0] ext1_m_axi_araddr; // From emaxi1 of emaxi.v
wire [1:0] ext1_m_axi_arburst; // From emaxi1 of emaxi.v
wire [3:0] ext1_m_axi_arcache; // From emaxi1 of emaxi.v
wire [M_IDW-1:0] ext1_m_axi_arid; // From emaxi1 of emaxi.v
wire [7:0] ext1_m_axi_arlen; // From emaxi1 of emaxi.v
wire ext1_m_axi_arlock; // From emaxi1 of emaxi.v
wire [2:0] ext1_m_axi_arprot; // From emaxi1 of emaxi.v
wire [3:0] ext1_m_axi_arqos; // From emaxi1 of emaxi.v
wire ext1_m_axi_arready; // From elink1 of axi_elink.v
wire [2:0] ext1_m_axi_arsize; // From emaxi1 of emaxi.v
wire ext1_m_axi_arvalid; // From emaxi1 of emaxi.v
wire [31:0] ext1_m_axi_awaddr; // From emaxi1 of emaxi.v
wire [1:0] ext1_m_axi_awburst; // From emaxi1 of emaxi.v
wire [3:0] ext1_m_axi_awcache; // From emaxi1 of emaxi.v
wire [M_IDW-1:0] ext1_m_axi_awid; // From emaxi1 of emaxi.v
wire [7:0] ext1_m_axi_awlen; // From emaxi1 of emaxi.v
wire ext1_m_axi_awlock; // From emaxi1 of emaxi.v
wire [2:0] ext1_m_axi_awprot; // From emaxi1 of emaxi.v
wire [3:0] ext1_m_axi_awqos; // From emaxi1 of emaxi.v
wire ext1_m_axi_awready; // From elink1 of axi_elink.v
wire [2:0] ext1_m_axi_awsize; // From emaxi1 of emaxi.v
wire ext1_m_axi_awvalid; // From emaxi1 of emaxi.v
wire [S_IDW-1:0] ext1_m_axi_bid; // From elink1 of axi_elink.v
wire ext1_m_axi_bready; // From emaxi1 of emaxi.v
wire [1:0] ext1_m_axi_bresp; // From elink1 of axi_elink.v
wire ext1_m_axi_bvalid; // From elink1 of axi_elink.v
wire [31:0] ext1_m_axi_rdata; // From elink1 of axi_elink.v
wire [S_IDW-1:0] ext1_m_axi_rid; // From elink1 of axi_elink.v
wire ext1_m_axi_rlast; // From elink1 of axi_elink.v
wire ext1_m_axi_rready; // From emaxi1 of emaxi.v
wire [1:0] ext1_m_axi_rresp; // From elink1 of axi_elink.v
wire ext1_m_axi_rvalid; // From elink1 of axi_elink.v
wire [63:0] ext1_m_axi_wdata; // From emaxi1 of emaxi.v
wire [M_IDW-1:0] ext1_m_axi_wid; // From emaxi1 of emaxi.v
wire ext1_m_axi_wlast; // From emaxi1 of emaxi.v
wire ext1_m_axi_wready; // From elink1 of axi_elink.v
wire [7:0] ext1_m_axi_wstrb; // From emaxi1 of emaxi.v
wire ext1_m_axi_wvalid; // From emaxi1 of emaxi.v
wire [31:0] m_axi_araddr; // From emaxi0 of emaxi.v
wire [1:0] m_axi_arburst; // From emaxi0 of emaxi.v
wire [3:0] m_axi_arcache; // From emaxi0 of emaxi.v
wire [M_IDW-1:0] m_axi_arid; // From emaxi0 of emaxi.v
wire [7:0] m_axi_arlen; // From emaxi0 of emaxi.v
wire m_axi_arlock; // From emaxi0 of emaxi.v
wire [2:0] m_axi_arprot; // From emaxi0 of emaxi.v
wire [3:0] m_axi_arqos; // From emaxi0 of emaxi.v
wire m_axi_arready; // From elink0 of axi_elink.v
wire [2:0] m_axi_arsize; // From emaxi0 of emaxi.v
wire m_axi_arvalid; // From emaxi0 of emaxi.v
wire [31:0] m_axi_awaddr; // From emaxi0 of emaxi.v
wire [1:0] m_axi_awburst; // From emaxi0 of emaxi.v
wire [3:0] m_axi_awcache; // From emaxi0 of emaxi.v
wire [M_IDW-1:0] m_axi_awid; // From emaxi0 of emaxi.v
wire [7:0] m_axi_awlen; // From emaxi0 of emaxi.v
wire m_axi_awlock; // From emaxi0 of emaxi.v
wire [2:0] m_axi_awprot; // From emaxi0 of emaxi.v
wire [3:0] m_axi_awqos; // From emaxi0 of emaxi.v
wire m_axi_awready; // From elink0 of axi_elink.v
wire [2:0] m_axi_awsize; // From emaxi0 of emaxi.v
wire m_axi_awvalid; // From emaxi0 of emaxi.v
wire [S_IDW-1:0] m_axi_bid; // From elink0 of axi_elink.v
wire m_axi_bready; // From emaxi0 of emaxi.v
wire [1:0] m_axi_bresp; // From elink0 of axi_elink.v
wire m_axi_bvalid; // From elink0 of axi_elink.v
wire [31:0] m_axi_rdata; // From elink0 of axi_elink.v
wire [S_IDW-1:0] m_axi_rid; // From elink0 of axi_elink.v
wire m_axi_rlast; // From elink0 of axi_elink.v
wire m_axi_rready; // From emaxi0 of emaxi.v
wire [1:0] m_axi_rresp; // From elink0 of axi_elink.v
wire m_axi_rvalid; // From elink0 of axi_elink.v
wire [63:0] m_axi_wdata; // From emaxi0 of emaxi.v
wire [M_IDW-1:0] m_axi_wid; // From emaxi0 of emaxi.v
wire m_axi_wlast; // From emaxi0 of emaxi.v
wire m_axi_wready; // From elink0 of axi_elink.v
wire [7:0] m_axi_wstrb; // From emaxi0 of emaxi.v
wire m_axi_wvalid; // From emaxi0 of emaxi.v
wire [31:0] mem_m_axi_araddr; // From elink1 of axi_elink.v
wire [1:0] mem_m_axi_arburst; // From elink1 of axi_elink.v
wire [3:0] mem_m_axi_arcache; // From elink1 of axi_elink.v
wire [M_IDW-1:0] mem_m_axi_arid; // From elink1 of axi_elink.v
wire [7:0] mem_m_axi_arlen; // From elink1 of axi_elink.v
wire mem_m_axi_arlock; // From elink1 of axi_elink.v
wire [2:0] mem_m_axi_arprot; // From elink1 of axi_elink.v
wire [3:0] mem_m_axi_arqos; // From elink1 of axi_elink.v
wire mem_m_axi_arready; // From esaxi of esaxi.v
wire [2:0] mem_m_axi_arsize; // From elink1 of axi_elink.v
wire mem_m_axi_arvalid; // From elink1 of axi_elink.v
wire [31:0] mem_m_axi_awaddr; // From elink1 of axi_elink.v
wire [1:0] mem_m_axi_awburst; // From elink1 of axi_elink.v
wire [3:0] mem_m_axi_awcache; // From elink1 of axi_elink.v
wire [M_IDW-1:0] mem_m_axi_awid; // From elink1 of axi_elink.v
wire [7:0] mem_m_axi_awlen; // From elink1 of axi_elink.v
wire mem_m_axi_awlock; // From elink1 of axi_elink.v
wire [2:0] mem_m_axi_awprot; // From elink1 of axi_elink.v
wire [3:0] mem_m_axi_awqos; // From elink1 of axi_elink.v
wire mem_m_axi_awready; // From esaxi of esaxi.v
wire [2:0] mem_m_axi_awsize; // From elink1 of axi_elink.v
wire mem_m_axi_awvalid; // From elink1 of axi_elink.v
wire [S_IDW-1:0] mem_m_axi_bid; // From esaxi of esaxi.v
wire mem_m_axi_bready; // From elink1 of axi_elink.v
wire [1:0] mem_m_axi_bresp; // From esaxi of esaxi.v
wire mem_m_axi_bvalid; // From esaxi of esaxi.v
wire [31:0] mem_m_axi_rdata; // From esaxi of esaxi.v
wire [S_IDW-1:0] mem_m_axi_rid; // From esaxi of esaxi.v
wire mem_m_axi_rlast; // From esaxi of esaxi.v
wire mem_m_axi_rready; // From elink1 of axi_elink.v
wire [1:0] mem_m_axi_rresp; // From esaxi of esaxi.v
wire mem_m_axi_rvalid; // From esaxi of esaxi.v
wire [63:0] mem_m_axi_wdata; // From elink1 of axi_elink.v
wire [M_IDW-1:0] mem_m_axi_wid; // From elink1 of axi_elink.v
wire mem_m_axi_wlast; // From elink1 of axi_elink.v
wire mem_m_axi_wready; // From esaxi of esaxi.v
wire [7:0] mem_m_axi_wstrb; // From elink1 of axi_elink.v
wire mem_m_axi_wvalid; // From elink1 of axi_elink.v
wire mem_rd_access; // From esaxi of esaxi.v
wire [PW-1:0] mem_rd_packet; // From esaxi of esaxi.v
wire mem_rr_access; // From ememory of ememory.v
wire [PW-1:0] mem_rr_packet; // From ememory of ememory.v
wire mem_rr_wait; // From esaxi of esaxi.v
wire mem_wait; // From ememory of ememory.v
wire mem_wr_access; // From esaxi of esaxi.v
wire [PW-1:0] mem_wr_packet; // From esaxi of esaxi.v
wire rd_wait0; // From emaxi0 of emaxi.v
wire rd_wait1; // From emaxi1 of emaxi.v
wire rr_access; // From emaxi1 of emaxi.v
wire [PW-1:0] rr_packet; // From emaxi1 of emaxi.v
wire wr_wait0; // From emaxi0 of emaxi.v
wire wr_wait1; // From emaxi1 of emaxi.v
// End of automatics
//###################
// GLUE
//###################
assign clkout = clk1;
// Provide an easy way to send mailbox messages to elink0 via the 0x910 address
wire elink0_access_in;
wire elink1_access_in;
wire ext1_write_in;
wire ext1_read_in;
assign elink0_access_in = access_in &
(packet_in[39:28]==12'h810 |
packet_in[39:28]==12'h808 |
packet_in[39:28]==12'h920);
assign elink1_access_in = access_in &
(packet_in[39:28]==12'h820 |
packet_in[39:28]==12'h910);
assign ext1_write_in = elink1_access_in & packet_in[0];
assign ext1_read_in = elink1_access_in & ~packet_in[0];
//######################################################################
//AXI MASTER
//######################################################################
wire write_in;
wire read_in;
//Split stimulus to read/write
assign wait_out = wr_wait0 | rd_wait0 | wr_wait1 | rd_wait1;
assign write_in = elink0_access_in & packet_in[0];
assign read_in = elink0_access_in & ~packet_in[0];
//######################################################################
//AXI MASTER (DRIVES STIMULUS) to configure elink0
//######################################################################
/*emaxi AUTO_TEMPLATE (//Stimulus
.m_axi_aresetn (nreset),
.m_axi_aclk (clk1),
.m_axi_rdata ({m_axi_rdata[31:0],m_axi_rdata[31:0]}),
.m_\(.*\) (m_\1[]),
.rr_wait (wait_in),
.rr_access (access_out),
.rr_packet (packet_out[PW-1:0]),
.wr_access (write_in),
.wr_packet (packet_in[PW-1:0]),
.rd_access (read_in),
.rd_packet (packet_in[PW-1:0]),
.wr_wait (wr_wait0),
.rd_wait (rd_wait0),
);
*/
emaxi #(.M_IDW(M_IDW))
emaxi0 (/*AUTOINST*/
// Outputs
.wr_wait (wr_wait0), // Templated
.rd_wait (rd_wait0), // Templated
.rr_access (access_out), // Templated
.rr_packet (packet_out[PW-1:0]), // Templated
.m_axi_awid (m_axi_awid[M_IDW-1:0]), // Templated
.m_axi_awaddr (m_axi_awaddr[31:0]), // Templated
.m_axi_awlen (m_axi_awlen[7:0]), // Templated
.m_axi_awsize (m_axi_awsize[2:0]), // Templated
.m_axi_awburst (m_axi_awburst[1:0]), // Templated
.m_axi_awlock (m_axi_awlock), // Templated
.m_axi_awcache (m_axi_awcache[3:0]), // Templated
.m_axi_awprot (m_axi_awprot[2:0]), // Templated
.m_axi_awqos (m_axi_awqos[3:0]), // Templated
.m_axi_awvalid (m_axi_awvalid), // Templated
.m_axi_wid (m_axi_wid[M_IDW-1:0]), // Templated
.m_axi_wdata (m_axi_wdata[63:0]), // Templated
.m_axi_wstrb (m_axi_wstrb[7:0]), // Templated
.m_axi_wlast (m_axi_wlast), // Templated
.m_axi_wvalid (m_axi_wvalid), // Templated
.m_axi_bready (m_axi_bready), // Templated
.m_axi_arid (m_axi_arid[M_IDW-1:0]), // Templated
.m_axi_araddr (m_axi_araddr[31:0]), // Templated
.m_axi_arlen (m_axi_arlen[7:0]), // Templated
.m_axi_arsize (m_axi_arsize[2:0]), // Templated
.m_axi_arburst (m_axi_arburst[1:0]), // Templated
.m_axi_arlock (m_axi_arlock), // Templated
.m_axi_arcache (m_axi_arcache[3:0]), // Templated
.m_axi_arprot (m_axi_arprot[2:0]), // Templated
.m_axi_arqos (m_axi_arqos[3:0]), // Templated
.m_axi_arvalid (m_axi_arvalid), // Templated
.m_axi_rready (m_axi_rready), // Templated
// Inputs
.wr_access (write_in), // Templated
.wr_packet (packet_in[PW-1:0]), // Templated
.rd_access (read_in), // Templated
.rd_packet (packet_in[PW-1:0]), // Templated
.rr_wait (wait_in), // Templated
.m_axi_aclk (clk1), // Templated
.m_axi_aresetn (nreset), // Templated
.m_axi_awready (m_axi_awready), // Templated
.m_axi_wready (m_axi_wready), // Templated
.m_axi_bid (m_axi_bid[M_IDW-1:0]), // Templated
.m_axi_bresp (m_axi_bresp[1:0]), // Templated
.m_axi_bvalid (m_axi_bvalid), // Templated
.m_axi_arready (m_axi_arready), // Templated
.m_axi_rid (m_axi_rid[M_IDW-1:0]), // Templated
.m_axi_rdata ({m_axi_rdata[31:0],m_axi_rdata[31:0]}), // Templated
.m_axi_rresp (m_axi_rresp[1:0]), // Templated
.m_axi_rlast (m_axi_rlast), // Templated
.m_axi_rvalid (m_axi_rvalid)); // Templated
//######################################################################
//ELINK
//######################################################################
/*axi_elink AUTO_TEMPLATE (.m_axi_aresetn (nreset),
.s_axi_aresetn (nreset),
.sys_nreset (nreset),
.s_\(.*\) (m_\1[]),
.sys_clk (clk1),
.rxi_\(.*\) (elink1_txo_\1[]),
.txi_\(.*\) (elink1_rxo_\1[]),
.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
);
*/
axi_elink #(.ID(12'h810),
.ETYPE(0))
elink0 (.elink_active (dut_active),
.s_axi_wstrb ((m_axi_wstrb[3:0] | m_axi_wstrb[7:4])),//NOTE:HACK!!
.m_axi_rdata ({mem_m_axi_rdata[31:0],mem_m_axi_rdata[31:0]}),
/*AUTOINST*/
// Outputs
.rxo_wr_wait_p (elink0_rxo_wr_wait_p), // Templated
.rxo_wr_wait_n (elink0_rxo_wr_wait_n), // Templated
.rxo_rd_wait_p (elink0_rxo_rd_wait_p), // Templated
.rxo_rd_wait_n (elink0_rxo_rd_wait_n), // Templated
.txo_lclk_p (elink0_txo_lclk_p), // Templated
.txo_lclk_n (elink0_txo_lclk_n), // Templated
.txo_frame_p (elink0_txo_frame_p), // Templated
.txo_frame_n (elink0_txo_frame_n), // Templated
.txo_data_p (elink0_txo_data_p[7:0]), // Templated
.txo_data_n (elink0_txo_data_n[7:0]), // Templated
.chipid (elink0_chipid[11:0]), // Templated
.chip_nreset (elink0_chip_nreset), // Templated
.cclk_p (elink0_cclk_p), // Templated
.cclk_n (elink0_cclk_n), // Templated
.mailbox_irq (elink0_mailbox_irq), // Templated
.m_axi_awid (elink0_m_axi_awid[M_IDW-1:0]), // Templated
.m_axi_awaddr (elink0_m_axi_awaddr[31:0]), // Templated
.m_axi_awlen (elink0_m_axi_awlen[7:0]), // Templated
.m_axi_awsize (elink0_m_axi_awsize[2:0]), // Templated
.m_axi_awburst (elink0_m_axi_awburst[1:0]), // Templated
.m_axi_awlock (elink0_m_axi_awlock), // Templated
.m_axi_awcache (elink0_m_axi_awcache[3:0]), // Templated
.m_axi_awprot (elink0_m_axi_awprot[2:0]), // Templated
.m_axi_awqos (elink0_m_axi_awqos[3:0]), // Templated
.m_axi_awvalid (elink0_m_axi_awvalid), // Templated
.m_axi_wid (elink0_m_axi_wid[M_IDW-1:0]), // Templated
.m_axi_wdata (elink0_m_axi_wdata[63:0]), // Templated
.m_axi_wstrb (elink0_m_axi_wstrb[7:0]), // Templated
.m_axi_wlast (elink0_m_axi_wlast), // Templated
.m_axi_wvalid (elink0_m_axi_wvalid), // Templated
.m_axi_bready (elink0_m_axi_bready), // Templated
.m_axi_arid (elink0_m_axi_arid[M_IDW-1:0]), // Templated
.m_axi_araddr (elink0_m_axi_araddr[31:0]), // Templated
.m_axi_arlen (elink0_m_axi_arlen[7:0]), // Templated
.m_axi_arsize (elink0_m_axi_arsize[2:0]), // Templated
.m_axi_arburst (elink0_m_axi_arburst[1:0]), // Templated
.m_axi_arlock (elink0_m_axi_arlock), // Templated
.m_axi_arcache (elink0_m_axi_arcache[3:0]), // Templated
.m_axi_arprot (elink0_m_axi_arprot[2:0]), // Templated
.m_axi_arqos (elink0_m_axi_arqos[3:0]), // Templated
.m_axi_arvalid (elink0_m_axi_arvalid), // Templated
.m_axi_rready (elink0_m_axi_rready), // Templated
.s_axi_arready (m_axi_arready), // Templated
.s_axi_awready (m_axi_awready), // Templated
.s_axi_bid (m_axi_bid[S_IDW-1:0]), // Templated
.s_axi_bresp (m_axi_bresp[1:0]), // Templated
.s_axi_bvalid (m_axi_bvalid), // Templated
.s_axi_rid (m_axi_rid[S_IDW-1:0]), // Templated
.s_axi_rdata (m_axi_rdata[31:0]), // Templated
.s_axi_rlast (m_axi_rlast), // Templated
.s_axi_rresp (m_axi_rresp[1:0]), // Templated
.s_axi_rvalid (m_axi_rvalid), // Templated
.s_axi_wready (m_axi_wready), // Templated
// Inputs
.sys_nreset (nreset), // Templated
.sys_clk (clk1), // Templated
.rxi_lclk_p (elink1_txo_lclk_p), // Templated
.rxi_lclk_n (elink1_txo_lclk_n), // Templated
.rxi_frame_p (elink1_txo_frame_p), // Templated
.rxi_frame_n (elink1_txo_frame_n), // Templated
.rxi_data_p (elink1_txo_data_p[7:0]), // Templated
.rxi_data_n (elink1_txo_data_n[7:0]), // Templated
.txi_wr_wait_p (elink1_rxo_wr_wait_p), // Templated
.txi_wr_wait_n (elink1_rxo_wr_wait_n), // Templated
.txi_rd_wait_p (elink1_rxo_rd_wait_p), // Templated
.txi_rd_wait_n (elink1_rxo_rd_wait_n), // Templated
.m_axi_aresetn (nreset), // Templated
.m_axi_awready (elink0_m_axi_awready), // Templated
.m_axi_wready (elink0_m_axi_wready), // Templated
.m_axi_bid (elink0_m_axi_bid[M_IDW-1:0]), // Templated
.m_axi_bresp (elink0_m_axi_bresp[1:0]), // Templated
.m_axi_bvalid (elink0_m_axi_bvalid), // Templated
.m_axi_arready (elink0_m_axi_arready), // Templated
.m_axi_rid (elink0_m_axi_rid[M_IDW-1:0]), // Templated
.m_axi_rresp (elink0_m_axi_rresp[1:0]), // Templated
.m_axi_rlast (elink0_m_axi_rlast), // Templated
.m_axi_rvalid (elink0_m_axi_rvalid), // Templated
.s_axi_aresetn (nreset), // Templated
.s_axi_arid (m_axi_arid[S_IDW-1:0]), // Templated
.s_axi_araddr (m_axi_araddr[31:0]), // Templated
.s_axi_arburst (m_axi_arburst[1:0]), // Templated
.s_axi_arcache (m_axi_arcache[3:0]), // Templated
.s_axi_arlock (m_axi_arlock), // Templated
.s_axi_arlen (m_axi_arlen[7:0]), // Templated
.s_axi_arprot (m_axi_arprot[2:0]), // Templated
.s_axi_arqos (m_axi_arqos[3:0]), // Templated
.s_axi_arsize (m_axi_arsize[2:0]), // Templated
.s_axi_arvalid (m_axi_arvalid), // Templated
.s_axi_awid (m_axi_awid[S_IDW-1:0]), // Templated
.s_axi_awaddr (m_axi_awaddr[31:0]), // Templated
.s_axi_awburst (m_axi_awburst[1:0]), // Templated
.s_axi_awcache (m_axi_awcache[3:0]), // Templated
.s_axi_awlock (m_axi_awlock), // Templated
.s_axi_awlen (m_axi_awlen[7:0]), // Templated
.s_axi_awprot (m_axi_awprot[2:0]), // Templated
.s_axi_awqos (m_axi_awqos[3:0]), // Templated
.s_axi_awsize (m_axi_awsize[2:0]), // Templated
.s_axi_awvalid (m_axi_awvalid), // Templated
.s_axi_bready (m_axi_bready), // Templated
.s_axi_rready (m_axi_rready), // Templated
.s_axi_wid (m_axi_wid[S_IDW-1:0]), // Templated
.s_axi_wdata (m_axi_wdata[31:0]), // Templated
.s_axi_wlast (m_axi_wlast), // Templated
.s_axi_wvalid (m_axi_wvalid)); // Templated
//######################################################################
//TIE OFF UNUSED MASTER PORT ON ELINK0
//######################################################################
/*axislave_stub AUTO_TEMPLATE (
// Outputs
.s_\(.*\) (elink0_m_\1[]),
);
*/
defparam axislave_stub.S_IDW = S_IDW;
axislave_stub axislave_stub (.s_axi_aclk (clk1),
.s_axi_aresetn (nreset),
/*AUTOINST*/
// Outputs
.s_axi_arready (elink0_m_axi_arready), // Templated
.s_axi_awready (elink0_m_axi_awready), // Templated
.s_axi_bid (elink0_m_axi_bid[S_IDW-1:0]), // Templated
.s_axi_bresp (elink0_m_axi_bresp[1:0]), // Templated
.s_axi_bvalid (elink0_m_axi_bvalid), // Templated
.s_axi_rid (elink0_m_axi_rid[S_IDW-1:0]), // Templated
.s_axi_rdata (elink0_m_axi_rdata[31:0]), // Templated
.s_axi_rlast (elink0_m_axi_rlast), // Templated
.s_axi_rresp (elink0_m_axi_rresp[1:0]), // Templated
.s_axi_rvalid (elink0_m_axi_rvalid), // Templated
.s_axi_wready (elink0_m_axi_wready), // Templated
// Inputs
.s_axi_arid (elink0_m_axi_arid[S_IDW-1:0]), // Templated
.s_axi_araddr (elink0_m_axi_araddr[31:0]), // Templated
.s_axi_arburst (elink0_m_axi_arburst[1:0]), // Templated
.s_axi_arcache (elink0_m_axi_arcache[3:0]), // Templated
.s_axi_arlock (elink0_m_axi_arlock), // Templated
.s_axi_arlen (elink0_m_axi_arlen[7:0]), // Templated
.s_axi_arprot (elink0_m_axi_arprot[2:0]), // Templated
.s_axi_arqos (elink0_m_axi_arqos[3:0]), // Templated
.s_axi_arsize (elink0_m_axi_arsize[2:0]), // Templated
.s_axi_arvalid (elink0_m_axi_arvalid), // Templated
.s_axi_awid (elink0_m_axi_awid[S_IDW-1:0]), // Templated
.s_axi_awaddr (elink0_m_axi_awaddr[31:0]), // Templated
.s_axi_awburst (elink0_m_axi_awburst[1:0]), // Templated
.s_axi_awcache (elink0_m_axi_awcache[3:0]), // Templated
.s_axi_awlock (elink0_m_axi_awlock), // Templated
.s_axi_awlen (elink0_m_axi_awlen[7:0]), // Templated
.s_axi_awprot (elink0_m_axi_awprot[2:0]), // Templated
.s_axi_awqos (elink0_m_axi_awqos[3:0]), // Templated
.s_axi_awsize (elink0_m_axi_awsize[2:0]), // Templated
.s_axi_awvalid (elink0_m_axi_awvalid), // Templated
.s_axi_bready (elink0_m_axi_bready), // Templated
.s_axi_rready (elink0_m_axi_rready), // Templated
.s_axi_wid (elink0_m_axi_wid[S_IDW-1:0]), // Templated
.s_axi_wdata (elink0_m_axi_wdata[31:0]), // Templated
.s_axi_wlast (elink0_m_axi_wlast), // Templated
.s_axi_wstrb (elink0_m_axi_wstrb[3:0]), // Templated
.s_axi_wvalid (elink0_m_axi_wvalid)); // Templated
//######################################################################
//AXI MASTER (DRIVES STIMULUS) to configure elink1
//######################################################################
/*emaxi AUTO_TEMPLATE (//Stimulus
.m_axi_aresetn (nreset),
.m_axi_aclk (clk1),
.m_\(.*\) (ext1_m_\1[]),
.rr_wait (1'b0),
.wr_access (ext1_write_in),
.wr_packet (packet_in[PW-1:0]),
.rd_access (ext1_read_in),
.rd_packet (packet_in[PW-1:0]),
.wr_wait (wr_wait1),
.rd_wait (rd_wait1),
);
*/
emaxi #(.M_IDW(M_IDW))
emaxi1 (/*AUTOINST*/
// Outputs
.wr_wait (wr_wait1), // Templated
.rd_wait (rd_wait1), // Templated
.rr_access (rr_access),
.rr_packet (rr_packet[PW-1:0]),
.m_axi_awid (ext1_m_axi_awid[M_IDW-1:0]), // Templated
.m_axi_awaddr (ext1_m_axi_awaddr[31:0]), // Templated
.m_axi_awlen (ext1_m_axi_awlen[7:0]), // Templated
.m_axi_awsize (ext1_m_axi_awsize[2:0]), // Templated
.m_axi_awburst (ext1_m_axi_awburst[1:0]), // Templated
.m_axi_awlock (ext1_m_axi_awlock), // Templated
.m_axi_awcache (ext1_m_axi_awcache[3:0]), // Templated
.m_axi_awprot (ext1_m_axi_awprot[2:0]), // Templated
.m_axi_awqos (ext1_m_axi_awqos[3:0]), // Templated
.m_axi_awvalid (ext1_m_axi_awvalid), // Templated
.m_axi_wid (ext1_m_axi_wid[M_IDW-1:0]), // Templated
.m_axi_wdata (ext1_m_axi_wdata[63:0]), // Templated
.m_axi_wstrb (ext1_m_axi_wstrb[7:0]), // Templated
.m_axi_wlast (ext1_m_axi_wlast), // Templated
.m_axi_wvalid (ext1_m_axi_wvalid), // Templated
.m_axi_bready (ext1_m_axi_bready), // Templated
.m_axi_arid (ext1_m_axi_arid[M_IDW-1:0]), // Templated
.m_axi_araddr (ext1_m_axi_araddr[31:0]), // Templated
.m_axi_arlen (ext1_m_axi_arlen[7:0]), // Templated
.m_axi_arsize (ext1_m_axi_arsize[2:0]), // Templated
.m_axi_arburst (ext1_m_axi_arburst[1:0]), // Templated
.m_axi_arlock (ext1_m_axi_arlock), // Templated
.m_axi_arcache (ext1_m_axi_arcache[3:0]), // Templated
.m_axi_arprot (ext1_m_axi_arprot[2:0]), // Templated
.m_axi_arqos (ext1_m_axi_arqos[3:0]), // Templated
.m_axi_arvalid (ext1_m_axi_arvalid), // Templated
.m_axi_rready (ext1_m_axi_rready), // Templated
// Inputs
.wr_access (ext1_write_in), // Templated
.wr_packet (packet_in[PW-1:0]), // Templated
.rd_access (ext1_read_in), // Templated
.rd_packet (packet_in[PW-1:0]), // Templated
.rr_wait (1'b0), // Templated
.m_axi_aclk (clk1), // Templated
.m_axi_aresetn (nreset), // Templated
.m_axi_awready (ext1_m_axi_awready), // Templated
.m_axi_wready (ext1_m_axi_wready), // Templated
.m_axi_bid (ext1_m_axi_bid[M_IDW-1:0]), // Templated
.m_axi_bresp (ext1_m_axi_bresp[1:0]), // Templated
.m_axi_bvalid (ext1_m_axi_bvalid), // Templated
.m_axi_arready (ext1_m_axi_arready), // Templated
.m_axi_rid (ext1_m_axi_rid[M_IDW-1:0]), // Templated
.m_axi_rdata (ext1_m_axi_rdata[63:0]), // Templated
.m_axi_rresp (ext1_m_axi_rresp[1:0]), // Templated
.m_axi_rlast (ext1_m_axi_rlast), // Templated
.m_axi_rvalid (ext1_m_axi_rvalid)); // Templated
//######################################################################
//2ND ELINK
//######################################################################
/*axi_elink AUTO_TEMPLATE (.m_axi_aresetn (nreset),
.s_axi_aresetn (nreset),
.sys_nreset (nreset),
.sys_clk (clk1),
.rxi_\(.*\) (elink0_txo_\1[]),
.txi_\(.*\) (elink0_rxo_\1[]),
.s_\(.*\) (ext1_m_\1[]),
.m_\(.*\) (mem_m_\1[]),
.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
);
*/
defparam elink1.ID = 12'h820;
defparam elink1.ETYPE = 0;
defparam elink1.S_IDW = S2_IDW;
defparam elink1.M_IDW = M2_IDW;
//defparam elink1.WAIT_WRRD = 0;
axi_elink elink1 ( .s_axi_wstrb ((ext1_m_axi_wstrb[3:0] | ext1_m_axi_wstrb[7:4])),//NOTE:HACK!!
/*AUTOINST*/
// Outputs
.elink_active (elink1_elink_active), // Templated
.rxo_wr_wait_p (elink1_rxo_wr_wait_p), // Templated
.rxo_wr_wait_n (elink1_rxo_wr_wait_n), // Templated
.rxo_rd_wait_p (elink1_rxo_rd_wait_p), // Templated
.rxo_rd_wait_n (elink1_rxo_rd_wait_n), // Templated
.txo_lclk_p (elink1_txo_lclk_p), // Templated
.txo_lclk_n (elink1_txo_lclk_n), // Templated
.txo_frame_p (elink1_txo_frame_p), // Templated
.txo_frame_n (elink1_txo_frame_n), // Templated
.txo_data_p (elink1_txo_data_p[7:0]), // Templated
.txo_data_n (elink1_txo_data_n[7:0]), // Templated
.chipid (elink1_chipid[11:0]), // Templated
.chip_nreset (elink1_chip_nreset), // Templated
.cclk_p (elink1_cclk_p), // Templated
.cclk_n (elink1_cclk_n), // Templated
.mailbox_irq (elink1_mailbox_irq), // Templated
.m_axi_awid (mem_m_axi_awid[M_IDW-1:0]), // Templated
.m_axi_awaddr (mem_m_axi_awaddr[31:0]), // Templated
.m_axi_awlen (mem_m_axi_awlen[7:0]), // Templated
.m_axi_awsize (mem_m_axi_awsize[2:0]), // Templated
.m_axi_awburst (mem_m_axi_awburst[1:0]), // Templated
.m_axi_awlock (mem_m_axi_awlock), // Templated
.m_axi_awcache (mem_m_axi_awcache[3:0]), // Templated
.m_axi_awprot (mem_m_axi_awprot[2:0]), // Templated
.m_axi_awqos (mem_m_axi_awqos[3:0]), // Templated
.m_axi_awvalid (mem_m_axi_awvalid), // Templated
.m_axi_wid (mem_m_axi_wid[M_IDW-1:0]), // Templated
.m_axi_wdata (mem_m_axi_wdata[63:0]), // Templated
.m_axi_wstrb (mem_m_axi_wstrb[7:0]), // Templated
.m_axi_wlast (mem_m_axi_wlast), // Templated
.m_axi_wvalid (mem_m_axi_wvalid), // Templated
.m_axi_bready (mem_m_axi_bready), // Templated
.m_axi_arid (mem_m_axi_arid[M_IDW-1:0]), // Templated
.m_axi_araddr (mem_m_axi_araddr[31:0]), // Templated
.m_axi_arlen (mem_m_axi_arlen[7:0]), // Templated
.m_axi_arsize (mem_m_axi_arsize[2:0]), // Templated
.m_axi_arburst (mem_m_axi_arburst[1:0]), // Templated
.m_axi_arlock (mem_m_axi_arlock), // Templated
.m_axi_arcache (mem_m_axi_arcache[3:0]), // Templated
.m_axi_arprot (mem_m_axi_arprot[2:0]), // Templated
.m_axi_arqos (mem_m_axi_arqos[3:0]), // Templated
.m_axi_arvalid (mem_m_axi_arvalid), // Templated
.m_axi_rready (mem_m_axi_rready), // Templated
.s_axi_arready (ext1_m_axi_arready), // Templated
.s_axi_awready (ext1_m_axi_awready), // Templated
.s_axi_bid (ext1_m_axi_bid[S_IDW-1:0]), // Templated
.s_axi_bresp (ext1_m_axi_bresp[1:0]), // Templated
.s_axi_bvalid (ext1_m_axi_bvalid), // Templated
.s_axi_rid (ext1_m_axi_rid[S_IDW-1:0]), // Templated
.s_axi_rdata (ext1_m_axi_rdata[31:0]), // Templated
.s_axi_rlast (ext1_m_axi_rlast), // Templated
.s_axi_rresp (ext1_m_axi_rresp[1:0]), // Templated
.s_axi_rvalid (ext1_m_axi_rvalid), // Templated
.s_axi_wready (ext1_m_axi_wready), // Templated
// Inputs
.sys_nreset (nreset), // Templated
.sys_clk (clk1), // Templated
.rxi_lclk_p (elink0_txo_lclk_p), // Templated
.rxi_lclk_n (elink0_txo_lclk_n), // Templated
.rxi_frame_p (elink0_txo_frame_p), // Templated
.rxi_frame_n (elink0_txo_frame_n), // Templated
.rxi_data_p (elink0_txo_data_p[7:0]), // Templated
.rxi_data_n (elink0_txo_data_n[7:0]), // Templated
.txi_wr_wait_p (elink0_rxo_wr_wait_p), // Templated
.txi_wr_wait_n (elink0_rxo_wr_wait_n), // Templated
.txi_rd_wait_p (elink0_rxo_rd_wait_p), // Templated
.txi_rd_wait_n (elink0_rxo_rd_wait_n), // Templated
.m_axi_aresetn (nreset), // Templated
.m_axi_awready (mem_m_axi_awready), // Templated
.m_axi_wready (mem_m_axi_wready), // Templated
.m_axi_bid (mem_m_axi_bid[M_IDW-1:0]), // Templated
.m_axi_bresp (mem_m_axi_bresp[1:0]), // Templated
.m_axi_bvalid (mem_m_axi_bvalid), // Templated
.m_axi_arready (mem_m_axi_arready), // Templated
.m_axi_rid (mem_m_axi_rid[M_IDW-1:0]), // Templated
.m_axi_rdata (mem_m_axi_rdata[63:0]), // Templated
.m_axi_rresp (mem_m_axi_rresp[1:0]), // Templated
.m_axi_rlast (mem_m_axi_rlast), // Templated
.m_axi_rvalid (mem_m_axi_rvalid), // Templated
.s_axi_aresetn (nreset), // Templated
.s_axi_arid (ext1_m_axi_arid[S_IDW-1:0]), // Templated
.s_axi_araddr (ext1_m_axi_araddr[31:0]), // Templated
.s_axi_arburst (ext1_m_axi_arburst[1:0]), // Templated
.s_axi_arcache (ext1_m_axi_arcache[3:0]), // Templated
.s_axi_arlock (ext1_m_axi_arlock), // Templated
.s_axi_arlen (ext1_m_axi_arlen[7:0]), // Templated
.s_axi_arprot (ext1_m_axi_arprot[2:0]), // Templated
.s_axi_arqos (ext1_m_axi_arqos[3:0]), // Templated
.s_axi_arsize (ext1_m_axi_arsize[2:0]), // Templated
.s_axi_arvalid (ext1_m_axi_arvalid), // Templated
.s_axi_awid (ext1_m_axi_awid[S_IDW-1:0]), // Templated
.s_axi_awaddr (ext1_m_axi_awaddr[31:0]), // Templated
.s_axi_awburst (ext1_m_axi_awburst[1:0]), // Templated
.s_axi_awcache (ext1_m_axi_awcache[3:0]), // Templated
.s_axi_awlock (ext1_m_axi_awlock), // Templated
.s_axi_awlen (ext1_m_axi_awlen[7:0]), // Templated
.s_axi_awprot (ext1_m_axi_awprot[2:0]), // Templated
.s_axi_awqos (ext1_m_axi_awqos[3:0]), // Templated
.s_axi_awsize (ext1_m_axi_awsize[2:0]), // Templated
.s_axi_awvalid (ext1_m_axi_awvalid), // Templated
.s_axi_bready (ext1_m_axi_bready), // Templated
.s_axi_rready (ext1_m_axi_rready), // Templated
.s_axi_wid (ext1_m_axi_wid[S_IDW-1:0]), // Templated
.s_axi_wdata (ext1_m_axi_wdata[31:0]), // Templated
.s_axi_wlast (ext1_m_axi_wlast), // Templated
.s_axi_wvalid (ext1_m_axi_wvalid)); // Templated
//######################################################################
//AXI SLAVE
//######################################################################
/*esaxi AUTO_TEMPLATE (//Stimulus
.s_\(.*\) (mem_m_\1[]),
.\(.*\) (mem_\1[]),
);
*/
esaxi #(.S_IDW(S_IDW), .RETURN_ADDR(RETURN_ADDR))
esaxi (.s_axi_aclk (clk1),
.s_axi_aresetn (nreset),
.s_axi_wstrb (mem_m_axi_wstrb[7:4] | mem_m_axi_wstrb[3:0]),
/*AUTOINST*/
// Outputs
.wr_access (mem_wr_access), // Templated
.wr_packet (mem_wr_packet[PW-1:0]), // Templated
.rd_access (mem_rd_access), // Templated
.rd_packet (mem_rd_packet[PW-1:0]), // Templated
.rr_wait (mem_rr_wait), // Templated
.s_axi_arready (mem_m_axi_arready), // Templated
.s_axi_awready (mem_m_axi_awready), // Templated
.s_axi_bid (mem_m_axi_bid[S_IDW-1:0]), // Templated
.s_axi_bresp (mem_m_axi_bresp[1:0]), // Templated
.s_axi_bvalid (mem_m_axi_bvalid), // Templated
.s_axi_rid (mem_m_axi_rid[S_IDW-1:0]), // Templated
.s_axi_rdata (mem_m_axi_rdata[31:0]), // Templated
.s_axi_rlast (mem_m_axi_rlast), // Templated
.s_axi_rresp (mem_m_axi_rresp[1:0]), // Templated
.s_axi_rvalid (mem_m_axi_rvalid), // Templated
.s_axi_wready (mem_m_axi_wready), // Templated
// Inputs
.wr_wait (mem_wr_wait), // Templated
.rd_wait (mem_rd_wait), // Templated
.rr_access (mem_rr_access), // Templated
.rr_packet (mem_rr_packet[PW-1:0]), // Templated
.s_axi_arid (mem_m_axi_arid[S_IDW-1:0]), // Templated
.s_axi_araddr (mem_m_axi_araddr[31:0]), // Templated
.s_axi_arburst (mem_m_axi_arburst[1:0]), // Templated
.s_axi_arcache (mem_m_axi_arcache[3:0]), // Templated
.s_axi_arlock (mem_m_axi_arlock), // Templated
.s_axi_arlen (mem_m_axi_arlen[7:0]), // Templated
.s_axi_arprot (mem_m_axi_arprot[2:0]), // Templated
.s_axi_arqos (mem_m_axi_arqos[3:0]), // Templated
.s_axi_arsize (mem_m_axi_arsize[2:0]), // Templated
.s_axi_arvalid (mem_m_axi_arvalid), // Templated
.s_axi_awid (mem_m_axi_awid[S_IDW-1:0]), // Templated
.s_axi_awaddr (mem_m_axi_awaddr[31:0]), // Templated
.s_axi_awburst (mem_m_axi_awburst[1:0]), // Templated
.s_axi_awcache (mem_m_axi_awcache[3:0]), // Templated
.s_axi_awlock (mem_m_axi_awlock), // Templated
.s_axi_awlen (mem_m_axi_awlen[7:0]), // Templated
.s_axi_awprot (mem_m_axi_awprot[2:0]), // Templated
.s_axi_awqos (mem_m_axi_awqos[3:0]), // Templated
.s_axi_awsize (mem_m_axi_awsize[2:0]), // Templated
.s_axi_awvalid (mem_m_axi_awvalid), // Templated
.s_axi_bready (mem_m_axi_bready), // Templated
.s_axi_rready (mem_m_axi_rready), // Templated
.s_axi_wid (mem_m_axi_wid[S_IDW-1:0]), // Templated
.s_axi_wdata (mem_m_axi_wdata[31:0]), // Templated
.s_axi_wlast (mem_m_axi_wlast), // Templated
.s_axi_wvalid (mem_m_axi_wvalid)); // Templated
//######################################################################
// MEMORY PORT
//######################################################################
//"Arbitration" between read/write transaction
assign mem_access = mem_wr_access | mem_rd_access;
assign mem_packet[PW-1:0] = mem_wr_access ? mem_wr_packet[PW-1:0]:
mem_rd_packet[PW-1:0];
assign mem_rd_wait = (mem_wait & mem_rd_access) |
mem_wr_access;
assign mem_wr_wait = (mem_wait & mem_wr_access);
/*ememory AUTO_TEMPLATE (
// Outputsd
.\(.*\)_out (mem_rr_\1[]),
.\(.*\)_in (mem_\1[]),
.wait_out (mem_wait),
.wait_in (mem_rr_wait), //pushback on reads
);
*/
ememory #(.WAIT(0),
.MON(1))
ememory (.clk (clk1),
.coreid (12'h0),
/*AUTOINST*/
// Outputs
.wait_out (mem_wait), // Templated
.access_out (mem_rr_access), // Templated
.packet_out (mem_rr_packet[PW-1:0]), // Templated
// Inputs
.nreset (nreset),
.access_in (mem_access), // Templated
.packet_in (mem_packet[PW-1:0]), // Templated
.wait_in (mem_rr_wait)); // Templated
endmodule // dv_elink
// Local Variables:
// verilog-library-directories:("." "../oh/elink/hdl" "../oh/emesh/dv" "../oh/axi/dv" "../oh/emesh/hdl" "../oh/memory/hdl" "../oh/axi/hdl")
// End:
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: tso_mon.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////;
// tso_mon.v
//
// Description: This is a rather eclectic monitor
// to do tso coverage gathering. It also has some checkers
// and other useful stuff. It pokes into L2 the sparc core pipeline
// as well as the LSU.
//
////////////////////////////////////////////////////////
`define FPOP1_RQ 5'b01010
`define FPOP2_RQ 5'b01011
`define STB_DRAIN_TO 8000
`ifdef GATE_SIM
`else
`include "cross_module.h"
`include "sys.h"
`include "iop.h"
`include "sctag.h"
`endif
//--------------------------------------------------------------------------------------
// module definition:
// Note that most of the stuff is cross-module referencing,
// so the interface is minimal
//--------------------------------------------------------------------------------------
module tso_mon ( clk, rst_l);
input clk; // the cpu clock
input rst_l; // reset (active low).
`ifdef GATE_SIM
`else
reg tso_mon_msg; // decides should we print all tso_mon messages
reg disable_lock_check; // disable one of my checkes
reg kill_on_cross_mod_code;
reg force_dfq;
integer stb_drain_to_max; // what the Store buffer timeout will be.
reg enable_ifu_lsu_inv_clear;
initial
begin
if( $test$plusargs("force_dfq") )
force_dfq = 1'b1;
else
force_dfq= 1'b0;
if( $test$plusargs("enable_ifu_lsu_inv_clear") )
enable_ifu_lsu_inv_clear = 1;
else
enable_ifu_lsu_inv_clear = 0;
if( $test$plusargs("tso_mon_msg") )
tso_mon_msg = 1'b1;
else
tso_mon_msg= 1'b0;
if( $test$plusargs("disable_lock_check") )
disable_lock_check = 1'b1;
else
disable_lock_check = 1'b0;
if (! $value$plusargs("stb_drain_to_max=%d", stb_drain_to_max)) begin
stb_drain_to_max = `STB_DRAIN_TO ;
end
$display("%0d tso_mon: stb_drain_to_max = %d", $time, stb_drain_to_max);
if( $test$plusargs("kill_on_cross_mod_code") )
kill_on_cross_mod_code = 1'b1;
else
kill_on_cross_mod_code = 1'b0;
end
wire tso_mon_vcc = 1'b1;
wire pll_lock = `TOP_MEMORY.ctu.u_pll.pll_lock;
//--------------------------------------------------------------------------------------
// related to bug 6372 - need to monitor some DFQ signals
//--------------------------------------------------------------------------------------
`ifdef RTL_SPARC0
wire spc0_dfq_byp_ff_en = `TOP_DESIGN.sparc0.lsu.qctl2.dfq_byp_ff_en;
wire spc0_dfq_wr_en = `TOP_DESIGN.sparc0.lsu.qctl2.dfq_wr_en;
reg spc0_dfq_byp_ff_en_d1;
reg spc0_dfq_wr_en_d1;
`endif
`ifdef RTL_SPARC1
wire spc1_dfq_byp_ff_en = `TOP_DESIGN.sparc1.lsu.qctl2.dfq_byp_ff_en;
wire spc1_dfq_wr_en = `TOP_DESIGN.sparc1.lsu.qctl2.dfq_wr_en;
reg spc1_dfq_byp_ff_en_d1;
reg spc1_dfq_wr_en_d1;
`endif
`ifdef RTL_SPARC2
wire spc2_dfq_byp_ff_en = `TOP_DESIGN.sparc2.lsu.qctl2.dfq_byp_ff_en;
wire spc2_dfq_wr_en = `TOP_DESIGN.sparc2.lsu.qctl2.dfq_wr_en;
reg spc2_dfq_byp_ff_en_d1;
reg spc2_dfq_wr_en_d1;
`endif
`ifdef RTL_SPARC3
wire spc3_dfq_byp_ff_en = `TOP_DESIGN.sparc3.lsu.qctl2.dfq_byp_ff_en;
wire spc3_dfq_wr_en = `TOP_DESIGN.sparc3.lsu.qctl2.dfq_wr_en;
reg spc3_dfq_byp_ff_en_d1;
reg spc3_dfq_wr_en_d1;
`endif
`ifdef RTL_SPARC4
wire spc4_dfq_byp_ff_en = `TOP_DESIGN.sparc4.lsu.qctl2.dfq_byp_ff_en;
wire spc4_dfq_wr_en = `TOP_DESIGN.sparc4.lsu.qctl2.dfq_wr_en;
reg spc4_dfq_byp_ff_en_d1;
reg spc4_dfq_wr_en_d1;
`endif
`ifdef RTL_SPARC5
wire spc5_dfq_byp_ff_en = `TOP_DESIGN.sparc5.lsu.qctl2.dfq_byp_ff_en;
wire spc5_dfq_wr_en = `TOP_DESIGN.sparc5.lsu.qctl2.dfq_wr_en;
reg spc5_dfq_byp_ff_en_d1;
reg spc5_dfq_wr_en_d1;
`endif
`ifdef RTL_SPARC6
wire spc6_dfq_byp_ff_en = `TOP_DESIGN.sparc6.lsu.qctl2.dfq_byp_ff_en;
wire spc6_dfq_wr_en = `TOP_DESIGN.sparc6.lsu.qctl2.dfq_wr_en;
reg spc6_dfq_byp_ff_en_d1;
reg spc6_dfq_wr_en_d1;
`endif
`ifdef RTL_SPARC7
wire spc7_dfq_byp_ff_en = `TOP_DESIGN.sparc7.lsu.qctl2.dfq_byp_ff_en;
wire spc7_dfq_wr_en = `TOP_DESIGN.sparc7.lsu.qctl2.dfq_wr_en;
reg spc7_dfq_byp_ff_en_d1;
reg spc7_dfq_wr_en_d1;
`endif
//--------------------------------------------------------------------------------------
// spc to pcx packets
//--------------------------------------------------------------------------------------
wire [4:0] spc0_pcx_req_pq = `TOP_MEMORY.spc0_pcx_req_pq[4:0];
wire spc0_pcx_atom_pq = `TOP_MEMORY.spc0_pcx_atom_pq;
wire [`PCX_WIDTH-1:0] spc0_pcx_data_pa = `TOP_MEMORY.spc0_pcx_data_pa[`PCX_WIDTH-1:0];
reg pcx0_vld_d1; // valid pcx packet
reg pcx0_atom_pq_d1; // atomic bit delayed by 1
reg pcx0_atom_pq_d2; // delayed by 2
reg pcx0_req_pq_d1; // OR of request bits delayed by 1
reg [5:0] pcx0_type_d1; // packet type delayed by 1
wire [4:0] spc1_pcx_req_pq = `TOP_MEMORY.spc1_pcx_req_pq[4:0];
wire spc1_pcx_atom_pq = `TOP_MEMORY.spc1_pcx_atom_pq;
wire [`PCX_WIDTH-1:0] spc1_pcx_data_pa = `TOP_MEMORY.spc1_pcx_data_pa[`PCX_WIDTH-1:0];
reg pcx1_vld_d1; // valid pcx packet
reg pcx1_atom_pq_d1; // atomic bit delayed by 1
reg pcx1_atom_pq_d2; // delayed by 2
reg pcx1_req_pq_d1; // OR of request bits delayed by 1
reg [5:0] pcx1_type_d1; // packet type delayed by 1
wire [4:0] spc2_pcx_req_pq = `TOP_MEMORY.spc2_pcx_req_pq[4:0];
wire spc2_pcx_atom_pq = `TOP_MEMORY.spc2_pcx_atom_pq;
wire [`PCX_WIDTH-1:0] spc2_pcx_data_pa = `TOP_MEMORY.spc2_pcx_data_pa[`PCX_WIDTH-1:0];
reg pcx2_vld_d1; // valid pcx packet
reg pcx2_atom_pq_d1; // atomic bit delayed by 1
reg pcx2_atom_pq_d2; // delayed by 2
reg pcx2_req_pq_d1; // OR of request bits delayed by 1
reg [5:0] pcx2_type_d1; // packet type delayed by 1
wire [4:0] spc3_pcx_req_pq = `TOP_MEMORY.spc3_pcx_req_pq[4:0];
wire spc3_pcx_atom_pq = `TOP_MEMORY.spc3_pcx_atom_pq;
wire [`PCX_WIDTH-1:0] spc3_pcx_data_pa = `TOP_MEMORY.spc3_pcx_data_pa[`PCX_WIDTH-1:0];
reg pcx3_vld_d1; // valid pcx packet
reg pcx3_atom_pq_d1; // atomic bit delayed by 1
reg pcx3_atom_pq_d2; // delayed by 2
reg pcx3_req_pq_d1; // OR of request bits delayed by 1
reg [5:0] pcx3_type_d1; // packet type delayed by 1
wire [4:0] spc4_pcx_req_pq = `TOP_MEMORY.spc4_pcx_req_pq[4:0];
wire spc4_pcx_atom_pq = `TOP_MEMORY.spc4_pcx_atom_pq;
wire [`PCX_WIDTH-1:0] spc4_pcx_data_pa = `TOP_MEMORY.spc4_pcx_data_pa[`PCX_WIDTH-1:0];
reg pcx4_vld_d1; // valid pcx packet
reg pcx4_atom_pq_d1; // atomic bit delayed by 1
reg pcx4_atom_pq_d2; // delayed by 2
reg pcx4_req_pq_d1; // OR of request bits delayed by 1
reg [5:0] pcx4_type_d1; // packet type delayed by 1
wire [4:0] spc5_pcx_req_pq = `TOP_MEMORY.spc5_pcx_req_pq[4:0];
wire spc5_pcx_atom_pq = `TOP_MEMORY.spc5_pcx_atom_pq;
wire [`PCX_WIDTH-1:0] spc5_pcx_data_pa = `TOP_MEMORY.spc5_pcx_data_pa[`PCX_WIDTH-1:0];
reg pcx5_vld_d1; // valid pcx packet
reg pcx5_atom_pq_d1; // atomic bit delayed by 1
reg pcx5_atom_pq_d2; // delayed by 2
reg pcx5_req_pq_d1; // OR of request bits delayed by 1
reg [5:0] pcx5_type_d1; // packet type delayed by 1
wire [4:0] spc6_pcx_req_pq = `TOP_MEMORY.spc6_pcx_req_pq[4:0];
wire spc6_pcx_atom_pq = `TOP_MEMORY.spc6_pcx_atom_pq;
wire [`PCX_WIDTH-1:0] spc6_pcx_data_pa = `TOP_MEMORY.spc6_pcx_data_pa[`PCX_WIDTH-1:0];
reg pcx6_vld_d1; // valid pcx packet
reg pcx6_atom_pq_d1; // atomic bit delayed by 1
reg pcx6_atom_pq_d2; // delayed by 2
reg pcx6_req_pq_d1; // OR of request bits delayed by 1
reg [5:0] pcx6_type_d1; // packet type delayed by 1
wire [4:0] spc7_pcx_req_pq = `TOP_MEMORY.spc7_pcx_req_pq[4:0];
wire spc7_pcx_atom_pq = `TOP_MEMORY.spc7_pcx_atom_pq;
wire [`PCX_WIDTH-1:0] spc7_pcx_data_pa = `TOP_MEMORY.spc7_pcx_data_pa[`PCX_WIDTH-1:0];
reg pcx7_vld_d1; // valid pcx packet
reg pcx7_atom_pq_d1; // atomic bit delayed by 1
reg pcx7_atom_pq_d2; // delayed by 2
reg pcx7_req_pq_d1; // OR of request bits delayed by 1
reg [5:0] pcx7_type_d1; // packet type delayed by 1
//--------------------------------------------------------------------------------------
// L2 tags tp cpx packets
//--------------------------------------------------------------------------------------
wire [7:0] sctag0_cpx_req_cq = `TOP_MEMORY.sctag0_cpx_req_cq[7:0];
wire [7:0] sctag0_cpx_atom_cq = `TOP_MEMORY.sctag0_cpx_atom_cq;
wire [`CPX_WIDTH-1:0] sctag0_cpx_data_ca = `TOP_MEMORY.sctag0_cpx_data_ca[`CPX_WIDTH-1:0];
wire sctag0_pcx_stall_pq = `TOP_MEMORY.sctag0_pcx_stall_pq;
reg [7:0] sctag0_cpx_req_cq_d1; // delayed by 1
reg [7:0] sctag0_cpx_req_cq_d2; // delayed by 2
reg [7:0] sctag0_cpx_atom_cq_d1; // delayed by 1
reg [7:0] sctag0_cpx_atom_cq_d2; // delayed by 2
reg [127:0] sctag0_cpx_type_str; // in string format
reg [3:0] sctag0_cpx_type; // packet type
reg sctag0_dc_lkup_c5;
reg sctag0_ic_lkup_c5;
reg sctag0_dc_lkup_c6;
reg sctag0_ic_lkup_c6;
wire [3:0] sctag0_dc_lkup_panel_dec_c4 = `TOP_MEMORY.sctag0.dirrep.dc_lkup_panel_dec_c4[3:0];
wire [3:0] sctag0_dc_lkup_row_dec_c4 = `TOP_MEMORY.sctag0.dirrep.dc_lkup_row_dec_c4[3:0];
wire [3:0] sctag0_ic_lkup_panel_dec_c4 = `TOP_MEMORY.sctag0.dirrep.ic_lkup_panel_dec_c4[3:0];
wire [3:0] sctag0_ic_lkup_row_dec_c4 = `TOP_MEMORY.sctag0.dirrep.ic_lkup_row_dec_c4[3:0];
wire [127:0] sctag0_dc_cam_hit_c6 = `TOP_MEMORY.sctag0.dirvec_dp.dc_cam_hit_c6[127:0];
wire [127:0] sctag0_ic_cam_hit_c6 = `TOP_MEMORY.sctag0.dirvec_dp.ic_cam_hit_c6[127:0];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble0_sum = sctag0_dc_cam_hit_c6[0] + sctag0_dc_cam_hit_c6[1] +
sctag0_dc_cam_hit_c6[2] + sctag0_dc_cam_hit_c6[3];
wire [2:0] sctag0_ic_cam_hit_c6_nibble0_sum = sctag0_ic_cam_hit_c6[0] + sctag0_ic_cam_hit_c6[1] +
sctag0_ic_cam_hit_c6[2] + sctag0_ic_cam_hit_c6[3];
wire [3:0] sctag0_both_cam_hit_c6_nibble0_sum= sctag0_dc_cam_hit_c6[0] + sctag0_dc_cam_hit_c6[1] +
sctag0_dc_cam_hit_c6[2] + sctag0_dc_cam_hit_c6[3] +
sctag0_ic_cam_hit_c6[0] + sctag0_ic_cam_hit_c6[1] +
sctag0_ic_cam_hit_c6[2] + sctag0_ic_cam_hit_c6[3];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble1_sum = sctag0_dc_cam_hit_c6[4] + sctag0_dc_cam_hit_c6[5] +
sctag0_dc_cam_hit_c6[6] + sctag0_dc_cam_hit_c6[7];
wire [2:0] sctag0_ic_cam_hit_c6_nibble1_sum = sctag0_ic_cam_hit_c6[4] + sctag0_ic_cam_hit_c6[5] +
sctag0_ic_cam_hit_c6[6] + sctag0_ic_cam_hit_c6[7];
wire [3:0] sctag0_both_cam_hit_c6_nibble1_sum= sctag0_dc_cam_hit_c6[4] + sctag0_dc_cam_hit_c6[5] +
sctag0_dc_cam_hit_c6[6] + sctag0_dc_cam_hit_c6[7] +
sctag0_ic_cam_hit_c6[4] + sctag0_ic_cam_hit_c6[5] +
sctag0_ic_cam_hit_c6[6] + sctag0_ic_cam_hit_c6[7];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble2_sum = sctag0_dc_cam_hit_c6[8] + sctag0_dc_cam_hit_c6[9] +
sctag0_dc_cam_hit_c6[10] + sctag0_dc_cam_hit_c6[11];
wire [2:0] sctag0_ic_cam_hit_c6_nibble2_sum = sctag0_ic_cam_hit_c6[8] + sctag0_ic_cam_hit_c6[9] +
sctag0_ic_cam_hit_c6[10] + sctag0_ic_cam_hit_c6[11];
wire [3:0] sctag0_both_cam_hit_c6_nibble2_sum= sctag0_dc_cam_hit_c6[8] + sctag0_dc_cam_hit_c6[9] +
sctag0_dc_cam_hit_c6[10] + sctag0_dc_cam_hit_c6[11] +
sctag0_ic_cam_hit_c6[8] + sctag0_ic_cam_hit_c6[9] +
sctag0_ic_cam_hit_c6[10] + sctag0_ic_cam_hit_c6[11];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble3_sum = sctag0_dc_cam_hit_c6[12] + sctag0_dc_cam_hit_c6[13] +
sctag0_dc_cam_hit_c6[14] + sctag0_dc_cam_hit_c6[15];
wire [2:0] sctag0_ic_cam_hit_c6_nibble3_sum = sctag0_ic_cam_hit_c6[12] + sctag0_ic_cam_hit_c6[13] +
sctag0_ic_cam_hit_c6[14] + sctag0_ic_cam_hit_c6[15];
wire [3:0] sctag0_both_cam_hit_c6_nibble3_sum= sctag0_dc_cam_hit_c6[12] + sctag0_dc_cam_hit_c6[13] +
sctag0_dc_cam_hit_c6[14] + sctag0_dc_cam_hit_c6[15] +
sctag0_ic_cam_hit_c6[12] + sctag0_ic_cam_hit_c6[13] +
sctag0_ic_cam_hit_c6[14] + sctag0_ic_cam_hit_c6[15];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble4_sum = sctag0_dc_cam_hit_c6[16] + sctag0_dc_cam_hit_c6[17] +
sctag0_dc_cam_hit_c6[18] + sctag0_dc_cam_hit_c6[19];
wire [2:0] sctag0_ic_cam_hit_c6_nibble4_sum = sctag0_ic_cam_hit_c6[16] + sctag0_ic_cam_hit_c6[17] +
sctag0_ic_cam_hit_c6[18] + sctag0_ic_cam_hit_c6[19];
wire [3:0] sctag0_both_cam_hit_c6_nibble4_sum= sctag0_dc_cam_hit_c6[16] + sctag0_dc_cam_hit_c6[17] +
sctag0_dc_cam_hit_c6[18] + sctag0_dc_cam_hit_c6[19] +
sctag0_ic_cam_hit_c6[16] + sctag0_ic_cam_hit_c6[17] +
sctag0_ic_cam_hit_c6[18] + sctag0_ic_cam_hit_c6[19];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble5_sum = sctag0_dc_cam_hit_c6[20] + sctag0_dc_cam_hit_c6[21] +
sctag0_dc_cam_hit_c6[22] + sctag0_dc_cam_hit_c6[23];
wire [2:0] sctag0_ic_cam_hit_c6_nibble5_sum = sctag0_ic_cam_hit_c6[20] + sctag0_ic_cam_hit_c6[21] +
sctag0_ic_cam_hit_c6[22] + sctag0_ic_cam_hit_c6[23];
wire [3:0] sctag0_both_cam_hit_c6_nibble5_sum= sctag0_dc_cam_hit_c6[20] + sctag0_dc_cam_hit_c6[21] +
sctag0_dc_cam_hit_c6[22] + sctag0_dc_cam_hit_c6[23] +
sctag0_ic_cam_hit_c6[20] + sctag0_ic_cam_hit_c6[21] +
sctag0_ic_cam_hit_c6[22] + sctag0_ic_cam_hit_c6[23];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble6_sum = sctag0_dc_cam_hit_c6[24] + sctag0_dc_cam_hit_c6[25] +
sctag0_dc_cam_hit_c6[26] + sctag0_dc_cam_hit_c6[27];
wire [2:0] sctag0_ic_cam_hit_c6_nibble6_sum = sctag0_ic_cam_hit_c6[24] + sctag0_ic_cam_hit_c6[25] +
sctag0_ic_cam_hit_c6[26] + sctag0_ic_cam_hit_c6[27];
wire [3:0] sctag0_both_cam_hit_c6_nibble6_sum= sctag0_dc_cam_hit_c6[24] + sctag0_dc_cam_hit_c6[25] +
sctag0_dc_cam_hit_c6[26] + sctag0_dc_cam_hit_c6[27] +
sctag0_ic_cam_hit_c6[24] + sctag0_ic_cam_hit_c6[25] +
sctag0_ic_cam_hit_c6[26] + sctag0_ic_cam_hit_c6[27];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble7_sum = sctag0_dc_cam_hit_c6[28] + sctag0_dc_cam_hit_c6[29] +
sctag0_dc_cam_hit_c6[30] + sctag0_dc_cam_hit_c6[31];
wire [2:0] sctag0_ic_cam_hit_c6_nibble7_sum = sctag0_ic_cam_hit_c6[28] + sctag0_ic_cam_hit_c6[29] +
sctag0_ic_cam_hit_c6[30] + sctag0_ic_cam_hit_c6[31];
wire [3:0] sctag0_both_cam_hit_c6_nibble7_sum= sctag0_dc_cam_hit_c6[28] + sctag0_dc_cam_hit_c6[29] +
sctag0_dc_cam_hit_c6[30] + sctag0_dc_cam_hit_c6[31] +
sctag0_ic_cam_hit_c6[28] + sctag0_ic_cam_hit_c6[29] +
sctag0_ic_cam_hit_c6[30] + sctag0_ic_cam_hit_c6[31];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble8_sum = sctag0_dc_cam_hit_c6[32] + sctag0_dc_cam_hit_c6[33] +
sctag0_dc_cam_hit_c6[34] + sctag0_dc_cam_hit_c6[35];
wire [2:0] sctag0_ic_cam_hit_c6_nibble8_sum = sctag0_ic_cam_hit_c6[32] + sctag0_ic_cam_hit_c6[33] +
sctag0_ic_cam_hit_c6[34] + sctag0_ic_cam_hit_c6[35];
wire [3:0] sctag0_both_cam_hit_c6_nibble8_sum= sctag0_dc_cam_hit_c6[32] + sctag0_dc_cam_hit_c6[33] +
sctag0_dc_cam_hit_c6[34] + sctag0_dc_cam_hit_c6[35] +
sctag0_ic_cam_hit_c6[32] + sctag0_ic_cam_hit_c6[33] +
sctag0_ic_cam_hit_c6[34] + sctag0_ic_cam_hit_c6[35];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble9_sum = sctag0_dc_cam_hit_c6[36] + sctag0_dc_cam_hit_c6[37] +
sctag0_dc_cam_hit_c6[38] + sctag0_dc_cam_hit_c6[39];
wire [2:0] sctag0_ic_cam_hit_c6_nibble9_sum = sctag0_ic_cam_hit_c6[36] + sctag0_ic_cam_hit_c6[37] +
sctag0_ic_cam_hit_c6[38] + sctag0_ic_cam_hit_c6[39];
wire [3:0] sctag0_both_cam_hit_c6_nibble9_sum= sctag0_dc_cam_hit_c6[36] + sctag0_dc_cam_hit_c6[37] +
sctag0_dc_cam_hit_c6[38] + sctag0_dc_cam_hit_c6[39] +
sctag0_ic_cam_hit_c6[36] + sctag0_ic_cam_hit_c6[37] +
sctag0_ic_cam_hit_c6[38] + sctag0_ic_cam_hit_c6[39];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble10_sum = sctag0_dc_cam_hit_c6[40] + sctag0_dc_cam_hit_c6[41] +
sctag0_dc_cam_hit_c6[42] + sctag0_dc_cam_hit_c6[43];
wire [2:0] sctag0_ic_cam_hit_c6_nibble10_sum = sctag0_ic_cam_hit_c6[40] + sctag0_ic_cam_hit_c6[41] +
sctag0_ic_cam_hit_c6[42] + sctag0_ic_cam_hit_c6[43];
wire [3:0] sctag0_both_cam_hit_c6_nibble10_sum= sctag0_dc_cam_hit_c6[40] + sctag0_dc_cam_hit_c6[41] +
sctag0_dc_cam_hit_c6[42] + sctag0_dc_cam_hit_c6[43] +
sctag0_ic_cam_hit_c6[40] + sctag0_ic_cam_hit_c6[41] +
sctag0_ic_cam_hit_c6[42] + sctag0_ic_cam_hit_c6[43];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble11_sum = sctag0_dc_cam_hit_c6[44] + sctag0_dc_cam_hit_c6[45] +
sctag0_dc_cam_hit_c6[46] + sctag0_dc_cam_hit_c6[47];
wire [2:0] sctag0_ic_cam_hit_c6_nibble11_sum = sctag0_ic_cam_hit_c6[44] + sctag0_ic_cam_hit_c6[45] +
sctag0_ic_cam_hit_c6[46] + sctag0_ic_cam_hit_c6[47];
wire [3:0] sctag0_both_cam_hit_c6_nibble11_sum= sctag0_dc_cam_hit_c6[44] + sctag0_dc_cam_hit_c6[45] +
sctag0_dc_cam_hit_c6[46] + sctag0_dc_cam_hit_c6[47] +
sctag0_ic_cam_hit_c6[44] + sctag0_ic_cam_hit_c6[45] +
sctag0_ic_cam_hit_c6[46] + sctag0_ic_cam_hit_c6[47];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble12_sum = sctag0_dc_cam_hit_c6[48] + sctag0_dc_cam_hit_c6[49] +
sctag0_dc_cam_hit_c6[50] + sctag0_dc_cam_hit_c6[51];
wire [2:0] sctag0_ic_cam_hit_c6_nibble12_sum = sctag0_ic_cam_hit_c6[48] + sctag0_ic_cam_hit_c6[49] +
sctag0_ic_cam_hit_c6[50] + sctag0_ic_cam_hit_c6[51];
wire [3:0] sctag0_both_cam_hit_c6_nibble12_sum= sctag0_dc_cam_hit_c6[48] + sctag0_dc_cam_hit_c6[49] +
sctag0_dc_cam_hit_c6[50] + sctag0_dc_cam_hit_c6[51] +
sctag0_ic_cam_hit_c6[48] + sctag0_ic_cam_hit_c6[49] +
sctag0_ic_cam_hit_c6[50] + sctag0_ic_cam_hit_c6[51];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble13_sum = sctag0_dc_cam_hit_c6[52] + sctag0_dc_cam_hit_c6[53] +
sctag0_dc_cam_hit_c6[54] + sctag0_dc_cam_hit_c6[55];
wire [2:0] sctag0_ic_cam_hit_c6_nibble13_sum = sctag0_ic_cam_hit_c6[52] + sctag0_ic_cam_hit_c6[53] +
sctag0_ic_cam_hit_c6[54] + sctag0_ic_cam_hit_c6[55];
wire [3:0] sctag0_both_cam_hit_c6_nibble13_sum= sctag0_dc_cam_hit_c6[52] + sctag0_dc_cam_hit_c6[53] +
sctag0_dc_cam_hit_c6[54] + sctag0_dc_cam_hit_c6[55] +
sctag0_ic_cam_hit_c6[52] + sctag0_ic_cam_hit_c6[53] +
sctag0_ic_cam_hit_c6[54] + sctag0_ic_cam_hit_c6[55];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble14_sum = sctag0_dc_cam_hit_c6[56] + sctag0_dc_cam_hit_c6[57] +
sctag0_dc_cam_hit_c6[58] + sctag0_dc_cam_hit_c6[59];
wire [2:0] sctag0_ic_cam_hit_c6_nibble14_sum = sctag0_ic_cam_hit_c6[56] + sctag0_ic_cam_hit_c6[57] +
sctag0_ic_cam_hit_c6[58] + sctag0_ic_cam_hit_c6[59];
wire [3:0] sctag0_both_cam_hit_c6_nibble14_sum= sctag0_dc_cam_hit_c6[56] + sctag0_dc_cam_hit_c6[57] +
sctag0_dc_cam_hit_c6[58] + sctag0_dc_cam_hit_c6[59] +
sctag0_ic_cam_hit_c6[56] + sctag0_ic_cam_hit_c6[57] +
sctag0_ic_cam_hit_c6[58] + sctag0_ic_cam_hit_c6[59];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble15_sum = sctag0_dc_cam_hit_c6[60] + sctag0_dc_cam_hit_c6[61] +
sctag0_dc_cam_hit_c6[62] + sctag0_dc_cam_hit_c6[63];
wire [2:0] sctag0_ic_cam_hit_c6_nibble15_sum = sctag0_ic_cam_hit_c6[60] + sctag0_ic_cam_hit_c6[61] +
sctag0_ic_cam_hit_c6[62] + sctag0_ic_cam_hit_c6[63];
wire [3:0] sctag0_both_cam_hit_c6_nibble15_sum= sctag0_dc_cam_hit_c6[60] + sctag0_dc_cam_hit_c6[61] +
sctag0_dc_cam_hit_c6[62] + sctag0_dc_cam_hit_c6[63] +
sctag0_ic_cam_hit_c6[60] + sctag0_ic_cam_hit_c6[61] +
sctag0_ic_cam_hit_c6[62] + sctag0_ic_cam_hit_c6[63];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble16_sum = sctag0_dc_cam_hit_c6[64] + sctag0_dc_cam_hit_c6[65] +
sctag0_dc_cam_hit_c6[66] + sctag0_dc_cam_hit_c6[67];
wire [2:0] sctag0_ic_cam_hit_c6_nibble16_sum = sctag0_ic_cam_hit_c6[64] + sctag0_ic_cam_hit_c6[65] +
sctag0_ic_cam_hit_c6[66] + sctag0_ic_cam_hit_c6[67];
wire [3:0] sctag0_both_cam_hit_c6_nibble16_sum= sctag0_dc_cam_hit_c6[64] + sctag0_dc_cam_hit_c6[65] +
sctag0_dc_cam_hit_c6[66] + sctag0_dc_cam_hit_c6[67] +
sctag0_ic_cam_hit_c6[64] + sctag0_ic_cam_hit_c6[65] +
sctag0_ic_cam_hit_c6[66] + sctag0_ic_cam_hit_c6[67];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble17_sum = sctag0_dc_cam_hit_c6[68] + sctag0_dc_cam_hit_c6[69] +
sctag0_dc_cam_hit_c6[70] + sctag0_dc_cam_hit_c6[71];
wire [2:0] sctag0_ic_cam_hit_c6_nibble17_sum = sctag0_ic_cam_hit_c6[68] + sctag0_ic_cam_hit_c6[69] +
sctag0_ic_cam_hit_c6[70] + sctag0_ic_cam_hit_c6[71];
wire [3:0] sctag0_both_cam_hit_c6_nibble17_sum= sctag0_dc_cam_hit_c6[68] + sctag0_dc_cam_hit_c6[69] +
sctag0_dc_cam_hit_c6[70] + sctag0_dc_cam_hit_c6[71] +
sctag0_ic_cam_hit_c6[68] + sctag0_ic_cam_hit_c6[69] +
sctag0_ic_cam_hit_c6[70] + sctag0_ic_cam_hit_c6[71];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble18_sum = sctag0_dc_cam_hit_c6[72] + sctag0_dc_cam_hit_c6[73] +
sctag0_dc_cam_hit_c6[74] + sctag0_dc_cam_hit_c6[75];
wire [2:0] sctag0_ic_cam_hit_c6_nibble18_sum = sctag0_ic_cam_hit_c6[72] + sctag0_ic_cam_hit_c6[73] +
sctag0_ic_cam_hit_c6[74] + sctag0_ic_cam_hit_c6[75];
wire [3:0] sctag0_both_cam_hit_c6_nibble18_sum= sctag0_dc_cam_hit_c6[72] + sctag0_dc_cam_hit_c6[73] +
sctag0_dc_cam_hit_c6[74] + sctag0_dc_cam_hit_c6[75] +
sctag0_ic_cam_hit_c6[72] + sctag0_ic_cam_hit_c6[73] +
sctag0_ic_cam_hit_c6[74] + sctag0_ic_cam_hit_c6[75];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble19_sum = sctag0_dc_cam_hit_c6[76] + sctag0_dc_cam_hit_c6[77] +
sctag0_dc_cam_hit_c6[78] + sctag0_dc_cam_hit_c6[79];
wire [2:0] sctag0_ic_cam_hit_c6_nibble19_sum = sctag0_ic_cam_hit_c6[76] + sctag0_ic_cam_hit_c6[77] +
sctag0_ic_cam_hit_c6[78] + sctag0_ic_cam_hit_c6[79];
wire [3:0] sctag0_both_cam_hit_c6_nibble19_sum= sctag0_dc_cam_hit_c6[76] + sctag0_dc_cam_hit_c6[77] +
sctag0_dc_cam_hit_c6[78] + sctag0_dc_cam_hit_c6[79] +
sctag0_ic_cam_hit_c6[76] + sctag0_ic_cam_hit_c6[77] +
sctag0_ic_cam_hit_c6[78] + sctag0_ic_cam_hit_c6[79];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble20_sum = sctag0_dc_cam_hit_c6[80] + sctag0_dc_cam_hit_c6[81] +
sctag0_dc_cam_hit_c6[82] + sctag0_dc_cam_hit_c6[83];
wire [2:0] sctag0_ic_cam_hit_c6_nibble20_sum = sctag0_ic_cam_hit_c6[80] + sctag0_ic_cam_hit_c6[81] +
sctag0_ic_cam_hit_c6[82] + sctag0_ic_cam_hit_c6[83];
wire [3:0] sctag0_both_cam_hit_c6_nibble20_sum= sctag0_dc_cam_hit_c6[80] + sctag0_dc_cam_hit_c6[81] +
sctag0_dc_cam_hit_c6[82] + sctag0_dc_cam_hit_c6[83] +
sctag0_ic_cam_hit_c6[80] + sctag0_ic_cam_hit_c6[81] +
sctag0_ic_cam_hit_c6[82] + sctag0_ic_cam_hit_c6[83];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble21_sum = sctag0_dc_cam_hit_c6[84] + sctag0_dc_cam_hit_c6[85] +
sctag0_dc_cam_hit_c6[86] + sctag0_dc_cam_hit_c6[87];
wire [2:0] sctag0_ic_cam_hit_c6_nibble21_sum = sctag0_ic_cam_hit_c6[84] + sctag0_ic_cam_hit_c6[85] +
sctag0_ic_cam_hit_c6[86] + sctag0_ic_cam_hit_c6[87];
wire [3:0] sctag0_both_cam_hit_c6_nibble21_sum= sctag0_dc_cam_hit_c6[84] + sctag0_dc_cam_hit_c6[85] +
sctag0_dc_cam_hit_c6[86] + sctag0_dc_cam_hit_c6[87] +
sctag0_ic_cam_hit_c6[84] + sctag0_ic_cam_hit_c6[85] +
sctag0_ic_cam_hit_c6[86] + sctag0_ic_cam_hit_c6[87];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble22_sum = sctag0_dc_cam_hit_c6[88] + sctag0_dc_cam_hit_c6[89] +
sctag0_dc_cam_hit_c6[90] + sctag0_dc_cam_hit_c6[91];
wire [2:0] sctag0_ic_cam_hit_c6_nibble22_sum = sctag0_ic_cam_hit_c6[88] + sctag0_ic_cam_hit_c6[89] +
sctag0_ic_cam_hit_c6[90] + sctag0_ic_cam_hit_c6[91];
wire [3:0] sctag0_both_cam_hit_c6_nibble22_sum= sctag0_dc_cam_hit_c6[88] + sctag0_dc_cam_hit_c6[89] +
sctag0_dc_cam_hit_c6[90] + sctag0_dc_cam_hit_c6[91] +
sctag0_ic_cam_hit_c6[88] + sctag0_ic_cam_hit_c6[89] +
sctag0_ic_cam_hit_c6[90] + sctag0_ic_cam_hit_c6[91];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble23_sum = sctag0_dc_cam_hit_c6[92] + sctag0_dc_cam_hit_c6[93] +
sctag0_dc_cam_hit_c6[94] + sctag0_dc_cam_hit_c6[95];
wire [2:0] sctag0_ic_cam_hit_c6_nibble23_sum = sctag0_ic_cam_hit_c6[92] + sctag0_ic_cam_hit_c6[93] +
sctag0_ic_cam_hit_c6[94] + sctag0_ic_cam_hit_c6[95];
wire [3:0] sctag0_both_cam_hit_c6_nibble23_sum= sctag0_dc_cam_hit_c6[92] + sctag0_dc_cam_hit_c6[93] +
sctag0_dc_cam_hit_c6[94] + sctag0_dc_cam_hit_c6[95] +
sctag0_ic_cam_hit_c6[92] + sctag0_ic_cam_hit_c6[93] +
sctag0_ic_cam_hit_c6[94] + sctag0_ic_cam_hit_c6[95];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble24_sum = sctag0_dc_cam_hit_c6[96] + sctag0_dc_cam_hit_c6[97] +
sctag0_dc_cam_hit_c6[98] + sctag0_dc_cam_hit_c6[99];
wire [2:0] sctag0_ic_cam_hit_c6_nibble24_sum = sctag0_ic_cam_hit_c6[96] + sctag0_ic_cam_hit_c6[97] +
sctag0_ic_cam_hit_c6[98] + sctag0_ic_cam_hit_c6[99];
wire [3:0] sctag0_both_cam_hit_c6_nibble24_sum= sctag0_dc_cam_hit_c6[96] + sctag0_dc_cam_hit_c6[97] +
sctag0_dc_cam_hit_c6[98] + sctag0_dc_cam_hit_c6[99] +
sctag0_ic_cam_hit_c6[96] + sctag0_ic_cam_hit_c6[97] +
sctag0_ic_cam_hit_c6[98] + sctag0_ic_cam_hit_c6[99];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble25_sum = sctag0_dc_cam_hit_c6[100] + sctag0_dc_cam_hit_c6[101] +
sctag0_dc_cam_hit_c6[102] + sctag0_dc_cam_hit_c6[103];
wire [2:0] sctag0_ic_cam_hit_c6_nibble25_sum = sctag0_ic_cam_hit_c6[100] + sctag0_ic_cam_hit_c6[101] +
sctag0_ic_cam_hit_c6[102] + sctag0_ic_cam_hit_c6[103];
wire [3:0] sctag0_both_cam_hit_c6_nibble25_sum= sctag0_dc_cam_hit_c6[100] + sctag0_dc_cam_hit_c6[101] +
sctag0_dc_cam_hit_c6[102] + sctag0_dc_cam_hit_c6[103] +
sctag0_ic_cam_hit_c6[100] + sctag0_ic_cam_hit_c6[101] +
sctag0_ic_cam_hit_c6[102] + sctag0_ic_cam_hit_c6[103];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble26_sum = sctag0_dc_cam_hit_c6[104] + sctag0_dc_cam_hit_c6[105] +
sctag0_dc_cam_hit_c6[106] + sctag0_dc_cam_hit_c6[107];
wire [2:0] sctag0_ic_cam_hit_c6_nibble26_sum = sctag0_ic_cam_hit_c6[104] + sctag0_ic_cam_hit_c6[105] +
sctag0_ic_cam_hit_c6[106] + sctag0_ic_cam_hit_c6[107];
wire [3:0] sctag0_both_cam_hit_c6_nibble26_sum= sctag0_dc_cam_hit_c6[104] + sctag0_dc_cam_hit_c6[105] +
sctag0_dc_cam_hit_c6[106] + sctag0_dc_cam_hit_c6[107] +
sctag0_ic_cam_hit_c6[104] + sctag0_ic_cam_hit_c6[105] +
sctag0_ic_cam_hit_c6[106] + sctag0_ic_cam_hit_c6[107];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble27_sum = sctag0_dc_cam_hit_c6[108] + sctag0_dc_cam_hit_c6[109] +
sctag0_dc_cam_hit_c6[110] + sctag0_dc_cam_hit_c6[111];
wire [2:0] sctag0_ic_cam_hit_c6_nibble27_sum = sctag0_ic_cam_hit_c6[108] + sctag0_ic_cam_hit_c6[109] +
sctag0_ic_cam_hit_c6[110] + sctag0_ic_cam_hit_c6[111];
wire [3:0] sctag0_both_cam_hit_c6_nibble27_sum= sctag0_dc_cam_hit_c6[108] + sctag0_dc_cam_hit_c6[109] +
sctag0_dc_cam_hit_c6[110] + sctag0_dc_cam_hit_c6[111] +
sctag0_ic_cam_hit_c6[108] + sctag0_ic_cam_hit_c6[109] +
sctag0_ic_cam_hit_c6[110] + sctag0_ic_cam_hit_c6[111];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble28_sum = sctag0_dc_cam_hit_c6[112] + sctag0_dc_cam_hit_c6[113] +
sctag0_dc_cam_hit_c6[114] + sctag0_dc_cam_hit_c6[115];
wire [2:0] sctag0_ic_cam_hit_c6_nibble28_sum = sctag0_ic_cam_hit_c6[112] + sctag0_ic_cam_hit_c6[113] +
sctag0_ic_cam_hit_c6[114] + sctag0_ic_cam_hit_c6[115];
wire [3:0] sctag0_both_cam_hit_c6_nibble28_sum= sctag0_dc_cam_hit_c6[112] + sctag0_dc_cam_hit_c6[113] +
sctag0_dc_cam_hit_c6[114] + sctag0_dc_cam_hit_c6[115] +
sctag0_ic_cam_hit_c6[112] + sctag0_ic_cam_hit_c6[113] +
sctag0_ic_cam_hit_c6[114] + sctag0_ic_cam_hit_c6[115];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble29_sum = sctag0_dc_cam_hit_c6[116] + sctag0_dc_cam_hit_c6[117] +
sctag0_dc_cam_hit_c6[118] + sctag0_dc_cam_hit_c6[119];
wire [2:0] sctag0_ic_cam_hit_c6_nibble29_sum = sctag0_ic_cam_hit_c6[116] + sctag0_ic_cam_hit_c6[117] +
sctag0_ic_cam_hit_c6[118] + sctag0_ic_cam_hit_c6[119];
wire [3:0] sctag0_both_cam_hit_c6_nibble29_sum= sctag0_dc_cam_hit_c6[116] + sctag0_dc_cam_hit_c6[117] +
sctag0_dc_cam_hit_c6[118] + sctag0_dc_cam_hit_c6[119] +
sctag0_ic_cam_hit_c6[116] + sctag0_ic_cam_hit_c6[117] +
sctag0_ic_cam_hit_c6[118] + sctag0_ic_cam_hit_c6[119];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble30_sum = sctag0_dc_cam_hit_c6[120] + sctag0_dc_cam_hit_c6[121] +
sctag0_dc_cam_hit_c6[122] + sctag0_dc_cam_hit_c6[123];
wire [2:0] sctag0_ic_cam_hit_c6_nibble30_sum = sctag0_ic_cam_hit_c6[120] + sctag0_ic_cam_hit_c6[121] +
sctag0_ic_cam_hit_c6[122] + sctag0_ic_cam_hit_c6[123];
wire [3:0] sctag0_both_cam_hit_c6_nibble30_sum= sctag0_dc_cam_hit_c6[120] + sctag0_dc_cam_hit_c6[121] +
sctag0_dc_cam_hit_c6[122] + sctag0_dc_cam_hit_c6[123] +
sctag0_ic_cam_hit_c6[120] + sctag0_ic_cam_hit_c6[121] +
sctag0_ic_cam_hit_c6[122] + sctag0_ic_cam_hit_c6[123];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble31_sum = sctag0_dc_cam_hit_c6[124] + sctag0_dc_cam_hit_c6[125] +
sctag0_dc_cam_hit_c6[126] + sctag0_dc_cam_hit_c6[127];
wire [2:0] sctag0_ic_cam_hit_c6_nibble31_sum = sctag0_ic_cam_hit_c6[124] + sctag0_ic_cam_hit_c6[125] +
sctag0_ic_cam_hit_c6[126] + sctag0_ic_cam_hit_c6[127];
wire [3:0] sctag0_both_cam_hit_c6_nibble31_sum= sctag0_dc_cam_hit_c6[124] + sctag0_dc_cam_hit_c6[125] +
sctag0_dc_cam_hit_c6[126] + sctag0_dc_cam_hit_c6[127] +
sctag0_ic_cam_hit_c6[124] + sctag0_ic_cam_hit_c6[125] +
sctag0_ic_cam_hit_c6[126] + sctag0_ic_cam_hit_c6[127];
wire [7:0] sctag1_cpx_req_cq = `TOP_MEMORY.sctag1_cpx_req_cq[7:0];
wire [7:0] sctag1_cpx_atom_cq = `TOP_MEMORY.sctag1_cpx_atom_cq;
wire [`CPX_WIDTH-1:0] sctag1_cpx_data_ca = `TOP_MEMORY.sctag1_cpx_data_ca[`CPX_WIDTH-1:0];
wire sctag1_pcx_stall_pq = `TOP_MEMORY.sctag1_pcx_stall_pq;
reg [7:0] sctag1_cpx_req_cq_d1; // delayed by 1
reg [7:0] sctag1_cpx_req_cq_d2; // delayed by 2
reg [7:0] sctag1_cpx_atom_cq_d1; // delayed by 1
reg [7:0] sctag1_cpx_atom_cq_d2; // delayed by 2
reg [127:0] sctag1_cpx_type_str; // in string format
reg [3:0] sctag1_cpx_type; // packet type
reg sctag1_dc_lkup_c5;
reg sctag1_ic_lkup_c5;
reg sctag1_dc_lkup_c6;
reg sctag1_ic_lkup_c6;
wire [3:0] sctag1_dc_lkup_panel_dec_c4 = `TOP_MEMORY.sctag1.dirrep.dc_lkup_panel_dec_c4[3:0];
wire [3:0] sctag1_dc_lkup_row_dec_c4 = `TOP_MEMORY.sctag1.dirrep.dc_lkup_row_dec_c4[3:0];
wire [3:0] sctag1_ic_lkup_panel_dec_c4 = `TOP_MEMORY.sctag1.dirrep.ic_lkup_panel_dec_c4[3:0];
wire [3:0] sctag1_ic_lkup_row_dec_c4 = `TOP_MEMORY.sctag1.dirrep.ic_lkup_row_dec_c4[3:0];
wire [127:0] sctag1_dc_cam_hit_c6 = `TOP_MEMORY.sctag1.dirvec_dp.dc_cam_hit_c6[127:0];
wire [127:0] sctag1_ic_cam_hit_c6 = `TOP_MEMORY.sctag1.dirvec_dp.ic_cam_hit_c6[127:0];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble0_sum = sctag1_dc_cam_hit_c6[0] + sctag1_dc_cam_hit_c6[1] +
sctag1_dc_cam_hit_c6[2] + sctag1_dc_cam_hit_c6[3];
wire [2:0] sctag1_ic_cam_hit_c6_nibble0_sum = sctag1_ic_cam_hit_c6[0] + sctag1_ic_cam_hit_c6[1] +
sctag1_ic_cam_hit_c6[2] + sctag1_ic_cam_hit_c6[3];
wire [3:0] sctag1_both_cam_hit_c6_nibble0_sum= sctag1_dc_cam_hit_c6[0] + sctag1_dc_cam_hit_c6[1] +
sctag1_dc_cam_hit_c6[2] + sctag1_dc_cam_hit_c6[3] +
sctag1_ic_cam_hit_c6[0] + sctag1_ic_cam_hit_c6[1] +
sctag1_ic_cam_hit_c6[2] + sctag1_ic_cam_hit_c6[3];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble1_sum = sctag1_dc_cam_hit_c6[4] + sctag1_dc_cam_hit_c6[5] +
sctag1_dc_cam_hit_c6[6] + sctag1_dc_cam_hit_c6[7];
wire [2:0] sctag1_ic_cam_hit_c6_nibble1_sum = sctag1_ic_cam_hit_c6[4] + sctag1_ic_cam_hit_c6[5] +
sctag1_ic_cam_hit_c6[6] + sctag1_ic_cam_hit_c6[7];
wire [3:0] sctag1_both_cam_hit_c6_nibble1_sum= sctag1_dc_cam_hit_c6[4] + sctag1_dc_cam_hit_c6[5] +
sctag1_dc_cam_hit_c6[6] + sctag1_dc_cam_hit_c6[7] +
sctag1_ic_cam_hit_c6[4] + sctag1_ic_cam_hit_c6[5] +
sctag1_ic_cam_hit_c6[6] + sctag1_ic_cam_hit_c6[7];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble2_sum = sctag1_dc_cam_hit_c6[8] + sctag1_dc_cam_hit_c6[9] +
sctag1_dc_cam_hit_c6[10] + sctag1_dc_cam_hit_c6[11];
wire [2:0] sctag1_ic_cam_hit_c6_nibble2_sum = sctag1_ic_cam_hit_c6[8] + sctag1_ic_cam_hit_c6[9] +
sctag1_ic_cam_hit_c6[10] + sctag1_ic_cam_hit_c6[11];
wire [3:0] sctag1_both_cam_hit_c6_nibble2_sum= sctag1_dc_cam_hit_c6[8] + sctag1_dc_cam_hit_c6[9] +
sctag1_dc_cam_hit_c6[10] + sctag1_dc_cam_hit_c6[11] +
sctag1_ic_cam_hit_c6[8] + sctag1_ic_cam_hit_c6[9] +
sctag1_ic_cam_hit_c6[10] + sctag1_ic_cam_hit_c6[11];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble3_sum = sctag1_dc_cam_hit_c6[12] + sctag1_dc_cam_hit_c6[13] +
sctag1_dc_cam_hit_c6[14] + sctag1_dc_cam_hit_c6[15];
wire [2:0] sctag1_ic_cam_hit_c6_nibble3_sum = sctag1_ic_cam_hit_c6[12] + sctag1_ic_cam_hit_c6[13] +
sctag1_ic_cam_hit_c6[14] + sctag1_ic_cam_hit_c6[15];
wire [3:0] sctag1_both_cam_hit_c6_nibble3_sum= sctag1_dc_cam_hit_c6[12] + sctag1_dc_cam_hit_c6[13] +
sctag1_dc_cam_hit_c6[14] + sctag1_dc_cam_hit_c6[15] +
sctag1_ic_cam_hit_c6[12] + sctag1_ic_cam_hit_c6[13] +
sctag1_ic_cam_hit_c6[14] + sctag1_ic_cam_hit_c6[15];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble4_sum = sctag1_dc_cam_hit_c6[16] + sctag1_dc_cam_hit_c6[17] +
sctag1_dc_cam_hit_c6[18] + sctag1_dc_cam_hit_c6[19];
wire [2:0] sctag1_ic_cam_hit_c6_nibble4_sum = sctag1_ic_cam_hit_c6[16] + sctag1_ic_cam_hit_c6[17] +
sctag1_ic_cam_hit_c6[18] + sctag1_ic_cam_hit_c6[19];
wire [3:0] sctag1_both_cam_hit_c6_nibble4_sum= sctag1_dc_cam_hit_c6[16] + sctag1_dc_cam_hit_c6[17] +
sctag1_dc_cam_hit_c6[18] + sctag1_dc_cam_hit_c6[19] +
sctag1_ic_cam_hit_c6[16] + sctag1_ic_cam_hit_c6[17] +
sctag1_ic_cam_hit_c6[18] + sctag1_ic_cam_hit_c6[19];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble5_sum = sctag1_dc_cam_hit_c6[20] + sctag1_dc_cam_hit_c6[21] +
sctag1_dc_cam_hit_c6[22] + sctag1_dc_cam_hit_c6[23];
wire [2:0] sctag1_ic_cam_hit_c6_nibble5_sum = sctag1_ic_cam_hit_c6[20] + sctag1_ic_cam_hit_c6[21] +
sctag1_ic_cam_hit_c6[22] + sctag1_ic_cam_hit_c6[23];
wire [3:0] sctag1_both_cam_hit_c6_nibble5_sum= sctag1_dc_cam_hit_c6[20] + sctag1_dc_cam_hit_c6[21] +
sctag1_dc_cam_hit_c6[22] + sctag1_dc_cam_hit_c6[23] +
sctag1_ic_cam_hit_c6[20] + sctag1_ic_cam_hit_c6[21] +
sctag1_ic_cam_hit_c6[22] + sctag1_ic_cam_hit_c6[23];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble6_sum = sctag1_dc_cam_hit_c6[24] + sctag1_dc_cam_hit_c6[25] +
sctag1_dc_cam_hit_c6[26] + sctag1_dc_cam_hit_c6[27];
wire [2:0] sctag1_ic_cam_hit_c6_nibble6_sum = sctag1_ic_cam_hit_c6[24] + sctag1_ic_cam_hit_c6[25] +
sctag1_ic_cam_hit_c6[26] + sctag1_ic_cam_hit_c6[27];
wire [3:0] sctag1_both_cam_hit_c6_nibble6_sum= sctag1_dc_cam_hit_c6[24] + sctag1_dc_cam_hit_c6[25] +
sctag1_dc_cam_hit_c6[26] + sctag1_dc_cam_hit_c6[27] +
sctag1_ic_cam_hit_c6[24] + sctag1_ic_cam_hit_c6[25] +
sctag1_ic_cam_hit_c6[26] + sctag1_ic_cam_hit_c6[27];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble7_sum = sctag1_dc_cam_hit_c6[28] + sctag1_dc_cam_hit_c6[29] +
sctag1_dc_cam_hit_c6[30] + sctag1_dc_cam_hit_c6[31];
wire [2:0] sctag1_ic_cam_hit_c6_nibble7_sum = sctag1_ic_cam_hit_c6[28] + sctag1_ic_cam_hit_c6[29] +
sctag1_ic_cam_hit_c6[30] + sctag1_ic_cam_hit_c6[31];
wire [3:0] sctag1_both_cam_hit_c6_nibble7_sum= sctag1_dc_cam_hit_c6[28] + sctag1_dc_cam_hit_c6[29] +
sctag1_dc_cam_hit_c6[30] + sctag1_dc_cam_hit_c6[31] +
sctag1_ic_cam_hit_c6[28] + sctag1_ic_cam_hit_c6[29] +
sctag1_ic_cam_hit_c6[30] + sctag1_ic_cam_hit_c6[31];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble8_sum = sctag1_dc_cam_hit_c6[32] + sctag1_dc_cam_hit_c6[33] +
sctag1_dc_cam_hit_c6[34] + sctag1_dc_cam_hit_c6[35];
wire [2:0] sctag1_ic_cam_hit_c6_nibble8_sum = sctag1_ic_cam_hit_c6[32] + sctag1_ic_cam_hit_c6[33] +
sctag1_ic_cam_hit_c6[34] + sctag1_ic_cam_hit_c6[35];
wire [3:0] sctag1_both_cam_hit_c6_nibble8_sum= sctag1_dc_cam_hit_c6[32] + sctag1_dc_cam_hit_c6[33] +
sctag1_dc_cam_hit_c6[34] + sctag1_dc_cam_hit_c6[35] +
sctag1_ic_cam_hit_c6[32] + sctag1_ic_cam_hit_c6[33] +
sctag1_ic_cam_hit_c6[34] + sctag1_ic_cam_hit_c6[35];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble9_sum = sctag1_dc_cam_hit_c6[36] + sctag1_dc_cam_hit_c6[37] +
sctag1_dc_cam_hit_c6[38] + sctag1_dc_cam_hit_c6[39];
wire [2:0] sctag1_ic_cam_hit_c6_nibble9_sum = sctag1_ic_cam_hit_c6[36] + sctag1_ic_cam_hit_c6[37] +
sctag1_ic_cam_hit_c6[38] + sctag1_ic_cam_hit_c6[39];
wire [3:0] sctag1_both_cam_hit_c6_nibble9_sum= sctag1_dc_cam_hit_c6[36] + sctag1_dc_cam_hit_c6[37] +
sctag1_dc_cam_hit_c6[38] + sctag1_dc_cam_hit_c6[39] +
sctag1_ic_cam_hit_c6[36] + sctag1_ic_cam_hit_c6[37] +
sctag1_ic_cam_hit_c6[38] + sctag1_ic_cam_hit_c6[39];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble10_sum = sctag1_dc_cam_hit_c6[40] + sctag1_dc_cam_hit_c6[41] +
sctag1_dc_cam_hit_c6[42] + sctag1_dc_cam_hit_c6[43];
wire [2:0] sctag1_ic_cam_hit_c6_nibble10_sum = sctag1_ic_cam_hit_c6[40] + sctag1_ic_cam_hit_c6[41] +
sctag1_ic_cam_hit_c6[42] + sctag1_ic_cam_hit_c6[43];
wire [3:0] sctag1_both_cam_hit_c6_nibble10_sum= sctag1_dc_cam_hit_c6[40] + sctag1_dc_cam_hit_c6[41] +
sctag1_dc_cam_hit_c6[42] + sctag1_dc_cam_hit_c6[43] +
sctag1_ic_cam_hit_c6[40] + sctag1_ic_cam_hit_c6[41] +
sctag1_ic_cam_hit_c6[42] + sctag1_ic_cam_hit_c6[43];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble11_sum = sctag1_dc_cam_hit_c6[44] + sctag1_dc_cam_hit_c6[45] +
sctag1_dc_cam_hit_c6[46] + sctag1_dc_cam_hit_c6[47];
wire [2:0] sctag1_ic_cam_hit_c6_nibble11_sum = sctag1_ic_cam_hit_c6[44] + sctag1_ic_cam_hit_c6[45] +
sctag1_ic_cam_hit_c6[46] + sctag1_ic_cam_hit_c6[47];
wire [3:0] sctag1_both_cam_hit_c6_nibble11_sum= sctag1_dc_cam_hit_c6[44] + sctag1_dc_cam_hit_c6[45] +
sctag1_dc_cam_hit_c6[46] + sctag1_dc_cam_hit_c6[47] +
sctag1_ic_cam_hit_c6[44] + sctag1_ic_cam_hit_c6[45] +
sctag1_ic_cam_hit_c6[46] + sctag1_ic_cam_hit_c6[47];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble12_sum = sctag1_dc_cam_hit_c6[48] + sctag1_dc_cam_hit_c6[49] +
sctag1_dc_cam_hit_c6[50] + sctag1_dc_cam_hit_c6[51];
wire [2:0] sctag1_ic_cam_hit_c6_nibble12_sum = sctag1_ic_cam_hit_c6[48] + sctag1_ic_cam_hit_c6[49] +
sctag1_ic_cam_hit_c6[50] + sctag1_ic_cam_hit_c6[51];
wire [3:0] sctag1_both_cam_hit_c6_nibble12_sum= sctag1_dc_cam_hit_c6[48] + sctag1_dc_cam_hit_c6[49] +
sctag1_dc_cam_hit_c6[50] + sctag1_dc_cam_hit_c6[51] +
sctag1_ic_cam_hit_c6[48] + sctag1_ic_cam_hit_c6[49] +
sctag1_ic_cam_hit_c6[50] + sctag1_ic_cam_hit_c6[51];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble13_sum = sctag1_dc_cam_hit_c6[52] + sctag1_dc_cam_hit_c6[53] +
sctag1_dc_cam_hit_c6[54] + sctag1_dc_cam_hit_c6[55];
wire [2:0] sctag1_ic_cam_hit_c6_nibble13_sum = sctag1_ic_cam_hit_c6[52] + sctag1_ic_cam_hit_c6[53] +
sctag1_ic_cam_hit_c6[54] + sctag1_ic_cam_hit_c6[55];
wire [3:0] sctag1_both_cam_hit_c6_nibble13_sum= sctag1_dc_cam_hit_c6[52] + sctag1_dc_cam_hit_c6[53] +
sctag1_dc_cam_hit_c6[54] + sctag1_dc_cam_hit_c6[55] +
sctag1_ic_cam_hit_c6[52] + sctag1_ic_cam_hit_c6[53] +
sctag1_ic_cam_hit_c6[54] + sctag1_ic_cam_hit_c6[55];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble14_sum = sctag1_dc_cam_hit_c6[56] + sctag1_dc_cam_hit_c6[57] +
sctag1_dc_cam_hit_c6[58] + sctag1_dc_cam_hit_c6[59];
wire [2:0] sctag1_ic_cam_hit_c6_nibble14_sum = sctag1_ic_cam_hit_c6[56] + sctag1_ic_cam_hit_c6[57] +
sctag1_ic_cam_hit_c6[58] + sctag1_ic_cam_hit_c6[59];
wire [3:0] sctag1_both_cam_hit_c6_nibble14_sum= sctag1_dc_cam_hit_c6[56] + sctag1_dc_cam_hit_c6[57] +
sctag1_dc_cam_hit_c6[58] + sctag1_dc_cam_hit_c6[59] +
sctag1_ic_cam_hit_c6[56] + sctag1_ic_cam_hit_c6[57] +
sctag1_ic_cam_hit_c6[58] + sctag1_ic_cam_hit_c6[59];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble15_sum = sctag1_dc_cam_hit_c6[60] + sctag1_dc_cam_hit_c6[61] +
sctag1_dc_cam_hit_c6[62] + sctag1_dc_cam_hit_c6[63];
wire [2:0] sctag1_ic_cam_hit_c6_nibble15_sum = sctag1_ic_cam_hit_c6[60] + sctag1_ic_cam_hit_c6[61] +
sctag1_ic_cam_hit_c6[62] + sctag1_ic_cam_hit_c6[63];
wire [3:0] sctag1_both_cam_hit_c6_nibble15_sum= sctag1_dc_cam_hit_c6[60] + sctag1_dc_cam_hit_c6[61] +
sctag1_dc_cam_hit_c6[62] + sctag1_dc_cam_hit_c6[63] +
sctag1_ic_cam_hit_c6[60] + sctag1_ic_cam_hit_c6[61] +
sctag1_ic_cam_hit_c6[62] + sctag1_ic_cam_hit_c6[63];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble16_sum = sctag1_dc_cam_hit_c6[64] + sctag1_dc_cam_hit_c6[65] +
sctag1_dc_cam_hit_c6[66] + sctag1_dc_cam_hit_c6[67];
wire [2:0] sctag1_ic_cam_hit_c6_nibble16_sum = sctag1_ic_cam_hit_c6[64] + sctag1_ic_cam_hit_c6[65] +
sctag1_ic_cam_hit_c6[66] + sctag1_ic_cam_hit_c6[67];
wire [3:0] sctag1_both_cam_hit_c6_nibble16_sum= sctag1_dc_cam_hit_c6[64] + sctag1_dc_cam_hit_c6[65] +
sctag1_dc_cam_hit_c6[66] + sctag1_dc_cam_hit_c6[67] +
sctag1_ic_cam_hit_c6[64] + sctag1_ic_cam_hit_c6[65] +
sctag1_ic_cam_hit_c6[66] + sctag1_ic_cam_hit_c6[67];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble17_sum = sctag1_dc_cam_hit_c6[68] + sctag1_dc_cam_hit_c6[69] +
sctag1_dc_cam_hit_c6[70] + sctag1_dc_cam_hit_c6[71];
wire [2:0] sctag1_ic_cam_hit_c6_nibble17_sum = sctag1_ic_cam_hit_c6[68] + sctag1_ic_cam_hit_c6[69] +
sctag1_ic_cam_hit_c6[70] + sctag1_ic_cam_hit_c6[71];
wire [3:0] sctag1_both_cam_hit_c6_nibble17_sum= sctag1_dc_cam_hit_c6[68] + sctag1_dc_cam_hit_c6[69] +
sctag1_dc_cam_hit_c6[70] + sctag1_dc_cam_hit_c6[71] +
sctag1_ic_cam_hit_c6[68] + sctag1_ic_cam_hit_c6[69] +
sctag1_ic_cam_hit_c6[70] + sctag1_ic_cam_hit_c6[71];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble18_sum = sctag1_dc_cam_hit_c6[72] + sctag1_dc_cam_hit_c6[73] +
sctag1_dc_cam_hit_c6[74] + sctag1_dc_cam_hit_c6[75];
wire [2:0] sctag1_ic_cam_hit_c6_nibble18_sum = sctag1_ic_cam_hit_c6[72] + sctag1_ic_cam_hit_c6[73] +
sctag1_ic_cam_hit_c6[74] + sctag1_ic_cam_hit_c6[75];
wire [3:0] sctag1_both_cam_hit_c6_nibble18_sum= sctag1_dc_cam_hit_c6[72] + sctag1_dc_cam_hit_c6[73] +
sctag1_dc_cam_hit_c6[74] + sctag1_dc_cam_hit_c6[75] +
sctag1_ic_cam_hit_c6[72] + sctag1_ic_cam_hit_c6[73] +
sctag1_ic_cam_hit_c6[74] + sctag1_ic_cam_hit_c6[75];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble19_sum = sctag1_dc_cam_hit_c6[76] + sctag1_dc_cam_hit_c6[77] +
sctag1_dc_cam_hit_c6[78] + sctag1_dc_cam_hit_c6[79];
wire [2:0] sctag1_ic_cam_hit_c6_nibble19_sum = sctag1_ic_cam_hit_c6[76] + sctag1_ic_cam_hit_c6[77] +
sctag1_ic_cam_hit_c6[78] + sctag1_ic_cam_hit_c6[79];
wire [3:0] sctag1_both_cam_hit_c6_nibble19_sum= sctag1_dc_cam_hit_c6[76] + sctag1_dc_cam_hit_c6[77] +
sctag1_dc_cam_hit_c6[78] + sctag1_dc_cam_hit_c6[79] +
sctag1_ic_cam_hit_c6[76] + sctag1_ic_cam_hit_c6[77] +
sctag1_ic_cam_hit_c6[78] + sctag1_ic_cam_hit_c6[79];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble20_sum = sctag1_dc_cam_hit_c6[80] + sctag1_dc_cam_hit_c6[81] +
sctag1_dc_cam_hit_c6[82] + sctag1_dc_cam_hit_c6[83];
wire [2:0] sctag1_ic_cam_hit_c6_nibble20_sum = sctag1_ic_cam_hit_c6[80] + sctag1_ic_cam_hit_c6[81] +
sctag1_ic_cam_hit_c6[82] + sctag1_ic_cam_hit_c6[83];
wire [3:0] sctag1_both_cam_hit_c6_nibble20_sum= sctag1_dc_cam_hit_c6[80] + sctag1_dc_cam_hit_c6[81] +
sctag1_dc_cam_hit_c6[82] + sctag1_dc_cam_hit_c6[83] +
sctag1_ic_cam_hit_c6[80] + sctag1_ic_cam_hit_c6[81] +
sctag1_ic_cam_hit_c6[82] + sctag1_ic_cam_hit_c6[83];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble21_sum = sctag1_dc_cam_hit_c6[84] + sctag1_dc_cam_hit_c6[85] +
sctag1_dc_cam_hit_c6[86] + sctag1_dc_cam_hit_c6[87];
wire [2:0] sctag1_ic_cam_hit_c6_nibble21_sum = sctag1_ic_cam_hit_c6[84] + sctag1_ic_cam_hit_c6[85] +
sctag1_ic_cam_hit_c6[86] + sctag1_ic_cam_hit_c6[87];
wire [3:0] sctag1_both_cam_hit_c6_nibble21_sum= sctag1_dc_cam_hit_c6[84] + sctag1_dc_cam_hit_c6[85] +
sctag1_dc_cam_hit_c6[86] + sctag1_dc_cam_hit_c6[87] +
sctag1_ic_cam_hit_c6[84] + sctag1_ic_cam_hit_c6[85] +
sctag1_ic_cam_hit_c6[86] + sctag1_ic_cam_hit_c6[87];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble22_sum = sctag1_dc_cam_hit_c6[88] + sctag1_dc_cam_hit_c6[89] +
sctag1_dc_cam_hit_c6[90] + sctag1_dc_cam_hit_c6[91];
wire [2:0] sctag1_ic_cam_hit_c6_nibble22_sum = sctag1_ic_cam_hit_c6[88] + sctag1_ic_cam_hit_c6[89] +
sctag1_ic_cam_hit_c6[90] + sctag1_ic_cam_hit_c6[91];
wire [3:0] sctag1_both_cam_hit_c6_nibble22_sum= sctag1_dc_cam_hit_c6[88] + sctag1_dc_cam_hit_c6[89] +
sctag1_dc_cam_hit_c6[90] + sctag1_dc_cam_hit_c6[91] +
sctag1_ic_cam_hit_c6[88] + sctag1_ic_cam_hit_c6[89] +
sctag1_ic_cam_hit_c6[90] + sctag1_ic_cam_hit_c6[91];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble23_sum = sctag1_dc_cam_hit_c6[92] + sctag1_dc_cam_hit_c6[93] +
sctag1_dc_cam_hit_c6[94] + sctag1_dc_cam_hit_c6[95];
wire [2:0] sctag1_ic_cam_hit_c6_nibble23_sum = sctag1_ic_cam_hit_c6[92] + sctag1_ic_cam_hit_c6[93] +
sctag1_ic_cam_hit_c6[94] + sctag1_ic_cam_hit_c6[95];
wire [3:0] sctag1_both_cam_hit_c6_nibble23_sum= sctag1_dc_cam_hit_c6[92] + sctag1_dc_cam_hit_c6[93] +
sctag1_dc_cam_hit_c6[94] + sctag1_dc_cam_hit_c6[95] +
sctag1_ic_cam_hit_c6[92] + sctag1_ic_cam_hit_c6[93] +
sctag1_ic_cam_hit_c6[94] + sctag1_ic_cam_hit_c6[95];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble24_sum = sctag1_dc_cam_hit_c6[96] + sctag1_dc_cam_hit_c6[97] +
sctag1_dc_cam_hit_c6[98] + sctag1_dc_cam_hit_c6[99];
wire [2:0] sctag1_ic_cam_hit_c6_nibble24_sum = sctag1_ic_cam_hit_c6[96] + sctag1_ic_cam_hit_c6[97] +
sctag1_ic_cam_hit_c6[98] + sctag1_ic_cam_hit_c6[99];
wire [3:0] sctag1_both_cam_hit_c6_nibble24_sum= sctag1_dc_cam_hit_c6[96] + sctag1_dc_cam_hit_c6[97] +
sctag1_dc_cam_hit_c6[98] + sctag1_dc_cam_hit_c6[99] +
sctag1_ic_cam_hit_c6[96] + sctag1_ic_cam_hit_c6[97] +
sctag1_ic_cam_hit_c6[98] + sctag1_ic_cam_hit_c6[99];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble25_sum = sctag1_dc_cam_hit_c6[100] + sctag1_dc_cam_hit_c6[101] +
sctag1_dc_cam_hit_c6[102] + sctag1_dc_cam_hit_c6[103];
wire [2:0] sctag1_ic_cam_hit_c6_nibble25_sum = sctag1_ic_cam_hit_c6[100] + sctag1_ic_cam_hit_c6[101] +
sctag1_ic_cam_hit_c6[102] + sctag1_ic_cam_hit_c6[103];
wire [3:0] sctag1_both_cam_hit_c6_nibble25_sum= sctag1_dc_cam_hit_c6[100] + sctag1_dc_cam_hit_c6[101] +
sctag1_dc_cam_hit_c6[102] + sctag1_dc_cam_hit_c6[103] +
sctag1_ic_cam_hit_c6[100] + sctag1_ic_cam_hit_c6[101] +
sctag1_ic_cam_hit_c6[102] + sctag1_ic_cam_hit_c6[103];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble26_sum = sctag1_dc_cam_hit_c6[104] + sctag1_dc_cam_hit_c6[105] +
sctag1_dc_cam_hit_c6[106] + sctag1_dc_cam_hit_c6[107];
wire [2:0] sctag1_ic_cam_hit_c6_nibble26_sum = sctag1_ic_cam_hit_c6[104] + sctag1_ic_cam_hit_c6[105] +
sctag1_ic_cam_hit_c6[106] + sctag1_ic_cam_hit_c6[107];
wire [3:0] sctag1_both_cam_hit_c6_nibble26_sum= sctag1_dc_cam_hit_c6[104] + sctag1_dc_cam_hit_c6[105] +
sctag1_dc_cam_hit_c6[106] + sctag1_dc_cam_hit_c6[107] +
sctag1_ic_cam_hit_c6[104] + sctag1_ic_cam_hit_c6[105] +
sctag1_ic_cam_hit_c6[106] + sctag1_ic_cam_hit_c6[107];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble27_sum = sctag1_dc_cam_hit_c6[108] + sctag1_dc_cam_hit_c6[109] +
sctag1_dc_cam_hit_c6[110] + sctag1_dc_cam_hit_c6[111];
wire [2:0] sctag1_ic_cam_hit_c6_nibble27_sum = sctag1_ic_cam_hit_c6[108] + sctag1_ic_cam_hit_c6[109] +
sctag1_ic_cam_hit_c6[110] + sctag1_ic_cam_hit_c6[111];
wire [3:0] sctag1_both_cam_hit_c6_nibble27_sum= sctag1_dc_cam_hit_c6[108] + sctag1_dc_cam_hit_c6[109] +
sctag1_dc_cam_hit_c6[110] + sctag1_dc_cam_hit_c6[111] +
sctag1_ic_cam_hit_c6[108] + sctag1_ic_cam_hit_c6[109] +
sctag1_ic_cam_hit_c6[110] + sctag1_ic_cam_hit_c6[111];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble28_sum = sctag1_dc_cam_hit_c6[112] + sctag1_dc_cam_hit_c6[113] +
sctag1_dc_cam_hit_c6[114] + sctag1_dc_cam_hit_c6[115];
wire [2:0] sctag1_ic_cam_hit_c6_nibble28_sum = sctag1_ic_cam_hit_c6[112] + sctag1_ic_cam_hit_c6[113] +
sctag1_ic_cam_hit_c6[114] + sctag1_ic_cam_hit_c6[115];
wire [3:0] sctag1_both_cam_hit_c6_nibble28_sum= sctag1_dc_cam_hit_c6[112] + sctag1_dc_cam_hit_c6[113] +
sctag1_dc_cam_hit_c6[114] + sctag1_dc_cam_hit_c6[115] +
sctag1_ic_cam_hit_c6[112] + sctag1_ic_cam_hit_c6[113] +
sctag1_ic_cam_hit_c6[114] + sctag1_ic_cam_hit_c6[115];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble29_sum = sctag1_dc_cam_hit_c6[116] + sctag1_dc_cam_hit_c6[117] +
sctag1_dc_cam_hit_c6[118] + sctag1_dc_cam_hit_c6[119];
wire [2:0] sctag1_ic_cam_hit_c6_nibble29_sum = sctag1_ic_cam_hit_c6[116] + sctag1_ic_cam_hit_c6[117] +
sctag1_ic_cam_hit_c6[118] + sctag1_ic_cam_hit_c6[119];
wire [3:0] sctag1_both_cam_hit_c6_nibble29_sum= sctag1_dc_cam_hit_c6[116] + sctag1_dc_cam_hit_c6[117] +
sctag1_dc_cam_hit_c6[118] + sctag1_dc_cam_hit_c6[119] +
sctag1_ic_cam_hit_c6[116] + sctag1_ic_cam_hit_c6[117] +
sctag1_ic_cam_hit_c6[118] + sctag1_ic_cam_hit_c6[119];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble30_sum = sctag1_dc_cam_hit_c6[120] + sctag1_dc_cam_hit_c6[121] +
sctag1_dc_cam_hit_c6[122] + sctag1_dc_cam_hit_c6[123];
wire [2:0] sctag1_ic_cam_hit_c6_nibble30_sum = sctag1_ic_cam_hit_c6[120] + sctag1_ic_cam_hit_c6[121] +
sctag1_ic_cam_hit_c6[122] + sctag1_ic_cam_hit_c6[123];
wire [3:0] sctag1_both_cam_hit_c6_nibble30_sum= sctag1_dc_cam_hit_c6[120] + sctag1_dc_cam_hit_c6[121] +
sctag1_dc_cam_hit_c6[122] + sctag1_dc_cam_hit_c6[123] +
sctag1_ic_cam_hit_c6[120] + sctag1_ic_cam_hit_c6[121] +
sctag1_ic_cam_hit_c6[122] + sctag1_ic_cam_hit_c6[123];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble31_sum = sctag1_dc_cam_hit_c6[124] + sctag1_dc_cam_hit_c6[125] +
sctag1_dc_cam_hit_c6[126] + sctag1_dc_cam_hit_c6[127];
wire [2:0] sctag1_ic_cam_hit_c6_nibble31_sum = sctag1_ic_cam_hit_c6[124] + sctag1_ic_cam_hit_c6[125] +
sctag1_ic_cam_hit_c6[126] + sctag1_ic_cam_hit_c6[127];
wire [3:0] sctag1_both_cam_hit_c6_nibble31_sum= sctag1_dc_cam_hit_c6[124] + sctag1_dc_cam_hit_c6[125] +
sctag1_dc_cam_hit_c6[126] + sctag1_dc_cam_hit_c6[127] +
sctag1_ic_cam_hit_c6[124] + sctag1_ic_cam_hit_c6[125] +
sctag1_ic_cam_hit_c6[126] + sctag1_ic_cam_hit_c6[127];
wire [7:0] sctag2_cpx_req_cq = `TOP_MEMORY.sctag2_cpx_req_cq[7:0];
wire [7:0] sctag2_cpx_atom_cq = `TOP_MEMORY.sctag2_cpx_atom_cq;
wire [`CPX_WIDTH-1:0] sctag2_cpx_data_ca = `TOP_MEMORY.sctag2_cpx_data_ca[`CPX_WIDTH-1:0];
wire sctag2_pcx_stall_pq = `TOP_MEMORY.sctag2_pcx_stall_pq;
reg [7:0] sctag2_cpx_req_cq_d1; // delayed by 1
reg [7:0] sctag2_cpx_req_cq_d2; // delayed by 2
reg [7:0] sctag2_cpx_atom_cq_d1; // delayed by 1
reg [7:0] sctag2_cpx_atom_cq_d2; // delayed by 2
reg [127:0] sctag2_cpx_type_str; // in string format
reg [3:0] sctag2_cpx_type; // packet type
reg sctag2_dc_lkup_c5;
reg sctag2_ic_lkup_c5;
reg sctag2_dc_lkup_c6;
reg sctag2_ic_lkup_c6;
wire [3:0] sctag2_dc_lkup_panel_dec_c4 = `TOP_MEMORY.sctag2.dirrep.dc_lkup_panel_dec_c4[3:0];
wire [3:0] sctag2_dc_lkup_row_dec_c4 = `TOP_MEMORY.sctag2.dirrep.dc_lkup_row_dec_c4[3:0];
wire [3:0] sctag2_ic_lkup_panel_dec_c4 = `TOP_MEMORY.sctag2.dirrep.ic_lkup_panel_dec_c4[3:0];
wire [3:0] sctag2_ic_lkup_row_dec_c4 = `TOP_MEMORY.sctag2.dirrep.ic_lkup_row_dec_c4[3:0];
wire [127:0] sctag2_dc_cam_hit_c6 = `TOP_MEMORY.sctag2.dirvec_dp.dc_cam_hit_c6[127:0];
wire [127:0] sctag2_ic_cam_hit_c6 = `TOP_MEMORY.sctag2.dirvec_dp.ic_cam_hit_c6[127:0];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble0_sum = sctag2_dc_cam_hit_c6[0] + sctag2_dc_cam_hit_c6[1] +
sctag2_dc_cam_hit_c6[2] + sctag2_dc_cam_hit_c6[3];
wire [2:0] sctag2_ic_cam_hit_c6_nibble0_sum = sctag2_ic_cam_hit_c6[0] + sctag2_ic_cam_hit_c6[1] +
sctag2_ic_cam_hit_c6[2] + sctag2_ic_cam_hit_c6[3];
wire [3:0] sctag2_both_cam_hit_c6_nibble0_sum= sctag2_dc_cam_hit_c6[0] + sctag2_dc_cam_hit_c6[1] +
sctag2_dc_cam_hit_c6[2] + sctag2_dc_cam_hit_c6[3] +
sctag2_ic_cam_hit_c6[0] + sctag2_ic_cam_hit_c6[1] +
sctag2_ic_cam_hit_c6[2] + sctag2_ic_cam_hit_c6[3];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble1_sum = sctag2_dc_cam_hit_c6[4] + sctag2_dc_cam_hit_c6[5] +
sctag2_dc_cam_hit_c6[6] + sctag2_dc_cam_hit_c6[7];
wire [2:0] sctag2_ic_cam_hit_c6_nibble1_sum = sctag2_ic_cam_hit_c6[4] + sctag2_ic_cam_hit_c6[5] +
sctag2_ic_cam_hit_c6[6] + sctag2_ic_cam_hit_c6[7];
wire [3:0] sctag2_both_cam_hit_c6_nibble1_sum= sctag2_dc_cam_hit_c6[4] + sctag2_dc_cam_hit_c6[5] +
sctag2_dc_cam_hit_c6[6] + sctag2_dc_cam_hit_c6[7] +
sctag2_ic_cam_hit_c6[4] + sctag2_ic_cam_hit_c6[5] +
sctag2_ic_cam_hit_c6[6] + sctag2_ic_cam_hit_c6[7];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble2_sum = sctag2_dc_cam_hit_c6[8] + sctag2_dc_cam_hit_c6[9] +
sctag2_dc_cam_hit_c6[10] + sctag2_dc_cam_hit_c6[11];
wire [2:0] sctag2_ic_cam_hit_c6_nibble2_sum = sctag2_ic_cam_hit_c6[8] + sctag2_ic_cam_hit_c6[9] +
sctag2_ic_cam_hit_c6[10] + sctag2_ic_cam_hit_c6[11];
wire [3:0] sctag2_both_cam_hit_c6_nibble2_sum= sctag2_dc_cam_hit_c6[8] + sctag2_dc_cam_hit_c6[9] +
sctag2_dc_cam_hit_c6[10] + sctag2_dc_cam_hit_c6[11] +
sctag2_ic_cam_hit_c6[8] + sctag2_ic_cam_hit_c6[9] +
sctag2_ic_cam_hit_c6[10] + sctag2_ic_cam_hit_c6[11];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble3_sum = sctag2_dc_cam_hit_c6[12] + sctag2_dc_cam_hit_c6[13] +
sctag2_dc_cam_hit_c6[14] + sctag2_dc_cam_hit_c6[15];
wire [2:0] sctag2_ic_cam_hit_c6_nibble3_sum = sctag2_ic_cam_hit_c6[12] + sctag2_ic_cam_hit_c6[13] +
sctag2_ic_cam_hit_c6[14] + sctag2_ic_cam_hit_c6[15];
wire [3:0] sctag2_both_cam_hit_c6_nibble3_sum= sctag2_dc_cam_hit_c6[12] + sctag2_dc_cam_hit_c6[13] +
sctag2_dc_cam_hit_c6[14] + sctag2_dc_cam_hit_c6[15] +
sctag2_ic_cam_hit_c6[12] + sctag2_ic_cam_hit_c6[13] +
sctag2_ic_cam_hit_c6[14] + sctag2_ic_cam_hit_c6[15];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble4_sum = sctag2_dc_cam_hit_c6[16] + sctag2_dc_cam_hit_c6[17] +
sctag2_dc_cam_hit_c6[18] + sctag2_dc_cam_hit_c6[19];
wire [2:0] sctag2_ic_cam_hit_c6_nibble4_sum = sctag2_ic_cam_hit_c6[16] + sctag2_ic_cam_hit_c6[17] +
sctag2_ic_cam_hit_c6[18] + sctag2_ic_cam_hit_c6[19];
wire [3:0] sctag2_both_cam_hit_c6_nibble4_sum= sctag2_dc_cam_hit_c6[16] + sctag2_dc_cam_hit_c6[17] +
sctag2_dc_cam_hit_c6[18] + sctag2_dc_cam_hit_c6[19] +
sctag2_ic_cam_hit_c6[16] + sctag2_ic_cam_hit_c6[17] +
sctag2_ic_cam_hit_c6[18] + sctag2_ic_cam_hit_c6[19];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble5_sum = sctag2_dc_cam_hit_c6[20] + sctag2_dc_cam_hit_c6[21] +
sctag2_dc_cam_hit_c6[22] + sctag2_dc_cam_hit_c6[23];
wire [2:0] sctag2_ic_cam_hit_c6_nibble5_sum = sctag2_ic_cam_hit_c6[20] + sctag2_ic_cam_hit_c6[21] +
sctag2_ic_cam_hit_c6[22] + sctag2_ic_cam_hit_c6[23];
wire [3:0] sctag2_both_cam_hit_c6_nibble5_sum= sctag2_dc_cam_hit_c6[20] + sctag2_dc_cam_hit_c6[21] +
sctag2_dc_cam_hit_c6[22] + sctag2_dc_cam_hit_c6[23] +
sctag2_ic_cam_hit_c6[20] + sctag2_ic_cam_hit_c6[21] +
sctag2_ic_cam_hit_c6[22] + sctag2_ic_cam_hit_c6[23];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble6_sum = sctag2_dc_cam_hit_c6[24] + sctag2_dc_cam_hit_c6[25] +
sctag2_dc_cam_hit_c6[26] + sctag2_dc_cam_hit_c6[27];
wire [2:0] sctag2_ic_cam_hit_c6_nibble6_sum = sctag2_ic_cam_hit_c6[24] + sctag2_ic_cam_hit_c6[25] +
sctag2_ic_cam_hit_c6[26] + sctag2_ic_cam_hit_c6[27];
wire [3:0] sctag2_both_cam_hit_c6_nibble6_sum= sctag2_dc_cam_hit_c6[24] + sctag2_dc_cam_hit_c6[25] +
sctag2_dc_cam_hit_c6[26] + sctag2_dc_cam_hit_c6[27] +
sctag2_ic_cam_hit_c6[24] + sctag2_ic_cam_hit_c6[25] +
sctag2_ic_cam_hit_c6[26] + sctag2_ic_cam_hit_c6[27];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble7_sum = sctag2_dc_cam_hit_c6[28] + sctag2_dc_cam_hit_c6[29] +
sctag2_dc_cam_hit_c6[30] + sctag2_dc_cam_hit_c6[31];
wire [2:0] sctag2_ic_cam_hit_c6_nibble7_sum = sctag2_ic_cam_hit_c6[28] + sctag2_ic_cam_hit_c6[29] +
sctag2_ic_cam_hit_c6[30] + sctag2_ic_cam_hit_c6[31];
wire [3:0] sctag2_both_cam_hit_c6_nibble7_sum= sctag2_dc_cam_hit_c6[28] + sctag2_dc_cam_hit_c6[29] +
sctag2_dc_cam_hit_c6[30] + sctag2_dc_cam_hit_c6[31] +
sctag2_ic_cam_hit_c6[28] + sctag2_ic_cam_hit_c6[29] +
sctag2_ic_cam_hit_c6[30] + sctag2_ic_cam_hit_c6[31];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble8_sum = sctag2_dc_cam_hit_c6[32] + sctag2_dc_cam_hit_c6[33] +
sctag2_dc_cam_hit_c6[34] + sctag2_dc_cam_hit_c6[35];
wire [2:0] sctag2_ic_cam_hit_c6_nibble8_sum = sctag2_ic_cam_hit_c6[32] + sctag2_ic_cam_hit_c6[33] +
sctag2_ic_cam_hit_c6[34] + sctag2_ic_cam_hit_c6[35];
wire [3:0] sctag2_both_cam_hit_c6_nibble8_sum= sctag2_dc_cam_hit_c6[32] + sctag2_dc_cam_hit_c6[33] +
sctag2_dc_cam_hit_c6[34] + sctag2_dc_cam_hit_c6[35] +
sctag2_ic_cam_hit_c6[32] + sctag2_ic_cam_hit_c6[33] +
sctag2_ic_cam_hit_c6[34] + sctag2_ic_cam_hit_c6[35];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble9_sum = sctag2_dc_cam_hit_c6[36] + sctag2_dc_cam_hit_c6[37] +
sctag2_dc_cam_hit_c6[38] + sctag2_dc_cam_hit_c6[39];
wire [2:0] sctag2_ic_cam_hit_c6_nibble9_sum = sctag2_ic_cam_hit_c6[36] + sctag2_ic_cam_hit_c6[37] +
sctag2_ic_cam_hit_c6[38] + sctag2_ic_cam_hit_c6[39];
wire [3:0] sctag2_both_cam_hit_c6_nibble9_sum= sctag2_dc_cam_hit_c6[36] + sctag2_dc_cam_hit_c6[37] +
sctag2_dc_cam_hit_c6[38] + sctag2_dc_cam_hit_c6[39] +
sctag2_ic_cam_hit_c6[36] + sctag2_ic_cam_hit_c6[37] +
sctag2_ic_cam_hit_c6[38] + sctag2_ic_cam_hit_c6[39];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble10_sum = sctag2_dc_cam_hit_c6[40] + sctag2_dc_cam_hit_c6[41] +
sctag2_dc_cam_hit_c6[42] + sctag2_dc_cam_hit_c6[43];
wire [2:0] sctag2_ic_cam_hit_c6_nibble10_sum = sctag2_ic_cam_hit_c6[40] + sctag2_ic_cam_hit_c6[41] +
sctag2_ic_cam_hit_c6[42] + sctag2_ic_cam_hit_c6[43];
wire [3:0] sctag2_both_cam_hit_c6_nibble10_sum= sctag2_dc_cam_hit_c6[40] + sctag2_dc_cam_hit_c6[41] +
sctag2_dc_cam_hit_c6[42] + sctag2_dc_cam_hit_c6[43] +
sctag2_ic_cam_hit_c6[40] + sctag2_ic_cam_hit_c6[41] +
sctag2_ic_cam_hit_c6[42] + sctag2_ic_cam_hit_c6[43];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble11_sum = sctag2_dc_cam_hit_c6[44] + sctag2_dc_cam_hit_c6[45] +
sctag2_dc_cam_hit_c6[46] + sctag2_dc_cam_hit_c6[47];
wire [2:0] sctag2_ic_cam_hit_c6_nibble11_sum = sctag2_ic_cam_hit_c6[44] + sctag2_ic_cam_hit_c6[45] +
sctag2_ic_cam_hit_c6[46] + sctag2_ic_cam_hit_c6[47];
wire [3:0] sctag2_both_cam_hit_c6_nibble11_sum= sctag2_dc_cam_hit_c6[44] + sctag2_dc_cam_hit_c6[45] +
sctag2_dc_cam_hit_c6[46] + sctag2_dc_cam_hit_c6[47] +
sctag2_ic_cam_hit_c6[44] + sctag2_ic_cam_hit_c6[45] +
sctag2_ic_cam_hit_c6[46] + sctag2_ic_cam_hit_c6[47];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble12_sum = sctag2_dc_cam_hit_c6[48] + sctag2_dc_cam_hit_c6[49] +
sctag2_dc_cam_hit_c6[50] + sctag2_dc_cam_hit_c6[51];
wire [2:0] sctag2_ic_cam_hit_c6_nibble12_sum = sctag2_ic_cam_hit_c6[48] + sctag2_ic_cam_hit_c6[49] +
sctag2_ic_cam_hit_c6[50] + sctag2_ic_cam_hit_c6[51];
wire [3:0] sctag2_both_cam_hit_c6_nibble12_sum= sctag2_dc_cam_hit_c6[48] + sctag2_dc_cam_hit_c6[49] +
sctag2_dc_cam_hit_c6[50] + sctag2_dc_cam_hit_c6[51] +
sctag2_ic_cam_hit_c6[48] + sctag2_ic_cam_hit_c6[49] +
sctag2_ic_cam_hit_c6[50] + sctag2_ic_cam_hit_c6[51];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble13_sum = sctag2_dc_cam_hit_c6[52] + sctag2_dc_cam_hit_c6[53] +
sctag2_dc_cam_hit_c6[54] + sctag2_dc_cam_hit_c6[55];
wire [2:0] sctag2_ic_cam_hit_c6_nibble13_sum = sctag2_ic_cam_hit_c6[52] + sctag2_ic_cam_hit_c6[53] +
sctag2_ic_cam_hit_c6[54] + sctag2_ic_cam_hit_c6[55];
wire [3:0] sctag2_both_cam_hit_c6_nibble13_sum= sctag2_dc_cam_hit_c6[52] + sctag2_dc_cam_hit_c6[53] +
sctag2_dc_cam_hit_c6[54] + sctag2_dc_cam_hit_c6[55] +
sctag2_ic_cam_hit_c6[52] + sctag2_ic_cam_hit_c6[53] +
sctag2_ic_cam_hit_c6[54] + sctag2_ic_cam_hit_c6[55];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble14_sum = sctag2_dc_cam_hit_c6[56] + sctag2_dc_cam_hit_c6[57] +
sctag2_dc_cam_hit_c6[58] + sctag2_dc_cam_hit_c6[59];
wire [2:0] sctag2_ic_cam_hit_c6_nibble14_sum = sctag2_ic_cam_hit_c6[56] + sctag2_ic_cam_hit_c6[57] +
sctag2_ic_cam_hit_c6[58] + sctag2_ic_cam_hit_c6[59];
wire [3:0] sctag2_both_cam_hit_c6_nibble14_sum= sctag2_dc_cam_hit_c6[56] + sctag2_dc_cam_hit_c6[57] +
sctag2_dc_cam_hit_c6[58] + sctag2_dc_cam_hit_c6[59] +
sctag2_ic_cam_hit_c6[56] + sctag2_ic_cam_hit_c6[57] +
sctag2_ic_cam_hit_c6[58] + sctag2_ic_cam_hit_c6[59];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble15_sum = sctag2_dc_cam_hit_c6[60] + sctag2_dc_cam_hit_c6[61] +
sctag2_dc_cam_hit_c6[62] + sctag2_dc_cam_hit_c6[63];
wire [2:0] sctag2_ic_cam_hit_c6_nibble15_sum = sctag2_ic_cam_hit_c6[60] + sctag2_ic_cam_hit_c6[61] +
sctag2_ic_cam_hit_c6[62] + sctag2_ic_cam_hit_c6[63];
wire [3:0] sctag2_both_cam_hit_c6_nibble15_sum= sctag2_dc_cam_hit_c6[60] + sctag2_dc_cam_hit_c6[61] +
sctag2_dc_cam_hit_c6[62] + sctag2_dc_cam_hit_c6[63] +
sctag2_ic_cam_hit_c6[60] + sctag2_ic_cam_hit_c6[61] +
sctag2_ic_cam_hit_c6[62] + sctag2_ic_cam_hit_c6[63];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble16_sum = sctag2_dc_cam_hit_c6[64] + sctag2_dc_cam_hit_c6[65] +
sctag2_dc_cam_hit_c6[66] + sctag2_dc_cam_hit_c6[67];
wire [2:0] sctag2_ic_cam_hit_c6_nibble16_sum = sctag2_ic_cam_hit_c6[64] + sctag2_ic_cam_hit_c6[65] +
sctag2_ic_cam_hit_c6[66] + sctag2_ic_cam_hit_c6[67];
wire [3:0] sctag2_both_cam_hit_c6_nibble16_sum= sctag2_dc_cam_hit_c6[64] + sctag2_dc_cam_hit_c6[65] +
sctag2_dc_cam_hit_c6[66] + sctag2_dc_cam_hit_c6[67] +
sctag2_ic_cam_hit_c6[64] + sctag2_ic_cam_hit_c6[65] +
sctag2_ic_cam_hit_c6[66] + sctag2_ic_cam_hit_c6[67];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble17_sum = sctag2_dc_cam_hit_c6[68] + sctag2_dc_cam_hit_c6[69] +
sctag2_dc_cam_hit_c6[70] + sctag2_dc_cam_hit_c6[71];
wire [2:0] sctag2_ic_cam_hit_c6_nibble17_sum = sctag2_ic_cam_hit_c6[68] + sctag2_ic_cam_hit_c6[69] +
sctag2_ic_cam_hit_c6[70] + sctag2_ic_cam_hit_c6[71];
wire [3:0] sctag2_both_cam_hit_c6_nibble17_sum= sctag2_dc_cam_hit_c6[68] + sctag2_dc_cam_hit_c6[69] +
sctag2_dc_cam_hit_c6[70] + sctag2_dc_cam_hit_c6[71] +
sctag2_ic_cam_hit_c6[68] + sctag2_ic_cam_hit_c6[69] +
sctag2_ic_cam_hit_c6[70] + sctag2_ic_cam_hit_c6[71];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble18_sum = sctag2_dc_cam_hit_c6[72] + sctag2_dc_cam_hit_c6[73] +
sctag2_dc_cam_hit_c6[74] + sctag2_dc_cam_hit_c6[75];
wire [2:0] sctag2_ic_cam_hit_c6_nibble18_sum = sctag2_ic_cam_hit_c6[72] + sctag2_ic_cam_hit_c6[73] +
sctag2_ic_cam_hit_c6[74] + sctag2_ic_cam_hit_c6[75];
wire [3:0] sctag2_both_cam_hit_c6_nibble18_sum= sctag2_dc_cam_hit_c6[72] + sctag2_dc_cam_hit_c6[73] +
sctag2_dc_cam_hit_c6[74] + sctag2_dc_cam_hit_c6[75] +
sctag2_ic_cam_hit_c6[72] + sctag2_ic_cam_hit_c6[73] +
sctag2_ic_cam_hit_c6[74] + sctag2_ic_cam_hit_c6[75];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble19_sum = sctag2_dc_cam_hit_c6[76] + sctag2_dc_cam_hit_c6[77] +
sctag2_dc_cam_hit_c6[78] + sctag2_dc_cam_hit_c6[79];
wire [2:0] sctag2_ic_cam_hit_c6_nibble19_sum = sctag2_ic_cam_hit_c6[76] + sctag2_ic_cam_hit_c6[77] +
sctag2_ic_cam_hit_c6[78] + sctag2_ic_cam_hit_c6[79];
wire [3:0] sctag2_both_cam_hit_c6_nibble19_sum= sctag2_dc_cam_hit_c6[76] + sctag2_dc_cam_hit_c6[77] +
sctag2_dc_cam_hit_c6[78] + sctag2_dc_cam_hit_c6[79] +
sctag2_ic_cam_hit_c6[76] + sctag2_ic_cam_hit_c6[77] +
sctag2_ic_cam_hit_c6[78] + sctag2_ic_cam_hit_c6[79];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble20_sum = sctag2_dc_cam_hit_c6[80] + sctag2_dc_cam_hit_c6[81] +
sctag2_dc_cam_hit_c6[82] + sctag2_dc_cam_hit_c6[83];
wire [2:0] sctag2_ic_cam_hit_c6_nibble20_sum = sctag2_ic_cam_hit_c6[80] + sctag2_ic_cam_hit_c6[81] +
sctag2_ic_cam_hit_c6[82] + sctag2_ic_cam_hit_c6[83];
wire [3:0] sctag2_both_cam_hit_c6_nibble20_sum= sctag2_dc_cam_hit_c6[80] + sctag2_dc_cam_hit_c6[81] +
sctag2_dc_cam_hit_c6[82] + sctag2_dc_cam_hit_c6[83] +
sctag2_ic_cam_hit_c6[80] + sctag2_ic_cam_hit_c6[81] +
sctag2_ic_cam_hit_c6[82] + sctag2_ic_cam_hit_c6[83];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble21_sum = sctag2_dc_cam_hit_c6[84] + sctag2_dc_cam_hit_c6[85] +
sctag2_dc_cam_hit_c6[86] + sctag2_dc_cam_hit_c6[87];
wire [2:0] sctag2_ic_cam_hit_c6_nibble21_sum = sctag2_ic_cam_hit_c6[84] + sctag2_ic_cam_hit_c6[85] +
sctag2_ic_cam_hit_c6[86] + sctag2_ic_cam_hit_c6[87];
wire [3:0] sctag2_both_cam_hit_c6_nibble21_sum= sctag2_dc_cam_hit_c6[84] + sctag2_dc_cam_hit_c6[85] +
sctag2_dc_cam_hit_c6[86] + sctag2_dc_cam_hit_c6[87] +
sctag2_ic_cam_hit_c6[84] + sctag2_ic_cam_hit_c6[85] +
sctag2_ic_cam_hit_c6[86] + sctag2_ic_cam_hit_c6[87];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble22_sum = sctag2_dc_cam_hit_c6[88] + sctag2_dc_cam_hit_c6[89] +
sctag2_dc_cam_hit_c6[90] + sctag2_dc_cam_hit_c6[91];
wire [2:0] sctag2_ic_cam_hit_c6_nibble22_sum = sctag2_ic_cam_hit_c6[88] + sctag2_ic_cam_hit_c6[89] +
sctag2_ic_cam_hit_c6[90] + sctag2_ic_cam_hit_c6[91];
wire [3:0] sctag2_both_cam_hit_c6_nibble22_sum= sctag2_dc_cam_hit_c6[88] + sctag2_dc_cam_hit_c6[89] +
sctag2_dc_cam_hit_c6[90] + sctag2_dc_cam_hit_c6[91] +
sctag2_ic_cam_hit_c6[88] + sctag2_ic_cam_hit_c6[89] +
sctag2_ic_cam_hit_c6[90] + sctag2_ic_cam_hit_c6[91];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble23_sum = sctag2_dc_cam_hit_c6[92] + sctag2_dc_cam_hit_c6[93] +
sctag2_dc_cam_hit_c6[94] + sctag2_dc_cam_hit_c6[95];
wire [2:0] sctag2_ic_cam_hit_c6_nibble23_sum = sctag2_ic_cam_hit_c6[92] + sctag2_ic_cam_hit_c6[93] +
sctag2_ic_cam_hit_c6[94] + sctag2_ic_cam_hit_c6[95];
wire [3:0] sctag2_both_cam_hit_c6_nibble23_sum= sctag2_dc_cam_hit_c6[92] + sctag2_dc_cam_hit_c6[93] +
sctag2_dc_cam_hit_c6[94] + sctag2_dc_cam_hit_c6[95] +
sctag2_ic_cam_hit_c6[92] + sctag2_ic_cam_hit_c6[93] +
sctag2_ic_cam_hit_c6[94] + sctag2_ic_cam_hit_c6[95];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble24_sum = sctag2_dc_cam_hit_c6[96] + sctag2_dc_cam_hit_c6[97] +
sctag2_dc_cam_hit_c6[98] + sctag2_dc_cam_hit_c6[99];
wire [2:0] sctag2_ic_cam_hit_c6_nibble24_sum = sctag2_ic_cam_hit_c6[96] + sctag2_ic_cam_hit_c6[97] +
sctag2_ic_cam_hit_c6[98] + sctag2_ic_cam_hit_c6[99];
wire [3:0] sctag2_both_cam_hit_c6_nibble24_sum= sctag2_dc_cam_hit_c6[96] + sctag2_dc_cam_hit_c6[97] +
sctag2_dc_cam_hit_c6[98] + sctag2_dc_cam_hit_c6[99] +
sctag2_ic_cam_hit_c6[96] + sctag2_ic_cam_hit_c6[97] +
sctag2_ic_cam_hit_c6[98] + sctag2_ic_cam_hit_c6[99];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble25_sum = sctag2_dc_cam_hit_c6[100] + sctag2_dc_cam_hit_c6[101] +
sctag2_dc_cam_hit_c6[102] + sctag2_dc_cam_hit_c6[103];
wire [2:0] sctag2_ic_cam_hit_c6_nibble25_sum = sctag2_ic_cam_hit_c6[100] + sctag2_ic_cam_hit_c6[101] +
sctag2_ic_cam_hit_c6[102] + sctag2_ic_cam_hit_c6[103];
wire [3:0] sctag2_both_cam_hit_c6_nibble25_sum= sctag2_dc_cam_hit_c6[100] + sctag2_dc_cam_hit_c6[101] +
sctag2_dc_cam_hit_c6[102] + sctag2_dc_cam_hit_c6[103] +
sctag2_ic_cam_hit_c6[100] + sctag2_ic_cam_hit_c6[101] +
sctag2_ic_cam_hit_c6[102] + sctag2_ic_cam_hit_c6[103];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble26_sum = sctag2_dc_cam_hit_c6[104] + sctag2_dc_cam_hit_c6[105] +
sctag2_dc_cam_hit_c6[106] + sctag2_dc_cam_hit_c6[107];
wire [2:0] sctag2_ic_cam_hit_c6_nibble26_sum = sctag2_ic_cam_hit_c6[104] + sctag2_ic_cam_hit_c6[105] +
sctag2_ic_cam_hit_c6[106] + sctag2_ic_cam_hit_c6[107];
wire [3:0] sctag2_both_cam_hit_c6_nibble26_sum= sctag2_dc_cam_hit_c6[104] + sctag2_dc_cam_hit_c6[105] +
sctag2_dc_cam_hit_c6[106] + sctag2_dc_cam_hit_c6[107] +
sctag2_ic_cam_hit_c6[104] + sctag2_ic_cam_hit_c6[105] +
sctag2_ic_cam_hit_c6[106] + sctag2_ic_cam_hit_c6[107];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble27_sum = sctag2_dc_cam_hit_c6[108] + sctag2_dc_cam_hit_c6[109] +
sctag2_dc_cam_hit_c6[110] + sctag2_dc_cam_hit_c6[111];
wire [2:0] sctag2_ic_cam_hit_c6_nibble27_sum = sctag2_ic_cam_hit_c6[108] + sctag2_ic_cam_hit_c6[109] +
sctag2_ic_cam_hit_c6[110] + sctag2_ic_cam_hit_c6[111];
wire [3:0] sctag2_both_cam_hit_c6_nibble27_sum= sctag2_dc_cam_hit_c6[108] + sctag2_dc_cam_hit_c6[109] +
sctag2_dc_cam_hit_c6[110] + sctag2_dc_cam_hit_c6[111] +
sctag2_ic_cam_hit_c6[108] + sctag2_ic_cam_hit_c6[109] +
sctag2_ic_cam_hit_c6[110] + sctag2_ic_cam_hit_c6[111];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble28_sum = sctag2_dc_cam_hit_c6[112] + sctag2_dc_cam_hit_c6[113] +
sctag2_dc_cam_hit_c6[114] + sctag2_dc_cam_hit_c6[115];
wire [2:0] sctag2_ic_cam_hit_c6_nibble28_sum = sctag2_ic_cam_hit_c6[112] + sctag2_ic_cam_hit_c6[113] +
sctag2_ic_cam_hit_c6[114] + sctag2_ic_cam_hit_c6[115];
wire [3:0] sctag2_both_cam_hit_c6_nibble28_sum= sctag2_dc_cam_hit_c6[112] + sctag2_dc_cam_hit_c6[113] +
sctag2_dc_cam_hit_c6[114] + sctag2_dc_cam_hit_c6[115] +
sctag2_ic_cam_hit_c6[112] + sctag2_ic_cam_hit_c6[113] +
sctag2_ic_cam_hit_c6[114] + sctag2_ic_cam_hit_c6[115];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble29_sum = sctag2_dc_cam_hit_c6[116] + sctag2_dc_cam_hit_c6[117] +
sctag2_dc_cam_hit_c6[118] + sctag2_dc_cam_hit_c6[119];
wire [2:0] sctag2_ic_cam_hit_c6_nibble29_sum = sctag2_ic_cam_hit_c6[116] + sctag2_ic_cam_hit_c6[117] +
sctag2_ic_cam_hit_c6[118] + sctag2_ic_cam_hit_c6[119];
wire [3:0] sctag2_both_cam_hit_c6_nibble29_sum= sctag2_dc_cam_hit_c6[116] + sctag2_dc_cam_hit_c6[117] +
sctag2_dc_cam_hit_c6[118] + sctag2_dc_cam_hit_c6[119] +
sctag2_ic_cam_hit_c6[116] + sctag2_ic_cam_hit_c6[117] +
sctag2_ic_cam_hit_c6[118] + sctag2_ic_cam_hit_c6[119];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble30_sum = sctag2_dc_cam_hit_c6[120] + sctag2_dc_cam_hit_c6[121] +
sctag2_dc_cam_hit_c6[122] + sctag2_dc_cam_hit_c6[123];
wire [2:0] sctag2_ic_cam_hit_c6_nibble30_sum = sctag2_ic_cam_hit_c6[120] + sctag2_ic_cam_hit_c6[121] +
sctag2_ic_cam_hit_c6[122] + sctag2_ic_cam_hit_c6[123];
wire [3:0] sctag2_both_cam_hit_c6_nibble30_sum= sctag2_dc_cam_hit_c6[120] + sctag2_dc_cam_hit_c6[121] +
sctag2_dc_cam_hit_c6[122] + sctag2_dc_cam_hit_c6[123] +
sctag2_ic_cam_hit_c6[120] + sctag2_ic_cam_hit_c6[121] +
sctag2_ic_cam_hit_c6[122] + sctag2_ic_cam_hit_c6[123];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble31_sum = sctag2_dc_cam_hit_c6[124] + sctag2_dc_cam_hit_c6[125] +
sctag2_dc_cam_hit_c6[126] + sctag2_dc_cam_hit_c6[127];
wire [2:0] sctag2_ic_cam_hit_c6_nibble31_sum = sctag2_ic_cam_hit_c6[124] + sctag2_ic_cam_hit_c6[125] +
sctag2_ic_cam_hit_c6[126] + sctag2_ic_cam_hit_c6[127];
wire [3:0] sctag2_both_cam_hit_c6_nibble31_sum= sctag2_dc_cam_hit_c6[124] + sctag2_dc_cam_hit_c6[125] +
sctag2_dc_cam_hit_c6[126] + sctag2_dc_cam_hit_c6[127] +
sctag2_ic_cam_hit_c6[124] + sctag2_ic_cam_hit_c6[125] +
sctag2_ic_cam_hit_c6[126] + sctag2_ic_cam_hit_c6[127];
wire [7:0] sctag3_cpx_req_cq = `TOP_MEMORY.sctag3_cpx_req_cq[7:0];
wire [7:0] sctag3_cpx_atom_cq = `TOP_MEMORY.sctag3_cpx_atom_cq;
wire [`CPX_WIDTH-1:0] sctag3_cpx_data_ca = `TOP_MEMORY.sctag3_cpx_data_ca[`CPX_WIDTH-1:0];
wire sctag3_pcx_stall_pq = `TOP_MEMORY.sctag3_pcx_stall_pq;
reg [7:0] sctag3_cpx_req_cq_d1; // delayed by 1
reg [7:0] sctag3_cpx_req_cq_d2; // delayed by 2
reg [7:0] sctag3_cpx_atom_cq_d1; // delayed by 1
reg [7:0] sctag3_cpx_atom_cq_d2; // delayed by 2
reg [127:0] sctag3_cpx_type_str; // in string format
reg [3:0] sctag3_cpx_type; // packet type
reg sctag3_dc_lkup_c5;
reg sctag3_ic_lkup_c5;
reg sctag3_dc_lkup_c6;
reg sctag3_ic_lkup_c6;
wire [3:0] sctag3_dc_lkup_panel_dec_c4 = `TOP_MEMORY.sctag3.dirrep.dc_lkup_panel_dec_c4[3:0];
wire [3:0] sctag3_dc_lkup_row_dec_c4 = `TOP_MEMORY.sctag3.dirrep.dc_lkup_row_dec_c4[3:0];
wire [3:0] sctag3_ic_lkup_panel_dec_c4 = `TOP_MEMORY.sctag3.dirrep.ic_lkup_panel_dec_c4[3:0];
wire [3:0] sctag3_ic_lkup_row_dec_c4 = `TOP_MEMORY.sctag3.dirrep.ic_lkup_row_dec_c4[3:0];
wire [127:0] sctag3_dc_cam_hit_c6 = `TOP_MEMORY.sctag3.dirvec_dp.dc_cam_hit_c6[127:0];
wire [127:0] sctag3_ic_cam_hit_c6 = `TOP_MEMORY.sctag3.dirvec_dp.ic_cam_hit_c6[127:0];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble0_sum = sctag3_dc_cam_hit_c6[0] + sctag3_dc_cam_hit_c6[1] +
sctag3_dc_cam_hit_c6[2] + sctag3_dc_cam_hit_c6[3];
wire [2:0] sctag3_ic_cam_hit_c6_nibble0_sum = sctag3_ic_cam_hit_c6[0] + sctag3_ic_cam_hit_c6[1] +
sctag3_ic_cam_hit_c6[2] + sctag3_ic_cam_hit_c6[3];
wire [3:0] sctag3_both_cam_hit_c6_nibble0_sum= sctag3_dc_cam_hit_c6[0] + sctag3_dc_cam_hit_c6[1] +
sctag3_dc_cam_hit_c6[2] + sctag3_dc_cam_hit_c6[3] +
sctag3_ic_cam_hit_c6[0] + sctag3_ic_cam_hit_c6[1] +
sctag3_ic_cam_hit_c6[2] + sctag3_ic_cam_hit_c6[3];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble1_sum = sctag3_dc_cam_hit_c6[4] + sctag3_dc_cam_hit_c6[5] +
sctag3_dc_cam_hit_c6[6] + sctag3_dc_cam_hit_c6[7];
wire [2:0] sctag3_ic_cam_hit_c6_nibble1_sum = sctag3_ic_cam_hit_c6[4] + sctag3_ic_cam_hit_c6[5] +
sctag3_ic_cam_hit_c6[6] + sctag3_ic_cam_hit_c6[7];
wire [3:0] sctag3_both_cam_hit_c6_nibble1_sum= sctag3_dc_cam_hit_c6[4] + sctag3_dc_cam_hit_c6[5] +
sctag3_dc_cam_hit_c6[6] + sctag3_dc_cam_hit_c6[7] +
sctag3_ic_cam_hit_c6[4] + sctag3_ic_cam_hit_c6[5] +
sctag3_ic_cam_hit_c6[6] + sctag3_ic_cam_hit_c6[7];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble2_sum = sctag3_dc_cam_hit_c6[8] + sctag3_dc_cam_hit_c6[9] +
sctag3_dc_cam_hit_c6[10] + sctag3_dc_cam_hit_c6[11];
wire [2:0] sctag3_ic_cam_hit_c6_nibble2_sum = sctag3_ic_cam_hit_c6[8] + sctag3_ic_cam_hit_c6[9] +
sctag3_ic_cam_hit_c6[10] + sctag3_ic_cam_hit_c6[11];
wire [3:0] sctag3_both_cam_hit_c6_nibble2_sum= sctag3_dc_cam_hit_c6[8] + sctag3_dc_cam_hit_c6[9] +
sctag3_dc_cam_hit_c6[10] + sctag3_dc_cam_hit_c6[11] +
sctag3_ic_cam_hit_c6[8] + sctag3_ic_cam_hit_c6[9] +
sctag3_ic_cam_hit_c6[10] + sctag3_ic_cam_hit_c6[11];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble3_sum = sctag3_dc_cam_hit_c6[12] + sctag3_dc_cam_hit_c6[13] +
sctag3_dc_cam_hit_c6[14] + sctag3_dc_cam_hit_c6[15];
wire [2:0] sctag3_ic_cam_hit_c6_nibble3_sum = sctag3_ic_cam_hit_c6[12] + sctag3_ic_cam_hit_c6[13] +
sctag3_ic_cam_hit_c6[14] + sctag3_ic_cam_hit_c6[15];
wire [3:0] sctag3_both_cam_hit_c6_nibble3_sum= sctag3_dc_cam_hit_c6[12] + sctag3_dc_cam_hit_c6[13] +
sctag3_dc_cam_hit_c6[14] + sctag3_dc_cam_hit_c6[15] +
sctag3_ic_cam_hit_c6[12] + sctag3_ic_cam_hit_c6[13] +
sctag3_ic_cam_hit_c6[14] + sctag3_ic_cam_hit_c6[15];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble4_sum = sctag3_dc_cam_hit_c6[16] + sctag3_dc_cam_hit_c6[17] +
sctag3_dc_cam_hit_c6[18] + sctag3_dc_cam_hit_c6[19];
wire [2:0] sctag3_ic_cam_hit_c6_nibble4_sum = sctag3_ic_cam_hit_c6[16] + sctag3_ic_cam_hit_c6[17] +
sctag3_ic_cam_hit_c6[18] + sctag3_ic_cam_hit_c6[19];
wire [3:0] sctag3_both_cam_hit_c6_nibble4_sum= sctag3_dc_cam_hit_c6[16] + sctag3_dc_cam_hit_c6[17] +
sctag3_dc_cam_hit_c6[18] + sctag3_dc_cam_hit_c6[19] +
sctag3_ic_cam_hit_c6[16] + sctag3_ic_cam_hit_c6[17] +
sctag3_ic_cam_hit_c6[18] + sctag3_ic_cam_hit_c6[19];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble5_sum = sctag3_dc_cam_hit_c6[20] + sctag3_dc_cam_hit_c6[21] +
sctag3_dc_cam_hit_c6[22] + sctag3_dc_cam_hit_c6[23];
wire [2:0] sctag3_ic_cam_hit_c6_nibble5_sum = sctag3_ic_cam_hit_c6[20] + sctag3_ic_cam_hit_c6[21] +
sctag3_ic_cam_hit_c6[22] + sctag3_ic_cam_hit_c6[23];
wire [3:0] sctag3_both_cam_hit_c6_nibble5_sum= sctag3_dc_cam_hit_c6[20] + sctag3_dc_cam_hit_c6[21] +
sctag3_dc_cam_hit_c6[22] + sctag3_dc_cam_hit_c6[23] +
sctag3_ic_cam_hit_c6[20] + sctag3_ic_cam_hit_c6[21] +
sctag3_ic_cam_hit_c6[22] + sctag3_ic_cam_hit_c6[23];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble6_sum = sctag3_dc_cam_hit_c6[24] + sctag3_dc_cam_hit_c6[25] +
sctag3_dc_cam_hit_c6[26] + sctag3_dc_cam_hit_c6[27];
wire [2:0] sctag3_ic_cam_hit_c6_nibble6_sum = sctag3_ic_cam_hit_c6[24] + sctag3_ic_cam_hit_c6[25] +
sctag3_ic_cam_hit_c6[26] + sctag3_ic_cam_hit_c6[27];
wire [3:0] sctag3_both_cam_hit_c6_nibble6_sum= sctag3_dc_cam_hit_c6[24] + sctag3_dc_cam_hit_c6[25] +
sctag3_dc_cam_hit_c6[26] + sctag3_dc_cam_hit_c6[27] +
sctag3_ic_cam_hit_c6[24] + sctag3_ic_cam_hit_c6[25] +
sctag3_ic_cam_hit_c6[26] + sctag3_ic_cam_hit_c6[27];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble7_sum = sctag3_dc_cam_hit_c6[28] + sctag3_dc_cam_hit_c6[29] +
sctag3_dc_cam_hit_c6[30] + sctag3_dc_cam_hit_c6[31];
wire [2:0] sctag3_ic_cam_hit_c6_nibble7_sum = sctag3_ic_cam_hit_c6[28] + sctag3_ic_cam_hit_c6[29] +
sctag3_ic_cam_hit_c6[30] + sctag3_ic_cam_hit_c6[31];
wire [3:0] sctag3_both_cam_hit_c6_nibble7_sum= sctag3_dc_cam_hit_c6[28] + sctag3_dc_cam_hit_c6[29] +
sctag3_dc_cam_hit_c6[30] + sctag3_dc_cam_hit_c6[31] +
sctag3_ic_cam_hit_c6[28] + sctag3_ic_cam_hit_c6[29] +
sctag3_ic_cam_hit_c6[30] + sctag3_ic_cam_hit_c6[31];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble8_sum = sctag3_dc_cam_hit_c6[32] + sctag3_dc_cam_hit_c6[33] +
sctag3_dc_cam_hit_c6[34] + sctag3_dc_cam_hit_c6[35];
wire [2:0] sctag3_ic_cam_hit_c6_nibble8_sum = sctag3_ic_cam_hit_c6[32] + sctag3_ic_cam_hit_c6[33] +
sctag3_ic_cam_hit_c6[34] + sctag3_ic_cam_hit_c6[35];
wire [3:0] sctag3_both_cam_hit_c6_nibble8_sum= sctag3_dc_cam_hit_c6[32] + sctag3_dc_cam_hit_c6[33] +
sctag3_dc_cam_hit_c6[34] + sctag3_dc_cam_hit_c6[35] +
sctag3_ic_cam_hit_c6[32] + sctag3_ic_cam_hit_c6[33] +
sctag3_ic_cam_hit_c6[34] + sctag3_ic_cam_hit_c6[35];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble9_sum = sctag3_dc_cam_hit_c6[36] + sctag3_dc_cam_hit_c6[37] +
sctag3_dc_cam_hit_c6[38] + sctag3_dc_cam_hit_c6[39];
wire [2:0] sctag3_ic_cam_hit_c6_nibble9_sum = sctag3_ic_cam_hit_c6[36] + sctag3_ic_cam_hit_c6[37] +
sctag3_ic_cam_hit_c6[38] + sctag3_ic_cam_hit_c6[39];
wire [3:0] sctag3_both_cam_hit_c6_nibble9_sum= sctag3_dc_cam_hit_c6[36] + sctag3_dc_cam_hit_c6[37] +
sctag3_dc_cam_hit_c6[38] + sctag3_dc_cam_hit_c6[39] +
sctag3_ic_cam_hit_c6[36] + sctag3_ic_cam_hit_c6[37] +
sctag3_ic_cam_hit_c6[38] + sctag3_ic_cam_hit_c6[39];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble10_sum = sctag3_dc_cam_hit_c6[40] + sctag3_dc_cam_hit_c6[41] +
sctag3_dc_cam_hit_c6[42] + sctag3_dc_cam_hit_c6[43];
wire [2:0] sctag3_ic_cam_hit_c6_nibble10_sum = sctag3_ic_cam_hit_c6[40] + sctag3_ic_cam_hit_c6[41] +
sctag3_ic_cam_hit_c6[42] + sctag3_ic_cam_hit_c6[43];
wire [3:0] sctag3_both_cam_hit_c6_nibble10_sum= sctag3_dc_cam_hit_c6[40] + sctag3_dc_cam_hit_c6[41] +
sctag3_dc_cam_hit_c6[42] + sctag3_dc_cam_hit_c6[43] +
sctag3_ic_cam_hit_c6[40] + sctag3_ic_cam_hit_c6[41] +
sctag3_ic_cam_hit_c6[42] + sctag3_ic_cam_hit_c6[43];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble11_sum = sctag3_dc_cam_hit_c6[44] + sctag3_dc_cam_hit_c6[45] +
sctag3_dc_cam_hit_c6[46] + sctag3_dc_cam_hit_c6[47];
wire [2:0] sctag3_ic_cam_hit_c6_nibble11_sum = sctag3_ic_cam_hit_c6[44] + sctag3_ic_cam_hit_c6[45] +
sctag3_ic_cam_hit_c6[46] + sctag3_ic_cam_hit_c6[47];
wire [3:0] sctag3_both_cam_hit_c6_nibble11_sum= sctag3_dc_cam_hit_c6[44] + sctag3_dc_cam_hit_c6[45] +
sctag3_dc_cam_hit_c6[46] + sctag3_dc_cam_hit_c6[47] +
sctag3_ic_cam_hit_c6[44] + sctag3_ic_cam_hit_c6[45] +
sctag3_ic_cam_hit_c6[46] + sctag3_ic_cam_hit_c6[47];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble12_sum = sctag3_dc_cam_hit_c6[48] + sctag3_dc_cam_hit_c6[49] +
sctag3_dc_cam_hit_c6[50] + sctag3_dc_cam_hit_c6[51];
wire [2:0] sctag3_ic_cam_hit_c6_nibble12_sum = sctag3_ic_cam_hit_c6[48] + sctag3_ic_cam_hit_c6[49] +
sctag3_ic_cam_hit_c6[50] + sctag3_ic_cam_hit_c6[51];
wire [3:0] sctag3_both_cam_hit_c6_nibble12_sum= sctag3_dc_cam_hit_c6[48] + sctag3_dc_cam_hit_c6[49] +
sctag3_dc_cam_hit_c6[50] + sctag3_dc_cam_hit_c6[51] +
sctag3_ic_cam_hit_c6[48] + sctag3_ic_cam_hit_c6[49] +
sctag3_ic_cam_hit_c6[50] + sctag3_ic_cam_hit_c6[51];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble13_sum = sctag3_dc_cam_hit_c6[52] + sctag3_dc_cam_hit_c6[53] +
sctag3_dc_cam_hit_c6[54] + sctag3_dc_cam_hit_c6[55];
wire [2:0] sctag3_ic_cam_hit_c6_nibble13_sum = sctag3_ic_cam_hit_c6[52] + sctag3_ic_cam_hit_c6[53] +
sctag3_ic_cam_hit_c6[54] + sctag3_ic_cam_hit_c6[55];
wire [3:0] sctag3_both_cam_hit_c6_nibble13_sum= sctag3_dc_cam_hit_c6[52] + sctag3_dc_cam_hit_c6[53] +
sctag3_dc_cam_hit_c6[54] + sctag3_dc_cam_hit_c6[55] +
sctag3_ic_cam_hit_c6[52] + sctag3_ic_cam_hit_c6[53] +
sctag3_ic_cam_hit_c6[54] + sctag3_ic_cam_hit_c6[55];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble14_sum = sctag3_dc_cam_hit_c6[56] + sctag3_dc_cam_hit_c6[57] +
sctag3_dc_cam_hit_c6[58] + sctag3_dc_cam_hit_c6[59];
wire [2:0] sctag3_ic_cam_hit_c6_nibble14_sum = sctag3_ic_cam_hit_c6[56] + sctag3_ic_cam_hit_c6[57] +
sctag3_ic_cam_hit_c6[58] + sctag3_ic_cam_hit_c6[59];
wire [3:0] sctag3_both_cam_hit_c6_nibble14_sum= sctag3_dc_cam_hit_c6[56] + sctag3_dc_cam_hit_c6[57] +
sctag3_dc_cam_hit_c6[58] + sctag3_dc_cam_hit_c6[59] +
sctag3_ic_cam_hit_c6[56] + sctag3_ic_cam_hit_c6[57] +
sctag3_ic_cam_hit_c6[58] + sctag3_ic_cam_hit_c6[59];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble15_sum = sctag3_dc_cam_hit_c6[60] + sctag3_dc_cam_hit_c6[61] +
sctag3_dc_cam_hit_c6[62] + sctag3_dc_cam_hit_c6[63];
wire [2:0] sctag3_ic_cam_hit_c6_nibble15_sum = sctag3_ic_cam_hit_c6[60] + sctag3_ic_cam_hit_c6[61] +
sctag3_ic_cam_hit_c6[62] + sctag3_ic_cam_hit_c6[63];
wire [3:0] sctag3_both_cam_hit_c6_nibble15_sum= sctag3_dc_cam_hit_c6[60] + sctag3_dc_cam_hit_c6[61] +
sctag3_dc_cam_hit_c6[62] + sctag3_dc_cam_hit_c6[63] +
sctag3_ic_cam_hit_c6[60] + sctag3_ic_cam_hit_c6[61] +
sctag3_ic_cam_hit_c6[62] + sctag3_ic_cam_hit_c6[63];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble16_sum = sctag3_dc_cam_hit_c6[64] + sctag3_dc_cam_hit_c6[65] +
sctag3_dc_cam_hit_c6[66] + sctag3_dc_cam_hit_c6[67];
wire [2:0] sctag3_ic_cam_hit_c6_nibble16_sum = sctag3_ic_cam_hit_c6[64] + sctag3_ic_cam_hit_c6[65] +
sctag3_ic_cam_hit_c6[66] + sctag3_ic_cam_hit_c6[67];
wire [3:0] sctag3_both_cam_hit_c6_nibble16_sum= sctag3_dc_cam_hit_c6[64] + sctag3_dc_cam_hit_c6[65] +
sctag3_dc_cam_hit_c6[66] + sctag3_dc_cam_hit_c6[67] +
sctag3_ic_cam_hit_c6[64] + sctag3_ic_cam_hit_c6[65] +
sctag3_ic_cam_hit_c6[66] + sctag3_ic_cam_hit_c6[67];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble17_sum = sctag3_dc_cam_hit_c6[68] + sctag3_dc_cam_hit_c6[69] +
sctag3_dc_cam_hit_c6[70] + sctag3_dc_cam_hit_c6[71];
wire [2:0] sctag3_ic_cam_hit_c6_nibble17_sum = sctag3_ic_cam_hit_c6[68] + sctag3_ic_cam_hit_c6[69] +
sctag3_ic_cam_hit_c6[70] + sctag3_ic_cam_hit_c6[71];
wire [3:0] sctag3_both_cam_hit_c6_nibble17_sum= sctag3_dc_cam_hit_c6[68] + sctag3_dc_cam_hit_c6[69] +
sctag3_dc_cam_hit_c6[70] + sctag3_dc_cam_hit_c6[71] +
sctag3_ic_cam_hit_c6[68] + sctag3_ic_cam_hit_c6[69] +
sctag3_ic_cam_hit_c6[70] + sctag3_ic_cam_hit_c6[71];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble18_sum = sctag3_dc_cam_hit_c6[72] + sctag3_dc_cam_hit_c6[73] +
sctag3_dc_cam_hit_c6[74] + sctag3_dc_cam_hit_c6[75];
wire [2:0] sctag3_ic_cam_hit_c6_nibble18_sum = sctag3_ic_cam_hit_c6[72] + sctag3_ic_cam_hit_c6[73] +
sctag3_ic_cam_hit_c6[74] + sctag3_ic_cam_hit_c6[75];
wire [3:0] sctag3_both_cam_hit_c6_nibble18_sum= sctag3_dc_cam_hit_c6[72] + sctag3_dc_cam_hit_c6[73] +
sctag3_dc_cam_hit_c6[74] + sctag3_dc_cam_hit_c6[75] +
sctag3_ic_cam_hit_c6[72] + sctag3_ic_cam_hit_c6[73] +
sctag3_ic_cam_hit_c6[74] + sctag3_ic_cam_hit_c6[75];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble19_sum = sctag3_dc_cam_hit_c6[76] + sctag3_dc_cam_hit_c6[77] +
sctag3_dc_cam_hit_c6[78] + sctag3_dc_cam_hit_c6[79];
wire [2:0] sctag3_ic_cam_hit_c6_nibble19_sum = sctag3_ic_cam_hit_c6[76] + sctag3_ic_cam_hit_c6[77] +
sctag3_ic_cam_hit_c6[78] + sctag3_ic_cam_hit_c6[79];
wire [3:0] sctag3_both_cam_hit_c6_nibble19_sum= sctag3_dc_cam_hit_c6[76] + sctag3_dc_cam_hit_c6[77] +
sctag3_dc_cam_hit_c6[78] + sctag3_dc_cam_hit_c6[79] +
sctag3_ic_cam_hit_c6[76] + sctag3_ic_cam_hit_c6[77] +
sctag3_ic_cam_hit_c6[78] + sctag3_ic_cam_hit_c6[79];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble20_sum = sctag3_dc_cam_hit_c6[80] + sctag3_dc_cam_hit_c6[81] +
sctag3_dc_cam_hit_c6[82] + sctag3_dc_cam_hit_c6[83];
wire [2:0] sctag3_ic_cam_hit_c6_nibble20_sum = sctag3_ic_cam_hit_c6[80] + sctag3_ic_cam_hit_c6[81] +
sctag3_ic_cam_hit_c6[82] + sctag3_ic_cam_hit_c6[83];
wire [3:0] sctag3_both_cam_hit_c6_nibble20_sum= sctag3_dc_cam_hit_c6[80] + sctag3_dc_cam_hit_c6[81] +
sctag3_dc_cam_hit_c6[82] + sctag3_dc_cam_hit_c6[83] +
sctag3_ic_cam_hit_c6[80] + sctag3_ic_cam_hit_c6[81] +
sctag3_ic_cam_hit_c6[82] + sctag3_ic_cam_hit_c6[83];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble21_sum = sctag3_dc_cam_hit_c6[84] + sctag3_dc_cam_hit_c6[85] +
sctag3_dc_cam_hit_c6[86] + sctag3_dc_cam_hit_c6[87];
wire [2:0] sctag3_ic_cam_hit_c6_nibble21_sum = sctag3_ic_cam_hit_c6[84] + sctag3_ic_cam_hit_c6[85] +
sctag3_ic_cam_hit_c6[86] + sctag3_ic_cam_hit_c6[87];
wire [3:0] sctag3_both_cam_hit_c6_nibble21_sum= sctag3_dc_cam_hit_c6[84] + sctag3_dc_cam_hit_c6[85] +
sctag3_dc_cam_hit_c6[86] + sctag3_dc_cam_hit_c6[87] +
sctag3_ic_cam_hit_c6[84] + sctag3_ic_cam_hit_c6[85] +
sctag3_ic_cam_hit_c6[86] + sctag3_ic_cam_hit_c6[87];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble22_sum = sctag3_dc_cam_hit_c6[88] + sctag3_dc_cam_hit_c6[89] +
sctag3_dc_cam_hit_c6[90] + sctag3_dc_cam_hit_c6[91];
wire [2:0] sctag3_ic_cam_hit_c6_nibble22_sum = sctag3_ic_cam_hit_c6[88] + sctag3_ic_cam_hit_c6[89] +
sctag3_ic_cam_hit_c6[90] + sctag3_ic_cam_hit_c6[91];
wire [3:0] sctag3_both_cam_hit_c6_nibble22_sum= sctag3_dc_cam_hit_c6[88] + sctag3_dc_cam_hit_c6[89] +
sctag3_dc_cam_hit_c6[90] + sctag3_dc_cam_hit_c6[91] +
sctag3_ic_cam_hit_c6[88] + sctag3_ic_cam_hit_c6[89] +
sctag3_ic_cam_hit_c6[90] + sctag3_ic_cam_hit_c6[91];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble23_sum = sctag3_dc_cam_hit_c6[92] + sctag3_dc_cam_hit_c6[93] +
sctag3_dc_cam_hit_c6[94] + sctag3_dc_cam_hit_c6[95];
wire [2:0] sctag3_ic_cam_hit_c6_nibble23_sum = sctag3_ic_cam_hit_c6[92] + sctag3_ic_cam_hit_c6[93] +
sctag3_ic_cam_hit_c6[94] + sctag3_ic_cam_hit_c6[95];
wire [3:0] sctag3_both_cam_hit_c6_nibble23_sum= sctag3_dc_cam_hit_c6[92] + sctag3_dc_cam_hit_c6[93] +
sctag3_dc_cam_hit_c6[94] + sctag3_dc_cam_hit_c6[95] +
sctag3_ic_cam_hit_c6[92] + sctag3_ic_cam_hit_c6[93] +
sctag3_ic_cam_hit_c6[94] + sctag3_ic_cam_hit_c6[95];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble24_sum = sctag3_dc_cam_hit_c6[96] + sctag3_dc_cam_hit_c6[97] +
sctag3_dc_cam_hit_c6[98] + sctag3_dc_cam_hit_c6[99];
wire [2:0] sctag3_ic_cam_hit_c6_nibble24_sum = sctag3_ic_cam_hit_c6[96] + sctag3_ic_cam_hit_c6[97] +
sctag3_ic_cam_hit_c6[98] + sctag3_ic_cam_hit_c6[99];
wire [3:0] sctag3_both_cam_hit_c6_nibble24_sum= sctag3_dc_cam_hit_c6[96] + sctag3_dc_cam_hit_c6[97] +
sctag3_dc_cam_hit_c6[98] + sctag3_dc_cam_hit_c6[99] +
sctag3_ic_cam_hit_c6[96] + sctag3_ic_cam_hit_c6[97] +
sctag3_ic_cam_hit_c6[98] + sctag3_ic_cam_hit_c6[99];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble25_sum = sctag3_dc_cam_hit_c6[100] + sctag3_dc_cam_hit_c6[101] +
sctag3_dc_cam_hit_c6[102] + sctag3_dc_cam_hit_c6[103];
wire [2:0] sctag3_ic_cam_hit_c6_nibble25_sum = sctag3_ic_cam_hit_c6[100] + sctag3_ic_cam_hit_c6[101] +
sctag3_ic_cam_hit_c6[102] + sctag3_ic_cam_hit_c6[103];
wire [3:0] sctag3_both_cam_hit_c6_nibble25_sum= sctag3_dc_cam_hit_c6[100] + sctag3_dc_cam_hit_c6[101] +
sctag3_dc_cam_hit_c6[102] + sctag3_dc_cam_hit_c6[103] +
sctag3_ic_cam_hit_c6[100] + sctag3_ic_cam_hit_c6[101] +
sctag3_ic_cam_hit_c6[102] + sctag3_ic_cam_hit_c6[103];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble26_sum = sctag3_dc_cam_hit_c6[104] + sctag3_dc_cam_hit_c6[105] +
sctag3_dc_cam_hit_c6[106] + sctag3_dc_cam_hit_c6[107];
wire [2:0] sctag3_ic_cam_hit_c6_nibble26_sum = sctag3_ic_cam_hit_c6[104] + sctag3_ic_cam_hit_c6[105] +
sctag3_ic_cam_hit_c6[106] + sctag3_ic_cam_hit_c6[107];
wire [3:0] sctag3_both_cam_hit_c6_nibble26_sum= sctag3_dc_cam_hit_c6[104] + sctag3_dc_cam_hit_c6[105] +
sctag3_dc_cam_hit_c6[106] + sctag3_dc_cam_hit_c6[107] +
sctag3_ic_cam_hit_c6[104] + sctag3_ic_cam_hit_c6[105] +
sctag3_ic_cam_hit_c6[106] + sctag3_ic_cam_hit_c6[107];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble27_sum = sctag3_dc_cam_hit_c6[108] + sctag3_dc_cam_hit_c6[109] +
sctag3_dc_cam_hit_c6[110] + sctag3_dc_cam_hit_c6[111];
wire [2:0] sctag3_ic_cam_hit_c6_nibble27_sum = sctag3_ic_cam_hit_c6[108] + sctag3_ic_cam_hit_c6[109] +
sctag3_ic_cam_hit_c6[110] + sctag3_ic_cam_hit_c6[111];
wire [3:0] sctag3_both_cam_hit_c6_nibble27_sum= sctag3_dc_cam_hit_c6[108] + sctag3_dc_cam_hit_c6[109] +
sctag3_dc_cam_hit_c6[110] + sctag3_dc_cam_hit_c6[111] +
sctag3_ic_cam_hit_c6[108] + sctag3_ic_cam_hit_c6[109] +
sctag3_ic_cam_hit_c6[110] + sctag3_ic_cam_hit_c6[111];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble28_sum = sctag3_dc_cam_hit_c6[112] + sctag3_dc_cam_hit_c6[113] +
sctag3_dc_cam_hit_c6[114] + sctag3_dc_cam_hit_c6[115];
wire [2:0] sctag3_ic_cam_hit_c6_nibble28_sum = sctag3_ic_cam_hit_c6[112] + sctag3_ic_cam_hit_c6[113] +
sctag3_ic_cam_hit_c6[114] + sctag3_ic_cam_hit_c6[115];
wire [3:0] sctag3_both_cam_hit_c6_nibble28_sum= sctag3_dc_cam_hit_c6[112] + sctag3_dc_cam_hit_c6[113] +
sctag3_dc_cam_hit_c6[114] + sctag3_dc_cam_hit_c6[115] +
sctag3_ic_cam_hit_c6[112] + sctag3_ic_cam_hit_c6[113] +
sctag3_ic_cam_hit_c6[114] + sctag3_ic_cam_hit_c6[115];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble29_sum = sctag3_dc_cam_hit_c6[116] + sctag3_dc_cam_hit_c6[117] +
sctag3_dc_cam_hit_c6[118] + sctag3_dc_cam_hit_c6[119];
wire [2:0] sctag3_ic_cam_hit_c6_nibble29_sum = sctag3_ic_cam_hit_c6[116] + sctag3_ic_cam_hit_c6[117] +
sctag3_ic_cam_hit_c6[118] + sctag3_ic_cam_hit_c6[119];
wire [3:0] sctag3_both_cam_hit_c6_nibble29_sum= sctag3_dc_cam_hit_c6[116] + sctag3_dc_cam_hit_c6[117] +
sctag3_dc_cam_hit_c6[118] + sctag3_dc_cam_hit_c6[119] +
sctag3_ic_cam_hit_c6[116] + sctag3_ic_cam_hit_c6[117] +
sctag3_ic_cam_hit_c6[118] + sctag3_ic_cam_hit_c6[119];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble30_sum = sctag3_dc_cam_hit_c6[120] + sctag3_dc_cam_hit_c6[121] +
sctag3_dc_cam_hit_c6[122] + sctag3_dc_cam_hit_c6[123];
wire [2:0] sctag3_ic_cam_hit_c6_nibble30_sum = sctag3_ic_cam_hit_c6[120] + sctag3_ic_cam_hit_c6[121] +
sctag3_ic_cam_hit_c6[122] + sctag3_ic_cam_hit_c6[123];
wire [3:0] sctag3_both_cam_hit_c6_nibble30_sum= sctag3_dc_cam_hit_c6[120] + sctag3_dc_cam_hit_c6[121] +
sctag3_dc_cam_hit_c6[122] + sctag3_dc_cam_hit_c6[123] +
sctag3_ic_cam_hit_c6[120] + sctag3_ic_cam_hit_c6[121] +
sctag3_ic_cam_hit_c6[122] + sctag3_ic_cam_hit_c6[123];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble31_sum = sctag3_dc_cam_hit_c6[124] + sctag3_dc_cam_hit_c6[125] +
sctag3_dc_cam_hit_c6[126] + sctag3_dc_cam_hit_c6[127];
wire [2:0] sctag3_ic_cam_hit_c6_nibble31_sum = sctag3_ic_cam_hit_c6[124] + sctag3_ic_cam_hit_c6[125] +
sctag3_ic_cam_hit_c6[126] + sctag3_ic_cam_hit_c6[127];
wire [3:0] sctag3_both_cam_hit_c6_nibble31_sum= sctag3_dc_cam_hit_c6[124] + sctag3_dc_cam_hit_c6[125] +
sctag3_dc_cam_hit_c6[126] + sctag3_dc_cam_hit_c6[127] +
sctag3_ic_cam_hit_c6[124] + sctag3_ic_cam_hit_c6[125] +
sctag3_ic_cam_hit_c6[126] + sctag3_ic_cam_hit_c6[127];
// This one is an OR of all 4 SCTAGS
//----------------------------------
wire sctag_pcx_stall_pq = sctag0_pcx_stall_pq | sctag1_pcx_stall_pq | sctag2_pcx_stall_pq | sctag3_pcx_stall_pq;
//--------------------------------------------------------------------------------------
// cpx to spc (sparc) packets
//--------------------------------------------------------------------------------------
wire cpx_spc0_data_vld = `TOP_MEMORY.cpx_spc0_data_cx2[`CPX_WIDTH-1];
wire [`CPX_WIDTH-1:0] cpx_spc0_data_cx2 = `TOP_MEMORY.cpx_spc0_data_cx2[`CPX_WIDTH-1:0];
reg [`CPX_WIDTH-1:0] cpx_spc0_data_cx2_d1; // packet delayed by 1
reg [`CPX_WIDTH-1:0] cpx_spc0_data_cx2_d2; // packet delayed by 2
reg [127:0] spc0_pcx_type_str; // packet type in string format for debug.
reg [127:0] cpx_spc0_type_str; // in string format for debug
wire [3:0] cpx_spc0_type = cpx_spc0_data_vld ? cpx_spc0_data_cx2[`CPX_RQ_HI:`CPX_RQ_LO] :4'h0;
wire cpx_spc0_wyvld = cpx_spc0_data_cx2[`CPX_WYVLD] & cpx_spc0_data_vld;
wire cpx_spc0_st_ack = (cpx_spc0_type == `ST_ACK) | (cpx_spc0_type == `STRST_ACK);
wire cpx_spc0_evict = (cpx_spc0_type == `EVICT_REQ);
reg cpx_spc0_ifill_wyvld;
reg cpx_spc0_dfill_wyvld;
wire cpx_spc0_st_ack_dc_inval_1c_tmp = (cpx_spc0_data_cx2[122:121] == 2'b00) ? cpx_spc0_data_cx2[0] :
(cpx_spc0_data_cx2[122:121] == 2'b01) ? cpx_spc0_data_cx2[32] :
(cpx_spc0_data_cx2[122:121] == 2'b10) ? cpx_spc0_data_cx2[56] :
cpx_spc0_data_cx2[88];
wire [2:0] cpx_spc0_st_ack_dc_inval_1c = {2'b00, cpx_spc0_st_ack & cpx_spc0_st_ack_dc_inval_1c_tmp};
wire cpx_spc0_st_ack_ic_inval_1c_tmp = cpx_spc0_data_cx2[122] ? cpx_spc0_data_cx2[57] : cpx_spc0_data_cx2[1];
wire [2:0] cpx_spc0_st_ack_ic_inval_1c = {2'b00, (cpx_spc0_st_ack & cpx_spc0_st_ack_ic_inval_1c_tmp)};
wire [5:0] cpx_spc0_st_ack_icdc_inval_1c = {6{cpx_spc0_st_ack}} &
{cpx_spc0_st_ack_ic_inval_1c, cpx_spc0_st_ack_dc_inval_1c};
wire [2:0] cpx_spc0_evict_dc_inval_1c = cpx_spc0_data_cx2[0] + cpx_spc0_data_cx2[32] +
cpx_spc0_data_cx2[56] + cpx_spc0_data_cx2[88];
wire [1:0] cpx_spc0_evict_ic_inval_1c = cpx_spc0_data_cx2[1] + cpx_spc0_data_cx2[57];
reg cpx_spc0_evict_d1;
always @(posedge clk)
cpx_spc0_evict_d1 <= cpx_spc0_evict;
wire cpx_spc0_b2b_evict = cpx_spc0_evict_d1 & cpx_spc0_evict;
wire [5:0] cpx_spc0_evict_icdc_inval_1c;
assign cpx_spc0_evict_icdc_inval_1c[4:0]={5{cpx_spc0_evict}} &
{cpx_spc0_evict_ic_inval_1c,cpx_spc0_evict_dc_inval_1c};
assign cpx_spc0_evict_icdc_inval_1c[5] = cpx_spc0_b2b_evict;
wire [5:0] cpx_spc0_st_ack_dc_inval_8c_tmp = (cpx_spc0_data_cx2[122:121] == 2'b00) ? (
cpx_spc0_data_cx2[0] + cpx_spc0_data_cx2[4] +
cpx_spc0_data_cx2[8] + cpx_spc0_data_cx2[12] +
cpx_spc0_data_cx2[16] + cpx_spc0_data_cx2[20] +
cpx_spc0_data_cx2[24] + cpx_spc0_data_cx2[28]
) :
(cpx_spc0_data_cx2[122:121] == 2'b01) ? (
cpx_spc0_data_cx2[32] + cpx_spc0_data_cx2[35] +
cpx_spc0_data_cx2[38] + cpx_spc0_data_cx2[41] +
cpx_spc0_data_cx2[44] + cpx_spc0_data_cx2[47] +
cpx_spc0_data_cx2[50] + cpx_spc0_data_cx2[53]
) :
(cpx_spc0_data_cx2[122:121] == 2'b10) ? (
cpx_spc0_data_cx2[56] + cpx_spc0_data_cx2[60] +
cpx_spc0_data_cx2[64] + cpx_spc0_data_cx2[68] +
cpx_spc0_data_cx2[72] + cpx_spc0_data_cx2[76] +
cpx_spc0_data_cx2[80] + cpx_spc0_data_cx2[84]
) :
( cpx_spc0_data_cx2[88] + cpx_spc0_data_cx2[91] +
cpx_spc0_data_cx2[94] + cpx_spc0_data_cx2[97] +
cpx_spc0_data_cx2[100]+ cpx_spc0_data_cx2[103]+
cpx_spc0_data_cx2[106]+ cpx_spc0_data_cx2[109]
) ;
wire [5:0] cpx_spc0_st_ack_dc_inval_8c = {6{cpx_spc0_st_ack}} & cpx_spc0_st_ack_dc_inval_8c_tmp;
wire [5:0] cpx_spc0_st_ack_ic_inval_8c_tmp = ~cpx_spc0_data_cx2[122] ? (
cpx_spc0_data_cx2[1] + cpx_spc0_data_cx2[5] +
cpx_spc0_data_cx2[9] + cpx_spc0_data_cx2[13] +
cpx_spc0_data_cx2[17] + cpx_spc0_data_cx2[21] +
cpx_spc0_data_cx2[25] + cpx_spc0_data_cx2[29]
) :
( cpx_spc0_data_cx2[57] + cpx_spc0_data_cx2[61] +
cpx_spc0_data_cx2[65] + cpx_spc0_data_cx2[69] +
cpx_spc0_data_cx2[73] + cpx_spc0_data_cx2[77] +
cpx_spc0_data_cx2[81] + cpx_spc0_data_cx2[85]
) ;
wire [5:0] cpx_spc0_st_ack_ic_inval_8c = {4{cpx_spc0_st_ack}} & cpx_spc0_st_ack_ic_inval_8c_tmp;
wire [5:0] cpx_spc0_evict_dc_inval_8c_tmp =
cpx_spc0_data_cx2[0] + cpx_spc0_data_cx2[4] +
cpx_spc0_data_cx2[8] + cpx_spc0_data_cx2[12] +
cpx_spc0_data_cx2[16] + cpx_spc0_data_cx2[20] +
cpx_spc0_data_cx2[24] + cpx_spc0_data_cx2[28] +
cpx_spc0_data_cx2[32] + cpx_spc0_data_cx2[35] +
cpx_spc0_data_cx2[38] + cpx_spc0_data_cx2[41] +
cpx_spc0_data_cx2[44] + cpx_spc0_data_cx2[47] +
cpx_spc0_data_cx2[50] + cpx_spc0_data_cx2[53] +
cpx_spc0_data_cx2[56] + cpx_spc0_data_cx2[60] +
cpx_spc0_data_cx2[64] + cpx_spc0_data_cx2[68] +
cpx_spc0_data_cx2[72] + cpx_spc0_data_cx2[76] +
cpx_spc0_data_cx2[80] + cpx_spc0_data_cx2[84] +
cpx_spc0_data_cx2[88] + cpx_spc0_data_cx2[91] +
cpx_spc0_data_cx2[94] + cpx_spc0_data_cx2[97] +
cpx_spc0_data_cx2[100]+ cpx_spc0_data_cx2[103]+
cpx_spc0_data_cx2[106]+ cpx_spc0_data_cx2[109];
wire [5:0] cpx_spc0_evict_dc_inval_8c = {6{cpx_spc0_evict}} & cpx_spc0_evict_dc_inval_8c_tmp;
wire [5:0] cpx_spc0_evict_ic_inval_8c_tmp =
cpx_spc0_data_cx2[1] + cpx_spc0_data_cx2[5] +
cpx_spc0_data_cx2[9] + cpx_spc0_data_cx2[13] +
cpx_spc0_data_cx2[17] + cpx_spc0_data_cx2[21] +
cpx_spc0_data_cx2[25] + cpx_spc0_data_cx2[29] +
cpx_spc0_data_cx2[57] + cpx_spc0_data_cx2[61] +
cpx_spc0_data_cx2[65] + cpx_spc0_data_cx2[69] +
cpx_spc0_data_cx2[73] + cpx_spc0_data_cx2[77] +
cpx_spc0_data_cx2[81] + cpx_spc0_data_cx2[85];
wire [5:0] cpx_spc0_evict_ic_inval_8c = {6{cpx_spc0_evict}} & cpx_spc0_evict_ic_inval_8c_tmp;
reg [3:0] blk_st_cnt0; // counts the number of block stores without an acknowledge in between
reg [3:0] ini_st_cnt0; // counts the number of init stores without an acknowledge in between
reg st_blkst_mixture0; // a flag set upon detection of block store and normal store mixture.
reg st_inist_mixture0; // a flag set upon detection of init store and normal store mixture.
reg atomic_ret0; // atomic cpx to spc package
reg non_b2b_atomic_ret0; // atomic cpx to spc package did not return in back to back cycles
wire cpx_spc1_data_vld = `TOP_MEMORY.cpx_spc1_data_cx2[`CPX_WIDTH-1];
wire [`CPX_WIDTH-1:0] cpx_spc1_data_cx2 = `TOP_MEMORY.cpx_spc1_data_cx2[`CPX_WIDTH-1:0];
reg [`CPX_WIDTH-1:0] cpx_spc1_data_cx2_d1; // packet delayed by 1
reg [`CPX_WIDTH-1:0] cpx_spc1_data_cx2_d2; // packet delayed by 2
reg [127:0] spc1_pcx_type_str; // packet type in string format for debug.
reg [127:0] cpx_spc1_type_str; // in string format for debug
wire [3:0] cpx_spc1_type = cpx_spc1_data_vld ? cpx_spc1_data_cx2[`CPX_RQ_HI:`CPX_RQ_LO] :4'h0;
wire cpx_spc1_wyvld = cpx_spc1_data_cx2[`CPX_WYVLD] & cpx_spc1_data_vld;
wire cpx_spc1_st_ack = (cpx_spc1_type == `ST_ACK) | (cpx_spc1_type == `STRST_ACK);
wire cpx_spc1_evict = (cpx_spc1_type == `EVICT_REQ);
reg cpx_spc1_ifill_wyvld;
reg cpx_spc1_dfill_wyvld;
wire cpx_spc1_st_ack_dc_inval_1c_tmp = (cpx_spc1_data_cx2[122:121] == 2'b00) ? cpx_spc1_data_cx2[0] :
(cpx_spc1_data_cx2[122:121] == 2'b01) ? cpx_spc1_data_cx2[32] :
(cpx_spc1_data_cx2[122:121] == 2'b10) ? cpx_spc1_data_cx2[56] :
cpx_spc1_data_cx2[88];
wire [2:0] cpx_spc1_st_ack_dc_inval_1c = {2'b00, cpx_spc1_st_ack & cpx_spc1_st_ack_dc_inval_1c_tmp};
wire cpx_spc1_st_ack_ic_inval_1c_tmp = cpx_spc1_data_cx2[122] ? cpx_spc1_data_cx2[57] : cpx_spc1_data_cx2[1];
wire [2:0] cpx_spc1_st_ack_ic_inval_1c = {2'b00, (cpx_spc1_st_ack & cpx_spc1_st_ack_ic_inval_1c_tmp)};
wire [5:0] cpx_spc1_st_ack_icdc_inval_1c = {6{cpx_spc1_st_ack}} &
{cpx_spc1_st_ack_ic_inval_1c, cpx_spc1_st_ack_dc_inval_1c};
wire [2:0] cpx_spc1_evict_dc_inval_1c = cpx_spc1_data_cx2[0] + cpx_spc1_data_cx2[32] +
cpx_spc1_data_cx2[56] + cpx_spc1_data_cx2[88];
wire [1:0] cpx_spc1_evict_ic_inval_1c = cpx_spc1_data_cx2[1] + cpx_spc1_data_cx2[57];
reg cpx_spc1_evict_d1;
always @(posedge clk)
cpx_spc1_evict_d1 <= cpx_spc1_evict;
wire cpx_spc1_b2b_evict = cpx_spc1_evict_d1 & cpx_spc1_evict;
wire [5:0] cpx_spc1_evict_icdc_inval_1c;
assign cpx_spc1_evict_icdc_inval_1c[4:0]={5{cpx_spc1_evict}} &
{cpx_spc1_evict_ic_inval_1c,cpx_spc1_evict_dc_inval_1c};
assign cpx_spc1_evict_icdc_inval_1c[5] = cpx_spc1_b2b_evict;
wire [5:0] cpx_spc1_st_ack_dc_inval_8c_tmp = (cpx_spc1_data_cx2[122:121] == 2'b00) ? (
cpx_spc1_data_cx2[0] + cpx_spc1_data_cx2[4] +
cpx_spc1_data_cx2[8] + cpx_spc1_data_cx2[12] +
cpx_spc1_data_cx2[16] + cpx_spc1_data_cx2[20] +
cpx_spc1_data_cx2[24] + cpx_spc1_data_cx2[28]
) :
(cpx_spc1_data_cx2[122:121] == 2'b01) ? (
cpx_spc1_data_cx2[32] + cpx_spc1_data_cx2[35] +
cpx_spc1_data_cx2[38] + cpx_spc1_data_cx2[41] +
cpx_spc1_data_cx2[44] + cpx_spc1_data_cx2[47] +
cpx_spc1_data_cx2[50] + cpx_spc1_data_cx2[53]
) :
(cpx_spc1_data_cx2[122:121] == 2'b10) ? (
cpx_spc1_data_cx2[56] + cpx_spc1_data_cx2[60] +
cpx_spc1_data_cx2[64] + cpx_spc1_data_cx2[68] +
cpx_spc1_data_cx2[72] + cpx_spc1_data_cx2[76] +
cpx_spc1_data_cx2[80] + cpx_spc1_data_cx2[84]
) :
( cpx_spc1_data_cx2[88] + cpx_spc1_data_cx2[91] +
cpx_spc1_data_cx2[94] + cpx_spc1_data_cx2[97] +
cpx_spc1_data_cx2[100]+ cpx_spc1_data_cx2[103]+
cpx_spc1_data_cx2[106]+ cpx_spc1_data_cx2[109]
) ;
wire [5:0] cpx_spc1_st_ack_dc_inval_8c = {6{cpx_spc1_st_ack}} & cpx_spc1_st_ack_dc_inval_8c_tmp;
wire [5:0] cpx_spc1_st_ack_ic_inval_8c_tmp = ~cpx_spc1_data_cx2[122] ? (
cpx_spc1_data_cx2[1] + cpx_spc1_data_cx2[5] +
cpx_spc1_data_cx2[9] + cpx_spc1_data_cx2[13] +
cpx_spc1_data_cx2[17] + cpx_spc1_data_cx2[21] +
cpx_spc1_data_cx2[25] + cpx_spc1_data_cx2[29]
) :
( cpx_spc1_data_cx2[57] + cpx_spc1_data_cx2[61] +
cpx_spc1_data_cx2[65] + cpx_spc1_data_cx2[69] +
cpx_spc1_data_cx2[73] + cpx_spc1_data_cx2[77] +
cpx_spc1_data_cx2[81] + cpx_spc1_data_cx2[85]
) ;
wire [5:0] cpx_spc1_st_ack_ic_inval_8c = {4{cpx_spc1_st_ack}} & cpx_spc1_st_ack_ic_inval_8c_tmp;
wire [5:0] cpx_spc1_evict_dc_inval_8c_tmp =
cpx_spc1_data_cx2[0] + cpx_spc1_data_cx2[4] +
cpx_spc1_data_cx2[8] + cpx_spc1_data_cx2[12] +
cpx_spc1_data_cx2[16] + cpx_spc1_data_cx2[20] +
cpx_spc1_data_cx2[24] + cpx_spc1_data_cx2[28] +
cpx_spc1_data_cx2[32] + cpx_spc1_data_cx2[35] +
cpx_spc1_data_cx2[38] + cpx_spc1_data_cx2[41] +
cpx_spc1_data_cx2[44] + cpx_spc1_data_cx2[47] +
cpx_spc1_data_cx2[50] + cpx_spc1_data_cx2[53] +
cpx_spc1_data_cx2[56] + cpx_spc1_data_cx2[60] +
cpx_spc1_data_cx2[64] + cpx_spc1_data_cx2[68] +
cpx_spc1_data_cx2[72] + cpx_spc1_data_cx2[76] +
cpx_spc1_data_cx2[80] + cpx_spc1_data_cx2[84] +
cpx_spc1_data_cx2[88] + cpx_spc1_data_cx2[91] +
cpx_spc1_data_cx2[94] + cpx_spc1_data_cx2[97] +
cpx_spc1_data_cx2[100]+ cpx_spc1_data_cx2[103]+
cpx_spc1_data_cx2[106]+ cpx_spc1_data_cx2[109];
wire [5:0] cpx_spc1_evict_dc_inval_8c = {6{cpx_spc1_evict}} & cpx_spc1_evict_dc_inval_8c_tmp;
wire [5:0] cpx_spc1_evict_ic_inval_8c_tmp =
cpx_spc1_data_cx2[1] + cpx_spc1_data_cx2[5] +
cpx_spc1_data_cx2[9] + cpx_spc1_data_cx2[13] +
cpx_spc1_data_cx2[17] + cpx_spc1_data_cx2[21] +
cpx_spc1_data_cx2[25] + cpx_spc1_data_cx2[29] +
cpx_spc1_data_cx2[57] + cpx_spc1_data_cx2[61] +
cpx_spc1_data_cx2[65] + cpx_spc1_data_cx2[69] +
cpx_spc1_data_cx2[73] + cpx_spc1_data_cx2[77] +
cpx_spc1_data_cx2[81] + cpx_spc1_data_cx2[85];
wire [5:0] cpx_spc1_evict_ic_inval_8c = {6{cpx_spc1_evict}} & cpx_spc1_evict_ic_inval_8c_tmp;
reg [3:0] blk_st_cnt1; // counts the number of block stores without an acknowledge in between
reg [3:0] ini_st_cnt1; // counts the number of init stores without an acknowledge in between
reg st_blkst_mixture1; // a flag set upon detection of block store and normal store mixture.
reg st_inist_mixture1; // a flag set upon detection of init store and normal store mixture.
reg atomic_ret1; // atomic cpx to spc package
reg non_b2b_atomic_ret1; // atomic cpx to spc package did not return in back to back cycles
wire cpx_spc2_data_vld = `TOP_MEMORY.cpx_spc2_data_cx2[`CPX_WIDTH-1];
wire [`CPX_WIDTH-1:0] cpx_spc2_data_cx2 = `TOP_MEMORY.cpx_spc2_data_cx2[`CPX_WIDTH-1:0];
reg [`CPX_WIDTH-1:0] cpx_spc2_data_cx2_d1; // packet delayed by 1
reg [`CPX_WIDTH-1:0] cpx_spc2_data_cx2_d2; // packet delayed by 2
reg [127:0] spc2_pcx_type_str; // packet type in string format for debug.
reg [127:0] cpx_spc2_type_str; // in string format for debug
wire [3:0] cpx_spc2_type = cpx_spc2_data_vld ? cpx_spc2_data_cx2[`CPX_RQ_HI:`CPX_RQ_LO] :4'h0;
wire cpx_spc2_wyvld = cpx_spc2_data_cx2[`CPX_WYVLD] & cpx_spc2_data_vld;
wire cpx_spc2_st_ack = (cpx_spc2_type == `ST_ACK) | (cpx_spc2_type == `STRST_ACK);
wire cpx_spc2_evict = (cpx_spc2_type == `EVICT_REQ);
reg cpx_spc2_ifill_wyvld;
reg cpx_spc2_dfill_wyvld;
wire cpx_spc2_st_ack_dc_inval_1c_tmp = (cpx_spc2_data_cx2[122:121] == 2'b00) ? cpx_spc2_data_cx2[0] :
(cpx_spc2_data_cx2[122:121] == 2'b01) ? cpx_spc2_data_cx2[32] :
(cpx_spc2_data_cx2[122:121] == 2'b10) ? cpx_spc2_data_cx2[56] :
cpx_spc2_data_cx2[88];
wire [2:0] cpx_spc2_st_ack_dc_inval_1c = {2'b00, cpx_spc2_st_ack & cpx_spc2_st_ack_dc_inval_1c_tmp};
wire cpx_spc2_st_ack_ic_inval_1c_tmp = cpx_spc2_data_cx2[122] ? cpx_spc2_data_cx2[57] : cpx_spc2_data_cx2[1];
wire [2:0] cpx_spc2_st_ack_ic_inval_1c = {2'b00, (cpx_spc2_st_ack & cpx_spc2_st_ack_ic_inval_1c_tmp)};
wire [5:0] cpx_spc2_st_ack_icdc_inval_1c = {6{cpx_spc2_st_ack}} &
{cpx_spc2_st_ack_ic_inval_1c, cpx_spc2_st_ack_dc_inval_1c};
wire [2:0] cpx_spc2_evict_dc_inval_1c = cpx_spc2_data_cx2[0] + cpx_spc2_data_cx2[32] +
cpx_spc2_data_cx2[56] + cpx_spc2_data_cx2[88];
wire [1:0] cpx_spc2_evict_ic_inval_1c = cpx_spc2_data_cx2[1] + cpx_spc2_data_cx2[57];
reg cpx_spc2_evict_d1;
always @(posedge clk)
cpx_spc2_evict_d1 <= cpx_spc2_evict;
wire cpx_spc2_b2b_evict = cpx_spc2_evict_d1 & cpx_spc2_evict;
wire [5:0] cpx_spc2_evict_icdc_inval_1c;
assign cpx_spc2_evict_icdc_inval_1c[4:0]={5{cpx_spc2_evict}} &
{cpx_spc2_evict_ic_inval_1c,cpx_spc2_evict_dc_inval_1c};
assign cpx_spc2_evict_icdc_inval_1c[5] = cpx_spc2_b2b_evict;
wire [5:0] cpx_spc2_st_ack_dc_inval_8c_tmp = (cpx_spc2_data_cx2[122:121] == 2'b00) ? (
cpx_spc2_data_cx2[0] + cpx_spc2_data_cx2[4] +
cpx_spc2_data_cx2[8] + cpx_spc2_data_cx2[12] +
cpx_spc2_data_cx2[16] + cpx_spc2_data_cx2[20] +
cpx_spc2_data_cx2[24] + cpx_spc2_data_cx2[28]
) :
(cpx_spc2_data_cx2[122:121] == 2'b01) ? (
cpx_spc2_data_cx2[32] + cpx_spc2_data_cx2[35] +
cpx_spc2_data_cx2[38] + cpx_spc2_data_cx2[41] +
cpx_spc2_data_cx2[44] + cpx_spc2_data_cx2[47] +
cpx_spc2_data_cx2[50] + cpx_spc2_data_cx2[53]
) :
(cpx_spc2_data_cx2[122:121] == 2'b10) ? (
cpx_spc2_data_cx2[56] + cpx_spc2_data_cx2[60] +
cpx_spc2_data_cx2[64] + cpx_spc2_data_cx2[68] +
cpx_spc2_data_cx2[72] + cpx_spc2_data_cx2[76] +
cpx_spc2_data_cx2[80] + cpx_spc2_data_cx2[84]
) :
( cpx_spc2_data_cx2[88] + cpx_spc2_data_cx2[91] +
cpx_spc2_data_cx2[94] + cpx_spc2_data_cx2[97] +
cpx_spc2_data_cx2[100]+ cpx_spc2_data_cx2[103]+
cpx_spc2_data_cx2[106]+ cpx_spc2_data_cx2[109]
) ;
wire [5:0] cpx_spc2_st_ack_dc_inval_8c = {6{cpx_spc2_st_ack}} & cpx_spc2_st_ack_dc_inval_8c_tmp;
wire [5:0] cpx_spc2_st_ack_ic_inval_8c_tmp = ~cpx_spc2_data_cx2[122] ? (
cpx_spc2_data_cx2[1] + cpx_spc2_data_cx2[5] +
cpx_spc2_data_cx2[9] + cpx_spc2_data_cx2[13] +
cpx_spc2_data_cx2[17] + cpx_spc2_data_cx2[21] +
cpx_spc2_data_cx2[25] + cpx_spc2_data_cx2[29]
) :
( cpx_spc2_data_cx2[57] + cpx_spc2_data_cx2[61] +
cpx_spc2_data_cx2[65] + cpx_spc2_data_cx2[69] +
cpx_spc2_data_cx2[73] + cpx_spc2_data_cx2[77] +
cpx_spc2_data_cx2[81] + cpx_spc2_data_cx2[85]
) ;
wire [5:0] cpx_spc2_st_ack_ic_inval_8c = {4{cpx_spc2_st_ack}} & cpx_spc2_st_ack_ic_inval_8c_tmp;
wire [5:0] cpx_spc2_evict_dc_inval_8c_tmp =
cpx_spc2_data_cx2[0] + cpx_spc2_data_cx2[4] +
cpx_spc2_data_cx2[8] + cpx_spc2_data_cx2[12] +
cpx_spc2_data_cx2[16] + cpx_spc2_data_cx2[20] +
cpx_spc2_data_cx2[24] + cpx_spc2_data_cx2[28] +
cpx_spc2_data_cx2[32] + cpx_spc2_data_cx2[35] +
cpx_spc2_data_cx2[38] + cpx_spc2_data_cx2[41] +
cpx_spc2_data_cx2[44] + cpx_spc2_data_cx2[47] +
cpx_spc2_data_cx2[50] + cpx_spc2_data_cx2[53] +
cpx_spc2_data_cx2[56] + cpx_spc2_data_cx2[60] +
cpx_spc2_data_cx2[64] + cpx_spc2_data_cx2[68] +
cpx_spc2_data_cx2[72] + cpx_spc2_data_cx2[76] +
cpx_spc2_data_cx2[80] + cpx_spc2_data_cx2[84] +
cpx_spc2_data_cx2[88] + cpx_spc2_data_cx2[91] +
cpx_spc2_data_cx2[94] + cpx_spc2_data_cx2[97] +
cpx_spc2_data_cx2[100]+ cpx_spc2_data_cx2[103]+
cpx_spc2_data_cx2[106]+ cpx_spc2_data_cx2[109];
wire [5:0] cpx_spc2_evict_dc_inval_8c = {6{cpx_spc2_evict}} & cpx_spc2_evict_dc_inval_8c_tmp;
wire [5:0] cpx_spc2_evict_ic_inval_8c_tmp =
cpx_spc2_data_cx2[1] + cpx_spc2_data_cx2[5] +
cpx_spc2_data_cx2[9] + cpx_spc2_data_cx2[13] +
cpx_spc2_data_cx2[17] + cpx_spc2_data_cx2[21] +
cpx_spc2_data_cx2[25] + cpx_spc2_data_cx2[29] +
cpx_spc2_data_cx2[57] + cpx_spc2_data_cx2[61] +
cpx_spc2_data_cx2[65] + cpx_spc2_data_cx2[69] +
cpx_spc2_data_cx2[73] + cpx_spc2_data_cx2[77] +
cpx_spc2_data_cx2[81] + cpx_spc2_data_cx2[85];
wire [5:0] cpx_spc2_evict_ic_inval_8c = {6{cpx_spc2_evict}} & cpx_spc2_evict_ic_inval_8c_tmp;
reg [3:0] blk_st_cnt2; // counts the number of block stores without an acknowledge in between
reg [3:0] ini_st_cnt2; // counts the number of init stores without an acknowledge in between
reg st_blkst_mixture2; // a flag set upon detection of block store and normal store mixture.
reg st_inist_mixture2; // a flag set upon detection of init store and normal store mixture.
reg atomic_ret2; // atomic cpx to spc package
reg non_b2b_atomic_ret2; // atomic cpx to spc package did not return in back to back cycles
wire cpx_spc3_data_vld = `TOP_MEMORY.cpx_spc3_data_cx2[`CPX_WIDTH-1];
wire [`CPX_WIDTH-1:0] cpx_spc3_data_cx2 = `TOP_MEMORY.cpx_spc3_data_cx2[`CPX_WIDTH-1:0];
reg [`CPX_WIDTH-1:0] cpx_spc3_data_cx2_d1; // packet delayed by 1
reg [`CPX_WIDTH-1:0] cpx_spc3_data_cx2_d2; // packet delayed by 2
reg [127:0] spc3_pcx_type_str; // packet type in string format for debug.
reg [127:0] cpx_spc3_type_str; // in string format for debug
wire [3:0] cpx_spc3_type = cpx_spc3_data_vld ? cpx_spc3_data_cx2[`CPX_RQ_HI:`CPX_RQ_LO] :4'h0;
wire cpx_spc3_wyvld = cpx_spc3_data_cx2[`CPX_WYVLD] & cpx_spc3_data_vld;
wire cpx_spc3_st_ack = (cpx_spc3_type == `ST_ACK) | (cpx_spc3_type == `STRST_ACK);
wire cpx_spc3_evict = (cpx_spc3_type == `EVICT_REQ);
reg cpx_spc3_ifill_wyvld;
reg cpx_spc3_dfill_wyvld;
wire cpx_spc3_st_ack_dc_inval_1c_tmp = (cpx_spc3_data_cx2[122:121] == 2'b00) ? cpx_spc3_data_cx2[0] :
(cpx_spc3_data_cx2[122:121] == 2'b01) ? cpx_spc3_data_cx2[32] :
(cpx_spc3_data_cx2[122:121] == 2'b10) ? cpx_spc3_data_cx2[56] :
cpx_spc3_data_cx2[88];
wire [2:0] cpx_spc3_st_ack_dc_inval_1c = {2'b00, cpx_spc3_st_ack & cpx_spc3_st_ack_dc_inval_1c_tmp};
wire cpx_spc3_st_ack_ic_inval_1c_tmp = cpx_spc3_data_cx2[122] ? cpx_spc3_data_cx2[57] : cpx_spc3_data_cx2[1];
wire [2:0] cpx_spc3_st_ack_ic_inval_1c = {2'b00, (cpx_spc3_st_ack & cpx_spc3_st_ack_ic_inval_1c_tmp)};
wire [5:0] cpx_spc3_st_ack_icdc_inval_1c = {6{cpx_spc3_st_ack}} &
{cpx_spc3_st_ack_ic_inval_1c, cpx_spc3_st_ack_dc_inval_1c};
wire [2:0] cpx_spc3_evict_dc_inval_1c = cpx_spc3_data_cx2[0] + cpx_spc3_data_cx2[32] +
cpx_spc3_data_cx2[56] + cpx_spc3_data_cx2[88];
wire [1:0] cpx_spc3_evict_ic_inval_1c = cpx_spc3_data_cx2[1] + cpx_spc3_data_cx2[57];
reg cpx_spc3_evict_d1;
always @(posedge clk)
cpx_spc3_evict_d1 <= cpx_spc3_evict;
wire cpx_spc3_b2b_evict = cpx_spc3_evict_d1 & cpx_spc3_evict;
wire [5:0] cpx_spc3_evict_icdc_inval_1c;
assign cpx_spc3_evict_icdc_inval_1c[4:0]={5{cpx_spc3_evict}} &
{cpx_spc3_evict_ic_inval_1c,cpx_spc3_evict_dc_inval_1c};
assign cpx_spc3_evict_icdc_inval_1c[5] = cpx_spc3_b2b_evict;
wire [5:0] cpx_spc3_st_ack_dc_inval_8c_tmp = (cpx_spc3_data_cx2[122:121] == 2'b00) ? (
cpx_spc3_data_cx2[0] + cpx_spc3_data_cx2[4] +
cpx_spc3_data_cx2[8] + cpx_spc3_data_cx2[12] +
cpx_spc3_data_cx2[16] + cpx_spc3_data_cx2[20] +
cpx_spc3_data_cx2[24] + cpx_spc3_data_cx2[28]
) :
(cpx_spc3_data_cx2[122:121] == 2'b01) ? (
cpx_spc3_data_cx2[32] + cpx_spc3_data_cx2[35] +
cpx_spc3_data_cx2[38] + cpx_spc3_data_cx2[41] +
cpx_spc3_data_cx2[44] + cpx_spc3_data_cx2[47] +
cpx_spc3_data_cx2[50] + cpx_spc3_data_cx2[53]
) :
(cpx_spc3_data_cx2[122:121] == 2'b10) ? (
cpx_spc3_data_cx2[56] + cpx_spc3_data_cx2[60] +
cpx_spc3_data_cx2[64] + cpx_spc3_data_cx2[68] +
cpx_spc3_data_cx2[72] + cpx_spc3_data_cx2[76] +
cpx_spc3_data_cx2[80] + cpx_spc3_data_cx2[84]
) :
( cpx_spc3_data_cx2[88] + cpx_spc3_data_cx2[91] +
cpx_spc3_data_cx2[94] + cpx_spc3_data_cx2[97] +
cpx_spc3_data_cx2[100]+ cpx_spc3_data_cx2[103]+
cpx_spc3_data_cx2[106]+ cpx_spc3_data_cx2[109]
) ;
wire [5:0] cpx_spc3_st_ack_dc_inval_8c = {6{cpx_spc3_st_ack}} & cpx_spc3_st_ack_dc_inval_8c_tmp;
wire [5:0] cpx_spc3_st_ack_ic_inval_8c_tmp = ~cpx_spc3_data_cx2[122] ? (
cpx_spc3_data_cx2[1] + cpx_spc3_data_cx2[5] +
cpx_spc3_data_cx2[9] + cpx_spc3_data_cx2[13] +
cpx_spc3_data_cx2[17] + cpx_spc3_data_cx2[21] +
cpx_spc3_data_cx2[25] + cpx_spc3_data_cx2[29]
) :
( cpx_spc3_data_cx2[57] + cpx_spc3_data_cx2[61] +
cpx_spc3_data_cx2[65] + cpx_spc3_data_cx2[69] +
cpx_spc3_data_cx2[73] + cpx_spc3_data_cx2[77] +
cpx_spc3_data_cx2[81] + cpx_spc3_data_cx2[85]
) ;
wire [5:0] cpx_spc3_st_ack_ic_inval_8c = {4{cpx_spc3_st_ack}} & cpx_spc3_st_ack_ic_inval_8c_tmp;
wire [5:0] cpx_spc3_evict_dc_inval_8c_tmp =
cpx_spc3_data_cx2[0] + cpx_spc3_data_cx2[4] +
cpx_spc3_data_cx2[8] + cpx_spc3_data_cx2[12] +
cpx_spc3_data_cx2[16] + cpx_spc3_data_cx2[20] +
cpx_spc3_data_cx2[24] + cpx_spc3_data_cx2[28] +
cpx_spc3_data_cx2[32] + cpx_spc3_data_cx2[35] +
cpx_spc3_data_cx2[38] + cpx_spc3_data_cx2[41] +
cpx_spc3_data_cx2[44] + cpx_spc3_data_cx2[47] +
cpx_spc3_data_cx2[50] + cpx_spc3_data_cx2[53] +
cpx_spc3_data_cx2[56] + cpx_spc3_data_cx2[60] +
cpx_spc3_data_cx2[64] + cpx_spc3_data_cx2[68] +
cpx_spc3_data_cx2[72] + cpx_spc3_data_cx2[76] +
cpx_spc3_data_cx2[80] + cpx_spc3_data_cx2[84] +
cpx_spc3_data_cx2[88] + cpx_spc3_data_cx2[91] +
cpx_spc3_data_cx2[94] + cpx_spc3_data_cx2[97] +
cpx_spc3_data_cx2[100]+ cpx_spc3_data_cx2[103]+
cpx_spc3_data_cx2[106]+ cpx_spc3_data_cx2[109];
wire [5:0] cpx_spc3_evict_dc_inval_8c = {6{cpx_spc3_evict}} & cpx_spc3_evict_dc_inval_8c_tmp;
wire [5:0] cpx_spc3_evict_ic_inval_8c_tmp =
cpx_spc3_data_cx2[1] + cpx_spc3_data_cx2[5] +
cpx_spc3_data_cx2[9] + cpx_spc3_data_cx2[13] +
cpx_spc3_data_cx2[17] + cpx_spc3_data_cx2[21] +
cpx_spc3_data_cx2[25] + cpx_spc3_data_cx2[29] +
cpx_spc3_data_cx2[57] + cpx_spc3_data_cx2[61] +
cpx_spc3_data_cx2[65] + cpx_spc3_data_cx2[69] +
cpx_spc3_data_cx2[73] + cpx_spc3_data_cx2[77] +
cpx_spc3_data_cx2[81] + cpx_spc3_data_cx2[85];
wire [5:0] cpx_spc3_evict_ic_inval_8c = {6{cpx_spc3_evict}} & cpx_spc3_evict_ic_inval_8c_tmp;
reg [3:0] blk_st_cnt3; // counts the number of block stores without an acknowledge in between
reg [3:0] ini_st_cnt3; // counts the number of init stores without an acknowledge in between
reg st_blkst_mixture3; // a flag set upon detection of block store and normal store mixture.
reg st_inist_mixture3; // a flag set upon detection of init store and normal store mixture.
reg atomic_ret3; // atomic cpx to spc package
reg non_b2b_atomic_ret3; // atomic cpx to spc package did not return in back to back cycles
wire cpx_spc4_data_vld = `TOP_MEMORY.cpx_spc4_data_cx2[`CPX_WIDTH-1];
wire [`CPX_WIDTH-1:0] cpx_spc4_data_cx2 = `TOP_MEMORY.cpx_spc4_data_cx2[`CPX_WIDTH-1:0];
reg [`CPX_WIDTH-1:0] cpx_spc4_data_cx2_d1; // packet delayed by 1
reg [`CPX_WIDTH-1:0] cpx_spc4_data_cx2_d2; // packet delayed by 2
reg [127:0] spc4_pcx_type_str; // packet type in string format for debug.
reg [127:0] cpx_spc4_type_str; // in string format for debug
wire [3:0] cpx_spc4_type = cpx_spc4_data_vld ? cpx_spc4_data_cx2[`CPX_RQ_HI:`CPX_RQ_LO] :4'h0;
wire cpx_spc4_wyvld = cpx_spc4_data_cx2[`CPX_WYVLD] & cpx_spc4_data_vld;
wire cpx_spc4_st_ack = (cpx_spc4_type == `ST_ACK) | (cpx_spc4_type == `STRST_ACK);
wire cpx_spc4_evict = (cpx_spc4_type == `EVICT_REQ);
reg cpx_spc4_ifill_wyvld;
reg cpx_spc4_dfill_wyvld;
wire cpx_spc4_st_ack_dc_inval_1c_tmp = (cpx_spc4_data_cx2[122:121] == 2'b00) ? cpx_spc4_data_cx2[0] :
(cpx_spc4_data_cx2[122:121] == 2'b01) ? cpx_spc4_data_cx2[32] :
(cpx_spc4_data_cx2[122:121] == 2'b10) ? cpx_spc4_data_cx2[56] :
cpx_spc4_data_cx2[88];
wire [2:0] cpx_spc4_st_ack_dc_inval_1c = {2'b00, cpx_spc4_st_ack & cpx_spc4_st_ack_dc_inval_1c_tmp};
wire cpx_spc4_st_ack_ic_inval_1c_tmp = cpx_spc4_data_cx2[122] ? cpx_spc4_data_cx2[57] : cpx_spc4_data_cx2[1];
wire [2:0] cpx_spc4_st_ack_ic_inval_1c = {2'b00, (cpx_spc4_st_ack & cpx_spc4_st_ack_ic_inval_1c_tmp)};
wire [5:0] cpx_spc4_st_ack_icdc_inval_1c = {6{cpx_spc4_st_ack}} &
{cpx_spc4_st_ack_ic_inval_1c, cpx_spc4_st_ack_dc_inval_1c};
wire [2:0] cpx_spc4_evict_dc_inval_1c = cpx_spc4_data_cx2[0] + cpx_spc4_data_cx2[32] +
cpx_spc4_data_cx2[56] + cpx_spc4_data_cx2[88];
wire [1:0] cpx_spc4_evict_ic_inval_1c = cpx_spc4_data_cx2[1] + cpx_spc4_data_cx2[57];
reg cpx_spc4_evict_d1;
always @(posedge clk)
cpx_spc4_evict_d1 <= cpx_spc4_evict;
wire cpx_spc4_b2b_evict = cpx_spc4_evict_d1 & cpx_spc4_evict;
wire [5:0] cpx_spc4_evict_icdc_inval_1c;
assign cpx_spc4_evict_icdc_inval_1c[4:0]={5{cpx_spc4_evict}} &
{cpx_spc4_evict_ic_inval_1c,cpx_spc4_evict_dc_inval_1c};
assign cpx_spc4_evict_icdc_inval_1c[5] = cpx_spc4_b2b_evict;
wire [5:0] cpx_spc4_st_ack_dc_inval_8c_tmp = (cpx_spc4_data_cx2[122:121] == 2'b00) ? (
cpx_spc4_data_cx2[0] + cpx_spc4_data_cx2[4] +
cpx_spc4_data_cx2[8] + cpx_spc4_data_cx2[12] +
cpx_spc4_data_cx2[16] + cpx_spc4_data_cx2[20] +
cpx_spc4_data_cx2[24] + cpx_spc4_data_cx2[28]
) :
(cpx_spc4_data_cx2[122:121] == 2'b01) ? (
cpx_spc4_data_cx2[32] + cpx_spc4_data_cx2[35] +
cpx_spc4_data_cx2[38] + cpx_spc4_data_cx2[41] +
cpx_spc4_data_cx2[44] + cpx_spc4_data_cx2[47] +
cpx_spc4_data_cx2[50] + cpx_spc4_data_cx2[53]
) :
(cpx_spc4_data_cx2[122:121] == 2'b10) ? (
cpx_spc4_data_cx2[56] + cpx_spc4_data_cx2[60] +
cpx_spc4_data_cx2[64] + cpx_spc4_data_cx2[68] +
cpx_spc4_data_cx2[72] + cpx_spc4_data_cx2[76] +
cpx_spc4_data_cx2[80] + cpx_spc4_data_cx2[84]
) :
( cpx_spc4_data_cx2[88] + cpx_spc4_data_cx2[91] +
cpx_spc4_data_cx2[94] + cpx_spc4_data_cx2[97] +
cpx_spc4_data_cx2[100]+ cpx_spc4_data_cx2[103]+
cpx_spc4_data_cx2[106]+ cpx_spc4_data_cx2[109]
) ;
wire [5:0] cpx_spc4_st_ack_dc_inval_8c = {6{cpx_spc4_st_ack}} & cpx_spc4_st_ack_dc_inval_8c_tmp;
wire [5:0] cpx_spc4_st_ack_ic_inval_8c_tmp = ~cpx_spc4_data_cx2[122] ? (
cpx_spc4_data_cx2[1] + cpx_spc4_data_cx2[5] +
cpx_spc4_data_cx2[9] + cpx_spc4_data_cx2[13] +
cpx_spc4_data_cx2[17] + cpx_spc4_data_cx2[21] +
cpx_spc4_data_cx2[25] + cpx_spc4_data_cx2[29]
) :
( cpx_spc4_data_cx2[57] + cpx_spc4_data_cx2[61] +
cpx_spc4_data_cx2[65] + cpx_spc4_data_cx2[69] +
cpx_spc4_data_cx2[73] + cpx_spc4_data_cx2[77] +
cpx_spc4_data_cx2[81] + cpx_spc4_data_cx2[85]
) ;
wire [5:0] cpx_spc4_st_ack_ic_inval_8c = {4{cpx_spc4_st_ack}} & cpx_spc4_st_ack_ic_inval_8c_tmp;
wire [5:0] cpx_spc4_evict_dc_inval_8c_tmp =
cpx_spc4_data_cx2[0] + cpx_spc4_data_cx2[4] +
cpx_spc4_data_cx2[8] + cpx_spc4_data_cx2[12] +
cpx_spc4_data_cx2[16] + cpx_spc4_data_cx2[20] +
cpx_spc4_data_cx2[24] + cpx_spc4_data_cx2[28] +
cpx_spc4_data_cx2[32] + cpx_spc4_data_cx2[35] +
cpx_spc4_data_cx2[38] + cpx_spc4_data_cx2[41] +
cpx_spc4_data_cx2[44] + cpx_spc4_data_cx2[47] +
cpx_spc4_data_cx2[50] + cpx_spc4_data_cx2[53] +
cpx_spc4_data_cx2[56] + cpx_spc4_data_cx2[60] +
cpx_spc4_data_cx2[64] + cpx_spc4_data_cx2[68] +
cpx_spc4_data_cx2[72] + cpx_spc4_data_cx2[76] +
cpx_spc4_data_cx2[80] + cpx_spc4_data_cx2[84] +
cpx_spc4_data_cx2[88] + cpx_spc4_data_cx2[91] +
cpx_spc4_data_cx2[94] + cpx_spc4_data_cx2[97] +
cpx_spc4_data_cx2[100]+ cpx_spc4_data_cx2[103]+
cpx_spc4_data_cx2[106]+ cpx_spc4_data_cx2[109];
wire [5:0] cpx_spc4_evict_dc_inval_8c = {6{cpx_spc4_evict}} & cpx_spc4_evict_dc_inval_8c_tmp;
wire [5:0] cpx_spc4_evict_ic_inval_8c_tmp =
cpx_spc4_data_cx2[1] + cpx_spc4_data_cx2[5] +
cpx_spc4_data_cx2[9] + cpx_spc4_data_cx2[13] +
cpx_spc4_data_cx2[17] + cpx_spc4_data_cx2[21] +
cpx_spc4_data_cx2[25] + cpx_spc4_data_cx2[29] +
cpx_spc4_data_cx2[57] + cpx_spc4_data_cx2[61] +
cpx_spc4_data_cx2[65] + cpx_spc4_data_cx2[69] +
cpx_spc4_data_cx2[73] + cpx_spc4_data_cx2[77] +
cpx_spc4_data_cx2[81] + cpx_spc4_data_cx2[85];
wire [5:0] cpx_spc4_evict_ic_inval_8c = {6{cpx_spc4_evict}} & cpx_spc4_evict_ic_inval_8c_tmp;
reg [3:0] blk_st_cnt4; // counts the number of block stores without an acknowledge in between
reg [3:0] ini_st_cnt4; // counts the number of init stores without an acknowledge in between
reg st_blkst_mixture4; // a flag set upon detection of block store and normal store mixture.
reg st_inist_mixture4; // a flag set upon detection of init store and normal store mixture.
reg atomic_ret4; // atomic cpx to spc package
reg non_b2b_atomic_ret4; // atomic cpx to spc package did not return in back to back cycles
wire cpx_spc5_data_vld = `TOP_MEMORY.cpx_spc5_data_cx2[`CPX_WIDTH-1];
wire [`CPX_WIDTH-1:0] cpx_spc5_data_cx2 = `TOP_MEMORY.cpx_spc5_data_cx2[`CPX_WIDTH-1:0];
reg [`CPX_WIDTH-1:0] cpx_spc5_data_cx2_d1; // packet delayed by 1
reg [`CPX_WIDTH-1:0] cpx_spc5_data_cx2_d2; // packet delayed by 2
reg [127:0] spc5_pcx_type_str; // packet type in string format for debug.
reg [127:0] cpx_spc5_type_str; // in string format for debug
wire [3:0] cpx_spc5_type = cpx_spc5_data_vld ? cpx_spc5_data_cx2[`CPX_RQ_HI:`CPX_RQ_LO] :4'h0;
wire cpx_spc5_wyvld = cpx_spc5_data_cx2[`CPX_WYVLD] & cpx_spc5_data_vld;
wire cpx_spc5_st_ack = (cpx_spc5_type == `ST_ACK) | (cpx_spc5_type == `STRST_ACK);
wire cpx_spc5_evict = (cpx_spc5_type == `EVICT_REQ);
reg cpx_spc5_ifill_wyvld;
reg cpx_spc5_dfill_wyvld;
wire cpx_spc5_st_ack_dc_inval_1c_tmp = (cpx_spc5_data_cx2[122:121] == 2'b00) ? cpx_spc5_data_cx2[0] :
(cpx_spc5_data_cx2[122:121] == 2'b01) ? cpx_spc5_data_cx2[32] :
(cpx_spc5_data_cx2[122:121] == 2'b10) ? cpx_spc5_data_cx2[56] :
cpx_spc5_data_cx2[88];
wire [2:0] cpx_spc5_st_ack_dc_inval_1c = {2'b00, cpx_spc5_st_ack & cpx_spc5_st_ack_dc_inval_1c_tmp};
wire cpx_spc5_st_ack_ic_inval_1c_tmp = cpx_spc5_data_cx2[122] ? cpx_spc5_data_cx2[57] : cpx_spc5_data_cx2[1];
wire [2:0] cpx_spc5_st_ack_ic_inval_1c = {2'b00, (cpx_spc5_st_ack & cpx_spc5_st_ack_ic_inval_1c_tmp)};
wire [5:0] cpx_spc5_st_ack_icdc_inval_1c = {6{cpx_spc5_st_ack}} &
{cpx_spc5_st_ack_ic_inval_1c, cpx_spc5_st_ack_dc_inval_1c};
wire [2:0] cpx_spc5_evict_dc_inval_1c = cpx_spc5_data_cx2[0] + cpx_spc5_data_cx2[32] +
cpx_spc5_data_cx2[56] + cpx_spc5_data_cx2[88];
wire [1:0] cpx_spc5_evict_ic_inval_1c = cpx_spc5_data_cx2[1] + cpx_spc5_data_cx2[57];
reg cpx_spc5_evict_d1;
always @(posedge clk)
cpx_spc5_evict_d1 <= cpx_spc5_evict;
wire cpx_spc5_b2b_evict = cpx_spc5_evict_d1 & cpx_spc5_evict;
wire [5:0] cpx_spc5_evict_icdc_inval_1c;
assign cpx_spc5_evict_icdc_inval_1c[4:0]={5{cpx_spc5_evict}} &
{cpx_spc5_evict_ic_inval_1c,cpx_spc5_evict_dc_inval_1c};
assign cpx_spc5_evict_icdc_inval_1c[5] = cpx_spc5_b2b_evict;
wire [5:0] cpx_spc5_st_ack_dc_inval_8c_tmp = (cpx_spc5_data_cx2[122:121] == 2'b00) ? (
cpx_spc5_data_cx2[0] + cpx_spc5_data_cx2[4] +
cpx_spc5_data_cx2[8] + cpx_spc5_data_cx2[12] +
cpx_spc5_data_cx2[16] + cpx_spc5_data_cx2[20] +
cpx_spc5_data_cx2[24] + cpx_spc5_data_cx2[28]
) :
(cpx_spc5_data_cx2[122:121] == 2'b01) ? (
cpx_spc5_data_cx2[32] + cpx_spc5_data_cx2[35] +
cpx_spc5_data_cx2[38] + cpx_spc5_data_cx2[41] +
cpx_spc5_data_cx2[44] + cpx_spc5_data_cx2[47] +
cpx_spc5_data_cx2[50] + cpx_spc5_data_cx2[53]
) :
(cpx_spc5_data_cx2[122:121] == 2'b10) ? (
cpx_spc5_data_cx2[56] + cpx_spc5_data_cx2[60] +
cpx_spc5_data_cx2[64] + cpx_spc5_data_cx2[68] +
cpx_spc5_data_cx2[72] + cpx_spc5_data_cx2[76] +
cpx_spc5_data_cx2[80] + cpx_spc5_data_cx2[84]
) :
( cpx_spc5_data_cx2[88] + cpx_spc5_data_cx2[91] +
cpx_spc5_data_cx2[94] + cpx_spc5_data_cx2[97] +
cpx_spc5_data_cx2[100]+ cpx_spc5_data_cx2[103]+
cpx_spc5_data_cx2[106]+ cpx_spc5_data_cx2[109]
) ;
wire [5:0] cpx_spc5_st_ack_dc_inval_8c = {6{cpx_spc5_st_ack}} & cpx_spc5_st_ack_dc_inval_8c_tmp;
wire [5:0] cpx_spc5_st_ack_ic_inval_8c_tmp = ~cpx_spc5_data_cx2[122] ? (
cpx_spc5_data_cx2[1] + cpx_spc5_data_cx2[5] +
cpx_spc5_data_cx2[9] + cpx_spc5_data_cx2[13] +
cpx_spc5_data_cx2[17] + cpx_spc5_data_cx2[21] +
cpx_spc5_data_cx2[25] + cpx_spc5_data_cx2[29]
) :
( cpx_spc5_data_cx2[57] + cpx_spc5_data_cx2[61] +
cpx_spc5_data_cx2[65] + cpx_spc5_data_cx2[69] +
cpx_spc5_data_cx2[73] + cpx_spc5_data_cx2[77] +
cpx_spc5_data_cx2[81] + cpx_spc5_data_cx2[85]
) ;
wire [5:0] cpx_spc5_st_ack_ic_inval_8c = {4{cpx_spc5_st_ack}} & cpx_spc5_st_ack_ic_inval_8c_tmp;
wire [5:0] cpx_spc5_evict_dc_inval_8c_tmp =
cpx_spc5_data_cx2[0] + cpx_spc5_data_cx2[4] +
cpx_spc5_data_cx2[8] + cpx_spc5_data_cx2[12] +
cpx_spc5_data_cx2[16] + cpx_spc5_data_cx2[20] +
cpx_spc5_data_cx2[24] + cpx_spc5_data_cx2[28] +
cpx_spc5_data_cx2[32] + cpx_spc5_data_cx2[35] +
cpx_spc5_data_cx2[38] + cpx_spc5_data_cx2[41] +
cpx_spc5_data_cx2[44] + cpx_spc5_data_cx2[47] +
cpx_spc5_data_cx2[50] + cpx_spc5_data_cx2[53] +
cpx_spc5_data_cx2[56] + cpx_spc5_data_cx2[60] +
cpx_spc5_data_cx2[64] + cpx_spc5_data_cx2[68] +
cpx_spc5_data_cx2[72] + cpx_spc5_data_cx2[76] +
cpx_spc5_data_cx2[80] + cpx_spc5_data_cx2[84] +
cpx_spc5_data_cx2[88] + cpx_spc5_data_cx2[91] +
cpx_spc5_data_cx2[94] + cpx_spc5_data_cx2[97] +
cpx_spc5_data_cx2[100]+ cpx_spc5_data_cx2[103]+
cpx_spc5_data_cx2[106]+ cpx_spc5_data_cx2[109];
wire [5:0] cpx_spc5_evict_dc_inval_8c = {6{cpx_spc5_evict}} & cpx_spc5_evict_dc_inval_8c_tmp;
wire [5:0] cpx_spc5_evict_ic_inval_8c_tmp =
cpx_spc5_data_cx2[1] + cpx_spc5_data_cx2[5] +
cpx_spc5_data_cx2[9] + cpx_spc5_data_cx2[13] +
cpx_spc5_data_cx2[17] + cpx_spc5_data_cx2[21] +
cpx_spc5_data_cx2[25] + cpx_spc5_data_cx2[29] +
cpx_spc5_data_cx2[57] + cpx_spc5_data_cx2[61] +
cpx_spc5_data_cx2[65] + cpx_spc5_data_cx2[69] +
cpx_spc5_data_cx2[73] + cpx_spc5_data_cx2[77] +
cpx_spc5_data_cx2[81] + cpx_spc5_data_cx2[85];
wire [5:0] cpx_spc5_evict_ic_inval_8c = {6{cpx_spc5_evict}} & cpx_spc5_evict_ic_inval_8c_tmp;
reg [3:0] blk_st_cnt5; // counts the number of block stores without an acknowledge in between
reg [3:0] ini_st_cnt5; // counts the number of init stores without an acknowledge in between
reg st_blkst_mixture5; // a flag set upon detection of block store and normal store mixture.
reg st_inist_mixture5; // a flag set upon detection of init store and normal store mixture.
reg atomic_ret5; // atomic cpx to spc package
reg non_b2b_atomic_ret5; // atomic cpx to spc package did not return in back to back cycles
wire cpx_spc6_data_vld = `TOP_MEMORY.cpx_spc6_data_cx2[`CPX_WIDTH-1];
wire [`CPX_WIDTH-1:0] cpx_spc6_data_cx2 = `TOP_MEMORY.cpx_spc6_data_cx2[`CPX_WIDTH-1:0];
reg [`CPX_WIDTH-1:0] cpx_spc6_data_cx2_d1; // packet delayed by 1
reg [`CPX_WIDTH-1:0] cpx_spc6_data_cx2_d2; // packet delayed by 2
reg [127:0] spc6_pcx_type_str; // packet type in string format for debug.
reg [127:0] cpx_spc6_type_str; // in string format for debug
wire [3:0] cpx_spc6_type = cpx_spc6_data_vld ? cpx_spc6_data_cx2[`CPX_RQ_HI:`CPX_RQ_LO] :4'h0;
wire cpx_spc6_wyvld = cpx_spc6_data_cx2[`CPX_WYVLD] & cpx_spc6_data_vld;
wire cpx_spc6_st_ack = (cpx_spc6_type == `ST_ACK) | (cpx_spc6_type == `STRST_ACK);
wire cpx_spc6_evict = (cpx_spc6_type == `EVICT_REQ);
reg cpx_spc6_ifill_wyvld;
reg cpx_spc6_dfill_wyvld;
wire cpx_spc6_st_ack_dc_inval_1c_tmp = (cpx_spc6_data_cx2[122:121] == 2'b00) ? cpx_spc6_data_cx2[0] :
(cpx_spc6_data_cx2[122:121] == 2'b01) ? cpx_spc6_data_cx2[32] :
(cpx_spc6_data_cx2[122:121] == 2'b10) ? cpx_spc6_data_cx2[56] :
cpx_spc6_data_cx2[88];
wire [2:0] cpx_spc6_st_ack_dc_inval_1c = {2'b00, cpx_spc6_st_ack & cpx_spc6_st_ack_dc_inval_1c_tmp};
wire cpx_spc6_st_ack_ic_inval_1c_tmp = cpx_spc6_data_cx2[122] ? cpx_spc6_data_cx2[57] : cpx_spc6_data_cx2[1];
wire [2:0] cpx_spc6_st_ack_ic_inval_1c = {2'b00, (cpx_spc6_st_ack & cpx_spc6_st_ack_ic_inval_1c_tmp)};
wire [5:0] cpx_spc6_st_ack_icdc_inval_1c = {6{cpx_spc6_st_ack}} &
{cpx_spc6_st_ack_ic_inval_1c, cpx_spc6_st_ack_dc_inval_1c};
wire [2:0] cpx_spc6_evict_dc_inval_1c = cpx_spc6_data_cx2[0] + cpx_spc6_data_cx2[32] +
cpx_spc6_data_cx2[56] + cpx_spc6_data_cx2[88];
wire [1:0] cpx_spc6_evict_ic_inval_1c = cpx_spc6_data_cx2[1] + cpx_spc6_data_cx2[57];
reg cpx_spc6_evict_d1;
always @(posedge clk)
cpx_spc6_evict_d1 <= cpx_spc6_evict;
wire cpx_spc6_b2b_evict = cpx_spc6_evict_d1 & cpx_spc6_evict;
wire [5:0] cpx_spc6_evict_icdc_inval_1c;
assign cpx_spc6_evict_icdc_inval_1c[4:0]={5{cpx_spc6_evict}} &
{cpx_spc6_evict_ic_inval_1c,cpx_spc6_evict_dc_inval_1c};
assign cpx_spc6_evict_icdc_inval_1c[5] = cpx_spc6_b2b_evict;
wire [5:0] cpx_spc6_st_ack_dc_inval_8c_tmp = (cpx_spc6_data_cx2[122:121] == 2'b00) ? (
cpx_spc6_data_cx2[0] + cpx_spc6_data_cx2[4] +
cpx_spc6_data_cx2[8] + cpx_spc6_data_cx2[12] +
cpx_spc6_data_cx2[16] + cpx_spc6_data_cx2[20] +
cpx_spc6_data_cx2[24] + cpx_spc6_data_cx2[28]
) :
(cpx_spc6_data_cx2[122:121] == 2'b01) ? (
cpx_spc6_data_cx2[32] + cpx_spc6_data_cx2[35] +
cpx_spc6_data_cx2[38] + cpx_spc6_data_cx2[41] +
cpx_spc6_data_cx2[44] + cpx_spc6_data_cx2[47] +
cpx_spc6_data_cx2[50] + cpx_spc6_data_cx2[53]
) :
(cpx_spc6_data_cx2[122:121] == 2'b10) ? (
cpx_spc6_data_cx2[56] + cpx_spc6_data_cx2[60] +
cpx_spc6_data_cx2[64] + cpx_spc6_data_cx2[68] +
cpx_spc6_data_cx2[72] + cpx_spc6_data_cx2[76] +
cpx_spc6_data_cx2[80] + cpx_spc6_data_cx2[84]
) :
( cpx_spc6_data_cx2[88] + cpx_spc6_data_cx2[91] +
cpx_spc6_data_cx2[94] + cpx_spc6_data_cx2[97] +
cpx_spc6_data_cx2[100]+ cpx_spc6_data_cx2[103]+
cpx_spc6_data_cx2[106]+ cpx_spc6_data_cx2[109]
) ;
wire [5:0] cpx_spc6_st_ack_dc_inval_8c = {6{cpx_spc6_st_ack}} & cpx_spc6_st_ack_dc_inval_8c_tmp;
wire [5:0] cpx_spc6_st_ack_ic_inval_8c_tmp = ~cpx_spc6_data_cx2[122] ? (
cpx_spc6_data_cx2[1] + cpx_spc6_data_cx2[5] +
cpx_spc6_data_cx2[9] + cpx_spc6_data_cx2[13] +
cpx_spc6_data_cx2[17] + cpx_spc6_data_cx2[21] +
cpx_spc6_data_cx2[25] + cpx_spc6_data_cx2[29]
) :
( cpx_spc6_data_cx2[57] + cpx_spc6_data_cx2[61] +
cpx_spc6_data_cx2[65] + cpx_spc6_data_cx2[69] +
cpx_spc6_data_cx2[73] + cpx_spc6_data_cx2[77] +
cpx_spc6_data_cx2[81] + cpx_spc6_data_cx2[85]
) ;
wire [5:0] cpx_spc6_st_ack_ic_inval_8c = {4{cpx_spc6_st_ack}} & cpx_spc6_st_ack_ic_inval_8c_tmp;
wire [5:0] cpx_spc6_evict_dc_inval_8c_tmp =
cpx_spc6_data_cx2[0] + cpx_spc6_data_cx2[4] +
cpx_spc6_data_cx2[8] + cpx_spc6_data_cx2[12] +
cpx_spc6_data_cx2[16] + cpx_spc6_data_cx2[20] +
cpx_spc6_data_cx2[24] + cpx_spc6_data_cx2[28] +
cpx_spc6_data_cx2[32] + cpx_spc6_data_cx2[35] +
cpx_spc6_data_cx2[38] + cpx_spc6_data_cx2[41] +
cpx_spc6_data_cx2[44] + cpx_spc6_data_cx2[47] +
cpx_spc6_data_cx2[50] + cpx_spc6_data_cx2[53] +
cpx_spc6_data_cx2[56] + cpx_spc6_data_cx2[60] +
cpx_spc6_data_cx2[64] + cpx_spc6_data_cx2[68] +
cpx_spc6_data_cx2[72] + cpx_spc6_data_cx2[76] +
cpx_spc6_data_cx2[80] + cpx_spc6_data_cx2[84] +
cpx_spc6_data_cx2[88] + cpx_spc6_data_cx2[91] +
cpx_spc6_data_cx2[94] + cpx_spc6_data_cx2[97] +
cpx_spc6_data_cx2[100]+ cpx_spc6_data_cx2[103]+
cpx_spc6_data_cx2[106]+ cpx_spc6_data_cx2[109];
wire [5:0] cpx_spc6_evict_dc_inval_8c = {6{cpx_spc6_evict}} & cpx_spc6_evict_dc_inval_8c_tmp;
wire [5:0] cpx_spc6_evict_ic_inval_8c_tmp =
cpx_spc6_data_cx2[1] + cpx_spc6_data_cx2[5] +
cpx_spc6_data_cx2[9] + cpx_spc6_data_cx2[13] +
cpx_spc6_data_cx2[17] + cpx_spc6_data_cx2[21] +
cpx_spc6_data_cx2[25] + cpx_spc6_data_cx2[29] +
cpx_spc6_data_cx2[57] + cpx_spc6_data_cx2[61] +
cpx_spc6_data_cx2[65] + cpx_spc6_data_cx2[69] +
cpx_spc6_data_cx2[73] + cpx_spc6_data_cx2[77] +
cpx_spc6_data_cx2[81] + cpx_spc6_data_cx2[85];
wire [5:0] cpx_spc6_evict_ic_inval_8c = {6{cpx_spc6_evict}} & cpx_spc6_evict_ic_inval_8c_tmp;
reg [3:0] blk_st_cnt6; // counts the number of block stores without an acknowledge in between
reg [3:0] ini_st_cnt6; // counts the number of init stores without an acknowledge in between
reg st_blkst_mixture6; // a flag set upon detection of block store and normal store mixture.
reg st_inist_mixture6; // a flag set upon detection of init store and normal store mixture.
reg atomic_ret6; // atomic cpx to spc package
reg non_b2b_atomic_ret6; // atomic cpx to spc package did not return in back to back cycles
wire cpx_spc7_data_vld = `TOP_MEMORY.cpx_spc7_data_cx2[`CPX_WIDTH-1];
wire [`CPX_WIDTH-1:0] cpx_spc7_data_cx2 = `TOP_MEMORY.cpx_spc7_data_cx2[`CPX_WIDTH-1:0];
reg [`CPX_WIDTH-1:0] cpx_spc7_data_cx2_d1; // packet delayed by 1
reg [`CPX_WIDTH-1:0] cpx_spc7_data_cx2_d2; // packet delayed by 2
reg [127:0] spc7_pcx_type_str; // packet type in string format for debug.
reg [127:0] cpx_spc7_type_str; // in string format for debug
wire [3:0] cpx_spc7_type = cpx_spc7_data_vld ? cpx_spc7_data_cx2[`CPX_RQ_HI:`CPX_RQ_LO] :4'h0;
wire cpx_spc7_wyvld = cpx_spc7_data_cx2[`CPX_WYVLD] & cpx_spc7_data_vld;
wire cpx_spc7_st_ack = (cpx_spc7_type == `ST_ACK) | (cpx_spc7_type == `STRST_ACK);
wire cpx_spc7_evict = (cpx_spc7_type == `EVICT_REQ);
reg cpx_spc7_ifill_wyvld;
reg cpx_spc7_dfill_wyvld;
wire cpx_spc7_st_ack_dc_inval_1c_tmp = (cpx_spc7_data_cx2[122:121] == 2'b00) ? cpx_spc7_data_cx2[0] :
(cpx_spc7_data_cx2[122:121] == 2'b01) ? cpx_spc7_data_cx2[32] :
(cpx_spc7_data_cx2[122:121] == 2'b10) ? cpx_spc7_data_cx2[56] :
cpx_spc7_data_cx2[88];
wire [2:0] cpx_spc7_st_ack_dc_inval_1c = {2'b00, cpx_spc7_st_ack & cpx_spc7_st_ack_dc_inval_1c_tmp};
wire cpx_spc7_st_ack_ic_inval_1c_tmp = cpx_spc7_data_cx2[122] ? cpx_spc7_data_cx2[57] : cpx_spc7_data_cx2[1];
wire [2:0] cpx_spc7_st_ack_ic_inval_1c = {2'b00, (cpx_spc7_st_ack & cpx_spc7_st_ack_ic_inval_1c_tmp)};
wire [5:0] cpx_spc7_st_ack_icdc_inval_1c = {6{cpx_spc7_st_ack}} &
{cpx_spc7_st_ack_ic_inval_1c, cpx_spc7_st_ack_dc_inval_1c};
wire [2:0] cpx_spc7_evict_dc_inval_1c = cpx_spc7_data_cx2[0] + cpx_spc7_data_cx2[32] +
cpx_spc7_data_cx2[56] + cpx_spc7_data_cx2[88];
wire [1:0] cpx_spc7_evict_ic_inval_1c = cpx_spc7_data_cx2[1] + cpx_spc7_data_cx2[57];
reg cpx_spc7_evict_d1;
always @(posedge clk)
cpx_spc7_evict_d1 <= cpx_spc7_evict;
wire cpx_spc7_b2b_evict = cpx_spc7_evict_d1 & cpx_spc7_evict;
wire [5:0] cpx_spc7_evict_icdc_inval_1c;
assign cpx_spc7_evict_icdc_inval_1c[4:0]={5{cpx_spc7_evict}} &
{cpx_spc7_evict_ic_inval_1c,cpx_spc7_evict_dc_inval_1c};
assign cpx_spc7_evict_icdc_inval_1c[5] = cpx_spc7_b2b_evict;
wire [5:0] cpx_spc7_st_ack_dc_inval_8c_tmp = (cpx_spc7_data_cx2[122:121] == 2'b00) ? (
cpx_spc7_data_cx2[0] + cpx_spc7_data_cx2[4] +
cpx_spc7_data_cx2[8] + cpx_spc7_data_cx2[12] +
cpx_spc7_data_cx2[16] + cpx_spc7_data_cx2[20] +
cpx_spc7_data_cx2[24] + cpx_spc7_data_cx2[28]
) :
(cpx_spc7_data_cx2[122:121] == 2'b01) ? (
cpx_spc7_data_cx2[32] + cpx_spc7_data_cx2[35] +
cpx_spc7_data_cx2[38] + cpx_spc7_data_cx2[41] +
cpx_spc7_data_cx2[44] + cpx_spc7_data_cx2[47] +
cpx_spc7_data_cx2[50] + cpx_spc7_data_cx2[53]
) :
(cpx_spc7_data_cx2[122:121] == 2'b10) ? (
cpx_spc7_data_cx2[56] + cpx_spc7_data_cx2[60] +
cpx_spc7_data_cx2[64] + cpx_spc7_data_cx2[68] +
cpx_spc7_data_cx2[72] + cpx_spc7_data_cx2[76] +
cpx_spc7_data_cx2[80] + cpx_spc7_data_cx2[84]
) :
( cpx_spc7_data_cx2[88] + cpx_spc7_data_cx2[91] +
cpx_spc7_data_cx2[94] + cpx_spc7_data_cx2[97] +
cpx_spc7_data_cx2[100]+ cpx_spc7_data_cx2[103]+
cpx_spc7_data_cx2[106]+ cpx_spc7_data_cx2[109]
) ;
wire [5:0] cpx_spc7_st_ack_dc_inval_8c = {6{cpx_spc7_st_ack}} & cpx_spc7_st_ack_dc_inval_8c_tmp;
wire [5:0] cpx_spc7_st_ack_ic_inval_8c_tmp = ~cpx_spc7_data_cx2[122] ? (
cpx_spc7_data_cx2[1] + cpx_spc7_data_cx2[5] +
cpx_spc7_data_cx2[9] + cpx_spc7_data_cx2[13] +
cpx_spc7_data_cx2[17] + cpx_spc7_data_cx2[21] +
cpx_spc7_data_cx2[25] + cpx_spc7_data_cx2[29]
) :
( cpx_spc7_data_cx2[57] + cpx_spc7_data_cx2[61] +
cpx_spc7_data_cx2[65] + cpx_spc7_data_cx2[69] +
cpx_spc7_data_cx2[73] + cpx_spc7_data_cx2[77] +
cpx_spc7_data_cx2[81] + cpx_spc7_data_cx2[85]
) ;
wire [5:0] cpx_spc7_st_ack_ic_inval_8c = {4{cpx_spc7_st_ack}} & cpx_spc7_st_ack_ic_inval_8c_tmp;
wire [5:0] cpx_spc7_evict_dc_inval_8c_tmp =
cpx_spc7_data_cx2[0] + cpx_spc7_data_cx2[4] +
cpx_spc7_data_cx2[8] + cpx_spc7_data_cx2[12] +
cpx_spc7_data_cx2[16] + cpx_spc7_data_cx2[20] +
cpx_spc7_data_cx2[24] + cpx_spc7_data_cx2[28] +
cpx_spc7_data_cx2[32] + cpx_spc7_data_cx2[35] +
cpx_spc7_data_cx2[38] + cpx_spc7_data_cx2[41] +
cpx_spc7_data_cx2[44] + cpx_spc7_data_cx2[47] +
cpx_spc7_data_cx2[50] + cpx_spc7_data_cx2[53] +
cpx_spc7_data_cx2[56] + cpx_spc7_data_cx2[60] +
cpx_spc7_data_cx2[64] + cpx_spc7_data_cx2[68] +
cpx_spc7_data_cx2[72] + cpx_spc7_data_cx2[76] +
cpx_spc7_data_cx2[80] + cpx_spc7_data_cx2[84] +
cpx_spc7_data_cx2[88] + cpx_spc7_data_cx2[91] +
cpx_spc7_data_cx2[94] + cpx_spc7_data_cx2[97] +
cpx_spc7_data_cx2[100]+ cpx_spc7_data_cx2[103]+
cpx_spc7_data_cx2[106]+ cpx_spc7_data_cx2[109];
wire [5:0] cpx_spc7_evict_dc_inval_8c = {6{cpx_spc7_evict}} & cpx_spc7_evict_dc_inval_8c_tmp;
wire [5:0] cpx_spc7_evict_ic_inval_8c_tmp =
cpx_spc7_data_cx2[1] + cpx_spc7_data_cx2[5] +
cpx_spc7_data_cx2[9] + cpx_spc7_data_cx2[13] +
cpx_spc7_data_cx2[17] + cpx_spc7_data_cx2[21] +
cpx_spc7_data_cx2[25] + cpx_spc7_data_cx2[29] +
cpx_spc7_data_cx2[57] + cpx_spc7_data_cx2[61] +
cpx_spc7_data_cx2[65] + cpx_spc7_data_cx2[69] +
cpx_spc7_data_cx2[73] + cpx_spc7_data_cx2[77] +
cpx_spc7_data_cx2[81] + cpx_spc7_data_cx2[85];
wire [5:0] cpx_spc7_evict_ic_inval_8c = {6{cpx_spc7_evict}} & cpx_spc7_evict_ic_inval_8c_tmp;
reg [3:0] blk_st_cnt7; // counts the number of block stores without an acknowledge in between
reg [3:0] ini_st_cnt7; // counts the number of init stores without an acknowledge in between
reg st_blkst_mixture7; // a flag set upon detection of block store and normal store mixture.
reg st_inist_mixture7; // a flag set upon detection of init store and normal store mixture.
reg atomic_ret7; // atomic cpx to spc package
reg non_b2b_atomic_ret7; // atomic cpx to spc package did not return in back to back cycles
//----------------------------------------------------------------------------------------
// The real thing starts somewhere here
//----------------------------------------------------------------------------------------
// This check belongs to another monitor (PLL) but since the PLL monitor does not
// exist and I do want this chip to work I put it here.
//--------------------------------------------------------------------------------
always @(posedge clk)
begin
if(rst_l & ~pll_lock & ~disable_lock_check)
finish_test("tso_mon", "PLL is not locked", 0);
end
always @(posedge clk)
begin
pcx0_vld_d1 <= spc0_pcx_data_pa[123];
pcx0_type_d1 <= spc0_pcx_data_pa[122:118];
pcx0_req_pq_d1 <= |spc0_pcx_req_pq;
pcx0_atom_pq_d1 <= spc0_pcx_atom_pq;
pcx0_atom_pq_d2 <= pcx0_atom_pq_d1;
// Multiple block stores without an ACK in between
//---------------------------------------------------
if((cpx_spc0_type == `ST_ACK) | ~rst_l)
blk_st_cnt0 <= 4'h0;
else if(pcx0_req_pq_d1 & (spc0_pcx_data_pa[122:118] == `STORE_RQ) & spc0_pcx_data_pa[109] & spc0_pcx_data_pa[110])
blk_st_cnt0 <= blk_st_cnt0 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(blk_st_cnt0 & (spc0_pcx_data_pa[122:118] == `STORE_RQ) & ~spc0_pcx_data_pa[109])
st_blkst_mixture0 <= 1'b1;
else if(blk_st_cnt0 == 4'h0)
st_blkst_mixture0 <= 1'b0;
// Multiple init stores without an ACK in between
//---------------------------------------------------
if((cpx_spc0_type == `ST_ACK) | ~rst_l)
ini_st_cnt0 <= 4'h0;
else if(pcx0_req_pq_d1 & (spc0_pcx_data_pa[122:118] == `STORE_RQ) & spc0_pcx_data_pa[109] & ~spc0_pcx_data_pa[110])
ini_st_cnt0 <= ini_st_cnt0 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(ini_st_cnt0 && (spc0_pcx_data_pa[122:118] == `STORE_RQ) & ~spc0_pcx_data_pa[109])
st_inist_mixture0 <= 1'b1;
else if(ini_st_cnt0 == 4'h0)
st_inist_mixture0 <= 1'b0;
if(~rst_l)
cpx_spc0_ifill_wyvld <= 1'b0;
else
cpx_spc0_ifill_wyvld <= ((cpx_spc0_type == `IFILL_RET) & cpx_spc0_wyvld);
if(~rst_l)
cpx_spc0_dfill_wyvld <= 1'b0;
else
cpx_spc0_dfill_wyvld <= ((cpx_spc0_type == `LOAD_RET) & cpx_spc0_wyvld);
pcx1_vld_d1 <= spc1_pcx_data_pa[123];
pcx1_type_d1 <= spc1_pcx_data_pa[122:118];
pcx1_req_pq_d1 <= |spc1_pcx_req_pq;
pcx1_atom_pq_d1 <= spc1_pcx_atom_pq;
pcx1_atom_pq_d2 <= pcx1_atom_pq_d1;
// Multiple block stores without an ACK in between
//---------------------------------------------------
if((cpx_spc1_type == `ST_ACK) | ~rst_l)
blk_st_cnt1 <= 4'h0;
else if(pcx1_req_pq_d1 & (spc1_pcx_data_pa[122:118] == `STORE_RQ) & spc1_pcx_data_pa[109] & spc1_pcx_data_pa[110])
blk_st_cnt1 <= blk_st_cnt1 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(blk_st_cnt1 & (spc1_pcx_data_pa[122:118] == `STORE_RQ) & ~spc1_pcx_data_pa[109])
st_blkst_mixture1 <= 1'b1;
else if(blk_st_cnt1 == 4'h0)
st_blkst_mixture1 <= 1'b0;
// Multiple init stores without an ACK in between
//---------------------------------------------------
if((cpx_spc1_type == `ST_ACK) | ~rst_l)
ini_st_cnt1 <= 4'h0;
else if(pcx1_req_pq_d1 & (spc1_pcx_data_pa[122:118] == `STORE_RQ) & spc1_pcx_data_pa[109] & ~spc1_pcx_data_pa[110])
ini_st_cnt1 <= ini_st_cnt1 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(ini_st_cnt1 && (spc1_pcx_data_pa[122:118] == `STORE_RQ) & ~spc1_pcx_data_pa[109])
st_inist_mixture1 <= 1'b1;
else if(ini_st_cnt1 == 4'h0)
st_inist_mixture1 <= 1'b0;
if(~rst_l)
cpx_spc1_ifill_wyvld <= 1'b0;
else
cpx_spc1_ifill_wyvld <= ((cpx_spc1_type == `IFILL_RET) & cpx_spc1_wyvld);
if(~rst_l)
cpx_spc1_dfill_wyvld <= 1'b0;
else
cpx_spc1_dfill_wyvld <= ((cpx_spc1_type == `LOAD_RET) & cpx_spc1_wyvld);
pcx2_vld_d1 <= spc2_pcx_data_pa[123];
pcx2_type_d1 <= spc2_pcx_data_pa[122:118];
pcx2_req_pq_d1 <= |spc2_pcx_req_pq;
pcx2_atom_pq_d1 <= spc2_pcx_atom_pq;
pcx2_atom_pq_d2 <= pcx2_atom_pq_d1;
// Multiple block stores without an ACK in between
//---------------------------------------------------
if((cpx_spc2_type == `ST_ACK) | ~rst_l)
blk_st_cnt2 <= 4'h0;
else if(pcx2_req_pq_d1 & (spc2_pcx_data_pa[122:118] == `STORE_RQ) & spc2_pcx_data_pa[109] & spc2_pcx_data_pa[110])
blk_st_cnt2 <= blk_st_cnt2 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(blk_st_cnt2 & (spc2_pcx_data_pa[122:118] == `STORE_RQ) & ~spc2_pcx_data_pa[109])
st_blkst_mixture2 <= 1'b1;
else if(blk_st_cnt2 == 4'h0)
st_blkst_mixture2 <= 1'b0;
// Multiple init stores without an ACK in between
//---------------------------------------------------
if((cpx_spc2_type == `ST_ACK) | ~rst_l)
ini_st_cnt2 <= 4'h0;
else if(pcx2_req_pq_d1 & (spc2_pcx_data_pa[122:118] == `STORE_RQ) & spc2_pcx_data_pa[109] & ~spc2_pcx_data_pa[110])
ini_st_cnt2 <= ini_st_cnt2 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(ini_st_cnt2 && (spc2_pcx_data_pa[122:118] == `STORE_RQ) & ~spc2_pcx_data_pa[109])
st_inist_mixture2 <= 1'b1;
else if(ini_st_cnt2 == 4'h0)
st_inist_mixture2 <= 1'b0;
if(~rst_l)
cpx_spc2_ifill_wyvld <= 1'b0;
else
cpx_spc2_ifill_wyvld <= ((cpx_spc2_type == `IFILL_RET) & cpx_spc2_wyvld);
if(~rst_l)
cpx_spc2_dfill_wyvld <= 1'b0;
else
cpx_spc2_dfill_wyvld <= ((cpx_spc2_type == `LOAD_RET) & cpx_spc2_wyvld);
pcx3_vld_d1 <= spc3_pcx_data_pa[123];
pcx3_type_d1 <= spc3_pcx_data_pa[122:118];
pcx3_req_pq_d1 <= |spc3_pcx_req_pq;
pcx3_atom_pq_d1 <= spc3_pcx_atom_pq;
pcx3_atom_pq_d2 <= pcx3_atom_pq_d1;
// Multiple block stores without an ACK in between
//---------------------------------------------------
if((cpx_spc3_type == `ST_ACK) | ~rst_l)
blk_st_cnt3 <= 4'h0;
else if(pcx3_req_pq_d1 & (spc3_pcx_data_pa[122:118] == `STORE_RQ) & spc3_pcx_data_pa[109] & spc3_pcx_data_pa[110])
blk_st_cnt3 <= blk_st_cnt3 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(blk_st_cnt3 & (spc3_pcx_data_pa[122:118] == `STORE_RQ) & ~spc3_pcx_data_pa[109])
st_blkst_mixture3 <= 1'b1;
else if(blk_st_cnt3 == 4'h0)
st_blkst_mixture3 <= 1'b0;
// Multiple init stores without an ACK in between
//---------------------------------------------------
if((cpx_spc3_type == `ST_ACK) | ~rst_l)
ini_st_cnt3 <= 4'h0;
else if(pcx3_req_pq_d1 & (spc3_pcx_data_pa[122:118] == `STORE_RQ) & spc3_pcx_data_pa[109] & ~spc3_pcx_data_pa[110])
ini_st_cnt3 <= ini_st_cnt3 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(ini_st_cnt3 && (spc3_pcx_data_pa[122:118] == `STORE_RQ) & ~spc3_pcx_data_pa[109])
st_inist_mixture3 <= 1'b1;
else if(ini_st_cnt3 == 4'h0)
st_inist_mixture3 <= 1'b0;
if(~rst_l)
cpx_spc3_ifill_wyvld <= 1'b0;
else
cpx_spc3_ifill_wyvld <= ((cpx_spc3_type == `IFILL_RET) & cpx_spc3_wyvld);
if(~rst_l)
cpx_spc3_dfill_wyvld <= 1'b0;
else
cpx_spc3_dfill_wyvld <= ((cpx_spc3_type == `LOAD_RET) & cpx_spc3_wyvld);
pcx4_vld_d1 <= spc4_pcx_data_pa[123];
pcx4_type_d1 <= spc4_pcx_data_pa[122:118];
pcx4_req_pq_d1 <= |spc4_pcx_req_pq;
pcx4_atom_pq_d1 <= spc4_pcx_atom_pq;
pcx4_atom_pq_d2 <= pcx4_atom_pq_d1;
// Multiple block stores without an ACK in between
//---------------------------------------------------
if((cpx_spc4_type == `ST_ACK) | ~rst_l)
blk_st_cnt4 <= 4'h0;
else if(pcx4_req_pq_d1 & (spc4_pcx_data_pa[122:118] == `STORE_RQ) & spc4_pcx_data_pa[109] & spc4_pcx_data_pa[110])
blk_st_cnt4 <= blk_st_cnt4 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(blk_st_cnt4 & (spc4_pcx_data_pa[122:118] == `STORE_RQ) & ~spc4_pcx_data_pa[109])
st_blkst_mixture4 <= 1'b1;
else if(blk_st_cnt4 == 4'h0)
st_blkst_mixture4 <= 1'b0;
// Multiple init stores without an ACK in between
//---------------------------------------------------
if((cpx_spc4_type == `ST_ACK) | ~rst_l)
ini_st_cnt4 <= 4'h0;
else if(pcx4_req_pq_d1 & (spc4_pcx_data_pa[122:118] == `STORE_RQ) & spc4_pcx_data_pa[109] & ~spc4_pcx_data_pa[110])
ini_st_cnt4 <= ini_st_cnt4 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(ini_st_cnt4 && (spc4_pcx_data_pa[122:118] == `STORE_RQ) & ~spc4_pcx_data_pa[109])
st_inist_mixture4 <= 1'b1;
else if(ini_st_cnt4 == 4'h0)
st_inist_mixture4 <= 1'b0;
if(~rst_l)
cpx_spc4_ifill_wyvld <= 1'b0;
else
cpx_spc4_ifill_wyvld <= ((cpx_spc4_type == `IFILL_RET) & cpx_spc4_wyvld);
if(~rst_l)
cpx_spc4_dfill_wyvld <= 1'b0;
else
cpx_spc4_dfill_wyvld <= ((cpx_spc4_type == `LOAD_RET) & cpx_spc4_wyvld);
pcx5_vld_d1 <= spc5_pcx_data_pa[123];
pcx5_type_d1 <= spc5_pcx_data_pa[122:118];
pcx5_req_pq_d1 <= |spc5_pcx_req_pq;
pcx5_atom_pq_d1 <= spc5_pcx_atom_pq;
pcx5_atom_pq_d2 <= pcx5_atom_pq_d1;
// Multiple block stores without an ACK in between
//---------------------------------------------------
if((cpx_spc5_type == `ST_ACK) | ~rst_l)
blk_st_cnt5 <= 4'h0;
else if(pcx5_req_pq_d1 & (spc5_pcx_data_pa[122:118] == `STORE_RQ) & spc5_pcx_data_pa[109] & spc5_pcx_data_pa[110])
blk_st_cnt5 <= blk_st_cnt5 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(blk_st_cnt5 & (spc5_pcx_data_pa[122:118] == `STORE_RQ) & ~spc5_pcx_data_pa[109])
st_blkst_mixture5 <= 1'b1;
else if(blk_st_cnt5 == 4'h0)
st_blkst_mixture5 <= 1'b0;
// Multiple init stores without an ACK in between
//---------------------------------------------------
if((cpx_spc5_type == `ST_ACK) | ~rst_l)
ini_st_cnt5 <= 4'h0;
else if(pcx5_req_pq_d1 & (spc5_pcx_data_pa[122:118] == `STORE_RQ) & spc5_pcx_data_pa[109] & ~spc5_pcx_data_pa[110])
ini_st_cnt5 <= ini_st_cnt5 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(ini_st_cnt5 && (spc5_pcx_data_pa[122:118] == `STORE_RQ) & ~spc5_pcx_data_pa[109])
st_inist_mixture5 <= 1'b1;
else if(ini_st_cnt5 == 4'h0)
st_inist_mixture5 <= 1'b0;
if(~rst_l)
cpx_spc5_ifill_wyvld <= 1'b0;
else
cpx_spc5_ifill_wyvld <= ((cpx_spc5_type == `IFILL_RET) & cpx_spc5_wyvld);
if(~rst_l)
cpx_spc5_dfill_wyvld <= 1'b0;
else
cpx_spc5_dfill_wyvld <= ((cpx_spc5_type == `LOAD_RET) & cpx_spc5_wyvld);
pcx6_vld_d1 <= spc6_pcx_data_pa[123];
pcx6_type_d1 <= spc6_pcx_data_pa[122:118];
pcx6_req_pq_d1 <= |spc6_pcx_req_pq;
pcx6_atom_pq_d1 <= spc6_pcx_atom_pq;
pcx6_atom_pq_d2 <= pcx6_atom_pq_d1;
// Multiple block stores without an ACK in between
//---------------------------------------------------
if((cpx_spc6_type == `ST_ACK) | ~rst_l)
blk_st_cnt6 <= 4'h0;
else if(pcx6_req_pq_d1 & (spc6_pcx_data_pa[122:118] == `STORE_RQ) & spc6_pcx_data_pa[109] & spc6_pcx_data_pa[110])
blk_st_cnt6 <= blk_st_cnt6 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(blk_st_cnt6 & (spc6_pcx_data_pa[122:118] == `STORE_RQ) & ~spc6_pcx_data_pa[109])
st_blkst_mixture6 <= 1'b1;
else if(blk_st_cnt6 == 4'h0)
st_blkst_mixture6 <= 1'b0;
// Multiple init stores without an ACK in between
//---------------------------------------------------
if((cpx_spc6_type == `ST_ACK) | ~rst_l)
ini_st_cnt6 <= 4'h0;
else if(pcx6_req_pq_d1 & (spc6_pcx_data_pa[122:118] == `STORE_RQ) & spc6_pcx_data_pa[109] & ~spc6_pcx_data_pa[110])
ini_st_cnt6 <= ini_st_cnt6 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(ini_st_cnt6 && (spc6_pcx_data_pa[122:118] == `STORE_RQ) & ~spc6_pcx_data_pa[109])
st_inist_mixture6 <= 1'b1;
else if(ini_st_cnt6 == 4'h0)
st_inist_mixture6 <= 1'b0;
if(~rst_l)
cpx_spc6_ifill_wyvld <= 1'b0;
else
cpx_spc6_ifill_wyvld <= ((cpx_spc6_type == `IFILL_RET) & cpx_spc6_wyvld);
if(~rst_l)
cpx_spc6_dfill_wyvld <= 1'b0;
else
cpx_spc6_dfill_wyvld <= ((cpx_spc6_type == `LOAD_RET) & cpx_spc6_wyvld);
pcx7_vld_d1 <= spc7_pcx_data_pa[123];
pcx7_type_d1 <= spc7_pcx_data_pa[122:118];
pcx7_req_pq_d1 <= |spc7_pcx_req_pq;
pcx7_atom_pq_d1 <= spc7_pcx_atom_pq;
pcx7_atom_pq_d2 <= pcx7_atom_pq_d1;
// Multiple block stores without an ACK in between
//---------------------------------------------------
if((cpx_spc7_type == `ST_ACK) | ~rst_l)
blk_st_cnt7 <= 4'h0;
else if(pcx7_req_pq_d1 & (spc7_pcx_data_pa[122:118] == `STORE_RQ) & spc7_pcx_data_pa[109] & spc7_pcx_data_pa[110])
blk_st_cnt7 <= blk_st_cnt7 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(blk_st_cnt7 & (spc7_pcx_data_pa[122:118] == `STORE_RQ) & ~spc7_pcx_data_pa[109])
st_blkst_mixture7 <= 1'b1;
else if(blk_st_cnt7 == 4'h0)
st_blkst_mixture7 <= 1'b0;
// Multiple init stores without an ACK in between
//---------------------------------------------------
if((cpx_spc7_type == `ST_ACK) | ~rst_l)
ini_st_cnt7 <= 4'h0;
else if(pcx7_req_pq_d1 & (spc7_pcx_data_pa[122:118] == `STORE_RQ) & spc7_pcx_data_pa[109] & ~spc7_pcx_data_pa[110])
ini_st_cnt7 <= ini_st_cnt7 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(ini_st_cnt7 && (spc7_pcx_data_pa[122:118] == `STORE_RQ) & ~spc7_pcx_data_pa[109])
st_inist_mixture7 <= 1'b1;
else if(ini_st_cnt7 == 4'h0)
st_inist_mixture7 <= 1'b0;
if(~rst_l)
cpx_spc7_ifill_wyvld <= 1'b0;
else
cpx_spc7_ifill_wyvld <= ((cpx_spc7_type == `IFILL_RET) & cpx_spc7_wyvld);
if(~rst_l)
cpx_spc7_dfill_wyvld <= 1'b0;
else
cpx_spc7_dfill_wyvld <= ((cpx_spc7_type == `LOAD_RET) & cpx_spc7_wyvld);
end
wire ifill_wyvld = cpx_spc0_ifill_wyvld;
wire dfill_wyvld = cpx_spc0_dfill_wyvld;
always @(negedge clk)
begin
if (rst_l & (^spc0_pcx_req_pq === 1'bx))
finish_test("spc", "pcx_req_pq has X-s", 0);
else if(rst_l & pcx0_req_pq_d1)
get_pcx( spc0_pcx_type_str, spc0_pcx_data_pa, pcx0_type_d1,
pcx0_atom_pq_d1, pcx0_atom_pq_d2, 3'h0, pcx0_req_pq_d1);
if (rst_l & (^spc1_pcx_req_pq === 1'bx))
finish_test("spc", "pcx_req_pq has X-s", 1);
else if(rst_l & pcx1_req_pq_d1)
get_pcx( spc1_pcx_type_str, spc1_pcx_data_pa, pcx1_type_d1,
pcx1_atom_pq_d1, pcx1_atom_pq_d2, 3'h1, pcx1_req_pq_d1);
if (rst_l & (^spc2_pcx_req_pq === 1'bx))
finish_test("spc", "pcx_req_pq has X-s", 2);
else if(rst_l & pcx2_req_pq_d1)
get_pcx( spc2_pcx_type_str, spc2_pcx_data_pa, pcx2_type_d1,
pcx2_atom_pq_d1, pcx2_atom_pq_d2, 3'h2, pcx2_req_pq_d1);
if (rst_l & (^spc3_pcx_req_pq === 1'bx))
finish_test("spc", "pcx_req_pq has X-s", 3);
else if(rst_l & pcx3_req_pq_d1)
get_pcx( spc3_pcx_type_str, spc3_pcx_data_pa, pcx3_type_d1,
pcx3_atom_pq_d1, pcx3_atom_pq_d2, 3'h3, pcx3_req_pq_d1);
if (rst_l & (^spc4_pcx_req_pq === 1'bx))
finish_test("spc", "pcx_req_pq has X-s", 4);
else if(rst_l & pcx4_req_pq_d1)
get_pcx( spc4_pcx_type_str, spc4_pcx_data_pa, pcx4_type_d1,
pcx4_atom_pq_d1, pcx4_atom_pq_d2, 3'h4, pcx4_req_pq_d1);
if (rst_l & (^spc5_pcx_req_pq === 1'bx))
finish_test("spc", "pcx_req_pq has X-s", 5);
else if(rst_l & pcx5_req_pq_d1)
get_pcx( spc5_pcx_type_str, spc5_pcx_data_pa, pcx5_type_d1,
pcx5_atom_pq_d1, pcx5_atom_pq_d2, 3'h5, pcx5_req_pq_d1);
if (rst_l & (^spc6_pcx_req_pq === 1'bx))
finish_test("spc", "pcx_req_pq has X-s", 6);
else if(rst_l & pcx6_req_pq_d1)
get_pcx( spc6_pcx_type_str, spc6_pcx_data_pa, pcx6_type_d1,
pcx6_atom_pq_d1, pcx6_atom_pq_d2, 3'h6, pcx6_req_pq_d1);
if (rst_l & (^spc7_pcx_req_pq === 1'bx))
finish_test("spc", "pcx_req_pq has X-s", 7);
else if(rst_l & pcx7_req_pq_d1)
get_pcx( spc7_pcx_type_str, spc7_pcx_data_pa, pcx7_type_d1,
pcx7_atom_pq_d1, pcx7_atom_pq_d2, 3'h7, pcx7_req_pq_d1);
end
//----------------------------------------------------------------------------------------
// This section deals with the sctag to cpx packets
// All the info signals are just for usage by the tso coverage vera objects
//----------------------------------------------------------------------------------------
reg [3:0] sctag0_valid_spcs;
reg [3:0] cpx0_inv_fanout;
reg [3:0] sctag1_valid_spcs;
reg [3:0] cpx1_inv_fanout;
reg [3:0] sctag2_valid_spcs;
reg [3:0] cpx2_inv_fanout;
reg [3:0] sctag3_valid_spcs;
reg [3:0] cpx3_inv_fanout;
reg [3:0] sctag4_valid_spcs;
reg [3:0] cpx4_inv_fanout;
reg [3:0] sctag5_valid_spcs;
reg [3:0] cpx5_inv_fanout;
reg [3:0] sctag6_valid_spcs;
reg [3:0] cpx6_inv_fanout;
reg [3:0] sctag7_valid_spcs;
reg [3:0] cpx7_inv_fanout;
reg multiple_inv01;
reg multiple_inv01_multiple_fanout;
reg multiple_inv0123;
reg multiple_inv0123_multiple_fanout;
wire [3:0] multiple_fanout_info = { multiple_inv01_multiple_fanout, multiple_inv01,
multiple_inv0123_multiple_fanout, multiple_inv0123};
always @(posedge clk)
begin
sctag0_cpx_req_cq_d1 <= sctag0_cpx_req_cq;
sctag0_cpx_atom_cq_d1 <= sctag0_cpx_atom_cq;
sctag0_cpx_atom_cq_d2 <= sctag0_cpx_atom_cq_d1;
sctag1_cpx_req_cq_d1 <= sctag1_cpx_req_cq;
sctag1_cpx_atom_cq_d1 <= sctag1_cpx_atom_cq;
sctag1_cpx_atom_cq_d2 <= sctag1_cpx_atom_cq_d1;
sctag2_cpx_req_cq_d1 <= sctag2_cpx_req_cq;
sctag2_cpx_atom_cq_d1 <= sctag2_cpx_atom_cq;
sctag2_cpx_atom_cq_d2 <= sctag2_cpx_atom_cq_d1;
sctag3_cpx_req_cq_d1 <= sctag3_cpx_req_cq;
sctag3_cpx_atom_cq_d1 <= sctag3_cpx_atom_cq;
sctag3_cpx_atom_cq_d2 <= sctag3_cpx_atom_cq_d1;
end
always @(negedge clk)
begin
if(rst_l)
begin
get_sctag_cpx(sctag0_cpx_type, sctag0_cpx_type_str, sctag0_cpx_req_cq_d1, sctag0_cpx_data_ca, 3'h0);
sctag0_valid_spcs =
sctag0_cpx_req_cq_d1[0] + sctag0_cpx_req_cq_d1[1] + sctag0_cpx_req_cq_d1[2] +
sctag0_cpx_req_cq_d1[3] + sctag0_cpx_req_cq_d1[4] + sctag0_cpx_req_cq_d1[5] +
sctag0_cpx_req_cq_d1[6] + sctag0_cpx_req_cq_d1[7];
if((sctag0_valid_spcs > 0) &
((sctag0_cpx_type == `ST_ACK) | (sctag0_cpx_type == `STRST_ACK) | (sctag0_cpx_type == `EVICT_REQ)))
begin
cpx0_inv_fanout = sctag0_valid_spcs;
if(tso_mon_msg) $display("%0d tso_mon: sctag0 invalidation to multiple cores %d", $time, cpx0_inv_fanout);
end
else
begin
cpx0_inv_fanout = 4'h0;
end
sctag0_dc_lkup_c5 <= |sctag0_dc_lkup_panel_dec_c4 & |sctag0_dc_lkup_row_dec_c4;
sctag0_ic_lkup_c5 <= |sctag0_ic_lkup_panel_dec_c4 & |sctag0_ic_lkup_row_dec_c4;
sctag0_dc_lkup_c6 <= sctag0_dc_lkup_c5;
sctag0_ic_lkup_c6 <= sctag0_ic_lkup_c5;
// THESE ARE ACTUALLY CHECKERS - THEY ARE IMPORTANT - CAUGHT A FEW BUGS
//----------------------------------------------------------------------
if(sctag0_ic_lkup_c6)
begin
if(sctag0_ic_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
end
if(sctag0_dc_lkup_c6)
begin
if(sctag0_dc_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble8_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble9_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble10_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble11_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble12_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble13_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble14_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble15_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble24_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble25_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble26_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble27_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble28_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble29_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble30_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble31_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
end
if(sctag0_ic_lkup_c6 & sctag0_dc_lkup_c6)
begin
if(sctag0_both_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
end
get_sctag_cpx(sctag1_cpx_type, sctag1_cpx_type_str, sctag1_cpx_req_cq_d1, sctag1_cpx_data_ca, 3'h1);
sctag1_valid_spcs =
sctag1_cpx_req_cq_d1[0] + sctag1_cpx_req_cq_d1[1] + sctag1_cpx_req_cq_d1[2] +
sctag1_cpx_req_cq_d1[3] + sctag1_cpx_req_cq_d1[4] + sctag1_cpx_req_cq_d1[5] +
sctag1_cpx_req_cq_d1[6] + sctag1_cpx_req_cq_d1[7];
if((sctag1_valid_spcs > 0) &
((sctag1_cpx_type == `ST_ACK) | (sctag1_cpx_type == `STRST_ACK) | (sctag1_cpx_type == `EVICT_REQ)))
begin
cpx1_inv_fanout = sctag1_valid_spcs;
if(tso_mon_msg) $display("%0d tso_mon: sctag1 invalidation to multiple cores %d", $time, cpx1_inv_fanout);
end
else
begin
cpx1_inv_fanout = 4'h0;
end
sctag1_dc_lkup_c5 <= |sctag1_dc_lkup_panel_dec_c4 & |sctag1_dc_lkup_row_dec_c4;
sctag1_ic_lkup_c5 <= |sctag1_ic_lkup_panel_dec_c4 & |sctag1_ic_lkup_row_dec_c4;
sctag1_dc_lkup_c6 <= sctag1_dc_lkup_c5;
sctag1_ic_lkup_c6 <= sctag1_ic_lkup_c5;
// THESE ARE ACTUALLY CHECKERS - THEY ARE IMPORTANT - CAUGHT A FEW BUGS
//----------------------------------------------------------------------
if(sctag1_ic_lkup_c6)
begin
if(sctag1_ic_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
end
if(sctag1_dc_lkup_c6)
begin
if(sctag1_dc_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble8_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble9_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble10_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble11_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble12_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble13_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble14_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble15_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble24_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble25_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble26_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble27_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble28_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble29_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble30_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble31_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
end
if(sctag1_ic_lkup_c6 & sctag1_dc_lkup_c6)
begin
if(sctag1_both_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
end
get_sctag_cpx(sctag2_cpx_type, sctag2_cpx_type_str, sctag2_cpx_req_cq_d1, sctag2_cpx_data_ca, 3'h2);
sctag2_valid_spcs =
sctag2_cpx_req_cq_d1[0] + sctag2_cpx_req_cq_d1[1] + sctag2_cpx_req_cq_d1[2] +
sctag2_cpx_req_cq_d1[3] + sctag2_cpx_req_cq_d1[4] + sctag2_cpx_req_cq_d1[5] +
sctag2_cpx_req_cq_d1[6] + sctag2_cpx_req_cq_d1[7];
if((sctag2_valid_spcs > 0) &
((sctag2_cpx_type == `ST_ACK) | (sctag2_cpx_type == `STRST_ACK) | (sctag2_cpx_type == `EVICT_REQ)))
begin
cpx2_inv_fanout = sctag2_valid_spcs;
if(tso_mon_msg) $display("%0d tso_mon: sctag2 invalidation to multiple cores %d", $time, cpx2_inv_fanout);
end
else
begin
cpx2_inv_fanout = 4'h0;
end
sctag2_dc_lkup_c5 <= |sctag2_dc_lkup_panel_dec_c4 & |sctag2_dc_lkup_row_dec_c4;
sctag2_ic_lkup_c5 <= |sctag2_ic_lkup_panel_dec_c4 & |sctag2_ic_lkup_row_dec_c4;
sctag2_dc_lkup_c6 <= sctag2_dc_lkup_c5;
sctag2_ic_lkup_c6 <= sctag2_ic_lkup_c5;
// THESE ARE ACTUALLY CHECKERS - THEY ARE IMPORTANT - CAUGHT A FEW BUGS
//----------------------------------------------------------------------
if(sctag2_ic_lkup_c6)
begin
if(sctag2_ic_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
end
if(sctag2_dc_lkup_c6)
begin
if(sctag2_dc_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble8_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble9_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble10_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble11_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble12_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble13_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble14_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble15_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble24_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble25_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble26_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble27_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble28_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble29_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble30_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble31_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
end
if(sctag2_ic_lkup_c6 & sctag2_dc_lkup_c6)
begin
if(sctag2_both_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
end
get_sctag_cpx(sctag3_cpx_type, sctag3_cpx_type_str, sctag3_cpx_req_cq_d1, sctag3_cpx_data_ca, 3'h3);
sctag3_valid_spcs =
sctag3_cpx_req_cq_d1[0] + sctag3_cpx_req_cq_d1[1] + sctag3_cpx_req_cq_d1[2] +
sctag3_cpx_req_cq_d1[3] + sctag3_cpx_req_cq_d1[4] + sctag3_cpx_req_cq_d1[5] +
sctag3_cpx_req_cq_d1[6] + sctag3_cpx_req_cq_d1[7];
if((sctag3_valid_spcs > 0) &
((sctag3_cpx_type == `ST_ACK) | (sctag3_cpx_type == `STRST_ACK) | (sctag3_cpx_type == `EVICT_REQ)))
begin
cpx3_inv_fanout = sctag3_valid_spcs;
if(tso_mon_msg) $display("%0d tso_mon: sctag3 invalidation to multiple cores %d", $time, cpx3_inv_fanout);
end
else
begin
cpx3_inv_fanout = 4'h0;
end
sctag3_dc_lkup_c5 <= |sctag3_dc_lkup_panel_dec_c4 & |sctag3_dc_lkup_row_dec_c4;
sctag3_ic_lkup_c5 <= |sctag3_ic_lkup_panel_dec_c4 & |sctag3_ic_lkup_row_dec_c4;
sctag3_dc_lkup_c6 <= sctag3_dc_lkup_c5;
sctag3_ic_lkup_c6 <= sctag3_ic_lkup_c5;
// THESE ARE ACTUALLY CHECKERS - THEY ARE IMPORTANT - CAUGHT A FEW BUGS
//----------------------------------------------------------------------
if(sctag3_ic_lkup_c6)
begin
if(sctag3_ic_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
end
if(sctag3_dc_lkup_c6)
begin
if(sctag3_dc_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble8_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble9_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble10_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble11_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble12_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble13_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble14_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble15_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble24_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble25_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble26_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble27_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble28_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble29_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble30_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble31_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
end
if(sctag3_ic_lkup_c6 & sctag3_dc_lkup_c6)
begin
if(sctag3_both_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
end
end // of if(rst_l)
else
begin
sctag0_dc_lkup_c5 <= 1'b0;
sctag0_ic_lkup_c5 <= 1'b0;
sctag0_dc_lkup_c6 <= 1'b0;
sctag0_ic_lkup_c6 <= 1'b0;
sctag1_dc_lkup_c5 <= 1'b0;
sctag1_ic_lkup_c5 <= 1'b0;
sctag1_dc_lkup_c6 <= 1'b0;
sctag1_ic_lkup_c6 <= 1'b0;
sctag2_dc_lkup_c5 <= 1'b0;
sctag2_ic_lkup_c5 <= 1'b0;
sctag2_dc_lkup_c6 <= 1'b0;
sctag2_ic_lkup_c6 <= 1'b0;
sctag3_dc_lkup_c5 <= 1'b0;
sctag3_ic_lkup_c5 <= 1'b0;
sctag3_dc_lkup_c6 <= 1'b0;
sctag3_ic_lkup_c6 <= 1'b0;
end // of else
end // of always
always @(negedge clk)
begin
if(rst_l)
begin
if(cpx0_inv_fanout && cpx1_inv_fanout)
begin
multiple_inv01 = 1'b1;
if((cpx0_inv_fanout>1) && (cpx1_inv_fanout > 1))
multiple_inv01_multiple_fanout = 1'b1;
end
else
begin
multiple_inv01 = 1'b0;
multiple_inv01_multiple_fanout = 1'b0;
end
if(cpx0_inv_fanout && cpx1_inv_fanout && cpx2_inv_fanout && cpx3_inv_fanout)
begin
multiple_inv0123 = 1'b1;
if((cpx0_inv_fanout>1) && (cpx1_inv_fanout>1) && (cpx2_inv_fanout>1) && (cpx3_inv_fanout>1))
multiple_inv0123_multiple_fanout = 1'b1;
end
else
begin
multiple_inv0123 = 1'b0;
multiple_inv0123_multiple_fanout = 1'b0;
end
end // of if(rst_l)
end // of always
//----------------------------------------------------------------------------------------
// This section deals with the cpx to spc packets
//----------------------------------------------------------------------------------------
always @(posedge clk)
begin
if(cpx_spc0_data_vld & (cpx_spc0_type == `LOAD_RET) & cpx_spc0_data_cx2[129])
begin
atomic_ret0 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: atomic_ret0 = 1");
end
else if(cpx_spc0_data_vld & (cpx_spc0_type == `ST_ACK) & cpx_spc0_data_cx2[129])
begin
atomic_ret0 <= 1'b0;
if(tso_mon_msg) $display("tso_mon: atomic_ret0 = 0");
end
if(atomic_ret0 & cpx_spc0_data_vld & ~(cpx_spc0_type == `ST_ACK))
begin
non_b2b_atomic_ret0 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: non_b2b_atomic_ret0");
end
else
non_b2b_atomic_ret0 <= 1'b0;
if(cpx_spc1_data_vld & (cpx_spc1_type == `LOAD_RET) & cpx_spc1_data_cx2[129])
begin
atomic_ret1 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: atomic_ret1 = 1");
end
else if(cpx_spc1_data_vld & (cpx_spc1_type == `ST_ACK) & cpx_spc1_data_cx2[129])
begin
atomic_ret1 <= 1'b0;
if(tso_mon_msg) $display("tso_mon: atomic_ret1 = 0");
end
if(atomic_ret1 & cpx_spc1_data_vld & ~(cpx_spc1_type == `ST_ACK))
begin
non_b2b_atomic_ret1 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: non_b2b_atomic_ret0");
end
else
non_b2b_atomic_ret1 <= 1'b0;
if(cpx_spc2_data_vld & (cpx_spc2_type == `LOAD_RET) & cpx_spc2_data_cx2[129])
begin
atomic_ret2 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: atomic_ret2 = 1");
end
else if(cpx_spc2_data_vld & (cpx_spc2_type == `ST_ACK) & cpx_spc2_data_cx2[129])
begin
atomic_ret2 <= 1'b0;
if(tso_mon_msg) $display("tso_mon: atomic_ret2 = 0");
end
if(atomic_ret2 & cpx_spc2_data_vld & ~(cpx_spc2_type == `ST_ACK))
begin
non_b2b_atomic_ret2 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: non_b2b_atomic_ret0");
end
else
non_b2b_atomic_ret2 <= 1'b0;
if(cpx_spc3_data_vld & (cpx_spc3_type == `LOAD_RET) & cpx_spc3_data_cx2[129])
begin
atomic_ret3 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: atomic_ret3 = 1");
end
else if(cpx_spc3_data_vld & (cpx_spc3_type == `ST_ACK) & cpx_spc3_data_cx2[129])
begin
atomic_ret3 <= 1'b0;
if(tso_mon_msg) $display("tso_mon: atomic_ret3 = 0");
end
if(atomic_ret3 & cpx_spc3_data_vld & ~(cpx_spc3_type == `ST_ACK))
begin
non_b2b_atomic_ret3 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: non_b2b_atomic_ret0");
end
else
non_b2b_atomic_ret3 <= 1'b0;
if(cpx_spc4_data_vld & (cpx_spc4_type == `LOAD_RET) & cpx_spc4_data_cx2[129])
begin
atomic_ret4 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: atomic_ret4 = 1");
end
else if(cpx_spc4_data_vld & (cpx_spc4_type == `ST_ACK) & cpx_spc4_data_cx2[129])
begin
atomic_ret4 <= 1'b0;
if(tso_mon_msg) $display("tso_mon: atomic_ret4 = 0");
end
if(atomic_ret4 & cpx_spc4_data_vld & ~(cpx_spc4_type == `ST_ACK))
begin
non_b2b_atomic_ret4 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: non_b2b_atomic_ret0");
end
else
non_b2b_atomic_ret4 <= 1'b0;
if(cpx_spc5_data_vld & (cpx_spc5_type == `LOAD_RET) & cpx_spc5_data_cx2[129])
begin
atomic_ret5 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: atomic_ret5 = 1");
end
else if(cpx_spc5_data_vld & (cpx_spc5_type == `ST_ACK) & cpx_spc5_data_cx2[129])
begin
atomic_ret5 <= 1'b0;
if(tso_mon_msg) $display("tso_mon: atomic_ret5 = 0");
end
if(atomic_ret5 & cpx_spc5_data_vld & ~(cpx_spc5_type == `ST_ACK))
begin
non_b2b_atomic_ret5 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: non_b2b_atomic_ret0");
end
else
non_b2b_atomic_ret5 <= 1'b0;
if(cpx_spc6_data_vld & (cpx_spc6_type == `LOAD_RET) & cpx_spc6_data_cx2[129])
begin
atomic_ret6 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: atomic_ret6 = 1");
end
else if(cpx_spc6_data_vld & (cpx_spc6_type == `ST_ACK) & cpx_spc6_data_cx2[129])
begin
atomic_ret6 <= 1'b0;
if(tso_mon_msg) $display("tso_mon: atomic_ret6 = 0");
end
if(atomic_ret6 & cpx_spc6_data_vld & ~(cpx_spc6_type == `ST_ACK))
begin
non_b2b_atomic_ret6 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: non_b2b_atomic_ret0");
end
else
non_b2b_atomic_ret6 <= 1'b0;
if(cpx_spc7_data_vld & (cpx_spc7_type == `LOAD_RET) & cpx_spc7_data_cx2[129])
begin
atomic_ret7 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: atomic_ret7 = 1");
end
else if(cpx_spc7_data_vld & (cpx_spc7_type == `ST_ACK) & cpx_spc7_data_cx2[129])
begin
atomic_ret7 <= 1'b0;
if(tso_mon_msg) $display("tso_mon: atomic_ret7 = 0");
end
if(atomic_ret7 & cpx_spc7_data_vld & ~(cpx_spc7_type == `ST_ACK))
begin
non_b2b_atomic_ret7 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: non_b2b_atomic_ret0");
end
else
non_b2b_atomic_ret7 <= 1'b0;
end
always @(negedge clk)
begin
if(rst_l)
begin
if(cpx_spc0_data_vld)
get_cpx_spc(cpx_spc0_type_str, cpx_spc0_type);
if(tso_mon_msg)
$display("%0d:Info cpx-to-spc%d packet TYPE= %s data= %x", $time, 0, cpx_spc0_type_str, cpx_spc0_data_cx2[127:0]);
if(cpx_spc1_data_vld)
get_cpx_spc(cpx_spc1_type_str, cpx_spc1_type);
if(tso_mon_msg)
$display("%0d:Info cpx-to-spc%d packet TYPE= %s data= %x", $time, 1, cpx_spc1_type_str, cpx_spc1_data_cx2[127:0]);
if(cpx_spc2_data_vld)
get_cpx_spc(cpx_spc2_type_str, cpx_spc2_type);
if(tso_mon_msg)
$display("%0d:Info cpx-to-spc%d packet TYPE= %s data= %x", $time, 2, cpx_spc2_type_str, cpx_spc2_data_cx2[127:0]);
if(cpx_spc3_data_vld)
get_cpx_spc(cpx_spc3_type_str, cpx_spc3_type);
if(tso_mon_msg)
$display("%0d:Info cpx-to-spc%d packet TYPE= %s data= %x", $time, 3, cpx_spc3_type_str, cpx_spc3_data_cx2[127:0]);
if(cpx_spc4_data_vld)
get_cpx_spc(cpx_spc4_type_str, cpx_spc4_type);
if(tso_mon_msg)
$display("%0d:Info cpx-to-spc%d packet TYPE= %s data= %x", $time, 4, cpx_spc4_type_str, cpx_spc4_data_cx2[127:0]);
if(cpx_spc5_data_vld)
get_cpx_spc(cpx_spc5_type_str, cpx_spc5_type);
if(tso_mon_msg)
$display("%0d:Info cpx-to-spc%d packet TYPE= %s data= %x", $time, 5, cpx_spc5_type_str, cpx_spc5_data_cx2[127:0]);
if(cpx_spc6_data_vld)
get_cpx_spc(cpx_spc6_type_str, cpx_spc6_type);
if(tso_mon_msg)
$display("%0d:Info cpx-to-spc%d packet TYPE= %s data= %x", $time, 6, cpx_spc6_type_str, cpx_spc6_data_cx2[127:0]);
if(cpx_spc7_data_vld)
get_cpx_spc(cpx_spc7_type_str, cpx_spc7_type);
if(tso_mon_msg)
$display("%0d:Info cpx-to-spc%d packet TYPE= %s data= %x", $time, 7, cpx_spc7_type_str, cpx_spc7_data_cx2[127:0]);
end // of rst_l
end
//==============================================================================
// L2 stuff
//==============================================================================
//==============================================================================
// This is stuff related to the L2 tags queues. Measure fullness and high-water mark
// The queus are - miss buffer, output q, input q, fill buffer, write back buffer
// rdma (write) q and snoop q.
//==============================================================================
wire [4:0] sctag0_mb_count = `TOP_MEMORY.sctag0.mbctl.mb_count_c4[4:0];
wire [4:0] sctag0_oq_count = `TOP_MEMORY.sctag0.oqctl.oq_count_p[4:0];
wire [4:0] sctag0_iq_count = `TOP_MEMORY.sctag0.iqctl.que_cnt[4:0];
wire [3:0] sctag0_fb_count = `TOP_MEMORY.sctag0.fbctl.fb_count[3:0];
wire [3:0] sctag0_wb_count = `TOP_MEMORY.sctag0.wbctl.wb_count[3:0];
wire [3:0] sctag0_rdma_valid = `TOP_MEMORY.sctag0.rdmatctl.rdma_valid[3:0];
wire [1:0] sctag0_snpq_valid = `TOP_MEMORY.sctag0.snpctl.snpq_valid[1:0];
wire sctag0_mb_full = (sctag0_mb_count == 5'd16);
wire sctag0_mb_hwm = (sctag0_mb_count >= 5'd12);
wire sctag0_oq_full = (sctag0_oq_count == 5'd16);
wire sctag0_oq_hwm = (sctag0_oq_count >= 5'd01);
wire sctag0_iq_full = (sctag0_iq_count == 5'd16);
wire sctag0_iq_hwm = (sctag0_iq_count >= 5'd11);
wire sctag0_fb_full = (sctag0_fb_count == 4'd8);
wire sctag0_fb_hwm = (sctag0_fb_count >= 4'd7);
wire sctag0_wb_full = (sctag0_wb_count == 4'd8);
wire sctag0_wb_hwm = (sctag0_wb_count >= 4'd1);
wire sctag0_rdma_full = (sctag0_rdma_valid == 4'b1111);
wire sctag0_snpq_full = (sctag0_snpq_valid == 2'b11);
wire [1:0] sctag0_mb_info = {sctag0_mb_full, sctag0_mb_hwm};
wire [1:0] sctag0_oq_info = {sctag0_oq_full, sctag0_oq_hwm};
wire [1:0] sctag0_iq_info = {sctag0_iq_full, sctag0_iq_hwm};
wire [1:0] sctag0_fb_info = {sctag0_fb_full, sctag0_fb_hwm};
wire [1:0] sctag0_wb_info = {sctag0_wb_full, sctag0_wb_hwm};
wire [4:0] sctag1_mb_count = `TOP_MEMORY.sctag1.mbctl.mb_count_c4[4:0];
wire [4:0] sctag1_oq_count = `TOP_MEMORY.sctag1.oqctl.oq_count_p[4:0];
wire [4:0] sctag1_iq_count = `TOP_MEMORY.sctag1.iqctl.que_cnt[4:0];
wire [3:0] sctag1_fb_count = `TOP_MEMORY.sctag1.fbctl.fb_count[3:0];
wire [3:0] sctag1_wb_count = `TOP_MEMORY.sctag1.wbctl.wb_count[3:0];
wire [3:0] sctag1_rdma_valid = `TOP_MEMORY.sctag1.rdmatctl.rdma_valid[3:0];
wire [1:0] sctag1_snpq_valid = `TOP_MEMORY.sctag1.snpctl.snpq_valid[1:0];
wire sctag1_mb_full = (sctag1_mb_count == 5'd16);
wire sctag1_mb_hwm = (sctag1_mb_count >= 5'd12);
wire sctag1_oq_full = (sctag1_oq_count == 5'd16);
wire sctag1_oq_hwm = (sctag1_oq_count >= 5'd01);
wire sctag1_iq_full = (sctag1_iq_count == 5'd16);
wire sctag1_iq_hwm = (sctag1_iq_count >= 5'd11);
wire sctag1_fb_full = (sctag1_fb_count == 4'd8);
wire sctag1_fb_hwm = (sctag1_fb_count >= 4'd7);
wire sctag1_wb_full = (sctag1_wb_count == 4'd8);
wire sctag1_wb_hwm = (sctag1_wb_count >= 4'd1);
wire sctag1_rdma_full = (sctag1_rdma_valid == 4'b1111);
wire sctag1_snpq_full = (sctag1_snpq_valid == 2'b11);
wire [1:0] sctag1_mb_info = {sctag1_mb_full, sctag1_mb_hwm};
wire [1:0] sctag1_oq_info = {sctag1_oq_full, sctag1_oq_hwm};
wire [1:0] sctag1_iq_info = {sctag1_iq_full, sctag1_iq_hwm};
wire [1:0] sctag1_fb_info = {sctag1_fb_full, sctag1_fb_hwm};
wire [1:0] sctag1_wb_info = {sctag1_wb_full, sctag1_wb_hwm};
wire [4:0] sctag2_mb_count = `TOP_MEMORY.sctag2.mbctl.mb_count_c4[4:0];
wire [4:0] sctag2_oq_count = `TOP_MEMORY.sctag2.oqctl.oq_count_p[4:0];
wire [4:0] sctag2_iq_count = `TOP_MEMORY.sctag2.iqctl.que_cnt[4:0];
wire [3:0] sctag2_fb_count = `TOP_MEMORY.sctag2.fbctl.fb_count[3:0];
wire [3:0] sctag2_wb_count = `TOP_MEMORY.sctag2.wbctl.wb_count[3:0];
wire [3:0] sctag2_rdma_valid = `TOP_MEMORY.sctag2.rdmatctl.rdma_valid[3:0];
wire [1:0] sctag2_snpq_valid = `TOP_MEMORY.sctag2.snpctl.snpq_valid[1:0];
wire sctag2_mb_full = (sctag2_mb_count == 5'd16);
wire sctag2_mb_hwm = (sctag2_mb_count >= 5'd12);
wire sctag2_oq_full = (sctag2_oq_count == 5'd16);
wire sctag2_oq_hwm = (sctag2_oq_count >= 5'd01);
wire sctag2_iq_full = (sctag2_iq_count == 5'd16);
wire sctag2_iq_hwm = (sctag2_iq_count >= 5'd11);
wire sctag2_fb_full = (sctag2_fb_count == 4'd8);
wire sctag2_fb_hwm = (sctag2_fb_count >= 4'd7);
wire sctag2_wb_full = (sctag2_wb_count == 4'd8);
wire sctag2_wb_hwm = (sctag2_wb_count >= 4'd1);
wire sctag2_rdma_full = (sctag2_rdma_valid == 4'b1111);
wire sctag2_snpq_full = (sctag2_snpq_valid == 2'b11);
wire [1:0] sctag2_mb_info = {sctag2_mb_full, sctag2_mb_hwm};
wire [1:0] sctag2_oq_info = {sctag2_oq_full, sctag2_oq_hwm};
wire [1:0] sctag2_iq_info = {sctag2_iq_full, sctag2_iq_hwm};
wire [1:0] sctag2_fb_info = {sctag2_fb_full, sctag2_fb_hwm};
wire [1:0] sctag2_wb_info = {sctag2_wb_full, sctag2_wb_hwm};
wire [4:0] sctag3_mb_count = `TOP_MEMORY.sctag3.mbctl.mb_count_c4[4:0];
wire [4:0] sctag3_oq_count = `TOP_MEMORY.sctag3.oqctl.oq_count_p[4:0];
wire [4:0] sctag3_iq_count = `TOP_MEMORY.sctag3.iqctl.que_cnt[4:0];
wire [3:0] sctag3_fb_count = `TOP_MEMORY.sctag3.fbctl.fb_count[3:0];
wire [3:0] sctag3_wb_count = `TOP_MEMORY.sctag3.wbctl.wb_count[3:0];
wire [3:0] sctag3_rdma_valid = `TOP_MEMORY.sctag3.rdmatctl.rdma_valid[3:0];
wire [1:0] sctag3_snpq_valid = `TOP_MEMORY.sctag3.snpctl.snpq_valid[1:0];
wire sctag3_mb_full = (sctag3_mb_count == 5'd16);
wire sctag3_mb_hwm = (sctag3_mb_count >= 5'd12);
wire sctag3_oq_full = (sctag3_oq_count == 5'd16);
wire sctag3_oq_hwm = (sctag3_oq_count >= 5'd01);
wire sctag3_iq_full = (sctag3_iq_count == 5'd16);
wire sctag3_iq_hwm = (sctag3_iq_count >= 5'd11);
wire sctag3_fb_full = (sctag3_fb_count == 4'd8);
wire sctag3_fb_hwm = (sctag3_fb_count >= 4'd7);
wire sctag3_wb_full = (sctag3_wb_count == 4'd8);
wire sctag3_wb_hwm = (sctag3_wb_count >= 4'd1);
wire sctag3_rdma_full = (sctag3_rdma_valid == 4'b1111);
wire sctag3_snpq_full = (sctag3_snpq_valid == 2'b11);
wire [1:0] sctag3_mb_info = {sctag3_mb_full, sctag3_mb_hwm};
wire [1:0] sctag3_oq_info = {sctag3_oq_full, sctag3_oq_hwm};
wire [1:0] sctag3_iq_info = {sctag3_iq_full, sctag3_iq_hwm};
wire [1:0] sctag3_fb_info = {sctag3_fb_full, sctag3_fb_hwm};
wire [1:0] sctag3_wb_info = {sctag3_wb_full, sctag3_wb_hwm};
//==============================================================================
// L2 Miss buffer linked list stuff
// valid, young, next link, type
//==============================================================================
wire [15:0] sctag0_mb_valid = `TOP_MEMORY.sctag0.mbctl.mb_valid[15:0];
wire [15:0] sctag0_mb_young = `TOP_MEMORY.sctag0.mbctl.mb_young[15:0];
//wire [3:0] sctag0_next_link_entry0 = `TOP_MEMORY.sctag0.mbctl.next_link_entry0[3:0];
//...
//wire [3:0] sctag0_next_link_entry15 = `TOP_MEMORY.sctag0.mbctl.next_link_entry15[3:0];
wire [155:0] sctag0_mb_data_array0 = `TOP_MEMORY.sctag0.mbdata.inq_ary[0];
wire [155:0] sctag0_mb_data_array1 = `TOP_MEMORY.sctag0.mbdata.inq_ary[1];
wire [155:0] sctag0_mb_data_array2 = `TOP_MEMORY.sctag0.mbdata.inq_ary[2];
wire [155:0] sctag0_mb_data_array3 = `TOP_MEMORY.sctag0.mbdata.inq_ary[3];
wire [155:0] sctag0_mb_data_array4 = `TOP_MEMORY.sctag0.mbdata.inq_ary[4];
wire [155:0] sctag0_mb_data_array5 = `TOP_MEMORY.sctag0.mbdata.inq_ary[5];
wire [155:0] sctag0_mb_data_array6 = `TOP_MEMORY.sctag0.mbdata.inq_ary[6];
wire [155:0] sctag0_mb_data_array7 = `TOP_MEMORY.sctag0.mbdata.inq_ary[7];
wire [155:0] sctag0_mb_data_array8 = `TOP_MEMORY.sctag0.mbdata.inq_ary[8];
wire [155:0] sctag0_mb_data_array9 = `TOP_MEMORY.sctag0.mbdata.inq_ary[9];
wire [155:0] sctag0_mb_data_array10 = `TOP_MEMORY.sctag0.mbdata.inq_ary[10];
wire [155:0] sctag0_mb_data_array11 = `TOP_MEMORY.sctag0.mbdata.inq_ary[11];
wire [155:0] sctag0_mb_data_array12 = `TOP_MEMORY.sctag0.mbdata.inq_ary[12];
wire [155:0] sctag0_mb_data_array13 = `TOP_MEMORY.sctag0.mbdata.inq_ary[13];
wire [155:0] sctag0_mb_data_array14 = `TOP_MEMORY.sctag0.mbdata.inq_ary[14];
wire [155:0] sctag0_mb_data_array15 = `TOP_MEMORY.sctag0.mbdata.inq_ary[15];
//-----------------------------------------------------------------------------------------------
// look at sctag.v for L2_RDMA_HI L2_RQTYP_HI L2_RQTYP_LO and L2_RSVD
// Based ont the equation: .mb_data_write_data({57'b0,mbdata_inst_tecc_c8...
//-----------------------------------------------------------------------------------------------
wire [5:0] sctag0_mb_type0 = {sctag0_mb_data_array0 [77], sctag0_mb_data_array0 [83:79]};
wire [5:0] sctag0_mb_type1 = {sctag0_mb_data_array1 [77], sctag0_mb_data_array1 [83:79]};
wire [5:0] sctag0_mb_type2 = {sctag0_mb_data_array2 [77], sctag0_mb_data_array2 [83:79]};
wire [5:0] sctag0_mb_type3 = {sctag0_mb_data_array3 [77], sctag0_mb_data_array3 [83:79]};
wire [5:0] sctag0_mb_type4 = {sctag0_mb_data_array4 [77], sctag0_mb_data_array4 [83:79]};
wire [5:0] sctag0_mb_type5 = {sctag0_mb_data_array5 [77], sctag0_mb_data_array5 [83:79]};
wire [5:0] sctag0_mb_type6 = {sctag0_mb_data_array6 [77], sctag0_mb_data_array6 [83:79]};
wire [5:0] sctag0_mb_type7 = {sctag0_mb_data_array7 [77], sctag0_mb_data_array7 [83:79]};
wire [5:0] sctag0_mb_type8 = {sctag0_mb_data_array8 [77], sctag0_mb_data_array8 [83:79]};
wire [5:0] sctag0_mb_type9 = {sctag0_mb_data_array9 [77], sctag0_mb_data_array9 [83:79]};
wire [5:0] sctag0_mb_type10 = {sctag0_mb_data_array10[77], sctag0_mb_data_array10[83:79]};
wire [5:0] sctag0_mb_type11 = {sctag0_mb_data_array11[77], sctag0_mb_data_array11[83:79]};
wire [5:0] sctag0_mb_type12 = {sctag0_mb_data_array12[77], sctag0_mb_data_array12[83:79]};
wire [5:0] sctag0_mb_type13 = {sctag0_mb_data_array13[77], sctag0_mb_data_array13[83:79]};
wire [5:0] sctag0_mb_type14 = {sctag0_mb_data_array14[77], sctag0_mb_data_array14[83:79]};
wire [5:0] sctag0_mb_type15 = {sctag0_mb_data_array15[77], sctag0_mb_data_array15[83:79]};
//--------------------------------------------------------------
// Start figuring out what the entries are.
// bit 5 says if this is a DMA type or normal type
//--------------------------------------------------------------
wire sctag0_mb0_st_ny = sctag0_mb_valid[0] & ~sctag0_mb_young[0] & ~sctag0_mb_type0[5] & (sctag0_mb_type0[4:0] == `STORE_RQ);
wire sctag0_mb0_ld_ny = sctag0_mb_valid[0] & ~sctag0_mb_young[0] & ~sctag0_mb_type0[5] & (sctag0_mb_type0[4:0] == `LOAD_RQ);
wire sctag0_mb0_wris8_ny = sctag0_mb_valid[0] & ~sctag0_mb_young[0] & sctag0_mb_type0[5] & sctag0_mb_type0[1];
wire sctag0_mb0_wris64_ny = sctag0_mb_valid[0] & ~sctag0_mb_young[0] & sctag0_mb_type0[5] & sctag0_mb_type0[2];
wire sctag0_mb0_st_y = sctag0_mb_valid[0] & sctag0_mb_young[0] & ~sctag0_mb_type0[5] & (sctag0_mb_type0[4:0] == `STORE_RQ);
wire sctag0_mb0_ld_y = sctag0_mb_valid[0] & sctag0_mb_young[0] & ~sctag0_mb_type0[5] & (sctag0_mb_type0[4:0] == `LOAD_RQ);
wire sctag0_mb0_wris8_y = sctag0_mb_valid[0] & sctag0_mb_young[0] & sctag0_mb_type0[5] & sctag0_mb_type0[1];
wire sctag0_mb0_wris64_y = sctag0_mb_valid[0] & sctag0_mb_young[0] & sctag0_mb_type0[5] & sctag0_mb_type0[2];
wire sctag0_mb1_st_ny = sctag0_mb_valid[1] & ~sctag0_mb_young[1] & ~sctag0_mb_type1[5] & (sctag0_mb_type1[4:0] == `STORE_RQ);
wire sctag0_mb1_ld_ny = sctag0_mb_valid[1] & ~sctag0_mb_young[1] & ~sctag0_mb_type1[5] & (sctag0_mb_type1[4:0] == `LOAD_RQ);
wire sctag0_mb1_wris8_ny = sctag0_mb_valid[1] & ~sctag0_mb_young[1] & sctag0_mb_type1[5] & sctag0_mb_type1[1];
wire sctag0_mb1_wris64_ny = sctag0_mb_valid[1] & ~sctag0_mb_young[1] & sctag0_mb_type1[5] & sctag0_mb_type1[2];
wire sctag0_mb1_st_y = sctag0_mb_valid[1] & sctag0_mb_young[1] & ~sctag0_mb_type1[5] & (sctag0_mb_type1[4:0] == `STORE_RQ);
wire sctag0_mb1_ld_y = sctag0_mb_valid[1] & sctag0_mb_young[1] & ~sctag0_mb_type1[5] & (sctag0_mb_type1[4:0] == `LOAD_RQ);
wire sctag0_mb1_wris8_y = sctag0_mb_valid[1] & sctag0_mb_young[1] & sctag0_mb_type1[5] & sctag0_mb_type1[1];
wire sctag0_mb1_wris64_y = sctag0_mb_valid[1] & sctag0_mb_young[1] & sctag0_mb_type1[5] & sctag0_mb_type1[2];
wire sctag0_mb2_st_ny = sctag0_mb_valid[2] & ~sctag0_mb_young[2] & ~sctag0_mb_type2[5] & (sctag0_mb_type2[4:0] == `STORE_RQ);
wire sctag0_mb2_ld_ny = sctag0_mb_valid[2] & ~sctag0_mb_young[2] & ~sctag0_mb_type2[5] & (sctag0_mb_type2[4:0] == `LOAD_RQ);
wire sctag0_mb2_wris8_ny = sctag0_mb_valid[2] & ~sctag0_mb_young[2] & sctag0_mb_type2[5] & sctag0_mb_type2[1];
wire sctag0_mb2_wris64_ny = sctag0_mb_valid[2] & ~sctag0_mb_young[2] & sctag0_mb_type2[5] & sctag0_mb_type2[2];
wire sctag0_mb2_st_y = sctag0_mb_valid[2] & sctag0_mb_young[2] & ~sctag0_mb_type2[5] & (sctag0_mb_type2[4:0] == `STORE_RQ);
wire sctag0_mb2_ld_y = sctag0_mb_valid[2] & sctag0_mb_young[2] & ~sctag0_mb_type2[5] & (sctag0_mb_type2[4:0] == `LOAD_RQ);
wire sctag0_mb2_wris8_y = sctag0_mb_valid[2] & sctag0_mb_young[2] & sctag0_mb_type2[5] & sctag0_mb_type2[1];
wire sctag0_mb2_wris64_y = sctag0_mb_valid[2] & sctag0_mb_young[2] & sctag0_mb_type2[5] & sctag0_mb_type2[2];
wire sctag0_mb3_st_ny = sctag0_mb_valid[3] & ~sctag0_mb_young[3] & ~sctag0_mb_type3[5] & (sctag0_mb_type3[4:0] == `STORE_RQ);
wire sctag0_mb3_ld_ny = sctag0_mb_valid[3] & ~sctag0_mb_young[3] & ~sctag0_mb_type3[5] & (sctag0_mb_type3[4:0] == `LOAD_RQ);
wire sctag0_mb3_wris8_ny = sctag0_mb_valid[3] & ~sctag0_mb_young[3] & sctag0_mb_type3[5] & sctag0_mb_type3[1];
wire sctag0_mb3_wris64_ny = sctag0_mb_valid[3] & ~sctag0_mb_young[3] & sctag0_mb_type3[5] & sctag0_mb_type3[2];
wire sctag0_mb3_st_y = sctag0_mb_valid[3] & sctag0_mb_young[3] & ~sctag0_mb_type3[5] & (sctag0_mb_type3[4:0] == `STORE_RQ);
wire sctag0_mb3_ld_y = sctag0_mb_valid[3] & sctag0_mb_young[3] & ~sctag0_mb_type3[5] & (sctag0_mb_type3[4:0] == `LOAD_RQ);
wire sctag0_mb3_wris8_y = sctag0_mb_valid[3] & sctag0_mb_young[3] & sctag0_mb_type3[5] & sctag0_mb_type3[1];
wire sctag0_mb3_wris64_y = sctag0_mb_valid[3] & sctag0_mb_young[3] & sctag0_mb_type3[5] & sctag0_mb_type3[2];
wire sctag0_mb4_st_ny = sctag0_mb_valid[4] & ~sctag0_mb_young[4] & ~sctag0_mb_type4[5] & (sctag0_mb_type4[4:0] == `STORE_RQ);
wire sctag0_mb4_ld_ny = sctag0_mb_valid[4] & ~sctag0_mb_young[4] & ~sctag0_mb_type4[5] & (sctag0_mb_type4[4:0] == `LOAD_RQ);
wire sctag0_mb4_wris8_ny = sctag0_mb_valid[4] & ~sctag0_mb_young[4] & sctag0_mb_type4[5] & sctag0_mb_type4[1];
wire sctag0_mb4_wris64_ny = sctag0_mb_valid[4] & ~sctag0_mb_young[4] & sctag0_mb_type4[5] & sctag0_mb_type4[2];
wire sctag0_mb4_st_y = sctag0_mb_valid[4] & sctag0_mb_young[4] & ~sctag0_mb_type4[5] & (sctag0_mb_type4[4:0] == `STORE_RQ);
wire sctag0_mb4_ld_y = sctag0_mb_valid[4] & sctag0_mb_young[4] & ~sctag0_mb_type4[5] & (sctag0_mb_type4[4:0] == `LOAD_RQ);
wire sctag0_mb4_wris8_y = sctag0_mb_valid[4] & sctag0_mb_young[4] & sctag0_mb_type4[5] & sctag0_mb_type4[1];
wire sctag0_mb4_wris64_y = sctag0_mb_valid[4] & sctag0_mb_young[4] & sctag0_mb_type4[5] & sctag0_mb_type4[2];
wire sctag0_mb5_st_ny = sctag0_mb_valid[5] & ~sctag0_mb_young[5] & ~sctag0_mb_type5[5] & (sctag0_mb_type5[4:0] == `STORE_RQ);
wire sctag0_mb5_ld_ny = sctag0_mb_valid[5] & ~sctag0_mb_young[5] & ~sctag0_mb_type5[5] & (sctag0_mb_type5[4:0] == `LOAD_RQ);
wire sctag0_mb5_wris8_ny = sctag0_mb_valid[5] & ~sctag0_mb_young[5] & sctag0_mb_type5[5] & sctag0_mb_type5[1];
wire sctag0_mb5_wris64_ny = sctag0_mb_valid[5] & ~sctag0_mb_young[5] & sctag0_mb_type5[5] & sctag0_mb_type5[2];
wire sctag0_mb5_st_y = sctag0_mb_valid[5] & sctag0_mb_young[5] & ~sctag0_mb_type5[5] & (sctag0_mb_type5[4:0] == `STORE_RQ);
wire sctag0_mb5_ld_y = sctag0_mb_valid[5] & sctag0_mb_young[5] & ~sctag0_mb_type5[5] & (sctag0_mb_type5[4:0] == `LOAD_RQ);
wire sctag0_mb5_wris8_y = sctag0_mb_valid[5] & sctag0_mb_young[5] & sctag0_mb_type5[5] & sctag0_mb_type5[1];
wire sctag0_mb5_wris64_y = sctag0_mb_valid[5] & sctag0_mb_young[5] & sctag0_mb_type5[5] & sctag0_mb_type5[2];
wire sctag0_mb6_st_ny = sctag0_mb_valid[6] & ~sctag0_mb_young[6] & ~sctag0_mb_type6[5] & (sctag0_mb_type6[4:0] == `STORE_RQ);
wire sctag0_mb6_ld_ny = sctag0_mb_valid[6] & ~sctag0_mb_young[6] & ~sctag0_mb_type6[5] & (sctag0_mb_type6[4:0] == `LOAD_RQ);
wire sctag0_mb6_wris8_ny = sctag0_mb_valid[6] & ~sctag0_mb_young[6] & sctag0_mb_type6[5] & sctag0_mb_type6[1];
wire sctag0_mb6_wris64_ny = sctag0_mb_valid[6] & ~sctag0_mb_young[6] & sctag0_mb_type6[5] & sctag0_mb_type6[2];
wire sctag0_mb6_st_y = sctag0_mb_valid[6] & sctag0_mb_young[6] & ~sctag0_mb_type6[5] & (sctag0_mb_type6[4:0] == `STORE_RQ);
wire sctag0_mb6_ld_y = sctag0_mb_valid[6] & sctag0_mb_young[6] & ~sctag0_mb_type6[5] & (sctag0_mb_type6[4:0] == `LOAD_RQ);
wire sctag0_mb6_wris8_y = sctag0_mb_valid[6] & sctag0_mb_young[6] & sctag0_mb_type6[5] & sctag0_mb_type6[1];
wire sctag0_mb6_wris64_y = sctag0_mb_valid[6] & sctag0_mb_young[6] & sctag0_mb_type6[5] & sctag0_mb_type6[2];
wire sctag0_mb7_st_ny = sctag0_mb_valid[7] & ~sctag0_mb_young[7] & ~sctag0_mb_type7[5] & (sctag0_mb_type7[4:0] == `STORE_RQ);
wire sctag0_mb7_ld_ny = sctag0_mb_valid[7] & ~sctag0_mb_young[7] & ~sctag0_mb_type7[5] & (sctag0_mb_type7[4:0] == `LOAD_RQ);
wire sctag0_mb7_wris8_ny = sctag0_mb_valid[7] & ~sctag0_mb_young[7] & sctag0_mb_type7[5] & sctag0_mb_type7[1];
wire sctag0_mb7_wris64_ny = sctag0_mb_valid[7] & ~sctag0_mb_young[7] & sctag0_mb_type7[5] & sctag0_mb_type7[2];
wire sctag0_mb7_st_y = sctag0_mb_valid[7] & sctag0_mb_young[7] & ~sctag0_mb_type7[5] & (sctag0_mb_type7[4:0] == `STORE_RQ);
wire sctag0_mb7_ld_y = sctag0_mb_valid[7] & sctag0_mb_young[7] & ~sctag0_mb_type7[5] & (sctag0_mb_type7[4:0] == `LOAD_RQ);
wire sctag0_mb7_wris8_y = sctag0_mb_valid[7] & sctag0_mb_young[7] & sctag0_mb_type7[5] & sctag0_mb_type7[1];
wire sctag0_mb7_wris64_y = sctag0_mb_valid[7] & sctag0_mb_young[7] & sctag0_mb_type7[5] & sctag0_mb_type7[2];
wire sctag0_mb8_st_ny = sctag0_mb_valid[8] & ~sctag0_mb_young[8] & ~sctag0_mb_type8[5] & (sctag0_mb_type8[4:0] == `STORE_RQ);
wire sctag0_mb8_ld_ny = sctag0_mb_valid[8] & ~sctag0_mb_young[8] & ~sctag0_mb_type8[5] & (sctag0_mb_type8[4:0] == `LOAD_RQ);
wire sctag0_mb8_wris8_ny = sctag0_mb_valid[8] & ~sctag0_mb_young[8] & sctag0_mb_type8[5] & sctag0_mb_type8[1];
wire sctag0_mb8_wris64_ny = sctag0_mb_valid[8] & ~sctag0_mb_young[8] & sctag0_mb_type8[5] & sctag0_mb_type8[2];
wire sctag0_mb8_st_y = sctag0_mb_valid[8] & sctag0_mb_young[8] & ~sctag0_mb_type8[5] & (sctag0_mb_type8[4:0] == `STORE_RQ);
wire sctag0_mb8_ld_y = sctag0_mb_valid[8] & sctag0_mb_young[8] & ~sctag0_mb_type8[5] & (sctag0_mb_type8[4:0] == `LOAD_RQ);
wire sctag0_mb8_wris8_y = sctag0_mb_valid[8] & sctag0_mb_young[8] & sctag0_mb_type8[5] & sctag0_mb_type8[1];
wire sctag0_mb8_wris64_y = sctag0_mb_valid[8] & sctag0_mb_young[8] & sctag0_mb_type8[5] & sctag0_mb_type8[2];
wire sctag0_mb9_st_ny = sctag0_mb_valid[9] & ~sctag0_mb_young[9] & ~sctag0_mb_type9[5] & (sctag0_mb_type9[4:0] == `STORE_RQ);
wire sctag0_mb9_ld_ny = sctag0_mb_valid[9] & ~sctag0_mb_young[9] & ~sctag0_mb_type9[5] & (sctag0_mb_type9[4:0] == `LOAD_RQ);
wire sctag0_mb9_wris8_ny = sctag0_mb_valid[9] & ~sctag0_mb_young[9] & sctag0_mb_type9[5] & sctag0_mb_type9[1];
wire sctag0_mb9_wris64_ny = sctag0_mb_valid[9] & ~sctag0_mb_young[9] & sctag0_mb_type9[5] & sctag0_mb_type9[2];
wire sctag0_mb9_st_y = sctag0_mb_valid[9] & sctag0_mb_young[9] & ~sctag0_mb_type9[5] & (sctag0_mb_type9[4:0] == `STORE_RQ);
wire sctag0_mb9_ld_y = sctag0_mb_valid[9] & sctag0_mb_young[9] & ~sctag0_mb_type9[5] & (sctag0_mb_type9[4:0] == `LOAD_RQ);
wire sctag0_mb9_wris8_y = sctag0_mb_valid[9] & sctag0_mb_young[9] & sctag0_mb_type9[5] & sctag0_mb_type9[1];
wire sctag0_mb9_wris64_y = sctag0_mb_valid[9] & sctag0_mb_young[9] & sctag0_mb_type9[5] & sctag0_mb_type9[2];
wire sctag0_mb10_st_ny = sctag0_mb_valid[10] & ~sctag0_mb_young[10] & ~sctag0_mb_type10[5] & (sctag0_mb_type10[4:0] == `STORE_RQ);
wire sctag0_mb10_ld_ny = sctag0_mb_valid[10] & ~sctag0_mb_young[10] & ~sctag0_mb_type10[5] & (sctag0_mb_type10[4:0] == `LOAD_RQ);
wire sctag0_mb10_wris8_ny = sctag0_mb_valid[10] & ~sctag0_mb_young[10] & sctag0_mb_type10[5] & sctag0_mb_type10[1];
wire sctag0_mb10_wris64_ny = sctag0_mb_valid[10] & ~sctag0_mb_young[10] & sctag0_mb_type10[5] & sctag0_mb_type10[2];
wire sctag0_mb10_st_y = sctag0_mb_valid[10] & sctag0_mb_young[10] & ~sctag0_mb_type10[5] & (sctag0_mb_type10[4:0] == `STORE_RQ);
wire sctag0_mb10_ld_y = sctag0_mb_valid[10] & sctag0_mb_young[10] & ~sctag0_mb_type10[5] & (sctag0_mb_type10[4:0] == `LOAD_RQ);
wire sctag0_mb10_wris8_y = sctag0_mb_valid[10] & sctag0_mb_young[10] & sctag0_mb_type10[5] & sctag0_mb_type10[1];
wire sctag0_mb10_wris64_y = sctag0_mb_valid[10] & sctag0_mb_young[10] & sctag0_mb_type10[5] & sctag0_mb_type10[2];
wire sctag0_mb11_st_ny = sctag0_mb_valid[11] & ~sctag0_mb_young[11] & ~sctag0_mb_type11[5] & (sctag0_mb_type11[4:0] == `STORE_RQ);
wire sctag0_mb11_ld_ny = sctag0_mb_valid[11] & ~sctag0_mb_young[11] & ~sctag0_mb_type11[5] & (sctag0_mb_type11[4:0] == `LOAD_RQ);
wire sctag0_mb11_wris8_ny = sctag0_mb_valid[11] & ~sctag0_mb_young[11] & sctag0_mb_type11[5] & sctag0_mb_type11[1];
wire sctag0_mb11_wris64_ny = sctag0_mb_valid[11] & ~sctag0_mb_young[11] & sctag0_mb_type11[5] & sctag0_mb_type11[2];
wire sctag0_mb11_st_y = sctag0_mb_valid[11] & sctag0_mb_young[11] & ~sctag0_mb_type11[5] & (sctag0_mb_type11[4:0] == `STORE_RQ);
wire sctag0_mb11_ld_y = sctag0_mb_valid[11] & sctag0_mb_young[11] & ~sctag0_mb_type11[5] & (sctag0_mb_type11[4:0] == `LOAD_RQ);
wire sctag0_mb11_wris8_y = sctag0_mb_valid[11] & sctag0_mb_young[11] & sctag0_mb_type11[5] & sctag0_mb_type11[1];
wire sctag0_mb11_wris64_y = sctag0_mb_valid[11] & sctag0_mb_young[11] & sctag0_mb_type11[5] & sctag0_mb_type11[2];
wire sctag0_mb12_st_ny = sctag0_mb_valid[12] & ~sctag0_mb_young[12] & ~sctag0_mb_type12[5] & (sctag0_mb_type12[4:0] == `STORE_RQ);
wire sctag0_mb12_ld_ny = sctag0_mb_valid[12] & ~sctag0_mb_young[12] & ~sctag0_mb_type12[5] & (sctag0_mb_type12[4:0] == `LOAD_RQ);
wire sctag0_mb12_wris8_ny = sctag0_mb_valid[12] & ~sctag0_mb_young[12] & sctag0_mb_type12[5] & sctag0_mb_type12[1];
wire sctag0_mb12_wris64_ny = sctag0_mb_valid[12] & ~sctag0_mb_young[12] & sctag0_mb_type12[5] & sctag0_mb_type12[2];
wire sctag0_mb12_st_y = sctag0_mb_valid[12] & sctag0_mb_young[12] & ~sctag0_mb_type12[5] & (sctag0_mb_type12[4:0] == `STORE_RQ);
wire sctag0_mb12_ld_y = sctag0_mb_valid[12] & sctag0_mb_young[12] & ~sctag0_mb_type12[5] & (sctag0_mb_type12[4:0] == `LOAD_RQ);
wire sctag0_mb12_wris8_y = sctag0_mb_valid[12] & sctag0_mb_young[12] & sctag0_mb_type12[5] & sctag0_mb_type12[1];
wire sctag0_mb12_wris64_y = sctag0_mb_valid[12] & sctag0_mb_young[12] & sctag0_mb_type12[5] & sctag0_mb_type12[2];
wire sctag0_mb13_st_ny = sctag0_mb_valid[13] & ~sctag0_mb_young[13] & ~sctag0_mb_type13[5] & (sctag0_mb_type13[4:0] == `STORE_RQ);
wire sctag0_mb13_ld_ny = sctag0_mb_valid[13] & ~sctag0_mb_young[13] & ~sctag0_mb_type13[5] & (sctag0_mb_type13[4:0] == `LOAD_RQ);
wire sctag0_mb13_wris8_ny = sctag0_mb_valid[13] & ~sctag0_mb_young[13] & sctag0_mb_type13[5] & sctag0_mb_type13[1];
wire sctag0_mb13_wris64_ny = sctag0_mb_valid[13] & ~sctag0_mb_young[13] & sctag0_mb_type13[5] & sctag0_mb_type13[2];
wire sctag0_mb13_st_y = sctag0_mb_valid[13] & sctag0_mb_young[13] & ~sctag0_mb_type13[5] & (sctag0_mb_type13[4:0] == `STORE_RQ);
wire sctag0_mb13_ld_y = sctag0_mb_valid[13] & sctag0_mb_young[13] & ~sctag0_mb_type13[5] & (sctag0_mb_type13[4:0] == `LOAD_RQ);
wire sctag0_mb13_wris8_y = sctag0_mb_valid[13] & sctag0_mb_young[13] & sctag0_mb_type13[5] & sctag0_mb_type13[1];
wire sctag0_mb13_wris64_y = sctag0_mb_valid[13] & sctag0_mb_young[13] & sctag0_mb_type13[5] & sctag0_mb_type13[2];
wire sctag0_mb14_st_ny = sctag0_mb_valid[14] & ~sctag0_mb_young[14] & ~sctag0_mb_type14[5] & (sctag0_mb_type14[4:0] == `STORE_RQ);
wire sctag0_mb14_ld_ny = sctag0_mb_valid[14] & ~sctag0_mb_young[14] & ~sctag0_mb_type14[5] & (sctag0_mb_type14[4:0] == `LOAD_RQ);
wire sctag0_mb14_wris8_ny = sctag0_mb_valid[14] & ~sctag0_mb_young[14] & sctag0_mb_type14[5] & sctag0_mb_type14[1];
wire sctag0_mb14_wris64_ny = sctag0_mb_valid[14] & ~sctag0_mb_young[14] & sctag0_mb_type14[5] & sctag0_mb_type14[2];
wire sctag0_mb14_st_y = sctag0_mb_valid[14] & sctag0_mb_young[14] & ~sctag0_mb_type14[5] & (sctag0_mb_type14[4:0] == `STORE_RQ);
wire sctag0_mb14_ld_y = sctag0_mb_valid[14] & sctag0_mb_young[14] & ~sctag0_mb_type14[5] & (sctag0_mb_type14[4:0] == `LOAD_RQ);
wire sctag0_mb14_wris8_y = sctag0_mb_valid[14] & sctag0_mb_young[14] & sctag0_mb_type14[5] & sctag0_mb_type14[1];
wire sctag0_mb14_wris64_y = sctag0_mb_valid[14] & sctag0_mb_young[14] & sctag0_mb_type14[5] & sctag0_mb_type14[2];
wire sctag0_mb15_st_ny = sctag0_mb_valid[15] & ~sctag0_mb_young[15] & ~sctag0_mb_type15[5] & (sctag0_mb_type15[4:0] == `STORE_RQ);
wire sctag0_mb15_ld_ny = sctag0_mb_valid[15] & ~sctag0_mb_young[15] & ~sctag0_mb_type15[5] & (sctag0_mb_type15[4:0] == `LOAD_RQ);
wire sctag0_mb15_wris8_ny = sctag0_mb_valid[15] & ~sctag0_mb_young[15] & sctag0_mb_type15[5] & sctag0_mb_type15[1];
wire sctag0_mb15_wris64_ny = sctag0_mb_valid[15] & ~sctag0_mb_young[15] & sctag0_mb_type15[5] & sctag0_mb_type15[2];
wire sctag0_mb15_st_y = sctag0_mb_valid[15] & sctag0_mb_young[15] & ~sctag0_mb_type15[5] & (sctag0_mb_type15[4:0] == `STORE_RQ);
wire sctag0_mb15_ld_y = sctag0_mb_valid[15] & sctag0_mb_young[15] & ~sctag0_mb_type15[5] & (sctag0_mb_type15[4:0] == `LOAD_RQ);
wire sctag0_mb15_wris8_y = sctag0_mb_valid[15] & sctag0_mb_young[15] & sctag0_mb_type15[5] & sctag0_mb_type15[1];
wire sctag0_mb15_wris64_y = sctag0_mb_valid[15] & sctag0_mb_young[15] & sctag0_mb_type15[5] & sctag0_mb_type15[2];
wire [15:0] sctag1_mb_valid = `TOP_MEMORY.sctag1.mbctl.mb_valid[15:0];
wire [15:0] sctag1_mb_young = `TOP_MEMORY.sctag1.mbctl.mb_young[15:0];
//wire [3:0] sctag1_next_link_entry0 = `TOP_MEMORY.sctag1.mbctl.next_link_entry0[3:0];
//...
//wire [3:0] sctag1_next_link_entry15 = `TOP_MEMORY.sctag1.mbctl.next_link_entry15[3:0];
wire [155:0] sctag1_mb_data_array0 = `TOP_MEMORY.sctag1.mbdata.inq_ary[0];
wire [155:0] sctag1_mb_data_array1 = `TOP_MEMORY.sctag1.mbdata.inq_ary[1];
wire [155:0] sctag1_mb_data_array2 = `TOP_MEMORY.sctag1.mbdata.inq_ary[2];
wire [155:0] sctag1_mb_data_array3 = `TOP_MEMORY.sctag1.mbdata.inq_ary[3];
wire [155:0] sctag1_mb_data_array4 = `TOP_MEMORY.sctag1.mbdata.inq_ary[4];
wire [155:0] sctag1_mb_data_array5 = `TOP_MEMORY.sctag1.mbdata.inq_ary[5];
wire [155:0] sctag1_mb_data_array6 = `TOP_MEMORY.sctag1.mbdata.inq_ary[6];
wire [155:0] sctag1_mb_data_array7 = `TOP_MEMORY.sctag1.mbdata.inq_ary[7];
wire [155:0] sctag1_mb_data_array8 = `TOP_MEMORY.sctag1.mbdata.inq_ary[8];
wire [155:0] sctag1_mb_data_array9 = `TOP_MEMORY.sctag1.mbdata.inq_ary[9];
wire [155:0] sctag1_mb_data_array10 = `TOP_MEMORY.sctag1.mbdata.inq_ary[10];
wire [155:0] sctag1_mb_data_array11 = `TOP_MEMORY.sctag1.mbdata.inq_ary[11];
wire [155:0] sctag1_mb_data_array12 = `TOP_MEMORY.sctag1.mbdata.inq_ary[12];
wire [155:0] sctag1_mb_data_array13 = `TOP_MEMORY.sctag1.mbdata.inq_ary[13];
wire [155:0] sctag1_mb_data_array14 = `TOP_MEMORY.sctag1.mbdata.inq_ary[14];
wire [155:0] sctag1_mb_data_array15 = `TOP_MEMORY.sctag1.mbdata.inq_ary[15];
//-----------------------------------------------------------------------------------------------
// look at sctag.v for L2_RDMA_HI L2_RQTYP_HI L2_RQTYP_LO and L2_RSVD
// Based ont the equation: .mb_data_write_data({57'b0,mbdata_inst_tecc_c8...
//-----------------------------------------------------------------------------------------------
wire [5:0] sctag1_mb_type0 = {sctag1_mb_data_array0 [77], sctag1_mb_data_array0 [83:79]};
wire [5:0] sctag1_mb_type1 = {sctag1_mb_data_array1 [77], sctag1_mb_data_array1 [83:79]};
wire [5:0] sctag1_mb_type2 = {sctag1_mb_data_array2 [77], sctag1_mb_data_array2 [83:79]};
wire [5:0] sctag1_mb_type3 = {sctag1_mb_data_array3 [77], sctag1_mb_data_array3 [83:79]};
wire [5:0] sctag1_mb_type4 = {sctag1_mb_data_array4 [77], sctag1_mb_data_array4 [83:79]};
wire [5:0] sctag1_mb_type5 = {sctag1_mb_data_array5 [77], sctag1_mb_data_array5 [83:79]};
wire [5:0] sctag1_mb_type6 = {sctag1_mb_data_array6 [77], sctag1_mb_data_array6 [83:79]};
wire [5:0] sctag1_mb_type7 = {sctag1_mb_data_array7 [77], sctag1_mb_data_array7 [83:79]};
wire [5:0] sctag1_mb_type8 = {sctag1_mb_data_array8 [77], sctag1_mb_data_array8 [83:79]};
wire [5:0] sctag1_mb_type9 = {sctag1_mb_data_array9 [77], sctag1_mb_data_array9 [83:79]};
wire [5:0] sctag1_mb_type10 = {sctag1_mb_data_array10[77], sctag1_mb_data_array10[83:79]};
wire [5:0] sctag1_mb_type11 = {sctag1_mb_data_array11[77], sctag1_mb_data_array11[83:79]};
wire [5:0] sctag1_mb_type12 = {sctag1_mb_data_array12[77], sctag1_mb_data_array12[83:79]};
wire [5:0] sctag1_mb_type13 = {sctag1_mb_data_array13[77], sctag1_mb_data_array13[83:79]};
wire [5:0] sctag1_mb_type14 = {sctag1_mb_data_array14[77], sctag1_mb_data_array14[83:79]};
wire [5:0] sctag1_mb_type15 = {sctag1_mb_data_array15[77], sctag1_mb_data_array15[83:79]};
//--------------------------------------------------------------
// Start figuring out what the entries are.
// bit 5 says if this is a DMA type or normal type
//--------------------------------------------------------------
wire sctag1_mb0_st_ny = sctag1_mb_valid[0] & ~sctag1_mb_young[0] & ~sctag1_mb_type0[5] & (sctag1_mb_type0[4:0] == `STORE_RQ);
wire sctag1_mb0_ld_ny = sctag1_mb_valid[0] & ~sctag1_mb_young[0] & ~sctag1_mb_type0[5] & (sctag1_mb_type0[4:0] == `LOAD_RQ);
wire sctag1_mb0_wris8_ny = sctag1_mb_valid[0] & ~sctag1_mb_young[0] & sctag1_mb_type0[5] & sctag1_mb_type0[1];
wire sctag1_mb0_wris64_ny = sctag1_mb_valid[0] & ~sctag1_mb_young[0] & sctag1_mb_type0[5] & sctag1_mb_type0[2];
wire sctag1_mb0_st_y = sctag1_mb_valid[0] & sctag1_mb_young[0] & ~sctag1_mb_type0[5] & (sctag1_mb_type0[4:0] == `STORE_RQ);
wire sctag1_mb0_ld_y = sctag1_mb_valid[0] & sctag1_mb_young[0] & ~sctag1_mb_type0[5] & (sctag1_mb_type0[4:0] == `LOAD_RQ);
wire sctag1_mb0_wris8_y = sctag1_mb_valid[0] & sctag1_mb_young[0] & sctag1_mb_type0[5] & sctag1_mb_type0[1];
wire sctag1_mb0_wris64_y = sctag1_mb_valid[0] & sctag1_mb_young[0] & sctag1_mb_type0[5] & sctag1_mb_type0[2];
wire sctag1_mb1_st_ny = sctag1_mb_valid[1] & ~sctag1_mb_young[1] & ~sctag1_mb_type1[5] & (sctag1_mb_type1[4:0] == `STORE_RQ);
wire sctag1_mb1_ld_ny = sctag1_mb_valid[1] & ~sctag1_mb_young[1] & ~sctag1_mb_type1[5] & (sctag1_mb_type1[4:0] == `LOAD_RQ);
wire sctag1_mb1_wris8_ny = sctag1_mb_valid[1] & ~sctag1_mb_young[1] & sctag1_mb_type1[5] & sctag1_mb_type1[1];
wire sctag1_mb1_wris64_ny = sctag1_mb_valid[1] & ~sctag1_mb_young[1] & sctag1_mb_type1[5] & sctag1_mb_type1[2];
wire sctag1_mb1_st_y = sctag1_mb_valid[1] & sctag1_mb_young[1] & ~sctag1_mb_type1[5] & (sctag1_mb_type1[4:0] == `STORE_RQ);
wire sctag1_mb1_ld_y = sctag1_mb_valid[1] & sctag1_mb_young[1] & ~sctag1_mb_type1[5] & (sctag1_mb_type1[4:0] == `LOAD_RQ);
wire sctag1_mb1_wris8_y = sctag1_mb_valid[1] & sctag1_mb_young[1] & sctag1_mb_type1[5] & sctag1_mb_type1[1];
wire sctag1_mb1_wris64_y = sctag1_mb_valid[1] & sctag1_mb_young[1] & sctag1_mb_type1[5] & sctag1_mb_type1[2];
wire sctag1_mb2_st_ny = sctag1_mb_valid[2] & ~sctag1_mb_young[2] & ~sctag1_mb_type2[5] & (sctag1_mb_type2[4:0] == `STORE_RQ);
wire sctag1_mb2_ld_ny = sctag1_mb_valid[2] & ~sctag1_mb_young[2] & ~sctag1_mb_type2[5] & (sctag1_mb_type2[4:0] == `LOAD_RQ);
wire sctag1_mb2_wris8_ny = sctag1_mb_valid[2] & ~sctag1_mb_young[2] & sctag1_mb_type2[5] & sctag1_mb_type2[1];
wire sctag1_mb2_wris64_ny = sctag1_mb_valid[2] & ~sctag1_mb_young[2] & sctag1_mb_type2[5] & sctag1_mb_type2[2];
wire sctag1_mb2_st_y = sctag1_mb_valid[2] & sctag1_mb_young[2] & ~sctag1_mb_type2[5] & (sctag1_mb_type2[4:0] == `STORE_RQ);
wire sctag1_mb2_ld_y = sctag1_mb_valid[2] & sctag1_mb_young[2] & ~sctag1_mb_type2[5] & (sctag1_mb_type2[4:0] == `LOAD_RQ);
wire sctag1_mb2_wris8_y = sctag1_mb_valid[2] & sctag1_mb_young[2] & sctag1_mb_type2[5] & sctag1_mb_type2[1];
wire sctag1_mb2_wris64_y = sctag1_mb_valid[2] & sctag1_mb_young[2] & sctag1_mb_type2[5] & sctag1_mb_type2[2];
wire sctag1_mb3_st_ny = sctag1_mb_valid[3] & ~sctag1_mb_young[3] & ~sctag1_mb_type3[5] & (sctag1_mb_type3[4:0] == `STORE_RQ);
wire sctag1_mb3_ld_ny = sctag1_mb_valid[3] & ~sctag1_mb_young[3] & ~sctag1_mb_type3[5] & (sctag1_mb_type3[4:0] == `LOAD_RQ);
wire sctag1_mb3_wris8_ny = sctag1_mb_valid[3] & ~sctag1_mb_young[3] & sctag1_mb_type3[5] & sctag1_mb_type3[1];
wire sctag1_mb3_wris64_ny = sctag1_mb_valid[3] & ~sctag1_mb_young[3] & sctag1_mb_type3[5] & sctag1_mb_type3[2];
wire sctag1_mb3_st_y = sctag1_mb_valid[3] & sctag1_mb_young[3] & ~sctag1_mb_type3[5] & (sctag1_mb_type3[4:0] == `STORE_RQ);
wire sctag1_mb3_ld_y = sctag1_mb_valid[3] & sctag1_mb_young[3] & ~sctag1_mb_type3[5] & (sctag1_mb_type3[4:0] == `LOAD_RQ);
wire sctag1_mb3_wris8_y = sctag1_mb_valid[3] & sctag1_mb_young[3] & sctag1_mb_type3[5] & sctag1_mb_type3[1];
wire sctag1_mb3_wris64_y = sctag1_mb_valid[3] & sctag1_mb_young[3] & sctag1_mb_type3[5] & sctag1_mb_type3[2];
wire sctag1_mb4_st_ny = sctag1_mb_valid[4] & ~sctag1_mb_young[4] & ~sctag1_mb_type4[5] & (sctag1_mb_type4[4:0] == `STORE_RQ);
wire sctag1_mb4_ld_ny = sctag1_mb_valid[4] & ~sctag1_mb_young[4] & ~sctag1_mb_type4[5] & (sctag1_mb_type4[4:0] == `LOAD_RQ);
wire sctag1_mb4_wris8_ny = sctag1_mb_valid[4] & ~sctag1_mb_young[4] & sctag1_mb_type4[5] & sctag1_mb_type4[1];
wire sctag1_mb4_wris64_ny = sctag1_mb_valid[4] & ~sctag1_mb_young[4] & sctag1_mb_type4[5] & sctag1_mb_type4[2];
wire sctag1_mb4_st_y = sctag1_mb_valid[4] & sctag1_mb_young[4] & ~sctag1_mb_type4[5] & (sctag1_mb_type4[4:0] == `STORE_RQ);
wire sctag1_mb4_ld_y = sctag1_mb_valid[4] & sctag1_mb_young[4] & ~sctag1_mb_type4[5] & (sctag1_mb_type4[4:0] == `LOAD_RQ);
wire sctag1_mb4_wris8_y = sctag1_mb_valid[4] & sctag1_mb_young[4] & sctag1_mb_type4[5] & sctag1_mb_type4[1];
wire sctag1_mb4_wris64_y = sctag1_mb_valid[4] & sctag1_mb_young[4] & sctag1_mb_type4[5] & sctag1_mb_type4[2];
wire sctag1_mb5_st_ny = sctag1_mb_valid[5] & ~sctag1_mb_young[5] & ~sctag1_mb_type5[5] & (sctag1_mb_type5[4:0] == `STORE_RQ);
wire sctag1_mb5_ld_ny = sctag1_mb_valid[5] & ~sctag1_mb_young[5] & ~sctag1_mb_type5[5] & (sctag1_mb_type5[4:0] == `LOAD_RQ);
wire sctag1_mb5_wris8_ny = sctag1_mb_valid[5] & ~sctag1_mb_young[5] & sctag1_mb_type5[5] & sctag1_mb_type5[1];
wire sctag1_mb5_wris64_ny = sctag1_mb_valid[5] & ~sctag1_mb_young[5] & sctag1_mb_type5[5] & sctag1_mb_type5[2];
wire sctag1_mb5_st_y = sctag1_mb_valid[5] & sctag1_mb_young[5] & ~sctag1_mb_type5[5] & (sctag1_mb_type5[4:0] == `STORE_RQ);
wire sctag1_mb5_ld_y = sctag1_mb_valid[5] & sctag1_mb_young[5] & ~sctag1_mb_type5[5] & (sctag1_mb_type5[4:0] == `LOAD_RQ);
wire sctag1_mb5_wris8_y = sctag1_mb_valid[5] & sctag1_mb_young[5] & sctag1_mb_type5[5] & sctag1_mb_type5[1];
wire sctag1_mb5_wris64_y = sctag1_mb_valid[5] & sctag1_mb_young[5] & sctag1_mb_type5[5] & sctag1_mb_type5[2];
wire sctag1_mb6_st_ny = sctag1_mb_valid[6] & ~sctag1_mb_young[6] & ~sctag1_mb_type6[5] & (sctag1_mb_type6[4:0] == `STORE_RQ);
wire sctag1_mb6_ld_ny = sctag1_mb_valid[6] & ~sctag1_mb_young[6] & ~sctag1_mb_type6[5] & (sctag1_mb_type6[4:0] == `LOAD_RQ);
wire sctag1_mb6_wris8_ny = sctag1_mb_valid[6] & ~sctag1_mb_young[6] & sctag1_mb_type6[5] & sctag1_mb_type6[1];
wire sctag1_mb6_wris64_ny = sctag1_mb_valid[6] & ~sctag1_mb_young[6] & sctag1_mb_type6[5] & sctag1_mb_type6[2];
wire sctag1_mb6_st_y = sctag1_mb_valid[6] & sctag1_mb_young[6] & ~sctag1_mb_type6[5] & (sctag1_mb_type6[4:0] == `STORE_RQ);
wire sctag1_mb6_ld_y = sctag1_mb_valid[6] & sctag1_mb_young[6] & ~sctag1_mb_type6[5] & (sctag1_mb_type6[4:0] == `LOAD_RQ);
wire sctag1_mb6_wris8_y = sctag1_mb_valid[6] & sctag1_mb_young[6] & sctag1_mb_type6[5] & sctag1_mb_type6[1];
wire sctag1_mb6_wris64_y = sctag1_mb_valid[6] & sctag1_mb_young[6] & sctag1_mb_type6[5] & sctag1_mb_type6[2];
wire sctag1_mb7_st_ny = sctag1_mb_valid[7] & ~sctag1_mb_young[7] & ~sctag1_mb_type7[5] & (sctag1_mb_type7[4:0] == `STORE_RQ);
wire sctag1_mb7_ld_ny = sctag1_mb_valid[7] & ~sctag1_mb_young[7] & ~sctag1_mb_type7[5] & (sctag1_mb_type7[4:0] == `LOAD_RQ);
wire sctag1_mb7_wris8_ny = sctag1_mb_valid[7] & ~sctag1_mb_young[7] & sctag1_mb_type7[5] & sctag1_mb_type7[1];
wire sctag1_mb7_wris64_ny = sctag1_mb_valid[7] & ~sctag1_mb_young[7] & sctag1_mb_type7[5] & sctag1_mb_type7[2];
wire sctag1_mb7_st_y = sctag1_mb_valid[7] & sctag1_mb_young[7] & ~sctag1_mb_type7[5] & (sctag1_mb_type7[4:0] == `STORE_RQ);
wire sctag1_mb7_ld_y = sctag1_mb_valid[7] & sctag1_mb_young[7] & ~sctag1_mb_type7[5] & (sctag1_mb_type7[4:0] == `LOAD_RQ);
wire sctag1_mb7_wris8_y = sctag1_mb_valid[7] & sctag1_mb_young[7] & sctag1_mb_type7[5] & sctag1_mb_type7[1];
wire sctag1_mb7_wris64_y = sctag1_mb_valid[7] & sctag1_mb_young[7] & sctag1_mb_type7[5] & sctag1_mb_type7[2];
wire sctag1_mb8_st_ny = sctag1_mb_valid[8] & ~sctag1_mb_young[8] & ~sctag1_mb_type8[5] & (sctag1_mb_type8[4:0] == `STORE_RQ);
wire sctag1_mb8_ld_ny = sctag1_mb_valid[8] & ~sctag1_mb_young[8] & ~sctag1_mb_type8[5] & (sctag1_mb_type8[4:0] == `LOAD_RQ);
wire sctag1_mb8_wris8_ny = sctag1_mb_valid[8] & ~sctag1_mb_young[8] & sctag1_mb_type8[5] & sctag1_mb_type8[1];
wire sctag1_mb8_wris64_ny = sctag1_mb_valid[8] & ~sctag1_mb_young[8] & sctag1_mb_type8[5] & sctag1_mb_type8[2];
wire sctag1_mb8_st_y = sctag1_mb_valid[8] & sctag1_mb_young[8] & ~sctag1_mb_type8[5] & (sctag1_mb_type8[4:0] == `STORE_RQ);
wire sctag1_mb8_ld_y = sctag1_mb_valid[8] & sctag1_mb_young[8] & ~sctag1_mb_type8[5] & (sctag1_mb_type8[4:0] == `LOAD_RQ);
wire sctag1_mb8_wris8_y = sctag1_mb_valid[8] & sctag1_mb_young[8] & sctag1_mb_type8[5] & sctag1_mb_type8[1];
wire sctag1_mb8_wris64_y = sctag1_mb_valid[8] & sctag1_mb_young[8] & sctag1_mb_type8[5] & sctag1_mb_type8[2];
wire sctag1_mb9_st_ny = sctag1_mb_valid[9] & ~sctag1_mb_young[9] & ~sctag1_mb_type9[5] & (sctag1_mb_type9[4:0] == `STORE_RQ);
wire sctag1_mb9_ld_ny = sctag1_mb_valid[9] & ~sctag1_mb_young[9] & ~sctag1_mb_type9[5] & (sctag1_mb_type9[4:0] == `LOAD_RQ);
wire sctag1_mb9_wris8_ny = sctag1_mb_valid[9] & ~sctag1_mb_young[9] & sctag1_mb_type9[5] & sctag1_mb_type9[1];
wire sctag1_mb9_wris64_ny = sctag1_mb_valid[9] & ~sctag1_mb_young[9] & sctag1_mb_type9[5] & sctag1_mb_type9[2];
wire sctag1_mb9_st_y = sctag1_mb_valid[9] & sctag1_mb_young[9] & ~sctag1_mb_type9[5] & (sctag1_mb_type9[4:0] == `STORE_RQ);
wire sctag1_mb9_ld_y = sctag1_mb_valid[9] & sctag1_mb_young[9] & ~sctag1_mb_type9[5] & (sctag1_mb_type9[4:0] == `LOAD_RQ);
wire sctag1_mb9_wris8_y = sctag1_mb_valid[9] & sctag1_mb_young[9] & sctag1_mb_type9[5] & sctag1_mb_type9[1];
wire sctag1_mb9_wris64_y = sctag1_mb_valid[9] & sctag1_mb_young[9] & sctag1_mb_type9[5] & sctag1_mb_type9[2];
wire sctag1_mb10_st_ny = sctag1_mb_valid[10] & ~sctag1_mb_young[10] & ~sctag1_mb_type10[5] & (sctag1_mb_type10[4:0] == `STORE_RQ);
wire sctag1_mb10_ld_ny = sctag1_mb_valid[10] & ~sctag1_mb_young[10] & ~sctag1_mb_type10[5] & (sctag1_mb_type10[4:0] == `LOAD_RQ);
wire sctag1_mb10_wris8_ny = sctag1_mb_valid[10] & ~sctag1_mb_young[10] & sctag1_mb_type10[5] & sctag1_mb_type10[1];
wire sctag1_mb10_wris64_ny = sctag1_mb_valid[10] & ~sctag1_mb_young[10] & sctag1_mb_type10[5] & sctag1_mb_type10[2];
wire sctag1_mb10_st_y = sctag1_mb_valid[10] & sctag1_mb_young[10] & ~sctag1_mb_type10[5] & (sctag1_mb_type10[4:0] == `STORE_RQ);
wire sctag1_mb10_ld_y = sctag1_mb_valid[10] & sctag1_mb_young[10] & ~sctag1_mb_type10[5] & (sctag1_mb_type10[4:0] == `LOAD_RQ);
wire sctag1_mb10_wris8_y = sctag1_mb_valid[10] & sctag1_mb_young[10] & sctag1_mb_type10[5] & sctag1_mb_type10[1];
wire sctag1_mb10_wris64_y = sctag1_mb_valid[10] & sctag1_mb_young[10] & sctag1_mb_type10[5] & sctag1_mb_type10[2];
wire sctag1_mb11_st_ny = sctag1_mb_valid[11] & ~sctag1_mb_young[11] & ~sctag1_mb_type11[5] & (sctag1_mb_type11[4:0] == `STORE_RQ);
wire sctag1_mb11_ld_ny = sctag1_mb_valid[11] & ~sctag1_mb_young[11] & ~sctag1_mb_type11[5] & (sctag1_mb_type11[4:0] == `LOAD_RQ);
wire sctag1_mb11_wris8_ny = sctag1_mb_valid[11] & ~sctag1_mb_young[11] & sctag1_mb_type11[5] & sctag1_mb_type11[1];
wire sctag1_mb11_wris64_ny = sctag1_mb_valid[11] & ~sctag1_mb_young[11] & sctag1_mb_type11[5] & sctag1_mb_type11[2];
wire sctag1_mb11_st_y = sctag1_mb_valid[11] & sctag1_mb_young[11] & ~sctag1_mb_type11[5] & (sctag1_mb_type11[4:0] == `STORE_RQ);
wire sctag1_mb11_ld_y = sctag1_mb_valid[11] & sctag1_mb_young[11] & ~sctag1_mb_type11[5] & (sctag1_mb_type11[4:0] == `LOAD_RQ);
wire sctag1_mb11_wris8_y = sctag1_mb_valid[11] & sctag1_mb_young[11] & sctag1_mb_type11[5] & sctag1_mb_type11[1];
wire sctag1_mb11_wris64_y = sctag1_mb_valid[11] & sctag1_mb_young[11] & sctag1_mb_type11[5] & sctag1_mb_type11[2];
wire sctag1_mb12_st_ny = sctag1_mb_valid[12] & ~sctag1_mb_young[12] & ~sctag1_mb_type12[5] & (sctag1_mb_type12[4:0] == `STORE_RQ);
wire sctag1_mb12_ld_ny = sctag1_mb_valid[12] & ~sctag1_mb_young[12] & ~sctag1_mb_type12[5] & (sctag1_mb_type12[4:0] == `LOAD_RQ);
wire sctag1_mb12_wris8_ny = sctag1_mb_valid[12] & ~sctag1_mb_young[12] & sctag1_mb_type12[5] & sctag1_mb_type12[1];
wire sctag1_mb12_wris64_ny = sctag1_mb_valid[12] & ~sctag1_mb_young[12] & sctag1_mb_type12[5] & sctag1_mb_type12[2];
wire sctag1_mb12_st_y = sctag1_mb_valid[12] & sctag1_mb_young[12] & ~sctag1_mb_type12[5] & (sctag1_mb_type12[4:0] == `STORE_RQ);
wire sctag1_mb12_ld_y = sctag1_mb_valid[12] & sctag1_mb_young[12] & ~sctag1_mb_type12[5] & (sctag1_mb_type12[4:0] == `LOAD_RQ);
wire sctag1_mb12_wris8_y = sctag1_mb_valid[12] & sctag1_mb_young[12] & sctag1_mb_type12[5] & sctag1_mb_type12[1];
wire sctag1_mb12_wris64_y = sctag1_mb_valid[12] & sctag1_mb_young[12] & sctag1_mb_type12[5] & sctag1_mb_type12[2];
wire sctag1_mb13_st_ny = sctag1_mb_valid[13] & ~sctag1_mb_young[13] & ~sctag1_mb_type13[5] & (sctag1_mb_type13[4:0] == `STORE_RQ);
wire sctag1_mb13_ld_ny = sctag1_mb_valid[13] & ~sctag1_mb_young[13] & ~sctag1_mb_type13[5] & (sctag1_mb_type13[4:0] == `LOAD_RQ);
wire sctag1_mb13_wris8_ny = sctag1_mb_valid[13] & ~sctag1_mb_young[13] & sctag1_mb_type13[5] & sctag1_mb_type13[1];
wire sctag1_mb13_wris64_ny = sctag1_mb_valid[13] & ~sctag1_mb_young[13] & sctag1_mb_type13[5] & sctag1_mb_type13[2];
wire sctag1_mb13_st_y = sctag1_mb_valid[13] & sctag1_mb_young[13] & ~sctag1_mb_type13[5] & (sctag1_mb_type13[4:0] == `STORE_RQ);
wire sctag1_mb13_ld_y = sctag1_mb_valid[13] & sctag1_mb_young[13] & ~sctag1_mb_type13[5] & (sctag1_mb_type13[4:0] == `LOAD_RQ);
wire sctag1_mb13_wris8_y = sctag1_mb_valid[13] & sctag1_mb_young[13] & sctag1_mb_type13[5] & sctag1_mb_type13[1];
wire sctag1_mb13_wris64_y = sctag1_mb_valid[13] & sctag1_mb_young[13] & sctag1_mb_type13[5] & sctag1_mb_type13[2];
wire sctag1_mb14_st_ny = sctag1_mb_valid[14] & ~sctag1_mb_young[14] & ~sctag1_mb_type14[5] & (sctag1_mb_type14[4:0] == `STORE_RQ);
wire sctag1_mb14_ld_ny = sctag1_mb_valid[14] & ~sctag1_mb_young[14] & ~sctag1_mb_type14[5] & (sctag1_mb_type14[4:0] == `LOAD_RQ);
wire sctag1_mb14_wris8_ny = sctag1_mb_valid[14] & ~sctag1_mb_young[14] & sctag1_mb_type14[5] & sctag1_mb_type14[1];
wire sctag1_mb14_wris64_ny = sctag1_mb_valid[14] & ~sctag1_mb_young[14] & sctag1_mb_type14[5] & sctag1_mb_type14[2];
wire sctag1_mb14_st_y = sctag1_mb_valid[14] & sctag1_mb_young[14] & ~sctag1_mb_type14[5] & (sctag1_mb_type14[4:0] == `STORE_RQ);
wire sctag1_mb14_ld_y = sctag1_mb_valid[14] & sctag1_mb_young[14] & ~sctag1_mb_type14[5] & (sctag1_mb_type14[4:0] == `LOAD_RQ);
wire sctag1_mb14_wris8_y = sctag1_mb_valid[14] & sctag1_mb_young[14] & sctag1_mb_type14[5] & sctag1_mb_type14[1];
wire sctag1_mb14_wris64_y = sctag1_mb_valid[14] & sctag1_mb_young[14] & sctag1_mb_type14[5] & sctag1_mb_type14[2];
wire sctag1_mb15_st_ny = sctag1_mb_valid[15] & ~sctag1_mb_young[15] & ~sctag1_mb_type15[5] & (sctag1_mb_type15[4:0] == `STORE_RQ);
wire sctag1_mb15_ld_ny = sctag1_mb_valid[15] & ~sctag1_mb_young[15] & ~sctag1_mb_type15[5] & (sctag1_mb_type15[4:0] == `LOAD_RQ);
wire sctag1_mb15_wris8_ny = sctag1_mb_valid[15] & ~sctag1_mb_young[15] & sctag1_mb_type15[5] & sctag1_mb_type15[1];
wire sctag1_mb15_wris64_ny = sctag1_mb_valid[15] & ~sctag1_mb_young[15] & sctag1_mb_type15[5] & sctag1_mb_type15[2];
wire sctag1_mb15_st_y = sctag1_mb_valid[15] & sctag1_mb_young[15] & ~sctag1_mb_type15[5] & (sctag1_mb_type15[4:0] == `STORE_RQ);
wire sctag1_mb15_ld_y = sctag1_mb_valid[15] & sctag1_mb_young[15] & ~sctag1_mb_type15[5] & (sctag1_mb_type15[4:0] == `LOAD_RQ);
wire sctag1_mb15_wris8_y = sctag1_mb_valid[15] & sctag1_mb_young[15] & sctag1_mb_type15[5] & sctag1_mb_type15[1];
wire sctag1_mb15_wris64_y = sctag1_mb_valid[15] & sctag1_mb_young[15] & sctag1_mb_type15[5] & sctag1_mb_type15[2];
wire [15:0] sctag2_mb_valid = `TOP_MEMORY.sctag2.mbctl.mb_valid[15:0];
wire [15:0] sctag2_mb_young = `TOP_MEMORY.sctag2.mbctl.mb_young[15:0];
//wire [3:0] sctag2_next_link_entry0 = `TOP_MEMORY.sctag2.mbctl.next_link_entry0[3:0];
//...
//wire [3:0] sctag2_next_link_entry15 = `TOP_MEMORY.sctag2.mbctl.next_link_entry15[3:0];
wire [155:0] sctag2_mb_data_array0 = `TOP_MEMORY.sctag2.mbdata.inq_ary[0];
wire [155:0] sctag2_mb_data_array1 = `TOP_MEMORY.sctag2.mbdata.inq_ary[1];
wire [155:0] sctag2_mb_data_array2 = `TOP_MEMORY.sctag2.mbdata.inq_ary[2];
wire [155:0] sctag2_mb_data_array3 = `TOP_MEMORY.sctag2.mbdata.inq_ary[3];
wire [155:0] sctag2_mb_data_array4 = `TOP_MEMORY.sctag2.mbdata.inq_ary[4];
wire [155:0] sctag2_mb_data_array5 = `TOP_MEMORY.sctag2.mbdata.inq_ary[5];
wire [155:0] sctag2_mb_data_array6 = `TOP_MEMORY.sctag2.mbdata.inq_ary[6];
wire [155:0] sctag2_mb_data_array7 = `TOP_MEMORY.sctag2.mbdata.inq_ary[7];
wire [155:0] sctag2_mb_data_array8 = `TOP_MEMORY.sctag2.mbdata.inq_ary[8];
wire [155:0] sctag2_mb_data_array9 = `TOP_MEMORY.sctag2.mbdata.inq_ary[9];
wire [155:0] sctag2_mb_data_array10 = `TOP_MEMORY.sctag2.mbdata.inq_ary[10];
wire [155:0] sctag2_mb_data_array11 = `TOP_MEMORY.sctag2.mbdata.inq_ary[11];
wire [155:0] sctag2_mb_data_array12 = `TOP_MEMORY.sctag2.mbdata.inq_ary[12];
wire [155:0] sctag2_mb_data_array13 = `TOP_MEMORY.sctag2.mbdata.inq_ary[13];
wire [155:0] sctag2_mb_data_array14 = `TOP_MEMORY.sctag2.mbdata.inq_ary[14];
wire [155:0] sctag2_mb_data_array15 = `TOP_MEMORY.sctag2.mbdata.inq_ary[15];
//-----------------------------------------------------------------------------------------------
// look at sctag.v for L2_RDMA_HI L2_RQTYP_HI L2_RQTYP_LO and L2_RSVD
// Based ont the equation: .mb_data_write_data({57'b0,mbdata_inst_tecc_c8...
//-----------------------------------------------------------------------------------------------
wire [5:0] sctag2_mb_type0 = {sctag2_mb_data_array0 [77], sctag2_mb_data_array0 [83:79]};
wire [5:0] sctag2_mb_type1 = {sctag2_mb_data_array1 [77], sctag2_mb_data_array1 [83:79]};
wire [5:0] sctag2_mb_type2 = {sctag2_mb_data_array2 [77], sctag2_mb_data_array2 [83:79]};
wire [5:0] sctag2_mb_type3 = {sctag2_mb_data_array3 [77], sctag2_mb_data_array3 [83:79]};
wire [5:0] sctag2_mb_type4 = {sctag2_mb_data_array4 [77], sctag2_mb_data_array4 [83:79]};
wire [5:0] sctag2_mb_type5 = {sctag2_mb_data_array5 [77], sctag2_mb_data_array5 [83:79]};
wire [5:0] sctag2_mb_type6 = {sctag2_mb_data_array6 [77], sctag2_mb_data_array6 [83:79]};
wire [5:0] sctag2_mb_type7 = {sctag2_mb_data_array7 [77], sctag2_mb_data_array7 [83:79]};
wire [5:0] sctag2_mb_type8 = {sctag2_mb_data_array8 [77], sctag2_mb_data_array8 [83:79]};
wire [5:0] sctag2_mb_type9 = {sctag2_mb_data_array9 [77], sctag2_mb_data_array9 [83:79]};
wire [5:0] sctag2_mb_type10 = {sctag2_mb_data_array10[77], sctag2_mb_data_array10[83:79]};
wire [5:0] sctag2_mb_type11 = {sctag2_mb_data_array11[77], sctag2_mb_data_array11[83:79]};
wire [5:0] sctag2_mb_type12 = {sctag2_mb_data_array12[77], sctag2_mb_data_array12[83:79]};
wire [5:0] sctag2_mb_type13 = {sctag2_mb_data_array13[77], sctag2_mb_data_array13[83:79]};
wire [5:0] sctag2_mb_type14 = {sctag2_mb_data_array14[77], sctag2_mb_data_array14[83:79]};
wire [5:0] sctag2_mb_type15 = {sctag2_mb_data_array15[77], sctag2_mb_data_array15[83:79]};
//--------------------------------------------------------------
// Start figuring out what the entries are.
// bit 5 says if this is a DMA type or normal type
//--------------------------------------------------------------
wire sctag2_mb0_st_ny = sctag2_mb_valid[0] & ~sctag2_mb_young[0] & ~sctag2_mb_type0[5] & (sctag2_mb_type0[4:0] == `STORE_RQ);
wire sctag2_mb0_ld_ny = sctag2_mb_valid[0] & ~sctag2_mb_young[0] & ~sctag2_mb_type0[5] & (sctag2_mb_type0[4:0] == `LOAD_RQ);
wire sctag2_mb0_wris8_ny = sctag2_mb_valid[0] & ~sctag2_mb_young[0] & sctag2_mb_type0[5] & sctag2_mb_type0[1];
wire sctag2_mb0_wris64_ny = sctag2_mb_valid[0] & ~sctag2_mb_young[0] & sctag2_mb_type0[5] & sctag2_mb_type0[2];
wire sctag2_mb0_st_y = sctag2_mb_valid[0] & sctag2_mb_young[0] & ~sctag2_mb_type0[5] & (sctag2_mb_type0[4:0] == `STORE_RQ);
wire sctag2_mb0_ld_y = sctag2_mb_valid[0] & sctag2_mb_young[0] & ~sctag2_mb_type0[5] & (sctag2_mb_type0[4:0] == `LOAD_RQ);
wire sctag2_mb0_wris8_y = sctag2_mb_valid[0] & sctag2_mb_young[0] & sctag2_mb_type0[5] & sctag2_mb_type0[1];
wire sctag2_mb0_wris64_y = sctag2_mb_valid[0] & sctag2_mb_young[0] & sctag2_mb_type0[5] & sctag2_mb_type0[2];
wire sctag2_mb1_st_ny = sctag2_mb_valid[1] & ~sctag2_mb_young[1] & ~sctag2_mb_type1[5] & (sctag2_mb_type1[4:0] == `STORE_RQ);
wire sctag2_mb1_ld_ny = sctag2_mb_valid[1] & ~sctag2_mb_young[1] & ~sctag2_mb_type1[5] & (sctag2_mb_type1[4:0] == `LOAD_RQ);
wire sctag2_mb1_wris8_ny = sctag2_mb_valid[1] & ~sctag2_mb_young[1] & sctag2_mb_type1[5] & sctag2_mb_type1[1];
wire sctag2_mb1_wris64_ny = sctag2_mb_valid[1] & ~sctag2_mb_young[1] & sctag2_mb_type1[5] & sctag2_mb_type1[2];
wire sctag2_mb1_st_y = sctag2_mb_valid[1] & sctag2_mb_young[1] & ~sctag2_mb_type1[5] & (sctag2_mb_type1[4:0] == `STORE_RQ);
wire sctag2_mb1_ld_y = sctag2_mb_valid[1] & sctag2_mb_young[1] & ~sctag2_mb_type1[5] & (sctag2_mb_type1[4:0] == `LOAD_RQ);
wire sctag2_mb1_wris8_y = sctag2_mb_valid[1] & sctag2_mb_young[1] & sctag2_mb_type1[5] & sctag2_mb_type1[1];
wire sctag2_mb1_wris64_y = sctag2_mb_valid[1] & sctag2_mb_young[1] & sctag2_mb_type1[5] & sctag2_mb_type1[2];
wire sctag2_mb2_st_ny = sctag2_mb_valid[2] & ~sctag2_mb_young[2] & ~sctag2_mb_type2[5] & (sctag2_mb_type2[4:0] == `STORE_RQ);
wire sctag2_mb2_ld_ny = sctag2_mb_valid[2] & ~sctag2_mb_young[2] & ~sctag2_mb_type2[5] & (sctag2_mb_type2[4:0] == `LOAD_RQ);
wire sctag2_mb2_wris8_ny = sctag2_mb_valid[2] & ~sctag2_mb_young[2] & sctag2_mb_type2[5] & sctag2_mb_type2[1];
wire sctag2_mb2_wris64_ny = sctag2_mb_valid[2] & ~sctag2_mb_young[2] & sctag2_mb_type2[5] & sctag2_mb_type2[2];
wire sctag2_mb2_st_y = sctag2_mb_valid[2] & sctag2_mb_young[2] & ~sctag2_mb_type2[5] & (sctag2_mb_type2[4:0] == `STORE_RQ);
wire sctag2_mb2_ld_y = sctag2_mb_valid[2] & sctag2_mb_young[2] & ~sctag2_mb_type2[5] & (sctag2_mb_type2[4:0] == `LOAD_RQ);
wire sctag2_mb2_wris8_y = sctag2_mb_valid[2] & sctag2_mb_young[2] & sctag2_mb_type2[5] & sctag2_mb_type2[1];
wire sctag2_mb2_wris64_y = sctag2_mb_valid[2] & sctag2_mb_young[2] & sctag2_mb_type2[5] & sctag2_mb_type2[2];
wire sctag2_mb3_st_ny = sctag2_mb_valid[3] & ~sctag2_mb_young[3] & ~sctag2_mb_type3[5] & (sctag2_mb_type3[4:0] == `STORE_RQ);
wire sctag2_mb3_ld_ny = sctag2_mb_valid[3] & ~sctag2_mb_young[3] & ~sctag2_mb_type3[5] & (sctag2_mb_type3[4:0] == `LOAD_RQ);
wire sctag2_mb3_wris8_ny = sctag2_mb_valid[3] & ~sctag2_mb_young[3] & sctag2_mb_type3[5] & sctag2_mb_type3[1];
wire sctag2_mb3_wris64_ny = sctag2_mb_valid[3] & ~sctag2_mb_young[3] & sctag2_mb_type3[5] & sctag2_mb_type3[2];
wire sctag2_mb3_st_y = sctag2_mb_valid[3] & sctag2_mb_young[3] & ~sctag2_mb_type3[5] & (sctag2_mb_type3[4:0] == `STORE_RQ);
wire sctag2_mb3_ld_y = sctag2_mb_valid[3] & sctag2_mb_young[3] & ~sctag2_mb_type3[5] & (sctag2_mb_type3[4:0] == `LOAD_RQ);
wire sctag2_mb3_wris8_y = sctag2_mb_valid[3] & sctag2_mb_young[3] & sctag2_mb_type3[5] & sctag2_mb_type3[1];
wire sctag2_mb3_wris64_y = sctag2_mb_valid[3] & sctag2_mb_young[3] & sctag2_mb_type3[5] & sctag2_mb_type3[2];
wire sctag2_mb4_st_ny = sctag2_mb_valid[4] & ~sctag2_mb_young[4] & ~sctag2_mb_type4[5] & (sctag2_mb_type4[4:0] == `STORE_RQ);
wire sctag2_mb4_ld_ny = sctag2_mb_valid[4] & ~sctag2_mb_young[4] & ~sctag2_mb_type4[5] & (sctag2_mb_type4[4:0] == `LOAD_RQ);
wire sctag2_mb4_wris8_ny = sctag2_mb_valid[4] & ~sctag2_mb_young[4] & sctag2_mb_type4[5] & sctag2_mb_type4[1];
wire sctag2_mb4_wris64_ny = sctag2_mb_valid[4] & ~sctag2_mb_young[4] & sctag2_mb_type4[5] & sctag2_mb_type4[2];
wire sctag2_mb4_st_y = sctag2_mb_valid[4] & sctag2_mb_young[4] & ~sctag2_mb_type4[5] & (sctag2_mb_type4[4:0] == `STORE_RQ);
wire sctag2_mb4_ld_y = sctag2_mb_valid[4] & sctag2_mb_young[4] & ~sctag2_mb_type4[5] & (sctag2_mb_type4[4:0] == `LOAD_RQ);
wire sctag2_mb4_wris8_y = sctag2_mb_valid[4] & sctag2_mb_young[4] & sctag2_mb_type4[5] & sctag2_mb_type4[1];
wire sctag2_mb4_wris64_y = sctag2_mb_valid[4] & sctag2_mb_young[4] & sctag2_mb_type4[5] & sctag2_mb_type4[2];
wire sctag2_mb5_st_ny = sctag2_mb_valid[5] & ~sctag2_mb_young[5] & ~sctag2_mb_type5[5] & (sctag2_mb_type5[4:0] == `STORE_RQ);
wire sctag2_mb5_ld_ny = sctag2_mb_valid[5] & ~sctag2_mb_young[5] & ~sctag2_mb_type5[5] & (sctag2_mb_type5[4:0] == `LOAD_RQ);
wire sctag2_mb5_wris8_ny = sctag2_mb_valid[5] & ~sctag2_mb_young[5] & sctag2_mb_type5[5] & sctag2_mb_type5[1];
wire sctag2_mb5_wris64_ny = sctag2_mb_valid[5] & ~sctag2_mb_young[5] & sctag2_mb_type5[5] & sctag2_mb_type5[2];
wire sctag2_mb5_st_y = sctag2_mb_valid[5] & sctag2_mb_young[5] & ~sctag2_mb_type5[5] & (sctag2_mb_type5[4:0] == `STORE_RQ);
wire sctag2_mb5_ld_y = sctag2_mb_valid[5] & sctag2_mb_young[5] & ~sctag2_mb_type5[5] & (sctag2_mb_type5[4:0] == `LOAD_RQ);
wire sctag2_mb5_wris8_y = sctag2_mb_valid[5] & sctag2_mb_young[5] & sctag2_mb_type5[5] & sctag2_mb_type5[1];
wire sctag2_mb5_wris64_y = sctag2_mb_valid[5] & sctag2_mb_young[5] & sctag2_mb_type5[5] & sctag2_mb_type5[2];
wire sctag2_mb6_st_ny = sctag2_mb_valid[6] & ~sctag2_mb_young[6] & ~sctag2_mb_type6[5] & (sctag2_mb_type6[4:0] == `STORE_RQ);
wire sctag2_mb6_ld_ny = sctag2_mb_valid[6] & ~sctag2_mb_young[6] & ~sctag2_mb_type6[5] & (sctag2_mb_type6[4:0] == `LOAD_RQ);
wire sctag2_mb6_wris8_ny = sctag2_mb_valid[6] & ~sctag2_mb_young[6] & sctag2_mb_type6[5] & sctag2_mb_type6[1];
wire sctag2_mb6_wris64_ny = sctag2_mb_valid[6] & ~sctag2_mb_young[6] & sctag2_mb_type6[5] & sctag2_mb_type6[2];
wire sctag2_mb6_st_y = sctag2_mb_valid[6] & sctag2_mb_young[6] & ~sctag2_mb_type6[5] & (sctag2_mb_type6[4:0] == `STORE_RQ);
wire sctag2_mb6_ld_y = sctag2_mb_valid[6] & sctag2_mb_young[6] & ~sctag2_mb_type6[5] & (sctag2_mb_type6[4:0] == `LOAD_RQ);
wire sctag2_mb6_wris8_y = sctag2_mb_valid[6] & sctag2_mb_young[6] & sctag2_mb_type6[5] & sctag2_mb_type6[1];
wire sctag2_mb6_wris64_y = sctag2_mb_valid[6] & sctag2_mb_young[6] & sctag2_mb_type6[5] & sctag2_mb_type6[2];
wire sctag2_mb7_st_ny = sctag2_mb_valid[7] & ~sctag2_mb_young[7] & ~sctag2_mb_type7[5] & (sctag2_mb_type7[4:0] == `STORE_RQ);
wire sctag2_mb7_ld_ny = sctag2_mb_valid[7] & ~sctag2_mb_young[7] & ~sctag2_mb_type7[5] & (sctag2_mb_type7[4:0] == `LOAD_RQ);
wire sctag2_mb7_wris8_ny = sctag2_mb_valid[7] & ~sctag2_mb_young[7] & sctag2_mb_type7[5] & sctag2_mb_type7[1];
wire sctag2_mb7_wris64_ny = sctag2_mb_valid[7] & ~sctag2_mb_young[7] & sctag2_mb_type7[5] & sctag2_mb_type7[2];
wire sctag2_mb7_st_y = sctag2_mb_valid[7] & sctag2_mb_young[7] & ~sctag2_mb_type7[5] & (sctag2_mb_type7[4:0] == `STORE_RQ);
wire sctag2_mb7_ld_y = sctag2_mb_valid[7] & sctag2_mb_young[7] & ~sctag2_mb_type7[5] & (sctag2_mb_type7[4:0] == `LOAD_RQ);
wire sctag2_mb7_wris8_y = sctag2_mb_valid[7] & sctag2_mb_young[7] & sctag2_mb_type7[5] & sctag2_mb_type7[1];
wire sctag2_mb7_wris64_y = sctag2_mb_valid[7] & sctag2_mb_young[7] & sctag2_mb_type7[5] & sctag2_mb_type7[2];
wire sctag2_mb8_st_ny = sctag2_mb_valid[8] & ~sctag2_mb_young[8] & ~sctag2_mb_type8[5] & (sctag2_mb_type8[4:0] == `STORE_RQ);
wire sctag2_mb8_ld_ny = sctag2_mb_valid[8] & ~sctag2_mb_young[8] & ~sctag2_mb_type8[5] & (sctag2_mb_type8[4:0] == `LOAD_RQ);
wire sctag2_mb8_wris8_ny = sctag2_mb_valid[8] & ~sctag2_mb_young[8] & sctag2_mb_type8[5] & sctag2_mb_type8[1];
wire sctag2_mb8_wris64_ny = sctag2_mb_valid[8] & ~sctag2_mb_young[8] & sctag2_mb_type8[5] & sctag2_mb_type8[2];
wire sctag2_mb8_st_y = sctag2_mb_valid[8] & sctag2_mb_young[8] & ~sctag2_mb_type8[5] & (sctag2_mb_type8[4:0] == `STORE_RQ);
wire sctag2_mb8_ld_y = sctag2_mb_valid[8] & sctag2_mb_young[8] & ~sctag2_mb_type8[5] & (sctag2_mb_type8[4:0] == `LOAD_RQ);
wire sctag2_mb8_wris8_y = sctag2_mb_valid[8] & sctag2_mb_young[8] & sctag2_mb_type8[5] & sctag2_mb_type8[1];
wire sctag2_mb8_wris64_y = sctag2_mb_valid[8] & sctag2_mb_young[8] & sctag2_mb_type8[5] & sctag2_mb_type8[2];
wire sctag2_mb9_st_ny = sctag2_mb_valid[9] & ~sctag2_mb_young[9] & ~sctag2_mb_type9[5] & (sctag2_mb_type9[4:0] == `STORE_RQ);
wire sctag2_mb9_ld_ny = sctag2_mb_valid[9] & ~sctag2_mb_young[9] & ~sctag2_mb_type9[5] & (sctag2_mb_type9[4:0] == `LOAD_RQ);
wire sctag2_mb9_wris8_ny = sctag2_mb_valid[9] & ~sctag2_mb_young[9] & sctag2_mb_type9[5] & sctag2_mb_type9[1];
wire sctag2_mb9_wris64_ny = sctag2_mb_valid[9] & ~sctag2_mb_young[9] & sctag2_mb_type9[5] & sctag2_mb_type9[2];
wire sctag2_mb9_st_y = sctag2_mb_valid[9] & sctag2_mb_young[9] & ~sctag2_mb_type9[5] & (sctag2_mb_type9[4:0] == `STORE_RQ);
wire sctag2_mb9_ld_y = sctag2_mb_valid[9] & sctag2_mb_young[9] & ~sctag2_mb_type9[5] & (sctag2_mb_type9[4:0] == `LOAD_RQ);
wire sctag2_mb9_wris8_y = sctag2_mb_valid[9] & sctag2_mb_young[9] & sctag2_mb_type9[5] & sctag2_mb_type9[1];
wire sctag2_mb9_wris64_y = sctag2_mb_valid[9] & sctag2_mb_young[9] & sctag2_mb_type9[5] & sctag2_mb_type9[2];
wire sctag2_mb10_st_ny = sctag2_mb_valid[10] & ~sctag2_mb_young[10] & ~sctag2_mb_type10[5] & (sctag2_mb_type10[4:0] == `STORE_RQ);
wire sctag2_mb10_ld_ny = sctag2_mb_valid[10] & ~sctag2_mb_young[10] & ~sctag2_mb_type10[5] & (sctag2_mb_type10[4:0] == `LOAD_RQ);
wire sctag2_mb10_wris8_ny = sctag2_mb_valid[10] & ~sctag2_mb_young[10] & sctag2_mb_type10[5] & sctag2_mb_type10[1];
wire sctag2_mb10_wris64_ny = sctag2_mb_valid[10] & ~sctag2_mb_young[10] & sctag2_mb_type10[5] & sctag2_mb_type10[2];
wire sctag2_mb10_st_y = sctag2_mb_valid[10] & sctag2_mb_young[10] & ~sctag2_mb_type10[5] & (sctag2_mb_type10[4:0] == `STORE_RQ);
wire sctag2_mb10_ld_y = sctag2_mb_valid[10] & sctag2_mb_young[10] & ~sctag2_mb_type10[5] & (sctag2_mb_type10[4:0] == `LOAD_RQ);
wire sctag2_mb10_wris8_y = sctag2_mb_valid[10] & sctag2_mb_young[10] & sctag2_mb_type10[5] & sctag2_mb_type10[1];
wire sctag2_mb10_wris64_y = sctag2_mb_valid[10] & sctag2_mb_young[10] & sctag2_mb_type10[5] & sctag2_mb_type10[2];
wire sctag2_mb11_st_ny = sctag2_mb_valid[11] & ~sctag2_mb_young[11] & ~sctag2_mb_type11[5] & (sctag2_mb_type11[4:0] == `STORE_RQ);
wire sctag2_mb11_ld_ny = sctag2_mb_valid[11] & ~sctag2_mb_young[11] & ~sctag2_mb_type11[5] & (sctag2_mb_type11[4:0] == `LOAD_RQ);
wire sctag2_mb11_wris8_ny = sctag2_mb_valid[11] & ~sctag2_mb_young[11] & sctag2_mb_type11[5] & sctag2_mb_type11[1];
wire sctag2_mb11_wris64_ny = sctag2_mb_valid[11] & ~sctag2_mb_young[11] & sctag2_mb_type11[5] & sctag2_mb_type11[2];
wire sctag2_mb11_st_y = sctag2_mb_valid[11] & sctag2_mb_young[11] & ~sctag2_mb_type11[5] & (sctag2_mb_type11[4:0] == `STORE_RQ);
wire sctag2_mb11_ld_y = sctag2_mb_valid[11] & sctag2_mb_young[11] & ~sctag2_mb_type11[5] & (sctag2_mb_type11[4:0] == `LOAD_RQ);
wire sctag2_mb11_wris8_y = sctag2_mb_valid[11] & sctag2_mb_young[11] & sctag2_mb_type11[5] & sctag2_mb_type11[1];
wire sctag2_mb11_wris64_y = sctag2_mb_valid[11] & sctag2_mb_young[11] & sctag2_mb_type11[5] & sctag2_mb_type11[2];
wire sctag2_mb12_st_ny = sctag2_mb_valid[12] & ~sctag2_mb_young[12] & ~sctag2_mb_type12[5] & (sctag2_mb_type12[4:0] == `STORE_RQ);
wire sctag2_mb12_ld_ny = sctag2_mb_valid[12] & ~sctag2_mb_young[12] & ~sctag2_mb_type12[5] & (sctag2_mb_type12[4:0] == `LOAD_RQ);
wire sctag2_mb12_wris8_ny = sctag2_mb_valid[12] & ~sctag2_mb_young[12] & sctag2_mb_type12[5] & sctag2_mb_type12[1];
wire sctag2_mb12_wris64_ny = sctag2_mb_valid[12] & ~sctag2_mb_young[12] & sctag2_mb_type12[5] & sctag2_mb_type12[2];
wire sctag2_mb12_st_y = sctag2_mb_valid[12] & sctag2_mb_young[12] & ~sctag2_mb_type12[5] & (sctag2_mb_type12[4:0] == `STORE_RQ);
wire sctag2_mb12_ld_y = sctag2_mb_valid[12] & sctag2_mb_young[12] & ~sctag2_mb_type12[5] & (sctag2_mb_type12[4:0] == `LOAD_RQ);
wire sctag2_mb12_wris8_y = sctag2_mb_valid[12] & sctag2_mb_young[12] & sctag2_mb_type12[5] & sctag2_mb_type12[1];
wire sctag2_mb12_wris64_y = sctag2_mb_valid[12] & sctag2_mb_young[12] & sctag2_mb_type12[5] & sctag2_mb_type12[2];
wire sctag2_mb13_st_ny = sctag2_mb_valid[13] & ~sctag2_mb_young[13] & ~sctag2_mb_type13[5] & (sctag2_mb_type13[4:0] == `STORE_RQ);
wire sctag2_mb13_ld_ny = sctag2_mb_valid[13] & ~sctag2_mb_young[13] & ~sctag2_mb_type13[5] & (sctag2_mb_type13[4:0] == `LOAD_RQ);
wire sctag2_mb13_wris8_ny = sctag2_mb_valid[13] & ~sctag2_mb_young[13] & sctag2_mb_type13[5] & sctag2_mb_type13[1];
wire sctag2_mb13_wris64_ny = sctag2_mb_valid[13] & ~sctag2_mb_young[13] & sctag2_mb_type13[5] & sctag2_mb_type13[2];
wire sctag2_mb13_st_y = sctag2_mb_valid[13] & sctag2_mb_young[13] & ~sctag2_mb_type13[5] & (sctag2_mb_type13[4:0] == `STORE_RQ);
wire sctag2_mb13_ld_y = sctag2_mb_valid[13] & sctag2_mb_young[13] & ~sctag2_mb_type13[5] & (sctag2_mb_type13[4:0] == `LOAD_RQ);
wire sctag2_mb13_wris8_y = sctag2_mb_valid[13] & sctag2_mb_young[13] & sctag2_mb_type13[5] & sctag2_mb_type13[1];
wire sctag2_mb13_wris64_y = sctag2_mb_valid[13] & sctag2_mb_young[13] & sctag2_mb_type13[5] & sctag2_mb_type13[2];
wire sctag2_mb14_st_ny = sctag2_mb_valid[14] & ~sctag2_mb_young[14] & ~sctag2_mb_type14[5] & (sctag2_mb_type14[4:0] == `STORE_RQ);
wire sctag2_mb14_ld_ny = sctag2_mb_valid[14] & ~sctag2_mb_young[14] & ~sctag2_mb_type14[5] & (sctag2_mb_type14[4:0] == `LOAD_RQ);
wire sctag2_mb14_wris8_ny = sctag2_mb_valid[14] & ~sctag2_mb_young[14] & sctag2_mb_type14[5] & sctag2_mb_type14[1];
wire sctag2_mb14_wris64_ny = sctag2_mb_valid[14] & ~sctag2_mb_young[14] & sctag2_mb_type14[5] & sctag2_mb_type14[2];
wire sctag2_mb14_st_y = sctag2_mb_valid[14] & sctag2_mb_young[14] & ~sctag2_mb_type14[5] & (sctag2_mb_type14[4:0] == `STORE_RQ);
wire sctag2_mb14_ld_y = sctag2_mb_valid[14] & sctag2_mb_young[14] & ~sctag2_mb_type14[5] & (sctag2_mb_type14[4:0] == `LOAD_RQ);
wire sctag2_mb14_wris8_y = sctag2_mb_valid[14] & sctag2_mb_young[14] & sctag2_mb_type14[5] & sctag2_mb_type14[1];
wire sctag2_mb14_wris64_y = sctag2_mb_valid[14] & sctag2_mb_young[14] & sctag2_mb_type14[5] & sctag2_mb_type14[2];
wire sctag2_mb15_st_ny = sctag2_mb_valid[15] & ~sctag2_mb_young[15] & ~sctag2_mb_type15[5] & (sctag2_mb_type15[4:0] == `STORE_RQ);
wire sctag2_mb15_ld_ny = sctag2_mb_valid[15] & ~sctag2_mb_young[15] & ~sctag2_mb_type15[5] & (sctag2_mb_type15[4:0] == `LOAD_RQ);
wire sctag2_mb15_wris8_ny = sctag2_mb_valid[15] & ~sctag2_mb_young[15] & sctag2_mb_type15[5] & sctag2_mb_type15[1];
wire sctag2_mb15_wris64_ny = sctag2_mb_valid[15] & ~sctag2_mb_young[15] & sctag2_mb_type15[5] & sctag2_mb_type15[2];
wire sctag2_mb15_st_y = sctag2_mb_valid[15] & sctag2_mb_young[15] & ~sctag2_mb_type15[5] & (sctag2_mb_type15[4:0] == `STORE_RQ);
wire sctag2_mb15_ld_y = sctag2_mb_valid[15] & sctag2_mb_young[15] & ~sctag2_mb_type15[5] & (sctag2_mb_type15[4:0] == `LOAD_RQ);
wire sctag2_mb15_wris8_y = sctag2_mb_valid[15] & sctag2_mb_young[15] & sctag2_mb_type15[5] & sctag2_mb_type15[1];
wire sctag2_mb15_wris64_y = sctag2_mb_valid[15] & sctag2_mb_young[15] & sctag2_mb_type15[5] & sctag2_mb_type15[2];
wire [15:0] sctag3_mb_valid = `TOP_MEMORY.sctag3.mbctl.mb_valid[15:0];
wire [15:0] sctag3_mb_young = `TOP_MEMORY.sctag3.mbctl.mb_young[15:0];
//wire [3:0] sctag3_next_link_entry0 = `TOP_MEMORY.sctag3.mbctl.next_link_entry0[3:0];
//...
//wire [3:0] sctag3_next_link_entry15 = `TOP_MEMORY.sctag3.mbctl.next_link_entry15[3:0];
wire [155:0] sctag3_mb_data_array0 = `TOP_MEMORY.sctag3.mbdata.inq_ary[0];
wire [155:0] sctag3_mb_data_array1 = `TOP_MEMORY.sctag3.mbdata.inq_ary[1];
wire [155:0] sctag3_mb_data_array2 = `TOP_MEMORY.sctag3.mbdata.inq_ary[2];
wire [155:0] sctag3_mb_data_array3 = `TOP_MEMORY.sctag3.mbdata.inq_ary[3];
wire [155:0] sctag3_mb_data_array4 = `TOP_MEMORY.sctag3.mbdata.inq_ary[4];
wire [155:0] sctag3_mb_data_array5 = `TOP_MEMORY.sctag3.mbdata.inq_ary[5];
wire [155:0] sctag3_mb_data_array6 = `TOP_MEMORY.sctag3.mbdata.inq_ary[6];
wire [155:0] sctag3_mb_data_array7 = `TOP_MEMORY.sctag3.mbdata.inq_ary[7];
wire [155:0] sctag3_mb_data_array8 = `TOP_MEMORY.sctag3.mbdata.inq_ary[8];
wire [155:0] sctag3_mb_data_array9 = `TOP_MEMORY.sctag3.mbdata.inq_ary[9];
wire [155:0] sctag3_mb_data_array10 = `TOP_MEMORY.sctag3.mbdata.inq_ary[10];
wire [155:0] sctag3_mb_data_array11 = `TOP_MEMORY.sctag3.mbdata.inq_ary[11];
wire [155:0] sctag3_mb_data_array12 = `TOP_MEMORY.sctag3.mbdata.inq_ary[12];
wire [155:0] sctag3_mb_data_array13 = `TOP_MEMORY.sctag3.mbdata.inq_ary[13];
wire [155:0] sctag3_mb_data_array14 = `TOP_MEMORY.sctag3.mbdata.inq_ary[14];
wire [155:0] sctag3_mb_data_array15 = `TOP_MEMORY.sctag3.mbdata.inq_ary[15];
//-----------------------------------------------------------------------------------------------
// look at sctag.v for L2_RDMA_HI L2_RQTYP_HI L2_RQTYP_LO and L2_RSVD
// Based ont the equation: .mb_data_write_data({57'b0,mbdata_inst_tecc_c8...
//-----------------------------------------------------------------------------------------------
wire [5:0] sctag3_mb_type0 = {sctag3_mb_data_array0 [77], sctag3_mb_data_array0 [83:79]};
wire [5:0] sctag3_mb_type1 = {sctag3_mb_data_array1 [77], sctag3_mb_data_array1 [83:79]};
wire [5:0] sctag3_mb_type2 = {sctag3_mb_data_array2 [77], sctag3_mb_data_array2 [83:79]};
wire [5:0] sctag3_mb_type3 = {sctag3_mb_data_array3 [77], sctag3_mb_data_array3 [83:79]};
wire [5:0] sctag3_mb_type4 = {sctag3_mb_data_array4 [77], sctag3_mb_data_array4 [83:79]};
wire [5:0] sctag3_mb_type5 = {sctag3_mb_data_array5 [77], sctag3_mb_data_array5 [83:79]};
wire [5:0] sctag3_mb_type6 = {sctag3_mb_data_array6 [77], sctag3_mb_data_array6 [83:79]};
wire [5:0] sctag3_mb_type7 = {sctag3_mb_data_array7 [77], sctag3_mb_data_array7 [83:79]};
wire [5:0] sctag3_mb_type8 = {sctag3_mb_data_array8 [77], sctag3_mb_data_array8 [83:79]};
wire [5:0] sctag3_mb_type9 = {sctag3_mb_data_array9 [77], sctag3_mb_data_array9 [83:79]};
wire [5:0] sctag3_mb_type10 = {sctag3_mb_data_array10[77], sctag3_mb_data_array10[83:79]};
wire [5:0] sctag3_mb_type11 = {sctag3_mb_data_array11[77], sctag3_mb_data_array11[83:79]};
wire [5:0] sctag3_mb_type12 = {sctag3_mb_data_array12[77], sctag3_mb_data_array12[83:79]};
wire [5:0] sctag3_mb_type13 = {sctag3_mb_data_array13[77], sctag3_mb_data_array13[83:79]};
wire [5:0] sctag3_mb_type14 = {sctag3_mb_data_array14[77], sctag3_mb_data_array14[83:79]};
wire [5:0] sctag3_mb_type15 = {sctag3_mb_data_array15[77], sctag3_mb_data_array15[83:79]};
//--------------------------------------------------------------
// Start figuring out what the entries are.
// bit 5 says if this is a DMA type or normal type
//--------------------------------------------------------------
wire sctag3_mb0_st_ny = sctag3_mb_valid[0] & ~sctag3_mb_young[0] & ~sctag3_mb_type0[5] & (sctag3_mb_type0[4:0] == `STORE_RQ);
wire sctag3_mb0_ld_ny = sctag3_mb_valid[0] & ~sctag3_mb_young[0] & ~sctag3_mb_type0[5] & (sctag3_mb_type0[4:0] == `LOAD_RQ);
wire sctag3_mb0_wris8_ny = sctag3_mb_valid[0] & ~sctag3_mb_young[0] & sctag3_mb_type0[5] & sctag3_mb_type0[1];
wire sctag3_mb0_wris64_ny = sctag3_mb_valid[0] & ~sctag3_mb_young[0] & sctag3_mb_type0[5] & sctag3_mb_type0[2];
wire sctag3_mb0_st_y = sctag3_mb_valid[0] & sctag3_mb_young[0] & ~sctag3_mb_type0[5] & (sctag3_mb_type0[4:0] == `STORE_RQ);
wire sctag3_mb0_ld_y = sctag3_mb_valid[0] & sctag3_mb_young[0] & ~sctag3_mb_type0[5] & (sctag3_mb_type0[4:0] == `LOAD_RQ);
wire sctag3_mb0_wris8_y = sctag3_mb_valid[0] & sctag3_mb_young[0] & sctag3_mb_type0[5] & sctag3_mb_type0[1];
wire sctag3_mb0_wris64_y = sctag3_mb_valid[0] & sctag3_mb_young[0] & sctag3_mb_type0[5] & sctag3_mb_type0[2];
wire sctag3_mb1_st_ny = sctag3_mb_valid[1] & ~sctag3_mb_young[1] & ~sctag3_mb_type1[5] & (sctag3_mb_type1[4:0] == `STORE_RQ);
wire sctag3_mb1_ld_ny = sctag3_mb_valid[1] & ~sctag3_mb_young[1] & ~sctag3_mb_type1[5] & (sctag3_mb_type1[4:0] == `LOAD_RQ);
wire sctag3_mb1_wris8_ny = sctag3_mb_valid[1] & ~sctag3_mb_young[1] & sctag3_mb_type1[5] & sctag3_mb_type1[1];
wire sctag3_mb1_wris64_ny = sctag3_mb_valid[1] & ~sctag3_mb_young[1] & sctag3_mb_type1[5] & sctag3_mb_type1[2];
wire sctag3_mb1_st_y = sctag3_mb_valid[1] & sctag3_mb_young[1] & ~sctag3_mb_type1[5] & (sctag3_mb_type1[4:0] == `STORE_RQ);
wire sctag3_mb1_ld_y = sctag3_mb_valid[1] & sctag3_mb_young[1] & ~sctag3_mb_type1[5] & (sctag3_mb_type1[4:0] == `LOAD_RQ);
wire sctag3_mb1_wris8_y = sctag3_mb_valid[1] & sctag3_mb_young[1] & sctag3_mb_type1[5] & sctag3_mb_type1[1];
wire sctag3_mb1_wris64_y = sctag3_mb_valid[1] & sctag3_mb_young[1] & sctag3_mb_type1[5] & sctag3_mb_type1[2];
wire sctag3_mb2_st_ny = sctag3_mb_valid[2] & ~sctag3_mb_young[2] & ~sctag3_mb_type2[5] & (sctag3_mb_type2[4:0] == `STORE_RQ);
wire sctag3_mb2_ld_ny = sctag3_mb_valid[2] & ~sctag3_mb_young[2] & ~sctag3_mb_type2[5] & (sctag3_mb_type2[4:0] == `LOAD_RQ);
wire sctag3_mb2_wris8_ny = sctag3_mb_valid[2] & ~sctag3_mb_young[2] & sctag3_mb_type2[5] & sctag3_mb_type2[1];
wire sctag3_mb2_wris64_ny = sctag3_mb_valid[2] & ~sctag3_mb_young[2] & sctag3_mb_type2[5] & sctag3_mb_type2[2];
wire sctag3_mb2_st_y = sctag3_mb_valid[2] & sctag3_mb_young[2] & ~sctag3_mb_type2[5] & (sctag3_mb_type2[4:0] == `STORE_RQ);
wire sctag3_mb2_ld_y = sctag3_mb_valid[2] & sctag3_mb_young[2] & ~sctag3_mb_type2[5] & (sctag3_mb_type2[4:0] == `LOAD_RQ);
wire sctag3_mb2_wris8_y = sctag3_mb_valid[2] & sctag3_mb_young[2] & sctag3_mb_type2[5] & sctag3_mb_type2[1];
wire sctag3_mb2_wris64_y = sctag3_mb_valid[2] & sctag3_mb_young[2] & sctag3_mb_type2[5] & sctag3_mb_type2[2];
wire sctag3_mb3_st_ny = sctag3_mb_valid[3] & ~sctag3_mb_young[3] & ~sctag3_mb_type3[5] & (sctag3_mb_type3[4:0] == `STORE_RQ);
wire sctag3_mb3_ld_ny = sctag3_mb_valid[3] & ~sctag3_mb_young[3] & ~sctag3_mb_type3[5] & (sctag3_mb_type3[4:0] == `LOAD_RQ);
wire sctag3_mb3_wris8_ny = sctag3_mb_valid[3] & ~sctag3_mb_young[3] & sctag3_mb_type3[5] & sctag3_mb_type3[1];
wire sctag3_mb3_wris64_ny = sctag3_mb_valid[3] & ~sctag3_mb_young[3] & sctag3_mb_type3[5] & sctag3_mb_type3[2];
wire sctag3_mb3_st_y = sctag3_mb_valid[3] & sctag3_mb_young[3] & ~sctag3_mb_type3[5] & (sctag3_mb_type3[4:0] == `STORE_RQ);
wire sctag3_mb3_ld_y = sctag3_mb_valid[3] & sctag3_mb_young[3] & ~sctag3_mb_type3[5] & (sctag3_mb_type3[4:0] == `LOAD_RQ);
wire sctag3_mb3_wris8_y = sctag3_mb_valid[3] & sctag3_mb_young[3] & sctag3_mb_type3[5] & sctag3_mb_type3[1];
wire sctag3_mb3_wris64_y = sctag3_mb_valid[3] & sctag3_mb_young[3] & sctag3_mb_type3[5] & sctag3_mb_type3[2];
wire sctag3_mb4_st_ny = sctag3_mb_valid[4] & ~sctag3_mb_young[4] & ~sctag3_mb_type4[5] & (sctag3_mb_type4[4:0] == `STORE_RQ);
wire sctag3_mb4_ld_ny = sctag3_mb_valid[4] & ~sctag3_mb_young[4] & ~sctag3_mb_type4[5] & (sctag3_mb_type4[4:0] == `LOAD_RQ);
wire sctag3_mb4_wris8_ny = sctag3_mb_valid[4] & ~sctag3_mb_young[4] & sctag3_mb_type4[5] & sctag3_mb_type4[1];
wire sctag3_mb4_wris64_ny = sctag3_mb_valid[4] & ~sctag3_mb_young[4] & sctag3_mb_type4[5] & sctag3_mb_type4[2];
wire sctag3_mb4_st_y = sctag3_mb_valid[4] & sctag3_mb_young[4] & ~sctag3_mb_type4[5] & (sctag3_mb_type4[4:0] == `STORE_RQ);
wire sctag3_mb4_ld_y = sctag3_mb_valid[4] & sctag3_mb_young[4] & ~sctag3_mb_type4[5] & (sctag3_mb_type4[4:0] == `LOAD_RQ);
wire sctag3_mb4_wris8_y = sctag3_mb_valid[4] & sctag3_mb_young[4] & sctag3_mb_type4[5] & sctag3_mb_type4[1];
wire sctag3_mb4_wris64_y = sctag3_mb_valid[4] & sctag3_mb_young[4] & sctag3_mb_type4[5] & sctag3_mb_type4[2];
wire sctag3_mb5_st_ny = sctag3_mb_valid[5] & ~sctag3_mb_young[5] & ~sctag3_mb_type5[5] & (sctag3_mb_type5[4:0] == `STORE_RQ);
wire sctag3_mb5_ld_ny = sctag3_mb_valid[5] & ~sctag3_mb_young[5] & ~sctag3_mb_type5[5] & (sctag3_mb_type5[4:0] == `LOAD_RQ);
wire sctag3_mb5_wris8_ny = sctag3_mb_valid[5] & ~sctag3_mb_young[5] & sctag3_mb_type5[5] & sctag3_mb_type5[1];
wire sctag3_mb5_wris64_ny = sctag3_mb_valid[5] & ~sctag3_mb_young[5] & sctag3_mb_type5[5] & sctag3_mb_type5[2];
wire sctag3_mb5_st_y = sctag3_mb_valid[5] & sctag3_mb_young[5] & ~sctag3_mb_type5[5] & (sctag3_mb_type5[4:0] == `STORE_RQ);
wire sctag3_mb5_ld_y = sctag3_mb_valid[5] & sctag3_mb_young[5] & ~sctag3_mb_type5[5] & (sctag3_mb_type5[4:0] == `LOAD_RQ);
wire sctag3_mb5_wris8_y = sctag3_mb_valid[5] & sctag3_mb_young[5] & sctag3_mb_type5[5] & sctag3_mb_type5[1];
wire sctag3_mb5_wris64_y = sctag3_mb_valid[5] & sctag3_mb_young[5] & sctag3_mb_type5[5] & sctag3_mb_type5[2];
wire sctag3_mb6_st_ny = sctag3_mb_valid[6] & ~sctag3_mb_young[6] & ~sctag3_mb_type6[5] & (sctag3_mb_type6[4:0] == `STORE_RQ);
wire sctag3_mb6_ld_ny = sctag3_mb_valid[6] & ~sctag3_mb_young[6] & ~sctag3_mb_type6[5] & (sctag3_mb_type6[4:0] == `LOAD_RQ);
wire sctag3_mb6_wris8_ny = sctag3_mb_valid[6] & ~sctag3_mb_young[6] & sctag3_mb_type6[5] & sctag3_mb_type6[1];
wire sctag3_mb6_wris64_ny = sctag3_mb_valid[6] & ~sctag3_mb_young[6] & sctag3_mb_type6[5] & sctag3_mb_type6[2];
wire sctag3_mb6_st_y = sctag3_mb_valid[6] & sctag3_mb_young[6] & ~sctag3_mb_type6[5] & (sctag3_mb_type6[4:0] == `STORE_RQ);
wire sctag3_mb6_ld_y = sctag3_mb_valid[6] & sctag3_mb_young[6] & ~sctag3_mb_type6[5] & (sctag3_mb_type6[4:0] == `LOAD_RQ);
wire sctag3_mb6_wris8_y = sctag3_mb_valid[6] & sctag3_mb_young[6] & sctag3_mb_type6[5] & sctag3_mb_type6[1];
wire sctag3_mb6_wris64_y = sctag3_mb_valid[6] & sctag3_mb_young[6] & sctag3_mb_type6[5] & sctag3_mb_type6[2];
wire sctag3_mb7_st_ny = sctag3_mb_valid[7] & ~sctag3_mb_young[7] & ~sctag3_mb_type7[5] & (sctag3_mb_type7[4:0] == `STORE_RQ);
wire sctag3_mb7_ld_ny = sctag3_mb_valid[7] & ~sctag3_mb_young[7] & ~sctag3_mb_type7[5] & (sctag3_mb_type7[4:0] == `LOAD_RQ);
wire sctag3_mb7_wris8_ny = sctag3_mb_valid[7] & ~sctag3_mb_young[7] & sctag3_mb_type7[5] & sctag3_mb_type7[1];
wire sctag3_mb7_wris64_ny = sctag3_mb_valid[7] & ~sctag3_mb_young[7] & sctag3_mb_type7[5] & sctag3_mb_type7[2];
wire sctag3_mb7_st_y = sctag3_mb_valid[7] & sctag3_mb_young[7] & ~sctag3_mb_type7[5] & (sctag3_mb_type7[4:0] == `STORE_RQ);
wire sctag3_mb7_ld_y = sctag3_mb_valid[7] & sctag3_mb_young[7] & ~sctag3_mb_type7[5] & (sctag3_mb_type7[4:0] == `LOAD_RQ);
wire sctag3_mb7_wris8_y = sctag3_mb_valid[7] & sctag3_mb_young[7] & sctag3_mb_type7[5] & sctag3_mb_type7[1];
wire sctag3_mb7_wris64_y = sctag3_mb_valid[7] & sctag3_mb_young[7] & sctag3_mb_type7[5] & sctag3_mb_type7[2];
wire sctag3_mb8_st_ny = sctag3_mb_valid[8] & ~sctag3_mb_young[8] & ~sctag3_mb_type8[5] & (sctag3_mb_type8[4:0] == `STORE_RQ);
wire sctag3_mb8_ld_ny = sctag3_mb_valid[8] & ~sctag3_mb_young[8] & ~sctag3_mb_type8[5] & (sctag3_mb_type8[4:0] == `LOAD_RQ);
wire sctag3_mb8_wris8_ny = sctag3_mb_valid[8] & ~sctag3_mb_young[8] & sctag3_mb_type8[5] & sctag3_mb_type8[1];
wire sctag3_mb8_wris64_ny = sctag3_mb_valid[8] & ~sctag3_mb_young[8] & sctag3_mb_type8[5] & sctag3_mb_type8[2];
wire sctag3_mb8_st_y = sctag3_mb_valid[8] & sctag3_mb_young[8] & ~sctag3_mb_type8[5] & (sctag3_mb_type8[4:0] == `STORE_RQ);
wire sctag3_mb8_ld_y = sctag3_mb_valid[8] & sctag3_mb_young[8] & ~sctag3_mb_type8[5] & (sctag3_mb_type8[4:0] == `LOAD_RQ);
wire sctag3_mb8_wris8_y = sctag3_mb_valid[8] & sctag3_mb_young[8] & sctag3_mb_type8[5] & sctag3_mb_type8[1];
wire sctag3_mb8_wris64_y = sctag3_mb_valid[8] & sctag3_mb_young[8] & sctag3_mb_type8[5] & sctag3_mb_type8[2];
wire sctag3_mb9_st_ny = sctag3_mb_valid[9] & ~sctag3_mb_young[9] & ~sctag3_mb_type9[5] & (sctag3_mb_type9[4:0] == `STORE_RQ);
wire sctag3_mb9_ld_ny = sctag3_mb_valid[9] & ~sctag3_mb_young[9] & ~sctag3_mb_type9[5] & (sctag3_mb_type9[4:0] == `LOAD_RQ);
wire sctag3_mb9_wris8_ny = sctag3_mb_valid[9] & ~sctag3_mb_young[9] & sctag3_mb_type9[5] & sctag3_mb_type9[1];
wire sctag3_mb9_wris64_ny = sctag3_mb_valid[9] & ~sctag3_mb_young[9] & sctag3_mb_type9[5] & sctag3_mb_type9[2];
wire sctag3_mb9_st_y = sctag3_mb_valid[9] & sctag3_mb_young[9] & ~sctag3_mb_type9[5] & (sctag3_mb_type9[4:0] == `STORE_RQ);
wire sctag3_mb9_ld_y = sctag3_mb_valid[9] & sctag3_mb_young[9] & ~sctag3_mb_type9[5] & (sctag3_mb_type9[4:0] == `LOAD_RQ);
wire sctag3_mb9_wris8_y = sctag3_mb_valid[9] & sctag3_mb_young[9] & sctag3_mb_type9[5] & sctag3_mb_type9[1];
wire sctag3_mb9_wris64_y = sctag3_mb_valid[9] & sctag3_mb_young[9] & sctag3_mb_type9[5] & sctag3_mb_type9[2];
wire sctag3_mb10_st_ny = sctag3_mb_valid[10] & ~sctag3_mb_young[10] & ~sctag3_mb_type10[5] & (sctag3_mb_type10[4:0] == `STORE_RQ);
wire sctag3_mb10_ld_ny = sctag3_mb_valid[10] & ~sctag3_mb_young[10] & ~sctag3_mb_type10[5] & (sctag3_mb_type10[4:0] == `LOAD_RQ);
wire sctag3_mb10_wris8_ny = sctag3_mb_valid[10] & ~sctag3_mb_young[10] & sctag3_mb_type10[5] & sctag3_mb_type10[1];
wire sctag3_mb10_wris64_ny = sctag3_mb_valid[10] & ~sctag3_mb_young[10] & sctag3_mb_type10[5] & sctag3_mb_type10[2];
wire sctag3_mb10_st_y = sctag3_mb_valid[10] & sctag3_mb_young[10] & ~sctag3_mb_type10[5] & (sctag3_mb_type10[4:0] == `STORE_RQ);
wire sctag3_mb10_ld_y = sctag3_mb_valid[10] & sctag3_mb_young[10] & ~sctag3_mb_type10[5] & (sctag3_mb_type10[4:0] == `LOAD_RQ);
wire sctag3_mb10_wris8_y = sctag3_mb_valid[10] & sctag3_mb_young[10] & sctag3_mb_type10[5] & sctag3_mb_type10[1];
wire sctag3_mb10_wris64_y = sctag3_mb_valid[10] & sctag3_mb_young[10] & sctag3_mb_type10[5] & sctag3_mb_type10[2];
wire sctag3_mb11_st_ny = sctag3_mb_valid[11] & ~sctag3_mb_young[11] & ~sctag3_mb_type11[5] & (sctag3_mb_type11[4:0] == `STORE_RQ);
wire sctag3_mb11_ld_ny = sctag3_mb_valid[11] & ~sctag3_mb_young[11] & ~sctag3_mb_type11[5] & (sctag3_mb_type11[4:0] == `LOAD_RQ);
wire sctag3_mb11_wris8_ny = sctag3_mb_valid[11] & ~sctag3_mb_young[11] & sctag3_mb_type11[5] & sctag3_mb_type11[1];
wire sctag3_mb11_wris64_ny = sctag3_mb_valid[11] & ~sctag3_mb_young[11] & sctag3_mb_type11[5] & sctag3_mb_type11[2];
wire sctag3_mb11_st_y = sctag3_mb_valid[11] & sctag3_mb_young[11] & ~sctag3_mb_type11[5] & (sctag3_mb_type11[4:0] == `STORE_RQ);
wire sctag3_mb11_ld_y = sctag3_mb_valid[11] & sctag3_mb_young[11] & ~sctag3_mb_type11[5] & (sctag3_mb_type11[4:0] == `LOAD_RQ);
wire sctag3_mb11_wris8_y = sctag3_mb_valid[11] & sctag3_mb_young[11] & sctag3_mb_type11[5] & sctag3_mb_type11[1];
wire sctag3_mb11_wris64_y = sctag3_mb_valid[11] & sctag3_mb_young[11] & sctag3_mb_type11[5] & sctag3_mb_type11[2];
wire sctag3_mb12_st_ny = sctag3_mb_valid[12] & ~sctag3_mb_young[12] & ~sctag3_mb_type12[5] & (sctag3_mb_type12[4:0] == `STORE_RQ);
wire sctag3_mb12_ld_ny = sctag3_mb_valid[12] & ~sctag3_mb_young[12] & ~sctag3_mb_type12[5] & (sctag3_mb_type12[4:0] == `LOAD_RQ);
wire sctag3_mb12_wris8_ny = sctag3_mb_valid[12] & ~sctag3_mb_young[12] & sctag3_mb_type12[5] & sctag3_mb_type12[1];
wire sctag3_mb12_wris64_ny = sctag3_mb_valid[12] & ~sctag3_mb_young[12] & sctag3_mb_type12[5] & sctag3_mb_type12[2];
wire sctag3_mb12_st_y = sctag3_mb_valid[12] & sctag3_mb_young[12] & ~sctag3_mb_type12[5] & (sctag3_mb_type12[4:0] == `STORE_RQ);
wire sctag3_mb12_ld_y = sctag3_mb_valid[12] & sctag3_mb_young[12] & ~sctag3_mb_type12[5] & (sctag3_mb_type12[4:0] == `LOAD_RQ);
wire sctag3_mb12_wris8_y = sctag3_mb_valid[12] & sctag3_mb_young[12] & sctag3_mb_type12[5] & sctag3_mb_type12[1];
wire sctag3_mb12_wris64_y = sctag3_mb_valid[12] & sctag3_mb_young[12] & sctag3_mb_type12[5] & sctag3_mb_type12[2];
wire sctag3_mb13_st_ny = sctag3_mb_valid[13] & ~sctag3_mb_young[13] & ~sctag3_mb_type13[5] & (sctag3_mb_type13[4:0] == `STORE_RQ);
wire sctag3_mb13_ld_ny = sctag3_mb_valid[13] & ~sctag3_mb_young[13] & ~sctag3_mb_type13[5] & (sctag3_mb_type13[4:0] == `LOAD_RQ);
wire sctag3_mb13_wris8_ny = sctag3_mb_valid[13] & ~sctag3_mb_young[13] & sctag3_mb_type13[5] & sctag3_mb_type13[1];
wire sctag3_mb13_wris64_ny = sctag3_mb_valid[13] & ~sctag3_mb_young[13] & sctag3_mb_type13[5] & sctag3_mb_type13[2];
wire sctag3_mb13_st_y = sctag3_mb_valid[13] & sctag3_mb_young[13] & ~sctag3_mb_type13[5] & (sctag3_mb_type13[4:0] == `STORE_RQ);
wire sctag3_mb13_ld_y = sctag3_mb_valid[13] & sctag3_mb_young[13] & ~sctag3_mb_type13[5] & (sctag3_mb_type13[4:0] == `LOAD_RQ);
wire sctag3_mb13_wris8_y = sctag3_mb_valid[13] & sctag3_mb_young[13] & sctag3_mb_type13[5] & sctag3_mb_type13[1];
wire sctag3_mb13_wris64_y = sctag3_mb_valid[13] & sctag3_mb_young[13] & sctag3_mb_type13[5] & sctag3_mb_type13[2];
wire sctag3_mb14_st_ny = sctag3_mb_valid[14] & ~sctag3_mb_young[14] & ~sctag3_mb_type14[5] & (sctag3_mb_type14[4:0] == `STORE_RQ);
wire sctag3_mb14_ld_ny = sctag3_mb_valid[14] & ~sctag3_mb_young[14] & ~sctag3_mb_type14[5] & (sctag3_mb_type14[4:0] == `LOAD_RQ);
wire sctag3_mb14_wris8_ny = sctag3_mb_valid[14] & ~sctag3_mb_young[14] & sctag3_mb_type14[5] & sctag3_mb_type14[1];
wire sctag3_mb14_wris64_ny = sctag3_mb_valid[14] & ~sctag3_mb_young[14] & sctag3_mb_type14[5] & sctag3_mb_type14[2];
wire sctag3_mb14_st_y = sctag3_mb_valid[14] & sctag3_mb_young[14] & ~sctag3_mb_type14[5] & (sctag3_mb_type14[4:0] == `STORE_RQ);
wire sctag3_mb14_ld_y = sctag3_mb_valid[14] & sctag3_mb_young[14] & ~sctag3_mb_type14[5] & (sctag3_mb_type14[4:0] == `LOAD_RQ);
wire sctag3_mb14_wris8_y = sctag3_mb_valid[14] & sctag3_mb_young[14] & sctag3_mb_type14[5] & sctag3_mb_type14[1];
wire sctag3_mb14_wris64_y = sctag3_mb_valid[14] & sctag3_mb_young[14] & sctag3_mb_type14[5] & sctag3_mb_type14[2];
wire sctag3_mb15_st_ny = sctag3_mb_valid[15] & ~sctag3_mb_young[15] & ~sctag3_mb_type15[5] & (sctag3_mb_type15[4:0] == `STORE_RQ);
wire sctag3_mb15_ld_ny = sctag3_mb_valid[15] & ~sctag3_mb_young[15] & ~sctag3_mb_type15[5] & (sctag3_mb_type15[4:0] == `LOAD_RQ);
wire sctag3_mb15_wris8_ny = sctag3_mb_valid[15] & ~sctag3_mb_young[15] & sctag3_mb_type15[5] & sctag3_mb_type15[1];
wire sctag3_mb15_wris64_ny = sctag3_mb_valid[15] & ~sctag3_mb_young[15] & sctag3_mb_type15[5] & sctag3_mb_type15[2];
wire sctag3_mb15_st_y = sctag3_mb_valid[15] & sctag3_mb_young[15] & ~sctag3_mb_type15[5] & (sctag3_mb_type15[4:0] == `STORE_RQ);
wire sctag3_mb15_ld_y = sctag3_mb_valid[15] & sctag3_mb_young[15] & ~sctag3_mb_type15[5] & (sctag3_mb_type15[4:0] == `LOAD_RQ);
wire sctag3_mb15_wris8_y = sctag3_mb_valid[15] & sctag3_mb_young[15] & sctag3_mb_type15[5] & sctag3_mb_type15[1];
wire sctag3_mb15_wris64_y = sctag3_mb_valid[15] & sctag3_mb_young[15] & sctag3_mb_type15[5] & sctag3_mb_type15[2];
//==========================================================================================
// L2 pipeline stuff. Detecting miss/hit combinations of stores.
//==========================================================================================
wire [`L2_FBF:`L2_SZ_LO] sctag0_inst_c2 = `TOP_MEMORY.sctag0.arbdecdp.arbdp_inst_c2;
wire [39:0] sctag0_addr_c2 = `TOP_MEMORY.sctag0.arbaddrdp.arbdp_addr_c2;
wire sctag0_tagctl_hit_c2 = `TOP_MEMORY.sctag0.tagctl.tagctl_hit_c2;
wire sctag0_inst_vld_c2 = `TOP_MEMORY.sctag0.arbctl_inst_vld_c2;
wire sctag0_mbctl_tagctl_hit_unqual_c2 = `TOP_MEMORY.sctag0.mbctl_tagctl_hit_unqual_c2;
wire sctag0_l2_enable = ~`TOP_MEMORY.sctag0.l2_bypass_mode_on;
wire sctag0_l2_dir_map_on = `TOP_MEMORY.sctag0.l2_dir_map_on;
// A store which does not hit in the L2 miss buffer
//-------------------------------------------------
wire store0 = (sctag0_inst_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STORE_RQ) & ~sctag0_inst_c2[`L2_RSVD] |
sctag0_inst_vld_c2 & ~sctag0_mbctl_tagctl_hit_unqual_c2;
wire wris80 = sctag0_inst_c2[`L2_RQTYP_LO + 1] & sctag0_inst_c2[`L2_RSVD] &
sctag0_inst_vld_c2 & ~sctag0_mbctl_tagctl_hit_unqual_c2;
wire wris640= sctag0_inst_c2[`L2_RQTYP_LO + 2] & sctag0_inst_c2[`L2_RSVD] &
sctag0_inst_vld_c2 & ~sctag0_mbctl_tagctl_hit_unqual_c2;
wire load0 = (sctag0_inst_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `LOAD_RQ) & ~sctag0_inst_c2[`L2_RSVD] &
sctag0_inst_vld_c2 & ~sctag0_mbctl_tagctl_hit_unqual_c2;
wire ldd0 = sctag0_inst_c2[`L2_RQTYP_LO] & sctag0_inst_c2[`L2_RSVD] &
sctag0_inst_vld_c2 & ~sctag0_mbctl_tagctl_hit_unqual_c2;
wire [`L2_FBF:`L2_SZ_LO] sctag1_inst_c2 = `TOP_MEMORY.sctag1.arbdecdp.arbdp_inst_c2;
wire [39:0] sctag1_addr_c2 = `TOP_MEMORY.sctag1.arbaddrdp.arbdp_addr_c2;
wire sctag1_tagctl_hit_c2 = `TOP_MEMORY.sctag1.tagctl.tagctl_hit_c2;
wire sctag1_inst_vld_c2 = `TOP_MEMORY.sctag1.arbctl_inst_vld_c2;
wire sctag1_mbctl_tagctl_hit_unqual_c2 = `TOP_MEMORY.sctag1.mbctl_tagctl_hit_unqual_c2;
wire sctag1_l2_enable = ~`TOP_MEMORY.sctag1.l2_bypass_mode_on;
wire sctag1_l2_dir_map_on = `TOP_MEMORY.sctag1.l2_dir_map_on;
// A store which does not hit in the L2 miss buffer
//-------------------------------------------------
wire store1 = (sctag1_inst_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STORE_RQ) & ~sctag1_inst_c2[`L2_RSVD] |
sctag1_inst_vld_c2 & ~sctag1_mbctl_tagctl_hit_unqual_c2;
wire wris81 = sctag1_inst_c2[`L2_RQTYP_LO + 1] & sctag1_inst_c2[`L2_RSVD] &
sctag1_inst_vld_c2 & ~sctag1_mbctl_tagctl_hit_unqual_c2;
wire wris641= sctag1_inst_c2[`L2_RQTYP_LO + 2] & sctag1_inst_c2[`L2_RSVD] &
sctag1_inst_vld_c2 & ~sctag1_mbctl_tagctl_hit_unqual_c2;
wire load1 = (sctag1_inst_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `LOAD_RQ) & ~sctag1_inst_c2[`L2_RSVD] &
sctag1_inst_vld_c2 & ~sctag1_mbctl_tagctl_hit_unqual_c2;
wire ldd1 = sctag1_inst_c2[`L2_RQTYP_LO] & sctag1_inst_c2[`L2_RSVD] &
sctag1_inst_vld_c2 & ~sctag1_mbctl_tagctl_hit_unqual_c2;
wire [`L2_FBF:`L2_SZ_LO] sctag2_inst_c2 = `TOP_MEMORY.sctag2.arbdecdp.arbdp_inst_c2;
wire [39:0] sctag2_addr_c2 = `TOP_MEMORY.sctag2.arbaddrdp.arbdp_addr_c2;
wire sctag2_tagctl_hit_c2 = `TOP_MEMORY.sctag2.tagctl.tagctl_hit_c2;
wire sctag2_inst_vld_c2 = `TOP_MEMORY.sctag2.arbctl_inst_vld_c2;
wire sctag2_mbctl_tagctl_hit_unqual_c2 = `TOP_MEMORY.sctag2.mbctl_tagctl_hit_unqual_c2;
wire sctag2_l2_enable = ~`TOP_MEMORY.sctag2.l2_bypass_mode_on;
wire sctag2_l2_dir_map_on = `TOP_MEMORY.sctag2.l2_dir_map_on;
// A store which does not hit in the L2 miss buffer
//-------------------------------------------------
wire store2 = (sctag2_inst_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STORE_RQ) & ~sctag2_inst_c2[`L2_RSVD] |
sctag2_inst_vld_c2 & ~sctag2_mbctl_tagctl_hit_unqual_c2;
wire wris82 = sctag2_inst_c2[`L2_RQTYP_LO + 1] & sctag2_inst_c2[`L2_RSVD] &
sctag2_inst_vld_c2 & ~sctag2_mbctl_tagctl_hit_unqual_c2;
wire wris642= sctag2_inst_c2[`L2_RQTYP_LO + 2] & sctag2_inst_c2[`L2_RSVD] &
sctag2_inst_vld_c2 & ~sctag2_mbctl_tagctl_hit_unqual_c2;
wire load2 = (sctag2_inst_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `LOAD_RQ) & ~sctag2_inst_c2[`L2_RSVD] &
sctag2_inst_vld_c2 & ~sctag2_mbctl_tagctl_hit_unqual_c2;
wire ldd2 = sctag2_inst_c2[`L2_RQTYP_LO] & sctag2_inst_c2[`L2_RSVD] &
sctag2_inst_vld_c2 & ~sctag2_mbctl_tagctl_hit_unqual_c2;
wire [`L2_FBF:`L2_SZ_LO] sctag3_inst_c2 = `TOP_MEMORY.sctag3.arbdecdp.arbdp_inst_c2;
wire [39:0] sctag3_addr_c2 = `TOP_MEMORY.sctag3.arbaddrdp.arbdp_addr_c2;
wire sctag3_tagctl_hit_c2 = `TOP_MEMORY.sctag3.tagctl.tagctl_hit_c2;
wire sctag3_inst_vld_c2 = `TOP_MEMORY.sctag3.arbctl_inst_vld_c2;
wire sctag3_mbctl_tagctl_hit_unqual_c2 = `TOP_MEMORY.sctag3.mbctl_tagctl_hit_unqual_c2;
wire sctag3_l2_enable = ~`TOP_MEMORY.sctag3.l2_bypass_mode_on;
wire sctag3_l2_dir_map_on = `TOP_MEMORY.sctag3.l2_dir_map_on;
// A store which does not hit in the L2 miss buffer
//-------------------------------------------------
wire store3 = (sctag3_inst_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STORE_RQ) & ~sctag3_inst_c2[`L2_RSVD] |
sctag3_inst_vld_c2 & ~sctag3_mbctl_tagctl_hit_unqual_c2;
wire wris83 = sctag3_inst_c2[`L2_RQTYP_LO + 1] & sctag3_inst_c2[`L2_RSVD] &
sctag3_inst_vld_c2 & ~sctag3_mbctl_tagctl_hit_unqual_c2;
wire wris643= sctag3_inst_c2[`L2_RQTYP_LO + 2] & sctag3_inst_c2[`L2_RSVD] &
sctag3_inst_vld_c2 & ~sctag3_mbctl_tagctl_hit_unqual_c2;
wire load3 = (sctag3_inst_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `LOAD_RQ) & ~sctag3_inst_c2[`L2_RSVD] &
sctag3_inst_vld_c2 & ~sctag3_mbctl_tagctl_hit_unqual_c2;
wire ldd3 = sctag3_inst_c2[`L2_RQTYP_LO] & sctag3_inst_c2[`L2_RSVD] &
sctag3_inst_vld_c2 & ~sctag3_mbctl_tagctl_hit_unqual_c2;
wire[3:0] l2_enable = {sctag3_l2_enable, sctag2_l2_enable, sctag1_l2_enable, sctag0_l2_enable};
always @(l2_enable)
$display("%0d tso_mon: l2_enable changed to %x", $time, l2_enable);
wire[3:0] l2_dir_map_on = {sctag3_l2_dir_map_on, sctag2_l2_dir_map_on, sctag1_l2_dir_map_on, sctag0_l2_dir_map_on};
always @(l2_dir_map_on)
$display("%0d tso_mon: l2_dir_map_on changed to %x", $time, l2_dir_map_on);
//==========================================================================================
// Some FSM-s for coverage - NOT very important
`define L2_FSM_IDLE 4'b0000
`define L2_FSM_ST1 4'b0001
`define L2_FSM_ST2M 4'b0010
`define L2_FSM_LD1M 4'b0011
`define L2_FSM_LD2M 4'b0100
`define L2_FSM_ST2H 4'b0101
`define L2_FSM_LD1H 4'b0110
`define L2_FSM_LD2H 4'b0111
//==========================================================================================
reg [3:0] l2_fsm1;
integer l2_fsm1_counter;
reg [39:8] l2_fsm1_addr1, l2_fsm1_addr2;
reg [4:0] l2_fsm1_id1, l2_fsm1_id2;
always @(posedge clk)
begin
if(~rst_l)
l2_fsm1_counter <= 0;
else if(l2_fsm1 == `L2_FSM_IDLE)
l2_fsm1_counter <= 0;
else
l2_fsm1_counter <= l2_fsm1_counter + 1;
if(~rst_l)
begin
l2_fsm1 <= `L2_FSM_IDLE;
end
// A first store not issued from miss buffer
//-------------------------------------------------------------------------------
else if(store0 & ~sctag0_inst_c2[`L2_MBF] & ~sctag0_tagctl_hit_c2 & (l2_fsm1 == `L2_FSM_IDLE))
begin
l2_fsm1_addr1 <= sctag0_addr_c2[39:8];
l2_fsm1_id1 <= sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm1 <= `L2_FSM_ST1;
end
else if(store1 & ~sctag1_inst_c2[`L2_MBF] & ~sctag1_tagctl_hit_c2 & (l2_fsm1 == `L2_FSM_IDLE))
begin
l2_fsm1_addr1 <= sctag1_addr_c2[39:8];
l2_fsm1_id1 <= sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm1 <= `L2_FSM_ST1;
end
else if(store2 & ~sctag2_inst_c2[`L2_MBF] & ~sctag2_tagctl_hit_c2 & (l2_fsm1 == `L2_FSM_IDLE))
begin
l2_fsm1_addr1 <= sctag2_addr_c2[39:8];
l2_fsm1_id1 <= sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm1 <= `L2_FSM_ST1;
end
else if(store3 & ~sctag3_inst_c2[`L2_MBF] & ~sctag3_tagctl_hit_c2 & (l2_fsm1 == `L2_FSM_IDLE))
begin
l2_fsm1_addr1 <= sctag3_addr_c2[39:8];
l2_fsm1_id1 <= sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm1 <= `L2_FSM_ST1;
end
// The second store - may be a miss or a hit
//-------------------------------------------------------------------------------
else if(store0 & ~sctag0_inst_c2[`L2_MBF] & (l2_fsm1 == `L2_FSM_ST1))
begin
l2_fsm1_addr2 <= sctag0_addr_c2[39:8];
l2_fsm1_id2 <= sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm1 <= sctag0_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(store1 & ~sctag1_inst_c2[`L2_MBF] & (l2_fsm1 == `L2_FSM_ST1))
begin
l2_fsm1_addr2 <= sctag1_addr_c2[39:8];
l2_fsm1_id2 <= sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm1 <= sctag1_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(store2 & ~sctag2_inst_c2[`L2_MBF] & (l2_fsm1 == `L2_FSM_ST1))
begin
l2_fsm1_addr2 <= sctag2_addr_c2[39:8];
l2_fsm1_id2 <= sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm1 <= sctag2_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(store3 & ~sctag3_inst_c2[`L2_MBF] & (l2_fsm1 == `L2_FSM_ST1))
begin
l2_fsm1_addr2 <= sctag3_addr_c2[39:8];
l2_fsm1_id2 <= sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm1 <= sctag3_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
// A load to address2 is a hit or returned already
// the load is eaither not starting from the L2 MB and is a hit
// or is starting from the L2MB.
//-------------------------------------------------------------------------------
else if(load0 & (~sctag0_inst_c2[`L2_MBF] & sctag0_tagctl_hit_c2 |
~sctag0_inst_c2[`L2_EVICT] & sctag0_inst_c2[`L2_MBF]) &
((l2_fsm1 == `L2_FSM_ST2M) | (l2_fsm1 == `L2_FSM_ST2H)) &
(sctag0_addr_c2[39:8] == l2_fsm1_addr2[39:8]))
begin
if(l2_fsm1 == `L2_FSM_ST2M) l2_fsm1 <= `L2_FSM_LD1M;
else l2_fsm1 <= `L2_FSM_LD1H;
end
else if(load1 & (~sctag1_inst_c2[`L2_MBF] & sctag1_tagctl_hit_c2 |
~sctag1_inst_c2[`L2_EVICT] & sctag1_inst_c2[`L2_MBF]) &
((l2_fsm1 == `L2_FSM_ST2M) | (l2_fsm1 == `L2_FSM_ST2H)) &
(sctag1_addr_c2[39:8] == l2_fsm1_addr2[39:8]))
begin
if(l2_fsm1 == `L2_FSM_ST2M) l2_fsm1 <= `L2_FSM_LD1M;
else l2_fsm1 <= `L2_FSM_LD1H;
end
else if(load2 & (~sctag2_inst_c2[`L2_MBF] & sctag2_tagctl_hit_c2 |
~sctag2_inst_c2[`L2_EVICT] & sctag2_inst_c2[`L2_MBF]) &
((l2_fsm1 == `L2_FSM_ST2M) | (l2_fsm1 == `L2_FSM_ST2H)) &
(sctag2_addr_c2[39:8] == l2_fsm1_addr2[39:8]))
begin
if(l2_fsm1 == `L2_FSM_ST2M) l2_fsm1 <= `L2_FSM_LD1M;
else l2_fsm1 <= `L2_FSM_LD1H;
end
else if(load3 & (~sctag3_inst_c2[`L2_MBF] & sctag3_tagctl_hit_c2 |
~sctag3_inst_c2[`L2_EVICT] & sctag3_inst_c2[`L2_MBF]) &
((l2_fsm1 == `L2_FSM_ST2M) | (l2_fsm1 == `L2_FSM_ST2H)) &
(sctag3_addr_c2[39:8] == l2_fsm1_addr2[39:8]))
begin
if(l2_fsm1 == `L2_FSM_ST2M) l2_fsm1 <= `L2_FSM_LD1M;
else l2_fsm1 <= `L2_FSM_LD1H;
end
// A load to address1 is a miss.
//-------------------------------------------------------------------------------
else if(load0 & ~sctag0_tagctl_hit_c2 &
((l2_fsm1 == `L2_FSM_LD1M) | (l2_fsm1 == `L2_FSM_LD1H)) &
(sctag0_addr_c2[39:8] == l2_fsm1_addr1))
begin
if(l2_fsm1 == `L2_FSM_LD1M) l2_fsm1 <= `L2_FSM_LD2M;
else l2_fsm1 <= `L2_FSM_LD2H;
end
else if(load1 & ~sctag1_tagctl_hit_c2 &
((l2_fsm1 == `L2_FSM_LD1M) | (l2_fsm1 == `L2_FSM_LD1H)) &
(sctag1_addr_c2[39:8] == l2_fsm1_addr1))
begin
if(l2_fsm1 == `L2_FSM_LD1M) l2_fsm1 <= `L2_FSM_LD2M;
else l2_fsm1 <= `L2_FSM_LD2H;
end
else if(load2 & ~sctag2_tagctl_hit_c2 &
((l2_fsm1 == `L2_FSM_LD1M) | (l2_fsm1 == `L2_FSM_LD1H)) &
(sctag2_addr_c2[39:8] == l2_fsm1_addr1))
begin
if(l2_fsm1 == `L2_FSM_LD1M) l2_fsm1 <= `L2_FSM_LD2M;
else l2_fsm1 <= `L2_FSM_LD2H;
end
else if(load3 & ~sctag3_tagctl_hit_c2 &
((l2_fsm1 == `L2_FSM_LD1M) | (l2_fsm1 == `L2_FSM_LD1H)) &
(sctag3_addr_c2[39:8] == l2_fsm1_addr1))
begin
if(l2_fsm1 == `L2_FSM_LD1M) l2_fsm1 <= `L2_FSM_LD2M;
else l2_fsm1 <= `L2_FSM_LD2H;
end
//-------------------------------------------
// returning the FSM to idle stuff
// when the original store does the last pass.
//-------------------------------------------
else if(store0 & (sctag0_addr_c2[39:8] == l2_fsm1_addr1[39:8]) &
(sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm1_id1) &
~sctag0_inst_c2[`L2_EVICT] & sctag0_inst_c2[`L2_MBF])
l2_fsm1 <= `L2_FSM_IDLE;
else if(store1 & (sctag1_addr_c2[39:8] == l2_fsm1_addr1[39:8]) &
(sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm1_id1) &
~sctag1_inst_c2[`L2_EVICT] & sctag1_inst_c2[`L2_MBF])
l2_fsm1 <= `L2_FSM_IDLE;
else if(store2 & (sctag2_addr_c2[39:8] == l2_fsm1_addr1[39:8]) &
(sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm1_id1) &
~sctag2_inst_c2[`L2_EVICT] & sctag2_inst_c2[`L2_MBF])
l2_fsm1 <= `L2_FSM_IDLE;
else if(store3 & (sctag3_addr_c2[39:8] == l2_fsm1_addr1[39:8]) &
(sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm1_id1) &
~sctag3_inst_c2[`L2_EVICT] & sctag3_inst_c2[`L2_MBF])
l2_fsm1 <= `L2_FSM_IDLE;
else if(l2_fsm1_counter > 1000)
l2_fsm1 <= `L2_FSM_IDLE;
end
//==========================================================================================
reg [3:0] l2_fsm2;
integer l2_fsm2_counter;
reg [39:8] l2_fsm2_addr1, l2_fsm2_addr2;
reg [4:0] l2_fsm2_id1, l2_fsm2_id2;
always @(posedge clk)
begin
if(~rst_l)
l2_fsm2_counter <= 0;
else if(l2_fsm2 == `L2_FSM_IDLE)
l2_fsm2_counter <= 0;
else
l2_fsm2_counter <= l2_fsm2_counter + 1;
if(~rst_l)
begin
l2_fsm2 <= `L2_FSM_IDLE;
end
// A first store or wris8 not issued from miss buffer.
//-------------------------------------------------------------------------------
else if(wris640 & ~sctag0_inst_c2[`L2_MBF] & ~sctag0_tagctl_hit_c2 & (l2_fsm2 == `L2_FSM_IDLE))
begin
l2_fsm2_addr1 <= sctag0_addr_c2[39:8];
l2_fsm2_id1 <= sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm2 <= `L2_FSM_ST1;
end
else if(wris641 & ~sctag1_inst_c2[`L2_MBF] & ~sctag1_tagctl_hit_c2 & (l2_fsm2 == `L2_FSM_IDLE))
begin
l2_fsm2_addr1 <= sctag1_addr_c2[39:8];
l2_fsm2_id1 <= sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm2 <= `L2_FSM_ST1;
end
else if(wris642 & ~sctag2_inst_c2[`L2_MBF] & ~sctag2_tagctl_hit_c2 & (l2_fsm2 == `L2_FSM_IDLE))
begin
l2_fsm2_addr1 <= sctag2_addr_c2[39:8];
l2_fsm2_id1 <= sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm2 <= `L2_FSM_ST1;
end
else if(wris643 & ~sctag3_inst_c2[`L2_MBF] & ~sctag3_tagctl_hit_c2 & (l2_fsm2 == `L2_FSM_IDLE))
begin
l2_fsm2_addr1 <= sctag3_addr_c2[39:8];
l2_fsm2_id1 <= sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm2 <= `L2_FSM_ST1;
end
// The second store - may be a miss or a hit
//-------------------------------------------------------------------------------
else if(wris640 & ~sctag0_inst_c2[`L2_MBF] & (l2_fsm2 == `L2_FSM_ST1))
begin
l2_fsm2_addr2 <= sctag0_addr_c2[39:8];
l2_fsm2_id2 <= sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm2 <= sctag0_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(wris641 & ~sctag1_inst_c2[`L2_MBF] & (l2_fsm2 == `L2_FSM_ST1))
begin
l2_fsm2_addr2 <= sctag1_addr_c2[39:8];
l2_fsm2_id2 <= sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm2 <= sctag1_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(wris642 & ~sctag2_inst_c2[`L2_MBF] & (l2_fsm2 == `L2_FSM_ST1))
begin
l2_fsm2_addr2 <= sctag2_addr_c2[39:8];
l2_fsm2_id2 <= sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm2 <= sctag2_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(wris643 & ~sctag3_inst_c2[`L2_MBF] & (l2_fsm2 == `L2_FSM_ST1))
begin
l2_fsm2_addr2 <= sctag3_addr_c2[39:8];
l2_fsm2_id2 <= sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm2 <= sctag3_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
// A load to address2 is a hit or returned already
// the load is eaither not starting from the L2 MB and is a hit
// or is starting from the L2MB.
//-------------------------------------------------------------------------------
else if(load0 & (~sctag0_inst_c2[`L2_MBF] & sctag0_tagctl_hit_c2 |
~sctag0_inst_c2[`L2_EVICT] & sctag0_inst_c2[`L2_MBF]) &
((l2_fsm2 == `L2_FSM_ST2M) | (l2_fsm2 == `L2_FSM_ST2H)) &
(sctag0_addr_c2[39:8] == l2_fsm2_addr2[39:8]))
begin
if(l2_fsm2 == `L2_FSM_ST2M) l2_fsm2 <= `L2_FSM_LD1M;
else l2_fsm2 <= `L2_FSM_LD1H;
end
else if(load1 & (~sctag1_inst_c2[`L2_MBF] & sctag1_tagctl_hit_c2 |
~sctag1_inst_c2[`L2_EVICT] & sctag1_inst_c2[`L2_MBF]) &
((l2_fsm2 == `L2_FSM_ST2M) | (l2_fsm2 == `L2_FSM_ST2H)) &
(sctag1_addr_c2[39:8] == l2_fsm2_addr2[39:8]))
begin
if(l2_fsm2 == `L2_FSM_ST2M) l2_fsm2 <= `L2_FSM_LD1M;
else l2_fsm2 <= `L2_FSM_LD1H;
end
else if(load2 & (~sctag2_inst_c2[`L2_MBF] & sctag2_tagctl_hit_c2 |
~sctag2_inst_c2[`L2_EVICT] & sctag2_inst_c2[`L2_MBF]) &
((l2_fsm2 == `L2_FSM_ST2M) | (l2_fsm2 == `L2_FSM_ST2H)) &
(sctag2_addr_c2[39:8] == l2_fsm2_addr2[39:8]))
begin
if(l2_fsm2 == `L2_FSM_ST2M) l2_fsm2 <= `L2_FSM_LD1M;
else l2_fsm2 <= `L2_FSM_LD1H;
end
else if(load3 & (~sctag3_inst_c2[`L2_MBF] & sctag3_tagctl_hit_c2 |
~sctag3_inst_c2[`L2_EVICT] & sctag3_inst_c2[`L2_MBF]) &
((l2_fsm2 == `L2_FSM_ST2M) | (l2_fsm2 == `L2_FSM_ST2H)) &
(sctag3_addr_c2[39:8] == l2_fsm2_addr2[39:8]))
begin
if(l2_fsm2 == `L2_FSM_ST2M) l2_fsm2 <= `L2_FSM_LD1M;
else l2_fsm2 <= `L2_FSM_LD1H;
end
// A load to address1 is a miss.
//-------------------------------------------------------------------------------
else if(load0 & ~sctag0_tagctl_hit_c2 &
((l2_fsm2 == `L2_FSM_LD1M) | (l2_fsm2 == `L2_FSM_LD1H)) &
(sctag0_addr_c2[39:8] == l2_fsm2_addr1))
begin
if(l2_fsm2 == `L2_FSM_LD1M) l2_fsm2 <= `L2_FSM_LD2M;
else l2_fsm2 <= `L2_FSM_LD2H;
end
else if(load1 & ~sctag1_tagctl_hit_c2 &
((l2_fsm2 == `L2_FSM_LD1M) | (l2_fsm2 == `L2_FSM_LD1H)) &
(sctag1_addr_c2[39:8] == l2_fsm2_addr1))
begin
if(l2_fsm2 == `L2_FSM_LD1M) l2_fsm2 <= `L2_FSM_LD2M;
else l2_fsm2 <= `L2_FSM_LD2H;
end
else if(load2 & ~sctag2_tagctl_hit_c2 &
((l2_fsm2 == `L2_FSM_LD1M) | (l2_fsm2 == `L2_FSM_LD1H)) &
(sctag2_addr_c2[39:8] == l2_fsm2_addr1))
begin
if(l2_fsm2 == `L2_FSM_LD1M) l2_fsm2 <= `L2_FSM_LD2M;
else l2_fsm2 <= `L2_FSM_LD2H;
end
else if(load3 & ~sctag3_tagctl_hit_c2 &
((l2_fsm2 == `L2_FSM_LD1M) | (l2_fsm2 == `L2_FSM_LD1H)) &
(sctag3_addr_c2[39:8] == l2_fsm2_addr1))
begin
if(l2_fsm2 == `L2_FSM_LD1M) l2_fsm2 <= `L2_FSM_LD2M;
else l2_fsm2 <= `L2_FSM_LD2H;
end
//-------------------------------------------
// returning the FSM to idle stuff
// when the original store does the last pass.
//-------------------------------------------
else if(store0 & (sctag0_addr_c2[39:8] == l2_fsm2_addr1[39:8]) &
(sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm2_id1) &
~sctag0_inst_c2[`L2_EVICT] & sctag0_inst_c2[`L2_MBF])
l2_fsm2 <= `L2_FSM_IDLE;
else if(store1 & (sctag1_addr_c2[39:8] == l2_fsm2_addr1[39:8]) &
(sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm2_id1) &
~sctag1_inst_c2[`L2_EVICT] & sctag1_inst_c2[`L2_MBF])
l2_fsm2 <= `L2_FSM_IDLE;
else if(store2 & (sctag2_addr_c2[39:8] == l2_fsm2_addr1[39:8]) &
(sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm2_id1) &
~sctag2_inst_c2[`L2_EVICT] & sctag2_inst_c2[`L2_MBF])
l2_fsm2 <= `L2_FSM_IDLE;
else if(store3 & (sctag3_addr_c2[39:8] == l2_fsm2_addr1[39:8]) &
(sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm2_id1) &
~sctag3_inst_c2[`L2_EVICT] & sctag3_inst_c2[`L2_MBF])
l2_fsm2 <= `L2_FSM_IDLE;
else if(l2_fsm2_counter > 1000)
l2_fsm2 <= `L2_FSM_IDLE;
end
//==========================================================================================
reg [3:0] l2_fsm3;
integer l2_fsm3_counter;
reg [39:8] l2_fsm3_addr1, l2_fsm3_addr2;
reg [4:0] l2_fsm3_id1, l2_fsm3_id2;
always @(posedge clk)
begin
if(~rst_l)
l2_fsm3_counter <= 0;
else if(l2_fsm3 == `L2_FSM_IDLE)
l2_fsm3_counter <= 0;
else
l2_fsm3_counter <= l2_fsm3_counter + 1;
if(~rst_l)
begin
l2_fsm3 <= `L2_FSM_IDLE;
end
// A first store or wris8 not issued from miss buffer.
//-------------------------------------------------------------------------------
else if(wris80 & ~sctag0_inst_c2[`L2_MBF] & ~sctag0_tagctl_hit_c2 & (l2_fsm3 == `L2_FSM_IDLE))
begin
l2_fsm3_addr1 <= sctag0_addr_c2[39:8];
l2_fsm3_id1 <= sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm3 <= `L2_FSM_ST1;
end
else if(wris81 & ~sctag1_inst_c2[`L2_MBF] & ~sctag1_tagctl_hit_c2 & (l2_fsm3 == `L2_FSM_IDLE))
begin
l2_fsm3_addr1 <= sctag1_addr_c2[39:8];
l2_fsm3_id1 <= sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm3 <= `L2_FSM_ST1;
end
else if(wris82 & ~sctag2_inst_c2[`L2_MBF] & ~sctag2_tagctl_hit_c2 & (l2_fsm3 == `L2_FSM_IDLE))
begin
l2_fsm3_addr1 <= sctag2_addr_c2[39:8];
l2_fsm3_id1 <= sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm3 <= `L2_FSM_ST1;
end
else if(wris83 & ~sctag3_inst_c2[`L2_MBF] & ~sctag3_tagctl_hit_c2 & (l2_fsm3 == `L2_FSM_IDLE))
begin
l2_fsm3_addr1 <= sctag3_addr_c2[39:8];
l2_fsm3_id1 <= sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm3 <= `L2_FSM_ST1;
end
// The second store - may be a miss or a hit
//-------------------------------------------------------------------------------
else if(wris80 & ~sctag0_inst_c2[`L2_MBF] & (l2_fsm3 == `L2_FSM_ST1))
begin
l2_fsm3_addr2 <= sctag0_addr_c2[39:8];
l2_fsm3_id2 <= sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm3 <= sctag0_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(wris81 & ~sctag1_inst_c2[`L2_MBF] & (l2_fsm3 == `L2_FSM_ST1))
begin
l2_fsm3_addr2 <= sctag1_addr_c2[39:8];
l2_fsm3_id2 <= sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm3 <= sctag1_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(wris82 & ~sctag2_inst_c2[`L2_MBF] & (l2_fsm3 == `L2_FSM_ST1))
begin
l2_fsm3_addr2 <= sctag2_addr_c2[39:8];
l2_fsm3_id2 <= sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm3 <= sctag2_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(wris83 & ~sctag3_inst_c2[`L2_MBF] & (l2_fsm3 == `L2_FSM_ST1))
begin
l2_fsm3_addr2 <= sctag3_addr_c2[39:8];
l2_fsm3_id2 <= sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm3 <= sctag3_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
// A load to address2 is a hit or returned already
// the load is eaither not starting from the L2 MB and is a hit
// or is starting from the L2MB.
//-------------------------------------------------------------------------------
else if(load0 & (~sctag0_inst_c2[`L2_MBF] & sctag0_tagctl_hit_c2 |
~sctag0_inst_c2[`L2_EVICT] & sctag0_inst_c2[`L2_MBF]) &
((l2_fsm3 == `L2_FSM_ST2M) | (l2_fsm3 == `L2_FSM_ST2H)) &
(sctag0_addr_c2[39:8] == l2_fsm3_addr2[39:8]))
begin
if(l2_fsm3 == `L2_FSM_ST2M) l2_fsm3 <= `L2_FSM_LD1M;
else l2_fsm3 <= `L2_FSM_LD1H;
end
else if(load1 & (~sctag1_inst_c2[`L2_MBF] & sctag1_tagctl_hit_c2 |
~sctag1_inst_c2[`L2_EVICT] & sctag1_inst_c2[`L2_MBF]) &
((l2_fsm3 == `L2_FSM_ST2M) | (l2_fsm3 == `L2_FSM_ST2H)) &
(sctag1_addr_c2[39:8] == l2_fsm3_addr2[39:8]))
begin
if(l2_fsm3 == `L2_FSM_ST2M) l2_fsm3 <= `L2_FSM_LD1M;
else l2_fsm3 <= `L2_FSM_LD1H;
end
else if(load2 & (~sctag2_inst_c2[`L2_MBF] & sctag2_tagctl_hit_c2 |
~sctag2_inst_c2[`L2_EVICT] & sctag2_inst_c2[`L2_MBF]) &
((l2_fsm3 == `L2_FSM_ST2M) | (l2_fsm3 == `L2_FSM_ST2H)) &
(sctag2_addr_c2[39:8] == l2_fsm3_addr2[39:8]))
begin
if(l2_fsm3 == `L2_FSM_ST2M) l2_fsm3 <= `L2_FSM_LD1M;
else l2_fsm3 <= `L2_FSM_LD1H;
end
else if(load3 & (~sctag3_inst_c2[`L2_MBF] & sctag3_tagctl_hit_c2 |
~sctag3_inst_c2[`L2_EVICT] & sctag3_inst_c2[`L2_MBF]) &
((l2_fsm3 == `L2_FSM_ST2M) | (l2_fsm3 == `L2_FSM_ST2H)) &
(sctag3_addr_c2[39:8] == l2_fsm3_addr2[39:8]))
begin
if(l2_fsm3 == `L2_FSM_ST2M) l2_fsm3 <= `L2_FSM_LD1M;
else l2_fsm3 <= `L2_FSM_LD1H;
end
// A load to address1 is a miss.
//-------------------------------------------------------------------------------
else if(load0 & ~sctag0_tagctl_hit_c2 &
((l2_fsm3 == `L2_FSM_LD1M) | (l2_fsm3 == `L2_FSM_LD1H)) &
(sctag0_addr_c2[39:8] == l2_fsm3_addr1))
begin
if(l2_fsm3 == `L2_FSM_LD1M) l2_fsm3 <= `L2_FSM_LD2M;
else l2_fsm3 <= `L2_FSM_LD2H;
end
else if(load1 & ~sctag1_tagctl_hit_c2 &
((l2_fsm3 == `L2_FSM_LD1M) | (l2_fsm3 == `L2_FSM_LD1H)) &
(sctag1_addr_c2[39:8] == l2_fsm3_addr1))
begin
if(l2_fsm3 == `L2_FSM_LD1M) l2_fsm3 <= `L2_FSM_LD2M;
else l2_fsm3 <= `L2_FSM_LD2H;
end
else if(load2 & ~sctag2_tagctl_hit_c2 &
((l2_fsm3 == `L2_FSM_LD1M) | (l2_fsm3 == `L2_FSM_LD1H)) &
(sctag2_addr_c2[39:8] == l2_fsm3_addr1))
begin
if(l2_fsm3 == `L2_FSM_LD1M) l2_fsm3 <= `L2_FSM_LD2M;
else l2_fsm3 <= `L2_FSM_LD2H;
end
else if(load3 & ~sctag3_tagctl_hit_c2 &
((l2_fsm3 == `L2_FSM_LD1M) | (l2_fsm3 == `L2_FSM_LD1H)) &
(sctag3_addr_c2[39:8] == l2_fsm3_addr1))
begin
if(l2_fsm3 == `L2_FSM_LD1M) l2_fsm3 <= `L2_FSM_LD2M;
else l2_fsm3 <= `L2_FSM_LD2H;
end
//-------------------------------------------
// returning the FSM to idle stuff
// Note - NOT when the original store does the last pass
// but when a new store comes
// when the original store does the last pass.
//-------------------------------------------
else if(wris80 & (sctag0_addr_c2[39:8] == l2_fsm3_addr1[39:8]) &
~sctag0_inst_c2[`L2_EVICT] & ~sctag0_inst_c2[`L2_MBF])
l2_fsm3 <= `L2_FSM_IDLE;
else if(wris81 & (sctag1_addr_c2[39:8] == l2_fsm3_addr1[39:8]) &
~sctag1_inst_c2[`L2_EVICT] & ~sctag1_inst_c2[`L2_MBF])
l2_fsm3 <= `L2_FSM_IDLE;
else if(wris82 & (sctag2_addr_c2[39:8] == l2_fsm3_addr1[39:8]) &
~sctag2_inst_c2[`L2_EVICT] & ~sctag2_inst_c2[`L2_MBF])
l2_fsm3 <= `L2_FSM_IDLE;
else if(wris83 & (sctag3_addr_c2[39:8] == l2_fsm3_addr1[39:8]) &
~sctag3_inst_c2[`L2_EVICT] & ~sctag3_inst_c2[`L2_MBF])
l2_fsm3 <= `L2_FSM_IDLE;
else if(l2_fsm3_counter > 1000)
l2_fsm3 <= `L2_FSM_IDLE;
end
//==========================================================================================
reg [3:0] l2_fsm4;
integer l2_fsm4_counter;
reg [39:8] l2_fsm4_addr1, l2_fsm4_addr2;
reg [4:0] l2_fsm4_id1, l2_fsm4_id2;
always @(posedge clk)
begin
if(~rst_l)
l2_fsm4_counter <= 0;
else if(l2_fsm4 == `L2_FSM_IDLE)
l2_fsm4_counter <= 0;
else
l2_fsm4_counter <= l2_fsm4_counter + 1;
if(~rst_l)
begin
l2_fsm4 <= `L2_FSM_IDLE;
end
// A first store not issued from miss buffer.
//-------------------------------------------------------------------------------
else if(store0 & ~sctag0_inst_c2[`L2_MBF] & ~sctag0_tagctl_hit_c2 & (l2_fsm4 == `L2_FSM_IDLE))
begin
l2_fsm4_addr1 <= sctag0_addr_c2[39:8];
l2_fsm4_id1 <= sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm4 <= `L2_FSM_ST1;
end
else if(store1 & ~sctag1_inst_c2[`L2_MBF] & ~sctag1_tagctl_hit_c2 & (l2_fsm4 == `L2_FSM_IDLE))
begin
l2_fsm4_addr1 <= sctag1_addr_c2[39:8];
l2_fsm4_id1 <= sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm4 <= `L2_FSM_ST1;
end
else if(store2 & ~sctag2_inst_c2[`L2_MBF] & ~sctag2_tagctl_hit_c2 & (l2_fsm4 == `L2_FSM_IDLE))
begin
l2_fsm4_addr1 <= sctag2_addr_c2[39:8];
l2_fsm4_id1 <= sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm4 <= `L2_FSM_ST1;
end
else if(store3 & ~sctag3_inst_c2[`L2_MBF] & ~sctag3_tagctl_hit_c2 & (l2_fsm4 == `L2_FSM_IDLE))
begin
l2_fsm4_addr1 <= sctag3_addr_c2[39:8];
l2_fsm4_id1 <= sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm4 <= `L2_FSM_ST1;
end
// The second store - may be a miss or a hit
//-------------------------------------------------------------------------------
else if(store0 & ~sctag0_inst_c2[`L2_MBF] & (l2_fsm4 == `L2_FSM_ST1))
begin
l2_fsm4_addr2 <= sctag0_addr_c2[39:8];
l2_fsm4_id2 <= sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm4 <= sctag0_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(store1 & ~sctag1_inst_c2[`L2_MBF] & (l2_fsm4 == `L2_FSM_ST1))
begin
l2_fsm4_addr2 <= sctag1_addr_c2[39:8];
l2_fsm4_id2 <= sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm4 <= sctag1_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(store2 & ~sctag2_inst_c2[`L2_MBF] & (l2_fsm4 == `L2_FSM_ST1))
begin
l2_fsm4_addr2 <= sctag2_addr_c2[39:8];
l2_fsm4_id2 <= sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm4 <= sctag2_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(store3 & ~sctag3_inst_c2[`L2_MBF] & (l2_fsm4 == `L2_FSM_ST1))
begin
l2_fsm4_addr2 <= sctag3_addr_c2[39:8];
l2_fsm4_id2 <= sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm4 <= sctag3_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
// A load to address2 is a hit or returned already
// the load is eaither not starting from the L2 MB and is a hit
// or is starting from the L2MB.
//-------------------------------------------------------------------------------
else if(ldd0 & (~sctag0_inst_c2[`L2_MBF] & sctag0_tagctl_hit_c2 |
~sctag0_inst_c2[`L2_EVICT] & sctag0_inst_c2[`L2_MBF]) &
((l2_fsm4 == `L2_FSM_ST2M) | (l2_fsm4 == `L2_FSM_ST2H)) &
(sctag0_addr_c2[39:8] == l2_fsm4_addr2[39:8]))
begin
if(l2_fsm4 == `L2_FSM_ST2M) l2_fsm4 <= `L2_FSM_LD1M;
else l2_fsm4 <= `L2_FSM_LD1H;
end
else if(ldd1 & (~sctag1_inst_c2[`L2_MBF] & sctag1_tagctl_hit_c2 |
~sctag1_inst_c2[`L2_EVICT] & sctag1_inst_c2[`L2_MBF]) &
((l2_fsm4 == `L2_FSM_ST2M) | (l2_fsm4 == `L2_FSM_ST2H)) &
(sctag1_addr_c2[39:8] == l2_fsm4_addr2[39:8]))
begin
if(l2_fsm4 == `L2_FSM_ST2M) l2_fsm4 <= `L2_FSM_LD1M;
else l2_fsm4 <= `L2_FSM_LD1H;
end
else if(ldd2 & (~sctag2_inst_c2[`L2_MBF] & sctag2_tagctl_hit_c2 |
~sctag2_inst_c2[`L2_EVICT] & sctag2_inst_c2[`L2_MBF]) &
((l2_fsm4 == `L2_FSM_ST2M) | (l2_fsm4 == `L2_FSM_ST2H)) &
(sctag2_addr_c2[39:8] == l2_fsm4_addr2[39:8]))
begin
if(l2_fsm4 == `L2_FSM_ST2M) l2_fsm4 <= `L2_FSM_LD1M;
else l2_fsm4 <= `L2_FSM_LD1H;
end
else if(ldd3 & (~sctag3_inst_c2[`L2_MBF] & sctag3_tagctl_hit_c2 |
~sctag3_inst_c2[`L2_EVICT] & sctag3_inst_c2[`L2_MBF]) &
((l2_fsm4 == `L2_FSM_ST2M) | (l2_fsm4 == `L2_FSM_ST2H)) &
(sctag3_addr_c2[39:8] == l2_fsm4_addr2[39:8]))
begin
if(l2_fsm4 == `L2_FSM_ST2M) l2_fsm4 <= `L2_FSM_LD1M;
else l2_fsm4 <= `L2_FSM_LD1H;
end
// A load to address1 is a miss.
//-------------------------------------------------------------------------------
else if(load0 & ~sctag0_tagctl_hit_c2 &
((l2_fsm4 == `L2_FSM_LD1M) | (l2_fsm4 == `L2_FSM_LD1H)) &
(sctag0_addr_c2[39:8] == l2_fsm4_addr1))
begin
if(l2_fsm4 == `L2_FSM_LD1M) l2_fsm4 <= `L2_FSM_LD2M;
else l2_fsm4 <= `L2_FSM_LD2H;
end
else if(load1 & ~sctag1_tagctl_hit_c2 &
((l2_fsm4 == `L2_FSM_LD1M) | (l2_fsm4 == `L2_FSM_LD1H)) &
(sctag1_addr_c2[39:8] == l2_fsm4_addr1))
begin
if(l2_fsm4 == `L2_FSM_LD1M) l2_fsm4 <= `L2_FSM_LD2M;
else l2_fsm4 <= `L2_FSM_LD2H;
end
else if(load2 & ~sctag2_tagctl_hit_c2 &
((l2_fsm4 == `L2_FSM_LD1M) | (l2_fsm4 == `L2_FSM_LD1H)) &
(sctag2_addr_c2[39:8] == l2_fsm4_addr1))
begin
if(l2_fsm4 == `L2_FSM_LD1M) l2_fsm4 <= `L2_FSM_LD2M;
else l2_fsm4 <= `L2_FSM_LD2H;
end
else if(load3 & ~sctag3_tagctl_hit_c2 &
((l2_fsm4 == `L2_FSM_LD1M) | (l2_fsm4 == `L2_FSM_LD1H)) &
(sctag3_addr_c2[39:8] == l2_fsm4_addr1))
begin
if(l2_fsm4 == `L2_FSM_LD1M) l2_fsm4 <= `L2_FSM_LD2M;
else l2_fsm4 <= `L2_FSM_LD2H;
end
//-------------------------------------------
// returning the FSM to idle stuff
// when the original store does the last pass.
//-------------------------------------------
else if(store0 & (sctag0_addr_c2[39:8] == l2_fsm4_addr1[39:8]) &
(sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm4_id1) &
~sctag0_inst_c2[`L2_EVICT] & sctag0_inst_c2[`L2_MBF])
l2_fsm4 <= `L2_FSM_IDLE;
else if(store1 & (sctag1_addr_c2[39:8] == l2_fsm4_addr1[39:8]) &
(sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm4_id1) &
~sctag1_inst_c2[`L2_EVICT] & sctag1_inst_c2[`L2_MBF])
l2_fsm4 <= `L2_FSM_IDLE;
else if(store2 & (sctag2_addr_c2[39:8] == l2_fsm4_addr1[39:8]) &
(sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm4_id1) &
~sctag2_inst_c2[`L2_EVICT] & sctag2_inst_c2[`L2_MBF])
l2_fsm4 <= `L2_FSM_IDLE;
else if(store3 & (sctag3_addr_c2[39:8] == l2_fsm4_addr1[39:8]) &
(sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm4_id1) &
~sctag3_inst_c2[`L2_EVICT] & sctag3_inst_c2[`L2_MBF])
l2_fsm4 <= `L2_FSM_IDLE;
else if(l2_fsm4_counter > 1000)
l2_fsm4 <= `L2_FSM_IDLE;
end
//-------------------------------------------------------------------
// L2MB related stuff again - the states of each individual L2MB
//-------------------------------------------------------------------
`define L2MB_IDLE 4'b0000
`define L2MB_EVICT 4'b0001
`define L2MB_EVICT_FILL 4'b0010
`define L2MB_EVICT_BYPASS 4'b0011
reg [39:8] sctag0_l2mb_addr [0:15];
reg [3:0] sctag0_l2mb_state[0:15];
wire [3:0] sctag0_l2mb_state0 = sctag0_l2mb_state[0];
wire [3:0] sctag0_l2mb_state1 = sctag0_l2mb_state[1];
wire [3:0] sctag0_l2mb_state2 = sctag0_l2mb_state[2];
wire [3:0] sctag0_l2mb_state3 = sctag0_l2mb_state[3];
wire [3:0] sctag0_l2mb_state4 = sctag0_l2mb_state[4];
wire [3:0] sctag0_l2mb_state5 = sctag0_l2mb_state[5];
wire [3:0] sctag0_l2mb_state6 = sctag0_l2mb_state[6];
wire [3:0] sctag0_l2mb_state7 = sctag0_l2mb_state[7];
wire [3:0] sctag0_l2mb_state8 = sctag0_l2mb_state[8];
wire [3:0] sctag0_l2mb_state9 = sctag0_l2mb_state[9];
wire [3:0] sctag0_l2mb_state10 = sctag0_l2mb_state[10];
wire [3:0] sctag0_l2mb_state11 = sctag0_l2mb_state[11];
wire [3:0] sctag0_l2mb_state12 = sctag0_l2mb_state[12];
wire [3:0] sctag0_l2mb_state13 = sctag0_l2mb_state[13];
wire [3:0] sctag0_l2mb_state14 = sctag0_l2mb_state[14];
wire [3:0] sctag0_l2mb_state15 = sctag0_l2mb_state[15];
reg sctag0_l2mb_pointer;
integer sctag0_iii;
reg [39:8] sctag1_l2mb_addr [0:15];
reg [3:0] sctag1_l2mb_state[0:15];
wire [3:0] sctag1_l2mb_state0 = sctag1_l2mb_state[0];
wire [3:0] sctag1_l2mb_state1 = sctag1_l2mb_state[1];
wire [3:0] sctag1_l2mb_state2 = sctag1_l2mb_state[2];
wire [3:0] sctag1_l2mb_state3 = sctag1_l2mb_state[3];
wire [3:0] sctag1_l2mb_state4 = sctag1_l2mb_state[4];
wire [3:0] sctag1_l2mb_state5 = sctag1_l2mb_state[5];
wire [3:0] sctag1_l2mb_state6 = sctag1_l2mb_state[6];
wire [3:0] sctag1_l2mb_state7 = sctag1_l2mb_state[7];
wire [3:0] sctag1_l2mb_state8 = sctag1_l2mb_state[8];
wire [3:0] sctag1_l2mb_state9 = sctag1_l2mb_state[9];
wire [3:0] sctag1_l2mb_state10 = sctag1_l2mb_state[10];
wire [3:0] sctag1_l2mb_state11 = sctag1_l2mb_state[11];
wire [3:0] sctag1_l2mb_state12 = sctag1_l2mb_state[12];
wire [3:0] sctag1_l2mb_state13 = sctag1_l2mb_state[13];
wire [3:0] sctag1_l2mb_state14 = sctag1_l2mb_state[14];
wire [3:0] sctag1_l2mb_state15 = sctag1_l2mb_state[15];
reg sctag1_l2mb_pointer;
integer sctag1_iii;
reg [39:8] sctag2_l2mb_addr [0:15];
reg [3:0] sctag2_l2mb_state[0:15];
wire [3:0] sctag2_l2mb_state0 = sctag2_l2mb_state[0];
wire [3:0] sctag2_l2mb_state1 = sctag2_l2mb_state[1];
wire [3:0] sctag2_l2mb_state2 = sctag2_l2mb_state[2];
wire [3:0] sctag2_l2mb_state3 = sctag2_l2mb_state[3];
wire [3:0] sctag2_l2mb_state4 = sctag2_l2mb_state[4];
wire [3:0] sctag2_l2mb_state5 = sctag2_l2mb_state[5];
wire [3:0] sctag2_l2mb_state6 = sctag2_l2mb_state[6];
wire [3:0] sctag2_l2mb_state7 = sctag2_l2mb_state[7];
wire [3:0] sctag2_l2mb_state8 = sctag2_l2mb_state[8];
wire [3:0] sctag2_l2mb_state9 = sctag2_l2mb_state[9];
wire [3:0] sctag2_l2mb_state10 = sctag2_l2mb_state[10];
wire [3:0] sctag2_l2mb_state11 = sctag2_l2mb_state[11];
wire [3:0] sctag2_l2mb_state12 = sctag2_l2mb_state[12];
wire [3:0] sctag2_l2mb_state13 = sctag2_l2mb_state[13];
wire [3:0] sctag2_l2mb_state14 = sctag2_l2mb_state[14];
wire [3:0] sctag2_l2mb_state15 = sctag2_l2mb_state[15];
reg sctag2_l2mb_pointer;
integer sctag2_iii;
reg [39:8] sctag3_l2mb_addr [0:15];
reg [3:0] sctag3_l2mb_state[0:15];
wire [3:0] sctag3_l2mb_state0 = sctag3_l2mb_state[0];
wire [3:0] sctag3_l2mb_state1 = sctag3_l2mb_state[1];
wire [3:0] sctag3_l2mb_state2 = sctag3_l2mb_state[2];
wire [3:0] sctag3_l2mb_state3 = sctag3_l2mb_state[3];
wire [3:0] sctag3_l2mb_state4 = sctag3_l2mb_state[4];
wire [3:0] sctag3_l2mb_state5 = sctag3_l2mb_state[5];
wire [3:0] sctag3_l2mb_state6 = sctag3_l2mb_state[6];
wire [3:0] sctag3_l2mb_state7 = sctag3_l2mb_state[7];
wire [3:0] sctag3_l2mb_state8 = sctag3_l2mb_state[8];
wire [3:0] sctag3_l2mb_state9 = sctag3_l2mb_state[9];
wire [3:0] sctag3_l2mb_state10 = sctag3_l2mb_state[10];
wire [3:0] sctag3_l2mb_state11 = sctag3_l2mb_state[11];
wire [3:0] sctag3_l2mb_state12 = sctag3_l2mb_state[12];
wire [3:0] sctag3_l2mb_state13 = sctag3_l2mb_state[13];
wire [3:0] sctag3_l2mb_state14 = sctag3_l2mb_state[14];
wire [3:0] sctag3_l2mb_state15 = sctag3_l2mb_state[15];
reg sctag3_l2mb_pointer;
integer sctag3_iii;
always @(posedge clk)
begin
if(~rst_l)
begin
for(sctag0_iii=0; sctag0_iii<16; sctag0_iii = sctag0_iii+1)
sctag0_l2mb_state[sctag0_iii] = `L2MB_IDLE;
end
else if(sctag0_inst_vld_c2 & sctag0_inst_c2[`L2_MBF] & sctag0_inst_c2[`L2_EVICT])
begin
sctag0_l2mb_pointer = sctag_find_next_available(2'h0);
sctag0_l2mb_addr [sctag0_l2mb_pointer] <= sctag0_addr_c2[39:8];
sctag0_l2mb_state[sctag0_l2mb_pointer] <= `L2MB_EVICT;
end
else if(sctag0_inst_vld_c2 & sctag0_inst_c2[`L2_FBF])
begin
sctag0_l2mb_pointer = sctag_l2mb_cam(2'h0);
sctag0_l2mb_state[sctag0_l2mb_pointer] <= (sctag0_l2mb_state[sctag0_l2mb_pointer] == `L2MB_EVICT) ?
`L2MB_EVICT_FILL: `L2MB_IDLE;
end
else if(sctag0_inst_vld_c2 & sctag0_inst_c2[`L2_MBF] & ~sctag0_inst_c2[`L2_EVICT])
begin
sctag0_l2mb_pointer = sctag_l2mb_cam(2'h0);
sctag0_l2mb_state[sctag0_l2mb_pointer] <= (sctag0_l2mb_state[sctag0_l2mb_pointer] == `L2MB_EVICT) ?
`L2MB_EVICT_BYPASS: `L2MB_IDLE;
end
end
always @(posedge clk)
begin
if(~rst_l)
begin
for(sctag1_iii=0; sctag1_iii<16; sctag1_iii = sctag1_iii+1)
sctag1_l2mb_state[sctag1_iii] = `L2MB_IDLE;
end
else if(sctag1_inst_vld_c2 & sctag1_inst_c2[`L2_MBF] & sctag1_inst_c2[`L2_EVICT])
begin
sctag1_l2mb_pointer = sctag_find_next_available(2'h1);
sctag1_l2mb_addr [sctag1_l2mb_pointer] <= sctag1_addr_c2[39:8];
sctag1_l2mb_state[sctag1_l2mb_pointer] <= `L2MB_EVICT;
end
else if(sctag1_inst_vld_c2 & sctag1_inst_c2[`L2_FBF])
begin
sctag1_l2mb_pointer = sctag_l2mb_cam(2'h1);
sctag1_l2mb_state[sctag1_l2mb_pointer] <= (sctag1_l2mb_state[sctag1_l2mb_pointer] == `L2MB_EVICT) ?
`L2MB_EVICT_FILL: `L2MB_IDLE;
end
else if(sctag1_inst_vld_c2 & sctag1_inst_c2[`L2_MBF] & ~sctag1_inst_c2[`L2_EVICT])
begin
sctag1_l2mb_pointer = sctag_l2mb_cam(2'h1);
sctag1_l2mb_state[sctag0_l2mb_pointer] <= (sctag1_l2mb_state[sctag1_l2mb_pointer] == `L2MB_EVICT) ?
`L2MB_EVICT_BYPASS: `L2MB_IDLE;
end
end
always @(posedge clk)
begin
if(~rst_l)
begin
for(sctag2_iii=0; sctag2_iii<16; sctag2_iii = sctag2_iii+1)
sctag2_l2mb_state[sctag2_iii] = `L2MB_IDLE;
end
else if(sctag2_inst_vld_c2 & sctag2_inst_c2[`L2_MBF] & sctag2_inst_c2[`L2_EVICT])
begin
sctag2_l2mb_pointer = sctag_find_next_available(2'h2);
sctag2_l2mb_addr [sctag2_l2mb_pointer] <= sctag2_addr_c2[39:8];
sctag2_l2mb_state[sctag2_l2mb_pointer] <= `L2MB_EVICT;
end
else if(sctag2_inst_vld_c2 & sctag2_inst_c2[`L2_FBF])
begin
sctag2_l2mb_pointer = sctag_l2mb_cam(2'h2);
sctag2_l2mb_state[sctag2_l2mb_pointer] <= (sctag2_l2mb_state[sctag2_l2mb_pointer] == `L2MB_EVICT) ?
`L2MB_EVICT_FILL: `L2MB_IDLE;
end
else if(sctag2_inst_vld_c2 & sctag2_inst_c2[`L2_MBF] & ~sctag2_inst_c2[`L2_EVICT])
begin
sctag2_l2mb_pointer = sctag_l2mb_cam(2'h2);
sctag2_l2mb_state[sctag0_l2mb_pointer] <= (sctag2_l2mb_state[sctag2_l2mb_pointer] == `L2MB_EVICT) ?
`L2MB_EVICT_BYPASS: `L2MB_IDLE;
end
end
always @(posedge clk)
begin
if(~rst_l)
begin
for(sctag3_iii=0; sctag3_iii<16; sctag3_iii = sctag3_iii+1)
sctag3_l2mb_state[sctag3_iii] = `L2MB_IDLE;
end
else if(sctag3_inst_vld_c2 & sctag3_inst_c2[`L2_MBF] & sctag3_inst_c2[`L2_EVICT])
begin
sctag3_l2mb_pointer = sctag_find_next_available(2'h3);
sctag3_l2mb_addr [sctag3_l2mb_pointer] <= sctag3_addr_c2[39:8];
sctag3_l2mb_state[sctag3_l2mb_pointer] <= `L2MB_EVICT;
end
else if(sctag3_inst_vld_c2 & sctag3_inst_c2[`L2_FBF])
begin
sctag3_l2mb_pointer = sctag_l2mb_cam(2'h3);
sctag3_l2mb_state[sctag3_l2mb_pointer] <= (sctag3_l2mb_state[sctag3_l2mb_pointer] == `L2MB_EVICT) ?
`L2MB_EVICT_FILL: `L2MB_IDLE;
end
else if(sctag3_inst_vld_c2 & sctag3_inst_c2[`L2_MBF] & ~sctag3_inst_c2[`L2_EVICT])
begin
sctag3_l2mb_pointer = sctag_l2mb_cam(2'h3);
sctag3_l2mb_state[sctag0_l2mb_pointer] <= (sctag3_l2mb_state[sctag3_l2mb_pointer] == `L2MB_EVICT) ?
`L2MB_EVICT_BYPASS: `L2MB_IDLE;
end
end
//============================================================================================
// LSU stuff
//============================================================================================
//============================================================================================
// Back to back invalidates and loads ...cores...
//============================================================================================
`ifdef RTL_SPARC0
wire C0T0_stb_ne = |`TOP_DESIGN.sparc0.lsu.stb_ctl0.stb_state_vld[7:0];
wire C0T1_stb_ne = |`TOP_DESIGN.sparc0.lsu.stb_ctl1.stb_state_vld[7:0];
wire C0T2_stb_ne = |`TOP_DESIGN.sparc0.lsu.stb_ctl2.stb_state_vld[7:0];
wire C0T3_stb_ne = |`TOP_DESIGN.sparc0.lsu.stb_ctl3.stb_state_vld[7:0];
wire C0T0_stb_nced = |( `TOP_DESIGN.sparc0.lsu.stb_ctl0.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc0.lsu.stb_ctl0.stb_state_ced[7:0]);
wire C0T1_stb_nced = |( `TOP_DESIGN.sparc0.lsu.stb_ctl1.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc0.lsu.stb_ctl1.stb_state_ced[7:0]);
wire C0T2_stb_nced = |( `TOP_DESIGN.sparc0.lsu.stb_ctl2.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc0.lsu.stb_ctl2.stb_state_ced[7:0]);
wire C0T3_stb_nced = |( `TOP_DESIGN.sparc0.lsu.stb_ctl3.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc0.lsu.stb_ctl3.stb_state_ced[7:0]);
`else
wire C0T0_stb_ne = 1'b0;
wire C0T1_stb_ne = 1'b0;
wire C0T2_stb_ne = 1'b0;
wire C0T3_stb_ne = 1'b0;
wire C0T0_stb_nced = 1'b0;
wire C0T1_stb_nced = 1'b0;
wire C0T2_stb_nced = 1'b0;
wire C0T3_stb_nced = 1'b0;
`endif // ifdef RTL_SPARC0
`ifdef RTL_SPARC0
wire spc0_lsu_ifill_pkt_vld = `TOP_DESIGN.sparc0.lsu.qctl2.lsu_ifill_pkt_vld;
wire spc0_dfq_rd_advance = `TOP_DESIGN.sparc0.lsu.qctl2.dfq_rd_advance;
wire spc0_dfq_int_type = `TOP_DESIGN.sparc0.lsu.qctl2.dfq_int_type;
wire spc0_ifu_lsu_inv_clear = `TOP_DESIGN.sparc0.lsu.qctl2.ifu_lsu_inv_clear;
wire spc0_dva_svld_e = `TOP_DESIGN.sparc0.lsu.qctl2.dva_svld_e;
wire spc0_dva_rvld_e = `TOP_DESIGN.sparc0.lsu.dva.rd_en;
wire [10:4] spc0_dva_rd_addr_e = `TOP_DESIGN.sparc0.lsu.dva.rd_adr1[6:0];
wire [4:0] spc0_dva_snp_addr_e = `TOP_DESIGN.sparc0.lsu.qctl2.dva_snp_addr_e[4:0];
wire [4:0] spc0_stb_data_rd_ptr = `TOP_DESIGN.sparc0.lsu.stb_data_rd_ptr[4:0];
wire [4:0] spc0_stb_data_wr_ptr = `TOP_DESIGN.sparc0.lsu.stb_data_wr_ptr[4:0];
wire spc0_stb_data_wptr_vld = `TOP_DESIGN.sparc0.lsu.stb_data_wptr_vld;
wire spc0_stb_data_rptr_vld = `TOP_DESIGN.sparc0.lsu.stb_data_rptr_vld;
wire spc0_stbrwctl_flush_pipe_w = `TOP_DESIGN.sparc0.lsu.stb_rwctl.lsu_stbrwctl_flush_pipe_w;
wire spc0_lsu_st_pcx_rq_pick = |`TOP_DESIGN.sparc0.lsu.stb_rwctl.lsu_st_pcx_rq_pick[3:0];
wire [3:0] spc0_lsu_rd_dtag_parity_g = `TOP_DESIGN.sparc0.lsu.dctl.lsu_rd_dtag_parity_g[3:0];
wire [3:0] spc0_dva_vld_g = `TOP_DESIGN.sparc0.lsu.dctl.dva_vld_g[3:0];
wire [3:0] spc0_lsu_dc_tag_pe_g_unmasked = spc0_lsu_rd_dtag_parity_g[3:0] & spc0_dva_vld_g[3:0];
wire spc0_lsu_dc_tag_pe_g_unmasked_or = |spc0_lsu_dc_tag_pe_g_unmasked[3:0];
wire C0T0_stb_full = &`TOP_DESIGN.sparc0.lsu.stb_ctl0.stb_state_vld[7:0];
wire C0T1_stb_full = &`TOP_DESIGN.sparc0.lsu.stb_ctl1.stb_state_vld[7:0];
wire C0T2_stb_full = &`TOP_DESIGN.sparc0.lsu.stb_ctl2.stb_state_vld[7:0];
wire C0T3_stb_full = &`TOP_DESIGN.sparc0.lsu.stb_ctl3.stb_state_vld[7:0];
wire [7:0] C0T0_stb_vld = `TOP_DESIGN.sparc0.lsu.stb_ctl0.stb_state_vld[7:0];
wire [7:0] C0T1_stb_vld = `TOP_DESIGN.sparc0.lsu.stb_ctl1.stb_state_vld[7:0];
wire [7:0] C0T2_stb_vld = `TOP_DESIGN.sparc0.lsu.stb_ctl2.stb_state_vld[7:0];
wire [7:0] C0T3_stb_vld = `TOP_DESIGN.sparc0.lsu.stb_ctl3.stb_state_vld[7:0];
wire [4:0] C0T0_stb_vld_sum = C0T0_stb_vld[0] + C0T0_stb_vld[1] + C0T0_stb_vld[2] + C0T0_stb_vld[3] +
C0T0_stb_vld[4] + C0T0_stb_vld[5] + C0T0_stb_vld[6] + C0T0_stb_vld[7] ;
wire [4:0] C0T1_stb_vld_sum = C0T1_stb_vld[0] + C0T1_stb_vld[1] + C0T1_stb_vld[2] + C0T1_stb_vld[3] +
C0T1_stb_vld[4] + C0T1_stb_vld[5] + C0T1_stb_vld[6] + C0T1_stb_vld[7] ;
wire [4:0] C0T2_stb_vld_sum = C0T2_stb_vld[0] + C0T2_stb_vld[1] + C0T2_stb_vld[2] + C0T2_stb_vld[3] +
C0T2_stb_vld[4] + C0T2_stb_vld[5] + C0T2_stb_vld[6] + C0T2_stb_vld[7] ;
wire [4:0] C0T3_stb_vld_sum = C0T3_stb_vld[0] + C0T3_stb_vld[1] + C0T3_stb_vld[2] + C0T3_stb_vld[3] +
C0T3_stb_vld[4] + C0T3_stb_vld[5] + C0T3_stb_vld[6] + C0T3_stb_vld[7] ;
reg [4:0] C0T0_stb_vld_sum_d1;
reg [4:0] C0T1_stb_vld_sum_d1;
reg [4:0] C0T2_stb_vld_sum_d1;
reg [4:0] C0T3_stb_vld_sum_d1;
wire C0T0_st_ack = &`TOP_DESIGN.sparc0.lsu.cpx_st_ack_tid0;
wire C0T1_st_ack = &`TOP_DESIGN.sparc0.lsu.cpx_st_ack_tid1;
wire C0T2_st_ack = &`TOP_DESIGN.sparc0.lsu.cpx_st_ack_tid2;
wire C0T3_st_ack = &`TOP_DESIGN.sparc0.lsu.cpx_st_ack_tid3;
wire C0T0_defr_trp_en = &`TOP_DESIGN.sparc0.lsu.excpctl.st_defr_trp_en0;
wire C0T1_defr_trp_en = &`TOP_DESIGN.sparc0.lsu.excpctl.st_defr_trp_en1;
wire C0T2_defr_trp_en = &`TOP_DESIGN.sparc0.lsu.excpctl.st_defr_trp_en2;
wire C0T3_defr_trp_en = &`TOP_DESIGN.sparc0.lsu.excpctl.st_defr_trp_en3;
reg C0T0_defr_trp_en_d1;
reg C0T1_defr_trp_en_d1;
reg C0T2_defr_trp_en_d1;
reg C0T3_defr_trp_en_d1;
integer C0T0_stb_drain_cnt;
integer C0T1_stb_drain_cnt;
integer C0T2_stb_drain_cnt;
integer C0T3_stb_drain_cnt;
// Hits in the store buffer
//-------------------------
wire spc0_inst_vld_w = `TOP_DESIGN.sparc0.ifu.fcl.inst_vld_w;
wire [1:0] spc0_sas_thrid_w = `TOP_DESIGN.sparc0.ifu.fcl.sas_thrid_w[1:0];
wire C0_st_ack_w = (spc0_sas_thrid_w == 2'b00) & C0T0_st_ack |
(spc0_sas_thrid_w == 2'b01) & C0T1_st_ack |
(spc0_sas_thrid_w == 2'b10) & C0T2_st_ack |
(spc0_sas_thrid_w == 2'b11) & C0T3_st_ack;
wire [7:0] spc0_stb_ld_full_raw = `TOP_DESIGN.sparc0.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc0_stb_ld_partial_raw = `TOP_DESIGN.sparc0.lsu.stb_ld_partial_raw[7:0];
wire spc0_stb_cam_mhit = `TOP_DESIGN.sparc0.lsu.stb_cam_mhit;
wire spc0_stb_cam_hit = `TOP_DESIGN.sparc0.lsu.stb_cam_hit;
wire [3:0] spc0_lsu_way_hit = `TOP_DESIGN.sparc0.lsu.dctl.lsu_way_hit[3:0];
wire spc0_lsu_ifu_ldst_miss_w = `TOP_DESIGN.sparc0.lsu.lsu_ifu_ldst_miss_w;
wire spc0_ld_inst_vld_g = `TOP_DESIGN.sparc0.lsu.dctl.ld_inst_vld_g;
wire spc0_ldst_dbl_g = `TOP_DESIGN.sparc0.lsu.dctl.ldst_dbl_g;
wire spc0_quad_asi_g = `TOP_DESIGN.sparc0.lsu.dctl.quad_asi_g;
wire [1:0] spc0_ldst_sz_g = `TOP_DESIGN.sparc0.lsu.dctl.ldst_sz_g;
wire spc0_lsu_alt_space_g = `TOP_DESIGN.sparc0.lsu.dctl.lsu_alt_space_g;
wire spc0_mbar_inst0_g = `TOP_DESIGN.sparc0.lsu.dctl.mbar_inst0_g;
wire spc0_mbar_inst1_g = `TOP_DESIGN.sparc0.lsu.dctl.mbar_inst1_g;
wire spc0_mbar_inst2_g = `TOP_DESIGN.sparc0.lsu.dctl.mbar_inst2_g;
wire spc0_mbar_inst3_g = `TOP_DESIGN.sparc0.lsu.dctl.mbar_inst3_g;
wire spc0_flush_inst0_g = `TOP_DESIGN.sparc0.lsu.dctl.flush_inst0_g;
wire spc0_flush_inst1_g = `TOP_DESIGN.sparc0.lsu.dctl.flush_inst1_g;
wire spc0_flush_inst2_g = `TOP_DESIGN.sparc0.lsu.dctl.flush_inst2_g;
wire spc0_flush_inst3_g = `TOP_DESIGN.sparc0.lsu.dctl.flush_inst3_g;
wire spc0_intrpt_disp_asi0_g = `TOP_DESIGN.sparc0.lsu.dctl.intrpt_disp_asi_g & (spc0_sas_thrid_w == 2'b00);
wire spc0_intrpt_disp_asi1_g = `TOP_DESIGN.sparc0.lsu.dctl.intrpt_disp_asi_g & (spc0_sas_thrid_w == 2'b01);
wire spc0_intrpt_disp_asi2_g = `TOP_DESIGN.sparc0.lsu.dctl.intrpt_disp_asi_g & (spc0_sas_thrid_w == 2'b10);
wire spc0_intrpt_disp_asi3_g = `TOP_DESIGN.sparc0.lsu.dctl.intrpt_disp_asi_g & (spc0_sas_thrid_w == 2'b11);
wire spc0_st_inst_vld_g = `TOP_DESIGN.sparc0.lsu.dctl.st_inst_vld_g;
wire spc0_non_altspace_ldst_g = `TOP_DESIGN.sparc0.lsu.dctl.non_altspace_ldst_g;
wire spc0_dctl_flush_pipe_w = `TOP_DESIGN.sparc0.lsu.dctl.dctl_flush_pipe_w;
wire [3:0] spc0_no_spc_rmo_st = `TOP_DESIGN.sparc0.lsu.dctl.no_spc_rmo_st[3:0];
wire spc0_ldst_fp_e = `TOP_DESIGN.sparc0.lsu.ifu_lsu_ldst_fp_e;
wire [2:0] spc0_stb_rdptr = `TOP_DESIGN.sparc0.lsu.stb_rwctl.stb_rdptr_l;
wire spc0_ld_l2cache_req = `TOP_DESIGN.sparc0.lsu.qctl1.ld3_l2cache_rq |
`TOP_DESIGN.sparc0.lsu.qctl1.ld2_l2cache_rq |
`TOP_DESIGN.sparc0.lsu.qctl1.ld1_l2cache_rq |
`TOP_DESIGN.sparc0.lsu.qctl1.ld0_l2cache_rq;
wire [3:0] spc0_dcache_enable = {`TOP_DESIGN.sparc0.lsu.dctl.lsu_ctl_reg0[1],
`TOP_DESIGN.sparc0.lsu.dctl.lsu_ctl_reg1[1],
`TOP_DESIGN.sparc0.lsu.dctl.lsu_ctl_reg2[1],
`TOP_DESIGN.sparc0.lsu.dctl.lsu_ctl_reg3[1]};
wire [3:0] spc0_icache_enable = `TOP_DESIGN.sparc0.lsu.lsu_ifu_icache_en[3:0];
wire spc0_dc_direct_map = `TOP_DESIGN.sparc0.lsu.dc_direct_map;
wire spc0_lsu_ifu_direct_map_l1 = `TOP_DESIGN.sparc0.lsu.lsu_ifu_direct_map_l1;
always @(spc0_dcache_enable)
$display("%0d tso_mon: spc0_dcache_enable changed to %x", $time, spc0_dcache_enable);
always @(spc0_icache_enable)
$display("%0d tso_mon: spc0_icache_enable changed to %x", $time, spc0_icache_enable);
always @(spc0_dc_direct_map)
$display("%0d tso_mon: spc0_dc_direct_map changed to %x", $time, spc0_dc_direct_map);
always @(spc0_lsu_ifu_direct_map_l1)
$display("%0d tso_mon: spc0_lsu_ifu_direct_map_l1 changed to %x", $time, spc0_lsu_ifu_direct_map_l1);
reg spc0_dva_svld_e_d1;
reg spc0_dva_rvld_e_d1;
reg [10:4] spc0_dva_rd_addr_e_d1;
reg [4:0] spc0_dva_snp_addr_e_d1;
reg spc0_lsu_snp_after_rd;
reg spc0_lsu_rd_after_snp;
reg spc0_ldst_fp_m, spc0_ldst_fp_g;
integer spc0_multiple_hits;
reg spc0_skid_d1, spc0_skid_d2, spc0_skid_d3;
initial begin
spc0_skid_d1 = 0;
spc0_skid_d2 = 0;
spc0_skid_d3 = 0;
end
always @(posedge clk)
begin
spc0_skid_d1 <= (~spc0_ifu_lsu_inv_clear & spc0_dfq_rd_advance & spc0_dfq_int_type);
spc0_skid_d2 <= spc0_skid_d1 & ~spc0_ifu_lsu_inv_clear;
spc0_skid_d3 <= spc0_skid_d2 & ~spc0_ifu_lsu_inv_clear;
// The full tracking of this condition is complicated since after the interrupt is advanced
// there may be more invalidations to the IFQ.
// All we care about is that the invalidations BEFORE the interrupt are finished.
// I provided a command line argument to disable this check.
if(spc0_skid_d3 & enable_ifu_lsu_inv_clear)
finish_test("spc", "tso_mon: spc0_ifu_lsu_inv_clear should have been clear by now", 0);
spc0_dva_svld_e_d1 <= spc0_dva_svld_e;
spc0_dva_rvld_e_d1 <= spc0_dva_rvld_e;
spc0_dva_rd_addr_e_d1 <= spc0_dva_rd_addr_e;
spc0_dva_snp_addr_e_d1 <= spc0_dva_snp_addr_e;
if(spc0_dva_svld_e_d1 & spc0_dva_rvld_e & (spc0_dva_rd_addr_e_d1[10:6] == spc0_dva_snp_addr_e[4:0]))
spc0_lsu_rd_after_snp <= 1'b1;
else
spc0_lsu_rd_after_snp <= 1'b0;
if(spc0_dva_svld_e & spc0_dva_rvld_e_d1 & (spc0_dva_rd_addr_e[10:6] == spc0_dva_snp_addr_e_d1[4:0]))
spc0_lsu_snp_after_rd <= 1'b1;
else
spc0_lsu_snp_after_rd <= 1'b0;
spc0_ldst_fp_m <= spc0_ldst_fp_e;
spc0_ldst_fp_g <= spc0_ldst_fp_m;
if(spc0_stb_data_rptr_vld & spc0_stb_data_wptr_vld & ~spc0_stbrwctl_flush_pipe_w &
(spc0_stb_data_rd_ptr == spc0_stb_data_wr_ptr) & spc0_lsu_st_pcx_rq_pick)
begin
finish_test("spc", "tso_mon: LSU stb data write and read in the same cycle", 0);
end
spc0_multiple_hits = (spc0_lsu_way_hit[3] + spc0_lsu_way_hit[2] + spc0_lsu_way_hit[1] + spc0_lsu_way_hit[0]);
if(!spc0_lsu_ifu_ldst_miss_w && (spc0_multiple_hits >1) && spc0_inst_vld_w && !spc0_dctl_flush_pipe_w && !spc0_lsu_dc_tag_pe_g_unmasked_or)
finish_test("spc", "tso_mon: LSU multiple hits ", 0);
end
wire spc0_ld_dbl = spc0_ld_inst_vld_g & spc0_ldst_dbl_g & ~spc0_quad_asi_g;
wire spc0_ld_quad = spc0_ld_inst_vld_g & spc0_ldst_dbl_g & spc0_quad_asi_g;
wire spc0_ld_other = spc0_ld_inst_vld_g & ~spc0_ldst_dbl_g;
wire spc0_ld_dbl_fp = spc0_ld_dbl & spc0_ldst_fp_g;
wire spc0_ld_other_fp = spc0_ld_other & spc0_ldst_fp_g;
wire spc0_ld_dbl_int = spc0_ld_dbl & ~spc0_ldst_fp_g;
wire spc0_ld_quad_int = spc0_ld_quad & ~spc0_ldst_fp_g;
wire spc0_ld_other_int= spc0_ld_other & ~spc0_ldst_fp_g;
wire spc0_ld_bypassok_hit = |spc0_stb_ld_full_raw[7:0] & ~spc0_stb_cam_mhit;
wire spc0_ld_partial_hit = |spc0_stb_ld_partial_raw[7:0] & ~spc0_stb_cam_mhit;
wire spc0_ld_multiple_hit = spc0_stb_cam_mhit;
wire spc0_any_lsu_way_hit = |spc0_lsu_way_hit;
wire [7:0] spc0_stb_rdptr_decoded = (spc0_stb_rdptr ==3'b000) ? 8'b00000001 :
(spc0_stb_rdptr ==3'b001) ? 8'b00000010 :
(spc0_stb_rdptr ==3'b010) ? 8'b00000100 :
(spc0_stb_rdptr ==3'b011) ? 8'b00001000 :
(spc0_stb_rdptr ==3'b100) ? 8'b00010000 :
(spc0_stb_rdptr ==3'b101) ? 8'b00100000 :
(spc0_stb_rdptr ==3'b110) ? 8'b01000000 :
(spc0_stb_rdptr ==3'b111) ? 8'b10000000 : 8'h00;
wire spc0_stb_top_hit = |(spc0_stb_rdptr_decoded & (spc0_stb_ld_full_raw | spc0_stb_ld_partial_raw));
//---------------------------------------------------------------------
// ld_type[4:0] hit_type[2:0], cache_hit, hit_top
// this is passed to the coverage monitor.
//---------------------------------------------------------------------
wire [10:0] spc0_stb_ld_hit_info =
{spc0_ld_dbl_fp, spc0_ld_other_fp,
spc0_ld_dbl_int, spc0_ld_quad_int, spc0_ld_other_int,
spc0_ld_bypassok_hit, spc0_ld_partial_hit, spc0_ld_multiple_hit,
spc0_any_lsu_way_hit,
spc0_stb_top_hit, C0_st_ack_w};
reg spc0_mbar0_active;
reg spc0_mbar1_active;
reg spc0_mbar2_active;
reg spc0_mbar3_active;
reg spc0_flush0_active;
reg spc0_flush1_active;
reg spc0_flush2_active;
reg spc0_flush3_active;
reg spc0_intr0_active;
reg spc0_intr1_active;
reg spc0_intr2_active;
reg spc0_intr3_active;
always @(negedge clk)
begin
if(~rst_l)
begin
spc0_mbar0_active <= 1'b0;
spc0_mbar1_active <= 1'b0;
spc0_mbar2_active <= 1'b0;
spc0_mbar3_active <= 1'b0;
spc0_flush0_active <= 1'b0;
spc0_flush1_active <= 1'b0;
spc0_flush2_active <= 1'b0;
spc0_flush3_active <= 1'b0;
spc0_intr0_active <= 1'b0;
spc0_intr1_active <= 1'b0;
spc0_intr2_active <= 1'b0;
spc0_intr3_active <= 1'b0;
end
else
begin
if(spc0_mbar_inst0_g & ~spc0_dctl_flush_pipe_w & (C0T0_stb_ne|~spc0_no_spc_rmo_st[0]))
spc0_mbar0_active <= 1'b1;
else if(~C0T0_stb_ne & spc0_no_spc_rmo_st[0])
spc0_mbar0_active <= 1'b0;
if(spc0_mbar_inst1_g & ~ spc0_dctl_flush_pipe_w & (C0T1_stb_ne|~spc0_no_spc_rmo_st[1]))
spc0_mbar1_active <= 1'b1;
else if(~C0T1_stb_ne & spc0_no_spc_rmo_st[1])
spc0_mbar1_active <= 1'b0;
if(spc0_mbar_inst2_g & ~ spc0_dctl_flush_pipe_w & (C0T2_stb_ne|~spc0_no_spc_rmo_st[2]))
spc0_mbar2_active <= 1'b1;
else if(~C0T2_stb_ne & spc0_no_spc_rmo_st[2])
spc0_mbar2_active <= 1'b0;
if(spc0_mbar_inst3_g & ~ spc0_dctl_flush_pipe_w & (C0T3_stb_ne|~spc0_no_spc_rmo_st[3]))
spc0_mbar3_active <= 1'b1;
else if(~C0T3_stb_ne & spc0_no_spc_rmo_st[3])
spc0_mbar3_active <= 1'b0;
if(spc0_flush_inst0_g & ~spc0_dctl_flush_pipe_w & C0T0_stb_ne) spc0_flush0_active <= 1'b1;
else if(~C0T0_stb_ne) spc0_flush0_active <= 1'b0;
if(spc0_flush_inst1_g & ~spc0_dctl_flush_pipe_w & C0T1_stb_ne) spc0_flush1_active <= 1'b1;
else if(~C0T1_stb_ne) spc0_flush1_active <= 1'b0;
if(spc0_flush_inst2_g & ~spc0_dctl_flush_pipe_w & C0T2_stb_ne) spc0_flush2_active <= 1'b1;
else if(~C0T2_stb_ne) spc0_flush2_active <= 1'b0;
if(spc0_flush_inst3_g & ~spc0_dctl_flush_pipe_w & C0T3_stb_ne) spc0_flush3_active <= 1'b1;
else if(~C0T3_stb_ne) spc0_flush3_active <= 1'b0;
if(spc0_intrpt_disp_asi0_g & spc0_st_inst_vld_g & ~spc0_non_altspace_ldst_g & ~spc0_dctl_flush_pipe_w & C0T0_stb_ne)
spc0_intr0_active <= 1'b1;
else if(~C0T0_stb_ne)
spc0_intr0_active <= 1'b0;
if(spc0_intrpt_disp_asi1_g & spc0_st_inst_vld_g & ~spc0_non_altspace_ldst_g & ~spc0_dctl_flush_pipe_w & C0T1_stb_ne)
spc0_intr1_active <= 1'b1;
else if(~C0T1_stb_ne)
spc0_intr1_active <= 1'b0;
if(spc0_intrpt_disp_asi2_g & spc0_st_inst_vld_g & ~spc0_non_altspace_ldst_g & ~spc0_dctl_flush_pipe_w & C0T2_stb_ne)
spc0_intr2_active <= 1'b1;
else if(~C0T2_stb_ne)
spc0_intr2_active <= 1'b0;
if(spc0_intrpt_disp_asi3_g & spc0_st_inst_vld_g & ~spc0_non_altspace_ldst_g & ~spc0_dctl_flush_pipe_w & C0T3_stb_ne)
spc0_intr3_active <= 1'b1;
else if(~C0T3_stb_ne)
spc0_intr3_active <= 1'b0;
end
if(spc0_mbar0_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "membar violation thread 0", 0);
if(spc0_mbar1_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "membar violation thread 1", 0);
if(spc0_mbar2_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "membar violation thread 2", 0);
if(spc0_mbar3_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "membar violation thread 3", 0);
if(spc0_flush0_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "flush violation thread 0", 0);
if(spc0_flush1_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "flush violation thread 1", 0);
if(spc0_flush2_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "flush violation thread 2", 0);
if(spc0_flush3_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "flush violation thread 3", 0);
if(spc0_intr0_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "intr violation thread 0", 0);
if(spc0_intr1_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "intr violation thread 1", 0);
if(spc0_intr2_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "intr violation thread 2", 0);
if(spc0_intr3_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "intr violation thread 3", 0);
if(~rst_l | ~C0T0_stb_full | sctag_pcx_stall_pq) C0T0_stb_drain_cnt = 0;
else C0T0_stb_drain_cnt = C0T0_stb_drain_cnt + 1;
if(C0T0_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 0 is not draining", 0);
if(~rst_l | ~C0T1_stb_full | sctag_pcx_stall_pq) C0T1_stb_drain_cnt = 0;
else C0T1_stb_drain_cnt = C0T1_stb_drain_cnt + 1;
if(C0T1_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 1 is not draining", 0);
if(~rst_l | ~C0T2_stb_full | sctag_pcx_stall_pq) C0T2_stb_drain_cnt = 0;
else C0T2_stb_drain_cnt = C0T2_stb_drain_cnt + 1;
if(C0T2_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 2 is not draining", 0);
if(~rst_l | ~C0T3_stb_full | sctag_pcx_stall_pq) C0T3_stb_drain_cnt = 0;
else C0T3_stb_drain_cnt = C0T3_stb_drain_cnt + 1;
if(C0T3_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 3 is not draining", 0);
C0T0_stb_vld_sum_d1 <= C0T0_stb_vld_sum;
C0T1_stb_vld_sum_d1 <= C0T1_stb_vld_sum;
C0T2_stb_vld_sum_d1 <= C0T2_stb_vld_sum;
C0T3_stb_vld_sum_d1 <= C0T3_stb_vld_sum;
C0T0_defr_trp_en_d1 <= C0T0_defr_trp_en;
C0T1_defr_trp_en_d1 <= C0T1_defr_trp_en;
C0T2_defr_trp_en_d1 <= C0T2_defr_trp_en;
C0T3_defr_trp_en_d1 <= C0T3_defr_trp_en;
if(rst_l & C0T0_defr_trp_en_d1 & (C0T0_stb_vld_sum_d1 < C0T0_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T0", 0);
if(rst_l & C0T1_defr_trp_en_d1 & (C0T1_stb_vld_sum_d1 < C0T1_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T1", 0);
if(rst_l & C0T2_defr_trp_en_d1 & (C0T2_stb_vld_sum_d1 < C0T2_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T2", 0);
if(rst_l & C0T3_defr_trp_en_d1 & (C0T3_stb_vld_sum_d1 < C0T3_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T3", 0);
end
`endif // ifdef RTL_SPARC0
`ifdef RTL_SPARC1
wire C1T0_stb_ne = |`TOP_DESIGN.sparc1.lsu.stb_ctl0.stb_state_vld[7:0];
wire C1T1_stb_ne = |`TOP_DESIGN.sparc1.lsu.stb_ctl1.stb_state_vld[7:0];
wire C1T2_stb_ne = |`TOP_DESIGN.sparc1.lsu.stb_ctl2.stb_state_vld[7:0];
wire C1T3_stb_ne = |`TOP_DESIGN.sparc1.lsu.stb_ctl3.stb_state_vld[7:0];
wire C1T0_stb_nced = |( `TOP_DESIGN.sparc1.lsu.stb_ctl0.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc1.lsu.stb_ctl0.stb_state_ced[7:0]);
wire C1T1_stb_nced = |( `TOP_DESIGN.sparc1.lsu.stb_ctl1.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc1.lsu.stb_ctl1.stb_state_ced[7:0]);
wire C1T2_stb_nced = |( `TOP_DESIGN.sparc1.lsu.stb_ctl2.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc1.lsu.stb_ctl2.stb_state_ced[7:0]);
wire C1T3_stb_nced = |( `TOP_DESIGN.sparc1.lsu.stb_ctl3.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc1.lsu.stb_ctl3.stb_state_ced[7:0]);
`else
wire C1T0_stb_ne = 1'b0;
wire C1T1_stb_ne = 1'b0;
wire C1T2_stb_ne = 1'b0;
wire C1T3_stb_ne = 1'b0;
wire C1T0_stb_nced = 1'b0;
wire C1T1_stb_nced = 1'b0;
wire C1T2_stb_nced = 1'b0;
wire C1T3_stb_nced = 1'b0;
`endif // ifdef RTL_SPARC1
`ifdef RTL_SPARC1
wire spc1_lsu_ifill_pkt_vld = `TOP_DESIGN.sparc1.lsu.qctl2.lsu_ifill_pkt_vld;
wire spc1_dfq_rd_advance = `TOP_DESIGN.sparc1.lsu.qctl2.dfq_rd_advance;
wire spc1_dfq_int_type = `TOP_DESIGN.sparc1.lsu.qctl2.dfq_int_type;
wire spc1_ifu_lsu_inv_clear = `TOP_DESIGN.sparc1.lsu.qctl2.ifu_lsu_inv_clear;
wire spc1_dva_svld_e = `TOP_DESIGN.sparc1.lsu.qctl2.dva_svld_e;
wire spc1_dva_rvld_e = `TOP_DESIGN.sparc1.lsu.dva.rd_en;
wire [10:4] spc1_dva_rd_addr_e = `TOP_DESIGN.sparc1.lsu.dva.rd_adr1[6:0];
wire [4:0] spc1_dva_snp_addr_e = `TOP_DESIGN.sparc1.lsu.qctl2.dva_snp_addr_e[4:0];
wire [4:0] spc1_stb_data_rd_ptr = `TOP_DESIGN.sparc1.lsu.stb_data_rd_ptr[4:0];
wire [4:0] spc1_stb_data_wr_ptr = `TOP_DESIGN.sparc1.lsu.stb_data_wr_ptr[4:0];
wire spc1_stb_data_wptr_vld = `TOP_DESIGN.sparc1.lsu.stb_data_wptr_vld;
wire spc1_stb_data_rptr_vld = `TOP_DESIGN.sparc1.lsu.stb_data_rptr_vld;
wire spc1_stbrwctl_flush_pipe_w = `TOP_DESIGN.sparc1.lsu.stb_rwctl.lsu_stbrwctl_flush_pipe_w;
wire spc1_lsu_st_pcx_rq_pick = |`TOP_DESIGN.sparc1.lsu.stb_rwctl.lsu_st_pcx_rq_pick[3:0];
wire [3:0] spc1_lsu_rd_dtag_parity_g = `TOP_DESIGN.sparc1.lsu.dctl.lsu_rd_dtag_parity_g[3:0];
wire [3:0] spc1_dva_vld_g = `TOP_DESIGN.sparc1.lsu.dctl.dva_vld_g[3:0];
wire [3:0] spc1_lsu_dc_tag_pe_g_unmasked = spc1_lsu_rd_dtag_parity_g[3:0] & spc1_dva_vld_g[3:0];
wire spc1_lsu_dc_tag_pe_g_unmasked_or = |spc1_lsu_dc_tag_pe_g_unmasked[3:0];
wire C1T0_stb_full = &`TOP_DESIGN.sparc1.lsu.stb_ctl0.stb_state_vld[7:0];
wire C1T1_stb_full = &`TOP_DESIGN.sparc1.lsu.stb_ctl1.stb_state_vld[7:0];
wire C1T2_stb_full = &`TOP_DESIGN.sparc1.lsu.stb_ctl2.stb_state_vld[7:0];
wire C1T3_stb_full = &`TOP_DESIGN.sparc1.lsu.stb_ctl3.stb_state_vld[7:0];
wire [7:0] C1T0_stb_vld = `TOP_DESIGN.sparc1.lsu.stb_ctl0.stb_state_vld[7:0];
wire [7:0] C1T1_stb_vld = `TOP_DESIGN.sparc1.lsu.stb_ctl1.stb_state_vld[7:0];
wire [7:0] C1T2_stb_vld = `TOP_DESIGN.sparc1.lsu.stb_ctl2.stb_state_vld[7:0];
wire [7:0] C1T3_stb_vld = `TOP_DESIGN.sparc1.lsu.stb_ctl3.stb_state_vld[7:0];
wire [4:0] C1T0_stb_vld_sum = C1T0_stb_vld[0] + C1T0_stb_vld[1] + C1T0_stb_vld[2] + C1T0_stb_vld[3] +
C1T0_stb_vld[4] + C1T0_stb_vld[5] + C1T0_stb_vld[6] + C1T0_stb_vld[7] ;
wire [4:0] C1T1_stb_vld_sum = C1T1_stb_vld[0] + C1T1_stb_vld[1] + C1T1_stb_vld[2] + C1T1_stb_vld[3] +
C1T1_stb_vld[4] + C1T1_stb_vld[5] + C1T1_stb_vld[6] + C1T1_stb_vld[7] ;
wire [4:0] C1T2_stb_vld_sum = C1T2_stb_vld[0] + C1T2_stb_vld[1] + C1T2_stb_vld[2] + C1T2_stb_vld[3] +
C1T2_stb_vld[4] + C1T2_stb_vld[5] + C1T2_stb_vld[6] + C1T2_stb_vld[7] ;
wire [4:0] C1T3_stb_vld_sum = C1T3_stb_vld[0] + C1T3_stb_vld[1] + C1T3_stb_vld[2] + C1T3_stb_vld[3] +
C1T3_stb_vld[4] + C1T3_stb_vld[5] + C1T3_stb_vld[6] + C1T3_stb_vld[7] ;
reg [4:0] C1T0_stb_vld_sum_d1;
reg [4:0] C1T1_stb_vld_sum_d1;
reg [4:0] C1T2_stb_vld_sum_d1;
reg [4:0] C1T3_stb_vld_sum_d1;
wire C1T0_st_ack = &`TOP_DESIGN.sparc1.lsu.cpx_st_ack_tid0;
wire C1T1_st_ack = &`TOP_DESIGN.sparc1.lsu.cpx_st_ack_tid1;
wire C1T2_st_ack = &`TOP_DESIGN.sparc1.lsu.cpx_st_ack_tid2;
wire C1T3_st_ack = &`TOP_DESIGN.sparc1.lsu.cpx_st_ack_tid3;
wire C1T0_defr_trp_en = &`TOP_DESIGN.sparc1.lsu.excpctl.st_defr_trp_en0;
wire C1T1_defr_trp_en = &`TOP_DESIGN.sparc1.lsu.excpctl.st_defr_trp_en1;
wire C1T2_defr_trp_en = &`TOP_DESIGN.sparc1.lsu.excpctl.st_defr_trp_en2;
wire C1T3_defr_trp_en = &`TOP_DESIGN.sparc1.lsu.excpctl.st_defr_trp_en3;
reg C1T0_defr_trp_en_d1;
reg C1T1_defr_trp_en_d1;
reg C1T2_defr_trp_en_d1;
reg C1T3_defr_trp_en_d1;
integer C1T0_stb_drain_cnt;
integer C1T1_stb_drain_cnt;
integer C1T2_stb_drain_cnt;
integer C1T3_stb_drain_cnt;
// Hits in the store buffer
//-------------------------
wire spc1_inst_vld_w = `TOP_DESIGN.sparc1.ifu.fcl.inst_vld_w;
wire [1:0] spc1_sas_thrid_w = `TOP_DESIGN.sparc1.ifu.fcl.sas_thrid_w[1:0];
wire C1_st_ack_w = (spc1_sas_thrid_w == 2'b00) & C1T0_st_ack |
(spc1_sas_thrid_w == 2'b01) & C1T1_st_ack |
(spc1_sas_thrid_w == 2'b10) & C1T2_st_ack |
(spc1_sas_thrid_w == 2'b11) & C1T3_st_ack;
wire [7:0] spc1_stb_ld_full_raw = `TOP_DESIGN.sparc1.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc1_stb_ld_partial_raw = `TOP_DESIGN.sparc1.lsu.stb_ld_partial_raw[7:0];
wire spc1_stb_cam_mhit = `TOP_DESIGN.sparc1.lsu.stb_cam_mhit;
wire spc1_stb_cam_hit = `TOP_DESIGN.sparc1.lsu.stb_cam_hit;
wire [3:0] spc1_lsu_way_hit = `TOP_DESIGN.sparc1.lsu.dctl.lsu_way_hit[3:0];
wire spc1_lsu_ifu_ldst_miss_w = `TOP_DESIGN.sparc1.lsu.lsu_ifu_ldst_miss_w;
wire spc1_ld_inst_vld_g = `TOP_DESIGN.sparc1.lsu.dctl.ld_inst_vld_g;
wire spc1_ldst_dbl_g = `TOP_DESIGN.sparc1.lsu.dctl.ldst_dbl_g;
wire spc1_quad_asi_g = `TOP_DESIGN.sparc1.lsu.dctl.quad_asi_g;
wire [1:0] spc1_ldst_sz_g = `TOP_DESIGN.sparc1.lsu.dctl.ldst_sz_g;
wire spc1_lsu_alt_space_g = `TOP_DESIGN.sparc1.lsu.dctl.lsu_alt_space_g;
wire spc1_mbar_inst0_g = `TOP_DESIGN.sparc1.lsu.dctl.mbar_inst0_g;
wire spc1_mbar_inst1_g = `TOP_DESIGN.sparc1.lsu.dctl.mbar_inst1_g;
wire spc1_mbar_inst2_g = `TOP_DESIGN.sparc1.lsu.dctl.mbar_inst2_g;
wire spc1_mbar_inst3_g = `TOP_DESIGN.sparc1.lsu.dctl.mbar_inst3_g;
wire spc1_flush_inst0_g = `TOP_DESIGN.sparc1.lsu.dctl.flush_inst0_g;
wire spc1_flush_inst1_g = `TOP_DESIGN.sparc1.lsu.dctl.flush_inst1_g;
wire spc1_flush_inst2_g = `TOP_DESIGN.sparc1.lsu.dctl.flush_inst2_g;
wire spc1_flush_inst3_g = `TOP_DESIGN.sparc1.lsu.dctl.flush_inst3_g;
wire spc1_intrpt_disp_asi0_g = `TOP_DESIGN.sparc1.lsu.dctl.intrpt_disp_asi_g & (spc1_sas_thrid_w == 2'b00);
wire spc1_intrpt_disp_asi1_g = `TOP_DESIGN.sparc1.lsu.dctl.intrpt_disp_asi_g & (spc1_sas_thrid_w == 2'b01);
wire spc1_intrpt_disp_asi2_g = `TOP_DESIGN.sparc1.lsu.dctl.intrpt_disp_asi_g & (spc1_sas_thrid_w == 2'b10);
wire spc1_intrpt_disp_asi3_g = `TOP_DESIGN.sparc1.lsu.dctl.intrpt_disp_asi_g & (spc1_sas_thrid_w == 2'b11);
wire spc1_st_inst_vld_g = `TOP_DESIGN.sparc1.lsu.dctl.st_inst_vld_g;
wire spc1_non_altspace_ldst_g = `TOP_DESIGN.sparc1.lsu.dctl.non_altspace_ldst_g;
wire spc1_dctl_flush_pipe_w = `TOP_DESIGN.sparc1.lsu.dctl.dctl_flush_pipe_w;
wire [3:0] spc1_no_spc_rmo_st = `TOP_DESIGN.sparc1.lsu.dctl.no_spc_rmo_st[3:0];
wire spc1_ldst_fp_e = `TOP_DESIGN.sparc1.lsu.ifu_lsu_ldst_fp_e;
wire [2:0] spc1_stb_rdptr = `TOP_DESIGN.sparc1.lsu.stb_rwctl.stb_rdptr_l;
wire spc1_ld_l2cache_req = `TOP_DESIGN.sparc1.lsu.qctl1.ld3_l2cache_rq |
`TOP_DESIGN.sparc1.lsu.qctl1.ld2_l2cache_rq |
`TOP_DESIGN.sparc1.lsu.qctl1.ld1_l2cache_rq |
`TOP_DESIGN.sparc1.lsu.qctl1.ld0_l2cache_rq;
wire [3:0] spc1_dcache_enable = {`TOP_DESIGN.sparc1.lsu.dctl.lsu_ctl_reg0[1],
`TOP_DESIGN.sparc1.lsu.dctl.lsu_ctl_reg1[1],
`TOP_DESIGN.sparc1.lsu.dctl.lsu_ctl_reg2[1],
`TOP_DESIGN.sparc1.lsu.dctl.lsu_ctl_reg3[1]};
wire [3:0] spc1_icache_enable = `TOP_DESIGN.sparc1.lsu.lsu_ifu_icache_en[3:0];
wire spc1_dc_direct_map = `TOP_DESIGN.sparc1.lsu.dc_direct_map;
wire spc1_lsu_ifu_direct_map_l1 = `TOP_DESIGN.sparc1.lsu.lsu_ifu_direct_map_l1;
always @(spc1_dcache_enable)
$display("%0d tso_mon: spc1_dcache_enable changed to %x", $time, spc1_dcache_enable);
always @(spc1_icache_enable)
$display("%0d tso_mon: spc1_icache_enable changed to %x", $time, spc1_icache_enable);
always @(spc1_dc_direct_map)
$display("%0d tso_mon: spc1_dc_direct_map changed to %x", $time, spc1_dc_direct_map);
always @(spc1_lsu_ifu_direct_map_l1)
$display("%0d tso_mon: spc1_lsu_ifu_direct_map_l1 changed to %x", $time, spc1_lsu_ifu_direct_map_l1);
reg spc1_dva_svld_e_d1;
reg spc1_dva_rvld_e_d1;
reg [10:4] spc1_dva_rd_addr_e_d1;
reg [4:0] spc1_dva_snp_addr_e_d1;
reg spc1_lsu_snp_after_rd;
reg spc1_lsu_rd_after_snp;
reg spc1_ldst_fp_m, spc1_ldst_fp_g;
integer spc1_multiple_hits;
reg spc1_skid_d1, spc1_skid_d2, spc1_skid_d3;
initial begin
spc1_skid_d1 = 0;
spc1_skid_d2 = 0;
spc1_skid_d3 = 0;
end
always @(posedge clk)
begin
spc1_skid_d1 <= (~spc1_ifu_lsu_inv_clear & spc1_dfq_rd_advance & spc1_dfq_int_type);
spc1_skid_d2 <= spc1_skid_d1 & ~spc1_ifu_lsu_inv_clear;
spc1_skid_d3 <= spc1_skid_d2 & ~spc1_ifu_lsu_inv_clear;
// The full tracking of this condition is complicated since after the interrupt is advanced
// there may be more invalidations to the IFQ.
// All we care about is that the invalidations BEFORE the interrupt are finished.
// I provided a command line argument to disable this check.
if(spc1_skid_d3 & enable_ifu_lsu_inv_clear)
finish_test("spc", "tso_mon: spc1_ifu_lsu_inv_clear should have been clear by now", 1);
spc1_dva_svld_e_d1 <= spc1_dva_svld_e;
spc1_dva_rvld_e_d1 <= spc1_dva_rvld_e;
spc1_dva_rd_addr_e_d1 <= spc1_dva_rd_addr_e;
spc1_dva_snp_addr_e_d1 <= spc1_dva_snp_addr_e;
if(spc1_dva_svld_e_d1 & spc1_dva_rvld_e & (spc1_dva_rd_addr_e_d1[10:6] == spc1_dva_snp_addr_e[4:0]))
spc1_lsu_rd_after_snp <= 1'b1;
else
spc1_lsu_rd_after_snp <= 1'b0;
if(spc1_dva_svld_e & spc1_dva_rvld_e_d1 & (spc1_dva_rd_addr_e[10:6] == spc1_dva_snp_addr_e_d1[4:0]))
spc1_lsu_snp_after_rd <= 1'b1;
else
spc1_lsu_snp_after_rd <= 1'b0;
spc1_ldst_fp_m <= spc1_ldst_fp_e;
spc1_ldst_fp_g <= spc1_ldst_fp_m;
if(spc1_stb_data_rptr_vld & spc1_stb_data_wptr_vld & ~spc1_stbrwctl_flush_pipe_w &
(spc1_stb_data_rd_ptr == spc1_stb_data_wr_ptr) & spc1_lsu_st_pcx_rq_pick)
begin
finish_test("spc", "tso_mon: LSU stb data write and read in the same cycle", 1);
end
spc1_multiple_hits = (spc1_lsu_way_hit[3] + spc1_lsu_way_hit[2] + spc1_lsu_way_hit[1] + spc1_lsu_way_hit[0]);
if(!spc1_lsu_ifu_ldst_miss_w && (spc1_multiple_hits >1) && spc1_inst_vld_w && !spc1_dctl_flush_pipe_w && !spc1_lsu_dc_tag_pe_g_unmasked_or)
finish_test("spc", "tso_mon: LSU multiple hits ", 1);
end
wire spc1_ld_dbl = spc1_ld_inst_vld_g & spc1_ldst_dbl_g & ~spc1_quad_asi_g;
wire spc1_ld_quad = spc1_ld_inst_vld_g & spc1_ldst_dbl_g & spc1_quad_asi_g;
wire spc1_ld_other = spc1_ld_inst_vld_g & ~spc1_ldst_dbl_g;
wire spc1_ld_dbl_fp = spc1_ld_dbl & spc1_ldst_fp_g;
wire spc1_ld_other_fp = spc1_ld_other & spc1_ldst_fp_g;
wire spc1_ld_dbl_int = spc1_ld_dbl & ~spc1_ldst_fp_g;
wire spc1_ld_quad_int = spc1_ld_quad & ~spc1_ldst_fp_g;
wire spc1_ld_other_int= spc1_ld_other & ~spc1_ldst_fp_g;
wire spc1_ld_bypassok_hit = |spc1_stb_ld_full_raw[7:0] & ~spc1_stb_cam_mhit;
wire spc1_ld_partial_hit = |spc1_stb_ld_partial_raw[7:0] & ~spc1_stb_cam_mhit;
wire spc1_ld_multiple_hit = spc1_stb_cam_mhit;
wire spc1_any_lsu_way_hit = |spc1_lsu_way_hit;
wire [7:0] spc1_stb_rdptr_decoded = (spc1_stb_rdptr ==3'b000) ? 8'b00000001 :
(spc1_stb_rdptr ==3'b001) ? 8'b00000010 :
(spc1_stb_rdptr ==3'b010) ? 8'b00000100 :
(spc1_stb_rdptr ==3'b011) ? 8'b00001000 :
(spc1_stb_rdptr ==3'b100) ? 8'b00010000 :
(spc1_stb_rdptr ==3'b101) ? 8'b00100000 :
(spc1_stb_rdptr ==3'b110) ? 8'b01000000 :
(spc1_stb_rdptr ==3'b111) ? 8'b10000000 : 8'h00;
wire spc1_stb_top_hit = |(spc1_stb_rdptr_decoded & (spc1_stb_ld_full_raw | spc1_stb_ld_partial_raw));
//---------------------------------------------------------------------
// ld_type[4:0] hit_type[2:0], cache_hit, hit_top
// this is passed to the coverage monitor.
//---------------------------------------------------------------------
wire [10:0] spc1_stb_ld_hit_info =
{spc1_ld_dbl_fp, spc1_ld_other_fp,
spc1_ld_dbl_int, spc1_ld_quad_int, spc1_ld_other_int,
spc1_ld_bypassok_hit, spc1_ld_partial_hit, spc1_ld_multiple_hit,
spc1_any_lsu_way_hit,
spc1_stb_top_hit, C1_st_ack_w};
reg spc1_mbar0_active;
reg spc1_mbar1_active;
reg spc1_mbar2_active;
reg spc1_mbar3_active;
reg spc1_flush0_active;
reg spc1_flush1_active;
reg spc1_flush2_active;
reg spc1_flush3_active;
reg spc1_intr0_active;
reg spc1_intr1_active;
reg spc1_intr2_active;
reg spc1_intr3_active;
always @(negedge clk)
begin
if(~rst_l)
begin
spc1_mbar0_active <= 1'b0;
spc1_mbar1_active <= 1'b0;
spc1_mbar2_active <= 1'b0;
spc1_mbar3_active <= 1'b0;
spc1_flush0_active <= 1'b0;
spc1_flush1_active <= 1'b0;
spc1_flush2_active <= 1'b0;
spc1_flush3_active <= 1'b0;
spc1_intr0_active <= 1'b0;
spc1_intr1_active <= 1'b0;
spc1_intr2_active <= 1'b0;
spc1_intr3_active <= 1'b0;
end
else
begin
if(spc1_mbar_inst0_g & ~spc1_dctl_flush_pipe_w & (C1T0_stb_ne|~spc1_no_spc_rmo_st[0]))
spc1_mbar0_active <= 1'b1;
else if(~C1T0_stb_ne & spc1_no_spc_rmo_st[0])
spc1_mbar0_active <= 1'b0;
if(spc1_mbar_inst1_g & ~ spc1_dctl_flush_pipe_w & (C1T1_stb_ne|~spc1_no_spc_rmo_st[1]))
spc1_mbar1_active <= 1'b1;
else if(~C1T1_stb_ne & spc1_no_spc_rmo_st[1])
spc1_mbar1_active <= 1'b0;
if(spc1_mbar_inst2_g & ~ spc1_dctl_flush_pipe_w & (C1T2_stb_ne|~spc1_no_spc_rmo_st[2]))
spc1_mbar2_active <= 1'b1;
else if(~C1T2_stb_ne & spc1_no_spc_rmo_st[2])
spc1_mbar2_active <= 1'b0;
if(spc1_mbar_inst3_g & ~ spc1_dctl_flush_pipe_w & (C1T3_stb_ne|~spc1_no_spc_rmo_st[3]))
spc1_mbar3_active <= 1'b1;
else if(~C1T3_stb_ne & spc1_no_spc_rmo_st[3])
spc1_mbar3_active <= 1'b0;
if(spc1_flush_inst0_g & ~spc1_dctl_flush_pipe_w & C1T0_stb_ne) spc1_flush0_active <= 1'b1;
else if(~C1T0_stb_ne) spc1_flush0_active <= 1'b0;
if(spc1_flush_inst1_g & ~spc1_dctl_flush_pipe_w & C1T1_stb_ne) spc1_flush1_active <= 1'b1;
else if(~C1T1_stb_ne) spc1_flush1_active <= 1'b0;
if(spc1_flush_inst2_g & ~spc1_dctl_flush_pipe_w & C1T2_stb_ne) spc1_flush2_active <= 1'b1;
else if(~C1T2_stb_ne) spc1_flush2_active <= 1'b0;
if(spc1_flush_inst3_g & ~spc1_dctl_flush_pipe_w & C1T3_stb_ne) spc1_flush3_active <= 1'b1;
else if(~C1T3_stb_ne) spc1_flush3_active <= 1'b0;
if(spc1_intrpt_disp_asi0_g & spc1_st_inst_vld_g & ~spc1_non_altspace_ldst_g & ~spc1_dctl_flush_pipe_w & C1T0_stb_ne)
spc1_intr0_active <= 1'b1;
else if(~C1T0_stb_ne)
spc1_intr0_active <= 1'b0;
if(spc1_intrpt_disp_asi1_g & spc1_st_inst_vld_g & ~spc1_non_altspace_ldst_g & ~spc1_dctl_flush_pipe_w & C1T1_stb_ne)
spc1_intr1_active <= 1'b1;
else if(~C1T1_stb_ne)
spc1_intr1_active <= 1'b0;
if(spc1_intrpt_disp_asi2_g & spc1_st_inst_vld_g & ~spc1_non_altspace_ldst_g & ~spc1_dctl_flush_pipe_w & C1T2_stb_ne)
spc1_intr2_active <= 1'b1;
else if(~C1T2_stb_ne)
spc1_intr2_active <= 1'b0;
if(spc1_intrpt_disp_asi3_g & spc1_st_inst_vld_g & ~spc1_non_altspace_ldst_g & ~spc1_dctl_flush_pipe_w & C1T3_stb_ne)
spc1_intr3_active <= 1'b1;
else if(~C1T3_stb_ne)
spc1_intr3_active <= 1'b0;
end
if(spc1_mbar0_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "membar violation thread 0", 1);
if(spc1_mbar1_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "membar violation thread 1", 1);
if(spc1_mbar2_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "membar violation thread 2", 1);
if(spc1_mbar3_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "membar violation thread 3", 1);
if(spc1_flush0_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "flush violation thread 0", 1);
if(spc1_flush1_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "flush violation thread 1", 1);
if(spc1_flush2_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "flush violation thread 2", 1);
if(spc1_flush3_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "flush violation thread 3", 1);
if(spc1_intr0_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "intr violation thread 0", 1);
if(spc1_intr1_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "intr violation thread 1", 1);
if(spc1_intr2_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "intr violation thread 2", 1);
if(spc1_intr3_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "intr violation thread 3", 1);
if(~rst_l | ~C1T0_stb_full | sctag_pcx_stall_pq) C1T0_stb_drain_cnt = 0;
else C1T0_stb_drain_cnt = C1T0_stb_drain_cnt + 1;
if(C1T0_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 0 is not draining", 1);
if(~rst_l | ~C1T1_stb_full | sctag_pcx_stall_pq) C1T1_stb_drain_cnt = 0;
else C1T1_stb_drain_cnt = C1T1_stb_drain_cnt + 1;
if(C1T1_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 1 is not draining", 1);
if(~rst_l | ~C1T2_stb_full | sctag_pcx_stall_pq) C1T2_stb_drain_cnt = 0;
else C1T2_stb_drain_cnt = C1T2_stb_drain_cnt + 1;
if(C1T2_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 2 is not draining", 1);
if(~rst_l | ~C1T3_stb_full | sctag_pcx_stall_pq) C1T3_stb_drain_cnt = 0;
else C1T3_stb_drain_cnt = C1T3_stb_drain_cnt + 1;
if(C1T3_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 3 is not draining", 1);
C1T0_stb_vld_sum_d1 <= C1T0_stb_vld_sum;
C1T1_stb_vld_sum_d1 <= C1T1_stb_vld_sum;
C1T2_stb_vld_sum_d1 <= C1T2_stb_vld_sum;
C1T3_stb_vld_sum_d1 <= C1T3_stb_vld_sum;
C1T0_defr_trp_en_d1 <= C1T0_defr_trp_en;
C1T1_defr_trp_en_d1 <= C1T1_defr_trp_en;
C1T2_defr_trp_en_d1 <= C1T2_defr_trp_en;
C1T3_defr_trp_en_d1 <= C1T3_defr_trp_en;
if(rst_l & C1T0_defr_trp_en_d1 & (C1T0_stb_vld_sum_d1 < C1T0_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T0", 1);
if(rst_l & C1T1_defr_trp_en_d1 & (C1T1_stb_vld_sum_d1 < C1T1_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T1", 1);
if(rst_l & C1T2_defr_trp_en_d1 & (C1T2_stb_vld_sum_d1 < C1T2_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T2", 1);
if(rst_l & C1T3_defr_trp_en_d1 & (C1T3_stb_vld_sum_d1 < C1T3_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T3", 1);
end
`endif // ifdef RTL_SPARC1
`ifdef RTL_SPARC2
wire C2T0_stb_ne = |`TOP_DESIGN.sparc2.lsu.stb_ctl0.stb_state_vld[7:0];
wire C2T1_stb_ne = |`TOP_DESIGN.sparc2.lsu.stb_ctl1.stb_state_vld[7:0];
wire C2T2_stb_ne = |`TOP_DESIGN.sparc2.lsu.stb_ctl2.stb_state_vld[7:0];
wire C2T3_stb_ne = |`TOP_DESIGN.sparc2.lsu.stb_ctl3.stb_state_vld[7:0];
wire C2T0_stb_nced = |( `TOP_DESIGN.sparc2.lsu.stb_ctl0.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc2.lsu.stb_ctl0.stb_state_ced[7:0]);
wire C2T1_stb_nced = |( `TOP_DESIGN.sparc2.lsu.stb_ctl1.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc2.lsu.stb_ctl1.stb_state_ced[7:0]);
wire C2T2_stb_nced = |( `TOP_DESIGN.sparc2.lsu.stb_ctl2.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc2.lsu.stb_ctl2.stb_state_ced[7:0]);
wire C2T3_stb_nced = |( `TOP_DESIGN.sparc2.lsu.stb_ctl3.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc2.lsu.stb_ctl3.stb_state_ced[7:0]);
`else
wire C2T0_stb_ne = 1'b0;
wire C2T1_stb_ne = 1'b0;
wire C2T2_stb_ne = 1'b0;
wire C2T3_stb_ne = 1'b0;
wire C2T0_stb_nced = 1'b0;
wire C2T1_stb_nced = 1'b0;
wire C2T2_stb_nced = 1'b0;
wire C2T3_stb_nced = 1'b0;
`endif // ifdef RTL_SPARC2
`ifdef RTL_SPARC2
wire spc2_lsu_ifill_pkt_vld = `TOP_DESIGN.sparc2.lsu.qctl2.lsu_ifill_pkt_vld;
wire spc2_dfq_rd_advance = `TOP_DESIGN.sparc2.lsu.qctl2.dfq_rd_advance;
wire spc2_dfq_int_type = `TOP_DESIGN.sparc2.lsu.qctl2.dfq_int_type;
wire spc2_ifu_lsu_inv_clear = `TOP_DESIGN.sparc2.lsu.qctl2.ifu_lsu_inv_clear;
wire spc2_dva_svld_e = `TOP_DESIGN.sparc2.lsu.qctl2.dva_svld_e;
wire spc2_dva_rvld_e = `TOP_DESIGN.sparc2.lsu.dva.rd_en;
wire [10:4] spc2_dva_rd_addr_e = `TOP_DESIGN.sparc2.lsu.dva.rd_adr1[6:0];
wire [4:0] spc2_dva_snp_addr_e = `TOP_DESIGN.sparc2.lsu.qctl2.dva_snp_addr_e[4:0];
wire [4:0] spc2_stb_data_rd_ptr = `TOP_DESIGN.sparc2.lsu.stb_data_rd_ptr[4:0];
wire [4:0] spc2_stb_data_wr_ptr = `TOP_DESIGN.sparc2.lsu.stb_data_wr_ptr[4:0];
wire spc2_stb_data_wptr_vld = `TOP_DESIGN.sparc2.lsu.stb_data_wptr_vld;
wire spc2_stb_data_rptr_vld = `TOP_DESIGN.sparc2.lsu.stb_data_rptr_vld;
wire spc2_stbrwctl_flush_pipe_w = `TOP_DESIGN.sparc2.lsu.stb_rwctl.lsu_stbrwctl_flush_pipe_w;
wire spc2_lsu_st_pcx_rq_pick = |`TOP_DESIGN.sparc2.lsu.stb_rwctl.lsu_st_pcx_rq_pick[3:0];
wire [3:0] spc2_lsu_rd_dtag_parity_g = `TOP_DESIGN.sparc2.lsu.dctl.lsu_rd_dtag_parity_g[3:0];
wire [3:0] spc2_dva_vld_g = `TOP_DESIGN.sparc2.lsu.dctl.dva_vld_g[3:0];
wire [3:0] spc2_lsu_dc_tag_pe_g_unmasked = spc2_lsu_rd_dtag_parity_g[3:0] & spc2_dva_vld_g[3:0];
wire spc2_lsu_dc_tag_pe_g_unmasked_or = |spc2_lsu_dc_tag_pe_g_unmasked[3:0];
wire C2T0_stb_full = &`TOP_DESIGN.sparc2.lsu.stb_ctl0.stb_state_vld[7:0];
wire C2T1_stb_full = &`TOP_DESIGN.sparc2.lsu.stb_ctl1.stb_state_vld[7:0];
wire C2T2_stb_full = &`TOP_DESIGN.sparc2.lsu.stb_ctl2.stb_state_vld[7:0];
wire C2T3_stb_full = &`TOP_DESIGN.sparc2.lsu.stb_ctl3.stb_state_vld[7:0];
wire [7:0] C2T0_stb_vld = `TOP_DESIGN.sparc2.lsu.stb_ctl0.stb_state_vld[7:0];
wire [7:0] C2T1_stb_vld = `TOP_DESIGN.sparc2.lsu.stb_ctl1.stb_state_vld[7:0];
wire [7:0] C2T2_stb_vld = `TOP_DESIGN.sparc2.lsu.stb_ctl2.stb_state_vld[7:0];
wire [7:0] C2T3_stb_vld = `TOP_DESIGN.sparc2.lsu.stb_ctl3.stb_state_vld[7:0];
wire [4:0] C2T0_stb_vld_sum = C2T0_stb_vld[0] + C2T0_stb_vld[1] + C2T0_stb_vld[2] + C2T0_stb_vld[3] +
C2T0_stb_vld[4] + C2T0_stb_vld[5] + C2T0_stb_vld[6] + C2T0_stb_vld[7] ;
wire [4:0] C2T1_stb_vld_sum = C2T1_stb_vld[0] + C2T1_stb_vld[1] + C2T1_stb_vld[2] + C2T1_stb_vld[3] +
C2T1_stb_vld[4] + C2T1_stb_vld[5] + C2T1_stb_vld[6] + C2T1_stb_vld[7] ;
wire [4:0] C2T2_stb_vld_sum = C2T2_stb_vld[0] + C2T2_stb_vld[1] + C2T2_stb_vld[2] + C2T2_stb_vld[3] +
C2T2_stb_vld[4] + C2T2_stb_vld[5] + C2T2_stb_vld[6] + C2T2_stb_vld[7] ;
wire [4:0] C2T3_stb_vld_sum = C2T3_stb_vld[0] + C2T3_stb_vld[1] + C2T3_stb_vld[2] + C2T3_stb_vld[3] +
C2T3_stb_vld[4] + C2T3_stb_vld[5] + C2T3_stb_vld[6] + C2T3_stb_vld[7] ;
reg [4:0] C2T0_stb_vld_sum_d1;
reg [4:0] C2T1_stb_vld_sum_d1;
reg [4:0] C2T2_stb_vld_sum_d1;
reg [4:0] C2T3_stb_vld_sum_d1;
wire C2T0_st_ack = &`TOP_DESIGN.sparc2.lsu.cpx_st_ack_tid0;
wire C2T1_st_ack = &`TOP_DESIGN.sparc2.lsu.cpx_st_ack_tid1;
wire C2T2_st_ack = &`TOP_DESIGN.sparc2.lsu.cpx_st_ack_tid2;
wire C2T3_st_ack = &`TOP_DESIGN.sparc2.lsu.cpx_st_ack_tid3;
wire C2T0_defr_trp_en = &`TOP_DESIGN.sparc2.lsu.excpctl.st_defr_trp_en0;
wire C2T1_defr_trp_en = &`TOP_DESIGN.sparc2.lsu.excpctl.st_defr_trp_en1;
wire C2T2_defr_trp_en = &`TOP_DESIGN.sparc2.lsu.excpctl.st_defr_trp_en2;
wire C2T3_defr_trp_en = &`TOP_DESIGN.sparc2.lsu.excpctl.st_defr_trp_en3;
reg C2T0_defr_trp_en_d1;
reg C2T1_defr_trp_en_d1;
reg C2T2_defr_trp_en_d1;
reg C2T3_defr_trp_en_d1;
integer C2T0_stb_drain_cnt;
integer C2T1_stb_drain_cnt;
integer C2T2_stb_drain_cnt;
integer C2T3_stb_drain_cnt;
// Hits in the store buffer
//-------------------------
wire spc2_inst_vld_w = `TOP_DESIGN.sparc2.ifu.fcl.inst_vld_w;
wire [1:0] spc2_sas_thrid_w = `TOP_DESIGN.sparc2.ifu.fcl.sas_thrid_w[1:0];
wire C2_st_ack_w = (spc2_sas_thrid_w == 2'b00) & C2T0_st_ack |
(spc2_sas_thrid_w == 2'b01) & C2T1_st_ack |
(spc2_sas_thrid_w == 2'b10) & C2T2_st_ack |
(spc2_sas_thrid_w == 2'b11) & C2T3_st_ack;
wire [7:0] spc2_stb_ld_full_raw = `TOP_DESIGN.sparc2.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc2_stb_ld_partial_raw = `TOP_DESIGN.sparc2.lsu.stb_ld_partial_raw[7:0];
wire spc2_stb_cam_mhit = `TOP_DESIGN.sparc2.lsu.stb_cam_mhit;
wire spc2_stb_cam_hit = `TOP_DESIGN.sparc2.lsu.stb_cam_hit;
wire [3:0] spc2_lsu_way_hit = `TOP_DESIGN.sparc2.lsu.dctl.lsu_way_hit[3:0];
wire spc2_lsu_ifu_ldst_miss_w = `TOP_DESIGN.sparc2.lsu.lsu_ifu_ldst_miss_w;
wire spc2_ld_inst_vld_g = `TOP_DESIGN.sparc2.lsu.dctl.ld_inst_vld_g;
wire spc2_ldst_dbl_g = `TOP_DESIGN.sparc2.lsu.dctl.ldst_dbl_g;
wire spc2_quad_asi_g = `TOP_DESIGN.sparc2.lsu.dctl.quad_asi_g;
wire [1:0] spc2_ldst_sz_g = `TOP_DESIGN.sparc2.lsu.dctl.ldst_sz_g;
wire spc2_lsu_alt_space_g = `TOP_DESIGN.sparc2.lsu.dctl.lsu_alt_space_g;
wire spc2_mbar_inst0_g = `TOP_DESIGN.sparc2.lsu.dctl.mbar_inst0_g;
wire spc2_mbar_inst1_g = `TOP_DESIGN.sparc2.lsu.dctl.mbar_inst1_g;
wire spc2_mbar_inst2_g = `TOP_DESIGN.sparc2.lsu.dctl.mbar_inst2_g;
wire spc2_mbar_inst3_g = `TOP_DESIGN.sparc2.lsu.dctl.mbar_inst3_g;
wire spc2_flush_inst0_g = `TOP_DESIGN.sparc2.lsu.dctl.flush_inst0_g;
wire spc2_flush_inst1_g = `TOP_DESIGN.sparc2.lsu.dctl.flush_inst1_g;
wire spc2_flush_inst2_g = `TOP_DESIGN.sparc2.lsu.dctl.flush_inst2_g;
wire spc2_flush_inst3_g = `TOP_DESIGN.sparc2.lsu.dctl.flush_inst3_g;
wire spc2_intrpt_disp_asi0_g = `TOP_DESIGN.sparc2.lsu.dctl.intrpt_disp_asi_g & (spc2_sas_thrid_w == 2'b00);
wire spc2_intrpt_disp_asi1_g = `TOP_DESIGN.sparc2.lsu.dctl.intrpt_disp_asi_g & (spc2_sas_thrid_w == 2'b01);
wire spc2_intrpt_disp_asi2_g = `TOP_DESIGN.sparc2.lsu.dctl.intrpt_disp_asi_g & (spc2_sas_thrid_w == 2'b10);
wire spc2_intrpt_disp_asi3_g = `TOP_DESIGN.sparc2.lsu.dctl.intrpt_disp_asi_g & (spc2_sas_thrid_w == 2'b11);
wire spc2_st_inst_vld_g = `TOP_DESIGN.sparc2.lsu.dctl.st_inst_vld_g;
wire spc2_non_altspace_ldst_g = `TOP_DESIGN.sparc2.lsu.dctl.non_altspace_ldst_g;
wire spc2_dctl_flush_pipe_w = `TOP_DESIGN.sparc2.lsu.dctl.dctl_flush_pipe_w;
wire [3:0] spc2_no_spc_rmo_st = `TOP_DESIGN.sparc2.lsu.dctl.no_spc_rmo_st[3:0];
wire spc2_ldst_fp_e = `TOP_DESIGN.sparc2.lsu.ifu_lsu_ldst_fp_e;
wire [2:0] spc2_stb_rdptr = `TOP_DESIGN.sparc2.lsu.stb_rwctl.stb_rdptr_l;
wire spc2_ld_l2cache_req = `TOP_DESIGN.sparc2.lsu.qctl1.ld3_l2cache_rq |
`TOP_DESIGN.sparc2.lsu.qctl1.ld2_l2cache_rq |
`TOP_DESIGN.sparc2.lsu.qctl1.ld1_l2cache_rq |
`TOP_DESIGN.sparc2.lsu.qctl1.ld0_l2cache_rq;
wire [3:0] spc2_dcache_enable = {`TOP_DESIGN.sparc2.lsu.dctl.lsu_ctl_reg0[1],
`TOP_DESIGN.sparc2.lsu.dctl.lsu_ctl_reg1[1],
`TOP_DESIGN.sparc2.lsu.dctl.lsu_ctl_reg2[1],
`TOP_DESIGN.sparc2.lsu.dctl.lsu_ctl_reg3[1]};
wire [3:0] spc2_icache_enable = `TOP_DESIGN.sparc2.lsu.lsu_ifu_icache_en[3:0];
wire spc2_dc_direct_map = `TOP_DESIGN.sparc2.lsu.dc_direct_map;
wire spc2_lsu_ifu_direct_map_l1 = `TOP_DESIGN.sparc2.lsu.lsu_ifu_direct_map_l1;
always @(spc2_dcache_enable)
$display("%0d tso_mon: spc2_dcache_enable changed to %x", $time, spc2_dcache_enable);
always @(spc2_icache_enable)
$display("%0d tso_mon: spc2_icache_enable changed to %x", $time, spc2_icache_enable);
always @(spc2_dc_direct_map)
$display("%0d tso_mon: spc2_dc_direct_map changed to %x", $time, spc2_dc_direct_map);
always @(spc2_lsu_ifu_direct_map_l1)
$display("%0d tso_mon: spc2_lsu_ifu_direct_map_l1 changed to %x", $time, spc2_lsu_ifu_direct_map_l1);
reg spc2_dva_svld_e_d1;
reg spc2_dva_rvld_e_d1;
reg [10:4] spc2_dva_rd_addr_e_d1;
reg [4:0] spc2_dva_snp_addr_e_d1;
reg spc2_lsu_snp_after_rd;
reg spc2_lsu_rd_after_snp;
reg spc2_ldst_fp_m, spc2_ldst_fp_g;
integer spc2_multiple_hits;
reg spc2_skid_d1, spc2_skid_d2, spc2_skid_d3;
initial begin
spc2_skid_d1 = 0;
spc2_skid_d2 = 0;
spc2_skid_d3 = 0;
end
always @(posedge clk)
begin
spc2_skid_d1 <= (~spc2_ifu_lsu_inv_clear & spc2_dfq_rd_advance & spc2_dfq_int_type);
spc2_skid_d2 <= spc2_skid_d1 & ~spc2_ifu_lsu_inv_clear;
spc2_skid_d3 <= spc2_skid_d2 & ~spc2_ifu_lsu_inv_clear;
// The full tracking of this condition is complicated since after the interrupt is advanced
// there may be more invalidations to the IFQ.
// All we care about is that the invalidations BEFORE the interrupt are finished.
// I provided a command line argument to disable this check.
if(spc2_skid_d3 & enable_ifu_lsu_inv_clear)
finish_test("spc", "tso_mon: spc2_ifu_lsu_inv_clear should have been clear by now", 2);
spc2_dva_svld_e_d1 <= spc2_dva_svld_e;
spc2_dva_rvld_e_d1 <= spc2_dva_rvld_e;
spc2_dva_rd_addr_e_d1 <= spc2_dva_rd_addr_e;
spc2_dva_snp_addr_e_d1 <= spc2_dva_snp_addr_e;
if(spc2_dva_svld_e_d1 & spc2_dva_rvld_e & (spc2_dva_rd_addr_e_d1[10:6] == spc2_dva_snp_addr_e[4:0]))
spc2_lsu_rd_after_snp <= 1'b1;
else
spc2_lsu_rd_after_snp <= 1'b0;
if(spc2_dva_svld_e & spc2_dva_rvld_e_d1 & (spc2_dva_rd_addr_e[10:6] == spc2_dva_snp_addr_e_d1[4:0]))
spc2_lsu_snp_after_rd <= 1'b1;
else
spc2_lsu_snp_after_rd <= 1'b0;
spc2_ldst_fp_m <= spc2_ldst_fp_e;
spc2_ldst_fp_g <= spc2_ldst_fp_m;
if(spc2_stb_data_rptr_vld & spc2_stb_data_wptr_vld & ~spc2_stbrwctl_flush_pipe_w &
(spc2_stb_data_rd_ptr == spc2_stb_data_wr_ptr) & spc2_lsu_st_pcx_rq_pick)
begin
finish_test("spc", "tso_mon: LSU stb data write and read in the same cycle", 2);
end
spc2_multiple_hits = (spc2_lsu_way_hit[3] + spc2_lsu_way_hit[2] + spc2_lsu_way_hit[1] + spc2_lsu_way_hit[0]);
if(!spc2_lsu_ifu_ldst_miss_w && (spc2_multiple_hits >1) && spc2_inst_vld_w && !spc2_dctl_flush_pipe_w && !spc2_lsu_dc_tag_pe_g_unmasked_or)
finish_test("spc", "tso_mon: LSU multiple hits ", 2);
end
wire spc2_ld_dbl = spc2_ld_inst_vld_g & spc2_ldst_dbl_g & ~spc2_quad_asi_g;
wire spc2_ld_quad = spc2_ld_inst_vld_g & spc2_ldst_dbl_g & spc2_quad_asi_g;
wire spc2_ld_other = spc2_ld_inst_vld_g & ~spc2_ldst_dbl_g;
wire spc2_ld_dbl_fp = spc2_ld_dbl & spc2_ldst_fp_g;
wire spc2_ld_other_fp = spc2_ld_other & spc2_ldst_fp_g;
wire spc2_ld_dbl_int = spc2_ld_dbl & ~spc2_ldst_fp_g;
wire spc2_ld_quad_int = spc2_ld_quad & ~spc2_ldst_fp_g;
wire spc2_ld_other_int= spc2_ld_other & ~spc2_ldst_fp_g;
wire spc2_ld_bypassok_hit = |spc2_stb_ld_full_raw[7:0] & ~spc2_stb_cam_mhit;
wire spc2_ld_partial_hit = |spc2_stb_ld_partial_raw[7:0] & ~spc2_stb_cam_mhit;
wire spc2_ld_multiple_hit = spc2_stb_cam_mhit;
wire spc2_any_lsu_way_hit = |spc2_lsu_way_hit;
wire [7:0] spc2_stb_rdptr_decoded = (spc2_stb_rdptr ==3'b000) ? 8'b00000001 :
(spc2_stb_rdptr ==3'b001) ? 8'b00000010 :
(spc2_stb_rdptr ==3'b010) ? 8'b00000100 :
(spc2_stb_rdptr ==3'b011) ? 8'b00001000 :
(spc2_stb_rdptr ==3'b100) ? 8'b00010000 :
(spc2_stb_rdptr ==3'b101) ? 8'b00100000 :
(spc2_stb_rdptr ==3'b110) ? 8'b01000000 :
(spc2_stb_rdptr ==3'b111) ? 8'b10000000 : 8'h00;
wire spc2_stb_top_hit = |(spc2_stb_rdptr_decoded & (spc2_stb_ld_full_raw | spc2_stb_ld_partial_raw));
//---------------------------------------------------------------------
// ld_type[4:0] hit_type[2:0], cache_hit, hit_top
// this is passed to the coverage monitor.
//---------------------------------------------------------------------
wire [10:0] spc2_stb_ld_hit_info =
{spc2_ld_dbl_fp, spc2_ld_other_fp,
spc2_ld_dbl_int, spc2_ld_quad_int, spc2_ld_other_int,
spc2_ld_bypassok_hit, spc2_ld_partial_hit, spc2_ld_multiple_hit,
spc2_any_lsu_way_hit,
spc2_stb_top_hit, C2_st_ack_w};
reg spc2_mbar0_active;
reg spc2_mbar1_active;
reg spc2_mbar2_active;
reg spc2_mbar3_active;
reg spc2_flush0_active;
reg spc2_flush1_active;
reg spc2_flush2_active;
reg spc2_flush3_active;
reg spc2_intr0_active;
reg spc2_intr1_active;
reg spc2_intr2_active;
reg spc2_intr3_active;
always @(negedge clk)
begin
if(~rst_l)
begin
spc2_mbar0_active <= 1'b0;
spc2_mbar1_active <= 1'b0;
spc2_mbar2_active <= 1'b0;
spc2_mbar3_active <= 1'b0;
spc2_flush0_active <= 1'b0;
spc2_flush1_active <= 1'b0;
spc2_flush2_active <= 1'b0;
spc2_flush3_active <= 1'b0;
spc2_intr0_active <= 1'b0;
spc2_intr1_active <= 1'b0;
spc2_intr2_active <= 1'b0;
spc2_intr3_active <= 1'b0;
end
else
begin
if(spc2_mbar_inst0_g & ~spc2_dctl_flush_pipe_w & (C2T0_stb_ne|~spc2_no_spc_rmo_st[0]))
spc2_mbar0_active <= 1'b1;
else if(~C2T0_stb_ne & spc2_no_spc_rmo_st[0])
spc2_mbar0_active <= 1'b0;
if(spc2_mbar_inst1_g & ~ spc2_dctl_flush_pipe_w & (C2T1_stb_ne|~spc2_no_spc_rmo_st[1]))
spc2_mbar1_active <= 1'b1;
else if(~C2T1_stb_ne & spc2_no_spc_rmo_st[1])
spc2_mbar1_active <= 1'b0;
if(spc2_mbar_inst2_g & ~ spc2_dctl_flush_pipe_w & (C2T2_stb_ne|~spc2_no_spc_rmo_st[2]))
spc2_mbar2_active <= 1'b1;
else if(~C2T2_stb_ne & spc2_no_spc_rmo_st[2])
spc2_mbar2_active <= 1'b0;
if(spc2_mbar_inst3_g & ~ spc2_dctl_flush_pipe_w & (C2T3_stb_ne|~spc2_no_spc_rmo_st[3]))
spc2_mbar3_active <= 1'b1;
else if(~C2T3_stb_ne & spc2_no_spc_rmo_st[3])
spc2_mbar3_active <= 1'b0;
if(spc2_flush_inst0_g & ~spc2_dctl_flush_pipe_w & C2T0_stb_ne) spc2_flush0_active <= 1'b1;
else if(~C2T0_stb_ne) spc2_flush0_active <= 1'b0;
if(spc2_flush_inst1_g & ~spc2_dctl_flush_pipe_w & C2T1_stb_ne) spc2_flush1_active <= 1'b1;
else if(~C2T1_stb_ne) spc2_flush1_active <= 1'b0;
if(spc2_flush_inst2_g & ~spc2_dctl_flush_pipe_w & C2T2_stb_ne) spc2_flush2_active <= 1'b1;
else if(~C2T2_stb_ne) spc2_flush2_active <= 1'b0;
if(spc2_flush_inst3_g & ~spc2_dctl_flush_pipe_w & C2T3_stb_ne) spc2_flush3_active <= 1'b1;
else if(~C2T3_stb_ne) spc2_flush3_active <= 1'b0;
if(spc2_intrpt_disp_asi0_g & spc2_st_inst_vld_g & ~spc2_non_altspace_ldst_g & ~spc2_dctl_flush_pipe_w & C2T0_stb_ne)
spc2_intr0_active <= 1'b1;
else if(~C2T0_stb_ne)
spc2_intr0_active <= 1'b0;
if(spc2_intrpt_disp_asi1_g & spc2_st_inst_vld_g & ~spc2_non_altspace_ldst_g & ~spc2_dctl_flush_pipe_w & C2T1_stb_ne)
spc2_intr1_active <= 1'b1;
else if(~C2T1_stb_ne)
spc2_intr1_active <= 1'b0;
if(spc2_intrpt_disp_asi2_g & spc2_st_inst_vld_g & ~spc2_non_altspace_ldst_g & ~spc2_dctl_flush_pipe_w & C2T2_stb_ne)
spc2_intr2_active <= 1'b1;
else if(~C2T2_stb_ne)
spc2_intr2_active <= 1'b0;
if(spc2_intrpt_disp_asi3_g & spc2_st_inst_vld_g & ~spc2_non_altspace_ldst_g & ~spc2_dctl_flush_pipe_w & C2T3_stb_ne)
spc2_intr3_active <= 1'b1;
else if(~C2T3_stb_ne)
spc2_intr3_active <= 1'b0;
end
if(spc2_mbar0_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "membar violation thread 0", 2);
if(spc2_mbar1_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "membar violation thread 1", 2);
if(spc2_mbar2_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "membar violation thread 2", 2);
if(spc2_mbar3_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "membar violation thread 3", 2);
if(spc2_flush0_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "flush violation thread 0", 2);
if(spc2_flush1_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "flush violation thread 1", 2);
if(spc2_flush2_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "flush violation thread 2", 2);
if(spc2_flush3_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "flush violation thread 3", 2);
if(spc2_intr0_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "intr violation thread 0", 2);
if(spc2_intr1_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "intr violation thread 1", 2);
if(spc2_intr2_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "intr violation thread 2", 2);
if(spc2_intr3_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "intr violation thread 3", 2);
if(~rst_l | ~C2T0_stb_full | sctag_pcx_stall_pq) C2T0_stb_drain_cnt = 0;
else C2T0_stb_drain_cnt = C2T0_stb_drain_cnt + 1;
if(C2T0_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 0 is not draining", 2);
if(~rst_l | ~C2T1_stb_full | sctag_pcx_stall_pq) C2T1_stb_drain_cnt = 0;
else C2T1_stb_drain_cnt = C2T1_stb_drain_cnt + 1;
if(C2T1_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 1 is not draining", 2);
if(~rst_l | ~C2T2_stb_full | sctag_pcx_stall_pq) C2T2_stb_drain_cnt = 0;
else C2T2_stb_drain_cnt = C2T2_stb_drain_cnt + 1;
if(C2T2_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 2 is not draining", 2);
if(~rst_l | ~C2T3_stb_full | sctag_pcx_stall_pq) C2T3_stb_drain_cnt = 0;
else C2T3_stb_drain_cnt = C2T3_stb_drain_cnt + 1;
if(C2T3_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 3 is not draining", 2);
C2T0_stb_vld_sum_d1 <= C2T0_stb_vld_sum;
C2T1_stb_vld_sum_d1 <= C2T1_stb_vld_sum;
C2T2_stb_vld_sum_d1 <= C2T2_stb_vld_sum;
C2T3_stb_vld_sum_d1 <= C2T3_stb_vld_sum;
C2T0_defr_trp_en_d1 <= C2T0_defr_trp_en;
C2T1_defr_trp_en_d1 <= C2T1_defr_trp_en;
C2T2_defr_trp_en_d1 <= C2T2_defr_trp_en;
C2T3_defr_trp_en_d1 <= C2T3_defr_trp_en;
if(rst_l & C2T0_defr_trp_en_d1 & (C2T0_stb_vld_sum_d1 < C2T0_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T0", 2);
if(rst_l & C2T1_defr_trp_en_d1 & (C2T1_stb_vld_sum_d1 < C2T1_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T1", 2);
if(rst_l & C2T2_defr_trp_en_d1 & (C2T2_stb_vld_sum_d1 < C2T2_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T2", 2);
if(rst_l & C2T3_defr_trp_en_d1 & (C2T3_stb_vld_sum_d1 < C2T3_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T3", 2);
end
`endif // ifdef RTL_SPARC2
`ifdef RTL_SPARC3
wire C3T0_stb_ne = |`TOP_DESIGN.sparc3.lsu.stb_ctl0.stb_state_vld[7:0];
wire C3T1_stb_ne = |`TOP_DESIGN.sparc3.lsu.stb_ctl1.stb_state_vld[7:0];
wire C3T2_stb_ne = |`TOP_DESIGN.sparc3.lsu.stb_ctl2.stb_state_vld[7:0];
wire C3T3_stb_ne = |`TOP_DESIGN.sparc3.lsu.stb_ctl3.stb_state_vld[7:0];
wire C3T0_stb_nced = |( `TOP_DESIGN.sparc3.lsu.stb_ctl0.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc3.lsu.stb_ctl0.stb_state_ced[7:0]);
wire C3T1_stb_nced = |( `TOP_DESIGN.sparc3.lsu.stb_ctl1.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc3.lsu.stb_ctl1.stb_state_ced[7:0]);
wire C3T2_stb_nced = |( `TOP_DESIGN.sparc3.lsu.stb_ctl2.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc3.lsu.stb_ctl2.stb_state_ced[7:0]);
wire C3T3_stb_nced = |( `TOP_DESIGN.sparc3.lsu.stb_ctl3.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc3.lsu.stb_ctl3.stb_state_ced[7:0]);
`else
wire C3T0_stb_ne = 1'b0;
wire C3T1_stb_ne = 1'b0;
wire C3T2_stb_ne = 1'b0;
wire C3T3_stb_ne = 1'b0;
wire C3T0_stb_nced = 1'b0;
wire C3T1_stb_nced = 1'b0;
wire C3T2_stb_nced = 1'b0;
wire C3T3_stb_nced = 1'b0;
`endif // ifdef RTL_SPARC3
`ifdef RTL_SPARC3
wire spc3_lsu_ifill_pkt_vld = `TOP_DESIGN.sparc3.lsu.qctl2.lsu_ifill_pkt_vld;
wire spc3_dfq_rd_advance = `TOP_DESIGN.sparc3.lsu.qctl2.dfq_rd_advance;
wire spc3_dfq_int_type = `TOP_DESIGN.sparc3.lsu.qctl2.dfq_int_type;
wire spc3_ifu_lsu_inv_clear = `TOP_DESIGN.sparc3.lsu.qctl2.ifu_lsu_inv_clear;
wire spc3_dva_svld_e = `TOP_DESIGN.sparc3.lsu.qctl2.dva_svld_e;
wire spc3_dva_rvld_e = `TOP_DESIGN.sparc3.lsu.dva.rd_en;
wire [10:4] spc3_dva_rd_addr_e = `TOP_DESIGN.sparc3.lsu.dva.rd_adr1[6:0];
wire [4:0] spc3_dva_snp_addr_e = `TOP_DESIGN.sparc3.lsu.qctl2.dva_snp_addr_e[4:0];
wire [4:0] spc3_stb_data_rd_ptr = `TOP_DESIGN.sparc3.lsu.stb_data_rd_ptr[4:0];
wire [4:0] spc3_stb_data_wr_ptr = `TOP_DESIGN.sparc3.lsu.stb_data_wr_ptr[4:0];
wire spc3_stb_data_wptr_vld = `TOP_DESIGN.sparc3.lsu.stb_data_wptr_vld;
wire spc3_stb_data_rptr_vld = `TOP_DESIGN.sparc3.lsu.stb_data_rptr_vld;
wire spc3_stbrwctl_flush_pipe_w = `TOP_DESIGN.sparc3.lsu.stb_rwctl.lsu_stbrwctl_flush_pipe_w;
wire spc3_lsu_st_pcx_rq_pick = |`TOP_DESIGN.sparc3.lsu.stb_rwctl.lsu_st_pcx_rq_pick[3:0];
wire [3:0] spc3_lsu_rd_dtag_parity_g = `TOP_DESIGN.sparc3.lsu.dctl.lsu_rd_dtag_parity_g[3:0];
wire [3:0] spc3_dva_vld_g = `TOP_DESIGN.sparc3.lsu.dctl.dva_vld_g[3:0];
wire [3:0] spc3_lsu_dc_tag_pe_g_unmasked = spc3_lsu_rd_dtag_parity_g[3:0] & spc3_dva_vld_g[3:0];
wire spc3_lsu_dc_tag_pe_g_unmasked_or = |spc3_lsu_dc_tag_pe_g_unmasked[3:0];
wire C3T0_stb_full = &`TOP_DESIGN.sparc3.lsu.stb_ctl0.stb_state_vld[7:0];
wire C3T1_stb_full = &`TOP_DESIGN.sparc3.lsu.stb_ctl1.stb_state_vld[7:0];
wire C3T2_stb_full = &`TOP_DESIGN.sparc3.lsu.stb_ctl2.stb_state_vld[7:0];
wire C3T3_stb_full = &`TOP_DESIGN.sparc3.lsu.stb_ctl3.stb_state_vld[7:0];
wire [7:0] C3T0_stb_vld = `TOP_DESIGN.sparc3.lsu.stb_ctl0.stb_state_vld[7:0];
wire [7:0] C3T1_stb_vld = `TOP_DESIGN.sparc3.lsu.stb_ctl1.stb_state_vld[7:0];
wire [7:0] C3T2_stb_vld = `TOP_DESIGN.sparc3.lsu.stb_ctl2.stb_state_vld[7:0];
wire [7:0] C3T3_stb_vld = `TOP_DESIGN.sparc3.lsu.stb_ctl3.stb_state_vld[7:0];
wire [4:0] C3T0_stb_vld_sum = C3T0_stb_vld[0] + C3T0_stb_vld[1] + C3T0_stb_vld[2] + C3T0_stb_vld[3] +
C3T0_stb_vld[4] + C3T0_stb_vld[5] + C3T0_stb_vld[6] + C3T0_stb_vld[7] ;
wire [4:0] C3T1_stb_vld_sum = C3T1_stb_vld[0] + C3T1_stb_vld[1] + C3T1_stb_vld[2] + C3T1_stb_vld[3] +
C3T1_stb_vld[4] + C3T1_stb_vld[5] + C3T1_stb_vld[6] + C3T1_stb_vld[7] ;
wire [4:0] C3T2_stb_vld_sum = C3T2_stb_vld[0] + C3T2_stb_vld[1] + C3T2_stb_vld[2] + C3T2_stb_vld[3] +
C3T2_stb_vld[4] + C3T2_stb_vld[5] + C3T2_stb_vld[6] + C3T2_stb_vld[7] ;
wire [4:0] C3T3_stb_vld_sum = C3T3_stb_vld[0] + C3T3_stb_vld[1] + C3T3_stb_vld[2] + C3T3_stb_vld[3] +
C3T3_stb_vld[4] + C3T3_stb_vld[5] + C3T3_stb_vld[6] + C3T3_stb_vld[7] ;
reg [4:0] C3T0_stb_vld_sum_d1;
reg [4:0] C3T1_stb_vld_sum_d1;
reg [4:0] C3T2_stb_vld_sum_d1;
reg [4:0] C3T3_stb_vld_sum_d1;
wire C3T0_st_ack = &`TOP_DESIGN.sparc3.lsu.cpx_st_ack_tid0;
wire C3T1_st_ack = &`TOP_DESIGN.sparc3.lsu.cpx_st_ack_tid1;
wire C3T2_st_ack = &`TOP_DESIGN.sparc3.lsu.cpx_st_ack_tid2;
wire C3T3_st_ack = &`TOP_DESIGN.sparc3.lsu.cpx_st_ack_tid3;
wire C3T0_defr_trp_en = &`TOP_DESIGN.sparc3.lsu.excpctl.st_defr_trp_en0;
wire C3T1_defr_trp_en = &`TOP_DESIGN.sparc3.lsu.excpctl.st_defr_trp_en1;
wire C3T2_defr_trp_en = &`TOP_DESIGN.sparc3.lsu.excpctl.st_defr_trp_en2;
wire C3T3_defr_trp_en = &`TOP_DESIGN.sparc3.lsu.excpctl.st_defr_trp_en3;
reg C3T0_defr_trp_en_d1;
reg C3T1_defr_trp_en_d1;
reg C3T2_defr_trp_en_d1;
reg C3T3_defr_trp_en_d1;
integer C3T0_stb_drain_cnt;
integer C3T1_stb_drain_cnt;
integer C3T2_stb_drain_cnt;
integer C3T3_stb_drain_cnt;
// Hits in the store buffer
//-------------------------
wire spc3_inst_vld_w = `TOP_DESIGN.sparc3.ifu.fcl.inst_vld_w;
wire [1:0] spc3_sas_thrid_w = `TOP_DESIGN.sparc3.ifu.fcl.sas_thrid_w[1:0];
wire C3_st_ack_w = (spc3_sas_thrid_w == 2'b00) & C3T0_st_ack |
(spc3_sas_thrid_w == 2'b01) & C3T1_st_ack |
(spc3_sas_thrid_w == 2'b10) & C3T2_st_ack |
(spc3_sas_thrid_w == 2'b11) & C3T3_st_ack;
wire [7:0] spc3_stb_ld_full_raw = `TOP_DESIGN.sparc3.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc3_stb_ld_partial_raw = `TOP_DESIGN.sparc3.lsu.stb_ld_partial_raw[7:0];
wire spc3_stb_cam_mhit = `TOP_DESIGN.sparc3.lsu.stb_cam_mhit;
wire spc3_stb_cam_hit = `TOP_DESIGN.sparc3.lsu.stb_cam_hit;
wire [3:0] spc3_lsu_way_hit = `TOP_DESIGN.sparc3.lsu.dctl.lsu_way_hit[3:0];
wire spc3_lsu_ifu_ldst_miss_w = `TOP_DESIGN.sparc3.lsu.lsu_ifu_ldst_miss_w;
wire spc3_ld_inst_vld_g = `TOP_DESIGN.sparc3.lsu.dctl.ld_inst_vld_g;
wire spc3_ldst_dbl_g = `TOP_DESIGN.sparc3.lsu.dctl.ldst_dbl_g;
wire spc3_quad_asi_g = `TOP_DESIGN.sparc3.lsu.dctl.quad_asi_g;
wire [1:0] spc3_ldst_sz_g = `TOP_DESIGN.sparc3.lsu.dctl.ldst_sz_g;
wire spc3_lsu_alt_space_g = `TOP_DESIGN.sparc3.lsu.dctl.lsu_alt_space_g;
wire spc3_mbar_inst0_g = `TOP_DESIGN.sparc3.lsu.dctl.mbar_inst0_g;
wire spc3_mbar_inst1_g = `TOP_DESIGN.sparc3.lsu.dctl.mbar_inst1_g;
wire spc3_mbar_inst2_g = `TOP_DESIGN.sparc3.lsu.dctl.mbar_inst2_g;
wire spc3_mbar_inst3_g = `TOP_DESIGN.sparc3.lsu.dctl.mbar_inst3_g;
wire spc3_flush_inst0_g = `TOP_DESIGN.sparc3.lsu.dctl.flush_inst0_g;
wire spc3_flush_inst1_g = `TOP_DESIGN.sparc3.lsu.dctl.flush_inst1_g;
wire spc3_flush_inst2_g = `TOP_DESIGN.sparc3.lsu.dctl.flush_inst2_g;
wire spc3_flush_inst3_g = `TOP_DESIGN.sparc3.lsu.dctl.flush_inst3_g;
wire spc3_intrpt_disp_asi0_g = `TOP_DESIGN.sparc3.lsu.dctl.intrpt_disp_asi_g & (spc3_sas_thrid_w == 2'b00);
wire spc3_intrpt_disp_asi1_g = `TOP_DESIGN.sparc3.lsu.dctl.intrpt_disp_asi_g & (spc3_sas_thrid_w == 2'b01);
wire spc3_intrpt_disp_asi2_g = `TOP_DESIGN.sparc3.lsu.dctl.intrpt_disp_asi_g & (spc3_sas_thrid_w == 2'b10);
wire spc3_intrpt_disp_asi3_g = `TOP_DESIGN.sparc3.lsu.dctl.intrpt_disp_asi_g & (spc3_sas_thrid_w == 2'b11);
wire spc3_st_inst_vld_g = `TOP_DESIGN.sparc3.lsu.dctl.st_inst_vld_g;
wire spc3_non_altspace_ldst_g = `TOP_DESIGN.sparc3.lsu.dctl.non_altspace_ldst_g;
wire spc3_dctl_flush_pipe_w = `TOP_DESIGN.sparc3.lsu.dctl.dctl_flush_pipe_w;
wire [3:0] spc3_no_spc_rmo_st = `TOP_DESIGN.sparc3.lsu.dctl.no_spc_rmo_st[3:0];
wire spc3_ldst_fp_e = `TOP_DESIGN.sparc3.lsu.ifu_lsu_ldst_fp_e;
wire [2:0] spc3_stb_rdptr = `TOP_DESIGN.sparc3.lsu.stb_rwctl.stb_rdptr_l;
wire spc3_ld_l2cache_req = `TOP_DESIGN.sparc3.lsu.qctl1.ld3_l2cache_rq |
`TOP_DESIGN.sparc3.lsu.qctl1.ld2_l2cache_rq |
`TOP_DESIGN.sparc3.lsu.qctl1.ld1_l2cache_rq |
`TOP_DESIGN.sparc3.lsu.qctl1.ld0_l2cache_rq;
wire [3:0] spc3_dcache_enable = {`TOP_DESIGN.sparc3.lsu.dctl.lsu_ctl_reg0[1],
`TOP_DESIGN.sparc3.lsu.dctl.lsu_ctl_reg1[1],
`TOP_DESIGN.sparc3.lsu.dctl.lsu_ctl_reg2[1],
`TOP_DESIGN.sparc3.lsu.dctl.lsu_ctl_reg3[1]};
wire [3:0] spc3_icache_enable = `TOP_DESIGN.sparc3.lsu.lsu_ifu_icache_en[3:0];
wire spc3_dc_direct_map = `TOP_DESIGN.sparc3.lsu.dc_direct_map;
wire spc3_lsu_ifu_direct_map_l1 = `TOP_DESIGN.sparc3.lsu.lsu_ifu_direct_map_l1;
always @(spc3_dcache_enable)
$display("%0d tso_mon: spc3_dcache_enable changed to %x", $time, spc3_dcache_enable);
always @(spc3_icache_enable)
$display("%0d tso_mon: spc3_icache_enable changed to %x", $time, spc3_icache_enable);
always @(spc3_dc_direct_map)
$display("%0d tso_mon: spc3_dc_direct_map changed to %x", $time, spc3_dc_direct_map);
always @(spc3_lsu_ifu_direct_map_l1)
$display("%0d tso_mon: spc3_lsu_ifu_direct_map_l1 changed to %x", $time, spc3_lsu_ifu_direct_map_l1);
reg spc3_dva_svld_e_d1;
reg spc3_dva_rvld_e_d1;
reg [10:4] spc3_dva_rd_addr_e_d1;
reg [4:0] spc3_dva_snp_addr_e_d1;
reg spc3_lsu_snp_after_rd;
reg spc3_lsu_rd_after_snp;
reg spc3_ldst_fp_m, spc3_ldst_fp_g;
integer spc3_multiple_hits;
reg spc3_skid_d1, spc3_skid_d2, spc3_skid_d3;
initial begin
spc3_skid_d1 = 0;
spc3_skid_d2 = 0;
spc3_skid_d3 = 0;
end
always @(posedge clk)
begin
spc3_skid_d1 <= (~spc3_ifu_lsu_inv_clear & spc3_dfq_rd_advance & spc3_dfq_int_type);
spc3_skid_d2 <= spc3_skid_d1 & ~spc3_ifu_lsu_inv_clear;
spc3_skid_d3 <= spc3_skid_d2 & ~spc3_ifu_lsu_inv_clear;
// The full tracking of this condition is complicated since after the interrupt is advanced
// there may be more invalidations to the IFQ.
// All we care about is that the invalidations BEFORE the interrupt are finished.
// I provided a command line argument to disable this check.
if(spc3_skid_d3 & enable_ifu_lsu_inv_clear)
finish_test("spc", "tso_mon: spc3_ifu_lsu_inv_clear should have been clear by now", 3);
spc3_dva_svld_e_d1 <= spc3_dva_svld_e;
spc3_dva_rvld_e_d1 <= spc3_dva_rvld_e;
spc3_dva_rd_addr_e_d1 <= spc3_dva_rd_addr_e;
spc3_dva_snp_addr_e_d1 <= spc3_dva_snp_addr_e;
if(spc3_dva_svld_e_d1 & spc3_dva_rvld_e & (spc3_dva_rd_addr_e_d1[10:6] == spc3_dva_snp_addr_e[4:0]))
spc3_lsu_rd_after_snp <= 1'b1;
else
spc3_lsu_rd_after_snp <= 1'b0;
if(spc3_dva_svld_e & spc3_dva_rvld_e_d1 & (spc3_dva_rd_addr_e[10:6] == spc3_dva_snp_addr_e_d1[4:0]))
spc3_lsu_snp_after_rd <= 1'b1;
else
spc3_lsu_snp_after_rd <= 1'b0;
spc3_ldst_fp_m <= spc3_ldst_fp_e;
spc3_ldst_fp_g <= spc3_ldst_fp_m;
if(spc3_stb_data_rptr_vld & spc3_stb_data_wptr_vld & ~spc3_stbrwctl_flush_pipe_w &
(spc3_stb_data_rd_ptr == spc3_stb_data_wr_ptr) & spc3_lsu_st_pcx_rq_pick)
begin
finish_test("spc", "tso_mon: LSU stb data write and read in the same cycle", 3);
end
spc3_multiple_hits = (spc3_lsu_way_hit[3] + spc3_lsu_way_hit[2] + spc3_lsu_way_hit[1] + spc3_lsu_way_hit[0]);
if(!spc3_lsu_ifu_ldst_miss_w && (spc3_multiple_hits >1) && spc3_inst_vld_w && !spc3_dctl_flush_pipe_w && !spc3_lsu_dc_tag_pe_g_unmasked_or)
finish_test("spc", "tso_mon: LSU multiple hits ", 3);
end
wire spc3_ld_dbl = spc3_ld_inst_vld_g & spc3_ldst_dbl_g & ~spc3_quad_asi_g;
wire spc3_ld_quad = spc3_ld_inst_vld_g & spc3_ldst_dbl_g & spc3_quad_asi_g;
wire spc3_ld_other = spc3_ld_inst_vld_g & ~spc3_ldst_dbl_g;
wire spc3_ld_dbl_fp = spc3_ld_dbl & spc3_ldst_fp_g;
wire spc3_ld_other_fp = spc3_ld_other & spc3_ldst_fp_g;
wire spc3_ld_dbl_int = spc3_ld_dbl & ~spc3_ldst_fp_g;
wire spc3_ld_quad_int = spc3_ld_quad & ~spc3_ldst_fp_g;
wire spc3_ld_other_int= spc3_ld_other & ~spc3_ldst_fp_g;
wire spc3_ld_bypassok_hit = |spc3_stb_ld_full_raw[7:0] & ~spc3_stb_cam_mhit;
wire spc3_ld_partial_hit = |spc3_stb_ld_partial_raw[7:0] & ~spc3_stb_cam_mhit;
wire spc3_ld_multiple_hit = spc3_stb_cam_mhit;
wire spc3_any_lsu_way_hit = |spc3_lsu_way_hit;
wire [7:0] spc3_stb_rdptr_decoded = (spc3_stb_rdptr ==3'b000) ? 8'b00000001 :
(spc3_stb_rdptr ==3'b001) ? 8'b00000010 :
(spc3_stb_rdptr ==3'b010) ? 8'b00000100 :
(spc3_stb_rdptr ==3'b011) ? 8'b00001000 :
(spc3_stb_rdptr ==3'b100) ? 8'b00010000 :
(spc3_stb_rdptr ==3'b101) ? 8'b00100000 :
(spc3_stb_rdptr ==3'b110) ? 8'b01000000 :
(spc3_stb_rdptr ==3'b111) ? 8'b10000000 : 8'h00;
wire spc3_stb_top_hit = |(spc3_stb_rdptr_decoded & (spc3_stb_ld_full_raw | spc3_stb_ld_partial_raw));
//---------------------------------------------------------------------
// ld_type[4:0] hit_type[2:0], cache_hit, hit_top
// this is passed to the coverage monitor.
//---------------------------------------------------------------------
wire [10:0] spc3_stb_ld_hit_info =
{spc3_ld_dbl_fp, spc3_ld_other_fp,
spc3_ld_dbl_int, spc3_ld_quad_int, spc3_ld_other_int,
spc3_ld_bypassok_hit, spc3_ld_partial_hit, spc3_ld_multiple_hit,
spc3_any_lsu_way_hit,
spc3_stb_top_hit, C3_st_ack_w};
reg spc3_mbar0_active;
reg spc3_mbar1_active;
reg spc3_mbar2_active;
reg spc3_mbar3_active;
reg spc3_flush0_active;
reg spc3_flush1_active;
reg spc3_flush2_active;
reg spc3_flush3_active;
reg spc3_intr0_active;
reg spc3_intr1_active;
reg spc3_intr2_active;
reg spc3_intr3_active;
always @(negedge clk)
begin
if(~rst_l)
begin
spc3_mbar0_active <= 1'b0;
spc3_mbar1_active <= 1'b0;
spc3_mbar2_active <= 1'b0;
spc3_mbar3_active <= 1'b0;
spc3_flush0_active <= 1'b0;
spc3_flush1_active <= 1'b0;
spc3_flush2_active <= 1'b0;
spc3_flush3_active <= 1'b0;
spc3_intr0_active <= 1'b0;
spc3_intr1_active <= 1'b0;
spc3_intr2_active <= 1'b0;
spc3_intr3_active <= 1'b0;
end
else
begin
if(spc3_mbar_inst0_g & ~spc3_dctl_flush_pipe_w & (C3T0_stb_ne|~spc3_no_spc_rmo_st[0]))
spc3_mbar0_active <= 1'b1;
else if(~C3T0_stb_ne & spc3_no_spc_rmo_st[0])
spc3_mbar0_active <= 1'b0;
if(spc3_mbar_inst1_g & ~ spc3_dctl_flush_pipe_w & (C3T1_stb_ne|~spc3_no_spc_rmo_st[1]))
spc3_mbar1_active <= 1'b1;
else if(~C3T1_stb_ne & spc3_no_spc_rmo_st[1])
spc3_mbar1_active <= 1'b0;
if(spc3_mbar_inst2_g & ~ spc3_dctl_flush_pipe_w & (C3T2_stb_ne|~spc3_no_spc_rmo_st[2]))
spc3_mbar2_active <= 1'b1;
else if(~C3T2_stb_ne & spc3_no_spc_rmo_st[2])
spc3_mbar2_active <= 1'b0;
if(spc3_mbar_inst3_g & ~ spc3_dctl_flush_pipe_w & (C3T3_stb_ne|~spc3_no_spc_rmo_st[3]))
spc3_mbar3_active <= 1'b1;
else if(~C3T3_stb_ne & spc3_no_spc_rmo_st[3])
spc3_mbar3_active <= 1'b0;
if(spc3_flush_inst0_g & ~spc3_dctl_flush_pipe_w & C3T0_stb_ne) spc3_flush0_active <= 1'b1;
else if(~C3T0_stb_ne) spc3_flush0_active <= 1'b0;
if(spc3_flush_inst1_g & ~spc3_dctl_flush_pipe_w & C3T1_stb_ne) spc3_flush1_active <= 1'b1;
else if(~C3T1_stb_ne) spc3_flush1_active <= 1'b0;
if(spc3_flush_inst2_g & ~spc3_dctl_flush_pipe_w & C3T2_stb_ne) spc3_flush2_active <= 1'b1;
else if(~C3T2_stb_ne) spc3_flush2_active <= 1'b0;
if(spc3_flush_inst3_g & ~spc3_dctl_flush_pipe_w & C3T3_stb_ne) spc3_flush3_active <= 1'b1;
else if(~C3T3_stb_ne) spc3_flush3_active <= 1'b0;
if(spc3_intrpt_disp_asi0_g & spc3_st_inst_vld_g & ~spc3_non_altspace_ldst_g & ~spc3_dctl_flush_pipe_w & C3T0_stb_ne)
spc3_intr0_active <= 1'b1;
else if(~C3T0_stb_ne)
spc3_intr0_active <= 1'b0;
if(spc3_intrpt_disp_asi1_g & spc3_st_inst_vld_g & ~spc3_non_altspace_ldst_g & ~spc3_dctl_flush_pipe_w & C3T1_stb_ne)
spc3_intr1_active <= 1'b1;
else if(~C3T1_stb_ne)
spc3_intr1_active <= 1'b0;
if(spc3_intrpt_disp_asi2_g & spc3_st_inst_vld_g & ~spc3_non_altspace_ldst_g & ~spc3_dctl_flush_pipe_w & C3T2_stb_ne)
spc3_intr2_active <= 1'b1;
else if(~C3T2_stb_ne)
spc3_intr2_active <= 1'b0;
if(spc3_intrpt_disp_asi3_g & spc3_st_inst_vld_g & ~spc3_non_altspace_ldst_g & ~spc3_dctl_flush_pipe_w & C3T3_stb_ne)
spc3_intr3_active <= 1'b1;
else if(~C3T3_stb_ne)
spc3_intr3_active <= 1'b0;
end
if(spc3_mbar0_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "membar violation thread 0", 3);
if(spc3_mbar1_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "membar violation thread 1", 3);
if(spc3_mbar2_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "membar violation thread 2", 3);
if(spc3_mbar3_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "membar violation thread 3", 3);
if(spc3_flush0_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "flush violation thread 0", 3);
if(spc3_flush1_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "flush violation thread 1", 3);
if(spc3_flush2_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "flush violation thread 2", 3);
if(spc3_flush3_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "flush violation thread 3", 3);
if(spc3_intr0_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "intr violation thread 0", 3);
if(spc3_intr1_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "intr violation thread 1", 3);
if(spc3_intr2_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "intr violation thread 2", 3);
if(spc3_intr3_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "intr violation thread 3", 3);
if(~rst_l | ~C3T0_stb_full | sctag_pcx_stall_pq) C3T0_stb_drain_cnt = 0;
else C3T0_stb_drain_cnt = C3T0_stb_drain_cnt + 1;
if(C3T0_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 0 is not draining", 3);
if(~rst_l | ~C3T1_stb_full | sctag_pcx_stall_pq) C3T1_stb_drain_cnt = 0;
else C3T1_stb_drain_cnt = C3T1_stb_drain_cnt + 1;
if(C3T1_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 1 is not draining", 3);
if(~rst_l | ~C3T2_stb_full | sctag_pcx_stall_pq) C3T2_stb_drain_cnt = 0;
else C3T2_stb_drain_cnt = C3T2_stb_drain_cnt + 1;
if(C3T2_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 2 is not draining", 3);
if(~rst_l | ~C3T3_stb_full | sctag_pcx_stall_pq) C3T3_stb_drain_cnt = 0;
else C3T3_stb_drain_cnt = C3T3_stb_drain_cnt + 1;
if(C3T3_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 3 is not draining", 3);
C3T0_stb_vld_sum_d1 <= C3T0_stb_vld_sum;
C3T1_stb_vld_sum_d1 <= C3T1_stb_vld_sum;
C3T2_stb_vld_sum_d1 <= C3T2_stb_vld_sum;
C3T3_stb_vld_sum_d1 <= C3T3_stb_vld_sum;
C3T0_defr_trp_en_d1 <= C3T0_defr_trp_en;
C3T1_defr_trp_en_d1 <= C3T1_defr_trp_en;
C3T2_defr_trp_en_d1 <= C3T2_defr_trp_en;
C3T3_defr_trp_en_d1 <= C3T3_defr_trp_en;
if(rst_l & C3T0_defr_trp_en_d1 & (C3T0_stb_vld_sum_d1 < C3T0_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T0", 3);
if(rst_l & C3T1_defr_trp_en_d1 & (C3T1_stb_vld_sum_d1 < C3T1_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T1", 3);
if(rst_l & C3T2_defr_trp_en_d1 & (C3T2_stb_vld_sum_d1 < C3T2_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T2", 3);
if(rst_l & C3T3_defr_trp_en_d1 & (C3T3_stb_vld_sum_d1 < C3T3_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T3", 3);
end
`endif // ifdef RTL_SPARC3
`ifdef RTL_SPARC4
wire C4T0_stb_ne = |`TOP_DESIGN.sparc4.lsu.stb_ctl0.stb_state_vld[7:0];
wire C4T1_stb_ne = |`TOP_DESIGN.sparc4.lsu.stb_ctl1.stb_state_vld[7:0];
wire C4T2_stb_ne = |`TOP_DESIGN.sparc4.lsu.stb_ctl2.stb_state_vld[7:0];
wire C4T3_stb_ne = |`TOP_DESIGN.sparc4.lsu.stb_ctl3.stb_state_vld[7:0];
wire C4T0_stb_nced = |( `TOP_DESIGN.sparc4.lsu.stb_ctl0.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc4.lsu.stb_ctl0.stb_state_ced[7:0]);
wire C4T1_stb_nced = |( `TOP_DESIGN.sparc4.lsu.stb_ctl1.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc4.lsu.stb_ctl1.stb_state_ced[7:0]);
wire C4T2_stb_nced = |( `TOP_DESIGN.sparc4.lsu.stb_ctl2.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc4.lsu.stb_ctl2.stb_state_ced[7:0]);
wire C4T3_stb_nced = |( `TOP_DESIGN.sparc4.lsu.stb_ctl3.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc4.lsu.stb_ctl3.stb_state_ced[7:0]);
`else
wire C4T0_stb_ne = 1'b0;
wire C4T1_stb_ne = 1'b0;
wire C4T2_stb_ne = 1'b0;
wire C4T3_stb_ne = 1'b0;
wire C4T0_stb_nced = 1'b0;
wire C4T1_stb_nced = 1'b0;
wire C4T2_stb_nced = 1'b0;
wire C4T3_stb_nced = 1'b0;
`endif // ifdef RTL_SPARC4
`ifdef RTL_SPARC4
wire spc4_lsu_ifill_pkt_vld = `TOP_DESIGN.sparc4.lsu.qctl2.lsu_ifill_pkt_vld;
wire spc4_dfq_rd_advance = `TOP_DESIGN.sparc4.lsu.qctl2.dfq_rd_advance;
wire spc4_dfq_int_type = `TOP_DESIGN.sparc4.lsu.qctl2.dfq_int_type;
wire spc4_ifu_lsu_inv_clear = `TOP_DESIGN.sparc4.lsu.qctl2.ifu_lsu_inv_clear;
wire spc4_dva_svld_e = `TOP_DESIGN.sparc4.lsu.qctl2.dva_svld_e;
wire spc4_dva_rvld_e = `TOP_DESIGN.sparc4.lsu.dva.rd_en;
wire [10:4] spc4_dva_rd_addr_e = `TOP_DESIGN.sparc4.lsu.dva.rd_adr1[6:0];
wire [4:0] spc4_dva_snp_addr_e = `TOP_DESIGN.sparc4.lsu.qctl2.dva_snp_addr_e[4:0];
wire [4:0] spc4_stb_data_rd_ptr = `TOP_DESIGN.sparc4.lsu.stb_data_rd_ptr[4:0];
wire [4:0] spc4_stb_data_wr_ptr = `TOP_DESIGN.sparc4.lsu.stb_data_wr_ptr[4:0];
wire spc4_stb_data_wptr_vld = `TOP_DESIGN.sparc4.lsu.stb_data_wptr_vld;
wire spc4_stb_data_rptr_vld = `TOP_DESIGN.sparc4.lsu.stb_data_rptr_vld;
wire spc4_stbrwctl_flush_pipe_w = `TOP_DESIGN.sparc4.lsu.stb_rwctl.lsu_stbrwctl_flush_pipe_w;
wire spc4_lsu_st_pcx_rq_pick = |`TOP_DESIGN.sparc4.lsu.stb_rwctl.lsu_st_pcx_rq_pick[3:0];
wire [3:0] spc4_lsu_rd_dtag_parity_g = `TOP_DESIGN.sparc4.lsu.dctl.lsu_rd_dtag_parity_g[3:0];
wire [3:0] spc4_dva_vld_g = `TOP_DESIGN.sparc4.lsu.dctl.dva_vld_g[3:0];
wire [3:0] spc4_lsu_dc_tag_pe_g_unmasked = spc4_lsu_rd_dtag_parity_g[3:0] & spc4_dva_vld_g[3:0];
wire spc4_lsu_dc_tag_pe_g_unmasked_or = |spc4_lsu_dc_tag_pe_g_unmasked[3:0];
wire C4T0_stb_full = &`TOP_DESIGN.sparc4.lsu.stb_ctl0.stb_state_vld[7:0];
wire C4T1_stb_full = &`TOP_DESIGN.sparc4.lsu.stb_ctl1.stb_state_vld[7:0];
wire C4T2_stb_full = &`TOP_DESIGN.sparc4.lsu.stb_ctl2.stb_state_vld[7:0];
wire C4T3_stb_full = &`TOP_DESIGN.sparc4.lsu.stb_ctl3.stb_state_vld[7:0];
wire [7:0] C4T0_stb_vld = `TOP_DESIGN.sparc4.lsu.stb_ctl0.stb_state_vld[7:0];
wire [7:0] C4T1_stb_vld = `TOP_DESIGN.sparc4.lsu.stb_ctl1.stb_state_vld[7:0];
wire [7:0] C4T2_stb_vld = `TOP_DESIGN.sparc4.lsu.stb_ctl2.stb_state_vld[7:0];
wire [7:0] C4T3_stb_vld = `TOP_DESIGN.sparc4.lsu.stb_ctl3.stb_state_vld[7:0];
wire [4:0] C4T0_stb_vld_sum = C4T0_stb_vld[0] + C4T0_stb_vld[1] + C4T0_stb_vld[2] + C4T0_stb_vld[3] +
C4T0_stb_vld[4] + C4T0_stb_vld[5] + C4T0_stb_vld[6] + C4T0_stb_vld[7] ;
wire [4:0] C4T1_stb_vld_sum = C4T1_stb_vld[0] + C4T1_stb_vld[1] + C4T1_stb_vld[2] + C4T1_stb_vld[3] +
C4T1_stb_vld[4] + C4T1_stb_vld[5] + C4T1_stb_vld[6] + C4T1_stb_vld[7] ;
wire [4:0] C4T2_stb_vld_sum = C4T2_stb_vld[0] + C4T2_stb_vld[1] + C4T2_stb_vld[2] + C4T2_stb_vld[3] +
C4T2_stb_vld[4] + C4T2_stb_vld[5] + C4T2_stb_vld[6] + C4T2_stb_vld[7] ;
wire [4:0] C4T3_stb_vld_sum = C4T3_stb_vld[0] + C4T3_stb_vld[1] + C4T3_stb_vld[2] + C4T3_stb_vld[3] +
C4T3_stb_vld[4] + C4T3_stb_vld[5] + C4T3_stb_vld[6] + C4T3_stb_vld[7] ;
reg [4:0] C4T0_stb_vld_sum_d1;
reg [4:0] C4T1_stb_vld_sum_d1;
reg [4:0] C4T2_stb_vld_sum_d1;
reg [4:0] C4T3_stb_vld_sum_d1;
wire C4T0_st_ack = &`TOP_DESIGN.sparc4.lsu.cpx_st_ack_tid0;
wire C4T1_st_ack = &`TOP_DESIGN.sparc4.lsu.cpx_st_ack_tid1;
wire C4T2_st_ack = &`TOP_DESIGN.sparc4.lsu.cpx_st_ack_tid2;
wire C4T3_st_ack = &`TOP_DESIGN.sparc4.lsu.cpx_st_ack_tid3;
wire C4T0_defr_trp_en = &`TOP_DESIGN.sparc4.lsu.excpctl.st_defr_trp_en0;
wire C4T1_defr_trp_en = &`TOP_DESIGN.sparc4.lsu.excpctl.st_defr_trp_en1;
wire C4T2_defr_trp_en = &`TOP_DESIGN.sparc4.lsu.excpctl.st_defr_trp_en2;
wire C4T3_defr_trp_en = &`TOP_DESIGN.sparc4.lsu.excpctl.st_defr_trp_en3;
reg C4T0_defr_trp_en_d1;
reg C4T1_defr_trp_en_d1;
reg C4T2_defr_trp_en_d1;
reg C4T3_defr_trp_en_d1;
integer C4T0_stb_drain_cnt;
integer C4T1_stb_drain_cnt;
integer C4T2_stb_drain_cnt;
integer C4T3_stb_drain_cnt;
// Hits in the store buffer
//-------------------------
wire spc4_inst_vld_w = `TOP_DESIGN.sparc4.ifu.fcl.inst_vld_w;
wire [1:0] spc4_sas_thrid_w = `TOP_DESIGN.sparc4.ifu.fcl.sas_thrid_w[1:0];
wire C4_st_ack_w = (spc4_sas_thrid_w == 2'b00) & C4T0_st_ack |
(spc4_sas_thrid_w == 2'b01) & C4T1_st_ack |
(spc4_sas_thrid_w == 2'b10) & C4T2_st_ack |
(spc4_sas_thrid_w == 2'b11) & C4T3_st_ack;
wire [7:0] spc4_stb_ld_full_raw = `TOP_DESIGN.sparc4.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc4_stb_ld_partial_raw = `TOP_DESIGN.sparc4.lsu.stb_ld_partial_raw[7:0];
wire spc4_stb_cam_mhit = `TOP_DESIGN.sparc4.lsu.stb_cam_mhit;
wire spc4_stb_cam_hit = `TOP_DESIGN.sparc4.lsu.stb_cam_hit;
wire [3:0] spc4_lsu_way_hit = `TOP_DESIGN.sparc4.lsu.dctl.lsu_way_hit[3:0];
wire spc4_lsu_ifu_ldst_miss_w = `TOP_DESIGN.sparc4.lsu.lsu_ifu_ldst_miss_w;
wire spc4_ld_inst_vld_g = `TOP_DESIGN.sparc4.lsu.dctl.ld_inst_vld_g;
wire spc4_ldst_dbl_g = `TOP_DESIGN.sparc4.lsu.dctl.ldst_dbl_g;
wire spc4_quad_asi_g = `TOP_DESIGN.sparc4.lsu.dctl.quad_asi_g;
wire [1:0] spc4_ldst_sz_g = `TOP_DESIGN.sparc4.lsu.dctl.ldst_sz_g;
wire spc4_lsu_alt_space_g = `TOP_DESIGN.sparc4.lsu.dctl.lsu_alt_space_g;
wire spc4_mbar_inst0_g = `TOP_DESIGN.sparc4.lsu.dctl.mbar_inst0_g;
wire spc4_mbar_inst1_g = `TOP_DESIGN.sparc4.lsu.dctl.mbar_inst1_g;
wire spc4_mbar_inst2_g = `TOP_DESIGN.sparc4.lsu.dctl.mbar_inst2_g;
wire spc4_mbar_inst3_g = `TOP_DESIGN.sparc4.lsu.dctl.mbar_inst3_g;
wire spc4_flush_inst0_g = `TOP_DESIGN.sparc4.lsu.dctl.flush_inst0_g;
wire spc4_flush_inst1_g = `TOP_DESIGN.sparc4.lsu.dctl.flush_inst1_g;
wire spc4_flush_inst2_g = `TOP_DESIGN.sparc4.lsu.dctl.flush_inst2_g;
wire spc4_flush_inst3_g = `TOP_DESIGN.sparc4.lsu.dctl.flush_inst3_g;
wire spc4_intrpt_disp_asi0_g = `TOP_DESIGN.sparc4.lsu.dctl.intrpt_disp_asi_g & (spc4_sas_thrid_w == 2'b00);
wire spc4_intrpt_disp_asi1_g = `TOP_DESIGN.sparc4.lsu.dctl.intrpt_disp_asi_g & (spc4_sas_thrid_w == 2'b01);
wire spc4_intrpt_disp_asi2_g = `TOP_DESIGN.sparc4.lsu.dctl.intrpt_disp_asi_g & (spc4_sas_thrid_w == 2'b10);
wire spc4_intrpt_disp_asi3_g = `TOP_DESIGN.sparc4.lsu.dctl.intrpt_disp_asi_g & (spc4_sas_thrid_w == 2'b11);
wire spc4_st_inst_vld_g = `TOP_DESIGN.sparc4.lsu.dctl.st_inst_vld_g;
wire spc4_non_altspace_ldst_g = `TOP_DESIGN.sparc4.lsu.dctl.non_altspace_ldst_g;
wire spc4_dctl_flush_pipe_w = `TOP_DESIGN.sparc4.lsu.dctl.dctl_flush_pipe_w;
wire [3:0] spc4_no_spc_rmo_st = `TOP_DESIGN.sparc4.lsu.dctl.no_spc_rmo_st[3:0];
wire spc4_ldst_fp_e = `TOP_DESIGN.sparc4.lsu.ifu_lsu_ldst_fp_e;
wire [2:0] spc4_stb_rdptr = `TOP_DESIGN.sparc4.lsu.stb_rwctl.stb_rdptr_l;
wire spc4_ld_l2cache_req = `TOP_DESIGN.sparc4.lsu.qctl1.ld3_l2cache_rq |
`TOP_DESIGN.sparc4.lsu.qctl1.ld2_l2cache_rq |
`TOP_DESIGN.sparc4.lsu.qctl1.ld1_l2cache_rq |
`TOP_DESIGN.sparc4.lsu.qctl1.ld0_l2cache_rq;
wire [3:0] spc4_dcache_enable = {`TOP_DESIGN.sparc4.lsu.dctl.lsu_ctl_reg0[1],
`TOP_DESIGN.sparc4.lsu.dctl.lsu_ctl_reg1[1],
`TOP_DESIGN.sparc4.lsu.dctl.lsu_ctl_reg2[1],
`TOP_DESIGN.sparc4.lsu.dctl.lsu_ctl_reg3[1]};
wire [3:0] spc4_icache_enable = `TOP_DESIGN.sparc4.lsu.lsu_ifu_icache_en[3:0];
wire spc4_dc_direct_map = `TOP_DESIGN.sparc4.lsu.dc_direct_map;
wire spc4_lsu_ifu_direct_map_l1 = `TOP_DESIGN.sparc4.lsu.lsu_ifu_direct_map_l1;
always @(spc4_dcache_enable)
$display("%0d tso_mon: spc4_dcache_enable changed to %x", $time, spc4_dcache_enable);
always @(spc4_icache_enable)
$display("%0d tso_mon: spc4_icache_enable changed to %x", $time, spc4_icache_enable);
always @(spc4_dc_direct_map)
$display("%0d tso_mon: spc4_dc_direct_map changed to %x", $time, spc4_dc_direct_map);
always @(spc4_lsu_ifu_direct_map_l1)
$display("%0d tso_mon: spc4_lsu_ifu_direct_map_l1 changed to %x", $time, spc4_lsu_ifu_direct_map_l1);
reg spc4_dva_svld_e_d1;
reg spc4_dva_rvld_e_d1;
reg [10:4] spc4_dva_rd_addr_e_d1;
reg [4:0] spc4_dva_snp_addr_e_d1;
reg spc4_lsu_snp_after_rd;
reg spc4_lsu_rd_after_snp;
reg spc4_ldst_fp_m, spc4_ldst_fp_g;
integer spc4_multiple_hits;
reg spc4_skid_d1, spc4_skid_d2, spc4_skid_d3;
initial begin
spc4_skid_d1 = 0;
spc4_skid_d2 = 0;
spc4_skid_d3 = 0;
end
always @(posedge clk)
begin
spc4_skid_d1 <= (~spc4_ifu_lsu_inv_clear & spc4_dfq_rd_advance & spc4_dfq_int_type);
spc4_skid_d2 <= spc4_skid_d1 & ~spc4_ifu_lsu_inv_clear;
spc4_skid_d3 <= spc4_skid_d2 & ~spc4_ifu_lsu_inv_clear;
// The full tracking of this condition is complicated since after the interrupt is advanced
// there may be more invalidations to the IFQ.
// All we care about is that the invalidations BEFORE the interrupt are finished.
// I provided a command line argument to disable this check.
if(spc4_skid_d3 & enable_ifu_lsu_inv_clear)
finish_test("spc", "tso_mon: spc4_ifu_lsu_inv_clear should have been clear by now", 4);
spc4_dva_svld_e_d1 <= spc4_dva_svld_e;
spc4_dva_rvld_e_d1 <= spc4_dva_rvld_e;
spc4_dva_rd_addr_e_d1 <= spc4_dva_rd_addr_e;
spc4_dva_snp_addr_e_d1 <= spc4_dva_snp_addr_e;
if(spc4_dva_svld_e_d1 & spc4_dva_rvld_e & (spc4_dva_rd_addr_e_d1[10:6] == spc4_dva_snp_addr_e[4:0]))
spc4_lsu_rd_after_snp <= 1'b1;
else
spc4_lsu_rd_after_snp <= 1'b0;
if(spc4_dva_svld_e & spc4_dva_rvld_e_d1 & (spc4_dva_rd_addr_e[10:6] == spc4_dva_snp_addr_e_d1[4:0]))
spc4_lsu_snp_after_rd <= 1'b1;
else
spc4_lsu_snp_after_rd <= 1'b0;
spc4_ldst_fp_m <= spc4_ldst_fp_e;
spc4_ldst_fp_g <= spc4_ldst_fp_m;
if(spc4_stb_data_rptr_vld & spc4_stb_data_wptr_vld & ~spc4_stbrwctl_flush_pipe_w &
(spc4_stb_data_rd_ptr == spc4_stb_data_wr_ptr) & spc4_lsu_st_pcx_rq_pick)
begin
finish_test("spc", "tso_mon: LSU stb data write and read in the same cycle", 4);
end
spc4_multiple_hits = (spc4_lsu_way_hit[3] + spc4_lsu_way_hit[2] + spc4_lsu_way_hit[1] + spc4_lsu_way_hit[0]);
if(!spc4_lsu_ifu_ldst_miss_w && (spc4_multiple_hits >1) && spc4_inst_vld_w && !spc4_dctl_flush_pipe_w && !spc4_lsu_dc_tag_pe_g_unmasked_or)
finish_test("spc", "tso_mon: LSU multiple hits ", 4);
end
wire spc4_ld_dbl = spc4_ld_inst_vld_g & spc4_ldst_dbl_g & ~spc4_quad_asi_g;
wire spc4_ld_quad = spc4_ld_inst_vld_g & spc4_ldst_dbl_g & spc4_quad_asi_g;
wire spc4_ld_other = spc4_ld_inst_vld_g & ~spc4_ldst_dbl_g;
wire spc4_ld_dbl_fp = spc4_ld_dbl & spc4_ldst_fp_g;
wire spc4_ld_other_fp = spc4_ld_other & spc4_ldst_fp_g;
wire spc4_ld_dbl_int = spc4_ld_dbl & ~spc4_ldst_fp_g;
wire spc4_ld_quad_int = spc4_ld_quad & ~spc4_ldst_fp_g;
wire spc4_ld_other_int= spc4_ld_other & ~spc4_ldst_fp_g;
wire spc4_ld_bypassok_hit = |spc4_stb_ld_full_raw[7:0] & ~spc4_stb_cam_mhit;
wire spc4_ld_partial_hit = |spc4_stb_ld_partial_raw[7:0] & ~spc4_stb_cam_mhit;
wire spc4_ld_multiple_hit = spc4_stb_cam_mhit;
wire spc4_any_lsu_way_hit = |spc4_lsu_way_hit;
wire [7:0] spc4_stb_rdptr_decoded = (spc4_stb_rdptr ==3'b000) ? 8'b00000001 :
(spc4_stb_rdptr ==3'b001) ? 8'b00000010 :
(spc4_stb_rdptr ==3'b010) ? 8'b00000100 :
(spc4_stb_rdptr ==3'b011) ? 8'b00001000 :
(spc4_stb_rdptr ==3'b100) ? 8'b00010000 :
(spc4_stb_rdptr ==3'b101) ? 8'b00100000 :
(spc4_stb_rdptr ==3'b110) ? 8'b01000000 :
(spc4_stb_rdptr ==3'b111) ? 8'b10000000 : 8'h00;
wire spc4_stb_top_hit = |(spc4_stb_rdptr_decoded & (spc4_stb_ld_full_raw | spc4_stb_ld_partial_raw));
//---------------------------------------------------------------------
// ld_type[4:0] hit_type[2:0], cache_hit, hit_top
// this is passed to the coverage monitor.
//---------------------------------------------------------------------
wire [10:0] spc4_stb_ld_hit_info =
{spc4_ld_dbl_fp, spc4_ld_other_fp,
spc4_ld_dbl_int, spc4_ld_quad_int, spc4_ld_other_int,
spc4_ld_bypassok_hit, spc4_ld_partial_hit, spc4_ld_multiple_hit,
spc4_any_lsu_way_hit,
spc4_stb_top_hit, C4_st_ack_w};
reg spc4_mbar0_active;
reg spc4_mbar1_active;
reg spc4_mbar2_active;
reg spc4_mbar3_active;
reg spc4_flush0_active;
reg spc4_flush1_active;
reg spc4_flush2_active;
reg spc4_flush3_active;
reg spc4_intr0_active;
reg spc4_intr1_active;
reg spc4_intr2_active;
reg spc4_intr3_active;
always @(negedge clk)
begin
if(~rst_l)
begin
spc4_mbar0_active <= 1'b0;
spc4_mbar1_active <= 1'b0;
spc4_mbar2_active <= 1'b0;
spc4_mbar3_active <= 1'b0;
spc4_flush0_active <= 1'b0;
spc4_flush1_active <= 1'b0;
spc4_flush2_active <= 1'b0;
spc4_flush3_active <= 1'b0;
spc4_intr0_active <= 1'b0;
spc4_intr1_active <= 1'b0;
spc4_intr2_active <= 1'b0;
spc4_intr3_active <= 1'b0;
end
else
begin
if(spc4_mbar_inst0_g & ~spc4_dctl_flush_pipe_w & (C4T0_stb_ne|~spc4_no_spc_rmo_st[0]))
spc4_mbar0_active <= 1'b1;
else if(~C4T0_stb_ne & spc4_no_spc_rmo_st[0])
spc4_mbar0_active <= 1'b0;
if(spc4_mbar_inst1_g & ~ spc4_dctl_flush_pipe_w & (C4T1_stb_ne|~spc4_no_spc_rmo_st[1]))
spc4_mbar1_active <= 1'b1;
else if(~C4T1_stb_ne & spc4_no_spc_rmo_st[1])
spc4_mbar1_active <= 1'b0;
if(spc4_mbar_inst2_g & ~ spc4_dctl_flush_pipe_w & (C4T2_stb_ne|~spc4_no_spc_rmo_st[2]))
spc4_mbar2_active <= 1'b1;
else if(~C4T2_stb_ne & spc4_no_spc_rmo_st[2])
spc4_mbar2_active <= 1'b0;
if(spc4_mbar_inst3_g & ~ spc4_dctl_flush_pipe_w & (C4T3_stb_ne|~spc4_no_spc_rmo_st[3]))
spc4_mbar3_active <= 1'b1;
else if(~C4T3_stb_ne & spc4_no_spc_rmo_st[3])
spc4_mbar3_active <= 1'b0;
if(spc4_flush_inst0_g & ~spc4_dctl_flush_pipe_w & C4T0_stb_ne) spc4_flush0_active <= 1'b1;
else if(~C4T0_stb_ne) spc4_flush0_active <= 1'b0;
if(spc4_flush_inst1_g & ~spc4_dctl_flush_pipe_w & C4T1_stb_ne) spc4_flush1_active <= 1'b1;
else if(~C4T1_stb_ne) spc4_flush1_active <= 1'b0;
if(spc4_flush_inst2_g & ~spc4_dctl_flush_pipe_w & C4T2_stb_ne) spc4_flush2_active <= 1'b1;
else if(~C4T2_stb_ne) spc4_flush2_active <= 1'b0;
if(spc4_flush_inst3_g & ~spc4_dctl_flush_pipe_w & C4T3_stb_ne) spc4_flush3_active <= 1'b1;
else if(~C4T3_stb_ne) spc4_flush3_active <= 1'b0;
if(spc4_intrpt_disp_asi0_g & spc4_st_inst_vld_g & ~spc4_non_altspace_ldst_g & ~spc4_dctl_flush_pipe_w & C4T0_stb_ne)
spc4_intr0_active <= 1'b1;
else if(~C4T0_stb_ne)
spc4_intr0_active <= 1'b0;
if(spc4_intrpt_disp_asi1_g & spc4_st_inst_vld_g & ~spc4_non_altspace_ldst_g & ~spc4_dctl_flush_pipe_w & C4T1_stb_ne)
spc4_intr1_active <= 1'b1;
else if(~C4T1_stb_ne)
spc4_intr1_active <= 1'b0;
if(spc4_intrpt_disp_asi2_g & spc4_st_inst_vld_g & ~spc4_non_altspace_ldst_g & ~spc4_dctl_flush_pipe_w & C4T2_stb_ne)
spc4_intr2_active <= 1'b1;
else if(~C4T2_stb_ne)
spc4_intr2_active <= 1'b0;
if(spc4_intrpt_disp_asi3_g & spc4_st_inst_vld_g & ~spc4_non_altspace_ldst_g & ~spc4_dctl_flush_pipe_w & C4T3_stb_ne)
spc4_intr3_active <= 1'b1;
else if(~C4T3_stb_ne)
spc4_intr3_active <= 1'b0;
end
if(spc4_mbar0_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "membar violation thread 0", 4);
if(spc4_mbar1_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "membar violation thread 1", 4);
if(spc4_mbar2_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "membar violation thread 2", 4);
if(spc4_mbar3_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "membar violation thread 3", 4);
if(spc4_flush0_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "flush violation thread 0", 4);
if(spc4_flush1_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "flush violation thread 1", 4);
if(spc4_flush2_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "flush violation thread 2", 4);
if(spc4_flush3_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "flush violation thread 3", 4);
if(spc4_intr0_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "intr violation thread 0", 4);
if(spc4_intr1_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "intr violation thread 1", 4);
if(spc4_intr2_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "intr violation thread 2", 4);
if(spc4_intr3_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "intr violation thread 3", 4);
if(~rst_l | ~C4T0_stb_full | sctag_pcx_stall_pq) C4T0_stb_drain_cnt = 0;
else C4T0_stb_drain_cnt = C4T0_stb_drain_cnt + 1;
if(C4T0_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 0 is not draining", 4);
if(~rst_l | ~C4T1_stb_full | sctag_pcx_stall_pq) C4T1_stb_drain_cnt = 0;
else C4T1_stb_drain_cnt = C4T1_stb_drain_cnt + 1;
if(C4T1_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 1 is not draining", 4);
if(~rst_l | ~C4T2_stb_full | sctag_pcx_stall_pq) C4T2_stb_drain_cnt = 0;
else C4T2_stb_drain_cnt = C4T2_stb_drain_cnt + 1;
if(C4T2_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 2 is not draining", 4);
if(~rst_l | ~C4T3_stb_full | sctag_pcx_stall_pq) C4T3_stb_drain_cnt = 0;
else C4T3_stb_drain_cnt = C4T3_stb_drain_cnt + 1;
if(C4T3_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 3 is not draining", 4);
C4T0_stb_vld_sum_d1 <= C4T0_stb_vld_sum;
C4T1_stb_vld_sum_d1 <= C4T1_stb_vld_sum;
C4T2_stb_vld_sum_d1 <= C4T2_stb_vld_sum;
C4T3_stb_vld_sum_d1 <= C4T3_stb_vld_sum;
C4T0_defr_trp_en_d1 <= C4T0_defr_trp_en;
C4T1_defr_trp_en_d1 <= C4T1_defr_trp_en;
C4T2_defr_trp_en_d1 <= C4T2_defr_trp_en;
C4T3_defr_trp_en_d1 <= C4T3_defr_trp_en;
if(rst_l & C4T0_defr_trp_en_d1 & (C4T0_stb_vld_sum_d1 < C4T0_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T0", 4);
if(rst_l & C4T1_defr_trp_en_d1 & (C4T1_stb_vld_sum_d1 < C4T1_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T1", 4);
if(rst_l & C4T2_defr_trp_en_d1 & (C4T2_stb_vld_sum_d1 < C4T2_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T2", 4);
if(rst_l & C4T3_defr_trp_en_d1 & (C4T3_stb_vld_sum_d1 < C4T3_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T3", 4);
end
`endif // ifdef RTL_SPARC4
`ifdef RTL_SPARC5
wire C5T0_stb_ne = |`TOP_DESIGN.sparc5.lsu.stb_ctl0.stb_state_vld[7:0];
wire C5T1_stb_ne = |`TOP_DESIGN.sparc5.lsu.stb_ctl1.stb_state_vld[7:0];
wire C5T2_stb_ne = |`TOP_DESIGN.sparc5.lsu.stb_ctl2.stb_state_vld[7:0];
wire C5T3_stb_ne = |`TOP_DESIGN.sparc5.lsu.stb_ctl3.stb_state_vld[7:0];
wire C5T0_stb_nced = |( `TOP_DESIGN.sparc5.lsu.stb_ctl0.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc5.lsu.stb_ctl0.stb_state_ced[7:0]);
wire C5T1_stb_nced = |( `TOP_DESIGN.sparc5.lsu.stb_ctl1.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc5.lsu.stb_ctl1.stb_state_ced[7:0]);
wire C5T2_stb_nced = |( `TOP_DESIGN.sparc5.lsu.stb_ctl2.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc5.lsu.stb_ctl2.stb_state_ced[7:0]);
wire C5T3_stb_nced = |( `TOP_DESIGN.sparc5.lsu.stb_ctl3.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc5.lsu.stb_ctl3.stb_state_ced[7:0]);
`else
wire C5T0_stb_ne = 1'b0;
wire C5T1_stb_ne = 1'b0;
wire C5T2_stb_ne = 1'b0;
wire C5T3_stb_ne = 1'b0;
wire C5T0_stb_nced = 1'b0;
wire C5T1_stb_nced = 1'b0;
wire C5T2_stb_nced = 1'b0;
wire C5T3_stb_nced = 1'b0;
`endif // ifdef RTL_SPARC5
`ifdef RTL_SPARC5
wire spc5_lsu_ifill_pkt_vld = `TOP_DESIGN.sparc5.lsu.qctl2.lsu_ifill_pkt_vld;
wire spc5_dfq_rd_advance = `TOP_DESIGN.sparc5.lsu.qctl2.dfq_rd_advance;
wire spc5_dfq_int_type = `TOP_DESIGN.sparc5.lsu.qctl2.dfq_int_type;
wire spc5_ifu_lsu_inv_clear = `TOP_DESIGN.sparc5.lsu.qctl2.ifu_lsu_inv_clear;
wire spc5_dva_svld_e = `TOP_DESIGN.sparc5.lsu.qctl2.dva_svld_e;
wire spc5_dva_rvld_e = `TOP_DESIGN.sparc5.lsu.dva.rd_en;
wire [10:4] spc5_dva_rd_addr_e = `TOP_DESIGN.sparc5.lsu.dva.rd_adr1[6:0];
wire [4:0] spc5_dva_snp_addr_e = `TOP_DESIGN.sparc5.lsu.qctl2.dva_snp_addr_e[4:0];
wire [4:0] spc5_stb_data_rd_ptr = `TOP_DESIGN.sparc5.lsu.stb_data_rd_ptr[4:0];
wire [4:0] spc5_stb_data_wr_ptr = `TOP_DESIGN.sparc5.lsu.stb_data_wr_ptr[4:0];
wire spc5_stb_data_wptr_vld = `TOP_DESIGN.sparc5.lsu.stb_data_wptr_vld;
wire spc5_stb_data_rptr_vld = `TOP_DESIGN.sparc5.lsu.stb_data_rptr_vld;
wire spc5_stbrwctl_flush_pipe_w = `TOP_DESIGN.sparc5.lsu.stb_rwctl.lsu_stbrwctl_flush_pipe_w;
wire spc5_lsu_st_pcx_rq_pick = |`TOP_DESIGN.sparc5.lsu.stb_rwctl.lsu_st_pcx_rq_pick[3:0];
wire [3:0] spc5_lsu_rd_dtag_parity_g = `TOP_DESIGN.sparc5.lsu.dctl.lsu_rd_dtag_parity_g[3:0];
wire [3:0] spc5_dva_vld_g = `TOP_DESIGN.sparc5.lsu.dctl.dva_vld_g[3:0];
wire [3:0] spc5_lsu_dc_tag_pe_g_unmasked = spc5_lsu_rd_dtag_parity_g[3:0] & spc5_dva_vld_g[3:0];
wire spc5_lsu_dc_tag_pe_g_unmasked_or = |spc5_lsu_dc_tag_pe_g_unmasked[3:0];
wire C5T0_stb_full = &`TOP_DESIGN.sparc5.lsu.stb_ctl0.stb_state_vld[7:0];
wire C5T1_stb_full = &`TOP_DESIGN.sparc5.lsu.stb_ctl1.stb_state_vld[7:0];
wire C5T2_stb_full = &`TOP_DESIGN.sparc5.lsu.stb_ctl2.stb_state_vld[7:0];
wire C5T3_stb_full = &`TOP_DESIGN.sparc5.lsu.stb_ctl3.stb_state_vld[7:0];
wire [7:0] C5T0_stb_vld = `TOP_DESIGN.sparc5.lsu.stb_ctl0.stb_state_vld[7:0];
wire [7:0] C5T1_stb_vld = `TOP_DESIGN.sparc5.lsu.stb_ctl1.stb_state_vld[7:0];
wire [7:0] C5T2_stb_vld = `TOP_DESIGN.sparc5.lsu.stb_ctl2.stb_state_vld[7:0];
wire [7:0] C5T3_stb_vld = `TOP_DESIGN.sparc5.lsu.stb_ctl3.stb_state_vld[7:0];
wire [4:0] C5T0_stb_vld_sum = C5T0_stb_vld[0] + C5T0_stb_vld[1] + C5T0_stb_vld[2] + C5T0_stb_vld[3] +
C5T0_stb_vld[4] + C5T0_stb_vld[5] + C5T0_stb_vld[6] + C5T0_stb_vld[7] ;
wire [4:0] C5T1_stb_vld_sum = C5T1_stb_vld[0] + C5T1_stb_vld[1] + C5T1_stb_vld[2] + C5T1_stb_vld[3] +
C5T1_stb_vld[4] + C5T1_stb_vld[5] + C5T1_stb_vld[6] + C5T1_stb_vld[7] ;
wire [4:0] C5T2_stb_vld_sum = C5T2_stb_vld[0] + C5T2_stb_vld[1] + C5T2_stb_vld[2] + C5T2_stb_vld[3] +
C5T2_stb_vld[4] + C5T2_stb_vld[5] + C5T2_stb_vld[6] + C5T2_stb_vld[7] ;
wire [4:0] C5T3_stb_vld_sum = C5T3_stb_vld[0] + C5T3_stb_vld[1] + C5T3_stb_vld[2] + C5T3_stb_vld[3] +
C5T3_stb_vld[4] + C5T3_stb_vld[5] + C5T3_stb_vld[6] + C5T3_stb_vld[7] ;
reg [4:0] C5T0_stb_vld_sum_d1;
reg [4:0] C5T1_stb_vld_sum_d1;
reg [4:0] C5T2_stb_vld_sum_d1;
reg [4:0] C5T3_stb_vld_sum_d1;
wire C5T0_st_ack = &`TOP_DESIGN.sparc5.lsu.cpx_st_ack_tid0;
wire C5T1_st_ack = &`TOP_DESIGN.sparc5.lsu.cpx_st_ack_tid1;
wire C5T2_st_ack = &`TOP_DESIGN.sparc5.lsu.cpx_st_ack_tid2;
wire C5T3_st_ack = &`TOP_DESIGN.sparc5.lsu.cpx_st_ack_tid3;
wire C5T0_defr_trp_en = &`TOP_DESIGN.sparc5.lsu.excpctl.st_defr_trp_en0;
wire C5T1_defr_trp_en = &`TOP_DESIGN.sparc5.lsu.excpctl.st_defr_trp_en1;
wire C5T2_defr_trp_en = &`TOP_DESIGN.sparc5.lsu.excpctl.st_defr_trp_en2;
wire C5T3_defr_trp_en = &`TOP_DESIGN.sparc5.lsu.excpctl.st_defr_trp_en3;
reg C5T0_defr_trp_en_d1;
reg C5T1_defr_trp_en_d1;
reg C5T2_defr_trp_en_d1;
reg C5T3_defr_trp_en_d1;
integer C5T0_stb_drain_cnt;
integer C5T1_stb_drain_cnt;
integer C5T2_stb_drain_cnt;
integer C5T3_stb_drain_cnt;
// Hits in the store buffer
//-------------------------
wire spc5_inst_vld_w = `TOP_DESIGN.sparc5.ifu.fcl.inst_vld_w;
wire [1:0] spc5_sas_thrid_w = `TOP_DESIGN.sparc5.ifu.fcl.sas_thrid_w[1:0];
wire C5_st_ack_w = (spc5_sas_thrid_w == 2'b00) & C5T0_st_ack |
(spc5_sas_thrid_w == 2'b01) & C5T1_st_ack |
(spc5_sas_thrid_w == 2'b10) & C5T2_st_ack |
(spc5_sas_thrid_w == 2'b11) & C5T3_st_ack;
wire [7:0] spc5_stb_ld_full_raw = `TOP_DESIGN.sparc5.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc5_stb_ld_partial_raw = `TOP_DESIGN.sparc5.lsu.stb_ld_partial_raw[7:0];
wire spc5_stb_cam_mhit = `TOP_DESIGN.sparc5.lsu.stb_cam_mhit;
wire spc5_stb_cam_hit = `TOP_DESIGN.sparc5.lsu.stb_cam_hit;
wire [3:0] spc5_lsu_way_hit = `TOP_DESIGN.sparc5.lsu.dctl.lsu_way_hit[3:0];
wire spc5_lsu_ifu_ldst_miss_w = `TOP_DESIGN.sparc5.lsu.lsu_ifu_ldst_miss_w;
wire spc5_ld_inst_vld_g = `TOP_DESIGN.sparc5.lsu.dctl.ld_inst_vld_g;
wire spc5_ldst_dbl_g = `TOP_DESIGN.sparc5.lsu.dctl.ldst_dbl_g;
wire spc5_quad_asi_g = `TOP_DESIGN.sparc5.lsu.dctl.quad_asi_g;
wire [1:0] spc5_ldst_sz_g = `TOP_DESIGN.sparc5.lsu.dctl.ldst_sz_g;
wire spc5_lsu_alt_space_g = `TOP_DESIGN.sparc5.lsu.dctl.lsu_alt_space_g;
wire spc5_mbar_inst0_g = `TOP_DESIGN.sparc5.lsu.dctl.mbar_inst0_g;
wire spc5_mbar_inst1_g = `TOP_DESIGN.sparc5.lsu.dctl.mbar_inst1_g;
wire spc5_mbar_inst2_g = `TOP_DESIGN.sparc5.lsu.dctl.mbar_inst2_g;
wire spc5_mbar_inst3_g = `TOP_DESIGN.sparc5.lsu.dctl.mbar_inst3_g;
wire spc5_flush_inst0_g = `TOP_DESIGN.sparc5.lsu.dctl.flush_inst0_g;
wire spc5_flush_inst1_g = `TOP_DESIGN.sparc5.lsu.dctl.flush_inst1_g;
wire spc5_flush_inst2_g = `TOP_DESIGN.sparc5.lsu.dctl.flush_inst2_g;
wire spc5_flush_inst3_g = `TOP_DESIGN.sparc5.lsu.dctl.flush_inst3_g;
wire spc5_intrpt_disp_asi0_g = `TOP_DESIGN.sparc5.lsu.dctl.intrpt_disp_asi_g & (spc5_sas_thrid_w == 2'b00);
wire spc5_intrpt_disp_asi1_g = `TOP_DESIGN.sparc5.lsu.dctl.intrpt_disp_asi_g & (spc5_sas_thrid_w == 2'b01);
wire spc5_intrpt_disp_asi2_g = `TOP_DESIGN.sparc5.lsu.dctl.intrpt_disp_asi_g & (spc5_sas_thrid_w == 2'b10);
wire spc5_intrpt_disp_asi3_g = `TOP_DESIGN.sparc5.lsu.dctl.intrpt_disp_asi_g & (spc5_sas_thrid_w == 2'b11);
wire spc5_st_inst_vld_g = `TOP_DESIGN.sparc5.lsu.dctl.st_inst_vld_g;
wire spc5_non_altspace_ldst_g = `TOP_DESIGN.sparc5.lsu.dctl.non_altspace_ldst_g;
wire spc5_dctl_flush_pipe_w = `TOP_DESIGN.sparc5.lsu.dctl.dctl_flush_pipe_w;
wire [3:0] spc5_no_spc_rmo_st = `TOP_DESIGN.sparc5.lsu.dctl.no_spc_rmo_st[3:0];
wire spc5_ldst_fp_e = `TOP_DESIGN.sparc5.lsu.ifu_lsu_ldst_fp_e;
wire [2:0] spc5_stb_rdptr = `TOP_DESIGN.sparc5.lsu.stb_rwctl.stb_rdptr_l;
wire spc5_ld_l2cache_req = `TOP_DESIGN.sparc5.lsu.qctl1.ld3_l2cache_rq |
`TOP_DESIGN.sparc5.lsu.qctl1.ld2_l2cache_rq |
`TOP_DESIGN.sparc5.lsu.qctl1.ld1_l2cache_rq |
`TOP_DESIGN.sparc5.lsu.qctl1.ld0_l2cache_rq;
wire [3:0] spc5_dcache_enable = {`TOP_DESIGN.sparc5.lsu.dctl.lsu_ctl_reg0[1],
`TOP_DESIGN.sparc5.lsu.dctl.lsu_ctl_reg1[1],
`TOP_DESIGN.sparc5.lsu.dctl.lsu_ctl_reg2[1],
`TOP_DESIGN.sparc5.lsu.dctl.lsu_ctl_reg3[1]};
wire [3:0] spc5_icache_enable = `TOP_DESIGN.sparc5.lsu.lsu_ifu_icache_en[3:0];
wire spc5_dc_direct_map = `TOP_DESIGN.sparc5.lsu.dc_direct_map;
wire spc5_lsu_ifu_direct_map_l1 = `TOP_DESIGN.sparc5.lsu.lsu_ifu_direct_map_l1;
always @(spc5_dcache_enable)
$display("%0d tso_mon: spc5_dcache_enable changed to %x", $time, spc5_dcache_enable);
always @(spc5_icache_enable)
$display("%0d tso_mon: spc5_icache_enable changed to %x", $time, spc5_icache_enable);
always @(spc5_dc_direct_map)
$display("%0d tso_mon: spc5_dc_direct_map changed to %x", $time, spc5_dc_direct_map);
always @(spc5_lsu_ifu_direct_map_l1)
$display("%0d tso_mon: spc5_lsu_ifu_direct_map_l1 changed to %x", $time, spc5_lsu_ifu_direct_map_l1);
reg spc5_dva_svld_e_d1;
reg spc5_dva_rvld_e_d1;
reg [10:4] spc5_dva_rd_addr_e_d1;
reg [4:0] spc5_dva_snp_addr_e_d1;
reg spc5_lsu_snp_after_rd;
reg spc5_lsu_rd_after_snp;
reg spc5_ldst_fp_m, spc5_ldst_fp_g;
integer spc5_multiple_hits;
reg spc5_skid_d1, spc5_skid_d2, spc5_skid_d3;
initial begin
spc5_skid_d1 = 0;
spc5_skid_d2 = 0;
spc5_skid_d3 = 0;
end
always @(posedge clk)
begin
spc5_skid_d1 <= (~spc5_ifu_lsu_inv_clear & spc5_dfq_rd_advance & spc5_dfq_int_type);
spc5_skid_d2 <= spc5_skid_d1 & ~spc5_ifu_lsu_inv_clear;
spc5_skid_d3 <= spc5_skid_d2 & ~spc5_ifu_lsu_inv_clear;
// The full tracking of this condition is complicated since after the interrupt is advanced
// there may be more invalidations to the IFQ.
// All we care about is that the invalidations BEFORE the interrupt are finished.
// I provided a command line argument to disable this check.
if(spc5_skid_d3 & enable_ifu_lsu_inv_clear)
finish_test("spc", "tso_mon: spc5_ifu_lsu_inv_clear should have been clear by now", 5);
spc5_dva_svld_e_d1 <= spc5_dva_svld_e;
spc5_dva_rvld_e_d1 <= spc5_dva_rvld_e;
spc5_dva_rd_addr_e_d1 <= spc5_dva_rd_addr_e;
spc5_dva_snp_addr_e_d1 <= spc5_dva_snp_addr_e;
if(spc5_dva_svld_e_d1 & spc5_dva_rvld_e & (spc5_dva_rd_addr_e_d1[10:6] == spc5_dva_snp_addr_e[4:0]))
spc5_lsu_rd_after_snp <= 1'b1;
else
spc5_lsu_rd_after_snp <= 1'b0;
if(spc5_dva_svld_e & spc5_dva_rvld_e_d1 & (spc5_dva_rd_addr_e[10:6] == spc5_dva_snp_addr_e_d1[4:0]))
spc5_lsu_snp_after_rd <= 1'b1;
else
spc5_lsu_snp_after_rd <= 1'b0;
spc5_ldst_fp_m <= spc5_ldst_fp_e;
spc5_ldst_fp_g <= spc5_ldst_fp_m;
if(spc5_stb_data_rptr_vld & spc5_stb_data_wptr_vld & ~spc5_stbrwctl_flush_pipe_w &
(spc5_stb_data_rd_ptr == spc5_stb_data_wr_ptr) & spc5_lsu_st_pcx_rq_pick)
begin
finish_test("spc", "tso_mon: LSU stb data write and read in the same cycle", 5);
end
spc5_multiple_hits = (spc5_lsu_way_hit[3] + spc5_lsu_way_hit[2] + spc5_lsu_way_hit[1] + spc5_lsu_way_hit[0]);
if(!spc5_lsu_ifu_ldst_miss_w && (spc5_multiple_hits >1) && spc5_inst_vld_w && !spc5_dctl_flush_pipe_w && !spc5_lsu_dc_tag_pe_g_unmasked_or)
finish_test("spc", "tso_mon: LSU multiple hits ", 5);
end
wire spc5_ld_dbl = spc5_ld_inst_vld_g & spc5_ldst_dbl_g & ~spc5_quad_asi_g;
wire spc5_ld_quad = spc5_ld_inst_vld_g & spc5_ldst_dbl_g & spc5_quad_asi_g;
wire spc5_ld_other = spc5_ld_inst_vld_g & ~spc5_ldst_dbl_g;
wire spc5_ld_dbl_fp = spc5_ld_dbl & spc5_ldst_fp_g;
wire spc5_ld_other_fp = spc5_ld_other & spc5_ldst_fp_g;
wire spc5_ld_dbl_int = spc5_ld_dbl & ~spc5_ldst_fp_g;
wire spc5_ld_quad_int = spc5_ld_quad & ~spc5_ldst_fp_g;
wire spc5_ld_other_int= spc5_ld_other & ~spc5_ldst_fp_g;
wire spc5_ld_bypassok_hit = |spc5_stb_ld_full_raw[7:0] & ~spc5_stb_cam_mhit;
wire spc5_ld_partial_hit = |spc5_stb_ld_partial_raw[7:0] & ~spc5_stb_cam_mhit;
wire spc5_ld_multiple_hit = spc5_stb_cam_mhit;
wire spc5_any_lsu_way_hit = |spc5_lsu_way_hit;
wire [7:0] spc5_stb_rdptr_decoded = (spc5_stb_rdptr ==3'b000) ? 8'b00000001 :
(spc5_stb_rdptr ==3'b001) ? 8'b00000010 :
(spc5_stb_rdptr ==3'b010) ? 8'b00000100 :
(spc5_stb_rdptr ==3'b011) ? 8'b00001000 :
(spc5_stb_rdptr ==3'b100) ? 8'b00010000 :
(spc5_stb_rdptr ==3'b101) ? 8'b00100000 :
(spc5_stb_rdptr ==3'b110) ? 8'b01000000 :
(spc5_stb_rdptr ==3'b111) ? 8'b10000000 : 8'h00;
wire spc5_stb_top_hit = |(spc5_stb_rdptr_decoded & (spc5_stb_ld_full_raw | spc5_stb_ld_partial_raw));
//---------------------------------------------------------------------
// ld_type[4:0] hit_type[2:0], cache_hit, hit_top
// this is passed to the coverage monitor.
//---------------------------------------------------------------------
wire [10:0] spc5_stb_ld_hit_info =
{spc5_ld_dbl_fp, spc5_ld_other_fp,
spc5_ld_dbl_int, spc5_ld_quad_int, spc5_ld_other_int,
spc5_ld_bypassok_hit, spc5_ld_partial_hit, spc5_ld_multiple_hit,
spc5_any_lsu_way_hit,
spc5_stb_top_hit, C5_st_ack_w};
reg spc5_mbar0_active;
reg spc5_mbar1_active;
reg spc5_mbar2_active;
reg spc5_mbar3_active;
reg spc5_flush0_active;
reg spc5_flush1_active;
reg spc5_flush2_active;
reg spc5_flush3_active;
reg spc5_intr0_active;
reg spc5_intr1_active;
reg spc5_intr2_active;
reg spc5_intr3_active;
always @(negedge clk)
begin
if(~rst_l)
begin
spc5_mbar0_active <= 1'b0;
spc5_mbar1_active <= 1'b0;
spc5_mbar2_active <= 1'b0;
spc5_mbar3_active <= 1'b0;
spc5_flush0_active <= 1'b0;
spc5_flush1_active <= 1'b0;
spc5_flush2_active <= 1'b0;
spc5_flush3_active <= 1'b0;
spc5_intr0_active <= 1'b0;
spc5_intr1_active <= 1'b0;
spc5_intr2_active <= 1'b0;
spc5_intr3_active <= 1'b0;
end
else
begin
if(spc5_mbar_inst0_g & ~spc5_dctl_flush_pipe_w & (C5T0_stb_ne|~spc5_no_spc_rmo_st[0]))
spc5_mbar0_active <= 1'b1;
else if(~C5T0_stb_ne & spc5_no_spc_rmo_st[0])
spc5_mbar0_active <= 1'b0;
if(spc5_mbar_inst1_g & ~ spc5_dctl_flush_pipe_w & (C5T1_stb_ne|~spc5_no_spc_rmo_st[1]))
spc5_mbar1_active <= 1'b1;
else if(~C5T1_stb_ne & spc5_no_spc_rmo_st[1])
spc5_mbar1_active <= 1'b0;
if(spc5_mbar_inst2_g & ~ spc5_dctl_flush_pipe_w & (C5T2_stb_ne|~spc5_no_spc_rmo_st[2]))
spc5_mbar2_active <= 1'b1;
else if(~C5T2_stb_ne & spc5_no_spc_rmo_st[2])
spc5_mbar2_active <= 1'b0;
if(spc5_mbar_inst3_g & ~ spc5_dctl_flush_pipe_w & (C5T3_stb_ne|~spc5_no_spc_rmo_st[3]))
spc5_mbar3_active <= 1'b1;
else if(~C5T3_stb_ne & spc5_no_spc_rmo_st[3])
spc5_mbar3_active <= 1'b0;
if(spc5_flush_inst0_g & ~spc5_dctl_flush_pipe_w & C5T0_stb_ne) spc5_flush0_active <= 1'b1;
else if(~C5T0_stb_ne) spc5_flush0_active <= 1'b0;
if(spc5_flush_inst1_g & ~spc5_dctl_flush_pipe_w & C5T1_stb_ne) spc5_flush1_active <= 1'b1;
else if(~C5T1_stb_ne) spc5_flush1_active <= 1'b0;
if(spc5_flush_inst2_g & ~spc5_dctl_flush_pipe_w & C5T2_stb_ne) spc5_flush2_active <= 1'b1;
else if(~C5T2_stb_ne) spc5_flush2_active <= 1'b0;
if(spc5_flush_inst3_g & ~spc5_dctl_flush_pipe_w & C5T3_stb_ne) spc5_flush3_active <= 1'b1;
else if(~C5T3_stb_ne) spc5_flush3_active <= 1'b0;
if(spc5_intrpt_disp_asi0_g & spc5_st_inst_vld_g & ~spc5_non_altspace_ldst_g & ~spc5_dctl_flush_pipe_w & C5T0_stb_ne)
spc5_intr0_active <= 1'b1;
else if(~C5T0_stb_ne)
spc5_intr0_active <= 1'b0;
if(spc5_intrpt_disp_asi1_g & spc5_st_inst_vld_g & ~spc5_non_altspace_ldst_g & ~spc5_dctl_flush_pipe_w & C5T1_stb_ne)
spc5_intr1_active <= 1'b1;
else if(~C5T1_stb_ne)
spc5_intr1_active <= 1'b0;
if(spc5_intrpt_disp_asi2_g & spc5_st_inst_vld_g & ~spc5_non_altspace_ldst_g & ~spc5_dctl_flush_pipe_w & C5T2_stb_ne)
spc5_intr2_active <= 1'b1;
else if(~C5T2_stb_ne)
spc5_intr2_active <= 1'b0;
if(spc5_intrpt_disp_asi3_g & spc5_st_inst_vld_g & ~spc5_non_altspace_ldst_g & ~spc5_dctl_flush_pipe_w & C5T3_stb_ne)
spc5_intr3_active <= 1'b1;
else if(~C5T3_stb_ne)
spc5_intr3_active <= 1'b0;
end
if(spc5_mbar0_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "membar violation thread 0", 5);
if(spc5_mbar1_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "membar violation thread 1", 5);
if(spc5_mbar2_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "membar violation thread 2", 5);
if(spc5_mbar3_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "membar violation thread 3", 5);
if(spc5_flush0_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "flush violation thread 0", 5);
if(spc5_flush1_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "flush violation thread 1", 5);
if(spc5_flush2_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "flush violation thread 2", 5);
if(spc5_flush3_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "flush violation thread 3", 5);
if(spc5_intr0_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "intr violation thread 0", 5);
if(spc5_intr1_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "intr violation thread 1", 5);
if(spc5_intr2_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "intr violation thread 2", 5);
if(spc5_intr3_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "intr violation thread 3", 5);
if(~rst_l | ~C5T0_stb_full | sctag_pcx_stall_pq) C5T0_stb_drain_cnt = 0;
else C5T0_stb_drain_cnt = C5T0_stb_drain_cnt + 1;
if(C5T0_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 0 is not draining", 5);
if(~rst_l | ~C5T1_stb_full | sctag_pcx_stall_pq) C5T1_stb_drain_cnt = 0;
else C5T1_stb_drain_cnt = C5T1_stb_drain_cnt + 1;
if(C5T1_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 1 is not draining", 5);
if(~rst_l | ~C5T2_stb_full | sctag_pcx_stall_pq) C5T2_stb_drain_cnt = 0;
else C5T2_stb_drain_cnt = C5T2_stb_drain_cnt + 1;
if(C5T2_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 2 is not draining", 5);
if(~rst_l | ~C5T3_stb_full | sctag_pcx_stall_pq) C5T3_stb_drain_cnt = 0;
else C5T3_stb_drain_cnt = C5T3_stb_drain_cnt + 1;
if(C5T3_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 3 is not draining", 5);
C5T0_stb_vld_sum_d1 <= C5T0_stb_vld_sum;
C5T1_stb_vld_sum_d1 <= C5T1_stb_vld_sum;
C5T2_stb_vld_sum_d1 <= C5T2_stb_vld_sum;
C5T3_stb_vld_sum_d1 <= C5T3_stb_vld_sum;
C5T0_defr_trp_en_d1 <= C5T0_defr_trp_en;
C5T1_defr_trp_en_d1 <= C5T1_defr_trp_en;
C5T2_defr_trp_en_d1 <= C5T2_defr_trp_en;
C5T3_defr_trp_en_d1 <= C5T3_defr_trp_en;
if(rst_l & C5T0_defr_trp_en_d1 & (C5T0_stb_vld_sum_d1 < C5T0_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T0", 5);
if(rst_l & C5T1_defr_trp_en_d1 & (C5T1_stb_vld_sum_d1 < C5T1_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T1", 5);
if(rst_l & C5T2_defr_trp_en_d1 & (C5T2_stb_vld_sum_d1 < C5T2_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T2", 5);
if(rst_l & C5T3_defr_trp_en_d1 & (C5T3_stb_vld_sum_d1 < C5T3_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T3", 5);
end
`endif // ifdef RTL_SPARC5
`ifdef RTL_SPARC6
wire C6T0_stb_ne = |`TOP_DESIGN.sparc6.lsu.stb_ctl0.stb_state_vld[7:0];
wire C6T1_stb_ne = |`TOP_DESIGN.sparc6.lsu.stb_ctl1.stb_state_vld[7:0];
wire C6T2_stb_ne = |`TOP_DESIGN.sparc6.lsu.stb_ctl2.stb_state_vld[7:0];
wire C6T3_stb_ne = |`TOP_DESIGN.sparc6.lsu.stb_ctl3.stb_state_vld[7:0];
wire C6T0_stb_nced = |( `TOP_DESIGN.sparc6.lsu.stb_ctl0.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc6.lsu.stb_ctl0.stb_state_ced[7:0]);
wire C6T1_stb_nced = |( `TOP_DESIGN.sparc6.lsu.stb_ctl1.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc6.lsu.stb_ctl1.stb_state_ced[7:0]);
wire C6T2_stb_nced = |( `TOP_DESIGN.sparc6.lsu.stb_ctl2.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc6.lsu.stb_ctl2.stb_state_ced[7:0]);
wire C6T3_stb_nced = |( `TOP_DESIGN.sparc6.lsu.stb_ctl3.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc6.lsu.stb_ctl3.stb_state_ced[7:0]);
`else
wire C6T0_stb_ne = 1'b0;
wire C6T1_stb_ne = 1'b0;
wire C6T2_stb_ne = 1'b0;
wire C6T3_stb_ne = 1'b0;
wire C6T0_stb_nced = 1'b0;
wire C6T1_stb_nced = 1'b0;
wire C6T2_stb_nced = 1'b0;
wire C6T3_stb_nced = 1'b0;
`endif // ifdef RTL_SPARC6
`ifdef RTL_SPARC6
wire spc6_lsu_ifill_pkt_vld = `TOP_DESIGN.sparc6.lsu.qctl2.lsu_ifill_pkt_vld;
wire spc6_dfq_rd_advance = `TOP_DESIGN.sparc6.lsu.qctl2.dfq_rd_advance;
wire spc6_dfq_int_type = `TOP_DESIGN.sparc6.lsu.qctl2.dfq_int_type;
wire spc6_ifu_lsu_inv_clear = `TOP_DESIGN.sparc6.lsu.qctl2.ifu_lsu_inv_clear;
wire spc6_dva_svld_e = `TOP_DESIGN.sparc6.lsu.qctl2.dva_svld_e;
wire spc6_dva_rvld_e = `TOP_DESIGN.sparc6.lsu.dva.rd_en;
wire [10:4] spc6_dva_rd_addr_e = `TOP_DESIGN.sparc6.lsu.dva.rd_adr1[6:0];
wire [4:0] spc6_dva_snp_addr_e = `TOP_DESIGN.sparc6.lsu.qctl2.dva_snp_addr_e[4:0];
wire [4:0] spc6_stb_data_rd_ptr = `TOP_DESIGN.sparc6.lsu.stb_data_rd_ptr[4:0];
wire [4:0] spc6_stb_data_wr_ptr = `TOP_DESIGN.sparc6.lsu.stb_data_wr_ptr[4:0];
wire spc6_stb_data_wptr_vld = `TOP_DESIGN.sparc6.lsu.stb_data_wptr_vld;
wire spc6_stb_data_rptr_vld = `TOP_DESIGN.sparc6.lsu.stb_data_rptr_vld;
wire spc6_stbrwctl_flush_pipe_w = `TOP_DESIGN.sparc6.lsu.stb_rwctl.lsu_stbrwctl_flush_pipe_w;
wire spc6_lsu_st_pcx_rq_pick = |`TOP_DESIGN.sparc6.lsu.stb_rwctl.lsu_st_pcx_rq_pick[3:0];
wire [3:0] spc6_lsu_rd_dtag_parity_g = `TOP_DESIGN.sparc6.lsu.dctl.lsu_rd_dtag_parity_g[3:0];
wire [3:0] spc6_dva_vld_g = `TOP_DESIGN.sparc6.lsu.dctl.dva_vld_g[3:0];
wire [3:0] spc6_lsu_dc_tag_pe_g_unmasked = spc6_lsu_rd_dtag_parity_g[3:0] & spc6_dva_vld_g[3:0];
wire spc6_lsu_dc_tag_pe_g_unmasked_or = |spc6_lsu_dc_tag_pe_g_unmasked[3:0];
wire C6T0_stb_full = &`TOP_DESIGN.sparc6.lsu.stb_ctl0.stb_state_vld[7:0];
wire C6T1_stb_full = &`TOP_DESIGN.sparc6.lsu.stb_ctl1.stb_state_vld[7:0];
wire C6T2_stb_full = &`TOP_DESIGN.sparc6.lsu.stb_ctl2.stb_state_vld[7:0];
wire C6T3_stb_full = &`TOP_DESIGN.sparc6.lsu.stb_ctl3.stb_state_vld[7:0];
wire [7:0] C6T0_stb_vld = `TOP_DESIGN.sparc6.lsu.stb_ctl0.stb_state_vld[7:0];
wire [7:0] C6T1_stb_vld = `TOP_DESIGN.sparc6.lsu.stb_ctl1.stb_state_vld[7:0];
wire [7:0] C6T2_stb_vld = `TOP_DESIGN.sparc6.lsu.stb_ctl2.stb_state_vld[7:0];
wire [7:0] C6T3_stb_vld = `TOP_DESIGN.sparc6.lsu.stb_ctl3.stb_state_vld[7:0];
wire [4:0] C6T0_stb_vld_sum = C6T0_stb_vld[0] + C6T0_stb_vld[1] + C6T0_stb_vld[2] + C6T0_stb_vld[3] +
C6T0_stb_vld[4] + C6T0_stb_vld[5] + C6T0_stb_vld[6] + C6T0_stb_vld[7] ;
wire [4:0] C6T1_stb_vld_sum = C6T1_stb_vld[0] + C6T1_stb_vld[1] + C6T1_stb_vld[2] + C6T1_stb_vld[3] +
C6T1_stb_vld[4] + C6T1_stb_vld[5] + C6T1_stb_vld[6] + C6T1_stb_vld[7] ;
wire [4:0] C6T2_stb_vld_sum = C6T2_stb_vld[0] + C6T2_stb_vld[1] + C6T2_stb_vld[2] + C6T2_stb_vld[3] +
C6T2_stb_vld[4] + C6T2_stb_vld[5] + C6T2_stb_vld[6] + C6T2_stb_vld[7] ;
wire [4:0] C6T3_stb_vld_sum = C6T3_stb_vld[0] + C6T3_stb_vld[1] + C6T3_stb_vld[2] + C6T3_stb_vld[3] +
C6T3_stb_vld[4] + C6T3_stb_vld[5] + C6T3_stb_vld[6] + C6T3_stb_vld[7] ;
reg [4:0] C6T0_stb_vld_sum_d1;
reg [4:0] C6T1_stb_vld_sum_d1;
reg [4:0] C6T2_stb_vld_sum_d1;
reg [4:0] C6T3_stb_vld_sum_d1;
wire C6T0_st_ack = &`TOP_DESIGN.sparc6.lsu.cpx_st_ack_tid0;
wire C6T1_st_ack = &`TOP_DESIGN.sparc6.lsu.cpx_st_ack_tid1;
wire C6T2_st_ack = &`TOP_DESIGN.sparc6.lsu.cpx_st_ack_tid2;
wire C6T3_st_ack = &`TOP_DESIGN.sparc6.lsu.cpx_st_ack_tid3;
wire C6T0_defr_trp_en = &`TOP_DESIGN.sparc6.lsu.excpctl.st_defr_trp_en0;
wire C6T1_defr_trp_en = &`TOP_DESIGN.sparc6.lsu.excpctl.st_defr_trp_en1;
wire C6T2_defr_trp_en = &`TOP_DESIGN.sparc6.lsu.excpctl.st_defr_trp_en2;
wire C6T3_defr_trp_en = &`TOP_DESIGN.sparc6.lsu.excpctl.st_defr_trp_en3;
reg C6T0_defr_trp_en_d1;
reg C6T1_defr_trp_en_d1;
reg C6T2_defr_trp_en_d1;
reg C6T3_defr_trp_en_d1;
integer C6T0_stb_drain_cnt;
integer C6T1_stb_drain_cnt;
integer C6T2_stb_drain_cnt;
integer C6T3_stb_drain_cnt;
// Hits in the store buffer
//-------------------------
wire spc6_inst_vld_w = `TOP_DESIGN.sparc6.ifu.fcl.inst_vld_w;
wire [1:0] spc6_sas_thrid_w = `TOP_DESIGN.sparc6.ifu.fcl.sas_thrid_w[1:0];
wire C6_st_ack_w = (spc6_sas_thrid_w == 2'b00) & C6T0_st_ack |
(spc6_sas_thrid_w == 2'b01) & C6T1_st_ack |
(spc6_sas_thrid_w == 2'b10) & C6T2_st_ack |
(spc6_sas_thrid_w == 2'b11) & C6T3_st_ack;
wire [7:0] spc6_stb_ld_full_raw = `TOP_DESIGN.sparc6.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc6_stb_ld_partial_raw = `TOP_DESIGN.sparc6.lsu.stb_ld_partial_raw[7:0];
wire spc6_stb_cam_mhit = `TOP_DESIGN.sparc6.lsu.stb_cam_mhit;
wire spc6_stb_cam_hit = `TOP_DESIGN.sparc6.lsu.stb_cam_hit;
wire [3:0] spc6_lsu_way_hit = `TOP_DESIGN.sparc6.lsu.dctl.lsu_way_hit[3:0];
wire spc6_lsu_ifu_ldst_miss_w = `TOP_DESIGN.sparc6.lsu.lsu_ifu_ldst_miss_w;
wire spc6_ld_inst_vld_g = `TOP_DESIGN.sparc6.lsu.dctl.ld_inst_vld_g;
wire spc6_ldst_dbl_g = `TOP_DESIGN.sparc6.lsu.dctl.ldst_dbl_g;
wire spc6_quad_asi_g = `TOP_DESIGN.sparc6.lsu.dctl.quad_asi_g;
wire [1:0] spc6_ldst_sz_g = `TOP_DESIGN.sparc6.lsu.dctl.ldst_sz_g;
wire spc6_lsu_alt_space_g = `TOP_DESIGN.sparc6.lsu.dctl.lsu_alt_space_g;
wire spc6_mbar_inst0_g = `TOP_DESIGN.sparc6.lsu.dctl.mbar_inst0_g;
wire spc6_mbar_inst1_g = `TOP_DESIGN.sparc6.lsu.dctl.mbar_inst1_g;
wire spc6_mbar_inst2_g = `TOP_DESIGN.sparc6.lsu.dctl.mbar_inst2_g;
wire spc6_mbar_inst3_g = `TOP_DESIGN.sparc6.lsu.dctl.mbar_inst3_g;
wire spc6_flush_inst0_g = `TOP_DESIGN.sparc6.lsu.dctl.flush_inst0_g;
wire spc6_flush_inst1_g = `TOP_DESIGN.sparc6.lsu.dctl.flush_inst1_g;
wire spc6_flush_inst2_g = `TOP_DESIGN.sparc6.lsu.dctl.flush_inst2_g;
wire spc6_flush_inst3_g = `TOP_DESIGN.sparc6.lsu.dctl.flush_inst3_g;
wire spc6_intrpt_disp_asi0_g = `TOP_DESIGN.sparc6.lsu.dctl.intrpt_disp_asi_g & (spc6_sas_thrid_w == 2'b00);
wire spc6_intrpt_disp_asi1_g = `TOP_DESIGN.sparc6.lsu.dctl.intrpt_disp_asi_g & (spc6_sas_thrid_w == 2'b01);
wire spc6_intrpt_disp_asi2_g = `TOP_DESIGN.sparc6.lsu.dctl.intrpt_disp_asi_g & (spc6_sas_thrid_w == 2'b10);
wire spc6_intrpt_disp_asi3_g = `TOP_DESIGN.sparc6.lsu.dctl.intrpt_disp_asi_g & (spc6_sas_thrid_w == 2'b11);
wire spc6_st_inst_vld_g = `TOP_DESIGN.sparc6.lsu.dctl.st_inst_vld_g;
wire spc6_non_altspace_ldst_g = `TOP_DESIGN.sparc6.lsu.dctl.non_altspace_ldst_g;
wire spc6_dctl_flush_pipe_w = `TOP_DESIGN.sparc6.lsu.dctl.dctl_flush_pipe_w;
wire [3:0] spc6_no_spc_rmo_st = `TOP_DESIGN.sparc6.lsu.dctl.no_spc_rmo_st[3:0];
wire spc6_ldst_fp_e = `TOP_DESIGN.sparc6.lsu.ifu_lsu_ldst_fp_e;
wire [2:0] spc6_stb_rdptr = `TOP_DESIGN.sparc6.lsu.stb_rwctl.stb_rdptr_l;
wire spc6_ld_l2cache_req = `TOP_DESIGN.sparc6.lsu.qctl1.ld3_l2cache_rq |
`TOP_DESIGN.sparc6.lsu.qctl1.ld2_l2cache_rq |
`TOP_DESIGN.sparc6.lsu.qctl1.ld1_l2cache_rq |
`TOP_DESIGN.sparc6.lsu.qctl1.ld0_l2cache_rq;
wire [3:0] spc6_dcache_enable = {`TOP_DESIGN.sparc6.lsu.dctl.lsu_ctl_reg0[1],
`TOP_DESIGN.sparc6.lsu.dctl.lsu_ctl_reg1[1],
`TOP_DESIGN.sparc6.lsu.dctl.lsu_ctl_reg2[1],
`TOP_DESIGN.sparc6.lsu.dctl.lsu_ctl_reg3[1]};
wire [3:0] spc6_icache_enable = `TOP_DESIGN.sparc6.lsu.lsu_ifu_icache_en[3:0];
wire spc6_dc_direct_map = `TOP_DESIGN.sparc6.lsu.dc_direct_map;
wire spc6_lsu_ifu_direct_map_l1 = `TOP_DESIGN.sparc6.lsu.lsu_ifu_direct_map_l1;
always @(spc6_dcache_enable)
$display("%0d tso_mon: spc6_dcache_enable changed to %x", $time, spc6_dcache_enable);
always @(spc6_icache_enable)
$display("%0d tso_mon: spc6_icache_enable changed to %x", $time, spc6_icache_enable);
always @(spc6_dc_direct_map)
$display("%0d tso_mon: spc6_dc_direct_map changed to %x", $time, spc6_dc_direct_map);
always @(spc6_lsu_ifu_direct_map_l1)
$display("%0d tso_mon: spc6_lsu_ifu_direct_map_l1 changed to %x", $time, spc6_lsu_ifu_direct_map_l1);
reg spc6_dva_svld_e_d1;
reg spc6_dva_rvld_e_d1;
reg [10:4] spc6_dva_rd_addr_e_d1;
reg [4:0] spc6_dva_snp_addr_e_d1;
reg spc6_lsu_snp_after_rd;
reg spc6_lsu_rd_after_snp;
reg spc6_ldst_fp_m, spc6_ldst_fp_g;
integer spc6_multiple_hits;
reg spc6_skid_d1, spc6_skid_d2, spc6_skid_d3;
initial begin
spc6_skid_d1 = 0;
spc6_skid_d2 = 0;
spc6_skid_d3 = 0;
end
always @(posedge clk)
begin
spc6_skid_d1 <= (~spc6_ifu_lsu_inv_clear & spc6_dfq_rd_advance & spc6_dfq_int_type);
spc6_skid_d2 <= spc6_skid_d1 & ~spc6_ifu_lsu_inv_clear;
spc6_skid_d3 <= spc6_skid_d2 & ~spc6_ifu_lsu_inv_clear;
// The full tracking of this condition is complicated since after the interrupt is advanced
// there may be more invalidations to the IFQ.
// All we care about is that the invalidations BEFORE the interrupt are finished.
// I provided a command line argument to disable this check.
if(spc6_skid_d3 & enable_ifu_lsu_inv_clear)
finish_test("spc", "tso_mon: spc6_ifu_lsu_inv_clear should have been clear by now", 6);
spc6_dva_svld_e_d1 <= spc6_dva_svld_e;
spc6_dva_rvld_e_d1 <= spc6_dva_rvld_e;
spc6_dva_rd_addr_e_d1 <= spc6_dva_rd_addr_e;
spc6_dva_snp_addr_e_d1 <= spc6_dva_snp_addr_e;
if(spc6_dva_svld_e_d1 & spc6_dva_rvld_e & (spc6_dva_rd_addr_e_d1[10:6] == spc6_dva_snp_addr_e[4:0]))
spc6_lsu_rd_after_snp <= 1'b1;
else
spc6_lsu_rd_after_snp <= 1'b0;
if(spc6_dva_svld_e & spc6_dva_rvld_e_d1 & (spc6_dva_rd_addr_e[10:6] == spc6_dva_snp_addr_e_d1[4:0]))
spc6_lsu_snp_after_rd <= 1'b1;
else
spc6_lsu_snp_after_rd <= 1'b0;
spc6_ldst_fp_m <= spc6_ldst_fp_e;
spc6_ldst_fp_g <= spc6_ldst_fp_m;
if(spc6_stb_data_rptr_vld & spc6_stb_data_wptr_vld & ~spc6_stbrwctl_flush_pipe_w &
(spc6_stb_data_rd_ptr == spc6_stb_data_wr_ptr) & spc6_lsu_st_pcx_rq_pick)
begin
finish_test("spc", "tso_mon: LSU stb data write and read in the same cycle", 6);
end
spc6_multiple_hits = (spc6_lsu_way_hit[3] + spc6_lsu_way_hit[2] + spc6_lsu_way_hit[1] + spc6_lsu_way_hit[0]);
if(!spc6_lsu_ifu_ldst_miss_w && (spc6_multiple_hits >1) && spc6_inst_vld_w && !spc6_dctl_flush_pipe_w && !spc6_lsu_dc_tag_pe_g_unmasked_or)
finish_test("spc", "tso_mon: LSU multiple hits ", 6);
end
wire spc6_ld_dbl = spc6_ld_inst_vld_g & spc6_ldst_dbl_g & ~spc6_quad_asi_g;
wire spc6_ld_quad = spc6_ld_inst_vld_g & spc6_ldst_dbl_g & spc6_quad_asi_g;
wire spc6_ld_other = spc6_ld_inst_vld_g & ~spc6_ldst_dbl_g;
wire spc6_ld_dbl_fp = spc6_ld_dbl & spc6_ldst_fp_g;
wire spc6_ld_other_fp = spc6_ld_other & spc6_ldst_fp_g;
wire spc6_ld_dbl_int = spc6_ld_dbl & ~spc6_ldst_fp_g;
wire spc6_ld_quad_int = spc6_ld_quad & ~spc6_ldst_fp_g;
wire spc6_ld_other_int= spc6_ld_other & ~spc6_ldst_fp_g;
wire spc6_ld_bypassok_hit = |spc6_stb_ld_full_raw[7:0] & ~spc6_stb_cam_mhit;
wire spc6_ld_partial_hit = |spc6_stb_ld_partial_raw[7:0] & ~spc6_stb_cam_mhit;
wire spc6_ld_multiple_hit = spc6_stb_cam_mhit;
wire spc6_any_lsu_way_hit = |spc6_lsu_way_hit;
wire [7:0] spc6_stb_rdptr_decoded = (spc6_stb_rdptr ==3'b000) ? 8'b00000001 :
(spc6_stb_rdptr ==3'b001) ? 8'b00000010 :
(spc6_stb_rdptr ==3'b010) ? 8'b00000100 :
(spc6_stb_rdptr ==3'b011) ? 8'b00001000 :
(spc6_stb_rdptr ==3'b100) ? 8'b00010000 :
(spc6_stb_rdptr ==3'b101) ? 8'b00100000 :
(spc6_stb_rdptr ==3'b110) ? 8'b01000000 :
(spc6_stb_rdptr ==3'b111) ? 8'b10000000 : 8'h00;
wire spc6_stb_top_hit = |(spc6_stb_rdptr_decoded & (spc6_stb_ld_full_raw | spc6_stb_ld_partial_raw));
//---------------------------------------------------------------------
// ld_type[4:0] hit_type[2:0], cache_hit, hit_top
// this is passed to the coverage monitor.
//---------------------------------------------------------------------
wire [10:0] spc6_stb_ld_hit_info =
{spc6_ld_dbl_fp, spc6_ld_other_fp,
spc6_ld_dbl_int, spc6_ld_quad_int, spc6_ld_other_int,
spc6_ld_bypassok_hit, spc6_ld_partial_hit, spc6_ld_multiple_hit,
spc6_any_lsu_way_hit,
spc6_stb_top_hit, C6_st_ack_w};
reg spc6_mbar0_active;
reg spc6_mbar1_active;
reg spc6_mbar2_active;
reg spc6_mbar3_active;
reg spc6_flush0_active;
reg spc6_flush1_active;
reg spc6_flush2_active;
reg spc6_flush3_active;
reg spc6_intr0_active;
reg spc6_intr1_active;
reg spc6_intr2_active;
reg spc6_intr3_active;
always @(negedge clk)
begin
if(~rst_l)
begin
spc6_mbar0_active <= 1'b0;
spc6_mbar1_active <= 1'b0;
spc6_mbar2_active <= 1'b0;
spc6_mbar3_active <= 1'b0;
spc6_flush0_active <= 1'b0;
spc6_flush1_active <= 1'b0;
spc6_flush2_active <= 1'b0;
spc6_flush3_active <= 1'b0;
spc6_intr0_active <= 1'b0;
spc6_intr1_active <= 1'b0;
spc6_intr2_active <= 1'b0;
spc6_intr3_active <= 1'b0;
end
else
begin
if(spc6_mbar_inst0_g & ~spc6_dctl_flush_pipe_w & (C6T0_stb_ne|~spc6_no_spc_rmo_st[0]))
spc6_mbar0_active <= 1'b1;
else if(~C6T0_stb_ne & spc6_no_spc_rmo_st[0])
spc6_mbar0_active <= 1'b0;
if(spc6_mbar_inst1_g & ~ spc6_dctl_flush_pipe_w & (C6T1_stb_ne|~spc6_no_spc_rmo_st[1]))
spc6_mbar1_active <= 1'b1;
else if(~C6T1_stb_ne & spc6_no_spc_rmo_st[1])
spc6_mbar1_active <= 1'b0;
if(spc6_mbar_inst2_g & ~ spc6_dctl_flush_pipe_w & (C6T2_stb_ne|~spc6_no_spc_rmo_st[2]))
spc6_mbar2_active <= 1'b1;
else if(~C6T2_stb_ne & spc6_no_spc_rmo_st[2])
spc6_mbar2_active <= 1'b0;
if(spc6_mbar_inst3_g & ~ spc6_dctl_flush_pipe_w & (C6T3_stb_ne|~spc6_no_spc_rmo_st[3]))
spc6_mbar3_active <= 1'b1;
else if(~C6T3_stb_ne & spc6_no_spc_rmo_st[3])
spc6_mbar3_active <= 1'b0;
if(spc6_flush_inst0_g & ~spc6_dctl_flush_pipe_w & C6T0_stb_ne) spc6_flush0_active <= 1'b1;
else if(~C6T0_stb_ne) spc6_flush0_active <= 1'b0;
if(spc6_flush_inst1_g & ~spc6_dctl_flush_pipe_w & C6T1_stb_ne) spc6_flush1_active <= 1'b1;
else if(~C6T1_stb_ne) spc6_flush1_active <= 1'b0;
if(spc6_flush_inst2_g & ~spc6_dctl_flush_pipe_w & C6T2_stb_ne) spc6_flush2_active <= 1'b1;
else if(~C6T2_stb_ne) spc6_flush2_active <= 1'b0;
if(spc6_flush_inst3_g & ~spc6_dctl_flush_pipe_w & C6T3_stb_ne) spc6_flush3_active <= 1'b1;
else if(~C6T3_stb_ne) spc6_flush3_active <= 1'b0;
if(spc6_intrpt_disp_asi0_g & spc6_st_inst_vld_g & ~spc6_non_altspace_ldst_g & ~spc6_dctl_flush_pipe_w & C6T0_stb_ne)
spc6_intr0_active <= 1'b1;
else if(~C6T0_stb_ne)
spc6_intr0_active <= 1'b0;
if(spc6_intrpt_disp_asi1_g & spc6_st_inst_vld_g & ~spc6_non_altspace_ldst_g & ~spc6_dctl_flush_pipe_w & C6T1_stb_ne)
spc6_intr1_active <= 1'b1;
else if(~C6T1_stb_ne)
spc6_intr1_active <= 1'b0;
if(spc6_intrpt_disp_asi2_g & spc6_st_inst_vld_g & ~spc6_non_altspace_ldst_g & ~spc6_dctl_flush_pipe_w & C6T2_stb_ne)
spc6_intr2_active <= 1'b1;
else if(~C6T2_stb_ne)
spc6_intr2_active <= 1'b0;
if(spc6_intrpt_disp_asi3_g & spc6_st_inst_vld_g & ~spc6_non_altspace_ldst_g & ~spc6_dctl_flush_pipe_w & C6T3_stb_ne)
spc6_intr3_active <= 1'b1;
else if(~C6T3_stb_ne)
spc6_intr3_active <= 1'b0;
end
if(spc6_mbar0_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "membar violation thread 0", 6);
if(spc6_mbar1_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "membar violation thread 1", 6);
if(spc6_mbar2_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "membar violation thread 2", 6);
if(spc6_mbar3_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "membar violation thread 3", 6);
if(spc6_flush0_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "flush violation thread 0", 6);
if(spc6_flush1_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "flush violation thread 1", 6);
if(spc6_flush2_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "flush violation thread 2", 6);
if(spc6_flush3_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "flush violation thread 3", 6);
if(spc6_intr0_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "intr violation thread 0", 6);
if(spc6_intr1_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "intr violation thread 1", 6);
if(spc6_intr2_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "intr violation thread 2", 6);
if(spc6_intr3_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "intr violation thread 3", 6);
if(~rst_l | ~C6T0_stb_full | sctag_pcx_stall_pq) C6T0_stb_drain_cnt = 0;
else C6T0_stb_drain_cnt = C6T0_stb_drain_cnt + 1;
if(C6T0_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 0 is not draining", 6);
if(~rst_l | ~C6T1_stb_full | sctag_pcx_stall_pq) C6T1_stb_drain_cnt = 0;
else C6T1_stb_drain_cnt = C6T1_stb_drain_cnt + 1;
if(C6T1_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 1 is not draining", 6);
if(~rst_l | ~C6T2_stb_full | sctag_pcx_stall_pq) C6T2_stb_drain_cnt = 0;
else C6T2_stb_drain_cnt = C6T2_stb_drain_cnt + 1;
if(C6T2_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 2 is not draining", 6);
if(~rst_l | ~C6T3_stb_full | sctag_pcx_stall_pq) C6T3_stb_drain_cnt = 0;
else C6T3_stb_drain_cnt = C6T3_stb_drain_cnt + 1;
if(C6T3_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 3 is not draining", 6);
C6T0_stb_vld_sum_d1 <= C6T0_stb_vld_sum;
C6T1_stb_vld_sum_d1 <= C6T1_stb_vld_sum;
C6T2_stb_vld_sum_d1 <= C6T2_stb_vld_sum;
C6T3_stb_vld_sum_d1 <= C6T3_stb_vld_sum;
C6T0_defr_trp_en_d1 <= C6T0_defr_trp_en;
C6T1_defr_trp_en_d1 <= C6T1_defr_trp_en;
C6T2_defr_trp_en_d1 <= C6T2_defr_trp_en;
C6T3_defr_trp_en_d1 <= C6T3_defr_trp_en;
if(rst_l & C6T0_defr_trp_en_d1 & (C6T0_stb_vld_sum_d1 < C6T0_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T0", 6);
if(rst_l & C6T1_defr_trp_en_d1 & (C6T1_stb_vld_sum_d1 < C6T1_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T1", 6);
if(rst_l & C6T2_defr_trp_en_d1 & (C6T2_stb_vld_sum_d1 < C6T2_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T2", 6);
if(rst_l & C6T3_defr_trp_en_d1 & (C6T3_stb_vld_sum_d1 < C6T3_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T3", 6);
end
`endif // ifdef RTL_SPARC6
`ifdef RTL_SPARC7
wire C7T0_stb_ne = |`TOP_DESIGN.sparc7.lsu.stb_ctl0.stb_state_vld[7:0];
wire C7T1_stb_ne = |`TOP_DESIGN.sparc7.lsu.stb_ctl1.stb_state_vld[7:0];
wire C7T2_stb_ne = |`TOP_DESIGN.sparc7.lsu.stb_ctl2.stb_state_vld[7:0];
wire C7T3_stb_ne = |`TOP_DESIGN.sparc7.lsu.stb_ctl3.stb_state_vld[7:0];
wire C7T0_stb_nced = |( `TOP_DESIGN.sparc7.lsu.stb_ctl0.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc7.lsu.stb_ctl0.stb_state_ced[7:0]);
wire C7T1_stb_nced = |( `TOP_DESIGN.sparc7.lsu.stb_ctl1.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc7.lsu.stb_ctl1.stb_state_ced[7:0]);
wire C7T2_stb_nced = |( `TOP_DESIGN.sparc7.lsu.stb_ctl2.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc7.lsu.stb_ctl2.stb_state_ced[7:0]);
wire C7T3_stb_nced = |( `TOP_DESIGN.sparc7.lsu.stb_ctl3.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc7.lsu.stb_ctl3.stb_state_ced[7:0]);
`else
wire C7T0_stb_ne = 1'b0;
wire C7T1_stb_ne = 1'b0;
wire C7T2_stb_ne = 1'b0;
wire C7T3_stb_ne = 1'b0;
wire C7T0_stb_nced = 1'b0;
wire C7T1_stb_nced = 1'b0;
wire C7T2_stb_nced = 1'b0;
wire C7T3_stb_nced = 1'b0;
`endif // ifdef RTL_SPARC7
`ifdef RTL_SPARC7
wire spc7_lsu_ifill_pkt_vld = `TOP_DESIGN.sparc7.lsu.qctl2.lsu_ifill_pkt_vld;
wire spc7_dfq_rd_advance = `TOP_DESIGN.sparc7.lsu.qctl2.dfq_rd_advance;
wire spc7_dfq_int_type = `TOP_DESIGN.sparc7.lsu.qctl2.dfq_int_type;
wire spc7_ifu_lsu_inv_clear = `TOP_DESIGN.sparc7.lsu.qctl2.ifu_lsu_inv_clear;
wire spc7_dva_svld_e = `TOP_DESIGN.sparc7.lsu.qctl2.dva_svld_e;
wire spc7_dva_rvld_e = `TOP_DESIGN.sparc7.lsu.dva.rd_en;
wire [10:4] spc7_dva_rd_addr_e = `TOP_DESIGN.sparc7.lsu.dva.rd_adr1[6:0];
wire [4:0] spc7_dva_snp_addr_e = `TOP_DESIGN.sparc7.lsu.qctl2.dva_snp_addr_e[4:0];
wire [4:0] spc7_stb_data_rd_ptr = `TOP_DESIGN.sparc7.lsu.stb_data_rd_ptr[4:0];
wire [4:0] spc7_stb_data_wr_ptr = `TOP_DESIGN.sparc7.lsu.stb_data_wr_ptr[4:0];
wire spc7_stb_data_wptr_vld = `TOP_DESIGN.sparc7.lsu.stb_data_wptr_vld;
wire spc7_stb_data_rptr_vld = `TOP_DESIGN.sparc7.lsu.stb_data_rptr_vld;
wire spc7_stbrwctl_flush_pipe_w = `TOP_DESIGN.sparc7.lsu.stb_rwctl.lsu_stbrwctl_flush_pipe_w;
wire spc7_lsu_st_pcx_rq_pick = |`TOP_DESIGN.sparc7.lsu.stb_rwctl.lsu_st_pcx_rq_pick[3:0];
wire [3:0] spc7_lsu_rd_dtag_parity_g = `TOP_DESIGN.sparc7.lsu.dctl.lsu_rd_dtag_parity_g[3:0];
wire [3:0] spc7_dva_vld_g = `TOP_DESIGN.sparc7.lsu.dctl.dva_vld_g[3:0];
wire [3:0] spc7_lsu_dc_tag_pe_g_unmasked = spc7_lsu_rd_dtag_parity_g[3:0] & spc7_dva_vld_g[3:0];
wire spc7_lsu_dc_tag_pe_g_unmasked_or = |spc7_lsu_dc_tag_pe_g_unmasked[3:0];
wire C7T0_stb_full = &`TOP_DESIGN.sparc7.lsu.stb_ctl0.stb_state_vld[7:0];
wire C7T1_stb_full = &`TOP_DESIGN.sparc7.lsu.stb_ctl1.stb_state_vld[7:0];
wire C7T2_stb_full = &`TOP_DESIGN.sparc7.lsu.stb_ctl2.stb_state_vld[7:0];
wire C7T3_stb_full = &`TOP_DESIGN.sparc7.lsu.stb_ctl3.stb_state_vld[7:0];
wire [7:0] C7T0_stb_vld = `TOP_DESIGN.sparc7.lsu.stb_ctl0.stb_state_vld[7:0];
wire [7:0] C7T1_stb_vld = `TOP_DESIGN.sparc7.lsu.stb_ctl1.stb_state_vld[7:0];
wire [7:0] C7T2_stb_vld = `TOP_DESIGN.sparc7.lsu.stb_ctl2.stb_state_vld[7:0];
wire [7:0] C7T3_stb_vld = `TOP_DESIGN.sparc7.lsu.stb_ctl3.stb_state_vld[7:0];
wire [4:0] C7T0_stb_vld_sum = C7T0_stb_vld[0] + C7T0_stb_vld[1] + C7T0_stb_vld[2] + C7T0_stb_vld[3] +
C7T0_stb_vld[4] + C7T0_stb_vld[5] + C7T0_stb_vld[6] + C7T0_stb_vld[7] ;
wire [4:0] C7T1_stb_vld_sum = C7T1_stb_vld[0] + C7T1_stb_vld[1] + C7T1_stb_vld[2] + C7T1_stb_vld[3] +
C7T1_stb_vld[4] + C7T1_stb_vld[5] + C7T1_stb_vld[6] + C7T1_stb_vld[7] ;
wire [4:0] C7T2_stb_vld_sum = C7T2_stb_vld[0] + C7T2_stb_vld[1] + C7T2_stb_vld[2] + C7T2_stb_vld[3] +
C7T2_stb_vld[4] + C7T2_stb_vld[5] + C7T2_stb_vld[6] + C7T2_stb_vld[7] ;
wire [4:0] C7T3_stb_vld_sum = C7T3_stb_vld[0] + C7T3_stb_vld[1] + C7T3_stb_vld[2] + C7T3_stb_vld[3] +
C7T3_stb_vld[4] + C7T3_stb_vld[5] + C7T3_stb_vld[6] + C7T3_stb_vld[7] ;
reg [4:0] C7T0_stb_vld_sum_d1;
reg [4:0] C7T1_stb_vld_sum_d1;
reg [4:0] C7T2_stb_vld_sum_d1;
reg [4:0] C7T3_stb_vld_sum_d1;
wire C7T0_st_ack = &`TOP_DESIGN.sparc7.lsu.cpx_st_ack_tid0;
wire C7T1_st_ack = &`TOP_DESIGN.sparc7.lsu.cpx_st_ack_tid1;
wire C7T2_st_ack = &`TOP_DESIGN.sparc7.lsu.cpx_st_ack_tid2;
wire C7T3_st_ack = &`TOP_DESIGN.sparc7.lsu.cpx_st_ack_tid3;
wire C7T0_defr_trp_en = &`TOP_DESIGN.sparc7.lsu.excpctl.st_defr_trp_en0;
wire C7T1_defr_trp_en = &`TOP_DESIGN.sparc7.lsu.excpctl.st_defr_trp_en1;
wire C7T2_defr_trp_en = &`TOP_DESIGN.sparc7.lsu.excpctl.st_defr_trp_en2;
wire C7T3_defr_trp_en = &`TOP_DESIGN.sparc7.lsu.excpctl.st_defr_trp_en3;
reg C7T0_defr_trp_en_d1;
reg C7T1_defr_trp_en_d1;
reg C7T2_defr_trp_en_d1;
reg C7T3_defr_trp_en_d1;
integer C7T0_stb_drain_cnt;
integer C7T1_stb_drain_cnt;
integer C7T2_stb_drain_cnt;
integer C7T3_stb_drain_cnt;
// Hits in the store buffer
//-------------------------
wire spc7_inst_vld_w = `TOP_DESIGN.sparc7.ifu.fcl.inst_vld_w;
wire [1:0] spc7_sas_thrid_w = `TOP_DESIGN.sparc7.ifu.fcl.sas_thrid_w[1:0];
wire C7_st_ack_w = (spc7_sas_thrid_w == 2'b00) & C7T0_st_ack |
(spc7_sas_thrid_w == 2'b01) & C7T1_st_ack |
(spc7_sas_thrid_w == 2'b10) & C7T2_st_ack |
(spc7_sas_thrid_w == 2'b11) & C7T3_st_ack;
wire [7:0] spc7_stb_ld_full_raw = `TOP_DESIGN.sparc7.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc7_stb_ld_partial_raw = `TOP_DESIGN.sparc7.lsu.stb_ld_partial_raw[7:0];
wire spc7_stb_cam_mhit = `TOP_DESIGN.sparc7.lsu.stb_cam_mhit;
wire spc7_stb_cam_hit = `TOP_DESIGN.sparc7.lsu.stb_cam_hit;
wire [3:0] spc7_lsu_way_hit = `TOP_DESIGN.sparc7.lsu.dctl.lsu_way_hit[3:0];
wire spc7_lsu_ifu_ldst_miss_w = `TOP_DESIGN.sparc7.lsu.lsu_ifu_ldst_miss_w;
wire spc7_ld_inst_vld_g = `TOP_DESIGN.sparc7.lsu.dctl.ld_inst_vld_g;
wire spc7_ldst_dbl_g = `TOP_DESIGN.sparc7.lsu.dctl.ldst_dbl_g;
wire spc7_quad_asi_g = `TOP_DESIGN.sparc7.lsu.dctl.quad_asi_g;
wire [1:0] spc7_ldst_sz_g = `TOP_DESIGN.sparc7.lsu.dctl.ldst_sz_g;
wire spc7_lsu_alt_space_g = `TOP_DESIGN.sparc7.lsu.dctl.lsu_alt_space_g;
wire spc7_mbar_inst0_g = `TOP_DESIGN.sparc7.lsu.dctl.mbar_inst0_g;
wire spc7_mbar_inst1_g = `TOP_DESIGN.sparc7.lsu.dctl.mbar_inst1_g;
wire spc7_mbar_inst2_g = `TOP_DESIGN.sparc7.lsu.dctl.mbar_inst2_g;
wire spc7_mbar_inst3_g = `TOP_DESIGN.sparc7.lsu.dctl.mbar_inst3_g;
wire spc7_flush_inst0_g = `TOP_DESIGN.sparc7.lsu.dctl.flush_inst0_g;
wire spc7_flush_inst1_g = `TOP_DESIGN.sparc7.lsu.dctl.flush_inst1_g;
wire spc7_flush_inst2_g = `TOP_DESIGN.sparc7.lsu.dctl.flush_inst2_g;
wire spc7_flush_inst3_g = `TOP_DESIGN.sparc7.lsu.dctl.flush_inst3_g;
wire spc7_intrpt_disp_asi0_g = `TOP_DESIGN.sparc7.lsu.dctl.intrpt_disp_asi_g & (spc7_sas_thrid_w == 2'b00);
wire spc7_intrpt_disp_asi1_g = `TOP_DESIGN.sparc7.lsu.dctl.intrpt_disp_asi_g & (spc7_sas_thrid_w == 2'b01);
wire spc7_intrpt_disp_asi2_g = `TOP_DESIGN.sparc7.lsu.dctl.intrpt_disp_asi_g & (spc7_sas_thrid_w == 2'b10);
wire spc7_intrpt_disp_asi3_g = `TOP_DESIGN.sparc7.lsu.dctl.intrpt_disp_asi_g & (spc7_sas_thrid_w == 2'b11);
wire spc7_st_inst_vld_g = `TOP_DESIGN.sparc7.lsu.dctl.st_inst_vld_g;
wire spc7_non_altspace_ldst_g = `TOP_DESIGN.sparc7.lsu.dctl.non_altspace_ldst_g;
wire spc7_dctl_flush_pipe_w = `TOP_DESIGN.sparc7.lsu.dctl.dctl_flush_pipe_w;
wire [3:0] spc7_no_spc_rmo_st = `TOP_DESIGN.sparc7.lsu.dctl.no_spc_rmo_st[3:0];
wire spc7_ldst_fp_e = `TOP_DESIGN.sparc7.lsu.ifu_lsu_ldst_fp_e;
wire [2:0] spc7_stb_rdptr = `TOP_DESIGN.sparc7.lsu.stb_rwctl.stb_rdptr_l;
wire spc7_ld_l2cache_req = `TOP_DESIGN.sparc7.lsu.qctl1.ld3_l2cache_rq |
`TOP_DESIGN.sparc7.lsu.qctl1.ld2_l2cache_rq |
`TOP_DESIGN.sparc7.lsu.qctl1.ld1_l2cache_rq |
`TOP_DESIGN.sparc7.lsu.qctl1.ld0_l2cache_rq;
wire [3:0] spc7_dcache_enable = {`TOP_DESIGN.sparc7.lsu.dctl.lsu_ctl_reg0[1],
`TOP_DESIGN.sparc7.lsu.dctl.lsu_ctl_reg1[1],
`TOP_DESIGN.sparc7.lsu.dctl.lsu_ctl_reg2[1],
`TOP_DESIGN.sparc7.lsu.dctl.lsu_ctl_reg3[1]};
wire [3:0] spc7_icache_enable = `TOP_DESIGN.sparc7.lsu.lsu_ifu_icache_en[3:0];
wire spc7_dc_direct_map = `TOP_DESIGN.sparc7.lsu.dc_direct_map;
wire spc7_lsu_ifu_direct_map_l1 = `TOP_DESIGN.sparc7.lsu.lsu_ifu_direct_map_l1;
always @(spc7_dcache_enable)
$display("%0d tso_mon: spc7_dcache_enable changed to %x", $time, spc7_dcache_enable);
always @(spc7_icache_enable)
$display("%0d tso_mon: spc7_icache_enable changed to %x", $time, spc7_icache_enable);
always @(spc7_dc_direct_map)
$display("%0d tso_mon: spc7_dc_direct_map changed to %x", $time, spc7_dc_direct_map);
always @(spc7_lsu_ifu_direct_map_l1)
$display("%0d tso_mon: spc7_lsu_ifu_direct_map_l1 changed to %x", $time, spc7_lsu_ifu_direct_map_l1);
reg spc7_dva_svld_e_d1;
reg spc7_dva_rvld_e_d1;
reg [10:4] spc7_dva_rd_addr_e_d1;
reg [4:0] spc7_dva_snp_addr_e_d1;
reg spc7_lsu_snp_after_rd;
reg spc7_lsu_rd_after_snp;
reg spc7_ldst_fp_m, spc7_ldst_fp_g;
integer spc7_multiple_hits;
reg spc7_skid_d1, spc7_skid_d2, spc7_skid_d3;
initial begin
spc7_skid_d1 = 0;
spc7_skid_d2 = 0;
spc7_skid_d3 = 0;
end
always @(posedge clk)
begin
spc7_skid_d1 <= (~spc7_ifu_lsu_inv_clear & spc7_dfq_rd_advance & spc7_dfq_int_type);
spc7_skid_d2 <= spc7_skid_d1 & ~spc7_ifu_lsu_inv_clear;
spc7_skid_d3 <= spc7_skid_d2 & ~spc7_ifu_lsu_inv_clear;
// The full tracking of this condition is complicated since after the interrupt is advanced
// there may be more invalidations to the IFQ.
// All we care about is that the invalidations BEFORE the interrupt are finished.
// I provided a command line argument to disable this check.
if(spc7_skid_d3 & enable_ifu_lsu_inv_clear)
finish_test("spc", "tso_mon: spc7_ifu_lsu_inv_clear should have been clear by now", 7);
spc7_dva_svld_e_d1 <= spc7_dva_svld_e;
spc7_dva_rvld_e_d1 <= spc7_dva_rvld_e;
spc7_dva_rd_addr_e_d1 <= spc7_dva_rd_addr_e;
spc7_dva_snp_addr_e_d1 <= spc7_dva_snp_addr_e;
if(spc7_dva_svld_e_d1 & spc7_dva_rvld_e & (spc7_dva_rd_addr_e_d1[10:6] == spc7_dva_snp_addr_e[4:0]))
spc7_lsu_rd_after_snp <= 1'b1;
else
spc7_lsu_rd_after_snp <= 1'b0;
if(spc7_dva_svld_e & spc7_dva_rvld_e_d1 & (spc7_dva_rd_addr_e[10:6] == spc7_dva_snp_addr_e_d1[4:0]))
spc7_lsu_snp_after_rd <= 1'b1;
else
spc7_lsu_snp_after_rd <= 1'b0;
spc7_ldst_fp_m <= spc7_ldst_fp_e;
spc7_ldst_fp_g <= spc7_ldst_fp_m;
if(spc7_stb_data_rptr_vld & spc7_stb_data_wptr_vld & ~spc7_stbrwctl_flush_pipe_w &
(spc7_stb_data_rd_ptr == spc7_stb_data_wr_ptr) & spc7_lsu_st_pcx_rq_pick)
begin
finish_test("spc", "tso_mon: LSU stb data write and read in the same cycle", 7);
end
spc7_multiple_hits = (spc7_lsu_way_hit[3] + spc7_lsu_way_hit[2] + spc7_lsu_way_hit[1] + spc7_lsu_way_hit[0]);
if(!spc7_lsu_ifu_ldst_miss_w && (spc7_multiple_hits >1) && spc7_inst_vld_w && !spc7_dctl_flush_pipe_w && !spc7_lsu_dc_tag_pe_g_unmasked_or)
finish_test("spc", "tso_mon: LSU multiple hits ", 7);
end
wire spc7_ld_dbl = spc7_ld_inst_vld_g & spc7_ldst_dbl_g & ~spc7_quad_asi_g;
wire spc7_ld_quad = spc7_ld_inst_vld_g & spc7_ldst_dbl_g & spc7_quad_asi_g;
wire spc7_ld_other = spc7_ld_inst_vld_g & ~spc7_ldst_dbl_g;
wire spc7_ld_dbl_fp = spc7_ld_dbl & spc7_ldst_fp_g;
wire spc7_ld_other_fp = spc7_ld_other & spc7_ldst_fp_g;
wire spc7_ld_dbl_int = spc7_ld_dbl & ~spc7_ldst_fp_g;
wire spc7_ld_quad_int = spc7_ld_quad & ~spc7_ldst_fp_g;
wire spc7_ld_other_int= spc7_ld_other & ~spc7_ldst_fp_g;
wire spc7_ld_bypassok_hit = |spc7_stb_ld_full_raw[7:0] & ~spc7_stb_cam_mhit;
wire spc7_ld_partial_hit = |spc7_stb_ld_partial_raw[7:0] & ~spc7_stb_cam_mhit;
wire spc7_ld_multiple_hit = spc7_stb_cam_mhit;
wire spc7_any_lsu_way_hit = |spc7_lsu_way_hit;
wire [7:0] spc7_stb_rdptr_decoded = (spc7_stb_rdptr ==3'b000) ? 8'b00000001 :
(spc7_stb_rdptr ==3'b001) ? 8'b00000010 :
(spc7_stb_rdptr ==3'b010) ? 8'b00000100 :
(spc7_stb_rdptr ==3'b011) ? 8'b00001000 :
(spc7_stb_rdptr ==3'b100) ? 8'b00010000 :
(spc7_stb_rdptr ==3'b101) ? 8'b00100000 :
(spc7_stb_rdptr ==3'b110) ? 8'b01000000 :
(spc7_stb_rdptr ==3'b111) ? 8'b10000000 : 8'h00;
wire spc7_stb_top_hit = |(spc7_stb_rdptr_decoded & (spc7_stb_ld_full_raw | spc7_stb_ld_partial_raw));
//---------------------------------------------------------------------
// ld_type[4:0] hit_type[2:0], cache_hit, hit_top
// this is passed to the coverage monitor.
//---------------------------------------------------------------------
wire [10:0] spc7_stb_ld_hit_info =
{spc7_ld_dbl_fp, spc7_ld_other_fp,
spc7_ld_dbl_int, spc7_ld_quad_int, spc7_ld_other_int,
spc7_ld_bypassok_hit, spc7_ld_partial_hit, spc7_ld_multiple_hit,
spc7_any_lsu_way_hit,
spc7_stb_top_hit, C7_st_ack_w};
reg spc7_mbar0_active;
reg spc7_mbar1_active;
reg spc7_mbar2_active;
reg spc7_mbar3_active;
reg spc7_flush0_active;
reg spc7_flush1_active;
reg spc7_flush2_active;
reg spc7_flush3_active;
reg spc7_intr0_active;
reg spc7_intr1_active;
reg spc7_intr2_active;
reg spc7_intr3_active;
always @(negedge clk)
begin
if(~rst_l)
begin
spc7_mbar0_active <= 1'b0;
spc7_mbar1_active <= 1'b0;
spc7_mbar2_active <= 1'b0;
spc7_mbar3_active <= 1'b0;
spc7_flush0_active <= 1'b0;
spc7_flush1_active <= 1'b0;
spc7_flush2_active <= 1'b0;
spc7_flush3_active <= 1'b0;
spc7_intr0_active <= 1'b0;
spc7_intr1_active <= 1'b0;
spc7_intr2_active <= 1'b0;
spc7_intr3_active <= 1'b0;
end
else
begin
if(spc7_mbar_inst0_g & ~spc7_dctl_flush_pipe_w & (C7T0_stb_ne|~spc7_no_spc_rmo_st[0]))
spc7_mbar0_active <= 1'b1;
else if(~C7T0_stb_ne & spc7_no_spc_rmo_st[0])
spc7_mbar0_active <= 1'b0;
if(spc7_mbar_inst1_g & ~ spc7_dctl_flush_pipe_w & (C7T1_stb_ne|~spc7_no_spc_rmo_st[1]))
spc7_mbar1_active <= 1'b1;
else if(~C7T1_stb_ne & spc7_no_spc_rmo_st[1])
spc7_mbar1_active <= 1'b0;
if(spc7_mbar_inst2_g & ~ spc7_dctl_flush_pipe_w & (C7T2_stb_ne|~spc7_no_spc_rmo_st[2]))
spc7_mbar2_active <= 1'b1;
else if(~C7T2_stb_ne & spc7_no_spc_rmo_st[2])
spc7_mbar2_active <= 1'b0;
if(spc7_mbar_inst3_g & ~ spc7_dctl_flush_pipe_w & (C7T3_stb_ne|~spc7_no_spc_rmo_st[3]))
spc7_mbar3_active <= 1'b1;
else if(~C7T3_stb_ne & spc7_no_spc_rmo_st[3])
spc7_mbar3_active <= 1'b0;
if(spc7_flush_inst0_g & ~spc7_dctl_flush_pipe_w & C7T0_stb_ne) spc7_flush0_active <= 1'b1;
else if(~C7T0_stb_ne) spc7_flush0_active <= 1'b0;
if(spc7_flush_inst1_g & ~spc7_dctl_flush_pipe_w & C7T1_stb_ne) spc7_flush1_active <= 1'b1;
else if(~C7T1_stb_ne) spc7_flush1_active <= 1'b0;
if(spc7_flush_inst2_g & ~spc7_dctl_flush_pipe_w & C7T2_stb_ne) spc7_flush2_active <= 1'b1;
else if(~C7T2_stb_ne) spc7_flush2_active <= 1'b0;
if(spc7_flush_inst3_g & ~spc7_dctl_flush_pipe_w & C7T3_stb_ne) spc7_flush3_active <= 1'b1;
else if(~C7T3_stb_ne) spc7_flush3_active <= 1'b0;
if(spc7_intrpt_disp_asi0_g & spc7_st_inst_vld_g & ~spc7_non_altspace_ldst_g & ~spc7_dctl_flush_pipe_w & C7T0_stb_ne)
spc7_intr0_active <= 1'b1;
else if(~C7T0_stb_ne)
spc7_intr0_active <= 1'b0;
if(spc7_intrpt_disp_asi1_g & spc7_st_inst_vld_g & ~spc7_non_altspace_ldst_g & ~spc7_dctl_flush_pipe_w & C7T1_stb_ne)
spc7_intr1_active <= 1'b1;
else if(~C7T1_stb_ne)
spc7_intr1_active <= 1'b0;
if(spc7_intrpt_disp_asi2_g & spc7_st_inst_vld_g & ~spc7_non_altspace_ldst_g & ~spc7_dctl_flush_pipe_w & C7T2_stb_ne)
spc7_intr2_active <= 1'b1;
else if(~C7T2_stb_ne)
spc7_intr2_active <= 1'b0;
if(spc7_intrpt_disp_asi3_g & spc7_st_inst_vld_g & ~spc7_non_altspace_ldst_g & ~spc7_dctl_flush_pipe_w & C7T3_stb_ne)
spc7_intr3_active <= 1'b1;
else if(~C7T3_stb_ne)
spc7_intr3_active <= 1'b0;
end
if(spc7_mbar0_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "membar violation thread 0", 7);
if(spc7_mbar1_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "membar violation thread 1", 7);
if(spc7_mbar2_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "membar violation thread 2", 7);
if(spc7_mbar3_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "membar violation thread 3", 7);
if(spc7_flush0_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "flush violation thread 0", 7);
if(spc7_flush1_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "flush violation thread 1", 7);
if(spc7_flush2_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "flush violation thread 2", 7);
if(spc7_flush3_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "flush violation thread 3", 7);
if(spc7_intr0_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "intr violation thread 0", 7);
if(spc7_intr1_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "intr violation thread 1", 7);
if(spc7_intr2_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "intr violation thread 2", 7);
if(spc7_intr3_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "intr violation thread 3", 7);
if(~rst_l | ~C7T0_stb_full | sctag_pcx_stall_pq) C7T0_stb_drain_cnt = 0;
else C7T0_stb_drain_cnt = C7T0_stb_drain_cnt + 1;
if(C7T0_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 0 is not draining", 7);
if(~rst_l | ~C7T1_stb_full | sctag_pcx_stall_pq) C7T1_stb_drain_cnt = 0;
else C7T1_stb_drain_cnt = C7T1_stb_drain_cnt + 1;
if(C7T1_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 1 is not draining", 7);
if(~rst_l | ~C7T2_stb_full | sctag_pcx_stall_pq) C7T2_stb_drain_cnt = 0;
else C7T2_stb_drain_cnt = C7T2_stb_drain_cnt + 1;
if(C7T2_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 2 is not draining", 7);
if(~rst_l | ~C7T3_stb_full | sctag_pcx_stall_pq) C7T3_stb_drain_cnt = 0;
else C7T3_stb_drain_cnt = C7T3_stb_drain_cnt + 1;
if(C7T3_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 3 is not draining", 7);
C7T0_stb_vld_sum_d1 <= C7T0_stb_vld_sum;
C7T1_stb_vld_sum_d1 <= C7T1_stb_vld_sum;
C7T2_stb_vld_sum_d1 <= C7T2_stb_vld_sum;
C7T3_stb_vld_sum_d1 <= C7T3_stb_vld_sum;
C7T0_defr_trp_en_d1 <= C7T0_defr_trp_en;
C7T1_defr_trp_en_d1 <= C7T1_defr_trp_en;
C7T2_defr_trp_en_d1 <= C7T2_defr_trp_en;
C7T3_defr_trp_en_d1 <= C7T3_defr_trp_en;
if(rst_l & C7T0_defr_trp_en_d1 & (C7T0_stb_vld_sum_d1 < C7T0_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T0", 7);
if(rst_l & C7T1_defr_trp_en_d1 & (C7T1_stb_vld_sum_d1 < C7T1_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T1", 7);
if(rst_l & C7T2_defr_trp_en_d1 & (C7T2_stb_vld_sum_d1 < C7T2_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T2", 7);
if(rst_l & C7T3_defr_trp_en_d1 & (C7T3_stb_vld_sum_d1 < C7T3_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T3", 7);
end
`endif // ifdef RTL_SPARC7
//-----------------------------------------------------------------------------
// This is put to catch a nasty rust bug where IFILL packet does not invalidate the
// D I exclusivity
// pardon my hardwired numbers
// FSM - 00 iDLE
// 01 started
// 10 ifill_pkt is out the ibuf_busy is high so handshake not finished
//----------------------------------------------------------------------------
reg [1:0] spc0_dfq_fsm1;
integer spc0_dfq_forced;
`ifdef RTL_SPARC0
initial begin
spc0_dfq_fsm1 = 2'b00;
spc0_dfq_forced = 0;
end
always @(posedge clk)
begin
if(~rst_l)
begin
cpx_spc0_data_cx2_d2 <= `CPX_WIDTH'b0;
cpx_spc0_data_cx2_d1 <= `CPX_WIDTH'b0;
spc0_dfq_byp_ff_en_d1 <= 1'b0;
spc0_dfq_wr_en_d1 <= 1'b0;
spc0_dfq_fsm1 <= 2'b00;
spc0_dfq_forced <= 0;
end
else
begin
cpx_spc0_data_cx2_d2 <= cpx_spc0_data_cx2_d1;
cpx_spc0_data_cx2_d1 <= cpx_spc0_data_cx2;
spc0_dfq_byp_ff_en_d1 <= spc0_dfq_byp_ff_en;
spc0_dfq_wr_en_d1 <= spc0_dfq_wr_en;
if(cpx_spc0_data_cx2_d2[144] & (cpx_spc0_data_cx2_d2[143:140] == 4'h1) & ~cpx_spc0_data_cx2_d2[133] &
cpx_spc0_data_cx2_d1[144] & (cpx_spc0_data_cx2_d1[143:140] == 4'h1) & cpx_spc0_data_cx2_d1[133])
begin
$display("%0d: spc%0d tso_mon:condition1 for bug6362\n", $time, 0);
if(spc0_dfq_wr_en & ~spc0_dfq_wr_en_d1 & ~spc0_dfq_byp_ff_en)
begin
$display("%0d: spc%0d tso_mon:condition2 for bug6362\n", $time, 0);
if(spc0_dfq_fsm1 == 2'b00)
spc0_dfq_fsm1 <= 2'b01;
else
finish_test("spc", "tso_mon:something is wrong with dfq_fsm1", 0);
if(kill_on_cross_mod_code)
finish_test("spc", "tso_mon:condition2 for bug6362", 0);
end
end
if((spc0_dfq_fsm1 == 2'b01) & spc0_lsu_ifill_pkt_vld & spc0_dfq_rd_advance)
begin
spc0_dfq_fsm1 <= 2'b00; // IDLE
end
else if((spc0_dfq_fsm1 == 2'b01) & spc0_lsu_ifill_pkt_vld & ~spc0_dfq_rd_advance)
begin
spc0_dfq_fsm1 <= 2'b10; // UNFINISHED HANDSHAKE
end
else if((spc0_dfq_fsm1 == 2'b10) & spc0_lsu_ifill_pkt_vld & spc0_dfq_rd_advance)
begin
spc0_dfq_fsm1 <= 2'b00;
end
else if((spc0_dfq_fsm1 == 2'b10) & ~spc0_lsu_ifill_pkt_vld)
begin
finish_test("spc", "tso_mon:bug6362 hit - ifill_pkt goes out BEFORE dfq_rd_advance", 0);
end
if(force_dfq & ~spc0_dfq_byp_ff_en & (spc0_dfq_forced == 0))
begin
$display("%0d: spc%0d forcing spc0_dfq_forced\n", $time, 0);
force `TOP_DESIGN.sparc0.lsu.qctl2.dfq_byp_ff_en = 1'b0;
spc0_dfq_forced = 1;
end
else if((spc0_dfq_forced >0) && (spc0_dfq_forced <10))
spc0_dfq_forced = spc0_dfq_forced + 1;
else if(spc0_dfq_forced !=0)
begin
$display("%0d: spc%0d releasing spc0_dfq_forced\n", $time, 0);
release `TOP_DESIGN.sparc0.lsu.qctl2.dfq_byp_ff_en;
spc0_dfq_forced = 0;
end
//-------------
end // of else reset
end
`endif // ifdef RTL_SPARC0
reg [1:0] spc1_dfq_fsm1;
integer spc1_dfq_forced;
`ifdef RTL_SPARC1
initial begin
spc1_dfq_fsm1 = 2'b00;
spc1_dfq_forced = 0;
end
always @(posedge clk)
begin
if(~rst_l)
begin
cpx_spc1_data_cx2_d2 <= `CPX_WIDTH'b0;
cpx_spc1_data_cx2_d1 <= `CPX_WIDTH'b0;
spc1_dfq_byp_ff_en_d1 <= 1'b0;
spc1_dfq_wr_en_d1 <= 1'b0;
spc1_dfq_fsm1 <= 2'b00;
spc1_dfq_forced <= 0;
end
else
begin
cpx_spc1_data_cx2_d2 <= cpx_spc1_data_cx2_d1;
cpx_spc1_data_cx2_d1 <= cpx_spc1_data_cx2;
spc1_dfq_byp_ff_en_d1 <= spc1_dfq_byp_ff_en;
spc1_dfq_wr_en_d1 <= spc1_dfq_wr_en;
if(cpx_spc1_data_cx2_d2[144] & (cpx_spc1_data_cx2_d2[143:140] == 4'h1) & ~cpx_spc1_data_cx2_d2[133] &
cpx_spc1_data_cx2_d1[144] & (cpx_spc1_data_cx2_d1[143:140] == 4'h1) & cpx_spc1_data_cx2_d1[133])
begin
$display("%0d: spc%0d tso_mon:condition1 for bug6362\n", $time, 1);
if(spc1_dfq_wr_en & ~spc1_dfq_wr_en_d1 & ~spc1_dfq_byp_ff_en)
begin
$display("%0d: spc%0d tso_mon:condition2 for bug6362\n", $time, 1);
if(spc1_dfq_fsm1 == 2'b00)
spc1_dfq_fsm1 <= 2'b01;
else
finish_test("spc", "tso_mon:something is wrong with dfq_fsm1", 1);
if(kill_on_cross_mod_code)
finish_test("spc", "tso_mon:condition2 for bug6362", 1);
end
end
if((spc1_dfq_fsm1 == 2'b01) & spc1_lsu_ifill_pkt_vld & spc1_dfq_rd_advance)
begin
spc1_dfq_fsm1 <= 2'b00; // IDLE
end
else if((spc1_dfq_fsm1 == 2'b01) & spc1_lsu_ifill_pkt_vld & ~spc1_dfq_rd_advance)
begin
spc1_dfq_fsm1 <= 2'b10; // UNFINISHED HANDSHAKE
end
else if((spc1_dfq_fsm1 == 2'b10) & spc1_lsu_ifill_pkt_vld & spc1_dfq_rd_advance)
begin
spc1_dfq_fsm1 <= 2'b00;
end
else if((spc1_dfq_fsm1 == 2'b10) & ~spc1_lsu_ifill_pkt_vld)
begin
finish_test("spc", "tso_mon:bug6362 hit - ifill_pkt goes out BEFORE dfq_rd_advance", 1);
end
if(force_dfq & ~spc1_dfq_byp_ff_en & (spc1_dfq_forced == 0))
begin
$display("%0d: spc%0d forcing spc1_dfq_forced\n", $time, 1);
force `TOP_DESIGN.sparc1.lsu.qctl2.dfq_byp_ff_en = 1'b0;
spc1_dfq_forced = 1;
end
else if((spc1_dfq_forced >0) && (spc1_dfq_forced <10))
spc1_dfq_forced = spc1_dfq_forced + 1;
else if(spc1_dfq_forced !=0)
begin
$display("%0d: spc%0d releasing spc1_dfq_forced\n", $time, 1);
release `TOP_DESIGN.sparc1.lsu.qctl2.dfq_byp_ff_en;
spc1_dfq_forced = 0;
end
//-------------
end // of else reset
end
`endif // ifdef RTL_SPARC1
reg [1:0] spc2_dfq_fsm1;
integer spc2_dfq_forced;
`ifdef RTL_SPARC2
initial begin
spc2_dfq_fsm1 = 2'b00;
spc2_dfq_forced = 0;
end
always @(posedge clk)
begin
if(~rst_l)
begin
cpx_spc2_data_cx2_d2 <= `CPX_WIDTH'b0;
cpx_spc2_data_cx2_d1 <= `CPX_WIDTH'b0;
spc2_dfq_byp_ff_en_d1 <= 1'b0;
spc2_dfq_wr_en_d1 <= 1'b0;
spc2_dfq_fsm1 <= 2'b00;
spc2_dfq_forced <= 0;
end
else
begin
cpx_spc2_data_cx2_d2 <= cpx_spc2_data_cx2_d1;
cpx_spc2_data_cx2_d1 <= cpx_spc2_data_cx2;
spc2_dfq_byp_ff_en_d1 <= spc2_dfq_byp_ff_en;
spc2_dfq_wr_en_d1 <= spc2_dfq_wr_en;
if(cpx_spc2_data_cx2_d2[144] & (cpx_spc2_data_cx2_d2[143:140] == 4'h1) & ~cpx_spc2_data_cx2_d2[133] &
cpx_spc2_data_cx2_d1[144] & (cpx_spc2_data_cx2_d1[143:140] == 4'h1) & cpx_spc2_data_cx2_d1[133])
begin
$display("%0d: spc%0d tso_mon:condition1 for bug6362\n", $time, 2);
if(spc2_dfq_wr_en & ~spc2_dfq_wr_en_d1 & ~spc2_dfq_byp_ff_en)
begin
$display("%0d: spc%0d tso_mon:condition2 for bug6362\n", $time, 2);
if(spc2_dfq_fsm1 == 2'b00)
spc2_dfq_fsm1 <= 2'b01;
else
finish_test("spc", "tso_mon:something is wrong with dfq_fsm1", 2);
if(kill_on_cross_mod_code)
finish_test("spc", "tso_mon:condition2 for bug6362", 2);
end
end
if((spc2_dfq_fsm1 == 2'b01) & spc2_lsu_ifill_pkt_vld & spc2_dfq_rd_advance)
begin
spc2_dfq_fsm1 <= 2'b00; // IDLE
end
else if((spc2_dfq_fsm1 == 2'b01) & spc2_lsu_ifill_pkt_vld & ~spc2_dfq_rd_advance)
begin
spc2_dfq_fsm1 <= 2'b10; // UNFINISHED HANDSHAKE
end
else if((spc2_dfq_fsm1 == 2'b10) & spc2_lsu_ifill_pkt_vld & spc2_dfq_rd_advance)
begin
spc2_dfq_fsm1 <= 2'b00;
end
else if((spc2_dfq_fsm1 == 2'b10) & ~spc2_lsu_ifill_pkt_vld)
begin
finish_test("spc", "tso_mon:bug6362 hit - ifill_pkt goes out BEFORE dfq_rd_advance", 2);
end
if(force_dfq & ~spc2_dfq_byp_ff_en & (spc2_dfq_forced == 0))
begin
$display("%0d: spc%0d forcing spc2_dfq_forced\n", $time, 2);
force `TOP_DESIGN.sparc2.lsu.qctl2.dfq_byp_ff_en = 1'b0;
spc2_dfq_forced = 1;
end
else if((spc2_dfq_forced >0) && (spc2_dfq_forced <10))
spc2_dfq_forced = spc2_dfq_forced + 1;
else if(spc2_dfq_forced !=0)
begin
$display("%0d: spc%0d releasing spc2_dfq_forced\n", $time, 2);
release `TOP_DESIGN.sparc2.lsu.qctl2.dfq_byp_ff_en;
spc2_dfq_forced = 0;
end
//-------------
end // of else reset
end
`endif // ifdef RTL_SPARC2
reg [1:0] spc3_dfq_fsm1;
integer spc3_dfq_forced;
`ifdef RTL_SPARC3
initial begin
spc3_dfq_fsm1 = 2'b00;
spc3_dfq_forced = 0;
end
always @(posedge clk)
begin
if(~rst_l)
begin
cpx_spc3_data_cx2_d2 <= `CPX_WIDTH'b0;
cpx_spc3_data_cx2_d1 <= `CPX_WIDTH'b0;
spc3_dfq_byp_ff_en_d1 <= 1'b0;
spc3_dfq_wr_en_d1 <= 1'b0;
spc3_dfq_fsm1 <= 2'b00;
spc3_dfq_forced <= 0;
end
else
begin
cpx_spc3_data_cx2_d2 <= cpx_spc3_data_cx2_d1;
cpx_spc3_data_cx2_d1 <= cpx_spc3_data_cx2;
spc3_dfq_byp_ff_en_d1 <= spc3_dfq_byp_ff_en;
spc3_dfq_wr_en_d1 <= spc3_dfq_wr_en;
if(cpx_spc3_data_cx2_d2[144] & (cpx_spc3_data_cx2_d2[143:140] == 4'h1) & ~cpx_spc3_data_cx2_d2[133] &
cpx_spc3_data_cx2_d1[144] & (cpx_spc3_data_cx2_d1[143:140] == 4'h1) & cpx_spc3_data_cx2_d1[133])
begin
$display("%0d: spc%0d tso_mon:condition1 for bug6362\n", $time, 3);
if(spc3_dfq_wr_en & ~spc3_dfq_wr_en_d1 & ~spc3_dfq_byp_ff_en)
begin
$display("%0d: spc%0d tso_mon:condition2 for bug6362\n", $time, 3);
if(spc3_dfq_fsm1 == 2'b00)
spc3_dfq_fsm1 <= 2'b01;
else
finish_test("spc", "tso_mon:something is wrong with dfq_fsm1", 3);
if(kill_on_cross_mod_code)
finish_test("spc", "tso_mon:condition2 for bug6362", 3);
end
end
if((spc3_dfq_fsm1 == 2'b01) & spc3_lsu_ifill_pkt_vld & spc3_dfq_rd_advance)
begin
spc3_dfq_fsm1 <= 2'b00; // IDLE
end
else if((spc3_dfq_fsm1 == 2'b01) & spc3_lsu_ifill_pkt_vld & ~spc3_dfq_rd_advance)
begin
spc3_dfq_fsm1 <= 2'b10; // UNFINISHED HANDSHAKE
end
else if((spc3_dfq_fsm1 == 2'b10) & spc3_lsu_ifill_pkt_vld & spc3_dfq_rd_advance)
begin
spc3_dfq_fsm1 <= 2'b00;
end
else if((spc3_dfq_fsm1 == 2'b10) & ~spc3_lsu_ifill_pkt_vld)
begin
finish_test("spc", "tso_mon:bug6362 hit - ifill_pkt goes out BEFORE dfq_rd_advance", 3);
end
if(force_dfq & ~spc3_dfq_byp_ff_en & (spc3_dfq_forced == 0))
begin
$display("%0d: spc%0d forcing spc3_dfq_forced\n", $time, 3);
force `TOP_DESIGN.sparc3.lsu.qctl2.dfq_byp_ff_en = 1'b0;
spc3_dfq_forced = 1;
end
else if((spc3_dfq_forced >0) && (spc3_dfq_forced <10))
spc3_dfq_forced = spc3_dfq_forced + 1;
else if(spc3_dfq_forced !=0)
begin
$display("%0d: spc%0d releasing spc3_dfq_forced\n", $time, 3);
release `TOP_DESIGN.sparc3.lsu.qctl2.dfq_byp_ff_en;
spc3_dfq_forced = 0;
end
//-------------
end // of else reset
end
`endif // ifdef RTL_SPARC3
reg [1:0] spc4_dfq_fsm1;
integer spc4_dfq_forced;
`ifdef RTL_SPARC4
initial begin
spc4_dfq_fsm1 = 2'b00;
spc4_dfq_forced = 0;
end
always @(posedge clk)
begin
if(~rst_l)
begin
cpx_spc4_data_cx2_d2 <= `CPX_WIDTH'b0;
cpx_spc4_data_cx2_d1 <= `CPX_WIDTH'b0;
spc4_dfq_byp_ff_en_d1 <= 1'b0;
spc4_dfq_wr_en_d1 <= 1'b0;
spc4_dfq_fsm1 <= 2'b00;
spc4_dfq_forced <= 0;
end
else
begin
cpx_spc4_data_cx2_d2 <= cpx_spc4_data_cx2_d1;
cpx_spc4_data_cx2_d1 <= cpx_spc4_data_cx2;
spc4_dfq_byp_ff_en_d1 <= spc4_dfq_byp_ff_en;
spc4_dfq_wr_en_d1 <= spc4_dfq_wr_en;
if(cpx_spc4_data_cx2_d2[144] & (cpx_spc4_data_cx2_d2[143:140] == 4'h1) & ~cpx_spc4_data_cx2_d2[133] &
cpx_spc4_data_cx2_d1[144] & (cpx_spc4_data_cx2_d1[143:140] == 4'h1) & cpx_spc4_data_cx2_d1[133])
begin
$display("%0d: spc%0d tso_mon:condition1 for bug6362\n", $time, 4);
if(spc4_dfq_wr_en & ~spc4_dfq_wr_en_d1 & ~spc4_dfq_byp_ff_en)
begin
$display("%0d: spc%0d tso_mon:condition2 for bug6362\n", $time, 4);
if(spc4_dfq_fsm1 == 2'b00)
spc4_dfq_fsm1 <= 2'b01;
else
finish_test("spc", "tso_mon:something is wrong with dfq_fsm1", 4);
if(kill_on_cross_mod_code)
finish_test("spc", "tso_mon:condition2 for bug6362", 4);
end
end
if((spc4_dfq_fsm1 == 2'b01) & spc4_lsu_ifill_pkt_vld & spc4_dfq_rd_advance)
begin
spc4_dfq_fsm1 <= 2'b00; // IDLE
end
else if((spc4_dfq_fsm1 == 2'b01) & spc4_lsu_ifill_pkt_vld & ~spc4_dfq_rd_advance)
begin
spc4_dfq_fsm1 <= 2'b10; // UNFINISHED HANDSHAKE
end
else if((spc4_dfq_fsm1 == 2'b10) & spc4_lsu_ifill_pkt_vld & spc4_dfq_rd_advance)
begin
spc4_dfq_fsm1 <= 2'b00;
end
else if((spc4_dfq_fsm1 == 2'b10) & ~spc4_lsu_ifill_pkt_vld)
begin
finish_test("spc", "tso_mon:bug6362 hit - ifill_pkt goes out BEFORE dfq_rd_advance", 4);
end
if(force_dfq & ~spc4_dfq_byp_ff_en & (spc4_dfq_forced == 0))
begin
$display("%0d: spc%0d forcing spc4_dfq_forced\n", $time, 4);
force `TOP_DESIGN.sparc4.lsu.qctl2.dfq_byp_ff_en = 1'b0;
spc4_dfq_forced = 1;
end
else if((spc4_dfq_forced >0) && (spc4_dfq_forced <10))
spc4_dfq_forced = spc4_dfq_forced + 1;
else if(spc4_dfq_forced !=0)
begin
$display("%0d: spc%0d releasing spc4_dfq_forced\n", $time, 4);
release `TOP_DESIGN.sparc4.lsu.qctl2.dfq_byp_ff_en;
spc4_dfq_forced = 0;
end
//-------------
end // of else reset
end
`endif // ifdef RTL_SPARC4
reg [1:0] spc5_dfq_fsm1;
integer spc5_dfq_forced;
`ifdef RTL_SPARC5
initial begin
spc5_dfq_fsm1 = 2'b00;
spc5_dfq_forced = 0;
end
always @(posedge clk)
begin
if(~rst_l)
begin
cpx_spc5_data_cx2_d2 <= `CPX_WIDTH'b0;
cpx_spc5_data_cx2_d1 <= `CPX_WIDTH'b0;
spc5_dfq_byp_ff_en_d1 <= 1'b0;
spc5_dfq_wr_en_d1 <= 1'b0;
spc5_dfq_fsm1 <= 2'b00;
spc5_dfq_forced <= 0;
end
else
begin
cpx_spc5_data_cx2_d2 <= cpx_spc5_data_cx2_d1;
cpx_spc5_data_cx2_d1 <= cpx_spc5_data_cx2;
spc5_dfq_byp_ff_en_d1 <= spc5_dfq_byp_ff_en;
spc5_dfq_wr_en_d1 <= spc5_dfq_wr_en;
if(cpx_spc5_data_cx2_d2[144] & (cpx_spc5_data_cx2_d2[143:140] == 4'h1) & ~cpx_spc5_data_cx2_d2[133] &
cpx_spc5_data_cx2_d1[144] & (cpx_spc5_data_cx2_d1[143:140] == 4'h1) & cpx_spc5_data_cx2_d1[133])
begin
$display("%0d: spc%0d tso_mon:condition1 for bug6362\n", $time, 5);
if(spc5_dfq_wr_en & ~spc5_dfq_wr_en_d1 & ~spc5_dfq_byp_ff_en)
begin
$display("%0d: spc%0d tso_mon:condition2 for bug6362\n", $time, 5);
if(spc5_dfq_fsm1 == 2'b00)
spc5_dfq_fsm1 <= 2'b01;
else
finish_test("spc", "tso_mon:something is wrong with dfq_fsm1", 5);
if(kill_on_cross_mod_code)
finish_test("spc", "tso_mon:condition2 for bug6362", 5);
end
end
if((spc5_dfq_fsm1 == 2'b01) & spc5_lsu_ifill_pkt_vld & spc5_dfq_rd_advance)
begin
spc5_dfq_fsm1 <= 2'b00; // IDLE
end
else if((spc5_dfq_fsm1 == 2'b01) & spc5_lsu_ifill_pkt_vld & ~spc5_dfq_rd_advance)
begin
spc5_dfq_fsm1 <= 2'b10; // UNFINISHED HANDSHAKE
end
else if((spc5_dfq_fsm1 == 2'b10) & spc5_lsu_ifill_pkt_vld & spc5_dfq_rd_advance)
begin
spc5_dfq_fsm1 <= 2'b00;
end
else if((spc5_dfq_fsm1 == 2'b10) & ~spc5_lsu_ifill_pkt_vld)
begin
finish_test("spc", "tso_mon:bug6362 hit - ifill_pkt goes out BEFORE dfq_rd_advance", 5);
end
if(force_dfq & ~spc5_dfq_byp_ff_en & (spc5_dfq_forced == 0))
begin
$display("%0d: spc%0d forcing spc5_dfq_forced\n", $time, 5);
force `TOP_DESIGN.sparc5.lsu.qctl2.dfq_byp_ff_en = 1'b0;
spc5_dfq_forced = 1;
end
else if((spc5_dfq_forced >0) && (spc5_dfq_forced <10))
spc5_dfq_forced = spc5_dfq_forced + 1;
else if(spc5_dfq_forced !=0)
begin
$display("%0d: spc%0d releasing spc5_dfq_forced\n", $time, 5);
release `TOP_DESIGN.sparc5.lsu.qctl2.dfq_byp_ff_en;
spc5_dfq_forced = 0;
end
//-------------
end // of else reset
end
`endif // ifdef RTL_SPARC5
reg [1:0] spc6_dfq_fsm1;
integer spc6_dfq_forced;
`ifdef RTL_SPARC6
initial begin
spc6_dfq_fsm1 = 2'b00;
spc6_dfq_forced = 0;
end
always @(posedge clk)
begin
if(~rst_l)
begin
cpx_spc6_data_cx2_d2 <= `CPX_WIDTH'b0;
cpx_spc6_data_cx2_d1 <= `CPX_WIDTH'b0;
spc6_dfq_byp_ff_en_d1 <= 1'b0;
spc6_dfq_wr_en_d1 <= 1'b0;
spc6_dfq_fsm1 <= 2'b00;
spc6_dfq_forced <= 0;
end
else
begin
cpx_spc6_data_cx2_d2 <= cpx_spc6_data_cx2_d1;
cpx_spc6_data_cx2_d1 <= cpx_spc6_data_cx2;
spc6_dfq_byp_ff_en_d1 <= spc6_dfq_byp_ff_en;
spc6_dfq_wr_en_d1 <= spc6_dfq_wr_en;
if(cpx_spc6_data_cx2_d2[144] & (cpx_spc6_data_cx2_d2[143:140] == 4'h1) & ~cpx_spc6_data_cx2_d2[133] &
cpx_spc6_data_cx2_d1[144] & (cpx_spc6_data_cx2_d1[143:140] == 4'h1) & cpx_spc6_data_cx2_d1[133])
begin
$display("%0d: spc%0d tso_mon:condition1 for bug6362\n", $time, 6);
if(spc6_dfq_wr_en & ~spc6_dfq_wr_en_d1 & ~spc6_dfq_byp_ff_en)
begin
$display("%0d: spc%0d tso_mon:condition2 for bug6362\n", $time, 6);
if(spc6_dfq_fsm1 == 2'b00)
spc6_dfq_fsm1 <= 2'b01;
else
finish_test("spc", "tso_mon:something is wrong with dfq_fsm1", 6);
if(kill_on_cross_mod_code)
finish_test("spc", "tso_mon:condition2 for bug6362", 6);
end
end
if((spc6_dfq_fsm1 == 2'b01) & spc6_lsu_ifill_pkt_vld & spc6_dfq_rd_advance)
begin
spc6_dfq_fsm1 <= 2'b00; // IDLE
end
else if((spc6_dfq_fsm1 == 2'b01) & spc6_lsu_ifill_pkt_vld & ~spc6_dfq_rd_advance)
begin
spc6_dfq_fsm1 <= 2'b10; // UNFINISHED HANDSHAKE
end
else if((spc6_dfq_fsm1 == 2'b10) & spc6_lsu_ifill_pkt_vld & spc6_dfq_rd_advance)
begin
spc6_dfq_fsm1 <= 2'b00;
end
else if((spc6_dfq_fsm1 == 2'b10) & ~spc6_lsu_ifill_pkt_vld)
begin
finish_test("spc", "tso_mon:bug6362 hit - ifill_pkt goes out BEFORE dfq_rd_advance", 6);
end
if(force_dfq & ~spc6_dfq_byp_ff_en & (spc6_dfq_forced == 0))
begin
$display("%0d: spc%0d forcing spc6_dfq_forced\n", $time, 6);
force `TOP_DESIGN.sparc6.lsu.qctl2.dfq_byp_ff_en = 1'b0;
spc6_dfq_forced = 1;
end
else if((spc6_dfq_forced >0) && (spc6_dfq_forced <10))
spc6_dfq_forced = spc6_dfq_forced + 1;
else if(spc6_dfq_forced !=0)
begin
$display("%0d: spc%0d releasing spc6_dfq_forced\n", $time, 6);
release `TOP_DESIGN.sparc6.lsu.qctl2.dfq_byp_ff_en;
spc6_dfq_forced = 0;
end
//-------------
end // of else reset
end
`endif // ifdef RTL_SPARC6
reg [1:0] spc7_dfq_fsm1;
integer spc7_dfq_forced;
`ifdef RTL_SPARC7
initial begin
spc7_dfq_fsm1 = 2'b00;
spc7_dfq_forced = 0;
end
always @(posedge clk)
begin
if(~rst_l)
begin
cpx_spc7_data_cx2_d2 <= `CPX_WIDTH'b0;
cpx_spc7_data_cx2_d1 <= `CPX_WIDTH'b0;
spc7_dfq_byp_ff_en_d1 <= 1'b0;
spc7_dfq_wr_en_d1 <= 1'b0;
spc7_dfq_fsm1 <= 2'b00;
spc7_dfq_forced <= 0;
end
else
begin
cpx_spc7_data_cx2_d2 <= cpx_spc7_data_cx2_d1;
cpx_spc7_data_cx2_d1 <= cpx_spc7_data_cx2;
spc7_dfq_byp_ff_en_d1 <= spc7_dfq_byp_ff_en;
spc7_dfq_wr_en_d1 <= spc7_dfq_wr_en;
if(cpx_spc7_data_cx2_d2[144] & (cpx_spc7_data_cx2_d2[143:140] == 4'h1) & ~cpx_spc7_data_cx2_d2[133] &
cpx_spc7_data_cx2_d1[144] & (cpx_spc7_data_cx2_d1[143:140] == 4'h1) & cpx_spc7_data_cx2_d1[133])
begin
$display("%0d: spc%0d tso_mon:condition1 for bug6362\n", $time, 7);
if(spc7_dfq_wr_en & ~spc7_dfq_wr_en_d1 & ~spc7_dfq_byp_ff_en)
begin
$display("%0d: spc%0d tso_mon:condition2 for bug6362\n", $time, 7);
if(spc7_dfq_fsm1 == 2'b00)
spc7_dfq_fsm1 <= 2'b01;
else
finish_test("spc", "tso_mon:something is wrong with dfq_fsm1", 7);
if(kill_on_cross_mod_code)
finish_test("spc", "tso_mon:condition2 for bug6362", 7);
end
end
if((spc7_dfq_fsm1 == 2'b01) & spc7_lsu_ifill_pkt_vld & spc7_dfq_rd_advance)
begin
spc7_dfq_fsm1 <= 2'b00; // IDLE
end
else if((spc7_dfq_fsm1 == 2'b01) & spc7_lsu_ifill_pkt_vld & ~spc7_dfq_rd_advance)
begin
spc7_dfq_fsm1 <= 2'b10; // UNFINISHED HANDSHAKE
end
else if((spc7_dfq_fsm1 == 2'b10) & spc7_lsu_ifill_pkt_vld & spc7_dfq_rd_advance)
begin
spc7_dfq_fsm1 <= 2'b00;
end
else if((spc7_dfq_fsm1 == 2'b10) & ~spc7_lsu_ifill_pkt_vld)
begin
finish_test("spc", "tso_mon:bug6362 hit - ifill_pkt goes out BEFORE dfq_rd_advance", 7);
end
if(force_dfq & ~spc7_dfq_byp_ff_en & (spc7_dfq_forced == 0))
begin
$display("%0d: spc%0d forcing spc7_dfq_forced\n", $time, 7);
force `TOP_DESIGN.sparc7.lsu.qctl2.dfq_byp_ff_en = 1'b0;
spc7_dfq_forced = 1;
end
else if((spc7_dfq_forced >0) && (spc7_dfq_forced <10))
spc7_dfq_forced = spc7_dfq_forced + 1;
else if(spc7_dfq_forced !=0)
begin
$display("%0d: spc%0d releasing spc7_dfq_forced\n", $time, 7);
release `TOP_DESIGN.sparc7.lsu.qctl2.dfq_byp_ff_en;
spc7_dfq_forced = 0;
end
//-------------
end // of else reset
end
`endif // ifdef RTL_SPARC7
//==============================================================================
//== End of Main program ====================================================
//==============================================================================
//==============================================================================
// Tasks and functions
//==============================================================================
//==============================================================================
// tso_mon models the 16 L2MB entries per sctag.
// sctag_l2mb_cam looks for the tso_mon L2MB entry which is valid and has the same
// address as the incoming sctag_addr_c2
//==============================================================================
function sctag_l2mb_cam;
input [1:0] tag;
integer i;
integer done;
begin
i = 0;
done = 0;
if(tag == 2'h0)
begin
while(!done)
begin
if((sctag0_l2mb_state[i] != `L2MB_IDLE) & (sctag0_l2mb_addr[i] == sctag0_addr_c2[39:8]))
begin
done = 1;
end
else
begin
i = i +1;
if(i>15) done = 1;
end
end
end
if(tag == 2'h1)
begin
while(!done)
begin
if((sctag1_l2mb_state[i] != `L2MB_IDLE) & (sctag1_l2mb_addr[i] == sctag1_addr_c2[39:8]))
begin
done = 1;
end
else
begin
i = i +1;
if(i>15) done = 1;
end
end
end
if(tag == 2'h2)
begin
while(!done)
begin
if((sctag2_l2mb_state[i] != `L2MB_IDLE) & (sctag2_l2mb_addr[i] == sctag2_addr_c2[39:8]))
begin
done = 1;
end
else
begin
i = i +1;
if(i>15) done = 1;
end
end
end
if(tag == 2'h3)
begin
while(!done)
begin
if((sctag3_l2mb_state[i] != `L2MB_IDLE) & (sctag3_l2mb_addr[i] == sctag3_addr_c2[39:8]))
begin
done = 1;
end
else
begin
i = i +1;
if(i>15) done = 1;
end
end
end
sctag_l2mb_cam = i;
end
endfunction
//==============================================================================
// tso_mon models the 16 L2MB entries per sctag.
// sctag_find_next_available finds the next available (free) entry to write stuff into it
//==============================================================================
function sctag_find_next_available;
input [1:0] tag;
integer i;
integer done;
begin
i = 0;
done = 0;
if(tag == 2'h0)
begin
while(!done)
begin
if(sctag0_l2mb_state[i] == `L2MB_IDLE)
begin
done = 1;
end
else
begin
i = i +1;
if(i>15) done = 1;
end
end
end
if(tag == 2'h1)
begin
while(!done)
begin
if(sctag1_l2mb_state[i] == `L2MB_IDLE)
begin
done = 1;
end
else
begin
i = i +1;
if(i>15) done = 1;
end
end
end
if(tag == 2'h2)
begin
while(!done)
begin
if(sctag2_l2mb_state[i] == `L2MB_IDLE)
begin
done = 1;
end
else
begin
i = i +1;
if(i>15) done = 1;
end
end
end
if(tag == 2'h3)
begin
while(!done)
begin
if(sctag3_l2mb_state[i] == `L2MB_IDLE)
begin
done = 1;
end
else
begin
i = i +1;
if(i>15) done = 1;
end
end
end
sctag_find_next_available = i;
end
endfunction
//=====================================================================
`define TSO_MON_PCX_VLD pcx_data[123]
`define TSO_MON_PCX_TYPE pcx_data[122:118]
`define TSO_MON_PCX_NC pcx_data[117]
`define TSO_MON_PCX_CPU_ID pcx_data[116:114]
`define TSO_MON_PCX_THR_ID pcx_data[113:112]
`define TSO_MON_PCX_INV pcx_data[111]
`define TSO_MON_PCX_PRF pcx_data[110]
`define TSO_MON_PCX_BST pcx_data[109]
`define TSO_MON_PCX_RPL pcx_data[108:107]
`define TSO_MON_PCX_SIZ pcx_data[106:104]
`define TSO_MON_PCX_ADD pcx_data[103:64]
`define TSO_MON_PCX_ADD39 pcx_data[103]
`define TSO_MON_PCX_DAT pcx_data[63:0]
//=====================================================================
// This task analyzes PCX packets
//=====================================================================
task get_pcx;
output [127:0] pcx_type_str;
input [`PCX_WIDTH-1:0] pcx_data;
input [5:0] pcx_type_d1;
input pcx_atom_pq_d1;
input pcx_atom_pq_d2;
input [2:0] spc_id;
input [4:0] pcx_req_pq_d1;
reg current_stb_nced;
begin
// This is just for easy debug
//-----------------------------
case(`TSO_MON_PCX_TYPE)
`LOAD_RQ : pcx_type_str = "LOAD_RQ";
`IMISS_RQ : pcx_type_str = "IMISS_RQ";
`STORE_RQ : pcx_type_str = "STORE_RQ";
`CAS1_RQ : pcx_type_str = "CAS1_RQ";
`CAS2_RQ : pcx_type_str = "CAS2_RQ";
`SWAP_RQ : pcx_type_str = "SWAP_RQ";
`STRLOAD_RQ: pcx_type_str = "STRLOAD_RQ";
`STRST_RQ : pcx_type_str = "STRST_RQ";
`STQ_RQ : pcx_type_str = "STQ_RQ";
`INT_RQ : pcx_type_str = "INT_RQ";
`FWD_RQ : pcx_type_str = "FWD_RQ";
`FWD_RPY : pcx_type_str = "FWD_RPY";
`RSVD_RQ : pcx_type_str = "RSVD_RQ";
`FPOP1_RQ : pcx_type_str = "FPOP1";
`FPOP2_RQ : pcx_type_str = "FPOP2";
default : pcx_type_str = "ILLEGAL";
endcase
if(tso_mon_msg)
$display("%0d tso_mon: cpu(%x) thr(%x) pcx pkt: TYPE= %s NC= %x INV= %x PRF= %x BST= %x RPL= %x SZ= %x PA= %x D= %x",
$time, `TSO_MON_PCX_CPU_ID, `TSO_MON_PCX_THR_ID, pcx_type_str, `TSO_MON_PCX_NC, `TSO_MON_PCX_INV, `TSO_MON_PCX_PRF, `TSO_MON_PCX_BST, `TSO_MON_PCX_RPL, `TSO_MON_PCX_SIZ, `TSO_MON_PCX_ADD, `TSO_MON_PCX_DAT);
// SOme sanity checks
//--------------------
if(`TSO_MON_PCX_VLD === 1'bx)
finish_test("spc", "valid bit - pcx_data[123] is X", spc_id);
// victorm Feb 2003 - removing the L1 way replacement info from the X checking
// since for prefetches and non-cacheables the way can be an X.
if(`TSO_MON_PCX_VLD & ~((`TSO_MON_PCX_TYPE == `FWD_RPY) || (`TSO_MON_PCX_TYPE == `INT_RQ)) & ((^pcx_data[122:109] === 1'bx) | (^pcx_data[106:64] === 1'bx)))
finish_test("spc", "PCX request with valid bit is 1, but pcx_data[122:64] is X", spc_id);
if(`TSO_MON_PCX_VLD & (`TSO_MON_PCX_TYPE == `INT_RQ) & (^pcx_data[122:109] === 1'bx))
finish_test("spc", "PCX INT request with valid bit is 1, but pcx_data[122:109] is X", spc_id);
if(`TSO_MON_PCX_VLD & ((`TSO_MON_PCX_TYPE == `CAS1_RQ) || (`TSO_MON_PCX_TYPE == `CAS2_RQ)) & (^pcx_data[122:0] === 1'bx))
finish_test("spc", "X in CAS packets", spc_id);
// victorm - when the request type is interrupt then this check is not valid.
//--------------------------------------------------------------------------
if(~((`TSO_MON_PCX_TYPE == `INT_RQ) | (`TSO_MON_PCX_TYPE == `FWD_RQ) | (`TSO_MON_PCX_TYPE == `FWD_RPY)) & ~(`TSO_MON_PCX_CPU_ID == spc_id))
finish_test("spc", "messed up pcx_id", spc_id);
if((pcx_type_d1 == `FPOP1_RQ) & ~(`TSO_MON_PCX_TYPE == `FPOP2_RQ))
finish_test("spc", "FPOP1 without FPOP2", spc_id);
if(pcx_atom_pq_d1 & ~((`TSO_MON_PCX_TYPE == `FPOP1_RQ) | (`TSO_MON_PCX_TYPE == `CAS1_RQ)))
begin
$display("pcx atomic1 problems heads up: pcx_type = %x", `TSO_MON_PCX_TYPE);
finish_test("spc", "pcx atomic1 problems ", spc_id);
end
if(pcx_atom_pq_d2 & ~((`TSO_MON_PCX_TYPE == `FPOP2_RQ) | (`TSO_MON_PCX_TYPE == `CAS2_RQ)))
begin
$display("pcx atomic2 problems heads up: pcx_type = %x", `TSO_MON_PCX_TYPE);
finish_test("spc", "pcx atomic2 problems ", spc_id);
end
if(~`TSO_MON_PCX_VLD & tso_mon_msg)
$display("%0d INFO: spc %d speculative request backoff", $time, spc_id);
case({`TSO_MON_PCX_CPU_ID, `TSO_MON_PCX_THR_ID})
5'h00: current_stb_nced = C0T0_stb_nced;
5'h01: current_stb_nced = C0T1_stb_nced;
5'h02: current_stb_nced = C0T2_stb_nced;
5'h03: current_stb_nced = C0T3_stb_nced;
5'h04: current_stb_nced = C1T0_stb_nced;
5'h05: current_stb_nced = C1T1_stb_nced;
5'h06: current_stb_nced = C1T2_stb_nced;
5'h07: current_stb_nced = C1T3_stb_nced;
5'h08: current_stb_nced = C2T0_stb_nced;
5'h09: current_stb_nced = C2T1_stb_nced;
5'h0a: current_stb_nced = C2T2_stb_nced;
5'h0b: current_stb_nced = C2T3_stb_nced;
5'h0c: current_stb_nced = C3T0_stb_nced;
5'h0d: current_stb_nced = C3T1_stb_nced;
5'h0e: current_stb_nced = C3T2_stb_nced;
5'h0f: current_stb_nced = C3T3_stb_nced;
5'h10: current_stb_nced = C4T0_stb_nced;
5'h11: current_stb_nced = C4T1_stb_nced;
5'h12: current_stb_nced = C4T2_stb_nced;
5'h13: current_stb_nced = C4T3_stb_nced;
5'h14: current_stb_nced = C5T0_stb_nced;
5'h15: current_stb_nced = C5T1_stb_nced;
5'h16: current_stb_nced = C5T2_stb_nced;
5'h17: current_stb_nced = C5T3_stb_nced;
5'h18: current_stb_nced = C6T0_stb_nced;
5'h19: current_stb_nced = C6T1_stb_nced;
5'h1a: current_stb_nced = C6T2_stb_nced;
5'h1b: current_stb_nced = C6T3_stb_nced;
5'h1c: current_stb_nced = C7T0_stb_nced;
5'h1d: current_stb_nced = C7T1_stb_nced;
5'h1e: current_stb_nced = C7T2_stb_nced;
5'h1f: current_stb_nced = C7T3_stb_nced;
default: current_stb_nced = 1'b1;
endcase
if(`TSO_MON_PCX_VLD & ((`TSO_MON_PCX_TYPE == `LOAD_RQ) | (`TSO_MON_PCX_TYPE == `STRLOAD_RQ)) & (`TSO_MON_PCX_ADD39 | pcx_req_pq_d1[4]) & current_stb_nced)
begin
finish_test("spc", "IO strong ordering problems ", spc_id);
end
if(`TSO_MON_PCX_VLD & ((`TSO_MON_PCX_TYPE == `LOAD_RQ) | (`TSO_MON_PCX_TYPE == `STRLOAD_RQ)) & (`TSO_MON_PCX_ADD39 | pcx_req_pq_d1[4]) & `TSO_MON_PCX_PRF)
begin
finish_test("spc", "prefetch to IO space ", spc_id);
end
end
endtask
//=====================================================================
// This task analyzes sctag to CPX packets
//=====================================================================
task get_sctag_cpx;
output [3:0] type;
output [127:0] sctag_cpx_type_str;
input sctag_cpx_req_cq_d1;
input [`CPX_WIDTH-1:0] sctag_cpx_data_ca;
input [1:0] sctag_id;
begin
type = sctag_cpx_data_ca[`CPX_RQ_HI:`CPX_RQ_LO];
// this is for debugging mostly
case(sctag_cpx_data_ca[`CPX_RQ_HI:`CPX_RQ_LO])
`LOAD_RET : sctag_cpx_type_str = "LOAD_RET";
`IFILL_RET: sctag_cpx_type_str = "IFILL_RET";
`INV_RET : sctag_cpx_type_str = "INV_RET";
`ST_ACK : sctag_cpx_type_str = "ST_ACK";
`AT_ACK : sctag_cpx_type_str = "AT_ACK";
`INT_RET : sctag_cpx_type_str = "INT_RET";
`TEST_RET : sctag_cpx_type_str = "TEST_RET";
`FP_RET : sctag_cpx_type_str = "FP_RET";
`EVICT_REQ: sctag_cpx_type_str = "EVICT_REQ";
`ERR_RET : sctag_cpx_type_str = "ERR_RET";
`STRLOAD_RET : sctag_cpx_type_str = "STRLOAD_RET";
`STRST_ACK: sctag_cpx_type_str = "STRST_ACK";
`FWD_RQ_RET: sctag_cpx_type_str = "FWD_RQ_RET";
`FWD_RPY_RET: sctag_cpx_type_str = "FWD_RPY_RET";
`RSVD_RET : sctag_cpx_type_str = "RSVD_RET";
default: sctag_cpx_type_str = "ILLEGAL";
endcase
if(sctag_cpx_req_cq_d1 & tso_mon_msg)
$display("%0d tso_mon: sctag%d-to-cpx pkt TYPE= %s data= %x",
$time, sctag_id, sctag_cpx_type_str, sctag_cpx_data_ca[127:0]);
end
endtask
//=====================================================================
// This task analyzes CPX to spc packets
//=====================================================================
task get_cpx_spc;
output [127:0] cpx_spc_type_str;
input [4:0] cpx_spc_type;
begin
case(cpx_spc_type)
`LOAD_RET : cpx_spc_type_str = "LOAD_RET";
`IFILL_RET: cpx_spc_type_str = "IFILL_RET";
`INV_RET : cpx_spc_type_str = "INV_RET";
`ST_ACK : cpx_spc_type_str = "ST_ACK";
`AT_ACK : cpx_spc_type_str = "AT_ACK";
`INT_RET : cpx_spc_type_str = "INT_RET";
`TEST_RET : cpx_spc_type_str = "TEST_RET";
`FP_RET : cpx_spc_type_str = "FP_RET";
`EVICT_REQ: cpx_spc_type_str = "EVICT_REQ";
`ERR_RET : cpx_spc_type_str = "ERR_RET";
`STRLOAD_RET : cpx_spc_type_str = "STRLOAD_RET";
`STRST_ACK: cpx_spc_type_str = "STRST_ACK";
`FWD_RQ_RET: cpx_spc_type_str = "FWD_RQ_RET";
`FWD_RPY_RET: cpx_spc_type_str = "FWD_RPY_RET";
`RSVD_RET : cpx_spc_type_str = "RSVD_RET";
default: cpx_spc_type_str = "ILLEGAL";
endcase
end
endtask
//------------------------------------------------
//=====================================================================
// This task allows some more clocks and kills the test
//=====================================================================
task finish_test;
input [512:0] message0;
input [512:0] message1;
input [2:0] id;
begin
$display("%0d ERROR: %s: %d %s", $time, message0, id, message1);
repeat(100) @(posedge clk);
$finish;
end
endtask
`endif // ifdef GATE_SIM
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 4
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_top,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "system_auto_us_0,axi_dwidth_converter_v2_1_top,{}" *)
(* CORE_GENERATION_INFO = "system_auto_us_0,axi_dwidth_converter_v2_1_top,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_M_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=0,C_AXI_SUPPORTS_READ=1,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BEATS=16,C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_auto_us_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_dwidth_converter_v2_1_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(0),
.C_AXI_SUPPORTS_READ(1),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(32'H00000000),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(3'H0),
.s_axi_awregion(4'H0),
.s_axi_awqos(4'H0),
.s_axi_awvalid(1'H0),
.s_axi_awready(),
.s_axi_wdata(32'H00000000),
.s_axi_wstrb(4'HF),
.s_axi_wlast(1'H1),
.s_axi_wvalid(1'H0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'H0),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awvalid(),
.m_axi_awready(1'H0),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wvalid(),
.m_axi_wready(1'H0),
.m_axi_bresp(2'H0),
.m_axi_bvalid(1'H0),
.m_axi_bready(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// file: clk_wiz_1.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1_____5.000______0.000______50.0______631.442____346.848
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module clk_wiz_1_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_clk_wiz_1),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_1;
wire clkfbout_buf_clk_wiz_1;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT_F (32.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (128.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_wiz_1),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_clk_wiz_1),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_wiz_1),
.CLKIN1 (clk_in1_clk_wiz_1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_wiz_1),
.I (clkfbout_clk_wiz_1));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_clk_wiz_1));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2_TB_V
`define SKY130_FD_SC_HD__OR2_TB_V
/**
* or2: 2-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__or2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVP_SYMBOL_V
`define SKY130_FD_SC_HVL__EINVP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVP_SYMBOL_V
|
`timescale 1ns / 100ps
`include "parameter.v"
module level3arch (count1,count2,max_pos_l3,min_pos_l3,
q_begin_l3,q_begin_l3_flag,qwindow1_full,s_end_l3,swindow1_full,
s_end_l3_flag,max_pos_l3_n,min_pos_l3_n,cD_min_found,
cA0,cA1,cA2,cA3,cA4,cA5,cA6,cA7,cA8,cA9,cA10,cA11,cA12,cA13,cA14,cA15,cA16,cA17,cA18,cA19,cA20,cA21,cA22,cA23,cA24,cA25,cA26,cA27,cA28,cA29,cA30,cA31,cA32,cA33,cA34,cA35,cA36,cA37,cA38,cA39,cA40,cA41,cA42,cA43,cA44,cA45,cA46,cA47,cA48,cA49,cA50,cA51,cA52,cA53,cA54,cA55,cA56,cA57,cA58,cA59,cA60,cA61,cA62,cA63,cA64,cA65,cA66,cA67,cA68,cA69,cA70,cA71,cA72,cA73,cA74,cA75,cA76,cA77,cA78,cA79,cA80,cA81,cA82,cA83,cA84,cA85,cA86,cA87,cA88,cA89,cA90,cA91,cA92,cA93,cA94,cA95,cA96,cA97,cA98,cA99,data_in,clk,nReset);
output [3:0] count1;
output [8:0] count2;
output signed [15:0] max_pos_l3,min_pos_l3,
cA0,cA1,cA2,cA3,cA4,cA5,cA6,cA7,cA8,cA9,cA10,cA11,cA12,cA13,cA14,cA15,cA16,cA17,cA18,cA19,cA20,cA21,cA22,cA23,cA24,cA25,cA26,cA27,cA28,cA29,cA30,cA31,cA32,cA33,cA34,cA35,cA36,cA37,cA38,cA39,cA40,cA41,cA42,cA43,cA44,cA45,cA46,cA47,cA48,cA49,cA50,cA51,cA52,cA53,cA54,cA55,cA56,cA57,cA58,cA59,cA60,cA61,cA62,cA63,cA64,cA65,cA66,cA67,cA68,cA69,cA70,cA71,cA72,cA73,cA74,cA75,cA76,cA77,cA78,cA79,cA80,cA81,cA82,cA83,cA84,cA85,cA86,cA87,cA88,cA89,cA90,cA91,cA92,cA93,cA94,cA95,cA96,cA97,cA98,cA99;
output [15:0] q_begin_l3,s_end_l3,max_pos_l3_n,min_pos_l3_n;
output q_begin_l3_flag,qwindow1_full,swindow1_full,s_end_l3_flag,cD_min_found;
reg signed [15:0] cD_l3,cA_l3,max_val_l3,min_val_l3,max_pos_l3,
min_pos_l3,q_begin_l3,q1maxv,q1maxp,s_end_l3,s1minv,
s1minp,max_val_l3_n,max_pos_l3_n,max_pos_l3_temp,min_val_l3_n,
min_pos_l3_n,min_pos_l3_temp;
reg q_begin_l3_flag,qwindow1_full,swindow1_full,s_end_l3_flag,
cD_max_found,cD_min_found;
input [15:0] data_in;
input clk, nReset;
wire clk, nReset;
reg [15:0] data0, data1;
reg [3:0] count1;
reg [8:0] count2;
reg [8:0] count3;
reg [15:0] pos;
reg signed [15:0] cD_l3_store [0:`n3-2];
reg signed [15:0] cA_l3_store [0:`n3-2];
reg [15:0] temp1,temp2,temp3,temp4,temp5,temp6,temp7,temp8;
reg [15:0] c2,c3,c4,c5;
integer i;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
data0 <= #20 0;
data1 <= #20 0;
cD_l3 <= #20 0;
cA_l3 <= #20 0;
count1 <= #20 0;
count2 <= #20 `n3;
count3 <= #20 0;
pos <= 0;
for (i=0; i<=`n3-2; i=i+1)
begin
cD_l3_store[i] <= #20 0;
cA_l3_store[i] <= #20 0;
end
end
else
begin
if (count1 < 9 && count2 > 0)
begin
case (count1)
0 : begin
data0 <= #20 0;
data1 <= #20 0;
count1 <= #20 count1 + 1;
end
1 : begin
if (count2 > 0)
begin
count1 <= #20 count1 + 1;
data0 <= #20 data_in;
if (count3 != 0 && count3 < `n3)
begin
cD_l3_store[count3-1] <= #20 cD_l3;
cA_l3_store[count3-1] <= #20 cA_l3;
end
else
begin
cD_l3_store[count3-1] <= #20 0;
cA_l3_store[count3-1] <= #20 0;
end
end
end
2 : begin
if(count2 > 1)
begin
data0 <= #20 data0 + data_in;
count1 <= #20 count1 + 1;
end
end
3 : begin
data0 <= #20 data0 + data_in;
count1 <= #20 count1 + 1;
end
4 : begin
data0 <= #20 data0 + data_in;
count1 <= #20 count1 + 1;
end
5 : begin
data1 <= #20 data_in;
count1 <= #20 count1 + 1;
end
6 : begin
data1 <= #20 data1 + data_in;
count1 <= #20 count1 + 1;
end
7 : begin
data1 <= #20 data1 + data_in;
count1 <= #20 count1 + 1;
end
8 : begin
cA_l3 <= #20 data0 + data1 + data_in;
cD_l3 <= #20 data0 - (data1 + data_in);
pos <= #20 pos + 1;
count3 <= #20 count3 + 1;
count1 <= #20 1;
count2 <= #20 count2 - 1;
end
default : begin
data0 <= #20 0;
data1 <= #20 0;
end
endcase
end
else
count1 <= #20 1;
end
always @(posedge clk or negedge nReset)
if (!nReset)
begin
max_val_l3 <= #20 0;
max_pos_l3 <= #20 0;
min_val_l3 <= #20 0;
min_pos_l3 <= #20 0;
end
else
begin
if (count1 == 1)
begin
if (count2 > 0)
begin
if (count2 == (`n3-1))
begin
max_val_l3 <= #20 cD_l3;
min_val_l3 <= #20 cD_l3;
max_pos_l3 <= #20 pos - 1;
min_pos_l3 <= #20 pos - 1; end
else
begin
if (cD_l3 > max_val_l3)
begin
max_val_l3 <= #20 cD_l3;
max_pos_l3 <= #20 pos - 1;
min_val_l3 <= #20 min_val_l3;
min_pos_l3 <= #20 min_pos_l3;
end
else
begin
if (cD_l3 < min_val_l3)
begin
min_val_l3 <= #20 cD_l3;
min_pos_l3 <= #20 pos - 1;
max_val_l3 <= #20 max_val_l3;
max_pos_l3 <= #20 max_pos_l3; end
else
begin
max_val_l3 <= #20 max_val_l3;
min_val_l3 <= #20 min_val_l3;
max_pos_l3 <= #20 max_pos_l3;
min_pos_l3 <= #20 min_pos_l3;
end
end
end
end
else
begin
max_val_l3 <= #20 max_val_l3;
min_val_l3 <= #20 min_val_l3;
max_pos_l3 <= #20 max_pos_l3;
min_pos_l3 <= #20 min_pos_l3;
end
end
else
begin
max_val_l3 <= #20 max_val_l3;
min_val_l3 <= #20 min_val_l3;
max_pos_l3 <= #20 max_pos_l3;
min_pos_l3 <= #20 min_pos_l3;
end
end
always @(*)
begin
temp1 = 0;
temp2 = 0;
temp3 = 0;
temp4 = 0;
temp5 = 0;
temp6 = 0;
temp7 = 0;
temp8 = 0;
if (count2 == 1)
begin
if (min_pos_l3 < max_pos_l3)
begin
temp1 = min_pos_l3 - `q_window_l3 - 1;
temp2 = min_pos_l3 - 1;
temp3 = max_pos_l3 + 1;
temp4 = max_pos_l3 + `s_window_l3 - 1;
temp5 = temp5;
temp6 = temp6;
temp7 = max_pos_l3;
temp8 = max_pos_l3 + (10*`rat);
end
else
begin
temp1 = max_pos_l3 - `q_window_l3 - 1;
temp2 = max_pos_l3 - 1;
temp3 = min_pos_l3 + 1;
temp4 = min_pos_l3 + `s_window_l3 - 1;
temp5 = min_pos_l3;
temp6 = min_pos_l3 + (10*`rat);
temp7 = max_pos_l3 - (15*`rat);
temp8 = max_pos_l3;
end
end
else
begin
temp1 = temp1;
temp2 = temp2;
temp3 = temp3;
temp4 = temp4;
temp5 = temp5;
temp6 = temp6;
temp7 = temp7;
temp8 = temp8;
end
end
always @(posedge clk or negedge nReset)
if (!nReset)
begin
c2 <= #20 0;
c3 <= #20 0;
c4 <= #20 0;
c5 <= #20 0;
q1maxv <= #20 0;
q1maxp <= #20 0;
qwindow1_full <= #20 0;
s1minv <= #20 0;
s1minp <= #20 0;
swindow1_full <= #20 0;
max_val_l3_n <= #20 0;
max_pos_l3_temp <= #20 0;
max_pos_l3_n <= #20 0;
cD_max_found <= #20 0;
min_val_l3_n <= #20 0;
min_pos_l3_temp <= #20 0;
min_pos_l3_n <= #20 0;
cD_min_found <= #20 0;
end
else
begin
if (count1 == 2 && count2 == 1)
begin
if (c2 <= temp2)
begin
if (c2 == 0)
c2 <= #20 temp1;
else
begin
if (c2 == temp1)
begin
c2 <= #20 temp1;
q1maxv <= #20 cD_l3_store[temp1];
q1maxp <= #20 temp1;
c2 <= #20 c2 + 1;
end
else
begin
if (cD_l3_store[c2] > q1maxv)
begin
q1maxv <= #20 cD_l3_store[c2];
q1maxp <= #20 c2;
end
else
begin
q1maxv <= #20 q1maxv;
q1maxp <= #20 q1maxp;
end
c2 <= #20 c2 + 1;
if (c2 >= temp2)
qwindow1_full <= #20 1;
else
qwindow1_full <= #20 qwindow1_full;
end
end
end
else
begin
c2 <= #20 c2;
q1maxv <= #20 q1maxv;
q1maxp <= #20 q1maxp;
qwindow1_full <= #20 qwindow1_full;
end
if (c3 <= temp4)
begin
if (c3 == 0)
c3 <= #20 temp3;
else
begin
if (c3 == temp3)
begin
c3 <= #20 temp3;
s1minv <= #20 cD_l3_store[temp3];
s1minp <= #20 temp3;
c3 <= #20 c3 + 1;
end
else
begin
if (cD_l3_store[c3] < s1minv)
begin
s1minv <= #20 cD_l3_store[c3];
s1minp <= #20 c3;
end
else
begin
s1minv <= #20 s1minv;
s1minp <= #20 s1minp;
end
c3 <= #20 c3 + 1;
if (c3 >= temp4)
swindow1_full <= #20 1;
else
swindow1_full <= #20 swindow1_full;
end
end
end
else
begin
c3 <= #20 c3;
s1minv <= #20 s1minv;
s1minp <= #20 s1minp;
swindow1_full <= #20 swindow1_full;
end
if (c4 <= temp6)
begin
if (c4 == 0)
c4 <= #20 temp5;
else
begin
if (c4 == temp5)
begin
c4 <= #20 temp5;
max_val_l3_n <= #20 cD_l3_store[temp5];
max_pos_l3_temp <= #20 temp5;
c4 <= #20 c4 + 1;
end
else
begin
if (cD_l3_store[c4] > max_val_l3_n)
begin
max_val_l3_n <= #20 cD_l3_store[c4];
max_pos_l3_temp <= #20 c4;
end
else
begin
max_val_l3_n <= #20 max_val_l3_n;
max_pos_l3_temp <= #20 max_pos_l3_temp;
end
c4 <= #20 c4 + 1;
if (c4 >= temp6)
cD_max_found <= #20 1;
else
cD_max_found <= #20 cD_max_found;
end
end
end
else
begin
c4 <= #20 c4;
max_val_l3_n <= #20 max_val_l3_n;
max_pos_l3_temp <= #20 max_pos_l3_temp;
max_pos_l3_n <= #20 max_pos_l3_n;
end
if (cD_max_found == 1)
max_pos_l3_n <= #20 max_pos_l3_temp;
else
max_pos_l3_n <= #20 max_pos_l3_n;
if (c5 <= temp8)
begin
if (c5 == 0)
c5 <= #20 temp7;
else
begin
if (c5 == temp7)
begin
c5 <= #20 temp7;
min_val_l3_n <= #20 cD_l3_store[temp7];
min_pos_l3_temp <= #20 temp7;
c5 <= #20 c5 + 1;
end
else
begin
if (cD_l3_store[c5] < min_val_l3_n)
begin
min_val_l3_n <= #20 cD_l3_store[c5];
min_pos_l3_temp <= #20 c5;
end
else
begin
min_val_l3_n <= #20 min_val_l3_n;
min_pos_l3_temp <= #20 min_pos_l3_temp;
end
c5 <= #20 c5 + 1;
if (c5 >= temp8)
cD_min_found <= #20 1;
else
cD_min_found <= #20 cD_min_found;
end
end
end
else
begin
c5 <= #20 c5;
min_val_l3_n <= #20 min_val_l3_n;
min_pos_l3_temp <= #20 min_pos_l3_temp;
min_pos_l3_n <= #20 min_pos_l3_n;
cD_min_found <= #20 cD_min_found;
end
if (cD_min_found == 1)
min_pos_l3_n <= #20 min_pos_l3_temp;
else
min_pos_l3_n <= #20 min_pos_l3_n;
end
else
begin
c2 <= #20 c2;
c3 <= #20 c3;
c4 <= #20 c4;
c5 <= #20 c5;
q1maxv <= #20 q1maxv;
q1maxp <= #20 q1maxp;
qwindow1_full <= #20 qwindow1_full;
s1minv <= #20 s1minv;
s1minp <= #20 s1minp;
swindow1_full <= #20 swindow1_full;
max_val_l3_n <= #20 max_val_l3_n;
max_pos_l3_temp <= #20 max_pos_l3_temp;
max_pos_l3_n <= #20 max_pos_l3_n;
cD_max_found <= #20 cD_max_found;
min_val_l3_n <= #20 min_val_l3_n;
min_pos_l3_temp <= #20 min_pos_l3_temp;
min_pos_l3_n <= #20 min_pos_l3_n;
cD_min_found <= #20 cD_min_found;
end
end
always @(*)
begin
q_begin_l3 = 0;
q_begin_l3_flag = 0;
if (qwindow1_full != 0)
begin
q_begin_l3 = q1maxp;
q_begin_l3_flag = 1;
end
else
begin
q_begin_l3 = q_begin_l3;
q_begin_l3_flag = q_begin_l3_flag;
end
end
always @(*)
begin
s_end_l3 = 0;
s_end_l3_flag = 0;
if (swindow1_full != 0)
begin
s_end_l3 = s1minp;
s_end_l3_flag = 1;
end
else
begin
s_end_l3 = s_end_l3;
s_end_l3_flag = s_end_l3_flag;
end
end
assign {cA0,cA1,cA2,cA3,cA4,cA5,cA6,cA7,cA8,cA9,cA10,cA11,cA12,cA13,cA14,cA15,cA16,cA17,cA18,cA19,cA20,cA21,cA22,cA23,cA24,cA25,cA26,cA27,cA28,cA29,cA30,cA31,cA32,cA33,cA34,cA35,cA36,cA37,cA38,cA39,cA40,cA41,cA42,cA43,cA44,cA45,cA46,cA47,cA48,cA49,cA50,cA51,cA52,cA53,cA54,cA55,cA56,cA57,cA58,cA59,cA60,cA61,cA62,cA63,cA64,cA65,cA66,cA67,cA68,cA69,cA70,cA71,cA72,cA73,cA74,cA75,cA76,cA77,cA78,cA79,cA80,cA81,cA82,cA83,cA84,cA85,cA86,cA87,cA88,cA89,cA90,
cA91,cA92,cA93,cA94,cA95,cA96,cA97,cA98,cA99} = {cA_l3_store[0],cA_l3_store[1],cA_l3_store[2],cA_l3_store[3],cA_l3_store[4],cA_l3_store[5],cA_l3_store[6],cA_l3_store[7],cA_l3_store[8],cA_l3_store[9],cA_l3_store[10],cA_l3_store[11],cA_l3_store[12],cA_l3_store[13],cA_l3_store[14],cA_l3_store[15],cA_l3_store[16],cA_l3_store[17],cA_l3_store[18],cA_l3_store[19],cA_l3_store[20],cA_l3_store[21],cA_l3_store[22],cA_l3_store[23],cA_l3_store[24],cA_l3_store[25],cA_l3_store[26],cA_l3_store[27],cA_l3_store[28],cA_l3_store[29],cA_l3_store[30],cA_l3_store[31],cA_l3_store[32],cA_l3_store[33],cA_l3_store[34],cA_l3_store[35],cA_l3_store[36],cA_l3_store[37],cA_l3_store[38],cA_l3_store[39],cA_l3_store[40],cA_l3_store[41],cA_l3_store[42],cA_l3_store[43],cA_l3_store[44],cA_l3_store[45],cA_l3_store[46],cA_l3_store[47],cA_l3_store[48],cA_l3_store[49],cA_l3_store[50],cA_l3_store[51],cA_l3_store[52],cA_l3_store[53],cA_l3_store[54],cA_l3_store[55],cA_l3_store[56],cA_l3_store[57],cA_l3_store[58],cA_l3_store[59],cA_l3_store[60],cA_l3_store[61],cA_l3_store[62],cA_l3_store[63],cA_l3_store[64],cA_l3_store[65],cA_l3_store[66],cA_l3_store[67],cA_l3_store[68],cA_l3_store[69],cA_l3_store[70],cA_l3_store[71],cA_l3_store[72],cA_l3_store[73],cA_l3_store[74],cA_l3_store[75],cA_l3_store[76],cA_l3_store[77],cA_l3_store[78],cA_l3_store[79],cA_l3_store[80],cA_l3_store[81],cA_l3_store[82],cA_l3_store[83],cA_l3_store[84],cA_l3_store[85],cA_l3_store[86],cA_l3_store[87],cA_l3_store[88],cA_l3_store[89],cA_l3_store[90],cA_l3_store[91],cA_l3_store[92],cA_l3_store[93],cA_l3_store[94],cA_l3_store[95],cA_l3_store[96],cA_l3_store[97],cA_l3_store[98],cA_l3_store[99]};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111O_TB_V
`define SKY130_FD_SC_HS__A2111O_TB_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a2111o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 C1 = 1'b1;
#240 D1 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 C1 = 1'b0;
#380 D1 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 D1 = 1'b1;
#500 C1 = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 D1 = 1'bx;
#640 C1 = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__a2111o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111O_TB_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module hls_contrast_strefYi_div_u
#(parameter
in0_WIDTH = 32,
in1_WIDTH = 32,
out_WIDTH = 32
)
(
input clk,
input reset,
input ce,
input [in0_WIDTH-1:0] dividend,
input [in1_WIDTH-1:0] divisor,
input [1:0] sign_i,
output wire [1:0] sign_o,
output wire [out_WIDTH-1:0] quot,
output wire [out_WIDTH-1:0] remd
);
localparam cal_WIDTH = (in0_WIDTH > in1_WIDTH)? in0_WIDTH : in1_WIDTH;
//------------------------Local signal-------------------
reg [in0_WIDTH-1:0] dividend_tmp[0:in0_WIDTH];
reg [in1_WIDTH-1:0] divisor_tmp[0:in0_WIDTH];
reg [in0_WIDTH-1:0] remd_tmp[0:in0_WIDTH];
wire [in0_WIDTH-1:0] comb_tmp[0:in0_WIDTH-1];
wire [cal_WIDTH:0] cal_tmp[0:in0_WIDTH-1];
reg [1:0] sign_tmp[0:in0_WIDTH];
//------------------------Body---------------------------
assign quot = dividend_tmp[in0_WIDTH];
assign remd = remd_tmp[in0_WIDTH];
assign sign_o = sign_tmp[in0_WIDTH];
// dividend_tmp[0], divisor_tmp[0], remd_tmp[0]
always @(posedge clk)
begin
if (ce) begin
dividend_tmp[0] <= dividend;
divisor_tmp[0] <= divisor;
sign_tmp[0] <= sign_i;
remd_tmp[0] <= 1'b0;
end
end
genvar i;
generate
for (i = 0; i < in0_WIDTH; i = i + 1)
begin : loop
if (in0_WIDTH == 1) assign comb_tmp[i] = dividend_tmp[i][0];
else assign comb_tmp[i] = {remd_tmp[i][in0_WIDTH-2:0], dividend_tmp[i][in0_WIDTH-1]};
assign cal_tmp[i] = {1'b0, comb_tmp[i]} - {1'b0, divisor_tmp[i]};
always @(posedge clk)
begin
if (ce) begin
if (in0_WIDTH == 1) dividend_tmp[i+1] <= ~cal_tmp[i][cal_WIDTH];
else dividend_tmp[i+1] <= {dividend_tmp[i][in0_WIDTH-2:0], ~cal_tmp[i][cal_WIDTH]};
divisor_tmp[i+1] <= divisor_tmp[i];
remd_tmp[i+1] <= cal_tmp[i][cal_WIDTH]? comb_tmp[i] : cal_tmp[i][in0_WIDTH-1:0];
sign_tmp[i+1] <= sign_tmp[i];
end
end
end
endgenerate
endmodule
module hls_contrast_strefYi_div
#(parameter
in0_WIDTH = 32,
in1_WIDTH = 32,
out_WIDTH = 32
)
(
input clk,
input reset,
input ce,
input [in0_WIDTH-1:0] dividend,
input [in1_WIDTH-1:0] divisor,
output reg [out_WIDTH-1:0] quot,
output reg [out_WIDTH-1:0] remd
);
//------------------------Local signal-------------------
reg [in0_WIDTH-1:0] dividend0;
reg [in1_WIDTH-1:0] divisor0;
wire [in0_WIDTH-1:0] dividend_u;
wire [in1_WIDTH-1:0] divisor_u;
wire [out_WIDTH-1:0] quot_u;
wire [out_WIDTH-1:0] remd_u;
wire [1:0] sign_i;
wire [1:0] sign_o;
//------------------------Instantiation------------------
hls_contrast_strefYi_div_u #(
.in0_WIDTH ( in0_WIDTH ),
.in1_WIDTH ( in1_WIDTH ),
.out_WIDTH ( out_WIDTH )
) hls_contrast_strefYi_div_u_0 (
.clk ( clk ),
.reset ( reset ),
.ce ( ce ),
.dividend ( dividend_u ),
.divisor ( divisor_u ),
.sign_i ( sign_i ),
.sign_o ( sign_o ),
.quot ( quot_u ),
.remd ( remd_u )
);
//------------------------Body---------------------------
assign sign_i = {dividend0[in0_WIDTH-1] ^ divisor0[in1_WIDTH-1], dividend0[in0_WIDTH-1]};
assign dividend_u = dividend0[in0_WIDTH-1]? ~dividend0[in0_WIDTH-1:0] + 1'b1 :
dividend0[in0_WIDTH-1:0];
assign divisor_u = divisor0[in1_WIDTH-1]? ~divisor0[in1_WIDTH-1:0] + 1'b1 :
divisor0[in1_WIDTH-1:0];
always @(posedge clk)
begin
if (ce) begin
dividend0 <= dividend;
divisor0 <= divisor;
end
end
always @(posedge clk)
begin
if (ce) begin
if (sign_o[1])
quot <= ~quot_u + 1'b1;
else
quot <= quot_u;
end
end
always @(posedge clk)
begin
if (ce) begin
if (sign_o[0])
remd <= ~remd_u + 1'b1;
else
remd <= remd_u;
end
end
endmodule
`timescale 1 ns / 1 ps
module hls_contrast_strefYi(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
wire[dout_WIDTH - 1:0] sig_remd;
hls_contrast_strefYi_div #(
.in0_WIDTH( din0_WIDTH ),
.in1_WIDTH( din1_WIDTH ),
.out_WIDTH( dout_WIDTH ))
hls_contrast_strefYi_div_U(
.dividend( din0 ),
.divisor( din1 ),
.quot( dout ),
.remd( sig_remd ),
.clk( clk ),
.ce( ce ),
.reset( reset ));
endmodule
|
module util_sigma_delta_spi (
input clk,
input resetn,
input spi_active,
input s_sclk,
input s_sdo,
input s_sdo_t,
output s_sdi,
input [NUM_CS-1:0] s_cs,
output m_sclk,
output m_sdo,
output m_sdo_t,
input m_sdi,
output [NUM_CS-1:0] m_cs,
output reg data_ready
);
parameter NUM_CS = 1;
parameter CS_PIN = 0;
parameter IDLE_TIMEOUT = 63;
/*
* For converters from the ADI SigmaDelta family the data ready interrupt signal
* uses the same physical wire as the the DOUT signal for the SPI bus. This
* module extracts the data ready signal from the SPI bus and makes sure to
* suppress false positives. The data ready signal is indicated by the converter
* by pulling DOUT low. This will only happen if the CS pin for the converter is
* low and no SPI transfer is active. There is a small delay between the end of
* the SPI transfer and the point where the converter starts to indicate the
* data ready signal. IDLE_TIMEOUT allows to specify the amount of clock cycles
* the bus needs to be idle before the data ready signal is detected.
*/
assign m_sclk = s_sclk;
assign m_sdo = s_sdo;
assign m_sdo_t = s_sdo_t;
assign s_sdi = m_sdi;
assign m_cs = s_cs;
reg [$clog2(IDLE_TIMEOUT)-1:0] counter = IDLE_TIMEOUT;
reg [2:0] sdi_d = 'h00;
always @(posedge clk) begin
if (resetn == 1'b0) begin
counter <= IDLE_TIMEOUT;
end else begin
if (s_cs[CS_PIN] == 1'b0 && spi_active == 1'b0) begin
if (counter != 'h00)
counter <= counter - 1'b1;
end else begin
counter <= IDLE_TIMEOUT;
end
end
end
always @(posedge clk) begin
/* The data ready signal is fully asynchronous */
sdi_d <= {sdi_d[1:0], m_sdi};
end
always @(posedge clk) begin
if (counter == 'h00 && sdi_d[2] == 1'b0) begin
data_ready <= 1'b1;
end else begin
data_ready <= 1'b0;
end
end
endmodule
|
module pulsar (clk, drv);
input clk /* synthesis chip_pin = "R8" */;
output drv /* synthesis chip_pin = "B5" */ ; // JP1.10 GPIO_07
// clk = 50MHz (20ns)
// run[0] = 25MHz (40ns)
// run[1] = 12.5MHz (80ns)
// run[2] = 6.25MHz (160ns)
// run[3] = 3.125MHz (320ns)
// run[4] = 1.5625MHz (640ns)
// run[5] = 0.78125MHz (1.28us)
// 40KHz = 25us (1250 clocks)
// 625 + 625
// /```\___/
// _/`0`\_1_/`2`\_3_/`4`\_5_...
reg [31:0] run; // free running counter
reg [31:0] mem [0:255]; // pulse sequence array
reg [31:0] limit;
reg [31:0] timer;
reg [7:0] pointer; // pointer
reg start; // start condition
reg prestart; // pre-history for the start condition
initial begin
$readmemh("ram.txt", mem);
end
always @ (*) limit = mem[pointer];
always @ (posedge clk) run <= run + 1;
// repeat after ~84ms (4 Mcycles)
always @ (posedge clk) prestart <= run[23];
always @ (*) start = ~prestart & run[23]; // __/``` posedge detector
always @ (posedge clk)
if (start) begin
pointer <= 0;
timer <= 0; // initial load
end else begin
if (timer == 0) begin
timer <= limit;
pointer <= pointer + 1;
end else begin
timer = timer - 1;
end
end
assign drv = pointer[0];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:46:40 09/28/2016
// Design Name:
// Module Name: test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// 8917 8174 1715 1136
module test(
input CLK_IN,
output [7:0] LEDS,
output [7:0] DEBUG,
output reg WS,
output OPEN,
input [2:0] COL,
inout [3:0] ROW,
input [3:0] SW
);
localparam CLKDIV = 20;
wire [7:0] BRT;
wire CLK; (* BUFG = "clk" *)
reg RESET = 1;
wire [255:0] W;
reg [255:0] W2 = 256'b0;
wire WS_asic;
wire ERROR;
reg [8:0] startup = 0;
reg [CLKDIV:0] counter = 0;
wire [3:0] ROW_asic;
custom challenge (
.RESET(SW[0]),
.CLK(CLK),
.COL(COL),
.ROW(ROW_asic),
.OPEN(OPEN),
.W(W),
.DEBUG(DEBUG[6:0])
);
ws2812b display (
.RESET(RESET),
.W(W2),
.CLK50(CLK_IN),
.WS(WS_asic),
// .DEBUG(DEBUG[7:0])
.OPENER(OPENER),
.ERROR(ERROR)
);
sr_timer #(200) success (
.S(OPEN),
.R(RESET),
.CLK(CLK),
.OUT(OPENER)
);
keypad keypad (
.COL(COL),
.ROW(ROW),
.ROW_asic(ROW_asic),
.ERROR(ERROR)
);
always @(posedge CLK_IN) begin
counter <= counter + 1;
end
wire CLK2;
assign CLK = counter[CLKDIV-1];
assign CLK2 = counter[CLKDIV-3];
always @(negedge CLK2) begin
W2 <= W;
end
always @(posedge CLK_IN)
if (startup < 8'hffff) startup <= startup + 1; // count to 255d, then stop
else RESET <= 0; // deassert reset at terminal count
assign LEDS = DEBUG | {8{OPENER}};
assign DEBUG[7] = WS;
always @(*) WS = WS_asic;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4B_PP_SYMBOL_V
`define SKY130_FD_SC_LP__NAND4B_PP_SYMBOL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand4b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4B_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_P_PP_SN_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_P_PP_SN_BLACKBOX_V
/**
* udp_dff$P_pp$sN: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$P_pp$sN (
Q ,
D ,
CLK ,
SLEEP_B ,
NOTIFIER
);
output Q ;
input D ;
input CLK ;
input SLEEP_B ;
input NOTIFIER;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_P_PP_SN_BLACKBOX_V
|
/*******************************************************************************
* File Name: B_SPI_HFC_Master_v0_1.v
* Version `$CY_MAJOR_VERSION`.`$CY_MINOR_VERSION`
*
* Description:
* This file provides a base level model of the SPI Master component
*
* Note:
* None
********************************************************************************
* Control and Status Register definitions
********************************************************************************
*
* Tx interrupt Status Register Definition
* +=======+--------+--------+--------+--------+--------+--------+--------+--------+
* | Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
* +=======+--------+--------+--------+--------+--------+--------+--------+--------+
* | Desc |interrupt|unused |unused |spi_idle|bt_cpmlt|tx_f_n_f|tx_f_emp|spi_done|
* +=======+--------+--------+--------+--------+--------+--------+--------+--------+
*
* Rx interrupt Status Register Definition
* +=======+--------+--------+--------+--------+--------+--------+--------+--------+
* | Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
* +=======+--------+--------+--------+--------+--------+--------+--------+--------+
* | Desc |interrupt|rx_overr|rx_n_emp|rx_full |unused | unused |unused | unused |
* +=======+--------+--------+--------+--------+--------+--------+--------+--------+
*
* spi_done => 0 = spi transmission not done
* 1 = spi transmission done
*
* tx_f_e => 0 = TX FIFO not empty
* 1 = TX FIFO empty
*
* tx_f_n_f => 0 = TX_FIFO full
* 1 = TX FIFO not full
*
* rx_f_fll => 0 = RX FIFO not full
* 1 = RX FIFO full
*
* rx_f_n_e => 0 = RX FIFO empty
* 1 = RX FIFO not empty
*
* rx_f_over => 0 = RX FIFO not overrun
* 1 = RX FIFO overrun
*
* bt_cmplt => 0 = byte transfer is not complete
* 1 = byte transfer complete
*
********************************************************************************
* Data Path register definitions
********************************************************************************
* INSTANCE NAME: DatapathName
* DESCRIPTION:
* REGISTER USAGE:
* F0 => TX FIFO buffer
* F1 => RX FIFO buffer
* D0 => na
* D1 => na
* A0 => SPI Master TX value
* A1 => SPI Master RX value
*
********************************************************************************
* I*O Signals:
********************************************************************************
* IO SIGNALS:
*
* reset input component reset input
* clock input component clock input
* miso input SPI MISO input
* sclk output SPI SCLK output
* ss output SPI SS output
* tx_enable output tx enable output(is used for Bidirectional Mode only)
* mosi output SPI MOSI output
* interrupt output interrupt output
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
`include "cypress.v"
`ifdef B_SPI_HFC_Master_v0_1__V_ALREADY_INCLUDED
`else
`define B_SPI_HFC_Master_v0_1__V_ALREADY_INCLUDED
<<<<<<< HEAD
module B_SPI_HFC_Master_v0_1 (
input wire reset, /* System Reset */
input wire clock, /* User Supplied clock = 2x bitrate of output */
input wire miso, /* SPI MISO input */
input wire rde, /* RX Data effective */
output wire mosi, /* SPI MOSI output */
output reg sclk, /* SPI SCLK output */
output reg ss, /* SPI SS output */
output wire tx_interpt, /* Interrupt output */
output wire rx_interpt, /* Interrupt output */
output reg tde, /* TX Data effective */
output wire rx_drq, /* RX DMA request */
output wire tx_drq /* TX DMA request */
);
/* Status Register inputs from the PLD/DP's */
wire [6:0] tx_status;
wire [6:0] rx_status;
/* Master Out Slave In from the Datapath. Selects between mosi_dp8 and mosi_dp16 based on NUM_BITS */
wire mosi_from_dp;
/* One compare output of the counter which signals when to load received data into the FIFO */
wire dpcounter_one;
wire dpcounter_zero;
/* 7-bit counter output used for a compare to one output */
wire [6:0] count;
wire miso_to_dp;
/* MOSI FIFO Status outputs */
wire dpMOSI_fifo_not_empty;
wire nc1, nc2, nc3, nc4;
reg [2:0] state;
/* bit order: default is MSb first (i.e Shift Left and ShiftLeft in static configuration is = 0) */
/* DO NOT CHANGE these two parameters. They define constants */
localparam SPIM_MSB_FIRST = 1'b0;
localparam SPIM_LSB_FIRST = 1'b1;
/* State Machine state names */
localparam SPIM_STATE_IDLE = 3'h0;
localparam SPIM_STATE_LOAD_TX_DATA = 3'h1;
localparam SPIM_STATE_SEND_TX_DATA = 3'h2;
localparam SPIM_STATE_CAPT_RX_DATA = 3'h3;
localparam SPIM_STATE_SHFT_N_LD_TX_DATA = 3'h4;
localparam SPIM_STATE_SPI_DONE = 3'h5;
localparam SPIM_STATE_WAIT = 3'h6;
localparam SPIM_STATE_SEND_TX_DATA_2 = 3'h7;
/* Status Register bits */
localparam SPIM_STS_SPI_DONE_BIT = 3'd0;
localparam SPIM_STS_TX_FIFO_EMPTY_BIT = 3'd1;
localparam SPIM_STS_TX_FIFO_NOT_FULL_BIT = 3'd2;
localparam SPIM_STS_BYTE_COMPLETE_BIT = 3'd3;
localparam SPIM_STS_SPI_IDLE_BIT = 3'd4;
localparam SPIM_STS_RX_FIFO_FULL_BIT = 3'd4;
localparam SPIM_STS_RX_FIFO_NOT_EMPTY_BIT = 3'd5;
localparam SPIM_STS_RX_FIFO_OVERRUN_BIT = 3'd6;
localparam CTRL_TX_PERMISSION = 1'b0;
/*******************************************************************************
*User parameters used to define how the component is compiled
******************************************************************************/
parameter [0:0] ShiftDir = SPIM_MSB_FIRST;
parameter [6:0] NumberOfDataBits = 7'd8; /* set to 2-16 bits only. Default is 8 bits */
parameter HighSpeedMode = 0;
parameter [0:0] ModeCPHA = 1'b0; /* Default is rising edge mode */
parameter [0:0] ModePOL = 1'b0; /* Default is rising edge mode */
localparam pol_supprt = (ModePOL == 1) ? 1'b1 : 1'b0;
localparam [2:0] dpMsbVal = (NumberOfDataBits % 8) - 3'b1;
localparam [7:0] dpMISOMask = (NumberOfDataBits == 8 || NumberOfDataBits == 16) ? 8'b1111_1111 :
(NumberOfDataBits == 7 || NumberOfDataBits == 15) ? 8'b0111_1111 :
(NumberOfDataBits == 6 || NumberOfDataBits == 14) ? 8'b0011_1111 :
(NumberOfDataBits == 5 || NumberOfDataBits == 13) ? 8'b0001_1111 :
(NumberOfDataBits == 4 || NumberOfDataBits == 12) ? 8'b0000_1111 :
(NumberOfDataBits == 3 || NumberOfDataBits == 11) ? 8'b0000_0111 :
(NumberOfDataBits == 2 || NumberOfDataBits == 10) ? 8'b0000_0011 :
(NumberOfDataBits == 9) ? 8'b0000_0001 : 8'b1111_1111;
localparam [1:0] dynShiftDir = (ShiftDir == SPIM_MSB_FIRST) ? 2'd1 : 2'd2;
localparam [1:0] dp16MSBSIChoice = (ShiftDir == SPIM_MSB_FIRST) ? `SC_SI_A_CHAIN : `SC_SI_A_ROUTE;
localparam [1:0] dp16LSBSIChoice = (ShiftDir == SPIM_MSB_FIRST) ? `SC_SI_A_ROUTE : `SC_SI_A_CHAIN;
localparam f1_ld_src = (ModeCPHA == 1) ? `SC_FIFO1_ALU : `SC_FIFO1__A1;
localparam [6:0] BitCntPeriod = (NumberOfDataBits << 1) - 1;
localparam SR8 = 8'd8;
localparam dp8_cfg = {
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: LOAD F0 to A0 */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: Change Shift Out */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: Capture Shift In */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: LDSHIFT */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: END */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: Change Shift Out */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
dpMISOMask, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_ENBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_ROUTE, /*CFG13-12: */
`SC_A0_SRC_ACC, ShiftDir, 1'h0,
1'h0, f1_ld_src, `SC_FIFO0_BUS,
`SC_MSB_ENBL, dpMsbVal, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
3'h00, `SC_FIFO_SYNC_NONE, 6'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
localparam dp16_lsb_cfg = {
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: LOAD F0 to A0 */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: Change Shift Out */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: Capture Shift In */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: LDSHIFT */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: END */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: Change Shift Out */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
8'hFF, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
dp16LSBSIChoice, /*CFG13-12: */
`SC_A0_SRC_ACC, ShiftDir, 1'h0,
1'h0, f1_ld_src, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT7, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
3'h00, `SC_FIFO_SYNC_NONE, 6'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
localparam dp16_msb_cfg = {
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: LOAD F0 to A0 */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: Change Shift Out */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: Capture Shift In */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: LDSHIFT */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: END */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: Change Shift Out */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
dpMISOMask, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_ENBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
dp16MSBSIChoice, /*CFG13-12: */
`SC_A0_SRC_ACC, ShiftDir, 1'h0,
1'h0, f1_ld_src, `SC_FIFO0_BUS,
`SC_MSB_ENBL, dpMsbVal, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
3'h00, `SC_FIFO_SYNC_NONE, 6'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
/* Clock Enable primitive instantiation */
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE))
ClkEn (
.clock_in(clock),
.enable(1'b1),
.clock_out(clk_fin)
);
wire dpMOSI_fifo_not_full;
wire dpMOSI_fifo_empty;
wire dpMISO_fifo_not_empty;
wire dpMISO_fifo_full;
wire miso_buf_overrun;
wire mosi_from_dpL;
wire mosi_from_dpR;
wire cnt_tc;
reg ld_ident;
reg load_cond;
wire load_rx_data;
wire pre_tx_enable;
wire so_send;
wire pre_mosi;
wire mosi_after_ld;
wire mosi_cpha_1, mosi_cpha_0 , mosi_fin;
reg cnt_enable;
reg byte_complete;
reg mosi_pre_reg, mosi_reg;
reg so_send_reg;
reg mosi_hs_reg;
reg is_spi_done;
=======
module B_SPI_HFC_Master_v0_1(
input wire reset, /* System Reset */
input wire clock, /* User Supplied clock = 2x bitrate of output */
input wire miso, /* SPI MISO input */
input wire rde, /* RX Data effective */
output reg mosi, /* SPI MOSI output */
output reg tde, /* TX Data effective */
output reg sclk, /* SPI SCLK output */
output reg ss, /* SPI SS output */
output wire tx_interpt, /* Interrupt output */
output wire rx_interpt, /* Interrupt output */
output wire rx_drq, /* RX DMA request */
output wire tx_drq /* TX DMA request */
);
localparam SPIM_MSB_FIRST = 1'b0;
localparam SPIM_LSB_FIRST = 1'b1;
parameter [0:0] ShiftDir = SPIM_MSB_FIRST;
parameter [6:0] NumberOfDataBits = 7'd8; /* set to 2-16 bits only. Default is 8 bits */
parameter [0:0] HighSpeedMode = 1'b0;
parameter [0:0] ModeCPHA = 1'b0; /* Default is rising edge mode */
parameter [0:0] ModePOL = 1'b0; /* Default is rising edge mode */
wire clk_fin;
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE))
ClkEn (
.clock_in(clock),
.enable(1'b1),
.clock_out(clk_fin)
);
localparam [6:0] BitCntPeriod = (NumberOfDataBits << 1) - 1;
wire [6:0] count;
wire cnt_tc;
reg cnt_enable;
cy_psoc3_count7 #(.cy_period(BitCntPeriod), .cy_route_ld(0), .cy_route_en(1))
BitCounter(
/* input */ .clock(clk_fin),
/* input */ .reset(reset),
/* input */ .load(1'b0),
/* input */ .enable(cnt_enable),
/* output [06:00] */ .count(count),
/* output */ .tc(cnt_tc)
);
wire dpcounter_one = (count[4:0] == 5'h1);
>>>>>>> origin/spim
reg dpcounter_one_reg;
<<<<<<< HEAD
generate
if (HighSpeedMode == 1 && ModeCPHA == 1) begin
assign load_rx_data = (rde == 1'b1) ? 1'b0 : dpcounter_one_reg;
end
else begin
assign load_rx_data = (rde == 1'b1) ? 1'b0 : dpcounter_one;
end
endgenerate
assign miso_to_dp = miso;
assign mosi_after_ld = so_send | so_send_reg;
assign mosi = (HighSpeedMode == 1) ? mosi_fin : mosi_reg;
assign mosi_fin = (ModeCPHA == 1) ? mosi_cpha_1 : mosi_cpha_0;
assign so_send = (state == SPIM_STATE_SEND_TX_DATA) ? mosi_from_dp : 1'b0;
assign mosi_cpha_0 = (state == SPIM_STATE_SPI_DONE || ss) ? 1'b0 : mosi_hs_reg;
assign mosi_cpha_1 = ss ? 1'b0 : mosi_hs_reg;
assign pre_mosi = ((count[4:0] == BitCntPeriod) || (count[4:0] == (BitCntPeriod - 1))) ?
mosi_pre_reg | mosi_reg : mosi_reg;
assign dpcounter_zero = (count[4:0] == 5'h0);
assign dpcounter_one = (count[4:0] == 5'h01);
=======
wire mosi_from_dp;
reg mosi_from_dp_reg;
>>>>>>> origin/spim
wire dpMOSI_fifo_not_full;
wire dpMOSI_fifo_empty;
wire dpMISO_fifo_not_empty;
wire dpMISO_fifo_full;
reg rde_reg;
generate
if (HighSpeedMode) begin
always @(posedge clk_fin) begin
dpcounter_one_reg <= dpcounter_one;
mosi_from_dp_reg <= mosi_from_dp;
end
end
endgenerate
wire load_rx_data = rde_reg ? 1'b0 : (HighSpeedMode == 1 && ModeCPHA == 1) ? dpcounter_one_reg : dpcounter_one;
reg ld_ident;
reg is_spi_done;
/* State Machine state names */
localparam SPIM_STATE_IDLE = 3'h0;
localparam SPIM_STATE_LOAD_TX_DATA = 3'h1;
localparam SPIM_STATE_SEND_TX_DATA = 3'h2;
localparam SPIM_STATE_CAPT_RX_DATA = 3'h3;
localparam SPIM_STATE_SHFT_N_LD_TX_DATA = 3'h4;
localparam SPIM_STATE_SPI_DONE = 3'h5;
localparam SPIM_STATE_WAIT = 3'h6;
localparam SPIM_STATE_SEND_TX_DATA_2 = 3'h7;
reg [2:0] state;
generate
if (ModeCPHA == 1 && HighSpeedMode) begin
/* State Logic */
always @(posedge clk_fin) begin
if (reset) begin
state <= SPIM_STATE_IDLE;
end
else begin
case (state)
SPIM_STATE_IDLE: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
sclk <= ModePOL;
tde <= dpMOSI_fifo_empty;
rde_reg <= rde;
state <= (dpMOSI_fifo_empty && rde_reg) ? SPIM_STATE_IDLE : SPIM_STATE_LOAD_TX_DATA;
end
SPIM_STATE_LOAD_TX_DATA: begin// 15
cnt_enable <= 1'b1;
ss <= 1'b0;
state <= SPIM_STATE_WAIT;
end
SPIM_STATE_WAIT: begin // 14
mosi <= mosi_from_dp;
sclk <= ~ModePOL;
state <= SPIM_STATE_SEND_TX_DATA;
end
SPIM_STATE_SEND_TX_DATA: begin // 13
sclk <= ModePOL;
rde_reg <= rde;
if (dpcounter_one && is_spi_done) begin
cnt_enable <= 1'b0;
state <= SPIM_STATE_SPI_DONE;
end
else begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
end
SPIM_STATE_CAPT_RX_DATA: begin // 12
mosi <= mosi_from_dp_reg;
sclk <= ~ModePOL;
if (count[4:0] != 5'h04) begin
state <= SPIM_STATE_SEND_TX_DATA;
end
else if (!dpMOSI_fifo_empty) begin
state <= SPIM_STATE_SHFT_N_LD_TX_DATA;
end
else begin
<<<<<<< HEAD
if (!dpMOSI_fifo_empty) begin
state <= SPIM_STATE_SHFT_N_LD_TX_DATA;
end
else begin
is_spi_done <= 1'b1;
state <= SPIM_STATE_SEND_TX_DATA;
end
end
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_SPI_DONE: begin
is_spi_done <= 1'b0;
state <= SPIM_STATE_IDLE;
end
default: begin
state <= SPIM_STATE_IDLE;
end
endcase
end
else begin
state <= SPIM_STATE_IDLE;
end
end /* END of CPHA == 1 State Machine implementation */
/* Output Logic */
always @(posedge clk_fin) begin
case (state)
SPIM_STATE_IDLE: begin
tde <= dpMOSI_fifo_empty;
ss <= 1'b1;
cnt_enable <= 1'b0;
mosi_pre_reg <= 1'b0;
sclk <= pol_supprt;
end
SPIM_STATE_LOAD_TX_DATA: begin
cnt_enable <= 1'b1;
ss <= 1'b0;
mosi_hs_reg <= mosi_from_dp;
end
SPIM_STATE_WAIT: begin
mosi_hs_reg <= mosi_from_dp;
mosi_pre_reg <= mosi_from_dp;
sclk <= ~pol_supprt;
end
SPIM_STATE_SEND_TX_DATA: begin
if (count[4:0] != 5'h01) begin
sclk <= pol_supprt;
mosi_pre_reg <= mosi_from_dp;
end
else begin
sclk <= pol_supprt;
if (!ld_ident) begin
mosi_pre_reg <= mosi_from_dp;
end
if (is_spi_done) begin
cnt_enable <= 1'b0;
end
end
end
SPIM_STATE_CAPT_RX_DATA: begin
mosi_hs_reg <= mosi_from_dp_reg;
sclk <= ~pol_supprt;
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin
ld_ident <= 1'b1;
sclk <= pol_supprt;
end
SPIM_STATE_SPI_DONE: begin
mosi_pre_reg <= 1'b0;
cnt_enable <= 1'b0;
sclk <= pol_supprt;
end
default: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
mosi_pre_reg <= 1'b0;
sclk <= pol_supprt;
ld_ident <= 1'b0;
end
endcase
end
end
else if (ModeCPHA == 1 && !HighSpeedMode) begin
/* "CPHA == 1" State Machine implementation */
/* State Logic */
always @(posedge clk_fin) begin
/*
mosi_pre_reg <= 1'b0;
so_send_reg <= 1'b0;
ld_ident <= 1'b0;
*/
if (!reset) begin
case (state)
SPIM_STATE_IDLE: begin
if (dpMOSI_fifo_empty && rde == 1'b1) begin
state <= SPIM_STATE_IDLE;
end
else begin
state <= SPIM_STATE_LOAD_TX_DATA;
end
end
SPIM_STATE_LOAD_TX_DATA: begin
state <= SPIM_STATE_SEND_TX_DATA;
end
=======
is_spi_done <= 1'b1;
state <= SPIM_STATE_SEND_TX_DATA;
end
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin
sclk <= ModePOL;
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_SPI_DONE: begin
cnt_enable <= 1'b0;
sclk <= ModePOL;
is_spi_done <= 1'b0;
state <= SPIM_STATE_IDLE;
end
default: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_IDLE;
end
endcase
end
end
end
>>>>>>> origin/spim
else if (ModeCPHA == 1 && !HighSpeedMode) begin
always @(posedge clk_fin) begin
if (reset) begin
state <= SPIM_STATE_IDLE;
end
else begin
case (state)
SPIM_STATE_IDLE: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
mosi <= 1'b0;
sclk <= ModePOL;
tde <= dpMOSI_fifo_empty;
rde_reg <= rde;
state <= (dpMOSI_fifo_empty && rde_reg) ? SPIM_STATE_IDLE : SPIM_STATE_LOAD_TX_DATA;
end
SPIM_STATE_LOAD_TX_DATA: begin // 15
cnt_enable <= 1'b1;
ss <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_SEND_TX_DATA;
end
SPIM_STATE_SEND_TX_DATA: begin // 14
sclk <= ~ModePOL;
mosi <= mosi_from_dp;
rde_reg <= rde;
state <= (count[4:0] == 5'h2 && !dpMOSI_fifo_empty) ? SPIM_STATE_SHFT_N_LD_TX_DATA : SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_CAPT_RX_DATA: begin // 13
sclk <= ModePOL;
if (!dpcounter_one) begin
state <= SPIM_STATE_SEND_TX_DATA;
end
else begin
cnt_enable <= 1'b0;
state <= SPIM_STATE_SPI_DONE;
end
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin
sclk <= ModePOL;
state <= SPIM_STATE_SEND_TX_DATA;
end
SPIM_STATE_SPI_DONE: begin
mosi <= 1'b0;
cnt_enable <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_IDLE;
end
default: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
mosi <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_IDLE;
end
endcase
end
end
end
/* "CPHA == 0" State Machine implementation */
else if (ModeCPHA == 0 && HighSpeedMode) begin
always @(posedge clk_fin) begin
if (reset) begin
state <= SPIM_STATE_IDLE;
end
else begin
case (state)
SPIM_STATE_IDLE: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
sclk <= ModePOL;
tde <= dpMOSI_fifo_empty;
rde_reg <= rde;
state <= (dpMOSI_fifo_empty && rde_reg) ? SPIM_STATE_IDLE : SPIM_STATE_LOAD_TX_DATA;
end
SPIM_STATE_LOAD_TX_DATA: begin
ss <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_SEND_TX_DATA_2;
end
SPIM_STATE_SEND_TX_DATA_2: begin
mosi <= mosi_from_dp;
state <= SPIM_STATE_WAIT;
end
SPIM_STATE_WAIT: begin // 15
cnt_enable <= 1'b1;
sclk <= ~ModePOL;
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_SEND_TX_DATA: begin // 13
if (dpcounter_one) begin
ld_ident <= 1'b0;
end
sclk <= ~ModePOL;
rde_reg <= rde;
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_CAPT_RX_DATA: begin // 14
mosi <= mosi_from_dp_reg;
sclk <= ModePOL;
if (count[4:0] == 5'h6 && !dpMOSI_fifo_empty) begin
state <= SPIM_STATE_SHFT_N_LD_TX_DATA;
end
else if ((count[4:0] == 5'h0 || count[4:0] == 5'h2) && !ld_ident) begin
state <= SPIM_STATE_SPI_DONE;
end
else begin
<<<<<<< HEAD
if (!dpMOSI_fifo_empty) begin
state <= SPIM_STATE_SHFT_N_LD_TX_DATA;
end
else begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
end
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin
state <= SPIM_STATE_SEND_TX_DATA;
end
SPIM_STATE_SPI_DONE: begin
state <= SPIM_STATE_IDLE;
end
default: begin
state <= SPIM_STATE_IDLE;
end
endcase
end
else begin
state <= SPIM_STATE_IDLE;
end
end /* END of CPHA ==1 State Machine implementation */
/* Output Logic */
always @(posedge clk_fin) begin
case (state)
SPIM_STATE_IDLE: begin
tde <= dpMOSI_fifo_empty;
ss <= 1'b1;
cnt_enable <= 1'b0;
mosi_reg <= 1'b0;
sclk <= pol_supprt;
end
SPIM_STATE_LOAD_TX_DATA: begin
cnt_enable <= 1'b1;
ss <= 1'b0;
sclk <= pol_supprt;
end
SPIM_STATE_CAPT_RX_DATA: begin
if (count[4:0] != 5'h01) begin
sclk <= pol_supprt;
end
else begin
cnt_enable <= 1'b0;
sclk <= pol_supprt;
end
end
SPIM_STATE_SEND_TX_DATA: begin
sclk <= ~pol_supprt;
mosi_reg <= mosi_from_dp;
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin
sclk <= pol_supprt;
end
SPIM_STATE_SPI_DONE: begin
mosi_reg <= 1'b0;
cnt_enable <= 1'b0;
sclk <= pol_supprt;
end
default: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
mosi_reg <= 1'b0;
sclk <= pol_supprt;
end
endcase
end
end
/* "CPHA == 0" State Machine implementation */
else if (ModeCPHA != 1 && HighSpeedMode) begin
always @(posedge clk_fin) begin
mosi_reg <= mosi_pre_reg;
end
/* State Logic */
always @(posedge clk_fin) begin
// so_send_reg <= 1'b0;
if (!reset) begin
case (state)
SPIM_STATE_IDLE: begin
if (dpMOSI_fifo_empty && rde == 1'b1) begin
state <= SPIM_STATE_IDLE;
end
else begin
state <= SPIM_STATE_LOAD_TX_DATA;
end
end
SPIM_STATE_LOAD_TX_DATA: begin
state <= SPIM_STATE_SEND_TX_DATA_2;
end
SPIM_STATE_SEND_TX_DATA_2: begin
state <= SPIM_STATE_WAIT;
end
SPIM_STATE_WAIT: begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_SEND_TX_DATA: begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_CAPT_RX_DATA: begin
if (count[4:0] == 5'h06 && !dpMOSI_fifo_empty) begin
state <= SPIM_STATE_SHFT_N_LD_TX_DATA;
end
else if (count[4:0] != 5'h02) begin
state <= SPIM_STATE_SEND_TX_DATA;
end
else begin
if (!ld_ident) begin
state <= SPIM_STATE_SPI_DONE;
end
else begin
state <= SPIM_STATE_SEND_TX_DATA;
end
end
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_SPI_DONE: begin
state <= SPIM_STATE_IDLE;
end
default: begin
state <= SPIM_STATE_IDLE;
end
endcase
end
else begin
state <= SPIM_STATE_IDLE;
end
end
/* Output Logic */
always @(posedge clk_fin) begin
case (state)
SPIM_STATE_IDLE: begin
tde <= dpMOSI_fifo_empty;
ss <= 1'b1;
cnt_enable <= 1'b0;
mosi_pre_reg <= 1'b0;
sclk <= pol_supprt;
end
SPIM_STATE_LOAD_TX_DATA: begin
ss <= 1'b0;
sclk <= pol_supprt;
end
SPIM_STATE_SEND_TX_DATA_2: begin
mosi_pre_reg <= mosi_from_dp;
mosi_hs_reg <= mosi_from_dp;
end
SPIM_STATE_WAIT: begin
cnt_enable <= 1'b1;
sclk <= ~pol_supprt;
end
SPIM_STATE_SEND_TX_DATA: begin
if (count[4:0] != 5'h01) begin
mosi_pre_reg <= mosi_from_dp;
end
else begin
ld_ident <= 1'b0;
end
sclk <= ~pol_supprt;
end
SPIM_STATE_CAPT_RX_DATA: begin
mosi_hs_reg <= mosi_from_dp_reg;
if (count[4:0] == 5'h0 && !ld_ident) begin
sclk <= pol_supprt;
mosi_pre_reg <= mosi_from_dp;
end
else if (count[4:0] != 5'h02) begin
sclk <= pol_supprt;
end
else begin
sclk <= pol_supprt;
if (!ld_ident) begin
mosi_pre_reg <= 1'b0;
end
end
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin
sclk <= ~pol_supprt;
ld_ident <= 1'b1;
mosi_pre_reg <= mosi_from_dp;
end
SPIM_STATE_SPI_DONE: begin
mosi_pre_reg <= 1'b0;
ss <= 1'b1;
cnt_enable <= 1'b0;
sclk <= pol_supprt;
end
default: begin
ss <= 1'b1;
mosi_pre_reg <= 1'b0;
cnt_enable <= 1'b0;
ld_ident <= 1'b0;
sclk <= pol_supprt;
end
endcase
end
end
/* END of "CPHA == 0" State Machine implementation */
else begin
/* State Logic */
always @(posedge clk_fin) begin
/*
mosi_pre_reg <= 1'b0;
so_send_reg <= 1'b0;
*/
if (!reset) begin
case (state)
SPIM_STATE_IDLE: begin
if (dpMOSI_fifo_empty && rde == 1'b1) begin
state <= SPIM_STATE_IDLE;
end
else begin
state <= SPIM_STATE_LOAD_TX_DATA;
end
end
SPIM_STATE_LOAD_TX_DATA: begin
state <= SPIM_STATE_SEND_TX_DATA_2;
end
SPIM_STATE_SEND_TX_DATA_2: begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_CAPT_RX_DATA: begin
if (count[4:0] != 5'h05) begin
state <= SPIM_STATE_SEND_TX_DATA;
end
else if (!dpMOSI_fifo_empty) begin
state <= SPIM_STATE_SHFT_N_LD_TX_DATA;
end
else begin
state <= SPIM_STATE_SEND_TX_DATA;
end
end
SPIM_STATE_SEND_TX_DATA: begin
if(count[4:0] != 5'h02) begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
else begin
if (!ld_ident) begin
state <= SPIM_STATE_SPI_DONE;
end
else begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
end
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_SPI_DONE: begin
state <= SPIM_STATE_IDLE;
end
default: begin
state <= SPIM_STATE_IDLE;
end
endcase
end
else begin
state <= SPIM_STATE_IDLE;
end
end
/* Output Logic */
always @(posedge clk_fin) begin
case (state)
SPIM_STATE_IDLE: begin
tde <= dpMOSI_fifo_empty;
ss <= 1'b1;
cnt_enable <= 1'b0;
mosi_reg <= 1'b0;
sclk <= pol_supprt;
end
SPIM_STATE_LOAD_TX_DATA: begin
ss <= 1'b0;
sclk <= pol_supprt;
end
SPIM_STATE_SEND_TX_DATA_2: begin
mosi_reg <= mosi_from_dp;
end
SPIM_STATE_CAPT_RX_DATA: begin
cnt_enable <= 1'b1;
sclk <= ~pol_supprt;
end
=======
state <= SPIM_STATE_SEND_TX_DATA;
end
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin // 5
sclk <= ~ModePOL;
ld_ident <= 1'b1;
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_SPI_DONE: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_IDLE;
end
default: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
ld_ident <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_IDLE;
end
endcase
end
end
end
>>>>>>> origin/spim
else begin
always @(posedge clk_fin) begin
if (reset) begin
state <= SPIM_STATE_IDLE;
end
else begin
case (state)
SPIM_STATE_IDLE: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
mosi <= 1'b0;
sclk <= ModePOL;
tde <= dpMOSI_fifo_empty;
rde_reg <= rde;
state <= (dpMOSI_fifo_empty && rde_reg) ? SPIM_STATE_IDLE : SPIM_STATE_LOAD_TX_DATA;
end
SPIM_STATE_LOAD_TX_DATA: begin
ss <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_SEND_TX_DATA_2;
end
SPIM_STATE_SEND_TX_DATA_2: begin
mosi <= mosi_from_dp;
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_CAPT_RX_DATA: begin // 15
cnt_enable <= 1'b1;
sclk <= ~ModePOL;
state <= (count[4:0] == 5'h5 && !dpMOSI_fifo_empty) ? SPIM_STATE_SHFT_N_LD_TX_DATA : SPIM_STATE_SEND_TX_DATA;
end
SPIM_STATE_SEND_TX_DATA: begin // 14
sclk <= ModePOL;
rde_reg <= rde;
if (count[4:0] == 5'h2 && !ld_ident) begin
mosi <= 1'b0;
state <= SPIM_STATE_SPI_DONE;
end
else begin
if (count[4:0] == 5'h2) begin
ld_ident <= 1'b0;
end
mosi <= mosi_from_dp;
state <= SPIM_STATE_CAPT_RX_DATA;
end
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin // 4
sclk <= ModePOL;
ld_ident <= 1'b1;
mosi <= mosi_from_dp;
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_SPI_DONE: begin
mosi <= 1'b0;
ss <= 1'b1;
cnt_enable <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_IDLE;
end
default: begin
ss <= 1'b1;
mosi <= 1'b0;
cnt_enable <= 1'b0;
ld_ident <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_IDLE;
end
endcase
end
end
end
endgenerate
/* Status Register bits */
localparam SPIM_STS_SPI_DONE_BIT = 3'd0;
localparam SPIM_STS_TX_FIFO_EMPTY_BIT = 3'd1;
localparam SPIM_STS_TX_FIFO_NOT_FULL_BIT = 3'd2;
localparam SPIM_STS_BYTE_COMPLETE_BIT = 3'd3;
localparam SPIM_STS_SPI_IDLE_BIT = 3'd4;
wire [6:0] tx_status;
assign tx_status[SPIM_STS_SPI_DONE_BIT] = (state == SPIM_STATE_SPI_DONE);
assign tx_status[SPIM_STS_TX_FIFO_EMPTY_BIT] = dpMOSI_fifo_empty;
assign tx_status[SPIM_STS_TX_FIFO_NOT_FULL_BIT] = dpMOSI_fifo_not_full;
assign tx_status[SPIM_STS_BYTE_COMPLETE_BIT] = dpcounter_one;
assign tx_status[SPIM_STS_SPI_IDLE_BIT] = (state == SPIM_STATE_IDLE);
assign tx_status[6:5] = 2'h0;
assign tx_drq = dpMOSI_fifo_not_full;
cy_psoc3_statusi #(.cy_force_order(1), .cy_md_select(7'h09), .cy_int_mask(7'h00))
TxStsReg(
/* input */ .clock(clk_fin),
/* input [06:00] */ .status(tx_status),
/* output */ .interrupt(tx_interpt)
);
localparam SPIM_STS_RX_FIFO_FULL_BIT = 3'd4;
localparam SPIM_STS_RX_FIFO_NOT_EMPTY_BIT = 3'd5;
localparam SPIM_STS_RX_FIFO_OVERRUN_BIT = 3'd6;
wire [6:0] rx_status;
assign rx_status[SPIM_STS_RX_FIFO_FULL_BIT] = dpMISO_fifo_full;
assign rx_status[SPIM_STS_RX_FIFO_NOT_EMPTY_BIT] = dpMISO_fifo_not_empty;
assign rx_status[SPIM_STS_RX_FIFO_OVERRUN_BIT] = dpcounter_one & dpMISO_fifo_full;
assign rx_status[3:0] = 4'h0;
assign rx_drq = dpMISO_fifo_not_empty;
cy_psoc3_statusi #(.cy_force_order(1), .cy_md_select(7'h40), .cy_int_mask(7'h00))
RxStsReg(
/* input */ .clock(clk_fin),
/* input [06:00] */ .status(rx_status),
/* output */ .interrupt(rx_interpt)
);
localparam SR8 = 8'd8;
localparam [2:0] dpMsbVal = (NumberOfDataBits % 8) - 3'b1;
localparam [7:0] dpMISOMask = (NumberOfDataBits == 8 || NumberOfDataBits == 16) ? 8'b1111_1111 :
(NumberOfDataBits == 7 || NumberOfDataBits == 15) ? 8'b0111_1111 :
(NumberOfDataBits == 6 || NumberOfDataBits == 14) ? 8'b0011_1111 :
(NumberOfDataBits == 5 || NumberOfDataBits == 13) ? 8'b0001_1111 :
(NumberOfDataBits == 4 || NumberOfDataBits == 12) ? 8'b0000_1111 :
(NumberOfDataBits == 3 || NumberOfDataBits == 11) ? 8'b0000_0111 :
(NumberOfDataBits == 2 || NumberOfDataBits == 10) ? 8'b0000_0011 :
(NumberOfDataBits == 9) ? 8'b0000_0001 : 8'b1111_1111;
localparam [1:0] dynShiftDir = (ShiftDir == SPIM_MSB_FIRST) ? 2'd1 : 2'd2;
localparam f1_ld_src = (ModeCPHA == 1) ? `SC_FIFO1_ALU : `SC_FIFO1__A1;
generate
if (NumberOfDataBits <= SR8) begin: sR8
localparam dp8_cfg = {
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: LOAD F0 to A0 */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: Change Shift Out */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: Capture Shift In */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: LDSHIFT */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: END */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: Change Shift Out */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
dpMISOMask, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_ENBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_ROUTE, /*CFG13-12: */
`SC_A0_SRC_ACC, ShiftDir, 1'h0,
1'h0, f1_ld_src, `SC_FIFO0_BUS,
`SC_MSB_ENBL, dpMsbVal, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
3'h00, `SC_FIFO_SYNC_NONE, 6'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
cy_psoc3_dp8 #(.cy_dpconfig_a(dp8_cfg))
Dp(
/* input */ .clk(clk_fin),
/* input */ .reset(reset),
/* input [02:00] */ .cs_addr(state),
/* input */ .route_si(miso),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(load_rx_data),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(mosi_from_dp),
/* output */ .f0_bus_stat(dpMOSI_fifo_not_full),
/* output */ .f0_blk_stat(dpMOSI_fifo_empty),
/* output */ .f1_bus_stat(dpMISO_fifo_not_empty),
/* output */ .f1_blk_stat(dpMISO_fifo_full)
);
end /* NumberOfDataBits <= SR8 */
else begin : sR16 /* NumberOfDataBits > 8 */
localparam [1:0] dp16MSBSIChoice = (ShiftDir == SPIM_MSB_FIRST) ? `SC_SI_A_CHAIN : `SC_SI_A_ROUTE;
localparam [1:0] dp16LSBSIChoice = (ShiftDir == SPIM_MSB_FIRST) ? `SC_SI_A_ROUTE : `SC_SI_A_CHAIN;
localparam dp16_lsb_cfg = {
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: LOAD F0 to A0 */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: Change Shift Out */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: Capture Shift In */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: LDSHIFT */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: END */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: Change Shift Out */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
8'hFF, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
dp16LSBSIChoice, /*CFG13-12: */
`SC_A0_SRC_ACC, ShiftDir, 1'h0,
1'h0, f1_ld_src, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT7, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
3'h00, `SC_FIFO_SYNC_NONE, 6'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
localparam dp16_msb_cfg = {
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: LOAD F0 to A0 */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: Change Shift Out */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: Capture Shift In */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: LDSHIFT */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: END */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: Change Shift Out */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
dpMISOMask, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_ENBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
dp16MSBSIChoice, /*CFG13-12: */
`SC_A0_SRC_ACC, ShiftDir, 1'h0,
1'h0, f1_ld_src, `SC_FIFO0_BUS,
`SC_MSB_ENBL, dpMsbVal, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
3'h00, `SC_FIFO_SYNC_NONE, 6'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
wire mosi_from_dpL;
wire mosi_from_dpR;
wire nc1, nc2, nc3, nc4;
cy_psoc3_dp16 #(.cy_dpconfig_a(dp16_lsb_cfg), .cy_dpconfig_b(dp16_msb_cfg))
Dp(
/* input */ .clk(clk_fin),
/* input */ .reset(reset),
/* input [02:00] */ .cs_addr(state),
/* input */ .route_si(miso),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(load_rx_data),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so({mosi_from_dpL,mosi_from_dpR}),
/* output */ .f0_bus_stat({dpMOSI_fifo_not_full, nc1}),
/* output */ .f0_blk_stat({dpMOSI_fifo_empty, nc2}),
/* output */ .f1_bus_stat({dpMISO_fifo_not_empty, nc3}),
/* output */ .f1_blk_stat({dpMISO_fifo_full, nc4})
);
assign mosi_from_dp = (ShiftDir == SPIM_MSB_FIRST) ? mosi_from_dpL : mosi_from_dpR;
end /* NumberOfDataBits <= sR16 */
endgenerate
endmodule
`endif /* B_SPIM_HFC_v0_1__V_ALREADY_INCLUDED */
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41AI_BLACKBOX_V
`define SKY130_FD_SC_HS__O41AI_BLACKBOX_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o41ai (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41AI_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__DLRTP_BEHAVIORAL_PP_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_r_no_pg/sky130_fd_sc_hs__u_dl_p_r_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dlrtp (
VPWR ,
VGND ,
Q ,
RESET_B,
D ,
GATE
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hs__u_dl_p_r_no_pg u_dl_p_r_no_pg0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTP_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:45:30 03/31/2017
// Design Name: maquina_estados
// Module Name: C:/Users/Pelo/Documents/Projects/testbench.v
// Project Name: Proyecto2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: maquina_estados
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbench;
// Inputs
reg clk;
reg rst;
reg piso1;
reg piso2;
reg piso3;
reg piso4;
reg S1;
reg B2;
reg S2;
reg B3;
reg S3;
reg B4;
// Outputs
wire [7:0] DISPLAY;
wire [3:0] ANODES;
/*wire [1:0] piso;
wire [1:0] accion;
wire puertas;
wire [3:0] contador_seg;
wire [3:0] memoria_m;*/
// Instantiate the Unit Under Test (UUT)
maquina_estados uut (
.clk(clk),
.rst(rst),
.piso1(piso1),
.piso2(piso2),
.piso3(piso3),
.piso4(piso4),
.S1(S1),
.B2(B2),
.S2(S2),
.B3(B3),
.S3(S3),
.B4(B4),
.DISPLAY(DISPLAY),
.ANODES(ANODES),
/* .piso(piso),
.accion(accion),
.puertas(puertas),
.contador_seg(contador_seg),
.memoria_m(memoria_m)*/
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
piso1 = 0;
piso2 = 0;
piso3 = 0;
piso4 = 0;
S1 = 0;
B2 = 0;
S2 = 0;
B3 = 0;
S3 = 0;
B4 = 0;
// Wait 100 ns for global reset to finish
#100;
#10 rst = 1;
#10 rst = 0;
#10 piso2 = 1;
#10 piso2 = 0;
// Add stimulus here
end
always
begin
#1 clk <= ~clk;
end
// Add stimulus here
endmodule
|
module fetch (clk, stall, busy, pc, rw, access_size, enable, j_addr, jump, br_addr, branch);
parameter START_ADDR = 32'h8002_0000;
// input
input clk;
input stall;
input busy;
input [31:0] j_addr;
input jump;
input [31:0] br_addr;
input branch;
// output
output [31:0] pc;
output [2:0] access_size;
output rw; //1 is write, 0 is read
output enable;
// local
reg [31:0] pc_reg = 32'h8001_FFFC; // current address
reg [2:0] access_size_reg = 3'b000;
reg rw_reg = 1'b0;
reg enable_reg = 1'b1;
// comb
assign pc = pc_reg;
assign access_size = access_size_reg;
assign rw = rw_reg;
assign enable = enable_reg;
// proc
always @(posedge clk)
begin
if(stall != 1 & busy != 1)
begin
if(jump != 1 & branch != 1)
begin
pc_reg = pc_reg + 32'h0000_0004;
end
else if (branch == 1)
begin
pc_reg = br_addr;
end
else if(jump == 1)
begin
pc_reg = j_addr;
end
end
else if (branch == 1)
begin
pc_reg = br_addr;
end
else if(jump == 1)
begin
pc_reg = j_addr;
end
end
endmodule
|
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 17
(* X_CORE_INFO = "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2" *)
(* CHECK_LICENSE_TYPE = "zybo_zynq_design_auto_pc_0,axi_protocol_converter_v2_1_17_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "zybo_zynq_design_auto_pc_0,axi_protocol_converter_v2_1_17_axi_protocol_converter,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=17,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_A\
XI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zybo_zynq_design_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_\
THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0, NUM_REA\
D_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_17_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
module glitch_filter(
clk,
s_in,
s_out
);
input clk;
input s_in;
output s_out;
reg s_tmp;
reg [31:0]counter_low, counter_high;
initial begin
counter_low <= 0;
counter_high <= 0;
end
assign s_out = s_tmp;
always @(posedge clk) begin
if(s_in == 1'b0)
counter_low <= counter_low + 1;
else
counter_low <= 0;
end
always @(posedge clk) begin
if(s_in == 1'b1)
counter_high <= counter_high + 1;
else
counter_high <= 0;
end
always @(posedge clk) begin
if (counter_low == 4) s_tmp <= 0;
else if (counter_high == 4) s_tmp <= 1;
end
endmodule
module BTN_Anti_jitter(
// Outputs
button_out,
SW_OK,
// Inputs
clk,
button,
SW
);
input clk;
input [3:0] button;
input [7:0] SW;
output [3:0] button_out;
output [7:0] SW_OK;
glitch_filter G0(clk, button[0], button_out[0]);
glitch_filter G1(clk, button[1], button_out[1]);
glitch_filter G2(clk, button[2], button_out[2]);
glitch_filter G3(clk, button[3], button_out[3]);
glitch_filter G4(clk, SW[0], SW_OK[0]);
glitch_filter G5(clk, SW[1], SW_OK[1]);
glitch_filter G6(clk, SW[2], SW_OK[2]);
glitch_filter G7(clk, SW[3], SW_OK[3]);
glitch_filter G8(clk, SW[4], SW_OK[4]);
glitch_filter G9(clk, SW[5], SW_OK[5]);
glitch_filter G10(clk, SW[6], SW_OK[6]);
glitch_filter G11(clk, SW[7], SW_OK[7]);
endmodule
module display(
input clk, rst, mode,
input [31:0]disp_num,
output reg [7:0]seg,
output reg [3:0]anode
);
reg [26:0]tick;
reg [1:0]an;
reg [3:0]num;
reg t;
reg [7:0]dots;
initial begin
an <= 2'b00;
tick <= 0;
dots <= 0;
num <= 0;
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) tick <= 0;
else tick <= tick+1;
end
always @(posedge tick[16] or posedge rst) begin
if (rst == 1'b1) an <= 0;
else an <= an + 1;
end
always @(an) begin
if (rst == 1'b1) begin
anode <= 4'b1111;
num <= 0;
dots <= 0;
end else begin
anode <= ~(4'b1<<an);
case(an)
2'b00: begin
num <= disp_num[3:0];
dots <= {disp_num[24], disp_num[0], disp_num[4], disp_num[16], disp_num[25], disp_num[17], disp_num[5], disp_num[12]};
end
2'b01: begin
num <= disp_num[7:4];
dots <= {disp_num[26], disp_num[1], disp_num[6], disp_num[18], disp_num[27], disp_num[19], disp_num[7], disp_num[13]};
end
2'b10: begin
num <= disp_num[11:8];
dots <= {disp_num[28], disp_num[2], disp_num[8], disp_num[20], disp_num[29], disp_num[21], disp_num[9], disp_num[14]};
end
2'b11: begin
num <= disp_num[15:12];
dots <= {disp_num[30], disp_num[3], disp_num[10], disp_num[22], disp_num[31], disp_num[23], disp_num[11], disp_num[15]};
end
default:;
endcase
end
end
always @(*) begin
if (rst == 1'b1) seg <= 0;
else begin
if(mode==1'b1) begin
case(num)
4'h0 : seg[7:0] <= 8'b10000001;
4'h1 : seg[7:0] <= 8'b11001111;
4'h2 : seg[7:0] <= 8'b10010010;
4'h3 : seg[7:0] <= 8'b10000110;
4'h4 : seg[7:0] <= 8'b11001100;
4'h5 : seg[7:0] <= 8'b10100100;
4'h6 : seg[7:0] <= 8'b10100000;
4'h7 : seg[7:0] <= 8'b10001111;
4'h8 : seg[7:0] <= 8'b10000000;
4'h9 : seg[7:0] <= 8'b10000100;
4'hA : seg[7:0] <= 8'b10001000;
4'hB : seg[7:0] <= 8'b11100000;
4'hC : seg[7:0] <= 8'b10110001;
4'hD : seg[7:0] <= 8'b11000010;
4'hE : seg[7:0] <= 8'b10110000;
default : seg[7:0] <= 8'b10111000;
endcase
end else seg[7:0] <= dots;
end
end
endmodule
module seven_seg_dev(
input wire [31:0] disp_num,
input wire clk,
input wire clr,
input wire [1:0]SW,
// input wire [1:0] Scanning,
output wire [7:0] SEGMENT,
output wire [3:0] AN
);
reg [31:0] number;
initial number <= 0;
display D0(clk, clr, SW[0], number, SEGMENT, AN);
always @(*) begin
case (SW)
2'b01 : number <= { 16'b0, disp_num[15:0] };
2'b11 : number <= { 16'b0, disp_num[31:16] };
default : number <= disp_num;
endcase
end
endmodule
module Regs(
clk,
rst,
reg_R_addr_A,
reg_R_addr_B,
reg_W_addr,
wdata,
reg_we,
rdata_A,
rdata_B
);
input clk, rst, reg_we;
input [4:0] reg_R_addr_A, reg_R_addr_B, reg_W_addr;
input [31:0] wdata;
output [31:0] rdata_A, rdata_B;
reg [31:0] register [1:31];// r1 - r31
integer i;
initial begin
for (i=1; i<32; i=i+1)
register[i] <= 0;//i;
end
assign rdata_A = (reg_R_addr_A == 0) ? 0 : register[reg_R_addr_A];//read
assign rdata_B = (reg_R_addr_B == 0) ? 0 : register[reg_R_addr_B];//read
always @(posedge clk or posedge rst) begin
if (rst==1) begin// reset
for (i=1; i<32; i=i+1)
register[i] <= 0;//i;
end else begin
if ((reg_W_addr != 0) && (reg_we == 1))
register[reg_W_addr] <= wdata;
end
end
endmodule
module alu(A, B, ALU_operation, res, zero, overflow );
input signed [31:0] A, B;
input [2:0] ALU_operation;
output [31:0] res;
output zero, overflow ;
wire [31:0] res_and, res_or, res_add, res_sub, res_nor, res_slt, res_xor, res_srl;
reg [31:0] res;
parameter one = 32'h00000001, zero_0 = 32'h00000000;
assign res_and = A&B;
assign res_or = A|B;
assign res_add = A+B;
assign res_sub = A-B;
assign res_nor=~(A | B);
assign res_slt =(A < B) ? one : zero_0;
assign res_xor = A^B;
assign res_srl = B>>1;
always @*
// (A or B or ALU_operation)
case (ALU_operation)
3'b000: res=res_and;
3'b001: res=res_or;
3'b010: res=res_add;
3'b110: res=res_sub;
3'b100: res=res_nor;
3'b111: res=res_slt;
3'b011: res=res_xor;
3'b101: res=res_srl;
default: res=res_add;
//32'hx;
endcase
assign zero = (res==0)? 1: 0;
endmodule
module clk_div(
input wire clk,
input wire rst,
input wire SW2,
output reg [31:0] clkdiv,
output wire Clk_CPU
);
initial clkdiv <= 0;
always @ (posedge clk or posedge rst) begin
if (rst) begin
clkdiv <= 0;
end else begin
clkdiv <= clkdiv + 1'b1;
end
end
assign Clk_CPU = SW2 ? clkdiv[22] : clkdiv[1];
endmodule
module seven_seg_Dev_IO(
input wire clk,
input wire rst,
input wire GPIOe0000000_we,
input wire [2:0] Test,
input wire [31:0] disp_cpudata,
input wire [31:0] Test_data0,
input wire [31:0] Test_data1,
input wire [31:0] Test_data2,
input wire [31:0] Test_data3,
input wire [31:0] Test_data4,
input wire [31:0] Test_data5,
input wire [31:0] Test_data6,
output reg [31:0] disp_num
);
always @(negedge clk or posedge rst) begin
if (rst) disp_num <= 32'h0000;
else begin
case (Test)
0: begin
if(GPIOe0000000_we) disp_num <= disp_cpudata;
else disp_num <= disp_num;
end
1: disp_num <= Test_data0;
2: disp_num <= Test_data1;
3: disp_num <= Test_data2;
4: disp_num <= Test_data3;
5: disp_num <= Test_data4;
6: disp_num <= Test_data5;
7: disp_num <= Test_data6;
endcase
end
end
endmodule
module MIO_BUS( input wire clk, input wire rst,
input wire [3:0] BTN,
input wire [7:0]SW,
input wire mem_w,
input wire [31:0] Cpu_data2bus,
input wire [31:0] addr_bus, //data from CPU
input wire [31:0] ram_data_out,
input wire [7:0] led_out,
input wire [31:0] counter_out,
input wire counter0_out,
input wire counter1_out,
input wire counter2_out,
output reg [31:0] Cpu_data4bus, //write to CPU
output reg [31:0] ram_data_in, //from CPU write to Memory
output reg [9: 0] ram_addr, //Memory Address signals
output reg data_ram_we,
output reg GPIOf0000000_we,
output reg GPIOe0000000_we,
output reg counter_we,
output reg [31: 0] Peripheral_in
);
reg [7:0] led_in;
always @(*) begin
data_ram_we = 0;
counter_we = 0;
GPIOe0000000_we = 0;
GPIOf0000000_we = 0;
ram_addr = 10'h0;
ram_data_in = 32'h0;
Peripheral_in = 32'h0;
Cpu_data4bus = 32'h0;
case(addr_bus[31:28])
4'h0: begin
data_ram_we = mem_w ;
ram_addr = addr_bus[11:2];
ram_data_in = Cpu_data2bus;
Cpu_data4bus = ram_data_out;
end
4'he: begin
GPIOf0000000_we = mem_w;
Peripheral_in = Cpu_data2bus;
Cpu_data4bus = counter_out;
end
4'hf: begin
if(addr_bus[2]) begin
counter_we = mem_w;
Peripheral_in = Cpu_data2bus;
Cpu_data4bus = counter_out;
end else begin
GPIOf0000000_we = mem_w;
Peripheral_in = Cpu_data2bus;
Cpu_data4bus = {counter0_out, counter1_out, counter2_out, 9'h00, led_out, BTN, SW};
end
end
endcase
end
endmodule
module Counter_x( input wire clk,
input wire rst,
input wire clk0,
input wire clk1,
input wire clk2,
input wire counter_we,
input wire [31:0]counter_val,
input wire [1:0] counter_ch,
output wire counter0_OUT,
output wire counter1_OUT,
output wire counter2_OUT,
output wire [31:0]counter_out
);
endmodule
module led_Dev_IO(
input wire clk ,
input wire rst,
input wire GPIOf0000000_we,
input wire [31:0] Peripheral_in,
output reg [1:0] counter_set,
output wire [7:0] led_out,
output reg [21:0] GPIOf0
);
reg [7:0]LED;
assign led_out = LED;
always @(negedge clk or posedge rst) begin
if (rst) begin
LED <= 8'hAA;
counter_set <= 2'b00;
end else begin
if (GPIOf0000000_we) {GPIOf0[21:0], LED, counter_set} <= Peripheral_in;
else begin
LED <= LED;
counter_set <= counter_set;
end
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_misc_chunk1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_misc_chunk1(io_ext_int_l ,spare_misc_pinoe ,sel_bypass ,
vss_sense ,vdd_sense ,test_mode ,ext_int_l ,temp_trig ,
spare_misc_pindata ,ckd ,vref ,vddo ,clk_stretch ,hiz_l ,rst_val_dn
,rst_val_up ,reset_l ,mode_ctl ,update_dr ,io_test_mode ,shift_dr
,clock_dr ,io_clk_stretch ,por_l ,rst_io_l ,bsi ,se ,si ,so ,bso ,
clk ,io_pgrm_en ,io_burnin ,burnin ,obsel ,pgrm_en ,io_temp_trig ,
pwron_rst_l ,io_pwron_rst_l ,spare_misc_pin ,spare_misc_pin_to_core
);
input [5:4] obsel ;
output io_ext_int_l ;
output io_test_mode ;
output io_clk_stretch ;
output so ;
output bso ;
output io_pgrm_en ;
output io_burnin ;
output io_temp_trig ;
output io_pwron_rst_l ;
output spare_misc_pin_to_core ;
input spare_misc_pinoe ;
input sel_bypass ;
input spare_misc_pindata ;
input ckd ;
input vref ;
input vddo ;
input hiz_l ;
input rst_val_dn ;
input rst_val_up ;
input reset_l ;
input mode_ctl ;
input update_dr ;
input shift_dr ;
input clock_dr ;
input por_l ;
input rst_io_l ;
input bsi ;
input se ;
input si ;
input clk ;
inout vss_sense ;
inout vdd_sense ;
inout test_mode ;
inout ext_int_l ;
inout temp_trig ;
inout clk_stretch ;
inout burnin ;
inout pgrm_en ;
inout pwron_rst_l ;
inout spare_misc_pin ;
supply1 vdd ;
supply0 vss ;
wire net107 ;
wire scan_clk_stretch_spare0 ;
wire bscan_temp_trig_ext_int_l ;
wire bscan_test_mode_por ;
wire bscan_ext_int_l_spare0 ;
wire bscan_spare0_clk_stretch ;
wire bscan_por_temp_trig ;
wire scan_ext_int_l_temp_trig ;
wire scan_spare0_ext_int_l ;
bw_u1_ckbuf_40x Iclkbuf_1 (
.clk (net107 ),
.rclk (clk ) );
bw_io_cmos2_pad burnin_pad (
.oe (vss ),
.vddo (vddo ),
.data (vss ),
.to_core (io_burnin ),
.pad (burnin ),
.por_l (por_l ) );
bw_io_cmos_pad test_mode_pad (
.oe (vss ),
.bsr_si (bsi ),
.rst_io_l (reset_l ),
.vddo (vddo ),
.se (vdd ),
.rst_val_up (rst_val_up ),
.data (vss ),
.mode_ctl (mode_ctl ),
.clock_dr (clock_dr ),
.update_dr (update_dr ),
.rst_val_dn (rst_val_dn ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.bso (bscan_test_mode_por ),
.to_core (io_test_mode ),
.pad (test_mode ),
.por_l (vss ) );
bw_io_hstl_pad temp_trig_pad (
.obsel ({obsel } ),
.so (so ),
.clock_dr (clock_dr ),
.vref (vref ),
.update_dr (update_dr ),
.clk (net107 ),
.reset_l (reset_l ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.rst_io_l (rst_io_l ),
.rst_val_up (rst_val_up ),
.bso (bscan_temp_trig_ext_int_l ),
.bsr_si (bscan_por_temp_trig ),
.rst_val_dn (rst_val_dn ),
.mode_ctl (mode_ctl ),
.si (scan_ext_int_l_temp_trig ),
.oe (vss ),
.data (vss ),
.se (se ),
.to_core (io_temp_trig ),
.por_l (por_l ),
.pad (temp_trig ),
.vddo (vddo ),
.sel_bypass (sel_bypass ),
.ckd (ckd ) );
bw_io_hstl_pad ext_int_l_pad (
.obsel ({obsel } ),
.so (scan_ext_int_l_temp_trig ),
.clock_dr (clock_dr ),
.vref (vref ),
.update_dr (update_dr ),
.clk (net107 ),
.reset_l (reset_l ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.rst_io_l (rst_io_l ),
.rst_val_up (rst_val_up ),
.bso (bscan_ext_int_l_spare0 ),
.bsr_si (bscan_temp_trig_ext_int_l ),
.rst_val_dn (rst_val_dn ),
.mode_ctl (mode_ctl ),
.si (scan_spare0_ext_int_l ),
.oe (vss ),
.data (vss ),
.se (se ),
.to_core (io_ext_int_l ),
.por_l (por_l ),
.pad (ext_int_l ),
.vddo (vddo ),
.sel_bypass (sel_bypass ),
.ckd (ckd ) );
bw_io_cmos_pad pwron_rst_l_pad (
.oe (vss ),
.bsr_si (bscan_test_mode_por ),
.rst_io_l (reset_l ),
.vddo (vddo ),
.se (vdd ),
.rst_val_up (rst_val_up ),
.data (vss ),
.mode_ctl (mode_ctl ),
.clock_dr (clock_dr ),
.update_dr (update_dr ),
.rst_val_dn (rst_val_dn ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.bso (bscan_por_temp_trig ),
.to_core (io_pwron_rst_l ),
.pad (pwron_rst_l ),
.por_l (vss ) );
bw_io_cmos2_pad pgrm_en_pad (
.oe (vss ),
.vddo (vddo ),
.data (vss ),
.to_core (io_pgrm_en ),
.pad (pgrm_en ),
.por_l (por_l ) );
bw_io_hstl_pad spare_misc_pin_0_pad (
.obsel ({obsel } ),
.so (scan_spare0_ext_int_l ),
.clock_dr (clock_dr ),
.vref (vref ),
.update_dr (update_dr ),
.clk (net107 ),
.reset_l (reset_l ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.rst_io_l (rst_io_l ),
.rst_val_up (rst_val_up ),
.bso (bscan_spare0_clk_stretch ),
.bsr_si (bscan_ext_int_l_spare0 ),
.rst_val_dn (rst_val_dn ),
.mode_ctl (mode_ctl ),
.si (scan_clk_stretch_spare0 ),
.oe (spare_misc_pinoe ),
.data (spare_misc_pindata ),
.se (se ),
.to_core (spare_misc_pin_to_core ),
.por_l (por_l ),
.pad (spare_misc_pin ),
.vddo (vddo ),
.sel_bypass (sel_bypass ),
.ckd (ckd ) );
bw_io_hstl_pad clk_stretch_pad (
.obsel ({obsel } ),
.so (scan_clk_stretch_spare0 ),
.clock_dr (clock_dr ),
.vref (vref ),
.update_dr (update_dr ),
.clk (net107 ),
.reset_l (reset_l ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.rst_io_l (rst_io_l ),
.rst_val_up (rst_val_up ),
.bso (bso ),
.bsr_si (bscan_spare0_clk_stretch ),
.rst_val_dn (rst_val_dn ),
.mode_ctl (mode_ctl ),
.si (si ),
.oe (vss ),
.data (vss ),
.se (se ),
.to_core (io_clk_stretch ),
.por_l (por_l ),
.pad (clk_stretch ),
.vddo (vddo ),
.sel_bypass (sel_bypass ),
.ckd (ckd ) );
endmodule
|
Require Export Coq.Program.Tactics.
Require Export Coq.Setoids.Setoid.
Require Export Coq.Classes.Morphisms.
Require Export Coq.Arith.Arith_base.
Require Export Coq.Relations.Relations.
Require Export Coq.Lists.List.
Import EqNotations.
Import ListNotations.
(***
*** Ordered Types = Types with a PreOrder
***)
(* NOTE: The idea with this approach is that each type uniquely determines its
ordered type, but we keep the types separate from the ordered types to make
type inference work properly... *)
Class OTRelation (A:Type) : Type := ot_R : relation A.
Class OType (A:Type) {R:OTRelation A} : Prop :=
{ ot_PreOrder :> PreOrder ot_R }.
Arguments OTRelation A%type.
Arguments OType A%type {R}.
Instance OType_Reflexive A `{OType A} : Reflexive ot_R.
Proof. typeclasses eauto. Qed.
Instance OType_Transitive A `{OType A} : Transitive ot_R.
Proof. typeclasses eauto. Qed.
(* The equivalence relation for an OrderedType *)
Definition ot_equiv {A} `{OTRelation A} : relation A :=
fun x y => ot_R x y /\ ot_R y x.
Instance ot_equiv_Equivalence A `{OType A} : Equivalence ot_equiv.
Proof.
constructor; intro; intros.
{ split; reflexivity. }
{ destruct H0; split; assumption. }
{ destruct H0; destruct H1; split; transitivity y; assumption. }
Qed.
Notation "x <o= y" :=
(ot_R x y) (no associativity, at level 70).
Notation "x =o= y" :=
(ot_equiv x y) (no associativity, at level 70).
(* FIXME: replace "ot_R" below with "<o=" notation *)
(* FIXME: figure out what versions of this we need for rewriting! *)
Instance Proper_ot_R_ot_R A `{OType A}
: Proper (ot_R --> ot_R ==> Basics.impl) (@ot_R A _).
Proof.
intros a1 a2 Ra b1 b2 Rb Rab.
transitivity a1; [ assumption | ]. transitivity b1; assumption.
Qed.
Instance Subrelation_ot_equiv_ot_R A `{OTRelation A} :
subrelation (@ot_equiv A _) ot_R.
Proof.
intros a1 a2 Ra; destruct Ra; assumption.
Qed.
Instance Proper_ot_equiv_ot_R A `{OType A} :
Proper (ot_equiv ==> ot_equiv ==> iff) (@ot_R A _).
Proof.
intros x1 x2 Rx y1 y2 Ry; destruct Rx; destruct Ry; split; intro Rxy.
transitivity x1; [ assumption | ]; transitivity y1; assumption.
transitivity x2; [ assumption | ]; transitivity y2; assumption.
Qed.
Instance Proper_ot_equiv A `{OType A} :
Proper (ot_equiv ==> ot_equiv ==> iff) (@ot_equiv A _).
Proof.
intros x1 x2 Rx y1 y2 Ry. rewrite Rx. rewrite Ry. reflexivity.
Qed.
Instance Proper_ot_equiv_partial A `{OType A} a :
Proper (ot_equiv ==> Basics.flip Basics.impl) (@ot_equiv A _ a).
Proof.
intros x1 x2 Rx. rewrite Rx. reflexivity.
Qed.
(***
*** Commonly-Used Ordered Types
***)
(* The ordered type of propositions *)
Instance OTProp_R : OTRelation Prop := Basics.impl.
Instance OTProp : OType Prop.
Proof. repeat constructor; typeclasses eauto. Qed.
(* The discrete ordered type, where things are only related to themselves; we
make this a definition, not an instance, so that it can be instantiated for
particular types. *)
Definition OTdiscrete_R (A:Type) : OTRelation A := eq.
Definition OTdiscrete A : @OType A (OTdiscrete_R A).
repeat constructor. typeclasses eauto.
Qed.
(* The only ordered type over unit is the discrete one *)
Instance OTunit_R : OTRelation unit := OTdiscrete_R unit.
Instance OTunit : OType unit := OTdiscrete unit.
(* The ordered type that flips the ordering of an underlying OType; this becomes
a type itself in Coq *)
Inductive Flip A : Type := flip (a:A).
Definition unflip {A} (f:Flip A) : A := let (x) := f in x.
Instance OTFlip_R A (R:OTRelation A) : OTRelation (Flip A) :=
fun x y => unflip y <o= unflip x.
Instance OTFlip A `{OType A} : OType (Flip A).
Proof.
repeat constructor; intro; intros.
- destruct x; compute; reflexivity.
- destruct x; destruct y; destruct z; compute; transitivity a0; assumption.
Qed.
(* The pointwise relation on pairs *)
Instance OTpair_R A B (RA:OTRelation A) (RB:OTRelation B) : OTRelation (A*B) :=
fun p1 p2 => ot_R (fst p1) (fst p2) /\ ot_R (snd p1) (snd p2).
Instance OTpair A B `(OType A) `(OType B) : OType (A*B).
Proof.
repeat constructor.
- destruct x. reflexivity.
- destruct x. reflexivity.
- destruct x; destruct y; destruct z; destruct H1; destruct H2;
transitivity a0; assumption.
- destruct x; destruct y; destruct z; destruct H1; destruct H2;
transitivity b0; assumption.
Qed.
(* The sort-of pointwise relation on sum types *)
Inductive sumR {A B} (RA:OTRelation A) (RB:OTRelation B) : A+B -> A+B -> Prop :=
| sumR_inl a1 a2 : RA a1 a2 -> sumR RA RB (inl a1) (inl a2)
| sumR_inr b1 b2 : RB b1 b2 -> sumR RA RB (inr b1) (inr b2).
Instance OTsum_R A B (RA:OTRelation A) (RB:OTRelation B) : OTRelation (A+B) :=
sumR RA RB.
Instance OTsum A B `(OType A) `(OType B) : OType (A+B).
Proof.
repeat constructor; intro; intros.
{ destruct x; constructor; reflexivity. }
{ destruct H1; inversion H2.
- constructor; transitivity a2; assumption.
- constructor; transitivity b2; assumption. }
Qed.
(* NOTE: the following definition requires everything above to be polymorphic *)
(* NOTE: The definition we choose for OTType is actually deep: instead of
requiring ot_Type A = ot_Type B, we could just require a coercion function from
ot_Type A to ot_Type B, which would yield something more like HoTT... though
maybe it wouldn't work unless we assumed the HoTT axiom? As it is, we might need
UIP to hold if we want to use the definition given here... *)
(*
Program Definition OTType : OType :=
{|
ot_Type := OType;
ot_R := (fun A B =>
exists (e:ot_Type A = ot_Type B),
forall (x y:A),
ot_R A x y ->
ot_R B (rew [fun A => A] e in x)
(rew [fun A => A] e in y));
|}.
*)
(***
*** Proper Instances for Simple Ordered Types
***)
Instance Proper_pair A B `{OTRelation A} `{OTRelation B} :
Proper (ot_R ==> ot_R ==> ot_R) (pair : A -> B -> A*B).
Proof.
repeat intro; split; assumption.
Qed.
Instance Proper_pair_equiv A B `{OTRelation A} `{OTRelation B} :
Proper (ot_equiv ==> ot_equiv ==> ot_equiv) (pair : A -> B -> A*B).
Proof.
intros a1 a2 Ra b1 b2 Rb; destruct Ra; destruct Rb; split; split; assumption.
Qed.
Instance Proper_fst A B `{OTRelation A} `{OTRelation B} :
Proper (ot_R ==> ot_R) (fst : A*B -> A).
Proof.
intros p1 p2 Rp; destruct Rp; assumption.
Qed.
Instance Proper_fst_equiv A B `{OTRelation A} `{OTRelation B} :
Proper (ot_equiv ==> ot_equiv) (fst : A*B -> A).
Proof.
intros p1 p2 Rp. destruct Rp.
split; eapply Proper_fst; assumption.
Qed.
Instance Proper_snd A B `{OTRelation A} `{OTRelation B} :
Proper (ot_R ==> ot_R) (snd : A*B -> B).
Proof.
intros p1 p2 Rp; destruct Rp; assumption.
Qed.
Instance Proper_snd_equiv A B `{OTRelation A} `{OTRelation B} :
Proper (ot_equiv ==> ot_equiv) (snd : A*B -> B).
Proof.
intros p1 p2 Rp. destruct Rp.
split; eapply Proper_snd; assumption.
Qed.
(***
*** The Ordered Type for Functions
***)
(* The type of continuous, i.e. Proper, functions between ordered types *)
Record Pfun A B {RA:OTRelation A} {RB:OTRelation B} :=
{
pfun_app : A -> B;
pfun_Proper : Proper (ot_R ==> ot_R) pfun_app
}.
Arguments pfun_app {_ _ _ _} _ _.
Arguments pfun_Proper [_ _ _ _] _ _ _ _.
Notation "A '-o>' B" :=
(Pfun A B) (right associativity, at level 99).
Notation "x @o@ y" :=
(pfun_app x y) (left associativity, at level 20).
(* The non-dependent function ordered type *)
Instance OTarrow_R A B {RA:OTRelation A} {RB:OTRelation B} : OTRelation (A -o> B) :=
fun f g =>
forall a1 a2, ot_R a1 a2 -> ot_R (pfun_app f a1) (pfun_app g a2).
Instance OTarrow A B `{OType A} `{OType B} : OType (A -o> B).
Proof.
repeat constructor; intro; intros; intro; intros.
{ apply pfun_Proper; assumption. }
{ transitivity (pfun_app y a1).
- apply H1; reflexivity.
- apply H2; assumption. }
Qed.
(* FIXME: could also do a forall type, but need the second type argument, B, to
itself be proper, i.e., to be an element of OTarrow A OType. *)
(* pfun_app is always Proper *)
Instance Proper_pfun_app A B `{OTRelation A} `{OTRelation B} :
Proper (ot_R ==> ot_R ==> ot_R) (@pfun_app A B _ _).
Proof.
intros f1 f2 Rf a1 a2 Ra. apply Rf; assumption.
Qed.
(* pfun_app is always Proper w.r.t. ot_equiv *)
Instance Proper_pfun_app_equiv A B `{OTRelation A} `{OTRelation B} :
Proper (ot_equiv ==> ot_equiv ==> ot_equiv) (@pfun_app A B _ _).
Proof.
intros f1 f2 Rf a1 a2 Ra; destruct Rf; destruct Ra.
split; apply Proper_pfun_app; assumption.
Qed.
Instance Proper_pfun_app_partial A B `{OTRelation A} `{OTRelation B} f :
Proper (ot_R ==> ot_R) (pfun_app (A:=A) (B:=B) f).
Proof.
apply pfun_Proper.
Qed.
Instance Proper_pfun_app_partial_equiv A B `{OTRelation A} `{OTRelation B} f :
Proper (ot_equiv ==> ot_equiv) (@pfun_app A B _ _ f).
Proof.
intros a1 a2 Ra; destruct Ra; split; apply pfun_Proper; assumption.
Qed.
(***
*** Ordered Expressions
***)
(* Helper typeclass to control instantiation of Proper instances when we build
Proper functions in OExpr types *)
Class ProperPfun {A B} {RA:OTRelation A} {RB:OTRelation B} f : Prop :=
properPFun : Proper (RA ==> RB) f.
(* Helper for building pfuns *)
Definition mkPfun {A B RA RB} f (prp:@ProperPfun A B RA RB f) : A -o> B :=
{| pfun_app := f; pfun_Proper := prp |}.
Inductive OExpr : forall A {RA:OTRelation A} (a1 a2:A), Type :=
| Embed {A} {RA:OTRelation A} {a1 a2:A} (Ra:RA a1 a2) :
@OExpr A RA a1 a2
| App {A B} {RA:OTRelation A} {RB:OTRelation B} {f1 f2 a1 a2}
(e1: OExpr (A -o> B) f1 f2) (e2: OExpr A a1 a2) :
OExpr B (f1 @o@ a1) (f2 @o@ a2)
| Lam {A B} {RA:OTRelation A} {RB:OTRelation B} {f1 f2}
(e: forall (a1 a2:A), RA a1 a2 -> OExpr B (f1 a1) (f2 a2))
{prp1 prp2} :
OExpr (A -o> B) (mkPfun f1 prp1) (mkPfun f2 prp2)
.
(* An ordered expression is always indexed by related objects *)
Lemma Parametricity {A RA a1 a2} (e:@OExpr A RA a1 a2) : RA a1 a2.
Proof.
induction e.
- assumption.
- apply Proper_pfun_app; assumption.
- exact H.
Qed.
FIXME HERE NOW: this is not going to work!!
(* Instance to build a ProperPfun for the first function in a Lam constructor *)
Instance ProperPfun_Lam1 {A B} {RA:OTRelation A} {RB:OTRelation B} {f1 f2}
(e: forall (a1 a2:A), RA a1 a2 -> OExpr B (f1 a1) (f2 a2)) :
ProperPfun f1.
Proof.
intros a1 a2 Ra. apply Parametricity. apply e.
Definition mkLam {A B} {RA:OTRelation A} {RB:OTRelation B} {f1 f2}
(f: forall {a1 a2}, OExpr A a1 a2 -> OExpr B (f1 a1) (f2 a2)) :
OExpr (A -> B) f1 f2 :=
Lam (fun a1 a2 Ra => f (Embed Ra)).
Definition OConst A {RA:OTRelation A} {a} : Prop :=
Proper RA a.
Definition ott : @OConst unit _ tt := eq_refl.
Definition opair {A} {RA:OTRelation A} {B} {RB:OTRelation B} :
@OConst _ _ (pair (A:=A) (B:=B)).
Proof.
repeat intro; split; assumption.
Qed.
Definition ofst A {RA:OTRelation A} B {RB:OTRelation B} :
@OConst _ _ (fst (A:=A) (B:=B)).
Proof.
intros p1 p2 Rp; destruct Rp; assumption.
Qed.
Check (fun A {RA:OTRelation A} => mkLam (fun (_:A) _ x => x)).
Check (mkLam (A:=unit) (fun _ _ x => Embed ott)).
Check (mkLam (A:=unit -> unit) (fun _ _ f => App f (Embed ott))).
Check (mkLam (fun _ _ f =>
App f (App (App (Embed opair) (Embed ott)) (Embed ott)))).
|
module TailLight(
input reset, left, right, clk,
output LC, LB, LA, RA, RB, RC
);
parameter ST_IDLE = 3'b000;
parameter ST_L1 = 3'b001;
parameter ST_L2 = 3'b010;
parameter ST_L3 = 3'b011;
parameter ST_R1 = 3'b100;
parameter ST_R2 = 3'b101;
parameter ST_R3 = 3'b110;
reg [2:0] state, next_state;
always @(posedge clk)
if (reset)
state <= ST_IDLE;
else
state <= next_state;
always @*
begin
case (state)
ST_IDLE: begin
if (left && ~right)
next_state = ST_L1;
else if (~left && right)
next_state = ST_R1;
else
next_state = ST_IDLE;
end
ST_L1: next_state = ST_L2;
ST_L2: next_state = ST_L3;
ST_R1: next_state = ST_R2;
ST_R2: next_state = ST_R3;
default: next_state = ST_IDLE;
endcase
if (left && right)
next_state = ST_IDLE;
end
assign LA = state == ST_L1 || state == ST_L2 || state == ST_L3;
assign LB = state == ST_L2 || state == ST_L3;
assign LC = state == ST_L3;
assign RA = state == ST_R1 || state == ST_R2 || state == ST_R3;
assign RB = state == ST_R2 || state == ST_R3;
assign RC = state == ST_R3;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22AI_BLACKBOX_V
`define SKY130_FD_SC_HD__O22AI_BLACKBOX_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o22ai (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22AI_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4_0_V
`define SKY130_FD_SC_LP__NOR4_0_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4_0 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4_0 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4_0_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22OI_1_V
`define SKY130_FD_SC_MS__A22OI_1_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a22oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a22oi_1 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22OI_1_V
|
// Author: Adam Nunez, [email protected]
// Copyright (C) 2015 Adam Nunez
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module LFSR25000(
input Clock,
input Reset,
output reg Out
);
// This module accepts 1 input plus a clock and returns 1
// on output after 25000 clock cycles have passed.
reg [14:0] LFSR;
always @(posedge Clock, negedge Reset) begin
if(Reset==0) begin
Out <= 0;
LFSR <= 15'b111111111111111;
end
else begin
LFSR[0] <= LFSR[13] ^ LFSR[14];
LFSR[14:1] <= LFSR[13:0];
if(LFSR==15'b001000010001100) Out <= 1;
end
end
endmodule |
// STD 10-30-16
//
// Synchronous 1-port ram with byte masking
// Only one read or one write may be done per cycle.
//
module bsg_mem_1rw_sync_mask_write_byte #(parameter `BSG_INV_PARAM(els_p )
,parameter `BSG_INV_PARAM(data_width_p )
,parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
,parameter write_mask_width_lp = data_width_p>>3
)
(input clk_i
,input reset_i
,input v_i
,input w_i
,input [addr_width_lp-1:0] addr_i
,input [data_width_p-1:0] data_i
,input [write_mask_width_lp-1:0] write_mask_i
,output [data_width_p-1:0] data_o
);
if ((els_p == 1024) & (data_width_p == 32))
begin : macro
wire [31:0] wen = ~{{8{write_mask_i[3]}}
,{8{write_mask_i[2]}}
,{8{write_mask_i[1]}}
,{8{write_mask_i[0]}}};
tsmc16_1rw_lg10_w32_byte mem
(.CLK (clk_i )
,.Q (data_o) // out
,.CEN (~v_i ) // lo true
,.WEN (wen )
,.GWEN (~w_i ) // lo true
,.A (addr_i) // in
,.D (data_i) // in
,.STOV (1'd0 ) // Self-timing Override - disabled
,.EMA (3'd3 ) // Extra Margin Adjustment - default value
,.EMAW (2'd1 ) // Extra Margin Adjustment Write - default value
,.EMAS (1'd0 ) // Extra Margin Adjustment Sense Amp. - default value
,.RET1N (1'b1 ) // Retention Mode (active low) - disabled
);
end // block: macro
// no hardened version found
else
begin: notmacro
// Instantiate a synthesizale 1rw sync mask write byte
bsg_mem_1rw_sync_mask_write_byte_synth #(.els_p(els_p), .data_width_p(data_width_p)) synth (.*);
end // block: notmacro
// synopsys translate_off
always_comb
assert (data_width_p % 8 == 0)
else $error("data width should be a multiple of 8 for byte masking");
initial
begin
$display("## bsg_mem_1rw_sync_mask_write_byte: instantiating data_width_p=%d, els_p=%d (%m)",data_width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_byte)
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench (
// inputs:
D_iw,
D_iw_op,
D_iw_opx,
D_valid,
E_alu_result,
E_mem_byte_en,
E_st_data,
E_valid,
F_pcb,
F_valid,
R_ctrl_exception,
R_ctrl_ld,
R_ctrl_ld_non_io,
R_dst_regnum,
R_wr_dst_reg,
W_bstatus_reg,
W_cmp_result,
W_estatus_reg,
W_ienable_reg,
W_ipending_reg,
W_mem_baddr,
W_rf_wr_data,
W_status_reg,
W_valid,
W_vinst,
W_wr_data,
av_ld_data_aligned_unfiltered,
clk,
d_address,
d_byteenable,
d_read,
d_write_nxt,
i_address,
i_read,
i_readdata,
i_waitrequest,
reset_n,
// outputs:
av_ld_data_aligned_filtered,
d_write,
test_has_ended
)
;
output [ 31: 0] av_ld_data_aligned_filtered;
output d_write;
output test_has_ended;
input [ 31: 0] D_iw;
input [ 5: 0] D_iw_op;
input [ 5: 0] D_iw_opx;
input D_valid;
input [ 31: 0] E_alu_result;
input [ 3: 0] E_mem_byte_en;
input [ 31: 0] E_st_data;
input E_valid;
input [ 16: 0] F_pcb;
input F_valid;
input R_ctrl_exception;
input R_ctrl_ld;
input R_ctrl_ld_non_io;
input [ 4: 0] R_dst_regnum;
input R_wr_dst_reg;
input W_bstatus_reg;
input W_cmp_result;
input W_estatus_reg;
input [ 31: 0] W_ienable_reg;
input [ 31: 0] W_ipending_reg;
input [ 18: 0] W_mem_baddr;
input [ 31: 0] W_rf_wr_data;
input W_status_reg;
input W_valid;
input [ 55: 0] W_vinst;
input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk;
input [ 18: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write_nxt;
input [ 16: 0] i_address;
input i_read;
input [ 31: 0] i_readdata;
input i_waitrequest;
input reset_n;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire av_ld_data_aligned_unfiltered_0_is_x;
wire av_ld_data_aligned_unfiltered_10_is_x;
wire av_ld_data_aligned_unfiltered_11_is_x;
wire av_ld_data_aligned_unfiltered_12_is_x;
wire av_ld_data_aligned_unfiltered_13_is_x;
wire av_ld_data_aligned_unfiltered_14_is_x;
wire av_ld_data_aligned_unfiltered_15_is_x;
wire av_ld_data_aligned_unfiltered_16_is_x;
wire av_ld_data_aligned_unfiltered_17_is_x;
wire av_ld_data_aligned_unfiltered_18_is_x;
wire av_ld_data_aligned_unfiltered_19_is_x;
wire av_ld_data_aligned_unfiltered_1_is_x;
wire av_ld_data_aligned_unfiltered_20_is_x;
wire av_ld_data_aligned_unfiltered_21_is_x;
wire av_ld_data_aligned_unfiltered_22_is_x;
wire av_ld_data_aligned_unfiltered_23_is_x;
wire av_ld_data_aligned_unfiltered_24_is_x;
wire av_ld_data_aligned_unfiltered_25_is_x;
wire av_ld_data_aligned_unfiltered_26_is_x;
wire av_ld_data_aligned_unfiltered_27_is_x;
wire av_ld_data_aligned_unfiltered_28_is_x;
wire av_ld_data_aligned_unfiltered_29_is_x;
wire av_ld_data_aligned_unfiltered_2_is_x;
wire av_ld_data_aligned_unfiltered_30_is_x;
wire av_ld_data_aligned_unfiltered_31_is_x;
wire av_ld_data_aligned_unfiltered_3_is_x;
wire av_ld_data_aligned_unfiltered_4_is_x;
wire av_ld_data_aligned_unfiltered_5_is_x;
wire av_ld_data_aligned_unfiltered_6_is_x;
wire av_ld_data_aligned_unfiltered_7_is_x;
wire av_ld_data_aligned_unfiltered_8_is_x;
wire av_ld_data_aligned_unfiltered_9_is_x;
reg d_write;
wire test_has_ended;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_write <= 0;
else
d_write <= d_write_nxt;
end
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(F_valid) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/F_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(D_valid) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/D_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(R_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/R_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/W_wr_data is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(R_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/R_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read & ~i_waitrequest)
if (^(i_readdata) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/i_readdata is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_ctrl_ld)
if (^(av_ld_data_aligned_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: WARNING: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/W_wr_data is 'x'\n", $time);
end
end
reg [31:0] trace_handle; // for $fopen
initial
begin
trace_handle = $fopen("altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst.tr");
$fwrite(trace_handle, "version 3\nnumThreads 1\n");
end
always @(posedge clk)
begin
if ((~reset_n || (W_valid)) && ~test_has_ended)
$fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h\n", $time, ~reset_n, F_pcb, 0, D_op_intr, D_op_hbreak, D_iw, ~(D_op_intr | D_op_hbreak), R_wr_dst_reg, R_dst_regnum, 0, W_rf_wr_data, W_mem_baddr, E_st_data, E_mem_byte_en, W_cmp_result, E_alu_result, W_status_reg, W_estatus_reg, W_bstatus_reg, W_ienable_reg, W_ipending_reg, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, R_ctrl_exception, 0, 0, 0, 0);
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_1_V
`define SKY130_FD_SC_HVL__NOR3_1_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__nor3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__nor3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_NSR_BLACKBOX_V
`define SKY130_FD_SC_LS__UDP_DFF_NSR_BLACKBOX_V
/**
* udp_dff$NSR: Negative edge triggered D flip-flop (Q output UDP)
* with both active high reset and set (set dominate).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dff$NSR (
Q ,
SET ,
RESET,
CLK_N,
D
);
output Q ;
input SET ;
input RESET;
input CLK_N;
input D ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_NSR_BLACKBOX_V
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
module jt51_lin2exp(
input [15:0] lin,
output reg [9:0] man,
output reg [2:0] exp
);
always @(*) begin
casez( lin[15:9] )
// negative numbers
7'b10?????: begin
man = lin[15:6];
exp = 3'd7;
end
7'b110????: begin
man = lin[14:5];
exp = 3'd6;
end
7'b1110???: begin
man = lin[13:4];
exp = 3'd5;
end
7'b11110??: begin
man = lin[12:3];
exp = 3'd4;
end
7'b111110?: begin
man = lin[11:2];
exp = 3'd3;
end
7'b1111110: begin
man = lin[10:1];
exp = 3'd2;
end
7'b1111111: begin
man = lin[ 9:0];
exp = 3'd1;
end
// positive numbers
7'b01?????: begin
man = lin[15:6];
exp = 3'd7;
end
7'b001????: begin
man = lin[14:5];
exp = 3'd6;
end
7'b0001???: begin
man = lin[13:4];
exp = 3'd5;
end
7'b00001??: begin
man = lin[12:3];
exp = 3'd4;
end
7'b000001?: begin
man = lin[11:2];
exp = 3'd3;
end
7'b0000001: begin
man = lin[10:1];
exp = 3'd2;
end
7'b0000000: begin
man = lin[ 9:0];
exp = 3'd1;
end
default: begin
man = lin[9:0];
exp = 3'd1;
end
endcase
end
endmodule
|
/*******************************************************************************
* Module: pll_base
* Date:2014-05-01
* Author: Andrey Filippov
* Description: PLLE2_BASE wrapper
*
* Copyright (c) 2014 Elphel, Inc.
* pll_base.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* pll_base.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module pll_base#(
parameter CLKIN_PERIOD = 0.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter BANDWIDTH = "OPTIMIZED", // "OPTIMIZED", "HIGH","LOW"
parameter CLKFBOUT_MULT = 1, // integer 1 to 64 . Together with CLKOUT#_DIVIDE and DIVCLK_DIVIDE
parameter CLKFBOUT_PHASE = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter CLKOUT0_PHASE = 0.000, // CLOCK0 phase in degrees (3 significant digits, -360.000...+360.000)
parameter CLKOUT1_PHASE = 0.000, // Initial/static fine phase shift, 1/(56*Fvco) actual step
parameter CLKOUT2_PHASE = 0.000,
parameter CLKOUT3_PHASE = 0.000,
parameter CLKOUT4_PHASE = 0.000,
parameter CLKOUT5_PHASE = 0.000,
parameter CLKOUT0_DUTY_CYCLE= 0.5, // CLOCK 0 output duty factor, 3 significant digits
parameter CLKOUT1_DUTY_CYCLE= 0.5,
parameter CLKOUT2_DUTY_CYCLE= 0.5,
parameter CLKOUT3_DUTY_CYCLE= 0.5,
parameter CLKOUT4_DUTY_CYCLE= 0.5,
parameter CLKOUT5_DUTY_CYCLE= 0.5,
parameter CLKOUT0_DIVIDE = 1, // CLK0 outout divide, integer 1..128
parameter CLKOUT1_DIVIDE = 1, // CLK1 outout divide, integer 1..128 (determins a phase step as a fraction of pi/4)
parameter CLKOUT2_DIVIDE = 1,
parameter CLKOUT3_DIVIDE = 1,
parameter CLKOUT4_DIVIDE = 1,
parameter CLKOUT5_DIVIDE = 1,
parameter DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter STARTUP_WAIT = "FALSE" // Delays "DONE" signal until MMCM is locked
)
(
input clkin, // General clock input
input clkfbin, // Feedback clock input
input rst, // asynchronous reset input
input pwrdwn, // power down input
output clkout0, // output 0, HPC BUFR/BUFIO capable
output clkout1, // output 1, HPC BUFR/BUFIO capable
output clkout2, // output 2, HPC BUFR/BUFIO capable
output clkout3, // output 3, HPC BUFR/BUFIO capable
output clkout4, // output 4, HPC BUFR/BUFIO not capable
output clkout5, // output 5, HPC BUFR/BUFIO not capable
output clkfbout, // dedicate feedback output
output locked // PLL locked output
);
PLLE2_BASE #(
.BANDWIDTH (BANDWIDTH),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.CLKIN1_PERIOD (CLKIN_PERIOD),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
.CLKOUT0_DUTY_CYCLE (CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE (CLKOUT0_PHASE),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE (CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE (CLKOUT1_PHASE),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE (CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE (CLKOUT2_PHASE),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE (CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE (CLKOUT3_PHASE),
.CLKOUT4_DIVIDE (CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE (CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE (CLKOUT4_PHASE),
.CLKOUT5_DIVIDE (CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE (CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE (CLKOUT5_PHASE),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.REF_JITTER1 (REF_JITTER1),
.STARTUP_WAIT (STARTUP_WAIT)
) PLLE2_BASE_i (
.CLKFBOUT (clkfbout), // output
.CLKOUT0 (clkout0), // output
.CLKOUT1 (clkout1), // output
.CLKOUT2 (clkout2), // output
.CLKOUT3 (clkout3), // output
.CLKOUT4 (clkout4), // output
.CLKOUT5 (clkout5), // output
.LOCKED (locked), // output
.CLKFBIN (clkfbin), // input
.CLKIN1 (clkin), // input
.PWRDWN (pwrdwn), // input
.RST (rst) // input
);
endmodule
|
module tb_ShiftRegister #(
parameter DATA_BITS = 8,
parameter MATRIX_SIZE = 8,
parameter OUTPUT_SIZE = 2*MATRIX_SIZE-1
) ();
reg clock;
reg reset;
reg load;
reg shift;
reg [DATA_BITS-1:0] data_in [0:MATRIX_SIZE-1][0:OUTPUT_SIZE-1];
wire [DATA_BITS-1:0] data_out [0:MATRIX_SIZE-1];
ShiftRegister #(
.DATA_BITS(DATA_BITS),
.MATRIX_SIZE(MATRIX_SIZE),
.OUTPUT_SIZE(OUTPUT_SIZE)
) DUT (
.clock(clock),
.reset(reset),
.load(load),
.shift(shift),
.data_in(data_in),
.data_out(data_out)
);
integer count;
initial begin
clock = 1'b0;
reset = 1'b0;
load = 1'b0;
shift = 1'b0;
$dumpfile("ShiftRegister.vcd") ;
$dumpvars;
end
always begin
#5 clock = ~clock;
#5 clock = ~clock;
end
always @(data_out) begin
$display("data_out[0] at %0t",data_out[0],$time);
$display("data_out[7] at %0t",data_out[7],$time);
end
initial begin
#10 reset = 1'b1;
#20 reset = 1'b0;
#200
#10 load = 1'b1;
#30
count=0;
for (integer i=0;i<MATRIX_SIZE;i++)
for (integer j =0; j< OUTPUT_SIZE;j++) begin
data_in[i][j]=count;
count= count+1;
end
#10 load = 1'b0;
#100 shift = 1'b1;
#250
#50 shift = 1'b0;
#50 $finish;
end
endmodule
|
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_test_bench (
// inputs:
D_iw,
D_iw_op,
D_iw_opx,
D_valid,
E_valid,
F_pcb,
F_valid,
R_ctrl_ld,
R_ctrl_ld_non_io,
R_dst_regnum,
R_wr_dst_reg,
W_valid,
W_vinst,
W_wr_data,
av_ld_data_aligned_unfiltered,
clk,
d_address,
d_byteenable,
d_read,
d_write,
i_address,
i_read,
i_readdata,
i_waitrequest,
reset_n,
// outputs:
av_ld_data_aligned_filtered,
test_has_ended
)
;
output [ 31: 0] av_ld_data_aligned_filtered;
output test_has_ended;
input [ 31: 0] D_iw;
input [ 5: 0] D_iw_op;
input [ 5: 0] D_iw_opx;
input D_valid;
input E_valid;
input [ 19: 0] F_pcb;
input F_valid;
input R_ctrl_ld;
input R_ctrl_ld_non_io;
input [ 4: 0] R_dst_regnum;
input R_wr_dst_reg;
input W_valid;
input [ 71: 0] W_vinst;
input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk;
input [ 26: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write;
input [ 19: 0] i_address;
input i_read;
input [ 31: 0] i_readdata;
input i_waitrequest;
input reset_n;
wire D_is_opx_inst;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_op_rsv02;
wire D_op_op_rsv09;
wire D_op_op_rsv10;
wire D_op_op_rsv17;
wire D_op_op_rsv18;
wire D_op_op_rsv25;
wire D_op_op_rsv26;
wire D_op_op_rsv33;
wire D_op_op_rsv34;
wire D_op_op_rsv41;
wire D_op_op_rsv42;
wire D_op_op_rsv49;
wire D_op_op_rsv57;
wire D_op_op_rsv61;
wire D_op_op_rsv62;
wire D_op_op_rsv63;
wire D_op_opx_rsv00;
wire D_op_opx_rsv10;
wire D_op_opx_rsv15;
wire D_op_opx_rsv17;
wire D_op_opx_rsv21;
wire D_op_opx_rsv25;
wire D_op_opx_rsv33;
wire D_op_opx_rsv34;
wire D_op_opx_rsv35;
wire D_op_opx_rsv42;
wire D_op_opx_rsv43;
wire D_op_opx_rsv44;
wire D_op_opx_rsv47;
wire D_op_opx_rsv50;
wire D_op_opx_rsv51;
wire D_op_opx_rsv55;
wire D_op_opx_rsv56;
wire D_op_opx_rsv60;
wire D_op_opx_rsv63;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire av_ld_data_aligned_unfiltered_0_is_x;
wire av_ld_data_aligned_unfiltered_10_is_x;
wire av_ld_data_aligned_unfiltered_11_is_x;
wire av_ld_data_aligned_unfiltered_12_is_x;
wire av_ld_data_aligned_unfiltered_13_is_x;
wire av_ld_data_aligned_unfiltered_14_is_x;
wire av_ld_data_aligned_unfiltered_15_is_x;
wire av_ld_data_aligned_unfiltered_16_is_x;
wire av_ld_data_aligned_unfiltered_17_is_x;
wire av_ld_data_aligned_unfiltered_18_is_x;
wire av_ld_data_aligned_unfiltered_19_is_x;
wire av_ld_data_aligned_unfiltered_1_is_x;
wire av_ld_data_aligned_unfiltered_20_is_x;
wire av_ld_data_aligned_unfiltered_21_is_x;
wire av_ld_data_aligned_unfiltered_22_is_x;
wire av_ld_data_aligned_unfiltered_23_is_x;
wire av_ld_data_aligned_unfiltered_24_is_x;
wire av_ld_data_aligned_unfiltered_25_is_x;
wire av_ld_data_aligned_unfiltered_26_is_x;
wire av_ld_data_aligned_unfiltered_27_is_x;
wire av_ld_data_aligned_unfiltered_28_is_x;
wire av_ld_data_aligned_unfiltered_29_is_x;
wire av_ld_data_aligned_unfiltered_2_is_x;
wire av_ld_data_aligned_unfiltered_30_is_x;
wire av_ld_data_aligned_unfiltered_31_is_x;
wire av_ld_data_aligned_unfiltered_3_is_x;
wire av_ld_data_aligned_unfiltered_4_is_x;
wire av_ld_data_aligned_unfiltered_5_is_x;
wire av_ld_data_aligned_unfiltered_6_is_x;
wire av_ld_data_aligned_unfiltered_7_is_x;
wire av_ld_data_aligned_unfiltered_8_is_x;
wire av_ld_data_aligned_unfiltered_9_is_x;
wire test_has_ended;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_op_rsv02 = D_iw_op == 2;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_op_rsv09 = D_iw_op == 9;
assign D_op_op_rsv10 = D_iw_op == 10;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_op_rsv17 = D_iw_op == 17;
assign D_op_op_rsv18 = D_iw_op == 18;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_op_rsv25 = D_iw_op == 25;
assign D_op_op_rsv26 = D_iw_op == 26;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_op_rsv33 = D_iw_op == 33;
assign D_op_op_rsv34 = D_iw_op == 34;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_op_rsv41 = D_iw_op == 41;
assign D_op_op_rsv42 = D_iw_op == 42;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_op_rsv49 = D_iw_op == 49;
assign D_op_custom = D_iw_op == 50;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_op_rsv57 = D_iw_op == 57;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_op_rsv61 = D_iw_op == 61;
assign D_op_op_rsv62 = D_iw_op == 62;
assign D_op_op_rsv63 = D_iw_op == 63;
assign D_op_opx_rsv00 = (D_iw_opx == 0) & D_is_opx_inst;
assign D_op_eret = (D_iw_opx == 1) & D_is_opx_inst;
assign D_op_roli = (D_iw_opx == 2) & D_is_opx_inst;
assign D_op_rol = (D_iw_opx == 3) & D_is_opx_inst;
assign D_op_flushp = (D_iw_opx == 4) & D_is_opx_inst;
assign D_op_ret = (D_iw_opx == 5) & D_is_opx_inst;
assign D_op_nor = (D_iw_opx == 6) & D_is_opx_inst;
assign D_op_mulxuu = (D_iw_opx == 7) & D_is_opx_inst;
assign D_op_cmpge = (D_iw_opx == 8) & D_is_opx_inst;
assign D_op_bret = (D_iw_opx == 9) & D_is_opx_inst;
assign D_op_opx_rsv10 = (D_iw_opx == 10) & D_is_opx_inst;
assign D_op_ror = (D_iw_opx == 11) & D_is_opx_inst;
assign D_op_flushi = (D_iw_opx == 12) & D_is_opx_inst;
assign D_op_jmp = (D_iw_opx == 13) & D_is_opx_inst;
assign D_op_and = (D_iw_opx == 14) & D_is_opx_inst;
assign D_op_opx_rsv15 = (D_iw_opx == 15) & D_is_opx_inst;
assign D_op_cmplt = (D_iw_opx == 16) & D_is_opx_inst;
assign D_op_opx_rsv17 = (D_iw_opx == 17) & D_is_opx_inst;
assign D_op_slli = (D_iw_opx == 18) & D_is_opx_inst;
assign D_op_sll = (D_iw_opx == 19) & D_is_opx_inst;
assign D_op_wrprs = (D_iw_opx == 20) & D_is_opx_inst;
assign D_op_opx_rsv21 = (D_iw_opx == 21) & D_is_opx_inst;
assign D_op_or = (D_iw_opx == 22) & D_is_opx_inst;
assign D_op_mulxsu = (D_iw_opx == 23) & D_is_opx_inst;
assign D_op_cmpne = (D_iw_opx == 24) & D_is_opx_inst;
assign D_op_opx_rsv25 = (D_iw_opx == 25) & D_is_opx_inst;
assign D_op_srli = (D_iw_opx == 26) & D_is_opx_inst;
assign D_op_srl = (D_iw_opx == 27) & D_is_opx_inst;
assign D_op_nextpc = (D_iw_opx == 28) & D_is_opx_inst;
assign D_op_callr = (D_iw_opx == 29) & D_is_opx_inst;
assign D_op_xor = (D_iw_opx == 30) & D_is_opx_inst;
assign D_op_mulxss = (D_iw_opx == 31) & D_is_opx_inst;
assign D_op_cmpeq = (D_iw_opx == 32) & D_is_opx_inst;
assign D_op_opx_rsv33 = (D_iw_opx == 33) & D_is_opx_inst;
assign D_op_opx_rsv34 = (D_iw_opx == 34) & D_is_opx_inst;
assign D_op_opx_rsv35 = (D_iw_opx == 35) & D_is_opx_inst;
assign D_op_divu = (D_iw_opx == 36) & D_is_opx_inst;
assign D_op_div = (D_iw_opx == 37) & D_is_opx_inst;
assign D_op_rdctl = (D_iw_opx == 38) & D_is_opx_inst;
assign D_op_mul = (D_iw_opx == 39) & D_is_opx_inst;
assign D_op_cmpgeu = (D_iw_opx == 40) & D_is_opx_inst;
assign D_op_initi = (D_iw_opx == 41) & D_is_opx_inst;
assign D_op_opx_rsv42 = (D_iw_opx == 42) & D_is_opx_inst;
assign D_op_opx_rsv43 = (D_iw_opx == 43) & D_is_opx_inst;
assign D_op_opx_rsv44 = (D_iw_opx == 44) & D_is_opx_inst;
assign D_op_trap = (D_iw_opx == 45) & D_is_opx_inst;
assign D_op_wrctl = (D_iw_opx == 46) & D_is_opx_inst;
assign D_op_opx_rsv47 = (D_iw_opx == 47) & D_is_opx_inst;
assign D_op_cmpltu = (D_iw_opx == 48) & D_is_opx_inst;
assign D_op_add = (D_iw_opx == 49) & D_is_opx_inst;
assign D_op_opx_rsv50 = (D_iw_opx == 50) & D_is_opx_inst;
assign D_op_opx_rsv51 = (D_iw_opx == 51) & D_is_opx_inst;
assign D_op_break = (D_iw_opx == 52) & D_is_opx_inst;
assign D_op_hbreak = (D_iw_opx == 53) & D_is_opx_inst;
assign D_op_sync = (D_iw_opx == 54) & D_is_opx_inst;
assign D_op_opx_rsv55 = (D_iw_opx == 55) & D_is_opx_inst;
assign D_op_opx_rsv56 = (D_iw_opx == 56) & D_is_opx_inst;
assign D_op_sub = (D_iw_opx == 57) & D_is_opx_inst;
assign D_op_srai = (D_iw_opx == 58) & D_is_opx_inst;
assign D_op_sra = (D_iw_opx == 59) & D_is_opx_inst;
assign D_op_opx_rsv60 = (D_iw_opx == 60) & D_is_opx_inst;
assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
assign D_is_opx_inst = D_iw_op == 58;
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(F_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/F_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(D_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/D_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(R_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/R_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/W_wr_data is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(R_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/R_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read & ~i_waitrequest)
if (^(i_readdata) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/i_readdata is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_ctrl_ld)
if (^(av_ld_data_aligned_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: wasca_nios2_gen2_0_cpu_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: WARNING: wasca_nios2_gen2_0_cpu_test_bench/W_wr_data is 'x'\n", $time);
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jan 22 23:54:01 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_0_0_sim_netlist.v
// Design : design_1_axi_gpio_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
(GPIO2_DBus_i,
GPIO_DBus_i,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg,
gpio_io_o,
gpio_io_t,
gpio2_io_o,
gpio2_io_t,
Q,
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ,
Read_Reg_Rst,
Read_Reg2_In,
s_axi_aclk,
Read_Reg_In,
SS,
bus2ip_rnw,
bus2ip_cs,
gpio_io_i,
gpio2_io_i,
E,
s_axi_wdata,
bus2ip_rnw_i_reg,
bus2ip_rnw_i_reg_0,
bus2ip_rnw_i_reg_1);
output [3:0]GPIO2_DBus_i;
output [3:0]GPIO_DBus_i;
output GPIO_xferAck_i;
output gpio_xferAck_Reg;
output ip2bus_rdack_i;
output ip2bus_wrack_i_D1_reg;
output [3:0]gpio_io_o;
output [3:0]gpio_io_t;
output [3:0]gpio2_io_o;
output [3:0]gpio2_io_t;
output [3:0]Q;
output [3:0]\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ;
input Read_Reg_Rst;
input [0:3]Read_Reg2_In;
input s_axi_aclk;
input [0:3]Read_Reg_In;
input [0:0]SS;
input bus2ip_rnw;
input bus2ip_cs;
input [3:0]gpio_io_i;
input [3:0]gpio2_io_i;
input [0:0]E;
input [3:0]s_axi_wdata;
input [0:0]bus2ip_rnw_i_reg;
input [0:0]bus2ip_rnw_i_reg_0;
input [0:0]bus2ip_rnw_i_reg_1;
wire [3:0]\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ;
wire [0:0]E;
wire [3:0]GPIO2_DBus_i;
wire [3:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [3:0]Q;
wire [0:3]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire [0:0]SS;
wire bus2ip_cs;
wire bus2ip_rnw;
wire [0:0]bus2ip_rnw_i_reg;
wire [0:0]bus2ip_rnw_i_reg_0;
wire [0:0]bus2ip_rnw_i_reg_1;
wire [3:0]gpio2_io_i;
wire [0:3]gpio2_io_i_d2;
wire [3:0]gpio2_io_o;
wire [3:0]gpio2_io_t;
wire [3:0]gpio_io_i;
wire [0:3]gpio_io_i_d2;
wire [3:0]gpio_io_o;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire iGPIO_xferAck;
wire ip2bus_rdack_i;
wire ip2bus_wrack_i_D1_reg;
wire s_axi_aclk;
wire [3:0]s_axi_wdata;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \Dual.INPUT_DOUBLE_REGS4
(.gpio_io_i(gpio_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3]}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 \Dual.INPUT_DOUBLE_REGS5
(.gpio2_io_i(gpio2_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio2_io_i_d2[0],gpio2_io_i_d2[1],gpio2_io_i_d2[2],gpio2_io_i_d2[3]}));
FDRE \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[0]),
.Q(GPIO2_DBus_i[3]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[1].GPIO2_DBus_i_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[1]),
.Q(GPIO2_DBus_i[2]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[2].GPIO2_DBus_i_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[2]),
.Q(GPIO2_DBus_i[1]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[3]),
.Q(GPIO2_DBus_i[0]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[0]),
.Q(GPIO_DBus_i[3]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[1]),
.Q(GPIO_DBus_i[2]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[2]),
.Q(GPIO_DBus_i[1]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[3]),
.Q(GPIO_DBus_i[0]),
.R(Read_Reg_Rst));
FDRE \Dual.gpio2_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[0]),
.Q(Q[3]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[1]),
.Q(Q[2]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[2]),
.Q(Q[1]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[3]),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(s_axi_wdata[3]),
.Q(gpio2_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(s_axi_wdata[2]),
.Q(gpio2_io_o[2]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(s_axi_wdata[1]),
.Q(gpio2_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(s_axi_wdata[0]),
.Q(gpio2_io_o[0]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(s_axi_wdata[3]),
.Q(gpio2_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(s_axi_wdata[2]),
.Q(gpio2_io_t[2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(s_axi_wdata[1]),
.Q(gpio2_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(s_axi_wdata[0]),
.Q(gpio2_io_t[0]),
.S(SS));
FDRE \Dual.gpio_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[0]),
.Q(\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [3]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[1]),
.Q(\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [2]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[2]),
.Q(\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [1]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[3]),
.Q(\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[3]),
.Q(gpio_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[2]),
.Q(gpio_io_o[2]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[1]),
.Q(gpio_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[0]),
.Q(gpio_io_o[0]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(s_axi_wdata[3]),
.Q(gpio_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(s_axi_wdata[2]),
.Q(gpio_io_t[2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(s_axi_wdata[1]),
.Q(gpio_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(s_axi_wdata[0]),
.Q(gpio_io_t[0]),
.S(SS));
FDRE gpio_xferAck_Reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_xferAck_i),
.Q(gpio_xferAck_Reg),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h04))
iGPIO_xferAck_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_cs),
.I2(gpio_xferAck_Reg),
.O(iGPIO_xferAck));
FDRE iGPIO_xferAck_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(iGPIO_xferAck),
.Q(GPIO_xferAck_i),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
ip2bus_rdack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_rdack_i));
LUT2 #(
.INIT(4'h2))
ip2bus_wrack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_wrack_i_D1_reg));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
s_axi_arready,
s_axi_wready,
Read_Reg2_In,
E,
\Dual.gpio2_Data_Out_reg[0] ,
D,
Read_Reg_In,
\Dual.gpio_OE_reg[0] ,
\Dual.gpio_Data_Out_reg[0] ,
Read_Reg_Rst,
s_axi_aclk,
Q,
is_read,
ip2bus_rdack_i_D1,
is_write_reg,
ip2bus_wrack_i_D1,
gpio2_io_t,
\Dual.gpio2_Data_In_reg[0] ,
\bus2ip_addr_i_reg[8] ,
bus2ip_rnw_i_reg,
rst_reg,
GPIO2_DBus_i,
GPIO_DBus_i,
gpio_io_t,
\Dual.gpio_Data_In_reg[0] ,
gpio_xferAck_Reg,
GPIO_xferAck_i,
start2,
s_axi_aresetn);
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
output s_axi_arready;
output s_axi_wready;
output [0:3]Read_Reg2_In;
output [0:0]E;
output [0:0]\Dual.gpio2_Data_Out_reg[0] ;
output [3:0]D;
output [0:3]Read_Reg_In;
output [0:0]\Dual.gpio_OE_reg[0] ;
output [0:0]\Dual.gpio_Data_Out_reg[0] ;
output Read_Reg_Rst;
input s_axi_aclk;
input [3:0]Q;
input is_read;
input ip2bus_rdack_i_D1;
input is_write_reg;
input ip2bus_wrack_i_D1;
input [3:0]gpio2_io_t;
input [3:0]\Dual.gpio2_Data_In_reg[0] ;
input [2:0]\bus2ip_addr_i_reg[8] ;
input bus2ip_rnw_i_reg;
input rst_reg;
input [3:0]GPIO2_DBus_i;
input [3:0]GPIO_DBus_i;
input [3:0]gpio_io_t;
input [3:0]\Dual.gpio_Data_In_reg[0] ;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input start2;
input s_axi_aresetn;
wire [3:0]D;
wire [3:0]\Dual.gpio2_Data_In_reg[0] ;
wire [0:0]\Dual.gpio2_Data_Out_reg[0] ;
wire [3:0]\Dual.gpio_Data_In_reg[0] ;
wire [0:0]\Dual.gpio_Data_Out_reg[0] ;
wire [0:0]\Dual.gpio_OE_reg[0] ;
wire [0:0]E;
wire [3:0]GPIO2_DBus_i;
wire [3:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
wire [3:0]Q;
wire [0:3]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire [2:0]\bus2ip_addr_i_reg[8] ;
wire bus2ip_rnw_i_reg;
wire [3:0]gpio2_io_t;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_write_reg;
wire rst_reg;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_wready;
wire start2;
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[0].GPIO2_DBus_i[28]_i_1
(.I0(gpio2_io_t[3]),
.I1(\Dual.gpio2_Data_In_reg[0] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[0]));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[1].GPIO2_DBus_i[29]_i_1
(.I0(gpio2_io_t[2]),
.I1(\Dual.gpio2_Data_In_reg[0] [2]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[1]));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[2].GPIO2_DBus_i[30]_i_1
(.I0(gpio2_io_t[1]),
.I1(\Dual.gpio2_Data_In_reg[0] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[2]));
LUT4 #(
.INIT(16'hFFDF))
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i[31]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(gpio_xferAck_Reg),
.I2(bus2ip_rnw_i_reg),
.I3(GPIO_xferAck_i),
.O(Read_Reg_Rst));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i[31]_i_2
(.I0(gpio2_io_t[0]),
.I1(\Dual.gpio2_Data_In_reg[0] [0]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[3]));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Dual.READ_REG_GEN[0].GPIO_DBus_i[28]_i_1
(.I0(gpio_io_t[3]),
.I1(\Dual.gpio_Data_In_reg[0] [3]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg_In[0]));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Dual.READ_REG_GEN[1].GPIO_DBus_i[29]_i_1
(.I0(gpio_io_t[2]),
.I1(\Dual.gpio_Data_In_reg[0] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg_In[1]));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Dual.READ_REG_GEN[2].GPIO_DBus_i[30]_i_1
(.I0(gpio_io_t[1]),
.I1(\Dual.gpio_Data_In_reg[0] [1]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg_In[2]));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Dual.READ_REG_GEN[3].GPIO_DBus_i[31]_i_1
(.I0(gpio_io_t[0]),
.I1(\Dual.gpio_Data_In_reg[0] [0]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg_In[3]));
LUT6 #(
.INIT(64'hFFFFFFFF00001000))
\Dual.gpio2_Data_Out[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(rst_reg),
.O(\Dual.gpio2_Data_Out_reg[0] ));
LUT6 #(
.INIT(64'hFFFFFFFF10000000))
\Dual.gpio2_OE[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(rst_reg),
.O(E));
LUT6 #(
.INIT(64'hFFFFFFFF00000100))
\Dual.gpio_Data_Out[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(rst_reg),
.O(\Dual.gpio_Data_Out_reg[0] ));
LUT6 #(
.INIT(64'hFFFFFFFF00040000))
\Dual.gpio_OE[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(rst_reg),
.O(\Dual.gpio_OE_reg[0] ));
LUT5 #(
.INIT(32'h000E0000))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(start2),
.I2(s_axi_wready),
.I3(s_axi_arready),
.I4(s_axi_aresetn),
.O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
.Q(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.R(1'b0));
LUT6 #(
.INIT(64'hABAAAAAAA8AAAAAA))
\ip2bus_data_i_D1[28]_i_1
(.I0(GPIO2_DBus_i[3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(bus2ip_rnw_i_reg),
.I5(GPIO_DBus_i[3]),
.O(D[3]));
LUT6 #(
.INIT(64'hABAAAAAAA8AAAAAA))
\ip2bus_data_i_D1[29]_i_1
(.I0(GPIO2_DBus_i[2]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(bus2ip_rnw_i_reg),
.I5(GPIO_DBus_i[2]),
.O(D[2]));
LUT6 #(
.INIT(64'hABAAAAAAA8AAAAAA))
\ip2bus_data_i_D1[30]_i_1
(.I0(GPIO2_DBus_i[1]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(bus2ip_rnw_i_reg),
.I5(GPIO_DBus_i[1]),
.O(D[1]));
LUT6 #(
.INIT(64'hABAAAAAAA8AAAAAA))
\ip2bus_data_i_D1[31]_i_1
(.I0(GPIO2_DBus_i[0]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(bus2ip_rnw_i_reg),
.I5(GPIO_DBus_i[0]),
.O(D[0]));
LUT6 #(
.INIT(64'hFFFFFFFF00020000))
s_axi_arready_INST_0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.I4(is_read),
.I5(ip2bus_rdack_i_D1),
.O(s_axi_arready));
LUT6 #(
.INIT(64'hFFFFFFFF00020000))
s_axi_wready_INST_0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.I4(is_write_reg),
.I5(ip2bus_wrack_i_D1),
.O(s_axi_wready));
endmodule
(* C_ALL_INPUTS = "1" *) (* C_ALL_INPUTS_2 = "1" *) (* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *) (* C_DOUT_DEFAULT = "0" *) (* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *) (* C_GPIO2_WIDTH = "4" *) (* C_GPIO_WIDTH = "4" *)
(* C_INTERRUPT_PRESENT = "0" *) (* C_IS_DUAL = "1" *) (* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rst" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt;
input [3:0]gpio_io_i;
output [3:0]gpio_io_o;
output [3:0]gpio_io_t;
input [3:0]gpio2_io_i;
output [3:0]gpio2_io_o;
output [3:0]gpio2_io_t;
wire \<const0> ;
wire AXI_LITE_IPIF_I_n_11;
wire AXI_LITE_IPIF_I_n_12;
wire AXI_LITE_IPIF_I_n_21;
wire AXI_LITE_IPIF_I_n_22;
wire [28:31]GPIO2_DBus_i;
wire [3:0]GPIO_DBus;
wire [28:31]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [0:3]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [0:3]gpio2_Data_In;
wire [3:0]gpio2_io_i;
wire [3:0]gpio2_io_o;
wire [3:0]gpio2_io_t;
wire [0:3]gpio_Data_In;
wire gpio_core_1_n_11;
wire [3:0]gpio_io_i;
wire [3:0]gpio_io_o;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [3:0]ip2bus_data_i_D1;
wire ip2bus_rdack_i;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [3:0]\^s_axi_rdata ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
assign ip2intc_irpt = \<const0> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3:0] = \^s_axi_rdata [3:0];
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
(.D(GPIO_DBus),
.\Dual.gpio2_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_12),
.\Dual.gpio_Data_In_reg[0] ({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
.\Dual.gpio_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_22),
.\Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_21),
.E(AXI_LITE_IPIF_I_n_11),
.GPIO2_DBus_i({GPIO2_DBus_i[28],GPIO2_DBus_i[29],GPIO2_DBus_i[30],GPIO2_DBus_i[31]}),
.GPIO_DBus_i({GPIO_DBus_i[28],GPIO_DBus_i[29],GPIO_DBus_i[30],GPIO_DBus_i[31]}),
.GPIO_xferAck_i(GPIO_xferAck_i),
.Q({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3]}),
.Read_Reg2_In(Read_Reg2_In),
.Read_Reg_In(Read_Reg_In),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.gpio2_io_t(gpio2_io_t),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[28] (ip2bus_data_i_D1),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(\^s_axi_rdata ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core gpio_core_1
(.\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
.E(AXI_LITE_IPIF_I_n_22),
.GPIO2_DBus_i({GPIO2_DBus_i[28],GPIO2_DBus_i[29],GPIO2_DBus_i[30],GPIO2_DBus_i[31]}),
.GPIO_DBus_i({GPIO_DBus_i[28],GPIO_DBus_i[29],GPIO_DBus_i[30],GPIO_DBus_i[31]}),
.GPIO_xferAck_i(GPIO_xferAck_i),
.Q({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3]}),
.Read_Reg2_In(Read_Reg2_In),
.Read_Reg_In(Read_Reg_In),
.Read_Reg_Rst(Read_Reg_Rst),
.SS(bus2ip_reset),
.bus2ip_cs(bus2ip_cs),
.bus2ip_rnw(bus2ip_rnw),
.bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_21),
.bus2ip_rnw_i_reg_0(AXI_LITE_IPIF_I_n_12),
.bus2ip_rnw_i_reg_1(AXI_LITE_IPIF_I_n_11),
.gpio2_io_i(gpio2_io_i),
.gpio2_io_o(gpio2_io_o),
.gpio2_io_t(gpio2_io_t),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i(ip2bus_rdack_i),
.ip2bus_wrack_i_D1_reg(gpio_core_1_n_11),
.s_axi_aclk(s_axi_aclk),
.s_axi_wdata(s_axi_wdata[3:0]));
FDRE \ip2bus_data_i_D1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[3]),
.Q(ip2bus_data_i_D1[3]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[2]),
.Q(ip2bus_data_i_D1[2]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[1]),
.Q(ip2bus_data_i_D1[1]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[0]),
.Q(ip2bus_data_i_D1[0]),
.R(bus2ip_reset));
FDRE ip2bus_rdack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_i),
.Q(ip2bus_rdack_i_D1),
.R(bus2ip_reset));
FDRE ip2bus_wrack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_core_1_n_11),
.Q(ip2bus_wrack_i_D1),
.R(bus2ip_reset));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
(bus2ip_reset,
bus2ip_rnw,
bus2ip_cs,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
s_axi_wready,
Read_Reg2_In,
E,
\Dual.gpio2_Data_Out_reg[0] ,
D,
Read_Reg_In,
\Dual.gpio_OE_reg[0] ,
\Dual.gpio_Data_Out_reg[0] ,
Read_Reg_Rst,
s_axi_rdata,
s_axi_aclk,
s_axi_arvalid,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_bready,
s_axi_rready,
s_axi_awaddr,
s_axi_araddr,
s_axi_awvalid,
s_axi_wvalid,
gpio2_io_t,
Q,
GPIO2_DBus_i,
GPIO_DBus_i,
gpio_io_t,
\Dual.gpio_Data_In_reg[0] ,
s_axi_aresetn,
gpio_xferAck_Reg,
GPIO_xferAck_i,
\ip2bus_data_i_D1_reg[28] );
output bus2ip_reset;
output bus2ip_rnw;
output bus2ip_cs;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output s_axi_wready;
output [0:3]Read_Reg2_In;
output [0:0]E;
output [0:0]\Dual.gpio2_Data_Out_reg[0] ;
output [3:0]D;
output [0:3]Read_Reg_In;
output [0:0]\Dual.gpio_OE_reg[0] ;
output [0:0]\Dual.gpio_Data_Out_reg[0] ;
output Read_Reg_Rst;
output [3:0]s_axi_rdata;
input s_axi_aclk;
input s_axi_arvalid;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input s_axi_bready;
input s_axi_rready;
input [2:0]s_axi_awaddr;
input [2:0]s_axi_araddr;
input s_axi_awvalid;
input s_axi_wvalid;
input [3:0]gpio2_io_t;
input [3:0]Q;
input [3:0]GPIO2_DBus_i;
input [3:0]GPIO_DBus_i;
input [3:0]gpio_io_t;
input [3:0]\Dual.gpio_Data_In_reg[0] ;
input s_axi_aresetn;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [3:0]\ip2bus_data_i_D1_reg[28] ;
wire [3:0]D;
wire [0:0]\Dual.gpio2_Data_Out_reg[0] ;
wire [3:0]\Dual.gpio_Data_In_reg[0] ;
wire [0:0]\Dual.gpio_Data_Out_reg[0] ;
wire [0:0]\Dual.gpio_OE_reg[0] ;
wire [0:0]E;
wire [3:0]GPIO2_DBus_i;
wire [3:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [3:0]Q;
wire [0:3]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [3:0]gpio2_io_t;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [3:0]\ip2bus_data_i_D1_reg[28] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [3:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_wready;
wire s_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
(.D(D),
.\Dual.gpio2_Data_Out_reg[0] (\Dual.gpio2_Data_Out_reg[0] ),
.\Dual.gpio2_OE_reg[0] (bus2ip_rnw),
.\Dual.gpio_Data_In_reg[0] (\Dual.gpio_Data_In_reg[0] ),
.\Dual.gpio_Data_Out_reg[0] (\Dual.gpio_Data_Out_reg[0] ),
.\Dual.gpio_OE_reg[0] (\Dual.gpio_OE_reg[0] ),
.E(E),
.GPIO2_DBus_i(GPIO2_DBus_i),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
.Q(Q),
.Read_Reg2_In(Read_Reg2_In),
.Read_Reg_In(Read_Reg_In),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_rnw_i_reg_0(bus2ip_reset),
.gpio2_io_t(gpio2_io_t),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[28] (\ip2bus_data_i_D1_reg[28] ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
(scndry_vect_out,
gpio_io_i,
s_axi_aclk);
output [3:0]scndry_vect_out;
input [3:0]gpio_io_i;
input s_axi_aclk;
wire [3:0]gpio_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire [3:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
(scndry_vect_out,
gpio2_io_i,
s_axi_aclk);
output [3:0]scndry_vect_out;
input [3:0]gpio2_io_i;
input s_axi_aclk;
wire [3:0]gpio2_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire [3:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "design_1_axi_gpio_0_0,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2016.4" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
gpio_io_i,
gpio2_io_i);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_I" *) input [3:0]gpio_io_i;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I" *) input [3:0]gpio2_io_i;
wire [3:0]gpio2_io_i;
wire [3:0]gpio_io_i;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ip2intc_irpt_UNCONNECTED;
wire [3:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [3:0]NLW_U0_gpio2_io_t_UNCONNECTED;
wire [3:0]NLW_U0_gpio_io_o_UNCONNECTED;
wire [3:0]NLW_U0_gpio_io_t_UNCONNECTED;
(* C_ALL_INPUTS = "1" *)
(* C_ALL_INPUTS_2 = "1" *)
(* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "0" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *)
(* C_GPIO2_WIDTH = "4" *)
(* C_GPIO_WIDTH = "4" *)
(* C_INTERRUPT_PRESENT = "0" *)
(* C_IS_DUAL = "1" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio U0
(.gpio2_io_i(gpio2_io_i),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[3:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[3:0]),
.gpio_io_i(gpio_io_i),
.gpio_io_o(NLW_U0_gpio_io_o_UNCONNECTED[3:0]),
.gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[3:0]),
.ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
(bus2ip_rnw_i_reg_0,
\Dual.gpio2_OE_reg[0] ,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
s_axi_wready,
Read_Reg2_In,
E,
\Dual.gpio2_Data_Out_reg[0] ,
D,
Read_Reg_In,
\Dual.gpio_OE_reg[0] ,
\Dual.gpio_Data_Out_reg[0] ,
Read_Reg_Rst,
s_axi_rdata,
s_axi_aclk,
s_axi_arvalid,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_bready,
s_axi_rready,
s_axi_awaddr,
s_axi_araddr,
s_axi_awvalid,
s_axi_wvalid,
gpio2_io_t,
Q,
GPIO2_DBus_i,
GPIO_DBus_i,
gpio_io_t,
\Dual.gpio_Data_In_reg[0] ,
s_axi_aresetn,
gpio_xferAck_Reg,
GPIO_xferAck_i,
\ip2bus_data_i_D1_reg[28] );
output bus2ip_rnw_i_reg_0;
output \Dual.gpio2_OE_reg[0] ;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output s_axi_wready;
output [0:3]Read_Reg2_In;
output [0:0]E;
output [0:0]\Dual.gpio2_Data_Out_reg[0] ;
output [3:0]D;
output [0:3]Read_Reg_In;
output [0:0]\Dual.gpio_OE_reg[0] ;
output [0:0]\Dual.gpio_Data_Out_reg[0] ;
output Read_Reg_Rst;
output [3:0]s_axi_rdata;
input s_axi_aclk;
input s_axi_arvalid;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input s_axi_bready;
input s_axi_rready;
input [2:0]s_axi_awaddr;
input [2:0]s_axi_araddr;
input s_axi_awvalid;
input s_axi_wvalid;
input [3:0]gpio2_io_t;
input [3:0]Q;
input [3:0]GPIO2_DBus_i;
input [3:0]GPIO_DBus_i;
input [3:0]gpio_io_t;
input [3:0]\Dual.gpio_Data_In_reg[0] ;
input s_axi_aresetn;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [3:0]\ip2bus_data_i_D1_reg[28] ;
wire [3:0]D;
wire [0:0]\Dual.gpio2_Data_Out_reg[0] ;
wire \Dual.gpio2_OE_reg[0] ;
wire [3:0]\Dual.gpio_Data_In_reg[0] ;
wire [0:0]\Dual.gpio_Data_Out_reg[0] ;
wire [0:0]\Dual.gpio_OE_reg[0] ;
wire [0:0]E;
wire [3:0]GPIO2_DBus_i;
wire [3:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire [3:0]Q;
wire [0:3]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire [0:6]bus2ip_addr;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_1_n_0 ;
wire bus2ip_rnw_i06_out;
wire bus2ip_rnw_i_reg_0;
wire clear;
wire [3:0]gpio2_io_t;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [3:0]\ip2bus_data_i_D1_reg[28] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire [1:0]p_0_out;
wire p_1_in;
wire [3:0]plusOp;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [3:0]s_axi_rdata;
wire s_axi_rdata_i;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire s_axi_wready;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire \state[1]_i_2_n_0 ;
wire \state[1]_i_3_n_0 ;
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[1]),
.I1(state[0]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
(.D(D),
.\Dual.gpio2_Data_In_reg[0] (Q),
.\Dual.gpio2_Data_Out_reg[0] (\Dual.gpio2_Data_Out_reg[0] ),
.\Dual.gpio_Data_In_reg[0] (\Dual.gpio_Data_In_reg[0] ),
.\Dual.gpio_Data_Out_reg[0] (\Dual.gpio_Data_Out_reg[0] ),
.\Dual.gpio_OE_reg[0] (\Dual.gpio_OE_reg[0] ),
.E(E),
.GPIO2_DBus_i(GPIO2_DBus_i),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.Read_Reg2_In(Read_Reg2_In),
.Read_Reg_In(Read_Reg_In),
.Read_Reg_Rst(Read_Reg_Rst),
.\bus2ip_addr_i_reg[8] ({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}),
.bus2ip_rnw_i_reg(\Dual.gpio2_OE_reg[0] ),
.gpio2_io_t(gpio2_io_t),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.rst_reg(bus2ip_rnw_i_reg_0),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_wready(s_axi_wready),
.start2(start2));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_awaddr[0]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[0]),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_awaddr[1]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[1]),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_awaddr[2]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[2]),
.O(\bus2ip_addr_i[8]_i_1_n_0 ));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(bus2ip_addr[6]),
.R(bus2ip_rnw_i_reg_0));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(bus2ip_addr[5]),
.R(bus2ip_rnw_i_reg_0));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(\bus2ip_addr_i[8]_i_1_n_0 ),
.Q(bus2ip_addr[0]),
.R(bus2ip_rnw_i_reg_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h02))
bus2ip_rnw_i_i_1
(.I0(s_axi_arvalid),
.I1(state[0]),
.I2(state[1]),
.O(bus2ip_rnw_i06_out));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(bus2ip_rnw_i06_out),
.Q(\Dual.gpio2_OE_reg[0] ),
.R(bus2ip_rnw_i_reg_0));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(\state[1]_i_2_n_0 ),
.I2(state[1]),
.I3(state[0]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(bus2ip_rnw_i_reg_0));
LUT6 #(
.INIT(64'h1000FFFF10000000))
is_write_i_1
(.I0(state[1]),
.I1(s_axi_arvalid),
.I2(s_axi_wvalid),
.I3(s_axi_awvalid),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.I4(state[1]),
.I5(state[0]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(bus2ip_rnw_i_reg_0));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(s_axi_aresetn),
.O(p_1_in));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_1_in),
.Q(bus2ip_rnw_i_reg_0),
.R(1'b0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(bus2ip_rnw_i_reg_0));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[3]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(s_axi_rdata_i));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[28] [0]),
.Q(s_axi_rdata[0]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[28] [1]),
.Q(s_axi_rdata[1]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[28] [2]),
.Q(s_axi_rdata[2]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[28] [3]),
.Q(s_axi_rdata[3]),
.R(bus2ip_rnw_i_reg_0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(bus2ip_rnw_i_reg_0));
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(state[1]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(bus2ip_rnw_i_reg_0));
LUT5 #(
.INIT(32'h0FFFAACC))
\state[0]_i_1
(.I0(s_axi_wready),
.I1(s_axi_arvalid),
.I2(\state[1]_i_2_n_0 ),
.I3(state[1]),
.I4(state[0]),
.O(p_0_out[0]));
LUT6 #(
.INIT(64'h2E2E2E2ECCCCFFCC))
\state[1]_i_1
(.I0(s_axi_arready),
.I1(state[1]),
.I2(\state[1]_i_2_n_0 ),
.I3(\state[1]_i_3_n_0 ),
.I4(s_axi_arvalid),
.I5(state[0]),
.O(p_0_out[1]));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(\state[1]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\state[1]_i_3
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out[0]),
.Q(state[0]),
.R(bus2ip_rnw_i_reg_0));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out[1]),
.Q(state[1]),
.R(bus2ip_rnw_i_reg_0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module CARRY4(
output [3:0] CO,
output [3:0] O,
input CI,
input CYINIT,
input [3:0] DI, S
);
parameter _TECHMAP_CONSTMSK_CI_ = 1;
parameter _TECHMAP_CONSTVAL_CI_ = 1'b0;
parameter _TECHMAP_CONSTMSK_CYINIT_ = 1;
parameter _TECHMAP_CONSTVAL_CYINIT_ = 1'b0;
localparam [0:0] IS_CI_ZERO = (
_TECHMAP_CONSTMSK_CI_ == 1 && _TECHMAP_CONSTVAL_CI_ == 0 &&
_TECHMAP_CONSTMSK_CYINIT_ == 1 && _TECHMAP_CONSTVAL_CYINIT_ == 0);
localparam [0:0] IS_CI_ONE = (
_TECHMAP_CONSTMSK_CI_ == 1 && _TECHMAP_CONSTVAL_CI_ == 0 &&
_TECHMAP_CONSTMSK_CYINIT_ == 1 && _TECHMAP_CONSTVAL_CYINIT_ == 1);
localparam [0:0] IS_CYINIT_FABRIC = _TECHMAP_CONSTMSK_CYINIT_ == 0;
localparam [0:0] IS_CI_DISCONNECTED = _TECHMAP_CONSTMSK_CI_ == 1 &&
_TECHMAP_CONSTVAL_CI_ != 1;
localparam [0:0] IS_CYINIT_DISCONNECTED = _TECHMAP_CONSTMSK_CYINIT_ == 1 &&
_TECHMAP_CONSTVAL_CYINIT_ != 1;
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
wire [3:0] O;
wire [3:0] CO;
wire [3:0] CO_output;
// Put in a placeholder object CARRY_CO_DIRECT.
//
// It will be used for 3 purposes:
// - Remain as CARRY_CO_DIRECT when OUT only connects to CARRY_COUT_PLUG
// - Remain as CARRY_CO_DIRECT when CO is used, but O is not used.
// - Change into CARRY_CO_LUT when O and CO are required (e.g. compute CO
// from O ^ S).
genvar i;
generate for (i = 0; i < 3; i = i + 1) begin:co_outputs
CARRY_CO_DIRECT #(.TOP_OF_CHAIN(0)) co_output(
.CO(CO_output[i]),
.O(O[i+1]),
.S(S[i+1]),
.OUT(CO[i])
);
end endgenerate
CARRY_CO_DIRECT #(.TOP_OF_CHAIN(1)) co_output(
.CO(CO_output[3]),
.O(O[3]),
.S(S[3]),
.DI(DI[3]),
.OUT(CO[3])
);
if(IS_CYINIT_FABRIC) begin
CARRY4_VPR #(
.CYINIT_AX(1'b1),
.CYINIT_C0(1'b0),
.CYINIT_C1(1'b0)
) _TECHMAP_REPLACE_ (
.CO0(CO_output[0]),
.CO1(CO_output[1]),
.CO2(CO_output[2]),
.CO3(CO_output[3]),
.CYINIT(CYINIT),
.O0(O[0]),
.O1(O[1]),
.O2(O[2]),
.O3(O[3]),
.DI0(DI[0]),
.DI1(DI[1]),
.DI2(DI[2]),
.DI3(DI[3]),
.S0(S[0]),
.S1(S[1]),
.S2(S[2]),
.S3(S[3])
);
end else if(IS_CI_ZERO || IS_CI_ONE) begin
CARRY4_VPR #(
.CYINIT_AX(1'b0),
.CYINIT_C0(IS_CI_ZERO),
.CYINIT_C1(IS_CI_ONE)
) _TECHMAP_REPLACE_ (
.CO0(CO_output[0]),
.CO1(CO_output[1]),
.CO2(CO_output[2]),
.CO3(CO_output[3]),
.O0(O[0]),
.O1(O[1]),
.O2(O[2]),
.O3(O[3]),
.DI0(DI[0]),
.DI1(DI[1]),
.DI2(DI[2]),
.DI3(DI[3]),
.S0(S[0]),
.S1(S[1]),
.S2(S[2]),
.S3(S[3])
);
end else begin
wire cin_from_below;
CARRY_COUT_PLUG cin_plug(
.CIN(CI),
.COUT(cin_from_below)
);
CARRY4_VPR #(
.CYINIT_AX(1'b0),
.CYINIT_C0(1'b0),
.CYINIT_C1(1'b0)
) _TECHMAP_REPLACE_ (
.CO0(CO_output[0]),
.CO1(CO_output[1]),
.CO2(CO_output[2]),
.CO3(CO_output[3]),
.O0(O[0]),
.O1(O[1]),
.O2(O[2]),
.O3(O[3]),
.DI0(DI[0]),
.DI1(DI[1]),
.DI2(DI[2]),
.DI3(DI[3]),
.S0(S[0]),
.S1(S[1]),
.S2(S[2]),
.S3(S[3]),
.CIN(cin_from_below)
);
end
endmodule
|
`timescale 1ns / 1ps
`include "z80_opcode_definitions.v"
////////////////////////////////////////////////////////////////////////////////////
//
// pGB, yet another FPGA fully functional and super fun GB classic clone!
// Copyright (C) 2015-2016 Diego Valverde ([email protected])
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
//
////////////////////////////////////////////////////////////////////////////////////
module dzcpu_ucode_lut
(
input wire[7:0] iMop,
output reg [8:0] oUopFlowIdx
);
always @ ( iMop )
begin
case ( iMop )
`LDSPnn: oUopFlowIdx = 9'd1;
`LDHLnn: oUopFlowIdx = 9'd5;
`LDHLDA: oUopFlowIdx = 9'd9;
`MAPcb: oUopFlowIdx = 9'd13;
`JRNZn: oUopFlowIdx = 9'd17;
`LDrn_c: oUopFlowIdx = 9'd23;
`LDrn_a: oUopFlowIdx = 9'd26;
`LDIOCA: oUopFlowIdx = 9'd29;
`INCr_c: oUopFlowIdx = 9'd32;
`LDHLmr_a: oUopFlowIdx = 9'd33;
`LDIOnA: oUopFlowIdx = 9'd36;
`LDDEnn: oUopFlowIdx = 9'd43;
`LDADEm: oUopFlowIdx = 9'd94;
`CALLnn: oUopFlowIdx = 9'd49;
`LDrn_b: oUopFlowIdx = 9'd60;
`PUSHBC: oUopFlowIdx = 9'd63;
`RLA: oUopFlowIdx = 9'd70; //TODO: Make sure this is OK!
`POPBC: oUopFlowIdx = 9'd71;
`DECr_b: oUopFlowIdx = 9'd300;
`LDHLIA: oUopFlowIdx = 9'd78;
`INCHL: oUopFlowIdx = 9'd82;
`RET: oUopFlowIdx = 9'd252;//8'd83;
`INCDE: oUopFlowIdx = 9'd89;
`CPn: oUopFlowIdx = 9'd90;
`LDmmA: oUopFlowIdx = 9'd98;
`DECr_a: oUopFlowIdx = 9'd47;
`DECr_c: oUopFlowIdx = 9'd48;
`JRZn: oUopFlowIdx = 9'd106;
`LDrn_l: oUopFlowIdx = 9'd112;
`JRn: oUopFlowIdx = 9'd115;
`INCr_b: oUopFlowIdx = 9'd161;
`LDrn_e: oUopFlowIdx = 9'd121;
`LDAIOn: oUopFlowIdx = 9'd124;
`INCr_h: oUopFlowIdx = 9'd312;
`SUBr_b: oUopFlowIdx = 9'd132;
`DECr_d: oUopFlowIdx = 9'd135;
`LDrn_d: oUopFlowIdx = 9'd136;
`JPnn: oUopFlowIdx = 9'd139;
`LDrn_h: oUopFlowIdx = 9'd146;
`LDAHLI: oUopFlowIdx = 9'd149;
`LDHLmn: oUopFlowIdx = 9'd154;
`NOP: oUopFlowIdx = 9'd162;
`DI: oUopFlowIdx = 9'd163;
`INCr_d: oUopFlowIdx = 9'd164;
`INCr_e: oUopFlowIdx = 9'd250; //8'd165;
`DECr_e: oUopFlowIdx = 9'd166;
`DECDE: oUopFlowIdx = 9'd168;
`DECBC: oUopFlowIdx = 9'd169; //OK
`DECr_h: oUopFlowIdx = 9'd170;
`DECHL: oUopFlowIdx = 9'd172;
`INCr_a: oUopFlowIdx = 9'd302;
`INCSP: oUopFlowIdx = 9'd304;
`DECSP: oUopFlowIdx = 9'd306;
`INCr_l: oUopFlowIdx = 9'd308;
`DECr_l: oUopFlowIdx = 9'd310;
`ADDr_a: oUopFlowIdx = 9'd175;
`ADDr_b: oUopFlowIdx = 9'd178;
`SUBr_c: oUopFlowIdx = 9'd181;
`ADDr_c: oUopFlowIdx = 9'd184;
`ADDr_d: oUopFlowIdx = 9'd187;
`ADDr_e: oUopFlowIdx = 9'd190;
`ADDr_h: oUopFlowIdx = 9'd193;
`ADDr_l: oUopFlowIdx = 9'd196;
`SUBr_d: oUopFlowIdx = 9'd199;
`SUBr_e: oUopFlowIdx = 9'd202;
`SUBr_h: oUopFlowIdx = 9'd205;
`SUBr_l: oUopFlowIdx = 9'd208;
`SUBr_a: oUopFlowIdx = 9'd211;
`PUSHDE: oUopFlowIdx = 9'd214;
`PUSHHL: oUopFlowIdx = 9'd220;
`POPDE: oUopFlowIdx = 9'd226;
`POPHL: oUopFlowIdx = 9'd232;
`LDHLmr_b: oUopFlowIdx = 9'd238;
`LDHLmr_c: oUopFlowIdx = 9'd241;
`LDHLmr_d: oUopFlowIdx = 9'd244;
`LDDEmA: oUopFlowIdx = 9'd247;
`PUSHAF: oUopFlowIdx = 9'd261;
`POPAF: oUopFlowIdx = 9'd267;
`LDBCnn: oUopFlowIdx = 9'd273;
`INCBC: oUopFlowIdx = 9'd83;
`LDAmm: oUopFlowIdx = 9'd280;
`ANDn: oUopFlowIdx = 9'd85;
`CALLNZnn: oUopFlowIdx = 9'd289;
`ADDn: oUopFlowIdx = 9'd314;
`SUBn: oUopFlowIdx = 9'd319;
`CPr_c: oUopFlowIdx = 9'd324;
`LDrHLm_b: oUopFlowIdx = 9'd327;
`LDrHLm_c: oUopFlowIdx = 9'd331;
`LDrHLm_d: oUopFlowIdx = 9'd335;
`XORHL: oUopFlowIdx = 9'd339;
`ADCn: oUopFlowIdx = 9'd345;
`ADDHLDE: oUopFlowIdx = 9'd351;
`JRNCn: oUopFlowIdx = 9'd414;
`XORn: oUopFlowIdx = 9'd359;
`RRA: oUopFlowIdx = 9'd363;
`RETNC: oUopFlowIdx = 9'd365;
`RETZ: oUopFlowIdx = 9'd377;
`ORHL: oUopFlowIdx = 9'd387;
`DECHLm: oUopFlowIdx = 9'd391;
`LDrHLm_l: oUopFlowIdx = 9'd397;
`RETNZ: oUopFlowIdx = 9'd401;
`ADDHLHL: oUopFlowIdx = 9'd411;
`ANDHL: oUopFlowIdx = 9'd420;
`LDHLmr_e: oUopFlowIdx = 9'd424;
`LDHLmr_h: oUopFlowIdx = 9'd427;
`LDHLmr_l: oUopFlowIdx = 9'd430;
`LDABCm: oUopFlowIdx = 9'd433;
`LDrHLm_a: oUopFlowIdx = 9'd437;
`LDrHLm_e: oUopFlowIdx = 9'd441;
`LDrHLm_h: oUopFlowIdx = 9'd445;
`ADCr_a: oUopFlowIdx = 9'd449;
`ADCr_b: oUopFlowIdx = 9'd453;
`ADCr_c: oUopFlowIdx = 9'd457;
`ADCr_d: oUopFlowIdx = 9'd461;
`ADCr_e: oUopFlowIdx = 9'd465;
`ADCr_h: oUopFlowIdx = 9'd469;
`ADCr_l: oUopFlowIdx = 9'd473;
default:
oUopFlowIdx = 9'd278;
endcase
end
endmodule
////////////////////////////////////////////////////////
//
// MAP CB -- EXTENDED OPERATIONS
//
////////////////////////////////////////////////////////
module dzcpu_ucode_cblut
(
input wire[7:0] iMop,
output reg [8:0] oUopFlowIdx
);
always @ ( iMop )
begin
case ( iMop )
8'h7C: oUopFlowIdx = 9'd16; //BIT7
8'h11: oUopFlowIdx = 9'd69; //RLr_b
8'h38: oUopFlowIdx = 9'd477; //SRL_b
default:
oUopFlowIdx = 9'd0;
endcase
end
endmodule
module dzcpu_ucode_rom
(
input wire[8:0] iAddr,
output reg [13:0] oUop
);
always @ ( iAddr )
begin
case ( iAddr )
//Regular 1 Byte mOp
0: oUop = { `inc_eof_fu, `z801bop , `a };
//LDSPnn
1: oUop = { `inc, `sma, `pc };
2: oUop = { `inc, `nop, `null };
3: oUop = { `op , `srm, `spl };
4: oUop = { `inc_eof , `srm, `sph };
//LDHLnn
5: oUop = { `inc, `sma, `pc };
6: oUop = { `inc, `nop, `null };
7: oUop = { `op , `srm, `l };
8: oUop = { `inc_eof , `srm, `h };
//LDHLDA
9: oUop = { `op, `sma, `hl };
10: oUop = { `op, `smw, `a };
11: oUop = { `inc, `sma, `pc };
12: oUop = { `eof, `dec16, `hl };
//MAPcb 0xCB
13: oUop = { `inc, `sma, `pc };
14: oUop = { `op, `nop, `null };
15: oUop = { `inc, `jcb, `null };
//BIT
16: oUop = { `eof_fu, `bit, `null };
//JRNZ
17: oUop = { `inc, `sma, `pc };
18: oUop = { `op, `nop, `null };
19: oUop = { `inc_eof_z, `srm, `x8 }; //If z return else x8 = MEM[pc]
20: oUop = { `op, `sx16r, `pc }; //x16 = pc
21: oUop = { `op,`addx16, `x8 }; //x16 = x16 + sign_extend{8'b0,x8}
22: oUop = { `eof, `spc, `x16 }; //pc = x16
//LDrn_c
23: oUop = {`inc, `sma, `pc};
24: oUop = { `inc, `nop, `null };
25: oUop = {`eof, `srm, `c };
//LDrn_a
26: oUop = {`inc, `sma, `pc};
27: oUop = { `inc, `nop, `null };
28: oUop = {`eof, `srm, `a };
//LDIOCA
29: oUop = {`op, `sma, `io_c };
30: oUop = {`op, `smw, `a };
31: oUop = {`inc_eof, `sma, `pc };
//INCr_c
32: oUop = {`inc_eof_fu, `inc16, `c };
//LDHLmr_a
33: oUop = {`inc, `sma, `hl };
34: oUop = {`op, `smw, `a };
35: oUop = {`eof, `sma, `pc };
//LDIOnA
36: oUop = { `inc, `sma, `pc };
37: oUop = { `op ,`sx8r, `c };
38: oUop = { `op ,`srm, `c };
39: oUop = { `op, `sma, `io_c };
40: oUop = { `op, `smw, `a };
41: oUop = { `inc, `srx8, `c };
42: oUop = { `eof, `sma, `pc };
//LDDEnn
43: oUop = { `inc, `sma, `pc };
44: oUop = { `inc, `nop, `null };
45: oUop = { `op , `srm, `e };
46: oUop = { `inc_eof , `srm, `d };
//DECr_a
47: oUop = { `inc_eof_fu, `dec16, `a };
//DECr_c
48: oUop = { `inc_eof_fu, `dec16, `c };
//CALLnn
49: oUop = { `inc, `dec16, `sp };
50: oUop = { `inc, `sx16r, `hl };
51: oUop = { `op , `srm, `l }; //l = MEM[pc] = literal
52: oUop = { `inc, `srm, `h }; //l = MEM[pc] = literal
53: oUop = { `op, `sma, `sp };
54: oUop = { `op, `smw, `pch }; //MEM[sp] = pc[7:0]
55: oUop = { `op, `dec16, `sp };
56: oUop = { `op , `smw, `pc }; //MEM[sp+1] = pc[15:8]
57: oUop = { `op , `spc, `hl };
58: oUop = { `op, `srx16, `hl };
59: oUop = { `eof ,`sma, `pc };
//LDrn_b
60: oUop = { `inc, `sma, `pc };
61: oUop = { `inc, `nop, `null };
62: oUop = { `eof , `srm, `b };
//PUSHBC
63: oUop = { `op, `dec16, `sp };
64: oUop = { `op, `sma, `sp };
65: oUop = { `op ,`smw, `b };
66: oUop = { `op, `dec16, `sp };
67: oUop = { `op ,`smw, `c };
68: oUop = { `inc_eof ,`sma,`pc };
//RLr_r
69: oUop = { `eof_fu, `shl, `null };
//RLA
70: oUop = { `inc_eof_fu, `shl, `null };
//POPBC
71: oUop = { `op, `sma, `sp };
72: oUop = { `op ,`inc16, `sp };
73: oUop = { `op ,`srm, `c };
74: oUop = { `op ,`srm, `b };
75: oUop = { `inc ,`inc16, `sp };
76: oUop = { `eof, `sma, `pc };
//UNUSED
77: oUop = { `inc_eof_fu, `dec16, `b };
//LDHLIA
78: oUop = {`op, `sma, `hl };
79: oUop = {`op, `smw, `a };
80: oUop = { `inc ,`inc16, `hl };
81: oUop = {`eof, `sma, `pc };
//INCHL
82: oUop = { `inc_eof ,`inc16, `hl };
//INCBC
83: oUop = { `inc_eof ,`inc16, `bc }; //flags might be wrong for 16bits
//UNUSED
84: oUop = { `inc_eof, `nop, `null };
//ANDn
85: oUop = { `inc, `sma, `pc };
86: oUop = { `op, `nop , `null };
87: oUop = { `update_flags ,`anda, `idata };
88: oUop = { `inc_eof ,`nop, `null };
//INCDE
89: oUop = { `inc_eof, `inc16, `de };
//CPn
90: oUop = { `inc, `sx16r, `a };
91: oUop = { `op, `nop, `null };
92: oUop = { `op, `srm, `x8 };
93: oUop = { `inc_eof_fu, `subx16, `x8 }; //x16 = x16 - x8 -> a = a - lit
//LDADEm
94: oUop = {`inc, `sma, `de };
95: oUop = {`op, `nop, `null };
96: oUop = {`op, `srm, `a };
97: oUop = {`eof, `sma, `pc };
//LDmmA
98: oUop = {`inc, `sx16r, `hl };
99: oUop = {`inc, `sma, `pc };
100: oUop = {`op, `srm, `l };
101: oUop = {`op, `srm, `h };
102: oUop = {`op, `sma, `hl };
103: oUop = {`op, `smw, `a };
104: oUop = {`inc, `sma, `pc };
105: oUop = {`eof, `srx16, `hl };
//JRZn
106: oUop = { `inc, `sma, `pc };
107: oUop = { `op, `nop, `null };
108: oUop = { `inc_eof_nz, `srm, `x8 }; //If not z return else x8 = MEM[pc]
109: oUop = { `op, `sx16r, `pc }; //x16 = pc
110: oUop = { `op,`addx16, `x8 }; //x16 = x16 + sign_extend{8'b0,x8}
111: oUop = { `eof, `spc, `x16 }; //pc = x16
//LDrn_l
112: oUop = {`inc, `sma, `pc };
113: oUop = { `inc, `nop, `null };
114: oUop = {`eof, `srm, `l };
//JRn
115: oUop = { `inc, `sma, `pc };
116: oUop = { `op, `nop, `null };
117: oUop = { `inc, `srm, `x8 };
118: oUop = { `op, `sx16r, `pc }; //x16 = pc
119: oUop = { `op,`addx16, `x8 }; //x16 = x16 + sign_extend{8'b0,x8}
120: oUop = { `eof, `spc, `x16 }; //pc = x16
//LDrn_e
121: oUop = {`inc, `sma, `pc };
122: oUop = { `inc, `nop, `null };
123: oUop = {`eof, `srm, `e };
//LDAIOn
124: oUop = { `inc, `sx8r, `c };
125: oUop = { `op, `nop, `null };
126: oUop = { `op, `srm, `c };
127: oUop = { `op, `sma, `io_c };
128: oUop = { `op, `srm, `a };
129: oUop = { `op, `srx8, `c };
130: oUop = { `inc_eof, `sma, `pc };
//UNUSED
131: oUop = { `op, `nop, `null };
//SUBr_b
132: oUop = { `op, `sx16r, `a };
133: oUop = { `update_flags, `subx16, `b };
134: oUop = { `inc_eof, `srx16, `a };
//DECr_d
135: oUop = { `inc_eof_fu, `dec16, `d };
//LDrn_d
136: oUop = {`inc, `sma, `pc };
137: oUop = { `inc, `nop, `null };
138: oUop = {`eof, `srm, `d };
//JPnn
139: oUop = {`op, `sx16r, `hl };
140: oUop = {`inc, `sma, `pc };
141: oUop = {`inc, `nop, `null };
142: oUop = {`inc, `srm, `l };
143: oUop = {`op, `srm, `h };
144: oUop = {`op, `spc, `hl };
145: oUop = {`eof, `srx16, `hl };
//LDrn_h
146: oUop = {`inc, `sma, `pc };
147: oUop = { `inc, `nop, `null };
148: oUop = {`eof, `srm, `h };
//LDAHLI
149: oUop = {`op, `sma, `hl };
150: oUop = {`op, `nop, `null };
151: oUop = {`op, `srm, `a };
152: oUop = { `inc ,`inc16, `hl };
153: oUop = {`eof, `sma, `pc };
//LDHLmn
154: oUop = {`inc, `sma, `pc };
155: oUop = {`op, `nop, `null };
156: oUop = {`op, `srm, `x8 };
157: oUop = {`op, `sma, `hl };
158: oUop = {`op, `nop, `null };
159: oUop = {`op, `smw, `x8 };
160: oUop = {`inc_eof, `sma, `pc };
//INCR_b
161: oUop = {`inc_eof_fu, `inc16, `b };
//NOP
162: oUop = { `inc_eof, `nop, `null };
//DI
163: oUop = { `inc_eof, `ceti, `null }; //Disable Interruption
//INCr_d
164: oUop = { `update_flags, `inc16, `d };
165: oUop = { `inc_eof, `nop, `null };
//DECr_e
166: oUop = { `update_flags, `dec16, `e };
167: oUop = { `inc_eof, `nop, `null };
//DECDE
168: oUop = { `inc_eof, `dec16, `de };
//DECBC
169: oUop = { `inc_eof, `dec16, `bc};
//DECr_h
170: oUop = { `update_flags, `dec16, `h };
171: oUop = { `inc_eof, `nop, `null };
//DECHL
172: oUop = { `inc_eof, `dec16, `hl };
//UNUSED
173: oUop = { `inc_eof, `nop, `null };
//UNUSED
174: oUop = { `inc_eof, `nop, `null };
//ADDr_a
175: oUop = { `op, `sx16r, `a };
176: oUop = { `update_flags, `addx16u, `a };
177: oUop = { `inc_eof, `srx16, `a };
//ADDr_b
178: oUop = { `op, `sx16r, `a };
179: oUop = { `update_flags, `addx16u, `b };
180: oUop = { `inc_eof, `srx16, `a };
//SUBr_c
181: oUop = { `op, `sx16r, `a };
182: oUop = { `update_flags, `subx16, `c };
183: oUop = { `inc_eof, `srx16, `a };
//ADDr_c
184: oUop = { `op, `sx16r, `a };
185: oUop = { `update_flags, `addx16u, `c };
186: oUop = { `inc_eof, `srx16, `a };
//ADDr_d
187: oUop = { `op, `sx16r, `a };
188: oUop = { `update_flags, `addx16u, `d };
189: oUop = { `inc_eof, `srx16, `a };
//ADDr_e
190: oUop = { `op, `sx16r, `a };
191: oUop = { `update_flags, `addx16u, `e };
192: oUop = { `inc_eof, `srx16, `a };
//ADDr_h
193: oUop = { `op, `sx16r, `a };
194: oUop = { `update_flags, `addx16u, `h };
195: oUop = { `inc_eof, `srx16, `a };
//ADDr_l
196: oUop = { `op, `sx16r, `a };
197: oUop = { `update_flags, `addx16u, `l };
198: oUop = { `inc_eof, `srx16, `a };
//SUBr_d
199: oUop = { `op, `sx16r, `a };
200: oUop = { `update_flags, `subx16, `d };
201: oUop = { `inc_eof, `srx16, `a };
//SUBr_e
202: oUop = { `op, `sx16r, `a };
203: oUop = { `update_flags, `subx16, `e };
204: oUop = { `inc_eof, `srx16, `a };
//SUBr_h
205: oUop = { `op, `sx16r, `a };
206: oUop = { `update_flags, `subx16, `h };
207: oUop = { `inc_eof, `srx16, `a };
//SUBr_l
208: oUop = { `op, `sx16r, `a };
209: oUop = { `update_flags, `subx16, `l };
210: oUop = { `inc_eof, `srx16, `a };
//SUB_a
211: oUop = { `op, `sx16r, `a };
212: oUop = { `update_flags, `subx16, `a };
213: oUop = { `inc_eof, `srx16, `a };
//PUSHDE
214: oUop = { `op, `dec16, `sp };
215: oUop = { `op, `sma, `sp };
216: oUop = { `op ,`smw, `d };
217: oUop = { `op, `dec16, `sp };
218: oUop = { `op ,`smw, `e };
219: oUop = { `inc_eof ,`sma,`pc };
//PUSHHL
220: oUop = { `op, `dec16, `sp };
221: oUop = { `op, `sma, `sp };
222: oUop = { `op ,`smw, `h };
223: oUop = { `op, `dec16, `sp };
224: oUop = { `op ,`smw, `l };
225: oUop = { `inc_eof ,`sma,`pc };
//POPDE
226: oUop = { `op, `sma, `sp };
227: oUop = { `op ,`inc16, `sp };
228: oUop = { `op ,`srm, `e };
229: oUop = { `op ,`srm, `d };
230: oUop = { `inc ,`inc16, `sp };
231: oUop = { `eof, `sma, `pc };
//POPHL
232: oUop = { `op, `sma, `sp };
233: oUop = { `op ,`inc16, `sp };
234: oUop = { `op ,`srm, `l };
235: oUop = { `op ,`srm, `h };
236: oUop = { `inc ,`inc16, `sp };
237: oUop = { `eof, `sma, `pc };
//LDHLmr_b
238: oUop = {`inc, `sma, `hl };
239: oUop = {`op, `smw, `b };
240: oUop = {`eof, `sma, `pc };
//LDHLmr_c
241: oUop = {`inc, `sma, `hl };
242: oUop = {`op, `smw, `c };
243: oUop = {`eof, `sma, `pc };
//LDHLmr_d
244: oUop = {`inc, `sma, `hl };
245: oUop = {`op, `smw, `d };
246: oUop = {`eof, `sma, `pc };
//LDDEmA
247: oUop = {`op, `sma, `de };
248: oUop = {`op, `smw, `a };
249: oUop = {`inc_eof, `sma, `pc };
//INCr_e
250: oUop = { `update_flags, `inc16, `e };
251: oUop = { `inc_eof, `nop, `null };
//RET
252: oUop = {`op ,`sma, `sp };
253: oUop = {`op, `sx16r, `hl };
254: oUop = {`op, `inc16, `sp };
255: oUop = {`op, `srm, `l };
256: oUop = {`op, `srm, `h };
257: oUop = {`op, `spc, `hl };
258: oUop = {`op, `srx16, `hl };
259: oUop = {`op, `inc16, `sp };
260: oUop = { `eof ,`sma, `pc };
//PUSHAF
261: oUop = { `op, `dec16, `sp };
262: oUop = { `op, `sma, `sp };
263: oUop = { `op ,`smw, `a };
264: oUop = { `op, `dec16, `sp };
265: oUop = { `op ,`smw, `f };
266: oUop = { `inc_eof ,`sma,`pc };
//POPAF
267: oUop = { `op, `sma, `sp };
268: oUop = { `op ,`inc16, `sp };
269: oUop = { `op ,`srm, `f };
270: oUop = { `op ,`srm, `a };
271: oUop = { `inc ,`inc16, `sp };
272: oUop = { `eof, `sma, `pc };
//LDBCnn
273: oUop = { `inc, `sma, `pc };
274: oUop = { `inc, `nop, `null };
275: oUop = { `op , `srm, `c };
276: oUop = { `inc_eof , `srm, `b };
//INCBC
277: oUop = { `inc_eof ,`inc16, `bc };
//Z80 1 Byte op
278: oUop = { `update_flags, `z801bop , `a };
279: oUop = { `inc_eof, `nop , `null };
//LDAmm
280: oUop = { `inc, `sx16r, `hl };
281: oUop = { `inc, `sma , `pc };
282: oUop = { `op ,`srm, `l };
283: oUop = { `op ,`srm, `h };
284: oUop = { `op, `sma , `hl };
285: oUop = { `op, `nop , `null }; //remember to wait 1cc after sma
286: oUop = { `op ,`srm, `a };
287: oUop = { `op, `srx16, `hl };
288: oUop = { `inc_eof, `sma , `pc };
//CALLNZnn
289: oUop = { `inc, `nop, `null };
290: oUop = { `inc, `nop, `null };
291: oUop = { `op , `srm, `y8 }; //l = MEM[pc] = literal
292: oUop = { `inc_eof_z, `srm, `x8 }; //l = MEM[pc] = literal
293: oUop = { `op, `sma, `sp };
294: oUop = { `op, `smw, `pch }; //MEM[sp] = pc[7:0]
295: oUop = { `op, `dec16, `sp };
296: oUop = { `op , `smw, `pc }; //MEM[sp+1] = pc[15:8]
297: oUop = { `op, `dec16, `sp };
298: oUop = { `op , `spc, `xy16 };
299: oUop = { `eof ,`sma, `pc };
//DECr_b
300: oUop = { `update_flags, `dec16, `b };
301: oUop = { `inc_eof, `nop, `null};
//INCr_a
302: oUop = { `update_flags, `inc16, `a };
303: oUop = { `inc_eof, `nop, `null};
//INCSP
304: oUop = { `op, `inc16, `sp }; //increment SP
305: oUop = { `inc_eof, `nop, `null};
//DECSP
306: oUop = { `inc_eof, `dec16, `sp };
//UNUSED
307: oUop = { `inc_eof, `nop, `null};
//INCr_l
308: oUop = { `update_flags, `inc16, `l };
309: oUop = { `inc_eof, `nop, `null};
//DECr_l
310: oUop = { `update_flags, `dec16, `l };
311: oUop = { `inc_eof, `nop, `null};
//INCr_h
312: oUop = { `update_flags, `inc16, `h };
313: oUop = { `inc_eof, `nop, `null};
//ADDn
314: oUop = { `inc, `sma, `pc };
315: oUop = { `op, `nop, `null };
316: oUop = { `op, `srm, `x16 };
317: oUop = { `update_flags, `addx16u, `a };
318: oUop = { `inc_eof, `srx16, `a};
//SUBn
319: oUop = { `inc, `sma, `pc };
320: oUop = { `op, `nop, `null };
321: oUop = { `op, `srm, `x16 };
322: oUop = { `update_flags, `subx16, `a };
323: oUop = { `inc_eof, `srx16, `a};
//CPr_c
324: oUop = { `op, `sx16r, `a };
325: oUop = { `update_flags, `subx16, `c };
326: oUop = { `inc_eof, `nop, `null};
//LDrHLm_b
327: oUop = { `op, `sma, `hl };
328: oUop = { `op, `nop, `null };
329: oUop = { `op, `srm, `b };
330: oUop = { `inc_eof, `sma, `pc};
//LDrHLm_c
331: oUop = { `op, `sma, `hl };
332: oUop = { `op, `nop, `null };
333: oUop = { `op, `srm, `c };
334: oUop = { `inc_eof, `sma, `pc};
//LDrHLm_d
335: oUop = { `op, `sma, `hl };
336: oUop = { `op, `nop, `null };
337: oUop = { `op, `srm, `d };
338: oUop = { `inc_eof, `sma, `pc};
//XORHL
339: oUop = { `op, `sma, `hl };
340: oUop = { `op, `nop, `null };
341: oUop = { `op, `srm, `x16 };
342: oUop = { `update_flags, `xorx16, `a};
343: oUop = { `op, `srx16, `a};
344: oUop = { `inc_eof, `sma, `pc};
//ADCn
345: oUop = { `inc, `sma, `pc };
346: oUop = { `op, `nop, `null };
347: oUop = { `op, `srm, `x16 };
348: oUop = { `op, `addx16, `a };
349: oUop = { `update_flags, `addx16, `carry };
350: oUop = { `inc_eof, `sma, `pc};
//ADDHLDE
351: oUop = { `inc, `sx16r, `hl };
352: oUop = { `update_flags, `addx16, `de };
353: oUop = { `eof, `srx16, `hl };
//UNUSED
354: oUop = { `inc, `sma, `pc };
355: oUop = { `op, `xorx16, `x16 };
356: oUop = { `update_flags, `addx16, `carry };
357: oUop = { `inc_eof_nz, `srm, `x16 };
358: oUop = { `eof, `addx16, `x16 };
//XORn
359: oUop = { `inc, `sma, `pc };
360: oUop = { `op, `sx16r , `a };
361: oUop = { `update_flags ,`xorx16, `idata };
362: oUop = { `inc_eof ,`srx16, `a };
//RRA
363: oUop = { `update_flags, `rrot, `null };
364: oUop = { `inc_eof, `nop, `null };
//RETNC
365: oUop = { `op, `xorx16, `x16 };
366: oUop = { `update_flags, `addx16, `carry };
367: oUop = { `inc_eof_nz, `srm, `x16 };
368: oUop = {`op ,`sma, `sp };
369: oUop = {`op, `sx16r, `hl };
370: oUop = {`op, `inc16, `sp };
371: oUop = {`op, `srm, `l };
372: oUop = {`op, `srm, `h };
373: oUop = {`op, `spc, `hl };
374: oUop = {`op, `srx16, `hl };
375: oUop = {`op, `inc16, `sp };
376: oUop = { `eof ,`sma, `pc };
//RETZ
377: oUop = { `inc_eof_z, `nop, `null };
378: oUop = {`op ,`sma, `sp };
379: oUop = {`op, `sx16r, `hl };
380: oUop = {`op, `inc16, `sp };
381: oUop = {`op, `srm, `l };
382: oUop = {`op, `srm, `h };
383: oUop = {`op, `spc, `hl };
384: oUop = {`op, `srx16, `hl };
385: oUop = {`op, `inc16, `sp };
386: oUop = { `eof ,`sma, `pc };
//ORHL
387: oUop = {`op ,`sma, `hl };
388: oUop = {`op, `nop, `null };
389: oUop = {`update_flags, `xora, `idata };
390: oUop = { `inc_eof ,`sma, `pc };
//DECHLm
391: oUop = {`op ,`sma, `hl };
392: oUop = {`op, `nop, `null };
393: oUop = {`op, `srm, `x16 };
394: oUop = {`update_flags, `dec16, `x16 };
395: oUop = {`nop, `smw, `x16 };
396: oUop = {`inc_eof, `sma, `pc };
//LDrHLm_l
397: oUop = {`op ,`sma, `hl };
398: oUop = {`op, `nop, `null };
399: oUop = {`op, `srm, `l };
400: oUop = {`inc_eof, `sma, `pc };
//RETNZ
401: oUop = { `inc_eof_nz, `nop, `null };
402: oUop = {`op ,`sma, `sp };
403: oUop = {`op, `sx16r, `hl };
404: oUop = {`op, `inc16, `sp };
405: oUop = {`op, `srm, `l };
406: oUop = {`op, `srm, `h };
407: oUop = {`op, `spc, `hl };
408: oUop = {`op, `srx16, `hl };
409: oUop = {`op, `inc16, `sp };
410: oUop = { `eof ,`sma, `pc };
//ADDHLHL
411: oUop = {`op, `sx16r, `hl };
412: oUop = {`update_flags, `addx16r16, `x16 };
413: oUop = {`inc_eof, `srx16, `hl };
//JRNCn
414: oUop = { `inc, `sma, `pc };
415: oUop = { `op, `xorx16, `x16 };
416: oUop = { `update_flags, `addx16, `carry };
417: oUop = { `inc_eof_nz, `srm, `x16 };
418: oUop = { `nop, `addx16, `pc };
419: oUop = { `eof, `spc, `x16 };
//ANDHL
420: oUop = { `inc, `sma, `hl };
421: oUop = { `op, `nop , `null };
422: oUop = { `update_flags ,`anda, `idata };
423: oUop = { `inc_eof ,`nop, `null };
//LDHLmr_e
424: oUop = {`inc, `sma, `hl };
425: oUop = {`op, `smw, `e };
426: oUop = {`eof, `sma, `pc };
//LDHLmr_h
427: oUop = {`inc, `sma, `hl };
428: oUop = {`op, `smw, `h };
429: oUop = {`eof, `sma, `pc };
//LDHLmr_h
430: oUop = {`inc, `sma, `hl };
431: oUop = {`op, `smw, `l };
432: oUop = {`eof, `sma, `pc };
//LDABCm
433: oUop = {`inc, `sma, `bc };
434: oUop = {`op, `nop, `null };
435: oUop = {`op, `srm, `a };
436: oUop = {`eof, `sma, `pc };
//LDrHLm_a
437: oUop = {`inc, `sma, `hl };
438: oUop = {`op, `nop, `null };
439: oUop = {`op, `srm, `a };
440: oUop = {`eof, `sma, `pc };
//LDrHLm_e
441: oUop = {`inc, `sma, `hl };
442: oUop = {`op, `nop, `null };
443: oUop = {`op, `srm, `e };
444: oUop = {`eof, `sma, `pc };
//LDrHLm_e
445: oUop = {`inc, `sma, `hl };
446: oUop = {`op, `nop, `null };
447: oUop = {`op, `srm, `h };
448: oUop = {`eof, `sma, `pc };
//ADCr_a
449: oUop = { `op, `sx16r, `a };
450: oUop = { `op, `addx16, `carry };
451: oUop = { `update_flags, `addx16, `a};
452: oUop = { `inc_eof, `srx16, `a };
//ADCr_b
453: oUop = { `op, `sx16r, `a };
454: oUop = { `op, `addx16, `carry };
455: oUop = { `update_flags, `addx16, `b};
456: oUop = { `inc_eof, `srx16, `a };
//ADCr_c
457: oUop = { `op, `sx16r, `a };
458: oUop = { `op, `addx16, `carry };
459: oUop = { `update_flags, `addx16, `c};
460: oUop = { `inc_eof, `srx16, `a };
//ADCr_d
461: oUop = { `op, `sx16r, `a };
462: oUop = { `op, `addx16, `carry };
463: oUop = { `update_flags, `addx16, `d};
464: oUop = { `inc_eof, `srx16, `a };
//ADCr_e
465: oUop = { `op, `sx16r, `a };
466: oUop = { `op, `addx16, `carry };
467: oUop = { `update_flags, `addx16, `e};
468: oUop = { `inc_eof, `srx16, `a };
//ADCr_h
469: oUop = { `op, `sx16r, `a };
470: oUop = { `op, `addx16, `carry };
471: oUop = { `update_flags, `addx16, `h};
472: oUop = { `inc_eof, `srx16, `a };
//ADCr_l
473: oUop = { `op, `sx16r, `a };
474: oUop = { `op, `addx16, `carry };
475: oUop = { `update_flags, `addx16, `l};
476: oUop = { `inc_eof, `srx16, `a };
//SHR
477: oUop = { `update_flags, `shr, `null };
478: oUop = { `inc_eof, `nop, `null };
//FLOW_ID_INT_VBLANK
/*
163: oUop = { `op, `ceti, `null}; //Disable interruption
164: oUop = { `inc, `dec16, `sp };
165: oUop = { `inc, `sx16r, `hl };
166: oUop = { `op , `srm, `l }; //l = MEM[pc] = literal
167: oUop = { `inc, `srm, `h }; //l = MEM[pc] = literal
168: oUop = { `op, `sma, `sp };
169: oUop = { `op, `smw, `pch }; //MEM[sp] = pc[7:0]
170: oUop = { `op, `dec16, `sp };
171: oUop = { `op , `smw, `pc }; //MEM[sp+1] = pc[15:8]
172: oUop = { `op , `sx16l, 8'h40 };
173: oUop = { `op, `srx16, `pc };
174: oUop = { `inc ,`sma, `pc };
*/
/*
//RETI
inc sma shadow_addr_reg
op smw
op inc16 x16
op smw b
op inc16 x16
op smw c
op inc16 x16
op smw e
op inc16 x16
op smw h
op inc16 x16
op smw l
op inc16 x16
op smw spl
op inc16 x16
op smw sph
*/
default:
oUop = {`op, `nop, `null };
endcase
end
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module amm_master_qsys_with_pcie_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
)
;
output almost_empty;
output almost_full;
output empty;
output full;
output [ 60: 0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [ 60: 0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1: 0] entries;
reg [ 60: 0] entry_0;
reg [ 60: 0] entry_1;
wire full;
reg rd_address;
reg [ 60: 0] rd_data;
wire [ 1: 0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address)
begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end
else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full)
begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty)
begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk)
begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module amm_master_qsys_with_pcie_sdram (
// inputs:
az_addr,
az_be_n,
az_cs,
az_data,
az_rd_n,
az_wr_n,
clk,
reset_n,
// outputs:
za_data,
za_valid,
za_waitrequest,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dq,
zs_dqm,
zs_ras_n,
zs_we_n
)
;
output [ 31: 0] za_data;
output za_valid;
output za_waitrequest;
output [ 11: 0] zs_addr;
output [ 1: 0] zs_ba;
output zs_cas_n;
output zs_cke;
output zs_cs_n;
inout [ 31: 0] zs_dq;
output [ 3: 0] zs_dqm;
output zs_ras_n;
output zs_we_n;
input [ 23: 0] az_addr;
input [ 3: 0] az_be_n;
input az_cs;
input [ 31: 0] az_data;
input az_rd_n;
input az_wr_n;
input clk;
input reset_n;
wire [ 23: 0] CODE;
reg ack_refresh_request;
reg [ 23: 0] active_addr;
wire [ 1: 0] active_bank;
reg active_cs_n;
reg [ 31: 0] active_data;
reg [ 3: 0] active_dqm;
reg active_rnw;
wire almost_empty;
wire almost_full;
wire bank_match;
wire [ 9: 0] cas_addr;
wire clk_en;
wire [ 3: 0] cmd_all;
wire [ 2: 0] cmd_code;
wire cs_n;
wire csn_decode;
wire csn_match;
wire [ 23: 0] f_addr;
wire [ 1: 0] f_bank;
wire f_cs_n;
wire [ 31: 0] f_data;
wire [ 3: 0] f_dqm;
wire f_empty;
reg f_pop;
wire f_rnw;
wire f_select;
wire [ 60: 0] fifo_read_data;
reg [ 11: 0] i_addr;
reg [ 3: 0] i_cmd;
reg [ 2: 0] i_count;
reg [ 2: 0] i_next;
reg [ 2: 0] i_refs;
reg [ 2: 0] i_state;
reg init_done;
reg [ 11: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 2: 0] m_count;
reg [ 31: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [ 3: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 8: 0] m_next;
reg [ 8: 0] m_state;
reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
wire pending;
wire rd_strobe;
reg [ 2: 0] rd_valid;
reg [ 12: 0] refresh_counter;
reg refresh_request;
wire rnw_match;
wire row_match;
wire [ 23: 0] txt_code;
reg za_cannotrefresh;
reg [ 31: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
reg za_valid;
wire za_waitrequest;
wire [ 11: 0] zs_addr;
wire [ 1: 0] zs_ba;
wire zs_cas_n;
wire zs_cke;
wire zs_cs_n;
wire [ 31: 0] zs_dq;
wire [ 3: 0] zs_dqm;
wire zs_ras_n;
wire zs_we_n;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;
assign zs_addr = m_addr;
assign zs_cke = clk_en;
assign zs_dq = oe?m_data:{32{1'bz}};
assign zs_dqm = m_dqm;
assign zs_ba = m_bank;
assign f_select = f_pop & pending;
assign f_cs_n = 1'b0;
assign cs_n = f_select ? f_cs_n : active_cs_n;
assign csn_decode = cs_n;
assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;
amm_master_qsys_with_pcie_sdram_input_efifo_module the_amm_master_qsys_with_pcie_sdram_input_efifo_module
(
.almost_empty (almost_empty),
.almost_full (almost_full),
.clk (clk),
.empty (f_empty),
.full (za_waitrequest),
.rd (f_select),
.rd_data (fifo_read_data),
.reset_n (reset_n),
.wr ((~az_wr_n | ~az_rd_n) & !za_waitrequest),
.wr_data ({az_wr_n, az_addr, az_wr_n ? 4'b0 : az_be_n, az_data})
);
assign f_bank = {f_addr[23],f_addr[10]};
// Refresh/init counter.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_counter <= 5000;
else if (refresh_counter == 0)
refresh_counter <= 781;
else
refresh_counter <= refresh_counter - 1'b1;
end
// Refresh request signal.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_request <= 0;
else if (1)
refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done;
end
// Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_cannotrefresh <= 0;
else if (1)
za_cannotrefresh <= (refresh_counter == 0) & refresh_request;
end
// Initialization-done flag.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
init_done <= 0;
else if (1)
init_done <= init_done | (i_state == 3'b101);
end
// **** Init FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
i_state <= 3'b000;
i_next <= 3'b000;
i_cmd <= 4'b1111;
i_addr <= {12{1'b1}};
i_count <= {3{1'b0}};
end
else
begin
i_addr <= {12{1'b1}};
case (i_state) // synthesis parallel_case full_case
3'b000: begin
i_cmd <= 4'b1111;
i_refs <= 3'b0;
//Wait for refresh count-down after reset
if (refresh_counter == 0)
i_state <= 3'b001;
end // 3'b000
3'b001: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h2};
i_count <= 0;
i_next <= 3'b010;
end // 3'b001
3'b010: begin
i_cmd <= {{1{1'b0}},3'h1};
i_refs <= i_refs + 1'b1;
i_state <= 3'b011;
i_count <= 3;
// Count up init_refresh_commands
if (i_refs == 3'h1)
i_next <= 3'b111;
else
i_next <= 3'b010;
end // 3'b010
3'b011: begin
i_cmd <= {{1{1'b0}},3'h7};
//WAIT til safe to Proceed...
if (i_count > 1)
i_count <= i_count - 1'b1;
else
i_state <= i_next;
end // 3'b011
3'b101: begin
i_state <= 3'b101;
end // 3'b101
3'b111: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h0};
i_addr <= {{2{1'b0}},1'b0,2'b00,3'h3,4'h0};
i_count <= 4;
i_next <= 3'b101;
end // 3'b111
default: begin
i_state <= 3'b000;
end // default
endcase // i_state
end
end
assign active_bank = {active_addr[23],active_addr[10]};
assign csn_match = active_cs_n == f_cs_n;
assign rnw_match = active_rnw == f_rnw;
assign bank_match = active_bank == f_bank;
assign row_match = {active_addr[22 : 11]} == {f_addr[22 : 11]};
assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;
assign cas_addr = f_select ? { {2{1'b0}},f_addr[9 : 0] } : { {2{1'b0}},active_addr[9 : 0] };
// **** Main FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= 4'b1111;
m_bank <= 2'b00;
m_addr <= 12'b000000000000;
m_data <= 32'b00000000000000000000000000000000;
m_dqm <= 4'b0000;
m_count <= 3'b000;
ack_refresh_request <= 1'b0;
f_pop <= 1'b0;
oe <= 1'b0;
end
else
begin
f_pop <= 1'b0;
oe <= 1'b0;
case (m_state) // synthesis parallel_case full_case
9'b000000001: begin
//Wait for init-fsm to be done...
if (init_done)
begin
//Hold bus if another cycle ended to arf.
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= 4'b1111;
ack_refresh_request <= 1'b0;
//Wait for a read/write request.
if (refresh_request)
begin
m_state <= 9'b001000000;
m_next <= 9'b010000000;
m_count <= 0;
active_cs_n <= 1'b1;
end
else if (!f_empty)
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
m_state <= 9'b000000010;
end
end
else
begin
m_addr <= i_addr;
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= i_cmd;
end
end // 9'b000000001
9'b000000010: begin
m_state <= 9'b000000100;
m_cmd <= {csn_decode,3'h3};
m_bank <= active_bank;
m_addr <= active_addr[22 : 11];
m_data <= active_data;
m_dqm <= active_dqm;
m_count <= 1;
m_next <= active_rnw ? 9'b000001000 : 9'b000010000;
end // 9'b000000010
9'b000000100: begin
// precharge all if arf, else precharge csn_decode
if (m_next == 9'b010000000)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
m_state <= m_next;
end // 9'b000000100
9'b000001000: begin
m_cmd <= {csn_decode,3'h5};
m_bank <= f_select ? f_bank : active_bank;
m_dqm <= f_select ? f_dqm : active_dqm;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end RD spin cycle if fifo mt
if (~pending & f_pop)
m_cmd <= {csn_decode,3'h7};
m_state <= 9'b100000000;
end
end // 9'b000001000
9'b000010000: begin
m_cmd <= {csn_decode,3'h4};
oe <= 1'b1;
m_data <= f_select ? f_data : active_data;
m_dqm <= f_select ? f_dqm : active_dqm;
m_bank <= f_select ? f_bank : active_bank;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end WR spin cycle if fifo empty
if (~pending & f_pop)
begin
m_cmd <= {csn_decode,3'h7};
oe <= 1'b0;
end
m_state <= 9'b100000000;
end
end // 9'b000010000
9'b000100000: begin
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
begin
m_state <= 9'b001000000;
m_count <= 0;
end
end // 9'b000100000
9'b001000000: begin
m_state <= 9'b000000100;
m_addr <= {12{1'b1}};
// precharge all if arf, else precharge csn_decode
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h2};
else
m_cmd <= {csn_decode,3'h2};
end // 9'b001000000
9'b010000000: begin
ack_refresh_request <= 1'b1;
m_state <= 9'b000000100;
m_cmd <= {{1{1'b0}},3'h1};
m_count <= 3;
m_next <= 9'b000000001;
end // 9'b010000000
9'b100000000: begin
m_cmd <= {csn_decode,3'h7};
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else //wait for fifo to have contents
if (!f_empty)
//Are we 'pending' yet?
if (csn_match && rnw_match && bank_match && row_match)
begin
m_state <= f_rnw ? 9'b000001000 : 9'b000010000;
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
else
begin
m_state <= 9'b000100000;
m_next <= 9'b000000001;
m_count <= 1;
end
end // 9'b100000000
// synthesis translate_off
default: begin
m_state <= m_state;
m_cmd <= 4'b1111;
f_pop <= 1'b0;
oe <= 1'b0;
end // default
// synthesis translate_on
endcase // m_state
end
end
assign rd_strobe = m_cmd[2 : 0] == 3'h5;
//Track RD Req's based on cas_latency w/shift reg
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_valid <= {3{1'b0}};
else
rd_valid <= (rd_valid << 1) | { {2{1'b0}}, rd_strobe };
end
// Register dq data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_data <= 0;
else
za_data <= zs_dq;
end
// Delay za_valid to match registered data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_valid <= 0;
else if (1)
za_valid <= rd_valid[2];
end
assign cmd_code = m_cmd[2 : 0];
assign cmd_all = m_cmd;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
initial
begin
$write("\n");
$write("This reference design requires a vendor simulation model.\n");
$write("To simulate accesses to SDRAM, you must:\n");
$write(" - Download the vendor model\n");
$write(" - Install the model in the system_sim directory\n");
$write(" - `include the vendor model in the the top-level system file,\n");
$write(" - Instantiate sdram simulation models and wire them to testbench signals\n");
$write(" - Be aware that you may have to disable some timing checks in the vendor model\n");
$write(" (because this simulation is zero-delay based)\n");
$write("\n");
end
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MAJ3_2_V
`define SKY130_FD_SC_HS__MAJ3_2_V
/**
* maj3: 3-input majority vote.
*
* Verilog wrapper for maj3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__maj3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__maj3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__maj3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__MAJ3_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21A_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O21A_PP_SYMBOL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o21a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21A_PP_SYMBOL_V
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Contribution by Claude Marché and Xavier Urbain *)
(** Euclidean Division
Defines first of function that allows Coq to normalize.
Then only after proves the main required property.
*)
Require Export ZArith_base.
Require Import Zbool Omega ZArithRing Zcomplements Setoid Morphisms.
Require ZDivFloor.
Open Local Scope Z_scope.
(** * Definitions of Euclidian operations *)
(** Euclidean division of a positive by a integer
(that is supposed to be positive).
Total function than returns an arbitrary value when
divisor is not positive
*)
Unboxed Fixpoint Zdiv_eucl_POS (a:positive) (b:Z) : Z * Z :=
match a with
| xH => if Zge_bool b 2 then (0, 1) else (1, 0)
| xO a' =>
let (q, r) := Zdiv_eucl_POS a' b in
let r' := 2 * r in
if Zgt_bool b r' then (2 * q, r') else (2 * q + 1, r' - b)
| xI a' =>
let (q, r) := Zdiv_eucl_POS a' b in
let r' := 2 * r + 1 in
if Zgt_bool b r' then (2 * q, r') else (2 * q + 1, r' - b)
end.
(** Euclidean division of integers.
Total function than returns (0,0) when dividing by 0.
*)
(**
The pseudo-code is:
if b = 0 : (0,0)
if b <> 0 and a = 0 : (0,0)
if b > 0 and a < 0 : let (q,r) = div_eucl_pos (-a) b in
if r = 0 then (-q,0) else (-(q+1),b-r)
if b < 0 and a < 0 : let (q,r) = div_eucl (-a) (-b) in (q,-r)
if b < 0 and a > 0 : let (q,r) = div_eucl a (-b) in
if r = 0 then (-q,0) else (-(q+1),b+r)
In other word, when b is non-zero, q is chosen to be the greatest integer
smaller or equal to a/b. And sgn(r)=sgn(b) and |r| < |b| (at least when
r is not null).
*)
(* Nota: At least two others conventions also exist for euclidean division.
They all satify the equation a=b*q+r, but differ on the choice of (q,r)
on negative numbers.
* Ocaml uses Round-Toward-Zero division: (-a)/b = a/(-b) = -(a/b).
Hence (-a) mod b = - (a mod b)
a mod (-b) = a mod b
And: |r| < |b| and sgn(r) = sgn(a) (notice the a here instead of b).
* Another solution is to always pick a non-negative remainder:
a=b*q+r with 0 <= r < |b|
*)
Definition Zdiv_eucl (a b:Z) : Z * Z :=
match a, b with
| Z0, _ => (0, 0)
| _, Z0 => (0, 0)
| Zpos a', Zpos _ => Zdiv_eucl_POS a' b
| Zneg a', Zpos _ =>
let (q, r) := Zdiv_eucl_POS a' b in
match r with
| Z0 => (- q, 0)
| _ => (- (q + 1), b - r)
end
| Zneg a', Zneg b' => let (q, r) := Zdiv_eucl_POS a' (Zpos b') in (q, - r)
| Zpos a', Zneg b' =>
let (q, r) := Zdiv_eucl_POS a' (Zpos b') in
match r with
| Z0 => (- q, 0)
| _ => (- (q + 1), b + r)
end
end.
(** Division and modulo are projections of [Zdiv_eucl] *)
Definition Zdiv (a b:Z) : Z := let (q, _) := Zdiv_eucl a b in q.
Definition Zmod (a b:Z) : Z := let (_, r) := Zdiv_eucl a b in r.
(** Syntax *)
Infix "/" := Zdiv : Z_scope.
Infix "mod" := Zmod (at level 40, no associativity) : Z_scope.
(* Tests:
Eval compute in (Zdiv_eucl 7 3).
Eval compute in (Zdiv_eucl (-7) 3).
Eval compute in (Zdiv_eucl 7 (-3)).
Eval compute in (Zdiv_eucl (-7) (-3)).
*)
(** * Main division theorem *)
(** First a lemma for two positive arguments *)
Lemma Z_div_mod_POS :
forall b:Z,
b > 0 ->
forall a:positive,
let (q, r) := Zdiv_eucl_POS a b in Zpos a = b * q + r /\ 0 <= r < b.
Proof.
simple induction a; cbv beta iota delta [Zdiv_eucl_POS] in |- *;
fold Zdiv_eucl_POS in |- *; cbv zeta.
intro p; case (Zdiv_eucl_POS p b); intros q r [H0 H1].
generalize (Zgt_cases b (2 * r + 1)).
case (Zgt_bool b (2 * r + 1));
(rewrite BinInt.Zpos_xI; rewrite H0; split; [ ring | omega ]).
intros p; case (Zdiv_eucl_POS p b); intros q r [H0 H1].
generalize (Zgt_cases b (2 * r)).
case (Zgt_bool b (2 * r)); rewrite BinInt.Zpos_xO;
change (Zpos (xO p)) with (2 * Zpos p) in |- *; rewrite H0;
(split; [ ring | omega ]).
generalize (Zge_cases b 2).
case (Zge_bool b 2); (intros; split; [ try ring | omega ]).
omega.
Qed.
(** Then the usual situation of a positive [b] and no restriction on [a] *)
Theorem Z_div_mod :
forall a b:Z,
b > 0 -> let (q, r) := Zdiv_eucl a b in a = b * q + r /\ 0 <= r < b.
Proof.
intros a b; case a; case b; try (simpl in |- *; intros; omega).
unfold Zdiv_eucl in |- *; intros; apply Z_div_mod_POS; trivial.
intros; discriminate.
intros.
generalize (Z_div_mod_POS (Zpos p) H p0).
unfold Zdiv_eucl in |- *.
case (Zdiv_eucl_POS p0 (Zpos p)).
intros z z0.
case z0.
intros [H1 H2].
split; trivial.
change (Zneg p0) with (- Zpos p0); rewrite H1; ring.
intros p1 [H1 H2].
split; trivial.
change (Zneg p0) with (- Zpos p0); rewrite H1; ring.
generalize (Zorder.Zgt_pos_0 p1); omega.
intros p1 [H1 H2].
split; trivial.
change (Zneg p0) with (- Zpos p0); rewrite H1; ring.
generalize (Zorder.Zlt_neg_0 p1); omega.
intros; discriminate.
Qed.
(** For stating the fully general result, let's give a short name
to the condition on the remainder. *)
Definition Remainder r b := 0 <= r < b \/ b < r <= 0.
(** Another equivalent formulation: *)
Definition Remainder_alt r b := Zabs r < Zabs b /\ Zsgn r <> - Zsgn b.
(* In the last formulation, [ Zsgn r <> - Zsgn b ] is less nice than saying
[ Zsgn r = Zsgn b ], but at least it works even when [r] is null. *)
Lemma Remainder_equiv : forall r b, Remainder r b <-> Remainder_alt r b.
Proof.
intros; unfold Remainder, Remainder_alt; omega with *.
Qed.
Hint Unfold Remainder.
(** Now comes the fully general result about Euclidean division. *)
Theorem Z_div_mod_full :
forall a b:Z,
b <> 0 -> let (q, r) := Zdiv_eucl a b in a = b * q + r /\ Remainder r b.
Proof.
destruct b as [|b|b].
(* b = 0 *)
intro H; elim H; auto.
(* b > 0 *)
intros _.
assert (Zpos b > 0) by auto with zarith.
generalize (Z_div_mod a (Zpos b) H).
destruct Zdiv_eucl as (q,r); intuition; simpl; auto.
(* b < 0 *)
intros _.
assert (Zpos b > 0) by auto with zarith.
generalize (Z_div_mod a (Zpos b) H).
unfold Remainder.
destruct a as [|a|a].
(* a = 0 *)
simpl; intuition.
(* a > 0 *)
unfold Zdiv_eucl; destruct Zdiv_eucl_POS as (q,r).
destruct r as [|r|r]; [ | | omega with *].
rewrite <- Zmult_opp_comm; simpl Zopp; intuition.
rewrite <- Zmult_opp_comm; simpl Zopp.
rewrite Zmult_plus_distr_r; omega with *.
(* a < 0 *)
unfold Zdiv_eucl.
generalize (Z_div_mod_POS (Zpos b) H a).
destruct Zdiv_eucl_POS as (q,r).
destruct r as [|r|r]; change (Zneg b) with (-Zpos b).
rewrite Zmult_opp_comm; omega with *.
rewrite <- Zmult_opp_comm, Zmult_plus_distr_r;
repeat rewrite Zmult_opp_comm; omega.
rewrite Zmult_opp_comm; omega with *.
Qed.
(** The same results as before, stated separately in terms of Zdiv and Zmod *)
Lemma Z_mod_remainder : forall a b:Z, b<>0 -> Remainder (a mod b) b.
Proof.
unfold Zmod; intros a b Hb; generalize (Z_div_mod_full a b Hb); auto.
destruct Zdiv_eucl; tauto.
Qed.
Lemma Z_mod_lt : forall a b:Z, b > 0 -> 0 <= a mod b < b.
Proof.
unfold Zmod; intros a b Hb; generalize (Z_div_mod a b Hb).
destruct Zdiv_eucl; tauto.
Qed.
Lemma Z_mod_neg : forall a b:Z, b < 0 -> b < a mod b <= 0.
Proof.
unfold Zmod; intros a b Hb.
assert (Hb' : b<>0) by (auto with zarith).
generalize (Z_div_mod_full a b Hb').
destruct Zdiv_eucl.
unfold Remainder; intuition.
Qed.
Lemma Z_div_mod_eq_full : forall a b:Z, b <> 0 -> a = b*(a/b) + (a mod b).
Proof.
unfold Zdiv, Zmod; intros a b Hb; generalize (Z_div_mod_full a b Hb).
destruct Zdiv_eucl; tauto.
Qed.
Lemma Z_div_mod_eq : forall a b:Z, b > 0 -> a = b*(a/b) + (a mod b).
Proof.
intros; apply Z_div_mod_eq_full; auto with zarith.
Qed.
Lemma Zmod_eq_full : forall a b:Z, b<>0 -> a mod b = a - (a/b)*b.
Proof.
intros.
rewrite <- Zeq_plus_swap, Zplus_comm, Zmult_comm; symmetry.
apply Z_div_mod_eq_full; auto.
Qed.
Lemma Zmod_eq : forall a b:Z, b>0 -> a mod b = a - (a/b)*b.
Proof.
intros.
rewrite <- Zeq_plus_swap, Zplus_comm, Zmult_comm; symmetry.
apply Z_div_mod_eq; auto.
Qed.
(** We know enough to prove that [Zdiv] and [Zmod] are instances of
one of the abstract Euclidean divisions of Numbers.
We hence benefit from generic results about this abstract division. *)
Module Z.
Definition div := Zdiv.
Definition modulo := Zmod.
Local Obligation Tactic := simpl_relation.
Program Instance div_wd : Proper (eq==>eq==>eq) div.
Program Instance mod_wd : Proper (eq==>eq==>eq) modulo.
Definition div_mod := Z_div_mod_eq_full.
Definition mod_pos_bound : forall a b:Z, 0<b -> 0<=a mod b<b.
Proof. intros; apply Z_mod_lt; auto with zarith. Qed.
Definition mod_neg_bound := Z_mod_neg.
Include ZBinary.Z <+ ZDivFloor.ZDivProp.
End Z.
(** Existence theorem *)
Theorem Zdiv_eucl_exist : forall (b:Z)(Hb:b>0)(a:Z),
{qr : Z * Z | let (q, r) := qr in a = b * q + r /\ 0 <= r < b}.
Proof.
intros b Hb a.
exists (Zdiv_eucl a b).
exact (Z_div_mod a b Hb).
Qed.
Implicit Arguments Zdiv_eucl_exist.
(** Uniqueness theorems *)
Theorem Zdiv_mod_unique :
forall b q1 q2 r1 r2:Z,
0 <= r1 < Zabs b -> 0 <= r2 < Zabs b ->
b*q1+r1 = b*q2+r2 -> q1=q2 /\ r1=r2.
Proof.
intros b q1 q2 r1 r2 Hr1 Hr2 H.
destruct (Z_eq_dec q1 q2) as [Hq|Hq].
split; trivial.
rewrite Hq in H; omega.
elim (Zlt_not_le (Zabs (r2 - r1)) (Zabs b)).
omega with *.
replace (r2-r1) with (b*(q1-q2)) by (rewrite Zmult_minus_distr_l; omega).
replace (Zabs b) with ((Zabs b)*1) by ring.
rewrite Zabs_Zmult.
apply Zmult_le_compat_l; auto with *.
omega with *.
Qed.
Theorem Zdiv_mod_unique_2 :
forall b q1 q2 r1 r2:Z,
Remainder r1 b -> Remainder r2 b ->
b*q1+r1 = b*q2+r2 -> q1=q2 /\ r1=r2.
Proof. exact Z.div_mod_unique. Qed.
Theorem Zdiv_unique_full:
forall a b q r, Remainder r b ->
a = b*q + r -> q = a/b.
Proof. exact Z.div_unique. Qed.
Theorem Zdiv_unique:
forall a b q r, 0 <= r < b ->
a = b*q + r -> q = a/b.
Proof. intros; eapply Zdiv_unique_full; eauto. Qed.
Theorem Zmod_unique_full:
forall a b q r, Remainder r b ->
a = b*q + r -> r = a mod b.
Proof. exact Z.mod_unique. Qed.
Theorem Zmod_unique:
forall a b q r, 0 <= r < b ->
a = b*q + r -> r = a mod b.
Proof. intros; eapply Zmod_unique_full; eauto. Qed.
(** * Basic values of divisions and modulo. *)
Lemma Zmod_0_l: forall a, 0 mod a = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zmod_0_r: forall a, a mod 0 = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zdiv_0_l: forall a, 0/a = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zdiv_0_r: forall a, a/0 = 0.
Proof.
destruct a; simpl; auto.
Qed.
Ltac zero_or_not a :=
destruct (Z_eq_dec a 0);
[subst; rewrite ?Zmod_0_l, ?Zdiv_0_l, ?Zmod_0_r, ?Zdiv_0_r;
auto with zarith|].
Lemma Zmod_1_r: forall a, a mod 1 = 0.
Proof. intros. zero_or_not a. apply Z.mod_1_r. Qed.
Lemma Zdiv_1_r: forall a, a/1 = a.
Proof. intros. zero_or_not a. apply Z.div_1_r. Qed.
Hint Resolve Zmod_0_l Zmod_0_r Zdiv_0_l Zdiv_0_r Zdiv_1_r Zmod_1_r
: zarith.
Lemma Zdiv_1_l: forall a, 1 < a -> 1/a = 0.
Proof. exact Z.div_1_l. Qed.
Lemma Zmod_1_l: forall a, 1 < a -> 1 mod a = 1.
Proof. exact Z.mod_1_l. Qed.
Lemma Z_div_same_full : forall a:Z, a<>0 -> a/a = 1.
Proof. exact Z.div_same. Qed.
Lemma Z_mod_same_full : forall a, a mod a = 0.
Proof. intros. zero_or_not a. apply Z.mod_same; auto. Qed.
Lemma Z_mod_mult : forall a b, (a*b) mod b = 0.
Proof. intros. zero_or_not b. apply Z.mod_mul. auto. Qed.
Lemma Z_div_mult_full : forall a b:Z, b <> 0 -> (a*b)/b = a.
Proof. exact Z.div_mul. Qed.
(** * Order results about Zmod and Zdiv *)
(* Division of positive numbers is positive. *)
Lemma Z_div_pos: forall a b, b > 0 -> 0 <= a -> 0 <= a/b.
Proof. intros. apply Z.div_pos; auto with zarith. Qed.
Lemma Z_div_ge0: forall a b, b > 0 -> a >= 0 -> a/b >=0.
Proof.
intros; generalize (Z_div_pos a b H); auto with zarith.
Qed.
(** As soon as the divisor is greater or equal than 2,
the division is strictly decreasing. *)
Lemma Z_div_lt : forall a b:Z, b >= 2 -> a > 0 -> a/b < a.
Proof. intros. apply Z.div_lt; auto with zarith. Qed.
(** A division of a small number by a bigger one yields zero. *)
Theorem Zdiv_small: forall a b, 0 <= a < b -> a/b = 0.
Proof. exact Z.div_small. Qed.
(** Same situation, in term of modulo: *)
Theorem Zmod_small: forall a n, 0 <= a < n -> a mod n = a.
Proof. exact Z.mod_small. Qed.
(** [Zge] is compatible with a positive division. *)
Lemma Z_div_ge : forall a b c:Z, c > 0 -> a >= b -> a/c >= b/c.
Proof. intros. apply Zle_ge. apply Z.div_le_mono; auto with zarith. Qed.
(** Same, with [Zle]. *)
Lemma Z_div_le : forall a b c:Z, c > 0 -> a <= b -> a/c <= b/c.
Proof. intros. apply Z.div_le_mono; auto with zarith. Qed.
(** With our choice of division, rounding of (a/b) is always done toward bottom: *)
Lemma Z_mult_div_ge : forall a b:Z, b > 0 -> b*(a/b) <= a.
Proof. intros. apply Z.mul_div_le; auto with zarith. Qed.
Lemma Z_mult_div_ge_neg : forall a b:Z, b < 0 -> b*(a/b) >= a.
Proof. intros. apply Zle_ge. apply Z.mul_div_ge; auto with zarith. Qed.
(** The previous inequalities are exact iff the modulo is zero. *)
Lemma Z_div_exact_full_1 : forall a b:Z, a = b*(a/b) -> a mod b = 0.
Proof. intros a b. zero_or_not b. rewrite Z.div_exact; auto. Qed.
Lemma Z_div_exact_full_2 : forall a b:Z, b <> 0 -> a mod b = 0 -> a = b*(a/b).
Proof. intros; rewrite Z.div_exact; auto. Qed.
(** A modulo cannot grow beyond its starting point. *)
Theorem Zmod_le: forall a b, 0 < b -> 0 <= a -> a mod b <= a.
Proof. intros. apply Z.mod_le; auto. Qed.
(** Some additionnal inequalities about Zdiv. *)
Theorem Zdiv_lt_upper_bound:
forall a b q, 0 < b -> a < q*b -> a/b < q.
Proof. intros a b q; rewrite Zmult_comm; apply Z.div_lt_upper_bound. Qed.
Theorem Zdiv_le_upper_bound:
forall a b q, 0 < b -> a <= q*b -> a/b <= q.
Proof. intros a b q; rewrite Zmult_comm; apply Z.div_le_upper_bound. Qed.
Theorem Zdiv_le_lower_bound:
forall a b q, 0 < b -> q*b <= a -> q <= a/b.
Proof. intros a b q; rewrite Zmult_comm; apply Z.div_le_lower_bound. Qed.
(** A division of respect opposite monotonicity for the divisor *)
Lemma Zdiv_le_compat_l: forall p q r, 0 <= p -> 0 < q < r ->
p / r <= p / q.
Proof. intros; apply Z.div_le_compat_l; auto with zarith. Qed.
Theorem Zdiv_sgn: forall a b,
0 <= Zsgn (a/b) * Zsgn a * Zsgn b.
Proof.
destruct a as [ |a|a]; destruct b as [ |b|b]; simpl; auto with zarith;
generalize (Z_div_pos (Zpos a) (Zpos b)); unfold Zdiv, Zdiv_eucl;
destruct Zdiv_eucl_POS as (q,r); destruct r; omega with *.
Qed.
(** * Relations between usual operations and Zmod and Zdiv *)
Lemma Z_mod_plus_full : forall a b c:Z, (a + b * c) mod c = a mod c.
Proof. intros. zero_or_not c. apply Z.mod_add; auto. Qed.
Lemma Z_div_plus_full : forall a b c:Z, c <> 0 -> (a + b * c) / c = a / c + b.
Proof. exact Z.div_add. Qed.
Theorem Z_div_plus_full_l: forall a b c : Z, b <> 0 -> (a * b + c) / b = a + c / b.
Proof. exact Z.div_add_l. Qed.
(** [Zopp] and [Zdiv], [Zmod].
Due to the choice of convention for our Euclidean division,
some of the relations about [Zopp] and divisions are rather complex. *)
Lemma Zdiv_opp_opp : forall a b:Z, (-a)/(-b) = a/b.
Proof. intros. zero_or_not b. apply Z.div_opp_opp; auto. Qed.
Lemma Zmod_opp_opp : forall a b:Z, (-a) mod (-b) = - (a mod b).
Proof. intros. zero_or_not b. apply Z.mod_opp_opp; auto. Qed.
Lemma Z_mod_zero_opp_full : forall a b:Z, a mod b = 0 -> (-a) mod b = 0.
Proof. intros. zero_or_not b. apply Z.mod_opp_l_z; auto. Qed.
Lemma Z_mod_nz_opp_full : forall a b:Z, a mod b <> 0 ->
(-a) mod b = b - (a mod b).
Proof. intros. zero_or_not b. apply Z.mod_opp_l_nz; auto. Qed.
Lemma Z_mod_zero_opp_r : forall a b:Z, a mod b = 0 -> a mod (-b) = 0.
Proof. intros. zero_or_not b. apply Z.mod_opp_r_z; auto. Qed.
Lemma Z_mod_nz_opp_r : forall a b:Z, a mod b <> 0 ->
a mod (-b) = (a mod b) - b.
Proof. intros. zero_or_not b. apply Z.mod_opp_r_nz; auto. Qed.
Lemma Z_div_zero_opp_full : forall a b:Z, a mod b = 0 -> (-a)/b = -(a/b).
Proof. intros. zero_or_not b. apply Z.div_opp_l_z; auto. Qed.
Lemma Z_div_nz_opp_full : forall a b:Z, a mod b <> 0 ->
(-a)/b = -(a/b)-1.
Proof. intros a b. zero_or_not b. intros; rewrite Z.div_opp_l_nz; auto. Qed.
Lemma Z_div_zero_opp_r : forall a b:Z, a mod b = 0 -> a/(-b) = -(a/b).
Proof. intros. zero_or_not b. apply Z.div_opp_r_z; auto. Qed.
Lemma Z_div_nz_opp_r : forall a b:Z, a mod b <> 0 ->
a/(-b) = -(a/b)-1.
Proof. intros a b. zero_or_not b. intros; rewrite Z.div_opp_r_nz; auto. Qed.
(** Cancellations. *)
Lemma Zdiv_mult_cancel_r : forall a b c:Z,
c <> 0 -> (a*c)/(b*c) = a/b.
Proof. intros. zero_or_not b. apply Z.div_mul_cancel_r; auto. Qed.
Lemma Zdiv_mult_cancel_l : forall a b c:Z,
c<>0 -> (c*a)/(c*b) = a/b.
Proof.
intros. rewrite (Zmult_comm c b); zero_or_not b.
rewrite (Zmult_comm b c). apply Z.div_mul_cancel_l; auto.
Qed.
Lemma Zmult_mod_distr_l: forall a b c,
(c*a) mod (c*b) = c * (a mod b).
Proof.
intros. zero_or_not c. rewrite (Zmult_comm c b); zero_or_not b.
rewrite (Zmult_comm b c). apply Z.mul_mod_distr_l; auto.
Qed.
Lemma Zmult_mod_distr_r: forall a b c,
(a*c) mod (b*c) = (a mod b) * c.
Proof.
intros. zero_or_not b. rewrite (Zmult_comm b c); zero_or_not c.
rewrite (Zmult_comm c b). apply Z.mul_mod_distr_r; auto.
Qed.
(** Operations modulo. *)
Theorem Zmod_mod: forall a n, (a mod n) mod n = a mod n.
Proof. intros. zero_or_not n. apply Z.mod_mod; auto. Qed.
Theorem Zmult_mod: forall a b n,
(a * b) mod n = ((a mod n) * (b mod n)) mod n.
Proof. intros. zero_or_not n. apply Z.mul_mod; auto. Qed.
Theorem Zplus_mod: forall a b n,
(a + b) mod n = (a mod n + b mod n) mod n.
Proof. intros. zero_or_not n. apply Z.add_mod; auto. Qed.
Theorem Zminus_mod: forall a b n,
(a - b) mod n = (a mod n - b mod n) mod n.
Proof.
intros.
replace (a - b) with (a + (-1) * b); auto with zarith.
replace (a mod n - b mod n) with (a mod n + (-1) * (b mod n)); auto with zarith.
rewrite Zplus_mod.
rewrite Zmult_mod.
rewrite Zplus_mod with (b:=(-1) * (b mod n)).
rewrite Zmult_mod.
rewrite Zmult_mod with (b:= b mod n).
repeat rewrite Zmod_mod; auto.
Qed.
Lemma Zplus_mod_idemp_l: forall a b n, (a mod n + b) mod n = (a + b) mod n.
Proof.
intros; rewrite Zplus_mod, Zmod_mod, <- Zplus_mod; auto.
Qed.
Lemma Zplus_mod_idemp_r: forall a b n, (b + a mod n) mod n = (b + a) mod n.
Proof.
intros; rewrite Zplus_mod, Zmod_mod, <- Zplus_mod; auto.
Qed.
Lemma Zminus_mod_idemp_l: forall a b n, (a mod n - b) mod n = (a - b) mod n.
Proof.
intros; rewrite Zminus_mod, Zmod_mod, <- Zminus_mod; auto.
Qed.
Lemma Zminus_mod_idemp_r: forall a b n, (a - b mod n) mod n = (a - b) mod n.
Proof.
intros; rewrite Zminus_mod, Zmod_mod, <- Zminus_mod; auto.
Qed.
Lemma Zmult_mod_idemp_l: forall a b n, (a mod n * b) mod n = (a * b) mod n.
Proof.
intros; rewrite Zmult_mod, Zmod_mod, <- Zmult_mod; auto.
Qed.
Lemma Zmult_mod_idemp_r: forall a b n, (b * (a mod n)) mod n = (b * a) mod n.
Proof.
intros; rewrite Zmult_mod, Zmod_mod, <- Zmult_mod; auto.
Qed.
(** For a specific number N, equality modulo N is hence a nice setoid
equivalence, compatible with [+], [-] and [*]. *)
Definition eqm N a b := (a mod N = b mod N).
Lemma eqm_refl N : forall a, (eqm N) a a.
Proof. unfold eqm; auto. Qed.
Lemma eqm_sym N : forall a b, (eqm N) a b -> (eqm N) b a.
Proof. unfold eqm; auto. Qed.
Lemma eqm_trans N : forall a b c,
(eqm N) a b -> (eqm N) b c -> (eqm N) a c.
Proof. unfold eqm; eauto with *. Qed.
Add Parametric Relation N : Z (eqm N)
reflexivity proved by (eqm_refl N)
symmetry proved by (eqm_sym N)
transitivity proved by (eqm_trans N) as eqm_setoid.
Add Parametric Morphism N : Zplus
with signature (eqm N) ==> (eqm N) ==> (eqm N) as Zplus_eqm.
Proof.
unfold eqm; intros; rewrite Zplus_mod, H, H0, <- Zplus_mod; auto.
Qed.
Add Parametric Morphism N : Zminus
with signature (eqm N) ==> (eqm N) ==> (eqm N) as Zminus_eqm.
Proof.
unfold eqm; intros; rewrite Zminus_mod, H, H0, <- Zminus_mod; auto.
Qed.
Add Parametric Morphism N : Zmult
with signature (eqm N) ==> (eqm N) ==> (eqm N) as Zmult_eqm.
Proof.
unfold eqm; intros; rewrite Zmult_mod, H, H0, <- Zmult_mod; auto.
Qed.
Add Parametric Morphism N : Zopp
with signature (eqm N) ==> (eqm N) as Zopp_eqm.
Proof.
intros; change ((eqm N) (-x) (-y)) with ((eqm N) (0-x) (0-y)).
rewrite H; red; auto.
Qed.
Lemma Zmod_eqm N : forall a, (eqm N) (a mod N) a.
Proof.
intros; exact (Zmod_mod a N).
Qed.
(* NB: Zmod and Zdiv are not morphisms with respect to eqm.
For instance, let (==) be (eqm 2). Then we have (3 == 1) but:
~ (3 mod 3 == 1 mod 3)
~ (1 mod 3 == 1 mod 1)
~ (3/3 == 1/3)
~ (1/3 == 1/1)
*)
Lemma Zdiv_Zdiv : forall a b c, 0<=b -> 0<=c -> (a/b)/c = a/(b*c).
Proof.
intros. zero_or_not b. rewrite Zmult_comm. zero_or_not c.
rewrite Zmult_comm. apply Z.div_div; auto with zarith.
Qed.
(** Unfortunately, the previous result isn't always true on negative numbers.
For instance: 3/(-2)/(-2) = 1 <> 0 = 3 / (-2*-2) *)
(** A last inequality: *)
Theorem Zdiv_mult_le:
forall a b c, 0<=a -> 0<=b -> 0<=c -> c*(a/b) <= (c*a)/b.
Proof.
intros. zero_or_not b. apply Z.div_mul_le; auto with zarith. Qed.
(** Zmod is related to divisibility (see more in Znumtheory) *)
Lemma Zmod_divides : forall a b, b<>0 ->
(a mod b = 0 <-> exists c, a = b*c).
Proof. exact Z.mod_divides. Qed.
(** * Compatibility *)
(** Weaker results kept only for compatibility *)
Lemma Z_mod_same : forall a, a > 0 -> a mod a = 0.
Proof.
intros; apply Z_mod_same_full.
Qed.
Lemma Z_div_same : forall a, a > 0 -> a/a = 1.
Proof.
intros; apply Z_div_same_full; auto with zarith.
Qed.
Lemma Z_div_plus : forall a b c:Z, c > 0 -> (a + b * c) / c = a / c + b.
Proof.
intros; apply Z_div_plus_full; auto with zarith.
Qed.
Lemma Z_div_mult : forall a b:Z, b > 0 -> (a*b)/b = a.
Proof.
intros; apply Z_div_mult_full; auto with zarith.
Qed.
Lemma Z_mod_plus : forall a b c:Z, c > 0 -> (a + b * c) mod c = a mod c.
Proof.
intros; apply Z_mod_plus_full; auto with zarith.
Qed.
Lemma Z_div_exact_1 : forall a b:Z, b > 0 -> a = b*(a/b) -> a mod b = 0.
Proof.
intros; apply Z_div_exact_full_1; auto with zarith.
Qed.
Lemma Z_div_exact_2 : forall a b:Z, b > 0 -> a mod b = 0 -> a = b*(a/b).
Proof.
intros; apply Z_div_exact_full_2; auto with zarith.
Qed.
Lemma Z_mod_zero_opp : forall a b:Z, b > 0 -> a mod b = 0 -> (-a) mod b = 0.
Proof.
intros; apply Z_mod_zero_opp_full; auto with zarith.
Qed.
(** * A direct way to compute Zmod *)
Fixpoint Zmod_POS (a : positive) (b : Z) : Z :=
match a with
| xI a' =>
let r := Zmod_POS a' b in
let r' := (2 * r + 1) in
if Zgt_bool b r' then r' else (r' - b)
| xO a' =>
let r := Zmod_POS a' b in
let r' := (2 * r) in
if Zgt_bool b r' then r' else (r' - b)
| xH => if Zge_bool b 2 then 1 else 0
end.
Definition Zmod' a b :=
match a with
| Z0 => 0
| Zpos a' =>
match b with
| Z0 => 0
| Zpos _ => Zmod_POS a' b
| Zneg b' =>
let r := Zmod_POS a' (Zpos b') in
match r with Z0 => 0 | _ => b + r end
end
| Zneg a' =>
match b with
| Z0 => 0
| Zpos _ =>
let r := Zmod_POS a' b in
match r with Z0 => 0 | _ => b - r end
| Zneg b' => - (Zmod_POS a' (Zpos b'))
end
end.
Theorem Zmod_POS_correct: forall a b, Zmod_POS a b = (snd (Zdiv_eucl_POS a b)).
Proof.
intros a b; elim a; simpl; auto.
intros p Rec; rewrite Rec.
case (Zdiv_eucl_POS p b); intros z1 z2; simpl; auto.
match goal with |- context [Zgt_bool _ ?X] => case (Zgt_bool b X) end; auto.
intros p Rec; rewrite Rec.
case (Zdiv_eucl_POS p b); intros z1 z2; simpl; auto.
match goal with |- context [Zgt_bool _ ?X] => case (Zgt_bool b X) end; auto.
case (Zge_bool b 2); auto.
Qed.
Theorem Zmod'_correct: forall a b, Zmod' a b = Zmod a b.
Proof.
intros a b; unfold Zmod; case a; simpl; auto.
intros p; case b; simpl; auto.
intros p1; refine (Zmod_POS_correct _ _); auto.
intros p1; rewrite Zmod_POS_correct; auto.
case (Zdiv_eucl_POS p (Zpos p1)); simpl; intros z1 z2; case z2; auto.
intros p; case b; simpl; auto.
intros p1; rewrite Zmod_POS_correct; auto.
case (Zdiv_eucl_POS p (Zpos p1)); simpl; intros z1 z2; case z2; auto.
intros p1; rewrite Zmod_POS_correct; simpl; auto.
case (Zdiv_eucl_POS p (Zpos p1)); auto.
Qed.
(** Another convention is possible for division by negative numbers:
* quotient is always the biggest integer smaller than or equal to a/b
* remainder is hence always positive or null. *)
Theorem Zdiv_eucl_extended :
forall b:Z,
b <> 0 ->
forall a:Z,
{qr : Z * Z | let (q, r) := qr in a = b * q + r /\ 0 <= r < Zabs b}.
Proof.
intros b Hb a.
elim (Z_le_gt_dec 0 b); intro Hb'.
cut (b > 0); [ intro Hb'' | omega ].
rewrite Zabs_eq; [ apply Zdiv_eucl_exist; assumption | assumption ].
cut (- b > 0); [ intro Hb'' | omega ].
elim (Zdiv_eucl_exist Hb'' a); intros qr.
elim qr; intros q r Hqr.
exists (- q, r).
elim Hqr; intros.
split.
rewrite <- Zmult_opp_comm; assumption.
rewrite Zabs_non_eq; [ assumption | omega ].
Qed.
Implicit Arguments Zdiv_eucl_extended.
(** A third convention: Ocaml.
See files ZOdiv_def.v and ZOdiv.v.
Ocaml uses Round-Toward-Zero division: (-a)/b = a/(-b) = -(a/b).
Hence (-a) mod b = - (a mod b)
a mod (-b) = a mod b
And: |r| < |b| and sgn(r) = sgn(a) (notice the a here instead of b).
*)
|
//# 18 inputs
//# 1 outputs
//# 16 D-type flipflops
//# 78 inverters
//# 140 gates (49 ANDs + 29 NANDs + 28 ORs + 34 NORs)
module dff (CK,Q,D);
input CK,D;
output Q;
wire NM,NCK;
trireg NQ,M;
nmos N7 (M,D,NCK);
not P3 (NM,M);
nmos N9 (NQ,NM,CK);
not P5 (Q,NQ);
not P1 (NCK,CK);
endmodule
module s420(GND,VDD,CK,C_0,C_1,C_10,C_11,C_12,C_13,C_14,C_15,C_16,C_2,C_3,C_4,
C_5,C_6,C_7,C_8,C_9,P_0,Z);
input GND,VDD,CK,P_0,C_16,C_15,C_14,C_13,C_12,C_11,C_10,C_9,C_8,C_7,C_6,C_5,
C_4,C_3,C_2,C_1,C_0;
output Z;
wire X_4,I12,X_3,I13,X_2,I14,X_1,I15,X_8,I110,X_7,I111,X_6,I112,X_5,I113,
X_12,I208,X_11,I209,X_10,I210,X_9,I211,X_16,I306,X_15,I307,X_14,I308,X_13,
I309,I73_1,I69,I73_2,I7_1,I66,I7_2,I88_1,I88_2,I48,I49,I50,I68,I171_1,I167,
I171_2,I105_1,I164,I105_2,I186_1,I186_2,I1_2,I146,I147,I148,I166,I269_1,
I265,I269_2,I203_1,I262,I203_2,I284_1,I284_2,I1_3,I244,I245,I246,I264,
I301_1,I359,I301_2,I378_1,I378_2,I1_4,I344,I345,I357,I358,I360,I410,I411,
I412,I413,I414,I423,I422,I438,I439,I440,I441,I442,I451,I450,I466,I467,I468,
I469,I470,I479,I478,I494,I495,I496,I497,I498,I506,I505,I546,P_2,I547,P_3,
I550,I551,I570,P_6,I571,P_7,I574,I575,I594,P_10,I595,P_11,I598,I599,I618,
P_14,I619,P_15,I622,I623,I73_3,I73_4,I7_3,I7_4,I88_3,I88_4,I171_3,I171_4,
I105_3,I105_4,I186_3,I186_4,I269_3,I269_4,I203_3,I203_4,I284_3,I284_4,
I301_3,I301_4,I378_3,I378_4,I387_1,I2_1,I2_2,I2_3,I408_2,I407_1,I407_2,
I408_3,I407_3,P_5,I403_2,I404_2,I405_2,P_8,I406_2,P_9,I403_3,I404_3,I405_3,
P_12,I406_3,P_13,I403_4,I404_4,I405_4,P_16,I406_4,I559_1,P_1,I559_2,I583_1,
I583_2,P_4,I607_1,I607_2,I631_1,I631_2,I534_5,I70_1,I95_1,I64,I168_1,
I193_1,I162,I266_1,I291_1,I260,I363_1,I361,I366_1,I384_1,I555_1,I555_2,
I579_1,I579_2,I603_1,I603_2,I627_1,I627_2,I534_2,I533_1,I533_2,I534_3,
I533_3,I534_4,I533_4,I62,I160,I258,I355,I420,I448,I476,I503,I554,I578,I602,
I626;
dff DFF_0(CK,X_4,I12);
dff DFF_1(CK,X_3,I13);
dff DFF_2(CK,X_2,I14);
dff DFF_3(CK,X_1,I15);
dff DFF_4(CK,X_8,I110);
dff DFF_5(CK,X_7,I111);
dff DFF_6(CK,X_6,I112);
dff DFF_7(CK,X_5,I113);
dff DFF_8(CK,X_12,I208);
dff DFF_9(CK,X_11,I209);
dff DFF_10(CK,X_10,I210);
dff DFF_11(CK,X_9,I211);
dff DFF_12(CK,X_16,I306);
dff DFF_13(CK,X_15,I307);
dff DFF_14(CK,X_14,I308);
dff DFF_15(CK,X_13,I309);
not NOT_0(I73_1,I69);
not NOT_1(I73_2,X_3);
not NOT_2(I7_1,I66);
not NOT_3(I7_2,X_2);
not NOT_4(I88_1,X_1);
not NOT_5(I88_2,P_0);
not NOT_6(I48,P_0);
not NOT_7(I49,X_4);
not NOT_8(I50,X_3);
not NOT_9(I68,I69);
not NOT_10(I171_1,I167);
not NOT_11(I171_2,X_7);
not NOT_12(I105_1,I164);
not NOT_13(I105_2,X_6);
not NOT_14(I186_1,X_5);
not NOT_15(I186_2,I1_2);
not NOT_16(I146,I1_2);
not NOT_17(I147,X_8);
not NOT_18(I148,X_7);
not NOT_19(I166,I167);
not NOT_20(I269_1,I265);
not NOT_21(I269_2,X_11);
not NOT_22(I203_1,I262);
not NOT_23(I203_2,X_10);
not NOT_24(I284_1,X_9);
not NOT_25(I284_2,I1_3);
not NOT_26(I244,I1_3);
not NOT_27(I245,X_12);
not NOT_28(I246,X_11);
not NOT_29(I264,I265);
not NOT_30(I301_1,I359);
not NOT_31(I301_2,X_14);
not NOT_32(I378_1,X_13);
not NOT_33(I378_2,I1_4);
not NOT_34(I344,X_15);
not NOT_35(I345,X_14);
not NOT_36(I357,I358);
not NOT_37(I360,I359);
not NOT_38(I410,P_0);
not NOT_39(I411,X_1);
not NOT_40(I412,X_2);
not NOT_41(I413,X_3);
not NOT_42(I414,X_4);
not NOT_43(I423,I422);
not NOT_44(I438,P_0);
not NOT_45(I439,X_5);
not NOT_46(I440,X_6);
not NOT_47(I441,X_7);
not NOT_48(I442,X_8);
not NOT_49(I451,I450);
not NOT_50(I466,P_0);
not NOT_51(I467,X_9);
not NOT_52(I468,X_10);
not NOT_53(I469,X_11);
not NOT_54(I470,X_12);
not NOT_55(I479,I478);
not NOT_56(I494,P_0);
not NOT_57(I495,X_13);
not NOT_58(I496,X_14);
not NOT_59(I497,X_15);
not NOT_60(I498,X_16);
not NOT_61(I506,I505);
not NOT_62(I546,P_2);
not NOT_63(I547,P_3);
not NOT_64(I550,C_2);
not NOT_65(I551,C_3);
not NOT_66(I570,P_6);
not NOT_67(I571,P_7);
not NOT_68(I574,C_6);
not NOT_69(I575,C_7);
not NOT_70(I594,P_10);
not NOT_71(I595,P_11);
not NOT_72(I598,C_10);
not NOT_73(I599,C_11);
not NOT_74(I618,P_14);
not NOT_75(I619,P_15);
not NOT_76(I622,C_14);
not NOT_77(I623,C_15);
and AND2_0(I73_3,I69,I73_2);
and AND2_1(I73_4,X_3,I73_1);
and AND2_2(I7_3,I66,I7_2);
and AND2_3(I7_4,X_2,I7_1);
and AND2_4(I88_3,X_1,I88_2);
and AND2_5(I88_4,P_0,I88_1);
and AND2_6(I171_3,I167,I171_2);
and AND2_7(I171_4,X_7,I171_1);
and AND2_8(I105_3,I164,I105_2);
and AND2_9(I105_4,X_6,I105_1);
and AND2_10(I186_3,X_5,I186_2);
and AND2_11(I186_4,I1_2,I186_1);
and AND2_12(I269_3,I265,I269_2);
and AND2_13(I269_4,X_11,I269_1);
and AND2_14(I203_3,I262,I203_2);
and AND2_15(I203_4,X_10,I203_1);
and AND2_16(I284_3,X_9,I284_2);
and AND2_17(I284_4,I1_3,I284_1);
and AND2_18(I301_3,I359,I301_2);
and AND2_19(I301_4,X_14,I301_1);
and AND2_20(I378_3,X_13,I378_2);
and AND2_21(I378_4,I1_4,I378_1);
and AND2_22(I387_1,I360,X_14);
and AND2_23(I1_2,I2_1,P_0);
and AND2_24(I1_3,I2_2,I1_2);
and AND2_25(I1_4,I2_3,I1_3);
and AND2_26(I408_2,I407_1,I407_2);
and AND2_27(I408_3,I408_2,I407_3);
and AND2_28(P_5,I407_1,I403_2);
and AND2_29(P_6,I407_1,I404_2);
and AND2_30(P_7,I407_1,I405_2);
and AND2_31(P_8,I407_1,I406_2);
and AND2_32(P_9,I408_2,I403_3);
and AND2_33(P_10,I408_2,I404_3);
and AND2_34(P_11,I408_2,I405_3);
and AND2_35(P_12,I408_2,I406_3);
and AND2_36(P_13,I408_3,I403_4);
and AND2_37(P_14,I408_3,I404_4);
and AND2_38(P_15,I408_3,I405_4);
and AND2_39(P_16,I408_3,I406_4);
and AND2_40(I559_1,P_1,C_1);
and AND2_41(I559_2,P_0,C_0);
and AND2_42(I583_1,P_5,C_5);
and AND2_43(I583_2,P_4,C_4);
and AND2_44(I607_1,P_9,C_9);
and AND2_45(I607_2,P_8,C_8);
and AND2_46(I631_1,P_13,C_13);
and AND2_47(I631_2,P_12,C_12);
and AND2_48(I534_5,P_16,C_16);
or OR3_0(I70_1,I68,X_4,I50);
or OR2_0(I13,I73_3,I73_4);
or OR2_1(I15,I88_3,I88_4);
or OR3_1(I95_1,I64,I50,I48);
or OR3_2(I168_1,I166,X_8,I148);
or OR2_2(I111,I171_3,I171_4);
or OR2_3(I113,I186_3,I186_4);
or OR3_3(I193_1,I162,I148,I146);
or OR3_4(I266_1,I264,X_12,I246);
or OR2_4(I209,I269_3,I269_4);
or OR2_5(I211,I284_3,I284_4);
or OR3_5(I291_1,I260,I246,I244);
or OR3_6(I363_1,I361,X_16,I344);
or OR2_6(I366_1,I361,X_15);
or OR2_7(I309,I378_3,I378_4);
or OR3_7(I384_1,I359,I345,I344);
or OR2_8(I555_1,I547,I551);
or OR2_9(I555_2,I546,I550);
or OR2_10(I579_1,I571,I575);
or OR2_11(I579_2,I570,I574);
or OR2_12(I603_1,I595,I599);
or OR2_13(I603_2,I594,I598);
or OR2_14(I627_1,I619,I623);
or OR2_15(I627_2,I618,I622);
or OR2_16(I534_2,I533_1,I533_2);
or OR2_17(I534_3,I534_2,I533_3);
or OR2_18(I534_4,I534_3,I533_4);
or OR2_19(Z,I534_4,I534_5);
nand NAND2_0(I12,I70_1,I62);
nand NAND2_1(I62,I95_1,X_4);
nand NAND2_2(I64,X_1,X_2);
nand NAND2_3(I66,X_1,P_0);
nand NAND2_4(I110,I168_1,I160);
nand NAND2_5(I160,I193_1,X_8);
nand NAND2_6(I162,X_5,X_6);
nand NAND2_7(I164,X_5,I1_2);
nand NAND2_8(I208,I266_1,I258);
nand NAND2_9(I258,I291_1,X_12);
nand NAND2_10(I260,X_9,X_10);
nand NAND2_11(I262,X_9,I1_3);
nand NAND2_12(I306,I363_1,I355);
nand NAND2_13(I307,I366_1,I357);
nand NAND2_14(I355,I384_1,X_16);
nand NAND2_15(I359,X_13,I1_4);
nand NAND2_16(I361,I360,X_14);
nand NAND2_17(I420,I423,I412);
nand NAND2_18(I422,I411,P_0);
nand NAND2_19(I448,I451,I440);
nand NAND2_20(I450,I439,P_0);
nand NAND2_21(I476,I479,I468);
nand NAND2_22(I478,I467,P_0);
nand NAND2_23(I503,I506,I496);
nand NAND2_24(I505,I495,P_0);
nand NAND3_0(I533_1,I555_1,I555_2,I554);
nand NAND3_1(I533_2,I579_1,I579_2,I578);
nand NAND3_2(I533_3,I603_1,I603_2,I602);
nand NAND3_3(I533_4,I627_1,I627_2,I626);
nor NOR2_0(I14,I7_3,I7_4);
nor NOR3_0(I2_1,I64,I49,I50);
nor NOR2_1(I69,I64,I48);
nor NOR2_2(I112,I105_3,I105_4);
nor NOR3_1(I2_2,I162,I147,I148);
nor NOR2_3(I167,I162,I146);
nor NOR2_4(I210,I203_3,I203_4);
nor NOR3_2(I2_3,I260,I245,I246);
nor NOR2_5(I265,I260,I244);
nor NOR2_6(I308,I301_3,I301_4);
nor NOR2_7(I358,I344,I387_1);
nor NOR2_8(P_1,I410,I411);
nor NOR2_9(P_2,I412,I422);
nor NOR2_10(P_3,I413,I420);
nor NOR3_3(P_4,X_3,I420,I414);
nor NOR4_0(I407_1,X_4,X_2,X_3,X_1);
nor NOR2_11(I403_2,I438,I439);
nor NOR2_12(I404_2,I440,I450);
nor NOR2_13(I405_2,I441,I448);
nor NOR3_4(I406_2,X_7,I448,I442);
nor NOR4_1(I407_2,X_8,X_6,X_7,X_5);
nor NOR2_14(I403_3,I466,I467);
nor NOR2_15(I404_3,I468,I478);
nor NOR2_16(I405_3,I469,I476);
nor NOR3_5(I406_3,X_11,I476,I470);
nor NOR4_2(I407_3,X_12,X_10,X_11,X_9);
nor NOR2_17(I403_4,I494,I495);
nor NOR2_18(I404_4,I496,I505);
nor NOR2_19(I405_4,I497,I503);
nor NOR3_6(I406_4,X_15,I503,I498);
nor NOR2_20(I554,I559_1,I559_2);
nor NOR2_21(I578,I583_1,I583_2);
nor NOR2_22(I602,I607_1,I607_2);
nor NOR2_23(I626,I631_1,I631_2);
endmodule
|
// bsg_mesosync_link devides the chip's clock to a slower clock for IO
// based on the configuration it receives. In the input side, for each
// input data line it can choose between the clock edge and which cycle
// in the divided clock to take the sameple, based on the bit_cfg configuration.
//
// To find out the proper values for bit configuration, it has a logic
// analzers which would sample input singal on both positive and negative
// edges of the clock. Master chooses a line at a time and sends known
// patterns to it and reads the logic analyzer's data to find out the delays
// of each line and find the proper line configurations.
// bsg_mesosync_input provides logic_analyzer data to be used in the
// bsg_mesosync_output module to send out these read values.
//
// There is no handshake protocl on the pin side, but from channel to core
// there is valid-only handshake to tell the FIFO which data is valid to be
// used. Moreover, it has a fifo-relay for both data and logic-analyzer data,
// so it can be connected to modules in distance on a chip.
//
//`ifndef DEFINITIONS_V
//`include "definitions.v"
//`endif
`include "bsg_defines.v"
module bsg_mesosync_input
#( parameter `BSG_INV_PARAM(cfg_tag_base_id_p )
, parameter `BSG_INV_PARAM(ch1_width_p )
, parameter `BSG_INV_PARAM(ch2_width_p )
, parameter `BSG_INV_PARAM(LA_els_p )
, parameter width_lp = ch1_width_p + ch2_width_p
)
( input clk
, input reset
, input config_s config_i
// Sinals with their acknowledge
, input [width_lp-1:0] pins_i
, output logic [width_lp-1:0] data_o
, output logic valid_o
// Logic analyzer signals for mesosync_output module
, output LA_data_o
, output LA_valid_o
, input ready_to_LA_i
);
//------------------------------------------------
//------------ CONFIG TAG NODEs ------------------
//------------------------------------------------
// Configuratons
logic [1:0] cfg_reset, cfg_reset_r;
logic channel_reset;
logic enable;
logic loopback_en; // not used
logic [maxDivisionWidth_p-1:0] input_clk_divider;
bit_cfg_s [width_lp-1:0] bit_cfg;
mode_cfg_s mode_cfg;
logic [`BSG_SAFE_CLOG2(width_lp)-1:0] la_input_bit_selector;
logic output_mode_is_LA;
// Calcuating data width of each configuration node
// reset (2 bits), clock divider for input digital clock, logic analyzer line selector
localparam input_node_data_width_p = 2 + maxDivisionWidth_p
+ `BSG_SAFE_CLOG2(width_lp);
// reset (2 bits), clock divider for output digital clock,
// logic analyzer data and valid line selector
localparam common_node_data_width_p = $bits(mode_cfg) + 1 + 1;
// bit configurations for input
localparam ch1_bit_cfg_node_data_width_p = $bits(bit_cfg[ch1_width_p-1:0]);
localparam ch2_bit_cfg_node_data_width_p = $bits(bit_cfg[width_lp-1:ch1_width_p]);
// relay nodes
config_s [1:0] relay_out;
relay_node input_relay_1(.config_i(config_i),
.config_o(relay_out[0]));
relay_node input_relay_2(.config_i(config_i),
.config_o(relay_out[1]));
assign output_mode_is_LA = (mode_cfg.output_mode == LA);
// Config nodes
config_node#(.id_p(cfg_tag_base_id_p)
,.data_bits_p(common_node_data_width_p)
,.default_p('d0)
) common_node
(.clk(clk)
,.reset(reset)
,.config_i(relay_out[0])
,.data_o({mode_cfg,enable,loopback_en})
);
config_node#(.id_p(cfg_tag_base_id_p+1)
,.data_bits_p(input_node_data_width_p)
,.default_p('d0)
) input_node
(.clk(clk)
,.reset(reset)
,.config_i(relay_out[0])
,.data_o({cfg_reset,input_clk_divider,la_input_bit_selector})
);
config_node#(.id_p(cfg_tag_base_id_p+3)
,.data_bits_p(ch1_bit_cfg_node_data_width_p)
,.default_p('d0)
) ch1_bit_cfg_node
(.clk(clk)
,.reset(reset)
,.config_i(relay_out[1])
,.data_o(bit_cfg[ch1_width_p-1:0])
);
config_node#(.id_p(cfg_tag_base_id_p+4)
,.data_bits_p(ch2_bit_cfg_node_data_width_p)
,.default_p('d0)
) ch2_bit_cfg_node
(.clk(clk)
,.reset(reset)
,.config_i(relay_out[1])
,.data_o(bit_cfg[width_lp-1:ch1_width_p])
);
//------------------------------------------------
//--------------- RESET LOGIC --------------------
//------------------------------------------------
always_ff @(posedge clk)
cfg_reset_r <= cfg_reset;
// reset is kept high until it is reset by the cfg node
// by changing reset value from 2'b01 to 2'b10, then
// it would remain low (unless another value is recieved)
always_ff @(posedge clk)
if ((cfg_reset == 2'b10) &
((cfg_reset_r == 2'b01)|(channel_reset == 1'b0)))
channel_reset <= 1'b0;
else
channel_reset <= 1'b1;
// Using a relay_fifo for enabling sending data through long distances in chip
logic [width_lp-1:0] data_o_r;
logic valid_o_r;
//------------------------------------------------
//---------------- OUTPUT RELAY ------------------
//------------------------------------------------
// For connecting to far parts on the die, we need to
// put a register before output
always_ff @ (posedge clk)
if (channel_reset) begin
valid_o <= 0;
data_o <= 0;
end else begin
valid_o <= valid_o_r;
data_o <= data_o_r;
end
//------------------------------------------------
//------------- CLOCK DIVIDER --------------------
//------------------------------------------------
logic [maxDivisionWidth_p-1:0] input_counter_r;
// clk is divided by the configured clk_divider_i plus one. So 0
// means no clk division and 15 means clk division by factor of 16.
bsg_counter_dynamic_limit #(.width_p(maxDivisionWidth_p)) input_counter
( .clk_i(clk)
, .reset_i(channel_reset)
, .limit_i(input_clk_divider)
, .counter_o(input_counter_r)
);
//------------------------------------------------
//------------- INPUT SAMPLER --------------------
//------------------------------------------------
// Sampling on both edges of the clock for all input bits
// and also providing stabled version of them using synchronizers
logic [width_lp-1:0] posedge_value, negedge_value,
posedge_synchronized, negedge_synchronized;
bsg_ddr_sampler #(.width_p(width_lp)) ddr_sampler
( .clk(clk)
, .reset(channel_reset)
, .to_be_sampled_i(pins_i)
, .pos_edge_value_o(posedge_value)
, .neg_edge_value_o(negedge_value)
, .pos_edge_synchronized_o(posedge_synchronized)
, .neg_edge_synchronized_o(negedge_synchronized)
);
//------------------------------------------------
//------------- INPUT MODULE ---------------------
//------------------------------------------------
// in normal mode, for each bit a clock edge and a clk cycle based on
// required phase delay is selected, and this data is latched
integer i1,i2,i3,i4;
logic [width_lp-1:0] sampled_r;
logic [width_lp-1:0] phase_match;
logic [width_lp-1:0] selected_edge;
// Select the edge to take sample
always_comb
for (i1 = 0; i1 < width_lp; i1 = i1 + 1)
if (bit_cfg[i1].clk_edge_selector)
selected_edge[i1] = posedge_value[i1];
else
selected_edge[i1] = negedge_value[i1];
// Signal which declares phase match,
// that would be 1 only once in each input period
always_comb
for (i2 = 0; i2 < width_lp; i2 = i2 + 1)
if (input_counter_r == bit_cfg[i2].phase)
phase_match[i2] = 1'b1;
else
phase_match[i2] = 1'b0;
// Latching the value of line on the phase match cycle
// to be used in rest of the input period
always_ff @ (posedge clk)
if (channel_reset)
sampled_r <= 0;
else if (mode_cfg.input_mode == NORMAL)
for (i3 = 0; i3 < width_lp; i3 = i3 + 1)
if (phase_match[i3])
sampled_r[i3] <= selected_edge[i3];
// When each line reaches its phase based on the input clk counter,
// its valid register would be set to 1, and it emains 1 until the
// yumi signal becomes 1, which means the data were send out. It remains
// zero until it reaches desired phase again. In case of clk divider of
// 0, which means no division, valid bit would always be one, since counter
// is always zero and all the phases must be zero.
logic [width_lp-1:0] valid_n,valid_r;
logic yumi_n,yumi_r;
// valid_n becomes 1 in case of phase match, otherwise it keeps valid_r
// value unless it recives the registered yumi signal,
// so it becomes zero the cycle after data is valid
assign valid_n = {width_lp{~channel_reset & (mode_cfg.input_mode == NORMAL)}}
& ((valid_r & ~{width_lp{yumi_r}}) | phase_match);
// Registering values
always_ff @ (posedge clk)
if (channel_reset) begin
valid_r <= 0;
yumi_r <= 0;
end
else begin
valid_r <= valid_n;
yumi_r <= yumi_n;
end
// bypassing register for the line(s) with latest phase
// Afterwards the registered values would be used
always_comb
for (i4 = 0; i4 < width_lp; i4 = i4 + 1)
if (phase_match[i4] & yumi_n)
data_o_r[i4] = selected_edge[i4];
else
data_o_r[i4] = sampled_r[i4];
// when all the bits are valid, it means the data is ready
// yumi_r is sent back to each bit, so from next cycle valid bits
// become zero and yumi_n goes to zero as well.
assign yumi_n = &valid_n;
assign valid_o_r = yumi_n & enable;
//------------------------------------------------
//------------- LOGIC ANAYZER --------------------
//------------------------------------------------
// Using a bsg_relay_fifo to abosrb any latency on the line
logic LA_valid, ready_to_LA, LA_data;
bsg_relay_fifo #(.width_p(1)) LA_relay
(.clk_i(clk)
,.reset_i(channel_reset)
,.ready_o(ready_to_LA)
,.data_i(LA_data)
,.v_i(LA_valid)
,.v_o(LA_valid_o)
,.data_o(LA_data_o)
,.ready_i(ready_to_LA_i)
);
// Logic Analyzer signals
logic LA_trigger, LA_deque, delayed_input_clk_edge;
// When logic analyzer is configured to sample, it has to start sampling
// from the sample that correspinds to time when input_clock_counter is zero,
// beginning of IO clock.
assign LA_trigger = (mode_cfg.input_mode == LA_STOP) & mode_cfg.LA_enque
& delayed_input_clk_edge;
// Synchronizer in ddr module that gives the input to logic anlzer has 2 cycle
// delay and input_clk_counter is comapred with value 2 to get the actual edge.
// If input_clk_divider is 0 every edge is correct, and if input_clk_divider is 1,
// when input_counter_r is zero is the actual edge.
assign delayed_input_clk_edge = (input_clk_divider<maxDivisionWidth_p'(2)) ?
(input_counter_r == maxDivisionWidth_p'(0)) :
(input_counter_r == maxDivisionWidth_p'(2)) ;
// when data is ready to send from Logic Analyzer FIFO to output, fifo will
// be dequed until it gets empty.
// Due to output_ready signal which is reset dependent, this singal does not
// assert during reset.
assign LA_deque = ready_to_LA & LA_valid;
// Due to fifo_relays in both mesosync_input and mesosync_output, we need
// 2 less elements in logic analyzer's fifo (each fifo_relay keeps 2 one bit
// values, hence we would get 2 two bit fifos in totall).
bsg_logic_analyzer #( .line_width_p(width_lp)
, .LA_els_p(LA_els_p)
) logic_analyzer
( .clk(clk)
, .reset(channel_reset)
, .valid_en_i(output_mode_is_LA)
, .posedge_value_i(posedge_synchronized)
, .negedge_value_i(negedge_synchronized)
, .input_bit_selector_i(la_input_bit_selector)
, .start_i(LA_trigger)
, .ready_o()
, .logic_analyzer_data_o(LA_data)
, .v_o(LA_valid)
, .deque_i(LA_deque)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_mesosync_input)
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb 3 15:07:20 EST 2014
//
//
// Ports:
// Name I/O size props
// wci_s_SResp O 2 reg
// wci_s_SData O 32 reg
// wci_s_SThreadBusy O 1
// wci_s_SFlag O 2
// wti_s_SThreadBusy O 1 reg
// wti_s_SReset_n O 1
// wmiS0_SResp O 2 reg
// wmiS0_SData O 128 reg
// wmiS0_SThreadBusy O 1
// wmiS0_SDataThreadBusy O 1
// wmiS0_SRespLast O 1 const
// wmiS0_SFlag O 32 reg
// wmiS0_SReset_n O 1
// RDY_server_request_put O 1
// server_response_get O 153
// RDY_server_response_get O 1
// pciDevice I 16
// CLK I 1 clock
// RST_N I 1 reset
// wci_s_MCmd I 3
// wci_s_MAddrSpace I 1
// wci_s_MByteEn I 4
// wci_s_MAddr I 32
// wci_s_MData I 32
// wci_s_MFlag I 2 unused
// wti_s_req I 67 reg
// wmiS0_MCmd I 3
// wmiS0_MReqInfo I 1
// wmiS0_MAddrSpace I 1
// wmiS0_MAddr I 14
// wmiS0_MBurstLength I 12
// wmiS0_MData I 128
// wmiS0_MDataByteEn I 16
// wmiS0_arg_mFlag I 32 reg
// server_request_put I 153
// wmiS0_MReqLast I 1
// wmiS0_MDataValid I 1
// wmiS0_MDataLast I 1
// wmiS0_MReset_n I 1 reg
// EN_server_request_put I 1
// EN_server_response_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkOCDP16B(pciDevice,
CLK,
RST_N,
wci_s_MCmd,
wci_s_MAddrSpace,
wci_s_MByteEn,
wci_s_MAddr,
wci_s_MData,
wci_s_SResp,
wci_s_SData,
wci_s_SThreadBusy,
wci_s_SFlag,
wci_s_MFlag,
wti_s_req,
wti_s_SThreadBusy,
wti_s_SReset_n,
wmiS0_MCmd,
wmiS0_MReqLast,
wmiS0_MReqInfo,
wmiS0_MAddrSpace,
wmiS0_MAddr,
wmiS0_MBurstLength,
wmiS0_MDataValid,
wmiS0_MDataLast,
wmiS0_MData,
wmiS0_MDataByteEn,
wmiS0_SResp,
wmiS0_SData,
wmiS0_SThreadBusy,
wmiS0_SDataThreadBusy,
wmiS0_SRespLast,
wmiS0_SFlag,
wmiS0_arg_mFlag,
wmiS0_SReset_n,
wmiS0_MReset_n,
server_request_put,
EN_server_request_put,
RDY_server_request_put,
EN_server_response_get,
server_response_get,
RDY_server_response_get);
parameter [0 : 0] hasPush = 1'b0;
parameter [0 : 0] hasPull = 1'b0;
parameter [0 : 0] hasDebugLogic = 1'b0;
input [15 : 0] pciDevice;
input CLK;
input RST_N;
// action method wci_s_mCmd
input [2 : 0] wci_s_MCmd;
// action method wci_s_mAddrSpace
input wci_s_MAddrSpace;
// action method wci_s_mByteEn
input [3 : 0] wci_s_MByteEn;
// action method wci_s_mAddr
input [31 : 0] wci_s_MAddr;
// action method wci_s_mData
input [31 : 0] wci_s_MData;
// value method wci_s_sResp
output [1 : 0] wci_s_SResp;
// value method wci_s_sData
output [31 : 0] wci_s_SData;
// value method wci_s_sThreadBusy
output wci_s_SThreadBusy;
// value method wci_s_sFlag
output [1 : 0] wci_s_SFlag;
// action method wci_s_mFlag
input [1 : 0] wci_s_MFlag;
// action method wti_s_put
input [66 : 0] wti_s_req;
// value method wti_s_sThreadBusy
output wti_s_SThreadBusy;
// value method wti_s_sReset_n
output wti_s_SReset_n;
// action method wmiS0_mCmd
input [2 : 0] wmiS0_MCmd;
// action method wmiS0_mReqLast
input wmiS0_MReqLast;
// action method wmiS0_mReqInfo
input wmiS0_MReqInfo;
// action method wmiS0_mAddrSpace
input wmiS0_MAddrSpace;
// action method wmiS0_mAddr
input [13 : 0] wmiS0_MAddr;
// action method wmiS0_mBurstLength
input [11 : 0] wmiS0_MBurstLength;
// action method wmiS0_mDataValid
input wmiS0_MDataValid;
// action method wmiS0_mDataLast
input wmiS0_MDataLast;
// action method wmiS0_mData
input [127 : 0] wmiS0_MData;
// action method wmiS0_mDataInfo
// action method wmiS0_mDataByteEn
input [15 : 0] wmiS0_MDataByteEn;
// value method wmiS0_sResp
output [1 : 0] wmiS0_SResp;
// value method wmiS0_sData
output [127 : 0] wmiS0_SData;
// value method wmiS0_sThreadBusy
output wmiS0_SThreadBusy;
// value method wmiS0_sDataThreadBusy
output wmiS0_SDataThreadBusy;
// value method wmiS0_sRespLast
output wmiS0_SRespLast;
// value method wmiS0_sFlag
output [31 : 0] wmiS0_SFlag;
// action method wmiS0_mFlag
input [31 : 0] wmiS0_arg_mFlag;
// value method wmiS0_sReset_n
output wmiS0_SReset_n;
// action method wmiS0_mReset_n
input wmiS0_MReset_n;
// action method server_request_put
input [152 : 0] server_request_put;
input EN_server_request_put;
output RDY_server_request_put;
// actionvalue method server_response_get
input EN_server_response_get;
output [152 : 0] server_response_get;
output RDY_server_response_get;
// signals for module outputs
wire [152 : 0] server_response_get;
wire [127 : 0] wmiS0_SData;
wire [31 : 0] wci_s_SData, wmiS0_SFlag;
wire [1 : 0] wci_s_SFlag, wci_s_SResp, wmiS0_SResp;
wire RDY_server_request_put,
RDY_server_response_get,
wci_s_SThreadBusy,
wmiS0_SDataThreadBusy,
wmiS0_SReset_n,
wmiS0_SRespLast,
wmiS0_SThreadBusy,
wti_s_SReset_n,
wti_s_SThreadBusy;
// inlined wires
wire [145 : 0] wmi_wmi_wmiDh_wget;
wire [129 : 0] wmi_wmi_respF_x_wire_wget;
wire [127 : 0] wmi_Es_mData_w_wget;
wire [71 : 0] wci_wciReq_wget;
wire [66 : 0] wti_wtiReq_wget;
wire [63 : 0] tlp_nowW_wget, wmi_nowW_wget;
wire [33 : 0] wci_respF_x_wire_wget;
wire [31 : 0] bram_0_serverAdapterA_outData_enqData_wget,
bram_0_serverAdapterA_outData_outData_wget,
bram_0_serverAdapterB_outData_enqData_wget,
bram_0_serverAdapterB_outData_outData_wget,
bram_1_serverAdapterA_outData_enqData_wget,
bram_1_serverAdapterA_outData_outData_wget,
bram_1_serverAdapterB_outData_enqData_wget,
bram_1_serverAdapterB_outData_outData_wget,
bram_2_serverAdapterA_outData_enqData_wget,
bram_2_serverAdapterA_outData_outData_wget,
bram_2_serverAdapterB_outData_enqData_wget,
bram_2_serverAdapterB_outData_outData_wget,
bram_3_serverAdapterA_outData_enqData_wget,
bram_3_serverAdapterA_outData_outData_wget,
bram_3_serverAdapterB_outData_enqData_wget,
bram_3_serverAdapterB_outData_outData_wget,
wci_Es_mAddr_w_wget,
wci_Es_mData_w_wget,
wmi_wmi_wmiMFlag_wget,
wmi_wmi_wmiReq_wget;
wire [15 : 0] bml_crdBuf_modulus_bw_wget,
bml_fabBuf_modulus_bw_wget,
bml_lclBuf_modulus_bw_wget,
bml_remBuf_modulus_bw_wget,
wmi_Es_mDataByteEn_w_wget;
wire [13 : 0] wmi_Es_mAddr_w_wget;
wire [11 : 0] wmi_Es_mBurstLength_w_wget;
wire [7 : 0] bml_dpControl_wget, tlp_dpControl_wget, wmi_dpControl_wget;
wire [3 : 0] wci_Es_mByteEn_w_wget;
wire [2 : 0] bram_0_serverAdapterA_cnt_1_wget,
bram_0_serverAdapterA_cnt_2_wget,
bram_0_serverAdapterA_cnt_3_wget,
bram_0_serverAdapterB_cnt_1_wget,
bram_0_serverAdapterB_cnt_2_wget,
bram_0_serverAdapterB_cnt_3_wget,
bram_1_serverAdapterA_cnt_1_wget,
bram_1_serverAdapterA_cnt_2_wget,
bram_1_serverAdapterA_cnt_3_wget,
bram_1_serverAdapterB_cnt_1_wget,
bram_1_serverAdapterB_cnt_2_wget,
bram_1_serverAdapterB_cnt_3_wget,
bram_2_serverAdapterA_cnt_1_wget,
bram_2_serverAdapterA_cnt_2_wget,
bram_2_serverAdapterA_cnt_3_wget,
bram_2_serverAdapterB_cnt_1_wget,
bram_2_serverAdapterB_cnt_2_wget,
bram_2_serverAdapterB_cnt_3_wget,
bram_3_serverAdapterA_cnt_1_wget,
bram_3_serverAdapterA_cnt_2_wget,
bram_3_serverAdapterA_cnt_3_wget,
bram_3_serverAdapterB_cnt_1_wget,
bram_3_serverAdapterB_cnt_2_wget,
bram_3_serverAdapterB_cnt_3_wget,
wci_Es_mCmd_w_wget,
wci_wEdge_wget,
wmi_Es_mCmd_w_wget;
wire [1 : 0] bram_0_serverAdapterA_s1_1_wget,
bram_0_serverAdapterA_writeWithResp_wget,
bram_0_serverAdapterB_s1_1_wget,
bram_0_serverAdapterB_writeWithResp_wget,
bram_1_serverAdapterA_s1_1_wget,
bram_1_serverAdapterA_writeWithResp_wget,
bram_1_serverAdapterB_s1_1_wget,
bram_1_serverAdapterB_writeWithResp_wget,
bram_2_serverAdapterA_s1_1_wget,
bram_2_serverAdapterA_writeWithResp_wget,
bram_2_serverAdapterB_s1_1_wget,
bram_2_serverAdapterB_writeWithResp_wget,
bram_3_serverAdapterA_s1_1_wget,
bram_3_serverAdapterA_writeWithResp_wget,
bram_3_serverAdapterB_s1_1_wget,
bram_3_serverAdapterB_writeWithResp_wget;
wire bml_crdBuf_decAction_whas,
bml_crdBuf_incAction_whas,
bml_datumAReg_1_wget,
bml_datumAReg_1_whas,
bml_dpControl_whas,
bml_fabAvail_1_wget,
bml_fabAvail_1_whas,
bml_fabBuf_decAction_whas,
bml_fabBuf_incAction_whas,
bml_fabDone_1_wget,
bml_fabDone_1_whas,
bml_lclBufDone_1_wget,
bml_lclBufDone_1_whas,
bml_lclBufStart_1_wget,
bml_lclBufStart_1_whas,
bml_lclBuf_decAction_whas,
bml_lclBuf_incAction_whas,
bml_remBuf_decAction_whas,
bml_remBuf_incAction_whas,
bml_remDone_1_wget,
bml_remDone_1_whas,
bml_remStart_1_wget,
bml_remStart_1_whas,
bram_0_serverAdapterA_cnt_1_whas,
bram_0_serverAdapterA_cnt_2_whas,
bram_0_serverAdapterA_cnt_3_whas,
bram_0_serverAdapterA_outData_deqCalled_whas,
bram_0_serverAdapterA_outData_enqData_whas,
bram_0_serverAdapterA_outData_outData_whas,
bram_0_serverAdapterA_s1_1_whas,
bram_0_serverAdapterA_writeWithResp_whas,
bram_0_serverAdapterB_cnt_1_whas,
bram_0_serverAdapterB_cnt_2_whas,
bram_0_serverAdapterB_cnt_3_whas,
bram_0_serverAdapterB_outData_deqCalled_whas,
bram_0_serverAdapterB_outData_enqData_whas,
bram_0_serverAdapterB_outData_outData_whas,
bram_0_serverAdapterB_s1_1_whas,
bram_0_serverAdapterB_writeWithResp_whas,
bram_1_serverAdapterA_cnt_1_whas,
bram_1_serverAdapterA_cnt_2_whas,
bram_1_serverAdapterA_cnt_3_whas,
bram_1_serverAdapterA_outData_deqCalled_whas,
bram_1_serverAdapterA_outData_enqData_whas,
bram_1_serverAdapterA_outData_outData_whas,
bram_1_serverAdapterA_s1_1_whas,
bram_1_serverAdapterA_writeWithResp_whas,
bram_1_serverAdapterB_cnt_1_whas,
bram_1_serverAdapterB_cnt_2_whas,
bram_1_serverAdapterB_cnt_3_whas,
bram_1_serverAdapterB_outData_deqCalled_whas,
bram_1_serverAdapterB_outData_enqData_whas,
bram_1_serverAdapterB_outData_outData_whas,
bram_1_serverAdapterB_s1_1_whas,
bram_1_serverAdapterB_writeWithResp_whas,
bram_2_serverAdapterA_cnt_1_whas,
bram_2_serverAdapterA_cnt_2_whas,
bram_2_serverAdapterA_cnt_3_whas,
bram_2_serverAdapterA_outData_deqCalled_whas,
bram_2_serverAdapterA_outData_enqData_whas,
bram_2_serverAdapterA_outData_outData_whas,
bram_2_serverAdapterA_s1_1_whas,
bram_2_serverAdapterA_writeWithResp_whas,
bram_2_serverAdapterB_cnt_1_whas,
bram_2_serverAdapterB_cnt_2_whas,
bram_2_serverAdapterB_cnt_3_whas,
bram_2_serverAdapterB_outData_deqCalled_whas,
bram_2_serverAdapterB_outData_enqData_whas,
bram_2_serverAdapterB_outData_outData_whas,
bram_2_serverAdapterB_s1_1_whas,
bram_2_serverAdapterB_writeWithResp_whas,
bram_3_serverAdapterA_cnt_1_whas,
bram_3_serverAdapterA_cnt_2_whas,
bram_3_serverAdapterA_cnt_3_whas,
bram_3_serverAdapterA_outData_deqCalled_whas,
bram_3_serverAdapterA_outData_enqData_whas,
bram_3_serverAdapterA_outData_outData_whas,
bram_3_serverAdapterA_s1_1_whas,
bram_3_serverAdapterA_writeWithResp_whas,
bram_3_serverAdapterB_cnt_1_whas,
bram_3_serverAdapterB_cnt_2_whas,
bram_3_serverAdapterB_cnt_3_whas,
bram_3_serverAdapterB_outData_deqCalled_whas,
bram_3_serverAdapterB_outData_enqData_whas,
bram_3_serverAdapterB_outData_outData_whas,
bram_3_serverAdapterB_s1_1_whas,
bram_3_serverAdapterB_writeWithResp_whas,
tlp_creditReady_1_wget,
tlp_creditReady_1_whas,
tlp_dmaDoneMark_1_wget,
tlp_dmaDoneMark_1_whas,
tlp_dmaStartMark_1_wget,
tlp_dmaStartMark_1_whas,
tlp_dpControl_whas,
tlp_farBufReady_1_wget,
tlp_farBufReady_1_whas,
tlp_nearBufReady_1_wget,
tlp_nearBufReady_1_whas,
tlp_nowW_whas,
tlp_pullTagMatch_1_wget,
tlp_pullTagMatch_1_whas,
tlp_remDone_1_wget,
tlp_remDone_1_whas,
tlp_remStart_1_wget,
tlp_remStart_1_whas,
wci_Es_mAddrSpace_w_wget,
wci_Es_mAddrSpace_w_whas,
wci_Es_mAddr_w_whas,
wci_Es_mByteEn_w_whas,
wci_Es_mCmd_w_whas,
wci_Es_mData_w_whas,
wci_ctlAckReg_1_wget,
wci_ctlAckReg_1_whas,
wci_reqF_r_clr_whas,
wci_reqF_r_deq_whas,
wci_reqF_r_enq_whas,
wci_respF_dequeueing_whas,
wci_respF_enqueueing_whas,
wci_respF_x_wire_whas,
wci_sFlagReg_1_wget,
wci_sFlagReg_1_whas,
wci_sThreadBusy_pw_whas,
wci_wEdge_whas,
wci_wciReq_whas,
wci_wci_cfrd_pw_whas,
wci_wci_cfwr_pw_whas,
wci_wci_ctrl_pw_whas,
wmi_Es_mAddrSpace_w_wget,
wmi_Es_mAddrSpace_w_whas,
wmi_Es_mAddr_w_whas,
wmi_Es_mBurstLength_w_whas,
wmi_Es_mCmd_w_whas,
wmi_Es_mDataByteEn_w_whas,
wmi_Es_mDataInfo_w_whas,
wmi_Es_mDataLast_w_whas,
wmi_Es_mDataValid_w_whas,
wmi_Es_mData_w_whas,
wmi_Es_mReqInfo_w_wget,
wmi_Es_mReqInfo_w_whas,
wmi_Es_mReqLast_w_whas,
wmi_dpControl_whas,
wmi_mesgBufReady_1_wget,
wmi_mesgBufReady_1_whas,
wmi_mesgDone_1_wget,
wmi_mesgDone_1_whas,
wmi_mesgStart_1_wget,
wmi_mesgStart_1_whas,
wmi_nowW_whas,
wmi_wmi_dhF_doResetClr_whas,
wmi_wmi_dhF_doResetDeq_whas,
wmi_wmi_dhF_doResetEnq_whas,
wmi_wmi_dhF_r_clr_whas,
wmi_wmi_dhF_r_deq_whas,
wmi_wmi_dhF_r_enq_whas,
wmi_wmi_forceSThreadBusy_pw_whas,
wmi_wmi_mFlagF_doResetClr_whas,
wmi_wmi_mFlagF_doResetDeq_whas,
wmi_wmi_mFlagF_doResetEnq_whas,
wmi_wmi_mFlagF_r_clr_whas,
wmi_wmi_mFlagF_r_deq_whas,
wmi_wmi_mFlagF_r_enq_whas,
wmi_wmi_operateD_1_wget,
wmi_wmi_operateD_1_whas,
wmi_wmi_peerIsReady_1_wget,
wmi_wmi_peerIsReady_1_whas,
wmi_wmi_reqF_doResetClr_whas,
wmi_wmi_reqF_doResetDeq_whas,
wmi_wmi_reqF_doResetEnq_whas,
wmi_wmi_reqF_r_clr_whas,
wmi_wmi_reqF_r_deq_whas,
wmi_wmi_reqF_r_enq_whas,
wmi_wmi_respF_dequeueing_whas,
wmi_wmi_respF_enqueueing_whas,
wmi_wmi_respF_x_wire_whas,
wmi_wmi_sDataThreadBusy_dw_wget,
wmi_wmi_sDataThreadBusy_dw_whas,
wmi_wmi_sThreadBusy_dw_wget,
wmi_wmi_sThreadBusy_dw_whas,
wmi_wmi_wmiDh_whas,
wmi_wmi_wmiMFlag_whas,
wmi_wmi_wmiReq_whas,
wti_operateD_1_wget,
wti_operateD_1_whas,
wti_wtiReq_whas;
// register bml_crdBuf_modulus
reg [15 : 0] bml_crdBuf_modulus;
wire [15 : 0] bml_crdBuf_modulus_D_IN;
wire bml_crdBuf_modulus_EN;
// register bml_crdBuf_value
reg [15 : 0] bml_crdBuf_value;
wire [15 : 0] bml_crdBuf_value_D_IN;
wire bml_crdBuf_value_EN;
// register bml_datumAReg
reg bml_datumAReg;
wire bml_datumAReg_D_IN, bml_datumAReg_EN;
// register bml_fabAvail
reg bml_fabAvail;
wire bml_fabAvail_D_IN, bml_fabAvail_EN;
// register bml_fabBuf_modulus
reg [15 : 0] bml_fabBuf_modulus;
wire [15 : 0] bml_fabBuf_modulus_D_IN;
wire bml_fabBuf_modulus_EN;
// register bml_fabBuf_value
reg [15 : 0] bml_fabBuf_value;
wire [15 : 0] bml_fabBuf_value_D_IN;
wire bml_fabBuf_value_EN;
// register bml_fabBufsAvail
reg [15 : 0] bml_fabBufsAvail;
wire [15 : 0] bml_fabBufsAvail_D_IN;
wire bml_fabBufsAvail_EN;
// register bml_fabDone
reg bml_fabDone;
wire bml_fabDone_D_IN, bml_fabDone_EN;
// register bml_fabFlowAddr
reg [31 : 0] bml_fabFlowAddr;
reg [31 : 0] bml_fabFlowAddr_D_IN;
wire bml_fabFlowAddr_EN;
// register bml_fabFlowBase
reg [31 : 0] bml_fabFlowBase;
wire [31 : 0] bml_fabFlowBase_D_IN;
wire bml_fabFlowBase_EN;
// register bml_fabFlowBaseMS
reg [31 : 0] bml_fabFlowBaseMS;
wire [31 : 0] bml_fabFlowBaseMS_D_IN;
wire bml_fabFlowBaseMS_EN;
// register bml_fabFlowSize
reg [31 : 0] bml_fabFlowSize;
wire [31 : 0] bml_fabFlowSize_D_IN;
wire bml_fabFlowSize_EN;
// register bml_fabMesgAddr
reg [31 : 0] bml_fabMesgAddr;
wire [31 : 0] bml_fabMesgAddr_D_IN;
wire bml_fabMesgAddr_EN;
// register bml_fabMesgBase
reg [31 : 0] bml_fabMesgBase;
wire [31 : 0] bml_fabMesgBase_D_IN;
wire bml_fabMesgBase_EN;
// register bml_fabMesgBaseMS
reg [31 : 0] bml_fabMesgBaseMS;
wire [31 : 0] bml_fabMesgBaseMS_D_IN;
wire bml_fabMesgBaseMS_EN;
// register bml_fabMesgSize
reg [31 : 0] bml_fabMesgSize;
wire [31 : 0] bml_fabMesgSize_D_IN;
wire bml_fabMesgSize_EN;
// register bml_fabMetaAddr
reg [31 : 0] bml_fabMetaAddr;
wire [31 : 0] bml_fabMetaAddr_D_IN;
wire bml_fabMetaAddr_EN;
// register bml_fabMetaBase
reg [31 : 0] bml_fabMetaBase;
wire [31 : 0] bml_fabMetaBase_D_IN;
wire bml_fabMetaBase_EN;
// register bml_fabMetaBaseMS
reg [31 : 0] bml_fabMetaBaseMS;
wire [31 : 0] bml_fabMetaBaseMS_D_IN;
wire bml_fabMetaBaseMS_EN;
// register bml_fabMetaSize
reg [31 : 0] bml_fabMetaSize;
wire [31 : 0] bml_fabMetaSize_D_IN;
wire bml_fabMetaSize_EN;
// register bml_fabNumBufs
reg [15 : 0] bml_fabNumBufs;
wire [15 : 0] bml_fabNumBufs_D_IN;
wire bml_fabNumBufs_EN;
// register bml_lclBufDone
reg bml_lclBufDone;
wire bml_lclBufDone_D_IN, bml_lclBufDone_EN;
// register bml_lclBufStart
reg bml_lclBufStart;
wire bml_lclBufStart_D_IN, bml_lclBufStart_EN;
// register bml_lclBuf_modulus
reg [15 : 0] bml_lclBuf_modulus;
wire [15 : 0] bml_lclBuf_modulus_D_IN;
wire bml_lclBuf_modulus_EN;
// register bml_lclBuf_value
reg [15 : 0] bml_lclBuf_value;
wire [15 : 0] bml_lclBuf_value_D_IN;
wire bml_lclBuf_value_EN;
// register bml_lclBufsAR
reg [15 : 0] bml_lclBufsAR;
wire [15 : 0] bml_lclBufsAR_D_IN;
wire bml_lclBufsAR_EN;
// register bml_lclBufsCF
reg [15 : 0] bml_lclBufsCF;
wire [15 : 0] bml_lclBufsCF_D_IN;
wire bml_lclBufsCF_EN;
// register bml_lclCredit
reg [15 : 0] bml_lclCredit;
wire [15 : 0] bml_lclCredit_D_IN;
wire bml_lclCredit_EN;
// register bml_lclDones
reg [15 : 0] bml_lclDones;
wire [15 : 0] bml_lclDones_D_IN;
wire bml_lclDones_EN;
// register bml_lclMesgAddr
reg [15 : 0] bml_lclMesgAddr;
wire [15 : 0] bml_lclMesgAddr_D_IN;
wire bml_lclMesgAddr_EN;
// register bml_lclMetaAddr
reg [15 : 0] bml_lclMetaAddr;
wire [15 : 0] bml_lclMetaAddr_D_IN;
wire bml_lclMetaAddr_EN;
// register bml_lclNumBufs
reg [15 : 0] bml_lclNumBufs;
wire [15 : 0] bml_lclNumBufs_D_IN;
wire bml_lclNumBufs_EN;
// register bml_lclStarts
reg [15 : 0] bml_lclStarts;
wire [15 : 0] bml_lclStarts_D_IN;
wire bml_lclStarts_EN;
// register bml_mesgBase
reg [15 : 0] bml_mesgBase;
wire [15 : 0] bml_mesgBase_D_IN;
wire bml_mesgBase_EN;
// register bml_mesgSize
reg [15 : 0] bml_mesgSize;
wire [15 : 0] bml_mesgSize_D_IN;
wire bml_mesgSize_EN;
// register bml_metaBase
reg [15 : 0] bml_metaBase;
wire [15 : 0] bml_metaBase_D_IN;
wire bml_metaBase_EN;
// register bml_metaSize
reg [15 : 0] bml_metaSize;
wire [15 : 0] bml_metaSize_D_IN;
wire bml_metaSize_EN;
// register bml_remBuf_modulus
reg [15 : 0] bml_remBuf_modulus;
wire [15 : 0] bml_remBuf_modulus_D_IN;
wire bml_remBuf_modulus_EN;
// register bml_remBuf_value
reg [15 : 0] bml_remBuf_value;
wire [15 : 0] bml_remBuf_value_D_IN;
wire bml_remBuf_value_EN;
// register bml_remDone
reg bml_remDone;
wire bml_remDone_D_IN, bml_remDone_EN;
// register bml_remDones
reg [15 : 0] bml_remDones;
wire [15 : 0] bml_remDones_D_IN;
wire bml_remDones_EN;
// register bml_remMesgAddr
reg [15 : 0] bml_remMesgAddr;
wire [15 : 0] bml_remMesgAddr_D_IN;
wire bml_remMesgAddr_EN;
// register bml_remMetaAddr
reg [15 : 0] bml_remMetaAddr;
wire [15 : 0] bml_remMetaAddr_D_IN;
wire bml_remMetaAddr_EN;
// register bml_remStart
reg bml_remStart;
wire bml_remStart_D_IN, bml_remStart_EN;
// register bml_remStarts
reg [15 : 0] bml_remStarts;
wire [15 : 0] bml_remStarts_D_IN;
wire bml_remStarts_EN;
// register bram_0_serverAdapterA_cnt
reg [2 : 0] bram_0_serverAdapterA_cnt;
wire [2 : 0] bram_0_serverAdapterA_cnt_D_IN;
wire bram_0_serverAdapterA_cnt_EN;
// register bram_0_serverAdapterA_s1
reg [1 : 0] bram_0_serverAdapterA_s1;
wire [1 : 0] bram_0_serverAdapterA_s1_D_IN;
wire bram_0_serverAdapterA_s1_EN;
// register bram_0_serverAdapterB_cnt
reg [2 : 0] bram_0_serverAdapterB_cnt;
wire [2 : 0] bram_0_serverAdapterB_cnt_D_IN;
wire bram_0_serverAdapterB_cnt_EN;
// register bram_0_serverAdapterB_s1
reg [1 : 0] bram_0_serverAdapterB_s1;
wire [1 : 0] bram_0_serverAdapterB_s1_D_IN;
wire bram_0_serverAdapterB_s1_EN;
// register bram_1_serverAdapterA_cnt
reg [2 : 0] bram_1_serverAdapterA_cnt;
wire [2 : 0] bram_1_serverAdapterA_cnt_D_IN;
wire bram_1_serverAdapterA_cnt_EN;
// register bram_1_serverAdapterA_s1
reg [1 : 0] bram_1_serverAdapterA_s1;
wire [1 : 0] bram_1_serverAdapterA_s1_D_IN;
wire bram_1_serverAdapterA_s1_EN;
// register bram_1_serverAdapterB_cnt
reg [2 : 0] bram_1_serverAdapterB_cnt;
wire [2 : 0] bram_1_serverAdapterB_cnt_D_IN;
wire bram_1_serverAdapterB_cnt_EN;
// register bram_1_serverAdapterB_s1
reg [1 : 0] bram_1_serverAdapterB_s1;
wire [1 : 0] bram_1_serverAdapterB_s1_D_IN;
wire bram_1_serverAdapterB_s1_EN;
// register bram_2_serverAdapterA_cnt
reg [2 : 0] bram_2_serverAdapterA_cnt;
wire [2 : 0] bram_2_serverAdapterA_cnt_D_IN;
wire bram_2_serverAdapterA_cnt_EN;
// register bram_2_serverAdapterA_s1
reg [1 : 0] bram_2_serverAdapterA_s1;
wire [1 : 0] bram_2_serverAdapterA_s1_D_IN;
wire bram_2_serverAdapterA_s1_EN;
// register bram_2_serverAdapterB_cnt
reg [2 : 0] bram_2_serverAdapterB_cnt;
wire [2 : 0] bram_2_serverAdapterB_cnt_D_IN;
wire bram_2_serverAdapterB_cnt_EN;
// register bram_2_serverAdapterB_s1
reg [1 : 0] bram_2_serverAdapterB_s1;
wire [1 : 0] bram_2_serverAdapterB_s1_D_IN;
wire bram_2_serverAdapterB_s1_EN;
// register bram_3_serverAdapterA_cnt
reg [2 : 0] bram_3_serverAdapterA_cnt;
wire [2 : 0] bram_3_serverAdapterA_cnt_D_IN;
wire bram_3_serverAdapterA_cnt_EN;
// register bram_3_serverAdapterA_s1
reg [1 : 0] bram_3_serverAdapterA_s1;
wire [1 : 0] bram_3_serverAdapterA_s1_D_IN;
wire bram_3_serverAdapterA_s1_EN;
// register bram_3_serverAdapterB_cnt
reg [2 : 0] bram_3_serverAdapterB_cnt;
wire [2 : 0] bram_3_serverAdapterB_cnt_D_IN;
wire bram_3_serverAdapterB_cnt_EN;
// register bram_3_serverAdapterB_s1
reg [1 : 0] bram_3_serverAdapterB_s1;
wire [1 : 0] bram_3_serverAdapterB_s1_D_IN;
wire bram_3_serverAdapterB_s1_EN;
// register dmaDoneTime
reg [63 : 0] dmaDoneTime;
wire [63 : 0] dmaDoneTime_D_IN;
wire dmaDoneTime_EN;
// register dmaStartTime
reg [63 : 0] dmaStartTime;
wire [63 : 0] dmaStartTime_D_IN;
wire dmaStartTime_EN;
// register dpControl
reg [7 : 0] dpControl;
wire [7 : 0] dpControl_D_IN;
wire dpControl_EN;
// register tlp_complTimerCount
reg [11 : 0] tlp_complTimerCount;
wire [11 : 0] tlp_complTimerCount_D_IN;
wire tlp_complTimerCount_EN;
// register tlp_complTimerRunning
reg tlp_complTimerRunning;
wire tlp_complTimerRunning_D_IN, tlp_complTimerRunning_EN;
// register tlp_creditReady
reg tlp_creditReady;
wire tlp_creditReady_D_IN, tlp_creditReady_EN;
// register tlp_dmaDoTailEvent
reg tlp_dmaDoTailEvent;
reg tlp_dmaDoTailEvent_D_IN;
wire tlp_dmaDoTailEvent_EN;
// register tlp_dmaDoneMark
reg tlp_dmaDoneMark;
wire tlp_dmaDoneMark_D_IN, tlp_dmaDoneMark_EN;
// register tlp_dmaPullRemainDWLen
reg [9 : 0] tlp_dmaPullRemainDWLen;
reg [9 : 0] tlp_dmaPullRemainDWLen_D_IN;
wire tlp_dmaPullRemainDWLen_EN;
// register tlp_dmaPullRemainDWSub
reg [9 : 0] tlp_dmaPullRemainDWSub;
wire [9 : 0] tlp_dmaPullRemainDWSub_D_IN;
wire tlp_dmaPullRemainDWSub_EN;
// register tlp_dmaReqTag
reg [4 : 0] tlp_dmaReqTag;
wire [4 : 0] tlp_dmaReqTag_D_IN;
wire tlp_dmaReqTag_EN;
// register tlp_dmaStartMark
reg tlp_dmaStartMark;
wire tlp_dmaStartMark_D_IN, tlp_dmaStartMark_EN;
// register tlp_dmaTag
reg [4 : 0] tlp_dmaTag;
wire [4 : 0] tlp_dmaTag_D_IN;
wire tlp_dmaTag_EN;
// register tlp_doXmtMetaBody
reg tlp_doXmtMetaBody;
wire tlp_doXmtMetaBody_D_IN, tlp_doXmtMetaBody_EN;
// register tlp_doorSeqDwell
reg [3 : 0] tlp_doorSeqDwell;
wire [3 : 0] tlp_doorSeqDwell_D_IN;
wire tlp_doorSeqDwell_EN;
// register tlp_fabFlowAddr
reg [31 : 0] tlp_fabFlowAddr;
wire [31 : 0] tlp_fabFlowAddr_D_IN;
wire tlp_fabFlowAddr_EN;
// register tlp_fabFlowAddrMS
reg [31 : 0] tlp_fabFlowAddrMS;
wire [31 : 0] tlp_fabFlowAddrMS_D_IN;
wire tlp_fabFlowAddrMS_EN;
// register tlp_fabMesgAccu
reg [31 : 0] tlp_fabMesgAccu;
reg [31 : 0] tlp_fabMesgAccu_D_IN;
wire tlp_fabMesgAccu_EN;
// register tlp_fabMesgAddr
reg [31 : 0] tlp_fabMesgAddr;
wire [31 : 0] tlp_fabMesgAddr_D_IN;
wire tlp_fabMesgAddr_EN;
// register tlp_fabMesgAddrMS
reg [31 : 0] tlp_fabMesgAddrMS;
wire [31 : 0] tlp_fabMesgAddrMS_D_IN;
wire tlp_fabMesgAddrMS_EN;
// register tlp_fabMeta
reg [128 : 0] tlp_fabMeta;
reg [128 : 0] tlp_fabMeta_D_IN;
wire tlp_fabMeta_EN;
// register tlp_fabMetaAddr
reg [31 : 0] tlp_fabMetaAddr;
wire [31 : 0] tlp_fabMetaAddr_D_IN;
wire tlp_fabMetaAddr_EN;
// register tlp_fabMetaAddrMS
reg [31 : 0] tlp_fabMetaAddrMS;
wire [31 : 0] tlp_fabMetaAddrMS_D_IN;
wire tlp_fabMetaAddrMS_EN;
// register tlp_farBufReady
reg tlp_farBufReady;
wire tlp_farBufReady_D_IN, tlp_farBufReady_EN;
// register tlp_flowDiagCount
reg [31 : 0] tlp_flowDiagCount;
wire [31 : 0] tlp_flowDiagCount_D_IN;
wire tlp_flowDiagCount_EN;
// register tlp_gotResponseHeader
reg tlp_gotResponseHeader;
reg tlp_gotResponseHeader_D_IN;
wire tlp_gotResponseHeader_EN;
// register tlp_inIgnorePkt
reg tlp_inIgnorePkt;
wire tlp_inIgnorePkt_D_IN, tlp_inIgnorePkt_EN;
// register tlp_lastMetaV_0
reg [31 : 0] tlp_lastMetaV_0;
wire [31 : 0] tlp_lastMetaV_0_D_IN;
wire tlp_lastMetaV_0_EN;
// register tlp_lastMetaV_1
reg [31 : 0] tlp_lastMetaV_1;
wire [31 : 0] tlp_lastMetaV_1_D_IN;
wire tlp_lastMetaV_1_EN;
// register tlp_lastMetaV_2
reg [31 : 0] tlp_lastMetaV_2;
wire [31 : 0] tlp_lastMetaV_2_D_IN;
wire tlp_lastMetaV_2_EN;
// register tlp_lastMetaV_3
reg [31 : 0] tlp_lastMetaV_3;
wire [31 : 0] tlp_lastMetaV_3_D_IN;
wire tlp_lastMetaV_3_EN;
// register tlp_lastRuleFired
reg [3 : 0] tlp_lastRuleFired;
reg [3 : 0] tlp_lastRuleFired_D_IN;
wire tlp_lastRuleFired_EN;
// register tlp_maxPayloadSize
reg [12 : 0] tlp_maxPayloadSize;
wire [12 : 0] tlp_maxPayloadSize_D_IN;
wire tlp_maxPayloadSize_EN;
// register tlp_maxReadReqSize
reg [12 : 0] tlp_maxReadReqSize;
wire [12 : 0] tlp_maxReadReqSize_D_IN;
wire tlp_maxReadReqSize_EN;
// register tlp_mesgComplReceived
reg [16 : 0] tlp_mesgComplReceived;
reg [16 : 0] tlp_mesgComplReceived_D_IN;
wire tlp_mesgComplReceived_EN;
// register tlp_mesgLengthRemainPull
reg [16 : 0] tlp_mesgLengthRemainPull;
reg [16 : 0] tlp_mesgLengthRemainPull_D_IN;
wire tlp_mesgLengthRemainPull_EN;
// register tlp_mesgLengthRemainPush
reg [16 : 0] tlp_mesgLengthRemainPush;
reg [16 : 0] tlp_mesgLengthRemainPush_D_IN;
wire tlp_mesgLengthRemainPush_EN;
// register tlp_nearBufReady
reg tlp_nearBufReady;
wire tlp_nearBufReady_D_IN, tlp_nearBufReady_EN;
// register tlp_outDwRemain
reg [9 : 0] tlp_outDwRemain;
reg [9 : 0] tlp_outDwRemain_D_IN;
wire tlp_outDwRemain_EN;
// register tlp_postSeqDwell
reg [3 : 0] tlp_postSeqDwell;
wire [3 : 0] tlp_postSeqDwell_D_IN;
wire tlp_postSeqDwell_EN;
// register tlp_pullTagMatch
reg tlp_pullTagMatch;
wire tlp_pullTagMatch_D_IN, tlp_pullTagMatch_EN;
// register tlp_remDone
reg tlp_remDone;
wire tlp_remDone_D_IN, tlp_remDone_EN;
// register tlp_remMesgAccu
reg [15 : 0] tlp_remMesgAccu;
reg [15 : 0] tlp_remMesgAccu_D_IN;
wire tlp_remMesgAccu_EN;
// register tlp_remMesgAddr
reg [15 : 0] tlp_remMesgAddr;
wire [15 : 0] tlp_remMesgAddr_D_IN;
wire tlp_remMesgAddr_EN;
// register tlp_remMetaAddr
reg [15 : 0] tlp_remMetaAddr;
wire [15 : 0] tlp_remMetaAddr_D_IN;
wire tlp_remMetaAddr_EN;
// register tlp_remStart
reg tlp_remStart;
wire tlp_remStart_D_IN, tlp_remStart_EN;
// register tlp_reqMesgInFlight
reg tlp_reqMesgInFlight;
reg tlp_reqMesgInFlight_D_IN;
wire tlp_reqMesgInFlight_EN;
// register tlp_reqMetaBodyInFlight
reg tlp_reqMetaBodyInFlight;
wire tlp_reqMetaBodyInFlight_D_IN, tlp_reqMetaBodyInFlight_EN;
// register tlp_reqMetaInFlight
reg tlp_reqMetaInFlight;
reg tlp_reqMetaInFlight_D_IN;
wire tlp_reqMetaInFlight_EN;
// register tlp_sentTail4DWHeader
reg tlp_sentTail4DWHeader;
wire tlp_sentTail4DWHeader_D_IN, tlp_sentTail4DWHeader_EN;
// register tlp_srcMesgAccu
reg [31 : 0] tlp_srcMesgAccu;
wire [31 : 0] tlp_srcMesgAccu_D_IN;
wire tlp_srcMesgAccu_EN;
// register tlp_tlpBRAM_debugBdata
reg [127 : 0] tlp_tlpBRAM_debugBdata;
wire [127 : 0] tlp_tlpBRAM_debugBdata_D_IN;
wire tlp_tlpBRAM_debugBdata_EN;
// register tlp_tlpBRAM_rdRespDwRemain
reg [9 : 0] tlp_tlpBRAM_rdRespDwRemain;
wire [9 : 0] tlp_tlpBRAM_rdRespDwRemain_D_IN;
wire tlp_tlpBRAM_rdRespDwRemain_EN;
// register tlp_tlpBRAM_readHeaderSent
reg tlp_tlpBRAM_readHeaderSent;
wire tlp_tlpBRAM_readHeaderSent_D_IN, tlp_tlpBRAM_readHeaderSent_EN;
// register tlp_tlpBRAM_readNxtDWAddr
reg [12 : 0] tlp_tlpBRAM_readNxtDWAddr;
wire [12 : 0] tlp_tlpBRAM_readNxtDWAddr_D_IN;
wire tlp_tlpBRAM_readNxtDWAddr_EN;
// register tlp_tlpBRAM_readRemainDWLen
reg [9 : 0] tlp_tlpBRAM_readRemainDWLen;
wire [9 : 0] tlp_tlpBRAM_readRemainDWLen_D_IN;
wire tlp_tlpBRAM_readRemainDWLen_EN;
// register tlp_tlpBRAM_readStarted
reg tlp_tlpBRAM_readStarted;
wire tlp_tlpBRAM_readStarted_D_IN, tlp_tlpBRAM_readStarted_EN;
// register tlp_tlpBRAM_writeDWAddr
reg [12 : 0] tlp_tlpBRAM_writeDWAddr;
wire [12 : 0] tlp_tlpBRAM_writeDWAddr_D_IN;
wire tlp_tlpBRAM_writeDWAddr_EN;
// register tlp_tlpBRAM_writeLastBE
reg [3 : 0] tlp_tlpBRAM_writeLastBE;
wire [3 : 0] tlp_tlpBRAM_writeLastBE_D_IN;
wire tlp_tlpBRAM_writeLastBE_EN;
// register tlp_tlpBRAM_writeRemainDWLen
reg [9 : 0] tlp_tlpBRAM_writeRemainDWLen;
wire [9 : 0] tlp_tlpBRAM_writeRemainDWLen_D_IN;
wire tlp_tlpBRAM_writeRemainDWLen_EN;
// register tlp_tlpMetaSent
reg tlp_tlpMetaSent;
wire tlp_tlpMetaSent_D_IN, tlp_tlpMetaSent_EN;
// register tlp_tlpRcvBusy
reg tlp_tlpRcvBusy;
reg tlp_tlpRcvBusy_D_IN;
wire tlp_tlpRcvBusy_EN;
// register tlp_tlpXmtBusy
reg tlp_tlpXmtBusy;
reg tlp_tlpXmtBusy_D_IN;
wire tlp_tlpXmtBusy_EN;
// register tlp_xmtMetaInFlight
reg tlp_xmtMetaInFlight;
wire tlp_xmtMetaInFlight_D_IN, tlp_xmtMetaInFlight_EN;
// register tlp_xmtMetaOK
reg tlp_xmtMetaOK;
reg tlp_xmtMetaOK_D_IN;
wire tlp_xmtMetaOK_EN;
// register wci_cEdge
reg [2 : 0] wci_cEdge;
wire [2 : 0] wci_cEdge_D_IN;
wire wci_cEdge_EN;
// register wci_cState
reg [2 : 0] wci_cState;
wire [2 : 0] wci_cState_D_IN;
wire wci_cState_EN;
// register wci_ctlAckReg
reg wci_ctlAckReg;
wire wci_ctlAckReg_D_IN, wci_ctlAckReg_EN;
// register wci_ctlOpActive
reg wci_ctlOpActive;
wire wci_ctlOpActive_D_IN, wci_ctlOpActive_EN;
// register wci_illegalEdge
reg wci_illegalEdge;
wire wci_illegalEdge_D_IN, wci_illegalEdge_EN;
// register wci_isReset_isInReset
reg wci_isReset_isInReset;
wire wci_isReset_isInReset_D_IN, wci_isReset_isInReset_EN;
// register wci_nState
reg [2 : 0] wci_nState;
reg [2 : 0] wci_nState_D_IN;
wire wci_nState_EN;
// register wci_reqF_countReg
reg [1 : 0] wci_reqF_countReg;
wire [1 : 0] wci_reqF_countReg_D_IN;
wire wci_reqF_countReg_EN;
// register wci_respF_cntr_r
reg [1 : 0] wci_respF_cntr_r;
wire [1 : 0] wci_respF_cntr_r_D_IN;
wire wci_respF_cntr_r_EN;
// register wci_respF_q_0
reg [33 : 0] wci_respF_q_0;
reg [33 : 0] wci_respF_q_0_D_IN;
wire wci_respF_q_0_EN;
// register wci_respF_q_1
reg [33 : 0] wci_respF_q_1;
reg [33 : 0] wci_respF_q_1_D_IN;
wire wci_respF_q_1_EN;
// register wci_sFlagReg
reg wci_sFlagReg;
wire wci_sFlagReg_D_IN, wci_sFlagReg_EN;
// register wci_sThreadBusy_d
reg wci_sThreadBusy_d;
wire wci_sThreadBusy_d_D_IN, wci_sThreadBusy_d_EN;
// register wmi_addr
reg [13 : 0] wmi_addr;
wire [13 : 0] wmi_addr_D_IN;
wire wmi_addr_EN;
// register wmi_bufDwell
reg [1 : 0] wmi_bufDwell;
wire [1 : 0] wmi_bufDwell_D_IN;
wire wmi_bufDwell_EN;
// register wmi_bytesRemainReq
reg [13 : 0] wmi_bytesRemainReq;
wire [13 : 0] wmi_bytesRemainReq_D_IN;
wire wmi_bytesRemainReq_EN;
// register wmi_bytesRemainResp
reg [13 : 0] wmi_bytesRemainResp;
wire [13 : 0] wmi_bytesRemainResp_D_IN;
wire wmi_bytesRemainResp_EN;
// register wmi_doneWithMesg
reg wmi_doneWithMesg;
wire wmi_doneWithMesg_D_IN, wmi_doneWithMesg_EN;
// register wmi_lastMesg
reg [31 : 0] wmi_lastMesg;
wire [31 : 0] wmi_lastMesg_D_IN;
wire wmi_lastMesg_EN;
// register wmi_lclMesgAddr
reg [14 : 0] wmi_lclMesgAddr;
wire [14 : 0] wmi_lclMesgAddr_D_IN;
wire wmi_lclMesgAddr_EN;
// register wmi_lclMetaAddr
reg [14 : 0] wmi_lclMetaAddr;
wire [14 : 0] wmi_lclMetaAddr_D_IN;
wire wmi_lclMetaAddr_EN;
// register wmi_mesgBufReady
reg wmi_mesgBufReady;
wire wmi_mesgBufReady_D_IN, wmi_mesgBufReady_EN;
// register wmi_mesgBusy
reg wmi_mesgBusy;
wire wmi_mesgBusy_D_IN, wmi_mesgBusy_EN;
// register wmi_mesgCount
reg [31 : 0] wmi_mesgCount;
wire [31 : 0] wmi_mesgCount_D_IN;
wire wmi_mesgCount_EN;
// register wmi_mesgDone
reg wmi_mesgDone;
wire wmi_mesgDone_D_IN, wmi_mesgDone_EN;
// register wmi_mesgMeta
reg [128 : 0] wmi_mesgMeta;
wire [128 : 0] wmi_mesgMeta_D_IN;
wire wmi_mesgMeta_EN;
// register wmi_mesgStart
reg wmi_mesgStart;
wire wmi_mesgStart_D_IN, wmi_mesgStart_EN;
// register wmi_metaBusy
reg wmi_metaBusy;
wire wmi_metaBusy_D_IN, wmi_metaBusy_EN;
// register wmi_p4B
reg [1 : 0] wmi_p4B;
wire [1 : 0] wmi_p4B_D_IN;
wire wmi_p4B_EN;
// register wmi_rdActive
reg wmi_rdActive;
wire wmi_rdActive_D_IN, wmi_rdActive_EN;
// register wmi_reqCount
reg [15 : 0] wmi_reqCount;
wire [15 : 0] wmi_reqCount_D_IN;
wire wmi_reqCount_EN;
// register wmi_thisMesg
reg [31 : 0] wmi_thisMesg;
wire [31 : 0] wmi_thisMesg_D_IN;
wire wmi_thisMesg_EN;
// register wmi_wmi_blockReq
reg wmi_wmi_blockReq;
wire wmi_wmi_blockReq_D_IN, wmi_wmi_blockReq_EN;
// register wmi_wmi_dhF_countReg
reg [1 : 0] wmi_wmi_dhF_countReg;
wire [1 : 0] wmi_wmi_dhF_countReg_D_IN;
wire wmi_wmi_dhF_countReg_EN;
// register wmi_wmi_dhF_levelsValid
reg wmi_wmi_dhF_levelsValid;
wire wmi_wmi_dhF_levelsValid_D_IN, wmi_wmi_dhF_levelsValid_EN;
// register wmi_wmi_errorSticky
reg wmi_wmi_errorSticky;
wire wmi_wmi_errorSticky_D_IN, wmi_wmi_errorSticky_EN;
// register wmi_wmi_isReset_isInReset
reg wmi_wmi_isReset_isInReset;
wire wmi_wmi_isReset_isInReset_D_IN, wmi_wmi_isReset_isInReset_EN;
// register wmi_wmi_mFlagF_countReg
reg [1 : 0] wmi_wmi_mFlagF_countReg;
wire [1 : 0] wmi_wmi_mFlagF_countReg_D_IN;
wire wmi_wmi_mFlagF_countReg_EN;
// register wmi_wmi_mFlagF_levelsValid
reg wmi_wmi_mFlagF_levelsValid;
wire wmi_wmi_mFlagF_levelsValid_D_IN, wmi_wmi_mFlagF_levelsValid_EN;
// register wmi_wmi_operateD
reg wmi_wmi_operateD;
wire wmi_wmi_operateD_D_IN, wmi_wmi_operateD_EN;
// register wmi_wmi_peerIsReady
reg wmi_wmi_peerIsReady;
wire wmi_wmi_peerIsReady_D_IN, wmi_wmi_peerIsReady_EN;
// register wmi_wmi_reqF_countReg
reg [1 : 0] wmi_wmi_reqF_countReg;
wire [1 : 0] wmi_wmi_reqF_countReg_D_IN;
wire wmi_wmi_reqF_countReg_EN;
// register wmi_wmi_reqF_levelsValid
reg wmi_wmi_reqF_levelsValid;
wire wmi_wmi_reqF_levelsValid_D_IN, wmi_wmi_reqF_levelsValid_EN;
// register wmi_wmi_respF_cntr_r
reg [1 : 0] wmi_wmi_respF_cntr_r;
wire [1 : 0] wmi_wmi_respF_cntr_r_D_IN;
wire wmi_wmi_respF_cntr_r_EN;
// register wmi_wmi_respF_q_0
reg [129 : 0] wmi_wmi_respF_q_0;
reg [129 : 0] wmi_wmi_respF_q_0_D_IN;
wire wmi_wmi_respF_q_0_EN;
// register wmi_wmi_respF_q_1
reg [129 : 0] wmi_wmi_respF_q_1;
reg [129 : 0] wmi_wmi_respF_q_1_D_IN;
wire wmi_wmi_respF_q_1_EN;
// register wmi_wmi_sFlagReg
reg [31 : 0] wmi_wmi_sFlagReg;
wire [31 : 0] wmi_wmi_sFlagReg_D_IN;
wire wmi_wmi_sFlagReg_EN;
// register wmi_wmi_statusR
reg [7 : 0] wmi_wmi_statusR;
wire [7 : 0] wmi_wmi_statusR_D_IN;
wire wmi_wmi_statusR_EN;
// register wmi_wmi_trafficSticky
reg wmi_wmi_trafficSticky;
wire wmi_wmi_trafficSticky_D_IN, wmi_wmi_trafficSticky_EN;
// register wmi_wrActive
reg wmi_wrActive;
wire wmi_wrActive_D_IN, wmi_wrActive_EN;
// register wmi_wrFinalize
reg wmi_wrFinalize;
wire wmi_wrFinalize_D_IN, wmi_wrFinalize_EN;
// register wmi_wrtCount
reg [15 : 0] wmi_wrtCount;
wire [15 : 0] wmi_wrtCount_D_IN;
wire wmi_wrtCount_EN;
// register wti_isReset_isInReset
reg wti_isReset_isInReset;
wire wti_isReset_isInReset_D_IN, wti_isReset_isInReset_EN;
// register wti_nowReq
reg [66 : 0] wti_nowReq;
wire [66 : 0] wti_nowReq_D_IN;
wire wti_nowReq_EN;
// register wti_operateD
reg wti_operateD;
wire wti_operateD_D_IN, wti_operateD_EN;
// ports of submodule bram_0_memory
reg [31 : 0] bram_0_memory_DIA, bram_0_memory_DIB;
reg [10 : 0] bram_0_memory_ADDRA, bram_0_memory_ADDRB;
wire [31 : 0] bram_0_memory_DOA, bram_0_memory_DOB;
wire bram_0_memory_ENA,
bram_0_memory_ENB,
bram_0_memory_WEA,
bram_0_memory_WEB;
// ports of submodule bram_0_serverAdapterA_outDataCore
wire [31 : 0] bram_0_serverAdapterA_outDataCore_D_IN,
bram_0_serverAdapterA_outDataCore_D_OUT;
wire bram_0_serverAdapterA_outDataCore_CLR,
bram_0_serverAdapterA_outDataCore_DEQ,
bram_0_serverAdapterA_outDataCore_EMPTY_N,
bram_0_serverAdapterA_outDataCore_ENQ,
bram_0_serverAdapterA_outDataCore_FULL_N;
// ports of submodule bram_0_serverAdapterB_outDataCore
wire [31 : 0] bram_0_serverAdapterB_outDataCore_D_IN,
bram_0_serverAdapterB_outDataCore_D_OUT;
wire bram_0_serverAdapterB_outDataCore_CLR,
bram_0_serverAdapterB_outDataCore_DEQ,
bram_0_serverAdapterB_outDataCore_EMPTY_N,
bram_0_serverAdapterB_outDataCore_ENQ,
bram_0_serverAdapterB_outDataCore_FULL_N;
// ports of submodule bram_1_memory
reg [31 : 0] bram_1_memory_DIA, bram_1_memory_DIB;
reg [10 : 0] bram_1_memory_ADDRA, bram_1_memory_ADDRB;
wire [31 : 0] bram_1_memory_DOA, bram_1_memory_DOB;
wire bram_1_memory_ENA,
bram_1_memory_ENB,
bram_1_memory_WEA,
bram_1_memory_WEB;
// ports of submodule bram_1_serverAdapterA_outDataCore
wire [31 : 0] bram_1_serverAdapterA_outDataCore_D_IN,
bram_1_serverAdapterA_outDataCore_D_OUT;
wire bram_1_serverAdapterA_outDataCore_CLR,
bram_1_serverAdapterA_outDataCore_DEQ,
bram_1_serverAdapterA_outDataCore_EMPTY_N,
bram_1_serverAdapterA_outDataCore_ENQ,
bram_1_serverAdapterA_outDataCore_FULL_N;
// ports of submodule bram_1_serverAdapterB_outDataCore
wire [31 : 0] bram_1_serverAdapterB_outDataCore_D_IN,
bram_1_serverAdapterB_outDataCore_D_OUT;
wire bram_1_serverAdapterB_outDataCore_CLR,
bram_1_serverAdapterB_outDataCore_DEQ,
bram_1_serverAdapterB_outDataCore_EMPTY_N,
bram_1_serverAdapterB_outDataCore_ENQ,
bram_1_serverAdapterB_outDataCore_FULL_N;
// ports of submodule bram_2_memory
reg [31 : 0] bram_2_memory_DIA, bram_2_memory_DIB;
reg [10 : 0] bram_2_memory_ADDRA, bram_2_memory_ADDRB;
wire [31 : 0] bram_2_memory_DOA, bram_2_memory_DOB;
wire bram_2_memory_ENA,
bram_2_memory_ENB,
bram_2_memory_WEA,
bram_2_memory_WEB;
// ports of submodule bram_2_serverAdapterA_outDataCore
wire [31 : 0] bram_2_serverAdapterA_outDataCore_D_IN,
bram_2_serverAdapterA_outDataCore_D_OUT;
wire bram_2_serverAdapterA_outDataCore_CLR,
bram_2_serverAdapterA_outDataCore_DEQ,
bram_2_serverAdapterA_outDataCore_EMPTY_N,
bram_2_serverAdapterA_outDataCore_ENQ,
bram_2_serverAdapterA_outDataCore_FULL_N;
// ports of submodule bram_2_serverAdapterB_outDataCore
wire [31 : 0] bram_2_serverAdapterB_outDataCore_D_IN,
bram_2_serverAdapterB_outDataCore_D_OUT;
wire bram_2_serverAdapterB_outDataCore_CLR,
bram_2_serverAdapterB_outDataCore_DEQ,
bram_2_serverAdapterB_outDataCore_EMPTY_N,
bram_2_serverAdapterB_outDataCore_ENQ,
bram_2_serverAdapterB_outDataCore_FULL_N;
// ports of submodule bram_3_memory
reg [31 : 0] bram_3_memory_DIA, bram_3_memory_DIB;
reg [10 : 0] bram_3_memory_ADDRA, bram_3_memory_ADDRB;
wire [31 : 0] bram_3_memory_DOA, bram_3_memory_DOB;
wire bram_3_memory_ENA,
bram_3_memory_ENB,
bram_3_memory_WEA,
bram_3_memory_WEB;
// ports of submodule bram_3_serverAdapterA_outDataCore
wire [31 : 0] bram_3_serverAdapterA_outDataCore_D_IN,
bram_3_serverAdapterA_outDataCore_D_OUT;
wire bram_3_serverAdapterA_outDataCore_CLR,
bram_3_serverAdapterA_outDataCore_DEQ,
bram_3_serverAdapterA_outDataCore_EMPTY_N,
bram_3_serverAdapterA_outDataCore_ENQ,
bram_3_serverAdapterA_outDataCore_FULL_N;
// ports of submodule bram_3_serverAdapterB_outDataCore
wire [31 : 0] bram_3_serverAdapterB_outDataCore_D_IN,
bram_3_serverAdapterB_outDataCore_D_OUT;
wire bram_3_serverAdapterB_outDataCore_CLR,
bram_3_serverAdapterB_outDataCore_DEQ,
bram_3_serverAdapterB_outDataCore_EMPTY_N,
bram_3_serverAdapterB_outDataCore_ENQ,
bram_3_serverAdapterB_outDataCore_FULL_N;
// ports of submodule tlp_inF
wire [152 : 0] tlp_inF_D_IN, tlp_inF_D_OUT;
wire tlp_inF_CLR, tlp_inF_DEQ, tlp_inF_EMPTY_N, tlp_inF_ENQ, tlp_inF_FULL_N;
// ports of submodule tlp_outF
reg [152 : 0] tlp_outF_D_IN;
wire [152 : 0] tlp_outF_D_OUT;
wire tlp_outF_CLR,
tlp_outF_DEQ,
tlp_outF_EMPTY_N,
tlp_outF_ENQ,
tlp_outF_FULL_N;
// ports of submodule tlp_tailEventF
wire tlp_tailEventF_CLR,
tlp_tailEventF_DEQ,
tlp_tailEventF_D_IN,
tlp_tailEventF_D_OUT,
tlp_tailEventF_EMPTY_N,
tlp_tailEventF_ENQ,
tlp_tailEventF_FULL_N;
// ports of submodule tlp_tlpBRAM_mReqF
reg [129 : 0] tlp_tlpBRAM_mReqF_D_IN;
wire [129 : 0] tlp_tlpBRAM_mReqF_D_OUT;
wire tlp_tlpBRAM_mReqF_CLR,
tlp_tlpBRAM_mReqF_DEQ,
tlp_tlpBRAM_mReqF_EMPTY_N,
tlp_tlpBRAM_mReqF_ENQ,
tlp_tlpBRAM_mReqF_FULL_N;
// ports of submodule tlp_tlpBRAM_mRespF
wire [138 : 0] tlp_tlpBRAM_mRespF_D_IN, tlp_tlpBRAM_mRespF_D_OUT;
wire tlp_tlpBRAM_mRespF_CLR,
tlp_tlpBRAM_mRespF_DEQ,
tlp_tlpBRAM_mRespF_EMPTY_N,
tlp_tlpBRAM_mRespF_ENQ,
tlp_tlpBRAM_mRespF_FULL_N;
// ports of submodule tlp_tlpBRAM_readReq
wire [60 : 0] tlp_tlpBRAM_readReq_D_IN, tlp_tlpBRAM_readReq_D_OUT;
wire tlp_tlpBRAM_readReq_CLR,
tlp_tlpBRAM_readReq_DEQ,
tlp_tlpBRAM_readReq_EMPTY_N,
tlp_tlpBRAM_readReq_ENQ,
tlp_tlpBRAM_readReq_FULL_N;
// ports of submodule wci_reqF
wire [71 : 0] wci_reqF_D_IN, wci_reqF_D_OUT;
wire wci_reqF_CLR, wci_reqF_DEQ, wci_reqF_EMPTY_N, wci_reqF_ENQ;
// ports of submodule wmi_wmi_dhF
wire [145 : 0] wmi_wmi_dhF_D_IN, wmi_wmi_dhF_D_OUT;
wire wmi_wmi_dhF_CLR,
wmi_wmi_dhF_DEQ,
wmi_wmi_dhF_EMPTY_N,
wmi_wmi_dhF_ENQ,
wmi_wmi_dhF_FULL_N;
// ports of submodule wmi_wmi_mFlagF
wire [31 : 0] wmi_wmi_mFlagF_D_IN, wmi_wmi_mFlagF_D_OUT;
wire wmi_wmi_mFlagF_CLR,
wmi_wmi_mFlagF_DEQ,
wmi_wmi_mFlagF_EMPTY_N,
wmi_wmi_mFlagF_ENQ,
wmi_wmi_mFlagF_FULL_N;
// ports of submodule wmi_wmi_reqF
wire [31 : 0] wmi_wmi_reqF_D_IN, wmi_wmi_reqF_D_OUT;
wire wmi_wmi_reqF_CLR,
wmi_wmi_reqF_DEQ,
wmi_wmi_reqF_EMPTY_N,
wmi_wmi_reqF_ENQ,
wmi_wmi_reqF_FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_bml_remAdvance,
CAN_FIRE_RL_tlp_dmaRespBodyFarMeta,
CAN_FIRE_RL_tlp_dmaTailEventSender,
CAN_FIRE_RL_tlp_dmaXmtMetaBody,
CAN_FIRE_RL_tlp_tlpRcv,
CAN_FIRE_RL_wmi_doWriteReq,
CAN_FIRE_RL_wmi_getRequest,
CAN_FIRE_RL_wmi_reqMetadata,
CAN_FIRE_RL_wmi_respMetadata,
WILL_FIRE_RL_bml_crdAdvance,
WILL_FIRE_RL_bml_fba,
WILL_FIRE_RL_bml_initAccumulators,
WILL_FIRE_RL_bml_lclAdvance,
WILL_FIRE_RL_bml_lcredit,
WILL_FIRE_RL_bml_remAdvance,
WILL_FIRE_RL_bram_0_serverAdapterA_outData_enqAndDeq,
WILL_FIRE_RL_bram_0_serverAdapterB_outData_enqAndDeq,
WILL_FIRE_RL_bram_1_serverAdapterA_outData_enqAndDeq,
WILL_FIRE_RL_bram_1_serverAdapterB_outData_enqAndDeq,
WILL_FIRE_RL_bram_2_serverAdapterA_outData_enqAndDeq,
WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq,
WILL_FIRE_RL_bram_2_serverAdapterB_outData_enqAndDeq,
WILL_FIRE_RL_bram_3_serverAdapterA_outData_enqAndDeq,
WILL_FIRE_RL_bram_3_serverAdapterB_outData_enqAndDeq,
WILL_FIRE_RL_tlp_dataXmt_Body,
WILL_FIRE_RL_tlp_dataXmt_Header,
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg,
WILL_FIRE_RL_tlp_dmaPullResponseBody,
WILL_FIRE_RL_tlp_dmaPullResponseHeader,
WILL_FIRE_RL_tlp_dmaPullTailEvent,
WILL_FIRE_RL_tlp_dmaPushRequestMesg,
WILL_FIRE_RL_tlp_dmaPushResponseBody,
WILL_FIRE_RL_tlp_dmaPushResponseHeader,
WILL_FIRE_RL_tlp_dmaRequestFarMeta,
WILL_FIRE_RL_tlp_dmaRequestNearMeta,
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta,
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta,
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody,
WILL_FIRE_RL_tlp_dmaResponseNearMetaHead,
WILL_FIRE_RL_tlp_dmaTailEventSender,
WILL_FIRE_RL_tlp_dmaXmtDoorbell,
WILL_FIRE_RL_tlp_dmaXmtMetaBody,
WILL_FIRE_RL_tlp_dmaXmtMetaHead,
WILL_FIRE_RL_tlp_dmaXmtTailEvent,
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq,
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp,
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq,
WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp,
WILL_FIRE_RL_tlp_tlpBRAM_writeData,
WILL_FIRE_RL_tlp_tlpBRAM_writeReq,
WILL_FIRE_RL_tlp_tlpRcv,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctl_op_complete,
WILL_FIRE_RL_wci_ctl_op_start,
WILL_FIRE_RL_wci_respF_both,
WILL_FIRE_RL_wci_respF_decCtr,
WILL_FIRE_RL_wci_respF_incCtr,
WILL_FIRE_RL_wmi_doReadReq,
WILL_FIRE_RL_wmi_doReadResp,
WILL_FIRE_RL_wmi_doWriteFinalize,
WILL_FIRE_RL_wmi_doWriteReq,
WILL_FIRE_RL_wmi_getRequest,
WILL_FIRE_RL_wmi_reqMetadata,
WILL_FIRE_RL_wmi_respMetadata,
WILL_FIRE_RL_wmi_wmi_dhF_reset,
WILL_FIRE_RL_wmi_wmi_mFlagF_reset,
WILL_FIRE_RL_wmi_wmi_reqF_reset,
WILL_FIRE_RL_wmi_wmi_respF_both,
WILL_FIRE_RL_wmi_wmi_respF_decCtr,
WILL_FIRE_RL_wmi_wmi_respF_incCtr;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_respF_q_0_write_1__VAL_2;
reg [10 : 0] MUX_bram_0_memory_a_put_2__VAL_1,
MUX_bram_0_memory_a_put_2__VAL_4,
MUX_bram_1_memory_a_put_2__VAL_1,
MUX_bram_1_memory_a_put_2__VAL_4,
MUX_bram_2_memory_a_put_2__VAL_1,
MUX_bram_2_memory_a_put_2__VAL_4,
MUX_bram_3_memory_a_put_2__VAL_1,
MUX_bram_3_memory_a_put_2__VAL_4;
wire [152 : 0] MUX_tlp_outF_enq_1__VAL_1,
MUX_tlp_outF_enq_1__VAL_2,
MUX_tlp_outF_enq_1__VAL_3,
MUX_tlp_outF_enq_1__VAL_4,
MUX_tlp_outF_enq_1__VAL_5,
MUX_tlp_outF_enq_1__VAL_6,
MUX_tlp_outF_enq_1__VAL_7,
MUX_tlp_outF_enq_1__VAL_8;
wire [138 : 0] MUX_tlp_tlpBRAM_mRespF_enq_1__VAL_1,
MUX_tlp_tlpBRAM_mRespF_enq_1__VAL_2;
wire [129 : 0] MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_1,
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_2,
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_3,
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_4,
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_5,
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_6,
MUX_wmi_wmi_respF_q_0_write_1__VAL_1,
MUX_wmi_wmi_respF_q_0_write_1__VAL_2,
MUX_wmi_wmi_respF_q_1_write_1__VAL_1;
wire [128 : 0] MUX_tlp_fabMeta_write_1__VAL_1,
MUX_tlp_fabMeta_write_1__VAL_3,
MUX_wmi_mesgMeta_write_1__VAL_2;
wire [33 : 0] MUX_wci_respF_q_0_write_1__VAL_1,
MUX_wci_respF_q_1_write_1__VAL_1,
MUX_wci_respF_x_wire_wset_1__VAL_1,
MUX_wci_respF_x_wire_wset_1__VAL_2;
wire [31 : 0] MUX_bml_fabFlowAddr_write_1__VAL_1,
MUX_bml_fabFlowAddr_write_1__VAL_3,
MUX_bml_fabMesgAddr_write_1__VAL_1,
MUX_bml_fabMetaAddr_write_1__VAL_1,
MUX_bram_0_memory_a_put_3__VAL_1,
MUX_bram_0_memory_a_put_3__VAL_2,
MUX_bram_1_memory_a_put_3__VAL_1,
MUX_bram_2_memory_a_put_3__VAL_1,
MUX_bram_3_memory_a_put_3__VAL_1,
MUX_tlp_fabMesgAccu_write_1__VAL_2,
MUX_tlp_fabMesgAccu_write_1__VAL_3,
MUX_tlp_srcMesgAccu_write_1__VAL_2,
MUX_wmi_mesgCount_write_1__VAL_1;
wire [16 : 0] MUX_tlp_mesgComplReceived_write_1__VAL_1,
MUX_tlp_mesgComplReceived_write_1__VAL_2,
MUX_tlp_mesgLengthRemainPull_write_1__VAL_1,
MUX_tlp_mesgLengthRemainPull_write_1__VAL_2,
MUX_tlp_mesgLengthRemainPull_write_1__VAL_3,
MUX_tlp_mesgLengthRemainPush_write_1__VAL_1,
MUX_tlp_mesgLengthRemainPush_write_1__VAL_2,
MUX_tlp_mesgLengthRemainPush_write_1__VAL_3;
wire [15 : 0] MUX_bml_crdBuf_value_write_1__VAL_3,
MUX_bml_fabBuf_value_write_1__VAL_3,
MUX_bml_fabBufsAvail_write_1__VAL_1,
MUX_bml_fabBufsAvail_write_1__VAL_2,
MUX_bml_lclBuf_value_write_1__VAL_3,
MUX_bml_lclBufsAR_write_1__VAL_1,
MUX_bml_lclBufsAR_write_1__VAL_2,
MUX_bml_lclBufsCF_write_1__VAL_1,
MUX_bml_lclBufsCF_write_1__VAL_2,
MUX_bml_lclCredit_write_1__VAL_1,
MUX_bml_lclMesgAddr_write_1__VAL_2,
MUX_bml_lclMetaAddr_write_1__VAL_2,
MUX_bml_remBuf_value_write_1__VAL_3,
MUX_bml_remMesgAddr_write_1__VAL_2,
MUX_bml_remMetaAddr_write_1__VAL_2,
MUX_tlp_remMesgAccu_write_1__VAL_2,
MUX_tlp_remMesgAccu_write_1__VAL_3;
wire [13 : 0] MUX_wmi_addr_write_1__VAL_1,
MUX_wmi_bytesRemainReq_write_1__VAL_1,
MUX_wmi_bytesRemainReq_write_1__VAL_2,
MUX_wmi_bytesRemainResp_write_1__VAL_2;
wire [12 : 0] MUX_tlp_tlpBRAM_readNxtDWAddr_write_1__VAL_1,
MUX_tlp_tlpBRAM_readNxtDWAddr_write_1__VAL_2,
MUX_tlp_tlpBRAM_writeDWAddr_write_1__VAL_1,
MUX_tlp_tlpBRAM_writeDWAddr_write_1__VAL_2;
wire [10 : 0] MUX_bram_0_memory_b_put_2__VAL_2;
wire [9 : 0] MUX_tlp_dmaPullRemainDWLen_write_1__VAL_2,
MUX_tlp_dmaPullRemainDWLen_write_1__VAL_3,
MUX_tlp_dmaPullRemainDWSub_write_1__VAL_1,
MUX_tlp_dmaPullRemainDWSub_write_1__VAL_2,
MUX_tlp_outDwRemain_write_1__VAL_1,
MUX_tlp_outDwRemain_write_1__VAL_2,
MUX_tlp_outDwRemain_write_1__VAL_3,
MUX_tlp_tlpBRAM_rdRespDwRemain_write_1__VAL_1,
MUX_tlp_tlpBRAM_rdRespDwRemain_write_1__VAL_2,
MUX_tlp_tlpBRAM_readRemainDWLen_write_1__VAL_1,
MUX_tlp_tlpBRAM_readRemainDWLen_write_1__VAL_2,
MUX_tlp_tlpBRAM_writeRemainDWLen_write_1__VAL_1,
MUX_tlp_tlpBRAM_writeRemainDWLen_write_1__VAL_2;
wire [3 : 0] MUX_tlp_doorSeqDwell_write_1__VAL_1,
MUX_tlp_lastRuleFired_write_1__VAL_3,
MUX_tlp_postSeqDwell_write_1__VAL_1,
MUX_tlp_postSeqDwell_write_1__VAL_2;
wire [1 : 0] MUX_wci_respF_cntr_r_write_1__VAL_2,
MUX_wmi_bufDwell_write_1__VAL_3,
MUX_wmi_wmi_respF_cntr_r_write_1__VAL_2;
wire MUX_bml_fabBufsAvail_write_1__SEL_1,
MUX_bml_fabFlowAddr_write_1__SEL_1,
MUX_bml_lclBufsAR_write_1__SEL_1,
MUX_bml_lclBufsCF_write_1__SEL_1,
MUX_bml_lclCredit_write_1__SEL_1,
MUX_bram_0_memory_a_put_1__SEL_1,
MUX_bram_0_memory_a_put_1__SEL_2,
MUX_bram_0_memory_a_put_1__SEL_3,
MUX_bram_0_serverAdapterB_writeWithResp_wset_1__SEL_1,
MUX_bram_1_memory_a_put_1__SEL_1,
MUX_bram_1_memory_a_put_1__SEL_2,
MUX_bram_1_memory_a_put_1__SEL_3,
MUX_bram_2_memory_a_put_1__SEL_1,
MUX_bram_2_memory_a_put_1__SEL_2,
MUX_bram_2_memory_a_put_1__SEL_3,
MUX_bram_3_memory_a_put_1__SEL_1,
MUX_bram_3_memory_a_put_1__SEL_2,
MUX_bram_3_memory_a_put_1__SEL_3,
MUX_tlp_dmaDoTailEvent_write_1__VAL_1,
MUX_tlp_fabMesgAccu_write_1__SEL_1,
MUX_tlp_fabMeta_write_1__SEL_2,
MUX_tlp_remDone_1_wset_1__SEL_1,
MUX_tlp_reqMesgInFlight_write_1__VAL_2,
MUX_tlp_tailEventF_enq_1__SEL_1,
MUX_tlp_tlpBRAM_mReqF_enq_1__SEL_1,
MUX_tlp_tlpBRAM_mReqF_enq_1__SEL_2,
MUX_tlp_tlpBRAM_readHeaderSent_write_1__SEL_1,
MUX_tlp_tlpBRAM_readStarted_write_1__SEL_1,
MUX_tlp_tlpXmtBusy_write_1__PSEL_2,
MUX_tlp_tlpXmtBusy_write_1__SEL_1,
MUX_tlp_tlpXmtBusy_write_1__SEL_2,
MUX_tlp_tlpXmtBusy_write_1__SEL_3,
MUX_tlp_tlpXmtBusy_write_1__SEL_4,
MUX_tlp_tlpXmtBusy_write_1__VAL_1,
MUX_tlp_xmtMetaOK_write_1__SEL_3,
MUX_tlp_xmtMetaOK_write_1__SEL_4,
MUX_wci_illegalEdge_write_1__SEL_1,
MUX_wci_illegalEdge_write_1__SEL_2,
MUX_wci_illegalEdge_write_1__VAL_2,
MUX_wci_respF_q_0_write_1__SEL_1,
MUX_wci_respF_q_0_write_1__SEL_2,
MUX_wci_respF_q_1_write_1__SEL_1,
MUX_wci_respF_q_1_write_1__SEL_2,
MUX_wmi_bufDwell_write_1__SEL_1,
MUX_wmi_bytesRemainResp_write_1__SEL_1,
MUX_wmi_doneWithMesg_write_1__PSEL_1,
MUX_wmi_doneWithMesg_write_1__SEL_1,
MUX_wmi_rdActive_write_1__SEL_1,
MUX_wmi_wmi_dhF_levelsValid_write_1__SEL_2,
MUX_wmi_wmi_mFlagF_levelsValid_write_1__SEL_2,
MUX_wmi_wmi_reqF_levelsValid_write_1__SEL_2,
MUX_wmi_wmi_respF_q_0_write_1__SEL_1,
MUX_wmi_wmi_respF_q_0_write_1__SEL_2,
MUX_wmi_wmi_respF_q_1_write_1__SEL_1,
MUX_wmi_wmi_respF_q_1_write_1__SEL_2,
MUX_wmi_wrActive_write_1__SEL_1,
MUX_wmi_wrFinalize_write_1__SEL_1;
// remaining internal signals
reg [63 : 0] v__h15577,
v__h15752,
v__h15896,
v__h41005,
v__h43090,
v__h47450,
v__h47790,
v__h48409,
v__h48757,
v__h50007,
v__h56382,
v__h56506,
v__h56714,
v__h57177,
v__h59442,
v__h63835,
v__h64356,
v__h65011,
v__h65359,
v__h65522,
v__h70765,
v__h82455,
v__h91331,
v__h91800,
v__h91963;
reg [31 : 0] SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863,
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700,
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708,
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716,
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724,
_theResult____h91947;
reg [15 : 0] CASE_tlp_outDwRemain_BITS_1_TO_0_0b0_0xFFFF_0b_ETC__q3;
reg [3 : 0] CASE_tlp_lastRuleFired_1_tlp_lastRuleFired_2_t_ETC__q1;
reg [1 : 0] lowAddr10__h29651, x__h29780, x__h29803;
reg CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q5,
CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q6,
CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_IF__ETC__q7,
CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_bml_ETC__q4,
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_30_TO_29_ETC___d736,
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_51_TO_50_ETC___d623,
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d805,
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d810,
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665,
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669,
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673,
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677;
wire [127 : 0] IF_tlp_fabMesgAddrMS_078_EQ_0_079_THEN_0_ELSE__ETC___d1353,
IF_tlp_fabMetaAddrMS_157_EQ_0_158_THEN_4_ELSE__ETC___d1248,
IF_tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_ETC___d929,
IF_tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_ETC___d934,
pkt__h71785,
rdata__h35173,
rdata__h83703,
w_data__h47916,
w_data__h48052,
w_data__h52877,
w_data__h65836,
w_data__h66940,
w_data__h67186;
wire [63 : 0] wti_nowReq_BITS_63_TO_0__q2;
wire [31 : 0] bml_fabFlowAddr_937_PLUS_bml_fabFlowSize_938___d1939,
mesgMeta_opcode__h81853,
nowLS__h46239,
nowLS__h62622,
nowMS__h45280,
nowMS__h61665,
opcode__h44022,
opcode__h60417,
rdat__h92026,
rdat__h92034,
rdat__h92042,
rdat__h92050,
rdat__h92058,
rdat__h92066,
rdat__h92074,
rdat__h92095,
rdat__h92102,
rdat__h92115,
rdat__h92122,
rdat__h92129,
rdat__h92401,
rdat__h92451,
rdat__h92551,
rdat__h92609,
rdat__h92631,
rdat__h92641,
rdat__h92763,
rdat__h92887,
rdat__h92915,
rdat__h92943,
rdat__h92971,
rdat__h93001,
rdat__h93035,
rdat__h93068,
rdat__h93102,
rresp_data__h29698,
x3__h81813,
x__h42208,
x__h47258,
x__h58352,
x__h63608,
y__h47623,
y__h48181,
y__h63989;
wire [16 : 0] tlp_mesgLengthRemainPull_PLUS_3__q14,
tlp_mesgLengthRemainPush_PLUS_3__q15,
x__h47542,
x__h63926,
y__h47529,
y__h47544,
y__h63918,
y__h63928,
y__h65310;
wire [15 : 0] w_be__h48508,
x__h88675,
x__h89803,
x__h89808,
x__h89915,
x__h89952,
x__h90034,
x__h90039,
x__h90073,
x__h90078,
y__h47671,
y__h64598;
wire [12 : 0] spanToNextPage__h47503,
spanToNextPage__h63892,
thisRequestLength__h47504,
thisRequestLength__h63893,
tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11,
tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12,
tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13,
tlp_tlpBRAM_writeDWAddr_PLUS_1__q8,
tlp_tlpBRAM_writeDWAddr_PLUS_2__q9,
tlp_tlpBRAM_writeDWAddr_PLUS_3__q10,
y__h17362,
y__h27665;
wire [11 : 0] byteCount__h29653, x__h29771, x__h29773, y__h29772, y__h29774;
wire [9 : 0] y__h17428, y__h27653, y__h30729, y__h48147;
wire [7 : 0] rreq_tag__h47719, tag__h64168, tagm__h64387;
wire [6 : 0] lowAddr__h29652;
wire [3 : 0] lastBE__h47950, lastBE__h64200;
wire [2 : 0] bram_0_serverAdapterA_cnt_6_PLUS_IF_bram_0_ser_ETC___d32,
bram_0_serverAdapterB_cnt_5_PLUS_IF_bram_0_ser_ETC___d91,
bram_1_serverAdapterA_cnt_44_PLUS_IF_bram_1_se_ETC___d150,
bram_1_serverAdapterB_cnt_03_PLUS_IF_bram_1_se_ETC___d209,
bram_2_serverAdapterA_cnt_62_PLUS_IF_bram_2_se_ETC___d268,
bram_2_serverAdapterB_cnt_21_PLUS_IF_bram_2_se_ETC___d327,
bram_3_serverAdapterA_cnt_80_PLUS_IF_bram_3_se_ETC___d386,
bram_3_serverAdapterB_cnt_39_PLUS_IF_bram_3_se_ETC___d445;
wire [1 : 0] ab__h10465,
ab__h11870,
ab__h1619,
ab__h3026,
ab__h4569,
ab__h5974,
ab__h7517,
ab__h8922,
idx__h21626,
idx__h23676,
idx__h24781,
idx__h25886,
idx__h27879,
idx__h28282,
idx__h28586,
idx__h28890,
tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_00_ETC___d922,
wci_respF_cntr_r_90_MINUS_1___d499,
wmi_wmi_respF_cntr_r_582_MINUS_1___d1590;
wire IF_bml_dpControl_wget__898_BITS_1_TO_0_904_EQ__ETC___d1984,
IF_bml_dpControl_wget__898_BITS_3_TO_2_899_EQ__ETC___d1995,
NOT_SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_5_ETC___d681,
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656,
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658,
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660,
NOT_wmi_wrActive_717_718_OR_NOT_wmi_rdActive_7_ETC___d1727,
_dfoo1,
_dfoo3,
_dfoo5,
_dfoo7,
_dfoo9,
bml_crdBuf_value_880_EQ_bml_crdBuf_modulus_bw__ETC___d1882,
bml_fabBuf_value_865_EQ_bml_fabBuf_modulus_bw__ETC___d1867,
bml_lclBufDone_922_AND_IF_bml_dpControl_wget___ETC___d2003,
bml_lclBuf_value_835_EQ_bml_lclBuf_modulus_bw__ETC___d1837,
bml_remBuf_value_850_EQ_bml_remBuf_modulus_bw__ETC___d1852,
bram_0_serverAdapterA_cnt_6_SLT_3___d619,
bram_0_serverAdapterA_outDataCore_notEmpty_OR__ETC___d887,
bram_0_serverAdapterB_cnt_5_SLT_3_666_AND_bram_ETC___d1672,
bram_0_serverAdapterB_cnt_5_SLT_3___d1666,
bram_0_serverAdapterB_outData_outData_whas__68_ETC___d1697,
bram_1_serverAdapterA_cnt_44_SLT_3___d620,
bram_1_serverAdapterB_cnt_03_SLT_3___d1667,
bram_1_serverAdapterB_outData_outData_whas__68_ETC___d1695,
bram_2_serverAdapterA_cnt_62_SLT_3___d621,
bram_2_serverAdapterA_outDataCore_notEmpty__38_ETC___d885,
bram_2_serverAdapterB_cnt_21_SLT_3___d1668,
bram_3_serverAdapterA_cnt_80_SLT_3___d622,
bram_3_serverAdapterB_cnt_39_SLT_3___d1669,
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1233,
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1274,
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1326,
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1365,
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1385,
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1410,
hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1058,
hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1098,
hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1155,
hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d985,
tlp_dmaPullRemainDWLen_373_ULE_tlp_dmaPullRema_ETC___d1395,
tlp_dmaPullRemainDWSub_387_ULE_4___d1388,
tlp_inF_first__259_BITS_63_TO_56_262_EQ_pciDev_ETC___d1272,
tlp_inF_first__259_BIT_152_462_AND_NOT_tlp_inF_ETC___d1487,
tlp_outDwRemain_129_ULE_4___d1130,
tlp_tlpBRAM_mRespF_first__000_BITS_71_TO_62_10_ETC___d1102,
tlp_tlpBRAM_mRespF_i_notFull__97_AND_tlp_tlpBR_ETC___d813,
tlp_tlpBRAM_rdRespDwRemain_16_ULE_4___d918,
tlp_tlpBRAM_readRemainDWLen_74_ULE_4___d775,
wmi_wmi_operateD_606_AND_wmi_wmi_peerIsReady_6_ETC___d1777,
wmi_wmi_operateD_606_AND_wmi_wmi_peerIsReady_6_ETC___d1798;
// value method wci_s_sResp
assign wci_s_SResp = wci_respF_q_0[33:32] ;
// value method wci_s_sData
assign wci_s_SData = wci_respF_q_0[31:0] ;
// value method wci_s_sThreadBusy
assign wci_s_SThreadBusy =
wci_reqF_countReg > 2'd1 || wci_isReset_isInReset ;
// value method wci_s_sFlag
assign wci_s_SFlag = { 1'd1, wci_sFlagReg } ;
// value method wti_s_sThreadBusy
assign wti_s_SThreadBusy = wti_isReset_isInReset ;
// value method wti_s_sReset_n
assign wti_s_SReset_n = !wti_isReset_isInReset && wti_operateD ;
// value method wmiS0_sResp
assign wmiS0_SResp = wmi_wmi_respF_q_0[129:128] ;
// value method wmiS0_sData
assign wmiS0_SData = wmi_wmi_respF_q_0[127:0] ;
// value method wmiS0_sThreadBusy
assign wmiS0_SThreadBusy =
!wmi_wmi_sThreadBusy_dw_whas || wmi_wmi_sThreadBusy_dw_wget ;
// value method wmiS0_sDataThreadBusy
assign wmiS0_SDataThreadBusy =
!wmi_wmi_sDataThreadBusy_dw_whas ||
wmi_wmi_sDataThreadBusy_dw_wget ;
// value method wmiS0_sRespLast
assign wmiS0_SRespLast = 1'd0 ;
// value method wmiS0_sFlag
assign wmiS0_SFlag = wmi_wmi_sFlagReg ;
// value method wmiS0_sReset_n
assign wmiS0_SReset_n = !wmi_wmi_isReset_isInReset && wmi_wmi_operateD ;
// action method server_request_put
assign RDY_server_request_put = tlp_inF_FULL_N ;
// actionvalue method server_response_get
assign server_response_get = tlp_outF_D_OUT ;
assign RDY_server_response_get = tlp_outF_EMPTY_N ;
// submodule bram_0_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd11),
.DATA_WIDTH(32'd32),
.MEMSIZE(12'd2048)) bram_0_memory(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(bram_0_memory_ADDRA),
.ADDRB(bram_0_memory_ADDRB),
.DIA(bram_0_memory_DIA),
.DIB(bram_0_memory_DIB),
.WEA(bram_0_memory_WEA),
.WEB(bram_0_memory_WEB),
.ENA(bram_0_memory_ENA),
.ENB(bram_0_memory_ENB),
.DOA(bram_0_memory_DOA),
.DOB(bram_0_memory_DOB));
// submodule bram_0_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) bram_0_serverAdapterA_outDataCore(.RST(RST_N),
.CLK(CLK),
.D_IN(bram_0_serverAdapterA_outDataCore_D_IN),
.ENQ(bram_0_serverAdapterA_outDataCore_ENQ),
.DEQ(bram_0_serverAdapterA_outDataCore_DEQ),
.CLR(bram_0_serverAdapterA_outDataCore_CLR),
.D_OUT(bram_0_serverAdapterA_outDataCore_D_OUT),
.FULL_N(bram_0_serverAdapterA_outDataCore_FULL_N),
.EMPTY_N(bram_0_serverAdapterA_outDataCore_EMPTY_N));
// submodule bram_0_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) bram_0_serverAdapterB_outDataCore(.RST(RST_N),
.CLK(CLK),
.D_IN(bram_0_serverAdapterB_outDataCore_D_IN),
.ENQ(bram_0_serverAdapterB_outDataCore_ENQ),
.DEQ(bram_0_serverAdapterB_outDataCore_DEQ),
.CLR(bram_0_serverAdapterB_outDataCore_CLR),
.D_OUT(bram_0_serverAdapterB_outDataCore_D_OUT),
.FULL_N(bram_0_serverAdapterB_outDataCore_FULL_N),
.EMPTY_N(bram_0_serverAdapterB_outDataCore_EMPTY_N));
// submodule bram_1_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd11),
.DATA_WIDTH(32'd32),
.MEMSIZE(12'd2048)) bram_1_memory(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(bram_1_memory_ADDRA),
.ADDRB(bram_1_memory_ADDRB),
.DIA(bram_1_memory_DIA),
.DIB(bram_1_memory_DIB),
.WEA(bram_1_memory_WEA),
.WEB(bram_1_memory_WEB),
.ENA(bram_1_memory_ENA),
.ENB(bram_1_memory_ENB),
.DOA(bram_1_memory_DOA),
.DOB(bram_1_memory_DOB));
// submodule bram_1_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) bram_1_serverAdapterA_outDataCore(.RST(RST_N),
.CLK(CLK),
.D_IN(bram_1_serverAdapterA_outDataCore_D_IN),
.ENQ(bram_1_serverAdapterA_outDataCore_ENQ),
.DEQ(bram_1_serverAdapterA_outDataCore_DEQ),
.CLR(bram_1_serverAdapterA_outDataCore_CLR),
.D_OUT(bram_1_serverAdapterA_outDataCore_D_OUT),
.FULL_N(bram_1_serverAdapterA_outDataCore_FULL_N),
.EMPTY_N(bram_1_serverAdapterA_outDataCore_EMPTY_N));
// submodule bram_1_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) bram_1_serverAdapterB_outDataCore(.RST(RST_N),
.CLK(CLK),
.D_IN(bram_1_serverAdapterB_outDataCore_D_IN),
.ENQ(bram_1_serverAdapterB_outDataCore_ENQ),
.DEQ(bram_1_serverAdapterB_outDataCore_DEQ),
.CLR(bram_1_serverAdapterB_outDataCore_CLR),
.D_OUT(bram_1_serverAdapterB_outDataCore_D_OUT),
.FULL_N(bram_1_serverAdapterB_outDataCore_FULL_N),
.EMPTY_N(bram_1_serverAdapterB_outDataCore_EMPTY_N));
// submodule bram_2_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd11),
.DATA_WIDTH(32'd32),
.MEMSIZE(12'd2048)) bram_2_memory(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(bram_2_memory_ADDRA),
.ADDRB(bram_2_memory_ADDRB),
.DIA(bram_2_memory_DIA),
.DIB(bram_2_memory_DIB),
.WEA(bram_2_memory_WEA),
.WEB(bram_2_memory_WEB),
.ENA(bram_2_memory_ENA),
.ENB(bram_2_memory_ENB),
.DOA(bram_2_memory_DOA),
.DOB(bram_2_memory_DOB));
// submodule bram_2_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) bram_2_serverAdapterA_outDataCore(.RST(RST_N),
.CLK(CLK),
.D_IN(bram_2_serverAdapterA_outDataCore_D_IN),
.ENQ(bram_2_serverAdapterA_outDataCore_ENQ),
.DEQ(bram_2_serverAdapterA_outDataCore_DEQ),
.CLR(bram_2_serverAdapterA_outDataCore_CLR),
.D_OUT(bram_2_serverAdapterA_outDataCore_D_OUT),
.FULL_N(bram_2_serverAdapterA_outDataCore_FULL_N),
.EMPTY_N(bram_2_serverAdapterA_outDataCore_EMPTY_N));
// submodule bram_2_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) bram_2_serverAdapterB_outDataCore(.RST(RST_N),
.CLK(CLK),
.D_IN(bram_2_serverAdapterB_outDataCore_D_IN),
.ENQ(bram_2_serverAdapterB_outDataCore_ENQ),
.DEQ(bram_2_serverAdapterB_outDataCore_DEQ),
.CLR(bram_2_serverAdapterB_outDataCore_CLR),
.D_OUT(bram_2_serverAdapterB_outDataCore_D_OUT),
.FULL_N(bram_2_serverAdapterB_outDataCore_FULL_N),
.EMPTY_N(bram_2_serverAdapterB_outDataCore_EMPTY_N));
// submodule bram_3_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd11),
.DATA_WIDTH(32'd32),
.MEMSIZE(12'd2048)) bram_3_memory(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(bram_3_memory_ADDRA),
.ADDRB(bram_3_memory_ADDRB),
.DIA(bram_3_memory_DIA),
.DIB(bram_3_memory_DIB),
.WEA(bram_3_memory_WEA),
.WEB(bram_3_memory_WEB),
.ENA(bram_3_memory_ENA),
.ENB(bram_3_memory_ENB),
.DOA(bram_3_memory_DOA),
.DOB(bram_3_memory_DOB));
// submodule bram_3_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) bram_3_serverAdapterA_outDataCore(.RST(RST_N),
.CLK(CLK),
.D_IN(bram_3_serverAdapterA_outDataCore_D_IN),
.ENQ(bram_3_serverAdapterA_outDataCore_ENQ),
.DEQ(bram_3_serverAdapterA_outDataCore_DEQ),
.CLR(bram_3_serverAdapterA_outDataCore_CLR),
.D_OUT(bram_3_serverAdapterA_outDataCore_D_OUT),
.FULL_N(bram_3_serverAdapterA_outDataCore_FULL_N),
.EMPTY_N(bram_3_serverAdapterA_outDataCore_EMPTY_N));
// submodule bram_3_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) bram_3_serverAdapterB_outDataCore(.RST(RST_N),
.CLK(CLK),
.D_IN(bram_3_serverAdapterB_outDataCore_D_IN),
.ENQ(bram_3_serverAdapterB_outDataCore_ENQ),
.DEQ(bram_3_serverAdapterB_outDataCore_DEQ),
.CLR(bram_3_serverAdapterB_outDataCore_CLR),
.D_OUT(bram_3_serverAdapterB_outDataCore_D_OUT),
.FULL_N(bram_3_serverAdapterB_outDataCore_FULL_N),
.EMPTY_N(bram_3_serverAdapterB_outDataCore_EMPTY_N));
// submodule tlp_inF
arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) tlp_inF(.CLK(CLK),
.RST_N(RST_N),
.D_IN(tlp_inF_D_IN),
.DEQ(tlp_inF_DEQ),
.ENQ(tlp_inF_ENQ),
.CLR(tlp_inF_CLR),
.D_OUT(tlp_inF_D_OUT),
.EMPTY_N(tlp_inF_EMPTY_N),
.FULL_N(tlp_inF_FULL_N));
// submodule tlp_outF
arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) tlp_outF(.CLK(CLK),
.RST_N(RST_N),
.D_IN(tlp_outF_D_IN),
.DEQ(tlp_outF_DEQ),
.ENQ(tlp_outF_ENQ),
.CLR(tlp_outF_CLR),
.D_OUT(tlp_outF_D_OUT),
.EMPTY_N(tlp_outF_EMPTY_N),
.FULL_N(tlp_outF_FULL_N));
// submodule tlp_tailEventF
FIFO2 #(.width(32'd1), .guarded(32'd1)) tlp_tailEventF(.RST(RST_N),
.CLK(CLK),
.D_IN(tlp_tailEventF_D_IN),
.ENQ(tlp_tailEventF_ENQ),
.DEQ(tlp_tailEventF_DEQ),
.CLR(tlp_tailEventF_CLR),
.D_OUT(tlp_tailEventF_D_OUT),
.FULL_N(tlp_tailEventF_FULL_N),
.EMPTY_N(tlp_tailEventF_EMPTY_N));
// submodule tlp_tlpBRAM_mReqF
FIFO2 #(.width(32'd130), .guarded(32'd1)) tlp_tlpBRAM_mReqF(.RST(RST_N),
.CLK(CLK),
.D_IN(tlp_tlpBRAM_mReqF_D_IN),
.ENQ(tlp_tlpBRAM_mReqF_ENQ),
.DEQ(tlp_tlpBRAM_mReqF_DEQ),
.CLR(tlp_tlpBRAM_mReqF_CLR),
.D_OUT(tlp_tlpBRAM_mReqF_D_OUT),
.FULL_N(tlp_tlpBRAM_mReqF_FULL_N),
.EMPTY_N(tlp_tlpBRAM_mReqF_EMPTY_N));
// submodule tlp_tlpBRAM_mRespF
FIFO2 #(.width(32'd139), .guarded(32'd1)) tlp_tlpBRAM_mRespF(.RST(RST_N),
.CLK(CLK),
.D_IN(tlp_tlpBRAM_mRespF_D_IN),
.ENQ(tlp_tlpBRAM_mRespF_ENQ),
.DEQ(tlp_tlpBRAM_mRespF_DEQ),
.CLR(tlp_tlpBRAM_mRespF_CLR),
.D_OUT(tlp_tlpBRAM_mRespF_D_OUT),
.FULL_N(tlp_tlpBRAM_mRespF_FULL_N),
.EMPTY_N(tlp_tlpBRAM_mRespF_EMPTY_N));
// submodule tlp_tlpBRAM_readReq
FIFO2 #(.width(32'd61), .guarded(32'd1)) tlp_tlpBRAM_readReq(.RST(RST_N),
.CLK(CLK),
.D_IN(tlp_tlpBRAM_readReq_D_IN),
.ENQ(tlp_tlpBRAM_readReq_ENQ),
.DEQ(tlp_tlpBRAM_readReq_DEQ),
.CLR(tlp_tlpBRAM_readReq_CLR),
.D_OUT(tlp_tlpBRAM_readReq_D_OUT),
.FULL_N(tlp_tlpBRAM_readReq_FULL_N),
.EMPTY_N(tlp_tlpBRAM_readReq_EMPTY_N));
// submodule wci_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_reqF(.RST(RST_N),
.CLK(CLK),
.D_IN(wci_reqF_D_IN),
.ENQ(wci_reqF_ENQ),
.DEQ(wci_reqF_DEQ),
.CLR(wci_reqF_CLR),
.D_OUT(wci_reqF_D_OUT),
.FULL_N(),
.EMPTY_N(wci_reqF_EMPTY_N));
// submodule wmi_wmi_dhF
SizedFIFO #(.p1width(32'd146),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wmi_wmi_dhF(.RST(RST_N),
.CLK(CLK),
.D_IN(wmi_wmi_dhF_D_IN),
.ENQ(wmi_wmi_dhF_ENQ),
.DEQ(wmi_wmi_dhF_DEQ),
.CLR(wmi_wmi_dhF_CLR),
.D_OUT(wmi_wmi_dhF_D_OUT),
.FULL_N(wmi_wmi_dhF_FULL_N),
.EMPTY_N(wmi_wmi_dhF_EMPTY_N));
// submodule wmi_wmi_mFlagF
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wmi_wmi_mFlagF(.RST(RST_N),
.CLK(CLK),
.D_IN(wmi_wmi_mFlagF_D_IN),
.ENQ(wmi_wmi_mFlagF_ENQ),
.DEQ(wmi_wmi_mFlagF_DEQ),
.CLR(wmi_wmi_mFlagF_CLR),
.D_OUT(wmi_wmi_mFlagF_D_OUT),
.FULL_N(wmi_wmi_mFlagF_FULL_N),
.EMPTY_N(wmi_wmi_mFlagF_EMPTY_N));
// submodule wmi_wmi_reqF
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wmi_wmi_reqF(.RST(RST_N),
.CLK(CLK),
.D_IN(wmi_wmi_reqF_D_IN),
.ENQ(wmi_wmi_reqF_ENQ),
.DEQ(wmi_wmi_reqF_DEQ),
.CLR(wmi_wmi_reqF_CLR),
.D_OUT(wmi_wmi_reqF_D_OUT),
.FULL_N(wmi_wmi_reqF_FULL_N),
.EMPTY_N(wmi_wmi_reqF_EMPTY_N));
// rule RL_bram_2_serverAdapterA_outData_setFirstEnq
assign WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq =
!bram_2_serverAdapterA_outDataCore_EMPTY_N &&
bram_2_serverAdapterA_outData_enqData_whas ;
// rule RL_wci_cfrd
assign WILL_FIRE_RL_wci_cfrd =
wci_respF_cntr_r != 2'd2 && wci_reqF_EMPTY_N &&
wci_wci_cfrd_pw_whas &&
!WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctl_op_start
assign WILL_FIRE_RL_wci_ctl_op_start =
wci_reqF_EMPTY_N && wci_wci_ctrl_pw_whas &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_tlp_dmaRequestNearMeta
assign WILL_FIRE_RL_tlp_dmaRequestNearMeta =
tlp_tlpBRAM_mReqF_FULL_N &&
hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d985 &&
tlp_farBufReady &&
tlp_postSeqDwell == 4'd0 ;
// rule RL_tlp_dmaPushRequestMesg
assign WILL_FIRE_RL_tlp_dmaPushRequestMesg =
tlp_tlpBRAM_mReqF_FULL_N &&
hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1058 &&
!WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ;
// rule RL_tlp_dmaResponseNearMetaHead
assign WILL_FIRE_RL_tlp_dmaResponseNearMetaHead =
tlp_tlpBRAM_mRespF_EMPTY_N && hasPush &&
dpControl[7:4] == 4'd0 &&
dpControl[3:2] == 2'd1 &&
dpControl[1:0] == 2'd1 &&
!tlp_tlpBRAM_mRespF_D_OUT[138] &&
tlp_tlpBRAM_mRespF_D_OUT[89:88] == 2'd3 ;
// rule RL_tlp_dmaPushResponseHeader
assign WILL_FIRE_RL_tlp_dmaPushResponseHeader =
tlp_outF_FULL_N && tlp_tlpBRAM_mRespF_EMPTY_N &&
hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1098 ;
// rule RL_tlp_dmaPushResponseBody
assign WILL_FIRE_RL_tlp_dmaPushResponseBody =
tlp_outF_FULL_N && tlp_tlpBRAM_mRespF_EMPTY_N && hasPush &&
dpControl[7:4] == 4'd0 &&
dpControl[3:2] == 2'd1 &&
dpControl[1:0] == 2'd1 &&
tlp_tlpBRAM_mRespF_D_OUT[138] &&
tlp_tlpBRAM_mRespF_D_OUT[137:136] == 2'd2 ;
// rule RL_tlp_dmaXmtMetaHead
assign WILL_FIRE_RL_tlp_dmaXmtMetaHead =
tlp_outF_FULL_N &&
hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1155 &&
!WILL_FIRE_RL_tlp_dmaPushResponseBody &&
!WILL_FIRE_RL_tlp_dmaPushResponseHeader ;
// rule RL_tlp_dmaXmtTailEvent
assign WILL_FIRE_RL_tlp_dmaXmtTailEvent =
tlp_tailEventF_FULL_N && hasPush && dpControl[7:4] == 4'd0 &&
dpControl[3:2] == 2'd1 &&
dpControl[1:0] == 2'd1 &&
tlp_fabMeta[128] &&
tlp_tlpMetaSent ;
// rule RL_tlp_dmaXmtMetaBody
assign CAN_FIRE_RL_tlp_dmaXmtMetaBody =
tlp_outF_FULL_N && hasPush && dpControl[7:4] == 4'd0 &&
dpControl[3:2] == 2'd1 &&
dpControl[1:0] == 2'd1 &&
tlp_fabMeta[128] &&
tlp_doXmtMetaBody ;
assign WILL_FIRE_RL_tlp_dmaXmtMetaBody =
CAN_FIRE_RL_tlp_dmaXmtMetaBody &&
!WILL_FIRE_RL_tlp_dmaXmtMetaHead &&
!WILL_FIRE_RL_tlp_dmaPushResponseBody &&
!WILL_FIRE_RL_tlp_dmaPushResponseHeader ;
// rule RL_tlp_dmaXmtDoorbell
assign WILL_FIRE_RL_tlp_dmaXmtDoorbell =
tlp_tailEventF_FULL_N && dpControl[1:0] == 2'd2 &&
tlp_creditReady &&
tlp_doorSeqDwell == 4'd0 ;
// rule RL_tlp_dmaRespHeadFarMeta
assign WILL_FIRE_RL_tlp_dmaRespHeadFarMeta =
tlp_inF_EMPTY_N && tlp_tlpBRAM_mReqF_FULL_N &&
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1274 ;
// rule RL_tlp_dmaPullTailEvent
assign WILL_FIRE_RL_tlp_dmaPullTailEvent =
tlp_tailEventF_FULL_N &&
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1410 ;
// rule RL_tlp_dmaRespBodyFarMeta
assign CAN_FIRE_RL_tlp_dmaRespBodyFarMeta =
tlp_inF_EMPTY_N && tlp_tlpBRAM_mReqF_FULL_N && hasPull &&
dpControl[7:4] == 4'd0 &&
dpControl[3:2] == 2'd2 &&
dpControl[1:0] == 2'd1 &&
tlp_reqMetaBodyInFlight &&
!tlp_tlpRcvBusy ;
assign WILL_FIRE_RL_tlp_dmaRespBodyFarMeta =
CAN_FIRE_RL_tlp_dmaRespBodyFarMeta &&
!WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ;
// rule RL_tlp_dmaPullResponseHeader
assign WILL_FIRE_RL_tlp_dmaPullResponseHeader =
tlp_inF_EMPTY_N && tlp_tlpBRAM_mReqF_FULL_N &&
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1365 &&
!WILL_FIRE_RL_tlp_dmaRespBodyFarMeta &&
!WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ;
// rule RL_tlp_dmaPullResponseBody
assign WILL_FIRE_RL_tlp_dmaPullResponseBody =
tlp_inF_EMPTY_N && tlp_tlpBRAM_mReqF_FULL_N &&
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1385 &&
!WILL_FIRE_RL_tlp_dmaRespBodyFarMeta &&
!WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ;
// rule RL_tlp_dmaTailEventSender
assign CAN_FIRE_RL_tlp_dmaTailEventSender =
tlp_outF_FULL_N && tlp_tailEventF_EMPTY_N &&
(!tlp_tlpXmtBusy && !tlp_sentTail4DWHeader &&
tlp_postSeqDwell == 4'd0 ||
tlp_tlpXmtBusy && tlp_sentTail4DWHeader) ;
assign WILL_FIRE_RL_tlp_dmaTailEventSender =
CAN_FIRE_RL_tlp_dmaTailEventSender &&
!WILL_FIRE_RL_tlp_dmaPullRequestFarMesg &&
!WILL_FIRE_RL_tlp_dmaRequestFarMeta &&
!(tlp_postSeqDwell != 4'd0) &&
!WILL_FIRE_RL_tlp_dmaXmtMetaBody &&
!WILL_FIRE_RL_tlp_dmaXmtMetaHead &&
!WILL_FIRE_RL_tlp_dmaPushResponseBody &&
!WILL_FIRE_RL_tlp_dmaPushResponseHeader ;
// rule RL_tlp_tlpRcv
assign CAN_FIRE_RL_tlp_tlpRcv =
tlp_inF_EMPTY_N &&
(tlp_inF_D_OUT[152] ?
tlp_inF_D_OUT[110] || tlp_inF_D_OUT[125] ||
tlp_inF_D_OUT[124:120] != 5'b0 ||
tlp_tlpBRAM_mReqF_FULL_N :
tlp_inIgnorePkt || tlp_tlpBRAM_mReqF_FULL_N) &&
!tlp_reqMetaInFlight &&
!tlp_reqMesgInFlight &&
!tlp_reqMetaBodyInFlight ;
assign WILL_FIRE_RL_tlp_tlpRcv =
CAN_FIRE_RL_tlp_tlpRcv && !WILL_FIRE_RL_tlp_dmaPushRequestMesg &&
!WILL_FIRE_RL_tlp_dmaRequestNearMeta ;
// rule RL_tlp_dmaResponseNearMetaBody
assign WILL_FIRE_RL_tlp_dmaResponseNearMetaBody =
tlp_tlpBRAM_mRespF_EMPTY_N && hasPush &&
dpControl[7:4] == 4'd0 &&
dpControl[3:2] == 2'd1 &&
dpControl[1:0] == 2'd1 &&
tlp_tlpBRAM_mRespF_D_OUT[138] &&
tlp_tlpBRAM_mRespF_D_OUT[137:136] == 2'd3 ;
// rule RL_tlp_dmaRequestFarMeta
assign WILL_FIRE_RL_tlp_dmaRequestFarMeta =
tlp_outF_FULL_N &&
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1233 &&
tlp_nearBufReady &&
tlp_farBufReady &&
tlp_postSeqDwell == 4'd0 ;
// rule RL_tlp_dmaPullRequestFarMesg
assign WILL_FIRE_RL_tlp_dmaPullRequestFarMesg =
tlp_outF_FULL_N &&
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1326 &&
!WILL_FIRE_RL_tlp_dmaRespBodyFarMeta &&
!WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ;
// rule RL_tlp_dataXmt_Header
assign WILL_FIRE_RL_tlp_dataXmt_Header =
tlp_outF_FULL_N && tlp_tlpBRAM_mRespF_EMPTY_N &&
!tlp_tlpBRAM_mRespF_D_OUT[138] &&
tlp_tlpBRAM_mRespF_D_OUT[89:88] == 2'd1 &&
!tlp_tlpXmtBusy &&
!WILL_FIRE_RL_tlp_dmaTailEventSender &&
!WILL_FIRE_RL_tlp_dmaPullRequestFarMesg &&
!WILL_FIRE_RL_tlp_dmaRequestFarMeta &&
!WILL_FIRE_RL_tlp_dmaXmtMetaBody &&
!WILL_FIRE_RL_tlp_dmaXmtMetaHead ;
// rule RL_tlp_dataXmt_Body
assign WILL_FIRE_RL_tlp_dataXmt_Body =
tlp_outF_FULL_N && tlp_tlpBRAM_mRespF_EMPTY_N &&
tlp_tlpBRAM_mRespF_D_OUT[138] &&
tlp_tlpBRAM_mRespF_D_OUT[137:136] == 2'd1 &&
!WILL_FIRE_RL_tlp_dmaTailEventSender &&
!WILL_FIRE_RL_tlp_dmaPullRequestFarMesg &&
!WILL_FIRE_RL_tlp_dmaRequestFarMeta &&
!WILL_FIRE_RL_tlp_dmaXmtMetaBody &&
!WILL_FIRE_RL_tlp_dmaXmtMetaHead ;
// rule RL_tlp_tlpBRAM_writeReq
assign WILL_FIRE_RL_tlp_tlpBRAM_writeReq =
tlp_tlpBRAM_mReqF_EMPTY_N &&
(tlp_tlpBRAM_mReqF_D_OUT[63] ||
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_51_TO_50_ETC___d623) &&
tlp_tlpBRAM_mReqF_D_OUT[129:128] == 2'd0 ;
// rule RL_tlp_tlpBRAM_writeData
assign WILL_FIRE_RL_tlp_tlpBRAM_writeData =
tlp_tlpBRAM_mReqF_EMPTY_N &&
(!SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 ||
bram_0_serverAdapterA_cnt_6_SLT_3___d619) &&
NOT_SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_5_ETC___d681 &&
tlp_tlpBRAM_mReqF_D_OUT[129:128] == 2'd1 ;
// rule RL_tlp_tlpBRAM_read_FirstReq
assign WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq =
tlp_tlpBRAM_mReqF_EMPTY_N && tlp_tlpBRAM_readReq_FULL_N &&
(tlp_tlpBRAM_mReqF_D_OUT[60] ||
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_30_TO_29_ETC___d736) &&
!tlp_tlpBRAM_readStarted &&
tlp_tlpBRAM_mReqF_D_OUT[129:128] != 2'd0 &&
tlp_tlpBRAM_mReqF_D_OUT[129:128] != 2'd1 ;
// rule RL_tlp_tlpBRAM_read_NextReq
assign WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq =
bram_0_serverAdapterA_cnt_6_SLT_3___d619 &&
bram_1_serverAdapterA_cnt_44_SLT_3___d620 &&
bram_2_serverAdapterA_cnt_62_SLT_3___d621 &&
bram_3_serverAdapterA_cnt_80_SLT_3___d622 &&
tlp_tlpBRAM_mReqF_EMPTY_N &&
tlp_tlpBRAM_readStarted &&
tlp_tlpBRAM_mReqF_D_OUT[129:128] != 2'd0 &&
tlp_tlpBRAM_mReqF_D_OUT[129:128] != 2'd1 ;
// rule RL_tlp_tlpBRAM_read_FirstResp
assign WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp =
tlp_tlpBRAM_readReq_EMPTY_N &&
tlp_tlpBRAM_mRespF_i_notFull__97_AND_tlp_tlpBR_ETC___d813 &&
!tlp_tlpBRAM_readHeaderSent ;
// rule RL_tlp_tlpBRAM_read_NextResp
assign WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp =
tlp_tlpBRAM_readReq_EMPTY_N &&
bram_0_serverAdapterA_outDataCore_notEmpty_OR__ETC___d887 &&
tlp_tlpBRAM_readHeaderSent ;
// rule RL_bram_0_serverAdapterA_outData_enqAndDeq
assign WILL_FIRE_RL_bram_0_serverAdapterA_outData_enqAndDeq =
bram_0_serverAdapterA_outDataCore_EMPTY_N &&
bram_0_serverAdapterA_outDataCore_FULL_N &&
bram_0_serverAdapterA_outData_deqCalled_whas &&
bram_0_serverAdapterA_outData_enqData_whas ;
// rule RL_bram_1_serverAdapterA_outData_enqAndDeq
assign WILL_FIRE_RL_bram_1_serverAdapterA_outData_enqAndDeq =
bram_1_serverAdapterA_outDataCore_EMPTY_N &&
bram_1_serverAdapterA_outDataCore_FULL_N &&
bram_1_serverAdapterA_outData_deqCalled_whas &&
bram_1_serverAdapterA_outData_enqData_whas ;
// rule RL_bram_2_serverAdapterA_outData_enqAndDeq
assign WILL_FIRE_RL_bram_2_serverAdapterA_outData_enqAndDeq =
bram_2_serverAdapterA_outDataCore_EMPTY_N &&
bram_2_serverAdapterA_outDataCore_FULL_N &&
bram_2_serverAdapterA_outData_deqCalled_whas &&
bram_2_serverAdapterA_outData_enqData_whas ;
// rule RL_bram_3_serverAdapterA_outData_enqAndDeq
assign WILL_FIRE_RL_bram_3_serverAdapterA_outData_enqAndDeq =
bram_3_serverAdapterA_outDataCore_EMPTY_N &&
bram_3_serverAdapterA_outDataCore_FULL_N &&
bram_3_serverAdapterA_outData_deqCalled_whas &&
bram_3_serverAdapterA_outData_enqData_whas ;
// rule RL_wmi_reqMetadata
assign CAN_FIRE_RL_wmi_reqMetadata =
bram_0_serverAdapterB_cnt_5_SLT_3_666_AND_bram_ETC___d1672 &&
dpControl[3:2] != 2'd1 &&
!wmi_mesgMeta[128] &&
wmi_mesgBufReady &&
!wmi_metaBusy &&
wmi_bufDwell == 2'd0 ;
assign WILL_FIRE_RL_wmi_reqMetadata =
CAN_FIRE_RL_wmi_reqMetadata && !WILL_FIRE_RL_wmi_doReadReq &&
!WILL_FIRE_RL_wmi_doWriteReq &&
!WILL_FIRE_RL_wmi_doWriteFinalize ;
// rule RL_wmi_doWriteFinalize
assign WILL_FIRE_RL_wmi_doWriteFinalize =
wmi_wmi_operateD_606_AND_wmi_wmi_peerIsReady_6_ETC___d1777 &&
wmi_wrFinalize ;
// rule RL_wmi_respMetadata
assign CAN_FIRE_RL_wmi_respMetadata =
wmi_wmi_operateD && wmi_wmi_peerIsReady &&
(bram_0_serverAdapterB_outDataCore_EMPTY_N ||
bram_0_serverAdapterB_outData_enqData_whas) &&
bram_0_serverAdapterB_outData_outData_whas__68_ETC___d1697 &&
dpControl[3:2] != 2'd1 &&
!wmi_mesgMeta[128] &&
wmi_mesgBufReady &&
wmi_metaBusy ;
assign WILL_FIRE_RL_wmi_respMetadata =
CAN_FIRE_RL_wmi_respMetadata && !WILL_FIRE_RL_wmi_doReadResp ;
// rule RL_wmi_doReadReq
assign WILL_FIRE_RL_wmi_doReadReq =
bram_0_serverAdapterB_cnt_5_SLT_3_666_AND_bram_ETC___d1672 &&
wmi_rdActive &&
!WILL_FIRE_RL_wmi_doWriteReq &&
!WILL_FIRE_RL_wmi_doWriteFinalize ;
// rule RL_wmi_doReadResp
assign WILL_FIRE_RL_wmi_doReadResp =
wmi_wmi_respF_cntr_r != 2'd2 &&
wmi_wmi_operateD_606_AND_wmi_wmi_peerIsReady_6_ETC___d1798 &&
wmi_bytesRemainResp != 14'd0 ;
// rule RL_bram_0_serverAdapterB_outData_enqAndDeq
assign WILL_FIRE_RL_bram_0_serverAdapterB_outData_enqAndDeq =
bram_0_serverAdapterB_outDataCore_EMPTY_N &&
bram_0_serverAdapterB_outDataCore_FULL_N &&
bram_0_serverAdapterB_outData_deqCalled_whas &&
bram_0_serverAdapterB_outData_enqData_whas ;
// rule RL_bram_1_serverAdapterB_outData_enqAndDeq
assign WILL_FIRE_RL_bram_1_serverAdapterB_outData_enqAndDeq =
bram_1_serverAdapterB_outDataCore_EMPTY_N &&
bram_1_serverAdapterB_outDataCore_FULL_N &&
bram_0_serverAdapterB_outData_deqCalled_whas &&
bram_1_serverAdapterB_outData_enqData_whas ;
// rule RL_bram_2_serverAdapterB_outData_enqAndDeq
assign WILL_FIRE_RL_bram_2_serverAdapterB_outData_enqAndDeq =
bram_2_serverAdapterB_outDataCore_EMPTY_N &&
bram_2_serverAdapterB_outDataCore_FULL_N &&
bram_0_serverAdapterB_outData_deqCalled_whas &&
bram_2_serverAdapterB_outData_enqData_whas ;
// rule RL_bram_3_serverAdapterB_outData_enqAndDeq
assign WILL_FIRE_RL_bram_3_serverAdapterB_outData_enqAndDeq =
bram_3_serverAdapterB_outDataCore_EMPTY_N &&
bram_3_serverAdapterB_outDataCore_FULL_N &&
bram_0_serverAdapterB_outData_deqCalled_whas &&
bram_3_serverAdapterB_outData_enqData_whas ;
// rule RL_wmi_getRequest
assign CAN_FIRE_RL_wmi_getRequest =
wmi_wmi_operateD && wmi_wmi_peerIsReady && !wmi_wmi_blockReq &&
wmi_wmi_reqF_EMPTY_N &&
NOT_wmi_wrActive_717_718_OR_NOT_wmi_rdActive_7_ETC___d1727 &&
wmi_bufDwell == 2'd0 ;
assign WILL_FIRE_RL_wmi_getRequest =
CAN_FIRE_RL_wmi_getRequest && !WILL_FIRE_RL_wmi_doReadReq &&
!WILL_FIRE_RL_wmi_doWriteReq ;
// rule RL_wmi_doWriteReq
assign CAN_FIRE_RL_wmi_doWriteReq =
wmi_wmi_operateD && wmi_wmi_peerIsReady &&
bram_0_serverAdapterB_cnt_5_SLT_3___d1666 &&
bram_1_serverAdapterB_cnt_03_SLT_3___d1667 &&
bram_2_serverAdapterB_cnt_21_SLT_3___d1668 &&
bram_3_serverAdapterB_cnt_39_SLT_3___d1669 &&
wmi_wmi_dhF_EMPTY_N &&
wmi_wrActive ;
assign WILL_FIRE_RL_wmi_doWriteReq =
CAN_FIRE_RL_wmi_doWriteReq && !WILL_FIRE_RL_wmi_doWriteFinalize ;
// rule RL_wmi_wmi_respF_incCtr
assign WILL_FIRE_RL_wmi_wmi_respF_incCtr =
WILL_FIRE_RL_wmi_doReadResp && WILL_FIRE_RL_wmi_doReadResp &&
!(wmi_wmi_respF_cntr_r != 2'd0) ;
// rule RL_wmi_wmi_respF_decCtr
assign WILL_FIRE_RL_wmi_wmi_respF_decCtr =
wmi_wmi_respF_cntr_r != 2'd0 && !WILL_FIRE_RL_wmi_doReadResp ;
// rule RL_wmi_wmi_respF_both
assign WILL_FIRE_RL_wmi_wmi_respF_both =
WILL_FIRE_RL_wmi_doReadResp && wmi_wmi_respF_cntr_r != 2'd0 &&
WILL_FIRE_RL_wmi_doReadResp ;
// rule RL_bml_fba
assign WILL_FIRE_RL_bml_fba = wci_cState == 3'd2 && dpControl[1:0] == 2'd1 ;
// rule RL_bml_lcredit
assign WILL_FIRE_RL_bml_lcredit =
wci_cState == 3'd2 && dpControl[1:0] == 2'd2 ;
// rule RL_bml_lclAdvance
assign WILL_FIRE_RL_bml_lclAdvance = wci_cState == 3'd2 && bml_lclBufDone ;
// rule RL_bml_remAdvance
assign CAN_FIRE_RL_bml_remAdvance = wci_cState == 3'd2 && bml_remDone ;
assign WILL_FIRE_RL_bml_remAdvance =
CAN_FIRE_RL_bml_remAdvance && !WILL_FIRE_RL_bml_crdAdvance ;
// rule RL_bml_crdAdvance
assign WILL_FIRE_RL_bml_crdAdvance =
wci_cState == 3'd2 && dpControl[1:0] == 2'd2 && bml_remStart ;
// rule RL_bml_initAccumulators
assign WILL_FIRE_RL_bml_initAccumulators =
wci_wci_ctrl_pw_whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd1 &&
wci_reqF_D_OUT[36:34] == 3'd1 ;
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
wci_respF_cntr_r != 2'd2 && wci_reqF_EMPTY_N &&
wci_wci_cfwr_pw_whas &&
!WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctl_op_complete
assign WILL_FIRE_RL_wci_ctl_op_complete =
wci_respF_cntr_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ;
// rule RL_wci_respF_incCtr
assign WILL_FIRE_RL_wci_respF_incCtr =
wci_respF_enqueueing_whas && wci_respF_enqueueing_whas &&
!(wci_respF_cntr_r != 2'd0) ;
// rule RL_wci_respF_decCtr
assign WILL_FIRE_RL_wci_respF_decCtr =
wci_respF_cntr_r != 2'd0 && !wci_respF_enqueueing_whas ;
// rule RL_wci_respF_both
assign WILL_FIRE_RL_wci_respF_both =
wci_respF_enqueueing_whas && wci_respF_cntr_r != 2'd0 &&
wci_respF_enqueueing_whas ;
// rule RL_wmi_wmi_reqF_reset
assign WILL_FIRE_RL_wmi_wmi_reqF_reset =
MUX_wmi_wmi_reqF_levelsValid_write_1__SEL_2 ||
WILL_FIRE_RL_wmi_getRequest ;
// rule RL_wmi_wmi_mFlagF_reset
assign WILL_FIRE_RL_wmi_wmi_mFlagF_reset =
MUX_wmi_wmi_mFlagF_levelsValid_write_1__SEL_2 ||
WILL_FIRE_RL_wmi_doWriteFinalize ;
// rule RL_wmi_wmi_dhF_reset
assign WILL_FIRE_RL_wmi_wmi_dhF_reset =
MUX_wmi_wmi_dhF_levelsValid_write_1__SEL_2 ||
WILL_FIRE_RL_wmi_doWriteReq ;
// inputs to muxes for submodule ports
assign MUX_bml_fabBufsAvail_write_1__SEL_1 =
WILL_FIRE_RL_bml_fba &&
(bml_fabAvail && !bml_remStart ||
!bml_fabAvail && bml_remStart) ;
assign MUX_bml_fabFlowAddr_write_1__SEL_1 =
WILL_FIRE_RL_bml_remAdvance && dpControl[1:0] == 2'd1 ;
assign MUX_bml_lclBufsAR_write_1__SEL_1 =
wci_cState == 3'd2 &&
IF_bml_dpControl_wget__898_BITS_1_TO_0_904_EQ__ETC___d1984 ;
assign MUX_bml_lclBufsCF_write_1__SEL_1 =
wci_cState == 3'd2 &&
bml_lclBufDone_922_AND_IF_bml_dpControl_wget___ETC___d2003 ;
assign MUX_bml_lclCredit_write_1__SEL_1 =
WILL_FIRE_RL_bml_lcredit &&
(bml_lclBufDone && !bml_remStart ||
!bml_lclBufDone && bml_remStart) ;
assign MUX_bram_0_memory_a_put_1__SEL_1 =
WILL_FIRE_RL_tlp_tlpBRAM_writeData &&
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 ;
assign MUX_bram_0_memory_a_put_1__SEL_2 =
WILL_FIRE_RL_tlp_tlpBRAM_writeReq &&
tlp_tlpBRAM_mReqF_D_OUT[51:50] == 2'd0 &&
!tlp_tlpBRAM_mReqF_D_OUT[63] ;
assign MUX_bram_0_memory_a_put_1__SEL_3 =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
tlp_tlpBRAM_mReqF_D_OUT[30:29] == 2'd0 &&
!tlp_tlpBRAM_mReqF_D_OUT[60] ;
assign MUX_bram_0_serverAdapterB_writeWithResp_wset_1__SEL_1 =
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ;
assign MUX_bram_1_memory_a_put_1__SEL_1 =
WILL_FIRE_RL_tlp_tlpBRAM_writeData &&
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 ;
assign MUX_bram_1_memory_a_put_1__SEL_2 =
WILL_FIRE_RL_tlp_tlpBRAM_writeReq &&
tlp_tlpBRAM_mReqF_D_OUT[51:50] == 2'd1 &&
!tlp_tlpBRAM_mReqF_D_OUT[63] ;
assign MUX_bram_1_memory_a_put_1__SEL_3 =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
tlp_tlpBRAM_mReqF_D_OUT[30:29] == 2'd1 &&
!tlp_tlpBRAM_mReqF_D_OUT[60] ;
assign MUX_bram_2_memory_a_put_1__SEL_1 =
WILL_FIRE_RL_tlp_tlpBRAM_writeData &&
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 ;
assign MUX_bram_2_memory_a_put_1__SEL_2 =
WILL_FIRE_RL_tlp_tlpBRAM_writeReq &&
tlp_tlpBRAM_mReqF_D_OUT[51:50] == 2'd2 &&
!tlp_tlpBRAM_mReqF_D_OUT[63] ;
assign MUX_bram_2_memory_a_put_1__SEL_3 =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
tlp_tlpBRAM_mReqF_D_OUT[30:29] == 2'd2 &&
!tlp_tlpBRAM_mReqF_D_OUT[60] ;
assign MUX_bram_3_memory_a_put_1__SEL_1 =
WILL_FIRE_RL_tlp_tlpBRAM_writeData &&
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 ;
assign MUX_bram_3_memory_a_put_1__SEL_2 =
WILL_FIRE_RL_tlp_tlpBRAM_writeReq &&
tlp_tlpBRAM_mReqF_D_OUT[51:50] == 2'd3 &&
!tlp_tlpBRAM_mReqF_D_OUT[63] ;
assign MUX_bram_3_memory_a_put_1__SEL_3 =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
tlp_tlpBRAM_mReqF_D_OUT[30:29] == 2'd3 &&
!tlp_tlpBRAM_mReqF_D_OUT[60] ;
assign MUX_tlp_fabMesgAccu_write_1__SEL_1 =
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ||
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ;
assign MUX_tlp_fabMeta_write_1__SEL_2 =
WILL_FIRE_RL_tlp_dmaTailEventSender &&
(tlp_fabFlowAddrMS == 32'd0 || tlp_sentTail4DWHeader) ;
assign MUX_tlp_remDone_1_wset_1__SEL_1 =
WILL_FIRE_RL_tlp_dmaTailEventSender &&
(tlp_fabFlowAddrMS == 32'd0 && tlp_tailEventF_D_OUT ||
tlp_fabFlowAddrMS != 32'd0 && !tlp_sentTail4DWHeader &&
tlp_tailEventF_D_OUT) ;
assign MUX_tlp_tailEventF_enq_1__SEL_1 =
WILL_FIRE_RL_tlp_dmaXmtDoorbell ||
WILL_FIRE_RL_tlp_dmaXmtTailEvent ;
assign MUX_tlp_tlpBRAM_mReqF_enq_1__SEL_1 =
WILL_FIRE_RL_tlp_tlpRcv &&
tlp_inF_first__259_BIT_152_462_AND_NOT_tlp_inF_ETC___d1487 ;
assign MUX_tlp_tlpBRAM_mReqF_enq_1__SEL_2 =
WILL_FIRE_RL_tlp_dmaPullResponseBody ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ;
assign MUX_tlp_tlpBRAM_readHeaderSent_write_1__SEL_1 =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp &&
(tlp_tlpBRAM_readReq_D_OUT[28:19] != 10'd1 ||
tlp_tlpBRAM_readReq_D_OUT[60]) ;
assign MUX_tlp_tlpBRAM_readStarted_write_1__SEL_1 =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
(tlp_tlpBRAM_mReqF_D_OUT[28:19] != 10'd1 ||
tlp_tlpBRAM_mReqF_D_OUT[60]) ;
assign MUX_tlp_tlpXmtBusy_write_1__SEL_1 =
WILL_FIRE_RL_tlp_dmaPushResponseHeader && _dfoo5 ;
assign MUX_tlp_tlpXmtBusy_write_1__PSEL_2 =
WILL_FIRE_RL_tlp_dataXmt_Body ||
WILL_FIRE_RL_tlp_dmaPushResponseBody ;
assign MUX_tlp_tlpXmtBusy_write_1__SEL_2 =
MUX_tlp_tlpXmtBusy_write_1__PSEL_2 &&
tlp_outDwRemain_129_ULE_4___d1130 ;
assign MUX_tlp_tlpXmtBusy_write_1__SEL_3 =
WILL_FIRE_RL_tlp_dmaTailEventSender &&
tlp_fabFlowAddrMS != 32'd0 ;
assign MUX_tlp_tlpXmtBusy_write_1__SEL_4 =
WILL_FIRE_RL_tlp_dataXmt_Header &&
!tlp_tlpBRAM_mRespF_first__000_BITS_71_TO_62_10_ETC___d1102 ;
assign MUX_tlp_xmtMetaOK_write_1__SEL_3 =
WILL_FIRE_RL_tlp_dmaPushResponseBody &&
tlp_outDwRemain_129_ULE_4___d1130 &&
tlp_tlpBRAM_mRespF_D_OUT[135:128] == 8'h01 ;
assign MUX_tlp_xmtMetaOK_write_1__SEL_4 =
WILL_FIRE_RL_tlp_dmaPushResponseHeader &&
tlp_fabMesgAddrMS == 32'd0 &&
tlp_tlpBRAM_mRespF_D_OUT[71:62] == 10'd1 &&
tlp_tlpBRAM_mRespF_D_OUT[42:35] == 8'h01 ;
assign MUX_wci_illegalEdge_write_1__SEL_1 =
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ;
assign MUX_wci_illegalEdge_write_1__SEL_2 =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF_D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 ||
wci_reqF_D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 &&
wci_cState != 3'd3 ||
wci_reqF_D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 ||
wci_reqF_D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 &&
wci_cState != 3'd2 &&
wci_cState != 3'd1 ||
wci_reqF_D_OUT[36:34] == 3'd4 ||
wci_reqF_D_OUT[36:34] == 3'd5 ||
wci_reqF_D_OUT[36:34] == 3'd6 ||
wci_reqF_D_OUT[36:34] == 3'd7) ;
assign MUX_wci_respF_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wci_respF_both && _dfoo3 ;
assign MUX_wci_respF_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_cntr_r == 2'd0 ;
assign MUX_wci_respF_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wci_respF_both && _dfoo1 ;
assign MUX_wci_respF_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_cntr_r == 2'd1 ;
assign MUX_wmi_bufDwell_write_1__SEL_1 =
WILL_FIRE_RL_wmi_doReadReq && wmi_bytesRemainReq == 14'd16 &&
wmi_doneWithMesg ;
assign MUX_wmi_bytesRemainResp_write_1__SEL_1 =
WILL_FIRE_RL_wmi_getRequest &&
wmi_wmi_reqF_D_OUT[31:29] == 3'd2 ;
assign MUX_wmi_doneWithMesg_write_1__PSEL_1 =
WILL_FIRE_RL_wmi_doReadReq || WILL_FIRE_RL_wmi_doWriteReq ;
assign MUX_wmi_doneWithMesg_write_1__SEL_1 =
MUX_wmi_doneWithMesg_write_1__PSEL_1 &&
wmi_bytesRemainReq == 14'd16 &&
wmi_doneWithMesg ;
assign MUX_wmi_rdActive_write_1__SEL_1 =
WILL_FIRE_RL_wmi_doReadReq && wmi_bytesRemainReq == 14'd16 ;
assign MUX_wmi_wmi_dhF_levelsValid_write_1__SEL_2 =
wmi_wmi_dhF_FULL_N && wmi_wmi_operateD && wmi_wmi_peerIsReady &&
wmi_wmi_wmiDh_wget[145] ;
assign MUX_wmi_wmi_mFlagF_levelsValid_write_1__SEL_2 =
wmi_wmi_mFlagF_FULL_N && wmi_wmi_operateD &&
wmi_wmi_peerIsReady &&
wmi_wmi_wmiReq_wget[31:29] != 3'd0 &&
wmi_wmi_wmiReq_wget[27] ;
assign MUX_wmi_wmi_reqF_levelsValid_write_1__SEL_2 =
wmi_wmi_reqF_FULL_N && wmi_wmi_operateD && wmi_wmi_peerIsReady &&
wmi_wmi_wmiReq_wget[31:29] != 3'd0 ;
assign MUX_wmi_wmi_respF_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wmi_wmi_respF_both && _dfoo9 ;
assign MUX_wmi_wmi_respF_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wmi_wmi_respF_incCtr &&
wmi_wmi_respF_cntr_r == 2'd0 ;
assign MUX_wmi_wmi_respF_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wmi_wmi_respF_both && _dfoo7 ;
assign MUX_wmi_wmi_respF_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wmi_wmi_respF_incCtr &&
wmi_wmi_respF_cntr_r == 2'd1 ;
assign MUX_wmi_wrActive_write_1__SEL_1 =
WILL_FIRE_RL_wmi_doWriteReq && wmi_bytesRemainReq == 14'd16 ;
assign MUX_wmi_wrFinalize_write_1__SEL_1 =
WILL_FIRE_RL_wmi_doWriteReq && wmi_bytesRemainReq == 14'd16 &&
wmi_doneWithMesg ;
assign MUX_bml_crdBuf_value_write_1__VAL_3 =
bml_crdBuf_value_880_EQ_bml_crdBuf_modulus_bw__ETC___d1882 ?
16'd0 :
bml_crdBuf_value + 16'd1 ;
assign MUX_bml_fabBuf_value_write_1__VAL_3 =
bml_fabBuf_value_865_EQ_bml_fabBuf_modulus_bw__ETC___d1867 ?
16'd0 :
bml_fabBuf_value + 16'd1 ;
assign MUX_bml_fabBufsAvail_write_1__VAL_1 =
(bml_fabAvail && !bml_remStart) ? x__h90034 : x__h90039 ;
assign MUX_bml_fabBufsAvail_write_1__VAL_2 =
(dpControl[3:2] == 2'd1) ? x__h88675 : 16'd0 ;
assign MUX_bml_fabFlowAddr_write_1__VAL_1 =
bml_fabBuf_value_865_EQ_bml_fabBuf_modulus_bw__ETC___d1867 ?
bml_fabFlowBase :
bml_fabFlowAddr_937_PLUS_bml_fabFlowSize_938___d1939 ;
assign MUX_bml_fabFlowAddr_write_1__VAL_3 =
bml_crdBuf_value_880_EQ_bml_crdBuf_modulus_bw__ETC___d1882 ?
bml_fabFlowBase :
bml_fabFlowAddr_937_PLUS_bml_fabFlowSize_938___d1939 ;
assign MUX_bml_fabMesgAddr_write_1__VAL_1 =
bml_fabBuf_value_865_EQ_bml_fabBuf_modulus_bw__ETC___d1867 ?
bml_fabMesgBase :
bml_fabMesgAddr + bml_fabMesgSize ;
assign MUX_bml_fabMetaAddr_write_1__VAL_1 =
bml_fabBuf_value_865_EQ_bml_fabBuf_modulus_bw__ETC___d1867 ?
bml_fabMetaBase :
bml_fabMetaAddr + bml_fabMetaSize ;
assign MUX_bml_lclBuf_value_write_1__VAL_3 =
bml_lclBuf_value_835_EQ_bml_lclBuf_modulus_bw__ETC___d1837 ?
16'd0 :
bml_lclBuf_value + 16'd1 ;
assign MUX_bml_lclBufsAR_write_1__VAL_1 =
(CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_bml_ETC__q4 &&
!bml_lclBufStart) ?
x__h89803 :
x__h89808 ;
assign MUX_bml_lclBufsAR_write_1__VAL_2 =
(dpControl[3:2] == 2'd1) ? bml_lclNumBufs : 16'd0 ;
assign MUX_bml_lclBufsCF_write_1__VAL_1 =
(bml_lclBufDone &&
CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q6) ?
x__h89915 :
x__h89952 ;
assign MUX_bml_lclBufsCF_write_1__VAL_2 =
(dpControl[3:2] == 2'd1) ? 16'd0 : bml_lclNumBufs ;
assign MUX_bml_lclCredit_write_1__VAL_1 =
(bml_lclBufDone && !bml_remStart) ? x__h90073 : x__h90078 ;
assign MUX_bml_lclMesgAddr_write_1__VAL_2 =
bml_lclBuf_value_835_EQ_bml_lclBuf_modulus_bw__ETC___d1837 ?
bml_mesgBase :
bml_lclMesgAddr + bml_mesgSize ;
assign MUX_bml_lclMetaAddr_write_1__VAL_2 =
bml_lclBuf_value_835_EQ_bml_lclBuf_modulus_bw__ETC___d1837 ?
bml_metaBase :
bml_lclMetaAddr + bml_metaSize ;
assign MUX_bml_remBuf_value_write_1__VAL_3 =
bml_remBuf_value_850_EQ_bml_remBuf_modulus_bw__ETC___d1852 ?
16'd0 :
bml_remBuf_value + 16'd1 ;
assign MUX_bml_remMesgAddr_write_1__VAL_2 =
bml_remBuf_value_850_EQ_bml_remBuf_modulus_bw__ETC___d1852 ?
bml_mesgBase :
bml_remMesgAddr + bml_mesgSize ;
assign MUX_bml_remMetaAddr_write_1__VAL_2 =
bml_remBuf_value_850_EQ_bml_remBuf_modulus_bw__ETC___d1852 ?
bml_metaBase :
bml_remMetaAddr + bml_metaSize ;
always@(idx__h21626 or
tlp_tlpBRAM_writeDWAddr or
tlp_tlpBRAM_writeDWAddr_PLUS_1__q8 or
tlp_tlpBRAM_writeDWAddr_PLUS_2__q9 or
tlp_tlpBRAM_writeDWAddr_PLUS_3__q10)
begin
case (idx__h21626)
2'd0: MUX_bram_0_memory_a_put_2__VAL_1 = tlp_tlpBRAM_writeDWAddr[12:2];
2'd1:
MUX_bram_0_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_1__q8[12:2];
2'd2:
MUX_bram_0_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_2__q9[12:2];
2'd3:
MUX_bram_0_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_3__q10[12:2];
endcase
end
always@(idx__h27879 or
tlp_tlpBRAM_readNxtDWAddr or
tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11 or
tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12 or
tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13)
begin
case (idx__h27879)
2'd0:
MUX_bram_0_memory_a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2];
2'd1:
MUX_bram_0_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11[12:2];
2'd2:
MUX_bram_0_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12[12:2];
2'd3:
MUX_bram_0_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13[12:2];
endcase
end
assign MUX_bram_0_memory_a_put_3__VAL_1 =
{ SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700[7:0],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700[15:8],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700[23:16],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700[31:24] } ;
assign MUX_bram_0_memory_a_put_3__VAL_2 =
{ tlp_tlpBRAM_mReqF_D_OUT[7:0],
tlp_tlpBRAM_mReqF_D_OUT[15:8],
tlp_tlpBRAM_mReqF_D_OUT[23:16],
tlp_tlpBRAM_mReqF_D_OUT[31:24] } ;
assign MUX_bram_0_memory_b_put_2__VAL_2 =
wmi_lclMesgAddr[14:4] + { 1'd0, wmi_addr[13:4] } ;
always@(idx__h23676 or
tlp_tlpBRAM_writeDWAddr or
tlp_tlpBRAM_writeDWAddr_PLUS_1__q8 or
tlp_tlpBRAM_writeDWAddr_PLUS_2__q9 or
tlp_tlpBRAM_writeDWAddr_PLUS_3__q10)
begin
case (idx__h23676)
2'd0: MUX_bram_1_memory_a_put_2__VAL_1 = tlp_tlpBRAM_writeDWAddr[12:2];
2'd1:
MUX_bram_1_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_1__q8[12:2];
2'd2:
MUX_bram_1_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_2__q9[12:2];
2'd3:
MUX_bram_1_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_3__q10[12:2];
endcase
end
always@(idx__h28282 or
tlp_tlpBRAM_readNxtDWAddr or
tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11 or
tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12 or
tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13)
begin
case (idx__h28282)
2'd0:
MUX_bram_1_memory_a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2];
2'd1:
MUX_bram_1_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11[12:2];
2'd2:
MUX_bram_1_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12[12:2];
2'd3:
MUX_bram_1_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13[12:2];
endcase
end
assign MUX_bram_1_memory_a_put_3__VAL_1 =
{ SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708[7:0],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708[15:8],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708[23:16],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708[31:24] } ;
always@(idx__h24781 or
tlp_tlpBRAM_writeDWAddr or
tlp_tlpBRAM_writeDWAddr_PLUS_1__q8 or
tlp_tlpBRAM_writeDWAddr_PLUS_2__q9 or
tlp_tlpBRAM_writeDWAddr_PLUS_3__q10)
begin
case (idx__h24781)
2'd0: MUX_bram_2_memory_a_put_2__VAL_1 = tlp_tlpBRAM_writeDWAddr[12:2];
2'd1:
MUX_bram_2_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_1__q8[12:2];
2'd2:
MUX_bram_2_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_2__q9[12:2];
2'd3:
MUX_bram_2_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_3__q10[12:2];
endcase
end
always@(idx__h28586 or
tlp_tlpBRAM_readNxtDWAddr or
tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11 or
tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12 or
tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13)
begin
case (idx__h28586)
2'd0:
MUX_bram_2_memory_a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2];
2'd1:
MUX_bram_2_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11[12:2];
2'd2:
MUX_bram_2_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12[12:2];
2'd3:
MUX_bram_2_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13[12:2];
endcase
end
assign MUX_bram_2_memory_a_put_3__VAL_1 =
{ SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716[7:0],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716[15:8],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716[23:16],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716[31:24] } ;
always@(idx__h25886 or
tlp_tlpBRAM_writeDWAddr or
tlp_tlpBRAM_writeDWAddr_PLUS_1__q8 or
tlp_tlpBRAM_writeDWAddr_PLUS_2__q9 or
tlp_tlpBRAM_writeDWAddr_PLUS_3__q10)
begin
case (idx__h25886)
2'd0: MUX_bram_3_memory_a_put_2__VAL_1 = tlp_tlpBRAM_writeDWAddr[12:2];
2'd1:
MUX_bram_3_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_1__q8[12:2];
2'd2:
MUX_bram_3_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_2__q9[12:2];
2'd3:
MUX_bram_3_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_3__q10[12:2];
endcase
end
always@(idx__h28890 or
tlp_tlpBRAM_readNxtDWAddr or
tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11 or
tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12 or
tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13)
begin
case (idx__h28890)
2'd0:
MUX_bram_3_memory_a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2];
2'd1:
MUX_bram_3_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11[12:2];
2'd2:
MUX_bram_3_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12[12:2];
2'd3:
MUX_bram_3_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13[12:2];
endcase
end
assign MUX_bram_3_memory_a_put_3__VAL_1 =
{ SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724[7:0],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724[15:8],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724[23:16],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724[31:24] } ;
assign MUX_tlp_dmaDoTailEvent_write_1__VAL_1 =
tlp_dmaPullRemainDWSub_387_ULE_4___d1388 &&
tlp_dmaPullRemainDWLen_373_ULE_tlp_dmaPullRema_ETC___d1395 ;
assign MUX_tlp_dmaPullRemainDWLen_write_1__VAL_2 =
tlp_dmaPullRemainDWLen - 10'd1 ;
assign MUX_tlp_dmaPullRemainDWLen_write_1__VAL_3 =
tlp_dmaPullRemainDWSub_387_ULE_4___d1388 ?
tlp_dmaPullRemainDWLen - tlp_dmaPullRemainDWSub :
tlp_dmaPullRemainDWLen - 10'd4 ;
assign MUX_tlp_dmaPullRemainDWSub_write_1__VAL_1 =
tlp_inF_D_OUT[105:96] - 10'd1 ;
assign MUX_tlp_dmaPullRemainDWSub_write_1__VAL_2 =
tlp_dmaPullRemainDWSub_387_ULE_4___d1388 ?
10'd0 :
tlp_dmaPullRemainDWSub - 10'd4 ;
assign MUX_tlp_doorSeqDwell_write_1__VAL_1 = tlp_doorSeqDwell - 4'd1 ;
assign MUX_tlp_fabMesgAccu_write_1__VAL_2 = tlp_fabMesgAccu + y__h48181 ;
assign MUX_tlp_fabMesgAccu_write_1__VAL_3 = tlp_fabMesgAccu + y__h63989 ;
assign MUX_tlp_fabMeta_write_1__VAL_1 =
{ 1'd1,
x__h47258,
opcode__h44022,
nowMS__h45280,
nowLS__h46239 } ;
assign MUX_tlp_fabMeta_write_1__VAL_3 =
{ 1'd1,
x__h63608,
opcode__h60417,
nowMS__h61665,
nowLS__h62622 } ;
assign MUX_tlp_lastRuleFired_write_1__VAL_3 =
(tlp_fabFlowAddrMS == 32'd0) ?
4'd8 :
(tlp_sentTail4DWHeader ? 4'd10 : 4'd9) ;
assign MUX_tlp_mesgComplReceived_write_1__VAL_1 =
tlp_mesgComplReceived + 17'd4 ;
assign MUX_tlp_mesgComplReceived_write_1__VAL_2 =
tlp_mesgComplReceived + y__h65310 ;
assign MUX_tlp_mesgLengthRemainPull_write_1__VAL_1 =
{ tlp_inF_D_OUT[8],
tlp_inF_D_OUT[23:16],
tlp_inF_D_OUT[31:24] } ;
assign MUX_tlp_mesgLengthRemainPull_write_1__VAL_2 =
{ tlp_mesgLengthRemainPull_PLUS_3__q14[16:2], 2'd0 } ;
assign MUX_tlp_mesgLengthRemainPull_write_1__VAL_3 =
tlp_mesgLengthRemainPull - y__h63918 ;
assign MUX_tlp_mesgLengthRemainPush_write_1__VAL_1 =
{ tlp_mesgLengthRemainPush_PLUS_3__q15[16:2], 2'd0 } ;
assign MUX_tlp_mesgLengthRemainPush_write_1__VAL_2 =
{ tlp_tlpBRAM_mRespF_D_OUT[8],
tlp_tlpBRAM_mRespF_D_OUT[23:16],
tlp_tlpBRAM_mRespF_D_OUT[31:24] } ;
assign MUX_tlp_mesgLengthRemainPush_write_1__VAL_3 =
tlp_mesgLengthRemainPush - y__h47529 ;
assign MUX_tlp_outDwRemain_write_1__VAL_1 =
tlp_tlpBRAM_mRespF_D_OUT[71:62] - y__h48147 ;
assign MUX_tlp_outDwRemain_write_1__VAL_2 = tlp_outDwRemain - 10'd4 ;
assign MUX_tlp_outDwRemain_write_1__VAL_3 =
tlp_tlpBRAM_mRespF_D_OUT[71:62] - 10'd1 ;
assign MUX_tlp_outF_enq_1__VAL_1 =
{ 1'd0,
tlp_outDwRemain_129_ULE_4___d1130,
7'h02,
w_be__h48508,
tlp_tlpBRAM_mRespF_D_OUT[127:0] } ;
assign MUX_tlp_outF_enq_1__VAL_2 =
(tlp_fabMesgAddrMS == 32'd0) ?
{ 1'd1,
tlp_tlpBRAM_mRespF_D_OUT[71:62] == 10'd1,
23'd196607,
w_data__h47916 } :
{ 25'd16973823, w_data__h48052 } ;
assign MUX_tlp_outF_enq_1__VAL_3 =
{ 25'd16973823,
(tlp_fabMetaAddrMS == 32'd0) ? 32'd1073741828 : 32'd1610612740,
pciDevice,
16'd255,
(tlp_fabMetaAddrMS == 32'd0) ?
{ tlp_fabMetaAddr,
tlp_fabMeta[103:96],
tlp_fabMeta[111:104],
tlp_fabMeta[119:112],
tlp_fabMeta[127:120] } :
{ tlp_fabMetaAddrMS, tlp_fabMetaAddr } } ;
assign MUX_tlp_outF_enq_1__VAL_4 =
(tlp_fabMetaAddrMS == 32'd0) ?
{ 25'd8585200,
tlp_fabMeta[71:64],
tlp_fabMeta[79:72],
tlp_fabMeta[87:80],
tlp_fabMeta[95:88],
tlp_fabMeta[39:32],
tlp_fabMeta[47:40],
tlp_fabMeta[55:48],
tlp_fabMeta[63:56],
tlp_fabMeta[7:0],
tlp_fabMeta[15:8],
tlp_fabMeta[23:16],
tlp_fabMeta[31:24],
tlp_fabMetaAddrMS } :
{ 25'd8585215, w_data__h52877 } ;
assign MUX_tlp_outF_enq_1__VAL_5 =
{ 9'd386,
(tlp_fabMetaAddrMS == 32'd0) ? 16'hFFF0 : 16'd65535,
IF_tlp_fabMetaAddrMS_157_EQ_0_158_THEN_4_ELSE__ETC___d1248 } ;
assign MUX_tlp_outF_enq_1__VAL_6 =
{ 9'd386,
(tlp_fabMesgAddrMS == 32'd0) ? 16'hFFF0 : 16'd65535,
IF_tlp_fabMesgAddrMS_078_EQ_0_079_THEN_0_ELSE__ETC___d1353 } ;
assign MUX_tlp_outF_enq_1__VAL_7 =
(tlp_fabFlowAddrMS == 32'd0) ?
{ 25'd25362431, w_data__h65836 } :
(tlp_sentTail4DWHeader ?
{ 25'd8581120, w_data__h67186 } :
{ 25'd16973823, w_data__h66940 }) ;
assign MUX_tlp_outF_enq_1__VAL_8 =
{ 1'd1,
tlp_tlpBRAM_mRespF_D_OUT[71:62] == 10'd1,
23'd196607,
pkt__h71785 } ;
assign MUX_tlp_postSeqDwell_write_1__VAL_1 =
(dpControl[1:0] == 2'd2) ? 4'd8 : 4'd4 ;
assign MUX_tlp_postSeqDwell_write_1__VAL_2 = tlp_postSeqDwell - 4'd1 ;
assign MUX_tlp_remMesgAccu_write_1__VAL_2 = tlp_remMesgAccu + y__h47671 ;
assign MUX_tlp_remMesgAccu_write_1__VAL_3 = tlp_remMesgAccu + y__h64598 ;
assign MUX_tlp_reqMesgInFlight_write_1__VAL_2 =
!tlp_dmaPullRemainDWSub_387_ULE_4___d1388 ||
!tlp_dmaPullRemainDWLen_373_ULE_tlp_dmaPullRema_ETC___d1395 ;
assign MUX_tlp_srcMesgAccu_write_1__VAL_2 = tlp_srcMesgAccu + y__h47623 ;
assign MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_1 =
tlp_inF_D_OUT[152] ?
(tlp_inF_D_OUT[126] ?
{ 67'h15555555555555554,
tlp_inF_D_OUT[46:34],
tlp_inF_D_OUT[105:96],
tlp_inF_D_OUT[67:64],
tlp_inF_D_OUT[71:68],
tlp_inF_D_OUT[31:0] } :
{ 72'h955555555555555551,
tlp_inF_D_OUT[95:80],
tlp_inF_D_OUT[46:34],
tlp_inF_D_OUT[105:96],
tlp_inF_D_OUT[67:64],
tlp_inF_D_OUT[71:68],
tlp_inF_D_OUT[79:72],
tlp_inF_D_OUT[118:116] }) :
{ 2'd1, tlp_inF_D_OUT[127:0] } ;
assign MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_2 = { 2'd1, tlp_inF_D_OUT[127:0] } ;
assign MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_3 =
{ 88'h955555555555555553FFF8,
tlp_remMetaAddr[14:2],
29'd2620074 } ;
assign MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_4 =
{ 69'h12AAAAAAAAAAAAAAAA,
tlp_fabMesgAddrMS != 32'd0,
18'd196600,
tlp_remMesgAccu[14:2],
thisRequestLength__h47504[11:2],
8'd255,
rreq_tag__h47719,
3'h2 } ;
assign MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_5 =
{ 67'h15555555555555554,
tlp_remMetaAddr[14:2],
18'd1279,
tlp_inF_D_OUT[31:0] } ;
assign MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_6 =
{ 67'h15555555555555554,
tlp_remMesgAccu[14:2],
tlp_inF_D_OUT[105:96],
8'd255,
tlp_inF_D_OUT[31:0] } ;
assign MUX_tlp_tlpBRAM_mRespF_enq_1__VAL_1 =
{ 48'h2AAAAAAAAAAA,
!tlp_tlpBRAM_readReq_D_OUT[60],
tlp_tlpBRAM_readReq_D_OUT[59:42],
tlp_tlpBRAM_readReq_D_OUT[28:19],
lowAddr__h29652,
byteCount__h29653,
tlp_tlpBRAM_readReq_D_OUT[10:0],
rresp_data__h29698 } ;
assign MUX_tlp_tlpBRAM_mRespF_enq_1__VAL_2 =
{ 1'd1,
tlp_tlpBRAM_readReq_D_OUT[59:58],
tlp_tlpBRAM_readReq_D_OUT[10:3],
rdata__h35173 } ;
assign MUX_tlp_tlpBRAM_rdRespDwRemain_write_1__VAL_1 =
tlp_tlpBRAM_readReq_D_OUT[28:19] - y__h30729 ;
assign MUX_tlp_tlpBRAM_rdRespDwRemain_write_1__VAL_2 =
tlp_tlpBRAM_rdRespDwRemain - 10'd4 ;
assign MUX_tlp_tlpBRAM_readNxtDWAddr_write_1__VAL_1 =
tlp_tlpBRAM_mReqF_D_OUT[41:29] + y__h27665 ;
assign MUX_tlp_tlpBRAM_readNxtDWAddr_write_1__VAL_2 =
tlp_tlpBRAM_readNxtDWAddr + 13'd4 ;
assign MUX_tlp_tlpBRAM_readRemainDWLen_write_1__VAL_1 =
tlp_tlpBRAM_mReqF_D_OUT[28:19] - y__h27653 ;
assign MUX_tlp_tlpBRAM_readRemainDWLen_write_1__VAL_2 =
tlp_tlpBRAM_readRemainDWLen - 10'd4 ;
assign MUX_tlp_tlpBRAM_writeDWAddr_write_1__VAL_1 =
tlp_tlpBRAM_mReqF_D_OUT[62:50] + y__h17362 ;
assign MUX_tlp_tlpBRAM_writeDWAddr_write_1__VAL_2 =
tlp_tlpBRAM_writeDWAddr + 13'd4 ;
assign MUX_tlp_tlpBRAM_writeRemainDWLen_write_1__VAL_1 =
tlp_tlpBRAM_mReqF_D_OUT[49:40] - y__h17428 ;
assign MUX_tlp_tlpBRAM_writeRemainDWLen_write_1__VAL_2 =
tlp_tlpBRAM_writeRemainDWLen - 10'd4 ;
assign MUX_tlp_tlpXmtBusy_write_1__VAL_1 =
tlp_fabMesgAddrMS != 32'd0 ||
tlp_tlpBRAM_mRespF_D_OUT[71:62] != 10'd1 ;
assign MUX_wci_illegalEdge_write_1__VAL_2 =
wci_reqF_D_OUT[36:34] != 3'd4 && wci_reqF_D_OUT[36:34] != 3'd5 &&
wci_reqF_D_OUT[36:34] != 3'd6 ;
assign MUX_wci_respF_cntr_r_write_1__VAL_2 = wci_respF_cntr_r + 2'd1 ;
assign MUX_wci_respF_q_0_write_1__VAL_1 =
(wci_respF_cntr_r == 2'd1) ?
MUX_wci_respF_q_0_write_1__VAL_2 :
wci_respF_q_1 ;
always@(WILL_FIRE_RL_wci_ctl_op_complete or
MUX_wci_respF_x_wire_wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_respF_x_wire_wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_ctl_op_complete:
MUX_wci_respF_q_0_write_1__VAL_2 =
MUX_wci_respF_x_wire_wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_respF_q_0_write_1__VAL_2 =
MUX_wci_respF_x_wire_wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0_write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_respF_q_0_write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_respF_q_1_write_1__VAL_1 =
(wci_respF_cntr_r == 2'd2) ?
MUX_wci_respF_q_0_write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wci_respF_x_wire_wset_1__VAL_1 =
wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_respF_x_wire_wset_1__VAL_2 = { 2'd1, _theResult____h91947 } ;
assign MUX_wmi_addr_write_1__VAL_1 = wmi_addr + 14'd16 ;
assign MUX_wmi_bufDwell_write_1__VAL_3 = wmi_bufDwell - 2'd1 ;
assign MUX_wmi_bytesRemainReq_write_1__VAL_1 = wmi_bytesRemainReq - 14'd16 ;
assign MUX_wmi_bytesRemainReq_write_1__VAL_2 =
{ wmi_wmi_reqF_D_OUT[9:0], 4'd0 } ;
assign MUX_wmi_bytesRemainResp_write_1__VAL_2 =
wmi_bytesRemainResp - 14'd16 ;
assign MUX_wmi_mesgCount_write_1__VAL_1 = wmi_mesgCount + 32'd1 ;
assign MUX_wmi_mesgMeta_write_1__VAL_2 =
{ 1'd1,
bram_0_serverAdapterB_outData_outData_wget,
bram_1_serverAdapterB_outData_outData_wget,
bram_2_serverAdapterB_outData_outData_wget,
bram_3_serverAdapterB_outData_outData_wget } ;
assign MUX_wmi_wmi_respF_cntr_r_write_1__VAL_2 =
wmi_wmi_respF_cntr_r + 2'd1 ;
assign MUX_wmi_wmi_respF_q_0_write_1__VAL_1 =
(wmi_wmi_respF_cntr_r == 2'd1) ?
MUX_wmi_wmi_respF_q_0_write_1__VAL_2 :
wmi_wmi_respF_q_1 ;
assign MUX_wmi_wmi_respF_q_0_write_1__VAL_2 = { 2'd1, rdata__h83703 } ;
assign MUX_wmi_wmi_respF_q_1_write_1__VAL_1 =
(wmi_wmi_respF_cntr_r == 2'd2) ?
MUX_wmi_wmi_respF_q_0_write_1__VAL_2 :
130'd0 ;
// inlined wires
assign bram_0_serverAdapterA_outData_enqData_wget = bram_0_memory_DOA ;
assign bram_0_serverAdapterA_outData_enqData_whas =
(!bram_0_serverAdapterA_s1[0] ||
bram_0_serverAdapterA_outDataCore_FULL_N) &&
bram_0_serverAdapterA_s1[1] &&
bram_0_serverAdapterA_s1[0] ;
assign bram_0_serverAdapterA_outData_outData_wget =
bram_0_serverAdapterA_outDataCore_EMPTY_N ?
bram_0_serverAdapterA_outDataCore_D_OUT :
bram_0_memory_DOA ;
assign bram_0_serverAdapterA_outData_outData_whas =
bram_0_serverAdapterA_outDataCore_EMPTY_N ||
!bram_0_serverAdapterA_outDataCore_EMPTY_N &&
bram_0_serverAdapterA_outData_enqData_whas ;
assign bram_0_serverAdapterA_cnt_1_wget = 3'd1 ;
assign bram_0_serverAdapterA_cnt_1_whas =
(MUX_bram_0_memory_a_put_1__SEL_1 ||
MUX_bram_0_memory_a_put_1__SEL_2 ||
MUX_bram_0_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) &&
(!ab__h1619[1] || ab__h1619[0]) ;
assign bram_0_serverAdapterA_cnt_2_wget = 3'd7 ;
assign bram_0_serverAdapterA_cnt_2_whas =
bram_0_serverAdapterA_outData_deqCalled_whas ;
assign bram_0_serverAdapterA_cnt_3_wget = 3'h0 ;
assign bram_0_serverAdapterA_cnt_3_whas = 1'b0 ;
assign bram_0_serverAdapterA_writeWithResp_wget = ab__h1619 ;
assign bram_0_serverAdapterA_writeWithResp_whas =
MUX_bram_0_memory_a_put_1__SEL_1 ||
MUX_bram_0_memory_a_put_1__SEL_2 ||
MUX_bram_0_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_0_serverAdapterA_s1_1_wget =
{ 1'd1, !ab__h1619[1] || ab__h1619[0] } ;
assign bram_0_serverAdapterA_s1_1_whas =
bram_0_serverAdapterA_writeWithResp_whas ;
assign bram_0_serverAdapterB_outData_enqData_wget = bram_0_memory_DOB ;
assign bram_0_serverAdapterB_outData_enqData_whas =
(!bram_0_serverAdapterB_s1[0] ||
bram_0_serverAdapterB_outDataCore_FULL_N) &&
bram_0_serverAdapterB_s1[1] &&
bram_0_serverAdapterB_s1[0] ;
assign bram_0_serverAdapterB_outData_outData_wget =
bram_0_serverAdapterB_outDataCore_EMPTY_N ?
bram_0_serverAdapterB_outDataCore_D_OUT :
bram_0_memory_DOB ;
assign bram_0_serverAdapterB_outData_outData_whas =
bram_0_serverAdapterB_outDataCore_EMPTY_N ||
!bram_0_serverAdapterB_outDataCore_EMPTY_N &&
bram_0_serverAdapterB_outData_enqData_whas ;
assign bram_0_serverAdapterB_cnt_1_wget = 3'd1 ;
assign bram_0_serverAdapterB_cnt_1_whas =
(WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ||
WILL_FIRE_RL_wmi_doWriteReq ||
WILL_FIRE_RL_wmi_doWriteFinalize) &&
(!ab__h3026[1] || ab__h3026[0]) ;
assign bram_0_serverAdapterB_cnt_2_wget = 3'd7 ;
assign bram_0_serverAdapterB_cnt_2_whas =
bram_0_serverAdapterB_outData_deqCalled_whas ;
assign bram_0_serverAdapterB_cnt_3_wget = 3'h0 ;
assign bram_0_serverAdapterB_cnt_3_whas = 1'b0 ;
assign bram_0_serverAdapterB_writeWithResp_wget = ab__h3026 ;
assign bram_0_serverAdapterB_writeWithResp_whas =
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ||
WILL_FIRE_RL_wmi_doWriteReq ||
WILL_FIRE_RL_wmi_doWriteFinalize ;
assign bram_0_serverAdapterB_s1_1_wget =
{ 1'd1, !ab__h3026[1] || ab__h3026[0] } ;
assign bram_0_serverAdapterB_s1_1_whas =
bram_0_serverAdapterB_writeWithResp_whas ;
assign bram_1_serverAdapterA_outData_enqData_wget = bram_1_memory_DOA ;
assign bram_1_serverAdapterA_outData_enqData_whas =
(!bram_1_serverAdapterA_s1[0] ||
bram_1_serverAdapterA_outDataCore_FULL_N) &&
bram_1_serverAdapterA_s1[1] &&
bram_1_serverAdapterA_s1[0] ;
assign bram_1_serverAdapterA_outData_outData_wget =
bram_1_serverAdapterA_outDataCore_EMPTY_N ?
bram_1_serverAdapterA_outDataCore_D_OUT :
bram_1_memory_DOA ;
assign bram_1_serverAdapterA_outData_outData_whas =
bram_1_serverAdapterA_outDataCore_EMPTY_N ||
!bram_1_serverAdapterA_outDataCore_EMPTY_N &&
bram_1_serverAdapterA_outData_enqData_whas ;
assign bram_1_serverAdapterA_cnt_1_wget = 3'd1 ;
assign bram_1_serverAdapterA_cnt_1_whas =
(MUX_bram_1_memory_a_put_1__SEL_1 ||
MUX_bram_1_memory_a_put_1__SEL_2 ||
MUX_bram_1_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) &&
(!ab__h4569[1] || ab__h4569[0]) ;
assign bram_1_serverAdapterA_cnt_2_wget = 3'd7 ;
assign bram_1_serverAdapterA_cnt_2_whas =
bram_1_serverAdapterA_outData_deqCalled_whas ;
assign bram_1_serverAdapterA_cnt_3_wget = 3'h0 ;
assign bram_1_serverAdapterA_cnt_3_whas = 1'b0 ;
assign bram_1_serverAdapterA_writeWithResp_wget = ab__h4569 ;
assign bram_1_serverAdapterA_writeWithResp_whas =
MUX_bram_1_memory_a_put_1__SEL_1 ||
MUX_bram_1_memory_a_put_1__SEL_2 ||
MUX_bram_1_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_1_serverAdapterA_s1_1_wget =
{ 1'd1, !ab__h4569[1] || ab__h4569[0] } ;
assign bram_1_serverAdapterA_s1_1_whas =
bram_1_serverAdapterA_writeWithResp_whas ;
assign bram_1_serverAdapterB_outData_enqData_wget = bram_1_memory_DOB ;
assign bram_1_serverAdapterB_outData_enqData_whas =
(!bram_1_serverAdapterB_s1[0] ||
bram_1_serverAdapterB_outDataCore_FULL_N) &&
bram_1_serverAdapterB_s1[1] &&
bram_1_serverAdapterB_s1[0] ;
assign bram_1_serverAdapterB_outData_outData_wget =
bram_1_serverAdapterB_outDataCore_EMPTY_N ?
bram_1_serverAdapterB_outDataCore_D_OUT :
bram_1_memory_DOB ;
assign bram_1_serverAdapterB_outData_outData_whas =
bram_1_serverAdapterB_outDataCore_EMPTY_N ||
!bram_1_serverAdapterB_outDataCore_EMPTY_N &&
bram_1_serverAdapterB_outData_enqData_whas ;
assign bram_1_serverAdapterB_cnt_1_wget = 3'd1 ;
assign bram_1_serverAdapterB_cnt_1_whas =
(WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ||
WILL_FIRE_RL_wmi_doWriteReq ||
WILL_FIRE_RL_wmi_doWriteFinalize) &&
(!ab__h5974[1] || ab__h5974[0]) ;
assign bram_1_serverAdapterB_cnt_2_wget = 3'd7 ;
assign bram_1_serverAdapterB_cnt_2_whas =
bram_0_serverAdapterB_outData_deqCalled_whas ;
assign bram_1_serverAdapterB_cnt_3_wget = 3'h0 ;
assign bram_1_serverAdapterB_cnt_3_whas = 1'b0 ;
assign bram_1_serverAdapterB_writeWithResp_wget = ab__h5974 ;
assign bram_1_serverAdapterB_writeWithResp_whas =
bram_0_serverAdapterB_writeWithResp_whas ;
assign bram_1_serverAdapterB_s1_1_wget =
{ 1'd1, !ab__h5974[1] || ab__h5974[0] } ;
assign bram_1_serverAdapterB_s1_1_whas =
bram_0_serverAdapterB_writeWithResp_whas ;
assign bram_2_serverAdapterA_outData_enqData_wget = bram_2_memory_DOA ;
assign bram_2_serverAdapterA_outData_enqData_whas =
(!bram_2_serverAdapterA_s1[0] ||
bram_2_serverAdapterA_outDataCore_FULL_N) &&
bram_2_serverAdapterA_s1[1] &&
bram_2_serverAdapterA_s1[0] ;
assign bram_2_serverAdapterA_outData_outData_wget =
WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq ?
bram_2_memory_DOA :
bram_2_serverAdapterA_outDataCore_D_OUT ;
assign bram_2_serverAdapterA_outData_outData_whas =
WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq ||
bram_2_serverAdapterA_outDataCore_EMPTY_N ;
assign bram_2_serverAdapterA_cnt_1_wget = 3'd1 ;
assign bram_2_serverAdapterA_cnt_1_whas =
(MUX_bram_2_memory_a_put_1__SEL_1 ||
MUX_bram_2_memory_a_put_1__SEL_2 ||
MUX_bram_2_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) &&
(!ab__h7517[1] || ab__h7517[0]) ;
assign bram_2_serverAdapterA_cnt_2_wget = 3'd7 ;
assign bram_2_serverAdapterA_cnt_2_whas =
bram_2_serverAdapterA_outData_deqCalled_whas ;
assign bram_2_serverAdapterA_cnt_3_wget = 3'h0 ;
assign bram_2_serverAdapterA_cnt_3_whas = 1'b0 ;
assign bram_2_serverAdapterA_writeWithResp_wget = ab__h7517 ;
assign bram_2_serverAdapterA_writeWithResp_whas =
MUX_bram_2_memory_a_put_1__SEL_1 ||
MUX_bram_2_memory_a_put_1__SEL_2 ||
MUX_bram_2_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_2_serverAdapterA_s1_1_wget =
{ 1'd1, !ab__h7517[1] || ab__h7517[0] } ;
assign bram_2_serverAdapterA_s1_1_whas =
bram_2_serverAdapterA_writeWithResp_whas ;
assign bram_2_serverAdapterB_outData_enqData_wget = bram_2_memory_DOB ;
assign bram_2_serverAdapterB_outData_enqData_whas =
(!bram_2_serverAdapterB_s1[0] ||
bram_2_serverAdapterB_outDataCore_FULL_N) &&
bram_2_serverAdapterB_s1[1] &&
bram_2_serverAdapterB_s1[0] ;
assign bram_2_serverAdapterB_outData_outData_wget =
bram_2_serverAdapterB_outDataCore_EMPTY_N ?
bram_2_serverAdapterB_outDataCore_D_OUT :
bram_2_memory_DOB ;
assign bram_2_serverAdapterB_outData_outData_whas =
bram_2_serverAdapterB_outDataCore_EMPTY_N ||
!bram_2_serverAdapterB_outDataCore_EMPTY_N &&
bram_2_serverAdapterB_outData_enqData_whas ;
assign bram_2_serverAdapterB_cnt_1_wget = 3'd1 ;
assign bram_2_serverAdapterB_cnt_1_whas =
(WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ||
WILL_FIRE_RL_wmi_doWriteReq ||
WILL_FIRE_RL_wmi_doWriteFinalize) &&
(!ab__h8922[1] || ab__h8922[0]) ;
assign bram_2_serverAdapterB_cnt_2_wget = 3'd7 ;
assign bram_2_serverAdapterB_cnt_2_whas =
bram_0_serverAdapterB_outData_deqCalled_whas ;
assign bram_2_serverAdapterB_cnt_3_wget = 3'h0 ;
assign bram_2_serverAdapterB_cnt_3_whas = 1'b0 ;
assign bram_2_serverAdapterB_writeWithResp_wget = ab__h8922 ;
assign bram_2_serverAdapterB_writeWithResp_whas =
bram_0_serverAdapterB_writeWithResp_whas ;
assign bram_2_serverAdapterB_s1_1_wget =
{ 1'd1, !ab__h8922[1] || ab__h8922[0] } ;
assign bram_2_serverAdapterB_s1_1_whas =
bram_0_serverAdapterB_writeWithResp_whas ;
assign bram_3_serverAdapterA_outData_enqData_wget = bram_3_memory_DOA ;
assign bram_3_serverAdapterA_outData_enqData_whas =
(!bram_3_serverAdapterA_s1[0] ||
bram_3_serverAdapterA_outDataCore_FULL_N) &&
bram_3_serverAdapterA_s1[1] &&
bram_3_serverAdapterA_s1[0] ;
assign bram_3_serverAdapterA_outData_outData_wget =
bram_3_serverAdapterA_outDataCore_EMPTY_N ?
bram_3_serverAdapterA_outDataCore_D_OUT :
bram_3_memory_DOA ;
assign bram_3_serverAdapterA_outData_outData_whas =
bram_3_serverAdapterA_outDataCore_EMPTY_N ||
!bram_3_serverAdapterA_outDataCore_EMPTY_N &&
bram_3_serverAdapterA_outData_enqData_whas ;
assign bram_3_serverAdapterA_cnt_1_wget = 3'd1 ;
assign bram_3_serverAdapterA_cnt_1_whas =
(MUX_bram_3_memory_a_put_1__SEL_1 ||
MUX_bram_3_memory_a_put_1__SEL_2 ||
MUX_bram_3_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) &&
(!ab__h10465[1] || ab__h10465[0]) ;
assign bram_3_serverAdapterA_cnt_2_wget = 3'd7 ;
assign bram_3_serverAdapterA_cnt_2_whas =
bram_3_serverAdapterA_outData_deqCalled_whas ;
assign bram_3_serverAdapterA_cnt_3_wget = 3'h0 ;
assign bram_3_serverAdapterA_cnt_3_whas = 1'b0 ;
assign bram_3_serverAdapterA_writeWithResp_wget = ab__h10465 ;
assign bram_3_serverAdapterA_writeWithResp_whas =
MUX_bram_3_memory_a_put_1__SEL_1 ||
MUX_bram_3_memory_a_put_1__SEL_2 ||
MUX_bram_3_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_3_serverAdapterA_s1_1_wget =
{ 1'd1, !ab__h10465[1] || ab__h10465[0] } ;
assign bram_3_serverAdapterA_s1_1_whas =
bram_3_serverAdapterA_writeWithResp_whas ;
assign bram_3_serverAdapterB_outData_enqData_wget = bram_3_memory_DOB ;
assign bram_3_serverAdapterB_outData_enqData_whas =
(!bram_3_serverAdapterB_s1[0] ||
bram_3_serverAdapterB_outDataCore_FULL_N) &&
bram_3_serverAdapterB_s1[1] &&
bram_3_serverAdapterB_s1[0] ;
assign bram_3_serverAdapterB_outData_outData_wget =
bram_3_serverAdapterB_outDataCore_EMPTY_N ?
bram_3_serverAdapterB_outDataCore_D_OUT :
bram_3_memory_DOB ;
assign bram_3_serverAdapterB_outData_outData_whas =
bram_3_serverAdapterB_outDataCore_EMPTY_N ||
!bram_3_serverAdapterB_outDataCore_EMPTY_N &&
bram_3_serverAdapterB_outData_enqData_whas ;
assign bram_3_serverAdapterB_cnt_1_wget = 3'd1 ;
assign bram_3_serverAdapterB_cnt_1_whas =
(WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ||
WILL_FIRE_RL_wmi_doWriteReq ||
WILL_FIRE_RL_wmi_doWriteFinalize) &&
(!ab__h11870[1] || ab__h11870[0]) ;
assign bram_3_serverAdapterB_cnt_2_wget = 3'd7 ;
assign bram_3_serverAdapterB_cnt_2_whas =
bram_0_serverAdapterB_outData_deqCalled_whas ;
assign bram_3_serverAdapterB_cnt_3_wget = 3'h0 ;
assign bram_3_serverAdapterB_cnt_3_whas = 1'b0 ;
assign bram_3_serverAdapterB_writeWithResp_wget = ab__h11870 ;
assign bram_3_serverAdapterB_writeWithResp_whas =
bram_0_serverAdapterB_writeWithResp_whas ;
assign bram_3_serverAdapterB_s1_1_wget =
{ 1'd1, !ab__h11870[1] || ab__h11870[0] } ;
assign bram_3_serverAdapterB_s1_1_whas =
bram_0_serverAdapterB_writeWithResp_whas ;
assign wci_wciReq_wget =
{ wci_s_MCmd,
wci_s_MAddrSpace,
wci_s_MByteEn,
wci_s_MAddr,
wci_s_MData } ;
assign wci_wciReq_whas = 1'd1 ;
assign wci_respF_x_wire_wget = MUX_wci_respF_q_0_write_1__VAL_2 ;
assign wci_respF_x_wire_whas = wci_respF_enqueueing_whas ;
assign wci_wEdge_wget = wci_reqF_D_OUT[36:34] ;
assign wci_wEdge_whas = WILL_FIRE_RL_wci_ctl_op_start ;
assign wci_sFlagReg_1_wget = 1'b0 ;
assign wci_sFlagReg_1_whas = 1'b0 ;
assign wci_ctlAckReg_1_wget = 1'd1 ;
assign wci_ctlAckReg_1_whas =
wci_wci_ctrl_pw_whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd2 &&
wci_reqF_D_OUT[36:34] == 3'd3 ||
wci_wci_ctrl_pw_whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd0 &&
wci_reqF_D_OUT[36:34] == 3'd0 ||
WILL_FIRE_RL_bml_initAccumulators ;
assign wti_wtiReq_wget = 67'h0 ;
assign wti_wtiReq_whas = 1'b0 ;
assign wti_operateD_1_wget = 1'b0 ;
assign wti_operateD_1_whas = 1'b0 ;
assign tlp_remStart_1_wget = 1'd1 ;
assign tlp_remStart_1_whas =
WILL_FIRE_RL_tlp_dmaRequestFarMeta ||
WILL_FIRE_RL_tlp_dmaXmtDoorbell ||
WILL_FIRE_RL_tlp_dmaRequestNearMeta ;
assign tlp_remDone_1_wget = 1'd1 ;
assign tlp_remDone_1_whas =
MUX_tlp_remDone_1_wset_1__SEL_1 ||
WILL_FIRE_RL_tlp_dmaXmtMetaBody ;
assign tlp_nearBufReady_1_wget = 1'd1 ;
assign tlp_nearBufReady_1_whas =
wci_cState == 3'd2 && bml_lclBufsCF != 16'd0 ;
assign tlp_farBufReady_1_wget = 1'd1 ;
assign tlp_farBufReady_1_whas =
wci_cState == 3'd2 && bml_fabBufsAvail != 16'd0 ;
assign tlp_creditReady_1_wget = 1'd1 ;
assign tlp_creditReady_1_whas =
wci_cState == 3'd2 && bml_lclCredit != 16'd0 ;
assign tlp_dpControl_wget = dpControl ;
assign tlp_dpControl_whas = 1'd1 ;
assign tlp_pullTagMatch_1_wget =
tagm__h64387 == tlp_inF_D_OUT[47:40] &&
tlp_inF_first__259_BITS_63_TO_56_262_EQ_pciDev_ETC___d1272 ;
assign tlp_pullTagMatch_1_whas =
tlp_inF_EMPTY_N && hasPull && dpControl[7:4] == 4'd0 &&
dpControl[3:2] == 2'd2 &&
dpControl[1:0] == 2'd1 ;
assign tlp_nowW_wget = wti_nowReq[63:0] ;
assign tlp_nowW_whas = 1'd1 ;
assign tlp_dmaStartMark_1_wget = 1'd1 ;
assign tlp_dmaStartMark_1_whas =
WILL_FIRE_RL_tlp_dmaRequestFarMeta ||
WILL_FIRE_RL_tlp_dmaRequestNearMeta ;
assign tlp_dmaDoneMark_1_wget = 1'd1 ;
assign tlp_dmaDoneMark_1_whas = WILL_FIRE_RL_tlp_dmaTailEventSender ;
assign wmi_wmi_wmiReq_wget =
{ wmiS0_MCmd,
wmiS0_MReqLast,
wmiS0_MReqInfo,
wmiS0_MAddrSpace,
wmiS0_MAddr,
wmiS0_MBurstLength } ;
assign wmi_wmi_wmiReq_whas = 1'd1 ;
assign wmi_wmi_wmiMFlag_wget = wmiS0_arg_mFlag ;
assign wmi_wmi_wmiMFlag_whas = 1'd1 ;
assign wmi_wmi_wmiDh_wget =
{ wmiS0_MDataValid,
wmiS0_MDataLast,
wmiS0_MData,
wmiS0_MDataByteEn } ;
assign wmi_wmi_wmiDh_whas = 1'd1 ;
assign wmi_wmi_respF_x_wire_wget = MUX_wmi_wmi_respF_q_0_write_1__VAL_2 ;
assign wmi_wmi_respF_x_wire_whas = WILL_FIRE_RL_wmi_doReadResp ;
assign wmi_wmi_operateD_1_wget = 1'd1 ;
assign wmi_wmi_operateD_1_whas = wci_cState == 3'd2 ;
assign wmi_wmi_peerIsReady_1_wget = 1'd1 ;
assign wmi_wmi_peerIsReady_1_whas = wmiS0_MReset_n ;
assign wmi_wmi_sThreadBusy_dw_wget = wmi_wmi_reqF_countReg > 2'd1 ;
assign wmi_wmi_sThreadBusy_dw_whas =
wmi_wmi_reqF_levelsValid && wmi_wmi_operateD &&
wmi_wmi_peerIsReady &&
!wmi_wmi_forceSThreadBusy_pw_whas ;
assign wmi_wmi_sDataThreadBusy_dw_wget = wmi_wmi_dhF_countReg > 2'd1 ;
assign wmi_wmi_sDataThreadBusy_dw_whas =
wmi_wmi_dhF_levelsValid && wmi_wmi_operateD &&
wmi_wmi_peerIsReady ;
assign wmi_mesgStart_1_wget = 1'd1 ;
assign wmi_mesgStart_1_whas = WILL_FIRE_RL_wmi_getRequest && !wmi_mesgBusy ;
assign wmi_mesgDone_1_wget = 1'd1 ;
assign wmi_mesgDone_1_whas =
WILL_FIRE_RL_wmi_doReadReq && wmi_bytesRemainReq == 14'd16 &&
wmi_doneWithMesg ||
WILL_FIRE_RL_wmi_doWriteFinalize ;
assign wmi_mesgBufReady_1_wget = 1'd1 ;
assign wmi_mesgBufReady_1_whas =
wci_cState == 3'd2 && bml_lclBufsAR != 16'd0 ;
assign wmi_dpControl_wget = dpControl ;
assign wmi_dpControl_whas = 1'd1 ;
assign wmi_nowW_wget = wti_nowReq[63:0] ;
assign wmi_nowW_whas = 1'd1 ;
assign bml_lclBufStart_1_wget = 1'd1 ;
assign bml_lclBufStart_1_whas = wmi_mesgStart ;
assign bml_lclBufDone_1_wget = 1'd1 ;
assign bml_lclBufDone_1_whas = wmi_mesgDone ;
assign bml_remStart_1_wget = 1'd1 ;
assign bml_remStart_1_whas = tlp_remStart ;
assign bml_remDone_1_wget = 1'd1 ;
assign bml_remDone_1_whas = tlp_remDone ;
assign bml_fabDone_1_wget = 1'd1 ;
assign bml_fabDone_1_whas =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h18 &&
dpControl[1:0] != 2'd1 ;
assign bml_fabAvail_1_wget = 1'd1 ;
assign bml_fabAvail_1_whas =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h18 &&
dpControl[1:0] == 2'd1 ;
assign bml_datumAReg_1_wget = bml_remDone ;
assign bml_datumAReg_1_whas = wci_cState == 3'd2 ;
assign bml_dpControl_wget = dpControl ;
assign bml_dpControl_whas = 1'd1 ;
assign wci_Es_mCmd_w_wget = wci_s_MCmd ;
assign wci_Es_mCmd_w_whas = 1'd1 ;
assign wci_Es_mAddrSpace_w_wget = wci_s_MAddrSpace ;
assign wci_Es_mAddrSpace_w_whas = 1'd1 ;
assign wci_Es_mByteEn_w_wget = wci_s_MByteEn ;
assign wci_Es_mByteEn_w_whas = 1'd1 ;
assign wci_Es_mAddr_w_wget = wci_s_MAddr ;
assign wci_Es_mAddr_w_whas = 1'd1 ;
assign wci_Es_mData_w_wget = wci_s_MData ;
assign wci_Es_mData_w_whas = 1'd1 ;
assign wmi_Es_mCmd_w_wget = wmiS0_MCmd ;
assign wmi_Es_mCmd_w_whas = 1'd1 ;
assign wmi_Es_mReqInfo_w_wget = wmiS0_MReqInfo ;
assign wmi_Es_mReqInfo_w_whas = 1'd1 ;
assign wmi_Es_mAddrSpace_w_wget = wmiS0_MAddrSpace ;
assign wmi_Es_mAddrSpace_w_whas = 1'd1 ;
assign wmi_Es_mAddr_w_wget = wmiS0_MAddr ;
assign wmi_Es_mAddr_w_whas = 1'd1 ;
assign wmi_Es_mBurstLength_w_wget = wmiS0_MBurstLength ;
assign wmi_Es_mBurstLength_w_whas = 1'd1 ;
assign wmi_Es_mData_w_wget = wmiS0_MData ;
assign wmi_Es_mData_w_whas = 1'd1 ;
assign wmi_Es_mDataByteEn_w_wget = wmiS0_MDataByteEn ;
assign wmi_Es_mDataByteEn_w_whas = 1'd1 ;
assign bram_0_serverAdapterA_outData_deqCalled_whas =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp &&
tlp_tlpBRAM_readReq_D_OUT[30:29] == 2'd0 &&
!tlp_tlpBRAM_readReq_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ;
assign bram_0_serverAdapterB_outData_deqCalled_whas =
WILL_FIRE_RL_wmi_respMetadata || WILL_FIRE_RL_wmi_doReadResp ;
assign bram_1_serverAdapterA_outData_deqCalled_whas =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp &&
tlp_tlpBRAM_readReq_D_OUT[30:29] == 2'd1 &&
!tlp_tlpBRAM_readReq_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ;
assign bram_1_serverAdapterB_outData_deqCalled_whas =
bram_0_serverAdapterB_outData_deqCalled_whas ;
assign bram_2_serverAdapterA_outData_deqCalled_whas =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp &&
tlp_tlpBRAM_readReq_D_OUT[30:29] == 2'd2 &&
!tlp_tlpBRAM_readReq_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ;
assign bram_2_serverAdapterB_outData_deqCalled_whas =
bram_0_serverAdapterB_outData_deqCalled_whas ;
assign bram_3_serverAdapterA_outData_deqCalled_whas =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp &&
tlp_tlpBRAM_readReq_D_OUT[30:29] == 2'd3 &&
!tlp_tlpBRAM_readReq_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ;
assign bram_3_serverAdapterB_outData_deqCalled_whas =
bram_0_serverAdapterB_outData_deqCalled_whas ;
assign wci_reqF_r_enq_whas = wci_wciReq_wget[71:69] != 3'd0 ;
assign wci_reqF_r_deq_whas =
WILL_FIRE_RL_wci_ctl_op_start || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_reqF_r_clr_whas = 1'b0 ;
assign wci_respF_enqueueing_whas =
WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_respF_dequeueing_whas = wci_respF_cntr_r != 2'd0 ;
assign wci_sThreadBusy_pw_whas = 1'b0 ;
assign wci_wci_cfwr_pw_whas =
wci_reqF_EMPTY_N && wci_reqF_D_OUT[68] &&
wci_reqF_D_OUT[71:69] == 3'd1 ;
assign wci_wci_cfrd_pw_whas =
wci_reqF_EMPTY_N && wci_reqF_D_OUT[68] &&
wci_reqF_D_OUT[71:69] == 3'd2 ;
assign wci_wci_ctrl_pw_whas =
wci_reqF_EMPTY_N && !wci_reqF_D_OUT[68] &&
wci_reqF_D_OUT[71:69] == 3'd2 ;
assign wmi_wmi_forceSThreadBusy_pw_whas =
dpControl[3:2] != 2'd1 && !wmi_mesgMeta[128] ||
dpControl[3:2] == 2'd1 && !wmi_mesgBufReady ;
assign wmi_wmi_reqF_r_enq_whas =
MUX_wmi_wmi_reqF_levelsValid_write_1__SEL_2 ;
assign wmi_wmi_reqF_r_deq_whas = WILL_FIRE_RL_wmi_getRequest ;
assign wmi_wmi_reqF_r_clr_whas = 1'b0 ;
assign wmi_wmi_reqF_doResetEnq_whas =
MUX_wmi_wmi_reqF_levelsValid_write_1__SEL_2 ;
assign wmi_wmi_reqF_doResetDeq_whas = WILL_FIRE_RL_wmi_getRequest ;
assign wmi_wmi_reqF_doResetClr_whas = 1'b0 ;
assign wmi_wmi_mFlagF_r_enq_whas =
MUX_wmi_wmi_mFlagF_levelsValid_write_1__SEL_2 ;
assign wmi_wmi_mFlagF_r_deq_whas = WILL_FIRE_RL_wmi_doWriteFinalize ;
assign wmi_wmi_mFlagF_r_clr_whas = 1'b0 ;
assign wmi_wmi_mFlagF_doResetEnq_whas =
MUX_wmi_wmi_mFlagF_levelsValid_write_1__SEL_2 ;
assign wmi_wmi_mFlagF_doResetDeq_whas = WILL_FIRE_RL_wmi_doWriteFinalize ;
assign wmi_wmi_mFlagF_doResetClr_whas = 1'b0 ;
assign wmi_wmi_dhF_r_enq_whas = MUX_wmi_wmi_dhF_levelsValid_write_1__SEL_2 ;
assign wmi_wmi_dhF_r_deq_whas = WILL_FIRE_RL_wmi_doWriteReq ;
assign wmi_wmi_dhF_r_clr_whas = 1'b0 ;
assign wmi_wmi_dhF_doResetEnq_whas =
MUX_wmi_wmi_dhF_levelsValid_write_1__SEL_2 ;
assign wmi_wmi_dhF_doResetDeq_whas = WILL_FIRE_RL_wmi_doWriteReq ;
assign wmi_wmi_dhF_doResetClr_whas = 1'b0 ;
assign wmi_wmi_respF_enqueueing_whas = WILL_FIRE_RL_wmi_doReadResp ;
assign wmi_wmi_respF_dequeueing_whas = wmi_wmi_respF_cntr_r != 2'd0 ;
assign bml_lclBuf_incAction_whas = WILL_FIRE_RL_bml_lclAdvance ;
assign bml_lclBuf_decAction_whas = 1'b0 ;
assign bml_remBuf_incAction_whas = WILL_FIRE_RL_bml_remAdvance ;
assign bml_remBuf_decAction_whas = 1'b0 ;
assign bml_fabBuf_incAction_whas = MUX_bml_fabFlowAddr_write_1__SEL_1 ;
assign bml_fabBuf_decAction_whas = 1'b0 ;
assign bml_crdBuf_incAction_whas = WILL_FIRE_RL_bml_crdAdvance ;
assign bml_crdBuf_decAction_whas = 1'b0 ;
assign wmi_Es_mReqLast_w_whas = wmiS0_MReqLast ;
assign wmi_Es_mDataValid_w_whas = wmiS0_MDataValid ;
assign wmi_Es_mDataLast_w_whas = wmiS0_MDataLast ;
assign wmi_Es_mDataInfo_w_whas = 1'd1 ;
assign bml_lclBuf_modulus_bw_wget = bml_lclBuf_modulus ;
assign bml_remBuf_modulus_bw_wget = bml_remBuf_modulus ;
assign bml_fabBuf_modulus_bw_wget = bml_fabBuf_modulus ;
assign bml_crdBuf_modulus_bw_wget = bml_crdBuf_modulus ;
// register bml_crdBuf_modulus
assign bml_crdBuf_modulus_D_IN = bml_lclNumBufs - 16'd1 ;
assign bml_crdBuf_modulus_EN = WILL_FIRE_RL_bml_initAccumulators ;
// register bml_crdBuf_value
assign bml_crdBuf_value_D_IN =
WILL_FIRE_RL_bml_initAccumulators ?
16'd0 :
MUX_bml_crdBuf_value_write_1__VAL_3 ;
assign bml_crdBuf_value_EN =
WILL_FIRE_RL_bml_crdAdvance ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_datumAReg
assign bml_datumAReg_D_IN = CAN_FIRE_RL_bml_remAdvance ;
assign bml_datumAReg_EN = 1'd1 ;
// register bml_fabAvail
assign bml_fabAvail_D_IN = bml_fabAvail_1_whas ;
assign bml_fabAvail_EN = 1'd1 ;
// register bml_fabBuf_modulus
assign bml_fabBuf_modulus_D_IN = bml_fabNumBufs - 16'd1 ;
assign bml_fabBuf_modulus_EN = WILL_FIRE_RL_bml_initAccumulators ;
// register bml_fabBuf_value
assign bml_fabBuf_value_D_IN =
WILL_FIRE_RL_bml_initAccumulators ?
16'd0 :
MUX_bml_fabBuf_value_write_1__VAL_3 ;
assign bml_fabBuf_value_EN =
MUX_bml_fabFlowAddr_write_1__SEL_1 ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_fabBufsAvail
assign bml_fabBufsAvail_D_IN =
MUX_bml_fabBufsAvail_write_1__SEL_1 ?
MUX_bml_fabBufsAvail_write_1__VAL_1 :
MUX_bml_fabBufsAvail_write_1__VAL_2 ;
assign bml_fabBufsAvail_EN =
WILL_FIRE_RL_bml_fba &&
(bml_fabAvail && !bml_remStart ||
!bml_fabAvail && bml_remStart) ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_fabDone
assign bml_fabDone_D_IN = bml_fabDone_1_whas ;
assign bml_fabDone_EN = 1'd1 ;
// register bml_fabFlowAddr
always@(MUX_bml_fabFlowAddr_write_1__SEL_1 or
MUX_bml_fabFlowAddr_write_1__VAL_1 or
WILL_FIRE_RL_bml_initAccumulators or
bml_fabFlowBase or
WILL_FIRE_RL_bml_crdAdvance or MUX_bml_fabFlowAddr_write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_bml_fabFlowAddr_write_1__SEL_1:
bml_fabFlowAddr_D_IN = MUX_bml_fabFlowAddr_write_1__VAL_1;
WILL_FIRE_RL_bml_initAccumulators:
bml_fabFlowAddr_D_IN = bml_fabFlowBase;
WILL_FIRE_RL_bml_crdAdvance:
bml_fabFlowAddr_D_IN = MUX_bml_fabFlowAddr_write_1__VAL_3;
default: bml_fabFlowAddr_D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign bml_fabFlowAddr_EN =
WILL_FIRE_RL_bml_remAdvance && dpControl[1:0] == 2'd1 ||
WILL_FIRE_RL_bml_initAccumulators ||
WILL_FIRE_RL_bml_crdAdvance ;
// register bml_fabFlowBase
assign bml_fabFlowBase_D_IN = wci_reqF_D_OUT[31:0] ;
assign bml_fabFlowBase_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h60 ;
// register bml_fabFlowBaseMS
assign bml_fabFlowBaseMS_D_IN = wci_reqF_D_OUT[31:0] ;
assign bml_fabFlowBaseMS_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h9C ;
// register bml_fabFlowSize
assign bml_fabFlowSize_D_IN = wci_reqF_D_OUT[31:0] ;
assign bml_fabFlowSize_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h64 ;
// register bml_fabMesgAddr
assign bml_fabMesgAddr_D_IN =
MUX_bml_fabFlowAddr_write_1__SEL_1 ?
MUX_bml_fabMesgAddr_write_1__VAL_1 :
bml_fabMesgBase ;
assign bml_fabMesgAddr_EN =
WILL_FIRE_RL_bml_remAdvance && dpControl[1:0] == 2'd1 ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_fabMesgBase
assign bml_fabMesgBase_D_IN = wci_reqF_D_OUT[31:0] ;
assign bml_fabMesgBase_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h50 ;
// register bml_fabMesgBaseMS
assign bml_fabMesgBaseMS_D_IN = wci_reqF_D_OUT[31:0] ;
assign bml_fabMesgBaseMS_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h94 ;
// register bml_fabMesgSize
assign bml_fabMesgSize_D_IN = wci_reqF_D_OUT[31:0] ;
assign bml_fabMesgSize_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h58 ;
// register bml_fabMetaAddr
assign bml_fabMetaAddr_D_IN =
MUX_bml_fabFlowAddr_write_1__SEL_1 ?
MUX_bml_fabMetaAddr_write_1__VAL_1 :
bml_fabMetaBase ;
assign bml_fabMetaAddr_EN =
WILL_FIRE_RL_bml_remAdvance && dpControl[1:0] == 2'd1 ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_fabMetaBase
assign bml_fabMetaBase_D_IN = wci_reqF_D_OUT[31:0] ;
assign bml_fabMetaBase_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h54 ;
// register bml_fabMetaBaseMS
assign bml_fabMetaBaseMS_D_IN = wci_reqF_D_OUT[31:0] ;
assign bml_fabMetaBaseMS_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h98 ;
// register bml_fabMetaSize
assign bml_fabMetaSize_D_IN = wci_reqF_D_OUT[31:0] ;
assign bml_fabMetaSize_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h5C ;
// register bml_fabNumBufs
assign bml_fabNumBufs_D_IN = wci_reqF_D_OUT[15:0] ;
assign bml_fabNumBufs_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h04 ;
// register bml_lclBufDone
assign bml_lclBufDone_D_IN = wmi_mesgDone ;
assign bml_lclBufDone_EN = 1'd1 ;
// register bml_lclBufStart
assign bml_lclBufStart_D_IN = wmi_mesgStart ;
assign bml_lclBufStart_EN = 1'd1 ;
// register bml_lclBuf_modulus
assign bml_lclBuf_modulus_D_IN = bml_crdBuf_modulus_D_IN ;
assign bml_lclBuf_modulus_EN = WILL_FIRE_RL_bml_initAccumulators ;
// register bml_lclBuf_value
assign bml_lclBuf_value_D_IN =
WILL_FIRE_RL_bml_initAccumulators ?
16'd0 :
MUX_bml_lclBuf_value_write_1__VAL_3 ;
assign bml_lclBuf_value_EN =
WILL_FIRE_RL_bml_lclAdvance ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_lclBufsAR
assign bml_lclBufsAR_D_IN =
MUX_bml_lclBufsAR_write_1__SEL_1 ?
MUX_bml_lclBufsAR_write_1__VAL_1 :
MUX_bml_lclBufsAR_write_1__VAL_2 ;
assign bml_lclBufsAR_EN =
wci_cState == 3'd2 &&
IF_bml_dpControl_wget__898_BITS_1_TO_0_904_EQ__ETC___d1984 ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_lclBufsCF
assign bml_lclBufsCF_D_IN =
MUX_bml_lclBufsCF_write_1__SEL_1 ?
MUX_bml_lclBufsCF_write_1__VAL_1 :
MUX_bml_lclBufsCF_write_1__VAL_2 ;
assign bml_lclBufsCF_EN =
wci_cState == 3'd2 &&
bml_lclBufDone_922_AND_IF_bml_dpControl_wget___ETC___d2003 ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_lclCredit
assign bml_lclCredit_D_IN =
MUX_bml_lclCredit_write_1__SEL_1 ?
MUX_bml_lclCredit_write_1__VAL_1 :
16'd0 ;
assign bml_lclCredit_EN =
WILL_FIRE_RL_bml_lcredit &&
(bml_lclBufDone && !bml_remStart ||
!bml_lclBufDone && bml_remStart) ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_lclDones
assign bml_lclDones_D_IN = bml_lclDones + 16'd1 ;
assign bml_lclDones_EN = WILL_FIRE_RL_bml_lclAdvance ;
// register bml_lclMesgAddr
assign bml_lclMesgAddr_D_IN =
WILL_FIRE_RL_bml_initAccumulators ?
bml_mesgBase :
MUX_bml_lclMesgAddr_write_1__VAL_2 ;
assign bml_lclMesgAddr_EN =
WILL_FIRE_RL_bml_initAccumulators ||
WILL_FIRE_RL_bml_lclAdvance ;
// register bml_lclMetaAddr
assign bml_lclMetaAddr_D_IN =
WILL_FIRE_RL_bml_initAccumulators ?
bml_metaBase :
MUX_bml_lclMetaAddr_write_1__VAL_2 ;
assign bml_lclMetaAddr_EN =
WILL_FIRE_RL_bml_initAccumulators ||
WILL_FIRE_RL_bml_lclAdvance ;
// register bml_lclNumBufs
assign bml_lclNumBufs_D_IN = wci_reqF_D_OUT[15:0] ;
assign bml_lclNumBufs_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h0 ;
// register bml_lclStarts
assign bml_lclStarts_D_IN = bml_lclStarts + 16'd1 ;
assign bml_lclStarts_EN = wci_cState == 3'd2 && bml_lclBufStart ;
// register bml_mesgBase
assign bml_mesgBase_D_IN = wci_reqF_D_OUT[15:0] ;
assign bml_mesgBase_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h08 ;
// register bml_mesgSize
assign bml_mesgSize_D_IN = wci_reqF_D_OUT[15:0] ;
assign bml_mesgSize_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h10 ;
// register bml_metaBase
assign bml_metaBase_D_IN = wci_reqF_D_OUT[15:0] ;
assign bml_metaBase_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h0C ;
// register bml_metaSize
assign bml_metaSize_D_IN = wci_reqF_D_OUT[15:0] ;
assign bml_metaSize_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h14 ;
// register bml_remBuf_modulus
assign bml_remBuf_modulus_D_IN = bml_crdBuf_modulus_D_IN ;
assign bml_remBuf_modulus_EN = WILL_FIRE_RL_bml_initAccumulators ;
// register bml_remBuf_value
assign bml_remBuf_value_D_IN =
WILL_FIRE_RL_bml_initAccumulators ?
16'd0 :
MUX_bml_remBuf_value_write_1__VAL_3 ;
assign bml_remBuf_value_EN =
WILL_FIRE_RL_bml_remAdvance ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_remDone
assign bml_remDone_D_IN = tlp_remDone ;
assign bml_remDone_EN = 1'd1 ;
// register bml_remDones
assign bml_remDones_D_IN = bml_remDones + 16'd1 ;
assign bml_remDones_EN = CAN_FIRE_RL_bml_remAdvance ;
// register bml_remMesgAddr
assign bml_remMesgAddr_D_IN =
WILL_FIRE_RL_bml_initAccumulators ?
bml_mesgBase :
MUX_bml_remMesgAddr_write_1__VAL_2 ;
assign bml_remMesgAddr_EN =
WILL_FIRE_RL_bml_initAccumulators ||
WILL_FIRE_RL_bml_remAdvance ;
// register bml_remMetaAddr
assign bml_remMetaAddr_D_IN =
WILL_FIRE_RL_bml_initAccumulators ?
bml_metaBase :
MUX_bml_remMetaAddr_write_1__VAL_2 ;
assign bml_remMetaAddr_EN =
WILL_FIRE_RL_bml_initAccumulators ||
WILL_FIRE_RL_bml_remAdvance ;
// register bml_remStart
assign bml_remStart_D_IN = tlp_remStart ;
assign bml_remStart_EN = 1'd1 ;
// register bml_remStarts
assign bml_remStarts_D_IN = bml_remStarts + 16'd1 ;
assign bml_remStarts_EN = wci_cState == 3'd2 && bml_remStart ;
// register bram_0_serverAdapterA_cnt
assign bram_0_serverAdapterA_cnt_D_IN =
bram_0_serverAdapterA_cnt_6_PLUS_IF_bram_0_ser_ETC___d32 ;
assign bram_0_serverAdapterA_cnt_EN =
bram_0_serverAdapterA_cnt_1_whas ||
bram_0_serverAdapterA_outData_deqCalled_whas ;
// register bram_0_serverAdapterA_s1
assign bram_0_serverAdapterA_s1_D_IN =
{ bram_0_serverAdapterA_writeWithResp_whas &&
bram_0_serverAdapterA_s1_1_wget[1],
bram_0_serverAdapterA_s1_1_wget[0] } ;
assign bram_0_serverAdapterA_s1_EN = 1'd1 ;
// register bram_0_serverAdapterB_cnt
assign bram_0_serverAdapterB_cnt_D_IN =
bram_0_serverAdapterB_cnt_5_PLUS_IF_bram_0_ser_ETC___d91 ;
assign bram_0_serverAdapterB_cnt_EN =
bram_0_serverAdapterB_cnt_1_whas ||
bram_0_serverAdapterB_outData_deqCalled_whas ;
// register bram_0_serverAdapterB_s1
assign bram_0_serverAdapterB_s1_D_IN =
{ bram_0_serverAdapterB_writeWithResp_whas &&
bram_0_serverAdapterB_s1_1_wget[1],
bram_0_serverAdapterB_s1_1_wget[0] } ;
assign bram_0_serverAdapterB_s1_EN = 1'd1 ;
// register bram_1_serverAdapterA_cnt
assign bram_1_serverAdapterA_cnt_D_IN =
bram_1_serverAdapterA_cnt_44_PLUS_IF_bram_1_se_ETC___d150 ;
assign bram_1_serverAdapterA_cnt_EN =
bram_1_serverAdapterA_cnt_1_whas ||
bram_1_serverAdapterA_outData_deqCalled_whas ;
// register bram_1_serverAdapterA_s1
assign bram_1_serverAdapterA_s1_D_IN =
{ bram_1_serverAdapterA_writeWithResp_whas &&
bram_1_serverAdapterA_s1_1_wget[1],
bram_1_serverAdapterA_s1_1_wget[0] } ;
assign bram_1_serverAdapterA_s1_EN = 1'd1 ;
// register bram_1_serverAdapterB_cnt
assign bram_1_serverAdapterB_cnt_D_IN =
bram_1_serverAdapterB_cnt_03_PLUS_IF_bram_1_se_ETC___d209 ;
assign bram_1_serverAdapterB_cnt_EN =
bram_1_serverAdapterB_cnt_1_whas ||
bram_0_serverAdapterB_outData_deqCalled_whas ;
// register bram_1_serverAdapterB_s1
assign bram_1_serverAdapterB_s1_D_IN =
{ bram_0_serverAdapterB_writeWithResp_whas &&
bram_1_serverAdapterB_s1_1_wget[1],
bram_1_serverAdapterB_s1_1_wget[0] } ;
assign bram_1_serverAdapterB_s1_EN = 1'd1 ;
// register bram_2_serverAdapterA_cnt
assign bram_2_serverAdapterA_cnt_D_IN =
bram_2_serverAdapterA_cnt_62_PLUS_IF_bram_2_se_ETC___d268 ;
assign bram_2_serverAdapterA_cnt_EN =
bram_2_serverAdapterA_cnt_1_whas ||
bram_2_serverAdapterA_outData_deqCalled_whas ;
// register bram_2_serverAdapterA_s1
assign bram_2_serverAdapterA_s1_D_IN =
{ bram_2_serverAdapterA_writeWithResp_whas &&
bram_2_serverAdapterA_s1_1_wget[1],
bram_2_serverAdapterA_s1_1_wget[0] } ;
assign bram_2_serverAdapterA_s1_EN = 1'd1 ;
// register bram_2_serverAdapterB_cnt
assign bram_2_serverAdapterB_cnt_D_IN =
bram_2_serverAdapterB_cnt_21_PLUS_IF_bram_2_se_ETC___d327 ;
assign bram_2_serverAdapterB_cnt_EN =
bram_2_serverAdapterB_cnt_1_whas ||
bram_0_serverAdapterB_outData_deqCalled_whas ;
// register bram_2_serverAdapterB_s1
assign bram_2_serverAdapterB_s1_D_IN =
{ bram_0_serverAdapterB_writeWithResp_whas &&
bram_2_serverAdapterB_s1_1_wget[1],
bram_2_serverAdapterB_s1_1_wget[0] } ;
assign bram_2_serverAdapterB_s1_EN = 1'd1 ;
// register bram_3_serverAdapterA_cnt
assign bram_3_serverAdapterA_cnt_D_IN =
bram_3_serverAdapterA_cnt_80_PLUS_IF_bram_3_se_ETC___d386 ;
assign bram_3_serverAdapterA_cnt_EN =
bram_3_serverAdapterA_cnt_1_whas ||
bram_3_serverAdapterA_outData_deqCalled_whas ;
// register bram_3_serverAdapterA_s1
assign bram_3_serverAdapterA_s1_D_IN =
{ bram_3_serverAdapterA_writeWithResp_whas &&
bram_3_serverAdapterA_s1_1_wget[1],
bram_3_serverAdapterA_s1_1_wget[0] } ;
assign bram_3_serverAdapterA_s1_EN = 1'd1 ;
// register bram_3_serverAdapterB_cnt
assign bram_3_serverAdapterB_cnt_D_IN =
bram_3_serverAdapterB_cnt_39_PLUS_IF_bram_3_se_ETC___d445 ;
assign bram_3_serverAdapterB_cnt_EN =
bram_3_serverAdapterB_cnt_1_whas ||
bram_0_serverAdapterB_outData_deqCalled_whas ;
// register bram_3_serverAdapterB_s1
assign bram_3_serverAdapterB_s1_D_IN =
{ bram_0_serverAdapterB_writeWithResp_whas &&
bram_3_serverAdapterB_s1_1_wget[1],
bram_3_serverAdapterB_s1_1_wget[0] } ;
assign bram_3_serverAdapterB_s1_EN = 1'd1 ;
// register dmaDoneTime
assign dmaDoneTime_D_IN = wti_nowReq[63:0] ;
assign dmaDoneTime_EN = tlp_dmaDoneMark ;
// register dmaStartTime
assign dmaStartTime_D_IN = wti_nowReq[63:0] ;
assign dmaStartTime_EN = tlp_dmaStartMark ;
// register dpControl
assign dpControl_D_IN = wci_reqF_D_OUT[7:0] ;
assign dpControl_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h68 ;
// register tlp_complTimerCount
assign tlp_complTimerCount_D_IN =
tlp_complTimerRunning ? tlp_complTimerCount + 12'd1 : 12'd0 ;
assign tlp_complTimerCount_EN = 1'd1 ;
// register tlp_complTimerRunning
assign tlp_complTimerRunning_D_IN =
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ||
WILL_FIRE_RL_tlp_dmaRequestFarMeta ;
assign tlp_complTimerRunning_EN =
WILL_FIRE_RL_tlp_dmaPullTailEvent ||
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ||
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ||
WILL_FIRE_RL_tlp_dmaRequestFarMeta ;
// register tlp_creditReady
assign tlp_creditReady_D_IN = tlp_creditReady_1_whas ;
assign tlp_creditReady_EN = 1'd1 ;
// register tlp_dmaDoTailEvent
always@(WILL_FIRE_RL_tlp_dmaPullResponseBody or
MUX_tlp_dmaDoTailEvent_write_1__VAL_1 or
WILL_FIRE_RL_tlp_dmaPullResponseHeader or
tlp_dmaPullRemainDWLen or
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta or
tlp_mesgLengthRemainPull or WILL_FIRE_RL_tlp_dmaPullTailEvent)
case (1'b1)
WILL_FIRE_RL_tlp_dmaPullResponseBody:
tlp_dmaDoTailEvent_D_IN = MUX_tlp_dmaDoTailEvent_write_1__VAL_1;
WILL_FIRE_RL_tlp_dmaPullResponseHeader:
tlp_dmaDoTailEvent_D_IN = tlp_dmaPullRemainDWLen == 10'd1;
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta:
tlp_dmaDoTailEvent_D_IN = tlp_mesgLengthRemainPull == 17'd0;
WILL_FIRE_RL_tlp_dmaPullTailEvent: tlp_dmaDoTailEvent_D_IN = 1'd0;
default: tlp_dmaDoTailEvent_D_IN = 1'b0 /* unspecified value */ ;
endcase
assign tlp_dmaDoTailEvent_EN =
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ||
WILL_FIRE_RL_tlp_dmaPullResponseHeader ||
WILL_FIRE_RL_tlp_dmaPullResponseBody ||
WILL_FIRE_RL_tlp_dmaPullTailEvent ;
// register tlp_dmaDoneMark
assign tlp_dmaDoneMark_D_IN = WILL_FIRE_RL_tlp_dmaTailEventSender ;
assign tlp_dmaDoneMark_EN = 1'd1 ;
// register tlp_dmaPullRemainDWLen
always@(WILL_FIRE_RL_tlp_dmaPullRequestFarMesg or
thisRequestLength__h63893 or
WILL_FIRE_RL_tlp_dmaPullResponseHeader or
MUX_tlp_dmaPullRemainDWLen_write_1__VAL_2 or
WILL_FIRE_RL_tlp_dmaPullResponseBody or
MUX_tlp_dmaPullRemainDWLen_write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg:
tlp_dmaPullRemainDWLen_D_IN = thisRequestLength__h63893[11:2];
WILL_FIRE_RL_tlp_dmaPullResponseHeader:
tlp_dmaPullRemainDWLen_D_IN =
MUX_tlp_dmaPullRemainDWLen_write_1__VAL_2;
WILL_FIRE_RL_tlp_dmaPullResponseBody:
tlp_dmaPullRemainDWLen_D_IN =
MUX_tlp_dmaPullRemainDWLen_write_1__VAL_3;
default: tlp_dmaPullRemainDWLen_D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign tlp_dmaPullRemainDWLen_EN =
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ||
WILL_FIRE_RL_tlp_dmaPullResponseHeader ||
WILL_FIRE_RL_tlp_dmaPullResponseBody ;
// register tlp_dmaPullRemainDWSub
assign tlp_dmaPullRemainDWSub_D_IN =
WILL_FIRE_RL_tlp_dmaPullResponseHeader ?
MUX_tlp_dmaPullRemainDWSub_write_1__VAL_1 :
MUX_tlp_dmaPullRemainDWSub_write_1__VAL_2 ;
assign tlp_dmaPullRemainDWSub_EN =
WILL_FIRE_RL_tlp_dmaPullResponseHeader ||
WILL_FIRE_RL_tlp_dmaPullResponseBody ;
// register tlp_dmaReqTag
assign tlp_dmaReqTag_D_IN = tlp_dmaTag ;
assign tlp_dmaReqTag_EN = tlp_complTimerRunning_D_IN ;
// register tlp_dmaStartMark
assign tlp_dmaStartMark_D_IN = tlp_dmaStartMark_1_whas ;
assign tlp_dmaStartMark_EN = 1'd1 ;
// register tlp_dmaTag
assign tlp_dmaTag_D_IN = tlp_dmaTag + 5'd1 ;
assign tlp_dmaTag_EN = tlp_complTimerRunning_D_IN ;
// register tlp_doXmtMetaBody
assign tlp_doXmtMetaBody_D_IN = !WILL_FIRE_RL_tlp_dmaXmtMetaBody ;
assign tlp_doXmtMetaBody_EN =
WILL_FIRE_RL_tlp_dmaXmtMetaBody ||
WILL_FIRE_RL_tlp_dmaXmtMetaHead ;
// register tlp_doorSeqDwell
assign tlp_doorSeqDwell_D_IN =
(tlp_doorSeqDwell != 4'd0) ?
MUX_tlp_doorSeqDwell_write_1__VAL_1 :
4'd8 ;
assign tlp_doorSeqDwell_EN =
tlp_doorSeqDwell != 4'd0 || WILL_FIRE_RL_tlp_dmaXmtDoorbell ;
// register tlp_fabFlowAddr
assign tlp_fabFlowAddr_D_IN = bml_fabFlowAddr ;
assign tlp_fabFlowAddr_EN = 1'd1 ;
// register tlp_fabFlowAddrMS
assign tlp_fabFlowAddrMS_D_IN = bml_fabFlowBaseMS ;
assign tlp_fabFlowAddrMS_EN = 1'd1 ;
// register tlp_fabMesgAccu
always@(MUX_tlp_fabMesgAccu_write_1__SEL_1 or
tlp_fabMesgAddr or
WILL_FIRE_RL_tlp_dmaPushResponseHeader or
MUX_tlp_fabMesgAccu_write_1__VAL_2 or
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg or
MUX_tlp_fabMesgAccu_write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_tlp_fabMesgAccu_write_1__SEL_1:
tlp_fabMesgAccu_D_IN = tlp_fabMesgAddr;
WILL_FIRE_RL_tlp_dmaPushResponseHeader:
tlp_fabMesgAccu_D_IN = MUX_tlp_fabMesgAccu_write_1__VAL_2;
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg:
tlp_fabMesgAccu_D_IN = MUX_tlp_fabMesgAccu_write_1__VAL_3;
default: tlp_fabMesgAccu_D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign tlp_fabMesgAccu_EN =
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ||
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaPushResponseHeader ||
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ;
// register tlp_fabMesgAddr
assign tlp_fabMesgAddr_D_IN = bml_fabMesgAddr ;
assign tlp_fabMesgAddr_EN = 1'd1 ;
// register tlp_fabMesgAddrMS
assign tlp_fabMesgAddrMS_D_IN = bml_fabMesgBaseMS ;
assign tlp_fabMesgAddrMS_EN = 1'd1 ;
// register tlp_fabMeta
always@(WILL_FIRE_RL_tlp_dmaResponseNearMetaBody or
MUX_tlp_fabMeta_write_1__VAL_1 or
MUX_tlp_fabMeta_write_1__SEL_2 or
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta or
MUX_tlp_fabMeta_write_1__VAL_3)
case (1'b1)
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody:
tlp_fabMeta_D_IN = MUX_tlp_fabMeta_write_1__VAL_1;
MUX_tlp_fabMeta_write_1__SEL_2:
tlp_fabMeta_D_IN = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta:
tlp_fabMeta_D_IN = MUX_tlp_fabMeta_write_1__VAL_3;
default: tlp_fabMeta_D_IN =
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign tlp_fabMeta_EN =
WILL_FIRE_RL_tlp_dmaTailEventSender &&
(tlp_fabFlowAddrMS == 32'd0 || tlp_sentTail4DWHeader) ||
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ;
// register tlp_fabMetaAddr
assign tlp_fabMetaAddr_D_IN = bml_fabMetaAddr ;
assign tlp_fabMetaAddr_EN = 1'd1 ;
// register tlp_fabMetaAddrMS
assign tlp_fabMetaAddrMS_D_IN = bml_fabMetaBaseMS ;
assign tlp_fabMetaAddrMS_EN = 1'd1 ;
// register tlp_farBufReady
assign tlp_farBufReady_D_IN = tlp_farBufReady_1_whas ;
assign tlp_farBufReady_EN = 1'd1 ;
// register tlp_flowDiagCount
assign tlp_flowDiagCount_D_IN = tlp_flowDiagCount + 32'd1 ;
assign tlp_flowDiagCount_EN = WILL_FIRE_RL_tlp_dmaXmtDoorbell ;
// register tlp_gotResponseHeader
always@(WILL_FIRE_RL_tlp_dmaPullResponseBody or
tlp_dmaPullRemainDWSub_387_ULE_4___d1388 or
WILL_FIRE_RL_tlp_dmaPullResponseHeader or
tlp_inF_D_OUT or WILL_FIRE_RL_tlp_dmaPullRequestFarMesg)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_tlp_dmaPullResponseBody:
tlp_gotResponseHeader_D_IN =
!tlp_dmaPullRemainDWSub_387_ULE_4___d1388;
WILL_FIRE_RL_tlp_dmaPullResponseHeader:
tlp_gotResponseHeader_D_IN = tlp_inF_D_OUT[105:96] != 10'd1;
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg:
tlp_gotResponseHeader_D_IN = 1'd0;
default: tlp_gotResponseHeader_D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign tlp_gotResponseHeader_EN =
WILL_FIRE_RL_tlp_dmaPullResponseBody ||
WILL_FIRE_RL_tlp_dmaPullResponseHeader ||
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ;
// register tlp_inIgnorePkt
assign tlp_inIgnorePkt_D_IN =
tlp_inF_D_OUT[110] || tlp_inF_D_OUT[125] ||
tlp_inF_D_OUT[124:120] != 5'b0 ;
assign tlp_inIgnorePkt_EN = WILL_FIRE_RL_tlp_tlpRcv && tlp_inF_D_OUT[152] ;
// register tlp_lastMetaV_0
assign tlp_lastMetaV_0_D_IN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaHead ?
x__h42208 :
x__h58352 ;
assign tlp_lastMetaV_0_EN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaHead ||
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ;
// register tlp_lastMetaV_1
assign tlp_lastMetaV_1_D_IN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ?
opcode__h44022 :
opcode__h60417 ;
assign tlp_lastMetaV_1_EN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ;
// register tlp_lastMetaV_2
assign tlp_lastMetaV_2_D_IN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ?
nowMS__h45280 :
nowMS__h61665 ;
assign tlp_lastMetaV_2_EN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ;
// register tlp_lastMetaV_3
assign tlp_lastMetaV_3_D_IN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ?
nowLS__h46239 :
nowLS__h62622 ;
assign tlp_lastMetaV_3_EN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ;
// register tlp_lastRuleFired
always@(WILL_FIRE_RL_tlp_dmaPullRequestFarMesg or
WILL_FIRE_RL_tlp_dmaRequestFarMeta or
WILL_FIRE_RL_tlp_dmaTailEventSender or
MUX_tlp_lastRuleFired_write_1__VAL_3 or
WILL_FIRE_RL_tlp_dmaPullResponseBody or
WILL_FIRE_RL_tlp_dmaPullResponseHeader or
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta or
WILL_FIRE_RL_tlp_dmaPullTailEvent or
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta)
case (1'b1)
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg: tlp_lastRuleFired_D_IN = 4'd4;
WILL_FIRE_RL_tlp_dmaRequestFarMeta: tlp_lastRuleFired_D_IN = 4'd1;
WILL_FIRE_RL_tlp_dmaTailEventSender:
tlp_lastRuleFired_D_IN = MUX_tlp_lastRuleFired_write_1__VAL_3;
WILL_FIRE_RL_tlp_dmaPullResponseBody: tlp_lastRuleFired_D_IN = 4'd6;
WILL_FIRE_RL_tlp_dmaPullResponseHeader: tlp_lastRuleFired_D_IN = 4'd5;
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta: tlp_lastRuleFired_D_IN = 4'd3;
WILL_FIRE_RL_tlp_dmaPullTailEvent: tlp_lastRuleFired_D_IN = 4'd7;
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta: tlp_lastRuleFired_D_IN = 4'd2;
default: tlp_lastRuleFired_D_IN = 4'b1010 /* unspecified value */ ;
endcase
assign tlp_lastRuleFired_EN =
WILL_FIRE_RL_tlp_dmaTailEventSender ||
WILL_FIRE_RL_tlp_dmaRequestFarMeta ||
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ||
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ||
WILL_FIRE_RL_tlp_dmaPullResponseHeader ||
WILL_FIRE_RL_tlp_dmaPullResponseBody ||
WILL_FIRE_RL_tlp_dmaPullTailEvent ;
// register tlp_maxPayloadSize
assign tlp_maxPayloadSize_D_IN = 13'h0 ;
assign tlp_maxPayloadSize_EN = 1'b0 ;
// register tlp_maxReadReqSize
assign tlp_maxReadReqSize_D_IN = 13'h0 ;
assign tlp_maxReadReqSize_EN = 1'b0 ;
// register tlp_mesgComplReceived
always@(WILL_FIRE_RL_tlp_dmaPullResponseHeader or
MUX_tlp_mesgComplReceived_write_1__VAL_1 or
WILL_FIRE_RL_tlp_dmaPullResponseBody or
MUX_tlp_mesgComplReceived_write_1__VAL_2 or
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_tlp_dmaPullResponseHeader:
tlp_mesgComplReceived_D_IN =
MUX_tlp_mesgComplReceived_write_1__VAL_1;
WILL_FIRE_RL_tlp_dmaPullResponseBody:
tlp_mesgComplReceived_D_IN =
MUX_tlp_mesgComplReceived_write_1__VAL_2;
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta: tlp_mesgComplReceived_D_IN = 17'd0;
default: tlp_mesgComplReceived_D_IN =
17'b01010101010101010 /* unspecified value */ ;
endcase
end
assign tlp_mesgComplReceived_EN =
WILL_FIRE_RL_tlp_dmaPullResponseHeader ||
WILL_FIRE_RL_tlp_dmaPullResponseBody ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ;
// register tlp_mesgLengthRemainPull
always@(WILL_FIRE_RL_tlp_dmaRespHeadFarMeta or
MUX_tlp_mesgLengthRemainPull_write_1__VAL_1 or
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta or
MUX_tlp_mesgLengthRemainPull_write_1__VAL_2 or
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg or
MUX_tlp_mesgLengthRemainPull_write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta:
tlp_mesgLengthRemainPull_D_IN =
MUX_tlp_mesgLengthRemainPull_write_1__VAL_1;
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta:
tlp_mesgLengthRemainPull_D_IN =
MUX_tlp_mesgLengthRemainPull_write_1__VAL_2;
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg:
tlp_mesgLengthRemainPull_D_IN =
MUX_tlp_mesgLengthRemainPull_write_1__VAL_3;
default: tlp_mesgLengthRemainPull_D_IN =
17'b01010101010101010 /* unspecified value */ ;
endcase
end
assign tlp_mesgLengthRemainPull_EN =
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ||
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ;
// register tlp_mesgLengthRemainPush
always@(WILL_FIRE_RL_tlp_dmaResponseNearMetaBody or
MUX_tlp_mesgLengthRemainPush_write_1__VAL_1 or
WILL_FIRE_RL_tlp_dmaResponseNearMetaHead or
MUX_tlp_mesgLengthRemainPush_write_1__VAL_2 or
WILL_FIRE_RL_tlp_dmaPushRequestMesg or
MUX_tlp_mesgLengthRemainPush_write_1__VAL_3)
case (1'b1)
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody:
tlp_mesgLengthRemainPush_D_IN =
MUX_tlp_mesgLengthRemainPush_write_1__VAL_1;
WILL_FIRE_RL_tlp_dmaResponseNearMetaHead:
tlp_mesgLengthRemainPush_D_IN =
MUX_tlp_mesgLengthRemainPush_write_1__VAL_2;
WILL_FIRE_RL_tlp_dmaPushRequestMesg:
tlp_mesgLengthRemainPush_D_IN =
MUX_tlp_mesgLengthRemainPush_write_1__VAL_3;
default: tlp_mesgLengthRemainPush_D_IN =
17'b01010101010101010 /* unspecified value */ ;
endcase
assign tlp_mesgLengthRemainPush_EN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaHead ||
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaPushRequestMesg ;
// register tlp_nearBufReady
assign tlp_nearBufReady_D_IN = tlp_nearBufReady_1_whas ;
assign tlp_nearBufReady_EN = 1'd1 ;
// register tlp_outDwRemain
always@(WILL_FIRE_RL_tlp_dmaPushResponseHeader or
MUX_tlp_outDwRemain_write_1__VAL_1 or
MUX_tlp_tlpXmtBusy_write_1__PSEL_2 or
MUX_tlp_outDwRemain_write_1__VAL_2 or
WILL_FIRE_RL_tlp_dataXmt_Header or
MUX_tlp_outDwRemain_write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_tlp_dmaPushResponseHeader:
tlp_outDwRemain_D_IN = MUX_tlp_outDwRemain_write_1__VAL_1;
MUX_tlp_tlpXmtBusy_write_1__PSEL_2:
tlp_outDwRemain_D_IN = MUX_tlp_outDwRemain_write_1__VAL_2;
WILL_FIRE_RL_tlp_dataXmt_Header:
tlp_outDwRemain_D_IN = MUX_tlp_outDwRemain_write_1__VAL_3;
default: tlp_outDwRemain_D_IN = 10'b1010101010 /* unspecified value */ ;
endcase
end
assign tlp_outDwRemain_EN =
WILL_FIRE_RL_tlp_dmaPushResponseHeader ||
WILL_FIRE_RL_tlp_dataXmt_Body ||
WILL_FIRE_RL_tlp_dmaPushResponseBody ||
WILL_FIRE_RL_tlp_dataXmt_Header ;
// register tlp_postSeqDwell
assign tlp_postSeqDwell_D_IN =
MUX_tlp_fabMeta_write_1__SEL_2 ?
MUX_tlp_postSeqDwell_write_1__VAL_1 :
MUX_tlp_postSeqDwell_write_1__VAL_2 ;
assign tlp_postSeqDwell_EN =
WILL_FIRE_RL_tlp_dmaTailEventSender &&
(tlp_fabFlowAddrMS == 32'd0 || tlp_sentTail4DWHeader) ||
tlp_postSeqDwell != 4'd0 ;
// register tlp_pullTagMatch
assign tlp_pullTagMatch_D_IN =
tlp_pullTagMatch_1_whas && tlp_pullTagMatch_1_wget ;
assign tlp_pullTagMatch_EN = 1'd1 ;
// register tlp_remDone
assign tlp_remDone_D_IN = tlp_remDone_1_whas ;
assign tlp_remDone_EN = 1'd1 ;
// register tlp_remMesgAccu
always@(MUX_tlp_fabMesgAccu_write_1__SEL_1 or
tlp_remMesgAddr or
WILL_FIRE_RL_tlp_dmaPushRequestMesg or
MUX_tlp_remMesgAccu_write_1__VAL_2 or
WILL_FIRE_RL_tlp_dmaPullResponseHeader or
MUX_tlp_remMesgAccu_write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_tlp_fabMesgAccu_write_1__SEL_1:
tlp_remMesgAccu_D_IN = tlp_remMesgAddr;
WILL_FIRE_RL_tlp_dmaPushRequestMesg:
tlp_remMesgAccu_D_IN = MUX_tlp_remMesgAccu_write_1__VAL_2;
WILL_FIRE_RL_tlp_dmaPullResponseHeader:
tlp_remMesgAccu_D_IN = MUX_tlp_remMesgAccu_write_1__VAL_3;
default: tlp_remMesgAccu_D_IN =
16'b1010101010101010 /* unspecified value */ ;
endcase
end
assign tlp_remMesgAccu_EN =
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ||
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaPushRequestMesg ||
WILL_FIRE_RL_tlp_dmaPullResponseHeader ;
// register tlp_remMesgAddr
assign tlp_remMesgAddr_D_IN = bml_remMesgAddr ;
assign tlp_remMesgAddr_EN = 1'd1 ;
// register tlp_remMetaAddr
assign tlp_remMetaAddr_D_IN = bml_remMetaAddr ;
assign tlp_remMetaAddr_EN = 1'd1 ;
// register tlp_remStart
assign tlp_remStart_D_IN = tlp_remStart_1_whas ;
assign tlp_remStart_EN = 1'd1 ;
// register tlp_reqMesgInFlight
always@(WILL_FIRE_RL_tlp_dmaPullResponseHeader or
tlp_dmaPullRemainDWLen or
WILL_FIRE_RL_tlp_dmaPullResponseBody or
MUX_tlp_reqMesgInFlight_write_1__VAL_2 or
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_tlp_dmaPullResponseHeader:
tlp_reqMesgInFlight_D_IN = tlp_dmaPullRemainDWLen != 10'd1;
WILL_FIRE_RL_tlp_dmaPullResponseBody:
tlp_reqMesgInFlight_D_IN = MUX_tlp_reqMesgInFlight_write_1__VAL_2;
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg: tlp_reqMesgInFlight_D_IN = 1'd1;
default: tlp_reqMesgInFlight_D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign tlp_reqMesgInFlight_EN =
WILL_FIRE_RL_tlp_dmaPullResponseHeader ||
WILL_FIRE_RL_tlp_dmaPullResponseBody ||
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ;
// register tlp_reqMetaBodyInFlight
assign tlp_reqMetaBodyInFlight_D_IN = !WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ;
assign tlp_reqMetaBodyInFlight_EN =
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ||
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ;
// register tlp_reqMetaInFlight
always@(WILL_FIRE_RL_tlp_dmaRequestFarMeta or
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody or
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta or
WILL_FIRE_RL_tlp_dmaRequestNearMeta)
case (1'b1)
WILL_FIRE_RL_tlp_dmaRequestFarMeta: tlp_reqMetaInFlight_D_IN = 1'd1;
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta:
tlp_reqMetaInFlight_D_IN = 1'd0;
WILL_FIRE_RL_tlp_dmaRequestNearMeta: tlp_reqMetaInFlight_D_IN = 1'd1;
default: tlp_reqMetaInFlight_D_IN = 1'b0 /* unspecified value */ ;
endcase
assign tlp_reqMetaInFlight_EN =
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ||
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaRequestFarMeta ||
WILL_FIRE_RL_tlp_dmaRequestNearMeta ;
// register tlp_sentTail4DWHeader
assign tlp_sentTail4DWHeader_D_IN = !tlp_sentTail4DWHeader ;
assign tlp_sentTail4DWHeader_EN = MUX_tlp_tlpXmtBusy_write_1__SEL_3 ;
// register tlp_srcMesgAccu
assign tlp_srcMesgAccu_D_IN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ?
tlp_fabMesgAddr :
MUX_tlp_srcMesgAccu_write_1__VAL_2 ;
assign tlp_srcMesgAccu_EN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaPushRequestMesg ;
// register tlp_tlpBRAM_debugBdata
assign tlp_tlpBRAM_debugBdata_D_IN =
{ bram_3_serverAdapterA_outData_outData_wget[7:0],
bram_3_serverAdapterA_outData_outData_wget[15:8],
bram_3_serverAdapterA_outData_outData_wget[23:16],
bram_3_serverAdapterA_outData_outData_wget[31:24],
bram_2_serverAdapterA_outData_outData_wget[7:0],
bram_2_serverAdapterA_outData_outData_wget[15:8],
bram_2_serverAdapterA_outData_outData_wget[23:16],
bram_2_serverAdapterA_outData_outData_wget[31:24],
bram_1_serverAdapterA_outData_outData_wget[7:0],
bram_1_serverAdapterA_outData_outData_wget[15:8],
bram_1_serverAdapterA_outData_outData_wget[23:16],
bram_1_serverAdapterA_outData_outData_wget[31:24],
bram_0_serverAdapterA_outData_outData_wget[7:0],
bram_0_serverAdapterA_outData_outData_wget[15:8],
bram_0_serverAdapterA_outData_outData_wget[23:16],
bram_0_serverAdapterA_outData_outData_wget[31:24] } ;
assign tlp_tlpBRAM_debugBdata_EN = WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ;
// register tlp_tlpBRAM_rdRespDwRemain
assign tlp_tlpBRAM_rdRespDwRemain_D_IN =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp ?
MUX_tlp_tlpBRAM_rdRespDwRemain_write_1__VAL_1 :
MUX_tlp_tlpBRAM_rdRespDwRemain_write_1__VAL_2 ;
assign tlp_tlpBRAM_rdRespDwRemain_EN =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ;
// register tlp_tlpBRAM_readHeaderSent
assign tlp_tlpBRAM_readHeaderSent_D_IN =
MUX_tlp_tlpBRAM_readHeaderSent_write_1__SEL_1 ;
assign tlp_tlpBRAM_readHeaderSent_EN =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp &&
(tlp_tlpBRAM_readReq_D_OUT[28:19] != 10'd1 ||
tlp_tlpBRAM_readReq_D_OUT[60]) ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp &&
tlp_tlpBRAM_rdRespDwRemain_16_ULE_4___d918 ;
// register tlp_tlpBRAM_readNxtDWAddr
assign tlp_tlpBRAM_readNxtDWAddr_D_IN =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq ?
MUX_tlp_tlpBRAM_readNxtDWAddr_write_1__VAL_1 :
MUX_tlp_tlpBRAM_readNxtDWAddr_write_1__VAL_2 ;
assign tlp_tlpBRAM_readNxtDWAddr_EN =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
// register tlp_tlpBRAM_readRemainDWLen
assign tlp_tlpBRAM_readRemainDWLen_D_IN =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq ?
MUX_tlp_tlpBRAM_readRemainDWLen_write_1__VAL_1 :
MUX_tlp_tlpBRAM_readRemainDWLen_write_1__VAL_2 ;
assign tlp_tlpBRAM_readRemainDWLen_EN =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
// register tlp_tlpBRAM_readStarted
assign tlp_tlpBRAM_readStarted_D_IN =
MUX_tlp_tlpBRAM_readStarted_write_1__SEL_1 ;
assign tlp_tlpBRAM_readStarted_EN =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
(tlp_tlpBRAM_mReqF_D_OUT[28:19] != 10'd1 ||
tlp_tlpBRAM_mReqF_D_OUT[60]) ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq &&
tlp_tlpBRAM_readRemainDWLen_74_ULE_4___d775 ;
// register tlp_tlpBRAM_writeDWAddr
assign tlp_tlpBRAM_writeDWAddr_D_IN =
WILL_FIRE_RL_tlp_tlpBRAM_writeReq ?
MUX_tlp_tlpBRAM_writeDWAddr_write_1__VAL_1 :
MUX_tlp_tlpBRAM_writeDWAddr_write_1__VAL_2 ;
assign tlp_tlpBRAM_writeDWAddr_EN =
WILL_FIRE_RL_tlp_tlpBRAM_writeReq ||
WILL_FIRE_RL_tlp_tlpBRAM_writeData ;
// register tlp_tlpBRAM_writeLastBE
assign tlp_tlpBRAM_writeLastBE_D_IN = tlp_tlpBRAM_mReqF_D_OUT[35:32] ;
assign tlp_tlpBRAM_writeLastBE_EN = WILL_FIRE_RL_tlp_tlpBRAM_writeReq ;
// register tlp_tlpBRAM_writeRemainDWLen
assign tlp_tlpBRAM_writeRemainDWLen_D_IN =
WILL_FIRE_RL_tlp_tlpBRAM_writeReq ?
MUX_tlp_tlpBRAM_writeRemainDWLen_write_1__VAL_1 :
MUX_tlp_tlpBRAM_writeRemainDWLen_write_1__VAL_2 ;
assign tlp_tlpBRAM_writeRemainDWLen_EN =
WILL_FIRE_RL_tlp_tlpBRAM_writeReq ||
WILL_FIRE_RL_tlp_tlpBRAM_writeData ;
// register tlp_tlpMetaSent
assign tlp_tlpMetaSent_D_IN = WILL_FIRE_RL_tlp_dmaXmtMetaBody ;
assign tlp_tlpMetaSent_EN =
WILL_FIRE_RL_tlp_dmaXmtTailEvent ||
WILL_FIRE_RL_tlp_dmaXmtMetaBody ;
// register tlp_tlpRcvBusy
always@(WILL_FIRE_RL_tlp_dmaPullResponseBody or
tlp_dmaPullRemainDWSub_387_ULE_4___d1388 or
WILL_FIRE_RL_tlp_dmaPullResponseHeader or
tlp_inF_D_OUT or WILL_FIRE_RL_tlp_tlpRcv)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_tlp_dmaPullResponseBody:
tlp_tlpRcvBusy_D_IN = !tlp_dmaPullRemainDWSub_387_ULE_4___d1388;
WILL_FIRE_RL_tlp_dmaPullResponseHeader:
tlp_tlpRcvBusy_D_IN = tlp_inF_D_OUT[105:96] != 10'd1;
WILL_FIRE_RL_tlp_tlpRcv: tlp_tlpRcvBusy_D_IN = !tlp_inF_D_OUT[151];
default: tlp_tlpRcvBusy_D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign tlp_tlpRcvBusy_EN =
WILL_FIRE_RL_tlp_dmaPullResponseBody ||
WILL_FIRE_RL_tlp_dmaPullResponseHeader ||
WILL_FIRE_RL_tlp_tlpRcv ;
// register tlp_tlpXmtBusy
always@(MUX_tlp_tlpXmtBusy_write_1__SEL_1 or
MUX_tlp_tlpXmtBusy_write_1__VAL_1 or
MUX_tlp_tlpXmtBusy_write_1__SEL_3 or
tlp_sentTail4DWHeader or
MUX_tlp_tlpXmtBusy_write_1__SEL_2 or
WILL_FIRE_RL_tlp_dmaXmtMetaBody or
MUX_tlp_tlpXmtBusy_write_1__SEL_4 or
WILL_FIRE_RL_tlp_dmaXmtMetaHead)
begin
case (1'b1) // synopsys parallel_case
MUX_tlp_tlpXmtBusy_write_1__SEL_1:
tlp_tlpXmtBusy_D_IN = MUX_tlp_tlpXmtBusy_write_1__VAL_1;
MUX_tlp_tlpXmtBusy_write_1__SEL_3:
tlp_tlpXmtBusy_D_IN = !tlp_sentTail4DWHeader;
MUX_tlp_tlpXmtBusy_write_1__SEL_2 || WILL_FIRE_RL_tlp_dmaXmtMetaBody:
tlp_tlpXmtBusy_D_IN = 1'd0;
MUX_tlp_tlpXmtBusy_write_1__SEL_4 || WILL_FIRE_RL_tlp_dmaXmtMetaHead:
tlp_tlpXmtBusy_D_IN = 1'd1;
default: tlp_tlpXmtBusy_D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign tlp_tlpXmtBusy_EN =
WILL_FIRE_RL_tlp_dmaPushResponseHeader && _dfoo5 ||
(WILL_FIRE_RL_tlp_dataXmt_Body ||
WILL_FIRE_RL_tlp_dmaPushResponseBody) &&
tlp_outDwRemain_129_ULE_4___d1130 ||
WILL_FIRE_RL_tlp_dmaTailEventSender &&
tlp_fabFlowAddrMS != 32'd0 ||
WILL_FIRE_RL_tlp_dataXmt_Header &&
!tlp_tlpBRAM_mRespF_first__000_BITS_71_TO_62_10_ETC___d1102 ||
WILL_FIRE_RL_tlp_dmaXmtMetaBody ||
WILL_FIRE_RL_tlp_dmaXmtMetaHead ;
// register tlp_xmtMetaInFlight
assign tlp_xmtMetaInFlight_D_IN = !WILL_FIRE_RL_tlp_dmaXmtTailEvent ;
assign tlp_xmtMetaInFlight_EN =
WILL_FIRE_RL_tlp_dmaXmtTailEvent ||
WILL_FIRE_RL_tlp_dmaXmtMetaHead ;
// register tlp_xmtMetaOK
always@(WILL_FIRE_RL_tlp_dmaResponseNearMetaBody or
tlp_mesgLengthRemainPush or
WILL_FIRE_RL_tlp_dmaXmtMetaHead or
MUX_tlp_xmtMetaOK_write_1__SEL_3 or
MUX_tlp_xmtMetaOK_write_1__SEL_4)
case (1'b1)
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody:
tlp_xmtMetaOK_D_IN = tlp_mesgLengthRemainPush == 17'd0;
WILL_FIRE_RL_tlp_dmaXmtMetaHead: tlp_xmtMetaOK_D_IN = 1'd0;
MUX_tlp_xmtMetaOK_write_1__SEL_3 || MUX_tlp_xmtMetaOK_write_1__SEL_4:
tlp_xmtMetaOK_D_IN = 1'd1;
default: tlp_xmtMetaOK_D_IN = 1'b0 /* unspecified value */ ;
endcase
assign tlp_xmtMetaOK_EN =
WILL_FIRE_RL_tlp_dmaPushResponseHeader &&
tlp_fabMesgAddrMS == 32'd0 &&
tlp_tlpBRAM_mRespF_D_OUT[71:62] == 10'd1 &&
tlp_tlpBRAM_mRespF_D_OUT[42:35] == 8'h01 ||
WILL_FIRE_RL_tlp_dmaPushResponseBody &&
tlp_outDwRemain_129_ULE_4___d1130 &&
tlp_tlpBRAM_mRespF_D_OUT[135:128] == 8'h01 ||
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaXmtMetaHead ;
// register wci_cEdge
assign wci_cEdge_D_IN = wci_reqF_D_OUT[36:34] ;
assign wci_cEdge_EN = WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_cState
assign wci_cState_D_IN = wci_nState ;
assign wci_cState_EN =
WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ;
// register wci_ctlAckReg
assign wci_ctlAckReg_D_IN = wci_ctlAckReg_1_whas ;
assign wci_ctlAckReg_EN = 1'd1 ;
// register wci_ctlOpActive
assign wci_ctlOpActive_D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ;
assign wci_ctlOpActive_EN =
WILL_FIRE_RL_wci_ctl_op_complete ||
WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_illegalEdge
assign wci_illegalEdge_D_IN =
!MUX_wci_illegalEdge_write_1__SEL_1 &&
MUX_wci_illegalEdge_write_1__VAL_2 ;
assign wci_illegalEdge_EN =
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ||
MUX_wci_illegalEdge_write_1__SEL_2 ;
// register wci_isReset_isInReset
assign wci_isReset_isInReset_D_IN = 1'd0 ;
assign wci_isReset_isInReset_EN = wci_isReset_isInReset ;
// register wci_nState
always@(wci_reqF_D_OUT)
begin
case (wci_reqF_D_OUT[36:34])
3'd0: wci_nState_D_IN = 3'd1;
3'd1: wci_nState_D_IN = 3'd2;
3'd2: wci_nState_D_IN = 3'd3;
default: wci_nState_D_IN = 3'd0;
endcase
end
assign wci_nState_EN =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF_D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 ||
wci_reqF_D_OUT[36:34] == 3'd1 &&
(wci_cState == 3'd1 || wci_cState == 3'd3) ||
wci_reqF_D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 ||
wci_reqF_D_OUT[36:34] == 3'd3 &&
(wci_cState == 3'd3 || wci_cState == 3'd2 ||
wci_cState == 3'd1)) ;
// register wci_reqF_countReg
assign wci_reqF_countReg_D_IN =
(wci_wciReq_wget[71:69] != 3'd0) ?
wci_reqF_countReg + 2'd1 :
wci_reqF_countReg - 2'd1 ;
assign wci_reqF_countReg_EN =
(wci_wciReq_wget[71:69] != 3'd0) != wci_reqF_r_deq_whas ;
// register wci_respF_cntr_r
assign wci_respF_cntr_r_D_IN =
WILL_FIRE_RL_wci_respF_decCtr ?
wci_respF_cntr_r_90_MINUS_1___d499 :
MUX_wci_respF_cntr_r_write_1__VAL_2 ;
assign wci_respF_cntr_r_EN =
WILL_FIRE_RL_wci_respF_decCtr || WILL_FIRE_RL_wci_respF_incCtr ;
// register wci_respF_q_0
always@(MUX_wci_respF_q_0_write_1__SEL_1 or
MUX_wci_respF_q_0_write_1__VAL_1 or
MUX_wci_respF_q_0_write_1__SEL_2 or
MUX_wci_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_respF_q_0_write_1__SEL_1:
wci_respF_q_0_D_IN = MUX_wci_respF_q_0_write_1__VAL_1;
MUX_wci_respF_q_0_write_1__SEL_2:
wci_respF_q_0_D_IN = MUX_wci_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0_D_IN = wci_respF_q_1;
default: wci_respF_q_0_D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_respF_q_0_EN =
WILL_FIRE_RL_wci_respF_both && _dfoo3 ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_cntr_r == 2'd0 ||
WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_respF_q_1
always@(MUX_wci_respF_q_1_write_1__SEL_1 or
MUX_wci_respF_q_1_write_1__VAL_1 or
MUX_wci_respF_q_1_write_1__SEL_2 or
MUX_wci_respF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_respF_q_1_write_1__SEL_1:
wci_respF_q_1_D_IN = MUX_wci_respF_q_1_write_1__VAL_1;
MUX_wci_respF_q_1_write_1__SEL_2:
wci_respF_q_1_D_IN = MUX_wci_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1_D_IN = 34'h0AAAAAAAA;
default: wci_respF_q_1_D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_respF_q_1_EN =
WILL_FIRE_RL_wci_respF_both && _dfoo1 ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_cntr_r == 2'd1 ||
WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_sFlagReg
assign wci_sFlagReg_D_IN = 1'b0 ;
assign wci_sFlagReg_EN = 1'd1 ;
// register wci_sThreadBusy_d
assign wci_sThreadBusy_d_D_IN = 1'b0 ;
assign wci_sThreadBusy_d_EN = 1'd1 ;
// register wmi_addr
assign wmi_addr_D_IN =
MUX_wmi_doneWithMesg_write_1__PSEL_1 ?
MUX_wmi_addr_write_1__VAL_1 :
wmi_wmi_reqF_D_OUT[25:12] ;
assign wmi_addr_EN =
WILL_FIRE_RL_wmi_doReadReq || WILL_FIRE_RL_wmi_doWriteReq ||
WILL_FIRE_RL_wmi_getRequest ;
// register wmi_bufDwell
assign wmi_bufDwell_D_IN =
(MUX_wmi_bufDwell_write_1__SEL_1 ||
WILL_FIRE_RL_wmi_doWriteFinalize) ?
2'd3 :
MUX_wmi_bufDwell_write_1__VAL_3 ;
assign wmi_bufDwell_EN =
WILL_FIRE_RL_wmi_doReadReq && wmi_bytesRemainReq == 14'd16 &&
wmi_doneWithMesg ||
wmi_bufDwell != 2'd0 ||
WILL_FIRE_RL_wmi_doWriteFinalize ;
// register wmi_bytesRemainReq
assign wmi_bytesRemainReq_D_IN =
MUX_wmi_doneWithMesg_write_1__PSEL_1 ?
MUX_wmi_bytesRemainReq_write_1__VAL_1 :
MUX_wmi_bytesRemainReq_write_1__VAL_2 ;
assign wmi_bytesRemainReq_EN =
WILL_FIRE_RL_wmi_doReadReq || WILL_FIRE_RL_wmi_doWriteReq ||
WILL_FIRE_RL_wmi_getRequest ;
// register wmi_bytesRemainResp
assign wmi_bytesRemainResp_D_IN =
MUX_wmi_bytesRemainResp_write_1__SEL_1 ?
MUX_wmi_bytesRemainReq_write_1__VAL_2 :
MUX_wmi_bytesRemainResp_write_1__VAL_2 ;
assign wmi_bytesRemainResp_EN =
WILL_FIRE_RL_wmi_getRequest &&
wmi_wmi_reqF_D_OUT[31:29] == 3'd2 ||
WILL_FIRE_RL_wmi_doReadResp ;
// register wmi_doneWithMesg
assign wmi_doneWithMesg_D_IN =
!MUX_wmi_doneWithMesg_write_1__SEL_1 && wmi_wmi_reqF_D_OUT[27] ;
assign wmi_doneWithMesg_EN =
(WILL_FIRE_RL_wmi_doReadReq || WILL_FIRE_RL_wmi_doWriteReq) &&
wmi_bytesRemainReq == 14'd16 &&
wmi_doneWithMesg ||
WILL_FIRE_RL_wmi_getRequest ;
// register wmi_lastMesg
assign wmi_lastMesg_D_IN = wmi_thisMesg ;
assign wmi_lastMesg_EN = WILL_FIRE_RL_wmi_doWriteFinalize ;
// register wmi_lclMesgAddr
assign wmi_lclMesgAddr_D_IN = bml_lclMesgAddr[14:0] ;
assign wmi_lclMesgAddr_EN = 1'd1 ;
// register wmi_lclMetaAddr
assign wmi_lclMetaAddr_D_IN = bml_lclMetaAddr[14:0] ;
assign wmi_lclMetaAddr_EN = 1'd1 ;
// register wmi_mesgBufReady
assign wmi_mesgBufReady_D_IN = wmi_mesgBufReady_1_whas ;
assign wmi_mesgBufReady_EN = 1'd1 ;
// register wmi_mesgBusy
assign wmi_mesgBusy_D_IN = wmi_bufDwell != 2'd1 ;
assign wmi_mesgBusy_EN =
wmi_bufDwell == 2'd1 || WILL_FIRE_RL_wmi_getRequest ;
// register wmi_mesgCount
assign wmi_mesgCount_D_IN =
MUX_wmi_bufDwell_write_1__SEL_1 ?
MUX_wmi_mesgCount_write_1__VAL_1 :
MUX_wmi_mesgCount_write_1__VAL_1 ;
assign wmi_mesgCount_EN = wmi_mesgDone_1_whas ;
// register wmi_mesgDone
assign wmi_mesgDone_D_IN = wmi_mesgDone_1_whas ;
assign wmi_mesgDone_EN = 1'd1 ;
// register wmi_mesgMeta
assign wmi_mesgMeta_D_IN =
MUX_wmi_bufDwell_write_1__SEL_1 ?
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
MUX_wmi_mesgMeta_write_1__VAL_2 ;
assign wmi_mesgMeta_EN =
WILL_FIRE_RL_wmi_doReadReq && wmi_bytesRemainReq == 14'd16 &&
wmi_doneWithMesg ||
WILL_FIRE_RL_wmi_respMetadata ;
// register wmi_mesgStart
assign wmi_mesgStart_D_IN = wmi_mesgStart_1_whas ;
assign wmi_mesgStart_EN = 1'd1 ;
// register wmi_metaBusy
assign wmi_metaBusy_D_IN = !WILL_FIRE_RL_wmi_respMetadata ;
assign wmi_metaBusy_EN =
WILL_FIRE_RL_wmi_respMetadata || WILL_FIRE_RL_wmi_reqMetadata ;
// register wmi_p4B
assign wmi_p4B_D_IN =
MUX_wmi_bytesRemainResp_write_1__SEL_1 ?
wmi_wmi_reqF_D_OUT[15:14] :
wmi_p4B ;
assign wmi_p4B_EN =
WILL_FIRE_RL_wmi_getRequest &&
wmi_wmi_reqF_D_OUT[31:29] == 3'd2 ||
WILL_FIRE_RL_wmi_doReadResp ;
// register wmi_rdActive
assign wmi_rdActive_D_IN =
!MUX_wmi_rdActive_write_1__SEL_1 &&
wmi_wmi_reqF_D_OUT[31:29] == 3'd2 ;
assign wmi_rdActive_EN =
WILL_FIRE_RL_wmi_doReadReq && wmi_bytesRemainReq == 14'd16 ||
WILL_FIRE_RL_wmi_getRequest ;
// register wmi_reqCount
assign wmi_reqCount_D_IN = wmi_reqCount + 16'd1 ;
assign wmi_reqCount_EN = WILL_FIRE_RL_wmi_getRequest ;
// register wmi_thisMesg
assign wmi_thisMesg_D_IN =
{ wmi_mesgCount[7:0],
wmi_wmi_mFlagF_D_OUT[31:24],
wmi_wmi_mFlagF_D_OUT[15:0] } ;
assign wmi_thisMesg_EN = WILL_FIRE_RL_wmi_doWriteFinalize ;
// register wmi_wmi_blockReq
assign wmi_wmi_blockReq_D_IN =
!MUX_wmi_bufDwell_write_1__SEL_1 &&
!WILL_FIRE_RL_wmi_doWriteFinalize ;
assign wmi_wmi_blockReq_EN =
WILL_FIRE_RL_wmi_getRequest && wmi_wmi_reqF_D_OUT[28] &&
wmi_wmi_reqF_D_OUT[27] ||
WILL_FIRE_RL_wmi_doReadReq && wmi_bytesRemainReq == 14'd16 &&
wmi_doneWithMesg ||
WILL_FIRE_RL_wmi_doWriteFinalize ;
// register wmi_wmi_dhF_countReg
assign wmi_wmi_dhF_countReg_D_IN =
MUX_wmi_wmi_dhF_levelsValid_write_1__SEL_2 ?
wmi_wmi_dhF_countReg + 2'd1 :
wmi_wmi_dhF_countReg - 2'd1 ;
assign wmi_wmi_dhF_countReg_EN =
MUX_wmi_wmi_dhF_levelsValid_write_1__SEL_2 !=
WILL_FIRE_RL_wmi_doWriteReq ;
// register wmi_wmi_dhF_levelsValid
assign wmi_wmi_dhF_levelsValid_D_IN = WILL_FIRE_RL_wmi_wmi_dhF_reset ;
assign wmi_wmi_dhF_levelsValid_EN =
wmi_wmi_dhF_FULL_N && wmi_wmi_operateD && wmi_wmi_peerIsReady &&
wmi_wmi_wmiDh_wget[145] ||
WILL_FIRE_RL_wmi_doWriteReq ||
WILL_FIRE_RL_wmi_wmi_dhF_reset ;
// register wmi_wmi_errorSticky
assign wmi_wmi_errorSticky_D_IN = 1'b0 ;
assign wmi_wmi_errorSticky_EN = 1'b0 ;
// register wmi_wmi_isReset_isInReset
assign wmi_wmi_isReset_isInReset_D_IN = 1'd0 ;
assign wmi_wmi_isReset_isInReset_EN = wmi_wmi_isReset_isInReset ;
// register wmi_wmi_mFlagF_countReg
assign wmi_wmi_mFlagF_countReg_D_IN =
MUX_wmi_wmi_mFlagF_levelsValid_write_1__SEL_2 ?
wmi_wmi_mFlagF_countReg + 2'd1 :
wmi_wmi_mFlagF_countReg - 2'd1 ;
assign wmi_wmi_mFlagF_countReg_EN =
MUX_wmi_wmi_mFlagF_levelsValid_write_1__SEL_2 !=
WILL_FIRE_RL_wmi_doWriteFinalize ;
// register wmi_wmi_mFlagF_levelsValid
assign wmi_wmi_mFlagF_levelsValid_D_IN = WILL_FIRE_RL_wmi_wmi_mFlagF_reset ;
assign wmi_wmi_mFlagF_levelsValid_EN =
wmi_wmi_mFlagF_FULL_N && wmi_wmi_operateD &&
wmi_wmi_peerIsReady &&
wmi_wmi_wmiReq_wget[31:29] != 3'd0 &&
wmi_wmi_wmiReq_wget[27] ||
WILL_FIRE_RL_wmi_doWriteFinalize ||
WILL_FIRE_RL_wmi_wmi_mFlagF_reset ;
// register wmi_wmi_operateD
assign wmi_wmi_operateD_D_IN = wci_cState == 3'd2 ;
assign wmi_wmi_operateD_EN = 1'd1 ;
// register wmi_wmi_peerIsReady
assign wmi_wmi_peerIsReady_D_IN = wmiS0_MReset_n ;
assign wmi_wmi_peerIsReady_EN = 1'd1 ;
// register wmi_wmi_reqF_countReg
assign wmi_wmi_reqF_countReg_D_IN =
MUX_wmi_wmi_reqF_levelsValid_write_1__SEL_2 ?
wmi_wmi_reqF_countReg + 2'd1 :
wmi_wmi_reqF_countReg - 2'd1 ;
assign wmi_wmi_reqF_countReg_EN =
MUX_wmi_wmi_reqF_levelsValid_write_1__SEL_2 !=
WILL_FIRE_RL_wmi_getRequest ;
// register wmi_wmi_reqF_levelsValid
assign wmi_wmi_reqF_levelsValid_D_IN = WILL_FIRE_RL_wmi_wmi_reqF_reset ;
assign wmi_wmi_reqF_levelsValid_EN =
wmi_wmi_reqF_FULL_N && wmi_wmi_operateD && wmi_wmi_peerIsReady &&
wmi_wmi_wmiReq_wget[31:29] != 3'd0 ||
WILL_FIRE_RL_wmi_getRequest ||
WILL_FIRE_RL_wmi_wmi_reqF_reset ;
// register wmi_wmi_respF_cntr_r
assign wmi_wmi_respF_cntr_r_D_IN =
WILL_FIRE_RL_wmi_wmi_respF_decCtr ?
wmi_wmi_respF_cntr_r_582_MINUS_1___d1590 :
MUX_wmi_wmi_respF_cntr_r_write_1__VAL_2 ;
assign wmi_wmi_respF_cntr_r_EN =
WILL_FIRE_RL_wmi_wmi_respF_decCtr ||
WILL_FIRE_RL_wmi_wmi_respF_incCtr ;
// register wmi_wmi_respF_q_0
always@(MUX_wmi_wmi_respF_q_0_write_1__SEL_1 or
MUX_wmi_wmi_respF_q_0_write_1__VAL_1 or
MUX_wmi_wmi_respF_q_0_write_1__SEL_2 or
MUX_wmi_wmi_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wmi_wmi_respF_decCtr or wmi_wmi_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wmi_wmi_respF_q_0_write_1__SEL_1:
wmi_wmi_respF_q_0_D_IN = MUX_wmi_wmi_respF_q_0_write_1__VAL_1;
MUX_wmi_wmi_respF_q_0_write_1__SEL_2:
wmi_wmi_respF_q_0_D_IN = MUX_wmi_wmi_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wmi_wmi_respF_decCtr:
wmi_wmi_respF_q_0_D_IN = wmi_wmi_respF_q_1;
default: wmi_wmi_respF_q_0_D_IN =
130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmi_wmi_respF_q_0_EN =
WILL_FIRE_RL_wmi_wmi_respF_both && _dfoo9 ||
WILL_FIRE_RL_wmi_wmi_respF_incCtr &&
wmi_wmi_respF_cntr_r == 2'd0 ||
WILL_FIRE_RL_wmi_wmi_respF_decCtr ;
// register wmi_wmi_respF_q_1
always@(MUX_wmi_wmi_respF_q_1_write_1__SEL_1 or
MUX_wmi_wmi_respF_q_1_write_1__VAL_1 or
MUX_wmi_wmi_respF_q_1_write_1__SEL_2 or
MUX_wmi_wmi_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wmi_wmi_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wmi_wmi_respF_q_1_write_1__SEL_1:
wmi_wmi_respF_q_1_D_IN = MUX_wmi_wmi_respF_q_1_write_1__VAL_1;
MUX_wmi_wmi_respF_q_1_write_1__SEL_2:
wmi_wmi_respF_q_1_D_IN = MUX_wmi_wmi_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wmi_wmi_respF_decCtr: wmi_wmi_respF_q_1_D_IN = 130'd0;
default: wmi_wmi_respF_q_1_D_IN =
130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmi_wmi_respF_q_1_EN =
WILL_FIRE_RL_wmi_wmi_respF_both && _dfoo7 ||
WILL_FIRE_RL_wmi_wmi_respF_incCtr &&
wmi_wmi_respF_cntr_r == 2'd1 ||
WILL_FIRE_RL_wmi_wmi_respF_decCtr ;
// register wmi_wmi_sFlagReg
assign wmi_wmi_sFlagReg_D_IN =
{ bram_1_serverAdapterB_outData_outData_wget[7:0],
bram_0_serverAdapterB_outData_outData_wget[23:0] } ;
assign wmi_wmi_sFlagReg_EN = WILL_FIRE_RL_wmi_respMetadata ;
// register wmi_wmi_statusR
assign wmi_wmi_statusR_D_IN = 8'h0 ;
assign wmi_wmi_statusR_EN = 1'b0 ;
// register wmi_wmi_trafficSticky
assign wmi_wmi_trafficSticky_D_IN = 1'b0 ;
assign wmi_wmi_trafficSticky_EN = 1'b0 ;
// register wmi_wrActive
assign wmi_wrActive_D_IN =
!MUX_wmi_wrActive_write_1__SEL_1 &&
wmi_wmi_reqF_D_OUT[31:29] == 3'd1 ;
assign wmi_wrActive_EN =
WILL_FIRE_RL_wmi_doWriteReq && wmi_bytesRemainReq == 14'd16 ||
WILL_FIRE_RL_wmi_getRequest ;
// register wmi_wrFinalize
assign wmi_wrFinalize_D_IN = MUX_wmi_wrFinalize_write_1__SEL_1 ;
assign wmi_wrFinalize_EN =
WILL_FIRE_RL_wmi_doWriteReq && wmi_bytesRemainReq == 14'd16 &&
wmi_doneWithMesg ||
WILL_FIRE_RL_wmi_doWriteFinalize ;
// register wmi_wrtCount
assign wmi_wrtCount_D_IN = wmi_wrtCount + 16'd1 ;
assign wmi_wrtCount_EN = WILL_FIRE_RL_wmi_doWriteReq ;
// register wti_isReset_isInReset
assign wti_isReset_isInReset_D_IN = 1'd0 ;
assign wti_isReset_isInReset_EN = wti_isReset_isInReset ;
// register wti_nowReq
assign wti_nowReq_D_IN = wti_s_req ;
assign wti_nowReq_EN = 1'd1 ;
// register wti_operateD
assign wti_operateD_D_IN = 1'b1 ;
assign wti_operateD_EN = 1'd1 ;
// submodule bram_0_memory
always@(MUX_bram_0_memory_a_put_1__SEL_1 or
MUX_bram_0_memory_a_put_2__VAL_1 or
MUX_bram_0_memory_a_put_1__SEL_2 or
tlp_tlpBRAM_mReqF_D_OUT or
MUX_bram_0_memory_a_put_1__SEL_3 or
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq or
MUX_bram_0_memory_a_put_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_bram_0_memory_a_put_1__SEL_1:
bram_0_memory_ADDRA = MUX_bram_0_memory_a_put_2__VAL_1;
MUX_bram_0_memory_a_put_1__SEL_2:
bram_0_memory_ADDRA = tlp_tlpBRAM_mReqF_D_OUT[62:52];
MUX_bram_0_memory_a_put_1__SEL_3:
bram_0_memory_ADDRA = tlp_tlpBRAM_mReqF_D_OUT[41:31];
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq:
bram_0_memory_ADDRA = MUX_bram_0_memory_a_put_2__VAL_4;
default: bram_0_memory_ADDRA = 11'b01010101010 /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_wmi_reqMetadata or
WILL_FIRE_RL_wmi_doWriteFinalize or
wmi_lclMetaAddr or
WILL_FIRE_RL_wmi_doReadReq or
MUX_bram_0_memory_b_put_2__VAL_2 or WILL_FIRE_RL_wmi_doWriteReq)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize:
bram_0_memory_ADDRB = wmi_lclMetaAddr[14:4];
WILL_FIRE_RL_wmi_doReadReq:
bram_0_memory_ADDRB = MUX_bram_0_memory_b_put_2__VAL_2;
WILL_FIRE_RL_wmi_doWriteReq:
bram_0_memory_ADDRB = MUX_bram_0_memory_b_put_2__VAL_2;
default: bram_0_memory_ADDRB = 11'b01010101010 /* unspecified value */ ;
endcase
end
always@(MUX_bram_0_memory_a_put_1__SEL_1 or
MUX_bram_0_memory_a_put_3__VAL_1 or
MUX_bram_0_memory_a_put_1__SEL_2 or
MUX_bram_0_memory_a_put_3__VAL_2 or
MUX_bram_0_memory_a_put_1__SEL_3 or
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq)
begin
case (1'b1) // synopsys parallel_case
MUX_bram_0_memory_a_put_1__SEL_1:
bram_0_memory_DIA = MUX_bram_0_memory_a_put_3__VAL_1;
MUX_bram_0_memory_a_put_1__SEL_2:
bram_0_memory_DIA = MUX_bram_0_memory_a_put_3__VAL_2;
MUX_bram_0_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq:
bram_0_memory_DIA = 32'd0;
default: bram_0_memory_DIA = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_wmi_doWriteReq or
wmi_wmi_dhF_D_OUT or
WILL_FIRE_RL_wmi_doWriteFinalize or
x3__h81813 or
WILL_FIRE_RL_wmi_reqMetadata or WILL_FIRE_RL_wmi_doReadReq)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_doWriteReq:
bram_0_memory_DIB = wmi_wmi_dhF_D_OUT[47:16];
WILL_FIRE_RL_wmi_doWriteFinalize: bram_0_memory_DIB = x3__h81813;
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq:
bram_0_memory_DIB = 32'd0;
default: bram_0_memory_DIB = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign bram_0_memory_WEA =
!MUX_bram_0_memory_a_put_1__SEL_3 &&
!WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_0_memory_WEB =
!WILL_FIRE_RL_wmi_reqMetadata && !WILL_FIRE_RL_wmi_doReadReq ;
assign bram_0_memory_ENA =
WILL_FIRE_RL_tlp_tlpBRAM_writeData &&
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 ||
WILL_FIRE_RL_tlp_tlpBRAM_writeReq &&
tlp_tlpBRAM_mReqF_D_OUT[51:50] == 2'd0 &&
!tlp_tlpBRAM_mReqF_D_OUT[63] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
tlp_tlpBRAM_mReqF_D_OUT[30:29] == 2'd0 &&
!tlp_tlpBRAM_mReqF_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_0_memory_ENB =
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ||
WILL_FIRE_RL_wmi_doWriteFinalize ||
WILL_FIRE_RL_wmi_doWriteReq ;
// submodule bram_0_serverAdapterA_outDataCore
assign bram_0_serverAdapterA_outDataCore_D_IN = bram_0_memory_DOA ;
assign bram_0_serverAdapterA_outDataCore_ENQ =
WILL_FIRE_RL_bram_0_serverAdapterA_outData_enqAndDeq ||
bram_0_serverAdapterA_outDataCore_FULL_N &&
!bram_0_serverAdapterA_outData_deqCalled_whas &&
bram_0_serverAdapterA_outData_enqData_whas ;
assign bram_0_serverAdapterA_outDataCore_DEQ =
WILL_FIRE_RL_bram_0_serverAdapterA_outData_enqAndDeq ||
bram_0_serverAdapterA_outDataCore_EMPTY_N &&
bram_0_serverAdapterA_outData_deqCalled_whas &&
!bram_0_serverAdapterA_outData_enqData_whas ;
assign bram_0_serverAdapterA_outDataCore_CLR = 1'b0 ;
// submodule bram_0_serverAdapterB_outDataCore
assign bram_0_serverAdapterB_outDataCore_D_IN = bram_0_memory_DOB ;
assign bram_0_serverAdapterB_outDataCore_ENQ =
WILL_FIRE_RL_bram_0_serverAdapterB_outData_enqAndDeq ||
bram_0_serverAdapterB_outDataCore_FULL_N &&
!bram_0_serverAdapterB_outData_deqCalled_whas &&
bram_0_serverAdapterB_outData_enqData_whas ;
assign bram_0_serverAdapterB_outDataCore_DEQ =
WILL_FIRE_RL_bram_0_serverAdapterB_outData_enqAndDeq ||
bram_0_serverAdapterB_outDataCore_EMPTY_N &&
bram_0_serverAdapterB_outData_deqCalled_whas &&
!bram_0_serverAdapterB_outData_enqData_whas ;
assign bram_0_serverAdapterB_outDataCore_CLR = 1'b0 ;
// submodule bram_1_memory
always@(MUX_bram_1_memory_a_put_1__SEL_1 or
MUX_bram_1_memory_a_put_2__VAL_1 or
MUX_bram_1_memory_a_put_1__SEL_2 or
tlp_tlpBRAM_mReqF_D_OUT or
MUX_bram_1_memory_a_put_1__SEL_3 or
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq or
MUX_bram_1_memory_a_put_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_bram_1_memory_a_put_1__SEL_1:
bram_1_memory_ADDRA = MUX_bram_1_memory_a_put_2__VAL_1;
MUX_bram_1_memory_a_put_1__SEL_2:
bram_1_memory_ADDRA = tlp_tlpBRAM_mReqF_D_OUT[62:52];
MUX_bram_1_memory_a_put_1__SEL_3:
bram_1_memory_ADDRA = tlp_tlpBRAM_mReqF_D_OUT[41:31];
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq:
bram_1_memory_ADDRA = MUX_bram_1_memory_a_put_2__VAL_4;
default: bram_1_memory_ADDRA = 11'b01010101010 /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_wmi_reqMetadata or
WILL_FIRE_RL_wmi_doWriteFinalize or
wmi_lclMetaAddr or
WILL_FIRE_RL_wmi_doReadReq or
MUX_bram_0_memory_b_put_2__VAL_2 or WILL_FIRE_RL_wmi_doWriteReq)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize:
bram_1_memory_ADDRB = wmi_lclMetaAddr[14:4];
WILL_FIRE_RL_wmi_doReadReq:
bram_1_memory_ADDRB = MUX_bram_0_memory_b_put_2__VAL_2;
WILL_FIRE_RL_wmi_doWriteReq:
bram_1_memory_ADDRB = MUX_bram_0_memory_b_put_2__VAL_2;
default: bram_1_memory_ADDRB = 11'b01010101010 /* unspecified value */ ;
endcase
end
always@(MUX_bram_1_memory_a_put_1__SEL_1 or
MUX_bram_1_memory_a_put_3__VAL_1 or
MUX_bram_1_memory_a_put_1__SEL_2 or
MUX_bram_0_memory_a_put_3__VAL_2 or
MUX_bram_1_memory_a_put_1__SEL_3 or
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq)
begin
case (1'b1) // synopsys parallel_case
MUX_bram_1_memory_a_put_1__SEL_1:
bram_1_memory_DIA = MUX_bram_1_memory_a_put_3__VAL_1;
MUX_bram_1_memory_a_put_1__SEL_2:
bram_1_memory_DIA = MUX_bram_0_memory_a_put_3__VAL_2;
MUX_bram_1_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq:
bram_1_memory_DIA = 32'd0;
default: bram_1_memory_DIA = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_wmi_doWriteReq or
wmi_wmi_dhF_D_OUT or
WILL_FIRE_RL_wmi_doWriteFinalize or
mesgMeta_opcode__h81853 or
WILL_FIRE_RL_wmi_reqMetadata or WILL_FIRE_RL_wmi_doReadReq)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_doWriteReq:
bram_1_memory_DIB = wmi_wmi_dhF_D_OUT[79:48];
WILL_FIRE_RL_wmi_doWriteFinalize:
bram_1_memory_DIB = mesgMeta_opcode__h81853;
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq:
bram_1_memory_DIB = 32'd0;
default: bram_1_memory_DIB = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign bram_1_memory_WEA =
!MUX_bram_1_memory_a_put_1__SEL_3 &&
!WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_1_memory_WEB = bram_0_memory_WEB ;
assign bram_1_memory_ENA =
WILL_FIRE_RL_tlp_tlpBRAM_writeData &&
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 ||
WILL_FIRE_RL_tlp_tlpBRAM_writeReq &&
tlp_tlpBRAM_mReqF_D_OUT[51:50] == 2'd1 &&
!tlp_tlpBRAM_mReqF_D_OUT[63] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
tlp_tlpBRAM_mReqF_D_OUT[30:29] == 2'd1 &&
!tlp_tlpBRAM_mReqF_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_1_memory_ENB =
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ||
WILL_FIRE_RL_wmi_doWriteFinalize ||
WILL_FIRE_RL_wmi_doWriteReq ;
// submodule bram_1_serverAdapterA_outDataCore
assign bram_1_serverAdapterA_outDataCore_D_IN = bram_1_memory_DOA ;
assign bram_1_serverAdapterA_outDataCore_ENQ =
WILL_FIRE_RL_bram_1_serverAdapterA_outData_enqAndDeq ||
bram_1_serverAdapterA_outDataCore_FULL_N &&
!bram_1_serverAdapterA_outData_deqCalled_whas &&
bram_1_serverAdapterA_outData_enqData_whas ;
assign bram_1_serverAdapterA_outDataCore_DEQ =
WILL_FIRE_RL_bram_1_serverAdapterA_outData_enqAndDeq ||
bram_1_serverAdapterA_outDataCore_EMPTY_N &&
bram_1_serverAdapterA_outData_deqCalled_whas &&
!bram_1_serverAdapterA_outData_enqData_whas ;
assign bram_1_serverAdapterA_outDataCore_CLR = 1'b0 ;
// submodule bram_1_serverAdapterB_outDataCore
assign bram_1_serverAdapterB_outDataCore_D_IN = bram_1_memory_DOB ;
assign bram_1_serverAdapterB_outDataCore_ENQ =
WILL_FIRE_RL_bram_1_serverAdapterB_outData_enqAndDeq ||
bram_1_serverAdapterB_outDataCore_FULL_N &&
!bram_0_serverAdapterB_outData_deqCalled_whas &&
bram_1_serverAdapterB_outData_enqData_whas ;
assign bram_1_serverAdapterB_outDataCore_DEQ =
WILL_FIRE_RL_bram_1_serverAdapterB_outData_enqAndDeq ||
bram_1_serverAdapterB_outDataCore_EMPTY_N &&
bram_0_serverAdapterB_outData_deqCalled_whas &&
!bram_1_serverAdapterB_outData_enqData_whas ;
assign bram_1_serverAdapterB_outDataCore_CLR = 1'b0 ;
// submodule bram_2_memory
always@(MUX_bram_2_memory_a_put_1__SEL_1 or
MUX_bram_2_memory_a_put_2__VAL_1 or
MUX_bram_2_memory_a_put_1__SEL_2 or
tlp_tlpBRAM_mReqF_D_OUT or
MUX_bram_2_memory_a_put_1__SEL_3 or
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq or
MUX_bram_2_memory_a_put_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_bram_2_memory_a_put_1__SEL_1:
bram_2_memory_ADDRA = MUX_bram_2_memory_a_put_2__VAL_1;
MUX_bram_2_memory_a_put_1__SEL_2:
bram_2_memory_ADDRA = tlp_tlpBRAM_mReqF_D_OUT[62:52];
MUX_bram_2_memory_a_put_1__SEL_3:
bram_2_memory_ADDRA = tlp_tlpBRAM_mReqF_D_OUT[41:31];
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq:
bram_2_memory_ADDRA = MUX_bram_2_memory_a_put_2__VAL_4;
default: bram_2_memory_ADDRA = 11'b01010101010 /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_wmi_reqMetadata or
WILL_FIRE_RL_wmi_doWriteFinalize or
wmi_lclMetaAddr or
WILL_FIRE_RL_wmi_doReadReq or
MUX_bram_0_memory_b_put_2__VAL_2 or WILL_FIRE_RL_wmi_doWriteReq)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize:
bram_2_memory_ADDRB = wmi_lclMetaAddr[14:4];
WILL_FIRE_RL_wmi_doReadReq:
bram_2_memory_ADDRB = MUX_bram_0_memory_b_put_2__VAL_2;
WILL_FIRE_RL_wmi_doWriteReq:
bram_2_memory_ADDRB = MUX_bram_0_memory_b_put_2__VAL_2;
default: bram_2_memory_ADDRB = 11'b01010101010 /* unspecified value */ ;
endcase
end
always@(MUX_bram_2_memory_a_put_1__SEL_1 or
MUX_bram_2_memory_a_put_3__VAL_1 or
MUX_bram_2_memory_a_put_1__SEL_2 or
MUX_bram_0_memory_a_put_3__VAL_2 or
MUX_bram_2_memory_a_put_1__SEL_3 or
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq)
begin
case (1'b1) // synopsys parallel_case
MUX_bram_2_memory_a_put_1__SEL_1:
bram_2_memory_DIA = MUX_bram_2_memory_a_put_3__VAL_1;
MUX_bram_2_memory_a_put_1__SEL_2:
bram_2_memory_DIA = MUX_bram_0_memory_a_put_3__VAL_2;
MUX_bram_2_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq:
bram_2_memory_DIA = 32'd0;
default: bram_2_memory_DIA = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_wmi_doWriteFinalize or
wmi_nowW_wget or
WILL_FIRE_RL_wmi_doWriteReq or
wmi_wmi_dhF_D_OUT or
WILL_FIRE_RL_wmi_reqMetadata or WILL_FIRE_RL_wmi_doReadReq)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_doWriteFinalize:
bram_2_memory_DIB = wmi_nowW_wget[63:32];
WILL_FIRE_RL_wmi_doWriteReq:
bram_2_memory_DIB = wmi_wmi_dhF_D_OUT[111:80];
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq:
bram_2_memory_DIB = 32'd0;
default: bram_2_memory_DIB = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign bram_2_memory_WEA =
!MUX_bram_2_memory_a_put_1__SEL_3 &&
!WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_2_memory_WEB = bram_0_memory_WEB ;
assign bram_2_memory_ENA =
WILL_FIRE_RL_tlp_tlpBRAM_writeData &&
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 ||
WILL_FIRE_RL_tlp_tlpBRAM_writeReq &&
tlp_tlpBRAM_mReqF_D_OUT[51:50] == 2'd2 &&
!tlp_tlpBRAM_mReqF_D_OUT[63] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
tlp_tlpBRAM_mReqF_D_OUT[30:29] == 2'd2 &&
!tlp_tlpBRAM_mReqF_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_2_memory_ENB =
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ||
WILL_FIRE_RL_wmi_doWriteFinalize ||
WILL_FIRE_RL_wmi_doWriteReq ;
// submodule bram_2_serverAdapterA_outDataCore
assign bram_2_serverAdapterA_outDataCore_D_IN = bram_2_memory_DOA ;
assign bram_2_serverAdapterA_outDataCore_ENQ =
WILL_FIRE_RL_bram_2_serverAdapterA_outData_enqAndDeq ||
bram_2_serverAdapterA_outDataCore_FULL_N &&
!bram_2_serverAdapterA_outData_deqCalled_whas &&
bram_2_serverAdapterA_outData_enqData_whas ;
assign bram_2_serverAdapterA_outDataCore_DEQ =
WILL_FIRE_RL_bram_2_serverAdapterA_outData_enqAndDeq ||
bram_2_serverAdapterA_outDataCore_EMPTY_N &&
bram_2_serverAdapterA_outData_deqCalled_whas &&
!bram_2_serverAdapterA_outData_enqData_whas ;
assign bram_2_serverAdapterA_outDataCore_CLR = 1'b0 ;
// submodule bram_2_serverAdapterB_outDataCore
assign bram_2_serverAdapterB_outDataCore_D_IN = bram_2_memory_DOB ;
assign bram_2_serverAdapterB_outDataCore_ENQ =
WILL_FIRE_RL_bram_2_serverAdapterB_outData_enqAndDeq ||
bram_2_serverAdapterB_outDataCore_FULL_N &&
!bram_0_serverAdapterB_outData_deqCalled_whas &&
bram_2_serverAdapterB_outData_enqData_whas ;
assign bram_2_serverAdapterB_outDataCore_DEQ =
WILL_FIRE_RL_bram_2_serverAdapterB_outData_enqAndDeq ||
bram_2_serverAdapterB_outDataCore_EMPTY_N &&
bram_0_serverAdapterB_outData_deqCalled_whas &&
!bram_2_serverAdapterB_outData_enqData_whas ;
assign bram_2_serverAdapterB_outDataCore_CLR = 1'b0 ;
// submodule bram_3_memory
always@(MUX_bram_3_memory_a_put_1__SEL_1 or
MUX_bram_3_memory_a_put_2__VAL_1 or
MUX_bram_3_memory_a_put_1__SEL_2 or
tlp_tlpBRAM_mReqF_D_OUT or
MUX_bram_3_memory_a_put_1__SEL_3 or
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq or
MUX_bram_3_memory_a_put_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_bram_3_memory_a_put_1__SEL_1:
bram_3_memory_ADDRA = MUX_bram_3_memory_a_put_2__VAL_1;
MUX_bram_3_memory_a_put_1__SEL_2:
bram_3_memory_ADDRA = tlp_tlpBRAM_mReqF_D_OUT[62:52];
MUX_bram_3_memory_a_put_1__SEL_3:
bram_3_memory_ADDRA = tlp_tlpBRAM_mReqF_D_OUT[41:31];
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq:
bram_3_memory_ADDRA = MUX_bram_3_memory_a_put_2__VAL_4;
default: bram_3_memory_ADDRA = 11'b01010101010 /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_wmi_reqMetadata or
WILL_FIRE_RL_wmi_doWriteFinalize or
wmi_lclMetaAddr or
WILL_FIRE_RL_wmi_doReadReq or
MUX_bram_0_memory_b_put_2__VAL_2 or WILL_FIRE_RL_wmi_doWriteReq)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize:
bram_3_memory_ADDRB = wmi_lclMetaAddr[14:4];
WILL_FIRE_RL_wmi_doReadReq:
bram_3_memory_ADDRB = MUX_bram_0_memory_b_put_2__VAL_2;
WILL_FIRE_RL_wmi_doWriteReq:
bram_3_memory_ADDRB = MUX_bram_0_memory_b_put_2__VAL_2;
default: bram_3_memory_ADDRB = 11'b01010101010 /* unspecified value */ ;
endcase
end
always@(MUX_bram_3_memory_a_put_1__SEL_1 or
MUX_bram_3_memory_a_put_3__VAL_1 or
MUX_bram_3_memory_a_put_1__SEL_2 or
MUX_bram_0_memory_a_put_3__VAL_2 or
MUX_bram_3_memory_a_put_1__SEL_3 or
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq)
begin
case (1'b1) // synopsys parallel_case
MUX_bram_3_memory_a_put_1__SEL_1:
bram_3_memory_DIA = MUX_bram_3_memory_a_put_3__VAL_1;
MUX_bram_3_memory_a_put_1__SEL_2:
bram_3_memory_DIA = MUX_bram_0_memory_a_put_3__VAL_2;
MUX_bram_3_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq:
bram_3_memory_DIA = 32'd0;
default: bram_3_memory_DIA = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_wmi_doWriteFinalize or
wmi_nowW_wget or
WILL_FIRE_RL_wmi_doWriteReq or
wmi_wmi_dhF_D_OUT or
WILL_FIRE_RL_wmi_reqMetadata or WILL_FIRE_RL_wmi_doReadReq)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_doWriteFinalize:
bram_3_memory_DIB = wmi_nowW_wget[31:0];
WILL_FIRE_RL_wmi_doWriteReq:
bram_3_memory_DIB = wmi_wmi_dhF_D_OUT[143:112];
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq:
bram_3_memory_DIB = 32'd0;
default: bram_3_memory_DIB = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign bram_3_memory_WEA =
!MUX_bram_3_memory_a_put_1__SEL_3 &&
!WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_3_memory_WEB = bram_0_memory_WEB ;
assign bram_3_memory_ENA =
WILL_FIRE_RL_tlp_tlpBRAM_writeData &&
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 ||
WILL_FIRE_RL_tlp_tlpBRAM_writeReq &&
tlp_tlpBRAM_mReqF_D_OUT[51:50] == 2'd3 &&
!tlp_tlpBRAM_mReqF_D_OUT[63] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
tlp_tlpBRAM_mReqF_D_OUT[30:29] == 2'd3 &&
!tlp_tlpBRAM_mReqF_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_3_memory_ENB =
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ||
WILL_FIRE_RL_wmi_doWriteFinalize ||
WILL_FIRE_RL_wmi_doWriteReq ;
// submodule bram_3_serverAdapterA_outDataCore
assign bram_3_serverAdapterA_outDataCore_D_IN = bram_3_memory_DOA ;
assign bram_3_serverAdapterA_outDataCore_ENQ =
WILL_FIRE_RL_bram_3_serverAdapterA_outData_enqAndDeq ||
bram_3_serverAdapterA_outDataCore_FULL_N &&
!bram_3_serverAdapterA_outData_deqCalled_whas &&
bram_3_serverAdapterA_outData_enqData_whas ;
assign bram_3_serverAdapterA_outDataCore_DEQ =
WILL_FIRE_RL_bram_3_serverAdapterA_outData_enqAndDeq ||
bram_3_serverAdapterA_outDataCore_EMPTY_N &&
bram_3_serverAdapterA_outData_deqCalled_whas &&
!bram_3_serverAdapterA_outData_enqData_whas ;
assign bram_3_serverAdapterA_outDataCore_CLR = 1'b0 ;
// submodule bram_3_serverAdapterB_outDataCore
assign bram_3_serverAdapterB_outDataCore_D_IN = bram_3_memory_DOB ;
assign bram_3_serverAdapterB_outDataCore_ENQ =
WILL_FIRE_RL_bram_3_serverAdapterB_outData_enqAndDeq ||
bram_3_serverAdapterB_outDataCore_FULL_N &&
!bram_0_serverAdapterB_outData_deqCalled_whas &&
bram_3_serverAdapterB_outData_enqData_whas ;
assign bram_3_serverAdapterB_outDataCore_DEQ =
WILL_FIRE_RL_bram_3_serverAdapterB_outData_enqAndDeq ||
bram_3_serverAdapterB_outDataCore_EMPTY_N &&
bram_0_serverAdapterB_outData_deqCalled_whas &&
!bram_3_serverAdapterB_outData_enqData_whas ;
assign bram_3_serverAdapterB_outDataCore_CLR = 1'b0 ;
// submodule tlp_inF
assign tlp_inF_D_IN = server_request_put ;
assign tlp_inF_DEQ =
WILL_FIRE_RL_tlp_tlpRcv ||
WILL_FIRE_RL_tlp_dmaPullResponseBody ||
WILL_FIRE_RL_tlp_dmaPullResponseHeader ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ||
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ;
assign tlp_inF_ENQ = EN_server_request_put ;
assign tlp_inF_CLR = 1'b0 ;
// submodule tlp_outF
always@(MUX_tlp_tlpXmtBusy_write_1__PSEL_2 or
MUX_tlp_outF_enq_1__VAL_1 or
WILL_FIRE_RL_tlp_dmaPushResponseHeader or
MUX_tlp_outF_enq_1__VAL_2 or
WILL_FIRE_RL_tlp_dmaXmtMetaHead or
MUX_tlp_outF_enq_1__VAL_3 or
WILL_FIRE_RL_tlp_dmaXmtMetaBody or
MUX_tlp_outF_enq_1__VAL_4 or
WILL_FIRE_RL_tlp_dmaRequestFarMeta or
MUX_tlp_outF_enq_1__VAL_5 or
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg or
MUX_tlp_outF_enq_1__VAL_6 or
WILL_FIRE_RL_tlp_dmaTailEventSender or
MUX_tlp_outF_enq_1__VAL_7 or
WILL_FIRE_RL_tlp_dataXmt_Header or MUX_tlp_outF_enq_1__VAL_8)
begin
case (1'b1) // synopsys parallel_case
MUX_tlp_tlpXmtBusy_write_1__PSEL_2:
tlp_outF_D_IN = MUX_tlp_outF_enq_1__VAL_1;
WILL_FIRE_RL_tlp_dmaPushResponseHeader:
tlp_outF_D_IN = MUX_tlp_outF_enq_1__VAL_2;
WILL_FIRE_RL_tlp_dmaXmtMetaHead:
tlp_outF_D_IN = MUX_tlp_outF_enq_1__VAL_3;
WILL_FIRE_RL_tlp_dmaXmtMetaBody:
tlp_outF_D_IN = MUX_tlp_outF_enq_1__VAL_4;
WILL_FIRE_RL_tlp_dmaRequestFarMeta:
tlp_outF_D_IN = MUX_tlp_outF_enq_1__VAL_5;
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg:
tlp_outF_D_IN = MUX_tlp_outF_enq_1__VAL_6;
WILL_FIRE_RL_tlp_dmaTailEventSender:
tlp_outF_D_IN = MUX_tlp_outF_enq_1__VAL_7;
WILL_FIRE_RL_tlp_dataXmt_Header:
tlp_outF_D_IN = MUX_tlp_outF_enq_1__VAL_8;
default: tlp_outF_D_IN =
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign tlp_outF_DEQ = EN_server_response_get ;
assign tlp_outF_ENQ =
WILL_FIRE_RL_tlp_dataXmt_Body ||
WILL_FIRE_RL_tlp_dmaPushResponseBody ||
WILL_FIRE_RL_tlp_dmaPushResponseHeader ||
WILL_FIRE_RL_tlp_dmaXmtMetaHead ||
WILL_FIRE_RL_tlp_dmaXmtMetaBody ||
WILL_FIRE_RL_tlp_dmaRequestFarMeta ||
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ||
WILL_FIRE_RL_tlp_dmaTailEventSender ||
WILL_FIRE_RL_tlp_dataXmt_Header ;
assign tlp_outF_CLR = 1'b0 ;
// submodule tlp_tailEventF
assign tlp_tailEventF_D_IN = !MUX_tlp_tailEventF_enq_1__SEL_1 ;
assign tlp_tailEventF_ENQ =
WILL_FIRE_RL_tlp_dmaXmtDoorbell ||
WILL_FIRE_RL_tlp_dmaXmtTailEvent ||
WILL_FIRE_RL_tlp_dmaPullTailEvent ;
assign tlp_tailEventF_DEQ = MUX_tlp_fabMeta_write_1__SEL_2 ;
assign tlp_tailEventF_CLR = 1'b0 ;
// submodule tlp_tlpBRAM_mReqF
always@(MUX_tlp_tlpBRAM_mReqF_enq_1__SEL_1 or
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_1 or
MUX_tlp_tlpBRAM_mReqF_enq_1__SEL_2 or
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_2 or
WILL_FIRE_RL_tlp_dmaRequestNearMeta or
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_3 or
WILL_FIRE_RL_tlp_dmaPushRequestMesg or
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_4 or
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta or
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_5 or
WILL_FIRE_RL_tlp_dmaPullResponseHeader or
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_tlp_tlpBRAM_mReqF_enq_1__SEL_1:
tlp_tlpBRAM_mReqF_D_IN = MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_1;
MUX_tlp_tlpBRAM_mReqF_enq_1__SEL_2:
tlp_tlpBRAM_mReqF_D_IN = MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_2;
WILL_FIRE_RL_tlp_dmaRequestNearMeta:
tlp_tlpBRAM_mReqF_D_IN = MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_3;
WILL_FIRE_RL_tlp_dmaPushRequestMesg:
tlp_tlpBRAM_mReqF_D_IN = MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_4;
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta:
tlp_tlpBRAM_mReqF_D_IN = MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_5;
WILL_FIRE_RL_tlp_dmaPullResponseHeader:
tlp_tlpBRAM_mReqF_D_IN = MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_6;
default: tlp_tlpBRAM_mReqF_D_IN =
130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign tlp_tlpBRAM_mReqF_ENQ =
WILL_FIRE_RL_tlp_tlpRcv &&
tlp_inF_first__259_BIT_152_462_AND_NOT_tlp_inF_ETC___d1487 ||
WILL_FIRE_RL_tlp_dmaPullResponseBody ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ||
WILL_FIRE_RL_tlp_dmaRequestNearMeta ||
WILL_FIRE_RL_tlp_dmaPushRequestMesg ||
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ||
WILL_FIRE_RL_tlp_dmaPullResponseHeader ;
assign tlp_tlpBRAM_mReqF_DEQ =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
tlp_tlpBRAM_mReqF_D_OUT[28:19] == 10'd1 &&
!tlp_tlpBRAM_mReqF_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq &&
tlp_tlpBRAM_readRemainDWLen_74_ULE_4___d775 ||
WILL_FIRE_RL_tlp_tlpBRAM_writeData ||
WILL_FIRE_RL_tlp_tlpBRAM_writeReq ;
assign tlp_tlpBRAM_mReqF_CLR = 1'b0 ;
// submodule tlp_tlpBRAM_mRespF
assign tlp_tlpBRAM_mRespF_D_IN =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp ?
MUX_tlp_tlpBRAM_mRespF_enq_1__VAL_1 :
MUX_tlp_tlpBRAM_mRespF_enq_1__VAL_2 ;
assign tlp_tlpBRAM_mRespF_ENQ =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ;
assign tlp_tlpBRAM_mRespF_DEQ =
WILL_FIRE_RL_tlp_dataXmt_Body ||
WILL_FIRE_RL_tlp_dataXmt_Header ||
WILL_FIRE_RL_tlp_dmaPushResponseBody ||
WILL_FIRE_RL_tlp_dmaPushResponseHeader ||
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaResponseNearMetaHead ;
assign tlp_tlpBRAM_mRespF_CLR = 1'b0 ;
// submodule tlp_tlpBRAM_readReq
assign tlp_tlpBRAM_readReq_D_IN = tlp_tlpBRAM_mReqF_D_OUT[60:0] ;
assign tlp_tlpBRAM_readReq_ENQ = WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq ;
assign tlp_tlpBRAM_readReq_DEQ =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp &&
tlp_tlpBRAM_readReq_D_OUT[28:19] == 10'd1 &&
!tlp_tlpBRAM_readReq_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp &&
tlp_tlpBRAM_rdRespDwRemain_16_ULE_4___d918 ;
assign tlp_tlpBRAM_readReq_CLR = 1'b0 ;
// submodule wci_reqF
assign wci_reqF_D_IN = wci_wciReq_wget ;
assign wci_reqF_ENQ = wci_wciReq_wget[71:69] != 3'd0 ;
assign wci_reqF_DEQ = wci_reqF_r_deq_whas ;
assign wci_reqF_CLR = 1'b0 ;
// submodule wmi_wmi_dhF
assign wmi_wmi_dhF_D_IN = wmi_wmi_wmiDh_wget ;
assign wmi_wmi_dhF_ENQ = MUX_wmi_wmi_dhF_levelsValid_write_1__SEL_2 ;
assign wmi_wmi_dhF_DEQ = WILL_FIRE_RL_wmi_doWriteReq ;
assign wmi_wmi_dhF_CLR = 1'b0 ;
// submodule wmi_wmi_mFlagF
assign wmi_wmi_mFlagF_D_IN = wmiS0_arg_mFlag ;
assign wmi_wmi_mFlagF_ENQ = MUX_wmi_wmi_mFlagF_levelsValid_write_1__SEL_2 ;
assign wmi_wmi_mFlagF_DEQ = WILL_FIRE_RL_wmi_doWriteFinalize ;
assign wmi_wmi_mFlagF_CLR = 1'b0 ;
// submodule wmi_wmi_reqF
assign wmi_wmi_reqF_D_IN = wmi_wmi_wmiReq_wget ;
assign wmi_wmi_reqF_ENQ = MUX_wmi_wmi_reqF_levelsValid_write_1__SEL_2 ;
assign wmi_wmi_reqF_DEQ = WILL_FIRE_RL_wmi_getRequest ;
assign wmi_wmi_reqF_CLR = 1'b0 ;
// remaining internal signals
assign IF_bml_dpControl_wget__898_BITS_1_TO_0_904_EQ__ETC___d1984 =
CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_bml_ETC__q4 &&
!bml_lclBufStart ||
CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q5 &&
bml_lclBufStart ;
assign IF_bml_dpControl_wget__898_BITS_3_TO_2_899_EQ__ETC___d1995 =
(dpControl[3:2] == 2'd1) ? !bml_remDone : !bml_remStart ;
assign IF_tlp_fabMesgAddrMS_078_EQ_0_079_THEN_0_ELSE__ETC___d1353 =
{ (tlp_fabMesgAddrMS == 32'd0) ? 22'd0 : 22'd524288,
thisRequestLength__h63893[11:2],
pciDevice,
tag__h64168,
lastBE__h64200,
4'd15,
(tlp_fabMesgAddrMS == 32'd0) ?
{ tlp_fabMesgAccu[31:2], 34'd0 } :
{ tlp_fabMesgAddrMS, tlp_fabMesgAccu[31:2], 2'b0 } } ;
assign IF_tlp_fabMetaAddrMS_157_EQ_0_158_THEN_4_ELSE__ETC___d1248 =
{ (tlp_fabMetaAddrMS == 32'd0) ? 32'd4 : 32'd536870916,
pciDevice,
tag__h64168,
8'd255,
(tlp_fabMetaAddrMS == 32'd0) ?
{ tlp_fabMetaAddr[31:2], 34'd0 } :
{ tlp_fabMetaAddrMS, tlp_fabMetaAddr[31:2], 2'b0 } } ;
assign IF_tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_ETC___d929 =
tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_00_ETC___d922[0] ?
{ bram_3_serverAdapterA_outData_outData_wget[7:0],
bram_3_serverAdapterA_outData_outData_wget[15:8],
bram_3_serverAdapterA_outData_outData_wget[23:16],
bram_3_serverAdapterA_outData_outData_wget[31:24],
bram_0_serverAdapterA_outData_outData_wget[7:0],
bram_0_serverAdapterA_outData_outData_wget[15:8],
bram_0_serverAdapterA_outData_outData_wget[23:16],
bram_0_serverAdapterA_outData_outData_wget[31:24],
bram_1_serverAdapterA_outData_outData_wget[7:0],
bram_1_serverAdapterA_outData_outData_wget[15:8],
bram_1_serverAdapterA_outData_outData_wget[23:16],
bram_1_serverAdapterA_outData_outData_wget[31:24],
bram_2_serverAdapterA_outData_outData_wget[7:0],
bram_2_serverAdapterA_outData_outData_wget[15:8],
bram_2_serverAdapterA_outData_outData_wget[23:16],
bram_2_serverAdapterA_outData_outData_wget[31:24] } :
{ bram_2_serverAdapterA_outData_outData_wget[7:0],
bram_2_serverAdapterA_outData_outData_wget[15:8],
bram_2_serverAdapterA_outData_outData_wget[23:16],
bram_2_serverAdapterA_outData_outData_wget[31:24],
bram_3_serverAdapterA_outData_outData_wget[7:0],
bram_3_serverAdapterA_outData_outData_wget[15:8],
bram_3_serverAdapterA_outData_outData_wget[23:16],
bram_3_serverAdapterA_outData_outData_wget[31:24],
bram_0_serverAdapterA_outData_outData_wget[7:0],
bram_0_serverAdapterA_outData_outData_wget[15:8],
bram_0_serverAdapterA_outData_outData_wget[23:16],
bram_0_serverAdapterA_outData_outData_wget[31:24],
bram_1_serverAdapterA_outData_outData_wget[7:0],
bram_1_serverAdapterA_outData_outData_wget[15:8],
bram_1_serverAdapterA_outData_outData_wget[23:16],
bram_1_serverAdapterA_outData_outData_wget[31:24] } ;
assign IF_tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_ETC___d934 =
tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_00_ETC___d922[0] ?
{ bram_1_serverAdapterA_outData_outData_wget[7:0],
bram_1_serverAdapterA_outData_outData_wget[15:8],
bram_1_serverAdapterA_outData_outData_wget[23:16],
bram_1_serverAdapterA_outData_outData_wget[31:24],
bram_2_serverAdapterA_outData_outData_wget[7:0],
bram_2_serverAdapterA_outData_outData_wget[15:8],
bram_2_serverAdapterA_outData_outData_wget[23:16],
bram_2_serverAdapterA_outData_outData_wget[31:24],
bram_3_serverAdapterA_outData_outData_wget[7:0],
bram_3_serverAdapterA_outData_outData_wget[15:8],
bram_3_serverAdapterA_outData_outData_wget[23:16],
bram_3_serverAdapterA_outData_outData_wget[31:24],
bram_0_serverAdapterA_outData_outData_wget[7:0],
bram_0_serverAdapterA_outData_outData_wget[15:8],
bram_0_serverAdapterA_outData_outData_wget[23:16],
bram_0_serverAdapterA_outData_outData_wget[31:24] } :
{ bram_0_serverAdapterA_outData_outData_wget[7:0],
bram_0_serverAdapterA_outData_outData_wget[15:8],
bram_0_serverAdapterA_outData_outData_wget[23:16],
bram_0_serverAdapterA_outData_outData_wget[31:24],
bram_1_serverAdapterA_outData_outData_wget[7:0],
bram_1_serverAdapterA_outData_outData_wget[15:8],
bram_1_serverAdapterA_outData_outData_wget[23:16],
bram_1_serverAdapterA_outData_outData_wget[31:24],
bram_2_serverAdapterA_outData_outData_wget[7:0],
bram_2_serverAdapterA_outData_outData_wget[15:8],
bram_2_serverAdapterA_outData_outData_wget[23:16],
bram_2_serverAdapterA_outData_outData_wget[31:24],
bram_3_serverAdapterA_outData_outData_wget[7:0],
bram_3_serverAdapterA_outData_outData_wget[15:8],
bram_3_serverAdapterA_outData_outData_wget[23:16],
bram_3_serverAdapterA_outData_outData_wget[31:24] } ;
assign NOT_SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_5_ETC___d681 =
(!SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 ||
bram_1_serverAdapterA_cnt_44_SLT_3___d620) &&
(!SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 ||
bram_2_serverAdapterA_cnt_62_SLT_3___d621) &&
(!SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 ||
bram_3_serverAdapterA_cnt_80_SLT_3___d622) ;
assign NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656 =
tlp_tlpBRAM_writeRemainDWLen > 10'd1 ;
assign NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658 =
tlp_tlpBRAM_writeRemainDWLen > 10'd2 ;
assign NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660 =
tlp_tlpBRAM_writeRemainDWLen > 10'd3 ;
assign NOT_wmi_wrActive_717_718_OR_NOT_wmi_rdActive_7_ETC___d1727 =
(!wmi_wrActive || !wmi_rdActive) && !wmi_wrFinalize &&
(wmi_mesgBufReady || wmi_mesgBusy) ;
assign _dfoo1 =
wci_respF_cntr_r != 2'd2 ||
wci_respF_cntr_r_90_MINUS_1___d499 == 2'd1 ;
assign _dfoo3 =
wci_respF_cntr_r != 2'd1 ||
wci_respF_cntr_r_90_MINUS_1___d499 == 2'd0 ;
assign _dfoo5 =
tlp_fabMesgAddrMS != 32'd0 ||
tlp_tlpBRAM_mRespF_D_OUT[71:62] != 10'd1 ||
tlp_tlpBRAM_mRespF_D_OUT[42:35] == 8'h01 ;
assign _dfoo7 =
wmi_wmi_respF_cntr_r != 2'd2 ||
wmi_wmi_respF_cntr_r_582_MINUS_1___d1590 == 2'd1 ;
assign _dfoo9 =
wmi_wmi_respF_cntr_r != 2'd1 ||
wmi_wmi_respF_cntr_r_582_MINUS_1___d1590 == 2'd0 ;
assign ab__h10465 =
(MUX_bram_3_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) ?
2'd0 :
2'd2 ;
assign ab__h11870 =
MUX_bram_0_serverAdapterB_writeWithResp_wset_1__SEL_1 ?
2'd0 :
2'd2 ;
assign ab__h1619 =
(MUX_bram_0_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) ?
2'd0 :
2'd2 ;
assign ab__h3026 =
MUX_bram_0_serverAdapterB_writeWithResp_wset_1__SEL_1 ?
2'd0 :
2'd2 ;
assign ab__h4569 =
(MUX_bram_1_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) ?
2'd0 :
2'd2 ;
assign ab__h5974 =
MUX_bram_0_serverAdapterB_writeWithResp_wset_1__SEL_1 ?
2'd0 :
2'd2 ;
assign ab__h7517 =
(MUX_bram_2_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) ?
2'd0 :
2'd2 ;
assign ab__h8922 =
MUX_bram_0_serverAdapterB_writeWithResp_wset_1__SEL_1 ?
2'd0 :
2'd2 ;
assign bml_crdBuf_value_880_EQ_bml_crdBuf_modulus_bw__ETC___d1882 =
bml_crdBuf_value == bml_crdBuf_modulus ;
assign bml_fabBuf_value_865_EQ_bml_fabBuf_modulus_bw__ETC___d1867 =
bml_fabBuf_value == bml_fabBuf_modulus ;
assign bml_fabFlowAddr_937_PLUS_bml_fabFlowSize_938___d1939 =
bml_fabFlowAddr + bml_fabFlowSize ;
assign bml_lclBufDone_922_AND_IF_bml_dpControl_wget___ETC___d2003 =
bml_lclBufDone &&
CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q6 ||
!bml_lclBufDone &&
CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_IF__ETC__q7 ;
assign bml_lclBuf_value_835_EQ_bml_lclBuf_modulus_bw__ETC___d1837 =
bml_lclBuf_value == bml_lclBuf_modulus ;
assign bml_remBuf_value_850_EQ_bml_remBuf_modulus_bw__ETC___d1852 =
bml_remBuf_value == bml_remBuf_modulus ;
assign bram_0_serverAdapterA_cnt_6_PLUS_IF_bram_0_ser_ETC___d32 =
bram_0_serverAdapterA_cnt +
(bram_0_serverAdapterA_cnt_1_whas ? 3'd1 : 3'd0) +
(bram_0_serverAdapterA_outData_deqCalled_whas ? 3'd7 : 3'd0) ;
assign bram_0_serverAdapterA_cnt_6_SLT_3___d619 =
(bram_0_serverAdapterA_cnt ^ 3'h4) < 3'd7 ;
assign bram_0_serverAdapterA_outDataCore_notEmpty_OR__ETC___d887 =
(bram_0_serverAdapterA_outDataCore_EMPTY_N ||
bram_0_serverAdapterA_outData_enqData_whas) &&
(bram_1_serverAdapterA_outDataCore_EMPTY_N ||
bram_1_serverAdapterA_outData_enqData_whas) &&
bram_2_serverAdapterA_outDataCore_notEmpty__38_ETC___d885 ;
assign bram_0_serverAdapterB_cnt_5_PLUS_IF_bram_0_ser_ETC___d91 =
bram_0_serverAdapterB_cnt +
(bram_0_serverAdapterB_cnt_1_whas ? 3'd1 : 3'd0) +
(bram_0_serverAdapterB_outData_deqCalled_whas ? 3'd7 : 3'd0) ;
assign bram_0_serverAdapterB_cnt_5_SLT_3_666_AND_bram_ETC___d1672 =
bram_0_serverAdapterB_cnt_5_SLT_3___d1666 &&
bram_1_serverAdapterB_cnt_03_SLT_3___d1667 &&
bram_2_serverAdapterB_cnt_21_SLT_3___d1668 &&
bram_3_serverAdapterB_cnt_39_SLT_3___d1669 ;
assign bram_0_serverAdapterB_cnt_5_SLT_3___d1666 =
(bram_0_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;
assign bram_0_serverAdapterB_outData_outData_whas__68_ETC___d1697 =
bram_0_serverAdapterB_outData_outData_whas &&
(bram_1_serverAdapterB_outDataCore_EMPTY_N ||
bram_1_serverAdapterB_outData_enqData_whas) &&
bram_1_serverAdapterB_outData_outData_whas__68_ETC___d1695 ;
assign bram_1_serverAdapterA_cnt_44_PLUS_IF_bram_1_se_ETC___d150 =
bram_1_serverAdapterA_cnt +
(bram_1_serverAdapterA_cnt_1_whas ? 3'd1 : 3'd0) +
(bram_1_serverAdapterA_outData_deqCalled_whas ? 3'd7 : 3'd0) ;
assign bram_1_serverAdapterA_cnt_44_SLT_3___d620 =
(bram_1_serverAdapterA_cnt ^ 3'h4) < 3'd7 ;
assign bram_1_serverAdapterB_cnt_03_PLUS_IF_bram_1_se_ETC___d209 =
bram_1_serverAdapterB_cnt +
(bram_1_serverAdapterB_cnt_1_whas ? 3'd1 : 3'd0) +
(bram_0_serverAdapterB_outData_deqCalled_whas ? 3'd7 : 3'd0) ;
assign bram_1_serverAdapterB_cnt_03_SLT_3___d1667 =
(bram_1_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;
assign bram_1_serverAdapterB_outData_outData_whas__68_ETC___d1695 =
bram_1_serverAdapterB_outData_outData_whas &&
(bram_2_serverAdapterB_outDataCore_EMPTY_N ||
bram_2_serverAdapterB_outData_enqData_whas) &&
bram_2_serverAdapterB_outData_outData_whas &&
(bram_3_serverAdapterB_outDataCore_EMPTY_N ||
bram_3_serverAdapterB_outData_enqData_whas) &&
bram_3_serverAdapterB_outData_outData_whas ;
assign bram_2_serverAdapterA_cnt_62_PLUS_IF_bram_2_se_ETC___d268 =
bram_2_serverAdapterA_cnt +
(bram_2_serverAdapterA_cnt_1_whas ? 3'd1 : 3'd0) +
(bram_2_serverAdapterA_outData_deqCalled_whas ? 3'd7 : 3'd0) ;
assign bram_2_serverAdapterA_cnt_62_SLT_3___d621 =
(bram_2_serverAdapterA_cnt ^ 3'h4) < 3'd7 ;
assign bram_2_serverAdapterA_outDataCore_notEmpty__38_ETC___d885 =
(bram_2_serverAdapterA_outDataCore_EMPTY_N ||
bram_2_serverAdapterA_outData_enqData_whas) &&
(bram_3_serverAdapterA_outDataCore_EMPTY_N ||
bram_3_serverAdapterA_outData_enqData_whas) &&
bram_0_serverAdapterA_outData_outData_whas &&
bram_1_serverAdapterA_outData_outData_whas &&
bram_2_serverAdapterA_outData_outData_whas &&
bram_3_serverAdapterA_outData_outData_whas &&
tlp_tlpBRAM_mRespF_FULL_N ;
assign bram_2_serverAdapterB_cnt_21_PLUS_IF_bram_2_se_ETC___d327 =
bram_2_serverAdapterB_cnt +
(bram_2_serverAdapterB_cnt_1_whas ? 3'd1 : 3'd0) +
(bram_0_serverAdapterB_outData_deqCalled_whas ? 3'd7 : 3'd0) ;
assign bram_2_serverAdapterB_cnt_21_SLT_3___d1668 =
(bram_2_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;
assign bram_3_serverAdapterA_cnt_80_PLUS_IF_bram_3_se_ETC___d386 =
bram_3_serverAdapterA_cnt +
(bram_3_serverAdapterA_cnt_1_whas ? 3'd1 : 3'd0) +
(bram_3_serverAdapterA_outData_deqCalled_whas ? 3'd7 : 3'd0) ;
assign bram_3_serverAdapterA_cnt_80_SLT_3___d622 =
(bram_3_serverAdapterA_cnt ^ 3'h4) < 3'd7 ;
assign bram_3_serverAdapterB_cnt_39_PLUS_IF_bram_3_se_ETC___d445 =
bram_3_serverAdapterB_cnt +
(bram_3_serverAdapterB_cnt_1_whas ? 3'd1 : 3'd0) +
(bram_0_serverAdapterB_outData_deqCalled_whas ? 3'd7 : 3'd0) ;
assign bram_3_serverAdapterB_cnt_39_SLT_3___d1669 =
(bram_3_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;
assign byteCount__h29653 = x__h29771 - y__h29772 ;
assign hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1233 =
hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 &&
dpControl[1:0] == 2'd1 &&
!tlp_tlpXmtBusy &&
!tlp_reqMetaInFlight &&
!tlp_reqMetaBodyInFlight &&
!tlp_fabMeta[128] ;
assign hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1274 =
hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 &&
dpControl[1:0] == 2'd1 &&
tlp_reqMetaInFlight &&
!tlp_tlpRcvBusy &&
tagm__h64387 == tlp_inF_D_OUT[47:40] &&
tlp_inF_first__259_BITS_63_TO_56_262_EQ_pciDev_ETC___d1272 ;
assign hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1326 =
hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 &&
dpControl[1:0] == 2'd1 &&
tlp_fabMeta[128] &&
tlp_fabMeta[127:96] != 32'd0 &&
!tlp_tlpXmtBusy &&
!tlp_reqMesgInFlight &&
tlp_mesgLengthRemainPull != 17'd0 ;
assign hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1365 =
hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 &&
dpControl[1:0] == 2'd1 &&
tlp_fabMeta[128] &&
tlp_reqMesgInFlight &&
!tlp_tlpRcvBusy &&
tlp_pullTagMatch &&
!tlp_gotResponseHeader ;
assign hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1385 =
hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 &&
dpControl[1:0] == 2'd1 &&
tlp_fabMeta[128] &&
tlp_reqMesgInFlight &&
tlp_gotResponseHeader ;
assign hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1410 =
hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 &&
dpControl[1:0] == 2'd1 &&
tlp_fabMeta[128] &&
tlp_dmaDoTailEvent &&
tlp_postSeqDwell == 4'd0 &&
tlp_mesgComplReceived >= tlp_fabMeta[112:96] ;
assign hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1058 =
hasPush && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd1 &&
dpControl[1:0] == 2'd1 &&
tlp_fabMeta[128] &&
tlp_fabMeta[127:96] != 32'd0 &&
!tlp_tlpRcvBusy &&
tlp_mesgLengthRemainPush != 17'd0 ;
assign hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1098 =
hasPush && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd1 &&
dpControl[1:0] == 2'd1 &&
!tlp_tlpBRAM_mRespF_D_OUT[138] &&
tlp_tlpBRAM_mRespF_D_OUT[89:88] == 2'd2 &&
!tlp_tlpXmtBusy &&
tlp_postSeqDwell == 4'd0 ;
assign hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1155 =
hasPush && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd1 &&
dpControl[1:0] == 2'd1 &&
tlp_fabMeta[128] &&
!tlp_tlpXmtBusy &&
!tlp_xmtMetaInFlight &&
tlp_xmtMetaOK &&
tlp_postSeqDwell == 4'd0 ;
assign hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d985 =
hasPush && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd1 &&
dpControl[1:0] == 2'd1 &&
!tlp_tlpRcvBusy &&
!tlp_reqMetaInFlight &&
!tlp_fabMeta[128] &&
tlp_nearBufReady ;
assign idx__h21626 = 2'd0 - tlp_tlpBRAM_writeDWAddr[1:0] ;
assign idx__h23676 = 2'd1 - tlp_tlpBRAM_writeDWAddr[1:0] ;
assign idx__h24781 = 2'd2 - tlp_tlpBRAM_writeDWAddr[1:0] ;
assign idx__h25886 = 2'd3 - tlp_tlpBRAM_writeDWAddr[1:0] ;
assign idx__h27879 = 2'd0 - tlp_tlpBRAM_readNxtDWAddr[1:0] ;
assign idx__h28282 = 2'd1 - tlp_tlpBRAM_readNxtDWAddr[1:0] ;
assign idx__h28586 = 2'd2 - tlp_tlpBRAM_readNxtDWAddr[1:0] ;
assign idx__h28890 = 2'd3 - tlp_tlpBRAM_readNxtDWAddr[1:0] ;
assign lastBE__h47950 =
tlp_tlpBRAM_mRespF_first__000_BITS_71_TO_62_10_ETC___d1102 ?
4'd0 :
4'd15 ;
assign lastBE__h64200 =
(thisRequestLength__h63893[11:2] == 10'd1) ? 4'd0 : 4'd15 ;
assign lowAddr__h29652 =
{ tlp_tlpBRAM_readReq_D_OUT[33:29], lowAddr10__h29651 } ;
assign mesgMeta_opcode__h81853 =
{ 24'h800000, wmi_wmi_mFlagF_D_OUT[31:24] } ;
assign nowLS__h46239 =
{ tlp_tlpBRAM_mRespF_D_OUT[39:32],
tlp_tlpBRAM_mRespF_D_OUT[47:40],
tlp_tlpBRAM_mRespF_D_OUT[55:48],
tlp_tlpBRAM_mRespF_D_OUT[63:56] } ;
assign nowLS__h62622 =
{ tlp_inF_D_OUT[39:32],
tlp_inF_D_OUT[47:40],
tlp_inF_D_OUT[55:48],
tlp_inF_D_OUT[63:56] } ;
assign nowMS__h45280 =
{ tlp_tlpBRAM_mRespF_D_OUT[71:64],
tlp_tlpBRAM_mRespF_D_OUT[79:72],
tlp_tlpBRAM_mRespF_D_OUT[87:80],
tlp_tlpBRAM_mRespF_D_OUT[95:88] } ;
assign nowMS__h61665 =
{ tlp_inF_D_OUT[71:64],
tlp_inF_D_OUT[79:72],
tlp_inF_D_OUT[87:80],
tlp_inF_D_OUT[95:88] } ;
assign opcode__h44022 =
{ tlp_tlpBRAM_mRespF_D_OUT[103:96],
tlp_tlpBRAM_mRespF_D_OUT[111:104],
tlp_tlpBRAM_mRespF_D_OUT[119:112],
tlp_tlpBRAM_mRespF_D_OUT[127:120] } ;
assign opcode__h60417 =
{ tlp_inF_D_OUT[103:96],
tlp_inF_D_OUT[111:104],
tlp_inF_D_OUT[119:112],
tlp_inF_D_OUT[127:120] } ;
assign pkt__h71785 =
{ 9'd148,
tlp_tlpBRAM_mRespF_D_OUT[34:32],
10'd0,
tlp_tlpBRAM_mRespF_D_OUT[71:62],
pciDevice,
4'd0,
tlp_tlpBRAM_mRespF_D_OUT[54:43],
tlp_tlpBRAM_mRespF_D_OUT[87:72],
tlp_tlpBRAM_mRespF_D_OUT[42:35],
1'b0,
tlp_tlpBRAM_mRespF_D_OUT[61:55],
tlp_tlpBRAM_mRespF_D_OUT[31:0] } ;
assign rdat__h92026 = { 16'd0, bml_lclNumBufs } ;
assign rdat__h92034 = { 16'd0, bml_fabNumBufs } ;
assign rdat__h92042 = { 16'd0, bml_mesgBase } ;
assign rdat__h92050 = { 16'd0, bml_metaBase } ;
assign rdat__h92058 = { 16'd0, bml_mesgSize } ;
assign rdat__h92066 = { 16'd0, bml_metaSize } ;
assign rdat__h92074 = { 16'd0, bml_lclBufsCF } ;
assign rdat__h92095 =
hasDebugLogic ? { bml_lclBufsAR, bml_fabBufsAvail } : 32'd0 ;
assign rdat__h92102 =
hasDebugLogic ? { bml_remBuf_value, bml_lclBuf_value } : 32'd0 ;
assign rdat__h92115 =
hasDebugLogic ? { bml_lclStarts, bml_lclDones } : 32'd0 ;
assign rdat__h92122 =
hasDebugLogic ? { bml_remStarts, bml_remDones } : 32'd0 ;
assign rdat__h92129 = hasDebugLogic ? wmi_thisMesg : 32'd0 ;
assign rdat__h92401 = hasDebugLogic ? wmi_lastMesg : 32'd0 ;
assign rdat__h92451 =
hasDebugLogic ? { wmi_reqCount, wmi_wrtCount } : 32'd0 ;
assign rdat__h92551 = hasDebugLogic ? 32'hDADEBABE : 32'd0 ;
assign rdat__h92609 = { 24'd0, dpControl } ;
assign rdat__h92631 = hasDebugLogic ? tlp_flowDiagCount : 32'd0 ;
assign rdat__h92641 =
hasDebugLogic ?
{ 4'h0,
tlp_complTimerCount,
12'h0,
CASE_tlp_lastRuleFired_1_tlp_lastRuleFired_2_t_ETC__q1 } :
32'd0 ;
assign rdat__h92763 = hasDebugLogic ? tlp_lastMetaV_0 : 32'd0 ;
assign rdat__h92887 = hasDebugLogic ? tlp_lastMetaV_1 : 32'd0 ;
assign rdat__h92915 = hasDebugLogic ? tlp_lastMetaV_2 : 32'd0 ;
assign rdat__h92943 = hasDebugLogic ? tlp_lastMetaV_3 : 32'd0 ;
assign rdat__h92971 = hasDebugLogic ? 32'hC0DE0111 : 32'd0 ;
assign rdat__h93001 = hasDebugLogic ? dmaStartTime[31:0] : 32'd0 ;
assign rdat__h93035 = hasDebugLogic ? dmaStartTime[63:32] : 32'd0 ;
assign rdat__h93068 = hasDebugLogic ? dmaDoneTime[31:0] : 32'd0 ;
assign rdat__h93102 = hasDebugLogic ? dmaDoneTime[63:32] : 32'd0 ;
assign rdata__h35173 =
tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_00_ETC___d922[1] ?
IF_tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_ETC___d929 :
IF_tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_ETC___d934 ;
assign rdata__h83703 =
{ bram_3_serverAdapterB_outData_outData_wget,
bram_2_serverAdapterB_outData_outData_wget,
bram_1_serverAdapterB_outData_outData_wget,
bram_0_serverAdapterB_outData_outData_wget } ;
assign rreq_tag__h47719 =
(y__h47529 == tlp_mesgLengthRemainPush) ? 8'h01 : 8'h0 ;
assign rresp_data__h29698 =
{ SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863[7:0],
SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863[15:8],
SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863[23:16],
SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863[31:24] } ;
assign spanToNextPage__h47503 = 13'd4096 - { 1'd0, tlp_srcMesgAccu[11:0] } ;
assign spanToNextPage__h63892 = 13'd4096 - { 1'd0, tlp_fabMesgAccu[11:0] } ;
assign tag__h64168 = { 3'd0, tlp_dmaTag } ;
assign tagm__h64387 = { 3'd0, tlp_dmaReqTag } ;
assign thisRequestLength__h47504 =
(x__h47542[12:0] <= spanToNextPage__h47503) ?
x__h47542[12:0] :
spanToNextPage__h47503 ;
assign thisRequestLength__h63893 =
(x__h63926[12:0] <= spanToNextPage__h63892) ?
x__h63926[12:0] :
spanToNextPage__h63892 ;
assign tlp_dmaPullRemainDWLen_373_ULE_tlp_dmaPullRema_ETC___d1395 =
tlp_dmaPullRemainDWLen <= tlp_dmaPullRemainDWSub ;
assign tlp_dmaPullRemainDWSub_387_ULE_4___d1388 =
tlp_dmaPullRemainDWSub <= 10'd4 ;
assign tlp_inF_first__259_BITS_63_TO_56_262_EQ_pciDev_ETC___d1272 =
tlp_inF_D_OUT[63:56] == pciDevice[15:8] &&
tlp_inF_D_OUT[55:51] == pciDevice[7:3] &&
tlp_inF_D_OUT[50:48] == pciDevice[2:0] ;
assign tlp_inF_first__259_BIT_152_462_AND_NOT_tlp_inF_ETC___d1487 =
tlp_inF_D_OUT[152] && !tlp_inF_D_OUT[110] &&
!tlp_inF_D_OUT[125] &&
tlp_inF_D_OUT[124:120] == 5'b0 ||
!tlp_inF_D_OUT[152] && !tlp_inIgnorePkt ;
assign tlp_mesgLengthRemainPull_PLUS_3__q14 =
tlp_mesgLengthRemainPull + 17'd3 ;
assign tlp_mesgLengthRemainPush_PLUS_3__q15 =
tlp_mesgLengthRemainPush + 17'd3 ;
assign tlp_outDwRemain_129_ULE_4___d1130 = tlp_outDwRemain <= 10'd4 ;
assign tlp_tlpBRAM_mRespF_first__000_BITS_71_TO_62_10_ETC___d1102 =
tlp_tlpBRAM_mRespF_D_OUT[71:62] <= 10'd1 ;
assign tlp_tlpBRAM_mRespF_i_notFull__97_AND_tlp_tlpBR_ETC___d813 =
tlp_tlpBRAM_mRespF_FULL_N &&
(tlp_tlpBRAM_readReq_D_OUT[60] ||
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d805 &&
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d810) ;
assign tlp_tlpBRAM_rdRespDwRemain_16_ULE_4___d918 =
tlp_tlpBRAM_rdRespDwRemain <= 10'd4 ;
assign tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11 =
tlp_tlpBRAM_readNxtDWAddr + 13'd1 ;
assign tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12 =
tlp_tlpBRAM_readNxtDWAddr + 13'd2 ;
assign tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13 =
tlp_tlpBRAM_readNxtDWAddr + 13'd3 ;
assign tlp_tlpBRAM_readRemainDWLen_74_ULE_4___d775 =
tlp_tlpBRAM_readRemainDWLen <= 10'd4 ;
assign tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_00_ETC___d922 =
tlp_tlpBRAM_readReq_D_OUT[30:29] +
(tlp_tlpBRAM_readReq_D_OUT[60] ? 2'd0 : 2'd1) ;
assign tlp_tlpBRAM_writeDWAddr_PLUS_1__q8 =
tlp_tlpBRAM_writeDWAddr + 13'd1 ;
assign tlp_tlpBRAM_writeDWAddr_PLUS_2__q9 =
tlp_tlpBRAM_writeDWAddr + 13'd2 ;
assign tlp_tlpBRAM_writeDWAddr_PLUS_3__q10 =
tlp_tlpBRAM_writeDWAddr + 13'd3 ;
assign w_be__h48508 =
tlp_outDwRemain_129_ULE_4___d1130 ?
CASE_tlp_outDwRemain_BITS_1_TO_0_0b0_0xFFFF_0b_ETC__q3 :
16'd65535 ;
assign w_data__h47916 =
{ 22'd1048576,
tlp_tlpBRAM_mRespF_D_OUT[71:62],
pciDevice,
8'd0,
lastBE__h47950,
4'd15,
tlp_fabMesgAccu,
tlp_tlpBRAM_mRespF_D_OUT[31:0] } ;
assign w_data__h48052 =
{ 22'd1572864,
tlp_tlpBRAM_mRespF_D_OUT[71:62],
pciDevice,
8'd0,
lastBE__h47950,
4'd15,
tlp_fabMesgAddrMS,
tlp_fabMesgAccu } ;
assign w_data__h52877 =
{ tlp_fabMeta[103:96],
tlp_fabMeta[111:104],
tlp_fabMeta[119:112],
tlp_fabMeta[127:120],
tlp_fabMeta[71:64],
tlp_fabMeta[79:72],
tlp_fabMeta[87:80],
tlp_fabMeta[95:88],
tlp_fabMeta[39:32],
tlp_fabMeta[47:40],
tlp_fabMeta[55:48],
tlp_fabMeta[63:56],
tlp_fabMeta[7:0],
tlp_fabMeta[15:8],
tlp_fabMeta[23:16],
tlp_fabMeta[31:24] } ;
assign w_data__h65836 =
{ 32'd1073741825,
pciDevice,
16'd15,
tlp_fabFlowAddr,
wti_nowReq_BITS_63_TO_0__q2[12:6],
1'd1,
wti_nowReq_BITS_63_TO_0__q2[20:13],
wti_nowReq_BITS_63_TO_0__q2[28:21],
wti_nowReq_BITS_63_TO_0__q2[36:29] } ;
assign w_data__h66940 =
{ 32'd1610612737,
pciDevice,
16'd15,
tlp_fabFlowAddrMS,
tlp_fabFlowAddr } ;
assign w_data__h67186 =
{ wti_nowReq_BITS_63_TO_0__q2[12:6],
1'd1,
wti_nowReq_BITS_63_TO_0__q2[20:13],
wti_nowReq_BITS_63_TO_0__q2[28:21],
wti_nowReq_BITS_63_TO_0__q2[36:29],
96'd0 } ;
assign wci_respF_cntr_r_90_MINUS_1___d499 = wci_respF_cntr_r - 2'd1 ;
assign wmi_wmi_operateD_606_AND_wmi_wmi_peerIsReady_6_ETC___d1777 =
wmi_wmi_operateD && wmi_wmi_peerIsReady &&
bram_0_serverAdapterB_cnt_5_SLT_3___d1666 &&
bram_1_serverAdapterB_cnt_03_SLT_3___d1667 &&
bram_2_serverAdapterB_cnt_21_SLT_3___d1668 &&
bram_3_serverAdapterB_cnt_39_SLT_3___d1669 &&
wmi_wmi_mFlagF_EMPTY_N ;
assign wmi_wmi_operateD_606_AND_wmi_wmi_peerIsReady_6_ETC___d1798 =
wmi_wmi_operateD && wmi_wmi_peerIsReady &&
(bram_0_serverAdapterB_outDataCore_EMPTY_N ||
bram_0_serverAdapterB_outData_enqData_whas) &&
bram_0_serverAdapterB_outData_outData_whas__68_ETC___d1697 ;
assign wmi_wmi_respF_cntr_r_582_MINUS_1___d1590 =
wmi_wmi_respF_cntr_r - 2'd1 ;
assign wti_nowReq_BITS_63_TO_0__q2 = wti_nowReq[63:0] ;
assign x3__h81813 = { 8'd0, wmi_wmi_mFlagF_D_OUT[23:0] } ;
assign x__h29771 = x__h29773 - y__h29774 ;
assign x__h29773 = { tlp_tlpBRAM_readReq_D_OUT[28:19], 2'b0 } ;
assign x__h42208 =
{ tlp_tlpBRAM_mRespF_D_OUT[7:0],
tlp_tlpBRAM_mRespF_D_OUT[15:8],
tlp_tlpBRAM_mRespF_D_OUT[23:16],
tlp_tlpBRAM_mRespF_D_OUT[31:24] } ;
assign x__h47258 = { 15'd0, tlp_mesgLengthRemainPush } ;
assign x__h47542 =
(tlp_mesgLengthRemainPush <= y__h47544) ?
tlp_mesgLengthRemainPush :
y__h47544 ;
assign x__h58352 =
{ tlp_inF_D_OUT[7:0],
tlp_inF_D_OUT[15:8],
tlp_inF_D_OUT[23:16],
tlp_inF_D_OUT[31:24] } ;
assign x__h63608 = { 15'd0, tlp_mesgLengthRemainPull } ;
assign x__h63926 =
(tlp_mesgLengthRemainPull <= y__h63928) ?
tlp_mesgLengthRemainPull :
y__h63928 ;
assign x__h88675 = (dpControl[1:0] == 2'd1) ? bml_fabNumBufs : 16'd0 ;
assign x__h89803 = bml_lclBufsAR + 16'd1 ;
assign x__h89808 = bml_lclBufsAR - 16'd1 ;
assign x__h89915 = bml_lclBufsCF + 16'd1 ;
assign x__h89952 = bml_lclBufsCF - 16'd1 ;
assign x__h90034 = bml_fabBufsAvail + 16'd1 ;
assign x__h90039 = bml_fabBufsAvail - 16'd1 ;
assign x__h90073 = bml_lclCredit + 16'd1 ;
assign x__h90078 = bml_lclCredit - 16'd1 ;
assign y__h17362 = tlp_tlpBRAM_mReqF_D_OUT[63] ? 13'd0 : 13'd1 ;
assign y__h17428 = tlp_tlpBRAM_mReqF_D_OUT[63] ? 10'd0 : 10'd1 ;
assign y__h27653 = tlp_tlpBRAM_mReqF_D_OUT[60] ? 10'd0 : 10'd1 ;
assign y__h27665 = tlp_tlpBRAM_mReqF_D_OUT[60] ? 13'd0 : 13'd1 ;
assign y__h29772 =
(tlp_tlpBRAM_readReq_D_OUT[28:19] == 10'd1) ?
12'd0 :
{ 10'd0, x__h29803 } ;
assign y__h29774 = { 10'd0, x__h29780 } ;
assign y__h30729 = tlp_tlpBRAM_readReq_D_OUT[60] ? 10'd0 : 10'd1 ;
assign y__h47529 = { 4'd0, thisRequestLength__h47504 } ;
assign y__h47544 = { 4'd0, tlp_maxPayloadSize } ;
assign y__h47623 = { 19'd0, thisRequestLength__h47504 } ;
assign y__h47671 = { 3'd0, thisRequestLength__h47504 } ;
assign y__h48147 = (tlp_fabMesgAddrMS == 32'd0) ? 10'd1 : 10'd0 ;
assign y__h48181 = { 20'd0, tlp_tlpBRAM_mRespF_D_OUT[71:62], 2'd0 } ;
assign y__h63918 = { 4'd0, thisRequestLength__h63893 } ;
assign y__h63928 = { 4'd0, tlp_maxReadReqSize } ;
assign y__h63989 = { 19'd0, thisRequestLength__h63893 } ;
assign y__h64598 = { 4'd0, tlp_inF_D_OUT[105:96], 2'd0 } ;
assign y__h65310 =
tlp_dmaPullRemainDWSub_387_ULE_4___d1388 ?
{ 5'd0, tlp_dmaPullRemainDWSub, 2'd0 } :
17'd16 ;
always@(tlp_tlpBRAM_readReq_D_OUT)
begin
case (tlp_tlpBRAM_readReq_D_OUT[18:15])
4'b1100: x__h29780 = 2'b10;
4'b1110: x__h29780 = 2'b01;
4'b1111: x__h29780 = 2'b0;
default: x__h29780 = 2'b11;
endcase
end
always@(tlp_tlpBRAM_readReq_D_OUT)
begin
case (tlp_tlpBRAM_readReq_D_OUT[14:11])
4'b1100: x__h29803 = 2'b10;
4'b1110: x__h29803 = 2'b01;
4'b1111: x__h29803 = 2'b0;
default: x__h29803 = 2'b11;
endcase
end
always@(tlp_lastRuleFired)
begin
case (tlp_lastRuleFired)
4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9, 4'd15:
CASE_tlp_lastRuleFired_1_tlp_lastRuleFired_2_t_ETC__q1 =
tlp_lastRuleFired;
default: CASE_tlp_lastRuleFired_1_tlp_lastRuleFired_2_t_ETC__q1 = 4'd10;
endcase
end
always@(wci_reqF_D_OUT or
rdat__h92026 or
rdat__h92034 or
rdat__h92042 or
rdat__h92050 or
rdat__h92058 or
rdat__h92066 or
rdat__h92074 or
rdat__h92095 or
rdat__h92102 or
rdat__h92115 or
rdat__h92122 or
rdat__h92129 or
rdat__h92401 or
rdat__h92451 or
rdat__h92551 or
bml_fabMesgBase or
bml_fabMetaBase or
bml_fabMesgSize or
bml_fabMetaSize or
bml_fabFlowBase or
bml_fabFlowSize or
rdat__h92609 or
rdat__h92631 or
rdat__h92641 or
rdat__h92763 or
rdat__h92887 or
rdat__h92915 or
rdat__h92943 or
rdat__h92971 or
bml_fabMesgBaseMS or
bml_fabMetaBaseMS or
bml_fabFlowBaseMS or
rdat__h93001 or rdat__h93035 or rdat__h93068 or rdat__h93102)
begin
case (wci_reqF_D_OUT[39:32])
8'h0: _theResult____h91947 = rdat__h92026;
8'h04: _theResult____h91947 = rdat__h92034;
8'h08: _theResult____h91947 = rdat__h92042;
8'h0C: _theResult____h91947 = rdat__h92050;
8'h10: _theResult____h91947 = rdat__h92058;
8'h14: _theResult____h91947 = rdat__h92066;
8'h20: _theResult____h91947 = rdat__h92074;
8'h24: _theResult____h91947 = 32'hF00DFACE;
8'h28: _theResult____h91947 = rdat__h92095;
8'h2C: _theResult____h91947 = rdat__h92102;
8'h30: _theResult____h91947 = rdat__h92115;
8'h34: _theResult____h91947 = rdat__h92122;
8'h38: _theResult____h91947 = rdat__h92129;
8'h3C: _theResult____h91947 = rdat__h92401;
8'h40: _theResult____h91947 = rdat__h92451;
8'h44: _theResult____h91947 = 32'd0;
8'h48: _theResult____h91947 = rdat__h92551;
8'h4C: _theResult____h91947 = 32'h00008000;
8'h50: _theResult____h91947 = bml_fabMesgBase;
8'h54: _theResult____h91947 = bml_fabMetaBase;
8'h58: _theResult____h91947 = bml_fabMesgSize;
8'h5C: _theResult____h91947 = bml_fabMetaSize;
8'h60: _theResult____h91947 = bml_fabFlowBase;
8'h64: _theResult____h91947 = bml_fabFlowSize;
8'h68: _theResult____h91947 = rdat__h92609;
8'h6C: _theResult____h91947 = rdat__h92631;
8'h70: _theResult____h91947 = rdat__h92641;
8'h80: _theResult____h91947 = rdat__h92763;
8'h84: _theResult____h91947 = rdat__h92887;
8'h88: _theResult____h91947 = rdat__h92915;
8'h8C: _theResult____h91947 = rdat__h92943;
8'h90: _theResult____h91947 = rdat__h92971;
8'h94: _theResult____h91947 = bml_fabMesgBaseMS;
8'h98: _theResult____h91947 = bml_fabMetaBaseMS;
8'h9C: _theResult____h91947 = bml_fabFlowBaseMS;
8'hA0: _theResult____h91947 = rdat__h93001;
8'hA4: _theResult____h91947 = rdat__h93035;
8'hA8: _theResult____h91947 = rdat__h93068;
8'hAC: _theResult____h91947 = rdat__h93102;
default: _theResult____h91947 = 32'd0;
endcase
end
always@(tlp_tlpBRAM_readReq_D_OUT)
begin
case (tlp_tlpBRAM_readReq_D_OUT[18:15])
4'b1000: lowAddr10__h29651 = 2'b11;
4'b1100: lowAddr10__h29651 = 2'b10;
4'b1110: lowAddr10__h29651 = 2'b01;
default: lowAddr10__h29651 = 2'b0;
endcase
end
always@(tlp_tlpBRAM_mReqF_D_OUT or
bram_0_serverAdapterA_cnt_6_SLT_3___d619 or
bram_1_serverAdapterA_cnt_44_SLT_3___d620 or
bram_2_serverAdapterA_cnt_62_SLT_3___d621 or
bram_3_serverAdapterA_cnt_80_SLT_3___d622)
begin
case (tlp_tlpBRAM_mReqF_D_OUT[51:50])
2'd0:
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_51_TO_50_ETC___d623 =
bram_0_serverAdapterA_cnt_6_SLT_3___d619;
2'd1:
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_51_TO_50_ETC___d623 =
bram_1_serverAdapterA_cnt_44_SLT_3___d620;
2'd2:
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_51_TO_50_ETC___d623 =
bram_2_serverAdapterA_cnt_62_SLT_3___d621;
2'd3:
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_51_TO_50_ETC___d623 =
bram_3_serverAdapterA_cnt_80_SLT_3___d622;
endcase
end
always@(idx__h21626 or
tlp_tlpBRAM_writeRemainDWLen or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656 or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658 or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660)
begin
case (idx__h21626)
2'd0:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 =
tlp_tlpBRAM_writeRemainDWLen != 10'd0;
2'd1:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656;
2'd2:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658;
2'd3:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660;
endcase
end
always@(idx__h23676 or
tlp_tlpBRAM_writeRemainDWLen or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656 or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658 or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660)
begin
case (idx__h23676)
2'd0:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 =
tlp_tlpBRAM_writeRemainDWLen != 10'd0;
2'd1:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656;
2'd2:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658;
2'd3:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660;
endcase
end
always@(idx__h24781 or
tlp_tlpBRAM_writeRemainDWLen or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656 or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658 or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660)
begin
case (idx__h24781)
2'd0:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 =
tlp_tlpBRAM_writeRemainDWLen != 10'd0;
2'd1:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656;
2'd2:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658;
2'd3:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660;
endcase
end
always@(idx__h25886 or
tlp_tlpBRAM_writeRemainDWLen or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656 or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658 or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660)
begin
case (idx__h25886)
2'd0:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 =
tlp_tlpBRAM_writeRemainDWLen != 10'd0;
2'd1:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656;
2'd2:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658;
2'd3:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660;
endcase
end
always@(idx__h21626 or tlp_tlpBRAM_mReqF_D_OUT)
begin
case (idx__h21626)
2'd0:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700 =
tlp_tlpBRAM_mReqF_D_OUT[127:96];
2'd1:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700 =
tlp_tlpBRAM_mReqF_D_OUT[95:64];
2'd2:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700 =
tlp_tlpBRAM_mReqF_D_OUT[63:32];
2'd3:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700 =
tlp_tlpBRAM_mReqF_D_OUT[31:0];
endcase
end
always@(idx__h23676 or tlp_tlpBRAM_mReqF_D_OUT)
begin
case (idx__h23676)
2'd0:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708 =
tlp_tlpBRAM_mReqF_D_OUT[127:96];
2'd1:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708 =
tlp_tlpBRAM_mReqF_D_OUT[95:64];
2'd2:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708 =
tlp_tlpBRAM_mReqF_D_OUT[63:32];
2'd3:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708 =
tlp_tlpBRAM_mReqF_D_OUT[31:0];
endcase
end
always@(idx__h24781 or tlp_tlpBRAM_mReqF_D_OUT)
begin
case (idx__h24781)
2'd0:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716 =
tlp_tlpBRAM_mReqF_D_OUT[127:96];
2'd1:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716 =
tlp_tlpBRAM_mReqF_D_OUT[95:64];
2'd2:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716 =
tlp_tlpBRAM_mReqF_D_OUT[63:32];
2'd3:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716 =
tlp_tlpBRAM_mReqF_D_OUT[31:0];
endcase
end
always@(idx__h25886 or tlp_tlpBRAM_mReqF_D_OUT)
begin
case (idx__h25886)
2'd0:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724 =
tlp_tlpBRAM_mReqF_D_OUT[127:96];
2'd1:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724 =
tlp_tlpBRAM_mReqF_D_OUT[95:64];
2'd2:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724 =
tlp_tlpBRAM_mReqF_D_OUT[63:32];
2'd3:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724 =
tlp_tlpBRAM_mReqF_D_OUT[31:0];
endcase
end
always@(tlp_tlpBRAM_mReqF_D_OUT or
bram_0_serverAdapterA_cnt_6_SLT_3___d619 or
bram_1_serverAdapterA_cnt_44_SLT_3___d620 or
bram_2_serverAdapterA_cnt_62_SLT_3___d621 or
bram_3_serverAdapterA_cnt_80_SLT_3___d622)
begin
case (tlp_tlpBRAM_mReqF_D_OUT[30:29])
2'd0:
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_30_TO_29_ETC___d736 =
bram_0_serverAdapterA_cnt_6_SLT_3___d619;
2'd1:
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_30_TO_29_ETC___d736 =
bram_1_serverAdapterA_cnt_44_SLT_3___d620;
2'd2:
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_30_TO_29_ETC___d736 =
bram_2_serverAdapterA_cnt_62_SLT_3___d621;
2'd3:
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_30_TO_29_ETC___d736 =
bram_3_serverAdapterA_cnt_80_SLT_3___d622;
endcase
end
always@(tlp_outDwRemain)
begin
case (tlp_outDwRemain[1:0])
2'b0: CASE_tlp_outDwRemain_BITS_1_TO_0_0b0_0xFFFF_0b_ETC__q3 = 16'hFFFF;
2'b01:
CASE_tlp_outDwRemain_BITS_1_TO_0_0b0_0xFFFF_0b_ETC__q3 = 16'hF000;
2'b10:
CASE_tlp_outDwRemain_BITS_1_TO_0_0b0_0xFFFF_0b_ETC__q3 = 16'hFF00;
2'd3: CASE_tlp_outDwRemain_BITS_1_TO_0_0b0_0xFFFF_0b_ETC__q3 = 16'hFFF0;
endcase
end
always@(dpControl or bml_fabDone or bml_remDone)
begin
case (dpControl[1:0])
2'd0:
CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_bml_ETC__q4 =
bml_fabDone;
2'd1:
CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_bml_ETC__q4 =
bml_remDone;
default: CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_bml_ETC__q4 =
bml_fabDone;
endcase
end
always@(dpControl or bml_fabDone or bml_remDone)
begin
case (dpControl[1:0])
2'd0:
CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q5 =
!bml_fabDone;
2'd1:
CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q5 =
!bml_remDone;
default: CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q5 =
!bml_fabDone;
endcase
end
always@(dpControl or
bml_fabDone or
IF_bml_dpControl_wget__898_BITS_3_TO_2_899_EQ__ETC___d1995)
begin
case (dpControl[1:0])
2'd0:
CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q6 =
!bml_fabDone;
2'd1:
CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q6 =
IF_bml_dpControl_wget__898_BITS_3_TO_2_899_EQ__ETC___d1995;
default: CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q6 =
!bml_fabDone;
endcase
end
always@(dpControl or bml_fabDone or bml_remDone or bml_remStart)
begin
case (dpControl[1:0])
2'd0:
CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_IF__ETC__q7 =
bml_fabDone;
2'd1:
CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_IF__ETC__q7 =
(dpControl[3:2] == 2'd1) ? bml_remDone : bml_remStart;
default: CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_IF__ETC__q7 =
bml_fabDone;
endcase
end
always@(tlp_tlpBRAM_readReq_D_OUT or
bram_0_serverAdapterA_outDataCore_EMPTY_N or
bram_0_serverAdapterA_outData_enqData_whas or
bram_1_serverAdapterA_outDataCore_EMPTY_N or
bram_1_serverAdapterA_outData_enqData_whas or
bram_2_serverAdapterA_outDataCore_EMPTY_N or
bram_2_serverAdapterA_outData_enqData_whas or
bram_3_serverAdapterA_outDataCore_EMPTY_N or
bram_3_serverAdapterA_outData_enqData_whas)
begin
case (tlp_tlpBRAM_readReq_D_OUT[30:29])
2'd0:
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d805 =
bram_0_serverAdapterA_outDataCore_EMPTY_N ||
bram_0_serverAdapterA_outData_enqData_whas;
2'd1:
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d805 =
bram_1_serverAdapterA_outDataCore_EMPTY_N ||
bram_1_serverAdapterA_outData_enqData_whas;
2'd2:
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d805 =
bram_2_serverAdapterA_outDataCore_EMPTY_N ||
bram_2_serverAdapterA_outData_enqData_whas;
2'd3:
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d805 =
bram_3_serverAdapterA_outDataCore_EMPTY_N ||
bram_3_serverAdapterA_outData_enqData_whas;
endcase
end
always@(tlp_tlpBRAM_readReq_D_OUT or
bram_0_serverAdapterA_outData_outData_wget or
bram_1_serverAdapterA_outData_outData_wget or
bram_2_serverAdapterA_outData_outData_wget or
bram_3_serverAdapterA_outData_outData_wget)
begin
case (tlp_tlpBRAM_readReq_D_OUT[30:29])
2'd0:
SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863 =
bram_0_serverAdapterA_outData_outData_wget;
2'd1:
SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863 =
bram_1_serverAdapterA_outData_outData_wget;
2'd2:
SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863 =
bram_2_serverAdapterA_outData_outData_wget;
2'd3:
SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863 =
bram_3_serverAdapterA_outData_outData_wget;
endcase
end
always@(tlp_tlpBRAM_readReq_D_OUT or
bram_0_serverAdapterA_outData_outData_whas or
bram_1_serverAdapterA_outData_outData_whas or
bram_2_serverAdapterA_outData_outData_whas or
bram_3_serverAdapterA_outData_outData_whas)
begin
case (tlp_tlpBRAM_readReq_D_OUT[30:29])
2'd0:
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d810 =
bram_0_serverAdapterA_outData_outData_whas;
2'd1:
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d810 =
bram_1_serverAdapterA_outData_outData_whas;
2'd2:
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d810 =
bram_2_serverAdapterA_outData_outData_whas;
2'd3:
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d810 =
bram_3_serverAdapterA_outData_outData_whas;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
bml_crdBuf_modulus <= `BSV_ASSIGNMENT_DELAY 16'd65535;
bml_crdBuf_value <= `BSV_ASSIGNMENT_DELAY 16'd0;
bml_datumAReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
bml_fabAvail <= `BSV_ASSIGNMENT_DELAY 1'd0;
bml_fabBuf_modulus <= `BSV_ASSIGNMENT_DELAY 16'd65535;
bml_fabBuf_value <= `BSV_ASSIGNMENT_DELAY 16'd0;
bml_fabDone <= `BSV_ASSIGNMENT_DELAY 1'd0;
bml_fabFlowBase <= `BSV_ASSIGNMENT_DELAY 32'hFFFF0018;
bml_fabFlowBaseMS <= `BSV_ASSIGNMENT_DELAY 32'h0;
bml_fabFlowSize <= `BSV_ASSIGNMENT_DELAY 32'h00000004;
bml_fabMesgBase <= `BSV_ASSIGNMENT_DELAY 32'hFFFF0000;
bml_fabMesgBaseMS <= `BSV_ASSIGNMENT_DELAY 32'h0;
bml_fabMesgSize <= `BSV_ASSIGNMENT_DELAY 32'h00000800;
bml_fabMetaBase <= `BSV_ASSIGNMENT_DELAY 32'hFFFF3800;
bml_fabMetaBaseMS <= `BSV_ASSIGNMENT_DELAY 32'h0;
bml_fabMetaSize <= `BSV_ASSIGNMENT_DELAY 32'h00000010;
bml_fabNumBufs <= `BSV_ASSIGNMENT_DELAY 16'd1;
bml_lclBufDone <= `BSV_ASSIGNMENT_DELAY 1'd0;
bml_lclBufStart <= `BSV_ASSIGNMENT_DELAY 1'd0;
bml_lclBuf_modulus <= `BSV_ASSIGNMENT_DELAY 16'd65535;
bml_lclBuf_value <= `BSV_ASSIGNMENT_DELAY 16'd0;
bml_lclDones <= `BSV_ASSIGNMENT_DELAY 16'd0;
bml_lclNumBufs <= `BSV_ASSIGNMENT_DELAY 16'd1;
bml_lclStarts <= `BSV_ASSIGNMENT_DELAY 16'd0;
bml_mesgBase <= `BSV_ASSIGNMENT_DELAY 16'h0;
bml_mesgSize <= `BSV_ASSIGNMENT_DELAY 16'h0800;
bml_metaBase <= `BSV_ASSIGNMENT_DELAY 16'h3800;
bml_metaSize <= `BSV_ASSIGNMENT_DELAY 16'h0010;
bml_remBuf_modulus <= `BSV_ASSIGNMENT_DELAY 16'd65535;
bml_remBuf_value <= `BSV_ASSIGNMENT_DELAY 16'd0;
bml_remDone <= `BSV_ASSIGNMENT_DELAY 1'd0;
bml_remDones <= `BSV_ASSIGNMENT_DELAY 16'd0;
bml_remStart <= `BSV_ASSIGNMENT_DELAY 1'd0;
bml_remStarts <= `BSV_ASSIGNMENT_DELAY 16'd0;
bram_0_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
bram_0_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
bram_0_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
bram_0_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
bram_1_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
bram_1_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
bram_1_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
bram_1_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
bram_2_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
bram_2_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
bram_2_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
bram_2_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
bram_3_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
bram_3_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
bram_3_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
bram_3_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
dmaDoneTime <= `BSV_ASSIGNMENT_DELAY 64'd0;
dmaStartTime <= `BSV_ASSIGNMENT_DELAY 64'd0;
dpControl <= `BSV_ASSIGNMENT_DELAY 8'd0;
tlp_complTimerCount <= `BSV_ASSIGNMENT_DELAY 12'd0;
tlp_complTimerRunning <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_creditReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_dmaDoTailEvent <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_dmaDoneMark <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_dmaStartMark <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_dmaTag <= `BSV_ASSIGNMENT_DELAY 5'd0;
tlp_doXmtMetaBody <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_doorSeqDwell <= `BSV_ASSIGNMENT_DELAY 4'd0;
tlp_fabMeta <= `BSV_ASSIGNMENT_DELAY
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
tlp_farBufReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_flowDiagCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
tlp_gotResponseHeader <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_lastMetaV_0 <= `BSV_ASSIGNMENT_DELAY 32'd0;
tlp_lastMetaV_1 <= `BSV_ASSIGNMENT_DELAY 32'd0;
tlp_lastMetaV_2 <= `BSV_ASSIGNMENT_DELAY 32'd0;
tlp_lastMetaV_3 <= `BSV_ASSIGNMENT_DELAY 32'd0;
tlp_lastRuleFired <= `BSV_ASSIGNMENT_DELAY 4'd15;
tlp_maxPayloadSize <= `BSV_ASSIGNMENT_DELAY 13'd128;
tlp_maxReadReqSize <= `BSV_ASSIGNMENT_DELAY 13'd4096;
tlp_nearBufReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_postSeqDwell <= `BSV_ASSIGNMENT_DELAY 4'd0;
tlp_pullTagMatch <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_remDone <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_remStart <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_reqMesgInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_reqMetaBodyInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_reqMetaInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_sentTail4DWHeader <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_tlpBRAM_debugBdata <= `BSV_ASSIGNMENT_DELAY 128'd0;
tlp_tlpBRAM_readHeaderSent <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_tlpBRAM_readStarted <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_tlpMetaSent <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_tlpRcvBusy <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_tlpXmtBusy <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_xmtMetaInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_xmtMetaOK <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmi_bufDwell <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmi_bytesRemainResp <= `BSV_ASSIGNMENT_DELAY 14'd0;
wmi_doneWithMesg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_lastMesg <= `BSV_ASSIGNMENT_DELAY 32'hFEFEFFFE;
wmi_mesgBufReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_mesgBusy <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_mesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmi_mesgDone <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_mesgMeta <= `BSV_ASSIGNMENT_DELAY
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmi_mesgStart <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_metaBusy <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_p4B <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmi_rdActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_reqCount <= `BSV_ASSIGNMENT_DELAY 16'd0;
wmi_thisMesg <= `BSV_ASSIGNMENT_DELAY 32'hFEFEFFFE;
wmi_wmi_blockReq <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_wmi_dhF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmi_wmi_dhF_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmi_wmi_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_wmi_mFlagF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmi_wmi_mFlagF_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmi_wmi_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_wmi_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_wmi_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmi_wmi_reqF_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmi_wmi_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmi_wmi_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 130'd0;
wmi_wmi_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 130'd0;
wmi_wmi_sFlagReg <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmi_wmi_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_wrActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_wrFinalize <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_wrtCount <= `BSV_ASSIGNMENT_DELAY 16'd0;
wti_nowReq <= `BSV_ASSIGNMENT_DELAY 67'd0;
wti_operateD <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (bml_crdBuf_modulus_EN)
bml_crdBuf_modulus <= `BSV_ASSIGNMENT_DELAY bml_crdBuf_modulus_D_IN;
if (bml_crdBuf_value_EN)
bml_crdBuf_value <= `BSV_ASSIGNMENT_DELAY bml_crdBuf_value_D_IN;
if (bml_datumAReg_EN)
bml_datumAReg <= `BSV_ASSIGNMENT_DELAY bml_datumAReg_D_IN;
if (bml_fabAvail_EN)
bml_fabAvail <= `BSV_ASSIGNMENT_DELAY bml_fabAvail_D_IN;
if (bml_fabBuf_modulus_EN)
bml_fabBuf_modulus <= `BSV_ASSIGNMENT_DELAY bml_fabBuf_modulus_D_IN;
if (bml_fabBuf_value_EN)
bml_fabBuf_value <= `BSV_ASSIGNMENT_DELAY bml_fabBuf_value_D_IN;
if (bml_fabDone_EN)
bml_fabDone <= `BSV_ASSIGNMENT_DELAY bml_fabDone_D_IN;
if (bml_fabFlowBase_EN)
bml_fabFlowBase <= `BSV_ASSIGNMENT_DELAY bml_fabFlowBase_D_IN;
if (bml_fabFlowBaseMS_EN)
bml_fabFlowBaseMS <= `BSV_ASSIGNMENT_DELAY bml_fabFlowBaseMS_D_IN;
if (bml_fabFlowSize_EN)
bml_fabFlowSize <= `BSV_ASSIGNMENT_DELAY bml_fabFlowSize_D_IN;
if (bml_fabMesgBase_EN)
bml_fabMesgBase <= `BSV_ASSIGNMENT_DELAY bml_fabMesgBase_D_IN;
if (bml_fabMesgBaseMS_EN)
bml_fabMesgBaseMS <= `BSV_ASSIGNMENT_DELAY bml_fabMesgBaseMS_D_IN;
if (bml_fabMesgSize_EN)
bml_fabMesgSize <= `BSV_ASSIGNMENT_DELAY bml_fabMesgSize_D_IN;
if (bml_fabMetaBase_EN)
bml_fabMetaBase <= `BSV_ASSIGNMENT_DELAY bml_fabMetaBase_D_IN;
if (bml_fabMetaBaseMS_EN)
bml_fabMetaBaseMS <= `BSV_ASSIGNMENT_DELAY bml_fabMetaBaseMS_D_IN;
if (bml_fabMetaSize_EN)
bml_fabMetaSize <= `BSV_ASSIGNMENT_DELAY bml_fabMetaSize_D_IN;
if (bml_fabNumBufs_EN)
bml_fabNumBufs <= `BSV_ASSIGNMENT_DELAY bml_fabNumBufs_D_IN;
if (bml_lclBufDone_EN)
bml_lclBufDone <= `BSV_ASSIGNMENT_DELAY bml_lclBufDone_D_IN;
if (bml_lclBufStart_EN)
bml_lclBufStart <= `BSV_ASSIGNMENT_DELAY bml_lclBufStart_D_IN;
if (bml_lclBuf_modulus_EN)
bml_lclBuf_modulus <= `BSV_ASSIGNMENT_DELAY bml_lclBuf_modulus_D_IN;
if (bml_lclBuf_value_EN)
bml_lclBuf_value <= `BSV_ASSIGNMENT_DELAY bml_lclBuf_value_D_IN;
if (bml_lclDones_EN)
bml_lclDones <= `BSV_ASSIGNMENT_DELAY bml_lclDones_D_IN;
if (bml_lclNumBufs_EN)
bml_lclNumBufs <= `BSV_ASSIGNMENT_DELAY bml_lclNumBufs_D_IN;
if (bml_lclStarts_EN)
bml_lclStarts <= `BSV_ASSIGNMENT_DELAY bml_lclStarts_D_IN;
if (bml_mesgBase_EN)
bml_mesgBase <= `BSV_ASSIGNMENT_DELAY bml_mesgBase_D_IN;
if (bml_mesgSize_EN)
bml_mesgSize <= `BSV_ASSIGNMENT_DELAY bml_mesgSize_D_IN;
if (bml_metaBase_EN)
bml_metaBase <= `BSV_ASSIGNMENT_DELAY bml_metaBase_D_IN;
if (bml_metaSize_EN)
bml_metaSize <= `BSV_ASSIGNMENT_DELAY bml_metaSize_D_IN;
if (bml_remBuf_modulus_EN)
bml_remBuf_modulus <= `BSV_ASSIGNMENT_DELAY bml_remBuf_modulus_D_IN;
if (bml_remBuf_value_EN)
bml_remBuf_value <= `BSV_ASSIGNMENT_DELAY bml_remBuf_value_D_IN;
if (bml_remDone_EN)
bml_remDone <= `BSV_ASSIGNMENT_DELAY bml_remDone_D_IN;
if (bml_remDones_EN)
bml_remDones <= `BSV_ASSIGNMENT_DELAY bml_remDones_D_IN;
if (bml_remStart_EN)
bml_remStart <= `BSV_ASSIGNMENT_DELAY bml_remStart_D_IN;
if (bml_remStarts_EN)
bml_remStarts <= `BSV_ASSIGNMENT_DELAY bml_remStarts_D_IN;
if (bram_0_serverAdapterA_cnt_EN)
bram_0_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
bram_0_serverAdapterA_cnt_D_IN;
if (bram_0_serverAdapterA_s1_EN)
bram_0_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
bram_0_serverAdapterA_s1_D_IN;
if (bram_0_serverAdapterB_cnt_EN)
bram_0_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
bram_0_serverAdapterB_cnt_D_IN;
if (bram_0_serverAdapterB_s1_EN)
bram_0_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
bram_0_serverAdapterB_s1_D_IN;
if (bram_1_serverAdapterA_cnt_EN)
bram_1_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
bram_1_serverAdapterA_cnt_D_IN;
if (bram_1_serverAdapterA_s1_EN)
bram_1_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
bram_1_serverAdapterA_s1_D_IN;
if (bram_1_serverAdapterB_cnt_EN)
bram_1_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
bram_1_serverAdapterB_cnt_D_IN;
if (bram_1_serverAdapterB_s1_EN)
bram_1_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
bram_1_serverAdapterB_s1_D_IN;
if (bram_2_serverAdapterA_cnt_EN)
bram_2_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
bram_2_serverAdapterA_cnt_D_IN;
if (bram_2_serverAdapterA_s1_EN)
bram_2_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
bram_2_serverAdapterA_s1_D_IN;
if (bram_2_serverAdapterB_cnt_EN)
bram_2_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
bram_2_serverAdapterB_cnt_D_IN;
if (bram_2_serverAdapterB_s1_EN)
bram_2_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
bram_2_serverAdapterB_s1_D_IN;
if (bram_3_serverAdapterA_cnt_EN)
bram_3_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
bram_3_serverAdapterA_cnt_D_IN;
if (bram_3_serverAdapterA_s1_EN)
bram_3_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
bram_3_serverAdapterA_s1_D_IN;
if (bram_3_serverAdapterB_cnt_EN)
bram_3_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
bram_3_serverAdapterB_cnt_D_IN;
if (bram_3_serverAdapterB_s1_EN)
bram_3_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
bram_3_serverAdapterB_s1_D_IN;
if (dmaDoneTime_EN)
dmaDoneTime <= `BSV_ASSIGNMENT_DELAY dmaDoneTime_D_IN;
if (dmaStartTime_EN)
dmaStartTime <= `BSV_ASSIGNMENT_DELAY dmaStartTime_D_IN;
if (dpControl_EN) dpControl <= `BSV_ASSIGNMENT_DELAY dpControl_D_IN;
if (tlp_complTimerCount_EN)
tlp_complTimerCount <= `BSV_ASSIGNMENT_DELAY
tlp_complTimerCount_D_IN;
if (tlp_complTimerRunning_EN)
tlp_complTimerRunning <= `BSV_ASSIGNMENT_DELAY
tlp_complTimerRunning_D_IN;
if (tlp_creditReady_EN)
tlp_creditReady <= `BSV_ASSIGNMENT_DELAY tlp_creditReady_D_IN;
if (tlp_dmaDoTailEvent_EN)
tlp_dmaDoTailEvent <= `BSV_ASSIGNMENT_DELAY tlp_dmaDoTailEvent_D_IN;
if (tlp_dmaDoneMark_EN)
tlp_dmaDoneMark <= `BSV_ASSIGNMENT_DELAY tlp_dmaDoneMark_D_IN;
if (tlp_dmaStartMark_EN)
tlp_dmaStartMark <= `BSV_ASSIGNMENT_DELAY tlp_dmaStartMark_D_IN;
if (tlp_dmaTag_EN)
tlp_dmaTag <= `BSV_ASSIGNMENT_DELAY tlp_dmaTag_D_IN;
if (tlp_doXmtMetaBody_EN)
tlp_doXmtMetaBody <= `BSV_ASSIGNMENT_DELAY tlp_doXmtMetaBody_D_IN;
if (tlp_doorSeqDwell_EN)
tlp_doorSeqDwell <= `BSV_ASSIGNMENT_DELAY tlp_doorSeqDwell_D_IN;
if (tlp_fabMeta_EN)
tlp_fabMeta <= `BSV_ASSIGNMENT_DELAY tlp_fabMeta_D_IN;
if (tlp_farBufReady_EN)
tlp_farBufReady <= `BSV_ASSIGNMENT_DELAY tlp_farBufReady_D_IN;
if (tlp_flowDiagCount_EN)
tlp_flowDiagCount <= `BSV_ASSIGNMENT_DELAY tlp_flowDiagCount_D_IN;
if (tlp_gotResponseHeader_EN)
tlp_gotResponseHeader <= `BSV_ASSIGNMENT_DELAY
tlp_gotResponseHeader_D_IN;
if (tlp_lastMetaV_0_EN)
tlp_lastMetaV_0 <= `BSV_ASSIGNMENT_DELAY tlp_lastMetaV_0_D_IN;
if (tlp_lastMetaV_1_EN)
tlp_lastMetaV_1 <= `BSV_ASSIGNMENT_DELAY tlp_lastMetaV_1_D_IN;
if (tlp_lastMetaV_2_EN)
tlp_lastMetaV_2 <= `BSV_ASSIGNMENT_DELAY tlp_lastMetaV_2_D_IN;
if (tlp_lastMetaV_3_EN)
tlp_lastMetaV_3 <= `BSV_ASSIGNMENT_DELAY tlp_lastMetaV_3_D_IN;
if (tlp_lastRuleFired_EN)
tlp_lastRuleFired <= `BSV_ASSIGNMENT_DELAY tlp_lastRuleFired_D_IN;
if (tlp_maxPayloadSize_EN)
tlp_maxPayloadSize <= `BSV_ASSIGNMENT_DELAY tlp_maxPayloadSize_D_IN;
if (tlp_maxReadReqSize_EN)
tlp_maxReadReqSize <= `BSV_ASSIGNMENT_DELAY tlp_maxReadReqSize_D_IN;
if (tlp_nearBufReady_EN)
tlp_nearBufReady <= `BSV_ASSIGNMENT_DELAY tlp_nearBufReady_D_IN;
if (tlp_postSeqDwell_EN)
tlp_postSeqDwell <= `BSV_ASSIGNMENT_DELAY tlp_postSeqDwell_D_IN;
if (tlp_pullTagMatch_EN)
tlp_pullTagMatch <= `BSV_ASSIGNMENT_DELAY tlp_pullTagMatch_D_IN;
if (tlp_remDone_EN)
tlp_remDone <= `BSV_ASSIGNMENT_DELAY tlp_remDone_D_IN;
if (tlp_remStart_EN)
tlp_remStart <= `BSV_ASSIGNMENT_DELAY tlp_remStart_D_IN;
if (tlp_reqMesgInFlight_EN)
tlp_reqMesgInFlight <= `BSV_ASSIGNMENT_DELAY
tlp_reqMesgInFlight_D_IN;
if (tlp_reqMetaBodyInFlight_EN)
tlp_reqMetaBodyInFlight <= `BSV_ASSIGNMENT_DELAY
tlp_reqMetaBodyInFlight_D_IN;
if (tlp_reqMetaInFlight_EN)
tlp_reqMetaInFlight <= `BSV_ASSIGNMENT_DELAY
tlp_reqMetaInFlight_D_IN;
if (tlp_sentTail4DWHeader_EN)
tlp_sentTail4DWHeader <= `BSV_ASSIGNMENT_DELAY
tlp_sentTail4DWHeader_D_IN;
if (tlp_tlpBRAM_debugBdata_EN)
tlp_tlpBRAM_debugBdata <= `BSV_ASSIGNMENT_DELAY
tlp_tlpBRAM_debugBdata_D_IN;
if (tlp_tlpBRAM_readHeaderSent_EN)
tlp_tlpBRAM_readHeaderSent <= `BSV_ASSIGNMENT_DELAY
tlp_tlpBRAM_readHeaderSent_D_IN;
if (tlp_tlpBRAM_readStarted_EN)
tlp_tlpBRAM_readStarted <= `BSV_ASSIGNMENT_DELAY
tlp_tlpBRAM_readStarted_D_IN;
if (tlp_tlpMetaSent_EN)
tlp_tlpMetaSent <= `BSV_ASSIGNMENT_DELAY tlp_tlpMetaSent_D_IN;
if (tlp_tlpRcvBusy_EN)
tlp_tlpRcvBusy <= `BSV_ASSIGNMENT_DELAY tlp_tlpRcvBusy_D_IN;
if (tlp_tlpXmtBusy_EN)
tlp_tlpXmtBusy <= `BSV_ASSIGNMENT_DELAY tlp_tlpXmtBusy_D_IN;
if (tlp_xmtMetaInFlight_EN)
tlp_xmtMetaInFlight <= `BSV_ASSIGNMENT_DELAY
tlp_xmtMetaInFlight_D_IN;
if (tlp_xmtMetaOK_EN)
tlp_xmtMetaOK <= `BSV_ASSIGNMENT_DELAY tlp_xmtMetaOK_D_IN;
if (wci_cEdge_EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge_D_IN;
if (wci_cState_EN)
wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState_D_IN;
if (wci_ctlAckReg_EN)
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg_D_IN;
if (wci_ctlOpActive_EN)
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive_D_IN;
if (wci_illegalEdge_EN)
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge_D_IN;
if (wci_nState_EN)
wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState_D_IN;
if (wci_reqF_countReg_EN)
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg_D_IN;
if (wci_respF_cntr_r_EN)
wci_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY wci_respF_cntr_r_D_IN;
if (wci_respF_q_0_EN)
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0_D_IN;
if (wci_respF_q_1_EN)
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1_D_IN;
if (wci_sFlagReg_EN)
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg_D_IN;
if (wci_sThreadBusy_d_EN)
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d_D_IN;
if (wmi_bufDwell_EN)
wmi_bufDwell <= `BSV_ASSIGNMENT_DELAY wmi_bufDwell_D_IN;
if (wmi_bytesRemainResp_EN)
wmi_bytesRemainResp <= `BSV_ASSIGNMENT_DELAY
wmi_bytesRemainResp_D_IN;
if (wmi_doneWithMesg_EN)
wmi_doneWithMesg <= `BSV_ASSIGNMENT_DELAY wmi_doneWithMesg_D_IN;
if (wmi_lastMesg_EN)
wmi_lastMesg <= `BSV_ASSIGNMENT_DELAY wmi_lastMesg_D_IN;
if (wmi_mesgBufReady_EN)
wmi_mesgBufReady <= `BSV_ASSIGNMENT_DELAY wmi_mesgBufReady_D_IN;
if (wmi_mesgBusy_EN)
wmi_mesgBusy <= `BSV_ASSIGNMENT_DELAY wmi_mesgBusy_D_IN;
if (wmi_mesgCount_EN)
wmi_mesgCount <= `BSV_ASSIGNMENT_DELAY wmi_mesgCount_D_IN;
if (wmi_mesgDone_EN)
wmi_mesgDone <= `BSV_ASSIGNMENT_DELAY wmi_mesgDone_D_IN;
if (wmi_mesgMeta_EN)
wmi_mesgMeta <= `BSV_ASSIGNMENT_DELAY wmi_mesgMeta_D_IN;
if (wmi_mesgStart_EN)
wmi_mesgStart <= `BSV_ASSIGNMENT_DELAY wmi_mesgStart_D_IN;
if (wmi_metaBusy_EN)
wmi_metaBusy <= `BSV_ASSIGNMENT_DELAY wmi_metaBusy_D_IN;
if (wmi_p4B_EN) wmi_p4B <= `BSV_ASSIGNMENT_DELAY wmi_p4B_D_IN;
if (wmi_rdActive_EN)
wmi_rdActive <= `BSV_ASSIGNMENT_DELAY wmi_rdActive_D_IN;
if (wmi_reqCount_EN)
wmi_reqCount <= `BSV_ASSIGNMENT_DELAY wmi_reqCount_D_IN;
if (wmi_thisMesg_EN)
wmi_thisMesg <= `BSV_ASSIGNMENT_DELAY wmi_thisMesg_D_IN;
if (wmi_wmi_blockReq_EN)
wmi_wmi_blockReq <= `BSV_ASSIGNMENT_DELAY wmi_wmi_blockReq_D_IN;
if (wmi_wmi_dhF_countReg_EN)
wmi_wmi_dhF_countReg <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_dhF_countReg_D_IN;
if (wmi_wmi_dhF_levelsValid_EN)
wmi_wmi_dhF_levelsValid <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_dhF_levelsValid_D_IN;
if (wmi_wmi_errorSticky_EN)
wmi_wmi_errorSticky <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_errorSticky_D_IN;
if (wmi_wmi_mFlagF_countReg_EN)
wmi_wmi_mFlagF_countReg <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_mFlagF_countReg_D_IN;
if (wmi_wmi_mFlagF_levelsValid_EN)
wmi_wmi_mFlagF_levelsValid <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_mFlagF_levelsValid_D_IN;
if (wmi_wmi_operateD_EN)
wmi_wmi_operateD <= `BSV_ASSIGNMENT_DELAY wmi_wmi_operateD_D_IN;
if (wmi_wmi_peerIsReady_EN)
wmi_wmi_peerIsReady <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_peerIsReady_D_IN;
if (wmi_wmi_reqF_countReg_EN)
wmi_wmi_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_reqF_countReg_D_IN;
if (wmi_wmi_reqF_levelsValid_EN)
wmi_wmi_reqF_levelsValid <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_reqF_levelsValid_D_IN;
if (wmi_wmi_respF_cntr_r_EN)
wmi_wmi_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_respF_cntr_r_D_IN;
if (wmi_wmi_respF_q_0_EN)
wmi_wmi_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_wmi_respF_q_0_D_IN;
if (wmi_wmi_respF_q_1_EN)
wmi_wmi_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wmi_wmi_respF_q_1_D_IN;
if (wmi_wmi_sFlagReg_EN)
wmi_wmi_sFlagReg <= `BSV_ASSIGNMENT_DELAY wmi_wmi_sFlagReg_D_IN;
if (wmi_wmi_trafficSticky_EN)
wmi_wmi_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_trafficSticky_D_IN;
if (wmi_wrActive_EN)
wmi_wrActive <= `BSV_ASSIGNMENT_DELAY wmi_wrActive_D_IN;
if (wmi_wrFinalize_EN)
wmi_wrFinalize <= `BSV_ASSIGNMENT_DELAY wmi_wrFinalize_D_IN;
if (wmi_wrtCount_EN)
wmi_wrtCount <= `BSV_ASSIGNMENT_DELAY wmi_wrtCount_D_IN;
if (wti_nowReq_EN)
wti_nowReq <= `BSV_ASSIGNMENT_DELAY wti_nowReq_D_IN;
if (wti_operateD_EN)
wti_operateD <= `BSV_ASSIGNMENT_DELAY wti_operateD_D_IN;
end
if (bml_fabBufsAvail_EN)
bml_fabBufsAvail <= `BSV_ASSIGNMENT_DELAY bml_fabBufsAvail_D_IN;
if (bml_fabFlowAddr_EN)
bml_fabFlowAddr <= `BSV_ASSIGNMENT_DELAY bml_fabFlowAddr_D_IN;
if (bml_fabMesgAddr_EN)
bml_fabMesgAddr <= `BSV_ASSIGNMENT_DELAY bml_fabMesgAddr_D_IN;
if (bml_fabMetaAddr_EN)
bml_fabMetaAddr <= `BSV_ASSIGNMENT_DELAY bml_fabMetaAddr_D_IN;
if (bml_lclBufsAR_EN)
bml_lclBufsAR <= `BSV_ASSIGNMENT_DELAY bml_lclBufsAR_D_IN;
if (bml_lclBufsCF_EN)
bml_lclBufsCF <= `BSV_ASSIGNMENT_DELAY bml_lclBufsCF_D_IN;
if (bml_lclCredit_EN)
bml_lclCredit <= `BSV_ASSIGNMENT_DELAY bml_lclCredit_D_IN;
if (bml_lclMesgAddr_EN)
bml_lclMesgAddr <= `BSV_ASSIGNMENT_DELAY bml_lclMesgAddr_D_IN;
if (bml_lclMetaAddr_EN)
bml_lclMetaAddr <= `BSV_ASSIGNMENT_DELAY bml_lclMetaAddr_D_IN;
if (bml_remMesgAddr_EN)
bml_remMesgAddr <= `BSV_ASSIGNMENT_DELAY bml_remMesgAddr_D_IN;
if (bml_remMetaAddr_EN)
bml_remMetaAddr <= `BSV_ASSIGNMENT_DELAY bml_remMetaAddr_D_IN;
if (tlp_dmaPullRemainDWLen_EN)
tlp_dmaPullRemainDWLen <= `BSV_ASSIGNMENT_DELAY
tlp_dmaPullRemainDWLen_D_IN;
if (tlp_dmaPullRemainDWSub_EN)
tlp_dmaPullRemainDWSub <= `BSV_ASSIGNMENT_DELAY
tlp_dmaPullRemainDWSub_D_IN;
if (tlp_dmaReqTag_EN)
tlp_dmaReqTag <= `BSV_ASSIGNMENT_DELAY tlp_dmaReqTag_D_IN;
if (tlp_fabFlowAddr_EN)
tlp_fabFlowAddr <= `BSV_ASSIGNMENT_DELAY tlp_fabFlowAddr_D_IN;
if (tlp_fabFlowAddrMS_EN)
tlp_fabFlowAddrMS <= `BSV_ASSIGNMENT_DELAY tlp_fabFlowAddrMS_D_IN;
if (tlp_fabMesgAccu_EN)
tlp_fabMesgAccu <= `BSV_ASSIGNMENT_DELAY tlp_fabMesgAccu_D_IN;
if (tlp_fabMesgAddr_EN)
tlp_fabMesgAddr <= `BSV_ASSIGNMENT_DELAY tlp_fabMesgAddr_D_IN;
if (tlp_fabMesgAddrMS_EN)
tlp_fabMesgAddrMS <= `BSV_ASSIGNMENT_DELAY tlp_fabMesgAddrMS_D_IN;
if (tlp_fabMetaAddr_EN)
tlp_fabMetaAddr <= `BSV_ASSIGNMENT_DELAY tlp_fabMetaAddr_D_IN;
if (tlp_fabMetaAddrMS_EN)
tlp_fabMetaAddrMS <= `BSV_ASSIGNMENT_DELAY tlp_fabMetaAddrMS_D_IN;
if (tlp_inIgnorePkt_EN)
tlp_inIgnorePkt <= `BSV_ASSIGNMENT_DELAY tlp_inIgnorePkt_D_IN;
if (tlp_mesgComplReceived_EN)
tlp_mesgComplReceived <= `BSV_ASSIGNMENT_DELAY
tlp_mesgComplReceived_D_IN;
if (tlp_mesgLengthRemainPull_EN)
tlp_mesgLengthRemainPull <= `BSV_ASSIGNMENT_DELAY
tlp_mesgLengthRemainPull_D_IN;
if (tlp_mesgLengthRemainPush_EN)
tlp_mesgLengthRemainPush <= `BSV_ASSIGNMENT_DELAY
tlp_mesgLengthRemainPush_D_IN;
if (tlp_outDwRemain_EN)
tlp_outDwRemain <= `BSV_ASSIGNMENT_DELAY tlp_outDwRemain_D_IN;
if (tlp_remMesgAccu_EN)
tlp_remMesgAccu <= `BSV_ASSIGNMENT_DELAY tlp_remMesgAccu_D_IN;
if (tlp_remMesgAddr_EN)
tlp_remMesgAddr <= `BSV_ASSIGNMENT_DELAY tlp_remMesgAddr_D_IN;
if (tlp_remMetaAddr_EN)
tlp_remMetaAddr <= `BSV_ASSIGNMENT_DELAY tlp_remMetaAddr_D_IN;
if (tlp_srcMesgAccu_EN)
tlp_srcMesgAccu <= `BSV_ASSIGNMENT_DELAY tlp_srcMesgAccu_D_IN;
if (tlp_tlpBRAM_rdRespDwRemain_EN)
tlp_tlpBRAM_rdRespDwRemain <= `BSV_ASSIGNMENT_DELAY
tlp_tlpBRAM_rdRespDwRemain_D_IN;
if (tlp_tlpBRAM_readNxtDWAddr_EN)
tlp_tlpBRAM_readNxtDWAddr <= `BSV_ASSIGNMENT_DELAY
tlp_tlpBRAM_readNxtDWAddr_D_IN;
if (tlp_tlpBRAM_readRemainDWLen_EN)
tlp_tlpBRAM_readRemainDWLen <= `BSV_ASSIGNMENT_DELAY
tlp_tlpBRAM_readRemainDWLen_D_IN;
if (tlp_tlpBRAM_writeDWAddr_EN)
tlp_tlpBRAM_writeDWAddr <= `BSV_ASSIGNMENT_DELAY
tlp_tlpBRAM_writeDWAddr_D_IN;
if (tlp_tlpBRAM_writeLastBE_EN)
tlp_tlpBRAM_writeLastBE <= `BSV_ASSIGNMENT_DELAY
tlp_tlpBRAM_writeLastBE_D_IN;
if (tlp_tlpBRAM_writeRemainDWLen_EN)
tlp_tlpBRAM_writeRemainDWLen <= `BSV_ASSIGNMENT_DELAY
tlp_tlpBRAM_writeRemainDWLen_D_IN;
if (wmi_addr_EN) wmi_addr <= `BSV_ASSIGNMENT_DELAY wmi_addr_D_IN;
if (wmi_bytesRemainReq_EN)
wmi_bytesRemainReq <= `BSV_ASSIGNMENT_DELAY wmi_bytesRemainReq_D_IN;
if (wmi_lclMesgAddr_EN)
wmi_lclMesgAddr <= `BSV_ASSIGNMENT_DELAY wmi_lclMesgAddr_D_IN;
if (wmi_lclMetaAddr_EN)
wmi_lclMetaAddr <= `BSV_ASSIGNMENT_DELAY wmi_lclMetaAddr_D_IN;
if (wmi_wmi_statusR_EN)
wmi_wmi_statusR <= `BSV_ASSIGNMENT_DELAY wmi_wmi_statusR_D_IN;
end
always@(posedge CLK or `BSV_RESET_EDGE RST_N)
if (RST_N == `BSV_RESET_VALUE)
begin
wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmi_wmi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wti_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wci_isReset_isInReset_EN)
wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_isReset_isInReset_D_IN;
if (wmi_wmi_isReset_isInReset_EN)
wmi_wmi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_isReset_isInReset_D_IN;
if (wti_isReset_isInReset_EN)
wti_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wti_isReset_isInReset_D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
bml_crdBuf_modulus = 16'hAAAA;
bml_crdBuf_value = 16'hAAAA;
bml_datumAReg = 1'h0;
bml_fabAvail = 1'h0;
bml_fabBuf_modulus = 16'hAAAA;
bml_fabBuf_value = 16'hAAAA;
bml_fabBufsAvail = 16'hAAAA;
bml_fabDone = 1'h0;
bml_fabFlowAddr = 32'hAAAAAAAA;
bml_fabFlowBase = 32'hAAAAAAAA;
bml_fabFlowBaseMS = 32'hAAAAAAAA;
bml_fabFlowSize = 32'hAAAAAAAA;
bml_fabMesgAddr = 32'hAAAAAAAA;
bml_fabMesgBase = 32'hAAAAAAAA;
bml_fabMesgBaseMS = 32'hAAAAAAAA;
bml_fabMesgSize = 32'hAAAAAAAA;
bml_fabMetaAddr = 32'hAAAAAAAA;
bml_fabMetaBase = 32'hAAAAAAAA;
bml_fabMetaBaseMS = 32'hAAAAAAAA;
bml_fabMetaSize = 32'hAAAAAAAA;
bml_fabNumBufs = 16'hAAAA;
bml_lclBufDone = 1'h0;
bml_lclBufStart = 1'h0;
bml_lclBuf_modulus = 16'hAAAA;
bml_lclBuf_value = 16'hAAAA;
bml_lclBufsAR = 16'hAAAA;
bml_lclBufsCF = 16'hAAAA;
bml_lclCredit = 16'hAAAA;
bml_lclDones = 16'hAAAA;
bml_lclMesgAddr = 16'hAAAA;
bml_lclMetaAddr = 16'hAAAA;
bml_lclNumBufs = 16'hAAAA;
bml_lclStarts = 16'hAAAA;
bml_mesgBase = 16'hAAAA;
bml_mesgSize = 16'hAAAA;
bml_metaBase = 16'hAAAA;
bml_metaSize = 16'hAAAA;
bml_remBuf_modulus = 16'hAAAA;
bml_remBuf_value = 16'hAAAA;
bml_remDone = 1'h0;
bml_remDones = 16'hAAAA;
bml_remMesgAddr = 16'hAAAA;
bml_remMetaAddr = 16'hAAAA;
bml_remStart = 1'h0;
bml_remStarts = 16'hAAAA;
bram_0_serverAdapterA_cnt = 3'h2;
bram_0_serverAdapterA_s1 = 2'h2;
bram_0_serverAdapterB_cnt = 3'h2;
bram_0_serverAdapterB_s1 = 2'h2;
bram_1_serverAdapterA_cnt = 3'h2;
bram_1_serverAdapterA_s1 = 2'h2;
bram_1_serverAdapterB_cnt = 3'h2;
bram_1_serverAdapterB_s1 = 2'h2;
bram_2_serverAdapterA_cnt = 3'h2;
bram_2_serverAdapterA_s1 = 2'h2;
bram_2_serverAdapterB_cnt = 3'h2;
bram_2_serverAdapterB_s1 = 2'h2;
bram_3_serverAdapterA_cnt = 3'h2;
bram_3_serverAdapterA_s1 = 2'h2;
bram_3_serverAdapterB_cnt = 3'h2;
bram_3_serverAdapterB_s1 = 2'h2;
dmaDoneTime = 64'hAAAAAAAAAAAAAAAA;
dmaStartTime = 64'hAAAAAAAAAAAAAAAA;
dpControl = 8'hAA;
tlp_complTimerCount = 12'hAAA;
tlp_complTimerRunning = 1'h0;
tlp_creditReady = 1'h0;
tlp_dmaDoTailEvent = 1'h0;
tlp_dmaDoneMark = 1'h0;
tlp_dmaPullRemainDWLen = 10'h2AA;
tlp_dmaPullRemainDWSub = 10'h2AA;
tlp_dmaReqTag = 5'h0A;
tlp_dmaStartMark = 1'h0;
tlp_dmaTag = 5'h0A;
tlp_doXmtMetaBody = 1'h0;
tlp_doorSeqDwell = 4'hA;
tlp_fabFlowAddr = 32'hAAAAAAAA;
tlp_fabFlowAddrMS = 32'hAAAAAAAA;
tlp_fabMesgAccu = 32'hAAAAAAAA;
tlp_fabMesgAddr = 32'hAAAAAAAA;
tlp_fabMesgAddrMS = 32'hAAAAAAAA;
tlp_fabMeta = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
tlp_fabMetaAddr = 32'hAAAAAAAA;
tlp_fabMetaAddrMS = 32'hAAAAAAAA;
tlp_farBufReady = 1'h0;
tlp_flowDiagCount = 32'hAAAAAAAA;
tlp_gotResponseHeader = 1'h0;
tlp_inIgnorePkt = 1'h0;
tlp_lastMetaV_0 = 32'hAAAAAAAA;
tlp_lastMetaV_1 = 32'hAAAAAAAA;
tlp_lastMetaV_2 = 32'hAAAAAAAA;
tlp_lastMetaV_3 = 32'hAAAAAAAA;
tlp_lastRuleFired = 4'hA;
tlp_maxPayloadSize = 13'h0AAA;
tlp_maxReadReqSize = 13'h0AAA;
tlp_mesgComplReceived = 17'h0AAAA;
tlp_mesgLengthRemainPull = 17'h0AAAA;
tlp_mesgLengthRemainPush = 17'h0AAAA;
tlp_nearBufReady = 1'h0;
tlp_outDwRemain = 10'h2AA;
tlp_postSeqDwell = 4'hA;
tlp_pullTagMatch = 1'h0;
tlp_remDone = 1'h0;
tlp_remMesgAccu = 16'hAAAA;
tlp_remMesgAddr = 16'hAAAA;
tlp_remMetaAddr = 16'hAAAA;
tlp_remStart = 1'h0;
tlp_reqMesgInFlight = 1'h0;
tlp_reqMetaBodyInFlight = 1'h0;
tlp_reqMetaInFlight = 1'h0;
tlp_sentTail4DWHeader = 1'h0;
tlp_srcMesgAccu = 32'hAAAAAAAA;
tlp_tlpBRAM_debugBdata = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
tlp_tlpBRAM_rdRespDwRemain = 10'h2AA;
tlp_tlpBRAM_readHeaderSent = 1'h0;
tlp_tlpBRAM_readNxtDWAddr = 13'h0AAA;
tlp_tlpBRAM_readRemainDWLen = 10'h2AA;
tlp_tlpBRAM_readStarted = 1'h0;
tlp_tlpBRAM_writeDWAddr = 13'h0AAA;
tlp_tlpBRAM_writeLastBE = 4'hA;
tlp_tlpBRAM_writeRemainDWLen = 10'h2AA;
tlp_tlpMetaSent = 1'h0;
tlp_tlpRcvBusy = 1'h0;
tlp_tlpXmtBusy = 1'h0;
tlp_xmtMetaInFlight = 1'h0;
tlp_xmtMetaOK = 1'h0;
wci_cEdge = 3'h2;
wci_cState = 3'h2;
wci_ctlAckReg = 1'h0;
wci_ctlOpActive = 1'h0;
wci_illegalEdge = 1'h0;
wci_isReset_isInReset = 1'h0;
wci_nState = 3'h2;
wci_reqF_countReg = 2'h2;
wci_respF_cntr_r = 2'h2;
wci_respF_q_0 = 34'h2AAAAAAAA;
wci_respF_q_1 = 34'h2AAAAAAAA;
wci_sFlagReg = 1'h0;
wci_sThreadBusy_d = 1'h0;
wmi_addr = 14'h2AAA;
wmi_bufDwell = 2'h2;
wmi_bytesRemainReq = 14'h2AAA;
wmi_bytesRemainResp = 14'h2AAA;
wmi_doneWithMesg = 1'h0;
wmi_lastMesg = 32'hAAAAAAAA;
wmi_lclMesgAddr = 15'h2AAA;
wmi_lclMetaAddr = 15'h2AAA;
wmi_mesgBufReady = 1'h0;
wmi_mesgBusy = 1'h0;
wmi_mesgCount = 32'hAAAAAAAA;
wmi_mesgDone = 1'h0;
wmi_mesgMeta = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmi_mesgStart = 1'h0;
wmi_metaBusy = 1'h0;
wmi_p4B = 2'h2;
wmi_rdActive = 1'h0;
wmi_reqCount = 16'hAAAA;
wmi_thisMesg = 32'hAAAAAAAA;
wmi_wmi_blockReq = 1'h0;
wmi_wmi_dhF_countReg = 2'h2;
wmi_wmi_dhF_levelsValid = 1'h0;
wmi_wmi_errorSticky = 1'h0;
wmi_wmi_isReset_isInReset = 1'h0;
wmi_wmi_mFlagF_countReg = 2'h2;
wmi_wmi_mFlagF_levelsValid = 1'h0;
wmi_wmi_operateD = 1'h0;
wmi_wmi_peerIsReady = 1'h0;
wmi_wmi_reqF_countReg = 2'h2;
wmi_wmi_reqF_levelsValid = 1'h0;
wmi_wmi_respF_cntr_r = 2'h2;
wmi_wmi_respF_q_0 = 130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmi_wmi_respF_q_1 = 130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmi_wmi_sFlagReg = 32'hAAAAAAAA;
wmi_wmi_statusR = 8'hAA;
wmi_wmi_trafficSticky = 1'h0;
wmi_wrActive = 1'h0;
wmi_wrFinalize = 1'h0;
wmi_wrtCount = 16'hAAAA;
wti_isReset_isInReset = 1'h0;
wti_nowReq = 67'h2AAAAAAAAAAAAAAAA;
wti_operateD = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (bram_0_serverAdapterA_s1[1] &&
!bram_0_serverAdapterA_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N != `BSV_RESET_VALUE)
if (bram_0_serverAdapterB_s1[1] &&
!bram_0_serverAdapterB_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N != `BSV_RESET_VALUE)
if (bram_1_serverAdapterA_s1[1] &&
!bram_1_serverAdapterA_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N != `BSV_RESET_VALUE)
if (bram_1_serverAdapterB_s1[1] &&
!bram_1_serverAdapterB_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N != `BSV_RESET_VALUE)
if (bram_2_serverAdapterA_s1[1] &&
!bram_2_serverAdapterA_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N != `BSV_RESET_VALUE)
if (bram_2_serverAdapterB_s1[1] &&
!bram_2_serverAdapterB_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N != `BSV_RESET_VALUE)
if (bram_3_serverAdapterA_s1[1] &&
!bram_3_serverAdapterA_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N != `BSV_RESET_VALUE)
if (bram_3_serverAdapterB_s1[1] &&
!bram_3_serverAdapterB_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
begin
v__h91963 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
$display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x",
v__h91963,
wci_reqF_D_OUT[63:32],
wci_reqF_D_OUT[67:64],
_theResult____h91947);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_start)
begin
v__h15577 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h15577,
wci_reqF_D_OUT[36:34],
wci_cState);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaRequestNearMeta)
begin
v__h41005 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaRequestNearMeta)
$display("[%0d]: %m: dmaRequestNearMeta FPactMesg-Step1/7",
v__h41005);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPushRequestMesg)
begin
v__h47790 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPushRequestMesg)
$display("[%0d]: %m: dmaPushRequestMesg FPactMesg-Step3/7",
v__h47790);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaResponseNearMetaHead)
begin
v__h43090 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaResponseNearMetaHead)
$display("[%0d]: %m: dmaResponseNearMetaHead FPactMesg-Step2a/7 mesgLength:%0x",
v__h43090,
x__h42208);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPushResponseHeader)
begin
v__h48409 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPushResponseHeader)
$display("[%0d]: %m: dmaPushResponseHeader FPactMesg-Step4a/7",
v__h48409);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPushResponseBody)
begin
v__h48757 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPushResponseBody)
$display("[%0d]: %m: dmaPushResponseBody FPactMesg-Step4b/7",
v__h48757);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaXmtMetaHead)
begin
v__h50007 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaXmtMetaHead)
$display("[%0d]: %m: dmaXmtMetaHead FPactMesg-Step5/7", v__h50007);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaXmtTailEvent)
begin
v__h56506 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaXmtTailEvent)
$display("[%0d]: %m: dmaXmtTailEvent FPactMesg-Step7/7", v__h56506);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaXmtMetaBody)
begin
v__h56382 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaXmtMetaBody)
$display("[%0d]: %m: dmaXmtMetaBody FPactMesg-Step6/7", v__h56382);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaXmtDoorbell)
begin
v__h56714 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaXmtDoorbell)
$display("[%0d]: %m: dmaXmtDoorbell FC/FPactFlow-Step1/1", v__h56714);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaRespHeadFarMeta)
begin
v__h59442 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaRespHeadFarMeta)
$display("[%0d]: %m: dmaRespHeadFarMeta FPactMesg-Step2a/N fabMeta:%0x",
v__h59442,
x__h58352);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPullTailEvent)
begin
v__h65522 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPullTailEvent)
$display("[%0d]: %m: dmaPullTailEvent FPactMesg-Step5/5", v__h65522);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaRespBodyFarMeta)
begin
v__h63835 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaRespBodyFarMeta)
$display("[%0d]: %m: dmaRespBodyFarMeta FPactMesg-Step2b/N opcode:%0x nowMS:%0x nowLS:%0x",
v__h63835,
opcode__h60417,
nowMS__h61665,
nowLS__h62622);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPullResponseHeader)
begin
v__h65011 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPullResponseHeader)
$display("[%0d]: %m: dmaPullResponseHeader FPactMesg-Step4a/5",
v__h65011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPullResponseBody)
begin
v__h65359 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPullResponseBody)
$display("[%0d]: %m: dmaPullResponseBody FPactMesg-Step4b/5",
v__h65359);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaTailEventSender)
begin
v__h70765 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaTailEventSender)
$display("[%0d]: %m: dmaTailEventSender - generic", v__h70765);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaResponseNearMetaBody)
begin
v__h47450 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaResponseNearMetaBody)
$display("[%0d]: %m: dmaResponseNearMetaBody FPactMesg-Step2b/7 opcode:%0x nowMS:%0x nowLS:%0x",
v__h47450,
opcode__h44022,
nowMS__h45280,
nowLS__h46239);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaRequestFarMeta)
begin
v__h57177 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaRequestFarMeta)
$display("[%0d]: %m: dmaRequestFarMeta FCactMesg-Step1/5", v__h57177);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPullRequestFarMesg)
begin
v__h64356 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPullRequestFarMesg)
$display("[%0d]: %m: dmaPullRequestFarMesg FCactMesg-Step3/5",
v__h64356);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wmi_doWriteFinalize)
begin
v__h82455 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wmi_doWriteFinalize)
$display("[%0d]: %m: doWriteFinalize lclMetaAddr :%0x length:%0x opcode:%0x nowMS:%0x nowLS:%0x ",
v__h82455,
wmi_lclMetaAddr,
x3__h81813,
mesgMeta_opcode__h81853,
dmaStartTime_D_IN[63:32],
dmaStartTime_D_IN[31:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h18)
begin
v__h91331 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h18)
$display("[%0d] %m: fabDoneAvail Event", v__h91331);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
begin
v__h91800 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
$display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
v__h91800,
wci_reqF_D_OUT[63:32],
wci_reqF_D_OUT[67:64],
wci_reqF_D_OUT[31:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/inf/OCDP.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
begin
v__h15896 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h15896,
wci_cEdge,
wci_cState);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
begin
v__h15752 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h15752,
wci_cEdge,
wci_cState,
wci_nState);
end
// synopsys translate_on
endmodule // mkOCDP16B
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKBUF_BLACKBOX_V
`define SKY130_FD_SC_MS__CLKBUF_BLACKBOX_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKBUF_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:40:07 08/24/2014
// Design Name:
// Module Name: Top_N3_Computer_IOBUS_VGA_PS2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "wb_conbus_defines.v"
//`define dw 32 // Data bus Width
//`define aw 32 // Address bus Width
//`define sw `dw / 8 // Number of Select Lines
module Top_N3_Computer_IOBUS_VGA_PS2(
clk_100mhz,
BTN,
// I/O:
SW,
LED,
SEGMENT,
AN_SEL,
PS2_clk, PS2_Data,
Red,
Green,
Blue,
HSYNC,
VSYNC,
uart_rx,
uart_tx
);
//for wb input and output ---------------------------------------------------
// Master 0 Interface
wire [`dw-1:0] m0_dat_i;
wire [`dw-1:0] m0_dat_o;
wire [`aw-1:0] m0_adr_i;
wire [`sw-1:0] m0_sel_i;
wire m0_we_i;
wire m0_stb_i;
wire m0_ack_o;
// Master 1 Interface
wire [`dw-1:0] m1_dat_i;
wire [`dw-1:0] m1_dat_o;
wire [`aw-1:0] m1_adr_i;
wire [`sw-1:0] m1_sel_i;
wire m1_we_i;
wire m1_stb_i;
wire m1_ack_o;
// Slave 0 Interface
wire [`dw-1:0] s0_dat_i;
wire [`dw-1:0] s0_dat_o;
wire [`aw-1:0] s0_adr_o;
wire [`sw-1:0] s0_sel_o;
wire s0_we_o;
wire s0_stb_o;
wire s0_ack_i;
// Slave 1 Interface
wire [`dw-1:0] s1_dat_i;
wire [`dw-1:0] s1_dat_o;
wire [`aw-1:0] s1_adr_o;
wire [`sw-1:0] s1_sel_o;
wire s1_we_o;
wire s1_stb_o;
wire s1_ack_i;
// Slave 2 Interface
wire [`dw-1:0] s2_dat_i;
wire [`dw-1:0] s2_dat_o;
wire [`aw-1:0] s2_adr_o;
wire [`sw-1:0] s2_sel_o;
wire s2_we_o;
wire s2_stb_o;
wire s2_ack_i;
// Slave 3 Interface
wire [`dw-1:0] s3_dat_i;
wire [`dw-1:0] s3_dat_o;
wire [`aw-1:0] s3_adr_o;
wire [`sw-1:0] s3_sel_o;
wire s3_we_o;
wire s3_stb_o;
wire s3_ack_i;
// Slave 4 Interface
wire [`dw-1:0] s4_dat_i;
wire [`dw-1:0] s4_dat_o;
wire [`aw-1:0] s4_adr_o;
wire [`sw-1:0] s4_sel_o;
wire s4_we_o;
wire s4_stb_o;
wire s4_ack_i;
// Slave 5 Interface
wire [`dw-1:0] s5_dat_i;
wire [`dw-1:0] s5_dat_o;
wire [`aw-1:0] s5_adr_o;
wire [`sw-1:0] s5_sel_o;
wire s5_we_o;
wire s5_stb_o;
wire s5_ack_i;
// Slave 6 Interface
wire [`dw-1:0] s6_dat_i;
wire [`dw-1:0] s6_dat_o;
wire [`aw-1:0] s6_adr_o;
wire [`sw-1:0] s6_sel_o;
wire s6_we_o;
wire s6_stb_o;
wire s6_ack_i;
// Slave 7 Interface
wire [`dw-1:0] s7_dat_i;
wire [`dw-1:0] s7_dat_o;
wire [`aw-1:0] s7_adr_o;
wire [`sw-1:0] s7_sel_o;
wire s7_we_o;
wire s7_stb_o;
wire s7_ack_i;
//----------------------------------------------------------
input clk_100mhz;
input PS2_clk, PS2_Data;
input [ 3: 0] BTN;
input [ 7: 0] SW;
input uart_rx;
output [ 7: 0] LED, SEGMENT;
output [ 3: 0] AN_SEL;
output [ 2: 0] Red, Green;
output [ 1: 0] Blue;
output HSYNC, VSYNC;
output uart_tx;
// Variable Declarations
wire Clk_CPU, rst,clk_m, mem_w, data_ram_we, GPIOfffffe00_we, GPIOffffff00_we, counter_we;
wire counter_OUT0, counter_OUT1, counter_OUT2;
wire [ 1: 0] Counter_set;
wire [ 4: 0] state;
wire [ 3: 0] digit_anode, blinke;
wire [ 3: 0] button_out;
wire [ 7: 0] SW_OK, SW, ps2_key, led_out, LED, SEGMENT; //led_out is current LED light
wire [11: 0] ram_addr;
wire [21: 0] GPIOf0;
wire [31: 0] pc, Inst, cpu_addr, Cpu_data2bus, ram_data_out, disp_num;
wire [31: 0] clkdiv, Cpu_data4bus, counter_out, ram_data_in, Peripheral_in;
wire [31: 0] vram_out, vram_data_in;
wire [10: 0] vram_addr, vga_addr;
wire MIO_ready;
wire CPU_MIO, vga_rdn;
wire [31: 0] key_d;
wire [ 7: 0] key;
reg key_ready;
// assign MIO_ready=~button_out[1];
// Variables for Interruppt
wire [31: 0] intrrupt_en;
wire [ 3: 0] gntInt;
wire Iack, Ireq; // CPU Interrupt signals
wire rx_irq, rx_iack, ps2_irq, ps2_iack, // Devices INT signals
timer_irq, timer_iack;
//assign rst=button_out[3];
assign rst = BTN[3];
assign SW2 = SW_OK[2];
assign LED = {led_out[7] | Clk_CPU, led_out[ 6: 0]};
assign clk_m = clk_100mhz; // ;~Clk_CPU
assign AN_SEL = digit_anode;
assign clk_io = ~Clk_CPU; // ~Clk_CPU; ~clk_100mhz
wire [12:0] Cursor = GPIOf0[12: 0];
wire text_Cursor_switch = GPIOf0[21]; // Disable Text Cursor
BUFG VGA_CLOCK_BUF(.O(VGA_clk), .I(clkdiv[1]));
// BUFG Key_CLOCK_BUF(.O(Key_clk), .I(clkdiv[2]));
seven_seg U6(
.disp_num (disp_num),
.clk (clk_100mhz),
.clr (rst),
.SW (SW_OK[ 1: 0]),
.Scanning (clkdiv[19:18]),
.SEGMENT (SEGMENT),
.AN (digit_anode)
);
BTN_Anti_jitter U9(
clk_100mhz,
BTN,
SW,
button_out,
SW_OK
);
clk_div U8(
clk_100mhz,
rst,
SW2,
clkdiv,
Clk_CPU
); // Clock divider-
//++++++++++++++++++++++muliti_cycle_cpu+++++++++++++++++++++++++++++++++++++++++++
Muliti_cycle_Cpu U1(
.clk (Clk_CPU),
.reset (rst),
.MIO_ready (m0_ack_o), // MIO_ready
// Internal signals:
.pc_out (pc), // Test
.Inst (Inst), // Test
//.mem_w (mem_w),
.mem_w (m0_we_i),
.cpu_stb_o (m0_stb_i),
//
.sel_o (m0_sel_i),
//.Addr_out (cpu_addr),
.Addr_out (m0_adr_i),
//.data_out (Cpu_data2bus),
.data_out (m0_dat_i),
//.data_in (Cpu_data4bus),
.data_in (m0_dat_o),
// Interrupt Interface
.Ireq (Ireq),
.gntInt (gntInt),
.Iack (Iack),
.intrrupt_en_o (intrrupt_en),
// .Half_W (Half_W),
.Signext (Signext),
.CPU_MIO (CPU_MIO), // not in use
.state (state) // Test
);
// data RAM (2048 * 32)
Mem_I_D U2(
//wb_input
.dat_i (s2_dat_o),
.adr_i (s2_adr_o),
.we_i (s2_we_o),
.stb_i (s2_stb_o),
.sel_i (s2_sel_o),
//wb_output
.dat_o (s2_dat_i),
.ack_o (s2_ack_i),
//.Half_W (Half_W),
.Signext (Signext),
.clk (clk_m)
// .W_En (data_ram_we),
// .Addr (ram_addr),
// .D_In (ram_data_in),
// .D_Out (ram_data_out)
); // Addre_Bus [9 : 0] ,Data_Bus [31 : 0]
// VRAM (4800 * 11)
Vram_B U3(
//wb_input
.dat_i (s1_dat_o),
.adr_i (s1_adr_o),
.we_i (s1_we_o),
.stb_i (s1_stb_o),
//wb_output
.dat_o (s1_dat_i),
.ack_o (s1_ack_i),
.vga_addr (vga_addr),
.vga_dout (vram_out),
.clk (clk_m)
// .W_En (vram_we),
// .Addr (vram_addr),
// .D_In (vram_data_in),
// .D_Out (vram_out)
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
wb_conbus_top UU4(
.clk_i(clk_100mhz), .rst_i(rst),
// Master 0 Interface
.m0_dat_i(m0_dat_i), .m0_dat_o(m0_dat_o), .m0_adr_i(m0_adr_i), .m0_sel_i(m0_sel_i), .m0_we_i(m0_we_i),
.m0_stb_i(m0_stb_i), .m0_ack_o(m0_ack_o),
// Master 1 Interface
.m1_dat_i(m1_dat_i), .m1_dat_o(m1_dat_o), .m1_adr_i(m1_adr_i), .m1_sel_i(m1_sel_i), .m1_we_i(m1_we_i),
.m1_stb_i(m1_stb_i), .m1_ack_o(m1_ack_o),
// Slave 0 Interface
.s0_dat_i(s0_dat_i), .s0_dat_o(s0_dat_o), .s0_adr_o(s0_adr_o), .s0_sel_o(s0_sel_o), .s0_we_o(s0_we_o),
.s0_stb_o(s0_stb_o), .s0_ack_i(s0_ack_i),
// Slave 1 Interface
.s1_dat_i(s1_dat_i), .s1_dat_o(s1_dat_o), .s1_adr_o(s1_adr_o), .s1_sel_o(s1_sel_o), .s1_we_o(s1_we_o),
.s1_stb_o(s1_stb_o), .s1_ack_i(s1_ack_i),
// Slave 2 Interface
.s2_dat_i(s2_dat_i), .s2_dat_o(s2_dat_o), .s2_adr_o(s2_adr_o), .s2_sel_o(s2_sel_o), .s2_we_o(s2_we_o),
.s2_stb_o(s2_stb_o), .s2_ack_i(s2_ack_i),
// Slave 3 Interface
.s3_dat_i(s3_dat_i), .s3_dat_o(s3_dat_o), .s3_adr_o(s3_adr_o), .s3_sel_o(s3_sel_o), .s3_we_o(s3_we_o),
.s3_stb_o(s3_stb_o), .s3_ack_i(s3_ack_i),
// Slave 4 Interface
.s4_dat_i(s4_dat_i), .s4_dat_o(s4_dat_o), .s4_adr_o(s4_adr_o), .s4_sel_o(s4_sel_o), .s4_we_o(s4_we_o),
.s4_stb_o(s4_stb_o), .s4_ack_i(s4_ack_i),
// Slave 5 Interface
.s5_dat_i(s5_dat_i), .s5_dat_o(s5_dat_o), .s5_adr_o(s5_adr_o), .s5_sel_o(s5_sel_o), .s5_we_o(s5_we_o),
.s5_stb_o(s5_stb_o), .s5_ack_i(s5_ack_i),
// Slave 6 Interface
.s6_dat_i(s6_dat_i), .s6_dat_o(s6_dat_o), .s6_adr_o(s6_adr_o), .s6_sel_o(s6_sel_o), .s6_we_o(s6_we_o),
.s6_stb_o(s6_stb_o), .s6_ack_i(s6_ack_i),
// Slave 7 Interface
.s7_dat_i(s7_dat_i), .s7_dat_o(s7_dat_o), .s7_adr_o(s7_adr_o), .s7_sel_o(s7_sel_o), .s7_we_o(s7_we_o),
.s7_stb_o(s7_stb_o), .s7_ack_i(s7_ack_i)
//for MIO_BUS
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
MIO_BUS U4(
//wb_input
.dat_i (s3_dat_o),
.adr_i (s3_adr_o),
.we_i (s3_we_o),
.stb_i (s3_stb_o),
//wb_output
.dat_o (s3_dat_i),
.ack_o (s3_ack_i),
.clk (clk_100mhz),
.rst (rst),
.BTN (button_out),
.SW (SW_OK),
//.vga_rdn (vga_rdn), //
//.ps2_ready (ps2_ready),
//.mem_w (mem_w),
//.key (key),
//.Cpu_data2bus (Cpu_data2bus), // Data from CPU
//.addr_bus (cpu_addr),
//.vga_addr (vga_addr),
//.ram_data_out (ram_data_out),
//.vram_out (vram_out),
.led_out (led_out),
.counter_out (counter_out),
.counter0_out (counter_OUT0),
.counter1_out (counter_OUT1),
.counter2_out (counter_OUT2),
//.CPU_wait (MIO_ready),
//.Cpu_data4bus (Cpu_data4bus), // Data write to CPU
//.ram_data_in (ram_data_in), // From CPU write to Memory
//.ram_addr (ram_addr), // Memory Address signals
//.vram_data_in (vram_data_in), // From CPU write to Vram Memory
//.vram_addr (vram_addr), // Vram Address signals
//.data_ram_we (data_ram_we),
//.vram_we (vram_we),
.GPIOffffff00_we (GPIOffffff00_we),
.GPIOfffffe00_we (GPIOfffffe00_we),
.counter_we (counter_we),
//.ps2_rd (ps2_rd),
.Peripheral_in (Peripheral_in)
);
//------Peripheral Driver-----------------------------------
/* GPIO out use on LEDs & Counter-Controler read and write addre=f0000000-ffffffff0
*/
Device_GPIO_led U7(
clk_io,
rst,
GPIOffffff00_we,
Peripheral_in,
Counter_set,
led_out,
GPIOf0
);
/* GPIO out use on 7-seg display & CPU state display addre=e0000000-efffffff */
Device_GPIO_7seg U14(
.clk (clk_io),
.rst (rst),
.GPIOfffffe00_we (GPIOfffffe00_we),
.Test (SW_OK[7:5]),
.disp_cpudata (Peripheral_in), // CPU data output
.Test_data0 (pc), // pc[31:2]
.Test_data1 (counter_out), // counter
.Test_data2 (Inst), // Inst
.Test_data3 (cpu_addr), // cpu_addr
.Test_data4 (m0_dat_i), // Cpu_data2bus;
.Test_data5 (m0_dat_o), // Cpu_data4bus;
.Test_data6 ({ps2_ready, 15'h0, ps2_key, key}),
//pc;
.disp_num (disp_num)
);
irq_controller U15(
.clk_i (clk_100mhz),
.rst_i (rst),
.intrrupt_en (intrrupt_en[0]),
.i_gnt_arb (gntInt), // granted Device, 0001 for d0(uart)
.m0_Iack_i (Iack),
.m0_irq_o (Ireq),
.d0_irq_i (rx_irq), // uart(disk)
.d0_Iack_o (rx_iack),
.d1_irq_i (ps2_irq), // ps2
.d1_Iack_o (ps2_iack),
.d2_irq_i (0), // timer
.d2_Iack_o (timer_iack),
.d3_irq_i (0), // not in use
.d3_Iack_o ()
);
Counter_x U10(
.clk (clk_io),
.rst (rst),
.clk0 (clkdiv[9]),
.clk1 (clkdiv[10]),
.clk2 (clkdiv[10]),
.counter_we (counter_we),
.counter_val (Peripheral_in),
.counter_ch (Counter_set),
.counter0_OUT (counter_OUT0),
.counter1_OUT (counter_OUT1),
.counter2_OUT (counter_OUT2),
.counter_out (counter_out)
);
/* VGA IO use on display More Information with Text & Graph addre= */
VGA_IO U11(
.vga_clk (VGA_clk),
.rst (rst),
.vram_out (vram_out),
.text_Cursor_switch (text_Cursor_switch),
.Cursor (Cursor),
.Blink (clkdiv[24]),
.R (Red),
.G (Green),
.B (Blue),
.HSYNC (HSYNC),
.VSYNC (VSYNC),
.vga_addr (vga_addr),
.vga_rdn (vga_rdn)
);
// latch the input key from PS/2 module when ps2_ready signals is asserted,
// note that the key here is still a scan code, and software needs to transform it into a ASCII code
assign io_read_clk = Clk_CPU;
PS2_IO U12(
//wb_input
.dat_i (s4_dat_o),
.adr_i (s4_adr_o),
.we_i (s4_we_o),
.stb_i (s4_stb_o),
//wb_output
.dat_o (s4_dat_i),
.ack_o (s4_ack_i),
.io_read_clk (io_read_clk),
.clk_ps2 (clkdiv[0]),
.rst (rst),
.PS2_clk (PS2_clk),
.PS2_Data (PS2_Data),
//.ps2_rd (ps2_rd),
.ps2_ready (ps2_ready),
.ps2_irq (ps2_irq),
.ps2_iack (ps2_iack),
.key_d (key_d),
.key (key),
.ps2_key (ps2_key)
);
uart U13(
//wb_input
.dat_i (s0_dat_o),
.adr_i (s0_adr_o),
.we_i (s0_we_o),
.stb_i (s0_stb_o),
//wb_output
.dat_o (s0_dat_i),
.ack_o (s0_ack_i),
.sys_clk (clk_m),
.sys_rst (rst),
.rx_irq (rx_irq),
.rx_iack (rx_iack),
.tx_irq (),
.uart_rx (uart_rx),
.uart_tx (uart_tx)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4_SYMBOL_V
`define SKY130_FD_SC_HDLL__OR4_SYMBOL_V
/**
* or4: 4-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DFXBP_FUNCTIONAL_PP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXBP_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2AI_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__O2BB2AI_PP_SYMBOL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o2bb2ai (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2AI_PP_SYMBOL_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: DE5Gen1x8If64
// Version:
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
// the Altera Stratix V Hard IP for PCI Express
// module and the Terasic DE5 net Development Board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "functions.vh"
`include "riffa.vh"
`include "altera.vh"
`timescale 1ps / 1ps
module DE5Gen1x8If64
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes
parameter C_NUM_LANES = 8,
// Settings from Quartus IP Library
parameter C_PCI_DATA_WIDTH = 64,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5
)
(
// ----------LEDs----------
output [7:0] LED,
// ----------PCIE----------
input PCIE_RESET_N,
input PCIE_REFCLK,
// ----------PCIE Serial RX----------
input [C_NUM_LANES-1:0] PCIE_RX_IN,
// ----------PCIE Serial TX----------
output [C_NUM_LANES-1:0] PCIE_TX_OUT,
// ----------Oscillators----------
input OSC_BANK3D_50MHZ
);
wire npor;
wire pin_perst;
// ----------LMI Interface----------
wire [11:0] lmi_addr;
wire [31:0] lmi_din;
wire lmi_rden;
wire lmi_wren;
wire lmi_ack;
wire [31:0] lmi_dout;
// ----------TL Config interface----------
wire [3:0] tl_cfg_add;
wire [31:0] tl_cfg_ctl;
wire [52:0] tl_cfg_sts;
// ----------Rx/TX Interfaces----------
wire [0:0] rx_st_sop;
wire [0:0] rx_st_eop;
wire [0:0] rx_st_err;
wire [0:0] rx_st_valid;
wire [0:0] rx_st_empty;
wire rx_st_ready;
wire [63:0] rx_st_data;
wire [7:0] rx_st_bar;
wire rx_st_mask;
wire [0:0] tx_st_sop;
wire [0:0] tx_st_eop;
wire [0:0] tx_st_err;
wire [0:0] tx_st_valid;
wire [0:0] tx_st_empty;
wire tx_st_ready;
wire [63:0] tx_st_data;
// ----------Clocks----------
wire pld_clk;
wire coreclkout_hip;
wire refclk;
wire pld_core_ready;
wire reset_status;
wire serdes_pll_locked;
wire pld_clk_inuse;
// ----------Reconfiguration busses----------
wire [699:0] reconfig_to_xcvr;
wire [505:0] reconfig_from_xcvr;
// ----------Interrupt Interfaces----------
wire app_int_sts;
wire [4:0] app_msi_num;
wire app_msi_req;
wire [2:0] app_msi_tc;
wire app_int_ack;
wire app_msi_ack;
// ----------Link status signals----------
wire derr_cor_ext_rcv;
wire derr_cor_ext_rpl;
wire derr_rpl;
wire dlup;
wire dlup_exit;
wire ev128ns;
wire ev1us;
wire hotrst_exit;
wire [3:0] int_status;
wire l2_exit;
wire [3:0] lane_act;
wire [4:0] ltssmstate;
wire rx_par_err;
wire [1:0] tx_par_err;
wire cfg_par_err;
wire [1:0] currentspeed;
wire [7:0] ko_cpl_spc_header;
wire [11:0] ko_cpl_spc_data;
// ----------Link Status Signals (Driver)----------
wire derr_cor_ext_rcv_drv;
wire derr_cor_ext_rpl_drv;
wire derr_rpl_drv;
wire dlup_drv;
wire dlup_exit_drv;
wire ev128ns_drv;
wire ev1us_drv;
wire hotrst_exit_drv;
wire [3:0] int_status_drv;
wire l2_exit_drv;
wire [3:0] lane_act_drv;
wire [4:0] ltssmstate_drv;
wire rx_par_err_drv;
wire [1:0] tx_par_err_drv;
wire cfg_par_err_drv;
wire [7:0] ko_cpl_spc_header_drv;
wire [11:0] ko_cpl_spc_data_drv;
// ----------Reconfiguration Controller signals----------
wire reconfig_busy;
wire mgmt_clk_clk;
wire mgmt_rst_reset;
wire [6:0] reconfig_mgmt_address;
wire reconfig_mgmt_read;
wire [31:0] reconfig_mgmt_readdata;
wire reconfig_mgmt_waitrequest;
wire reconfig_mgmt_write;
wire [31:0] reconfig_mgmt_writedata;
// ----------Reconfiguration Driver signals----------
wire reconfig_xcvr_clk;
wire reconfig_xcvr_rst;
wire [7:0] rx_in;
wire [7:0] tx_out;
// ----------Serial interfaces----------
assign rx_in = PCIE_RX_IN;
assign PCIE_TX_OUT = tx_out;
// ----------Clocks----------
assign pld_clk = coreclkout_hip;
assign mgmt_clk_clk = PCIE_REFCLK;
assign reconfig_xcvr_clk = PCIE_REFCLK;
assign refclk = PCIE_REFCLK;
assign pld_core_ready = serdes_pll_locked;
// ----------Resets----------
assign reconfig_xcvr_rst = 1'b0;
assign mgmt_rst_reset = 1'b0;
assign pin_perst = PCIE_RESET_N;
assign npor = PCIE_RESET_N;
// ----------LED's----------
assign LED[7:0] = 8'hff;
// -------------------- BEGIN ALTERA IP INSTANTIATION --------------------
// Transciever driver (Required for Gen1)
altpcie_reconfig_driver
#(.number_of_reconfig_interfaces(10),
.gen123_lane_rate_mode_hwtcl("Gen1 (2.5 Gbps)"), // This must be changed between generations
.INTENDED_DEVICE_FAMILY("Stratix V"))
XCVRDriverGen1x8_inst
(
// Outputs
.reconfig_mgmt_address (reconfig_mgmt_address[6:0]),
.reconfig_mgmt_read (reconfig_mgmt_read),
.reconfig_mgmt_write (reconfig_mgmt_write),
.reconfig_mgmt_writedata (reconfig_mgmt_writedata[31:0]),
// Inputs
.pld_clk (pld_clk),
.reconfig_xcvr_rst (reconfig_xcvr_rst),
.reconfig_mgmt_readdata (reconfig_mgmt_readdata[31:0]),
.reconfig_mgmt_waitrequest (reconfig_mgmt_waitrequest),
.reconfig_xcvr_clk (reconfig_xcvr_clk),
.reconfig_busy (reconfig_busy),
// Link Status signals
.derr_cor_ext_rcv_drv (derr_cor_ext_rcv_drv),
.derr_cor_ext_rpl_drv (derr_cor_ext_rpl_drv),
.derr_rpl_drv (derr_rpl_drv),
.dlup_drv (dlup_drv),
.dlup_exit_drv (dlup_exit_drv),
.ev128ns_drv (ev128ns_drv),
.ev1us_drv (ev1us_drv),
.hotrst_exit_drv (hotrst_exit_drv),
.int_status_drv (int_status_drv[3:0]),
.l2_exit_drv (l2_exit_drv),
.lane_act_drv (lane_act_drv[3:0]),
.ltssmstate_drv (ltssmstate_drv[4:0]),
.rx_par_err_drv (rx_par_err_drv),
.tx_par_err_drv (tx_par_err_drv[1:0]),
.cfg_par_err_drv (cfg_par_err_drv),
.ko_cpl_spc_header_drv (ko_cpl_spc_header_drv[7:0]),
.ko_cpl_spc_data_drv (ko_cpl_spc_data_drv[11:0]),
.currentspeed (currentspeed[1:0]));
assign derr_cor_ext_rcv_drv = derr_cor_ext_rcv;
assign derr_cor_ext_rpl_drv = derr_cor_ext_rpl;
assign derr_rpl_drv = derr_rpl;
assign dlup_drv = dlup;
assign dlup_exit_drv = dlup_exit;
assign ev128ns_drv = ev128ns;
assign ev1us_drv = ev1us;
assign hotrst_exit_drv = hotrst_exit;
assign int_status_drv = int_status;
assign l2_exit_drv = l2_exit;
assign lane_act_drv = lane_act;
assign ltssmstate_drv = ltssmstate;
assign rx_par_err_drv = rx_par_err;
assign tx_par_err_drv = tx_par_err;
assign cfg_par_err_drv = cfg_par_err;
assign ko_cpl_spc_header_drv = ko_cpl_spc_header;
assign ko_cpl_spc_data_drv = ko_cpl_spc_data;
XCVRCtrlGen1x8 XCVRCtrlGen1x8_inst
(
// Outputs
.reconfig_busy (reconfig_busy),
.reconfig_mgmt_readdata (reconfig_mgmt_readdata[31:0]),
.reconfig_mgmt_waitrequest (reconfig_mgmt_waitrequest),
.reconfig_to_xcvr (reconfig_to_xcvr[699:0]),
// Inputs
.mgmt_clk_clk (mgmt_clk_clk),
.mgmt_rst_reset (mgmt_rst_reset),
.reconfig_mgmt_address (reconfig_mgmt_address[6:0]),
.reconfig_mgmt_read (reconfig_mgmt_read),
.reconfig_mgmt_write (reconfig_mgmt_write),
.reconfig_mgmt_writedata (reconfig_mgmt_writedata[31:0]),
.reconfig_from_xcvr (reconfig_from_xcvr[459:0]));
// PCIE Core
PCIeGen1x8If64 PCIeGen1x8If64_inst
(
// Outputs
// Local Management Interface
.lmi_ack (lmi_ack),
.lmi_dout (lmi_dout[31:0]),
.tl_cfg_add (tl_cfg_add[3:0]),
.tl_cfg_ctl (tl_cfg_ctl[31:0]),
.tl_cfg_sts (tl_cfg_sts[52:0]),
// RX Interface
.rx_st_sop (rx_st_sop[0:0]),
.rx_st_eop (rx_st_eop[0:0]),
.rx_st_err (rx_st_err[0:0]),
.rx_st_valid (rx_st_valid[0:0]),
.rx_st_data (rx_st_data[63:0]),
.rx_st_bar (rx_st_bar[7:0]),
// TX Interface
.tx_st_ready (tx_st_ready),
.coreclkout_hip (coreclkout_hip),
.reset_status (reset_status),
.serdes_pll_locked (serdes_pll_locked),
.pld_clk_inuse (pld_clk_inuse),
// Reconfiguration Interface
.reconfig_from_xcvr (reconfig_from_xcvr[459:0]),
.tx_out0 (tx_out[0]),
.tx_out1 (tx_out[1]),
.tx_out2 (tx_out[2]),
.tx_out3 (tx_out[3]),
.tx_out4 (tx_out[4]),
.tx_out5 (tx_out[5]),
.tx_out6 (tx_out[6]),
.tx_out7 (tx_out[7]),
.app_int_ack (app_int_ack),
.app_msi_ack (app_msi_ack),
// Link status signals
.derr_cor_ext_rcv (derr_cor_ext_rcv),
.derr_cor_ext_rpl (derr_cor_ext_rpl),
.derr_rpl (derr_rpl),
.dlup (dlup),
.dlup_exit (dlup_exit),
.ev128ns (ev128ns),
.ev1us (ev1us),
.hotrst_exit (hotrst_exit),
.int_status (int_status[3:0]),
.l2_exit (l2_exit),
.lane_act (lane_act[3:0]),
.ltssmstate (ltssmstate[4:0]),
.rx_par_err (rx_par_err),
.tx_par_err (tx_par_err[1:0]),
.cfg_par_err (cfg_par_err),
.ko_cpl_spc_header (ko_cpl_spc_header[7:0]),
.ko_cpl_spc_data (ko_cpl_spc_data[11:0]),
.currentspeed (currentspeed[1:0]),
// Inputs
// Resets
.npor (npor),
.pin_perst (pin_perst),
// Clocks
.pld_clk (pld_clk),
.refclk (refclk),
.pld_core_ready (pld_core_ready),
// Local management Interface
.lmi_addr (lmi_addr[11:0]),
.lmi_din (lmi_din[31:0]),
.lmi_rden (lmi_rden),
.lmi_wren (lmi_wren),
// RX Interface
.rx_st_ready (rx_st_ready),
.rx_st_mask (rx_st_mask),
// TX Interface
.tx_st_sop (tx_st_sop[0:0]),
.tx_st_eop (tx_st_eop[0:0]),
.tx_st_err (tx_st_err[0:0]),
.tx_st_valid (tx_st_valid[0:0]),
.tx_st_data (tx_st_data[63:0]),
// Reconfiguration Interface
.reconfig_to_xcvr (reconfig_to_xcvr[699:0]),
// RX Serial interface
.rx_in0 (rx_in[0]),
.rx_in1 (rx_in[1]),
.rx_in2 (rx_in[2]),
.rx_in3 (rx_in[3]),
.rx_in4 (rx_in[4]),
.rx_in5 (rx_in[5]),
.rx_in6 (rx_in[6]),
.rx_in7 (rx_in[7]),
// Interrupt Interface
.app_int_sts (app_int_sts),
.app_msi_num (app_msi_num[4:0]),
.app_msi_req (app_msi_req),
.app_msi_tc (app_msi_tc[2:0]),
.simu_mode_pipe (1'b0));
// -------------------- END ALTERA IP INSTANTIATION --------------------
// -------------------- BEGIN RIFFA INSTANTAION --------------------
// RIFFA channel interface
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*32)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*31)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*32)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*31)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
wire chnl_reset;
wire chnl_clk;
wire riffa_reset;
wire riffa_clk;
assign chnl_clk = pld_clk;
assign chnl_reset = rst_out;
riffa_wrapper_de5
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(
// Outputs
.RX_ST_READY (rx_st_ready),
.TX_ST_DATA (tx_st_data[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (tx_st_valid[0:0]),
.TX_ST_EOP (tx_st_eop[0:0]),
.TX_ST_SOP (tx_st_sop[0:0]),
.TX_ST_EMPTY (tx_st_empty[0:0]),
.APP_MSI_REQ (app_msi_req),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.RX_ST_DATA (rx_st_data[C_PCI_DATA_WIDTH-1:0]),
.RX_ST_EOP (rx_st_eop[0:0]),
.RX_ST_SOP (rx_st_sop[0:0]),
.RX_ST_VALID (rx_st_valid[0:0]),
.RX_ST_EMPTY (rx_st_empty[0:0]),
.TX_ST_READY (tx_st_ready),
.TL_CFG_CTL (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
.TL_CFG_ADD (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
.TL_CFG_STS (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
.KO_CPL_SPC_HEADER (ko_cpl_spc_header[`SIG_KO_CPLH_W-1:0]),
.KO_CPL_SPC_DATA (ko_cpl_spc_data[`SIG_KO_CPLD_W-1:0]),
.APP_MSI_ACK (app_msi_ack),
.PLD_CLK (pld_clk),
.RESET_STATUS (reset_status),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
// -------------------- END RIFFA INSTANTAION --------------------
// -------------------- BEGIN USER CODE --------------------
genvar i;
generate
for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
// Instantiate and assign modules to RIFFA channels. Users should
// replace the chnl_tester instantiation with their own core.
chnl_tester
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
)
chnl_tester_i
(
.CLK(chnl_clk),
.RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[i]),
.CHNL_RX(chnl_rx[i]),
.CHNL_RX_ACK(chnl_rx_ack[i]),
.CHNL_RX_LAST(chnl_rx_last[i]),
.CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]),
.CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[i]),
.CHNL_TX(chnl_tx[i]),
.CHNL_TX_ACK(chnl_tx_ack[i]),
.CHNL_TX_LAST(chnl_tx_last[i]),
.CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]),
.CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
);
end
endgenerate
// -------------------- END USER CODE --------------------
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD1_1_V
`define SKY130_FD_SC_LS__DLYGATE4SD1_1_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog wrapper for dlygate4sd1 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlygate4sd1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlygate4sd1_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlygate4sd1 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlygate4sd1_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlygate4sd1 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD1_1_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:33:10 03/01/2016
// Design Name:
// Module Name: Sincronizador
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Sincronizador(incambiarfuncion,incambiarsalida,inrst,inbtup,inbtdown,outcambiarfuncion,outcambiarsalida,outrst,outbtup,outbtdown,clk);
input wire incambiarfuncion,incambiarsalida,inrst,inbtup,inbtdown,clk;
output wire outcambiarfuncion,outcambiarsalida,outbtup,outbtdown,outrst;
Synchro S1 (
.dato(incambiarfuncion),
.clk(clk),
.ds(outcambiarfuncion)
);
Synchro S2 (
.dato(incambiarsalida),
.clk(clk),
.ds(outcambiarsalida)
);
Synchro S3 (
.dato(inrst),
.clk(clk),
.ds(outrst)
);
Synchro S4 (
.dato(inbtup),
.clk(clk),
.ds(outbtup)
);
Synchro S5 (
.dato(inbtdown),
.clk(clk),
.ds(outbtdown)
);
endmodule
|
// hps_sdram.v
// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1 162 at 2014.06.17.12:43:32
`timescale 1 ps / 1 ps
module hps_sdram (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
input wire oct_rzqin // oct.rzqin
);
wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
hps_sdram_pll pll (
.global_reset_n (global_reset_n), // global_reset.reset_n
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
);
hps_sdram_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.afi_reset_export_n (), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (), // avl_clk.clk
.avl_reset_n (), // avl_reset.reset_n
.scc_clk (), // scc_clk.clk
.scc_reset_n (), // scc_reset.reset_n
.avl_address (), // avl.address
.avl_write (), // .write
.avl_writedata (), // .writedata
.avl_read (), // .read
.avl_readdata (), // .readdata
.avl_waitrequest (), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (), // scc.scc_data
.scc_dqs_ena (), // .scc_dqs_ena
.scc_dqs_io_ena (), // .scc_dqs_io_ena
.scc_dq_ena (), // .scc_dq_ena
.scc_dm_ena (), // .scc_dm_ena
.capture_strobe_tracking (), // .capture_strobe_tracking
.scc_upd (), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
altera_mem_if_hhp_qseq_synth_top #(
.MEM_IF_DM_WIDTH (4),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_DQ_WIDTH (32)
) seq (
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (27),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (1),
.AVL_ADDR_WIDTH_PORT_0 (1),
.AVL_NUM_SYMBOLS_PORT_0 (1),
.LSB_WFIFO_PORT_0 (5),
.MSB_WFIFO_PORT_0 (5),
.LSB_RFIFO_PORT_0 (5),
.MSB_RFIFO_PORT_0 (5),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("DDR3"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("DISABLE"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
.ENUM_MEM_IF_TCCD ("TCCD_4"),
.ENUM_MEM_IF_TCL ("TCL_11"),
.ENUM_MEM_IF_TCWL ("TCWL_8"),
.ENUM_MEM_IF_TFAW ("TFAW_12"),
.ENUM_MEM_IF_TMRD ("TMRD_4"),
.ENUM_MEM_IF_TRAS ("TRAS_14"),
.ENUM_MEM_IF_TRC ("TRC_20"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_3"),
.ENUM_MEM_IF_TRTP ("TRTP_3"),
.ENUM_MEM_IF_TWR ("TWR_6"),
.ENUM_MEM_IF_TWTR ("TWTR_4"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (3120),
.INTG_MEM_IF_TRFC (104),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (15),
.AFI_BANKADDR_WIDTH (3),
.AFI_CONTROL_WIDTH (1),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (1),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.local_init_done (), // status.local_init_done
.local_cal_success (), // .local_cal_success
.local_cal_fail (), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (), // .afi_init_req
.afi_cal_req (), // .afi_cal_req
.afi_seq_busy (), // .afi_seq_busy
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
.afi_ctl_long_idle (), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_0 (1'b0), // (terminated)
.mp_cmd_reset_n_0 (1'b1), // (terminated)
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_0 (1'b0), // (terminated)
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
.mp_wfifo_clk_0 (1'b0), // (terminated)
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_0 (), // (terminated)
.avl_burstbegin_0 (1'b0), // (terminated)
.avl_addr_0 (1'b0), // (terminated)
.avl_rdata_valid_0 (), // (terminated)
.avl_rdata_0 (), // (terminated)
.avl_wdata_0 (1'b0), // (terminated)
.avl_be_0 (1'b0), // (terminated)
.avl_read_req_0 (1'b0), // (terminated)
.avl_write_req_0 (1'b0), // (terminated)
.avl_size_0 (3'b000), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
) dll (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A221O_FUNCTIONAL_PP_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a221o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out, C1);
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221O_FUNCTIONAL_PP_V |
module register (clk, we, d, q);
input [31:0] d;
input clk;
input we;
output [31:0] q;
wire clk;
wire we;
wire [31:0] d;
reg [31:0] q;
always @ (posedge clk)
if (we) q <= d;
endmodule // register
module fibfast (clk, n, start, fibn, done);
input [31:0] n;
input clk;
input start;
output [31:0] fibn;
output done;
wire start;
wire [31:0] n;
wire clk;
reg [31:0] fibn;
reg [31:0] in_n;
reg done;
reg [2:0] state;
reg [2:0] nextstate;
reg [31:0] b;
reg [31:0] h;
reg [31:0] d;
reg [31:0] f;
wire [31:0] nextn;
wire [31:0] nextb;
wire [31:0] nexth;
wire [31:0] nextd;
wire [31:0] nextf;
assign nextn = in_n / 2;
assign nextb = (b * f) + (d * f) + (b * h);
assign nexth = (f * f) + (h * h);
assign nextd = (b * f) + (d * h);
assign nextf = (f * f) + (2 * f * h);
initial begin
done = 1;
state = 0;
in_n = n;
end
always @ (posedge clk)
state = nextstate;
always @ (posedge clk)
if (state == 0 && start) begin
nextstate = 1;
end else if (state == 1) begin
done = 0;
b = 0;
h = 0;
d = 1;
f = 1;
nextstate = 2;
end else if (state == 2) begin
if (n <= 0) begin
nextstate = 0;
fibn = b;
done = 1;
end else begin
nextstate = 3;
end
end else if (state == 3) begin
if (n & 1 == 1) begin
b = nextb;
d = nextd;
end
f = nextf;
h = nexth;
in_n = nextn;
nextstate = 2;
end
endmodule // fibfast
module testbench;
reg clk;
reg [31:0] n;
reg start;
wire [31:0] fibn;
wire done;
fibfast ff (clk, n, start, fibn, done);
initial begin
clk = 0;
n = 10;
start = 1;
$monitor($time,, "%b %d %b %d %b", clk, n, start, fibn, done);
#100 $finish();
end
always
#10 clk = ~clk;
endmodule // testbench
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
// > Intel FPGA technology mapping. User must first simulate the generated \
// > netlist before going to test it on board.
// Input buffer map
module \$__inpad (input I, output O);
cycloneiv_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
cycloneiv_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
// LUT Map
/* 0 -> datac
1 -> cin */
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
cycloneiv_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));
end else
if(WIDTH == 3) begin
cycloneiv_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
end else
if(WIDTH == 4) begin
cycloneiv_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule //
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A311O_BEHAVIORAL_PP_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311O_BEHAVIORAL_PP_V |
<?
if (elem.Label="")
panic("err_romNeedsALabelToBeExported");
romMaxSize := 1 << elem.AddrBits;
data:=elem.Data;
if (elem.autoReload) {
data=loadHex(elem.lastDataFile, elem.Bits);
}
romSize := sizeOf(data);
moduleName = format("%s_%dX%d_%s", moduleName, romMaxSize, elem.Bits, identifier(elem.Label));
dBitRange := format("[%d:0]", elem.Bits - 1);
aBitRange := format("[%d:0]", elem.AddrBits - 1);
?>module <?= moduleName ?> (
input <?= aBitRange ?> A,
input sel,
output reg <?= dBitRange ?> D
);
reg <?= dBitRange ?> my_rom [0:<?= (romSize - 1) ?>];
always @ (*) begin
if (~sel)
D = <?= elem.Bits ?>'hz;<?
if (romSize < romMaxSize) {
lastAddr := format("%d'h%x", elem.AddrBits, romSize - 1); ?>
else if (A > <?= lastAddr ?>)
D = <?= elem.Bits ?>'h0;<?
} ?>
else
D = my_rom[A];
end
initial begin<?
for (i := 0; i < romSize; i++) { ?>
my_rom[<?= i ?>] = <?= format("%d'h%x", elem.Bits, data[i]) ?>;<?
} ?>
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module altera_mem_if_ddr3_phy_0001_reset_sync(
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
begin: reset_stage
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
reset_reg[i] <= 1'b0;
else
begin
if (i==0)
reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES)
reset_reg[i] <= reset_reg[i-1];
else
reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
|
`timescale 1 ns / 1 ps
`include "vga_axi_buffer_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define SAXI_MAX_BURST_LENGTH 1
`define SAXI_DATA_BUS_WIDTH 32
`define SAXI_ADDRESS_BUS_WIDTH 32
`define SAXI_MAX_DATA_SIZE (`SAXI_DATA_BUS_WIDTH*`SAXI_MAX_BURST_LENGTH)/8
module vga_axi_buffer_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA SAXI AXI4 Lite Local Reg
reg [`SAXI_DATA_BUS_WIDTH-1:0] SAXI_rd_data_lite;
reg [`SAXI_DATA_BUS_WIDTH-1:0] SAXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] SAXI_lite_response;
reg [`SAXI_ADDRESS_BUS_WIDTH-1:0] SAXI_mtestAddress;
reg [3-1:0] SAXI_mtestProtection_lite;
integer SAXI_mtestvectorlite; // Master side testvector
integer SAXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic SAXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : SAXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
SAXI_mtestvectorlite = 0;
SAXI_mtestAddress = `SAXI_SLAVE_ADDRESS;
SAXI_mtestProtection_lite = 0;
SAXI_mtestdatasizelite = `SAXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (SAXI_mtestvectorlite = 0; SAXI_mtestvectorlite <= 3; SAXI_mtestvectorlite = SAXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( SAXI_mtestAddress,
SAXI_mtestProtection_lite,
SAXI_test_data_lite[SAXI_mtestvectorlite],
SAXI_mtestdatasizelite,
SAXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",SAXI_mtestvectorlite,SAXI_test_data_lite[SAXI_mtestvectorlite],SAXI_lite_response);
CHECK_RESPONSE_OKAY(SAXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(SAXI_mtestAddress,
SAXI_mtestProtection_lite,
SAXI_rd_data_lite,
SAXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",SAXI_mtestvectorlite,SAXI_rd_data_lite,SAXI_lite_response);
CHECK_RESPONSE_OKAY(SAXI_lite_response);
COMPARE_LITE_DATA(SAXI_test_data_lite[SAXI_mtestvectorlite],SAXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",SAXI_mtestvectorlite,SAXI_mtestvectorlite);
SAXI_mtestAddress = SAXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST SAXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
SAXI_test_data_lite[0] = 32'h0101FFFF;
SAXI_test_data_lite[1] = 32'habcd0001;
SAXI_test_data_lite[2] = 32'hdead0011;
SAXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
SAXI_TEST();
end
endmodule
|
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