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//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module nios_altmemddr_0_phy_alt_mem_phy_seq_wrapper (
// dss ports
phy_clk_1x,
reset_phy_clk_1x_n,
ctl_cal_success,
ctl_cal_fail,
ctl_cal_warning,
ctl_cal_req,
int_RANK_HAS_ADDR_SWAP,
ctl_cal_byte_lane_sel_n,
seq_pll_inc_dec_n,
seq_pll_start_reconfig,
seq_pll_select,
phs_shft_busy,
pll_resync_clk_index,
pll_measure_clk_index,
sc_clk_dp,
scan_enable_dqs_config,
scan_update,
scan_din,
scan_enable_ck,
scan_enable_dqs,
scan_enable_dqsn,
scan_enable_dq,
scan_enable_dm,
hr_rsc_clk,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n,
seq_ac_sel,
seq_mem_clk_disable,
ctl_add_1t_ac_lat_internal,
ctl_add_1t_odt_lat_internal,
ctl_add_intermediate_regs_internal,
seq_rdv_doing_rd,
seq_rdp_reset_req_n,
seq_rdp_inc_read_lat_1x,
seq_rdp_dec_read_lat_1x,
ctl_rdata,
int_rdata_valid_1t,
seq_rdata_valid_lat_inc,
seq_rdata_valid_lat_dec,
ctl_rlat,
seq_poa_lat_dec_1x,
seq_poa_lat_inc_1x,
seq_poa_protection_override_1x,
seq_oct_oct_delay,
seq_oct_oct_extend,
seq_oct_val,
seq_wdp_dqs_burst,
seq_wdp_wdata_valid,
seq_wdp_wdata,
seq_wdp_dm,
seq_wdp_dqs,
seq_wdp_ovride,
seq_dqs_add_2t_delay,
ctl_wlat,
seq_mmc_start,
mmc_seq_done,
mmc_seq_value,
mem_err_out_n,
parity_error_n,
dbg_clk,
dbg_reset_n,
dbg_addr,
dbg_wr,
dbg_rd,
dbg_cs,
dbg_wr_data,
dbg_rd_data,
dbg_waitrequest
);
//Inserted Generics
localparam SPEED_GRADE = "C8";
localparam MEM_IF_DQS_WIDTH = 1;
localparam MEM_IF_DWIDTH = 8;
localparam MEM_IF_DM_WIDTH = 1;
localparam MEM_IF_DQ_PER_DQS = 8;
localparam DWIDTH_RATIO = 4;
localparam CLOCK_INDEX_WIDTH = 3;
localparam MEM_IF_CLK_PAIR_COUNT = 1;
localparam MEM_IF_ADDR_WIDTH = 14;
localparam MEM_IF_BANKADDR_WIDTH = 2;
localparam MEM_IF_CS_WIDTH = 1;
localparam RESYNCHRONISE_AVALON_DBG = 0;
localparam DBG_A_WIDTH = 13;
localparam DQS_PHASE_SETTING = 2;
localparam SCAN_CLK_DIVIDE_BY = 2;
localparam PLL_STEPS_PER_CYCLE = 80;
localparam MEM_IF_CLK_PS = 8000;
localparam DQS_DELAY_CTL_WIDTH = 6;
localparam MEM_IF_MEMTYPE = "DDR2";
localparam RANK_HAS_ADDR_SWAP = 0;
localparam MEM_IF_MR_0 = 579;
localparam MEM_IF_MR_1 = 1024;
localparam MEM_IF_MR_2 = 0;
localparam MEM_IF_MR_3 = 0;
localparam MEM_IF_OCT_EN = 0;
localparam IP_BUILDNUM = 0;
localparam FAMILY = "Cyclone IV E";
localparam FAMILYGROUP_ID = 2;
localparam MEM_IF_ADDR_CMD_PHASE = 90;
localparam CAPABILITIES = 2048;
localparam WRITE_DESKEW_T10 = 0;
localparam WRITE_DESKEW_HC_T10 = 0;
localparam WRITE_DESKEW_T9NI = 0;
localparam WRITE_DESKEW_HC_T9NI = 0;
localparam WRITE_DESKEW_T9I = 0;
localparam WRITE_DESKEW_HC_T9I = 0;
localparam WRITE_DESKEW_RANGE = 0;
localparam IOE_PHASES_PER_TCK = 12;
localparam ADV_LAT_WIDTH = 5;
localparam RDP_ADDR_WIDTH = 4;
localparam IOE_DELAYS_PER_PHS = 5;
localparam SINGLE_DQS_DELAY_CONTROL_CODE = 0;
localparam PRESET_RLAT = 0;
localparam FORCE_HC = 0;
localparam MEM_IF_DQS_CAPTURE_EN = 0;
localparam REDUCE_SIM_TIME = 0;
localparam TINIT_TCK = 12500;
localparam TINIT_RST = 0;
localparam GENERATE_ADDITIONAL_DBG_RTL = 0;
localparam MEM_IF_CS_PER_RANK = 1;
localparam MEM_IF_RANKS_PER_SLOT = 1;
localparam CHIP_OR_DIMM = "Discrete Device";
localparam RDIMM_CONFIG_BITS = "0000000000000000000000000000000000000000000000000000000000000000";
localparam OCT_LAT_WIDTH = ADV_LAT_WIDTH;
localparam GENERATE_TRACKING_PHASE_STORE = 0;
// note that num_ranks if the number of discrete chip select signals output from the sequencer
// cs_width is the total number of chip selects which go from the phy to the memory (there can
// be more than one chip select per rank).
localparam MEM_IF_NUM_RANKS = MEM_IF_CS_WIDTH/MEM_IF_CS_PER_RANK;
input wire phy_clk_1x;
input wire reset_phy_clk_1x_n;
output wire ctl_cal_success;
output wire ctl_cal_fail;
output wire ctl_cal_warning;
input wire ctl_cal_req;
input wire [MEM_IF_NUM_RANKS - 1 : 0] int_RANK_HAS_ADDR_SWAP;
input wire [MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
output wire seq_pll_inc_dec_n;
output wire seq_pll_start_reconfig;
output wire [CLOCK_INDEX_WIDTH - 1 : 0] seq_pll_select;
input wire phs_shft_busy;
input wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_resync_clk_index;
input wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_measure_clk_index;
output [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqs_config;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_update;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_din;
output wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] scan_enable_ck;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqs;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqsn;
output wire [MEM_IF_DWIDTH - 1 : 0] scan_enable_dq;
output wire [MEM_IF_DM_WIDTH - 1 : 0] scan_enable_dm;
input wire hr_rsc_clk;
output wire [(DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 : 0] seq_ac_addr;
output wire [(DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 : 0] seq_ac_ba;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_cas_n;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_ras_n;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_we_n;
output wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] seq_ac_cke;
output wire [(DWIDTH_RATIO/2) * MEM_IF_CS_WIDTH - 1 : 0] seq_ac_cs_n;
output wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] seq_ac_odt;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_rst_n;
output wire seq_ac_sel;
output wire seq_mem_clk_disable;
output wire ctl_add_1t_ac_lat_internal;
output wire ctl_add_1t_odt_lat_internal;
output wire ctl_add_intermediate_regs_internal;
output wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_rdv_doing_rd;
output wire seq_rdp_reset_req_n;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_rdp_inc_read_lat_1x;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_rdp_dec_read_lat_1x;
input wire [DWIDTH_RATIO * MEM_IF_DWIDTH - 1 : 0] ctl_rdata;
input wire [DWIDTH_RATIO/2 - 1 : 0] int_rdata_valid_1t;
output wire seq_rdata_valid_lat_inc;
output wire seq_rdata_valid_lat_dec;
output wire [ADV_LAT_WIDTH - 1 : 0] ctl_rlat;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_poa_lat_dec_1x;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_poa_lat_inc_1x;
output wire seq_poa_protection_override_1x;
output wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_delay;
output wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_extend;
output wire seq_oct_val;
output wire [(DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 : 0] seq_wdp_dqs_burst;
output wire [(DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 : 0] seq_wdp_wdata_valid;
output wire [DWIDTH_RATIO * MEM_IF_DWIDTH - 1 : 0] seq_wdp_wdata;
output wire [DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 : 0] seq_wdp_dm;
output wire [DWIDTH_RATIO - 1 : 0] seq_wdp_dqs;
output wire seq_wdp_ovride;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_dqs_add_2t_delay;
output wire [ADV_LAT_WIDTH - 1 : 0] ctl_wlat;
output wire seq_mmc_start;
input wire mmc_seq_done;
input wire mmc_seq_value;
input wire dbg_clk;
input wire dbg_reset_n;
input wire [DBG_A_WIDTH - 1 : 0] dbg_addr;
input wire dbg_wr;
input wire dbg_rd;
input wire dbg_cs;
input wire [ 31 : 0] dbg_wr_data;
output wire [ 31 : 0] dbg_rd_data;
output wire dbg_waitrequest;
input wire mem_err_out_n;
output wire parity_error_n;
(* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
// instantiate the deskew (DDR3) or non-deskew (DDR/DDR2/DDR3) sequencer:
//
nios_altmemddr_0_phy_alt_mem_phy_seq #(
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.DWIDTH_RATIO (DWIDTH_RATIO),
.CLOCK_INDEX_WIDTH (CLOCK_INDEX_WIDTH),
.MEM_IF_CLK_PAIR_COUNT (MEM_IF_CLK_PAIR_COUNT),
.MEM_IF_ADDR_WIDTH (MEM_IF_ADDR_WIDTH),
.MEM_IF_BANKADDR_WIDTH (MEM_IF_BANKADDR_WIDTH),
.MEM_IF_CS_WIDTH (MEM_IF_CS_WIDTH),
.MEM_IF_NUM_RANKS (MEM_IF_NUM_RANKS),
.MEM_IF_RANKS_PER_SLOT (MEM_IF_RANKS_PER_SLOT),
.ADV_LAT_WIDTH (ADV_LAT_WIDTH),
.RESYNCHRONISE_AVALON_DBG (RESYNCHRONISE_AVALON_DBG),
.AV_IF_ADDR_WIDTH (DBG_A_WIDTH),
.NOM_DQS_PHASE_SETTING (DQS_PHASE_SETTING),
.SCAN_CLK_DIVIDE_BY (SCAN_CLK_DIVIDE_BY),
.RDP_ADDR_WIDTH (RDP_ADDR_WIDTH),
.PLL_STEPS_PER_CYCLE (PLL_STEPS_PER_CYCLE),
.IOE_PHASES_PER_TCK (IOE_PHASES_PER_TCK),
.IOE_DELAYS_PER_PHS (IOE_DELAYS_PER_PHS),
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.PHY_DEF_MR_1ST (MEM_IF_MR_0),
.PHY_DEF_MR_2ND (MEM_IF_MR_1),
.PHY_DEF_MR_3RD (MEM_IF_MR_2),
.PHY_DEF_MR_4TH (MEM_IF_MR_3),
.MEM_IF_DQSN_EN (0),
.MEM_IF_DQS_CAPTURE_EN (MEM_IF_DQS_CAPTURE_EN),
.FAMILY (FAMILY),
.FAMILYGROUP_ID (FAMILYGROUP_ID),
.SPEED_GRADE (SPEED_GRADE),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.WRITE_DESKEW_T10 (WRITE_DESKEW_T10),
.WRITE_DESKEW_HC_T10 (WRITE_DESKEW_HC_T10),
.WRITE_DESKEW_T9NI (WRITE_DESKEW_T9NI),
.WRITE_DESKEW_HC_T9NI (WRITE_DESKEW_HC_T9NI),
.WRITE_DESKEW_T9I (WRITE_DESKEW_T9I),
.WRITE_DESKEW_HC_T9I (WRITE_DESKEW_HC_T9I),
.WRITE_DESKEW_RANGE (WRITE_DESKEW_RANGE),
.SINGLE_DQS_DELAY_CONTROL_CODE (SINGLE_DQS_DELAY_CONTROL_CODE),
.PRESET_RLAT (PRESET_RLAT),
.EN_OCT (MEM_IF_OCT_EN),
.SIM_TIME_REDUCTIONS (REDUCE_SIM_TIME),
.FORCE_HC (FORCE_HC),
.CAPABILITIES (CAPABILITIES),
.GENERATE_ADDITIONAL_DBG_RTL (GENERATE_ADDITIONAL_DBG_RTL),
.TINIT_TCK (TINIT_TCK),
.TINIT_RST (TINIT_RST),
.GENERATE_TRACKING_PHASE_STORE (0),
.OCT_LAT_WIDTH (OCT_LAT_WIDTH),
.IP_BUILDNUM (IP_BUILDNUM),
.CHIP_OR_DIMM (CHIP_OR_DIMM),
.RDIMM_CONFIG_BITS (RDIMM_CONFIG_BITS)
) seq_inst (
.clk (phy_clk_1x),
.rst_n (reset_phy_clk_1x_n),
.ctl_init_success (ctl_cal_success),
.ctl_init_fail (ctl_cal_fail),
.ctl_init_warning (ctl_cal_warning),
.ctl_recalibrate_req (ctl_cal_req),
.MEM_AC_SWAPPED_RANKS (int_RANK_HAS_ADDR_SWAP),
.ctl_cal_byte_lanes (ctl_cal_byte_lane_sel_n),
.seq_pll_inc_dec_n (seq_pll_inc_dec_n),
.seq_pll_start_reconfig (seq_pll_start_reconfig),
.seq_pll_select (seq_pll_select),
.seq_pll_phs_shift_busy (phs_shft_busy),
.pll_resync_clk_index (pll_resync_clk_index),
.pll_measure_clk_index (pll_measure_clk_index),
.seq_scan_clk (sc_clk_dp),
.seq_scan_enable_dqs_config (scan_enable_dqs_config),
.seq_scan_update (scan_update),
.seq_scan_din (scan_din),
.seq_scan_enable_ck (scan_enable_ck),
.seq_scan_enable_dqs (scan_enable_dqs),
.seq_scan_enable_dqsn (scan_enable_dqsn),
.seq_scan_enable_dq (scan_enable_dq),
.seq_scan_enable_dm (scan_enable_dm),
.hr_rsc_clk (hr_rsc_clk),
.seq_ac_addr (seq_ac_addr),
.seq_ac_ba (seq_ac_ba),
.seq_ac_cas_n (seq_ac_cas_n),
.seq_ac_ras_n (seq_ac_ras_n),
.seq_ac_we_n (seq_ac_we_n),
.seq_ac_cke (seq_ac_cke),
.seq_ac_cs_n (seq_ac_cs_n),
.seq_ac_odt (seq_ac_odt),
.seq_ac_rst_n (seq_ac_rst_n),
.seq_ac_sel (seq_ac_sel),
.seq_mem_clk_disable (seq_mem_clk_disable),
.seq_ac_add_1t_ac_lat_internal (ctl_add_1t_ac_lat_internal),
.seq_ac_add_1t_odt_lat_internal (ctl_add_1t_odt_lat_internal),
.seq_ac_add_2t (ctl_add_intermediate_regs_internal),
.seq_rdv_doing_rd (seq_rdv_doing_rd),
.seq_rdp_reset_req_n (seq_rdp_reset_req_n),
.seq_rdp_inc_read_lat_1x (seq_rdp_inc_read_lat_1x),
.seq_rdp_dec_read_lat_1x (seq_rdp_dec_read_lat_1x),
.rdata (ctl_rdata),
.rdata_valid (int_rdata_valid_1t),
.seq_rdata_valid_lat_inc (seq_rdata_valid_lat_inc),
.seq_rdata_valid_lat_dec (seq_rdata_valid_lat_dec),
.seq_ctl_rlat (ctl_rlat),
.seq_poa_lat_dec_1x (seq_poa_lat_dec_1x),
.seq_poa_lat_inc_1x (seq_poa_lat_inc_1x),
.seq_poa_protection_override_1x (seq_poa_protection_override_1x),
.seq_oct_oct_delay (seq_oct_oct_delay),
.seq_oct_oct_extend (seq_oct_oct_extend),
.seq_oct_value (seq_oct_val),
.seq_wdp_dqs_burst (seq_wdp_dqs_burst),
.seq_wdp_wdata_valid (seq_wdp_wdata_valid),
.seq_wdp_wdata (seq_wdp_wdata),
.seq_wdp_dm (seq_wdp_dm),
.seq_wdp_dqs (seq_wdp_dqs),
.seq_wdp_ovride (seq_wdp_ovride),
.seq_dqs_add_2t_delay (seq_dqs_add_2t_delay),
.seq_ctl_wlat (ctl_wlat),
.seq_mmc_start (seq_mmc_start),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value),
.mem_err_out_n (mem_err_out_n),
.parity_error_n (parity_error_n),
.dbg_seq_clk (dbg_clk),
.dbg_seq_rst_n (dbg_reset_n),
.dbg_seq_addr (dbg_addr),
.dbg_seq_wr (dbg_wr),
.dbg_seq_rd (dbg_rd),
.dbg_seq_cs (dbg_cs),
.dbg_seq_wr_data (dbg_wr_data),
.seq_dbg_rd_data (dbg_rd_data),
.seq_dbg_waitrequest (dbg_waitrequest)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_cntrl.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Structural block instantiating the three sub blocks that make up
// a bank machine.
`timescale 1ps/1ps
module bank_cntrl #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter BANK_WIDTH = 3,
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter ECC = "OFF",
parameter ID = 4,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nCNFG2RD_EN = 2,
parameter nCNFG2WR = 2,
parameter nOP_WAIT = 0,
parameter nRAS_CLKS = 10,
parameter nRCD = 5,
parameter nRTP = 4,
parameter nRP = 10,
parameter nWTP_CLKS = 5,
parameter ORDERING = "NORM",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter RAS_TIMER_WIDTH = 5,
parameter ROW_WIDTH = 16,
parameter STARVE_LIMIT = 2
)
(/*AUTOARG*/
// Outputs
wr_this_rank_r, start_rcd, start_pre_wait, rts_row, rts_col, rts_pre, rtc,
row_cmd_wr, row_addr, req_size_r, req_row_r, req_ras,
req_periodic_rd_r, req_cas, req_bank_r, rd_this_rank_r,
rb_hit_busy_ns, ras_timer_ns, rank_busy_r, ordered_r,
ordered_issued, op_exit_req, end_rtp, demand_priority,
demand_act_priority, col_rdy_wr, col_addr, act_this_rank_r, idle_ns,
req_wr_r, rd_wr_r, bm_end, idle_r, head_r, req_rank_r,
rb_hit_busy_r, passing_open_bank, maint_hit, req_data_buf_addr_r,
// Inputs
wtr_inhbt_config_r, was_wr, was_priority, use_addr, start_rcd_in,
size, sent_row, sent_col, sending_row, sending_pre, sending_col, rst, row,
req_rank_r_in, rd_rmw, rd_data_addr, rb_hit_busy_ns_in,
rb_hit_busy_cnt, ras_timer_ns_in, rank, periodic_rd_rank_r,
periodic_rd_insert, periodic_rd_ack_r, passing_open_bank_in,
order_cnt, op_exit_grant, maint_zq_r, maint_req_r, maint_rank_r,
maint_idle, low_idle_cnt_r, io_config_valid_r, io_config_strobe,
io_config, inhbt_wr_config, inhbt_rd_r, inhbt_wr_r, inhbt_rd_config,
inhbt_act_faw_r, idle_cnt, hi_priority, dq_busy_data,
phy_rddata_valid, demand_priority_in, demand_act_priority_in,
data_buf_addr, col, cmd, clk, bm_end_in, bank, adv_order_q,
accept_req, accept_internal_r
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input accept_internal_r; // To bank_queue0 of bank_queue.v
input accept_req; // To bank_queue0 of bank_queue.v
input adv_order_q; // To bank_queue0 of bank_queue.v
input [BANK_WIDTH-1:0] bank; // To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] bm_end_in; // To bank_queue0 of bank_queue.v
input clk; // To bank_compare0 of bank_compare.v, ...
input [2:0] cmd; // To bank_compare0 of bank_compare.v
input [COL_WIDTH-1:0] col; // To bank_compare0 of bank_compare.v
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;// To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;// To bank_state0 of bank_state.v
input [(nBANK_MACHS*2)-1:0] demand_priority_in;// To bank_state0 of bank_state.v
input phy_rddata_valid; // To bank_state0 of bank_state.v
input dq_busy_data; // To bank_state0 of bank_state.v
input hi_priority; // To bank_compare0 of bank_compare.v
input [BM_CNT_WIDTH-1:0] idle_cnt; // To bank_queue0 of bank_queue.v
input [RANKS-1:0] inhbt_act_faw_r; // To bank_state0 of bank_state.v
input inhbt_rd_config; // To bank_state0 of bank_state.v
input [RANKS-1:0] inhbt_rd_r; // To bank_state0 of bank_state.v
input [RANKS-1:0] inhbt_wr_r; // To bank_state0 of bank_state.v
input inhbt_wr_config; // To bank_state0 of bank_state.v
input [RANK_WIDTH:0] io_config; // To bank_state0 of bank_state.v
input io_config_strobe; // To bank_state0 of bank_state.v
input io_config_valid_r; // To bank_state0 of bank_state.v
input low_idle_cnt_r; // To bank_state0 of bank_state.v
input maint_idle; // To bank_queue0 of bank_queue.v
input [RANK_WIDTH-1:0] maint_rank_r; // To bank_compare0 of bank_compare.v
input maint_req_r; // To bank_queue0 of bank_queue.v
input maint_zq_r; // To bank_compare0 of bank_compare.v
input op_exit_grant; // To bank_state0 of bank_state.v
input [BM_CNT_WIDTH-1:0] order_cnt; // To bank_queue0 of bank_queue.v
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;// To bank_queue0 of bank_queue.v
input periodic_rd_ack_r; // To bank_queue0 of bank_queue.v
input periodic_rd_insert; // To bank_compare0 of bank_compare.v
input [RANK_WIDTH-1:0] periodic_rd_rank_r; // To bank_compare0 of bank_compare.v
input [RANK_WIDTH-1:0] rank; // To bank_compare0 of bank_compare.v
input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;// To bank_state0 of bank_state.v
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // To bank_queue0 of bank_queue.v
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;// To bank_queue0 of bank_queue.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To bank_state0 of bank_state.v
input rd_rmw; // To bank_state0 of bank_state.v
input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;// To bank_state0 of bank_state.v
input [ROW_WIDTH-1:0] row; // To bank_compare0 of bank_compare.v
input rst; // To bank_state0 of bank_state.v, ...
input sending_col; // To bank_compare0 of bank_compare.v, ...
input sending_row; // To bank_state0 of bank_state.v
input sending_pre;
input sent_col; // To bank_state0 of bank_state.v
input sent_row; // To bank_state0 of bank_state.v
input size; // To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] start_rcd_in; // To bank_state0 of bank_state.v
input use_addr; // To bank_queue0 of bank_queue.v
input was_priority; // To bank_queue0 of bank_queue.v
input was_wr; // To bank_queue0 of bank_queue.v
input [RANKS-1:0] wtr_inhbt_config_r; // To bank_state0 of bank_state.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [RANKS-1:0] act_this_rank_r; // From bank_state0 of bank_state.v
output [ROW_WIDTH-1:0] col_addr; // From bank_compare0 of bank_compare.v
output col_rdy_wr; // From bank_state0 of bank_state.v
output demand_act_priority; // From bank_state0 of bank_state.v
output demand_priority; // From bank_state0 of bank_state.v
output end_rtp; // From bank_state0 of bank_state.v
output op_exit_req; // From bank_state0 of bank_state.v
output ordered_issued; // From bank_queue0 of bank_queue.v
output ordered_r; // From bank_queue0 of bank_queue.v
output [RANKS-1:0] rank_busy_r; // From bank_compare0 of bank_compare.v
output [RAS_TIMER_WIDTH-1:0] ras_timer_ns; // From bank_state0 of bank_state.v
output rb_hit_busy_ns; // From bank_compare0 of bank_compare.v
output [RANKS-1:0] rd_this_rank_r; // From bank_state0 of bank_state.v
output [BANK_WIDTH-1:0] req_bank_r; // From bank_compare0 of bank_compare.v
output req_cas; // From bank_compare0 of bank_compare.v
output req_periodic_rd_r; // From bank_compare0 of bank_compare.v
output req_ras; // From bank_compare0 of bank_compare.v
output [ROW_WIDTH-1:0] req_row_r; // From bank_compare0 of bank_compare.v
output req_size_r; // From bank_compare0 of bank_compare.v
output [ROW_WIDTH-1:0] row_addr; // From bank_compare0 of bank_compare.v
output row_cmd_wr; // From bank_compare0 of bank_compare.v
output rtc; // From bank_state0 of bank_state.v
output rts_col; // From bank_state0 of bank_state.v
output rts_row; // From bank_state0 of bank_state.v
output rts_pre;
output start_pre_wait; // From bank_state0 of bank_state.v
output start_rcd; // From bank_state0 of bank_state.v
output [RANKS-1:0] wr_this_rank_r; // From bank_state0 of bank_state.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire act_wait_r; // From bank_state0 of bank_state.v
wire allow_auto_pre; // From bank_state0 of bank_state.v
wire auto_pre_r; // From bank_queue0 of bank_queue.v
wire bank_wait_in_progress; // From bank_state0 of bank_state.v
wire order_q_zero; // From bank_queue0 of bank_queue.v
wire pass_open_bank_ns; // From bank_queue0 of bank_queue.v
wire pass_open_bank_r; // From bank_queue0 of bank_queue.v
wire pre_wait_r; // From bank_state0 of bank_state.v
wire precharge_bm_end; // From bank_state0 of bank_state.v
wire q_has_priority; // From bank_queue0 of bank_queue.v
wire q_has_rd; // From bank_queue0 of bank_queue.v
wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; // From bank_queue0 of bank_queue.v
wire rcv_open_bank; // From bank_queue0 of bank_queue.v
wire rd_half_rmw; // From bank_state0 of bank_state.v
wire req_priority_r; // From bank_compare0 of bank_compare.v
wire row_hit_r; // From bank_compare0 of bank_compare.v
wire tail_r; // From bank_queue0 of bank_queue.v
wire wait_for_maint_r; // From bank_queue0 of bank_queue.v
// End of automatics
output idle_ns;
output req_wr_r;
output rd_wr_r;
output bm_end;
output idle_r;
output head_r;
output [RANK_WIDTH-1:0] req_rank_r;
output rb_hit_busy_r;
output passing_open_bank;
output maint_hit;
output [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
bank_compare #
(/*AUTOINSTPARAM*/
// Parameters
.BANK_WIDTH (BANK_WIDTH),
.TCQ (TCQ),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH))
bank_compare0
(/*AUTOINST*/
// Outputs
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.req_periodic_rd_r (req_periodic_rd_r),
.req_size_r (req_size_r),
.rd_wr_r (rd_wr_r),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_bank_r (req_bank_r[BANK_WIDTH-1:0]),
.req_row_r (req_row_r[ROW_WIDTH-1:0]),
.req_wr_r (req_wr_r),
.req_priority_r (req_priority_r),
.rb_hit_busy_r (rb_hit_busy_r),
.rb_hit_busy_ns (rb_hit_busy_ns),
.row_hit_r (row_hit_r),
.maint_hit (maint_hit),
.col_addr (col_addr[ROW_WIDTH-1:0]),
.req_ras (req_ras),
.req_cas (req_cas),
.row_cmd_wr (row_cmd_wr),
.row_addr (row_addr[ROW_WIDTH-1:0]),
.rank_busy_r (rank_busy_r[RANKS-1:0]),
// Inputs
.clk (clk),
.idle_ns (idle_ns),
.idle_r (idle_r),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.periodic_rd_insert (periodic_rd_insert),
.size (size),
.cmd (cmd[2:0]),
.sending_col (sending_col),
.rank (rank[RANK_WIDTH-1:0]),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.bank (bank[BANK_WIDTH-1:0]),
.row (row[ROW_WIDTH-1:0]),
.col (col[COL_WIDTH-1:0]),
.hi_priority (hi_priority),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_zq_r (maint_zq_r),
.auto_pre_r (auto_pre_r),
.rd_half_rmw (rd_half_rmw),
.act_wait_r (act_wait_r));
bank_state #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.ECC (ECC),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCNFG2RD_EN (nCNFG2RD_EN),
.nCNFG2WR (nCNFG2WR),
.nOP_WAIT (nOP_WAIT),
.nRAS_CLKS (nRAS_CLKS),
.nRP (nRP),
.nRTP (nRTP),
.nRCD (nRCD),
.nWTP_CLKS (nWTP_CLKS),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
.STARVE_LIMIT (STARVE_LIMIT))
bank_state0
(/*AUTOINST*/
// Outputs
.start_rcd (start_rcd),
.act_wait_r (act_wait_r),
.rd_half_rmw (rd_half_rmw),
.ras_timer_ns (ras_timer_ns[RAS_TIMER_WIDTH-1:0]),
.end_rtp (end_rtp),
.bank_wait_in_progress (bank_wait_in_progress),
.start_pre_wait (start_pre_wait),
.op_exit_req (op_exit_req),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.precharge_bm_end (precharge_bm_end),
.demand_act_priority (demand_act_priority),
.rts_row (rts_row),
.rts_pre (rts_pre),
.act_this_rank_r (act_this_rank_r[RANKS-1:0]),
.demand_priority (demand_priority),
.rtc (rtc),
.col_rdy_wr (col_rdy_wr),
.rts_col (rts_col),
.wr_this_rank_r (wr_this_rank_r[RANKS-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANKS-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.bm_end (bm_end),
.pass_open_bank_r (pass_open_bank_r),
.sending_row (sending_row),
.sending_pre (sending_pre),
.rcv_open_bank (rcv_open_bank),
.sending_col (sending_col),
.rd_wr_r (rd_wr_r),
.req_wr_r (req_wr_r),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.rd_rmw (rd_rmw),
.ras_timer_ns_in (ras_timer_ns_in[(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0]),
.rb_hit_busies_r (rb_hit_busies_r[(nBANK_MACHS*2)-1:0]),
.idle_r (idle_r),
.passing_open_bank (passing_open_bank),
.low_idle_cnt_r (low_idle_cnt_r),
.op_exit_grant (op_exit_grant),
.tail_r (tail_r),
.auto_pre_r (auto_pre_r),
.pass_open_bank_ns (pass_open_bank_ns),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_rank_r_in (req_rank_r_in[(RANK_WIDTH*nBANK_MACHS*2)-1:0]),
.start_rcd_in (start_rcd_in[(nBANK_MACHS*2)-1:0]),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.wait_for_maint_r (wait_for_maint_r),
.head_r (head_r),
.sent_row (sent_row),
.demand_act_priority_in (demand_act_priority_in[(nBANK_MACHS*2)-1:0]),
.order_q_zero (order_q_zero),
.sent_col (sent_col),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.req_priority_r (req_priority_r),
.idle_ns (idle_ns),
.demand_priority_in (demand_priority_in[(nBANK_MACHS*2)-1:0]),
.io_config_strobe (io_config_strobe),
.io_config_valid_r (io_config_valid_r),
.io_config (io_config[RANK_WIDTH:0]),
.wtr_inhbt_config_r (wtr_inhbt_config_r[RANKS-1:0]),
.inhbt_rd_config (inhbt_rd_config),
.inhbt_wr_config (inhbt_wr_config),
.inhbt_rd_r (inhbt_rd_r[RANKS-1:0]),
.inhbt_wr_r (inhbt_wr_r[RANKS-1:0]),
.dq_busy_data (dq_busy_data));
bank_queue #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.nBANK_MACHS (nBANK_MACHS),
.ORDERING (ORDERING),
.ID (ID))
bank_queue0
(/*AUTOINST*/
// Outputs
.head_r (head_r),
.tail_r (tail_r),
.idle_ns (idle_ns),
.idle_r (idle_r),
.pass_open_bank_ns (pass_open_bank_ns),
.pass_open_bank_r (pass_open_bank_r),
.auto_pre_r (auto_pre_r),
.bm_end (bm_end),
.passing_open_bank (passing_open_bank),
.ordered_issued (ordered_issued),
.ordered_r (ordered_r),
.order_q_zero (order_q_zero),
.rcv_open_bank (rcv_open_bank),
.rb_hit_busies_r (rb_hit_busies_r[nBANK_MACHS*2-1:0]),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.wait_for_maint_r (wait_for_maint_r),
// Inputs
.clk (clk),
.rst (rst),
.accept_internal_r (accept_internal_r),
.use_addr (use_addr),
.periodic_rd_ack_r (periodic_rd_ack_r),
.bm_end_in (bm_end_in[(nBANK_MACHS*2)-1:0]),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.accept_req (accept_req),
.rb_hit_busy_r (rb_hit_busy_r),
.maint_idle (maint_idle),
.maint_hit (maint_hit),
.row_hit_r (row_hit_r),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.sending_col (sending_col),
.req_wr_r (req_wr_r),
.rd_wr_r (rd_wr_r),
.bank_wait_in_progress (bank_wait_in_progress),
.precharge_bm_end (precharge_bm_end),
.adv_order_q (adv_order_q),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_ns_in (rb_hit_busy_ns_in[(nBANK_MACHS*2)-1:0]),
.passing_open_bank_in (passing_open_bank_in[(nBANK_MACHS*2)-1:0]),
.was_wr (was_wr),
.maint_req_r (maint_req_r),
.was_priority (was_priority));
endmodule // bank_cntrl
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This is the top level of the Guru core graphics logic.
// This file encompasses the IP for the Guru series of Display controllers.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module mc_cache
(
input mclock,
input mc_rstn,
input [3:0] mc_dev_sel,
// to/from mc
input mc_local_write_req,
input mc_local_read_req,
input mc_local_burstbegin,
input [23:0] mc_local_address,
input [127:0] mc_local_wdata,
input [15:0] mc_local_be,
input [5:0] mc_local_size,
output mc_local_ready,
output reg [127:0] mc_local_rdata,
output reg mc_local_rdata_valid,
//
// to/from ddr3
//
input ddr3_ready,
input ddr3_rdata_valid,
input [255:0] ddr3_rdata,
output reg ddr3_write_req,
output reg ddr3_read_req,
output reg ddr3_burstbegin,
output reg [23:0] ddr3_address,
output reg [4:0] ddr3_size,
output reg [255:0] ddr3_wdata,
output reg [31:0] ddr3_be,
output reg ff_rdata_pop,
output local_read_empty,
output [7:0] data_fifo_used,
output [3:0] read_cmd_used,
output read_adr_0,
output [5:0] read_count_128
);
parameter READ_IDLE = 2'b00,
READ_FIRST = 2'b01,
READ_SECOND = 2'b10;
// reg ff_rdata_pop;
// wire local_read_empty;
// wire read_adr_0;
// wire [5:0] read_count_128;
reg [1:0] read_state;
reg local_word;
reg [5:0] local_size_128;
reg [5:0] read_size;
reg read_start;
reg bb_hold;
reg ddr3_burstbegin_wr;
reg [23:1] ddr3_address_wr;
reg [4:0] ddr3_size_wr;
wire [255:0] local_rdata;
wire one_word;
wire read_cmd_empty;
reg pop_read_128;
reg z_hit;
reg z_miss;
reg z_valid;
reg [22:0] z_address;
reg z_addr_0;
reg z_rdata_valid;
reg [255:0] z_cache;
wire z_load;
assign last_word = ~|local_size_128[5:1] & local_size_128[0];
assign one_word = ~|mc_local_size[5:1] & mc_local_size[0];
// Pack Data.
always @(posedge mclock, negedge mc_rstn) begin
if(!mc_rstn) begin
local_size_128 <= 6'h0;
local_word <= 1'b0;
end
else begin
ddr3_address_wr <= mc_local_address[23:1];
ddr3_size_wr <= (mc_local_size >> 1) + (mc_local_size[0] | mc_local_address[0]);
if(mc_local_burstbegin) begin
local_size_128 <= mc_local_size - 6'h1;
local_word <= ~mc_local_address[0];
end
else if(mc_local_write_req) begin
local_size_128 <= local_size_128 - 6'h1;
local_word <= ~local_word;
end
bb_hold <= 1'b0;
casex({mc_local_write_req, mc_local_burstbegin, one_word, last_word, mc_local_address[0], local_word})
// Write one word low.
6'b111x0x: begin // Mask Hi, Write Lo, We, BB.
ddr3_be[15:0] <= mc_local_be;
ddr3_be[31:16] <= 16'h0;
ddr3_wdata[127:0] <= mc_local_wdata;
ddr3_write_req <= 1'b1;
ddr3_burstbegin_wr <= 1'b1;
end
// Write one word high
6'b111x1x: begin // Write Hi, Mask Lo, We, BB.
ddr3_be[15:0] <= 16'h0;
ddr3_be[31:16] <= mc_local_be;
ddr3_wdata[255:128] <= mc_local_wdata;
ddr3_write_req <= 1'b1;
ddr3_burstbegin_wr <= 1'b1;
end
// Write first word low
6'b110x0x: begin // Write Lo, Mask hi. No We, No BB
ddr3_be[15:0] <= mc_local_be;
ddr3_wdata[127:0] <= mc_local_wdata;
ddr3_write_req <= 1'b0;
ddr3_burstbegin_wr <= 1'b0;
bb_hold <= 1'b1;
end
// Write first word high
6'b110x1x: begin // Write Hi, Mask lo. We, BB
ddr3_be[31:16] <= mc_local_be;
ddr3_be[15:0] <= 16'h0;
ddr3_wdata[255:128] <= mc_local_wdata;
ddr3_write_req <= 1'b1;
ddr3_burstbegin_wr <= 1'b1;
end
// Normal Write Low
6'b10x0x0: begin // Mask Hi, Write Lo, No We, No BB
ddr3_be[15:0] <= mc_local_be;
ddr3_wdata[127:0] <= mc_local_wdata;
ddr3_write_req <= 1'b0;
ddr3_burstbegin_wr <= 1'b0;
end
// Normal Write High, now push.
6'b10xxx1: begin
ddr3_be[31:16] <= mc_local_be;
ddr3_wdata[255:128] <= mc_local_wdata;
ddr3_write_req <= 1'b1;
ddr3_burstbegin_wr <= bb_hold;
end
// Write last word low
6'b10x1x0: begin // Mask Hi, Write Lo, We, BB
ddr3_be[15:0] <= mc_local_be;
ddr3_be[31:16] <= 16'h0;
ddr3_wdata[127:0] <= mc_local_wdata;
ddr3_write_req <= 1'b1;
ddr3_burstbegin_wr <= 1'b0;
end
default: begin
ddr3_be <= 32'hffffffff;
ddr3_write_req <= 1'b0;
ddr3_burstbegin_wr <= 1'b0;
end
endcase
end
end
// Chech for Z in the cache.
always @* z_hit = (mc_dev_sel == 4'h8) & ({z_valid, z_address} == {1'b1, mc_local_address[23:1]});
always @* z_miss = (mc_dev_sel == 4'h8) & ({z_valid, z_address} != {1'b1, mc_local_address[23:1]});
// Read Request.
// Don't request read if there is a Z hit.
always @* begin
if(mc_local_read_req & ddr3_ready & ~z_hit) begin
ddr3_read_req = 1'b1;
ddr3_burstbegin = 1'b1;
ddr3_address = mc_local_address[23:1];
ddr3_size = (mc_local_size >> 1) + (mc_local_size[0] | mc_local_address[0]);
end
else begin
ddr3_read_req = 1'b0;
ddr3_burstbegin = ddr3_burstbegin_wr;
ddr3_address = ddr3_address_wr;
ddr3_size = ddr3_size_wr;
end
end
assign mc_local_ready = ddr3_ready;
// Z Cache.
always @(posedge mclock, negedge mc_rstn) begin
if(!mc_rstn) begin
z_valid <= 1'b0;
z_address <= 23'h0;;
end
// Z miss, load the address, valid, and enable data load..
else if(~z_hit & mc_local_read_req & (mc_dev_sel == 4'h8)) begin
z_valid <= 1'b1;
z_address <= mc_local_address[23:1];
end
end
mc_cache_fifo_256 u0_read_fifo_la
(
.clock (mclock),
.aclr (~mc_rstn),
.wrreq (ddr3_rdata_valid),
.data (ddr3_rdata),
.rdreq (ff_rdata_pop),
.almost_full (),
.empty (local_read_empty),
.full (),
.usedw (data_fifo_used),
.q (local_rdata)
);
sfifo_8x16_la u_read_128
(
.aclr (~mc_rstn),
.clock (mclock),
.wrreq (mc_local_read_req & ddr3_ready),
.data ({z_miss, mc_local_address[0], {6{~z_hit}} & mc_local_size}),
.rdreq (pop_read_128),
.q ({z_load, read_adr_0, read_count_128}),
.full (),
.empty (read_cmd_empty),
.usedw (read_cmd_used),
.almost_full ()
);
// Register to hold the Z.
always @(posedge mclock, negedge mc_rstn) begin
if(!mc_rstn) z_cache <= 256'h0;
else if(z_load & ddr3_rdata_valid) z_cache <= ddr3_rdata;
end
// Unpack data.
always @(posedge mclock, negedge mc_rstn) begin
if(!mc_rstn) begin
read_state <= READ_FIRST;
read_size <= 6'h0;
read_start <= 1'b0;
z_rdata_valid <= 1'b0;
z_addr_0 <= 1'b0;
end
else begin
z_rdata_valid <= 1'b0;
case(read_state)
READ_IDLE: begin
read_start <= read_adr_0;
if(!read_cmd_empty & (read_count_128 == 6'h0)) begin // This is a Z cache hit.
read_state <= READ_IDLE;
z_rdata_valid <= 1'b1;
z_addr_0 <= read_adr_0;
end
else if(~local_read_empty) begin
if(read_adr_0) read_state <= READ_SECOND;
else read_state <= READ_FIRST;
read_size <= read_count_128;
end
else read_state <= READ_IDLE;
end
READ_FIRST: begin
// Last word to send
if((read_size == 6'h1) & ~local_read_empty) begin
read_size <= read_size - 6'h1;
read_state <= READ_IDLE;
end
// More to send.
else if((read_size != 6'h0) & ~local_read_empty) begin
read_size <= read_size - 6'h1;
read_state <= READ_SECOND;
read_start <= ~read_start;
end
// Wait for more data.
else if((read_size != 6'h0) & local_read_empty) begin
read_state <= READ_FIRST;
end
// Done.
else read_state <= READ_IDLE;
end
READ_SECOND: begin
// Last word to send
if((read_size == 6'h1) & ~local_read_empty) begin
read_size <= read_size - 6'h1;
read_state <= READ_IDLE;
end
// More to send.
else if((read_size != 6'h0) & ~local_read_empty) begin
read_size <= read_size - 6'h1;
read_state <= READ_FIRST;
read_start <= ~read_start;
end
// Wait for more data.
else if((read_size != 6'h0) & local_read_empty) begin
read_state <= READ_SECOND;
end
// Done.
else read_state <= READ_IDLE;
end
endcase
end
end
always @* pop_read_128 = ((((read_state == READ_FIRST) | (read_state == READ_SECOND)) & (read_size == 6'h1)) & ~local_read_empty) |
((read_state == READ_IDLE) & (!read_cmd_empty & (read_count_128 == 6'h0))); // This is a Z cache hit.
always @* ff_rdata_pop = (((read_state == READ_FIRST) & (read_size == 6'h1)) | (read_state == READ_SECOND)) & ~local_read_empty;
always @* mc_local_rdata = (z_rdata_valid & z_addr_0) ? z_cache[255:128] :
(z_rdata_valid & ~z_addr_0) ? z_cache[127:0] :
(read_start) ? local_rdata[255:128] : local_rdata[127:0];
always @* mc_local_rdata_valid = (((read_state == READ_FIRST) | (read_state == READ_SECOND)) & ((read_size != 6'h0) & ~local_read_empty)) | z_rdata_valid;
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 10
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module block_design_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32]" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4]" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32]" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_rready;
axi_crossbar_v2_1_10_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(128'H0000000043c100000000000043c00000),
.C_M_AXI_ADDR_WIDTH(64'H0000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_M_AXI_READ_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(64'H0000000100000001),
.C_M_AXI_READ_ISSUING(64'H0000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(2'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(2'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(2'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(2'H3),
.m_axi_ruser(2'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCON_PP_SYMBOL_V
`define SKY130_FD_SC_HS__FAHCON_PP_SYMBOL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fahcon (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT_N,
output SUM ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCON_PP_SYMBOL_V
|
module 17var_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q;
output valid;
wire [8:0] min_value = 9'd120;
wire [8:0] max_weight = 9'd60;
wire [8:0] max_volume = 9'd60;
wire [8:0] total_value =
A * 9'd4
+ B * 9'd8
+ C * 9'd0
+ D * 9'd20
+ E * 9'd10
+ F * 9'd12
+ G * 9'd18
+ H * 9'd14
+ I * 9'd6
+ J * 9'd15
+ K * 9'd30
+ L * 9'd8
+ M * 9'd16
+ N * 9'd18
+ O * 9'd18
+ P * 9'd14
+ Q * 9'd7;
wire [8:0] total_weight =
A * 9'd28
+ B * 9'd8
+ C * 9'd27
+ D * 9'd18
+ E * 9'd27
+ F * 9'd28
+ G * 9'd6
+ H * 9'd1
+ I * 9'd20
+ J * 9'd0
+ K * 9'd5
+ L * 9'd13
+ M * 9'd8
+ N * 9'd14
+ O * 9'd22
+ P * 9'd12
+ Q * 9'd23;
wire [8:0] total_volume =
A * 9'd27
+ B * 9'd27
+ C * 9'd4
+ D * 9'd4
+ E * 9'd0
+ F * 9'd24
+ G * 9'd4
+ H * 9'd20
+ I * 9'd12
+ J * 9'd15
+ K * 9'd5
+ L * 9'd2
+ M * 9'd9
+ N * 9'd28
+ O * 9'd19
+ P * 9'd18
+ Q * 9'd30;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 16:51:24 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71,
n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99,
n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110,
n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121,
n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132,
n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143,
n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154,
n155, n156, n157, n158, n159, n160, n161, n162, n163, n164, n165,
n166, n167, n168, n169, n170, n171, n172, n173, n174, n175, n176,
n177, n178, n179, n180, n181, n182, n183, n184;
OA21XLTS U74 ( .A0(n181), .A1(n183), .B0(n161), .Y(n131) );
NAND2X1TS U75 ( .A(n64), .B(n63), .Y(n182) );
NAND2X1TS U76 ( .A(n117), .B(in1[3]), .Y(n161) );
XNOR2X2TS U77 ( .A(n69), .B(in2[15]), .Y(n112) );
NAND2X1TS U78 ( .A(n100), .B(in1[10]), .Y(n136) );
NAND2X1TS U79 ( .A(n70), .B(add_sub), .Y(n71) );
NAND2X1TS U80 ( .A(in1[2]), .B(n59), .Y(n181) );
CMPR32X2TS U81 ( .A(n157), .B(in1[7]), .C(n156), .CO(n170), .S(res[7]) );
XOR2X2TS U82 ( .A(n73), .B(in2[13]), .Y(n107) );
NOR2X1TS U83 ( .A(n72), .B(n101), .Y(n73) );
NAND2XLTS U84 ( .A(n98), .B(add_sub), .Y(n99) );
NOR2XLTS U85 ( .A(n102), .B(n101), .Y(n103) );
XOR2X2TS U86 ( .A(n91), .B(in2[9]), .Y(n95) );
NOR2X1TS U87 ( .A(n90), .B(n101), .Y(n91) );
INVX2TS U88 ( .A(add_sub), .Y(n101) );
NOR2XLTS U89 ( .A(n101), .B(n60), .Y(n61) );
XOR2X1TS U90 ( .A(n103), .B(in2[11]), .Y(n104) );
NAND2X1TS U91 ( .A(n106), .B(in1[12]), .Y(n145) );
NOR2X6TS U92 ( .A(n92), .B(in2[8]), .Y(n90) );
NAND2X2TS U93 ( .A(n79), .B(add_sub), .Y(n80) );
NAND2X2TS U94 ( .A(n177), .B(n176), .Y(n178) );
XNOR2X2TS U95 ( .A(n75), .B(in2[12]), .Y(n106) );
NAND2X2TS U96 ( .A(n74), .B(add_sub), .Y(n75) );
NOR2X6TS U97 ( .A(n79), .B(in2[6]), .Y(n77) );
AO21X2TS U98 ( .A0(n114), .A1(n174), .B0(n113), .Y(res[16]) );
XOR2X1TS U99 ( .A(n155), .B(n154), .Y(res[13]) );
AOI21X2TS U100 ( .A0(n151), .A1(n150), .B0(n149), .Y(n155) );
NAND2X2TS U101 ( .A(n107), .B(in1[13]), .Y(n152) );
XOR2X1TS U102 ( .A(n129), .B(n128), .Y(res[9]) );
XNOR2X2TS U103 ( .A(n99), .B(in2[10]), .Y(n100) );
XOR2X1TS U104 ( .A(n166), .B(n165), .Y(res[6]) );
XNOR2X2TS U105 ( .A(n93), .B(in2[8]), .Y(n94) );
XOR2X1TS U106 ( .A(n121), .B(n158), .Y(res[5]) );
NOR2X1TS U107 ( .A(n164), .B(n163), .Y(n165) );
AND2X2TS U108 ( .A(n88), .B(in1[6]), .Y(n163) );
OA21XLTS U109 ( .A0(n64), .A1(n63), .B0(n182), .Y(res[2]) );
INVX1TS U110 ( .A(n158), .Y(n162) );
XOR2XLTS U111 ( .A(n180), .B(n122), .Y(res[1]) );
XOR2X1TS U112 ( .A(n130), .B(in1[1]), .Y(n122) );
OAI21X1TS U113 ( .A0(n180), .A1(in1[1]), .B0(n130), .Y(n62) );
AOI2BB1XLTS U114 ( .A0N(in2[0]), .A1N(in1[0]), .B0(n180), .Y(res[0]) );
OAI21X1TS U115 ( .A0(in2[1]), .A1(in2[0]), .B0(add_sub), .Y(n58) );
OAI21X1TS U116 ( .A0(n131), .A1(n160), .B0(n119), .Y(n121) );
NAND2X4TS U117 ( .A(n118), .B(in1[4]), .Y(n119) );
XNOR2X2TS U118 ( .A(n116), .B(in2[3]), .Y(n117) );
NAND2BX4TS U119 ( .AN(in2[7]), .B(n77), .Y(n92) );
XNOR2X2TS U120 ( .A(n82), .B(in2[4]), .Y(n118) );
NAND2X1TS U121 ( .A(n81), .B(add_sub), .Y(n82) );
XNOR2X2TS U122 ( .A(n84), .B(in2[5]), .Y(n120) );
NAND2X2TS U123 ( .A(n92), .B(add_sub), .Y(n93) );
NOR2BX2TS U124 ( .AN(in1[0]), .B(n60), .Y(n180) );
OAI21X2TS U125 ( .A0(n118), .A1(in1[4]), .B0(n119), .Y(n160) );
INVX2TS U126 ( .A(n167), .Y(n124) );
NAND2BX2TS U127 ( .AN(in2[13]), .B(n72), .Y(n70) );
INVX2TS U128 ( .A(n163), .Y(n89) );
NAND2X1TS U129 ( .A(n168), .B(n167), .Y(n169) );
XOR2XLTS U130 ( .A(n139), .B(n138), .Y(res[10]) );
NAND2X1TS U131 ( .A(n150), .B(n145), .Y(n146) );
NOR2X4TS U132 ( .A(n95), .B(in1[9]), .Y(n125) );
AOI21X2TS U133 ( .A0(n89), .A1(n159), .B0(n164), .Y(n156) );
NOR2X4TS U134 ( .A(n112), .B(in1[15]), .Y(n175) );
OAI21X4TS U135 ( .A0(n110), .A1(n144), .B0(n109), .Y(n174) );
AOI21X4TS U136 ( .A0(n143), .A1(n141), .B0(n105), .Y(n144) );
AOI21X2TS U137 ( .A0(n153), .A1(n149), .B0(n108), .Y(n109) );
NAND2BX4TS U138 ( .AN(in2[9]), .B(n90), .Y(n98) );
XNOR2X4TS U139 ( .A(n71), .B(in2[14]), .Y(n111) );
OAI21X4TS U140 ( .A0(n119), .A1(n85), .B0(n120), .Y(n86) );
XNOR2X4TS U141 ( .A(n80), .B(in2[6]), .Y(n88) );
XNOR2X1TS U142 ( .A(n58), .B(in2[2]), .Y(n59) );
OAI21X1TS U143 ( .A0(in1[2]), .A1(n59), .B0(n181), .Y(n133) );
INVX2TS U144 ( .A(n133), .Y(n64) );
INVX4TS U145 ( .A(in2[0]), .Y(n60) );
CLKXOR2X2TS U146 ( .A(n61), .B(in2[1]), .Y(n130) );
OAI2BB1X1TS U147 ( .A0N(n180), .A1N(in1[1]), .B0(n62), .Y(n63) );
INVX2TS U148 ( .A(in2[1]), .Y(n67) );
INVX2TS U149 ( .A(in2[2]), .Y(n66) );
INVX2TS U150 ( .A(in2[3]), .Y(n65) );
NAND4X4TS U151 ( .A(n60), .B(n67), .C(n66), .D(n65), .Y(n81) );
NOR2X4TS U152 ( .A(n81), .B(in2[4]), .Y(n83) );
INVX2TS U153 ( .A(in2[5]), .Y(n68) );
NAND2X4TS U154 ( .A(n83), .B(n68), .Y(n79) );
NOR2X4TS U155 ( .A(n98), .B(in2[10]), .Y(n102) );
NAND2BX4TS U156 ( .AN(in2[11]), .B(n102), .Y(n74) );
NOR2X4TS U157 ( .A(n74), .B(in2[12]), .Y(n72) );
OAI21X1TS U158 ( .A0(n70), .A1(in2[14]), .B0(add_sub), .Y(n69) );
NOR2X2TS U159 ( .A(n111), .B(in1[14]), .Y(n147) );
NOR2X1TS U160 ( .A(n175), .B(n147), .Y(n114) );
OR2X2TS U161 ( .A(n107), .B(in1[13]), .Y(n153) );
NOR2X1TS U162 ( .A(n106), .B(in1[12]), .Y(n76) );
INVX2TS U163 ( .A(n76), .Y(n150) );
NAND2X2TS U164 ( .A(n153), .B(n150), .Y(n110) );
NOR2X1TS U165 ( .A(n77), .B(n101), .Y(n78) );
XOR2X1TS U166 ( .A(n78), .B(in2[7]), .Y(n157) );
INVX2TS U167 ( .A(n119), .Y(n87) );
INVX2TS U168 ( .A(in1[5]), .Y(n85) );
NOR2X1TS U169 ( .A(n83), .B(n101), .Y(n84) );
OAI21X4TS U170 ( .A0(n87), .A1(in1[5]), .B0(n86), .Y(n159) );
NOR2X2TS U171 ( .A(n88), .B(in1[6]), .Y(n164) );
NOR2X2TS U172 ( .A(n94), .B(in1[8]), .Y(n123) );
NOR2X1TS U173 ( .A(n125), .B(n123), .Y(n97) );
NAND2X2TS U174 ( .A(n94), .B(in1[8]), .Y(n167) );
NAND2X2TS U175 ( .A(n95), .B(in1[9]), .Y(n126) );
OAI21X1TS U176 ( .A0(n125), .A1(n167), .B0(n126), .Y(n96) );
AOI21X4TS U177 ( .A0(n170), .A1(n97), .B0(n96), .Y(n139) );
NOR2X2TS U178 ( .A(n100), .B(in1[10]), .Y(n135) );
OAI21X4TS U179 ( .A0(n139), .A1(n135), .B0(n136), .Y(n143) );
OR2X2TS U180 ( .A(n104), .B(in1[11]), .Y(n141) );
NAND2X2TS U181 ( .A(n104), .B(in1[11]), .Y(n140) );
INVX2TS U182 ( .A(n140), .Y(n105) );
INVX2TS U183 ( .A(n145), .Y(n149) );
INVX2TS U184 ( .A(n152), .Y(n108) );
NAND2X2TS U185 ( .A(n111), .B(in1[14]), .Y(n171) );
NAND2X2TS U186 ( .A(n112), .B(in1[15]), .Y(n176) );
OAI21X1TS U187 ( .A0(n175), .A1(n171), .B0(n176), .Y(n113) );
OR3X1TS U188 ( .A(in2[2]), .B(in2[1]), .C(in2[0]), .Y(n115) );
NAND2X1TS U189 ( .A(add_sub), .B(n115), .Y(n116) );
OAI21X2TS U190 ( .A0(n117), .A1(in1[3]), .B0(n161), .Y(n183) );
XNOR2X1TS U191 ( .A(n120), .B(in1[5]), .Y(n158) );
INVX2TS U192 ( .A(n123), .Y(n168) );
AOI21X1TS U193 ( .A0(n170), .A1(n168), .B0(n124), .Y(n129) );
INVX2TS U194 ( .A(n125), .Y(n127) );
NAND2X1TS U195 ( .A(n127), .B(n126), .Y(n128) );
NAND2X1TS U196 ( .A(n130), .B(in1[1]), .Y(n132) );
OAI31X1TS U197 ( .A0(n133), .A1(n183), .A2(n132), .B0(n131), .Y(n134) );
XNOR2X1TS U198 ( .A(n134), .B(n160), .Y(res[4]) );
INVX2TS U199 ( .A(n135), .Y(n137) );
NAND2X1TS U200 ( .A(n137), .B(n136), .Y(n138) );
NAND2X1TS U201 ( .A(n141), .B(n140), .Y(n142) );
XNOR2X1TS U202 ( .A(n143), .B(n142), .Y(res[11]) );
INVX2TS U203 ( .A(n144), .Y(n151) );
XNOR2X1TS U204 ( .A(n151), .B(n146), .Y(res[12]) );
INVX2TS U205 ( .A(n147), .Y(n173) );
NAND2X1TS U206 ( .A(n173), .B(n171), .Y(n148) );
XNOR2X1TS U207 ( .A(n174), .B(n148), .Y(res[14]) );
NAND2X1TS U208 ( .A(n153), .B(n152), .Y(n154) );
OAI31X1TS U209 ( .A0(n162), .A1(n161), .A2(n160), .B0(n159), .Y(n166) );
XNOR2X1TS U210 ( .A(n170), .B(n169), .Y(res[8]) );
INVX2TS U211 ( .A(n171), .Y(n172) );
AOI21X4TS U212 ( .A0(n174), .A1(n173), .B0(n172), .Y(n179) );
INVX2TS U213 ( .A(n175), .Y(n177) );
XOR2X1TS U214 ( .A(n179), .B(n178), .Y(res[15]) );
NAND2X1TS U215 ( .A(n182), .B(n181), .Y(n184) );
XNOR2X1TS U216 ( .A(n184), .B(n183), .Y(res[3]) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_GDAN8M8P3_syn.sdf");
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Hantek HDG2000 FPGA
*/
module fpga_core
(
// clocks
input wire clk_250mhz_int,
input wire rst_250mhz_int,
input wire clk_250mhz,
input wire rst_250mhz,
input wire clk_10mhz,
input wire rst_10mhz,
input wire ext_clock_selected,
// SoC interface
input wire cntrl_cs,
input wire cntrl_sck,
input wire cntrl_mosi,
output wire cntrl_miso,
// Trigger
input wire ext_trig,
// Frequency counter
input wire ext_prescale,
// Front end relay control
output wire ferc_dat,
output wire ferc_clk,
output wire ferc_lat,
// Analog mux
output wire [2:0] mux_s,
// ADC
output wire adc_sclk,
input wire adc_sdo,
output wire adc_sdi,
output wire adc_cs,
input wire adc_eoc,
output wire adc_convst,
// digital output
output wire [15:0] dout,
// Sync DAC
output wire [7:0] sync_dac,
// Main DAC
output wire dac_clk,
output wire [15:0] dac_p1_d,
output wire [15:0] dac_p2_d,
input wire dac_sdo,
output wire dac_sdio,
output wire dac_sclk,
output wire dac_csb,
output wire dac_reset,
// ram 1 MCB (U8)
input wire ram1_calib_done,
output wire ram1_p0_cmd_clk,
output wire ram1_p0_cmd_en,
output wire [2:0] ram1_p0_cmd_instr,
output wire [5:0] ram1_p0_cmd_bl,
output wire [31:0] ram1_p0_cmd_byte_addr,
input wire ram1_p0_cmd_empty,
input wire ram1_p0_cmd_full,
output wire ram1_p0_wr_clk,
output wire ram1_p0_wr_en,
output wire [3:0] ram1_p0_wr_mask,
output wire [31:0] ram1_p0_wr_data,
input wire ram1_p0_wr_empty,
input wire ram1_p0_wr_full,
input wire ram1_p0_wr_underrun,
input wire [6:0] ram1_p0_wr_count,
input wire ram1_p0_wr_error,
output wire ram1_p0_rd_clk,
output wire ram1_p0_rd_en,
input wire [31:0] ram1_p0_rd_data,
input wire ram1_p0_rd_empty,
input wire ram1_p0_rd_full,
input wire ram1_p0_rd_overflow,
input wire [6:0] ram1_p0_rd_count,
input wire ram1_p0_rd_error,
output wire ram1_p1_cmd_clk,
output wire ram1_p1_cmd_en,
output wire [2:0] ram1_p1_cmd_instr,
output wire [5:0] ram1_p1_cmd_bl,
output wire [31:0] ram1_p1_cmd_byte_addr,
input wire ram1_p1_cmd_empty,
input wire ram1_p1_cmd_full,
output wire ram1_p1_wr_clk,
output wire ram1_p1_wr_en,
output wire [3:0] ram1_p1_wr_mask,
output wire [31:0] ram1_p1_wr_data,
input wire ram1_p1_wr_empty,
input wire ram1_p1_wr_full,
input wire ram1_p1_wr_underrun,
input wire [6:0] ram1_p1_wr_count,
input wire ram1_p1_wr_error,
output wire ram1_p1_rd_clk,
output wire ram1_p1_rd_en,
input wire [31:0] ram1_p1_rd_data,
input wire ram1_p1_rd_empty,
input wire ram1_p1_rd_full,
input wire ram1_p1_rd_overflow,
input wire [6:0] ram1_p1_rd_count,
input wire ram1_p1_rd_error,
output wire ram1_p2_cmd_clk,
output wire ram1_p2_cmd_en,
output wire [2:0] ram1_p2_cmd_instr,
output wire [5:0] ram1_p2_cmd_bl,
output wire [31:0] ram1_p2_cmd_byte_addr,
input wire ram1_p2_cmd_empty,
input wire ram1_p2_cmd_full,
output wire ram1_p2_rd_clk,
output wire ram1_p2_rd_en,
input wire [31:0] ram1_p2_rd_data,
input wire ram1_p2_rd_empty,
input wire ram1_p2_rd_full,
input wire ram1_p2_rd_overflow,
input wire [6:0] ram1_p2_rd_count,
input wire ram1_p2_rd_error,
output wire ram1_p3_cmd_clk,
output wire ram1_p3_cmd_en,
output wire [2:0] ram1_p3_cmd_instr,
output wire [5:0] ram1_p3_cmd_bl,
output wire [31:0] ram1_p3_cmd_byte_addr,
input wire ram1_p3_cmd_empty,
input wire ram1_p3_cmd_full,
output wire ram1_p3_rd_clk,
output wire ram1_p3_rd_en,
input wire [31:0] ram1_p3_rd_data,
input wire ram1_p3_rd_empty,
input wire ram1_p3_rd_full,
input wire ram1_p3_rd_overflow,
input wire [6:0] ram1_p3_rd_count,
input wire ram1_p3_rd_error,
output wire ram1_p4_cmd_clk,
output wire ram1_p4_cmd_en,
output wire [2:0] ram1_p4_cmd_instr,
output wire [5:0] ram1_p4_cmd_bl,
output wire [31:0] ram1_p4_cmd_byte_addr,
input wire ram1_p4_cmd_empty,
input wire ram1_p4_cmd_full,
output wire ram1_p4_rd_clk,
output wire ram1_p4_rd_en,
input wire [31:0] ram1_p4_rd_data,
input wire ram1_p4_rd_empty,
input wire ram1_p4_rd_full,
input wire ram1_p4_rd_overflow,
input wire [6:0] ram1_p4_rd_count,
input wire ram1_p4_rd_error,
output wire ram1_p5_cmd_clk,
output wire ram1_p5_cmd_en,
output wire [2:0] ram1_p5_cmd_instr,
output wire [5:0] ram1_p5_cmd_bl,
output wire [31:0] ram1_p5_cmd_byte_addr,
input wire ram1_p5_cmd_empty,
input wire ram1_p5_cmd_full,
output wire ram1_p5_rd_clk,
output wire ram1_p5_rd_en,
input wire [31:0] ram1_p5_rd_data,
input wire ram1_p5_rd_empty,
input wire ram1_p5_rd_full,
input wire ram1_p5_rd_overflow,
input wire [6:0] ram1_p5_rd_count,
input wire ram1_p5_rd_error,
// ram 2 MCB (U12)
input wire ram2_calib_done,
output wire ram2_p0_cmd_clk,
output wire ram2_p0_cmd_en,
output wire [2:0] ram2_p0_cmd_instr,
output wire [5:0] ram2_p0_cmd_bl,
output wire [31:0] ram2_p0_cmd_byte_addr,
input wire ram2_p0_cmd_empty,
input wire ram2_p0_cmd_full,
output wire ram2_p0_wr_clk,
output wire ram2_p0_wr_en,
output wire [3:0] ram2_p0_wr_mask,
output wire [31:0] ram2_p0_wr_data,
input wire ram2_p0_wr_empty,
input wire ram2_p0_wr_full,
input wire ram2_p0_wr_underrun,
input wire [6:0] ram2_p0_wr_count,
input wire ram2_p0_wr_error,
output wire ram2_p0_rd_clk,
output wire ram2_p0_rd_en,
input wire [31:0] ram2_p0_rd_data,
input wire ram2_p0_rd_empty,
input wire ram2_p0_rd_full,
input wire ram2_p0_rd_overflow,
input wire [6:0] ram2_p0_rd_count,
input wire ram2_p0_rd_error,
output wire ram2_p1_cmd_clk,
output wire ram2_p1_cmd_en,
output wire [2:0] ram2_p1_cmd_instr,
output wire [5:0] ram2_p1_cmd_bl,
output wire [31:0] ram2_p1_cmd_byte_addr,
input wire ram2_p1_cmd_empty,
input wire ram2_p1_cmd_full,
output wire ram2_p1_wr_clk,
output wire ram2_p1_wr_en,
output wire [3:0] ram2_p1_wr_mask,
output wire [31:0] ram2_p1_wr_data,
input wire ram2_p1_wr_empty,
input wire ram2_p1_wr_full,
input wire ram2_p1_wr_underrun,
input wire [6:0] ram2_p1_wr_count,
input wire ram2_p1_wr_error,
output wire ram2_p1_rd_clk,
output wire ram2_p1_rd_en,
input wire [31:0] ram2_p1_rd_data,
input wire ram2_p1_rd_empty,
input wire ram2_p1_rd_full,
input wire ram2_p1_rd_overflow,
input wire [6:0] ram2_p1_rd_count,
input wire ram2_p1_rd_error,
output wire ram2_p2_cmd_clk,
output wire ram2_p2_cmd_en,
output wire [2:0] ram2_p2_cmd_instr,
output wire [5:0] ram2_p2_cmd_bl,
output wire [31:0] ram2_p2_cmd_byte_addr,
input wire ram2_p2_cmd_empty,
input wire ram2_p2_cmd_full,
output wire ram2_p2_rd_clk,
output wire ram2_p2_rd_en,
input wire [31:0] ram2_p2_rd_data,
input wire ram2_p2_rd_empty,
input wire ram2_p2_rd_full,
input wire ram2_p2_rd_overflow,
input wire [6:0] ram2_p2_rd_count,
input wire ram2_p2_rd_error,
output wire ram2_p3_cmd_clk,
output wire ram2_p3_cmd_en,
output wire [2:0] ram2_p3_cmd_instr,
output wire [5:0] ram2_p3_cmd_bl,
output wire [31:0] ram2_p3_cmd_byte_addr,
input wire ram2_p3_cmd_empty,
input wire ram2_p3_cmd_full,
output wire ram2_p3_rd_clk,
output wire ram2_p3_rd_en,
input wire [31:0] ram2_p3_rd_data,
input wire ram2_p3_rd_empty,
input wire ram2_p3_rd_full,
input wire ram2_p3_rd_overflow,
input wire [6:0] ram2_p3_rd_count,
input wire ram2_p3_rd_error,
output wire ram2_p4_cmd_clk,
output wire ram2_p4_cmd_en,
output wire [2:0] ram2_p4_cmd_instr,
output wire [5:0] ram2_p4_cmd_bl,
output wire [31:0] ram2_p4_cmd_byte_addr,
input wire ram2_p4_cmd_empty,
input wire ram2_p4_cmd_full,
output wire ram2_p4_rd_clk,
output wire ram2_p4_rd_en,
input wire [31:0] ram2_p4_rd_data,
input wire ram2_p4_rd_empty,
input wire ram2_p4_rd_full,
input wire ram2_p4_rd_overflow,
input wire [6:0] ram2_p4_rd_count,
input wire ram2_p4_rd_error,
output wire ram2_p5_cmd_clk,
output wire ram2_p5_cmd_en,
output wire [2:0] ram2_p5_cmd_instr,
output wire [5:0] ram2_p5_cmd_bl,
output wire [31:0] ram2_p5_cmd_byte_addr,
input wire ram2_p5_cmd_empty,
input wire ram2_p5_cmd_full,
output wire ram2_p5_rd_clk,
output wire ram2_p5_rd_en,
input wire [31:0] ram2_p5_rd_data,
input wire ram2_p5_rd_empty,
input wire ram2_p5_rd_full,
input wire ram2_p5_rd_overflow,
input wire [6:0] ram2_p5_rd_count,
input wire ram2_p5_rd_error
);
reg [15:0] count = 0;
assign ferc_dat = 0;
assign ferc_lat = 0;
assign ferc_clk = 0;
assign mux_s = 0;
assign adc_sclk = 0;
assign adc_sdi = 0;
assign adc_cs = 0;
assign adc_convst = 0;
assign dac_clk = clk_250mhz;
reg [15:0] dac_p1_d_reg = 0;
reg [15:0] dac_p2_d_reg = 0;
always @(posedge clk_250mhz) begin
dac_p1_d_reg <= count;
dac_p2_d_reg <= -count;
end
assign dac_p1_d = dac_p1_d_reg;
assign dac_p2_d = dac_p2_d_reg;
assign dac_sdio = 0;
assign dac_sclk = 0;
assign dac_csb = 0;
assign dac_reset = 0;
assign sync_dac = count[15:8];
assign dout = count;
always @(posedge clk_250mhz) begin
count <= count + 1;
end
/////////////////////////////////////////////////
// //
// DDR2 RX path SRL FIFOs //
// //
/////////////////////////////////////////////////
// These help timing closure with the MCB read data path since Tmcbcko_RDDATA
// is a very high 2.7 ns. A LUT in SRL mode has a very low Tds of 90 ps,
// compared to a LUT in RAM mode (Tds 730 ps) or a FF (Tdick 470 ps).
wire ram1_p0_rd_en_fifo;
wire [31:0] ram1_p0_rd_data_fifo;
wire ram1_p0_rd_empty_fifo;
wire ram1_p0_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram1_p0_rd_fifo (
.clk(ram1_p0_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram1_p0_rd_empty),
.write_data(ram1_p0_rd_data),
.read_en(ram1_p0_rd_en_fifo),
.read_data(ram1_p0_rd_data_fifo),
.full(ram1_p0_rd_full_fifo),
.empty(ram1_p0_rd_empty_fifo)
);
assign ram1_p0_rd_en = ~ram1_p0_rd_full;
wire ram1_p1_rd_en_fifo;
wire [31:0] ram1_p1_rd_data_fifo;
wire ram1_p1_rd_empty_fifo;
wire ram1_p1_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram1_p1_rd_fifo (
.clk(ram1_p1_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram1_p1_rd_empty),
.write_data(ram1_p1_rd_data),
.read_en(ram1_p1_rd_en_fifo),
.read_data(ram1_p1_rd_data_fifo),
.full(ram1_p1_rd_full_fifo),
.empty(ram1_p1_rd_empty_fifo)
);
assign ram1_p1_rd_en = ~ram1_p1_rd_full;
wire ram1_p2_rd_en_fifo;
wire [31:0] ram1_p2_rd_data_fifo;
wire ram1_p2_rd_empty_fifo;
wire ram1_p2_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram1_p2_rd_fifo (
.clk(ram1_p2_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram1_p2_rd_empty),
.write_data(ram1_p2_rd_data),
.read_en(ram1_p2_rd_en_fifo),
.read_data(ram1_p2_rd_data_fifo),
.full(ram1_p2_rd_full_fifo),
.empty(ram1_p2_rd_empty_fifo)
);
assign ram1_p2_rd_en = ~ram1_p2_rd_full;
wire ram1_p3_rd_en_fifo;
wire [31:0] ram1_p3_rd_data_fifo;
wire ram1_p3_rd_empty_fifo;
wire ram1_p3_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram1_p3_rd_fifo (
.clk(ram1_p3_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram1_p3_rd_empty),
.write_data(ram1_p3_rd_data),
.read_en(ram1_p3_rd_en_fifo),
.read_data(ram1_p3_rd_data_fifo),
.full(ram1_p3_rd_full_fifo),
.empty(ram1_p3_rd_empty_fifo)
);
assign ram1_p3_rd_en = ~ram1_p3_rd_full;
wire ram1_p4_rd_en_fifo;
wire [31:0] ram1_p4_rd_data_fifo;
wire ram1_p4_rd_empty_fifo;
wire ram1_p4_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram1_p4_rd_fifo (
.clk(ram1_p4_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram1_p4_rd_empty),
.write_data(ram1_p4_rd_data),
.read_en(ram1_p4_rd_en_fifo),
.read_data(ram1_p4_rd_data_fifo),
.full(ram1_p4_rd_full_fifo),
.empty(ram1_p4_rd_empty_fifo)
);
assign ram1_p4_rd_en = ~ram1_p4_rd_full;
wire ram1_p5_rd_en_fifo;
wire [31:0] ram1_p5_rd_data_fifo;
wire ram1_p5_rd_empty_fifo;
wire ram1_p5_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram1_p5_rd_fifo (
.clk(ram1_p5_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram1_p5_rd_empty),
.write_data(ram1_p5_rd_data),
.read_en(ram1_p5_rd_en_fifo),
.read_data(ram1_p5_rd_data_fifo),
.full(ram1_p5_rd_full_fifo),
.empty(ram1_p5_rd_empty_fifo)
);
assign ram1_p5_rd_en = ~ram1_p5_rd_full;
wire ram2_p0_rd_en_fifo;
wire [31:0] ram2_p0_rd_data_fifo;
wire ram2_p0_rd_empty_fifo;
wire ram2_p0_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram2_p0_rd_fifo (
.clk(ram2_p0_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram2_p0_rd_empty),
.write_data(ram2_p0_rd_data),
.read_en(ram2_p0_rd_en_fifo),
.read_data(ram2_p0_rd_data_fifo),
.full(ram2_p0_rd_full_fifo),
.empty(ram2_p0_rd_empty_fifo)
);
assign ram2_p0_rd_en = ~ram2_p0_rd_full;
wire ram2_p1_rd_en_fifo;
wire [31:0] ram2_p1_rd_data_fifo;
wire ram2_p1_rd_empty_fifo;
wire ram2_p1_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram2_p1_rd_fifo (
.clk(ram2_p1_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram2_p1_rd_empty),
.write_data(ram2_p1_rd_data),
.read_en(ram2_p1_rd_en_fifo),
.read_data(ram2_p1_rd_data_fifo),
.full(ram2_p1_rd_full_fifo),
.empty(ram2_p1_rd_empty_fifo)
);
assign ram2_p1_rd_en = ~ram2_p1_rd_full;
wire ram2_p2_rd_en_fifo;
wire [31:0] ram2_p2_rd_data_fifo;
wire ram2_p2_rd_empty_fifo;
wire ram2_p2_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram2_p2_rd_fifo (
.clk(ram2_p2_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram2_p2_rd_empty),
.write_data(ram2_p2_rd_data),
.read_en(ram2_p2_rd_en_fifo),
.read_data(ram2_p2_rd_data_fifo),
.full(ram2_p2_rd_full_fifo),
.empty(ram2_p2_rd_empty_fifo)
);
assign ram2_p2_rd_en = ~ram2_p2_rd_full;
wire ram2_p3_rd_en_fifo;
wire [31:0] ram2_p3_rd_data_fifo;
wire ram2_p3_rd_empty_fifo;
wire ram2_p3_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram2_p3_rd_fifo (
.clk(ram2_p3_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram2_p3_rd_empty),
.write_data(ram2_p3_rd_data),
.read_en(ram2_p3_rd_en_fifo),
.read_data(ram2_p3_rd_data_fifo),
.full(ram2_p3_rd_full_fifo),
.empty(ram2_p3_rd_empty_fifo)
);
assign ram2_p3_rd_en = ~ram2_p3_rd_full;
wire ram2_p4_rd_en_fifo;
wire [31:0] ram2_p4_rd_data_fifo;
wire ram2_p4_rd_empty_fifo;
wire ram2_p4_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram2_p4_rd_fifo (
.clk(ram2_p4_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram2_p4_rd_empty),
.write_data(ram2_p4_rd_data),
.read_en(ram2_p4_rd_en_fifo),
.read_data(ram2_p4_rd_data_fifo),
.full(ram2_p4_rd_full_fifo),
.empty(ram2_p4_rd_empty_fifo)
);
assign ram2_p4_rd_en = ~ram2_p4_rd_full;
wire ram2_p5_rd_en_fifo;
wire [31:0] ram2_p5_rd_data_fifo;
wire ram2_p5_rd_empty_fifo;
wire ram2_p5_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram2_p5_rd_fifo (
.clk(ram2_p5_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram2_p5_rd_empty),
.write_data(ram2_p5_rd_data),
.read_en(ram2_p5_rd_en_fifo),
.read_data(ram2_p5_rd_data_fifo),
.full(ram2_p5_rd_full_fifo),
.empty(ram2_p5_rd_empty_fifo)
);
assign ram2_p5_rd_en = ~ram2_p5_rd_full;
/////////////////////////////////////////////////
// //
// SoC Interface //
// //
/////////////////////////////////////////////////
wire [7:0] cntrl_rx_tdata;
wire cntrl_rx_tvalid;
wire cntrl_rx_tready;
wire cntrl_rx_tlast;
wire [7:0] cntrl_tx_tdata;
wire cntrl_tx_tvalid;
wire cntrl_tx_tready;
wire cntrl_tx_tlast;
wire [35:0] wbm_adr_o;
wire [7:0] wbm_dat_i;
wire [7:0] wbm_dat_o;
wire wbm_we_o;
wire wbm_stb_o;
wire wbm_ack_i;
wire wbm_err_i;
wire wbm_cyc_o;
wire [31:0] ram1_wb_adr_i;
wire [7:0] ram1_wb_dat_i;
wire [7:0] ram1_wb_dat_o;
wire ram1_wb_we_i;
wire ram1_wb_stb_i;
wire ram1_wb_ack_o;
wire ram1_wb_err_o;
wire ram1_wb_cyc_i;
wire [31:0] ram2_wb_adr_i;
wire [7:0] ram2_wb_dat_i;
wire [7:0] ram2_wb_dat_o;
wire ram2_wb_we_i;
wire ram2_wb_stb_i;
wire ram2_wb_ack_o;
wire ram2_wb_err_o;
wire ram2_wb_cyc_i;
wire [31:0] ctrl_wb_adr_i;
wire [7:0] ctrl_wb_dat_i;
wire [7:0] ctrl_wb_dat_o;
wire ctrl_wb_we_i;
wire ctrl_wb_stb_i;
wire ctrl_wb_ack_o;
wire ctrl_wb_err_o;
wire ctrl_wb_cyc_i;
wire [31:0] ctrl_int_wb_adr_i;
wire [7:0] ctrl_int_wb_dat_i;
wire [7:0] ctrl_int_wb_dat_o;
wire ctrl_int_wb_we_i;
wire ctrl_int_wb_stb_i;
wire ctrl_int_wb_ack_o;
wire ctrl_int_wb_err_o;
wire ctrl_int_wb_cyc_i;
axis_spi_slave #(
.DATA_WIDTH(8)
)
spi_slave_inst (
.clk(clk_250mhz_int),
.rst(rst_250mhz_int),
// axi input
.input_axis_tdata(cntrl_tx_tdata),
.input_axis_tvalid(cntrl_tx_tvalid),
.input_axis_tready(cntrl_tx_tready),
.input_axis_tlast(cntrl_tx_tlast),
// axi output
.output_axis_tdata(cntrl_rx_tdata),
.output_axis_tvalid(cntrl_rx_tvalid),
.output_axis_tready(cntrl_rx_tready),
.output_axis_tlast(cntrl_rx_tlast),
// spi interface
.cs(cntrl_cs),
.sck(cntrl_sck),
.mosi(cntrl_mosi),
.miso(cntrl_miso),
// status
.busy()
);
soc_interface_wb_8
soc_interface_wb_inst (
.clk(clk_250mhz_int),
.rst(rst_250mhz_int),
// axi input
.input_axis_tdata(cntrl_rx_tdata),
.input_axis_tvalid(cntrl_rx_tvalid),
.input_axis_tready(cntrl_rx_tready),
.input_axis_tlast(cntrl_rx_tlast),
// axi output
.output_axis_tdata(cntrl_tx_tdata),
.output_axis_tvalid(cntrl_tx_tvalid),
.output_axis_tready(cntrl_tx_tready),
.output_axis_tlast(cntrl_tx_tlast),
// wb interface
.wb_adr_o(wbm_adr_o),
.wb_dat_i(wbm_dat_i),
.wb_dat_o(wbm_dat_o),
.wb_we_o(wbm_we_o),
.wb_stb_o(wbm_stb_o),
.wb_ack_i(wbm_ack_i),
.wb_err_i(wbm_err_i),
.wb_cyc_o(wbm_cyc_o),
// status
.busy()
);
wb_mux_3 #(
.DATA_WIDTH(8),
.ADDR_WIDTH(36)
)
wb_mux_inst (
.clk(clk_250mhz_int),
.rst(rst_250mhz_int),
// from SoC interface
.wbm_adr_i(wbm_adr_o),
.wbm_dat_i(wbm_dat_o),
.wbm_dat_o(wbm_dat_i),
.wbm_we_i(wbm_we_o),
.wbm_sel_i(1),
.wbm_stb_i(wbm_stb_o),
.wbm_ack_o(wbm_ack_i),
.wbm_err_o(wbm_err_i),
.wbm_rty_o(),
.wbm_cyc_i(wbm_cyc_o),
// MCB 1
.wbs0_adr_o(ram1_wb_adr_i),
.wbs0_dat_i(ram1_wb_dat_o),
.wbs0_dat_o(ram1_wb_dat_i),
.wbs0_we_o(ram1_wb_we_i),
.wbs0_sel_o(),
.wbs0_stb_o(ram1_wb_stb_i),
.wbs0_ack_i(ram1_wb_ack_o),
.wbs0_err_i(ram1_wb_err_o),
.wbs0_rty_i(0),
.wbs0_cyc_o(ram1_wb_cyc_i),
.wbs0_addr(36'h000000000),
.wbs0_addr_msk(36'hF00000000),
// MCB 2
.wbs1_adr_o(ram2_wb_adr_i),
.wbs1_dat_i(ram2_wb_dat_o),
.wbs1_dat_o(ram2_wb_dat_i),
.wbs1_we_o(ram2_wb_we_i),
.wbs1_sel_o(),
.wbs1_stb_o(ram2_wb_stb_i),
.wbs1_ack_i(ram2_wb_ack_o),
.wbs1_err_i(ram2_wb_err_o),
.wbs1_rty_i(0),
.wbs1_cyc_o(ram2_wb_cyc_i),
.wbs1_addr(36'h100000000),
.wbs1_addr_msk(36'hF00000000),
// Control
.wbs2_adr_o(ctrl_wb_adr_i),
.wbs2_dat_i(ctrl_wb_dat_o),
.wbs2_dat_o(ctrl_wb_dat_i),
.wbs2_we_o(ctrl_wb_we_i),
.wbs2_sel_o(),
.wbs2_stb_o(ctrl_wb_stb_i),
.wbs2_ack_i(ctrl_wb_ack_o),
.wbs2_err_i(ctrl_wb_err_o),
.wbs2_rty_i(0),
.wbs2_cyc_o(ctrl_wb_cyc_i),
.wbs2_addr(36'hF00000000),
.wbs2_addr_msk(36'hF00000000)
);
assign ram1_wb_err_o = 0;
wb_mcb_8
wb_mcb_ram1_inst (
.clk(clk_250mhz_int),
.rst(rst_250mhz_int),
// wb interface
.wb_adr_i(ram1_wb_adr_i),
.wb_dat_i(ram1_wb_dat_i),
.wb_dat_o(ram1_wb_dat_o),
.wb_we_i(ram1_wb_we_i),
.wb_stb_i(ram1_wb_stb_i),
.wb_ack_o(ram1_wb_ack_o),
.wb_cyc_i(ram1_wb_cyc_i),
// mcb interface
.mcb_cmd_clk(ram1_p0_cmd_clk),
.mcb_cmd_en(ram1_p0_cmd_en),
.mcb_cmd_instr(ram1_p0_cmd_instr),
.mcb_cmd_bl(ram1_p0_cmd_bl),
.mcb_cmd_byte_addr(ram1_p0_cmd_byte_addr),
.mcb_cmd_empty(ram1_p0_cmd_empty),
.mcb_cmd_full(ram1_p0_cmd_full),
.mcb_wr_clk(ram1_p0_wr_clk),
.mcb_wr_en(ram1_p0_wr_en),
.mcb_wr_mask(ram1_p0_wr_mask),
.mcb_wr_data(ram1_p0_wr_data),
.mcb_wr_empty(ram1_p0_wr_empty),
.mcb_wr_full(ram1_p0_wr_full),
.mcb_wr_underrun(ram1_p0_wr_underrun),
.mcb_wr_count(ram1_p0_wr_count),
.mcb_wr_error(ram1_p0_wr_error),
.mcb_rd_clk(ram1_p0_rd_clk),
.mcb_rd_en(ram1_p0_rd_en_fifo),
.mcb_rd_data(ram1_p0_rd_data_fifo),
.mcb_rd_empty(ram1_p0_rd_empty_fifo),
.mcb_rd_full(ram1_p0_rd_full_fifo),
.mcb_rd_overflow(ram1_p0_rd_overflow),
.mcb_rd_count(ram1_p0_rd_count),
.mcb_rd_error(ram1_p0_rd_error)
);
assign ram2_wb_err_o = 0;
wb_mcb_8
wb_mcb_ram2_inst (
.clk(clk_250mhz_int),
.rst(rst_250mhz_int),
// wb interface
.wb_adr_i(ram2_wb_adr_i),
.wb_dat_i(ram2_wb_dat_i),
.wb_dat_o(ram2_wb_dat_o),
.wb_we_i(ram2_wb_we_i),
.wb_stb_i(ram2_wb_stb_i),
.wb_ack_o(ram2_wb_ack_o),
.wb_cyc_i(ram2_wb_cyc_i),
// mcb interface
.mcb_cmd_clk(ram2_p0_cmd_clk),
.mcb_cmd_en(ram2_p0_cmd_en),
.mcb_cmd_instr(ram2_p0_cmd_instr),
.mcb_cmd_bl(ram2_p0_cmd_bl),
.mcb_cmd_byte_addr(ram2_p0_cmd_byte_addr),
.mcb_cmd_empty(ram2_p0_cmd_empty),
.mcb_cmd_full(ram2_p0_cmd_full),
.mcb_wr_clk(ram2_p0_wr_clk),
.mcb_wr_en(ram2_p0_wr_en),
.mcb_wr_mask(ram2_p0_wr_mask),
.mcb_wr_data(ram2_p0_wr_data),
.mcb_wr_empty(ram2_p0_wr_empty),
.mcb_wr_full(ram2_p0_wr_full),
.mcb_wr_underrun(ram2_p0_wr_underrun),
.mcb_wr_count(ram2_p0_wr_count),
.mcb_wr_error(ram2_p0_wr_error),
.mcb_rd_clk(ram2_p0_rd_clk),
.mcb_rd_en(ram2_p0_rd_en_fifo),
.mcb_rd_data(ram2_p0_rd_data_fifo),
.mcb_rd_empty(ram2_p0_rd_empty_fifo),
.mcb_rd_full(ram2_p0_rd_full_fifo),
.mcb_rd_overflow(ram2_p0_rd_overflow),
.mcb_rd_count(ram2_p0_rd_count),
.mcb_rd_error(ram2_p0_rd_error)
);
wb_async_reg #(
.DATA_WIDTH(8),
.ADDR_WIDTH(32)
)
wb_async_reg_inst (
.wbm_clk(clk_250mhz_int),
.wbm_rst(rst_250mhz_int),
.wbm_adr_i(ctrl_wb_adr_i),
.wbm_dat_i(ctrl_wb_dat_i),
.wbm_dat_o(ctrl_wb_dat_o),
.wbm_we_i(ctrl_wb_we_i),
.wbm_sel_i(1),
.wbm_stb_i(ctrl_wb_stb_i),
.wbm_ack_o(ctrl_wb_ack_o),
.wbm_err_o(ctrl_wb_err_o),
.wbm_rty_o(),
.wbm_cyc_i(ctrl_wb_cyc_i),
.wbs_clk(clk_250mhz),
.wbs_rst(rst_250mhz),
.wbs_adr_o(ctrl_int_wb_adr_i),
.wbs_dat_i(ctrl_int_wb_dat_o),
.wbs_dat_o(ctrl_int_wb_dat_i),
.wbs_we_o(ctrl_int_wb_we_i),
.wbs_sel_o(),
.wbs_stb_o(ctrl_int_wb_stb_i),
.wbs_ack_i(ctrl_int_wb_ack_o),
.wbs_err_i(ctrl_int_wb_err_o),
.wbs_rty_i(0),
.wbs_cyc_o(ctrl_int_wb_cyc_i)
);
assign ctrl_int_wb_err_o = 0;
wb_ram #(
.DATA_WIDTH(8),
.ADDR_WIDTH(10)
)
wb_ram_inst(
.clk(clk_250mhz),
.adr_i(ctrl_int_wb_adr_i),
.dat_i(ctrl_int_wb_dat_i),
.dat_o(ctrl_int_wb_dat_o),
.we_i(ctrl_int_wb_we_i),
.sel_i(1),
.stb_i(ctrl_int_wb_stb_i),
.ack_o(ctrl_int_wb_ack_o),
.cyc_i(ctrl_int_wb_cyc_i)
);
// currenly unused signals
assign ram1_p1_cmd_clk = 0;
assign ram1_p1_cmd_en = 0;
assign ram1_p1_cmd_instr = 0;
assign ram1_p1_cmd_bl = 0;
assign ram1_p1_cmd_byte_addr = 0;
assign ram1_p1_wr_clk = 0;
assign ram1_p1_wr_en = 0;
assign ram1_p1_wr_mask = 0;
assign ram1_p1_wr_data = 0;
assign ram1_p1_rd_clk = 0;
assign ram1_p1_rd_en_fifo = 0;
assign ram1_p2_cmd_clk = 0;
assign ram1_p2_cmd_en = 0;
assign ram1_p2_cmd_instr = 0;
assign ram1_p2_cmd_bl = 0;
assign ram1_p2_cmd_byte_addr = 0;
assign ram1_p2_rd_clk = 0;
assign ram1_p2_rd_en_fifo = 0;
assign ram1_p3_cmd_clk = 0;
assign ram1_p3_cmd_en = 0;
assign ram1_p3_cmd_instr = 0;
assign ram1_p3_cmd_bl = 0;
assign ram1_p3_cmd_byte_addr = 0;
assign ram1_p3_rd_clk = 0;
assign ram1_p3_rd_en_fifo = 0;
assign ram1_p4_cmd_clk = 0;
assign ram1_p4_cmd_en = 0;
assign ram1_p4_cmd_instr = 0;
assign ram1_p4_cmd_bl = 0;
assign ram1_p4_cmd_byte_addr = 0;
assign ram1_p4_rd_clk = 0;
assign ram1_p4_rd_en_fifo = 0;
assign ram1_p5_cmd_clk = 0;
assign ram1_p5_cmd_en = 0;
assign ram1_p5_cmd_instr = 0;
assign ram1_p5_cmd_bl = 0;
assign ram1_p5_cmd_byte_addr = 0;
assign ram1_p5_rd_clk = 0;
assign ram1_p5_rd_en_fifo = 0;
assign ram2_p1_cmd_clk = 0;
assign ram2_p1_cmd_en = 0;
assign ram2_p1_cmd_instr = 0;
assign ram2_p1_cmd_bl = 0;
assign ram2_p1_cmd_byte_addr = 0;
assign ram2_p1_wr_clk = 0;
assign ram2_p1_wr_en = 0;
assign ram2_p1_wr_mask = 0;
assign ram2_p1_wr_data = 0;
assign ram2_p1_rd_clk = 0;
assign ram2_p1_rd_en_fifo = 0;
assign ram2_p2_cmd_clk = 0;
assign ram2_p2_cmd_en = 0;
assign ram2_p2_cmd_instr = 0;
assign ram2_p2_cmd_bl = 0;
assign ram2_p2_cmd_byte_addr = 0;
assign ram2_p2_rd_clk = 0;
assign ram2_p2_rd_en_fifo = 0;
assign ram2_p3_cmd_clk = 0;
assign ram2_p3_cmd_en = 0;
assign ram2_p3_cmd_instr = 0;
assign ram2_p3_cmd_bl = 0;
assign ram2_p3_cmd_byte_addr = 0;
assign ram2_p3_rd_clk = 0;
assign ram2_p3_rd_en_fifo = 0;
assign ram2_p4_cmd_clk = 0;
assign ram2_p4_cmd_en = 0;
assign ram2_p4_cmd_instr = 0;
assign ram2_p4_cmd_bl = 0;
assign ram2_p4_cmd_byte_addr = 0;
assign ram2_p4_rd_clk = 0;
assign ram2_p4_rd_en_fifo = 0;
assign ram2_p5_cmd_clk = 0;
assign ram2_p5_cmd_en = 0;
assign ram2_p5_cmd_instr = 0;
assign ram2_p5_cmd_bl = 0;
assign ram2_p5_cmd_byte_addr = 0;
assign ram2_p5_rd_clk = 0;
assign ram2_p5_rd_en_fifo = 0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_PP_V
/**
* lpflow_inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso1p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , or0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_PP_V |
module vga(/*AUTOARG*/
// Outputs
hsync, vsync, x, y, ve, newline, newfield,
// Inputs
clk_p, rst
);
input wire clk_p;
input wire rst;
output wire hsync, vsync;
output wire [9:0] x, y; //1023
output wire ve;
output wire newline, newfield;
assign newline = x_i == 0;
assign newfield = y_i == 0;
reg [10:0] x_i, y_i; //2047
//wire clk_l; //clk_p pixel clock, clk_l line clock
//60Hz 0 < x < 1023, 0 < y < 767 75Mhz clk_d
//Horizontal (line) Front Porch 24clk_p Sync 136clk_p Back Porch 160clk_p = 1344
//Vertical (field) 3clk_l 6clk_l 29clk_l = 806
//60Hz 0 < x < 799, 0 < y < 599 40Mhz clk_d
// parameter h_pixel = 'd799;
// parameter v_pixel = 'd599;
// parameter h_front_porch = 'd40;
// parameter h_sync_pulse = 'd128;
// parameter h_back_porch = 'd88;
// parameter v_front_porch = 'd1;
// parameter v_sync_pulse = 'd4;
// parameter v_back_porch = 'd23;
// parameter line = h_pixel + h_front_porch + h_sync_pulse + h_back_porch;
// parameter field = v_pixel + v_front_porch + v_sync_pulse + v_back_porch;
//60Hz 0 < x < 639, 0 < y < 479 25Mhz clk_d
parameter h_pixel = 'd639;
parameter v_pixel = 'd479;
parameter v_front_porch = 'd10;
parameter v_sync_pulse = 'd2;
parameter v_back_porch = 'd29; //33
parameter h_front_porch = 'd16;
parameter h_sync_pulse = 'd96;
parameter h_back_porch = 'd48;
parameter line = h_pixel + h_front_porch + h_sync_pulse + h_back_porch;
parameter field = v_pixel + v_front_porch + v_sync_pulse + v_back_porch;
always @(posedge clk_p) begin
if(~rst) begin
x_i <= 0;
end
else begin
if(x_i == line) begin
x_i <= 0;
end
else begin
x_i <= x_i + 1;
end
end
end
always @(posedge clk_p) begin
if(~rst) begin
y_i <= 0;
end
else if (x_i == line) begin
if(y_i == field) begin
y_i <= 0;
end
else begin
y_i <= y_i + 1;
end
end
end
assign hsync = (x_i >= h_sync_pulse) ? 1: 0;
assign vsync = (y_i >= v_sync_pulse) ? 1: 0;
assign ve = 0
|| (x_i >= h_sync_pulse + h_back_porch && x_i <= line - h_front_porch) && (y_i >= v_sync_pulse + v_back_porch && y_i <= field - v_front_porch)
// && ( (|y[2:0]))
// || (x_i >= h_sync_pulse + h_back_porch && x_i <=1+ line - h_front_porch) && (y_i >= v_sync_pulse + v_back_porch && y_i <= field - v_front_porch)
// && (!(|y[2:0]))
;
//assign x = (ve) ? x_i - h_back_porch - h_sync_pulse : 0;
//assign y = (ve) ? y_i - v_back_porch - v_sync_pulse : 0;
assign x = x_i - h_back_porch - h_sync_pulse;
assign y = y_i - v_back_porch - v_sync_pulse;
endmodule
|
`timescale 100 ps / 10 ps
`define MSBI 7 // Most significant Bit of DAC input
//This is a Delta-Sigma Digital to Analog Converter
module dac(DACout, DACin, Clk, Reset);
output DACout; // This is the average output that feeds low pass filter
reg DACout; // for optimum performance, ensure that this ff is in IOB
input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)
input Clk;
input Reset;
reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
reg [`MSBI+2:0] SigmaLatch; // Latches output of Sigma adder
reg [`MSBI+2:0] DeltaB; // B input of Delta adder
always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk or posedge Reset)
begin
if(Reset)
begin
SigmaLatch <= 1'b1 << (`MSBI+1);
DACout <= 1'b0;
end
else
begin
SigmaLatch <= SigmaAdder;
DACout <= SigmaLatch[`MSBI+2];
end
end
endmodule
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA top-level module
*/
module fpga (
// CPU reset button
input wire CPU_RESET_n,
// buttons
input wire [3:0] BUTTON,
input wire [3:0] SW,
// LEDs
output wire [6:0] HEX0_D,
output wire HEX0_DP,
output wire [6:0] HEX1_D,
output wire HEX1_DP,
output wire [3:0] LED,
output wire [3:0] LED_BRACKET,
output wire LED_RJ45_L,
output wire LED_RJ45_R,
// Temperature control
//inout wire TEMP_CLK,
//inout wire TEMP_DATA,
//input wire TEMP_INT_n,
//input wire TEMP_OVERT_n,
output wire FAN_CTRL,
// 50 MHz clock inputs
input wire OSC_50_B3B,
input wire OSC_50_B3D,
input wire OSC_50_B4A,
input wire OSC_50_B4D,
input wire OSC_50_B7A,
input wire OSC_50_B7D,
input wire OSC_50_B8A,
input wire OSC_50_B8D,
// PCIe interface
//input wire PCIE_PERST_n,
//input wire PCIE_REFCLK_p,
//input wire [7:0] PCIE_RX_p,
//output wire [7:0] PCIE_TX_p,
//input wire PCIE_WAKE_n,
//inout wire PCIE_SMBCLK,
//inout wire PCIE_SMBDAT,
// Si570
inout wire CLOCK_SCL,
inout wire CLOCK_SDA,
// 10G Ethernet
input wire SFPA_LOS,
input wire SFPA_TXFAULT,
input wire SFPA_MOD0_PRESNT_n,
inout wire SFPA_MOD1_SCL,
inout wire SFPA_MOD2_SDA,
output wire SFPA_TXDISABLE,
output wire [1:0] SPFA_RATESEL,
input wire SFPA_RX_p,
output wire SFPA_TX_p,
input wire SFPB_LOS,
input wire SFPB_TXFAULT,
input wire SFPB_MOD0_PRESNT_n,
inout wire SFPB_MOD1_SCL,
inout wire SFPB_MOD2_SDA,
output wire SFPB_TXDISABLE,
output wire [1:0] SPFB_RATESEL,
input wire SFPB_RX_p,
output wire SFPB_TX_p,
input wire SFPC_LOS,
input wire SFPC_TXFAULT,
input wire SFPC_MOD0_PRESNT_n,
inout wire SFPC_MOD1_SCL,
inout wire SFPC_MOD2_SDA,
output wire SFPC_TXDISABLE,
output wire [1:0] SPFC_RATESEL,
input wire SFPC_RX_p,
output wire SFPC_TX_p,
input wire SFPD_LOS,
input wire SFPD_TXFAULT,
input wire SFPD_MOD0_PRESNT_n,
inout wire SFPD_MOD1_SCL,
inout wire SFPD_MOD2_SDA,
output wire SFPD_TXDISABLE,
output wire [1:0] SPFD_RATESEL,
input wire SFPD_RX_p,
output wire SFPD_TX_p,
input wire SFP_REFCLK_P
);
// Clock and reset
wire clk_50mhz = OSC_50_B3B;
wire rst_50mhz;
sync_reset #(
.N(4)
)
sync_reset_50mhz_inst (
.clk(clk_50mhz),
.rst(~CPU_RESET_n),
.out(rst_50mhz)
);
wire clk_156mhz;
wire rst_156mhz;
wire phy_pll_locked;
sync_reset #(
.N(4)
)
sync_reset_156mhz_inst (
.clk(clk_156mhz),
.rst(rst_50mhz | ~phy_pll_locked),
.out(rst_156mhz)
);
// GPIO
wire [3:0] btn_int;
wire [3:0] sw_int;
wire [3:0] led_int;
wire [3:0] led_bkt_int;
wire [6:0] led_hex0_d_int;
wire led_hex0_dp_int;
wire [6:0] led_hex1_d_int;
wire led_hex1_dp_int;
debounce_switch #(
.WIDTH(8),
.N(4),
.RATE(156250)
)
debounce_switch_inst (
.clk(clk_156mhz),
.rst(rst_156mhz),
.in({BUTTON,
SW}),
.out({btn_int,
sw_int})
);
assign LED = ~led_int;
assign LED_BRACKET = ~led_bkt_int;
assign HEX0_D = ~led_hex0_d_int;
assign HEX0_DP = ~led_hex0_dp_int;
assign HEX1_D = ~led_hex1_d_int;
assign HEX1_DP = ~led_hex1_dp_int;
assign FAN_CTRL = 1;
// Si570 oscillator I2C init
wire si570_scl_i;
wire si570_scl_o;
wire si570_scl_t;
wire si570_sda_i;
wire si570_sda_o;
wire si570_sda_t;
assign si570_sda_i = CLOCK_SDA;
assign CLOCK_SDA = si570_sda_t ? 1'bz : si570_sda_o;
assign si570_scl_i = CLOCK_SCL;
assign CLOCK_SCL = si570_scl_t ? 1'bz : si570_scl_o;
wire [6:0] si570_i2c_cmd_address;
wire si570_i2c_cmd_start;
wire si570_i2c_cmd_read;
wire si570_i2c_cmd_write;
wire si570_i2c_cmd_write_multiple;
wire si570_i2c_cmd_stop;
wire si570_i2c_cmd_valid;
wire si570_i2c_cmd_ready;
wire [7:0] si570_i2c_data;
wire si570_i2c_data_valid;
wire si570_i2c_data_ready;
wire si570_i2c_data_last;
si570_i2c_init
si570_i2c_init_inst (
.clk(clk_50mhz),
.rst(rst_50mhz),
.cmd_address(si570_i2c_cmd_address),
.cmd_start(si570_i2c_cmd_start),
.cmd_read(si570_i2c_cmd_read),
.cmd_write(si570_i2c_cmd_write),
.cmd_write_multiple(si570_i2c_cmd_write_multiple),
.cmd_stop(si570_i2c_cmd_stop),
.cmd_valid(si570_i2c_cmd_valid),
.cmd_ready(si570_i2c_cmd_ready),
.data_out(si570_i2c_data),
.data_out_valid(si570_i2c_data_valid),
.data_out_ready(si570_i2c_data_ready),
.data_out_last(si570_i2c_data_last),
.busy(),
.start(1)
);
i2c_master
si570_i2c_master_inst (
.clk(clk_50mhz),
.rst(rst_50mhz),
.cmd_address(si570_i2c_cmd_address),
.cmd_start(si570_i2c_cmd_start),
.cmd_read(si570_i2c_cmd_read),
.cmd_write(si570_i2c_cmd_write),
.cmd_write_multiple(si570_i2c_cmd_write_multiple),
.cmd_stop(si570_i2c_cmd_stop),
.cmd_valid(si570_i2c_cmd_valid),
.cmd_ready(si570_i2c_cmd_ready),
.data_in(si570_i2c_data),
.data_in_valid(si570_i2c_data_valid),
.data_in_ready(si570_i2c_data_ready),
.data_in_last(si570_i2c_data_last),
.data_out(),
.data_out_valid(),
.data_out_ready(1),
.data_out_last(),
.scl_i(si570_scl_i),
.scl_o(si570_scl_o),
.scl_t(si570_scl_t),
.sda_i(si570_sda_i),
.sda_o(si570_sda_o),
.sda_t(si570_sda_t),
.busy(),
.bus_control(),
.bus_active(),
.missed_ack(),
.prescale(312),
.stop_on_idle(1)
);
// 10G Ethernet PHY
wire [71:0] sfp_a_tx_dc;
wire [71:0] sfp_a_rx_dc;
wire [71:0] sfp_b_tx_dc;
wire [71:0] sfp_b_rx_dc;
wire [71:0] sfp_c_tx_dc;
wire [71:0] sfp_c_rx_dc;
wire [71:0] sfp_d_tx_dc;
wire [71:0] sfp_d_rx_dc;
wire [367:0] phy_reconfig_from_xcvr;
wire [559:0] phy_reconfig_to_xcvr;
assign SFPA_MOD1_SCL = 1'bz;
assign SFPA_MOD2_SDA = 1'bz;
assign SFPA_TXDISABLE = 1'b0;
assign SPFA_RATESEL = 2'b00;
assign SFPB_MOD1_SCL = 1'bz;
assign SFPB_MOD2_SDA = 1'bz;
assign SFPB_TXDISABLE = 1'b0;
assign SPFB_RATESEL = 2'b00;
assign SFPC_MOD1_SCL = 1'bz;
assign SFPC_MOD2_SDA = 1'bz;
assign SFPC_TXDISABLE = 1'b0;
assign SPFC_RATESEL = 2'b00;
assign SFPD_MOD1_SCL = 1'bz;
assign SFPD_MOD2_SDA = 1'bz;
assign SFPD_TXDISABLE = 1'b0;
assign SPFD_RATESEL = 2'b00;
phy
phy_inst (
.pll_ref_clk(SFP_REFCLK_P),
.pll_locked(phy_pll_locked),
.tx_serial_data_0(SFPA_TX_p),
.rx_serial_data_0(SFPA_RX_p),
.tx_serial_data_1(SFPB_TX_p),
.rx_serial_data_1(SFPB_RX_p),
.tx_serial_data_2(SFPC_TX_p),
.rx_serial_data_2(SFPC_RX_p),
.tx_serial_data_3(SFPD_TX_p),
.rx_serial_data_3(SFPD_RX_p),
.xgmii_tx_dc_0(sfp_a_tx_dc),
.xgmii_rx_dc_0(sfp_a_rx_dc),
.xgmii_tx_dc_1(sfp_b_tx_dc),
.xgmii_rx_dc_1(sfp_b_rx_dc),
.xgmii_tx_dc_2(sfp_c_tx_dc),
.xgmii_rx_dc_2(sfp_c_rx_dc),
.xgmii_tx_dc_3(sfp_d_tx_dc),
.xgmii_rx_dc_3(sfp_d_rx_dc),
.xgmii_rx_clk(clk_156mhz),
.xgmii_tx_clk(clk_156mhz),
.tx_ready(~rst_156mhz),
.rx_ready(),
.rx_data_ready(),
.phy_mgmt_clk(clk_50mhz),
.phy_mgmt_clk_reset(rst_50mhz),
.phy_mgmt_address(9'd0),
.phy_mgmt_read(1'b0),
.phy_mgmt_readdata(),
.phy_mgmt_waitrequest(),
.phy_mgmt_write(1'b0),
.phy_mgmt_writedata(32'd0),
.reconfig_from_xcvr(phy_reconfig_from_xcvr),
.reconfig_to_xcvr(phy_reconfig_to_xcvr)
);
phy_reconfig
phy_reconfig_inst (
.reconfig_busy(),
.mgmt_clk_clk(clk_50mhz),
.mgmt_rst_reset(rst_50mhz),
.reconfig_mgmt_address(7'd0),
.reconfig_mgmt_read(1'b0),
.reconfig_mgmt_readdata(),
.reconfig_mgmt_waitrequest(),
.reconfig_mgmt_write(1'b0),
.reconfig_mgmt_writedata(32'd0),
.reconfig_to_xcvr(phy_reconfig_to_xcvr),
.reconfig_from_xcvr(phy_reconfig_from_xcvr)
);
// Convert XGMII interfaces
wire [63:0] sfp_a_txd_int;
wire [7:0] sfp_a_txc_int;
wire [63:0] sfp_a_rxd_int;
wire [7:0] sfp_a_rxc_int;
wire [63:0] sfp_b_txd_int;
wire [7:0] sfp_b_txc_int;
wire [63:0] sfp_b_rxd_int;
wire [7:0] sfp_b_rxc_int;
wire [63:0] sfp_c_txd_int;
wire [7:0] sfp_c_txc_int;
wire [63:0] sfp_c_rxd_int;
wire [7:0] sfp_c_rxc_int;
wire [63:0] sfp_d_txd_int;
wire [7:0] sfp_d_txc_int;
wire [63:0] sfp_d_rxd_int;
wire [7:0] sfp_d_rxc_int;
xgmii_interleave
xgmii_interleave_inst_a (
.input_xgmii_d(sfp_a_txd_int),
.input_xgmii_c(sfp_a_txc_int),
.output_xgmii_dc(sfp_a_tx_dc)
);
xgmii_deinterleave
xgmii_deinterleave_inst_a (
.input_xgmii_dc(sfp_a_rx_dc),
.output_xgmii_d(sfp_a_rxd_int),
.output_xgmii_c(sfp_a_rxc_int)
);
xgmii_interleave
xgmii_interleave_inst_b (
.input_xgmii_d(sfp_b_txd_int),
.input_xgmii_c(sfp_b_txc_int),
.output_xgmii_dc(sfp_b_tx_dc)
);
xgmii_deinterleave
xgmii_deinterleave_inst_b (
.input_xgmii_dc(sfp_b_rx_dc),
.output_xgmii_d(sfp_b_rxd_int),
.output_xgmii_c(sfp_b_rxc_int)
);
xgmii_interleave
xgmii_interleave_inst_c (
.input_xgmii_d(sfp_c_txd_int),
.input_xgmii_c(sfp_c_txc_int),
.output_xgmii_dc(sfp_c_tx_dc)
);
xgmii_deinterleave
xgmii_deinterleave_inst_c (
.input_xgmii_dc(sfp_c_rx_dc),
.output_xgmii_d(sfp_c_rxd_int),
.output_xgmii_c(sfp_c_rxc_int)
);
xgmii_interleave
xgmii_interleave_inst_d (
.input_xgmii_d(sfp_d_txd_int),
.input_xgmii_c(sfp_d_txc_int),
.output_xgmii_dc(sfp_d_tx_dc)
);
xgmii_deinterleave
xgmii_deinterleave_inst_d (
.input_xgmii_dc(sfp_d_rx_dc),
.output_xgmii_d(sfp_d_rxd_int),
.output_xgmii_c(sfp_d_rxc_int)
);
// Core logic
fpga_core
core_inst (
/*
* Clock: 156.25MHz
* Synchronous reset
*/
.clk(clk_156mhz),
.rst(rst_156mhz),
/*
* GPIO
*/
.btn(btn_int),
.sw(sw_int),
.led(led_int),
.led_bkt(led_bkt_int),
.led_hex0_d(led_hex0_d_int),
.led_hex0_dp(led_hex0_dp_int),
.led_hex1_d(led_hex1_d_int),
.led_hex1_dp(led_hex1_dp_int),
/*
* 10G Ethernet
*/
.sfp_a_txd(sfp_a_txd_int),
.sfp_a_txc(sfp_a_txc_int),
.sfp_a_rxd(sfp_a_rxd_int),
.sfp_a_rxc(sfp_a_rxc_int),
.sfp_b_txd(sfp_b_txd_int),
.sfp_b_txc(sfp_b_txc_int),
.sfp_b_rxd(sfp_b_rxd_int),
.sfp_b_rxc(sfp_b_rxc_int),
.sfp_c_txd(sfp_c_txd_int),
.sfp_c_txc(sfp_c_txc_int),
.sfp_c_rxd(sfp_c_rxd_int),
.sfp_c_rxc(sfp_c_rxc_int),
.sfp_d_txd(sfp_d_txd_int),
.sfp_d_txc(sfp_d_txc_int),
.sfp_d_rxd(sfp_d_rxd_int),
.sfp_d_rxc(sfp_d_rxc_int)
);
endmodule
`resetall
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DFXTP_FUNCTIONAL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_df_p_pg/sky130_fd_sc_hs__u_df_p_pg.v"
`celldefine
module sky130_fd_sc_hs__dfxtp (
VPWR,
VGND,
Q ,
CLK ,
D
);
// Module ports
input VPWR;
input VGND;
output Q ;
input CLK ;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_df_p_pg `UNIT_DELAY u_df_p_pg0 (buf_Q , D, CLK, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXTP_FUNCTIONAL_V |
module project (GPIO_0,SW,CLOCK_50,LEDR,LEDG, PS2_DAT, PS2_CLK);
output [25:0]GPIO_0;
output [0:17]LEDR;
output [0:6]LEDG;
input PS2_DAT;
input PS2_CLK;
input[16:0] SW;
input CLOCK_50;
wire hertz_10;
wire hertz_1;
reg [0:7] LINE_1,LINE_2,LINE_3,LINE_4,LINE_5,LINE_6,LINE_7,LINE_0;
wire reset = 1'b0;
wire [7:0] scan_code;
reg [7:0] pressed;
wire read, scan_ready;
always @(posedge scan_ready)
begin
pressed <= scan_code;
end
oneshot pulser(
.pulse_out(read),
.trigger_in(scan_ready),
.clk(CLOCK_50)
);
keyboard kbd(
.keyboard_clk(PS2_CLK),
.keyboard_data(PS2_DAT),
.clock50(CLOCK_50),
.reset(reset),
.read(read),
.scan_ready(scan_ready),
.scan_code(scan_code)
);
assign LEDR[0:7] = LINE_0[0:7];
reg [0:255]ROWDATA_1;
reg [0:255]ROWDATA_2;
reg [0:255]ROWDATA_3;
reg [0:255]ROWDATA_4;
reg [0:255]ROWDATA_5;
reg [0:255]ROWDATA_6;
reg [0:255]ROWDATA_7;
reg [0:255]ROWDATA_8;
integer counter1;
integer counter2;
integer counter3;
integer counter4;
integer counter5;
integer counter6;
integer counter7;
integer counter8;
integer seconds;
integer minutes;
integer hours;
reg isBirthday;
wire [0:15]sROW1, sROW2, sROW3, sROW4, sROW5, sROW6, sROW7, sROW8;
wire [0:15]mROW1, mROW2, mROW3, mROW4, mROW5, mROW6, mROW7, mROW8;
wire [0:15]hROW1, hROW2, hROW3, hROW4, hROW5, hROW6, hROW7, hROW8;
twoDigitNumberTo8BitDisplay hoursDisplay(hours,hROW1, hROW2, hROW3, hROW4, hROW5, hROW6, hROW7, hROW8);
twoDigitNumberTo8BitDisplay minutesDisplay(minutes,mROW1, mROW2, mROW3, mROW4, mROW5, mROW6, mROW7, mROW8);
twoDigitNumberTo8BitDisplay secondsDisplay(seconds,sROW1, sROW2, sROW3, sROW4, sROW5, sROW6, sROW7, sROW8);
initial begin
isBirthday = 0;
counter1 = 0;
counter2 = 1;
counter3 = 2;
counter4 = 3;
counter5 = 4;
counter6 = 5;
counter7 = 6;
counter8 = 7;
seconds = 59;
minutes = 0;
hours = 0;
ROWDATA_1 [0:255]= 256'b1000100000000000000000000000000000000000111100000100000000000000010000001000000000001000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000000000000000000000000000000000000000000;
ROWDATA_2 [0:255]= 256'b1000100000000000000000000000000000000000100010000000000000000000010000001000000000001000000000000000000000000000010000000000000000000000000000000000000011000000000000000000000011000000000000000000000000000000100010000000000000000000000000000000000000000000;
ROWDATA_3 [0:255]= 256'b1000100001110000100010001011000000000000100010001100000010110000111000001011000001101000011100001000100000000000010000000111000000000000000000000000000011000000000000000000000011000000000000000000000000000000100010001000100001110000100010000000000000000000;
ROWDATA_4 [0:255]= 256'b0101000010001000100010001100100000000000111100000100000011001000010000001100100010011000000010001000100000000000010000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010001010100000001000100010000000000000000000;
ROWDATA_5 [0:255]= 256'b0010000010001000100010001000000000000000100010000100000010000000010000001000100010001000011110000111100000000000010000000111000000000000000000000000000011000000000000000000000011000000000000000000000000000000111110001010100001111000011110000000000000000000;
ROWDATA_6 [0:255]= 256'b0010000010001000100110001000000000000000100010000100000010000000010010001000100010001000100010000000100000000000010000000000100000000000000000000000000011000000000000000000000011000000000000000000000000000000100010001010100010001000000010000000000000000000;
ROWDATA_7 [0:255]= 256'b0010000001110000011010001000000000000000111100001110000010000000001100001000100001111000011110000111000000000000111000001111000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010000101000001111000011100000000000000000000;
ROWDATA_8 [0:255]= 256'b0;
end
toLED tL1 (GPIO_0, SW,CLOCK_50, LEDG, LINE_0, LINE_1, LINE_2, LINE_3, LINE_4, LINE_5, LINE_6, LINE_7);
clk_1_tenth_sec (CLOCK_50,hertz_10);
clk_1_sec (CLOCK_50,hertz_1);
reg [3:0]i;
always @(posedge hertz_10) begin
// Shift reader 8 bits to the right
counter1 = counter1 + 1;
counter2 = counter2 + 1;
counter3 = counter3 + 1;
counter4 = counter4 + 1;
counter5 = counter5 + 1;
counter6 = counter6 + 1;
counter7 = counter7 + 1;
counter8 = counter8 + 1;
if (counter1 == 256) begin
counter1 = 0;
end
if (counter2 == 256) begin
counter2 = 0;
end
if (counter3 == 256) begin
counter3 = 0;
end
if (counter4 == 256) begin
counter4 = 0;
end
if (counter5 == 256) begin
counter5 = 0;
end
if (counter6 == 256) begin
counter6 = 0;
end
if (counter7 == 256) begin
counter7 = 0;
end
if (counter8 == 256) begin
counter8 = 0;
end
// Assign the 8 bits to be displayed out of the 256 bit string
LINE_0 [0:7] = ({ROWDATA_1[counter1],ROWDATA_1[counter2],ROWDATA_1[counter3],ROWDATA_1[counter4],ROWDATA_1[counter5],ROWDATA_1[counter6],ROWDATA_1[counter7],ROWDATA_1[counter8]});
LINE_1 [0:7] = ({ROWDATA_2[counter1],ROWDATA_2[counter2],ROWDATA_2[counter3],ROWDATA_2[counter4],ROWDATA_2[counter5],ROWDATA_2[counter6],ROWDATA_2[counter7],ROWDATA_2[counter8]});
LINE_2 [0:7] = ({ROWDATA_3[counter1],ROWDATA_3[counter2],ROWDATA_3[counter3],ROWDATA_3[counter4],ROWDATA_3[counter5],ROWDATA_3[counter6],ROWDATA_3[counter7],ROWDATA_3[counter8]});
LINE_3 [0:7] = ({ROWDATA_4[counter1],ROWDATA_4[counter2],ROWDATA_4[counter3],ROWDATA_4[counter4],ROWDATA_4[counter5],ROWDATA_4[counter6],ROWDATA_4[counter7],ROWDATA_4[counter8]});
LINE_4 [0:7] = ({ROWDATA_5[counter1],ROWDATA_5[counter2],ROWDATA_5[counter3],ROWDATA_5[counter4],ROWDATA_5[counter5],ROWDATA_5[counter6],ROWDATA_5[counter7],ROWDATA_5[counter8]});
LINE_5 [0:7] = ({ROWDATA_6[counter1],ROWDATA_6[counter2],ROWDATA_6[counter3],ROWDATA_6[counter4],ROWDATA_6[counter5],ROWDATA_6[counter6],ROWDATA_6[counter7],ROWDATA_6[counter8]});
LINE_6 [0:7] = ({ROWDATA_7[counter1],ROWDATA_7[counter2],ROWDATA_7[counter3],ROWDATA_7[counter4],ROWDATA_7[counter5],ROWDATA_7[counter6],ROWDATA_7[counter7],ROWDATA_7[counter8]});
LINE_7 [0:7] = ({ROWDATA_8[counter1],ROWDATA_8[counter2],ROWDATA_8[counter3],ROWDATA_8[counter4],ROWDATA_8[counter5],ROWDATA_8[counter6],ROWDATA_8[counter7],ROWDATA_8[counter8]});
// If it's not your birthday yet then output
// Your Birthday Is 00:00:00 Away
if (isBirthday == 0)
begin
// Set boiler plate bits
ROWDATA_1 [0:255]= 256'b1000100000000000000000000000000000000000111100000100000000000000010000001000000000001000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000000000000000000000000000000000000000000;
ROWDATA_2 [0:255]= 256'b1000100000000000000000000000000000000000100010000000000000000000010000001000000000001000000000000000000000000000010000000000000000000000000000000000000011000000000000000000000011000000000000000000000000000000100010000000000000000000000000000000000000000000;
ROWDATA_3 [0:255]= 256'b1000100001110000100010001011000000000000100010001100000010110000111000001011000001101000011100001000100000000000010000000111000000000000000000000000000011000000000000000000000011000000000000000000000000000000100010001000100001110000100010000000000000000000;
ROWDATA_4 [0:255]= 256'b0101000010001000100010001100100000000000111100000100000011001000010000001100100010011000000010001000100000000000010000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010001010100000001000100010000000000000000000;
ROWDATA_5 [0:255]= 256'b0010000010001000100010001000000000000000100010000100000010000000010000001000100010001000011110000111100000000000010000000111000000000000000000000000000011000000000000000000000011000000000000000000000000000000111110001010100001111000011110000000000000000000;
ROWDATA_6 [0:255]= 256'b0010000010001000100110001000000000000000100010000100000010000000010010001000100010001000100010000000100000000000010000000000100000000000000000000000000011000000000000000000000011000000000000000000000000000000100010001010100010001000000010000000000000000000;
ROWDATA_7 [0:255]= 256'b0010000001110000011010001000000000000000111100001110000010000000001100001000100001111000011110000111000000000000111000001111000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010000101000001111000011100000000000000000000;
ROWDATA_8 [0:255]= 256'b0;
// Hours
ROWDATA_1[136:151] = hROW1[0:15];
ROWDATA_2[136:151] = hROW2[0:15];
ROWDATA_3[136:151] = hROW3[0:15];
ROWDATA_4[136:151] = hROW4[0:15];
ROWDATA_5[136:151] = hROW5[0:15];
ROWDATA_6[136:151] = hROW6[0:15];
ROWDATA_7[136:151] = hROW7[0:15];
ROWDATA_8[136:151] = hROW8[0:15];
// Minutes
ROWDATA_1[160:175] = mROW1[0:15];
ROWDATA_2[160:175] = mROW2[0:15];
ROWDATA_3[160:175] = mROW3[0:15];
ROWDATA_4[160:175] = mROW4[0:15];
ROWDATA_5[160:175] = mROW5[0:15];
ROWDATA_6[160:175] = mROW6[0:15];
ROWDATA_7[160:175] = mROW7[0:15];
ROWDATA_8[160:175] = mROW8[0:15];
// Seconds
ROWDATA_1[184:199] = sROW1[0:15];
ROWDATA_2[184:199] = sROW2[0:15];
ROWDATA_3[184:199] = sROW3[0:15];
ROWDATA_4[184:199] = sROW4[0:15];
ROWDATA_5[184:199] = sROW5[0:15];
ROWDATA_6[184:199] = sROW6[0:15];
ROWDATA_7[184:199] = sROW7[0:15];
ROWDATA_8[184:199] = sROW8[0:15];
end
else
begin
// Assign fixed text to lines
// HAPPY BIRTHDAY!
ROWDATA_1 [0:255]= 256'b1000100000000000000000000000000000000000000000001111000001000000000000000100000010000000000010000000000000000000100000000000000000111100000000000011110000000000001111000000000000111100000000000011110000000000001111000000000000111100000000000011110000000000;
ROWDATA_2 [0:255]= 256'b1000100000000000000000000000000000000000000000001000100000000000000000000100000010000000000010000000000000000000100000000000000001000010000000000100001000000000010000100000000001000010000000000100001000000000010000100000000001000010000000000100001000000000;
ROWDATA_3 [0:255]= 256'b1000100001110000111100001111000010001000000000001000100011000000101100001110000010110000011010000111000010001000100000000000000010101001000000001010100100000000101010010000000010101001000000001010100100000000101010010000000010101001000000001010100100000000;
ROWDATA_4 [0:255]= 256'b1111100000001000100010001000100010001000000000001111000001000000110010000100000011001000100110000000100010001000100000000000000010101001000000001010100100000000101010010000000010101001000000001010100100000000101010010000000010101001000000001010100100000000;
ROWDATA_5 [0:255]= 256'b1000100001111000111100001111000001111000000000001000100001000000100000000100000010001000100010000111100001111000000000000000000010000101000000001000010100000000100001010000000010000101000000001000010100000000100001010000000010000101000000001000010100000000;
ROWDATA_6 [0:255]= 256'b1000100010001000100000001000000000001000000000001000100001000000100000000100100010001000100010001000100000001000000000000000000010111001000000001011100100000000101110010000000010111001000000001011100100000000101110010000000010111001000000001011100100000000;
ROWDATA_7 [0:255]= 256'b1000100001111000100000001000000001110000000000001111000011100000100000000011000010001000011110000111100001110000100000000000000001000010000000000100001000000000010000100000000001000010000000000100001000000000010000100000000001000010000000000100001000000000;
ROWDATA_8 [0:255]= 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111100000000000011110000000000001111000000000000111100000000000011110000000000001111000000000000111100000000000011110000000000;
end
end
always @(posedge hertz_1) begin
if (seconds == 0) begin
if (minutes == 0) begin
if (hours == 0) begin
isBirthday = 1;
end
else begin
seconds = 59;
minutes = 59;
isBirthday = 0;
hours = hours -1;
end
end
else begin
seconds = 59;
isBirthday = 0;
minutes = minutes - 1;
end
end
else begin
isBirthday = 0;
seconds = seconds - 1;
end
if (pressed[7:0] == 8'h15)
begin
seconds = 0;
if (hours <99)
begin
hours = hours + 1;
end
end
if (pressed[7:0] == 8'h1C)
begin
seconds = 0;
if (hours >0)
begin
hours = hours - 1;
end
end
if (pressed[7:0] == 8'h1D)
begin
seconds = 0;
if (minutes <59)
begin
seconds = 0;
minutes = minutes + 1;
end
end
if (pressed[7:0] == 8'h1B)
begin
seconds = 0;
if (minutes > 0)
begin
minutes = minutes - 1;
end
end
end
endmodule
module toLED (GPIO_0, SW,CLOCK_50, LEDG ,LINE_0 , LINE_1, LINE_2, LINE_3, LINE_4, LINE_5, LINE_6, LINE_7);
output [25:0]GPIO_0;
input CLOCK_50;
//output [17:0]LEDR;
output [6:0]LEDG;
input[16:0] SW;
input [0:7] LINE_1,LINE_2,LINE_3,LINE_4,LINE_5,LINE_6,LINE_7,LINE_0;
reg data_in, load_in;
reg [0:15]enterDigit0;
reg [0:15]enterDigit1;
reg [0:15]enterDigit2;
reg [0:15]enterDigit3;
reg [0:15]enterDigit4;
reg [0:15]enterDigit5;
reg [0:15]enterDigit6;
reg [0:15]enterDigit7;
reg [0:15]enterDigit8;
reg [0:15]enterDigit9;
reg [0:15]enterDigit10;
reg [15:0]testLED;
reg [6:0] testGLED;
reg [0:7] start0,start1,start2,start3,start4,start5,start6,start7;
reg [31:0]counterX;
reg [31:0]counterY;
wire clockToUse;
CLOCKER clocker1(CLOCK_50,clockToUse);
initial
begin
counterX = 0;
counterY = 7;
load_in = 0;
testGLED = 7'b0;
start0 [0:7]= 8'b11110001;
start1[0:7] = 8'b11110010;
start2[0:7] = 8'b11110011;
start3[0:7] = 8'b11110100;
start4[0:7] = 8'b11110101;
start5[0:7] = 8'b11110110;
start6[0:7] = 8'b11110111;
start7[0:7] = 8'b11111000;
// Number of bits : 4 (4)(8)
// Format of bits : xxxx (0000) (00000000)
// Description of bits : anything (address) (data)
enterDigit0[0:15] = ({start0[0:7],LINE_0[0:7]});
enterDigit1[0:15] = ({start1[0:7],LINE_1[0:7]});
enterDigit2[0:15] = ({start2[0:7],LINE_2[0:7]});
enterDigit3[0:15] = ({start3[0:7],LINE_3[0:7]});
enterDigit4[0:15] = ({start4[0:7],LINE_4[0:7]});
enterDigit5[0:15] = ({start5[0:7],LINE_5[0:7]});
enterDigit6[0:15] = ({start6[0:7],LINE_6[0:7]});
enterDigit7[0:15] = ({start7[0:7],LINE_7[0:7]});
enterDigit8[0:15] = 16'b1111110011111111; //op current set to shutdown - NORMAL OPERATION
enterDigit9[0:15] = 16'b1111101111111111; //scan limit set to 7
enterDigit10[0:15]= 16'b1111101011111111; //Intensity set to max
end
assign GPIO_0[10] = data_in; //DIN
assign GPIO_0[14] = clockToUse; //CLOCK
assign LEDG = testGLED;
assign GPIO_0 [12] = load_in;
//assign LEDR[16] = load_in;
always @ (negedge clockToUse) begin
// re update data
enterDigit0[0:15] = ({start0[0:7],LINE_0[0:7]});
enterDigit1[0:15] = ({start1[0:7],LINE_1[0:7]});
enterDigit2[0:15] = ({start2[0:7],LINE_2[0:7]});
enterDigit3[0:15] = ({start3[0:7],LINE_3[0:7]});
enterDigit4[0:15] = ({start4[0:7],LINE_4[0:7]});
enterDigit5[0:15] = ({start5[0:7],LINE_5[0:7]});
enterDigit6[0:15] = ({start6[0:7],LINE_6[0:7]});
enterDigit7[0:15] = ({start7[0:7],LINE_7[0:7]});
// Load data for row
case (counterY)
0 :
begin
data_in <= enterDigit0[counterX];
testLED[counterX] <= enterDigit0[counterX];
end
1 :
begin
data_in <= enterDigit1[counterX];
testLED[counterX] <= enterDigit1[counterX];
end
2 :
begin
data_in <= enterDigit2[counterX];
testLED[counterX] <= enterDigit2[counterX];
end
3 :
begin
data_in <= enterDigit3[counterX];
testLED[counterX] <= enterDigit3[counterX];
end
4 :
begin
data_in <= enterDigit4[counterX];
testLED[counterX] <= enterDigit4[counterX];
end
5 :
begin
data_in <= enterDigit5[counterX];
testLED[counterX] <= enterDigit5[counterX];
end
6 :
begin
data_in <= enterDigit6[counterX];
testLED[counterX] <= enterDigit6[counterX];
end
7 :
begin
data_in <= enterDigit7[counterX];
testLED[counterX] <= enterDigit7[counterX];
end
8 :
begin
data_in <= enterDigit8[counterX];
testLED[counterX] <= enterDigit8[counterX];
end
9 :
begin
data_in <= enterDigit9[counterX];
testLED[counterX] <= enterDigit9[counterX];
end
10 :
begin
data_in <= enterDigit10[counterX];
testLED[counterX] <= enterDigit10[counterX];
end
endcase
testGLED[6:0] = 7'b0;
testGLED[counterY] <= 1;
// If on the 1st clock edge set load in low
if (counterX == 0)
begin
load_in = 1;
end
else
begin
load_in = 0;
end
if (counterX == 15)
begin
// On the 16th clock edge set load in low
testLED[15:0] = 16'b0000000000000000;
// Reset column
counterX =0;
// Increment row
counterY = counterY + 1;
// Reset row
if (counterY == 11)
begin
counterY = 0;
end
end
else
begin
counterX = counterX + 1;
end
end
endmodule
module clk_1_sec(
input clk_50mhz,
output reg clk_1hz
);
reg [31:0] count;
always @(posedge clk_50mhz)
begin
count <= count + 1;
if(count == 25000000) begin
count <= 0;
clk_1hz <= ~clk_1hz;
end
end
endmodule
module clk_1_tenth_sec(
input clk_50mhz,
output reg clk_1hz
);
reg [31:0] count;
always @(posedge clk_50mhz)
begin
count <= count + 1;
if(count == 2500000) begin
count <= 0;
clk_1hz <= ~clk_1hz;
end
end
endmodule
module CLOCKER(
input clk_50mhz,
output reg clk_1hz
);
reg [31:0] count;
always @(posedge clk_50mhz)
begin
count <= count + 1;
if(count == 500) begin
count <= 0;
clk_1hz <= ~clk_1hz;
end
end
endmodule
module twoDigitNumberTo8BitDisplay(NUMBER, ROW1, ROW2, ROW3, ROW4, ROW5, ROW6, ROW7, ROW8);
output reg [0:15]ROW1, ROW2, ROW3, ROW4, ROW5, ROW6, ROW7, ROW8;
input [31:0] NUMBER;
reg [0:7]firstDigitRow1, firstDigitRow2, firstDigitRow3, firstDigitRow4, firstDigitRow5, firstDigitRow6, firstDigitRow7, firstDigitRow8;
reg [0:7]secondDigitRow1, secondDigitRow2, secondDigitRow3, secondDigitRow4, secondDigitRow5, secondDigitRow6, secondDigitRow7, secondDigitRow8;
integer firstDigit;
integer secondDigit;
always
begin
firstDigit = (NUMBER/10);
secondDigit = (NUMBER%10);
case(firstDigit)
0 :
begin
firstDigitRow1 [0:7]=8'b01110000;
firstDigitRow2 [0:7]=8'b10001000;
firstDigitRow3 [0:7]=8'b10011000;
firstDigitRow4 [0:7]=8'b10101000;
firstDigitRow5 [0:7]=8'b11001000;
firstDigitRow6 [0:7]=8'b10001000;
firstDigitRow7 [0:7]=8'b01110000;
firstDigitRow8 [0:7]=8'b00000000;
end
1 :
begin
firstDigitRow1 [0:7]=8'b01000000;
firstDigitRow2 [0:7]=8'b11000000;
firstDigitRow3 [0:7]=8'b01000000;
firstDigitRow4 [0:7]=8'b01000000;
firstDigitRow5 [0:7]=8'b01000000;
firstDigitRow6 [0:7]=8'b01000000;
firstDigitRow7 [0:7]=8'b11100000;
firstDigitRow8 [0:7]=8'b00000000;
end
2 :
begin
firstDigitRow1 [0:7]=8'b01110000;
firstDigitRow2 [0:7]=8'b10001000;
firstDigitRow3 [0:7]=8'b00001000;
firstDigitRow4 [0:7]=8'b00010000;
firstDigitRow5 [0:7]=8'b00100000;
firstDigitRow6 [0:7]=8'b01000000;
firstDigitRow7 [0:7]=8'b11111000;
firstDigitRow8 [0:7]=8'b00000000;
end
3 :
begin
firstDigitRow1 [0:7]=8'b11111000;
firstDigitRow2 [0:7]=8'b00010000;
firstDigitRow3 [0:7]=8'b00100000;
firstDigitRow4 [0:7]=8'b00010000;
firstDigitRow5 [0:7]=8'b00001000;
firstDigitRow6 [0:7]=8'b10001000;
firstDigitRow7 [0:7]=8'b01110000;
firstDigitRow8 [0:7]=8'b00000000;
end
4 :
begin
firstDigitRow1 [0:7]=8'b00010000;
firstDigitRow2 [0:7]=8'b00110000;
firstDigitRow3 [0:7]=8'b01010000;
firstDigitRow4 [0:7]=8'b10010000;
firstDigitRow5 [0:7]=8'b11111000;
firstDigitRow6 [0:7]=8'b00010000;
firstDigitRow7 [0:7]=8'b00010000;
firstDigitRow8 [0:7]=8'b00000000;
end
5 :
begin
firstDigitRow1 [0:7]=8'b11111000;
firstDigitRow2 [0:7]=8'b10000000;
firstDigitRow3 [0:7]=8'b11110000;
firstDigitRow4 [0:7]=8'b00001000;
firstDigitRow5 [0:7]=8'b00001000;
firstDigitRow6 [0:7]=8'b10001000;
firstDigitRow7 [0:7]=8'b01110000;
firstDigitRow8 [0:7]=8'b00000000;
end
6 :
begin
firstDigitRow1 [0:7]=8'b00110000;
firstDigitRow2 [0:7]=8'b01000000;
firstDigitRow3 [0:7]=8'b10000000;
firstDigitRow4 [0:7]=8'b11110000;
firstDigitRow5 [0:7]=8'b10001000;
firstDigitRow6 [0:7]=8'b10001000;
firstDigitRow7 [0:7]=8'b01110000;
firstDigitRow8 [0:7]=8'b00000000;
end
7 :
begin
firstDigitRow1 [0:7]=8'b11111000;
firstDigitRow2 [0:7]=8'b10001000;
firstDigitRow3 [0:7]=8'b00001000;
firstDigitRow4 [0:7]=8'b00010000;
firstDigitRow5 [0:7]=8'b00100000;
firstDigitRow6 [0:7]=8'b00100000;
firstDigitRow7 [0:7]=8'b00100000;
firstDigitRow8 [0:7]=8'b00000000;
end
8 :
begin
firstDigitRow1 [0:7]=8'b01110000;
firstDigitRow2 [0:7]=8'b10001000;
firstDigitRow3 [0:7]=8'b10001000;
firstDigitRow4 [0:7]=8'b01110000;
firstDigitRow5 [0:7]=8'b10001000;
firstDigitRow6 [0:7]=8'b10001000;
firstDigitRow7 [0:7]=8'b01110000;
firstDigitRow8 [0:7]=8'b00000000;
end
9 :
begin
firstDigitRow1 [0:7]=8'b01110000;
firstDigitRow2 [0:7]=8'b10001000;
firstDigitRow3 [0:7]=8'b10001000;
firstDigitRow4 [0:7]=8'b01111000;
firstDigitRow5 [0:7]=8'b00001000;
firstDigitRow6 [0:7]=8'b00010000;
firstDigitRow7 [0:7]=8'b01100000;
firstDigitRow8 [0:7]=8'b00000000;
end
endcase
case(secondDigit)
0 :
begin
secondDigitRow1 [0:7]=8'b01110000;
secondDigitRow2 [0:7]=8'b10001000;
secondDigitRow3 [0:7]=8'b10011000;
secondDigitRow4 [0:7]=8'b10101000;
secondDigitRow5 [0:7]=8'b11001000;
secondDigitRow6 [0:7]=8'b10001000;
secondDigitRow7 [0:7]=8'b01110000;
secondDigitRow8 [0:7]=8'b00000000;
end
1 :
begin
secondDigitRow1 [0:7]=8'b01000000;
secondDigitRow2 [0:7]=8'b11000000;
secondDigitRow3 [0:7]=8'b01000000;
secondDigitRow4 [0:7]=8'b01000000;
secondDigitRow5 [0:7]=8'b01000000;
secondDigitRow6 [0:7]=8'b01000000;
secondDigitRow7 [0:7]=8'b11100000;
secondDigitRow8 [0:7]=8'b00000000;
end
2 :
begin
secondDigitRow1 [0:7]=8'b01110000;
secondDigitRow2 [0:7]=8'b10001000;
secondDigitRow3 [0:7]=8'b00001000;
secondDigitRow4 [0:7]=8'b00010000;
secondDigitRow5 [0:7]=8'b00100000;
secondDigitRow6 [0:7]=8'b01000000;
secondDigitRow7 [0:7]=8'b11111000;
secondDigitRow8 [0:7]=8'b00000000;
end
3 :
begin
secondDigitRow1 [0:7]=8'b11111000;
secondDigitRow2 [0:7]=8'b00010000;
secondDigitRow3 [0:7]=8'b00100000;
secondDigitRow4 [0:7]=8'b00010000;
secondDigitRow5 [0:7]=8'b00001000;
secondDigitRow6 [0:7]=8'b10001000;
secondDigitRow7 [0:7]=8'b01110000;
secondDigitRow8 [0:7]=8'b00000000;
end
4 :
begin
secondDigitRow1 [0:7]=8'b00010000;
secondDigitRow2 [0:7]=8'b00110000;
secondDigitRow3 [0:7]=8'b01010000;
secondDigitRow4 [0:7]=8'b10010000;
secondDigitRow5 [0:7]=8'b11111000;
secondDigitRow6 [0:7]=8'b00010000;
secondDigitRow7 [0:7]=8'b00010000;
secondDigitRow8 [0:7]=8'b00000000;
end
5 :
begin
secondDigitRow1 [0:7]=8'b11111000;
secondDigitRow2 [0:7]=8'b10000000;
secondDigitRow3 [0:7]=8'b11110000;
secondDigitRow4 [0:7]=8'b00001000;
secondDigitRow5 [0:7]=8'b00001000;
secondDigitRow6 [0:7]=8'b10001000;
secondDigitRow7 [0:7]=8'b01110000;
secondDigitRow8 [0:7]=8'b00000000;
end
6 :
begin
secondDigitRow1 [0:7]=8'b00110000;
secondDigitRow2 [0:7]=8'b01000000;
secondDigitRow3 [0:7]=8'b10000000;
secondDigitRow4 [0:7]=8'b11110000;
secondDigitRow5 [0:7]=8'b10001000;
secondDigitRow6 [0:7]=8'b10001000;
secondDigitRow7 [0:7]=8'b01110000;
secondDigitRow8 [0:7]=8'b00000000;
end
7 :
begin
secondDigitRow1 [0:7]=8'b11111000;
secondDigitRow2 [0:7]=8'b10001000;
secondDigitRow3 [0:7]=8'b00001000;
secondDigitRow4 [0:7]=8'b00010000;
secondDigitRow5 [0:7]=8'b00100000;
secondDigitRow6 [0:7]=8'b00100000;
secondDigitRow7 [0:7]=8'b00100000;
secondDigitRow8 [0:7]=8'b00000000;
end
8 :
begin
secondDigitRow1 [0:7]=8'b01110000;
secondDigitRow2 [0:7]=8'b10001000;
secondDigitRow3 [0:7]=8'b10001000;
secondDigitRow4 [0:7]=8'b01110000;
secondDigitRow5 [0:7]=8'b10001000;
secondDigitRow6 [0:7]=8'b10001000;
secondDigitRow7 [0:7]=8'b01110000;
secondDigitRow8 [0:7]=8'b00000000;
end
9 :
begin
secondDigitRow1 [0:7]=8'b01110000;
secondDigitRow2 [0:7]=8'b10001000;
secondDigitRow3 [0:7]=8'b10001000;
secondDigitRow4 [0:7]=8'b01111000;
secondDigitRow5 [0:7]=8'b00001000;
secondDigitRow6 [0:7]=8'b00010000;
secondDigitRow7 [0:7]=8'b01100000;
secondDigitRow8 [0:7]=8'b00000000;
end
endcase
ROW1[0:15] = ({firstDigitRow1[0:7] , secondDigitRow1[0:7]});
ROW2[0:15]= ({firstDigitRow2[0:7] , secondDigitRow2[0:7]});
ROW3[0:15] = ({firstDigitRow3[0:7] , secondDigitRow3[0:7]});
ROW4[0:15] = ({firstDigitRow4 [0:7], secondDigitRow4[0:7]});
ROW5[0:15] = ({firstDigitRow5 [0:7], secondDigitRow5[0:7]});
ROW6[0:15] = ({firstDigitRow6 [0:7], secondDigitRow6[0:7]});
ROW7[0:15] = ({firstDigitRow7[0:7] , secondDigitRow7[0:7]});
ROW8[0:15] = ({firstDigitRow8[0:7], secondDigitRow8[0:7]});
end
endmodule |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module tb_aceusb();
reg sys_clk;
reg sys_rst;
reg ace_clk;
reg [31:0] wb_adr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
wire [6:0] aceusb_a;
wire [15:0] aceusb_d;
wire aceusb_oe_n;
wire aceusb_we_n;
wire ace_clkin;
wire ace_mpce_n;
wire ace_mpirq;
wire usb_cs_n;
wire usb_hpi_reset_n;
wire usb_hpi_int;
aceusb dut(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_we_i(wb_we_i),
.wb_ack_o(wb_ack_o),
.aceusb_a(aceusb_a),
.aceusb_d(aceusb_d),
.aceusb_oe_n(aceusb_oe_n),
.aceusb_we_n(aceusb_we_n),
.ace_clkin(ace_clk),
.ace_mpce_n(ace_mpce_n),
.ace_mpirq(ace_mpirq),
.usb_cs_n(usb_cs_n),
.usb_hpi_reset_n(usb_hpi_reset_n),
.usb_hpi_int(usb_hpi_int)
);
assign aceusb_d = aceusb_oe_n ? 16'h1234 : 16'hzzzz;
initial begin
$dumpfile("aceusb.vcd");
$dumpvars(1, dut);
end
/* Generate ~33MHz SystemACE clock */
initial ace_clk <= 0;
always #7.5 ace_clk <= ~ace_clk;
task wbwrite;
input [31:0] address;
input [31:0] data;
integer i;
begin
wb_adr_i = address;
wb_dat_i = data;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b1;
i = 1;
while(~wb_ack_o) begin
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
i = i + 1;
end
$display("Write address %h completed in %d cycles", address, i);
/* Let the core release its ack */
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
wb_we_i = 1'b1;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
end
endtask
task wbread;
input [31:0] address;
integer i;
begin
wb_adr_i = address;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b0;
i = 1;
while(~wb_ack_o) begin
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
i = i + 1;
end
$display("Read address %h completed in %d cycles, result %h", address, i, wb_dat_o);
/* Let the core release its ack */
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
end
endtask
initial begin
sys_rst = 1'b1;
sys_clk = 1'b0;
wb_adr_i = 32'h00000000;
wb_dat_i = 32'h00000000;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
sys_rst = 1'b0;
wbwrite(32'h00000180, 32'hcafebabe);
wbread(32'h00000020);
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__A21O_BEHAVIORAL_PP_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21O_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4B_2_V
`define SKY130_FD_SC_LS__NOR4B_2_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4b_2 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4b_2 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4B_2_V
|
//-------------------------------------------------------------------
//-- Test para arranque del tipo "warm boot" en la iCE40HX.
//-- Pulsando el botón 1 cambiamos el valor de la imagen a cargar.
//-- Pulsando el botón 2 generamos la señal "boot" para cargar dicha
//-- imagen.
//-------------------------------------------------------------------
//-- Juan Manuel Rico - Ridotech - Marzo 2017.
//-------------------------------------------------------------------
module test_warmboot (input wire btn1, btn2, output reg [7:0] data);
//-- Instanciar el bloque warm boot.
top wb (
.boot(btn2),
.s1(image[1]),
.s0(image[0])
);
// Registro del valor de la imagen a cargar.
reg [1:0] image = 2'b00;
//-- Al pulsar el botón 1 hacemos cambiar el bit 7
// para mostrar la pulsación y elegimos la siguiente imagen.
always @(posedge(btn1)) begin
data[7] = ~data[7];
image = image + 1;
end
// Se muestra la imagen a cargar tras el warn boot (al pulsar el botón 2).
assign data[6:0] = {5'b00000, image[1], image[0]};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_BLACKBOX_V
`define SKY130_FD_SC_LS__O311A_BLACKBOX_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_BLACKBOX_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: cx4_mul.v
// /___/ /\ Timestamp: Fri Sep 16 13:20:56 2016
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /media/sf_borti4938/Documents/Workspaces/GitHub/sd2snes/verilog/sd2snes_cx4/ipcore_dir/tmp/_cg/cx4_mul.ngc /media/sf_borti4938/Documents/Workspaces/GitHub/sd2snes/verilog/sd2snes_cx4/ipcore_dir/tmp/_cg/cx4_mul.v
// Device : 3s400pq208-4
// Input file : /media/sf_borti4938/Documents/Workspaces/GitHub/sd2snes/verilog/sd2snes_cx4/ipcore_dir/tmp/_cg/cx4_mul.ngc
// Output file : /media/sf_borti4938/Documents/Workspaces/GitHub/sd2snes/verilog/sd2snes_cx4/ipcore_dir/tmp/_cg/cx4_mul.v
// # of Modules : 1
// Design Name : cx4_mul
// Xilinx : /opt/Xilinx/14.7/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module cx4_mul (
clk, p, a, b
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
output [47 : 0] p;
input [23 : 0] a;
input [23 : 0] b;
// synthesis translate_off
wire \blk00000001/sig0000021b ;
wire \blk00000001/sig0000021a ;
wire \blk00000001/sig00000219 ;
wire \blk00000001/sig00000218 ;
wire \blk00000001/sig00000217 ;
wire \blk00000001/sig00000216 ;
wire \blk00000001/sig00000215 ;
wire \blk00000001/sig00000214 ;
wire \blk00000001/sig00000213 ;
wire \blk00000001/sig00000212 ;
wire \blk00000001/sig00000211 ;
wire \blk00000001/sig00000210 ;
wire \blk00000001/sig0000020f ;
wire \blk00000001/sig0000020e ;
wire \blk00000001/sig0000020d ;
wire \blk00000001/sig0000020c ;
wire \blk00000001/sig0000020b ;
wire \blk00000001/sig0000020a ;
wire \blk00000001/sig00000209 ;
wire \blk00000001/sig00000208 ;
wire \blk00000001/sig00000207 ;
wire \blk00000001/sig00000206 ;
wire \blk00000001/sig00000205 ;
wire \blk00000001/sig00000204 ;
wire \blk00000001/sig00000203 ;
wire \blk00000001/sig00000202 ;
wire \blk00000001/sig00000201 ;
wire \blk00000001/sig00000200 ;
wire \blk00000001/sig000001ff ;
wire \blk00000001/sig000001fe ;
wire \blk00000001/sig000001fd ;
wire \blk00000001/sig000001fc ;
wire \blk00000001/sig000001fb ;
wire \blk00000001/sig000001fa ;
wire \blk00000001/sig000001f9 ;
wire \blk00000001/sig000001f8 ;
wire \blk00000001/sig000001f7 ;
wire \blk00000001/sig000001f6 ;
wire \blk00000001/sig000001f5 ;
wire \blk00000001/sig000001f4 ;
wire \blk00000001/sig000001f3 ;
wire \blk00000001/sig000001f2 ;
wire \blk00000001/sig000001f1 ;
wire \blk00000001/sig000001f0 ;
wire \blk00000001/sig000001ef ;
wire \blk00000001/sig000001ee ;
wire \blk00000001/sig000001ed ;
wire \blk00000001/sig000001ec ;
wire \blk00000001/sig000001eb ;
wire \blk00000001/sig000001ea ;
wire \blk00000001/sig000001e9 ;
wire \blk00000001/sig000001e8 ;
wire \blk00000001/sig000001e7 ;
wire \blk00000001/sig000001e6 ;
wire \blk00000001/sig000001e5 ;
wire \blk00000001/sig000001e4 ;
wire \blk00000001/sig000001e3 ;
wire \blk00000001/sig000001e2 ;
wire \blk00000001/sig000001e1 ;
wire \blk00000001/sig000001e0 ;
wire \blk00000001/sig000001df ;
wire \blk00000001/sig000001de ;
wire \blk00000001/sig000001dd ;
wire \blk00000001/sig000001dc ;
wire \blk00000001/sig000001db ;
wire \blk00000001/sig000001da ;
wire \blk00000001/sig000001d9 ;
wire \blk00000001/sig000001d8 ;
wire \blk00000001/sig000001d7 ;
wire \blk00000001/sig000001d6 ;
wire \blk00000001/sig000001d5 ;
wire \blk00000001/sig000001d4 ;
wire \blk00000001/sig000001d3 ;
wire \blk00000001/sig000001d2 ;
wire \blk00000001/sig000001d1 ;
wire \blk00000001/sig000001d0 ;
wire \blk00000001/sig000001cf ;
wire \blk00000001/sig000001ce ;
wire \blk00000001/sig000001cd ;
wire \blk00000001/sig000001cc ;
wire \blk00000001/sig000001cb ;
wire \blk00000001/sig000001ca ;
wire \blk00000001/sig000001c9 ;
wire \blk00000001/sig000001c8 ;
wire \blk00000001/sig000001c7 ;
wire \blk00000001/sig000001c6 ;
wire \blk00000001/sig000001c5 ;
wire \blk00000001/sig000001c4 ;
wire \blk00000001/sig000001c3 ;
wire \blk00000001/sig000001c2 ;
wire \blk00000001/sig000001c1 ;
wire \blk00000001/sig000001c0 ;
wire \blk00000001/sig000001bf ;
wire \blk00000001/sig000001be ;
wire \blk00000001/sig000001bd ;
wire \blk00000001/sig000001bc ;
wire \blk00000001/sig000001bb ;
wire \blk00000001/sig000001ba ;
wire \blk00000001/sig000001b9 ;
wire \blk00000001/sig000001b8 ;
wire \blk00000001/sig000001b7 ;
wire \blk00000001/sig000001b6 ;
wire \blk00000001/sig000001b5 ;
wire \blk00000001/sig000001b4 ;
wire \blk00000001/sig000001b3 ;
wire \blk00000001/sig000001b2 ;
wire \blk00000001/sig000001b1 ;
wire \blk00000001/sig000001b0 ;
wire \blk00000001/sig000001af ;
wire \blk00000001/sig000001ae ;
wire \blk00000001/sig000001ad ;
wire \blk00000001/sig000001ac ;
wire \blk00000001/sig000001ab ;
wire \blk00000001/sig000001aa ;
wire \blk00000001/sig000001a9 ;
wire \blk00000001/sig000001a8 ;
wire \blk00000001/sig000001a7 ;
wire \blk00000001/sig000001a6 ;
wire \blk00000001/sig000001a5 ;
wire \blk00000001/sig000001a4 ;
wire \blk00000001/sig000001a3 ;
wire \blk00000001/sig000001a2 ;
wire \blk00000001/sig000001a1 ;
wire \blk00000001/sig000001a0 ;
wire \blk00000001/sig0000019f ;
wire \blk00000001/sig0000019e ;
wire \blk00000001/sig0000019d ;
wire \blk00000001/sig0000019c ;
wire \blk00000001/sig0000019b ;
wire \blk00000001/sig0000019a ;
wire \blk00000001/sig00000199 ;
wire \blk00000001/sig00000198 ;
wire \blk00000001/sig00000197 ;
wire \blk00000001/sig00000196 ;
wire \blk00000001/sig00000195 ;
wire \blk00000001/sig00000194 ;
wire \blk00000001/sig00000193 ;
wire \blk00000001/sig00000192 ;
wire \blk00000001/sig00000191 ;
wire \blk00000001/sig00000190 ;
wire \blk00000001/sig0000018f ;
wire \blk00000001/sig0000018e ;
wire \blk00000001/sig0000018d ;
wire \blk00000001/sig0000018c ;
wire \blk00000001/sig0000018b ;
wire \blk00000001/sig0000018a ;
wire \blk00000001/sig00000189 ;
wire \blk00000001/sig00000188 ;
wire \blk00000001/sig00000187 ;
wire \blk00000001/sig00000186 ;
wire \blk00000001/sig00000185 ;
wire \blk00000001/sig00000184 ;
wire \blk00000001/sig00000183 ;
wire \blk00000001/sig00000182 ;
wire \blk00000001/sig00000181 ;
wire \blk00000001/sig00000180 ;
wire \blk00000001/sig0000017f ;
wire \blk00000001/sig0000017e ;
wire \blk00000001/sig0000017d ;
wire \blk00000001/sig0000017c ;
wire \blk00000001/sig0000017b ;
wire \blk00000001/sig0000017a ;
wire \blk00000001/sig00000179 ;
wire \blk00000001/sig00000178 ;
wire \blk00000001/sig00000177 ;
wire \blk00000001/sig00000176 ;
wire \blk00000001/sig00000175 ;
wire \blk00000001/sig00000174 ;
wire \blk00000001/sig00000173 ;
wire \blk00000001/sig00000172 ;
wire \blk00000001/sig00000171 ;
wire \blk00000001/sig00000170 ;
wire \blk00000001/sig0000016f ;
wire \blk00000001/sig0000016e ;
wire \blk00000001/sig0000016d ;
wire \blk00000001/sig0000016c ;
wire \blk00000001/sig0000016b ;
wire \blk00000001/sig0000016a ;
wire \blk00000001/sig00000169 ;
wire \blk00000001/sig00000168 ;
wire \blk00000001/sig00000167 ;
wire \blk00000001/sig00000166 ;
wire \blk00000001/sig00000165 ;
wire \blk00000001/sig00000164 ;
wire \blk00000001/sig00000163 ;
wire \blk00000001/sig00000162 ;
wire \blk00000001/sig00000161 ;
wire \blk00000001/sig00000160 ;
wire \blk00000001/sig0000015f ;
wire \blk00000001/sig0000015e ;
wire \blk00000001/sig0000015d ;
wire \blk00000001/sig0000015c ;
wire \blk00000001/sig0000015b ;
wire \blk00000001/sig0000015a ;
wire \blk00000001/sig00000159 ;
wire \blk00000001/sig00000158 ;
wire \blk00000001/sig00000157 ;
wire \blk00000001/sig00000156 ;
wire \blk00000001/sig00000155 ;
wire \blk00000001/sig00000154 ;
wire \blk00000001/sig00000153 ;
wire \blk00000001/sig00000152 ;
wire \blk00000001/sig00000151 ;
wire \blk00000001/sig00000150 ;
wire \blk00000001/sig0000014f ;
wire \blk00000001/sig0000014e ;
wire \blk00000001/sig0000014d ;
wire \blk00000001/sig0000014c ;
wire \blk00000001/sig0000014b ;
wire \blk00000001/sig0000014a ;
wire \blk00000001/sig00000149 ;
wire \blk00000001/sig00000148 ;
wire \blk00000001/sig00000147 ;
wire \blk00000001/sig00000146 ;
wire \blk00000001/sig00000145 ;
wire \blk00000001/sig00000144 ;
wire \blk00000001/sig00000143 ;
wire \blk00000001/sig00000142 ;
wire \blk00000001/sig00000141 ;
wire \blk00000001/sig00000140 ;
wire \blk00000001/sig0000013f ;
wire \blk00000001/sig0000013e ;
wire \blk00000001/sig0000013d ;
wire \blk00000001/sig0000013c ;
wire \blk00000001/sig0000013b ;
wire \blk00000001/sig0000013a ;
wire \blk00000001/sig00000139 ;
wire \blk00000001/sig00000138 ;
wire \blk00000001/sig00000137 ;
wire \blk00000001/sig00000136 ;
wire \blk00000001/sig00000135 ;
wire \blk00000001/sig00000134 ;
wire \blk00000001/sig00000133 ;
wire \blk00000001/sig00000132 ;
wire \blk00000001/sig00000131 ;
wire \blk00000001/sig00000130 ;
wire \blk00000001/sig0000012f ;
wire \blk00000001/sig0000012e ;
wire \blk00000001/sig0000012d ;
wire \blk00000001/sig0000012c ;
wire \blk00000001/sig0000012b ;
wire \blk00000001/sig0000012a ;
wire \blk00000001/sig00000129 ;
wire \blk00000001/sig00000128 ;
wire \blk00000001/sig00000127 ;
wire \blk00000001/sig00000126 ;
wire \blk00000001/sig00000125 ;
wire \blk00000001/sig00000124 ;
wire \blk00000001/sig00000123 ;
wire \blk00000001/sig00000122 ;
wire \blk00000001/sig00000121 ;
wire \blk00000001/sig00000120 ;
wire \blk00000001/sig0000011f ;
wire \blk00000001/sig0000011e ;
wire \blk00000001/sig0000011d ;
wire \blk00000001/sig0000011c ;
wire \blk00000001/sig0000011b ;
wire \blk00000001/sig0000011a ;
wire \blk00000001/sig00000119 ;
wire \blk00000001/sig00000118 ;
wire \blk00000001/sig00000117 ;
wire \blk00000001/sig00000116 ;
wire \blk00000001/sig00000115 ;
wire \blk00000001/sig00000114 ;
wire \blk00000001/sig00000113 ;
wire \blk00000001/sig00000112 ;
wire \blk00000001/sig00000111 ;
wire \blk00000001/sig00000110 ;
wire \blk00000001/sig0000010f ;
wire \blk00000001/sig0000010e ;
wire \blk00000001/sig0000010d ;
wire \blk00000001/sig0000010c ;
wire \blk00000001/sig0000010b ;
wire \blk00000001/sig0000010a ;
wire \blk00000001/sig00000109 ;
wire \blk00000001/sig00000108 ;
wire \blk00000001/sig00000107 ;
wire \blk00000001/sig00000106 ;
wire \blk00000001/sig00000105 ;
wire \blk00000001/sig00000104 ;
wire \blk00000001/sig00000103 ;
wire \blk00000001/sig00000102 ;
wire \blk00000001/sig00000101 ;
wire \blk00000001/sig00000100 ;
wire \blk00000001/sig000000ff ;
wire \blk00000001/sig000000fe ;
wire \blk00000001/sig000000fd ;
wire \blk00000001/sig000000fc ;
wire \blk00000001/sig000000fb ;
wire \blk00000001/sig000000fa ;
wire \blk00000001/sig000000f9 ;
wire \blk00000001/sig000000f8 ;
wire \blk00000001/sig000000f7 ;
wire \blk00000001/sig000000f6 ;
wire \blk00000001/sig000000f5 ;
wire \blk00000001/sig000000f4 ;
wire \blk00000001/sig000000f3 ;
wire \blk00000001/sig000000f2 ;
wire \blk00000001/sig000000f1 ;
wire \blk00000001/sig000000f0 ;
wire \blk00000001/sig000000ef ;
wire \blk00000001/sig000000ee ;
wire \blk00000001/sig000000ed ;
wire \blk00000001/sig000000ec ;
wire \blk00000001/sig000000eb ;
wire \blk00000001/sig000000ea ;
wire \blk00000001/sig000000e9 ;
wire \blk00000001/sig000000e8 ;
wire \blk00000001/sig000000e7 ;
wire \blk00000001/sig000000e6 ;
wire \blk00000001/sig000000e5 ;
wire \blk00000001/sig000000e4 ;
wire \blk00000001/sig000000e3 ;
wire \blk00000001/sig000000e2 ;
wire \blk00000001/sig000000e1 ;
wire \blk00000001/sig000000e0 ;
wire \blk00000001/sig000000df ;
wire \blk00000001/sig000000de ;
wire \blk00000001/sig000000dd ;
wire \blk00000001/sig000000dc ;
wire \blk00000001/sig000000db ;
wire \blk00000001/sig000000da ;
wire \blk00000001/sig000000d9 ;
wire \blk00000001/sig000000d8 ;
wire \blk00000001/sig000000d7 ;
wire \blk00000001/sig000000d6 ;
wire \blk00000001/sig000000d5 ;
wire \blk00000001/sig000000d4 ;
wire \blk00000001/sig000000d3 ;
wire \blk00000001/sig000000d2 ;
wire \blk00000001/sig000000d1 ;
wire \blk00000001/sig000000d0 ;
wire \blk00000001/sig000000cf ;
wire \blk00000001/sig000000ce ;
wire \blk00000001/sig000000cd ;
wire \blk00000001/sig000000cc ;
wire \blk00000001/sig000000cb ;
wire \blk00000001/sig000000ca ;
wire \blk00000001/sig000000c9 ;
wire \blk00000001/sig000000c8 ;
wire \blk00000001/sig000000c7 ;
wire \blk00000001/sig000000c6 ;
wire \blk00000001/sig000000c5 ;
wire \blk00000001/sig000000c4 ;
wire \blk00000001/sig000000c3 ;
wire \blk00000001/sig000000c2 ;
wire \blk00000001/sig000000c1 ;
wire \blk00000001/sig000000c0 ;
wire \blk00000001/sig000000bf ;
wire \blk00000001/sig000000be ;
wire \blk00000001/sig000000bd ;
wire \blk00000001/sig000000bc ;
wire \blk00000001/sig000000bb ;
wire \blk00000001/sig000000ba ;
wire \blk00000001/sig000000b9 ;
wire \blk00000001/sig000000b8 ;
wire \blk00000001/sig000000b7 ;
wire \blk00000001/sig000000b6 ;
wire \blk00000001/sig000000b5 ;
wire \blk00000001/sig000000b4 ;
wire \blk00000001/sig000000b3 ;
wire \blk00000001/sig000000b2 ;
wire \blk00000001/sig000000b1 ;
wire \blk00000001/sig000000b0 ;
wire \blk00000001/sig000000af ;
wire \blk00000001/sig000000ae ;
wire \blk00000001/sig000000ad ;
wire \blk00000001/sig000000ac ;
wire \blk00000001/sig000000ab ;
wire \blk00000001/sig000000aa ;
wire \blk00000001/sig000000a9 ;
wire \blk00000001/sig000000a8 ;
wire \blk00000001/sig000000a7 ;
wire \blk00000001/sig000000a6 ;
wire \blk00000001/sig000000a5 ;
wire \blk00000001/sig000000a4 ;
wire \blk00000001/sig000000a3 ;
wire \blk00000001/sig000000a2 ;
wire \blk00000001/sig000000a1 ;
wire \blk00000001/sig000000a0 ;
wire \blk00000001/sig0000009f ;
wire \blk00000001/sig0000009e ;
wire \blk00000001/sig0000009d ;
wire \blk00000001/sig0000009c ;
wire \blk00000001/sig0000009b ;
wire \blk00000001/sig0000009a ;
wire \blk00000001/sig00000099 ;
wire \blk00000001/sig00000098 ;
wire \blk00000001/sig00000097 ;
wire \blk00000001/sig00000096 ;
wire \blk00000001/sig00000095 ;
wire \blk00000001/sig00000094 ;
wire \blk00000001/sig00000093 ;
wire \blk00000001/sig00000092 ;
wire \blk00000001/sig00000091 ;
wire \blk00000001/sig00000090 ;
wire \blk00000001/sig0000008f ;
wire \blk00000001/sig0000008e ;
wire \blk00000001/sig0000008d ;
wire \blk00000001/sig0000008c ;
wire \blk00000001/sig0000008b ;
wire \blk00000001/sig0000008a ;
wire \blk00000001/sig00000089 ;
wire \blk00000001/sig00000088 ;
wire \blk00000001/sig00000087 ;
wire \blk00000001/sig00000086 ;
wire \blk00000001/sig00000085 ;
wire \blk00000001/sig00000084 ;
wire \blk00000001/sig00000083 ;
wire \blk00000001/sig00000082 ;
wire \blk00000001/sig00000081 ;
wire \blk00000001/sig00000080 ;
wire \blk00000001/sig0000007f ;
wire \blk00000001/sig0000007e ;
wire \blk00000001/sig0000007d ;
wire \blk00000001/sig0000007c ;
wire \blk00000001/sig0000007b ;
wire \blk00000001/sig0000007a ;
wire \blk00000001/sig00000079 ;
wire \blk00000001/sig00000078 ;
wire \blk00000001/sig00000077 ;
wire \blk00000001/sig00000076 ;
wire \blk00000001/sig00000075 ;
wire \blk00000001/sig00000074 ;
wire \blk00000001/sig00000073 ;
wire \blk00000001/sig00000072 ;
wire \blk00000001/sig00000071 ;
wire \blk00000001/sig00000070 ;
wire \blk00000001/sig0000006f ;
wire \blk00000001/sig0000006e ;
wire \blk00000001/sig0000006d ;
wire \blk00000001/sig0000006c ;
wire \blk00000001/sig0000006b ;
wire \blk00000001/sig0000006a ;
wire \blk00000001/sig00000069 ;
wire \blk00000001/sig00000068 ;
wire \blk00000001/sig00000067 ;
wire \blk00000001/sig00000066 ;
wire \blk00000001/sig00000065 ;
wire \blk00000001/sig00000064 ;
wire \blk00000001/sig00000063 ;
wire \blk00000001/sig00000062 ;
wire \blk00000001/sig00000061 ;
wire \blk00000001/sig00000060 ;
wire \blk00000001/sig0000005f ;
wire \blk00000001/sig0000005e ;
wire \blk00000001/sig0000005d ;
wire \blk00000001/sig0000005c ;
wire \blk00000001/sig0000005b ;
wire \blk00000001/sig0000005a ;
wire \blk00000001/sig00000059 ;
wire \blk00000001/sig00000058 ;
wire \blk00000001/sig00000057 ;
wire \blk00000001/sig00000056 ;
wire \blk00000001/sig00000055 ;
wire \blk00000001/sig00000054 ;
wire \blk00000001/sig00000053 ;
wire \blk00000001/sig00000052 ;
wire \blk00000001/sig00000051 ;
wire \blk00000001/sig00000050 ;
wire \blk00000001/sig0000004f ;
wire \blk00000001/sig0000004e ;
wire \blk00000001/sig0000004d ;
wire \blk00000001/sig0000004c ;
wire \blk00000001/sig0000004b ;
wire \blk00000001/sig0000004a ;
wire \blk00000001/sig00000049 ;
wire \blk00000001/sig00000048 ;
wire \blk00000001/sig00000047 ;
wire \blk00000001/sig00000046 ;
wire \blk00000001/sig00000045 ;
wire \blk00000001/sig00000044 ;
wire \blk00000001/sig00000043 ;
wire \blk00000001/sig00000042 ;
wire \blk00000001/sig00000041 ;
wire \blk00000001/sig00000040 ;
wire \blk00000001/sig0000003f ;
wire \blk00000001/sig0000003e ;
wire \blk00000001/sig0000003d ;
wire \blk00000001/sig0000003c ;
wire \blk00000001/sig0000003b ;
wire \blk00000001/sig0000003a ;
wire \blk00000001/sig00000039 ;
wire \blk00000001/sig00000038 ;
wire \blk00000001/sig00000037 ;
wire \blk00000001/sig00000036 ;
wire \blk00000001/sig00000035 ;
wire \blk00000001/sig00000034 ;
wire \blk00000001/sig00000033 ;
wire \blk00000001/sig00000032 ;
wire \NLW_blk00000001/blk0000001e_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<14>_UNCONNECTED ;
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001be (
.C(clk),
.D(\blk00000001/sig000000d8 ),
.Q(\blk00000001/sig000000e9 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001bd (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000135 ),
.Q(\blk00000001/sig000000d8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001bc (
.C(clk),
.D(\blk00000001/sig000000d9 ),
.Q(\blk00000001/sig000000ea )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001bb (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000140 ),
.Q(\blk00000001/sig000000d9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ba (
.C(clk),
.D(\blk00000001/sig000000e2 ),
.Q(\blk00000001/sig000000f3 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b9 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000146 ),
.Q(\blk00000001/sig000000e2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b8 (
.C(clk),
.D(\blk00000001/sig000000e3 ),
.Q(\blk00000001/sig000000f4 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b7 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000147 ),
.Q(\blk00000001/sig000000e3 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b6 (
.C(clk),
.D(\blk00000001/sig000000e1 ),
.Q(\blk00000001/sig000000f2 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b5 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000145 ),
.Q(\blk00000001/sig000000e1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b4 (
.C(clk),
.D(\blk00000001/sig000000e4 ),
.Q(\blk00000001/sig000000f5 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b3 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000148 ),
.Q(\blk00000001/sig000000e4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b2 (
.C(clk),
.D(\blk00000001/sig000000e5 ),
.Q(\blk00000001/sig000000f6 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b1 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000149 ),
.Q(\blk00000001/sig000000e5 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b0 (
.C(clk),
.D(\blk00000001/sig000000e7 ),
.Q(\blk00000001/sig000000f8 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001af (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig0000014b ),
.Q(\blk00000001/sig000000e7 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ae (
.C(clk),
.D(\blk00000001/sig000000e8 ),
.Q(\blk00000001/sig000000f9 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001ad (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig0000014c ),
.Q(\blk00000001/sig000000e8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ac (
.C(clk),
.D(\blk00000001/sig000000e6 ),
.Q(\blk00000001/sig000000f7 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001ab (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig0000014a ),
.Q(\blk00000001/sig000000e6 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001aa (
.C(clk),
.D(\blk00000001/sig000000da ),
.Q(\blk00000001/sig000000eb )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a9 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000136 ),
.Q(\blk00000001/sig000000da )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a8 (
.C(clk),
.D(\blk00000001/sig000000db ),
.Q(\blk00000001/sig000000ec )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a7 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000137 ),
.Q(\blk00000001/sig000000db )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a6 (
.C(clk),
.D(\blk00000001/sig000000dd ),
.Q(\blk00000001/sig000000ee )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a5 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000139 ),
.Q(\blk00000001/sig000000dd )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a4 (
.C(clk),
.D(\blk00000001/sig000000de ),
.Q(\blk00000001/sig000000ef )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a3 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig0000013a ),
.Q(\blk00000001/sig000000de )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a2 (
.C(clk),
.D(\blk00000001/sig000000dc ),
.Q(\blk00000001/sig000000ed )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a1 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000138 ),
.Q(\blk00000001/sig000000dc )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a0 (
.C(clk),
.D(\blk00000001/sig000000e0 ),
.Q(\blk00000001/sig000000f1 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000019f (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig0000013c ),
.Q(\blk00000001/sig000000e0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019e (
.C(clk),
.D(\blk00000001/sig00000043 ),
.Q(p[24])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000019d (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000202 ),
.Q(\blk00000001/sig00000043 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019c (
.C(clk),
.D(\blk00000001/sig000000df ),
.Q(\blk00000001/sig000000f0 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000019b (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig0000013b ),
.Q(\blk00000001/sig000000df )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019a (
.C(clk),
.D(\blk00000001/sig00000041 ),
.Q(p[22])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000199 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000200 ),
.Q(\blk00000001/sig00000041 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000198 (
.C(clk),
.D(\blk00000001/sig00000040 ),
.Q(p[21])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000197 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000001fe ),
.Q(\blk00000001/sig00000040 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000196 (
.C(clk),
.D(\blk00000001/sig00000042 ),
.Q(p[23])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000195 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000201 ),
.Q(\blk00000001/sig00000042 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000194 (
.C(clk),
.D(\blk00000001/sig0000003f ),
.Q(p[20])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000193 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000001fd ),
.Q(\blk00000001/sig0000003f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000192 (
.C(clk),
.D(\blk00000001/sig0000003d ),
.Q(p[19])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000191 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000001fc ),
.Q(\blk00000001/sig0000003d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000190 (
.C(clk),
.D(\blk00000001/sig0000003b ),
.Q(p[17])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000018f (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000001e6 ),
.Q(\blk00000001/sig0000003b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018e (
.C(clk),
.D(\blk00000001/sig0000003a ),
.Q(p[16])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000018d (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000101 ),
.Q(\blk00000001/sig0000003a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018c (
.C(clk),
.D(\blk00000001/sig0000003c ),
.Q(p[18])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000018b (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000001f1 ),
.Q(\blk00000001/sig0000003c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018a (
.C(clk),
.D(\blk00000001/sig00000039 ),
.Q(p[15])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000189 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000100 ),
.Q(\blk00000001/sig00000039 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000188 (
.C(clk),
.D(\blk00000001/sig00000038 ),
.Q(p[14])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000187 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000000ff ),
.Q(\blk00000001/sig00000038 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000186 (
.C(clk),
.D(\blk00000001/sig00000036 ),
.Q(p[12])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000185 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000000fd ),
.Q(\blk00000001/sig00000036 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000184 (
.C(clk),
.D(\blk00000001/sig00000035 ),
.Q(p[11])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000183 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000000fc ),
.Q(\blk00000001/sig00000035 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000182 (
.C(clk),
.D(\blk00000001/sig00000037 ),
.Q(p[13])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000181 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000000fe ),
.Q(\blk00000001/sig00000037 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000180 (
.C(clk),
.D(\blk00000001/sig00000034 ),
.Q(p[10])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000017f (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000000fb ),
.Q(\blk00000001/sig00000034 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017e (
.C(clk),
.D(\blk00000001/sig0000004a ),
.Q(p[9])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000017d (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig0000011c ),
.Q(\blk00000001/sig0000004a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017c (
.C(clk),
.D(\blk00000001/sig00000048 ),
.Q(p[7])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000017b (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig0000011a ),
.Q(\blk00000001/sig00000048 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017a (
.C(clk),
.D(\blk00000001/sig00000047 ),
.Q(p[6])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000179 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000119 ),
.Q(\blk00000001/sig00000047 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000178 (
.C(clk),
.D(\blk00000001/sig00000049 ),
.Q(p[8])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000177 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig0000011b ),
.Q(\blk00000001/sig00000049 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000176 (
.C(clk),
.D(\blk00000001/sig00000045 ),
.Q(p[4])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000175 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000117 ),
.Q(\blk00000001/sig00000045 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000174 (
.C(clk),
.D(\blk00000001/sig00000044 ),
.Q(p[3])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000173 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000116 ),
.Q(\blk00000001/sig00000044 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000172 (
.C(clk),
.D(\blk00000001/sig00000046 ),
.Q(p[5])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000171 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000118 ),
.Q(\blk00000001/sig00000046 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000170 (
.C(clk),
.D(\blk00000001/sig00000033 ),
.Q(p[1])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000016f (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000105 ),
.Q(\blk00000001/sig00000033 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016e (
.C(clk),
.D(\blk00000001/sig00000032 ),
.Q(p[0])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000016d (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000000fa ),
.Q(\blk00000001/sig00000032 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016c (
.C(clk),
.D(\blk00000001/sig0000003e ),
.Q(p[2])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000016b (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000110 ),
.Q(\blk00000001/sig0000003e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016a (
.C(clk),
.D(\blk00000001/sig00000102 ),
.Q(\blk00000001/sig0000015b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000169 (
.C(clk),
.D(\blk00000001/sig00000103 ),
.Q(\blk00000001/sig0000015c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000168 (
.C(clk),
.D(\blk00000001/sig00000104 ),
.Q(\blk00000001/sig0000015d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000167 (
.C(clk),
.D(\blk00000001/sig00000106 ),
.Q(\blk00000001/sig0000015e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000166 (
.C(clk),
.D(\blk00000001/sig00000107 ),
.Q(\blk00000001/sig0000015f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000165 (
.C(clk),
.D(\blk00000001/sig00000108 ),
.Q(\blk00000001/sig00000160 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000164 (
.C(clk),
.D(\blk00000001/sig00000109 ),
.Q(\blk00000001/sig00000161 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000163 (
.C(clk),
.D(\blk00000001/sig0000010a ),
.Q(\blk00000001/sig00000162 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000162 (
.C(clk),
.D(\blk00000001/sig0000010b ),
.Q(\blk00000001/sig00000163 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000161 (
.C(clk),
.D(\blk00000001/sig0000010c ),
.Q(\blk00000001/sig00000164 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000160 (
.C(clk),
.D(\blk00000001/sig0000010d ),
.Q(\blk00000001/sig00000165 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015f (
.C(clk),
.D(\blk00000001/sig0000010e ),
.Q(\blk00000001/sig00000166 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015e (
.C(clk),
.D(\blk00000001/sig0000010f ),
.Q(\blk00000001/sig00000167 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015d (
.C(clk),
.D(\blk00000001/sig00000111 ),
.Q(\blk00000001/sig00000168 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015c (
.C(clk),
.D(\blk00000001/sig00000112 ),
.Q(\blk00000001/sig00000169 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015b (
.C(clk),
.D(\blk00000001/sig00000113 ),
.Q(\blk00000001/sig0000016a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015a (
.C(clk),
.D(\blk00000001/sig00000114 ),
.Q(\blk00000001/sig0000016b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000159 (
.C(clk),
.D(\blk00000001/sig00000115 ),
.Q(\blk00000001/sig0000016c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000158 (
.C(clk),
.D(\blk00000001/sig0000011d ),
.Q(\blk00000001/sig0000016d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000157 (
.C(clk),
.D(\blk00000001/sig00000128 ),
.Q(\blk00000001/sig0000016e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000156 (
.C(clk),
.D(\blk00000001/sig0000012d ),
.Q(\blk00000001/sig00000179 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000155 (
.C(clk),
.D(\blk00000001/sig0000012e ),
.Q(\blk00000001/sig0000017e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000154 (
.C(clk),
.D(\blk00000001/sig0000012f ),
.Q(\blk00000001/sig0000017f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000153 (
.C(clk),
.D(\blk00000001/sig00000130 ),
.Q(\blk00000001/sig00000180 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000152 (
.C(clk),
.D(\blk00000001/sig00000131 ),
.Q(\blk00000001/sig00000181 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000151 (
.C(clk),
.D(\blk00000001/sig00000132 ),
.Q(\blk00000001/sig00000182 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000150 (
.C(clk),
.D(\blk00000001/sig00000133 ),
.Q(\blk00000001/sig00000183 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014f (
.C(clk),
.D(\blk00000001/sig00000134 ),
.Q(\blk00000001/sig00000184 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014e (
.C(clk),
.D(\blk00000001/sig0000011e ),
.Q(\blk00000001/sig0000016f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014d (
.C(clk),
.D(\blk00000001/sig0000011f ),
.Q(\blk00000001/sig00000170 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014c (
.C(clk),
.D(\blk00000001/sig00000120 ),
.Q(\blk00000001/sig00000171 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014b (
.C(clk),
.D(\blk00000001/sig00000121 ),
.Q(\blk00000001/sig00000172 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014a (
.C(clk),
.D(\blk00000001/sig00000122 ),
.Q(\blk00000001/sig00000173 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000149 (
.C(clk),
.D(\blk00000001/sig00000123 ),
.Q(\blk00000001/sig00000174 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000148 (
.C(clk),
.D(\blk00000001/sig00000124 ),
.Q(\blk00000001/sig00000175 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000147 (
.C(clk),
.D(\blk00000001/sig00000125 ),
.Q(\blk00000001/sig00000176 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000146 (
.C(clk),
.D(\blk00000001/sig00000126 ),
.Q(\blk00000001/sig00000177 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000145 (
.C(clk),
.D(\blk00000001/sig00000127 ),
.Q(\blk00000001/sig00000178 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000144 (
.C(clk),
.D(\blk00000001/sig00000129 ),
.Q(\blk00000001/sig0000017a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000143 (
.C(clk),
.D(\blk00000001/sig0000012a ),
.Q(\blk00000001/sig0000017b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000142 (
.C(clk),
.D(\blk00000001/sig0000012b ),
.Q(\blk00000001/sig0000017c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000141 (
.C(clk),
.D(\blk00000001/sig0000012c ),
.Q(\blk00000001/sig0000017d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000140 (
.C(clk),
.D(\blk00000001/sig0000013d ),
.Q(\blk00000001/sig00000185 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013f (
.C(clk),
.D(\blk00000001/sig0000013e ),
.Q(\blk00000001/sig00000186 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013e (
.C(clk),
.D(\blk00000001/sig0000013f ),
.Q(\blk00000001/sig00000187 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013d (
.C(clk),
.D(\blk00000001/sig00000141 ),
.Q(\blk00000001/sig00000188 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013c (
.C(clk),
.D(\blk00000001/sig00000142 ),
.Q(\blk00000001/sig00000189 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013b (
.C(clk),
.D(\blk00000001/sig00000143 ),
.Q(\blk00000001/sig0000018a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013a (
.C(clk),
.D(\blk00000001/sig00000144 ),
.Q(\blk00000001/sig0000018b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000139 (
.C(clk),
.D(\blk00000001/sig0000014d ),
.Q(\blk00000001/sig0000018c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000138 (
.C(clk),
.D(\blk00000001/sig00000152 ),
.Q(\blk00000001/sig0000018d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000137 (
.C(clk),
.D(\blk00000001/sig00000153 ),
.Q(\blk00000001/sig00000192 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000136 (
.C(clk),
.D(\blk00000001/sig00000154 ),
.Q(\blk00000001/sig00000193 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000135 (
.C(clk),
.D(\blk00000001/sig00000155 ),
.Q(\blk00000001/sig00000194 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000134 (
.C(clk),
.D(\blk00000001/sig00000156 ),
.Q(\blk00000001/sig00000195 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000133 (
.C(clk),
.D(\blk00000001/sig00000157 ),
.Q(\blk00000001/sig00000196 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000132 (
.C(clk),
.D(\blk00000001/sig00000158 ),
.Q(\blk00000001/sig00000197 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000131 (
.C(clk),
.D(\blk00000001/sig00000159 ),
.Q(\blk00000001/sig00000198 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000130 (
.C(clk),
.D(\blk00000001/sig0000015a ),
.Q(\blk00000001/sig00000199 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012f (
.C(clk),
.D(\blk00000001/sig0000014e ),
.Q(\blk00000001/sig0000018e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012e (
.C(clk),
.D(\blk00000001/sig0000014f ),
.Q(\blk00000001/sig0000018f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012d (
.C(clk),
.D(\blk00000001/sig00000150 ),
.Q(\blk00000001/sig00000190 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012c (
.C(clk),
.D(\blk00000001/sig00000151 ),
.Q(\blk00000001/sig00000191 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012b (
.C(clk),
.D(\blk00000001/sig000001ca ),
.Q(\blk00000001/sig000001d8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012a (
.C(clk),
.D(\blk00000001/sig000001cf ),
.Q(\blk00000001/sig000001d9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000129 (
.C(clk),
.D(\blk00000001/sig000001d0 ),
.Q(\blk00000001/sig000001de )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000128 (
.C(clk),
.D(\blk00000001/sig000001d1 ),
.Q(\blk00000001/sig000001df )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000127 (
.C(clk),
.D(\blk00000001/sig000001d2 ),
.Q(\blk00000001/sig000001e0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000126 (
.C(clk),
.D(\blk00000001/sig000001d3 ),
.Q(\blk00000001/sig000001e1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000125 (
.C(clk),
.D(\blk00000001/sig000001d4 ),
.Q(\blk00000001/sig000001e2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000124 (
.C(clk),
.D(\blk00000001/sig000001d5 ),
.Q(\blk00000001/sig000001e3 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000123 (
.C(clk),
.D(\blk00000001/sig000001d6 ),
.Q(\blk00000001/sig000001e4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000122 (
.C(clk),
.D(\blk00000001/sig000001d7 ),
.Q(\blk00000001/sig000001e5 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000121 (
.C(clk),
.D(\blk00000001/sig000001cb ),
.Q(\blk00000001/sig000001da )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000120 (
.C(clk),
.D(\blk00000001/sig000001cc ),
.Q(\blk00000001/sig000001db )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011f (
.C(clk),
.D(\blk00000001/sig000001cd ),
.Q(\blk00000001/sig000001dc )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011e (
.C(clk),
.D(\blk00000001/sig000001ce ),
.Q(\blk00000001/sig000001dd )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011d (
.C(clk),
.D(\blk00000001/sig0000019a ),
.Q(\blk00000001/sig000001b2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011c (
.C(clk),
.D(\blk00000001/sig000001a5 ),
.Q(\blk00000001/sig000001b3 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011b (
.C(clk),
.D(\blk00000001/sig000001aa ),
.Q(\blk00000001/sig000001be )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011a (
.C(clk),
.D(\blk00000001/sig000001ab ),
.Q(\blk00000001/sig000001c3 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000119 (
.C(clk),
.D(\blk00000001/sig000001ac ),
.Q(\blk00000001/sig000001c4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000118 (
.C(clk),
.D(\blk00000001/sig000001ad ),
.Q(\blk00000001/sig000001c5 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000117 (
.C(clk),
.D(\blk00000001/sig000001ae ),
.Q(\blk00000001/sig000001c6 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000116 (
.C(clk),
.D(\blk00000001/sig000001af ),
.Q(\blk00000001/sig000001c7 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000115 (
.C(clk),
.D(\blk00000001/sig000001b0 ),
.Q(\blk00000001/sig000001c8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000114 (
.C(clk),
.D(\blk00000001/sig000001b1 ),
.Q(\blk00000001/sig000001c9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000113 (
.C(clk),
.D(\blk00000001/sig0000019b ),
.Q(\blk00000001/sig000001b4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000112 (
.C(clk),
.D(\blk00000001/sig0000019c ),
.Q(\blk00000001/sig000001b5 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000111 (
.C(clk),
.D(\blk00000001/sig0000019d ),
.Q(\blk00000001/sig000001b6 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000110 (
.C(clk),
.D(\blk00000001/sig0000019e ),
.Q(\blk00000001/sig000001b7 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010f (
.C(clk),
.D(\blk00000001/sig0000019f ),
.Q(\blk00000001/sig000001b8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010e (
.C(clk),
.D(\blk00000001/sig000001a0 ),
.Q(\blk00000001/sig000001b9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010d (
.C(clk),
.D(\blk00000001/sig000001a1 ),
.Q(\blk00000001/sig000001ba )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010c (
.C(clk),
.D(\blk00000001/sig000001a2 ),
.Q(\blk00000001/sig000001bb )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010b (
.C(clk),
.D(\blk00000001/sig000001a3 ),
.Q(\blk00000001/sig000001bc )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010a (
.C(clk),
.D(\blk00000001/sig000001a4 ),
.Q(\blk00000001/sig000001bd )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000109 (
.C(clk),
.D(\blk00000001/sig000001a6 ),
.Q(\blk00000001/sig000001bf )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000108 (
.C(clk),
.D(\blk00000001/sig000001a7 ),
.Q(\blk00000001/sig000001c0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000107 (
.C(clk),
.D(\blk00000001/sig000001a8 ),
.Q(\blk00000001/sig000001c1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000106 (
.C(clk),
.D(\blk00000001/sig000001a9 ),
.Q(\blk00000001/sig000001c2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000105 (
.C(clk),
.D(\blk00000001/sig00000203 ),
.Q(\blk00000001/sig0000021a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000104 (
.C(clk),
.D(\blk00000001/sig00000204 ),
.Q(\blk00000001/sig0000021b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000103 (
.C(clk),
.D(\blk00000001/sig000001e7 ),
.Q(\blk00000001/sig00000205 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000102 (
.C(clk),
.D(\blk00000001/sig000001e8 ),
.Q(\blk00000001/sig00000206 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000101 (
.C(clk),
.D(\blk00000001/sig000001e9 ),
.Q(\blk00000001/sig00000207 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000100 (
.C(clk),
.D(\blk00000001/sig000001ea ),
.Q(\blk00000001/sig00000208 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ff (
.C(clk),
.D(\blk00000001/sig000001eb ),
.Q(\blk00000001/sig00000209 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fe (
.C(clk),
.D(\blk00000001/sig000001ec ),
.Q(\blk00000001/sig0000020a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fd (
.C(clk),
.D(\blk00000001/sig000001ed ),
.Q(\blk00000001/sig0000020b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fc (
.C(clk),
.D(\blk00000001/sig000001ee ),
.Q(\blk00000001/sig0000020c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fb (
.C(clk),
.D(\blk00000001/sig000001ef ),
.Q(\blk00000001/sig0000020d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fa (
.C(clk),
.D(\blk00000001/sig000001f0 ),
.Q(\blk00000001/sig0000020e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f9 (
.C(clk),
.D(\blk00000001/sig000001f2 ),
.Q(\blk00000001/sig0000020f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f8 (
.C(clk),
.D(\blk00000001/sig000001f3 ),
.Q(\blk00000001/sig00000210 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f7 (
.C(clk),
.D(\blk00000001/sig000001f4 ),
.Q(\blk00000001/sig00000211 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f6 (
.C(clk),
.D(\blk00000001/sig000001f5 ),
.Q(\blk00000001/sig00000212 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f5 (
.C(clk),
.D(\blk00000001/sig000001f6 ),
.Q(\blk00000001/sig00000213 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f4 (
.C(clk),
.D(\blk00000001/sig000001f7 ),
.Q(\blk00000001/sig00000214 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f3 (
.C(clk),
.D(\blk00000001/sig000001f8 ),
.Q(\blk00000001/sig00000215 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f2 (
.C(clk),
.D(\blk00000001/sig000001f9 ),
.Q(\blk00000001/sig00000216 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f1 (
.C(clk),
.D(\blk00000001/sig000001fa ),
.Q(\blk00000001/sig00000217 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f0 (
.C(clk),
.D(\blk00000001/sig000001fb ),
.Q(\blk00000001/sig00000218 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ef (
.C(clk),
.D(\blk00000001/sig000001ff ),
.Q(\blk00000001/sig00000219 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ee (
.I0(\blk00000001/sig00000185 ),
.I1(\blk00000001/sig0000018c ),
.O(\blk00000001/sig00000089 )
);
MUXCY \blk00000001/blk000000ed (
.CI(\blk00000001/sig0000004b ),
.DI(\blk00000001/sig00000185 ),
.S(\blk00000001/sig00000089 ),
.O(\blk00000001/sig0000007c )
);
XORCY \blk00000001/blk000000ec (
.CI(\blk00000001/sig0000004b ),
.LI(\blk00000001/sig00000089 ),
.O(\blk00000001/sig000001ca )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000eb (
.I0(\blk00000001/sig00000186 ),
.I1(\blk00000001/sig0000018d ),
.O(\blk00000001/sig0000008e )
);
MUXCY \blk00000001/blk000000ea (
.CI(\blk00000001/sig0000007c ),
.DI(\blk00000001/sig00000186 ),
.S(\blk00000001/sig0000008e ),
.O(\blk00000001/sig00000080 )
);
XORCY \blk00000001/blk000000e9 (
.CI(\blk00000001/sig0000007c ),
.LI(\blk00000001/sig0000008e ),
.O(\blk00000001/sig000001cf )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000e8 (
.I0(\blk00000001/sig00000187 ),
.I1(\blk00000001/sig00000192 ),
.O(\blk00000001/sig0000008f )
);
MUXCY \blk00000001/blk000000e7 (
.CI(\blk00000001/sig00000080 ),
.DI(\blk00000001/sig00000187 ),
.S(\blk00000001/sig0000008f ),
.O(\blk00000001/sig00000081 )
);
XORCY \blk00000001/blk000000e6 (
.CI(\blk00000001/sig00000080 ),
.LI(\blk00000001/sig0000008f ),
.O(\blk00000001/sig000001d0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000e5 (
.I0(\blk00000001/sig00000188 ),
.I1(\blk00000001/sig00000193 ),
.O(\blk00000001/sig00000090 )
);
MUXCY \blk00000001/blk000000e4 (
.CI(\blk00000001/sig00000081 ),
.DI(\blk00000001/sig00000188 ),
.S(\blk00000001/sig00000090 ),
.O(\blk00000001/sig00000082 )
);
XORCY \blk00000001/blk000000e3 (
.CI(\blk00000001/sig00000081 ),
.LI(\blk00000001/sig00000090 ),
.O(\blk00000001/sig000001d1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000e2 (
.I0(\blk00000001/sig00000189 ),
.I1(\blk00000001/sig00000194 ),
.O(\blk00000001/sig00000091 )
);
MUXCY \blk00000001/blk000000e1 (
.CI(\blk00000001/sig00000082 ),
.DI(\blk00000001/sig00000189 ),
.S(\blk00000001/sig00000091 ),
.O(\blk00000001/sig00000083 )
);
XORCY \blk00000001/blk000000e0 (
.CI(\blk00000001/sig00000082 ),
.LI(\blk00000001/sig00000091 ),
.O(\blk00000001/sig000001d2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000df (
.I0(\blk00000001/sig0000018a ),
.I1(\blk00000001/sig00000195 ),
.O(\blk00000001/sig00000092 )
);
MUXCY \blk00000001/blk000000de (
.CI(\blk00000001/sig00000083 ),
.DI(\blk00000001/sig0000018a ),
.S(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000084 )
);
XORCY \blk00000001/blk000000dd (
.CI(\blk00000001/sig00000083 ),
.LI(\blk00000001/sig00000092 ),
.O(\blk00000001/sig000001d3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000dc (
.I0(\blk00000001/sig0000018b ),
.I1(\blk00000001/sig00000196 ),
.O(\blk00000001/sig00000093 )
);
MUXCY \blk00000001/blk000000db (
.CI(\blk00000001/sig00000084 ),
.DI(\blk00000001/sig0000018b ),
.S(\blk00000001/sig00000093 ),
.O(\blk00000001/sig00000085 )
);
XORCY \blk00000001/blk000000da (
.CI(\blk00000001/sig00000084 ),
.LI(\blk00000001/sig00000093 ),
.O(\blk00000001/sig000001d4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d9 (
.I0(\blk00000001/sig0000018b ),
.I1(\blk00000001/sig00000197 ),
.O(\blk00000001/sig00000094 )
);
MUXCY \blk00000001/blk000000d8 (
.CI(\blk00000001/sig00000085 ),
.DI(\blk00000001/sig0000018b ),
.S(\blk00000001/sig00000094 ),
.O(\blk00000001/sig00000086 )
);
XORCY \blk00000001/blk000000d7 (
.CI(\blk00000001/sig00000085 ),
.LI(\blk00000001/sig00000094 ),
.O(\blk00000001/sig000001d5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d6 (
.I0(\blk00000001/sig0000018b ),
.I1(\blk00000001/sig00000198 ),
.O(\blk00000001/sig00000095 )
);
MUXCY \blk00000001/blk000000d5 (
.CI(\blk00000001/sig00000086 ),
.DI(\blk00000001/sig0000018b ),
.S(\blk00000001/sig00000095 ),
.O(\blk00000001/sig00000087 )
);
XORCY \blk00000001/blk000000d4 (
.CI(\blk00000001/sig00000086 ),
.LI(\blk00000001/sig00000095 ),
.O(\blk00000001/sig000001d6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d3 (
.I0(\blk00000001/sig0000018b ),
.I1(\blk00000001/sig00000199 ),
.O(\blk00000001/sig00000096 )
);
MUXCY \blk00000001/blk000000d2 (
.CI(\blk00000001/sig00000087 ),
.DI(\blk00000001/sig0000018b ),
.S(\blk00000001/sig00000096 ),
.O(\blk00000001/sig00000088 )
);
XORCY \blk00000001/blk000000d1 (
.CI(\blk00000001/sig00000087 ),
.LI(\blk00000001/sig00000096 ),
.O(\blk00000001/sig000001d7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d0 (
.I0(\blk00000001/sig0000018b ),
.I1(\blk00000001/sig0000018e ),
.O(\blk00000001/sig0000008a )
);
MUXCY \blk00000001/blk000000cf (
.CI(\blk00000001/sig00000088 ),
.DI(\blk00000001/sig0000018b ),
.S(\blk00000001/sig0000008a ),
.O(\blk00000001/sig0000007d )
);
XORCY \blk00000001/blk000000ce (
.CI(\blk00000001/sig00000088 ),
.LI(\blk00000001/sig0000008a ),
.O(\blk00000001/sig000001cb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000cd (
.I0(\blk00000001/sig0000018b ),
.I1(\blk00000001/sig0000018f ),
.O(\blk00000001/sig0000008b )
);
MUXCY \blk00000001/blk000000cc (
.CI(\blk00000001/sig0000007d ),
.DI(\blk00000001/sig0000018b ),
.S(\blk00000001/sig0000008b ),
.O(\blk00000001/sig0000007e )
);
XORCY \blk00000001/blk000000cb (
.CI(\blk00000001/sig0000007d ),
.LI(\blk00000001/sig0000008b ),
.O(\blk00000001/sig000001cc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ca (
.I0(\blk00000001/sig0000018b ),
.I1(\blk00000001/sig00000190 ),
.O(\blk00000001/sig0000008c )
);
MUXCY \blk00000001/blk000000c9 (
.CI(\blk00000001/sig0000007e ),
.DI(\blk00000001/sig0000018b ),
.S(\blk00000001/sig0000008c ),
.O(\blk00000001/sig0000007f )
);
XORCY \blk00000001/blk000000c8 (
.CI(\blk00000001/sig0000007e ),
.LI(\blk00000001/sig0000008c ),
.O(\blk00000001/sig000001cd )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c7 (
.I0(\blk00000001/sig0000018b ),
.I1(\blk00000001/sig00000191 ),
.O(\blk00000001/sig0000008d )
);
XORCY \blk00000001/blk000000c6 (
.CI(\blk00000001/sig0000007f ),
.LI(\blk00000001/sig0000008d ),
.O(\blk00000001/sig000001ce )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c5 (
.I0(\blk00000001/sig0000015b ),
.I1(\blk00000001/sig0000016d ),
.O(\blk00000001/sig00000064 )
);
MUXCY \blk00000001/blk000000c4 (
.CI(\blk00000001/sig0000004b ),
.DI(\blk00000001/sig0000015b ),
.S(\blk00000001/sig00000064 ),
.O(\blk00000001/sig0000004d )
);
XORCY \blk00000001/blk000000c3 (
.CI(\blk00000001/sig0000004b ),
.LI(\blk00000001/sig00000064 ),
.O(\blk00000001/sig0000019a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c2 (
.I0(\blk00000001/sig0000015c ),
.I1(\blk00000001/sig0000016e ),
.O(\blk00000001/sig0000006f )
);
MUXCY \blk00000001/blk000000c1 (
.CI(\blk00000001/sig0000004d ),
.DI(\blk00000001/sig0000015c ),
.S(\blk00000001/sig0000006f ),
.O(\blk00000001/sig00000058 )
);
XORCY \blk00000001/blk000000c0 (
.CI(\blk00000001/sig0000004d ),
.LI(\blk00000001/sig0000006f ),
.O(\blk00000001/sig000001a5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000bf (
.I0(\blk00000001/sig0000015d ),
.I1(\blk00000001/sig00000179 ),
.O(\blk00000001/sig00000074 )
);
MUXCY \blk00000001/blk000000be (
.CI(\blk00000001/sig00000058 ),
.DI(\blk00000001/sig0000015d ),
.S(\blk00000001/sig00000074 ),
.O(\blk00000001/sig0000005c )
);
XORCY \blk00000001/blk000000bd (
.CI(\blk00000001/sig00000058 ),
.LI(\blk00000001/sig00000074 ),
.O(\blk00000001/sig000001aa )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000bc (
.I0(\blk00000001/sig0000015e ),
.I1(\blk00000001/sig0000017e ),
.O(\blk00000001/sig00000075 )
);
MUXCY \blk00000001/blk000000bb (
.CI(\blk00000001/sig0000005c ),
.DI(\blk00000001/sig0000015e ),
.S(\blk00000001/sig00000075 ),
.O(\blk00000001/sig0000005d )
);
XORCY \blk00000001/blk000000ba (
.CI(\blk00000001/sig0000005c ),
.LI(\blk00000001/sig00000075 ),
.O(\blk00000001/sig000001ab )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000b9 (
.I0(\blk00000001/sig0000015f ),
.I1(\blk00000001/sig0000017f ),
.O(\blk00000001/sig00000076 )
);
MUXCY \blk00000001/blk000000b8 (
.CI(\blk00000001/sig0000005d ),
.DI(\blk00000001/sig0000015f ),
.S(\blk00000001/sig00000076 ),
.O(\blk00000001/sig0000005e )
);
XORCY \blk00000001/blk000000b7 (
.CI(\blk00000001/sig0000005d ),
.LI(\blk00000001/sig00000076 ),
.O(\blk00000001/sig000001ac )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000b6 (
.I0(\blk00000001/sig00000160 ),
.I1(\blk00000001/sig00000180 ),
.O(\blk00000001/sig00000077 )
);
MUXCY \blk00000001/blk000000b5 (
.CI(\blk00000001/sig0000005e ),
.DI(\blk00000001/sig00000160 ),
.S(\blk00000001/sig00000077 ),
.O(\blk00000001/sig0000005f )
);
XORCY \blk00000001/blk000000b4 (
.CI(\blk00000001/sig0000005e ),
.LI(\blk00000001/sig00000077 ),
.O(\blk00000001/sig000001ad )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000b3 (
.I0(\blk00000001/sig00000161 ),
.I1(\blk00000001/sig00000181 ),
.O(\blk00000001/sig00000078 )
);
MUXCY \blk00000001/blk000000b2 (
.CI(\blk00000001/sig0000005f ),
.DI(\blk00000001/sig00000161 ),
.S(\blk00000001/sig00000078 ),
.O(\blk00000001/sig00000060 )
);
XORCY \blk00000001/blk000000b1 (
.CI(\blk00000001/sig0000005f ),
.LI(\blk00000001/sig00000078 ),
.O(\blk00000001/sig000001ae )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000b0 (
.I0(\blk00000001/sig00000162 ),
.I1(\blk00000001/sig00000182 ),
.O(\blk00000001/sig00000079 )
);
MUXCY \blk00000001/blk000000af (
.CI(\blk00000001/sig00000060 ),
.DI(\blk00000001/sig00000162 ),
.S(\blk00000001/sig00000079 ),
.O(\blk00000001/sig00000061 )
);
XORCY \blk00000001/blk000000ae (
.CI(\blk00000001/sig00000060 ),
.LI(\blk00000001/sig00000079 ),
.O(\blk00000001/sig000001af )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ad (
.I0(\blk00000001/sig00000163 ),
.I1(\blk00000001/sig00000183 ),
.O(\blk00000001/sig0000007a )
);
MUXCY \blk00000001/blk000000ac (
.CI(\blk00000001/sig00000061 ),
.DI(\blk00000001/sig00000163 ),
.S(\blk00000001/sig0000007a ),
.O(\blk00000001/sig00000062 )
);
XORCY \blk00000001/blk000000ab (
.CI(\blk00000001/sig00000061 ),
.LI(\blk00000001/sig0000007a ),
.O(\blk00000001/sig000001b0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000aa (
.I0(\blk00000001/sig00000164 ),
.I1(\blk00000001/sig00000184 ),
.O(\blk00000001/sig0000007b )
);
MUXCY \blk00000001/blk000000a9 (
.CI(\blk00000001/sig00000062 ),
.DI(\blk00000001/sig00000164 ),
.S(\blk00000001/sig0000007b ),
.O(\blk00000001/sig00000063 )
);
XORCY \blk00000001/blk000000a8 (
.CI(\blk00000001/sig00000062 ),
.LI(\blk00000001/sig0000007b ),
.O(\blk00000001/sig000001b1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000a7 (
.I0(\blk00000001/sig00000165 ),
.I1(\blk00000001/sig0000016f ),
.O(\blk00000001/sig00000065 )
);
MUXCY \blk00000001/blk000000a6 (
.CI(\blk00000001/sig00000063 ),
.DI(\blk00000001/sig00000165 ),
.S(\blk00000001/sig00000065 ),
.O(\blk00000001/sig0000004e )
);
XORCY \blk00000001/blk000000a5 (
.CI(\blk00000001/sig00000063 ),
.LI(\blk00000001/sig00000065 ),
.O(\blk00000001/sig0000019b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000a4 (
.I0(\blk00000001/sig00000166 ),
.I1(\blk00000001/sig00000170 ),
.O(\blk00000001/sig00000066 )
);
MUXCY \blk00000001/blk000000a3 (
.CI(\blk00000001/sig0000004e ),
.DI(\blk00000001/sig00000166 ),
.S(\blk00000001/sig00000066 ),
.O(\blk00000001/sig0000004f )
);
XORCY \blk00000001/blk000000a2 (
.CI(\blk00000001/sig0000004e ),
.LI(\blk00000001/sig00000066 ),
.O(\blk00000001/sig0000019c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000a1 (
.I0(\blk00000001/sig00000167 ),
.I1(\blk00000001/sig00000171 ),
.O(\blk00000001/sig00000067 )
);
MUXCY \blk00000001/blk000000a0 (
.CI(\blk00000001/sig0000004f ),
.DI(\blk00000001/sig00000167 ),
.S(\blk00000001/sig00000067 ),
.O(\blk00000001/sig00000050 )
);
XORCY \blk00000001/blk0000009f (
.CI(\blk00000001/sig0000004f ),
.LI(\blk00000001/sig00000067 ),
.O(\blk00000001/sig0000019d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000009e (
.I0(\blk00000001/sig00000168 ),
.I1(\blk00000001/sig00000172 ),
.O(\blk00000001/sig00000068 )
);
MUXCY \blk00000001/blk0000009d (
.CI(\blk00000001/sig00000050 ),
.DI(\blk00000001/sig00000168 ),
.S(\blk00000001/sig00000068 ),
.O(\blk00000001/sig00000051 )
);
XORCY \blk00000001/blk0000009c (
.CI(\blk00000001/sig00000050 ),
.LI(\blk00000001/sig00000068 ),
.O(\blk00000001/sig0000019e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000009b (
.I0(\blk00000001/sig00000169 ),
.I1(\blk00000001/sig00000173 ),
.O(\blk00000001/sig00000069 )
);
MUXCY \blk00000001/blk0000009a (
.CI(\blk00000001/sig00000051 ),
.DI(\blk00000001/sig00000169 ),
.S(\blk00000001/sig00000069 ),
.O(\blk00000001/sig00000052 )
);
XORCY \blk00000001/blk00000099 (
.CI(\blk00000001/sig00000051 ),
.LI(\blk00000001/sig00000069 ),
.O(\blk00000001/sig0000019f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000098 (
.I0(\blk00000001/sig0000016a ),
.I1(\blk00000001/sig00000174 ),
.O(\blk00000001/sig0000006a )
);
MUXCY \blk00000001/blk00000097 (
.CI(\blk00000001/sig00000052 ),
.DI(\blk00000001/sig0000016a ),
.S(\blk00000001/sig0000006a ),
.O(\blk00000001/sig00000053 )
);
XORCY \blk00000001/blk00000096 (
.CI(\blk00000001/sig00000052 ),
.LI(\blk00000001/sig0000006a ),
.O(\blk00000001/sig000001a0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000095 (
.I0(\blk00000001/sig0000016b ),
.I1(\blk00000001/sig00000175 ),
.O(\blk00000001/sig0000006b )
);
MUXCY \blk00000001/blk00000094 (
.CI(\blk00000001/sig00000053 ),
.DI(\blk00000001/sig0000016b ),
.S(\blk00000001/sig0000006b ),
.O(\blk00000001/sig00000054 )
);
XORCY \blk00000001/blk00000093 (
.CI(\blk00000001/sig00000053 ),
.LI(\blk00000001/sig0000006b ),
.O(\blk00000001/sig000001a1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000092 (
.I0(\blk00000001/sig0000016c ),
.I1(\blk00000001/sig00000176 ),
.O(\blk00000001/sig0000006c )
);
MUXCY \blk00000001/blk00000091 (
.CI(\blk00000001/sig00000054 ),
.DI(\blk00000001/sig0000016c ),
.S(\blk00000001/sig0000006c ),
.O(\blk00000001/sig00000055 )
);
XORCY \blk00000001/blk00000090 (
.CI(\blk00000001/sig00000054 ),
.LI(\blk00000001/sig0000006c ),
.O(\blk00000001/sig000001a2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000008f (
.I0(\blk00000001/sig0000016c ),
.I1(\blk00000001/sig00000177 ),
.O(\blk00000001/sig0000006d )
);
MUXCY \blk00000001/blk0000008e (
.CI(\blk00000001/sig00000055 ),
.DI(\blk00000001/sig0000016c ),
.S(\blk00000001/sig0000006d ),
.O(\blk00000001/sig00000056 )
);
XORCY \blk00000001/blk0000008d (
.CI(\blk00000001/sig00000055 ),
.LI(\blk00000001/sig0000006d ),
.O(\blk00000001/sig000001a3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000008c (
.I0(\blk00000001/sig0000016c ),
.I1(\blk00000001/sig00000178 ),
.O(\blk00000001/sig0000006e )
);
MUXCY \blk00000001/blk0000008b (
.CI(\blk00000001/sig00000056 ),
.DI(\blk00000001/sig0000016c ),
.S(\blk00000001/sig0000006e ),
.O(\blk00000001/sig00000057 )
);
XORCY \blk00000001/blk0000008a (
.CI(\blk00000001/sig00000056 ),
.LI(\blk00000001/sig0000006e ),
.O(\blk00000001/sig000001a4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000089 (
.I0(\blk00000001/sig0000016c ),
.I1(\blk00000001/sig0000017a ),
.O(\blk00000001/sig00000070 )
);
MUXCY \blk00000001/blk00000088 (
.CI(\blk00000001/sig00000057 ),
.DI(\blk00000001/sig0000016c ),
.S(\blk00000001/sig00000070 ),
.O(\blk00000001/sig00000059 )
);
XORCY \blk00000001/blk00000087 (
.CI(\blk00000001/sig00000057 ),
.LI(\blk00000001/sig00000070 ),
.O(\blk00000001/sig000001a6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000086 (
.I0(\blk00000001/sig0000016c ),
.I1(\blk00000001/sig0000017b ),
.O(\blk00000001/sig00000071 )
);
MUXCY \blk00000001/blk00000085 (
.CI(\blk00000001/sig00000059 ),
.DI(\blk00000001/sig0000016c ),
.S(\blk00000001/sig00000071 ),
.O(\blk00000001/sig0000005a )
);
XORCY \blk00000001/blk00000084 (
.CI(\blk00000001/sig00000059 ),
.LI(\blk00000001/sig00000071 ),
.O(\blk00000001/sig000001a7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000083 (
.I0(\blk00000001/sig0000016c ),
.I1(\blk00000001/sig0000017c ),
.O(\blk00000001/sig00000072 )
);
MUXCY \blk00000001/blk00000082 (
.CI(\blk00000001/sig0000005a ),
.DI(\blk00000001/sig0000016c ),
.S(\blk00000001/sig00000072 ),
.O(\blk00000001/sig0000005b )
);
XORCY \blk00000001/blk00000081 (
.CI(\blk00000001/sig0000005a ),
.LI(\blk00000001/sig00000072 ),
.O(\blk00000001/sig000001a8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000080 (
.I0(\blk00000001/sig0000016c ),
.I1(\blk00000001/sig0000017d ),
.O(\blk00000001/sig00000073 )
);
XORCY \blk00000001/blk0000007f (
.CI(\blk00000001/sig0000005b ),
.LI(\blk00000001/sig00000073 ),
.O(\blk00000001/sig000001a9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000007e (
.I0(\blk00000001/sig000001b2 ),
.I1(\blk00000001/sig000000e9 ),
.O(\blk00000001/sig000000b7 )
);
MUXCY \blk00000001/blk0000007d (
.CI(\blk00000001/sig0000004b ),
.DI(\blk00000001/sig000001b2 ),
.S(\blk00000001/sig000000b7 ),
.O(\blk00000001/sig00000097 )
);
XORCY \blk00000001/blk0000007c (
.CI(\blk00000001/sig0000004b ),
.LI(\blk00000001/sig000000b7 ),
.O(\blk00000001/sig000001e6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000007b (
.I0(\blk00000001/sig000001b3 ),
.I1(\blk00000001/sig000000ea ),
.O(\blk00000001/sig000000c2 )
);
MUXCY \blk00000001/blk0000007a (
.CI(\blk00000001/sig00000097 ),
.DI(\blk00000001/sig000001b3 ),
.S(\blk00000001/sig000000c2 ),
.O(\blk00000001/sig000000a2 )
);
XORCY \blk00000001/blk00000079 (
.CI(\blk00000001/sig00000097 ),
.LI(\blk00000001/sig000000c2 ),
.O(\blk00000001/sig000001f1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000078 (
.I0(\blk00000001/sig000001be ),
.I1(\blk00000001/sig000000f2 ),
.O(\blk00000001/sig000000cd )
);
MUXCY \blk00000001/blk00000077 (
.CI(\blk00000001/sig000000a2 ),
.DI(\blk00000001/sig000001be ),
.S(\blk00000001/sig000000cd ),
.O(\blk00000001/sig000000ad )
);
XORCY \blk00000001/blk00000076 (
.CI(\blk00000001/sig000000a2 ),
.LI(\blk00000001/sig000000cd ),
.O(\blk00000001/sig000001fc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000075 (
.I0(\blk00000001/sig000001c3 ),
.I1(\blk00000001/sig000000f3 ),
.O(\blk00000001/sig000000d1 )
);
MUXCY \blk00000001/blk00000074 (
.CI(\blk00000001/sig000000ad ),
.DI(\blk00000001/sig000001c3 ),
.S(\blk00000001/sig000000d1 ),
.O(\blk00000001/sig000000b0 )
);
XORCY \blk00000001/blk00000073 (
.CI(\blk00000001/sig000000ad ),
.LI(\blk00000001/sig000000d1 ),
.O(\blk00000001/sig000001fd )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000072 (
.I0(\blk00000001/sig000001c4 ),
.I1(\blk00000001/sig000000f4 ),
.O(\blk00000001/sig000000d2 )
);
MUXCY \blk00000001/blk00000071 (
.CI(\blk00000001/sig000000b0 ),
.DI(\blk00000001/sig000001c4 ),
.S(\blk00000001/sig000000d2 ),
.O(\blk00000001/sig000000b1 )
);
XORCY \blk00000001/blk00000070 (
.CI(\blk00000001/sig000000b0 ),
.LI(\blk00000001/sig000000d2 ),
.O(\blk00000001/sig000001fe )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000006f (
.I0(\blk00000001/sig000001c5 ),
.I1(\blk00000001/sig000000f5 ),
.O(\blk00000001/sig000000d3 )
);
MUXCY \blk00000001/blk0000006e (
.CI(\blk00000001/sig000000b1 ),
.DI(\blk00000001/sig000001c5 ),
.S(\blk00000001/sig000000d3 ),
.O(\blk00000001/sig000000b2 )
);
XORCY \blk00000001/blk0000006d (
.CI(\blk00000001/sig000000b1 ),
.LI(\blk00000001/sig000000d3 ),
.O(\blk00000001/sig00000200 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000006c (
.I0(\blk00000001/sig000001c6 ),
.I1(\blk00000001/sig000000f6 ),
.O(\blk00000001/sig000000d4 )
);
MUXCY \blk00000001/blk0000006b (
.CI(\blk00000001/sig000000b2 ),
.DI(\blk00000001/sig000001c6 ),
.S(\blk00000001/sig000000d4 ),
.O(\blk00000001/sig000000b3 )
);
XORCY \blk00000001/blk0000006a (
.CI(\blk00000001/sig000000b2 ),
.LI(\blk00000001/sig000000d4 ),
.O(\blk00000001/sig00000201 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000069 (
.I0(\blk00000001/sig000001c7 ),
.I1(\blk00000001/sig000000f7 ),
.O(\blk00000001/sig000000d5 )
);
MUXCY \blk00000001/blk00000068 (
.CI(\blk00000001/sig000000b3 ),
.DI(\blk00000001/sig000001c7 ),
.S(\blk00000001/sig000000d5 ),
.O(\blk00000001/sig000000b4 )
);
XORCY \blk00000001/blk00000067 (
.CI(\blk00000001/sig000000b3 ),
.LI(\blk00000001/sig000000d5 ),
.O(\blk00000001/sig00000202 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000066 (
.I0(\blk00000001/sig000001c8 ),
.I1(\blk00000001/sig000000f8 ),
.O(\blk00000001/sig000000d6 )
);
MUXCY \blk00000001/blk00000065 (
.CI(\blk00000001/sig000000b4 ),
.DI(\blk00000001/sig000001c8 ),
.S(\blk00000001/sig000000d6 ),
.O(\blk00000001/sig000000b5 )
);
XORCY \blk00000001/blk00000064 (
.CI(\blk00000001/sig000000b4 ),
.LI(\blk00000001/sig000000d6 ),
.O(\blk00000001/sig00000203 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000063 (
.I0(\blk00000001/sig000001c9 ),
.I1(\blk00000001/sig000000f9 ),
.O(\blk00000001/sig000000d7 )
);
MUXCY \blk00000001/blk00000062 (
.CI(\blk00000001/sig000000b5 ),
.DI(\blk00000001/sig000001c9 ),
.S(\blk00000001/sig000000d7 ),
.O(\blk00000001/sig000000b6 )
);
XORCY \blk00000001/blk00000061 (
.CI(\blk00000001/sig000000b5 ),
.LI(\blk00000001/sig000000d7 ),
.O(\blk00000001/sig00000204 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000060 (
.I0(\blk00000001/sig000001b4 ),
.I1(\blk00000001/sig000000eb ),
.O(\blk00000001/sig000000b8 )
);
MUXCY \blk00000001/blk0000005f (
.CI(\blk00000001/sig000000b6 ),
.DI(\blk00000001/sig000001b4 ),
.S(\blk00000001/sig000000b8 ),
.O(\blk00000001/sig00000098 )
);
XORCY \blk00000001/blk0000005e (
.CI(\blk00000001/sig000000b6 ),
.LI(\blk00000001/sig000000b8 ),
.O(\blk00000001/sig000001e7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000005d (
.I0(\blk00000001/sig000001b5 ),
.I1(\blk00000001/sig000000ec ),
.O(\blk00000001/sig000000b9 )
);
MUXCY \blk00000001/blk0000005c (
.CI(\blk00000001/sig00000098 ),
.DI(\blk00000001/sig000001b5 ),
.S(\blk00000001/sig000000b9 ),
.O(\blk00000001/sig00000099 )
);
XORCY \blk00000001/blk0000005b (
.CI(\blk00000001/sig00000098 ),
.LI(\blk00000001/sig000000b9 ),
.O(\blk00000001/sig000001e8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000005a (
.I0(\blk00000001/sig000001b6 ),
.I1(\blk00000001/sig000000ed ),
.O(\blk00000001/sig000000ba )
);
MUXCY \blk00000001/blk00000059 (
.CI(\blk00000001/sig00000099 ),
.DI(\blk00000001/sig000001b6 ),
.S(\blk00000001/sig000000ba ),
.O(\blk00000001/sig0000009a )
);
XORCY \blk00000001/blk00000058 (
.CI(\blk00000001/sig00000099 ),
.LI(\blk00000001/sig000000ba ),
.O(\blk00000001/sig000001e9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000057 (
.I0(\blk00000001/sig000001b7 ),
.I1(\blk00000001/sig000000ee ),
.O(\blk00000001/sig000000bb )
);
MUXCY \blk00000001/blk00000056 (
.CI(\blk00000001/sig0000009a ),
.DI(\blk00000001/sig000001b7 ),
.S(\blk00000001/sig000000bb ),
.O(\blk00000001/sig0000009b )
);
XORCY \blk00000001/blk00000055 (
.CI(\blk00000001/sig0000009a ),
.LI(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000001ea )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000054 (
.I0(\blk00000001/sig000001b8 ),
.I1(\blk00000001/sig000000ef ),
.O(\blk00000001/sig000000bc )
);
MUXCY \blk00000001/blk00000053 (
.CI(\blk00000001/sig0000009b ),
.DI(\blk00000001/sig000001b8 ),
.S(\blk00000001/sig000000bc ),
.O(\blk00000001/sig0000009c )
);
XORCY \blk00000001/blk00000052 (
.CI(\blk00000001/sig0000009b ),
.LI(\blk00000001/sig000000bc ),
.O(\blk00000001/sig000001eb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000051 (
.I0(\blk00000001/sig000001b9 ),
.I1(\blk00000001/sig000000f0 ),
.O(\blk00000001/sig000000bd )
);
MUXCY \blk00000001/blk00000050 (
.CI(\blk00000001/sig0000009c ),
.DI(\blk00000001/sig000001b9 ),
.S(\blk00000001/sig000000bd ),
.O(\blk00000001/sig0000009d )
);
XORCY \blk00000001/blk0000004f (
.CI(\blk00000001/sig0000009c ),
.LI(\blk00000001/sig000000bd ),
.O(\blk00000001/sig000001ec )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000004e (
.I0(\blk00000001/sig000001ba ),
.I1(\blk00000001/sig000000f1 ),
.O(\blk00000001/sig000000be )
);
MUXCY \blk00000001/blk0000004d (
.CI(\blk00000001/sig0000009d ),
.DI(\blk00000001/sig000001ba ),
.S(\blk00000001/sig000000be ),
.O(\blk00000001/sig0000009e )
);
XORCY \blk00000001/blk0000004c (
.CI(\blk00000001/sig0000009d ),
.LI(\blk00000001/sig000000be ),
.O(\blk00000001/sig000001ed )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000004b (
.I0(\blk00000001/sig000001bb ),
.I1(\blk00000001/sig000001d8 ),
.O(\blk00000001/sig000000bf )
);
MUXCY \blk00000001/blk0000004a (
.CI(\blk00000001/sig0000009e ),
.DI(\blk00000001/sig000001bb ),
.S(\blk00000001/sig000000bf ),
.O(\blk00000001/sig0000009f )
);
XORCY \blk00000001/blk00000049 (
.CI(\blk00000001/sig0000009e ),
.LI(\blk00000001/sig000000bf ),
.O(\blk00000001/sig000001ee )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000048 (
.I0(\blk00000001/sig000001bc ),
.I1(\blk00000001/sig000001d9 ),
.O(\blk00000001/sig000000c0 )
);
MUXCY \blk00000001/blk00000047 (
.CI(\blk00000001/sig0000009f ),
.DI(\blk00000001/sig000001bc ),
.S(\blk00000001/sig000000c0 ),
.O(\blk00000001/sig000000a0 )
);
XORCY \blk00000001/blk00000046 (
.CI(\blk00000001/sig0000009f ),
.LI(\blk00000001/sig000000c0 ),
.O(\blk00000001/sig000001ef )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000045 (
.I0(\blk00000001/sig000001bd ),
.I1(\blk00000001/sig000001de ),
.O(\blk00000001/sig000000c1 )
);
MUXCY \blk00000001/blk00000044 (
.CI(\blk00000001/sig000000a0 ),
.DI(\blk00000001/sig000001bd ),
.S(\blk00000001/sig000000c1 ),
.O(\blk00000001/sig000000a1 )
);
XORCY \blk00000001/blk00000043 (
.CI(\blk00000001/sig000000a0 ),
.LI(\blk00000001/sig000000c1 ),
.O(\blk00000001/sig000001f0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000042 (
.I0(\blk00000001/sig000001bf ),
.I1(\blk00000001/sig000001df ),
.O(\blk00000001/sig000000c3 )
);
MUXCY \blk00000001/blk00000041 (
.CI(\blk00000001/sig000000a1 ),
.DI(\blk00000001/sig000001bf ),
.S(\blk00000001/sig000000c3 ),
.O(\blk00000001/sig000000a3 )
);
XORCY \blk00000001/blk00000040 (
.CI(\blk00000001/sig000000a1 ),
.LI(\blk00000001/sig000000c3 ),
.O(\blk00000001/sig000001f2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003f (
.I0(\blk00000001/sig000001c0 ),
.I1(\blk00000001/sig000001e0 ),
.O(\blk00000001/sig000000c4 )
);
MUXCY \blk00000001/blk0000003e (
.CI(\blk00000001/sig000000a3 ),
.DI(\blk00000001/sig000001c0 ),
.S(\blk00000001/sig000000c4 ),
.O(\blk00000001/sig000000a4 )
);
XORCY \blk00000001/blk0000003d (
.CI(\blk00000001/sig000000a3 ),
.LI(\blk00000001/sig000000c4 ),
.O(\blk00000001/sig000001f3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003c (
.I0(\blk00000001/sig000001c1 ),
.I1(\blk00000001/sig000001e1 ),
.O(\blk00000001/sig000000c5 )
);
MUXCY \blk00000001/blk0000003b (
.CI(\blk00000001/sig000000a4 ),
.DI(\blk00000001/sig000001c1 ),
.S(\blk00000001/sig000000c5 ),
.O(\blk00000001/sig000000a5 )
);
XORCY \blk00000001/blk0000003a (
.CI(\blk00000001/sig000000a4 ),
.LI(\blk00000001/sig000000c5 ),
.O(\blk00000001/sig000001f4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000039 (
.I0(\blk00000001/sig000001e2 ),
.I1(\blk00000001/sig000001c2 ),
.O(\blk00000001/sig000000c6 )
);
MUXCY \blk00000001/blk00000038 (
.CI(\blk00000001/sig000000a5 ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig000000c6 ),
.O(\blk00000001/sig000000a6 )
);
XORCY \blk00000001/blk00000037 (
.CI(\blk00000001/sig000000a5 ),
.LI(\blk00000001/sig000000c6 ),
.O(\blk00000001/sig000001f5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000036 (
.I0(\blk00000001/sig000001c2 ),
.I1(\blk00000001/sig000001e3 ),
.O(\blk00000001/sig000000c7 )
);
MUXCY \blk00000001/blk00000035 (
.CI(\blk00000001/sig000000a6 ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig000000c7 ),
.O(\blk00000001/sig000000a7 )
);
XORCY \blk00000001/blk00000034 (
.CI(\blk00000001/sig000000a6 ),
.LI(\blk00000001/sig000000c7 ),
.O(\blk00000001/sig000001f6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000033 (
.I0(\blk00000001/sig000001c2 ),
.I1(\blk00000001/sig000001e4 ),
.O(\blk00000001/sig000000c8 )
);
MUXCY \blk00000001/blk00000032 (
.CI(\blk00000001/sig000000a7 ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig000000c8 ),
.O(\blk00000001/sig000000a8 )
);
XORCY \blk00000001/blk00000031 (
.CI(\blk00000001/sig000000a7 ),
.LI(\blk00000001/sig000000c8 ),
.O(\blk00000001/sig000001f7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000030 (
.I0(\blk00000001/sig000001c2 ),
.I1(\blk00000001/sig000001e5 ),
.O(\blk00000001/sig000000c9 )
);
MUXCY \blk00000001/blk0000002f (
.CI(\blk00000001/sig000000a8 ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig000000c9 ),
.O(\blk00000001/sig000000a9 )
);
XORCY \blk00000001/blk0000002e (
.CI(\blk00000001/sig000000a8 ),
.LI(\blk00000001/sig000000c9 ),
.O(\blk00000001/sig000001f8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000002d (
.I0(\blk00000001/sig000001c2 ),
.I1(\blk00000001/sig000001da ),
.O(\blk00000001/sig000000ca )
);
MUXCY \blk00000001/blk0000002c (
.CI(\blk00000001/sig000000a9 ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig000000ca ),
.O(\blk00000001/sig000000aa )
);
XORCY \blk00000001/blk0000002b (
.CI(\blk00000001/sig000000a9 ),
.LI(\blk00000001/sig000000ca ),
.O(\blk00000001/sig000001f9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000002a (
.I0(\blk00000001/sig000001c2 ),
.I1(\blk00000001/sig000001db ),
.O(\blk00000001/sig000000cb )
);
MUXCY \blk00000001/blk00000029 (
.CI(\blk00000001/sig000000aa ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig000000cb ),
.O(\blk00000001/sig000000ab )
);
XORCY \blk00000001/blk00000028 (
.CI(\blk00000001/sig000000aa ),
.LI(\blk00000001/sig000000cb ),
.O(\blk00000001/sig000001fa )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000027 (
.I0(\blk00000001/sig000001c2 ),
.I1(\blk00000001/sig000001dc ),
.O(\blk00000001/sig000000cc )
);
MUXCY \blk00000001/blk00000026 (
.CI(\blk00000001/sig000000ab ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig000000cc ),
.O(\blk00000001/sig000000ac )
);
XORCY \blk00000001/blk00000025 (
.CI(\blk00000001/sig000000ab ),
.LI(\blk00000001/sig000000cc ),
.O(\blk00000001/sig000001fb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000024 (
.I0(\blk00000001/sig000001c2 ),
.I1(\blk00000001/sig000001dd ),
.O(\blk00000001/sig000000ce )
);
MUXCY \blk00000001/blk00000023 (
.CI(\blk00000001/sig000000ac ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig000000ce ),
.O(\blk00000001/sig000000ae )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000022 (
.I0(\blk00000001/sig000001c2 ),
.I1(\blk00000001/sig000001dd ),
.O(\blk00000001/sig000000cf )
);
MUXCY \blk00000001/blk00000021 (
.CI(\blk00000001/sig000000ae ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig000000cf ),
.O(\blk00000001/sig000000af )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000020 (
.I0(\blk00000001/sig000001c2 ),
.I1(\blk00000001/sig000001dd ),
.O(\blk00000001/sig000000d0 )
);
XORCY \blk00000001/blk0000001f (
.CI(\blk00000001/sig000000af ),
.LI(\blk00000001/sig000000d0 ),
.O(\blk00000001/sig000001ff )
);
MULT18X18S \blk00000001/blk0000001e (
.C(clk),
.CE(\blk00000001/sig0000004c ),
.R(\blk00000001/sig0000004b ),
.A({\blk00000001/sig0000004b , a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
.B({\blk00000001/sig0000004b , b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
.P({\NLW_blk00000001/blk0000001e_P<35>_UNCONNECTED , \blk00000001/sig00000115 , \blk00000001/sig00000114 , \blk00000001/sig00000113 ,
\blk00000001/sig00000112 , \blk00000001/sig00000111 , \blk00000001/sig0000010f , \blk00000001/sig0000010e , \blk00000001/sig0000010d ,
\blk00000001/sig0000010c , \blk00000001/sig0000010b , \blk00000001/sig0000010a , \blk00000001/sig00000109 , \blk00000001/sig00000108 ,
\blk00000001/sig00000107 , \blk00000001/sig00000106 , \blk00000001/sig00000104 , \blk00000001/sig00000103 , \blk00000001/sig00000102 ,
\blk00000001/sig00000101 , \blk00000001/sig00000100 , \blk00000001/sig000000ff , \blk00000001/sig000000fe , \blk00000001/sig000000fd ,
\blk00000001/sig000000fc , \blk00000001/sig000000fb , \blk00000001/sig0000011c , \blk00000001/sig0000011b , \blk00000001/sig0000011a ,
\blk00000001/sig00000119 , \blk00000001/sig00000118 , \blk00000001/sig00000117 , \blk00000001/sig00000116 , \blk00000001/sig00000110 ,
\blk00000001/sig00000105 , \blk00000001/sig000000fa })
);
MULT18X18S \blk00000001/blk0000001d (
.C(clk),
.CE(\blk00000001/sig0000004c ),
.R(\blk00000001/sig0000004b ),
.A({\blk00000001/sig0000004b , a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
.B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}),
.P({\NLW_blk00000001/blk0000001d_P<35>_UNCONNECTED , \NLW_blk00000001/blk0000001d_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000001d_P<33>_UNCONNECTED , \NLW_blk00000001/blk0000001d_P<32>_UNCONNECTED , \NLW_blk00000001/blk0000001d_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk0000001d_P<30>_UNCONNECTED , \NLW_blk00000001/blk0000001d_P<29>_UNCONNECTED , \NLW_blk00000001/blk0000001d_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000001d_P<27>_UNCONNECTED , \NLW_blk00000001/blk0000001d_P<26>_UNCONNECTED , \NLW_blk00000001/blk0000001d_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk0000001d_P<24>_UNCONNECTED , \blk00000001/sig0000012c , \blk00000001/sig0000012b , \blk00000001/sig0000012a ,
\blk00000001/sig00000129 , \blk00000001/sig00000127 , \blk00000001/sig00000126 , \blk00000001/sig00000125 , \blk00000001/sig00000124 ,
\blk00000001/sig00000123 , \blk00000001/sig00000122 , \blk00000001/sig00000121 , \blk00000001/sig00000120 , \blk00000001/sig0000011f ,
\blk00000001/sig0000011e , \blk00000001/sig00000134 , \blk00000001/sig00000133 , \blk00000001/sig00000132 , \blk00000001/sig00000131 ,
\blk00000001/sig00000130 , \blk00000001/sig0000012f , \blk00000001/sig0000012e , \blk00000001/sig0000012d , \blk00000001/sig00000128 ,
\blk00000001/sig0000011d })
);
MULT18X18S \blk00000001/blk0000001c (
.C(clk),
.CE(\blk00000001/sig0000004c ),
.R(\blk00000001/sig0000004b ),
.A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}),
.B({\blk00000001/sig0000004b , b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
.P({\NLW_blk00000001/blk0000001c_P<35>_UNCONNECTED , \NLW_blk00000001/blk0000001c_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000001c_P<33>_UNCONNECTED , \NLW_blk00000001/blk0000001c_P<32>_UNCONNECTED , \NLW_blk00000001/blk0000001c_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk0000001c_P<30>_UNCONNECTED , \NLW_blk00000001/blk0000001c_P<29>_UNCONNECTED , \NLW_blk00000001/blk0000001c_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000001c_P<27>_UNCONNECTED , \NLW_blk00000001/blk0000001c_P<26>_UNCONNECTED , \NLW_blk00000001/blk0000001c_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk0000001c_P<24>_UNCONNECTED , \blk00000001/sig00000144 , \blk00000001/sig00000143 , \blk00000001/sig00000142 ,
\blk00000001/sig00000141 , \blk00000001/sig0000013f , \blk00000001/sig0000013e , \blk00000001/sig0000013d , \blk00000001/sig0000013c ,
\blk00000001/sig0000013b , \blk00000001/sig0000013a , \blk00000001/sig00000139 , \blk00000001/sig00000138 , \blk00000001/sig00000137 ,
\blk00000001/sig00000136 , \blk00000001/sig0000014c , \blk00000001/sig0000014b , \blk00000001/sig0000014a , \blk00000001/sig00000149 ,
\blk00000001/sig00000148 , \blk00000001/sig00000147 , \blk00000001/sig00000146 , \blk00000001/sig00000145 , \blk00000001/sig00000140 ,
\blk00000001/sig00000135 })
);
MULT18X18S \blk00000001/blk0000001b (
.C(clk),
.CE(\blk00000001/sig0000004c ),
.R(\blk00000001/sig0000004b ),
.A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}),
.B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}),
.P({\NLW_blk00000001/blk0000001b_P<35>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000001b_P<33>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<32>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk0000001b_P<30>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<29>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000001b_P<27>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<26>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk0000001b_P<24>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<23>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000001b_P<21>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<20>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<19>_UNCONNECTED ,
\NLW_blk00000001/blk0000001b_P<18>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<17>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000001b_P<15>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<14>_UNCONNECTED , \blk00000001/sig00000151 , \blk00000001/sig00000150
, \blk00000001/sig0000014f , \blk00000001/sig0000014e , \blk00000001/sig0000015a , \blk00000001/sig00000159 , \blk00000001/sig00000158 ,
\blk00000001/sig00000157 , \blk00000001/sig00000156 , \blk00000001/sig00000155 , \blk00000001/sig00000154 , \blk00000001/sig00000153 ,
\blk00000001/sig00000152 , \blk00000001/sig0000014d })
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001a (
.C(clk),
.D(\blk00000001/sig00000219 ),
.Q(p[47])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000019 (
.C(clk),
.D(\blk00000001/sig00000218 ),
.Q(p[46])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000018 (
.C(clk),
.D(\blk00000001/sig00000217 ),
.Q(p[45])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000017 (
.C(clk),
.D(\blk00000001/sig00000216 ),
.Q(p[44])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000016 (
.C(clk),
.D(\blk00000001/sig00000215 ),
.Q(p[43])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000015 (
.C(clk),
.D(\blk00000001/sig00000214 ),
.Q(p[42])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000014 (
.C(clk),
.D(\blk00000001/sig00000213 ),
.Q(p[41])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000013 (
.C(clk),
.D(\blk00000001/sig00000212 ),
.Q(p[40])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000012 (
.C(clk),
.D(\blk00000001/sig00000211 ),
.Q(p[39])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000011 (
.C(clk),
.D(\blk00000001/sig00000210 ),
.Q(p[38])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000010 (
.C(clk),
.D(\blk00000001/sig0000020f ),
.Q(p[37])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000f (
.C(clk),
.D(\blk00000001/sig0000020e ),
.Q(p[36])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000e (
.C(clk),
.D(\blk00000001/sig0000020d ),
.Q(p[35])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000d (
.C(clk),
.D(\blk00000001/sig0000020c ),
.Q(p[34])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000c (
.C(clk),
.D(\blk00000001/sig0000020b ),
.Q(p[33])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000b (
.C(clk),
.D(\blk00000001/sig0000020a ),
.Q(p[32])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000a (
.C(clk),
.D(\blk00000001/sig00000209 ),
.Q(p[31])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000009 (
.C(clk),
.D(\blk00000001/sig00000208 ),
.Q(p[30])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000008 (
.C(clk),
.D(\blk00000001/sig00000207 ),
.Q(p[29])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000007 (
.C(clk),
.D(\blk00000001/sig00000206 ),
.Q(p[28])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000006 (
.C(clk),
.D(\blk00000001/sig00000205 ),
.Q(p[27])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000005 (
.C(clk),
.D(\blk00000001/sig0000021b ),
.Q(p[26])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000004 (
.C(clk),
.D(\blk00000001/sig0000021a ),
.Q(p[25])
);
VCC \blk00000001/blk00000003 (
.P(\blk00000001/sig0000004c )
);
GND \blk00000001/blk00000002 (
.G(\blk00000001/sig0000004b )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTP_4_V
`define SKY130_FD_SC_HS__DLRTP_4_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlrtp_4 (
RESET_B,
D ,
GATE ,
Q ,
VPWR ,
VGND
);
input RESET_B;
input D ;
input GATE ;
output Q ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dlrtp base (
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.Q(Q),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlrtp_4 (
RESET_B,
D ,
GATE ,
Q
);
input RESET_B;
input D ;
input GATE ;
output Q ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlrtp base (
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.Q(Q)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTP_4_V
|
//
// Paul Gao 02/2021
//
// This is an output SDR PHY
//
// clk_o is center-aligned to data_o and is inverted from clk_i
// Waveform below shows the detailed behavior of the module
//
// WARNING:
// Source of clk_o is combinational logic instead of a register
// Duty-cycle of clk_o may not be ideal under certain cirtumstances
// Using negedge of clk_o may result in timing violation
//
/****************************************************************************
+---+ +---+ +---+ +---+ +---+ +---+ +---+ +---+
clk_i | | | | | | | | | | | | | | |
+---+ +---+ +---+ +---+ +---+ +---+ +---+ +---+
-----------------+-------+-------+-------+-------+-------+-------
data_i D00 | D01 | D02 | D03 | D04 | D05 | D06
-----------------------------------------------------------------
+---+ +---+ +---+ +---+ +---+ +---+ +--+
clk_o | | | | | | | | | | | | |
+------------+ +---+ +---+ +---+ +---+ +---+ +---+
-----------------------------------------------------------------
data_o D00 | D01 | D02 | D03 | D04 | D05
-------------------------+-------+-------+-------+-------+-------
****************************************************************************/
module bsg_link_osdr_phy
#(parameter `BSG_INV_PARAM(width_p )
,parameter strength_p = 0)
(input clk_i
,input reset_i
,input [width_p-1:0] data_i
,output clk_o
,output [width_p-1:0] data_o
);
bsg_link_osdr_phy_phase_align clk_pa
(.clk_i (clk_i)
,.reset_i(reset_i)
,.clk_o (clk_o)
);
bsg_dff #(.width_p(width_p)) data_ff
(.clk_i(clk_i),.data_i(data_i),.data_o(data_o));
endmodule
`BSG_ABSTRACT_MODULE(bsg_link_osdr_phy)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINV_1_V
`define SKY130_FD_SC_HD__CLKINV_1_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkinv_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkinv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINV_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_4_V
`define SKY130_FD_SC_LP__DFXTP_4_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog wrapper for dfxtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfxtp_4 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfxtp_4 (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_4_V
|
/*
* Copyright (c) 2008 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
`include "defines.v"
module cpu (
`ifdef DEBUG
output [15:0] cs,
output [15:0] ip,
output [ 2:0] state,
output [ 2:0] next_state,
output [ 5:0] iralu,
output [15:0] x,
output [15:0] y,
output [15:0] imm,
output [15:0] aluo,
output [15:0] ax,
output [15:0] dx,
output [15:0] bp,
output [15:0] si,
output [15:0] es,
input dbg_block,
output [15:0] c,
output [ 3:0] addr_c,
output [15:0] cpu_dat_o,
output [15:0] d,
output [ 3:0] addr_d,
output byte_exec,
output [ 8:0] flags,
output end_seq,
output ext_int,
output cpu_block,
`endif
// Wishbone master interface
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
output [19:1] wb_adr_o,
output wb_we_o,
output wb_tga_o, // io/mem
output [ 1:0] wb_sel_o,
output wb_stb_o,
output wb_cyc_o,
input wb_ack_i,
input wb_tgc_i, // intr
output wb_tgc_o // inta
);
// Net declarations
`ifndef DEBUG
wire [15:0] cs, ip;
wire [15:0] imm;
wire [15:0] cpu_dat_o;
wire byte_exec;
wire cpu_block;
`endif
wire [`IR_SIZE-1:0] ir;
wire [15:0] off;
wire [19:0] addr_exec, addr_fetch;
wire byte_fetch, fetch_or_exec;
wire of, zf, cx_zero;
wire div_exc;
wire wr_ip0;
wire ifl;
wire cpu_byte_o;
wire cpu_m_io;
wire [19:0] cpu_adr_o;
wire wb_block;
wire [15:0] cpu_dat_i;
wire cpu_we_o;
wire [15:0] iid_dat_i;
// Module instantiations
fetch fetch0 (
`ifdef DEBUG
.state (state),
.next_state (next_state),
.ext_int (ext_int),
.end_seq (end_seq),
`endif
.clk (wb_clk_i),
.rst (wb_rst_i),
.cs (cs),
.ip (ip),
.of (of),
.zf (zf),
.data (cpu_dat_i),
.ir (ir),
.off (off),
.imm (imm),
.pc (addr_fetch),
.cx_zero (cx_zero),
.bytefetch (byte_fetch),
.fetch_or_exec (fetch_or_exec),
.block (cpu_block),
.div_exc (div_exc),
.wr_ip0 (wr_ip0),
.intr (wb_tgc_i),
.ifl (ifl),
.inta (wb_tgc_o)
);
exec exec0 (
`ifdef DEBUG
.x (x),
.y (y),
.aluo (aluo),
.ax (ax),
.dx (dx),
.bp (bp),
.si (si),
.es (es),
.c (c),
.addr_c (addr_c),
.omemalu (d),
.addr_d (addr_d),
.flags (flags),
`endif
.ir (ir),
.off (off),
.imm (imm),
.cs (cs),
.ip (ip),
.of (of),
.zf (zf),
.cx_zero (cx_zero),
.clk (wb_clk_i),
.rst (wb_rst_i),
.memout (iid_dat_i),
.wr_data (cpu_dat_o),
.addr (addr_exec),
.we (cpu_we_o),
.m_io (cpu_m_io),
.byteop (byte_exec),
.block (cpu_block),
.div_exc (div_exc),
.wrip0 (wr_ip0),
.ifl (ifl)
);
wb_master wm0 (
.cpu_byte_o (cpu_byte_o),
.cpu_memop (ir[`MEM_OP]),
.cpu_m_io (cpu_m_io),
.cpu_adr_o (cpu_adr_o),
.cpu_block (wb_block),
.cpu_dat_i (cpu_dat_i),
.cpu_dat_o (cpu_dat_o),
.cpu_we_o (cpu_we_o),
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (wb_dat_o),
.wb_adr_o (wb_adr_o),
.wb_we_o (wb_we_o),
.wb_tga_o (wb_tga_o),
.wb_sel_o (wb_sel_o),
.wb_stb_o (wb_stb_o),
.wb_cyc_o (wb_cyc_o),
.wb_ack_i (wb_ack_i)
);
// Assignments
assign cpu_adr_o = fetch_or_exec ? addr_exec : addr_fetch;
assign cpu_byte_o = fetch_or_exec ? byte_exec : byte_fetch;
assign iid_dat_i = wb_tgc_o ? wb_dat_i : cpu_dat_i;
`ifdef DEBUG
assign iralu = ir[28:23];
assign cpu_block = wb_block | dbg_block;
`else
assign cpu_block = wb_block;
`endif
endmodule
module wb_master (
input cpu_byte_o,
input cpu_memop,
input cpu_m_io,
input [19:0] cpu_adr_o,
output reg cpu_block,
output reg [15:0] cpu_dat_i,
input [15:0] cpu_dat_o,
input cpu_we_o,
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
output reg [19:1] wb_adr_o,
output wb_we_o,
output wb_tga_o,
output reg [ 1:0] wb_sel_o,
output reg wb_stb_o,
output reg wb_cyc_o,
input wb_ack_i
);
// Register and nets declarations
reg [ 1:0] cs; // current state
wire op; // in an operation
wire odd_word; // unaligned word
wire a0; // address 0 pin
wire [15:0] blw; // low byte (sign extended)
wire [15:0] bhw; // high byte (sign extended)
wire [19:1] adr1; // next address (for unaligned acc)
wire [ 1:0] sel_o; // bus byte select
// Declare the symbolic names for states
parameter [1:0]
cyc0_lo = 3'd0,
stb1_hi = 3'd1,
stb1_lo = 3'd2,
stb2_hi = 3'd3;
// Assignments
assign op = (cpu_memop | cpu_m_io);
assign odd_word = (cpu_adr_o[0] & !cpu_byte_o);
assign a0 = cpu_adr_o[0];
assign blw = { {8{wb_dat_i[7]}}, wb_dat_i[7:0] };
assign bhw = { {8{wb_dat_i[15]}}, wb_dat_i[15:8] };
assign adr1 = a0 ? (cpu_adr_o[19:1] + 1'b1)
: cpu_adr_o[19:1];
assign wb_dat_o = a0 ? { cpu_dat_o[7:0], cpu_dat_o[15:8] }
: cpu_dat_o;
assign wb_we_o = cpu_we_o;
assign wb_tga_o = cpu_m_io;
assign sel_o = a0 ? 2'b10 : (cpu_byte_o ? 2'b01 : 2'b11);
// Behaviour
// cpu_dat_i
always @(posedge wb_clk_i)
cpu_dat_i <= (cs == cyc0_lo) ?
(wb_ack_i ?
(a0 ? bhw : (cpu_byte_o ? blw : wb_dat_i))
: cpu_dat_i)
: ((cs == stb1_lo && wb_ack_i) ?
{ wb_dat_i[7:0], cpu_dat_i[7:0] }
: cpu_dat_i);
// outputs setup
always @(*)
case (cs)
default:
begin
cpu_block <= op;
wb_adr_o <= cpu_adr_o[19:1];
wb_sel_o <= sel_o;
wb_stb_o <= op;
wb_cyc_o <= op;
end
stb1_hi:
begin
cpu_block <= odd_word | wb_ack_i;
wb_adr_o <= cpu_adr_o[19:1];
wb_sel_o <= sel_o;
wb_stb_o <= 1'b0;
wb_cyc_o <= odd_word;
end
stb1_lo:
begin
cpu_block <= 1'b1;
wb_adr_o <= adr1;
wb_sel_o <= 2'b01;
wb_stb_o <= 1'b1;
wb_cyc_o <= 1'b1;
end
stb2_hi:
begin
cpu_block <= wb_ack_i;
wb_adr_o <= adr1;
wb_sel_o <= 2'b01;
wb_stb_o <= 1'b0;
wb_cyc_o <= 1'b0;
end
endcase
// state machine
always @(posedge wb_clk_i)
if (wb_rst_i) cs <= cyc0_lo;
else
case (cs)
default: cs <= wb_ack_i ? (op ? stb1_hi : cyc0_lo)
: cyc0_lo;
stb1_hi: cs <= wb_ack_i ? stb1_hi
: (odd_word ? stb1_lo : cyc0_lo);
stb1_lo: cs <= wb_ack_i ? stb2_hi : stb1_lo;
stb2_hi: cs <= wb_ack_i ? stb2_hi : cyc0_lo;
endcase
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_min_wdq.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Description: Write Decomposition Block
// Top level Module: jbi_min_wdq
// Where Instantiated: jbi_min
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "jbi.h"
module jbi_min_wdq(/*AUTOARG*/
// Outputs
wdq_wr_vld, wdq_rq_tag_byps, wdq_rhq_wdata, wdq_rhq3_push,
wdq_rhq2_push, wdq_rhq1_push, wdq_rhq0_push, wdq_rdq_wdata,
wdq_rdq3_push, wdq_rdq2_push, wdq_rdq1_push, wdq_rdq0_push,
min_csr_perf_dma_wr8, min_aok_on, min_aok_off,
// Inputs
testmux_sel, rst_tri_en, rst_l, rhq3_full, rhq2_full, rhq1_full,
rhq0_full, rdq3_full, rdq2_full, rdq1_full, rdq0_full,
parse_wdq_push, parse_subline_req, parse_sctag_req, parse_rw,
parse_install_mode, parse_hdr, parse_err_nonex_rd, parse_data_err,
io_jbi_j_adtype_ff, hold, csr_jbi_config2_ord_wr,
csr_jbi_config2_ord_rd, csr_jbi_config2_iq_low,
csr_jbi_config2_iq_high, clk, arst_l, io_jbi_j_ad_ff
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input arst_l; // To u_wdq_buf of jbi_min_wdq_buf.v
input clk; // To u_wdq_ctl of jbi_min_wdq_ctl.v, ...
input [3:0] csr_jbi_config2_iq_high;// To u_wdq_ctl of jbi_min_wdq_ctl.v
input [3:0] csr_jbi_config2_iq_low; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input csr_jbi_config2_ord_rd; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input csr_jbi_config2_ord_wr; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input hold; // To u_wdq_buf of jbi_min_wdq_buf.v
input [`JBI_ADTYPE_JID_HI:`JBI_ADTYPE_JID_LO]io_jbi_j_adtype_ff;// To u_wdq_ctl of jbi_min_wdq_ctl.v
input parse_data_err; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input parse_err_nonex_rd; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input parse_hdr; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input parse_install_mode; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input parse_rw; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input [2:0] parse_sctag_req; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input parse_subline_req; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input parse_wdq_push; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input rdq0_full; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input rdq1_full; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input rdq2_full; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input rdq3_full; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input rhq0_full; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input rhq1_full; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input rhq2_full; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input rhq3_full; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input rst_l; // To u_wdq_ctl of jbi_min_wdq_ctl.v
input rst_tri_en; // To u_wdq_buf of jbi_min_wdq_buf.v
input testmux_sel; // To u_wdq_buf of jbi_min_wdq_buf.v
// End of automatics
input [127:0] io_jbi_j_ad_ff;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output min_aok_off; // From u_wdq_ctl of jbi_min_wdq_ctl.v
output min_aok_on; // From u_wdq_ctl of jbi_min_wdq_ctl.v
output min_csr_perf_dma_wr8; // From u_wdq_ctl of jbi_min_wdq_ctl.v
output wdq_rdq0_push; // From u_wdq_ctl of jbi_min_wdq_ctl.v
output wdq_rdq1_push; // From u_wdq_ctl of jbi_min_wdq_ctl.v
output wdq_rdq2_push; // From u_wdq_ctl of jbi_min_wdq_ctl.v
output wdq_rdq3_push; // From u_wdq_ctl of jbi_min_wdq_ctl.v
output [`JBI_RDQ_WIDTH-1:0]wdq_rdq_wdata; // From u_wdq_ctl of jbi_min_wdq_ctl.v
output wdq_rhq0_push; // From u_wdq_ctl of jbi_min_wdq_ctl.v
output wdq_rhq1_push; // From u_wdq_ctl of jbi_min_wdq_ctl.v
output wdq_rhq2_push; // From u_wdq_ctl of jbi_min_wdq_ctl.v
output wdq_rhq3_push; // From u_wdq_ctl of jbi_min_wdq_ctl.v
output [`JBI_RHQ_WIDTH-1:0]wdq_rhq_wdata; // From u_wdq_ctl of jbi_min_wdq_ctl.v
output wdq_rq_tag_byps; // From u_wdq_ctl of jbi_min_wdq_ctl.v
output wdq_wr_vld; // From u_wdq_ctl of jbi_min_wdq_ctl.v
// End of automatics
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [`JBI_WDQ_ADDR_WIDTH-1:0]wdq_raddr; // From u_wdq_ctl of jbi_min_wdq_ctl.v
wire wdq_rd_en; // From u_wdq_ctl of jbi_min_wdq_ctl.v
wire [`JBI_WDQ_WIDTH-1:0]wdq_rdata; // From u_wdq_buf of jbi_min_wdq_buf.v
wire [`JBI_WDQ_ADDR_WIDTH-1:0]wdq_waddr; // From u_wdq_ctl of jbi_min_wdq_ctl.v
wire [127:0] wdq_wdata; // From u_wdq_ctl of jbi_min_wdq_ctl.v
wire [6:0] wdq_wdata_ecc0; // From u_wdq_ctl of jbi_min_wdq_ctl.v
wire [6:0] wdq_wdata_ecc1; // From u_wdq_ctl of jbi_min_wdq_ctl.v
wire [6:0] wdq_wdata_ecc2; // From u_wdq_ctl of jbi_min_wdq_ctl.v
wire [6:0] wdq_wdata_ecc3; // From u_wdq_ctl of jbi_min_wdq_ctl.v
wire wdq_wr_en; // From u_wdq_ctl of jbi_min_wdq_ctl.v
// End of automatics
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
//
// Code start here
//
jbi_min_wdq_ctl u_wdq_ctl (/*AUTOINST*/
// Outputs
.min_csr_perf_dma_wr8(min_csr_perf_dma_wr8),
.wdq_wr_en (wdq_wr_en),
.wdq_wdata (wdq_wdata[127:0]),
.wdq_wdata_ecc0(wdq_wdata_ecc0[6:0]),
.wdq_wdata_ecc1(wdq_wdata_ecc1[6:0]),
.wdq_wdata_ecc2(wdq_wdata_ecc2[6:0]),
.wdq_wdata_ecc3(wdq_wdata_ecc3[6:0]),
.wdq_waddr (wdq_waddr[`JBI_WDQ_ADDR_WIDTH-1:0]),
.wdq_rd_en (wdq_rd_en),
.wdq_raddr (wdq_raddr[`JBI_WDQ_ADDR_WIDTH-1:0]),
.wdq_rdq0_push(wdq_rdq0_push),
.wdq_rdq1_push(wdq_rdq1_push),
.wdq_rdq2_push(wdq_rdq2_push),
.wdq_rdq3_push(wdq_rdq3_push),
.wdq_rdq_wdata(wdq_rdq_wdata[`JBI_RDQ_WIDTH-1:0]),
.wdq_rhq0_push(wdq_rhq0_push),
.wdq_rhq1_push(wdq_rhq1_push),
.wdq_rhq2_push(wdq_rhq2_push),
.wdq_rhq3_push(wdq_rhq3_push),
.wdq_rhq_wdata(wdq_rhq_wdata[`JBI_RHQ_WIDTH-1:0]),
.wdq_rq_tag_byps(wdq_rq_tag_byps),
.wdq_wr_vld (wdq_wr_vld),
.min_aok_on (min_aok_on),
.min_aok_off (min_aok_off),
// Inputs
.clk (clk),
.rst_l (rst_l),
.csr_jbi_config2_iq_high(csr_jbi_config2_iq_high[3:0]),
.csr_jbi_config2_iq_low(csr_jbi_config2_iq_low[3:0]),
.csr_jbi_config2_ord_wr(csr_jbi_config2_ord_wr),
.csr_jbi_config2_ord_rd(csr_jbi_config2_ord_rd),
.io_jbi_j_ad_ff(io_jbi_j_ad_ff[127:0]),
.io_jbi_j_adtype_ff(io_jbi_j_adtype_ff[`JBI_ADTYPE_JID_HI:`JBI_ADTYPE_JID_LO]),
.parse_wdq_push(parse_wdq_push),
.parse_sctag_req(parse_sctag_req[2:0]),
.parse_hdr (parse_hdr),
.parse_rw (parse_rw),
.parse_subline_req(parse_subline_req),
.parse_install_mode(parse_install_mode),
.parse_data_err(parse_data_err),
.parse_err_nonex_rd(parse_err_nonex_rd),
.rdq0_full (rdq0_full),
.rdq1_full (rdq1_full),
.rdq2_full (rdq2_full),
.rdq3_full (rdq3_full),
.wdq_rdata (wdq_rdata[`JBI_WDQ_WIDTH-1:0]),
.rhq0_full (rhq0_full),
.rhq1_full (rhq1_full),
.rhq2_full (rhq2_full),
.rhq3_full (rhq3_full));
jbi_min_wdq_buf u_wdq_buf (/*AUTOINST*/
// Outputs
.wdq_rdata (wdq_rdata[`JBI_WDQ_WIDTH-1:0]),
// Inputs
.clk (clk),
.arst_l (arst_l),
.testmux_sel (testmux_sel),
.hold (hold),
.rst_tri_en (rst_tri_en),
.wdq_wr_en (wdq_wr_en),
.wdq_rd_en (wdq_rd_en),
.wdq_waddr (wdq_waddr[`JBI_WDQ_ADDR_WIDTH-1:0]),
.wdq_raddr (wdq_raddr[`JBI_WDQ_ADDR_WIDTH-1:0]),
.wdq_wdata (wdq_wdata[127:0]),
.wdq_wdata_ecc0(wdq_wdata_ecc0[6:0]),
.wdq_wdata_ecc1(wdq_wdata_ecc1[6:0]),
.wdq_wdata_ecc2(wdq_wdata_ecc2[6:0]),
.wdq_wdata_ecc3(wdq_wdata_ecc3[6:0]));
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-sense-defines-constant:t
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SDFXBP_BEHAVIORAL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXBP_BEHAVIORAL_V |
//altera message_off 10230 10036
//altera message_off 10762
`timescale 1 ps / 1 ps
module alt_mem_ddrx_rank_timer #
( parameter
CFG_DWIDTH_RATIO = 2,
CFG_CTL_TBP_NUM = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_ENABLE_BURST_INTERRUPT = 0,
CFG_ENABLE_BURST_TERMINATE = 0,
CFG_REG_GRANT = 0,
CFG_RANK_TIMER_OUTPUT_REG = 0,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
T_PARAM_FOUR_ACT_TO_ACT_WIDTH = 0,
T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH = 0,
T_PARAM_WR_TO_WR_WIDTH = 0,
T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH = 0,
T_PARAM_WR_TO_RD_WIDTH = 0,
T_PARAM_WR_TO_RD_BC_WIDTH = 0,
T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH = 0,
T_PARAM_RD_TO_RD_WIDTH = 0,
T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH = 0,
T_PARAM_RD_TO_WR_WIDTH = 0,
T_PARAM_RD_TO_WR_BC_WIDTH = 0,
T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH = 0
)
(
ctl_clk,
ctl_reset_n,
// MMR Configurations
cfg_burst_length,
// Timing parameters
t_param_four_act_to_act,
t_param_act_to_act_diff_bank,
t_param_wr_to_wr,
t_param_wr_to_wr_diff_chip,
t_param_wr_to_rd,
t_param_wr_to_rd_bc,
t_param_wr_to_rd_diff_chip,
t_param_rd_to_rd,
t_param_rd_to_rd_diff_chip,
t_param_rd_to_wr,
t_param_rd_to_wr_bc,
t_param_rd_to_wr_diff_chip,
// Arbiter Interface
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_activate,
bg_do_precharge,
bg_to_chip,
bg_effective_size,
bg_interrupt_ready,
// Command Generator Interface
cmd_gen_chipsel,
// TBP Interface
tbp_chipsel,
tbp_load,
// Sideband Interface
stall_chip,
can_activate,
can_precharge,
can_read,
can_write
);
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
input [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
input [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
input [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
input [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
input [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
input [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
input [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
input [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
input [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
input [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
input [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
input [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
input bg_interrupt_ready;
input [CFG_MEM_IF_CS_WIDTH - 1 : 0] cmd_gen_chipsel;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_chipsel;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_load;
input [CFG_MEM_IF_CHIP - 1 : 0] stall_chip;
output [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
output [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
output [CFG_CTL_TBP_NUM - 1 : 0] can_read;
output [CFG_CTL_TBP_NUM - 1 : 0] can_write;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// General
localparam RANK_TIMER_COUNTER_OFFSET = (CFG_RANK_TIMER_OUTPUT_REG) ? ((CFG_REG_GRANT) ? 4 : 3) : ((CFG_REG_GRANT) ? 3 : 2);
localparam RANK_TIMER_TFAW_OFFSET = (CFG_RANK_TIMER_OUTPUT_REG) ? ((CFG_REG_GRANT) ? 2 : 1) : ((CFG_REG_GRANT) ? 1 : 0);
localparam ENABLE_BETTER_TRRD_EFFICIENCY = 0; // ONLY set to '1' when CFG_RANK_TIMER_OUTPUT_REG is enabled, else it will fail
wire one = 1'b1;
wire zero = 1'b0;
// Timing Parameter Comparison Logic
reg less_than_1_act_to_act_diff_bank;
reg less_than_2_act_to_act_diff_bank;
reg less_than_3_act_to_act_diff_bank;
reg less_than_4_act_to_act_diff_bank;
reg less_than_4_four_act_to_act;
reg less_than_1_rd_to_rd;
reg less_than_1_rd_to_wr;
reg less_than_1_wr_to_wr;
reg less_than_1_wr_to_rd;
reg less_than_1_rd_to_wr_bc;
reg less_than_1_wr_to_rd_bc;
reg less_than_1_rd_to_rd_diff_chip;
reg less_than_1_rd_to_wr_diff_chip;
reg less_than_1_wr_to_wr_diff_chip;
reg less_than_1_wr_to_rd_diff_chip;
reg less_than_2_rd_to_rd;
reg less_than_2_rd_to_wr;
reg less_than_2_wr_to_wr;
reg less_than_2_wr_to_rd;
reg less_than_2_rd_to_wr_bc;
reg less_than_2_wr_to_rd_bc;
reg less_than_2_rd_to_rd_diff_chip;
reg less_than_2_rd_to_wr_diff_chip;
reg less_than_2_wr_to_wr_diff_chip;
reg less_than_2_wr_to_rd_diff_chip;
reg less_than_3_rd_to_rd;
reg less_than_3_rd_to_wr;
reg less_than_3_wr_to_wr;
reg less_than_3_wr_to_rd;
reg less_than_3_rd_to_wr_bc;
reg less_than_3_wr_to_rd_bc;
reg less_than_3_rd_to_rd_diff_chip;
reg less_than_3_rd_to_wr_diff_chip;
reg less_than_3_wr_to_wr_diff_chip;
reg less_than_3_wr_to_rd_diff_chip;
reg less_than_4_rd_to_rd;
reg less_than_4_rd_to_wr;
reg less_than_4_wr_to_wr;
reg less_than_4_wr_to_rd;
reg less_than_4_rd_to_wr_bc;
reg less_than_4_wr_to_rd_bc;
reg less_than_4_rd_to_rd_diff_chip;
reg less_than_4_rd_to_wr_diff_chip;
reg less_than_4_wr_to_wr_diff_chip;
reg less_than_4_wr_to_rd_diff_chip;
reg more_than_3_rd_to_rd;
reg more_than_3_rd_to_wr;
reg more_than_3_wr_to_wr;
reg more_than_3_wr_to_rd;
reg more_than_3_rd_to_wr_bc;
reg more_than_3_wr_to_rd_bc;
reg more_than_3_rd_to_rd_diff_chip;
reg more_than_3_rd_to_wr_diff_chip;
reg more_than_3_wr_to_wr_diff_chip;
reg more_than_3_wr_to_rd_diff_chip;
reg less_than_xn1_act_to_act_diff_bank;
reg less_than_xn1_rd_to_rd;
reg less_than_xn1_rd_to_wr;
reg less_than_xn1_wr_to_wr;
reg less_than_xn1_wr_to_rd;
reg less_than_xn1_rd_to_wr_bc;
reg less_than_xn1_wr_to_rd_bc;
reg less_than_xn1_rd_to_rd_diff_chip;
reg less_than_xn1_rd_to_wr_diff_chip;
reg less_than_xn1_wr_to_wr_diff_chip;
reg less_than_xn1_wr_to_rd_diff_chip;
reg less_than_x0_act_to_act_diff_bank;
reg less_than_x0_rd_to_rd;
reg less_than_x0_rd_to_wr;
reg less_than_x0_wr_to_wr;
reg less_than_x0_wr_to_rd;
reg less_than_x0_rd_to_wr_bc;
reg less_than_x0_wr_to_rd_bc;
reg less_than_x0_rd_to_rd_diff_chip;
reg less_than_x0_rd_to_wr_diff_chip;
reg less_than_x0_wr_to_wr_diff_chip;
reg less_than_x0_wr_to_rd_diff_chip;
reg less_than_x1_act_to_act_diff_bank;
reg less_than_x1_rd_to_rd;
reg less_than_x1_rd_to_wr;
reg less_than_x1_wr_to_wr;
reg less_than_x1_wr_to_rd;
reg less_than_x1_rd_to_wr_bc;
reg less_than_x1_wr_to_rd_bc;
reg less_than_x1_rd_to_rd_diff_chip;
reg less_than_x1_rd_to_wr_diff_chip;
reg less_than_x1_wr_to_wr_diff_chip;
reg less_than_x1_wr_to_rd_diff_chip;
// Input
reg int_do_activate;
reg int_do_precharge;
reg int_do_burst_chop;
reg int_do_burst_terminate;
reg int_do_write;
reg int_do_read;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_to_chip_r;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_to_chip_c;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_effective_size;
reg int_interrupt_ready;
// Activate Monitor
localparam ACTIVATE_COUNTER_WIDTH = T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH;
localparam ACTIVATE_COMMAND_WIDTH = 3;
localparam NUM_OF_TFAW_SHIFT_REG = 2 ** T_PARAM_FOUR_ACT_TO_ACT_WIDTH;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_tfaw_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_tfaw_ready_combi;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_trrd_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_trrd_ready_combi;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_ready;
wire [ACTIVATE_COMMAND_WIDTH - 1 : 0] act_tfaw_cmd_count [CFG_MEM_IF_CHIP - 1 : 0];
// Read/Write Monitor
localparam IDLE = 32'h49444C45;
localparam WR = 32'h20205752;
localparam RD = 32'h20205244;
localparam RDWR_COUNTER_WIDTH = (T_PARAM_RD_TO_WR_WIDTH > T_PARAM_WR_TO_RD_WIDTH) ? T_PARAM_RD_TO_WR_WIDTH : T_PARAM_WR_TO_RD_WIDTH;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] max_local_burst_size;
reg [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] effective_rd_to_wr_combi;
reg [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] effective_rd_to_wr_diff_chip_combi;
reg [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] effective_wr_to_rd_combi;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] effective_wr_to_rd_diff_chip_combi;
reg [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] effective_rd_to_wr;
reg [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] effective_rd_to_wr_diff_chip;
reg [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] effective_wr_to_rd;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] effective_wr_to_rd_diff_chip;
reg [CFG_MEM_IF_CHIP - 1 : 0] read_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] write_ready;
// Precharge Monitor
reg [CFG_MEM_IF_CHIP - 1 : 0] pch_ready;
// Output
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_activate;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_precharge;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_read;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_write;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_read;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_write;
reg [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] sel_act_tfaw_shift_out_point;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Input
//
//--------------------------------------------------------------------------------------------------------
// Do activate
always @ (*)
begin
int_do_activate = |bg_do_activate;
end
// Do precharge
always @ (*)
begin
int_do_precharge = |bg_do_precharge;
end
//Do burst chop
always @ (*)
begin
int_do_burst_chop = |bg_do_burst_chop;
end
//Do burst terminate
always @ (*)
begin
int_do_burst_terminate = |bg_do_burst_terminate;
end
// Do write
always @ (*)
begin
int_do_write = |bg_do_write;
end
// Do read
always @ (*)
begin
int_do_read = |bg_do_read;
end
// To chip
always @ (*)
begin
// _r for row command and _c for column command
if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
int_to_chip_c = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0 ];
int_to_chip_r = bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
end
else if (CFG_CTL_ARBITER_TYPE == "ROWCOL")
begin
int_to_chip_r = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0 ];
int_to_chip_c = bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
end
end
// Effective size
always @ (*)
begin
int_effective_size = bg_effective_size;
end
// Interrupt ready
always @ (*)
begin
int_interrupt_ready = bg_interrupt_ready;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Input
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Output
//
//--------------------------------------------------------------------------------------------------------
generate
genvar x_cs;
for (x_cs = 0; x_cs < CFG_CTL_TBP_NUM;x_cs = x_cs + 1)
begin : can_logic_per_chip
reg [CFG_MEM_IF_CS_WIDTH - 1 : 0] chip_addr;
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG && tbp_load [x_cs])
begin
chip_addr = cmd_gen_chipsel;
end
else
begin
chip_addr = tbp_chipsel [(x_cs + 1) * CFG_MEM_IF_CS_WIDTH - 1 : x_cs * CFG_MEM_IF_CS_WIDTH];
end
end
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
always @ (*)
begin
can_activate [x_cs] = int_can_activate [x_cs] ;
can_precharge [x_cs] = int_can_precharge [x_cs] ;
can_read [x_cs] = int_can_read [x_cs] & int_interrupt_ready;
can_write [x_cs] = int_can_write [x_cs] & int_interrupt_ready;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_activate [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_activate [x_cs] <= 1'b0;
end
else if (int_do_activate && int_to_chip_r [chip_addr] && !ENABLE_BETTER_TRRD_EFFICIENCY)
begin
int_can_activate [x_cs] <= 1'b0;
end
else
begin
int_can_activate [x_cs] <= act_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_precharge [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_precharge [x_cs] <= 1'b0;
end
else
begin
int_can_precharge [x_cs] <= pch_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_read [x_cs] <= 1'b0;
end
else if (int_do_write)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (int_do_burst_chop && more_than_3_wr_to_rd_bc)
begin
int_can_read [x_cs] <= 1'b0;
end
else if (!int_do_burst_chop && more_than_3_wr_to_rd)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
int_can_read [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_read [x_cs] <= 1'b0;
end
end
else if (int_do_read)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (more_than_3_rd_to_rd)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
int_can_read [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_read [x_cs] <= 1'b0;
end
end
else
begin
int_can_read [x_cs] <= read_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_write [x_cs] <= 1'b0;
end
else if (int_do_read)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (int_do_burst_chop && more_than_3_rd_to_wr_bc)
begin
int_can_write [x_cs] <= 1'b0;
end
else if (!int_do_burst_chop && more_than_3_rd_to_wr)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
int_can_write [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_write [x_cs] <= 1'b0;
end
end
else if (int_do_write)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (more_than_3_wr_to_wr)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
int_can_write [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_write [x_cs] <= 1'b0;
end
end
else
begin
int_can_write [x_cs] <= write_ready [chip_addr];
end
end
end
end
else
begin
// Can activate
always @ (*)
begin
can_activate [x_cs] = act_ready [chip_addr];
end
// Can precharge
always @ (*)
begin
can_precharge [x_cs] = pch_ready [chip_addr];
end
// Can read
always @ (*)
begin
can_read [x_cs] = read_ready [chip_addr];
end
// Can write
always @ (*)
begin
can_write [x_cs] = write_ready [chip_addr];
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Output
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Timing Parameter Comparison Logic
//
//--------------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 1)
less_than_1_act_to_act_diff_bank <= 1'b1;
else
less_than_1_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 2)
less_than_2_act_to_act_diff_bank <= 1'b1;
else
less_than_2_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 3)
less_than_3_act_to_act_diff_bank <= 1'b1;
else
less_than_3_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 4)
less_than_4_act_to_act_diff_bank <= 1'b1;
else
less_than_4_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_four_act_to_act <= 1'b0;
end
else
begin
if (t_param_four_act_to_act <= 4)
less_than_4_four_act_to_act <= 1'b1;
else
less_than_4_four_act_to_act <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 1)
less_than_1_rd_to_rd <= 1'b1;
else
less_than_1_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 1)
less_than_1_rd_to_wr <= 1'b1;
else
less_than_1_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 1)
less_than_1_wr_to_wr <= 1'b1;
else
less_than_1_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 1)
less_than_1_wr_to_rd <= 1'b1;
else
less_than_1_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 1)
less_than_1_rd_to_wr_bc <= 1'b1;
else
less_than_1_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 1)
less_than_1_wr_to_rd_bc <= 1'b1;
else
less_than_1_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 1)
less_than_1_rd_to_rd_diff_chip <= 1'b1;
else
less_than_1_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 1)
less_than_1_rd_to_wr_diff_chip <= 1'b1;
else
less_than_1_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 1)
less_than_1_wr_to_wr_diff_chip <= 1'b1;
else
less_than_1_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 1)
less_than_1_wr_to_rd_diff_chip <= 1'b1;
else
less_than_1_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 2)
less_than_2_rd_to_rd <= 1'b1;
else
less_than_2_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 2)
less_than_2_rd_to_wr <= 1'b1;
else
less_than_2_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 2)
less_than_2_wr_to_wr <= 1'b1;
else
less_than_2_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 2)
less_than_2_wr_to_rd <= 1'b1;
else
less_than_2_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 2)
less_than_2_rd_to_wr_bc <= 1'b1;
else
less_than_2_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 2)
less_than_2_wr_to_rd_bc <= 1'b1;
else
less_than_2_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 2)
less_than_2_rd_to_rd_diff_chip <= 1'b1;
else
less_than_2_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 2)
less_than_2_rd_to_wr_diff_chip <= 1'b1;
else
less_than_2_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 2)
less_than_2_wr_to_wr_diff_chip <= 1'b1;
else
less_than_2_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 2)
less_than_2_wr_to_rd_diff_chip <= 1'b1;
else
less_than_2_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 3)
less_than_3_rd_to_rd <= 1'b1;
else
less_than_3_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 3)
less_than_3_rd_to_wr <= 1'b1;
else
less_than_3_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 3)
less_than_3_wr_to_wr <= 1'b1;
else
less_than_3_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 3)
less_than_3_wr_to_rd <= 1'b1;
else
less_than_3_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 3)
less_than_3_rd_to_wr_bc <= 1'b1;
else
less_than_3_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 3)
less_than_3_wr_to_rd_bc <= 1'b1;
else
less_than_3_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 3)
less_than_3_rd_to_rd_diff_chip <= 1'b1;
else
less_than_3_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 3)
less_than_3_rd_to_wr_diff_chip <= 1'b1;
else
less_than_3_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 3)
less_than_3_wr_to_wr_diff_chip <= 1'b1;
else
less_than_3_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 3)
less_than_3_wr_to_rd_diff_chip <= 1'b1;
else
less_than_3_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 4)
less_than_4_rd_to_rd <= 1'b1;
else
less_than_4_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 4)
less_than_4_rd_to_wr <= 1'b1;
else
less_than_4_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 4)
less_than_4_wr_to_wr <= 1'b1;
else
less_than_4_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 4)
less_than_4_wr_to_rd <= 1'b1;
else
less_than_4_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 4)
less_than_4_rd_to_wr_bc <= 1'b1;
else
less_than_4_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 4)
less_than_4_wr_to_rd_bc <= 1'b1;
else
less_than_4_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 4)
less_than_4_rd_to_rd_diff_chip <= 1'b1;
else
less_than_4_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 4)
less_than_4_rd_to_wr_diff_chip <= 1'b1;
else
less_than_4_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 4)
less_than_4_wr_to_wr_diff_chip <= 1'b1;
else
less_than_4_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 4)
less_than_4_wr_to_rd_diff_chip <= 1'b1;
else
less_than_4_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd >= 3)
more_than_3_rd_to_rd <= 1'b1;
else
more_than_3_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr >= 3)
more_than_3_rd_to_wr <= 1'b1;
else
more_than_3_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr >= 3)
more_than_3_wr_to_wr <= 1'b1;
else
more_than_3_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd >= 3)
more_than_3_wr_to_rd <= 1'b1;
else
more_than_3_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc >= 3)
more_than_3_rd_to_wr_bc <= 1'b1;
else
more_than_3_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc >= 3)
more_than_3_wr_to_rd_bc <= 1'b1;
else
more_than_3_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip >= 3)
more_than_3_rd_to_rd_diff_chip <= 1'b1;
else
more_than_3_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip >= 3)
more_than_3_rd_to_wr_diff_chip <= 1'b1;
else
more_than_3_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip >= 3)
more_than_3_wr_to_wr_diff_chip <= 1'b1;
else
more_than_3_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip >= 3)
more_than_3_wr_to_rd_diff_chip <= 1'b1;
else
more_than_3_wr_to_rd_diff_chip <= 1'b0;
end
end
generate
begin
if (CFG_REG_GRANT)
begin
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
less_than_xn1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_2_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_2_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_2_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_2_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_3_rd_to_rd;
less_than_x0_rd_to_wr = less_than_3_rd_to_wr;
less_than_x0_wr_to_wr = less_than_3_wr_to_wr;
less_than_x0_wr_to_rd = less_than_3_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_4_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_4_rd_to_rd;
less_than_x1_rd_to_wr = less_than_4_rd_to_wr;
less_than_x1_wr_to_wr = less_than_4_wr_to_wr;
less_than_x1_wr_to_rd = less_than_4_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_4_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_4_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_4_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_4_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_4_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_4_wr_to_rd_diff_chip;
end
else
begin
// Doesn't matter for less_than_xn1_* if CFG_RANK_TIMER_OUTPUT_REG is '0'
less_than_xn1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_2_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_2_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_2_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_2_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_2_rd_to_rd;
less_than_x0_rd_to_wr = less_than_2_rd_to_wr;
less_than_x0_wr_to_wr = less_than_2_wr_to_wr;
less_than_x0_wr_to_rd = less_than_2_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_3_rd_to_rd;
less_than_x1_rd_to_wr = less_than_3_rd_to_wr;
less_than_x1_wr_to_wr = less_than_3_wr_to_wr;
less_than_x1_wr_to_rd = less_than_3_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
end
end
end
else
begin
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
less_than_xn1_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_1_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_1_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_1_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_1_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_2_rd_to_rd;
less_than_x0_rd_to_wr = less_than_2_rd_to_wr;
less_than_x0_wr_to_wr = less_than_2_wr_to_wr;
less_than_x0_wr_to_rd = less_than_2_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_3_rd_to_rd;
less_than_x1_rd_to_wr = less_than_3_rd_to_wr;
less_than_x1_wr_to_wr = less_than_3_wr_to_wr;
less_than_x1_wr_to_rd = less_than_3_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
end
else
begin
// Doesn't matter for less_than_xn1_* if CFG_RANK_TIMER_OUTPUT_REG is '0'
less_than_xn1_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_1_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_1_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_1_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_1_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_1_rd_to_rd;
less_than_x0_rd_to_wr = less_than_1_rd_to_wr;
less_than_x0_wr_to_wr = less_than_1_wr_to_wr;
less_than_x0_wr_to_rd = less_than_1_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_2_rd_to_rd;
less_than_x1_rd_to_wr = less_than_2_rd_to_wr;
less_than_x1_wr_to_wr = less_than_2_wr_to_wr;
less_than_x1_wr_to_rd = less_than_2_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Timing Parameter Comparison Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Activate Monitor
//
// Monitors the following rank timing parameters:
//
// - tFAW, four activate window, only four activate is allowed in a specific timing window
// - tRRD, activate to activate different bank
//
//--------------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sel_act_tfaw_shift_out_point <= 0;
end
else
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
sel_act_tfaw_shift_out_point <= t_param_four_act_to_act - RANK_TIMER_TFAW_OFFSET + 1;
end
else
begin
sel_act_tfaw_shift_out_point <= t_param_four_act_to_act - RANK_TIMER_TFAW_OFFSET;
end
end
end
generate
genvar t_cs;
genvar t_tfaw;
for (t_cs = 0;t_cs < CFG_MEM_IF_CHIP;t_cs = t_cs + 1)
begin : act_monitor_per_chip
//----------------------------------------------------------------------------------------------------
// tFAW Monitor
//----------------------------------------------------------------------------------------------------
reg [ACTIVATE_COMMAND_WIDTH - 1 : 0] act_tfaw_cmd_cnt;
reg [NUM_OF_TFAW_SHIFT_REG - 1 : 0] act_tfaw_shift_reg;
assign act_tfaw_cmd_count [t_cs] = act_tfaw_cmd_cnt;
// Shift register to keep track of tFAW
// Shift in -> n, n-1, n-2, n-3.......4, 3 -> Shift out
// Shift in '1' when there is an activate else shift in '0'
// Shift out every clock cycles
// Shift register [3]
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_shift_reg [3] <= 1'b0;
end
else
begin
// Shift in '1' if there is an activate
// else shift in '0'
if (int_do_activate && int_to_chip_r [t_cs])
act_tfaw_shift_reg [3] <= 1'b1;
else
act_tfaw_shift_reg [3] <= 1'b0;
end
end
// Shift register [n : 3]
for (t_tfaw = 4;t_tfaw < NUM_OF_TFAW_SHIFT_REG;t_tfaw = t_tfaw + 1)
begin : tfaw_shift_register
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_shift_reg [t_tfaw] <= 1'b0;
end
else
begin
act_tfaw_shift_reg [t_tfaw] <= act_tfaw_shift_reg [t_tfaw - 1];
end
end
end
// Activate command counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_cmd_cnt <= 0;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (act_tfaw_shift_reg [sel_act_tfaw_shift_out_point]) // Shift out when activate reaches tFAW point in shift register
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt;
else
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt + 1'b1;
end
else if (act_tfaw_shift_reg [sel_act_tfaw_shift_out_point]) // Shift out when activate reaches tFAW point in shift register
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt - 1'b1;
end
end
// tFAW ready signal
always @ (*)
begin
// If tFAW is lesser than 4, this means we can do back-to-back activate without tFAW constraint
if (less_than_4_four_act_to_act)
begin
act_tfaw_ready_combi [t_cs] = 1'b1;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs] && act_tfaw_cmd_cnt == 3'd3)
act_tfaw_ready_combi [t_cs] = 1'b0;
else if (act_tfaw_cmd_cnt < 3'd4)
act_tfaw_ready_combi [t_cs] = 1'b1;
else
act_tfaw_ready_combi [t_cs] = 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_ready [t_cs] <= 1'b0;
end
else
begin
act_tfaw_ready [t_cs] <= act_tfaw_ready_combi [t_cs];
end
end
//----------------------------------------------------------------------------------------------------
// tRRD Monitor
//----------------------------------------------------------------------------------------------------
reg [ACTIVATE_COUNTER_WIDTH - 1 : 0] act_trrd_cnt;
// tRRD counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_trrd_cnt <= 0;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
act_trrd_cnt <= RANK_TIMER_COUNTER_OFFSET - 1;
end
else
begin
act_trrd_cnt <= RANK_TIMER_COUNTER_OFFSET;
end
end
else if (act_trrd_cnt != {ACTIVATE_COUNTER_WIDTH{1'b1}})
begin
act_trrd_cnt <= act_trrd_cnt + 1'b1;
end
end
end
// tRRD monitor
always @ (*)
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (!ENABLE_BETTER_TRRD_EFFICIENCY && less_than_x0_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else if (ENABLE_BETTER_TRRD_EFFICIENCY && less_than_xn1_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else
act_trrd_ready_combi [t_cs] = 1'b0;
end
else if (act_trrd_cnt >= t_param_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else
act_trrd_ready_combi [t_cs] = 1'b0;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_trrd_ready [t_cs] <= 1'b0;
end
else
begin
act_trrd_ready [t_cs] <= act_trrd_ready_combi [t_cs];
end
end
//----------------------------------------------------------------------------------------------------
// Overall activate ready
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [t_cs])
begin
act_ready [t_cs] = 1'b0;
end
else
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
act_ready [t_cs] = act_trrd_ready_combi [t_cs] & act_tfaw_ready_combi [t_cs];
end
else
begin
act_ready [t_cs] = act_trrd_ready [t_cs] & act_tfaw_ready [t_cs];
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Activate Monitor
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Read/Write Monitor
//
// Monitors the following rank timing parameters:
//
// - Write to read timing parameter (tWTR)
// - Read to write timing parameter
//
// Missing Features:
//
// - Burst interrupt
// - Burst terminate
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Effective Timing Parameters
// Only when burst interrupt option is enabled
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size <= 0;
end
else
begin
max_local_burst_size <= cfg_burst_length / CFG_DWIDTH_RATIO;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
effective_rd_to_wr <= 0;
effective_rd_to_wr_diff_chip <= 0;
effective_wr_to_rd <= 0;
effective_wr_to_rd_diff_chip <= 0;
end
else
begin
if (int_do_burst_chop)
begin
effective_rd_to_wr <= t_param_rd_to_wr_bc;
effective_rd_to_wr_diff_chip <= t_param_rd_to_wr_diff_chip;
effective_wr_to_rd <= t_param_wr_to_rd_bc;
effective_wr_to_rd_diff_chip <= t_param_wr_to_rd_diff_chip;
end
else if (int_do_burst_terminate)
begin
if (t_param_rd_to_wr > (max_local_burst_size - int_effective_size))
effective_rd_to_wr <= t_param_rd_to_wr - (max_local_burst_size - int_effective_size);
else
effective_rd_to_wr <= 1'b1;
if (t_param_rd_to_wr_diff_chip > (max_local_burst_size - int_effective_size))
effective_rd_to_wr_diff_chip <= t_param_rd_to_wr_diff_chip - (max_local_burst_size - int_effective_size);
else
effective_rd_to_wr_diff_chip <= 1'b1;
if (t_param_wr_to_rd > (max_local_burst_size - int_effective_size))
effective_wr_to_rd <= t_param_wr_to_rd - (max_local_burst_size - int_effective_size);
else
effective_wr_to_rd <= 1'b1;
if (t_param_wr_to_rd_diff_chip > (max_local_burst_size - int_effective_size))
effective_wr_to_rd_diff_chip <= t_param_wr_to_rd_diff_chip - (max_local_burst_size - int_effective_size);
else
effective_wr_to_rd_diff_chip <= 1'b1;
end
end
end
//----------------------------------------------------------------------------------------------------
// Read / Write State Machine
//----------------------------------------------------------------------------------------------------
generate
genvar s_cs;
for (s_cs = 0;s_cs < CFG_MEM_IF_CHIP;s_cs = s_cs + 1)
begin : rdwr_monitor_per_chip
reg [31 : 0] rdwr_state;
reg [RDWR_COUNTER_WIDTH - 1 : 0] read_cnt_this_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] write_cnt_this_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] read_cnt_diff_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] write_cnt_diff_chip;
reg int_do_read_this_chip;
reg int_do_write_this_chip;
reg int_do_read_diff_chip;
reg int_do_write_diff_chip;
reg doing_burst_chop;
reg doing_burst_terminate;
reg int_read_ready;
reg int_write_ready;
// Do read/write to this/different chip
always @ (*)
begin
if (int_do_read)
begin
if (int_to_chip_c [s_cs])
begin
int_do_read_this_chip = 1'b1;
int_do_read_diff_chip = 1'b0;
end
else
begin
int_do_read_this_chip = 1'b0;
int_do_read_diff_chip = 1'b1;
end
end
else
begin
int_do_read_this_chip = 1'b0;
int_do_read_diff_chip = 1'b0;
end
end
always @ (*)
begin
if (int_do_write)
begin
if (int_to_chip_c [s_cs])
begin
int_do_write_this_chip = 1'b1;
int_do_write_diff_chip = 1'b0;
end
else
begin
int_do_write_this_chip = 1'b0;
int_do_write_diff_chip = 1'b1;
end
end
else
begin
int_do_write_this_chip = 1'b0;
int_do_write_diff_chip = 1'b0;
end
end
// Read write counter to this chip address
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
read_cnt_this_chip <= 0;
write_cnt_this_chip <= 0;
end
else
begin
if (int_do_read_this_chip)
read_cnt_this_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (read_cnt_this_chip != {RDWR_COUNTER_WIDTH{1'b1}})
read_cnt_this_chip <= read_cnt_this_chip + 1'b1;
if (int_do_write_this_chip)
write_cnt_this_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (write_cnt_this_chip != {RDWR_COUNTER_WIDTH{1'b1}})
write_cnt_this_chip <= write_cnt_this_chip + 1'b1;
end
end
// Read write counter to different chip address
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
read_cnt_diff_chip <= 0;
write_cnt_diff_chip <= 0;
end
else
begin
if (int_do_read_diff_chip)
read_cnt_diff_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (read_cnt_diff_chip != {RDWR_COUNTER_WIDTH{1'b1}})
read_cnt_diff_chip <= read_cnt_diff_chip + 1'b1;
if (int_do_write_diff_chip)
write_cnt_diff_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (write_cnt_diff_chip != {RDWR_COUNTER_WIDTH{1'b1}})
write_cnt_diff_chip <= write_cnt_diff_chip + 1'b1;
end
end
// Doing burst chop signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_chop <= 1'b0;
end
else
begin
if (int_do_read || int_do_write)
begin
if (int_do_burst_chop)
doing_burst_chop <= 1'b1;
else
doing_burst_chop <= 1'b0;
end
end
end
// Doing burst terminate signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_terminate <= 1'b0;
end
else
begin
if (int_do_read || int_do_write)
doing_burst_terminate <= 1'b0;
else if (int_do_burst_terminate)
doing_burst_terminate <= 1'b1;
end
end
// Register comparison logic for better fMAX
reg compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd;
reg compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip;
reg compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr;
reg compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr;
reg compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd;
reg compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip;
reg compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr;
reg compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd;
reg compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
// Read to this chip comparison
if (int_do_read_this_chip)
begin
if (less_than_x1_rd_to_rd)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
end
if (less_than_x1_rd_to_wr)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
end
end
else
begin
if (read_cnt_this_chip >= (t_param_rd_to_rd - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
end
if (read_cnt_this_chip >= (t_param_rd_to_wr - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
end
end
// Read to different chip comparison
if (int_do_read_diff_chip)
begin
if (less_than_x1_rd_to_rd_diff_chip)
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
end
if (less_than_x1_rd_to_wr_diff_chip)
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
end
end
else
begin
if (read_cnt_diff_chip >= (t_param_rd_to_rd_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
end
if (read_cnt_diff_chip >= (t_param_rd_to_wr_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
end
end
// Write to this chip comparison
if (int_do_write_this_chip)
begin
if (less_than_x1_wr_to_wr)
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
end
if (less_than_x1_wr_to_rd)
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
end
end
else
begin
if (write_cnt_this_chip >= (t_param_wr_to_wr - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
end
if (write_cnt_this_chip >= (t_param_wr_to_rd - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
end
end
// Write to different chip comparison
if (int_do_write_diff_chip)
begin
if (less_than_x1_wr_to_wr_diff_chip)
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
end
if (less_than_x1_wr_to_rd_diff_chip)
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
end
else
begin
if (write_cnt_diff_chip >= (t_param_wr_to_wr_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
end
if (write_cnt_diff_chip >= (t_param_wr_to_rd_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
// Read to this chip comparison
if (int_do_read_this_chip)
begin
if (t_param_rd_to_wr <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
end
end
else
begin
if (read_cnt_this_chip >= (effective_rd_to_wr - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
end
end
// Read to different chip comparison
if (int_do_read_diff_chip)
begin
if (t_param_rd_to_wr_diff_chip <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
end
end
else
begin
if (read_cnt_diff_chip >= (effective_rd_to_wr_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
end
end
// Write to this chip comparison
if (int_do_write_this_chip)
begin
if (t_param_wr_to_rd <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
end
end
else
begin
if (write_cnt_this_chip >= (effective_wr_to_rd - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
end
end
// Write to different chip comparison
if (int_do_write_diff_chip)
begin
if (t_param_wr_to_rd_diff_chip <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
end
else
begin
if (write_cnt_diff_chip >= (effective_wr_to_rd_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
end
end
end
// Read write monitor state machine
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_state <= IDLE;
int_read_ready <= 1'b0;
int_write_ready <= 1'b0;
end
else
begin
case (rdwr_state)
IDLE :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
rdwr_state <= IDLE;
int_read_ready <= 1'b1;
int_write_ready <= 1'b1;
end
end
WR :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (doing_burst_chop || doing_burst_terminate) // burst chop or burst terminate
begin
if (compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd &&
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr && compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
end
RD :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (doing_burst_chop || doing_burst_terminate) // burst chop or burst terminate
begin
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr &&
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
end
default :
rdwr_state <= IDLE;
endcase
end
end
// Assign read/write ready signal to top
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [s_cs])
begin
read_ready [s_cs] = 1'b0;
write_ready [s_cs] = 1'b0;
end
else
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
read_ready [s_cs] = int_read_ready;
write_ready [s_cs] = int_write_ready;
end
else
begin
read_ready [s_cs] = int_read_ready & int_interrupt_ready;
write_ready [s_cs] = int_write_ready & int_interrupt_ready;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Read/Write Monitor
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Precharge Monitor
//
//--------------------------------------------------------------------------------------------------------
generate
genvar u_cs;
for (u_cs = 0;u_cs < CFG_MEM_IF_CHIP;u_cs = u_cs + 1)
begin : pch_monitor_per_chip
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [u_cs])
pch_ready [u_cs] = 1'b0;
else
pch_ready [u_cs] = one;
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Precharge Monitor
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Wishbone controller for ////
//// Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/minsoc/ ////
//// ////
//// Description ////
//// This Wishbone controller connects to the wrapper of ////
//// the single-port synchronous memory interface. ////
//// Besides universal memory due to onchip_ram it provides a ////
//// generic way to set the depth of the memory. ////
//// ////
//// To Do: ////
//// ////
//// Author(s): ////
//// - Raul Fajardo, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revision History
//
// Revision 1.1 2009/10/02 16:49 fajardo
// Not using the oe signal (output enable) from
// memories, instead multiplexing the outputs
// between the different instantiated blocks
//
//
// Revision 1.0 2009/08/18 15:15:00 fajardo
// Created interface and tested
//
`include "minsoc_defines.v"
`define mem_init_file "uart-nocache.mif" //specific memory initalization file name, which can be intel hex(.hex) or Altera mif file
//if no initalization file used, give a name of "UNUSED"
module minsoc_onchip_ram_top (
wb_clk_i, wb_rst_i,
wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o
);
//
// Parameters
//
parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12
localparam aw_int = 11; //11 = 2048
localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data
//
// I/O Ports
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f
//
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
//
// Internal regs and wires
//
wire we;
wire [3:0] be_i;
wire [31:0] wb_dat_o;
reg ack_we;
reg ack_re;
//
// Aliases and simple assignments
//
assign wb_ack_o = ack_re | ack_we;
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored)
assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]);
assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;
//
// Write acknowledge
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_we <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
ack_we <= #1 1'b1;
else
ack_we <= #1 1'b0;
end
//
// read acknowledge
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_re <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)
ack_re <= #1 1'b1;
else
ack_re <= #1 1'b0;
end
`ifdef ALTERA_FPGA //only for altera memory initialization
//2^adr_width x 32bit single-port ram.
altsyncram altsyncram_component (
.wren_a (we),
.clock0 (wb_clk_i),
.byteena_a (be_i),
.address_a (wb_adr_i[adr_width+1:2]),
.data_a (wb_dat_i),
.q_a (wb_dat_o),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = `mem_init_file,
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.numwords_a = (1<<adr_width),
altsyncram_component.widthad_a = adr_width,
altsyncram_component.width_a = 32,
altsyncram_component.byte_size = 8,
altsyncram_component.width_byteena_a = 4;
`else //other FPGA Type
//Generic (multiple inputs x 1 output) MUX
localparam mux_in_nr = blocks;
localparam slices = adr_width-aw_int;
localparam mux_out_nr = blocks-1;
wire [31:0] int_dat_o[0:mux_in_nr-1];
wire [31:0] mux_out[0:mux_out_nr-1];
generate
genvar j, k;
for (j=0; j<slices; j=j+1) begin : SLICES
for (k=0; k<(mux_in_nr>>(j+1)); k=k+1) begin : MUX
if (j==0) begin
mux2 #
(
.dw(32)
)
mux_int(
.sel( wb_adr_i[aw_int+2+j] ),
.in1( int_dat_o[k*2] ),
.in2( int_dat_o[k*2+1] ),
.out( mux_out[k] )
);
end
else begin
mux2 #
(
.dw(32)
)
mux_int(
.sel( wb_adr_i[aw_int+2+j] ),
.in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ),
.in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ),
.out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] )
);
end
end
end
endgenerate
//last output = total output
assign wb_dat_o = mux_out[mux_out_nr-1];
//(mux_in_nr-(mux_in_nr>>j)):
//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x
//so, with this expression I'm evaluating how many times the internal loop has been run
wire [blocks-1:0] bank;
generate
genvar i;
for (i=0; i < blocks; i=i+1) begin : MEM
assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i;
//BANK0
minsoc_onchip_ram block_ram_0 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[7:0]),
.doq(int_dat_o[i][7:0]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[0])
);
minsoc_onchip_ram block_ram_1 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[15:8]),
.doq(int_dat_o[i][15:8]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[1])
);
minsoc_onchip_ram block_ram_2 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[23:16]),
.doq(int_dat_o[i][23:16]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[2])
);
minsoc_onchip_ram block_ram_3 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[31:24]),
.doq(int_dat_o[i][31:24]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[3])
);
end
endgenerate
`endif
endmodule
module mux2(sel,in1,in2,out);
parameter dw = 32;
input sel;
input [dw-1:0] in1, in2;
output reg [dw-1:0] out;
always @ (sel or in1 or in2)
begin
case (sel)
1'b0: out = in1;
1'b1: out = in2;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAPKAPWR_SYMBOL_V
`define SKY130_FD_SC_LP__DECAPKAPWR_SYMBOL_V
/**
* decapkapwr: Decoupling capacitance filler on keep-alive rail.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__decapkapwr ();
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAPKAPWR_SYMBOL_V
|
module sorter_testbench;
reg reset;
reg clock;
wire load;
wire [7:0] in0;
wire [7:0] in1;
wire [7:0] in2;
wire [7:0] in3;
wire [7:0] in4;
wire [7:0] in5;
wire [7:0] in6;
wire [7:0] in7;
wire sorted;
wire [7:0] out0;
wire [7:0] out1;
wire [7:0] out2;
wire [7:0] out3;
wire [7:0] out4;
wire [7:0] out5;
wire [7:0] out6;
wire [7:0] out7;
sorter dut
( .reset(reset)
, .clock(clock)
, .in7(in7)
, .in6(in6)
, .in5(in5)
, .in4(in4)
, .in3(in3)
, .in2(in2)
, .in1(in1)
, .in0(in0)
, .load(load)
, .sorted(sorted)
, .out0(out0)
, .out1(out1)
, .out2(out2)
, .out3(out3)
, .out4(out4)
, .out5(out5)
, .out6(out6)
, .out7(out7)
);
sorter_stimulus stim
( .reset(reset)
, .clock(clock)
, .in7(in7)
, .in6(in6)
, .in5(in5)
, .in4(in4)
, .in3(in3)
, .in2(in2)
, .in1(in1)
, .in0(in0)
, .load(load)
, .sorted(sorted)
, .out0(out0)
, .out1(out1)
, .out2(out2)
, .out3(out3)
, .out4(out4)
, .out5(out5)
, .out6(out6)
, .out7(out7)
);
initial begin
reset = 0;
clock = 0;
#1 reset = 1;
#1 reset = 0;
forever begin
#1 clock = 1;
#1 clock = 0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2I_PP_SYMBOL_V
`define SKY130_FD_SC_HS__MUX2I_PP_SYMBOL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__mux2i (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
output Y ,
//# {{control|Control Signals}}
input S ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2I_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XNOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__XNOR2_FUNCTIONAL_PP_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y , A, B );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__XNOR2_FUNCTIONAL_PP_V |
// ======================================================================
// Data_Collection_Firmware.v generated from TopDesign.cysch
// 09/04/2014 at 17:45
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_DIE_LEOPARD 1
`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
`define CYDEV_CHIP_REV_LEOPARD_ES3 3
`define CYDEV_CHIP_REV_LEOPARD_ES2 1
`define CYDEV_CHIP_REV_LEOPARD_ES1 0
`define CYDEV_CHIP_DIE_PSOC4A 2
`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17
`define CYDEV_CHIP_REV_PSOC4A_ES0 17
`define CYDEV_CHIP_DIE_PANTHER 3
`define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1
`define CYDEV_CHIP_REV_PANTHER_ES1 1
`define CYDEV_CHIP_REV_PANTHER_ES0 0
`define CYDEV_CHIP_DIE_PSOC5LP 4
`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0
`define CYDEV_CHIP_REV_PSOC5LP_ES0 0
`define CYDEV_CHIP_DIE_EXPECT 1
`define CYDEV_CHIP_REV_EXPECT 3
`define CYDEV_CHIP_DIE_ACTUAL 1
/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4A 2
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4D 3
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4D_ES0 0
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5A 4
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_MEMBER_5B 5
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_FAMILY_USED 1
`define CYDEV_CHIP_MEMBER_USED 1
`define CYDEV_CHIP_REVISION_USED 3
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif
// USBFS_v2_70(AudioDescriptors=<?xml version="1.0" encoding="utf-16"?> <Tree xmlns:CustomizerVersion="2_0"> <Tree_x0020_Descriptors> <DescriptorNode Key="Audio"> <Nodes /> </DescriptorNode> </Tree_x0020_Descriptors> </Tree>, CDCDescriptors=<?xml version="1.0" encoding="utf-16"?> <Tree xmlns:CustomizerVersion="2_0"> <Tree_x0020_Descriptors> <DescriptorNode Key="CDC"> <Nodes> <DescriptorNode Key="Interface847"> <Value d6p1:type="InterfaceGeneralDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ALTERNATE</bDescriptorType> <bLength>0</bLength> <DisplayName>CDC Interface 1</DisplayName> </Value> <Nodes> <DescriptorNode Key="USBDescriptor848"> <Value d8p1:type="CyCommunicationsInterfaceDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>INTERFACE</bDescriptorType> <bLength>9</bLength> <iwInterface>9</iwInterface> <bInterfaceClass>2</bInterfaceClass> <bAlternateSetting>0</bAlternateSetting> <bInterfaceNumber>0</bInterfaceNumber> <bNumEndpoints>1</bNumEndpoints> <bInterfaceSubClass>2</bInterfaceSubClass> <bInterfaceProtocol>0</bInterfaceProtocol> <iInterface>2</iInterface> <sInterface>CDC Communication Interface</sInterface> </Value> <Nodes> <DescriptorNode Key="USBDescriptor850"> <Value d10p1:type="CyCDCHeaderDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>CDC</bDescriptorType> <bLength>5</bLength> <bDescriptorSubtype>HEADER</bDescriptorSubtype> <bcdADC>272</bcdADC> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor851"> <Value d10p1:type="CyCDCAbstractControlMgmtDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>CDC</bDescriptorType> <bLength>4</bLength> <bDescriptorSubtype>ABSTRACT_CONTROL_MANAGEMENT</bDescriptorSubtype> <bmCapabilities>2</bmCapabilities> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor852"> <Value d10p1:type="CyCDCUnionDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>CDC</bDescriptorType> <bLength>5</bLength> <bDescriptorSubtype>UNION</bDescriptorSubtype> <bControlInterface>0</bControlInterface> <bSubordinateInterface>AQ==</bSubordinateInterface> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor853"> <Value d10p1:type="CyCDCCallManagementDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>CDC</bDescriptorType> <bLength>5</bLength> <bDescriptorSubtype>CALL_MANAGEMENT</bDescriptorSubtype> <bmCapabilities>0</bmCapabilities> <bDataInterface>1</bDataInterface> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor854"> <Value d10p1:type="EndpointDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ENDPOINT</bDescriptorType> <bLength>7</bLength> <DoubleBuffer>false</DoubleBuffer> <bInterval>10</bInterval> <bEndpointAddress>129</bEndpointAddress> <bmAttributes>3</bmAttributes> <wMaxPacketSize>8</wMaxPacketSize> </Value> <Nodes /> </DescriptorNode> </Nodes> </DescriptorNode> </Nodes> </DescriptorNode> <DescriptorNode Key="Interface855"> <Value d6p1:type="InterfaceGeneralDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ALTERNATE</bDescriptorType> <bLength>0</bLength> <DisplayName>CDC Interface 2</DisplayName> </Value> <Nodes> <DescriptorNode Key="USBDescriptor856"> <Value d8p1:type="CyDataInterfaceDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>INTERFACE</bDescriptorType> <bLength>9</bLength> <iwInterface>612</iwInterface> <bInterfaceClass>10</bInterfaceClass> <bAlternateSetting>0</bAlternateSetting> <bInterfaceNumber>1</bInterfaceNumber> <bNumEndpoints>2</bNumEndpoints> <bInterfaceSubClass>0</bInterfaceSubClass> <bInterfaceProtocol>0</bInterfaceProtocol> <iInterface>3</iInterface> <sInterface>CDC Data Interface</sInterface> </Value> <Nodes> <DescriptorNode Key="USBDescriptor858"> <Value d10p1:type="EndpointDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ENDPOINT</bDescriptorType> <bLength>7</bLength> <DoubleBuffer>false</DoubleBuffer> <bInterval>10</bInterval> <bEndpointAddress>130</bEndpointAddress> <bmAttributes>2</bmAttributes> <wMaxPacketSize>64</wMaxPacketSize> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor859"> <Value d10p1:type="EndpointDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ENDPOINT</bDescriptorType> <bLength>7</bLength> <DoubleBuffer>false</DoubleBuffer> <bInterval>10</bInterval> <bEndpointAddress>3</bEndpointAddress> <bmAttributes>2</bmAttributes> <wMaxPacketSize>64</wMaxPacketSize> </Value> <Nodes /> </DescriptorNode> </Nodes> </DescriptorNode> </Nodes> </DescriptorNode> </Nodes> </DescriptorNode> </Tree_x0020_Descriptors> </Tree>, DeviceDescriptors=<?xml version="1.0" encoding="utf-16"?> <Tree xmlns:CustomizerVersion="2_0"> <Tree_x0020_Descriptors> <DescriptorNode Key="Device"> <Nodes> <DescriptorNode Key="USBDescriptor838"> <Value d6p1:type="DeviceDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>DEVICE</bDescriptorType> <bLength>18</bLength> <iwManufacturer>7</iwManufacturer> <iwProduct>613</iwProduct> <sManufacturer>Cypress Semiconductor</sManufacturer> <sProduct>USBUART</sProduct> <sSerialNumber /> <bDeviceClass>2</bDeviceClass> <bDeviceSubClass>0</bDeviceSubClass> <bDeviceProtocol>0</bDeviceProtocol> <bMaxPacketSize0>0</bMaxPacketSize0> <idVendor>1204</idVendor> <idProduct>62002</idProduct> <bcdDevice>1</bcdDevice> <iManufacturer>1</iManufacturer> <iProduct>4</iProduct> <iSerialNumber>0</iSerialNumber> <bNumConfigurations>1</bNumConfigurations> <bMemoryMgmt>0</bMemoryMgmt> <bMemoryAlloc>0</bMemoryAlloc> </Value> <Nodes> <DescriptorNode Key="USBDescriptor843"> <Value d8p1:type="ConfigDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>CONFIGURATION</bDescriptorType> <bLength>9</bLength> <iwConfiguration>7</iwConfiguration> <sConfiguration>Cypress Semiconductor</sConfiguration> <wTotalLength>67</wTotalLength> <bNumInterfaces>2</bNumInterfaces> <bConfigurationValue>0</bConfigurationValue> <iConfiguration>1</iConfiguration> <bmAttributes>192</bmAttributes> <bMaxPower>50</bMaxPower> </Value> <Nodes> <DescriptorNode Key="Interface847"> <Value d10p1:type="InterfaceGeneralDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ALTERNATE</bDescriptorType> <bLength>0</bLength> <DisplayName>CDC Interface 1</DisplayName> </Value> <Nodes> <DescriptorNode Key="USBDescriptor848"> <Value d12p1:type="CyCommunicationsInterfaceDescriptor" xmlns:d12p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>INTERFACE</bDescriptorType> <bLength>9</bLength> <iwInterface>9</iwInterface> <bInterfaceClass>2</bInterfaceClass> <bAlternateSetting>0</bAlternateSetting> <bInterfaceNumber>0</bInterfaceNumber> <bNumEndpoints>1</bNumEndpoints> <bInterfaceSubClass>2</bInterfaceSubClass> <bInterfaceProtocol>0</bInterfaceProtocol> <iInterface>2</iInterface> <sInterface>CDC Communication Interface</sInterface> </Value> <Nodes> <DescriptorNode Key="USBDescriptor850"> <Value d14p1:type="CyCDCHeaderDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>CDC</bDescriptorType> <bLength>5</bLength> <bDescriptorSubtype>HEADER</bDescriptorSubtype> <bcdADC>272</bcdADC> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor851"> <Value d14p1:type="CyCDCAbstractControlMgmtDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>CDC</bDescriptorType> <bLength>4</bLength> <bDescriptorSubtype>ABSTRACT_CONTROL_MANAGEMENT</bDescriptorSubtype> <bmCapabilities>2</bmCapabilities> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor852"> <Value d14p1:type="CyCDCUnionDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>CDC</bDescriptorType> <bLength>5</bLength> <bDescriptorSubtype>UNION</bDescriptorSubtype> <bControlInterface>0</bControlInterface> <bSubordinateInterface>AQ==</bSubordinateInterface> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor853"> <Value d14p1:type="CyCDCCallManagementDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>CDC</bDescriptorType> <bLength>5</bLength> <bDescriptorSubtype>CALL_MANAGEMENT</bDescriptorSubtype> <bmCapabilities>0</bmCapabilities> <bDataInterface>1</bDataInterface> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor854"> <Value d14p1:type="EndpointDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ENDPOINT</bDescriptorType> <bLength>7</bLength> <DoubleBuffer>false</DoubleBuffer> <bInterval>10</bInterval> <bEndpointAddress>129</bEndpointAddress> <bmAttributes>3</bmAttributes> <wMaxPacketSize>8</wMaxPacketSize> </Value> <Nodes /> </DescriptorNode> </Nodes> </DescriptorNode> </Nodes> </DescriptorNode> <DescriptorNode Key="Interface855"> <Value d10p1:type="InterfaceGeneralDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ALTERNATE</bDescriptorType> <bLength>0</bLength> <DisplayName>CDC Interface 2</DisplayName> </Value> <Nodes> <DescriptorNode Key="USBDescriptor856"> <Value d12p1:type="CyDataInterfaceDescriptor" xmlns:d12p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>INTERFACE</bDescriptorType> <bLength>9</bLength> <iwInterface>612</iwInterface> <bInterfaceClass>10</bInterfaceClass> <bAlternateSetting>0</bAlternateSetting> <bInterfaceNumber>1</bInterfaceNumber> <bNumEndpoints>2</bNumEndpoints> <bInterfaceSubClass>0</bInterfaceSubClass> <bInterfaceProtocol>0</bInterfaceProtocol> <iInterface>3</iInterface> <sInterface>CDC Data Interface</sInterface> </Value> <Nodes> <DescriptorNode Key="USBDescriptor858"> <Value d14p1:type="EndpointDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ENDPOINT</bDescriptorType> <bLength>7</bLength> <DoubleBuffer>false</DoubleBuffer> <bInterval>10</bInterval> <bEndpointAddress>130</bEndpointAddress> <bmAttributes>2</bmAttributes> <wMaxPacketSize>64</wMaxPacketSize> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor859"> <Value d14p1:type="EndpointDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ENDPOINT</bDescriptorType> <bLength>7</bLength> <DoubleBuffer>false</DoubleBuffer> <bInterval>10</bInterval> <bEndpointAddress>3</bEndpointAddress> <bmAttributes>2</bmAttributes> <wMaxPacketSize>64</wMaxPacketSize> </Value> <Nodes /> </DescriptorNode> </Nodes> </DescriptorNode> </Nodes> </DescriptorNode> </Nodes> </DescriptorNode> </Nodes> </DescriptorNode> </Nodes> </DescriptorNode> </Tree_x0020_Descriptors> </Tree>, EnableCDCApi=true, EnableMidiApi=true, endpointMA=0, endpointMM=0, epDMAautoOptimization=false, extern_cls=false, extern_vbus=false, extern_vnd=false, extJackCount=0, HIDReportDescriptors=<?xml version="1.0" encoding="utf-16"?> <Tree xmlns:CustomizerVersion="2_0"> <Tree_x0020_Descriptors> <DescriptorNode Key="HIDReport"> <Nodes> <DescriptorNode Key="USBDescriptor761"> <Value d6p1:type="HIDReportDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT</bDescriptorType> <bLength>2</bLength> <Name>3-Button Mouse</Name> <wLength>50</wLength> </Value> <Nodes> <DescriptorNode Key="USBDescriptor762"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="4" Size="1" Type="USAGE_PAGE"> <Value> <unsignedByte>5</unsignedByte> <unsignedByte>1</unsignedByte> </Value> <Kind>List</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor763"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="8" Size="1" Type="USAGE"> <Value> <unsignedByte>9</unsignedByte> <unsignedByte>2</unsignedByte> </Value> <Kind>List</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor764"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="160" Size="1" Type="COLLECTION"> <Value> <unsignedByte>161</unsignedByte> <unsignedByte>1</unsignedByte> </Value> <Kind>List</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor765"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="8" Size="1" Type="USAGE"> <Value> <unsignedByte>9</unsignedByte> <unsignedByte>1</unsignedByte> </Value> <Kind>List</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor766"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="160" Size="1" Type="COLLECTION"> <Value> <unsignedByte>161</unsignedByte> <unsignedByte>0</unsignedByte> </Value> <Kind>List</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor767"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="4" Size="1" Type="USAGE_PAGE"> <Value> <unsignedByte>5</unsignedByte> <unsignedByte>9</unsignedByte> </Value> <Kind>List</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor768"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="24" Size="1" Type="USAGE_MINIMUM"> <Value> <unsignedByte>25</unsignedByte> <unsignedByte>1</unsignedByte> </Value> <Kind>Int</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor769"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="40" Size="1" Type="USAGE_MAXIMUM"> <Value> <unsignedByte>41</unsignedByte> <unsignedByte>3</unsignedByte> </Value> <Kind>Int</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor770"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="20" Size="1" Type="LOGICAL_MINIMUM"> <Value> <unsignedByte>21</unsignedByte> <unsignedByte>0</unsignedByte> </Value> <Kind>Int</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor771"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="36" Size="1" Type="LOGICAL_MAXIMUM"> <Value> <unsignedByte>37</unsignedByte> <unsignedByte>1</unsignedByte> </Value> <Kind>Int</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor772"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="148" Size="1" Type="REPORT_COUNT"> <Value> <unsignedByte>149</unsignedByte> <unsignedByte>3</unsignedByte> </Value> <Kind>Int</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor773"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="116" Size="1" Type="REPORT_SIZE"> <Value> <unsignedByte>117</unsignedByte> <unsignedByte>1</unsignedByte> </Value> <Kind>Int</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor774"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="128" Size="1" Type="INPUT"> <Value> <unsignedByte>129</unsignedByte> <unsignedByte>2</unsignedByte> </Value> <Kind>Bits</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor775"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="148" Size="1" Type="REPORT_COUNT"> <Value> <unsignedByte>149</unsignedByte> <unsignedByte>1</unsignedByte> </Value> <Kind>Int</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor776"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="116" Size="1" Type="REPORT_SIZE"> <Value> <unsignedByte>117</unsignedByte> <unsignedByte>5</unsignedByte> </Value> <Kind>Int</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor777"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="128" Size="1" Type="INPUT"> <Value> <unsignedByte>129</unsignedByte> <unsignedByte>1</unsignedByte> </Value> <Kind>Bits</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor778"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="4" Size="1" Type="USAGE_PAGE"> <Value> <unsignedByte>5</unsignedByte> <unsignedByte>1</unsignedByte> </Value> <Kind>List</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor779"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="8" Size="1" Type="USAGE"> <Value> <unsignedByte>9</unsignedByte> <unsignedByte>48</unsignedByte> </Value> <Kind>List</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor780"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="8" Size="1" Type="USAGE"> <Value> <unsignedByte>9</unsignedByte> <unsignedByte>49</unsignedByte> </Value> <Kind>List</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor781"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="20" Size="1" Type="LOGICAL_MINIMUM"> <Value> <unsignedByte>21</unsignedByte> <unsignedByte>129</unsignedByte> <unsignedByte>0</unsignedByte> </Value> <Kind>Int</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor782"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="36" Size="1" Type="LOGICAL_MAXIMUM"> <Value> <unsignedByte>37</unsignedByte> <unsignedByte>127</unsignedByte> </Value> <Kind>Int</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor783"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="116" Size="1" Type="REPORT_SIZE"> <Value> <unsignedByte>117</unsignedByte> <unsignedByte>8</unsignedByte> </Value> <Kind>Int</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor784"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="148" Size="1" Type="REPORT_COUNT"> <Value> <unsignedByte>149</unsignedByte> <unsignedByte>2</unsignedByte> </Value> <Kind>Int</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor785"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="128" Size="1" Type="INPUT"> <Value> <unsignedByte>129</unsignedByte> <unsignedByte>6</unsignedByte> </Value> <Kind>Bits</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor786"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="192" Size="0" Type="END_COLLECTION"> <Value> <unsignedByte>192</unsignedByte> <unsignedByte>0</unsignedByte> </Value> <Kind>None</Kind> </Item> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor787"> <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>HID_REPORT_ITEM</bDescriptorType> <bLength>1</bLength> <Item Code="192" Size="0" Type="END_COLLECTION"> <Value> <unsignedByte>192</unsignedByte> <unsignedByte>0</unsignedByte> </Value> <Kind>None</Kind> </Item> </Value> <Nodes /> </DescriptorNode> </Nodes> </DescriptorNode> </Nodes> </DescriptorNode> </Tree_x0020_Descriptors> </Tree>, max_interfaces_num=2, MidiDescriptors=, Mode=false, mon_vbus=false, out_sof=false, Pid=F232, rm_arb_int=false, rm_dma_1=true, rm_dma_2=true, rm_dma_3=true, rm_dma_4=true, rm_dma_5=true, rm_dma_6=true, rm_dma_7=true, rm_dma_8=true, rm_dp_int=false, rm_ep_isr_0=false, rm_ep_isr_1=false, rm_ep_isr_2=false, rm_ep_isr_3=false, rm_ep_isr_4=true, rm_ep_isr_5=true, rm_ep_isr_6=true, rm_ep_isr_7=true, rm_ep_isr_8=true, rm_ord_int=false, rm_sof_int=false, rm_usb_int=false, StringDescriptors=<?xml version="1.0" encoding="utf-16"?> <Tree xmlns:CustomizerVersion="2_0"> <Tree_x0020_Descriptors> <DescriptorNode Key="String"> <Nodes> <DescriptorNode Key="LANGID"> <Value d6p1:type="StringZeroDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>STRING</bDescriptorType> <bLength>4</bLength> <wLANGID>1033</wLANGID> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor7"> <Value d6p1:type="StringDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>STRING</bDescriptorType> <bLength>44</bLength> <snType>USER_ENTERED_TEXT</snType> <bString>Cypress Semiconductor</bString> <bUsed>true</bUsed> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor9"> <Value d6p1:type="StringDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>STRING</bDescriptorType> <bLength>56</bLength> <snType>USER_ENTERED_TEXT</snType> <bString>CDC Communication Interface</bString> <bUsed>true</bUsed> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor612"> <Value d6p1:type="StringDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>STRING</bDescriptorType> <bLength>38</bLength> <snType>USER_ENTERED_TEXT</snType> <bString>CDC Data Interface</bString> <bUsed>false</bUsed> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor613"> <Value d6p1:type="StringDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>STRING</bDescriptorType> <bLength>16</bLength> <snType>USER_ENTERED_TEXT</snType> <bString>USBUART</bString> <bUsed>false</bUsed> </Value> <Nodes /> </DescriptorNode> </Nodes> </DescriptorNode> <DescriptorNode Key="SpecialString"> <Nodes> <DescriptorNode Key="Serial"> <Value d6p1:type="StringDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>STRING</bDescriptorType> <bLength>2</bLength> <snType>SILICON_NUMBER</snType> <bString /> <bUsed>true</bUsed> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="EE"> <Value d6p1:type="StringDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>STRING</bDescriptorType> <bLength>16</bLength> <snType>USER_ENTERED_TEXT</snType> <bString>MSFT100</bString> <bUsed>true</bUsed> </Value> <Nodes /> </DescriptorNode> </Nodes> </DescriptorNode> </Tree_x0020_Descriptors> </Tree>, Vid=04B4, CY_COMPONENT_NAME=USBFS_v2_70, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=USBUART_1, CY_INSTANCE_SHORT_NAME=USBUART_1, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=70, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=USBUART_1, )
module USBFS_v2_70_0 (
sof,
vbusdet);
output sof;
input vbusdet;
parameter epDMAautoOptimization = 0;
wire Net_1785;
wire Net_1771;
wire Net_1754;
wire Net_1753;
wire [8:0] ept_int;
wire Net_1583;
wire Net_1582;
wire Net_1568;
wire Net_1561;
wire Net_1499;
wire Net_1494;
wire [7:0] dma_req;
wire [7:0] Net_1649;
wire Net_1648;
wire Net_1647;
wire Net_1646;
wire Net_1645;
wire Net_1643;
wire Net_1642;
wire Net_1730;
wire Net_1775;
wire Net_1599;
wire Net_1719;
wire Net_1718;
wire Net_1717;
wire Net_1716;
wire Net_1777;
wire [7:0] dma_nrq;
wire Net_1715;
wire Net_1714;
wire Net_1713;
wire Net_1712;
wire [7:0] Net_1208;
wire Net_1207;
wire Net_1206;
wire Net_1205;
wire Net_1204;
wire Net_1203;
wire Net_1201;
wire Net_1200;
wire Net_1199;
wire Net_1269;
wire Net_1202;
wire Net_1768;
wire Net_1591;
wire [7:0] dma_nrq_sync;
wire Net_1588;
wire Net_1522;
wire Net_1579;
wire Net_1576;
wire Net_1567;
wire Net_1559;
wire Net_1498;
wire Net_1495;
wire Net_1010;
electrical Net_1000;
wire Net_824;
electrical Net_597;
wire Net_95;
wire Net_81;
wire Net_79;
cy_clock_v1_0
#(.id("c39ef993-d787-4c0c-8ad6-c0c81f866442/03f503a7-085a-4304-b786-de885b1c2f21"),
.source_clock_id("75C2148C-3656-4d8a-846D-0CAE99AB6FF7"),
.divisor(0),
.period("0"),
.is_direct(1),
.is_digital(1))
Clock_vbus
(.clock_out(Net_1202));
cy_isr_v1_0
#(.int_type(2'b10))
dp_int
(.int_signal(Net_1010));
wire [0:0] tmpOE__Dm_net;
wire [0:0] tmpFB_0__Dm_net;
wire [0:0] tmpIO_0__Dm_net;
wire [0:0] tmpINTERRUPT_0__Dm_net;
electrical [0:0] tmpSIOVREF__Dm_net;
cy_psoc3_pins_v1_10
#(.id("c39ef993-d787-4c0c-8ad6-c0c81f866442/8b77a6c4-10a0-4390-971c-672353e2a49c"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("NONCONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("A"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(1),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
Dm
(.oe(tmpOE__Dm_net),
.y({1'b0}),
.fb({tmpFB_0__Dm_net[0:0]}),
.analog({Net_597}),
.io({tmpIO_0__Dm_net[0:0]}),
.siovref(tmpSIOVREF__Dm_net),
.interrupt({tmpINTERRUPT_0__Dm_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Dm_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Dp_net;
wire [0:0] tmpFB_0__Dp_net;
wire [0:0] tmpIO_0__Dp_net;
electrical [0:0] tmpSIOVREF__Dp_net;
cy_psoc3_pins_v1_10
#(.id("c39ef993-d787-4c0c-8ad6-c0c81f866442/618a72fc-5ddd-4df5-958f-a3d55102db42"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b10),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
Dp
(.oe(tmpOE__Dp_net),
.y({1'b0}),
.fb({tmpFB_0__Dp_net[0:0]}),
.analog({Net_1000}),
.io({tmpIO_0__Dp_net[0:0]}),
.siovref(tmpSIOVREF__Dp_net),
.interrupt({Net_1010}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Dp_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_psoc3_usb_v1_0 USB (
.dp(Net_1000),
.dm(Net_597),
.sof_int(sof),
.arb_int(Net_79),
.usb_int(Net_81),
.ept_int(ept_int[8:0]),
.ord_int(Net_95),
.dma_req(dma_req[7:0]),
.dma_termin(Net_824));
cy_isr_v1_0
#(.int_type(2'b10))
ord_int
(.int_signal(Net_95));
cy_isr_v1_0
#(.int_type(2'b10))
ep_3
(.int_signal(ept_int[3:3]));
cy_isr_v1_0
#(.int_type(2'b10))
ep_2
(.int_signal(ept_int[2:2]));
cy_isr_v1_0
#(.int_type(2'b10))
ep_1
(.int_signal(ept_int[1:1]));
cy_isr_v1_0
#(.int_type(2'b10))
ep_0
(.int_signal(ept_int[0:0]));
cy_isr_v1_0
#(.int_type(2'b10))
bus_reset
(.int_signal(Net_81));
cy_isr_v1_0
#(.int_type(2'b10))
arb_int
(.int_signal(Net_79));
cy_isr_v1_0
#(.int_type(2'b10))
sof_int
(.int_signal(sof));
// VirtualMux_1 (cy_virtualmux_v1_0)
assign dma_nrq[0] = Net_1494;
ZeroTerminal ZeroTerminal_1 (
.z(Net_1494));
// VirtualMux_2 (cy_virtualmux_v1_0)
assign dma_nrq[1] = Net_1499;
ZeroTerminal ZeroTerminal_2 (
.z(Net_1499));
// VirtualMux_3 (cy_virtualmux_v1_0)
assign dma_nrq[2] = Net_1561;
ZeroTerminal ZeroTerminal_3 (
.z(Net_1561));
// VirtualMux_4 (cy_virtualmux_v1_0)
assign dma_nrq[3] = Net_1568;
ZeroTerminal ZeroTerminal_4 (
.z(Net_1568));
// VirtualMux_5 (cy_virtualmux_v1_0)
assign dma_nrq[4] = Net_1582;
// VirtualMux_6 (cy_virtualmux_v1_0)
assign dma_nrq[5] = Net_1583;
ZeroTerminal ZeroTerminal_5 (
.z(Net_1582));
ZeroTerminal ZeroTerminal_6 (
.z(Net_1583));
// VirtualMux_7 (cy_virtualmux_v1_0)
assign dma_nrq[6] = Net_1753;
// VirtualMux_8 (cy_virtualmux_v1_0)
assign dma_nrq[7] = Net_1754;
ZeroTerminal ZeroTerminal_7 (
.z(Net_1753));
ZeroTerminal ZeroTerminal_8 (
.z(Net_1754));
endmodule
// CharLCD_v2_0(ConversionRoutines=true, CUSTOM0=0,E,8,8,8,E,0, CUSTOM1=0,A,A,4,4,4,0, CUSTOM2=0,E,A,E,8,8,0, CUSTOM3=0,E,A,C,A,A,0, CUSTOM4=0,E,8,C,8,E,0, CUSTOM5=0,E,8,E,2,E,0, CUSTOM6=0,E,8,E,2,E,0, CUSTOM7=0,4,4,4,0,4,0, CustomCharacterSet=0, TypeReplacementString=uint8, CY_COMPONENT_NAME=CharLCD_v2_0, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=LCD, CY_INSTANCE_SHORT_NAME=LCD, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=LCD, )
module CharLCD_v2_0_1 ;
wire [6:0] tmpOE__LCDPort_net;
wire [6:0] tmpFB_6__LCDPort_net;
wire [6:0] tmpIO_6__LCDPort_net;
wire [0:0] tmpINTERRUPT_0__LCDPort_net;
electrical [0:0] tmpSIOVREF__LCDPort_net;
cy_psoc3_pins_v1_10
#(.id("ac8fb70c-7191-4547-91f8-16d96c1410fe/ed092b9b-d398-4703-be89-cebf998501f6"),
.drive_mode(21'b110_110_110_110_110_110_110),
.ibuf_enabled(7'b1_1_1_1_1_1_1),
.init_dr_st(7'b0_0_0_0_0_0_0),
.input_clk_en(0),
.input_sync(7'b1_1_1_1_1_1_1),
.input_sync_mode(7'b0_0_0_0_0_0_0),
.intr_mode(14'b00_00_00_00_00_00_00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(",,,,,,"),
.layout_mode("CONTIGUOUS"),
.oe_conn(7'b0_0_0_0_0_0_0),
.oe_reset(0),
.oe_sync(7'b0_0_0_0_0_0_0),
.output_clk_en(0),
.output_clock_mode(7'b0_0_0_0_0_0_0),
.output_conn(7'b0_0_0_0_0_0_0),
.output_mode(7'b0_0_0_0_0_0_0),
.output_reset(0),
.output_sync(7'b0_0_0_0_0_0_0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(",,,,,,"),
.pin_mode("OOOOOOO"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(7'b0_0_0_0_0_0_0),
.sio_ibuf(""),
.sio_info(14'b00_00_00_00_00_00_00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(7'b0_0_0_0_0_0_0),
.spanning(0),
.use_annotation(7'b0_0_0_0_0_0_0),
.vtrip(14'b10_10_10_10_10_10_10),
.width(7))
LCDPort
(.oe(tmpOE__LCDPort_net),
.y({7'b0}),
.fb({tmpFB_6__LCDPort_net[6:0]}),
.io({tmpIO_6__LCDPort_net[6:0]}),
.siovref(tmpSIOVREF__LCDPort_net),
.interrupt({tmpINTERRUPT_0__LCDPort_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__LCDPort_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{7'b1111111} : {7'b1111111};
endmodule
// top
module top ;
wire Net_60;
wire Net_55;
USBFS_v2_70_0 USBUART_1 (
.sof(Net_55),
.vbusdet(1'b0));
defparam USBUART_1.epDMAautoOptimization = 0;
CharLCD_v2_0_1 LCD ();
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:30:38 03/19/2013
// Design Name:
// Module Name: vga640x480
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga640x480(
input wire pix_en, //pixel clock: 25MHz
input wire clk, //100MHz
input wire rst, //asynchronous reset,
input wire [8:0] o_vec,
input wire [8:0] x_vec,
input wire [2:0] game_status,
output wire hsync, //horizontal sync out
output wire vsync, //vertical sync out
output reg [2:0] red, //red vga output
output reg [2:0] green, //green vga output
output reg [1:0] blue //blue vga output
);
// video structure constants
parameter [9:0] hpixels = 800;// horizontal pixels per line
parameter [9:0] vlines = 521; // vertical lines per frame
parameter [9:0] hpulse = 96; // hsync pulse length
parameter [9:0] vpulse = 2; // vsync pulse length
parameter [9:0] hbp = 144; // end of horizontal back porch
parameter [9:0] hfp = 784; // beginning of horizontal front porch
parameter [9:0] vbp = 31; // end of vertical back porch
parameter [9:0] vfp = 511; // beginning of vertical front porch
// active horizontal video is therefore: 784 - 144 = 640
// active vertical video is therefore: 511 - 31 = 480
// registers for storing the horizontal & vertical counters
reg [9:0] hc;
reg [9:0] vc;
// Horizontal & vertical counters --
// this is how we keep track of where we are on the screen.
// ------------------------
// Sequential "always block", which is a block that is
// only triggered on signal transitions or "edges".
// posedge = rising edge & negedge = falling edge
// Assignment statements can only be used on type "reg" and need to be of the "non-blocking" type: <=
always @(posedge clk)
begin
// reset condition
if (rst == 1)
begin
hc <= 0;
vc <= 0;
end
else if (pix_en == 1)
begin
// keep counting until the end of the line
if (hc < hpixels - 1)
hc <= hc + 1;
else
// When we hit the end of the line, reset the horizontal
// counter and increment the vertical counter.
// If vertical counter is at the end of the frame, then
// reset that one too.
begin
hc <= 0;
if (vc < vlines - 1)
vc <= vc + 1;
else
vc <= 0;
end
end
end
// generate sync pulses (active low)
// ----------------
// "assign" statements are a quick way to
// give values to variables of type: wire
assign hsync = (hc < hpulse) ? 0:1;
assign vsync = (vc < vpulse) ? 0:1;
parameter [9:0] line_thickness = 2;
parameter [9:0] tile_offset = 10;
parameter [9:0] tile_width = 50;
parameter [9:0] radius = 15;
parameter [9:0] circle_thickness = 2;
//parameter [9:0] o_vec = 9'b111111111;
//parameter [9:0] x_vec = 9'b000000000;
reg [50:0] x_arr [50:0];//INDEX {..., 1, 0}. Note that 50 should be equal to tile_width
reg [50:0] y_arr [50:0];//INDEX {..., 1, 0}. Note that 50 should be equal to tile_width
parameter [2500:0] o_pic = {
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000001111111111100000000000000000000},
{50'b00000000000000001111111111111111100000000000000000},
{50'b00000000000000011111111111111111110000000000000000},
{50'b00000000000001111110000000000011111100000000000000},
{50'b00000000000011111000000000000000111110000000000000},
{50'b00000000000111100000000000000000001111000000000000},
{50'b00000000001111000000000000000000000111100000000000},
{50'b00000000001110000000000000000000000011100000000000},
{50'b00000000011100000000000000000000000001110000000000},
{50'b00000000111100000000000000000000000001111000000000},
{50'b00000000111000000000000000000000000000111000000000},
{50'b00000000111000000000000000000000000000111000000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000000111000000000000000000000000000111000000000},
{50'b00000000111000000000000000000000000000111000000000},
{50'b00000000111100000000000000000000000001111000000000},
{50'b00000000011100000000000000000000000001110000000000},
{50'b00000000001110000000000000000000000011100000000000},
{50'b00000000001111000000000000000000000111100000000000},
{50'b00000000000111100000000000000000001111000000000000},
{50'b00000000000011111000000000000000111110000000000000},
{50'b00000000000001111110000000000011111100000000000000},
{50'b00000000000000011111111111111111110000000000000000},
{50'b00000000000000001111111111111111100000000000000000},
{50'b00000000000000000001111111111100000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000}
};
parameter [2500:0] x_pic = {
{50'b00000000000000000000000000000000000000000000000000},
{50'b01110000000000000000000000000000000000000000000111},
{50'b00111000000000000000000000000000000000000000001110},
{50'b00011100000000000000000000000000000000000000011100},
{50'b00001110000000000000000000000000000000000000111000},
{50'b00000111000000000000000000000000000000000001110000},
{50'b00000011100000000000000000000000000000000011100000},
{50'b00000001110000000000000000000000000000000111000000},
{50'b00000000111000000000000000000000000000001110000000},
{50'b00000000011100000000000000000000000000011100000000},
{50'b00000000001110000000000000000000000000111000000000},
{50'b00000000000111000000000000000000000001110000000000},
{50'b00000000000011100000000000000000000011100000000000},
{50'b00000000000001110000000000000000000111000000000000},
{50'b00000000000000111000000000000000001110000000000000},
{50'b00000000000000011100000000000000011100000000000000},
{50'b00000000000000001110000000000000111000000000000000},
{50'b00000000000000000111000000000001110000000000000000},
{50'b00000000000000000011100000000011100000000000000000},
{50'b00000000000000000001110000000111000000000000000000},
{50'b00000000000000000000111000001110000000000000000000},
{50'b00000000000000000000011100011100000000000000000000},
{50'b00000000000000000000001110111000000000000000000000},
{50'b00000000000000000000000111110000000000000000000000},
{50'b00000000000000000000000011100000000000000000000000},
{50'b00000000000000000000000111110000000000000000000000},
{50'b00000000000000000000001110111000000000000000000000},
{50'b00000000000000000000011100011100000000000000000000},
{50'b00000000000000000000111000001110000000000000000000},
{50'b00000000000000000001110000000111000000000000000000},
{50'b00000000000000000011100000000011100000000000000000},
{50'b00000000000000000111000000000001110000000000000000},
{50'b00000000000000001110000000000000111000000000000000},
{50'b00000000000000011100000000000000011100000000000000},
{50'b00000000000000111000000000000000001110000000000000},
{50'b00000000000001110000000000000000000111000000000000},
{50'b00000000000011100000000000000000000011100000000000},
{50'b00000000000111000000000000000000000001110000000000},
{50'b00000000001110000000000000000000000000111000000000},
{50'b00000000011100000000000000000000000000011100000000},
{50'b00000000111000000000000000000000000000001110000000},
{50'b00000001110000000000000000000000000000000111000000},
{50'b00000011100000000000000000000000000000000011100000},
{50'b00000111000000000000000000000000000000000001110000},
{50'b00001110000000000000000000000000000000000000111000},
{50'b00011100000000000000000000000000000000000000011100},
{50'b00111000000000000000000000000000000000000000001110},
{50'b01110000000000000000000000000000000000000000000111},
{50'b01100000000000000000000000000000000000000000000011},
{50'b01000000000000000000000000000000000000000000000001}
};
// display 100% saturation colorbars
// ------------------------
// Combinational "always block", which is a block that is
// triggered when anything in the "sensitivity list" changes.
// The asterisk implies that everything that is capable of triggering the block
// is automatically included in the sensitivty list. In this case, it would be
// equivalent to the following: always @(hc, vc)
// Assignment statements can only be used on type "reg" and should be of the "blocking" type: =
always @(*)
begin
// first check if we're within vertical active video range
if (vc >= vbp && vc < vfp)
begin
// Tic-Tac-Toe Lines
if ( (hc >= (hbp + tile_offset + tile_width) && hc < (hbp + tile_offset + tile_width + line_thickness)
&& vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + 3*tile_width + 2*line_thickness))
|| (hc >= (hbp + tile_offset + tile_width*2 + line_thickness) && hc < (hbp + tile_offset + tile_width*2 + line_thickness*2)
&& vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + 3*tile_width + 2*line_thickness))
|| (vc >= (vbp + tile_offset + tile_width*2 + line_thickness) && vc < (vbp + tile_offset + tile_width*2 + line_thickness*2)
&& hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + 3*tile_width + 2*line_thickness))
|| (vc >= (vbp + tile_offset + tile_width) && vc < (vbp + tile_offset + tile_width + line_thickness)
&& hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + 3*tile_width + 2*line_thickness)))
begin
red = 3'b010;
green = 3'b100;
blue = 2'b11;
end
// Tile Blocks
// 0 | 1 | 2
// 3 | 4 | 5
// 6 | 7 | 8
// Begin Row 1
else if ( (hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + tile_width))
&& (vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + tile_width)))
begin // Tile 0
if (o_vec[0])
begin
if (o_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b00;
end
end
else if (x_vec[0])
begin
if (x_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b00;
end
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness + tile_width) && hc < (hbp + tile_offset + tile_width*2 + line_thickness))
&& (vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + tile_width)))
begin //Tile 1
if (o_vec[1])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b00;
end
end
else if (x_vec[1])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b00;
end
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness*2 + tile_width*2) && hc < (hbp + tile_offset + tile_width*3 + line_thickness*2))
&& (vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + tile_width)))
begin // Tile 2
if (o_vec[2])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness*2) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b000;
blue = 2'b11;
end
end
else if (x_vec[2])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness*2) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b000;
blue = 2'b11;
end
end
else
begin
red = 3'b000;
green = 3'b000;
blue = 2'b11;
end
end
// Begin Row 2
else if ( (hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + tile_width))
&& (vc >= (vbp + tile_offset + line_thickness + tile_width) && vc < (vbp + tile_offset + tile_width*2 + line_thickness)))
begin // Tile 3
if (o_vec[3])
begin
if (o_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b111;
blue = 2'b00;
end
end
else if (x_vec[3])
begin
if (x_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b111;
blue = 2'b00;
end
end
else
begin
red = 3'b111;
green = 3'b111;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness + tile_width) && hc < (hbp + tile_offset + tile_width*2 + line_thickness))
&& (vc >= (vbp + tile_offset + line_thickness + tile_width) && vc < (vbp + tile_offset + tile_width*2 + line_thickness)))
begin // Tile 4
if (o_vec[4])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b11;
end
end
else if (x_vec[4])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b11;
end
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b11;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness*2 + tile_width*2) && hc < (hbp + tile_offset + tile_width*3 + line_thickness*2))
&& (vc >= (vbp + tile_offset + line_thickness + tile_width) && vc < (vbp + tile_offset + tile_width*2 + line_thickness)))
begin // Tile 5
if (o_vec[5])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness*2) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b11;
end
end
else if (x_vec[5])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness*2) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b11;
end
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b11;
end
end
// Begin Row 3
else if ( (hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + tile_width))
&& (vc >= (vbp + tile_offset + line_thickness*2 + tile_width*2) && vc < (vbp + tile_offset + tile_width*3 + line_thickness*2)))
begin // Tile 6
if (o_vec[6])
begin
if (o_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness * 2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b010;
green = 3'b000;
blue = 2'b00;
end
end
else if (x_vec[6])
begin
if (x_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness * 2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b010;
green = 3'b000;
blue = 2'b00;
end
end
else
begin
red = 3'b010;
green = 3'b000;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness + tile_width) && hc < (hbp + tile_offset + tile_width*2 + line_thickness))
&& (vc >= (vbp + tile_offset + line_thickness*2 + tile_width*2) && vc < (vbp + tile_offset + tile_width*3 + line_thickness*2)))
begin // Tile 7
if (o_vec[7])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness*2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b010;
blue = 2'b00;
end
end
else if (x_vec[7])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness*2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b010;
blue = 2'b00;
end
end
else
begin
red = 3'b000;
green = 3'b010;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness*2 + tile_width*2) && hc < (hbp + tile_offset + tile_width*3 + line_thickness*2))
&& (vc >= (vbp + tile_offset + line_thickness*2 + tile_width*2) && vc < (vbp + tile_offset + tile_width*3 + line_thickness*2)))
begin // Tile 8
if (o_vec[8])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness * 2) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness * 2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b010;
green = 3'b010;
blue = 2'b00;
end
end
else if (x_vec[8])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness * 2) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness * 2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b010;
green = 3'b010;
blue = 2'b00;
end
end
else
begin
red = 3'b010;
green = 3'b010;
blue = 2'b00;
end
end
else if (hc >= (hbp) && hc < (hfp))
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
// we're outside active horizontal range so display black
else
begin
red = 0;
green = 0;
blue = 0;
end
end
// we're outside active vertical range so display black
else
begin
red = 0;
green = 0;
blue = 0;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cl_iobdg_cmp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: iobdg clock macro
// Description: Clock macro that encapsulates the cluster header.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module bw_clk_cl_iobdg_cmp (/*AUTOARG*/
// Outputs
so, rclk, dbginit_l, cluster_grst_l,
// Inputs
si, se, grst_l, gdbginit_l, gclk, cluster_cken, arst_l,
adbginit_l
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l; // To cluster_header of cluster_header.v
input arst_l; // To cluster_header of cluster_header.v
input cluster_cken; // To cluster_header of cluster_header.v
input gclk; // To cluster_header of cluster_header.v
input gdbginit_l; // To cluster_header of cluster_header.v
input grst_l; // To cluster_header of cluster_header.v
input se; // To cluster_header of cluster_header.v
input si; // To cluster_header of cluster_header.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output cluster_grst_l; // From cluster_header of cluster_header.v
output dbginit_l; // From cluster_header of cluster_header.v
output rclk; // From cluster_header of cluster_header.v
output so; // From cluster_header of cluster_header.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
////////////////////////////////////////////////////////////////////////
// Code start here
////////////////////////////////////////////////////////////////////////
cluster_header cluster_header (/*AUTOINST*/
// Outputs
.dbginit_l(dbginit_l),
.cluster_grst_l(cluster_grst_l),
.rclk (rclk),
.so (so),
// Inputs
.gclk (gclk),
.cluster_cken(cluster_cken),
.arst_l(arst_l),
.grst_l(grst_l),
.adbginit_l(adbginit_l),
.gdbginit_l(gdbginit_l),
.si (si),
.se (se));
endmodule // bw_clk_cl_iobdg_cmp
// Local Variables:
// verilog-library-directories:("." "../../common/rtl")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S6S_1_V
`define SKY130_FD_SC_LP__DLYMETAL6S6S_1_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog wrapper for dlymetal6s6s with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlymetal6s6s.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlymetal6s6s_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlymetal6s6s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlymetal6s6s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlymetal6s6s base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S6S_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3_TB_V
`define SKY130_FD_SC_MS__NOR3_TB_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ms__nor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3_TB_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 15:19:47 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub
// /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_processing_system7_0_0/led_controller_design_processing_system7_0_0_stub.v
// Design : led_controller_design_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.3" *)
module led_controller_design_processing_system7_0_0(TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
module GS_3032(
config_n, // ACEX1K config pins
status_n, //
conf_done, //
cs, //
init_done, //
clk24in, // 24mhz in
clk20in, // 20mhz in
clkout, // clock out
clksel0, // clock select 0 (1=divide by 2, 0=no divide)
clksel1, // clock select 1 (1=clk20in, 0=clk24in)
a6,a7,a14,a15, // z80 signals
iorq_n,mreq_n, //
rd_n,wr_n, //
d7,d0, //
mema14,mema15, // signals to memories
romcs_n,ramcs0_n,
memoe_n,memwe_n,
coldres_n, // cold reset input
warmres_n, // warm reset output
clkin // input of clkout signal
);
output config_n; reg config_n;
input status_n;
input conf_done;
output cs; reg cs;
input init_done;
input clk24in;
input clk20in;
output clkout; reg clkout;
input clksel0,clksel1;
input a6,a7,a14,a15;
input iorq_n,mreq_n,rd_n,wr_n;
inout d7,d0; reg d7,d0;
output mema14,mema15; reg mema14,mema15;
output romcs_n,ramcs0_n; reg romcs_n,ramcs0_n;
output memoe_n,memwe_n; reg memoe_n,memwe_n;
input coldres_n;
input warmres_n;
input clkin;
reg int_mema14,int_mema15;
reg int_romcs_n,int_ramcs0_n;
reg int_memoe_n,int_memwe_n;
reg int_cs;
reg [1:0] memcfg; // memcfg[1]: 1 ram, 0 roms
// memcfg[0]: 0 page0, 1 page1 -> in 8000-ffff region
reg diver [0:10];
reg disbl; // =1 - 3032 disabled, =0 - enabled
reg was_cold_reset_n; // 1 - no cold reset, 0 - was cold reset
reg [1:0] dbout;
wire [1:0] dbin;
assign dbin[1] = d7;
assign dbin[0] = d0;
wire memcfg_write;
wire rescfg_write;
wire coldrstf_read;
wire fpgastat_read;
reg [3:0] rstcount; // counter for warm reset period
reg [2:0] disbl_sync;
clocker myclk( .clk1(clk24in),
.clk2(clk20in),
.clksel(clksel1),
.divsel(clksel0),
.clkout(clkout) );
always @*
begin
cs <= 1'b0;
d0 <= 1'bZ;
d7 <= 1'bZ;
mema14 <= 1'bZ;
mema15 <= 1'bZ;
romcs_n <= 1'bZ;
ramcs0_n <= 1'bZ;
memoe_n <= 1'bZ;
memwe_n <= 1'bZ;
end
always @(coldres_n, warmres_n)
begin
if( coldres_n==1'b0)
config_n <= 1'b0;
else if( warmres_n==1'b0 )
config_n <= 1'b1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUF_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__BUF_PP_SYMBOL_V
/**
* buf: Buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__buf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUF_PP_SYMBOL_V
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sp_find_segment_n1_62 (
ph_seg_p_2_1_1_V_read,
th_seg_p_2_1_0_V_read,
th_seg_p_2_1_1_V_read,
cpat_seg_p_2_1_1_V_read,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3
);
input [11:0] ph_seg_p_2_1_1_V_read;
input [6:0] th_seg_p_2_1_0_V_read;
input [6:0] th_seg_p_2_1_1_V_read;
input [3:0] cpat_seg_p_2_1_1_V_read;
output [11:0] ap_return_0;
output [3:0] ap_return_1;
output [6:0] ap_return_2;
output [6:0] ap_return_3;
assign ap_return_0 = ph_seg_p_2_1_1_V_read;
assign ap_return_1 = cpat_seg_p_2_1_1_V_read;
assign ap_return_2 = th_seg_p_2_1_0_V_read;
assign ap_return_3 = th_seg_p_2_1_1_V_read;
endmodule //sp_find_segment_n1_62
|
// file: clk_wiz_v3_6_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge dut.clknetwork.dcm_sp_inst.LOCKED)
module clk_wiz_v3_6_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_wiz_v3_6_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT));
// Freq Check
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
// Date : Thu Aug 25 17:35:25 2016
// Host : fpgaserv running 64-bit Ubuntu 14.04.4 LTS
// Command : write_verilog -force -mode synth_stub
// /home/kobayashi/PCIe_test/branches/IEICE/4-way/src/ip_pcie/PCIeGen2x8If128_stub.v
// Design : PCIeGen2x8If128
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "PCIeGen2x8If128_pcie2_top,Vivado 2015.4" *)
module PCIeGen2x8If128(pci_exp_txp, pci_exp_txn, pci_exp_rxp, pci_exp_rxn, user_clk_out, user_reset_out, user_lnk_up, user_app_rdy, tx_buf_av, tx_cfg_req, tx_err_drop, s_axis_tx_tready, s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tlast, s_axis_tx_tvalid, s_axis_tx_tuser, tx_cfg_gnt, m_axis_rx_tdata, m_axis_rx_tkeep, m_axis_rx_tlast, m_axis_rx_tvalid, m_axis_rx_tready, m_axis_rx_tuser, rx_np_ok, rx_np_req, fc_cpld, fc_cplh, fc_npd, fc_nph, fc_pd, fc_ph, fc_sel, cfg_status, cfg_command, cfg_dstatus, cfg_dcommand, cfg_lstatus, cfg_lcommand, cfg_dcommand2, cfg_pcie_link_state, cfg_pmcsr_pme_en, cfg_pmcsr_powerstate, cfg_pmcsr_pme_status, cfg_received_func_lvl_rst, cfg_trn_pending, cfg_pm_halt_aspm_l0s, cfg_pm_halt_aspm_l1, cfg_pm_force_state_en, cfg_pm_force_state, cfg_dsn, cfg_interrupt, cfg_interrupt_rdy, cfg_interrupt_assert, cfg_interrupt_di, cfg_interrupt_do, cfg_interrupt_mmenable, cfg_interrupt_msienable, cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_stat, cfg_pciecap_interrupt_msgnum, cfg_to_turnoff, cfg_turnoff_ok, cfg_bus_number, cfg_device_number, cfg_function_number, cfg_pm_wake, cfg_pm_send_pme_to, cfg_ds_bus_number, cfg_ds_device_number, cfg_ds_function_number, cfg_bridge_serr_en, cfg_slot_control_electromech_il_ctl_pulse, cfg_root_control_syserr_corr_err_en, cfg_root_control_syserr_non_fatal_err_en, cfg_root_control_syserr_fatal_err_en, cfg_root_control_pme_int_en, cfg_aer_rooterr_corr_err_reporting_en, cfg_aer_rooterr_non_fatal_err_reporting_en, cfg_aer_rooterr_fatal_err_reporting_en, cfg_aer_rooterr_corr_err_received, cfg_aer_rooterr_non_fatal_err_received, cfg_aer_rooterr_fatal_err_received, cfg_vc_tcvc_map, sys_clk, sys_rst_n)
/* synthesis syn_black_box black_box_pad_pin="pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],user_clk_out,user_reset_out,user_lnk_up,user_app_rdy,tx_buf_av[5:0],tx_cfg_req,tx_err_drop,s_axis_tx_tready,s_axis_tx_tdata[127:0],s_axis_tx_tkeep[15:0],s_axis_tx_tlast,s_axis_tx_tvalid,s_axis_tx_tuser[3:0],tx_cfg_gnt,m_axis_rx_tdata[127:0],m_axis_rx_tkeep[15:0],m_axis_rx_tlast,m_axis_rx_tvalid,m_axis_rx_tready,m_axis_rx_tuser[21:0],rx_np_ok,rx_np_req,fc_cpld[11:0],fc_cplh[7:0],fc_npd[11:0],fc_nph[7:0],fc_pd[11:0],fc_ph[7:0],fc_sel[2:0],cfg_status[15:0],cfg_command[15:0],cfg_dstatus[15:0],cfg_dcommand[15:0],cfg_lstatus[15:0],cfg_lcommand[15:0],cfg_dcommand2[15:0],cfg_pcie_link_state[2:0],cfg_pmcsr_pme_en,cfg_pmcsr_powerstate[1:0],cfg_pmcsr_pme_status,cfg_received_func_lvl_rst,cfg_trn_pending,cfg_pm_halt_aspm_l0s,cfg_pm_halt_aspm_l1,cfg_pm_force_state_en,cfg_pm_force_state[1:0],cfg_dsn[63:0],cfg_interrupt,cfg_interrupt_rdy,cfg_interrupt_assert,cfg_interrupt_di[7:0],cfg_interrupt_do[7:0],cfg_interrupt_mmenable[2:0],cfg_interrupt_msienable,cfg_interrupt_msixenable,cfg_interrupt_msixfm,cfg_interrupt_stat,cfg_pciecap_interrupt_msgnum[4:0],cfg_to_turnoff,cfg_turnoff_ok,cfg_bus_number[7:0],cfg_device_number[4:0],cfg_function_number[2:0],cfg_pm_wake,cfg_pm_send_pme_to,cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_bridge_serr_en,cfg_slot_control_electromech_il_ctl_pulse,cfg_root_control_syserr_corr_err_en,cfg_root_control_syserr_non_fatal_err_en,cfg_root_control_syserr_fatal_err_en,cfg_root_control_pme_int_en,cfg_aer_rooterr_corr_err_reporting_en,cfg_aer_rooterr_non_fatal_err_reporting_en,cfg_aer_rooterr_fatal_err_reporting_en,cfg_aer_rooterr_corr_err_received,cfg_aer_rooterr_non_fatal_err_received,cfg_aer_rooterr_fatal_err_received,cfg_vc_tcvc_map[6:0],sys_clk,sys_rst_n" */;
output [7:0]pci_exp_txp;
output [7:0]pci_exp_txn;
input [7:0]pci_exp_rxp;
input [7:0]pci_exp_rxn;
output user_clk_out;
output user_reset_out;
output user_lnk_up;
output user_app_rdy;
output [5:0]tx_buf_av;
output tx_cfg_req;
output tx_err_drop;
output s_axis_tx_tready;
input [127:0]s_axis_tx_tdata;
input [15:0]s_axis_tx_tkeep;
input s_axis_tx_tlast;
input s_axis_tx_tvalid;
input [3:0]s_axis_tx_tuser;
input tx_cfg_gnt;
output [127:0]m_axis_rx_tdata;
output [15:0]m_axis_rx_tkeep;
output m_axis_rx_tlast;
output m_axis_rx_tvalid;
input m_axis_rx_tready;
output [21:0]m_axis_rx_tuser;
input rx_np_ok;
input rx_np_req;
output [11:0]fc_cpld;
output [7:0]fc_cplh;
output [11:0]fc_npd;
output [7:0]fc_nph;
output [11:0]fc_pd;
output [7:0]fc_ph;
input [2:0]fc_sel;
output [15:0]cfg_status;
output [15:0]cfg_command;
output [15:0]cfg_dstatus;
output [15:0]cfg_dcommand;
output [15:0]cfg_lstatus;
output [15:0]cfg_lcommand;
output [15:0]cfg_dcommand2;
output [2:0]cfg_pcie_link_state;
output cfg_pmcsr_pme_en;
output [1:0]cfg_pmcsr_powerstate;
output cfg_pmcsr_pme_status;
output cfg_received_func_lvl_rst;
input cfg_trn_pending;
input cfg_pm_halt_aspm_l0s;
input cfg_pm_halt_aspm_l1;
input cfg_pm_force_state_en;
input [1:0]cfg_pm_force_state;
input [63:0]cfg_dsn;
input cfg_interrupt;
output cfg_interrupt_rdy;
input cfg_interrupt_assert;
input [7:0]cfg_interrupt_di;
output [7:0]cfg_interrupt_do;
output [2:0]cfg_interrupt_mmenable;
output cfg_interrupt_msienable;
output cfg_interrupt_msixenable;
output cfg_interrupt_msixfm;
input cfg_interrupt_stat;
input [4:0]cfg_pciecap_interrupt_msgnum;
output cfg_to_turnoff;
input cfg_turnoff_ok;
output [7:0]cfg_bus_number;
output [4:0]cfg_device_number;
output [2:0]cfg_function_number;
input cfg_pm_wake;
input cfg_pm_send_pme_to;
input [7:0]cfg_ds_bus_number;
input [4:0]cfg_ds_device_number;
input [2:0]cfg_ds_function_number;
output cfg_bridge_serr_en;
output cfg_slot_control_electromech_il_ctl_pulse;
output cfg_root_control_syserr_corr_err_en;
output cfg_root_control_syserr_non_fatal_err_en;
output cfg_root_control_syserr_fatal_err_en;
output cfg_root_control_pme_int_en;
output cfg_aer_rooterr_corr_err_reporting_en;
output cfg_aer_rooterr_non_fatal_err_reporting_en;
output cfg_aer_rooterr_fatal_err_reporting_en;
output cfg_aer_rooterr_corr_err_received;
output cfg_aer_rooterr_non_fatal_err_received;
output cfg_aer_rooterr_fatal_err_received;
output [6:0]cfg_vc_tcvc_map;
input sys_clk;
input sys_rst_n;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311OI_TB_V
`define SKY130_FD_SC_MS__A311OI_TB_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a311oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__a311oi dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311OI_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22OI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A22OI_BEHAVIORAL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a22oi (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22OI_BEHAVIORAL_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_dac(
clk,
// control ports
control,
status,
// FIFO interface
src_dac_enable,
src_dac_data,
src_dac_valid,
dst_dac_enable,
dst_dac_data,
dst_dac_valid
);
localparam RP_ID = 8'hA1;
parameter CHANNEL_ID = 0;
input clk;
input [31:0] control;
output [31:0] status;
output src_dac_enable;
input [15:0] src_dac_data;
output src_dac_valid;
input dst_dac_enable;
output [15:0] dst_dac_data;
input dst_dac_valid;
reg [15:0] dst_dac_data = 0;
reg src_dac_valid = 0;
reg src_dac_enable = 0;
reg [15:0] dac_prbs = 32'hA2F19C;
reg [31:0] status = 0;
reg [ 2:0] counter = 0;
reg pattern = 0;
reg [15:0] sin_tone = 0;
reg [15:0] cos_tone = 0;
reg [ 3:0] mode;
wire [15:0] dac_pattern_s;
// prbs function
function [15:0] pn;
input [15:0] din;
reg [15:0] dout;
begin
dout[15] = din[14] ^ din[15];
dout[14] = din[13] ^ din[14];
dout[13] = din[12] ^ din[13];
dout[12] = din[11] ^ din[12];
dout[11] = din[10] ^ din[11];
dout[10] = din[ 9] ^ din[10];
dout[ 9] = din[ 8] ^ din[ 9];
dout[ 8] = din[ 7] ^ din[ 8];
dout[ 7] = din[ 6] ^ din[ 7];
dout[ 6] = din[ 5] ^ din[ 6];
dout[ 5] = din[ 4] ^ din[ 5];
dout[ 4] = din[ 3] ^ din[ 4];
dout[ 3] = din[ 2] ^ din[ 3];
dout[ 2] = din[ 1] ^ din[ 2];
dout[ 1] = din[ 0] ^ din[ 1];
dout[ 0] = din[14] ^ din[15] ^ din[ 0];
pn = dout;
end
endfunction
always @(posedge clk) begin
status <= {24'h0, RP_ID};
mode <= control[7:4];
end
// sine tone generation
always @(posedge clk) begin
if ((dst_dac_enable == 1'h1) && (dst_dac_valid == 1'h1)) begin
counter <= counter + 1;
end
end
always @(counter) begin
case(counter)
3'd0 : begin
sin_tone <= 16'h0000;
cos_tone <= 16'h7FFF;
end
3'd1 : begin
sin_tone <= 16'h5A82;
cos_tone <= 16'h5A82;
end
3'd2 : begin
sin_tone <= 16'h7FFF;
cos_tone <= 16'h0000;
end
3'd3 : begin
sin_tone <= 16'h5A82;
cos_tone <= 16'hA57E;
end
3'd4 : begin
sin_tone <= 16'h0000;
cos_tone <= 16'h8001;
end
3'd5 : begin
sin_tone <= 16'hA57E;
cos_tone <= 16'hA57E;
end
3'd6 : begin
sin_tone <= 16'h8001;
cos_tone <= 16'h0000;
end
3'd7 : begin
sin_tone <= 16'hA57E;
cos_tone <= 16'h5A82;
end
endcase
end
// prbs generation
always @(posedge clk) begin
if((dst_dac_enable == 1'h1) && (dst_dac_valid == 1'h1)) begin
dac_prbs <= pn(dac_prbs);
end
end
// constant pattern generator
always @(posedge clk) begin
if((dst_dac_enable == 1'h1) && (dst_dac_valid == 1'h1)) begin
pattern <= ~pattern;
end
end
assign dac_pattern_s = (pattern == 1'h1) ? 16'h5555 : 16'hAAAA;
// output mux for tx side
always @(posedge clk) begin
src_dac_enable <= dst_dac_enable;
src_dac_valid <= (mode == 0) ? dst_dac_valid : 1'b0;
end
always @(posedge clk) begin
case(mode)
4'h0 : begin
dst_dac_data <= src_dac_data;
end
4'h1 : begin
dst_dac_data <= {cos_tone, sin_tone};
end
4'h2 : begin
dst_dac_data <= dac_prbs;
end
4'h3 : begin
dst_dac_data <= dac_pattern_s;
end
default : begin
dst_dac_data <= src_dac_data;
end
endcase
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:18:21 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_sim_netlist.v
// Design : system_vga_sync_reset_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_sync_reset_0_0,vga_sync_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_sync_reset,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_sync_reset_0_0
(clk,
rst,
active,
hsync,
vsync,
xaddr,
yaddr);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 rst RST" *) input rst;
output active;
output hsync;
output vsync;
output [9:0]xaddr;
output [9:0]yaddr;
wire active;
wire clk;
wire hsync;
wire rst;
wire vsync;
wire [9:0]xaddr;
wire [9:0]yaddr;
system_vga_sync_reset_0_0_vga_sync_reset U0
(.active(active),
.clk(clk),
.hsync(hsync),
.rst(rst),
.vsync(vsync),
.xaddr(xaddr),
.yaddr(yaddr));
endmodule
(* ORIG_REF_NAME = "vga_sync_reset" *)
module system_vga_sync_reset_0_0_vga_sync_reset
(xaddr,
yaddr,
active,
hsync,
vsync,
clk,
rst);
output [9:0]xaddr;
output [9:0]yaddr;
output active;
output hsync;
output vsync;
input clk;
input rst;
wire active;
wire active_i_1_n_0;
wire active_i_2_n_0;
wire clk;
wire \h_count_reg[0]_i_1_n_0 ;
wire \h_count_reg[9]_i_1_n_0 ;
wire \h_count_reg[9]_i_3_n_0 ;
wire \h_count_reg[9]_i_4_n_0 ;
wire hsync;
wire hsync_i_1_n_0;
wire hsync_i_2_n_0;
wire hsync_i_3_n_0;
wire [9:1]plusOp;
wire [9:0]plusOp__0;
wire rst;
wire \v_count_reg[9]_i_1_n_0 ;
wire \v_count_reg[9]_i_2_n_0 ;
wire \v_count_reg[9]_i_4_n_0 ;
wire \v_count_reg[9]_i_5_n_0 ;
wire \v_count_reg[9]_i_6_n_0 ;
wire vsync;
wire vsync_i_1_n_0;
wire vsync_i_2_n_0;
wire [9:0]xaddr;
wire [9:0]yaddr;
LUT6 #(
.INIT(64'h0000222A00000000))
active_i_1
(.I0(active_i_2_n_0),
.I1(xaddr[9]),
.I2(xaddr[7]),
.I3(xaddr[8]),
.I4(yaddr[9]),
.I5(rst),
.O(active_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h7FFF))
active_i_2
(.I0(yaddr[7]),
.I1(yaddr[5]),
.I2(yaddr[6]),
.I3(yaddr[8]),
.O(active_i_2_n_0));
FDRE #(
.INIT(1'b0))
active_reg
(.C(clk),
.CE(1'b1),
.D(active_i_1_n_0),
.Q(active),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\h_count_reg[0]_i_1
(.I0(xaddr[0]),
.O(\h_count_reg[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\h_count_reg[1]_i_1
(.I0(xaddr[0]),
.I1(xaddr[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h78))
\h_count_reg[2]_i_1
(.I0(xaddr[1]),
.I1(xaddr[0]),
.I2(xaddr[2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\h_count_reg[3]_i_1
(.I0(xaddr[2]),
.I1(xaddr[0]),
.I2(xaddr[1]),
.I3(xaddr[3]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\h_count_reg[4]_i_1
(.I0(xaddr[3]),
.I1(xaddr[1]),
.I2(xaddr[0]),
.I3(xaddr[2]),
.I4(xaddr[4]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\h_count_reg[5]_i_1
(.I0(xaddr[4]),
.I1(xaddr[2]),
.I2(xaddr[0]),
.I3(xaddr[1]),
.I4(xaddr[3]),
.I5(xaddr[5]),
.O(plusOp[5]));
LUT3 #(
.INIT(8'hD2))
\h_count_reg[6]_i_1
(.I0(xaddr[5]),
.I1(\h_count_reg[9]_i_3_n_0 ),
.I2(xaddr[6]),
.O(plusOp[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hBF40))
\h_count_reg[7]_i_1
(.I0(\h_count_reg[9]_i_3_n_0 ),
.I1(xaddr[5]),
.I2(xaddr[6]),
.I3(xaddr[7]),
.O(plusOp[7]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hFF7F0080))
\h_count_reg[8]_i_1
(.I0(xaddr[7]),
.I1(xaddr[6]),
.I2(xaddr[5]),
.I3(\h_count_reg[9]_i_3_n_0 ),
.I4(xaddr[8]),
.O(plusOp[8]));
LUT6 #(
.INIT(64'h10000000FFFFFFFF))
\h_count_reg[9]_i_1
(.I0(\h_count_reg[9]_i_3_n_0 ),
.I1(xaddr[7]),
.I2(xaddr[8]),
.I3(xaddr[9]),
.I4(\h_count_reg[9]_i_4_n_0 ),
.I5(rst),
.O(\h_count_reg[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'hDFFFFFFF20000000))
\h_count_reg[9]_i_2
(.I0(xaddr[8]),
.I1(\h_count_reg[9]_i_3_n_0 ),
.I2(xaddr[5]),
.I3(xaddr[6]),
.I4(xaddr[7]),
.I5(xaddr[9]),
.O(plusOp[9]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h7FFFFFFF))
\h_count_reg[9]_i_3
(.I0(xaddr[3]),
.I1(xaddr[1]),
.I2(xaddr[0]),
.I3(xaddr[2]),
.I4(xaddr[4]),
.O(\h_count_reg[9]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h1))
\h_count_reg[9]_i_4
(.I0(xaddr[5]),
.I1(xaddr[6]),
.O(\h_count_reg[9]_i_4_n_0 ));
FDRE \h_count_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(\h_count_reg[0]_i_1_n_0 ),
.Q(xaddr[0]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[1]
(.C(clk),
.CE(1'b1),
.D(plusOp[1]),
.Q(xaddr[1]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[2]
(.C(clk),
.CE(1'b1),
.D(plusOp[2]),
.Q(xaddr[2]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[3]
(.C(clk),
.CE(1'b1),
.D(plusOp[3]),
.Q(xaddr[3]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[4]
(.C(clk),
.CE(1'b1),
.D(plusOp[4]),
.Q(xaddr[4]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[5]
(.C(clk),
.CE(1'b1),
.D(plusOp[5]),
.Q(xaddr[5]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[6]
(.C(clk),
.CE(1'b1),
.D(plusOp[6]),
.Q(xaddr[6]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[7]
(.C(clk),
.CE(1'b1),
.D(plusOp[7]),
.Q(xaddr[7]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[8]
(.C(clk),
.CE(1'b1),
.D(plusOp[8]),
.Q(xaddr[8]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[9]
(.C(clk),
.CE(1'b1),
.D(plusOp[9]),
.Q(xaddr[9]),
.R(\h_count_reg[9]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'hABEAFFFF))
hsync_i_1
(.I0(hsync_i_2_n_0),
.I1(xaddr[5]),
.I2(xaddr[6]),
.I3(hsync_i_3_n_0),
.I4(rst),
.O(hsync_i_1_n_0));
LUT3 #(
.INIT(8'hDF))
hsync_i_2
(.I0(xaddr[9]),
.I1(xaddr[8]),
.I2(xaddr[7]),
.O(hsync_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h0001FFFF))
hsync_i_3
(.I0(xaddr[2]),
.I1(xaddr[3]),
.I2(xaddr[0]),
.I3(xaddr[1]),
.I4(xaddr[4]),
.O(hsync_i_3_n_0));
FDRE #(
.INIT(1'b0))
hsync_reg
(.C(clk),
.CE(1'b1),
.D(hsync_i_1_n_0),
.Q(hsync),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT1 #(
.INIT(2'h1))
\v_count_reg[0]_i_1
(.I0(yaddr[0]),
.O(plusOp__0[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\v_count_reg[1]_i_1
(.I0(yaddr[0]),
.I1(yaddr[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\v_count_reg[2]_i_1
(.I0(yaddr[1]),
.I1(yaddr[0]),
.I2(yaddr[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h7F80))
\v_count_reg[3]_i_1
(.I0(yaddr[2]),
.I1(yaddr[0]),
.I2(yaddr[1]),
.I3(yaddr[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h7FFF8000))
\v_count_reg[4]_i_1
(.I0(yaddr[3]),
.I1(yaddr[1]),
.I2(yaddr[0]),
.I3(yaddr[2]),
.I4(yaddr[4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\v_count_reg[5]_i_1
(.I0(yaddr[4]),
.I1(yaddr[2]),
.I2(yaddr[0]),
.I3(yaddr[1]),
.I4(yaddr[3]),
.I5(yaddr[5]),
.O(plusOp__0[5]));
LUT3 #(
.INIT(8'hD2))
\v_count_reg[6]_i_1
(.I0(yaddr[5]),
.I1(\v_count_reg[9]_i_6_n_0 ),
.I2(yaddr[6]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hF708))
\v_count_reg[7]_i_1
(.I0(yaddr[5]),
.I1(yaddr[6]),
.I2(\v_count_reg[9]_i_6_n_0 ),
.I3(yaddr[7]),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hBFFF4000))
\v_count_reg[8]_i_1
(.I0(\v_count_reg[9]_i_6_n_0 ),
.I1(yaddr[6]),
.I2(yaddr[5]),
.I3(yaddr[7]),
.I4(yaddr[8]),
.O(plusOp__0[8]));
LUT6 #(
.INIT(64'h00400000FFFFFFFF))
\v_count_reg[9]_i_1
(.I0(\h_count_reg[9]_i_3_n_0 ),
.I1(\v_count_reg[9]_i_4_n_0 ),
.I2(\h_count_reg[9]_i_4_n_0 ),
.I3(yaddr[0]),
.I4(\v_count_reg[9]_i_5_n_0 ),
.I5(rst),
.O(\v_count_reg[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000001000))
\v_count_reg[9]_i_2
(.I0(xaddr[5]),
.I1(xaddr[6]),
.I2(xaddr[9]),
.I3(xaddr[8]),
.I4(xaddr[7]),
.I5(\h_count_reg[9]_i_3_n_0 ),
.O(\v_count_reg[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBFFFFFFF40000000))
\v_count_reg[9]_i_3
(.I0(\v_count_reg[9]_i_6_n_0 ),
.I1(yaddr[7]),
.I2(yaddr[5]),
.I3(yaddr[6]),
.I4(yaddr[8]),
.I5(yaddr[9]),
.O(plusOp__0[9]));
LUT6 #(
.INIT(64'h0002000000000000))
\v_count_reg[9]_i_4
(.I0(yaddr[9]),
.I1(xaddr[7]),
.I2(yaddr[7]),
.I3(yaddr[8]),
.I4(xaddr[9]),
.I5(xaddr[8]),
.O(\v_count_reg[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000020))
\v_count_reg[9]_i_5
(.I0(yaddr[3]),
.I1(yaddr[4]),
.I2(yaddr[2]),
.I3(yaddr[1]),
.I4(yaddr[6]),
.I5(yaddr[5]),
.O(\v_count_reg[9]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h7FFFFFFF))
\v_count_reg[9]_i_6
(.I0(yaddr[3]),
.I1(yaddr[1]),
.I2(yaddr[0]),
.I3(yaddr[2]),
.I4(yaddr[4]),
.O(\v_count_reg[9]_i_6_n_0 ));
FDRE \v_count_reg_reg[0]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[0]),
.Q(yaddr[0]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[1]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[1]),
.Q(yaddr[1]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[2]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[2]),
.Q(yaddr[2]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[3]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[3]),
.Q(yaddr[3]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[4]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[4]),
.Q(yaddr[4]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[5]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[5]),
.Q(yaddr[5]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[6]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[6]),
.Q(yaddr[6]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[7]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[7]),
.Q(yaddr[7]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[8]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[8]),
.Q(yaddr[8]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[9]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[9]),
.Q(yaddr[9]),
.R(\v_count_reg[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFBFFFFFFFF))
vsync_i_1
(.I0(vsync_i_2_n_0),
.I1(yaddr[1]),
.I2(yaddr[2]),
.I3(yaddr[9]),
.I4(yaddr[4]),
.I5(rst),
.O(vsync_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h7FFFFFFF))
vsync_i_2
(.I0(yaddr[8]),
.I1(yaddr[6]),
.I2(yaddr[5]),
.I3(yaddr[7]),
.I4(yaddr[3]),
.O(vsync_i_2_n_0));
FDRE #(
.INIT(1'b0))
vsync_reg
(.C(clk),
.CE(1'b1),
.D(vsync_i_1_n_0),
.Q(vsync),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O311A_FUNCTIONAL_PP_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311A_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:10:55 06/01/2015
// Design Name: UART_TX
// Module Name: /home/sadique/Work/Verilog/Spartan6/USB-uart/tx_test.v
// Project Name: USB-uart
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: UART_TX
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tx_test;
// Inputs
reg [7:0] RxD_par;
reg RxD_start;
reg RTS;
reg sys_clk;
wire BaudTick;
// Outputs
wire TxD_ser;
BaudGen baudgen (
.sys_clk(sys_clk),
.BaudTick(BaudTick)
);
// Instantiate the Unit Under Test (UUT)
UART_TX uut (
.RxD_par(RxD_par),
.RxD_start(RxD_start),
.RTS(RTS),
.sys_clk(sys_clk),
.BaudTick(BaudTick),
.TxD_ser(TxD_ser)
);
initial begin
// Initialize Inputs
RxD_par = 8'b01010101;
RxD_start = 0;
RTS = 1;
sys_clk = 0;
// Wait 100 ns for global reset to finish
#4000;
#37 RxD_start = 1;
#74 RxD_start = 0;
// Add stimulus here
end
always begin
#18.5 sys_clk <= !sys_clk;
end
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire5;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire locked = sub_wire5;
altpll altpll_component (
.areset (areset),
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire5),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 4,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 41666,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "ON",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "96.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Sat Sep 23 13:26:00 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top zqynq_lab_1_design_auto_pc_1 -prefix
// zqynq_lab_1_design_auto_pc_1_ zqynq_lab_1_design_auto_pc_1_stub.v
// Design : zqynq_lab_1_design_auto_pc_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module zqynq_lab_1_design_auto_pc_1(aclk, aresetn, s_axi_awaddr, s_axi_awlen,
s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awregion,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr,
s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot,
s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21OI_1_V
`define SKY130_FD_SC_LS__A21OI_1_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21oi_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21OI_1_V
|
module clock_counter(
input clk_i, //often, "tags" are added to variables to denote what they do for the user
input reset_n, //here, 'i' is used for input and 'o' for the output, while 'n' specifies an active low signal ("not")
output reg clk_o
);
reg [14:0] count; //register stores the counter value so that it can be modified on a clock edge. register size needs to store as large of a number as the counter reaches
//for this implementation, count must reach 415999, so 2^n >= 415999, n = 19
always @ (posedge clk_i, negedge reset_n)
begin
count <= count + 1; //at every positive edge, the counter is increased by 1
if(!reset_n)
begin
clk_o <= 0;
count <= 0; //if reset (active low) is pushed, the counter is reset
end
else
if(count >= 5000) //initial 17330 //count value of greater than or equal to this value causes the output clock to be inverted. the resulting frequency will be input_frequency/(1+count_value)
begin //for this implementation, a frequency of 5 Hz was desired, so 2.08e6/5 - 1 = 415999
clk_o <= ~clk_o;
count <= 0; //resets the counter after the output clock has been inverted
end
end
endmodule |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of IO60DRV1
//
// Generated
// by: wig
// on: Wed Mar 7 06:35:27 2007
// cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl ../../bugver2006.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: io60drv1.v,v 1.1 2007/03/08 09:32:07 wig Exp $
// $Date: 2007/03/08 09:32:07 $
// $Log: io60drv1.v,v $
// Revision 1.1 2007/03/08 09:32:07 wig
// Import missing file ...
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of IO60DRV1
//
// No user `defines in this module
module IO60DRV1
//
// Generated Module pad_data9
//
(
pad // From TopLevel Boundary
);
// Generated Module In/Outputs:
inout pad;
// Generated Wires:
wire pad;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of IO60DRV1
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* RX (Receive)
*
* Including Frame-Sync Detector, CRC-5, CRC-16, Command Buffer
*
* The clock signal in RX is delayed PIE code from Analog front-end circuit
* so we can directly transfer to binary code by clocking PIE code without decoder
*/
`timescale 1us / 1ns
module rx
(
output [7:0]cmd,
output [51:0]param,
output package_complete,
output crc_check_pass,
output [15:0]crc_16,
output en_crc5,
output en_crc16,
input pie_code,
input clk_dpie,
input clk_crc5,
input clk_crc16,
input rst_n,
input rst_for_new_package,
input rst_crc16,
input reply_data,
input en_crc16_for_rpy
);
fs_detector fs_detector_1
(
.sync(sync),
.pie_code(pie_code),
.clk_fsd(clk_dpie),
.rst_n(rst_n),
.package_complete(package_complete)
);
crc5 crc5_1
(
.crc5_check_pass(crc5_check_pass),
.clk_crc5(clk_crc5),
.rst_for_new_package(rst_for_new_package),
.data(pie_code),
.sync(sync),
.package_complete(package_complete)
);
crc16 crc16_1
(
.crc16_check_pass_reg(crc16_check_pass_reg),
.crc_16(crc_16),
.clk_crc16(clk_crc16),
.rst_crc16(rst_crc16),
.data(pie_code),
.reply_data(reply_data),
.sync(sync),
.package_complete(package_complete),
.en_crc16_for_rpy(en_crc16_for_rpy)
);
cmd_buf cmd_buf_1
(
.cmd(cmd),
.param(param),
.package_complete(package_complete),
.en_crc5(en_crc5),
.en_crc16(en_crc16),
.clk_cmd(clk_dpie),
.rst_for_new_package(rst_for_new_package),
.bits_in(pie_code),
.sync(sync)
);
assign crc_check_pass = crc5_check_pass | crc16_check_pass_reg;
endmodule
|
module fa1242(
output ml,
output md,
output mc,
output rstb,
input clk_s, // should be slower than 5Mhz
input rst);
parameter IDLE = 0;
parameter RST = 1;
parameter RST_WAIT = 2;
parameter SET_FUNCTION = 3;
parameter SET_FUNCTION_WAIT = 4;
// attn settings
wire [10:0] al = 0;
wire [10:0] ar = 0;
// mode settings
wire [1:0] om = 2'b0; // outlp: L, outlm: -L, outrp: R, outrm: -R
wire [1:0] bit = 2'b10; // 24bit
wire [1:0] zm = 2'b0; // open drain + pull up
wire atc = 2'b0; // attn. common for LR (off)
wire mute = 2'b0; // unmute
wire [1:0] emph = 2'b0; // no de-emphasis
// for reset
reg [4:0] wait_counter;
parameter WAIT_COUNTER_MAX = 5'h1f;
// for mode set
reg [1:0] mode;
reg [4:0] mode_set_counter;
// FSM transition
reg [3:0] state;
initial state = IDLE;
always @(posedge clk_s or rst) begin
if(rst) begin
state <= RST;
wait_counter <= 0;
mode_set_counter <= 0;
end else begin
case(state)
IDLE: state <= IDLE;
RST: begin
state <= RST_WAIT;
wait_counter <= 0;
end
RST_WAIT: begin
if(wait_counter == WAIT_COUNTER_MAX) begin
state <= SET_FUNCTION;
mode <= 2'd0;
mode_set_counter <= 2'd0;
end else begin
wait_counter <= wait_counter + 1;
end
end
SET_FUNCTION: begin
if(mode_set_counter == 5'h1f) begin
mode_set_counter <= 0;
state <= SET_FUNCTION_WAIT;
wait_counter <= 0;
end else
mode_set_counter <= mode_set_counter + 1;
end
SET_FUNCTION_WAIT: begin
if(wait_counter == WAIT_COUNTER_MAX) begin
if(mode == 2'd2)
// all done!
state <= IDLE;
else begin
// set next mode vector
state <= SET_FUNCTION;
mode <= mode + 1;
mode_set_counter <= 2'd0;
end
end else begin
wait_counter <= wait_counter + 1;
end
end
default: state <= IDLE;
endcase
end
end
assign rstb = (state == RST);
assign mc = mode_set_counter[0];
assign ml = ~((state == SET_FUNCTION_WAIT) && (wait_counter == 2));
function mode_set_data(
input [3:0] mode_set_idx,
input [1:0] mode);
reg [10:0] mode3;
begin
mode3 = {om, /*rst*/1'b0, bit, zm, atc, mute, emph};
if(mode_set_idx < 5)
case(mode_set_idx)
// res
4'd00: mode_set_data = 0;
4'd01: mode_set_data = 0;
4'd02: mode_set_data = 0;
// mode
4'd03: mode_set_data = mode[1];
4'd04: mode_set_data = mode[0];
endcase
else
case(mode)
2'd0: mode_set_data = al[10+5-mode_set_idx];
2'd1: mode_set_data = ar[10+5-mode_set_idx];
2'd2: mode_set_data = mode3[10+5-mode_set_idx];
endcase
end
endfunction
assign md = mode_set_data(mode_set_counter[4:1], mode);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:49:41 04/02/2016
// Design Name: register
// Module Name: Y:/TEOCOA/EXPR4/REGISTER_TEST.v
// Project Name: EXPR4
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: register
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module REGISTER_TEST;
// Inputs
reg clk;
reg Reset;
reg [4:0] R_Addr_A;
reg [4:0] R_Addr_B;
reg [4:0] W_Addr;
reg [31:0] W_Data;
reg Write_Reg;
// Outputs
wire [31:0] R_Data_A;
wire [31:0] R_Data_B;
// Instantiate the Unit Under Test (UUT)
register uut (
.clk(clk),
.Reset(Reset),
.R_Addr_A(R_Addr_A),
.R_Addr_B(R_Addr_B),
.W_Addr(W_Addr),
.W_Data(W_Data),
.Write_Reg(Write_Reg),
.R_Data_A(R_Data_A),
.R_Data_B(R_Data_B)
);
initial begin
// Initialize Inputs
clk = 0;
Reset = 1;
# 10;
Reset = 1;
R_Addr_A = 1;
R_Addr_B = 2;
W_Addr = 10;
W_Data = 3;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 0;
R_Addr_B = 1;
W_Addr = 0;
W_Data = 3;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 1;
R_Addr_B = 2;
W_Addr = 1;
W_Data = 4;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 2;
R_Addr_B = 3;
W_Addr = 2;
W_Data = 5;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 3;
R_Addr_B = 4;
W_Addr = 3;
W_Data = 6;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 4;
R_Addr_B = 5;
W_Addr = 4;
W_Data = 7;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 5;
R_Addr_B = 6;
W_Addr = 5;
W_Data = 8;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 6;
R_Addr_B = 7;
W_Addr = 6;
W_Data = 9;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 7;
R_Addr_B = 8;
W_Addr = 7;
W_Data = 10;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 8;
R_Addr_B = 9;
W_Addr = 8;
W_Data = 11;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 9;
R_Addr_B = 10;
W_Addr = 9;
W_Data = 12;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 10;
R_Addr_B = 11;
W_Addr = 10;
W_Data = 13;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 11;
R_Addr_B = 12;
W_Addr = 11;
W_Data = 14;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 0;
R_Addr_B = 1;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 1;
R_Addr_B = 2;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 2;
R_Addr_B = 3;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 3;
R_Addr_B = 4;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 4;
R_Addr_B = 5;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 5;
R_Addr_B = 6;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 6;
R_Addr_B = 7;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 7;
R_Addr_B = 8;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 8;
R_Addr_B = 9;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 9;
R_Addr_B = 10;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 10;
R_Addr_B = 11;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 11;
R_Addr_B = 12;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
end
always #2 clk = ~clk;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FA_1_V
`define SKY130_FD_SC_LS__FA_1_V
/**
* fa: Full adder.
*
* Verilog wrapper for fa with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fa.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fa_1 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fa_1 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__FA_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_SIO_SYMBOL_V
`define SKY130_FD_IO__TOP_SIO_SYMBOL_V
/**
* top_sio: Special I/O PAD that provides additionally a
* regulated output buffer and a differential input buffer.
* SIO cells are ONLY available IN pairs (see top_sio_macro).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_sio (
//# {{data|Data Signals}}
input SLOW ,
output IN ,
input INP_DIS ,
output IN_H ,
input OUT ,
inout PAD ,
inout PAD_A_ESD_0_H,
inout PAD_A_ESD_1_H,
inout PAD_A_NOESD_H,
//# {{control|Control Signals}}
input [2:0] DM ,
input ENABLE_H ,
input HLD_H_N ,
input HLD_OVR ,
input IBUF_SEL ,
input OE_N ,
//# {{power|Power}}
input VREG_EN ,
input VTRIP_SEL ,
input REFLEAK_BIAS ,
input VINREF ,
input VOUTREF ,
output TIE_LO_ESD
);
// Voltage supply signals
supply0 VSSIO ;
supply0 VSSIO_Q;
supply0 VSSD ;
supply1 VCCD ;
supply1 VDDIO ;
supply1 VCCHIB ;
supply1 VDDIO_Q;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_SIO_SYMBOL_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: Alok:user:sample_generator:1.0
// IP Revision: 1
(* X_CORE_INFO = "sample_generator_v1_0,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "design_1_sample_generator_0_1,sample_generator_v1_0,{}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_sample_generator_0_1 (
FrameSize,
En,
AXI_En,
m_axis_tdata,
m_axis_tstrb,
m_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_aclk,
m_axis_aresetn,
s_axis_tdata,
s_axis_tstrb,
s_axis_tlast,
s_axis_tvalid,
s_axis_tready,
s_axis_aclk,
s_axis_aresetn
);
input wire [7 : 0] FrameSize;
input wire En;
input wire AXI_En;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [31 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TSTRB" *)
output wire [3 : 0] m_axis_tstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output wire m_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXIS_CLK CLK" *)
input wire m_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 M_AXIS_RST RST" *)
input wire m_axis_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input wire [31 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TSTRB" *)
input wire [3 : 0] s_axis_tstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input wire s_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input wire s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output wire s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXIS_CLK CLK" *)
input wire s_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_AXIS_RST RST" *)
input wire s_axis_aresetn;
sample_generator_v1_0 #(
.C_M_AXIS_TDATA_WIDTH(32), // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
.C_M_AXIS_START_COUNT(32), // Start count is the numeber of clock cycles the master will wait before initiating/issuing any transaction.
.C_S_AXIS_TDATA_WIDTH(32) // AXI4Stream sink: Data Width
) inst (
.FrameSize(FrameSize),
.En(En),
.AXI_En(AXI_En),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(m_axis_tstrb),
.m_axis_tlast(m_axis_tlast),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(s_axis_tstrb),
.s_axis_tlast(s_axis_tlast),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_aclk(s_axis_aclk),
.s_axis_aresetn(s_axis_aresetn)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_BEHAVIORAL_V
`define SKY130_FD_SC_LS__FILL_BEHAVIORAL_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_BEHAVIORAL_V |
//wishbone_interconnect.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Thanks Rudolf Usselmann yours was a better implementation than mine
Copyright (C) 2000-2002
Rudolf Usselmann
www.asics.ws
[email protected]
*/
`timescale 1 ns/1 ps
module wishbone_interconnect (
//control signals
input clk,
input rst,
//wishbone master signals
input i_m_we,
input i_m_stb,
input i_m_cyc,
input [3:0] i_m_sel,
input [31:0] i_m_adr,
input [31:0] i_m_dat,
output reg [31:0] o_m_dat,
output reg o_m_ack,
output o_m_int,
//Slave 0
output o_s0_we,
output o_s0_cyc,
output o_s0_stb,
output [3:0] o_s0_sel,
input i_s0_ack,
output [31:0] o_s0_dat,
input [31:0] i_s0_dat,
output [31:0] o_s0_adr,
input i_s0_int,
//Slave 1
output o_s1_we,
output o_s1_cyc,
output o_s1_stb,
output [3:0] o_s1_sel,
input i_s1_ack,
output [31:0] o_s1_dat,
input [31:0] i_s1_dat,
output [31:0] o_s1_adr,
input i_s1_int,
//Slave 2
output o_s2_we,
output o_s2_cyc,
output o_s2_stb,
output [3:0] o_s2_sel,
input i_s2_ack,
output [31:0] o_s2_dat,
input [31:0] i_s2_dat,
output [31:0] o_s2_adr,
input i_s2_int
);
parameter ADDR_0 = 0;
parameter ADDR_1 = 1;
parameter ADDR_2 = 2;
parameter ADDR_FF = 8'hFF;
//state
//wishbone slave signals
//this should be parameterized
wire [7:0]slave_select;
wire [31:0] interrupts;
assign slave_select = i_m_adr[31:24];
//data in from slave
always @ (slave_select or i_s0_dat or i_s1_dat or i_s2_dat or interrupts) begin
case (slave_select)
ADDR_0: begin
o_m_dat <= i_s0_dat;
end
ADDR_1: begin
o_m_dat <= i_s1_dat;
end
ADDR_2: begin
o_m_dat <= i_s2_dat;
end
default: begin
o_m_dat <= interrupts;
end
endcase
end
//ack in from slave
always @ (slave_select or i_s0_ack or i_s1_ack or i_s2_ack) begin
case (slave_select)
ADDR_0: begin
o_m_ack <= i_s0_ack;
end
ADDR_1: begin
o_m_ack <= i_s1_ack;
end
ADDR_2: begin
o_m_ack <= i_s2_ack;
end
default: begin
o_m_ack <= 1'h0;
end
endcase
end
//int in from slave
assign interrupts[0] = i_s0_int;
assign interrupts[1] = i_s1_int;
assign interrupts[2] = i_s2_int;
assign interrupts[31:3] = 0;
assign o_m_int = (interrupts != 0);
assign o_s0_we = (slave_select == ADDR_0) ? i_m_we: 1'b0;
assign o_s0_stb = (slave_select == ADDR_0) ? i_m_stb: 1'b0;
assign o_s0_sel = (slave_select == ADDR_0) ? i_m_sel: 4'h0;
assign o_s0_cyc = (slave_select == ADDR_0) ? i_m_cyc: 1'b0;
assign o_s0_adr = (slave_select == ADDR_0) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s0_dat = (slave_select == ADDR_0) ? i_m_dat: 32'h0;
assign o_s1_we = (slave_select == ADDR_1) ? i_m_we: 1'b0;
assign o_s1_stb = (slave_select == ADDR_1) ? i_m_stb: 1'b0;
assign o_s1_sel = (slave_select == ADDR_1) ? i_m_sel: 4'h0;
assign o_s1_cyc = (slave_select == ADDR_1) ? i_m_cyc: 1'b0;
assign o_s1_adr = (slave_select == ADDR_1) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s1_dat = (slave_select == ADDR_1) ? i_m_dat: 32'h0;
assign o_s2_we = (slave_select == ADDR_2) ? i_m_we: 1'b0;
assign o_s2_stb = (slave_select == ADDR_2) ? i_m_stb: 1'b0;
assign o_s2_sel = (slave_select == ADDR_2) ? i_m_sel: 4'h0;
assign o_s2_cyc = (slave_select == ADDR_2) ? i_m_cyc: 1'b0;
assign o_s2_adr = (slave_select == ADDR_2) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s2_dat = (slave_select == ADDR_2) ? i_m_dat: 32'h0;
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2015 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ogfx_backend_lut_fifo.v
//
// *Module Description:
// Mini-cache memory for the LUT memory accesses.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_defines.v"
`endif
module ogfx_backend_lut_fifo (
// OUTPUTs
frame_data_request_o, // Request for next frame data
refresh_data_o, // Display Refresh data
refresh_data_ready_o, // Display Refresh data ready
`ifdef WITH_PROGRAMMABLE_LUT
lut_ram_addr_o, // LUT-RAM address
lut_ram_cen_o, // LUT-RAM enable (active low)
`endif
// INPUTs
mclk, // Main system clock
puc_rst, // Main system reset
frame_data_i, // Frame data
frame_data_ready_i, // Frame data ready
gfx_mode_i, // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
`ifdef WITH_PROGRAMMABLE_LUT
lut_ram_dout_i, // LUT-RAM data output
lut_ram_dout_rdy_nxt_i, // LUT-RAM data output ready during next cycle
`endif
refresh_active_i, // Display refresh on going
refresh_data_request_i, // Request for next refresh data
hw_lut_palette_sel_i, // Hardware LUT palette configuration
hw_lut_bgcolor_i, // Hardware LUT background-color selection
hw_lut_fgcolor_i, // Hardware LUT foreground-color selection
sw_lut_enable_i, // Refresh LUT-RAM enable
sw_lut_bank_select_i // Refresh LUT-RAM bank selection
);
// OUTPUTs
//=========
output frame_data_request_o; // Request for next frame data
output [15:0] refresh_data_o; // Display Refresh data
output refresh_data_ready_o; // Display Refresh data ready
`ifdef WITH_PROGRAMMABLE_LUT
output [`LRAM_MSB:0] lut_ram_addr_o; // LUT-RAM address
output lut_ram_cen_o; // LUT-RAM enable (active low)
`endif
// INPUTs
//=========
input mclk; // Main system clock
input puc_rst; // Main system reset
input [15:0] frame_data_i; // Frame data
input frame_data_ready_i; // Frame data ready
input [2:0] gfx_mode_i; // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
`ifdef WITH_PROGRAMMABLE_LUT
input [15:0] lut_ram_dout_i; // LUT-RAM data output
input lut_ram_dout_rdy_nxt_i; // LUT-RAM data output ready during next cycle
`endif
input refresh_active_i; // Display refresh on going
input refresh_data_request_i; // Request for next refresh data
input [2:0] hw_lut_palette_sel_i; // Hardware LUT palette configuration
input [3:0] hw_lut_bgcolor_i; // Hardware LUT background-color selection
input [3:0] hw_lut_fgcolor_i; // Hardware LUT foreground-color selection
input sw_lut_enable_i; // Refresh LUT-RAM enable
input sw_lut_bank_select_i; // Refresh LUT-RAM bank selection
//=============================================================================
// 1) WIRE, REGISTERS AND PARAMETER DECLARATION
//=============================================================================
// State machine registers
reg [1:0] lut_state;
reg [1:0] lut_state_nxt;
// State definition
parameter STATE_IDLE = 0,
STATE_FRAME_DATA = 1,
STATE_LUT_DATA = 2,
STATE_HOLD = 3;
// Some parameter(s)
parameter FIFO_EMPTY = 3'h0,
FIFO_FULL = 3'h5;
// Video modes decoding
wire gfx_mode_1_bpp = (gfx_mode_i == 3'b000);
wire gfx_mode_2_bpp = (gfx_mode_i == 3'b001);
wire gfx_mode_4_bpp = (gfx_mode_i == 3'b010);
wire gfx_mode_8_bpp = (gfx_mode_i == 3'b011);
wire gfx_mode_16_bpp = ~(gfx_mode_8_bpp | gfx_mode_4_bpp |
gfx_mode_2_bpp | gfx_mode_1_bpp);
// Others
reg [2:0] fifo_counter;
wire [2:0] fifo_counter_nxt;
//============================================================================
// 2) HARD CODED LOOKUP TABLE
//============================================================================
// 16 full CGA color selection
parameter [3:0] CGA_BLACK = 4'h0,
CGA_BLUE = 4'h1,
CGA_GREEN = 4'h2,
CGA_CYAN = 4'h3,
CGA_RED = 4'h4,
CGA_MAGENTA = 4'h5,
CGA_BROWN = 4'h6,
CGA_LIGHT_GRAY = 4'h7,
CGA_GRAY = 4'h8,
CGA_LIGHT_BLUE = 4'h9,
CGA_LIGHT_GREEN = 4'hA,
CGA_LIGHT_CYAN = 4'hB,
CGA_LIGHT_RED = 4'hC,
CGA_LIGHT_MAGENTA = 4'hD,
CGA_YELLOW = 4'hE,
CGA_WHITE = 4'hF;
// Decode CGA 4 color mode (2bpp)
wire cga_palette0_hi = (hw_lut_palette_sel_i==3'h0);
wire cga_palette0_lo = (hw_lut_palette_sel_i==3'h1);
wire cga_palette1_hi = (hw_lut_palette_sel_i==3'h2);
wire cga_palette1_lo = (hw_lut_palette_sel_i==3'h3);
wire cga_palette2_hi = (hw_lut_palette_sel_i==3'h4);
wire cga_palette2_lo = (hw_lut_palette_sel_i==3'h5) | (hw_lut_palette_sel_i==3'h6) | (hw_lut_palette_sel_i==3'h7);
// LUT color decoding
// 1 BPP
wire [3:0] lut_hw_sel_1bpp = ({4{gfx_mode_1_bpp & (frame_data_i[0] ==1'b0 )}} & hw_lut_bgcolor_i ) | // 1 bpp: Black (default bgcolor)
({4{gfx_mode_1_bpp & (frame_data_i[0] ==1'b1 )}} & hw_lut_fgcolor_i ) ; // White (default fgcolor)
// 2 BPP (Palette #0, low-intensity)
wire [3:0] lut_hw_sel_2bpp = ({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b01)}} & CGA_GREEN ) | // Green
({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b10)}} & CGA_RED ) | // Red
({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b11)}} & CGA_BROWN ) | // Brown
// 2 BPP (Palette #0, high-intensity)
({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b01)}} & CGA_LIGHT_GREEN ) | // Light-Green
({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b10)}} & CGA_LIGHT_RED ) | // Light-Red
({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b11)}} & CGA_YELLOW ) | // Yellow
// 2 BPP (Palette #1, low-intensity)
({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b01)}} & CGA_CYAN ) | // Cyan
({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b10)}} & CGA_MAGENTA ) | // Magenta
({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b11)}} & CGA_LIGHT_GRAY ) | // Light-Gray
// 2 BPP (Palette #1, high-intensity)
({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b01)}} & CGA_LIGHT_CYAN ) | // Light-Cyan
({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b10)}} & CGA_LIGHT_MAGENTA) | // Light-Magenta
({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b11)}} & CGA_WHITE ) | // White
// 2 BPP (Palette #2, low-intensity)
({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b01)}} & CGA_CYAN ) | // Cyan
({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b10)}} & CGA_RED ) | // Red
({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b11)}} & CGA_LIGHT_GRAY ) | // Light-Gray
// 2 BPP (Palette #2, high-intensity)
({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b01)}} & CGA_LIGHT_CYAN ) | // Light-Cyan
({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b10)}} & CGA_LIGHT_RED ) | // Light-Red
({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b11)}} & CGA_WHITE ) ; // White
// 4 BPP (full CGA 16-color palette)
wire [3:0] lut_hw_sel_4bpp = ({4{gfx_mode_4_bpp}} & frame_data_i[3:0]);
wire [3:0] lut_hw_color_sel = lut_hw_sel_4bpp | lut_hw_sel_2bpp | lut_hw_sel_1bpp;
// Color encoding for 1-bit / 2-bit and 4-bit modes
reg [15:0] lut_hw_data_1_2_4_bpp;
always @(lut_hw_color_sel)
case(lut_hw_color_sel)
CGA_BLACK : lut_hw_data_1_2_4_bpp = {5'b00000, 6'b000000, 5'b00000}; // Black
CGA_BLUE : lut_hw_data_1_2_4_bpp = {5'b00000, 6'b000000, 5'b10101}; // Blue
CGA_GREEN : lut_hw_data_1_2_4_bpp = {5'b00000, 6'b101011, 5'b00000}; // Green
CGA_CYAN : lut_hw_data_1_2_4_bpp = {5'b00000, 6'b101011, 5'b10101}; // Cyan
CGA_RED : lut_hw_data_1_2_4_bpp = {5'b10101, 6'b000000, 5'b00000}; // Red
CGA_MAGENTA : lut_hw_data_1_2_4_bpp = {5'b10101, 6'b000000, 5'b10101}; // Magenta
CGA_BROWN : lut_hw_data_1_2_4_bpp = {5'b10101, 6'b010101, 5'b00000}; // Brown
CGA_LIGHT_GRAY : lut_hw_data_1_2_4_bpp = {5'b10101, 6'b101011, 5'b10101}; // Light Gray
CGA_GRAY : lut_hw_data_1_2_4_bpp = {5'b01011, 6'b010101, 5'b01011}; // Gray
CGA_LIGHT_BLUE : lut_hw_data_1_2_4_bpp = {5'b01011, 6'b010101, 5'b11111}; // Light Blue
CGA_LIGHT_GREEN : lut_hw_data_1_2_4_bpp = {5'b01011, 6'b111111, 5'b01011}; // Light Green
CGA_LIGHT_CYAN : lut_hw_data_1_2_4_bpp = {5'b01011, 6'b111111, 5'b11111}; // Light Cyan
CGA_LIGHT_RED : lut_hw_data_1_2_4_bpp = {5'b11111, 6'b010101, 5'b01011}; // Light Red
CGA_LIGHT_MAGENTA : lut_hw_data_1_2_4_bpp = {5'b11111, 6'b010101, 5'b11111}; // Light Magenta
CGA_YELLOW : lut_hw_data_1_2_4_bpp = {5'b11111, 6'b111111, 5'b01011}; // Yellow
CGA_WHITE : lut_hw_data_1_2_4_bpp = {5'b11111, 6'b111111, 5'b11111}; // White
// pragma coverage off
default : lut_hw_data_1_2_4_bpp = 16'h0000;
// pragma coverage on
endcase
// 8-bit truecolor RGB mapping (3-bit red / 3-bit green / 2-bit blue)
wire [15:0] lut_hw_data_8_bpp = {frame_data_i[7],frame_data_i[6],frame_data_i[5],frame_data_i[5],frame_data_i[5], // 8 bpp: R = D<7,6,5,5,5>
frame_data_i[4],frame_data_i[3],frame_data_i[2],frame_data_i[2],frame_data_i[2],frame_data_i[2], // G = D<4,3,2,2,2,2>
frame_data_i[1],frame_data_i[0],frame_data_i[0],frame_data_i[0],frame_data_i[0]}; // B = D<1,0,0,0,0>
wire [15:0] lut_hw_data = (lut_hw_data_1_2_4_bpp & {16{gfx_mode_1_bpp | gfx_mode_2_bpp | gfx_mode_4_bpp}}) |
(lut_hw_data_8_bpp & {16{gfx_mode_8_bpp}});
wire lut_hw_enabled = ~gfx_mode_16_bpp & ~sw_lut_enable_i;
wire lut_sw_enabled = ~gfx_mode_16_bpp & sw_lut_enable_i;
//============================================================================
// 3) STATE MACHINE
//============================================================================
//--------------------------------
// States Transitions
//--------------------------------
always @(lut_state or refresh_active_i or frame_data_ready_i or
`ifdef WITH_PROGRAMMABLE_LUT
lut_sw_enabled or lut_ram_dout_rdy_nxt_i or
`endif
fifo_counter_nxt)
case(lut_state)
STATE_IDLE : lut_state_nxt = ~refresh_active_i ? STATE_IDLE : STATE_FRAME_DATA ;
STATE_FRAME_DATA : lut_state_nxt = ~refresh_active_i ? STATE_IDLE :
~frame_data_ready_i ? STATE_FRAME_DATA :
`ifdef WITH_PROGRAMMABLE_LUT
lut_sw_enabled ? STATE_LUT_DATA :
`endif
STATE_HOLD ;
`ifdef WITH_PROGRAMMABLE_LUT
STATE_LUT_DATA : lut_state_nxt = ~refresh_active_i ? STATE_IDLE :
lut_ram_dout_rdy_nxt_i ? STATE_HOLD : STATE_LUT_DATA ;
`endif
STATE_HOLD : lut_state_nxt = ~refresh_active_i ? STATE_IDLE :
(fifo_counter_nxt!=FIFO_FULL) ? STATE_FRAME_DATA : STATE_HOLD ;
// pragma coverage off
default : lut_state_nxt = STATE_IDLE;
// pragma coverage on
endcase
//--------------------------------
// State machine
//--------------------------------
always @(posedge mclk or posedge puc_rst)
if (puc_rst) lut_state <= STATE_IDLE;
else lut_state <= lut_state_nxt;
// Request for the next frame data
assign frame_data_request_o = (lut_state == STATE_FRAME_DATA);
//============================================================================
// 4) LUT MEMORY INTERFACE
//============================================================================
//--------------------------------
// Enable
//--------------------------------
`ifdef WITH_PROGRAMMABLE_LUT
assign lut_ram_cen_o = ~(lut_state == STATE_LUT_DATA);
`endif
//--------------------------------
// Address
//--------------------------------
// Mask with chip enable to save power
`ifdef WITH_PROGRAMMABLE_LUT
`ifdef WITH_EXTRA_LUT_BANK
// Allow LUT bank switching only when the refresh is not on going
reg refresh_lut_bank_select_sync;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) refresh_lut_bank_select_sync <= 1'b0;
else if (~refresh_active_i) refresh_lut_bank_select_sync <= sw_lut_bank_select_i;
assign lut_ram_addr_o = {refresh_lut_bank_select_sync, frame_data_i[7:0]} & {9{~lut_ram_cen_o}};
`else
assign lut_ram_addr_o = frame_data_i[7:0] & {8{~lut_ram_cen_o}};
`endif
`endif
//--------------------------------
// Data Ready
//--------------------------------
// When filling the FIFO, the data is available on the bus
// one cycle after the rdy_nxt signal
reg lut_ram_dout_ready;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) lut_ram_dout_ready <= 1'b0;
`ifdef WITH_PROGRAMMABLE_LUT
else lut_ram_dout_ready <= lut_sw_enabled ? lut_ram_dout_rdy_nxt_i :
(frame_data_ready_i & (lut_state == STATE_FRAME_DATA));
`else
else lut_ram_dout_ready <= (frame_data_ready_i & (lut_state == STATE_FRAME_DATA));
`endif
//============================================================================
// 5) FIFO COUNTER
//============================================================================
// Control signals
wire fifo_push = lut_ram_dout_ready & (fifo_counter != FIFO_FULL);
wire fifo_pop = refresh_data_request_i & (fifo_counter != FIFO_EMPTY);
// Fifo counter
assign fifo_counter_nxt = ~refresh_active_i ? FIFO_EMPTY : // Initialize
(fifo_push & fifo_pop) ? fifo_counter : // Keep value (pop & push at the same time)
fifo_push ? fifo_counter + 3'h1 : // Push
fifo_pop ? fifo_counter - 3'h1 : // Pop
fifo_counter; // Hold
always @(posedge mclk or posedge puc_rst)
if (puc_rst) fifo_counter <= FIFO_EMPTY;
else fifo_counter <= fifo_counter_nxt;
//============================================================================
// 6) FIFO MEMORY & RD/WR POINTERS
//============================================================================
// Write pointer
reg [2:0] wr_ptr;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) wr_ptr <= 3'h0;
else if (~refresh_active_i) wr_ptr <= 3'h0;
else if (fifo_push)
begin
if (wr_ptr==(FIFO_FULL-1)) wr_ptr <= 3'h0;
else wr_ptr <= wr_ptr + 3'h1;
end
// Memory
reg [15:0] fifo_mem [0:4];
always @(posedge mclk or posedge puc_rst)
if (puc_rst)
begin
fifo_mem[0] <= 16'h0000;
fifo_mem[1] <= 16'h0000;
fifo_mem[2] <= 16'h0000;
fifo_mem[3] <= 16'h0000;
fifo_mem[4] <= 16'h0000;
end
else if (fifo_push)
begin
fifo_mem[wr_ptr] <= lut_hw_enabled ? lut_hw_data :
`ifdef WITH_PROGRAMMABLE_LUT
lut_sw_enabled ? lut_ram_dout_i :
`endif
frame_data_i;
end
// Read pointer
reg [2:0] rd_ptr;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) rd_ptr <= 3'h0;
else if (~refresh_active_i) rd_ptr <= 3'h0;
else if (fifo_pop)
begin
if (rd_ptr==(FIFO_FULL-1)) rd_ptr <= 3'h0;
else rd_ptr <= rd_ptr + 3'h1;
end
//============================================================================
// 7) REFRESH_DATA
//============================================================================
// Refresh Data is ready
reg refresh_data_ready_o;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) refresh_data_ready_o <= 1'h0;
else if (~refresh_active_i) refresh_data_ready_o <= 1'h0;
else refresh_data_ready_o <= fifo_pop;
// Refresh Data
reg [15:0] refresh_data_o;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) refresh_data_o <= 16'h0000;
else if (fifo_pop) refresh_data_o <= fifo_mem[rd_ptr];
endmodule // ogfx_backend_lut_fifo
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_undefines.v"
`endif
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
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// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module image_processing_2d_design_processing_system7_0_0 (
GPIO_I,
GPIO_O,
GPIO_T,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
IRQ_F2P,
FCLK_CLK0,
FCLK_CLK1,
FCLK_CLK2,
FCLK_RESET0_N,
FCLK_RESET1_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
input [3 : 0] GPIO_I;
output [3 : 0] GPIO_O;
output [3 : 0] GPIO_T;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1 : 0] S_AXI_HP0_BRESP;
output [1 : 0] S_AXI_HP0_RRESP;
output [5 : 0] S_AXI_HP0_BID;
output [5 : 0] S_AXI_HP0_RID;
output [31 : 0] S_AXI_HP0_RDATA;
output [7 : 0] S_AXI_HP0_RCOUNT;
output [7 : 0] S_AXI_HP0_WCOUNT;
output [2 : 0] S_AXI_HP0_RACOUNT;
output [5 : 0] S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1 : 0] S_AXI_HP0_ARBURST;
input [1 : 0] S_AXI_HP0_ARLOCK;
input [2 : 0] S_AXI_HP0_ARSIZE;
input [1 : 0] S_AXI_HP0_AWBURST;
input [1 : 0] S_AXI_HP0_AWLOCK;
input [2 : 0] S_AXI_HP0_AWSIZE;
input [2 : 0] S_AXI_HP0_ARPROT;
input [2 : 0] S_AXI_HP0_AWPROT;
input [31 : 0] S_AXI_HP0_ARADDR;
input [31 : 0] S_AXI_HP0_AWADDR;
input [3 : 0] S_AXI_HP0_ARCACHE;
input [3 : 0] S_AXI_HP0_ARLEN;
input [3 : 0] S_AXI_HP0_ARQOS;
input [3 : 0] S_AXI_HP0_AWCACHE;
input [3 : 0] S_AXI_HP0_AWLEN;
input [3 : 0] S_AXI_HP0_AWQOS;
input [5 : 0] S_AXI_HP0_ARID;
input [5 : 0] S_AXI_HP0_AWID;
input [5 : 0] S_AXI_HP0_WID;
input [31 : 0] S_AXI_HP0_WDATA;
input [3 : 0] S_AXI_HP0_WSTRB;
input [1 : 0] IRQ_F2P;
output FCLK_CLK0;
output FCLK_CLK1;
output FCLK_CLK2;
output FCLK_RESET0_N;
output FCLK_RESET1_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_5_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(1),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(32),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(100.0),
.C_FCLK_CLK1_FREQ(50.0),
.C_FCLK_CLK2_FREQ(20.0),
.C_FCLK_CLK3_FREQ(10.0),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY),
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY),
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID),
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST),
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID),
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY),
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP),
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP),
.S_AXI_HP0_BID(S_AXI_HP0_BID),
.S_AXI_HP0_RID(S_AXI_HP0_RID),
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA),
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK),
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID),
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID),
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY),
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY),
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST),
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID),
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST),
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK),
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE),
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST),
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK),
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE),
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT),
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT),
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR),
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR),
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE),
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN),
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS),
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE),
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN),
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS),
.S_AXI_HP0_ARID(S_AXI_HP0_ARID),
.S_AXI_HP0_AWID(S_AXI_HP0_AWID),
.S_AXI_HP0_WID(S_AXI_HP0_WID),
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA),
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(FCLK_CLK1),
.FCLK_CLK2(FCLK_CLK2),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(FCLK_RESET1_N),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(IRQ_F2P),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
`timescale 1ns / 1ps
// @module
// when timing clock match real clock, start these flow leds
// @input
// power: flow leds logical power
// sig_ring: signal for starting running flow leds
// sig_step: flow speed
// @output
// alarm_light: bind to FPGA board
module flow_led
#(parameter LEN = 5, NUM = 5)
(
input power,
input sig_ring,
input sig_step,
output reg [(NUM-1):0] alarm_light
);
reg [31:0] count;
// 1: representation for ring on
// 0: representaion for ring off
reg alarm;
initial begin
alarm <= 0;
count <= 0;
alarm_light <= 0;
end
always @(posedge sig_step) begin
if (power) begin
if (sig_ring) begin
count = 0;
alarm = 1;
alarm_light = 1;
end else begin
if (alarm == 1) begin
count = count + 1;
alarm_light = alarm_light * 2 ? alarm_light * 2 : 1;
end
if (count == LEN) begin
count = 0;
alarm = 0;
alarm_light = 0;
end
end
end else begin
count = 0;
alarm = 0;
alarm_light = 0;
end
end
endmodule
|
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:hls:gcd:1.0
// IP Revision: 1909171525
(* X_CORE_INFO = "gcd,Vivado 2018.2" *)
(* CHECK_LICENSE_TYPE = "gcd_block_design_gcd_0_1,gcd,{}" *)
(* CORE_GENERATION_INFO = "gcd_block_design_gcd_0_1,gcd,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=hls,x_ipName=gcd,x_ipVersion=1.0,x_ipCoreRevision=1909171525,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_GCD_BUS_ADDR_WIDTH=6,C_S_AXI_GCD_BUS_DATA_WIDTH=32}" *)
(* IP_DEFINITION_SOURCE = "HLS" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module gcd_block_design_gcd_0_1 (
s_axi_gcd_bus_AWADDR,
s_axi_gcd_bus_AWVALID,
s_axi_gcd_bus_AWREADY,
s_axi_gcd_bus_WDATA,
s_axi_gcd_bus_WSTRB,
s_axi_gcd_bus_WVALID,
s_axi_gcd_bus_WREADY,
s_axi_gcd_bus_BRESP,
s_axi_gcd_bus_BVALID,
s_axi_gcd_bus_BREADY,
s_axi_gcd_bus_ARADDR,
s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_ARREADY,
s_axi_gcd_bus_RDATA,
s_axi_gcd_bus_RRESP,
s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_RREADY,
ap_clk,
ap_rst_n,
interrupt
);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWADDR" *)
input wire [5 : 0] s_axi_gcd_bus_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWVALID" *)
input wire s_axi_gcd_bus_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWREADY" *)
output wire s_axi_gcd_bus_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WDATA" *)
input wire [31 : 0] s_axi_gcd_bus_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WSTRB" *)
input wire [3 : 0] s_axi_gcd_bus_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WVALID" *)
input wire s_axi_gcd_bus_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WREADY" *)
output wire s_axi_gcd_bus_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BRESP" *)
output wire [1 : 0] s_axi_gcd_bus_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BVALID" *)
output wire s_axi_gcd_bus_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BREADY" *)
input wire s_axi_gcd_bus_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARADDR" *)
input wire [5 : 0] s_axi_gcd_bus_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARVALID" *)
input wire s_axi_gcd_bus_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARREADY" *)
output wire s_axi_gcd_bus_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RDATA" *)
output wire [31 : 0] s_axi_gcd_bus_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RRESP" *)
output wire [1 : 0] s_axi_gcd_bus_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RVALID" *)
output wire s_axi_gcd_bus_RVALID;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_gcd_bus, ADDR_WIDTH 6, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, \
ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RREADY" *)
input wire s_axi_gcd_bus_RREADY;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_gcd_bus, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN \
gcd_block_design_processing_system7_0_2_FCLK_CLK0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
input wire ap_clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ap_rst_n RST" *)
input wire ap_rst_n;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT" *)
output wire interrupt;
gcd #(
.C_S_AXI_GCD_BUS_ADDR_WIDTH(6),
.C_S_AXI_GCD_BUS_DATA_WIDTH(32)
) inst (
.s_axi_gcd_bus_AWADDR(s_axi_gcd_bus_AWADDR),
.s_axi_gcd_bus_AWVALID(s_axi_gcd_bus_AWVALID),
.s_axi_gcd_bus_AWREADY(s_axi_gcd_bus_AWREADY),
.s_axi_gcd_bus_WDATA(s_axi_gcd_bus_WDATA),
.s_axi_gcd_bus_WSTRB(s_axi_gcd_bus_WSTRB),
.s_axi_gcd_bus_WVALID(s_axi_gcd_bus_WVALID),
.s_axi_gcd_bus_WREADY(s_axi_gcd_bus_WREADY),
.s_axi_gcd_bus_BRESP(s_axi_gcd_bus_BRESP),
.s_axi_gcd_bus_BVALID(s_axi_gcd_bus_BVALID),
.s_axi_gcd_bus_BREADY(s_axi_gcd_bus_BREADY),
.s_axi_gcd_bus_ARADDR(s_axi_gcd_bus_ARADDR),
.s_axi_gcd_bus_ARVALID(s_axi_gcd_bus_ARVALID),
.s_axi_gcd_bus_ARREADY(s_axi_gcd_bus_ARREADY),
.s_axi_gcd_bus_RDATA(s_axi_gcd_bus_RDATA),
.s_axi_gcd_bus_RRESP(s_axi_gcd_bus_RRESP),
.s_axi_gcd_bus_RVALID(s_axi_gcd_bus_RVALID),
.s_axi_gcd_bus_RREADY(s_axi_gcd_bus_RREADY),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.interrupt(interrupt)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
/// ////
/// Wishbone arbiter, burst-compatible ////
/// ////
/// Simple arbiter, multi-master, multi-slave with default slave ////
/// for chaining with peripheral arbiter ////
/// ////
/// Julius Baxter, [email protected] ////
/// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "orpsoc-defines.v"
// 2 Masters, a few slaves
module arbiter_dbus
(
// or1200 data master
// Wishbone Master interface
wbm0_adr_o,
wbm0_dat_o,
wbm0_sel_o,
wbm0_we_o,
wbm0_cyc_o,
wbm0_stb_o,
wbm0_cti_o,
wbm0_bte_o,
wbm0_dat_i,
wbm0_ack_i,
wbm0_err_i,
wbm0_rty_i,
// or1200 debug master
// Wishbone Master interface
wbm1_adr_o,
wbm1_dat_o,
wbm1_sel_o,
wbm1_we_o,
wbm1_cyc_o,
wbm1_stb_o,
wbm1_cti_o,
wbm1_bte_o,
wbm1_dat_i,
wbm1_ack_i,
wbm1_err_i,
wbm1_rty_i,
// Slave one
// Wishbone Slave interface
wbs0_adr_i,
wbs0_dat_i,
wbs0_sel_i,
wbs0_we_i,
wbs0_cyc_i,
wbs0_stb_i,
wbs0_cti_i,
wbs0_bte_i,
wbs0_dat_o,
wbs0_ack_o,
wbs0_err_o,
wbs0_rty_o,
// Slave two
// Wishbone Slave interface
wbs1_adr_i,
wbs1_dat_i,
wbs1_sel_i,
wbs1_we_i,
wbs1_cyc_i,
wbs1_stb_i,
wbs1_cti_i,
wbs1_bte_i,
wbs1_dat_o,
wbs1_ack_o,
wbs1_err_o,
wbs1_rty_o,
// Slave three
// Wishbone Slave interface
wbs2_adr_i,
wbs2_dat_i,
wbs2_sel_i,
wbs2_we_i,
wbs2_cyc_i,
wbs2_stb_i,
wbs2_cti_i,
wbs2_bte_i,
wbs2_dat_o,
wbs2_ack_o,
wbs2_err_o,
wbs2_rty_o,
/*
// Slave four
// Wishbone Slave interface
wbs3_adr_i,
wbs3_dat_i,
wbs3_sel_i,
wbs3_we_i,
wbs3_cyc_i,
wbs3_stb_i,
wbs3_cti_i,
wbs3_bte_i,
wbs3_dat_o,
wbs3_ack_o,
wbs3_err_o,
wbs3_rty_o,
// Slave five
// Wishbone Slave interface
wbs4_adr_i,
wbs4_dat_i,
wbs4_sel_i,
wbs4_we_i,
wbs4_cyc_i,
wbs4_stb_i,
wbs4_cti_i,
wbs4_bte_i,
wbs4_dat_o,
wbs4_ack_o,
wbs4_err_o,
wbs4_rty_o,
// Slave six
// Wishbone Slave interface
wbs5_adr_i,
wbs5_dat_i,
wbs5_sel_i,
wbs5_we_i,
wbs5_cyc_i,
wbs5_stb_i,
wbs5_cti_i,
wbs5_bte_i,
wbs5_dat_o,
wbs5_ack_o,
wbs5_err_o,
wbs5_rty_o,
// Slave seven
// Wishbone Slave interface
wbs6_adr_i,
wbs6_dat_i,
wbs6_sel_i,
wbs6_we_i,
wbs6_cyc_i,
wbs6_stb_i,
wbs6_cti_i,
wbs6_bte_i,
wbs6_dat_o,
wbs6_ack_o,
wbs6_err_o,
wbs6_rty_o,
// Slave eight
// Wishbone Slave interface
wbs7_adr_i,
wbs7_dat_i,
wbs7_sel_i,
wbs7_we_i,
wbs7_cyc_i,
wbs7_stb_i,
wbs7_cti_i,
wbs7_bte_i,
wbs7_dat_o,
wbs7_ack_o,
wbs7_err_o,
wbs7_rty_o,
// Slave nine
// Wishbone Slave interface
wbs8_adr_i,
wbs8_dat_i,
wbs8_sel_i,
wbs8_we_i,
wbs8_cyc_i,
wbs8_stb_i,
wbs8_cti_i,
wbs8_bte_i,
wbs8_dat_o,
wbs8_ack_o,
wbs8_err_o,
wbs8_rty_o,
// Slave ten
// Wishbone Slave interface
wbs9_adr_i,
wbs9_dat_i,
wbs9_sel_i,
wbs9_we_i,
wbs9_cyc_i,
wbs9_stb_i,
wbs9_cti_i,
wbs9_bte_i,
wbs9_dat_o,
wbs9_ack_o,
wbs9_err_o,
wbs9_rty_o,
// Slave eleven
// Wishbone Slave interface
wbs10_adr_i,
wbs10_dat_i,
wbs10_sel_i,
wbs10_we_i,
wbs10_cyc_i,
wbs10_stb_i,
wbs10_cti_i,
wbs10_bte_i,
wbs10_dat_o,
wbs10_ack_o,
wbs10_err_o,
wbs10_rty_o,
// Slave twelve
// Wishbone Slave interface
wbs11_adr_i,
wbs11_dat_i,
wbs11_sel_i,
wbs11_we_i,
wbs11_cyc_i,
wbs11_stb_i,
wbs11_cti_i,
wbs11_bte_i,
wbs11_dat_o,
wbs11_ack_o,
wbs11_err_o,
wbs11_rty_o,
// Slave thirteen
// Wishbone Slave interface
wbs12_adr_i,
wbs12_dat_i,
wbs12_sel_i,
wbs12_we_i,
wbs12_cyc_i,
wbs12_stb_i,
wbs12_cti_i,
wbs12_bte_i,
wbs12_dat_o,
wbs12_ack_o,
wbs12_err_o,
wbs12_rty_o,
// Slave fourteen
// Wishbone Slave interface
wbs13_adr_i,
wbs13_dat_i,
wbs13_sel_i,
wbs13_we_i,
wbs13_cyc_i,
wbs13_stb_i,
wbs13_cti_i,
wbs13_bte_i,
wbs13_dat_o,
wbs13_ack_o,
wbs13_err_o,
wbs13_rty_o,
// Slave fifteen
// Wishbone Slave interface
wbs14_adr_i,
wbs14_dat_i,
wbs14_sel_i,
wbs14_we_i,
wbs14_cyc_i,
wbs14_stb_i,
wbs14_cti_i,
wbs14_bte_i,
wbs14_dat_o,
wbs14_ack_o,
wbs14_err_o,
wbs14_rty_o,
// Slave sixteen
// Wishbone Slave interface
wbs15_adr_i,
wbs15_dat_i,
wbs15_sel_i,
wbs15_we_i,
wbs15_cyc_i,
wbs15_stb_i,
wbs15_cti_i,
wbs15_bte_i,
wbs15_dat_o,
wbs15_ack_o,
wbs15_err_o,
wbs15_rty_o,
// Slave seventeen
// Wishbone Slave interface
wbs16_adr_i,
wbs16_dat_i,
wbs16_sel_i,
wbs16_we_i,
wbs16_cyc_i,
wbs16_stb_i,
wbs16_cti_i,
wbs16_bte_i,
wbs16_dat_o,
wbs16_ack_o,
wbs16_err_o,
wbs16_rty_o,
*/
wb_clk,
wb_rst
);
parameter wb_dat_width = 32;
parameter wb_adr_width = 32;
parameter wb_addr_match_width = 8;
parameter wb_num_slaves = 2; // must also (un)comment things if changing
// Slave addresses - these should be defparam'd from top level
// Declare them as you need them
parameter slave0_adr = 0;
parameter slave1_adr = 0;
parameter slave2_adr = 0;
parameter slave3_adr = 0;
parameter slave4_adr = 0;
parameter slave5_adr = 0;
parameter slave6_adr = 0;
parameter slave7_adr = 0;
parameter slave8_adr = 0;
parameter slave9_adr = 0;
parameter slave10_adr = 0;
parameter slave11_adr = 0;
parameter slave12_adr = 0;
// Select for slave 0
`define WB_ARB_ADDR_MATCH_SEL_SLAVE0 wb_adr_width-1:wb_adr_width-4
`define WB_ARB_ADDR_MATCH_SEL wb_adr_width-1:wb_adr_width-wb_addr_match_width
input wb_clk;
input wb_rst;
// WB Master one
input [wb_adr_width-1:0] wbm0_adr_o;
input [wb_dat_width-1:0] wbm0_dat_o;
input [3:0] wbm0_sel_o;
input wbm0_we_o;
input wbm0_cyc_o;
input wbm0_stb_o;
input [2:0] wbm0_cti_o;
input [1:0] wbm0_bte_o;
output [wb_dat_width-1:0] wbm0_dat_i;
output wbm0_ack_i;
output wbm0_err_i;
output wbm0_rty_i;
input [wb_adr_width-1:0] wbm1_adr_o;
input [wb_dat_width-1:0] wbm1_dat_o;
input [3:0] wbm1_sel_o;
input wbm1_we_o;
input wbm1_cyc_o;
input wbm1_stb_o;
input [2:0] wbm1_cti_o;
input [1:0] wbm1_bte_o;
output [wb_dat_width-1:0] wbm1_dat_i;
output wbm1_ack_i;
output wbm1_err_i;
output wbm1_rty_i;
// Slave one
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs0_adr_i;
output [wb_dat_width-1:0] wbs0_dat_i;
output [3:0] wbs0_sel_i;
output wbs0_we_i;
output wbs0_cyc_i;
output wbs0_stb_i;
output [2:0] wbs0_cti_i;
output [1:0] wbs0_bte_i;
input [wb_dat_width-1:0] wbs0_dat_o;
input wbs0_ack_o;
input wbs0_err_o;
input wbs0_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs1_adr_i;
output [wb_dat_width-1:0] wbs1_dat_i;
output [3:0] wbs1_sel_i;
output wbs1_we_i;
output wbs1_cyc_i;
output wbs1_stb_i;
output [2:0] wbs1_cti_i;
output [1:0] wbs1_bte_i;
input [wb_dat_width-1:0] wbs1_dat_o;
input wbs1_ack_o;
input wbs1_err_o;
input wbs1_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs2_adr_i;
output [wb_dat_width-1:0] wbs2_dat_i;
output [3:0] wbs2_sel_i;
output wbs2_we_i;
output wbs2_cyc_i;
output wbs2_stb_i;
output [2:0] wbs2_cti_i;
output [1:0] wbs2_bte_i;
input [wb_dat_width-1:0] wbs2_dat_o;
input wbs2_ack_o;
input wbs2_err_o;
input wbs2_rty_o;
/*
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs3_adr_i;
output [wb_dat_width-1:0] wbs3_dat_i;
output [3:0] wbs3_sel_i;
output wbs3_we_i;
output wbs3_cyc_i;
output wbs3_stb_i;
output [2:0] wbs3_cti_i;
output [1:0] wbs3_bte_i;
input [wb_dat_width-1:0] wbs3_dat_o;
input wbs3_ack_o;
input wbs3_err_o;
input wbs3_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs4_adr_i;
output [wb_dat_width-1:0] wbs4_dat_i;
output [3:0] wbs4_sel_i;
output wbs4_we_i;
output wbs4_cyc_i;
output wbs4_stb_i;
output [2:0] wbs4_cti_i;
output [1:0] wbs4_bte_i;
input [wb_dat_width-1:0] wbs4_dat_o;
input wbs4_ack_o;
input wbs4_err_o;
input wbs4_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs5_adr_i;
output [wb_dat_width-1:0] wbs5_dat_i;
output [3:0] wbs5_sel_i;
output wbs5_we_i;
output wbs5_cyc_i;
output wbs5_stb_i;
output [2:0] wbs5_cti_i;
output [1:0] wbs5_bte_i;
input [wb_dat_width-1:0] wbs5_dat_o;
input wbs5_ack_o;
input wbs5_err_o;
input wbs5_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs6_adr_i;
output [wb_dat_width-1:0] wbs6_dat_i;
output [3:0] wbs6_sel_i;
output wbs6_we_i;
output wbs6_cyc_i;
output wbs6_stb_i;
output [2:0] wbs6_cti_i;
output [1:0] wbs6_bte_i;
input [wb_dat_width-1:0] wbs6_dat_o;
input wbs6_ack_o;
input wbs6_err_o;
input wbs6_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs7_adr_i;
output [wb_dat_width-1:0] wbs7_dat_i;
output [3:0] wbs7_sel_i;
output wbs7_we_i;
output wbs7_cyc_i;
output wbs7_stb_i;
output [2:0] wbs7_cti_i;
output [1:0] wbs7_bte_i;
input [wb_dat_width-1:0] wbs7_dat_o;
input wbs7_ack_o;
input wbs7_err_o;
input wbs7_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs8_adr_i;
output [wb_dat_width-1:0] wbs8_dat_i;
output [3:0] wbs8_sel_i;
output wbs8_we_i;
output wbs8_cyc_i;
output wbs8_stb_i;
output [2:0] wbs8_cti_i;
output [1:0] wbs8_bte_i;
input [wb_dat_width-1:0] wbs8_dat_o;
input wbs8_ack_o;
input wbs8_err_o;
input wbs8_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs9_adr_i;
output [wb_dat_width-1:0] wbs9_dat_i;
output [3:0] wbs9_sel_i;
output wbs9_we_i;
output wbs9_cyc_i;
output wbs9_stb_i;
output [2:0] wbs9_cti_i;
output [1:0] wbs9_bte_i;
input [wb_dat_width-1:0] wbs9_dat_o;
input wbs9_ack_o;
input wbs9_err_o;
input wbs9_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs10_adr_i;
output [wb_dat_width-1:0] wbs10_dat_i;
output [3:0] wbs10_sel_i;
output wbs10_we_i;
output wbs10_cyc_i;
output wbs10_stb_i;
output [2:0] wbs10_cti_i;
output [1:0] wbs10_bte_i;
input [wb_dat_width-1:0] wbs10_dat_o;
input wbs10_ack_o;
input wbs10_err_o;
input wbs10_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs11_adr_i;
output [wb_dat_width-1:0] wbs11_dat_i;
output [3:0] wbs11_sel_i;
output wbs11_we_i;
output wbs11_cyc_i;
output wbs11_stb_i;
output [2:0] wbs11_cti_i;
output [1:0] wbs11_bte_i;
input [wb_dat_width-1:0] wbs11_dat_o;
input wbs11_ack_o;
input wbs11_err_o;
input wbs11_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs12_adr_i;
output [wb_dat_width-1:0] wbs12_dat_i;
output [3:0] wbs12_sel_i;
output wbs12_we_i;
output wbs12_cyc_i;
output wbs12_stb_i;
output [2:0] wbs12_cti_i;
output [1:0] wbs12_bte_i;
input [wb_dat_width-1:0] wbs12_dat_o;
input wbs12_ack_o;
input wbs12_err_o;
input wbs12_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs13_adr_i;
output [wb_dat_width-1:0] wbs13_dat_i;
output [3:0] wbs13_sel_i;
output wbs13_we_i;
output wbs13_cyc_i;
output wbs13_stb_i;
output [2:0] wbs13_cti_i;
output [1:0] wbs13_bte_i;
input [wb_dat_width-1:0] wbs13_dat_o;
input wbs13_ack_o;
input wbs13_err_o;
input wbs13_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs14_adr_i;
output [wb_dat_width-1:0] wbs14_dat_i;
output [3:0] wbs14_sel_i;
output wbs14_we_i;
output wbs14_cyc_i;
output wbs14_stb_i;
output [2:0] wbs14_cti_i;
output [1:0] wbs14_bte_i;
input [wb_dat_width-1:0] wbs14_dat_o;
input wbs14_ack_o;
input wbs14_err_o;
input wbs14_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs15_adr_i;
output [wb_dat_width-1:0] wbs15_dat_i;
output [3:0] wbs15_sel_i;
output wbs15_we_i;
output wbs15_cyc_i;
output wbs15_stb_i;
output [2:0] wbs15_cti_i;
output [1:0] wbs15_bte_i;
input [wb_dat_width-1:0] wbs15_dat_o;
input wbs15_ack_o;
input wbs15_err_o;
input wbs15_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs16_adr_i;
output [wb_dat_width-1:0] wbs16_dat_i;
output [3:0] wbs16_sel_i;
output wbs16_we_i;
output wbs16_cyc_i;
output wbs16_stb_i;
output [2:0] wbs16_cti_i;
output [1:0] wbs16_bte_i;
input [wb_dat_width-1:0] wbs16_dat_o;
input wbs16_ack_o;
input wbs16_err_o;
input wbs16_rty_o;
*/
reg watchdog_err;
`ifdef ARBITER_DBUS_REGISTERING
// Registering setup:
// Masters typically register their outputs, so do the master selection and
// muxing before registering in the arbiter. Keep the common parts outside
// for code brevity.
// Master ins -> |MUX> -> these wires
wire [wb_adr_width-1:0] wbm_adr_o_w;
wire [wb_dat_width-1:0] wbm_dat_o_w;
wire [3:0] wbm_sel_o_w;
wire wbm_we_o_w;
wire wbm_cyc_o_w;
wire wbm_stb_o_w;
wire [2:0] wbm_cti_o_w;
wire [1:0] wbm_bte_o_w;
// Slave ins -> |MUX> -> these wires
wire [wb_dat_width-1:0] wbm_dat_i;
wire wbm_ack_i;
wire wbm_err_i;
wire wbm_rty_i;
// Registers after masters input mux
reg [wb_adr_width-1:0] wbm_adr_o_r;
reg [wb_dat_width-1:0] wbm_dat_o_r;
reg [3:0] wbm_sel_o_r;
reg wbm_we_o_r;
reg wbm_cyc_o_r;
reg wbm_stb_o_r;
reg [2:0] wbm_cti_o_r;
reg [1:0] wbm_bte_o_r;
// Master input mux register wires
wire [wb_adr_width-1:0] wbm_adr_o;
wire [wb_dat_width-1:0] wbm_dat_o;
wire [3:0] wbm_sel_o;
wire wbm_we_o;
wire wbm_cyc_o;
wire wbm_stb_o;
wire [2:0] wbm_cti_o;
wire [1:0] wbm_bte_o;
// Registers after slaves input mux
reg [wb_dat_width-1:0] wbm_dat_i_r;
reg wbm_ack_i_r;
reg wbm_err_i_r;
reg wbm_rty_i_r;
// Master select (MUX controls)
wire [1:0] master_sel;
// priority to wbm1, the debug master
assign master_sel[0] = wbm0_cyc_o & !wbm1_cyc_o;
assign master_sel[1] = wbm1_cyc_o;
// Master input mux, priority to debug master
assign wbm_adr_o_w = master_sel[1] ? wbm1_adr_o :
wbm0_adr_o;
assign wbm_dat_o_w = master_sel[1] ? wbm1_dat_o :
wbm0_dat_o;
assign wbm_sel_o_w = master_sel[1] ? wbm1_sel_o :
wbm0_sel_o;
assign wbm_we_o_w = master_sel[1] ? wbm1_we_o :
wbm0_we_o;
assign wbm_cyc_o_w = master_sel[1] ? wbm1_cyc_o :
wbm0_cyc_o;
assign wbm_stb_o_w = master_sel[1] ? wbm1_stb_o :
wbm0_stb_o;
assign wbm_cti_o_w = master_sel[1] ? wbm1_cti_o :
wbm0_cti_o;
assign wbm_bte_o_w = master_sel[1] ? wbm1_bte_o :
wbm0_bte_o;
// Register muxed master signals
always @(posedge wb_clk)
begin
wbm_adr_o_r <= wbm_adr_o_w;
wbm_dat_o_r <= wbm_dat_o_w;
wbm_sel_o_r <= wbm_sel_o_w;
wbm_we_o_r <= wbm_we_o_w;
wbm_cyc_o_r <= wbm_cyc_o_w;
wbm_stb_o_r <= wbm_stb_o_w & !wbm_ack_i & !wbm_ack_i_r;
wbm_cti_o_r <= wbm_cti_o_w;
wbm_bte_o_r <= wbm_bte_o_w;
wbm_dat_i_r <= wbm_dat_i;
wbm_ack_i_r <= wbm_ack_i;
wbm_err_i_r <= wbm_err_i;
wbm_rty_i_r <= wbm_rty_i;
end // always @ (posedge wb_clk)
assign wbm_adr_o = wbm_adr_o_r;
assign wbm_dat_o = wbm_dat_o_r;
assign wbm_sel_o = wbm_sel_o_r;
assign wbm_we_o = wbm_we_o_r;
assign wbm_cyc_o = wbm_cyc_o_r;
assign wbm_stb_o = wbm_stb_o_r;
assign wbm_cti_o = wbm_cti_o_r;
assign wbm_bte_o = wbm_bte_o_r;
// Master input mux, priority to debug master
assign wbm0_dat_i = wbm_dat_i_r;
assign wbm0_ack_i = wbm_ack_i_r & master_sel[0];
assign wbm0_err_i = wbm_err_i_r & master_sel[0];
assign wbm0_rty_i = wbm_rty_i_r & master_sel[0];
assign wbm1_dat_i = wbm_dat_i_r;
assign wbm1_ack_i = wbm_ack_i_r & master_sel[1];
assign wbm1_err_i = wbm_err_i_r & master_sel[1];
assign wbm1_rty_i = wbm_rty_i_r & master_sel[1];
`else // !`ifdef ARBITER_DBUS_REGISTERING
// Master input mux output wires
wire [wb_adr_width-1:0] wbm_adr_o;
wire [wb_dat_width-1:0] wbm_dat_o;
wire [3:0] wbm_sel_o;
wire wbm_we_o;
wire wbm_cyc_o;
wire wbm_stb_o;
wire [2:0] wbm_cti_o;
wire [1:0] wbm_bte_o;
// Master select
wire [1:0] master_sel;
// priority to wbm1, the debug master
assign master_sel[0] = wbm0_cyc_o & !wbm1_cyc_o;
assign master_sel[1] = wbm1_cyc_o;
// Master input mux, priority to debug master
assign wbm_adr_o = master_sel[1] ? wbm1_adr_o :
wbm0_adr_o;
assign wbm_dat_o = master_sel[1] ? wbm1_dat_o :
wbm0_dat_o;
assign wbm_sel_o = master_sel[1] ? wbm1_sel_o :
wbm0_sel_o;
assign wbm_we_o = master_sel[1] ? wbm1_we_o :
wbm0_we_o;
assign wbm_cyc_o = master_sel[1] ? wbm1_cyc_o :
wbm0_cyc_o;
assign wbm_stb_o = master_sel[1] ? wbm1_stb_o :
wbm0_stb_o;
assign wbm_cti_o = master_sel[1] ? wbm1_cti_o :
wbm0_cti_o;
assign wbm_bte_o = master_sel[1] ? wbm1_bte_o :
wbm0_bte_o;
wire [wb_dat_width-1:0] wbm_dat_i;
wire wbm_ack_i;
wire wbm_err_i;
wire wbm_rty_i;
assign wbm0_dat_i = wbm_dat_i;
assign wbm0_ack_i = wbm_ack_i & master_sel[0];
assign wbm0_err_i = wbm_err_i & master_sel[0];
assign wbm0_rty_i = wbm_rty_i & master_sel[0];
assign wbm1_dat_i = wbm_dat_i;
assign wbm1_ack_i = wbm_ack_i & master_sel[1];
assign wbm1_err_i = wbm_err_i & master_sel[1];
assign wbm1_rty_i = wbm_rty_i & master_sel[1];
`endif // !`ifdef ARBITER_DBUS_REGISTERING
// Slave select wire
wire [wb_num_slaves-1:0] wb_slave_sel;
reg [wb_num_slaves-1:0] wb_slave_sel_r;
// Register wb_slave_sel_r to break combinatorial loop when selecting default
// slave
always @(posedge wb_clk)
wb_slave_sel_r <= wb_slave_sel;
// Slave out mux in wires
wire [wb_dat_width-1:0] wbs_dat_o_mux_i [0:wb_num_slaves-1];
wire wbs_ack_o_mux_i [0:wb_num_slaves-1];
wire wbs_err_o_mux_i [0:wb_num_slaves-1];
wire wbs_rty_o_mux_i [0:wb_num_slaves-1];
//
// Slave selects
//
assign wb_slave_sel[0] = wbm_adr_o[31:28] == slave0_adr | wbm_adr_o[31:28] == 4'hf; // Special case, point all reads to ROM address to here
assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr;
// Auto select last slave when others are not selected
assign wb_slave_sel[2] = !(wb_slave_sel_r[0] | wb_slave_sel_r[1]);
/*
assign wb_slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave2_adr;
assign wb_slave_sel[3] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave3_adr;
assign wb_slave_sel[4] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave4_adr;
assign wb_slave_sel[5] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave5_adr;
assign wb_slave_sel[6] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave6_adr;
assign wb_slave_sel[7] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave7_adr;
assign wb_slave_sel[8] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave8_adr;
assign wb_slave_sel[9] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave9_adr;
assign wb_slave_sel[10] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave10_adr;
assign wb_slave_sel[11] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave11_adr;
assign wb_slave_sel[12] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave12_adr;
assign wb_slave_sel[13] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave13_adr;
assign wb_slave_sel[14] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave14_adr;
assign wb_slave_sel[15] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave15_adr;
assign wb_slave_sel[16] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave16_adr;
*/
`ifdef ARBITER_DBUS_WATCHDOG
reg [`ARBITER_DBUS_WATCHDOG_TIMER_WIDTH:0] watchdog_timer;
reg wbm_stb_r; // Register strobe
wire wbm_stb_edge; // Detect its edge
always @(posedge wb_clk)
wbm_stb_r <= wbm_stb_o;
assign wbm_stb_edge = (wbm_stb_o & !wbm_stb_r);
// Counter logic
always @(posedge wb_clk)
if (wb_rst) watchdog_timer <= 0;
else if (wbm_ack_i) // When we see an ack, turn off timer
watchdog_timer <= 0;
else if (wbm_stb_edge) // New access means start timer again
watchdog_timer <= 1;
else if (|watchdog_timer) // Continue counting if counter > 0
watchdog_timer <= watchdog_timer + 1;
always @(posedge wb_clk)
watchdog_err <= (&watchdog_timer);
`else // !`ifdef ARBITER_DBUS_WATCHDOG
always @(posedge wb_clk)
watchdog_err <= 0;
`endif // !`ifdef ARBITER_DBUS_WATCHDOG
// Slave 0 inputs
assign wbs0_adr_i = wbm_adr_o;
assign wbs0_dat_i = wbm_dat_o;
assign wbs0_sel_i = wbm_sel_o;
assign wbs0_cyc_i = wbm_cyc_o & wb_slave_sel_r[0];
assign wbs0_stb_i = wbm_stb_o & wb_slave_sel_r[0];
assign wbs0_we_i = wbm_we_o;
assign wbs0_cti_i = wbm_cti_o;
assign wbs0_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[0] = wbs0_dat_o;
assign wbs_ack_o_mux_i[0] = wbs0_ack_o & wb_slave_sel_r[0];
assign wbs_err_o_mux_i[0] = wbs0_err_o & wb_slave_sel_r[0];
assign wbs_rty_o_mux_i[0] = wbs0_rty_o & wb_slave_sel_r[0];
// Slave 1 inputs
assign wbs1_adr_i = wbm_adr_o;
assign wbs1_dat_i = wbm_dat_o;
assign wbs1_sel_i = wbm_sel_o;
assign wbs1_cyc_i = wbm_cyc_o & wb_slave_sel_r[1];
assign wbs1_stb_i = wbm_stb_o & wb_slave_sel_r[1];
assign wbs1_we_i = wbm_we_o;
assign wbs1_cti_i = wbm_cti_o;
assign wbs1_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[1] = wbs1_dat_o;
assign wbs_ack_o_mux_i[1] = wbs1_ack_o & wb_slave_sel_r[1];
assign wbs_err_o_mux_i[1] = wbs1_err_o & wb_slave_sel_r[1];
assign wbs_rty_o_mux_i[1] = wbs1_rty_o & wb_slave_sel_r[1];
// Slave 2 inputs
assign wbs2_adr_i = wbm_adr_o;
assign wbs2_dat_i = wbm_dat_o;
assign wbs2_sel_i = wbm_sel_o;
assign wbs2_cyc_i = wbm_cyc_o & wb_slave_sel_r[2];
assign wbs2_stb_i = wbm_stb_o & wb_slave_sel_r[2];
assign wbs2_we_i = wbm_we_o;
assign wbs2_cti_i = wbm_cti_o;
assign wbs2_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[2] = wbs2_dat_o;
assign wbs_ack_o_mux_i[2] = wbs2_ack_o & wb_slave_sel_r[2];
assign wbs_err_o_mux_i[2] = wbs2_err_o & wb_slave_sel_r[2];
assign wbs_rty_o_mux_i[2] = wbs2_rty_o & wb_slave_sel_r[2];
/*
// Slave 3 inputs
assign wbs3_adr_i = wbm_adr_o;
assign wbs3_dat_i = wbm_dat_o;
assign wbs3_sel_i = wbm_sel_o;
assign wbs3_cyc_i = wbm_cyc_o & wb_slave_sel_r[3];
assign wbs3_stb_i = wbm_stb_o & wb_slave_sel_r[3];
assign wbs3_we_i = wbm_we_o;
assign wbs3_cti_i = wbm_cti_o;
assign wbs3_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[3] = wbs3_dat_o;
assign wbs_ack_o_mux_i[3] = wbs3_ack_o & wb_slave_sel_r[3];
assign wbs_err_o_mux_i[3] = wbs3_err_o & wb_slave_sel_r[3];
assign wbs_rty_o_mux_i[3] = wbs3_rty_o & wb_slave_sel_r[3];
// Slave 4 inputs
assign wbs4_adr_i = wbm_adr_o;
assign wbs4_dat_i = wbm_dat_o;
assign wbs4_sel_i = wbm_sel_o;
assign wbs4_cyc_i = wbm_cyc_o & wb_slave_sel_r[4];
assign wbs4_stb_i = wbm_stb_o & wb_slave_sel_r[4];
assign wbs4_we_i = wbm_we_o;
assign wbs4_cti_i = wbm_cti_o;
assign wbs4_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[4] = wbs4_dat_o;
assign wbs_ack_o_mux_i[4] = wbs4_ack_o & wb_slave_sel_r[4];
assign wbs_err_o_mux_i[4] = wbs4_err_o & wb_slave_sel_r[4];
assign wbs_rty_o_mux_i[4] = wbs4_rty_o & wb_slave_sel_r[4];
// Slave 5 inputs
assign wbs5_adr_i = wbm_adr_o;
assign wbs5_dat_i = wbm_dat_o;
assign wbs5_sel_i = wbm_sel_o;
assign wbs5_cyc_i = wbm_cyc_o & wb_slave_sel_r[5];
assign wbs5_stb_i = wbm_stb_o & wb_slave_sel_r[5];
assign wbs5_we_i = wbm_we_o;
assign wbs5_cti_i = wbm_cti_o;
assign wbs5_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[5] = wbs5_dat_o;
assign wbs_ack_o_mux_i[5] = wbs5_ack_o & wb_slave_sel_r[5];
assign wbs_err_o_mux_i[5] = wbs5_err_o & wb_slave_sel_r[5];
assign wbs_rty_o_mux_i[5] = wbs5_rty_o & wb_slave_sel_r[5];
// Slave 6 inputs
assign wbs6_adr_i = wbm_adr_o;
assign wbs6_dat_i = wbm_dat_o;
assign wbs6_sel_i = wbm_sel_o;
assign wbs6_cyc_i = wbm_cyc_o & wb_slave_sel_r[6];
assign wbs6_stb_i = wbm_stb_o & wb_slave_sel_r[6];
assign wbs6_we_i = wbm_we_o;
assign wbs6_cti_i = wbm_cti_o;
assign wbs6_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[6] = wbs6_dat_o;
assign wbs_ack_o_mux_i[6] = wbs6_ack_o & wb_slave_sel_r[6];
assign wbs_err_o_mux_i[6] = wbs6_err_o & wb_slave_sel_r[6];
assign wbs_rty_o_mux_i[6] = wbs6_rty_o & wb_slave_sel_r[6];
// Slave 7 inputs
assign wbs7_adr_i = wbm_adr_o;
assign wbs7_dat_i = wbm_dat_o;
assign wbs7_sel_i = wbm_sel_o;
assign wbs7_cyc_i = wbm_cyc_o & wb_slave_sel_r[7];
assign wbs7_stb_i = wbm_stb_o & wb_slave_sel_r[7];
assign wbs7_we_i = wbm_we_o;
assign wbs7_cti_i = wbm_cti_o;
assign wbs7_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[7] = wbs7_dat_o;
assign wbs_ack_o_mux_i[7] = wbs7_ack_o & wb_slave_sel_r[7];
assign wbs_err_o_mux_i[7] = wbs7_err_o & wb_slave_sel_r[7];
assign wbs_rty_o_mux_i[7] = wbs7_rty_o & wb_slave_sel_r[7];
// Slave 8 inputs
assign wbs8_adr_i = wbm_adr_o;
assign wbs8_dat_i = wbm_dat_o;
assign wbs8_sel_i = wbm_sel_o;
assign wbs8_cyc_i = wbm_cyc_o & wb_slave_sel_r[8];
assign wbs8_stb_i = wbm_stb_o & wb_slave_sel_r[8];
assign wbs8_we_i = wbm_we_o;
assign wbs8_cti_i = wbm_cti_o;
assign wbs8_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[8] = wbs8_dat_o;
assign wbs_ack_o_mux_i[8] = wbs8_ack_o & wb_slave_sel_r[8];
assign wbs_err_o_mux_i[8] = wbs8_err_o & wb_slave_sel_r[8];
assign wbs_rty_o_mux_i[8] = wbs8_rty_o & wb_slave_sel_r[8];
// Slave 9 inputs
assign wbs9_adr_i = wbm_adr_o;
assign wbs9_dat_i = wbm_dat_o;
assign wbs9_sel_i = wbm_sel_o;
assign wbs9_cyc_i = wbm_cyc_o & wb_slave_sel_r[9];
assign wbs9_stb_i = wbm_stb_o & wb_slave_sel_r[9];
assign wbs9_we_i = wbm_we_o;
assign wbs9_cti_i = wbm_cti_o;
assign wbs9_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[9] = wbs9_dat_o;
assign wbs_ack_o_mux_i[9] = wbs9_ack_o & wb_slave_sel_r[9];
assign wbs_err_o_mux_i[9] = wbs9_err_o & wb_slave_sel_r[9];
assign wbs_rty_o_mux_i[9] = wbs9_rty_o & wb_slave_sel_r[9];
// Slave 10 inputs
assign wbs10_adr_i = wbm_adr_o;
assign wbs10_dat_i = wbm_dat_o;
assign wbs10_sel_i = wbm_sel_o;
assign wbs10_cyc_i = wbm_cyc_o & wb_slave_sel_r[10];
assign wbs10_stb_i = wbm_stb_o & wb_slave_sel_r[10];
assign wbs10_we_i = wbm_we_o;
assign wbs10_cti_i = wbm_cti_o;
assign wbs10_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[10] = wbs10_dat_o;
assign wbs_ack_o_mux_i[10] = wbs10_ack_o & wb_slave_sel_r[10];
assign wbs_err_o_mux_i[10] = wbs10_err_o & wb_slave_sel_r[10];
assign wbs_rty_o_mux_i[10] = wbs10_rty_o & wb_slave_sel_r[10];
// Slave 11 inputs
assign wbs11_adr_i = wbm_adr_o;
assign wbs11_dat_i = wbm_dat_o;
assign wbs11_sel_i = wbm_sel_o;
assign wbs11_cyc_i = wbm_cyc_o & wb_slave_sel_r[11];
assign wbs11_stb_i = wbm_stb_o & wb_slave_sel_r[11];
assign wbs11_we_i = wbm_we_o;
assign wbs11_cti_i = wbm_cti_o;
assign wbs11_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[11] = wbs11_dat_o;
assign wbs_ack_o_mux_i[11] = wbs11_ack_o & wb_slave_sel_r[11];
assign wbs_err_o_mux_i[11] = wbs11_err_o & wb_slave_sel_r[11];
assign wbs_rty_o_mux_i[11] = wbs11_rty_o & wb_slave_sel_r[11];
// Slave 12 inputs
assign wbs12_adr_i = wbm_adr_o;
assign wbs12_dat_i = wbm_dat_o;
assign wbs12_sel_i = wbm_sel_o;
assign wbs12_cyc_i = wbm_cyc_o & wb_slave_sel_r[12];
assign wbs12_stb_i = wbm_stb_o & wb_slave_sel_r[12];
assign wbs12_we_i = wbm_we_o;
assign wbs12_cti_i = wbm_cti_o;
assign wbs12_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[12] = wbs12_dat_o;
assign wbs_ack_o_mux_i[12] = wbs12_ack_o & wb_slave_sel_r[12];
assign wbs_err_o_mux_i[12] = wbs12_err_o & wb_slave_sel_r[12];
assign wbs_rty_o_mux_i[12] = wbs12_rty_o & wb_slave_sel_r[12];
// Slave 13 inputs
assign wbs13_adr_i = wbm_adr_o;
assign wbs13_dat_i = wbm_dat_o;
assign wbs13_sel_i = wbm_sel_o;
assign wbs13_cyc_i = wbm_cyc_o & wb_slave_sel_r[13];
assign wbs13_stb_i = wbm_stb_o & wb_slave_sel_r[13];
assign wbs13_we_i = wbm_we_o;
assign wbs13_cti_i = wbm_cti_o;
assign wbs13_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[13] = wbs13_dat_o;
assign wbs_ack_o_mux_i[13] = wbs13_ack_o & wb_slave_sel_r[13];
assign wbs_err_o_mux_i[13] = wbs13_err_o & wb_slave_sel_r[13];
assign wbs_rty_o_mux_i[13] = wbs13_rty_o & wb_slave_sel_r[13];
// Slave 14 inputs
assign wbs14_adr_i = wbm_adr_o;
assign wbs14_dat_i = wbm_dat_o;
assign wbs14_sel_i = wbm_sel_o;
assign wbs14_cyc_i = wbm_cyc_o & wb_slave_sel_r[14];
assign wbs14_stb_i = wbm_stb_o & wb_slave_sel_r[14];
assign wbs14_we_i = wbm_we_o;
assign wbs14_cti_i = wbm_cti_o;
assign wbs14_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[14] = wbs14_dat_o;
assign wbs_ack_o_mux_i[14] = wbs14_ack_o & wb_slave_sel_r[14];
assign wbs_err_o_mux_i[14] = wbs14_err_o & wb_slave_sel_r[14];
assign wbs_rty_o_mux_i[14] = wbs14_rty_o & wb_slave_sel_r[14];
// Slave 15 inputs
assign wbs15_adr_i = wbm_adr_o;
assign wbs15_dat_i = wbm_dat_o;
assign wbs15_sel_i = wbm_sel_o;
assign wbs15_cyc_i = wbm_cyc_o & wb_slave_sel_r[15];
assign wbs15_stb_i = wbm_stb_o & wb_slave_sel_r[15];
assign wbs15_we_i = wbm_we_o;
assign wbs15_cti_i = wbm_cti_o;
assign wbs15_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[15] = wbs15_dat_o;
assign wbs_ack_o_mux_i[15] = wbs15_ack_o & wb_slave_sel_r[15];
assign wbs_err_o_mux_i[15] = wbs15_err_o & wb_slave_sel_r[15];
assign wbs_rty_o_mux_i[15] = wbs15_rty_o & wb_slave_sel_r[15];
// Slave 16 inputs
assign wbs16_adr_i = wbm_adr_o;
assign wbs16_dat_i = wbm_dat_o;
assign wbs16_sel_i = wbm_sel_o;
assign wbs16_cyc_i = wbm_cyc_o & wb_slave_sel_r[16];
assign wbs16_stb_i = wbm_stb_o & wb_slave_sel_r[16];
assign wbs16_we_i = wbm_we_o;
assign wbs16_cti_i = wbm_cti_o;
assign wbs16_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[16] = wbs16_dat_o;
assign wbs_ack_o_mux_i[16] = wbs16_ack_o & wb_slave_sel_r[16];
assign wbs_err_o_mux_i[16] = wbs16_err_o & wb_slave_sel_r[16];
assign wbs_rty_o_mux_i[16] = wbs16_rty_o & wb_slave_sel_r[16];
*/
// Master out mux from slave in data
assign wbm_dat_i = wb_slave_sel_r[0] ? wbs_dat_o_mux_i[0] :
wb_slave_sel_r[1] ? wbs_dat_o_mux_i[1] :
wb_slave_sel_r[2] ? wbs_dat_o_mux_i[2] :
/* wb_slave_sel_r[3] ? wbs_dat_o_mux_i[3] :
wb_slave_sel_r[4] ? wbs_dat_o_mux_i[4] :
wb_slave_sel_r[5] ? wbs_dat_o_mux_i[5] :
wb_slave_sel_r[6] ? wbs_dat_o_mux_i[6] :
wb_slave_sel_r[7] ? wbs_dat_o_mux_i[7] :
wb_slave_sel_r[8] ? wbs_dat_o_mux_i[8] :
wb_slave_sel_r[9] ? wbs_dat_o_mux_i[9] :
wb_slave_sel_r[10] ? wbs_dat_o_mux_i[10] :
wb_slave_sel_r[11] ? wbs_dat_o_mux_i[11] :
wb_slave_sel_r[12] ? wbs_dat_o_mux_i[12] :
wb_slave_sel_r[13] ? wbs_dat_o_mux_i[13] :
wb_slave_sel_r[14] ? wbs_dat_o_mux_i[14] :
wb_slave_sel_r[15] ? wbs_dat_o_mux_i[15] :
wb_slave_sel_r[16] ? wbs_dat_o_mux_i[16] :
*/
wbs_dat_o_mux_i[0];
// Master out acks, or together
assign wbm_ack_i = wbs_ack_o_mux_i[0] |
wbs_ack_o_mux_i[1] |
wbs_ack_o_mux_i[2] /*|
wbs_ack_o_mux_i[3] |
wbs_ack_o_mux_i[4] |
wbs_ack_o_mux_i[5] |
wbs_ack_o_mux_i[6] |
wbs_ack_o_mux_i[7] |
wbs_ack_o_mux_i[8] |
wbs_ack_o_mux_i[9] |
wbs_ack_o_mux_i[10] |
wbs_ack_o_mux_i[11] |
wbs_ack_o_mux_i[12] |
wbs_ack_o_mux_i[13] |
wbs_ack_o_mux_i[14] |
wbs_ack_o_mux_i[15] |
wbs_ack_o_mux_i[16] */
;
assign wbm_err_i = wbs_err_o_mux_i[0] |
wbs_err_o_mux_i[1] |
wbs_err_o_mux_i[2] |/*
wbs_err_o_mux_i[3] |
wbs_err_o_mux_i[4] |
wbs_err_o_mux_i[5] |
wbs_err_o_mux_i[6] |
wbs_err_o_mux_i[7] |
wbs_err_o_mux_i[8] |
wbs_err_o_mux_i[9] |
wbs_err_o_mux_i[10] |
wbs_err_o_mux_i[11] |
wbs_err_o_mux_i[12] |
wbs_err_o_mux_i[13] |
wbs_err_o_mux_i[14] |
wbs_err_o_mux_i[15] |
wbs_err_o_mux_i[16] |*/
watchdog_err ;
assign wbm_rty_i = wbs_rty_o_mux_i[0] |
wbs_rty_o_mux_i[1] |
wbs_rty_o_mux_i[2] /*|
wbs_rty_o_mux_i[3] |
wbs_rty_o_mux_i[4] |
wbs_rty_o_mux_i[5] |
wbs_rty_o_mux_i[6] |
wbs_rty_o_mux_i[7] |
wbs_rty_o_mux_i[8] |
wbs_rty_o_mux_i[9] |
wbs_rty_o_mux_i[10] |
wbs_rty_o_mux_i[11] |
wbs_rty_o_mux_i[12] |
wbs_rty_o_mux_i[13] |
wbs_rty_o_mux_i[14] |
wbs_rty_o_mux_i[15] |
wbs_rty_o_mux_i[16]*/;
endmodule // arbiter_dbus
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file gc_command_fifo.v when simulating
// the core, gc_command_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module gc_command_fifo(
clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty,
data_count,
prog_full
);
input clk;
input rst;
input [28 : 0] din;
input wr_en;
input rd_en;
output [28 : 0] dout;
output full;
output empty;
output [5 : 0] data_count;
output prog_full;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(6),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(29),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(29),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(1),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(1),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(6),
.C_RD_DEPTH(32),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(5),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(6),
.C_WR_DEPTH(32),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(5),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.CLK(clk),
.RST(rst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.DATA_COUNT(data_count),
.PROG_FULL(prog_full),
.BACKUP(),
.BACKUP_MARKER(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
(* Copyright (c) 2008-2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import List.
Require Import CpdtTactics.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* end hide *)
(** %\part{Basic Programming and Proving}
\chapter{Introducing Inductive Types}% *)
(** The logical foundation of Coq is the Calculus of Inductive Constructions, or CIC. In a sense, CIC is built from just two relatively straightforward features: function types and inductive types. From this modest foundation, we can prove essentially all of the theorems of math and carry out effectively all program verifications, with enough effort expended. This chapter introduces induction and recursion for functional programming in Coq. Most of our examples reproduce functionality from the Coq standard library, and I have tried to copy the standard library's choices of identifiers, where possible, so many of the definitions here are already available in the default Coq environment.
The last chapter took a deep dive into some of the more advanced Coq features, to highlight the unusual approach that I advocate in this book. However, from this point on, we will rewind and go back to basics, presenting the relevant features of Coq in a more bottom-up manner. A useful first step is a discussion of the differences and relationships between proofs and programs in Coq. *)
(** * Proof Terms *)
(** Mainstream presentations of mathematics treat proofs as objects that exist outside of the universe of mathematical objects. However, for a variety of reasoning tasks, it is convenient to encode proofs, traditional mathematical objects, and programs within a single formal language. Validity checks on mathematical objects are useful in any setting, to catch typos and other uninteresting errors. The benefits of static typing for programs are widely recognized, and Coq brings those benefits to both mathematical objects and programs via a uniform mechanism. In fact, from this point on, we will not bother to distinguish between programs and mathematical objects. Many mathematical formalisms are most easily encoded in terms of programs.
Proofs are fundamentally different from programs, because any two proofs of a theorem are considered equivalent, from a formal standpoint if not from an engineering standpoint. However, we can use the same type-checking technology to check proofs as we use to validate our programs. This is the%\index{Curry-Howard correspondence}% _Curry-Howard correspondence_ %\cite{Curry,Howard}%, an approach for relating proofs and programs. We represent mathematical theorems as types, such that a theorem's proofs are exactly those programs that type-check at the corresponding type.
The last chapter's example already snuck in an instance of Curry-Howard. We used the token [->] to stand for both function types and logical implications. One reasonable conclusion upon seeing this might be that some fancy overloading of notations is at work. In fact, functions and implications are precisely identical according to Curry-Howard! That is, they are just two ways of describing the same computational phenomenon.
A short demonstration should explain how this can be. The identity function over the natural numbers is certainly not a controversial program. *)
Check (fun x : nat => x).
(** [: nat -> nat] *)
(** %\smallskip{}%Consider this alternate program, which is almost identical to the last one. *)
Check (fun x : True => x).
(** [: True -> True] *)
(** %\smallskip{}%The identity program is interpreted as a proof that %\index{Gallina terms!True}%[True], the always-true proposition, implies itself! What we see is that Curry-Howard interprets implications as functions, where an input is a proposition being assumed and an output is a proposition being deduced. This intuition is not too far from a common one for informal theorem proving, where we might already think of an implication proof as a process for transforming a hypothesis into a conclusion.
There are also more primitive proof forms available. For instance, the term %\index{Gallina terms!I}%[I] is the single proof of [True], applicable in any context. *)
Check I.
(** [: True] *)
(** %\smallskip{}%With [I], we can prove another simple propositional theorem. *)
Check (fun _ : False => I).
(** [: False -> True] *)
(** %\smallskip{}%No proofs of %\index{Gallina terms!False}%[False] exist in the top-level context, but the implication-as-function analogy gives us an easy way to, for example, show that [False] implies itself. *)
Check (fun x : False => x).
(** [: False -> False] *)
(** %\smallskip{}%Every one of these example programs whose type looks like a logical formula is a%\index{proof term}% _proof term_. We use that name for any Gallina term of a logical type, and we will elaborate shortly on what makes a type logical.
In the rest of this chapter, we will introduce different ways of defining types. Every example type can be interpreted alternatively as a type of programs or proofs.
One of the first types we introduce will be [bool], with constructors [true] and [false]. Newcomers to Coq often wonder about the distinction between [True] and [true] and the distinction between [False] and [false]. One glib answer is that [True] and [False] are types, but [true] and [false] are not. A more useful answer is that Coq's metatheory guarantees that any term of type [bool] _evaluates_ to either [true] or [false]. This means that we have an _algorithm_ for answering any question phrased as an expression of type [bool]. Conversely, most propositions do not evaluate to [True] or [False]; the language of inductively defined propositions is much richer than that. We ought to be glad that we have no algorithm for deciding our formalized version of mathematical truth, since otherwise it would be clear that we could not formalize undecidable properties, like almost any interesting property of general-purpose programs. *)
(** * Enumerations *)
(** Coq inductive types generalize the %\index{algebraic datatypes}%algebraic datatypes found in %\index{Haskell}%Haskell and %\index{ML}%ML. Confusingly enough, inductive types also generalize %\index{generalized algebraic datatypes}%generalized algebraic datatypes (GADTs), by adding the possibility for type dependency. Even so, it is worth backing up from the examples of the last chapter and going over basic, algebraic-datatype uses of inductive datatypes, because the chance to prove things about the values of these types adds new wrinkles beyond usual practice in Haskell and ML.
The singleton type [unit] is an inductive type:%\index{Gallina terms!unit}\index{Gallina terms!tt}% *)
Inductive unit : Set :=
| tt.
(** This vernacular command defines a new inductive type [unit] whose only value is [tt]. We can verify the types of the two identifiers we introduce: *)
Check unit.
(** [unit : Set] *)
Check tt.
(** [tt : unit] *)
(** %\smallskip{}%We can prove that [unit] is a genuine singleton type. *)
Theorem unit_singleton : forall x : unit, x = tt.
(** The important thing about an inductive type is, unsurprisingly, that you can do induction over its values, and induction is the key to proving this theorem. We ask to proceed by induction on the variable [x].%\index{tactics!induction}% *)
(* begin thide *)
induction x.
(** The goal changes to:
[[
tt = tt
]]
*)
(** %\noindent{}%...which we can discharge trivially. *)
reflexivity.
Qed.
(* end thide *)
(** It seems kind of odd to write a proof by induction with no inductive hypotheses. We could have arrived at the same result by beginning the proof with:%\index{tactics!destruct}% [[
destruct x.
]]
%\noindent%...which corresponds to "proof by case analysis" in classical math. For non-recursive inductive types, the two tactics will always have identical behavior. Often case analysis is sufficient, even in proofs about recursive types, and it is nice to avoid introducing unneeded induction hypotheses.
What exactly _is_ the %\index{induction principles}%induction principle for [unit]? We can ask Coq: *)
Check unit_ind.
(** [unit_ind : forall P : unit -> Prop, P tt -> forall u : unit, P u] *)
(** %\smallskip{}%Every [Inductive] command defining a type [T] also defines an induction principle named [T_ind]. Recall from the last section that our type, operations over it, and principles for reasoning about it all live in the same language and are described by the same type system. The key to telling what is a program and what is a proof lies in the distinction between the type %\index{Gallina terms!Prop}%[Prop], which appears in our induction principle; and the type %\index{Gallina terms!Set}%[Set], which we have seen a few times already.
The convention goes like this: [Set] is the type of normal types used in programming, and the values of such types are programs. [Prop] is the type of logical propositions, and the values of such types are proofs. Thus, an induction principle has a type that shows us that it is a function for building proofs.
Specifically, [unit_ind] quantifies over a predicate [P] over [unit] values. If we can present a proof that [P] holds of [tt], then we are rewarded with a proof that [P] holds for any value [u] of type [unit]. In our last proof, the predicate was [(fun u : unit => u = tt)].
The definition of [unit] places the type in [Set]. By replacing [Set] with [Prop], [unit] with [True], and [tt] with [I], we arrive at precisely the definition of [True] that the Coq standard library employs! The program type [unit] is the Curry-Howard equivalent of the proposition [True]. We might make the tongue-in-cheek claim that, while philosophers have expended much ink on the nature of truth, we have now determined that truth is the [unit] type of functional programming.
%\medskip%
We can define an inductive type even simpler than [unit]:%\index{Gallina terms!Empty\_set}% *)
Inductive Empty_set : Set := .
(** [Empty_set] has no elements. We can prove fun theorems about it: *)
Theorem the_sky_is_falling : forall x : Empty_set, 2 + 2 = 5.
(* begin thide *)
destruct 1.
Qed.
(* end thide *)
(** Because [Empty_set] has no elements, the fact of having an element of this type implies anything. We use [destruct 1] instead of [destruct x] in the proof because unused quantified variables are relegated to being referred to by number. (There is a good reason for this, related to the unity of quantifiers and implication. At least within Coq's logical foundation of %\index{constructive logic}%constructive logic, which we elaborate on more in the next chapter, an implication is just a quantification over a proof, where the quantified variable is never used. It generally makes more sense to refer to implication hypotheses by number than by name, and Coq treats our quantifier over an unused variable as an implication in determining the proper behavior.)
We can see the induction principle that made this proof so easy: *)
Check Empty_set_ind.
(** [Empty_set_ind : forall (P : Empty_set -> Prop) (e : Empty_set), P e] *)
(** %\smallskip{}%In other words, any predicate over values from the empty set holds vacuously of every such element. In the last proof, we chose the predicate [(fun _ : Empty_set => 2 + 2 = 5)].
We can also apply this get-out-of-jail-free card programmatically. Here is a lazy way of converting values of [Empty_set] to values of [unit]: *)
Definition e2u (e : Empty_set) : unit := match e with end.
(** We employ [match] pattern matching as in the last chapter. Since we match on a value whose type has no constructors, there is no need to provide any branches. It turns out that [Empty_set] is the Curry-Howard equivalent of [False]. As for why [Empty_set] starts with a capital letter and not a lowercase letter like [unit] does, we must refer the reader to the authors of the Coq standard library, to which we try to be faithful.
%\medskip%
Moving up the ladder of complexity, we can define the Booleans:%\index{Gallina terms!bool}\index{Gallina terms!true}\index{Gallina terms!false}% *)
Inductive bool : Set :=
| true
| false.
(** We can use less vacuous pattern matching to define Boolean negation.%\index{Gallina terms!negb}% *)
Definition negb (b : bool) : bool :=
match b with
| true => false
| false => true
end.
(** An alternative definition desugars to the above, thanks to an %\index{Gallina terms!if}%[if] notation overloaded to work with any inductive type that has exactly two constructors: *)
Definition negb' (b : bool) : bool :=
if b then false else true.
(** We might want to prove that [negb] is its own inverse operation. *)
Theorem negb_inverse : forall b : bool, negb (negb b) = b.
(* begin thide *)
destruct b.
(** After we case-analyze on [b], we are left with one subgoal for each constructor of [bool].
[[
2 subgoals
============================
negb (negb true) = true
subgoal 2 is
negb (negb false) = false
]]
The first subgoal follows by Coq's rules of computation, so we can dispatch it easily: *)
reflexivity.
(** Likewise for the second subgoal, so we can restart the proof and give a very compact justification.%\index{Vernacular commands!Restart}% *)
Restart.
destruct b; reflexivity.
Qed.
(* end thide *)
(** Another theorem about Booleans illustrates another useful tactic.%\index{tactics!discriminate}% *)
Theorem negb_ineq : forall b : bool, negb b <> b.
(* begin thide *)
destruct b; discriminate.
Qed.
(* end thide *)
(** The [discriminate] tactic is used to prove that two values of an inductive type are not equal, whenever the values are formed with different constructors. In this case, the different constructors are [true] and [false].
At this point, it is probably not hard to guess what the underlying induction principle for [bool] is. *)
Check bool_ind.
(** [bool_ind : forall P : bool -> Prop, P true -> P false -> forall b : bool, P b] *)
(** %\smallskip{}%That is, to prove that a property describes all [bool]s, prove that it describes both [true] and [false].
There is no interesting Curry-Howard analogue of [bool]. Of course, we can define such a type by replacing [Set] by [Prop] above, but the proposition we arrive at is not very useful. It is logically equivalent to [True], but it provides two indistinguishable primitive proofs, [true] and [false]. In the rest of the chapter, we will skip commenting on Curry-Howard versions of inductive definitions where such versions are not interesting. *)
(** * Simple Recursive Types *)
(** The natural numbers are the simplest common example of an inductive type that actually deserves the name.%\index{Gallina terms!nat}\index{Gallina terms!O}\index{Gallina terms!S}% *)
Inductive nat : Set :=
| O : nat
| S : nat -> nat.
(** The constructor [O] is zero, and [S] is the successor function, so that [0] is syntactic sugar for [O], [1] for [S O], [2] for [S (S O)], and so on.
Pattern matching works as we demonstrated in the last chapter:%\index{Gallina terms!pred}% *)
Definition isZero (n : nat) : bool :=
match n with
| O => true
| S _ => false
end.
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** We can prove theorems by case analysis with [destruct] as for simpler inductive types, but we can also now get into genuine inductive theorems. First, we will need a recursive function, to make things interesting.%\index{Gallina terms!plus}% *)
Fixpoint plus (n m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Recall that [Fixpoint] is Coq's mechanism for recursive function definitions. Some theorems about [plus] can be proved without induction. *)
Theorem O_plus_n : forall n : nat, plus O n = n.
(* begin thide *)
intro; reflexivity.
Qed.
(* end thide *)
(** Coq's computation rules automatically simplify the application of [plus], because unfolding the definition of [plus] gives us a [match] expression where the branch to be taken is obvious from syntax alone. If we just reverse the order of the arguments, though, this no longer works, and we need induction. *)
Theorem n_plus_O : forall n : nat, plus n O = n.
(* begin thide *)
induction n.
(** Our first subgoal is [plus O O = O], which _is_ trivial by computation. *)
reflexivity.
(** Our second subgoal requires more work and also demonstrates our first inductive hypothesis.
[[
n : nat
IHn : plus n O = n
============================
plus (S n) O = S n
]]
We can start out by using computation to simplify the goal as far as we can.%\index{tactics!simpl}% *)
simpl.
(** Now the conclusion is [S (plus n O) = S n]. Using our inductive hypothesis: *)
rewrite IHn.
(** %\noindent{}%...we get a trivial conclusion [S n = S n]. *)
reflexivity.
(** Not much really went on in this proof, so the [crush] tactic from the [CpdtTactics] module can prove this theorem automatically. *)
Restart.
induction n; crush.
Qed.
(* end thide *)
(** We can check out the induction principle at work here: *)
Check nat_ind.
(** %\vspace{-.15in}% [[
nat_ind : forall P : nat -> Prop,
P O -> (forall n : nat, P n -> P (S n)) -> forall n : nat, P n
]]
Each of the two cases of our last proof came from the type of one of the arguments to [nat_ind]. We chose [P] to be [(fun n : nat => plus n O = n)]. The first proof case corresponded to [P O] and the second case to [(forall n : nat, P n -> P (S n))]. The free variable [n] and inductive hypothesis [IHn] came from the argument types given here.
Since [nat] has a constructor that takes an argument, we may sometimes need to know that that constructor is injective.%\index{tactics!injection}\index{tactics!trivial}% *)
Theorem S_inj : forall n m : nat, S n = S m -> n = m.
(* begin thide *)
injection 1; trivial.
Qed.
(* end thide *)
(** The [injection] tactic refers to a premise by number, adding new equalities between the corresponding arguments of equated terms that are formed with the same constructor. We end up needing to prove [n = m -> n = m], so it is unsurprising that a tactic named [trivial] is able to finish the proof. This tactic attempts a variety of single proof steps, drawn from a user-specified database that we will later see how to extend.
There is also a very useful tactic called %\index{tactics!congruence}%[congruence] that can prove this theorem immediately. The [congruence] tactic generalizes [discriminate] and [injection], and it also adds reasoning about the general properties of equality, such as that a function returns equal results on equal arguments. That is, [congruence] is a%\index{theory of equality and uninterpreted functions}% _complete decision procedure for the theory of equality and uninterpreted functions_, plus some smarts about inductive types.
%\medskip%
We can define a type of lists of natural numbers. *)
Inductive nat_list : Set :=
| NNil : nat_list
| NCons : nat -> nat_list -> nat_list.
(** Recursive definitions over [nat_list] are straightforward extensions of what we have seen before. *)
Fixpoint nlength (ls : nat_list) : nat :=
match ls with
| NNil => O
| NCons _ ls' => S (nlength ls')
end.
Fixpoint napp (ls1 ls2 : nat_list) : nat_list :=
match ls1 with
| NNil => ls2
| NCons n ls1' => NCons n (napp ls1' ls2)
end.
(** Inductive theorem proving can again be automated quite effectively. *)
Theorem nlength_napp : forall ls1 ls2 : nat_list, nlength (napp ls1 ls2)
= plus (nlength ls1) (nlength ls2).
(* begin thide *)
induction ls1; crush.
Qed.
(* end thide *)
Check nat_list_ind.
(** %\vspace{-.15in}% [[
nat_list_ind
: forall P : nat_list -> Prop,
P NNil ->
(forall (n : nat) (n0 : nat_list), P n0 -> P (NCons n n0)) ->
forall n : nat_list, P n
]]
%\medskip%
In general, we can implement any "tree" type as an inductive type. For example, here are binary trees of naturals. *)
Inductive nat_btree : Set :=
| NLeaf : nat_btree
| NNode : nat_btree -> nat -> nat_btree -> nat_btree.
(** Here are two functions whose intuitive explanations are not so important. The first one computes the size of a tree, and the second performs some sort of splicing of one tree into the leftmost available leaf node of another. *)
Fixpoint nsize (tr : nat_btree) : nat :=
match tr with
| NLeaf => S O
| NNode tr1 _ tr2 => plus (nsize tr1) (nsize tr2)
end.
Fixpoint nsplice (tr1 tr2 : nat_btree) : nat_btree :=
match tr1 with
| NLeaf => NNode tr2 O NLeaf
| NNode tr1' n tr2' => NNode (nsplice tr1' tr2) n tr2'
end.
Theorem plus_assoc : forall n1 n2 n3 : nat, plus (plus n1 n2) n3 = plus n1 (plus n2 n3).
(* begin thide *)
induction n1; crush.
Qed.
(* end thide *)
Hint Rewrite n_plus_O plus_assoc.
Theorem nsize_nsplice : forall tr1 tr2 : nat_btree, nsize (nsplice tr1 tr2)
= plus (nsize tr2) (nsize tr1).
(* begin thide *)
induction tr1; crush.
Qed.
(* end thide *)
(** It is convenient that these proofs go through so easily, but it is still useful to look into the details of what happened, by checking the statement of the tree induction principle. *)
Check nat_btree_ind.
(** %\vspace{-.15in}% [[
nat_btree_ind
: forall P : nat_btree -> Prop,
P NLeaf ->
(forall n : nat_btree,
P n -> forall (n0 : nat) (n1 : nat_btree), P n1 -> P (NNode n n0 n1)) ->
forall n : nat_btree, P n
]]
We have the usual two cases, one for each constructor of [nat_btree]. *)
(** * Parameterized Types *)
(** We can also define %\index{polymorphism}%polymorphic inductive types, as with algebraic datatypes in Haskell and ML.%\index{Gallina terms!list}\index{Gallina terms!Nil}\index{Gallina terms!Cons}\index{Gallina terms!length}\index{Gallina terms!app}% *)
Inductive list (T : Set) : Set :=
| Nil : list T
| Cons : T -> list T -> list T.
Fixpoint length T (ls : list T) : nat :=
match ls with
| Nil => O
| Cons _ ls' => S (length ls')
end.
Fixpoint app T (ls1 ls2 : list T) : list T :=
match ls1 with
| Nil => ls2
| Cons x ls1' => Cons x (app ls1' ls2)
end.
Theorem length_app : forall T (ls1 ls2 : list T), length (app ls1 ls2)
= plus (length ls1) (length ls2).
(* begin thide *)
induction ls1; crush.
Qed.
(* end thide *)
(** There is a useful shorthand for writing many definitions that share the same parameter, based on Coq's%\index{sections}\index{Vernacular commands!Section}\index{Vernacular commands!Variable}% _section_ mechanism. The following block of code is equivalent to the above: *)
(* begin hide *)
Reset list.
(* end hide *)
Section list.
Variable T : Set.
Inductive list : Set :=
| Nil : list
| Cons : T -> list -> list.
Fixpoint length (ls : list) : nat :=
match ls with
| Nil => O
| Cons _ ls' => S (length ls')
end.
Fixpoint app (ls1 ls2 : list) : list :=
match ls1 with
| Nil => ls2
| Cons x ls1' => Cons x (app ls1' ls2)
end.
Theorem length_app : forall ls1 ls2 : list, length (app ls1 ls2)
= plus (length ls1) (length ls2).
(* begin thide *)
induction ls1; crush.
Qed.
(* end thide *)
End list.
Implicit Arguments Nil [T].
(** After we end the section, the [Variable]s we used are added as extra function parameters for each defined identifier, as needed. With an [Implicit Arguments]%~\index{Vernacular commands!Implicit Arguments}% command, we ask that [T] be inferred when we use [Nil]; Coq's heuristics already decided to apply a similar policy to [Cons], because of the [Set Implicit Arguments]%~\index{Vernacular commands!Set Implicit Arguments}% command elided at the beginning of this chapter. We verify that our definitions have been saved properly using the [Print] command, a cousin of [Check] which shows the definition of a symbol, rather than just its type. *)
Print list.
(** %\vspace{-.15in}% [[
Inductive list (T : Set) : Set :=
Nil : list T | Cons : T -> list T -> list T
]]
The final definition is the same as what we wrote manually before. The other elements of the section are altered similarly, turning out exactly as they were before, though we managed to write their definitions more succinctly. *)
Check length.
(** %\vspace{-.15in}% [[
length
: forall T : Set, list T -> nat
]]
The parameter [T] is treated as a new argument to the induction principle, too. *)
Check list_ind.
(** %\vspace{-.15in}% [[
list_ind
: forall (T : Set) (P : list T -> Prop),
P (Nil T) ->
(forall (t : T) (l : list T), P l -> P (Cons t l)) ->
forall l : list T, P l
]]
Thus, despite a very real sense in which the type [T] is an argument to the constructor [Cons], the inductive case in the type of [list_ind] (i.e., the third line of the type) includes no quantifier for [T], even though all of the other arguments are quantified explicitly. Parameters in other inductive definitions are treated similarly in stating induction principles. *)
(** * Mutually Inductive Types *)
(** We can define inductive types that refer to each other: *)
Inductive even_list : Set :=
| ENil : even_list
| ECons : nat -> odd_list -> even_list
with odd_list : Set :=
| OCons : nat -> even_list -> odd_list.
Fixpoint elength (el : even_list) : nat :=
match el with
| ENil => O
| ECons _ ol => S (olength ol)
end
with olength (ol : odd_list) : nat :=
match ol with
| OCons _ el => S (elength el)
end.
Fixpoint eapp (el1 el2 : even_list) : even_list :=
match el1 with
| ENil => el2
| ECons n ol => ECons n (oapp ol el2)
end
with oapp (ol : odd_list) (el : even_list) : odd_list :=
match ol with
| OCons n el' => OCons n (eapp el' el)
end.
(** Everything is going roughly the same as in past examples, until we try to prove a theorem similar to those that came before. *)
Theorem elength_eapp : forall el1 el2 : even_list,
elength (eapp el1 el2) = plus (elength el1) (elength el2).
Proof.
induction el1;
crush.
(** One goal remains: [[
n : nat
o : odd_list
el2 : even_list
============================
S (olength (oapp o el2)) = S (plus (olength o) (elength el2))
]]
We have no induction hypothesis, so we cannot prove this goal without starting another induction, which would reach a similar point, sending us into a futile infinite chain of inductions. The problem is that Coq's generation of [T_ind] principles is incomplete. We only get non-mutual induction principles generated by default. *)
Abort.
Check even_list_ind.
(** %\vspace{-.15in}% [[
even_list_ind
: forall P : even_list -> Prop,
P ENil ->
(forall (n : nat) (o : odd_list), P (ECons n o)) ->
forall e : even_list, P e
]]
We see that no inductive hypotheses are included anywhere in the type. To get them, we must ask for mutual principles as we need them, using the %\index{Vernacular commands!Scheme}%[Scheme] command. *)
Scheme even_list_mut := Induction for even_list Sort Prop
with odd_list_mut := Induction for odd_list Sort Prop.
(** This invocation of [Scheme] asks for the creation of induction principles [even_list_mut] for the type [even_list] and [odd_list_mut] for the type [odd_list]. The [Induction] keyword says we want standard induction schemes, since [Scheme] supports more exotic choices. Finally, [Sort Prop] establishes that we really want induction schemes, not recursion schemes, which are the same according to Curry-Howard, save for the [Prop]/[Set] distinction. *)
Check even_list_mut.
(** %\vspace{-.15in}% [[
even_list_mut
: forall (P : even_list -> Prop) (P0 : odd_list -> Prop),
P ENil ->
(forall (n : nat) (o : odd_list), P0 o -> P (ECons n o)) ->
(forall (n : nat) (e : even_list), P e -> P0 (OCons n e)) ->
forall e : even_list, P e
]]
This is the principle we wanted in the first place.
The [Scheme] command is for asking Coq to generate particular induction schemes that are mutual among a set of inductive types (possibly only one such type, in which case we get a normal induction principle). In a sense, it generalizes the induction scheme generation that goes on automatically for each inductive definition. Future Coq versions might make that automatic generation smarter, so that [Scheme] is needed in fewer places. In a few sections, we will see how induction principles are derived theorems in Coq, so that there is not actually any need to build in _any_ automatic scheme generation.
There is one more wrinkle left in using the [even_list_mut] induction principle: the [induction] tactic will not apply it for us automatically. It will be helpful to look at how to prove one of our past examples without using [induction], so that we can then generalize the technique to mutual inductive types.%\index{tactics!apply}% *)
Theorem n_plus_O' : forall n : nat, plus n O = n.
apply nat_ind.
(** Here we use [apply], which is one of the most essential basic tactics. When we are trying to prove fact [P], and when [thm] is a theorem whose conclusion can be made to match [P] by proper choice of quantified variable values, the invocation [apply thm] will replace the current goal with one new goal for each premise of [thm].
This use of [apply] may seem a bit _too_ magical. To better see what is going on, we use a variant where we partially apply the theorem [nat_ind] to give an explicit value for the predicate that gives our induction hypothesis. *)
Undo.
apply (nat_ind (fun n => plus n O = n)); crush.
Qed.
(** From this example, we can see that [induction] is not magic. It only does some bookkeeping for us to make it easy to apply a theorem, which we can do directly with the [apply] tactic.
This technique generalizes to our mutual example: *)
Theorem elength_eapp : forall el1 el2 : even_list,
elength (eapp el1 el2) = plus (elength el1) (elength el2).
apply (even_list_mut
(fun el1 : even_list => forall el2 : even_list,
elength (eapp el1 el2) = plus (elength el1) (elength el2))
(fun ol : odd_list => forall el : even_list,
olength (oapp ol el) = plus (olength ol) (elength el))); crush.
Qed.
(* end thide *)
(** We simply need to specify two predicates, one for each of the mutually inductive types. In general, it is not a good idea to assume that a proof assistant can infer extra predicates, so this way of applying mutual induction is about as straightforward as we may hope for. *)
(** * Reflexive Types *)
(** A kind of inductive type called a _reflexive type_ includes at least one constructor that takes as an argument _a function returning the same type we are defining_. One very useful class of examples is in modeling variable binders. Our example will be an encoding of the syntax of first-order logic. Since the idea of syntactic encodings of logic may require a bit of acclimation, let us first consider a simpler formula type for a subset of propositional logic. We are not yet using a reflexive type, but later we will extend the example reflexively. *)
Inductive pformula : Set :=
| Truth : pformula
| Falsehood : pformula
| Conjunction : pformula -> pformula -> pformula.
(* begin hide *)
(* begin thide *)
Definition prod' := prod.
(* end thide *)
(* end hide *)
(** A key distinction here is between, for instance, the _syntax_ [Truth] and its _semantics_ [True]. We can make the semantics explicit with a recursive function. This function uses the infix operator %\index{Gallina operators!/\textbackslash}%[/\], which desugars to instances of the type family %\index{Gallina terms!and}%[and] from the standard library. The family [and] implements conjunction, the [Prop] Curry-Howard analogue of the usual pair type from functional programming (which is the type family %\index{Gallina terms!prod}%[prod] in Coq's standard library). *)
Fixpoint pformulaDenote (f : pformula) : Prop :=
match f with
| Truth => True
| Falsehood => False
| Conjunction f1 f2 => pformulaDenote f1 /\ pformulaDenote f2
end.
(** This is just a warm-up that does not use reflexive types, the new feature we mean to introduce. When we set our sights on first-order logic instead, it becomes very handy to give constructors recursive arguments that are functions. *)
Inductive formula : Set :=
| Eq : nat -> nat -> formula
| And : formula -> formula -> formula
| Forall : (nat -> formula) -> formula.
(** Our kinds of formulas are equalities between naturals, conjunction, and universal quantification over natural numbers. We avoid needing to include a notion of "variables" in our type, by using Coq functions to encode the syntax of quantification. For instance, here is the encoding of [forall x : nat, x = x]:%\index{Vernacular commands!Example}% *)
Example forall_refl : formula := Forall (fun x => Eq x x).
(** We can write recursive functions over reflexive types quite naturally. Here is one translating our formulas into native Coq propositions. *)
Fixpoint formulaDenote (f : formula) : Prop :=
match f with
| Eq n1 n2 => n1 = n2
| And f1 f2 => formulaDenote f1 /\ formulaDenote f2
| Forall f' => forall n : nat, formulaDenote (f' n)
end.
(** We can also encode a trivial formula transformation that swaps the order of equality and conjunction operands. *)
Fixpoint swapper (f : formula) : formula :=
match f with
| Eq n1 n2 => Eq n2 n1
| And f1 f2 => And (swapper f2) (swapper f1)
| Forall f' => Forall (fun n => swapper (f' n))
end.
(** It is helpful to prove that this transformation does not make true formulas false. *)
Theorem swapper_preserves_truth : forall f, formulaDenote f -> formulaDenote (swapper f).
(* begin thide *)
induction f; crush.
Qed.
(* end thide *)
(** We can take a look at the induction principle behind this proof. *)
Check formula_ind.
(** %\vspace{-.15in}% [[
formula_ind
: forall P : formula -> Prop,
(forall n n0 : nat, P (Eq n n0)) ->
(forall f0 : formula,
P f0 -> forall f1 : formula, P f1 -> P (And f0 f1)) ->
(forall f1 : nat -> formula,
(forall n : nat, P (f1 n)) -> P (Forall f1)) ->
forall f2 : formula, P f2
]]
Focusing on the [Forall] case, which comes third, we see that we are allowed to assume that the theorem holds _for any application of the argument function [f1]_. That is, Coq induction principles do not follow a simple rule that the textual representations of induction variables must get shorter in appeals to induction hypotheses. Luckily for us, the people behind the metatheory of Coq have verified that this flexibility does not introduce unsoundness.
%\medskip%
Up to this point, we have seen how to encode in Coq more and more of what is possible with algebraic datatypes in %\index{Haskell}%Haskell and %\index{ML}%ML. This may have given the inaccurate impression that inductive types are a strict extension of algebraic datatypes. In fact, Coq must rule out some types allowed by Haskell and ML, for reasons of soundness. Reflexive types provide our first good example of such a case; only some of them are legal.
Given our last example of an inductive type, many readers are probably eager to try encoding the syntax of %\index{lambda calculus}%lambda calculus. Indeed, the function-based representation technique that we just used, called%\index{higher-order abstract syntax}\index{HOAS|see{higher-order abstract syntax}}% _higher-order abstract syntax_ (HOAS)%~\cite{HOAS}%, is the representation of choice for lambda calculi in %\index{Twelf}%Twelf and in many applications implemented in Haskell and ML. Let us try to import that choice to Coq: *)
(* begin hide *)
(* begin thide *)
Inductive term : Set := App | Abs.
Reset term.
Definition uhoh := O.
(* end thide *)
(* end hide *)
(** [[
Inductive term : Set :=
| App : term -> term -> term
| Abs : (term -> term) -> term.
]]
<<
Error: Non strictly positive occurrence of "term" in "(term -> term) -> term"
>>
We have run afoul of the%\index{strict positivity requirement}\index{positivity requirement}% _strict positivity requirement_ for inductive definitions, which says that the type being defined may not occur to the left of an arrow in the type of a constructor argument. It is important that the type of a constructor is viewed in terms of a series of arguments and a result, since obviously we need recursive occurrences to the lefts of the outermost arrows if we are to have recursive occurrences at all. Our candidate definition above violates the positivity requirement because it involves an argument of type [term -> term], where the type [term] that we are defining appears to the left of an arrow. The candidate type of [App] is fine, however, since every occurrence of [term] is either a constructor argument or the final result type.
Why must Coq enforce this restriction? Imagine that our last definition had been accepted, allowing us to write this function:
%\vspace{-.15in}%[[
Definition uhoh (t : term) : term :=
match t with
| Abs f => f t
| _ => t
end.
]]
Using an informal idea of Coq's semantics, it is easy to verify that the application [uhoh (Abs uhoh)] will run forever. This would be a mere curiosity in OCaml and Haskell, where non-termination is commonplace, though the fact that we have a non-terminating program without explicit recursive function definitions is unusual.
%\index{termination checking}%For Coq, however, this would be a disaster. The possibility of writing such a function would destroy all our confidence that proving a theorem means anything. Since Coq combines programs and proofs in one language, we would be able to prove every theorem with an infinite loop.
Nonetheless, the basic insight of HOAS is a very useful one, and there are ways to realize most benefits of HOAS in Coq. We will study a particular technique of this kind in the final chapter, on programming language syntax and semantics. *)
(** * An Interlude on Induction Principles *)
(** As we have emphasized a few times already, Coq proofs are actually programs, written in the same language we have been using in our examples all along. We can get a first sense of what this means by taking a look at the definitions of some of the %\index{induction principles}%induction principles we have used. A close look at the details here will help us construct induction principles manually, which we will see is necessary for some more advanced inductive definitions. *)
Print nat_ind.
(** %\vspace{-.15in}%[[
nat_ind =
fun P : nat -> Prop => nat_rect P
: forall P : nat -> Prop,
P O -> (forall n : nat, P n -> P (S n)) -> forall n : nat, P n
]]
We see that this induction principle is defined in terms of a more general principle, [nat_rect]. The <<rec>> stands for "recursion principle," and the <<t>> at the end stands for [Type]. *)
Check nat_rect.
(** %\vspace{-.15in}% [[
nat_rect
: forall P : nat -> Type,
P O -> (forall n : nat, P n -> P (S n)) -> forall n : nat, P n
]]
The principle [nat_rect] gives [P] type [nat -> Type] instead of [nat -> Prop]. This [Type] is another universe, like [Set] and [Prop]. In fact, it is a common supertype of both. Later on, we will discuss exactly what the significances of the different universes are. For now, it is just important that we can use [Type] as a sort of meta-universe that may turn out to be either [Set] or [Prop]. We can see the symmetry inherent in the subtyping relationship by printing the definition of another principle that was generated for [nat] automatically: *)
Print nat_rec.
(** %\vspace{-.15in}%[[
nat_rec =
fun P : nat -> Set => nat_rect P
: forall P : nat -> Set,
P O -> (forall n : nat, P n -> P (S n)) -> forall n : nat, P n
]]
This is identical to the definition for [nat_ind], except that we have substituted [Set] for [Prop]. For most inductive types [T], then, we get not just induction principles [T_ind], but also %\index{recursion principles}%recursion principles [T_rec]. We can use [T_rec] to write recursive definitions without explicit [Fixpoint] recursion. For instance, the following two definitions are equivalent: *)
Fixpoint plus_recursive (n : nat) : nat -> nat :=
match n with
| O => fun m => m
| S n' => fun m => S (plus_recursive n' m)
end.
Definition plus_rec : nat -> nat -> nat :=
nat_rec (fun _ : nat => nat -> nat) (fun m => m) (fun _ r m => S (r m)).
Theorem plus_equivalent : plus_recursive = plus_rec.
reflexivity.
Qed.
(** Going even further down the rabbit hole, [nat_rect] itself is not even a primitive. It is a functional program that we can write manually. *)
Print nat_rect.
(** %\vspace{-.15in}%[[
nat_rect =
fun (P : nat -> Type) (f : P O) (f0 : forall n : nat, P n -> P (S n)) =>
fix F (n : nat) : P n :=
match n as n0 return (P n0) with
| O => f
| S n0 => f0 n0 (F n0)
end
: forall P : nat -> Type,
P O -> (forall n : nat, P n -> P (S n)) -> forall n : nat, P n
]]
The only new wrinkles here are, first, an anonymous recursive function definition, using the %\index{Gallina terms!fix}%[fix] keyword of Gallina (which is like [fun] with recursion supported); and, second, the annotations on the [match] expression. This is a%\index{dependent pattern matching}% _dependently typed_ pattern match, because the _type_ of the expression depends on the _value_ being matched on. We will meet more involved examples later, especially in Part II of the book.
%\index{type inference}%Type inference for dependent pattern matching is undecidable, which can be proved by reduction from %\index{higher-order unification}%higher-order unification%~\cite{HOU}%. Thus, we often find ourselves needing to annotate our programs in a way that explains dependencies to the type checker. In the example of [nat_rect], we have an %\index{Gallina terms!as}%[as] clause, which binds a name for the discriminee; and a %\index{Gallina terms!return}%[return] clause, which gives a way to compute the [match] result type as a function of the discriminee.
To prove that [nat_rect] is nothing special, we can reimplement it manually. *)
Fixpoint nat_rect' (P : nat -> Type)
(HO : P O)
(HS : forall n, P n -> P (S n)) (n : nat) :=
match n return P n with
| O => HO
| S n' => HS n' (nat_rect' P HO HS n')
end.
(** We can understand the definition of [nat_rect] better by reimplementing [nat_ind] using sections. *)
Section nat_ind'.
(** First, we have the property of natural numbers that we aim to prove. *)
Variable P : nat -> Prop.
(** Then we require a proof of the [O] case, which we declare with the command %\index{Vernacular commands!Hypothesis}%[Hypothesis], which is a synonym for [Variable] that, by convention, is used for variables whose types are propositions. *)
Hypothesis O_case : P O.
(** Next is a proof of the [S] case, which may assume an inductive hypothesis. *)
Hypothesis S_case : forall n : nat, P n -> P (S n).
(** Finally, we define a recursive function to tie the pieces together. *)
Fixpoint nat_ind' (n : nat) : P n :=
match n with
| O => O_case
| S n' => S_case (nat_ind' n')
end.
End nat_ind'.
(** Closing the section adds the [Variable]s and [Hypothesis]es as new [fun]-bound arguments to [nat_ind'], and, modulo the use of [Prop] instead of [Type], we end up with the exact same definition that was generated automatically for [nat_rect].
%\medskip%
We can also examine the definition of [even_list_mut], which we generated with [Scheme] for a mutually recursive type. *)
Print even_list_mut.
(** %\vspace{-.15in}%[[
even_list_mut =
fun (P : even_list -> Prop) (P0 : odd_list -> Prop)
(f : P ENil) (f0 : forall (n : nat) (o : odd_list), P0 o -> P (ECons n o))
(f1 : forall (n : nat) (e : even_list), P e -> P0 (OCons n e)) =>
fix F (e : even_list) : P e :=
match e as e0 return (P e0) with
| ENil => f
| ECons n o => f0 n o (F0 o)
end
with F0 (o : odd_list) : P0 o :=
match o as o0 return (P0 o0) with
| OCons n e => f1 n e (F e)
end
for F
: forall (P : even_list -> Prop) (P0 : odd_list -> Prop),
P ENil ->
(forall (n : nat) (o : odd_list), P0 o -> P (ECons n o)) ->
(forall (n : nat) (e : even_list), P e -> P0 (OCons n e)) ->
forall e : even_list, P e
]]
We see a mutually recursive [fix], with the different functions separated by %\index{Gallina terms!with}%[with] in the same way that they would be separated by <<and>> in ML. A final %\index{Gallina terms!for}%[for] clause identifies which of the mutually recursive functions should be the final value of the [fix] expression. Using this definition as a template, we can reimplement [even_list_mut] directly. *)
Section even_list_mut'.
(** First, we need the properties that we are proving. *)
Variable Peven : even_list -> Prop.
Variable Podd : odd_list -> Prop.
(** Next, we need proofs of the three cases. *)
Hypothesis ENil_case : Peven ENil.
Hypothesis ECons_case : forall (n : nat) (o : odd_list), Podd o -> Peven (ECons n o).
Hypothesis OCons_case : forall (n : nat) (e : even_list), Peven e -> Podd (OCons n e).
(** Finally, we define the recursive functions. *)
Fixpoint even_list_mut' (e : even_list) : Peven e :=
match e with
| ENil => ENil_case
| ECons n o => ECons_case n (odd_list_mut' o)
end
with odd_list_mut' (o : odd_list) : Podd o :=
match o with
| OCons n e => OCons_case n (even_list_mut' e)
end.
End even_list_mut'.
(** Even induction principles for reflexive types are easy to implement directly. For our [formula] type, we can use a recursive definition much like those we wrote above. *)
Section formula_ind'.
Variable P : formula -> Prop.
Hypothesis Eq_case : forall n1 n2 : nat, P (Eq n1 n2).
Hypothesis And_case : forall f1 f2 : formula,
P f1 -> P f2 -> P (And f1 f2).
Hypothesis Forall_case : forall f : nat -> formula,
(forall n : nat, P (f n)) -> P (Forall f).
Fixpoint formula_ind' (f : formula) : P f :=
match f with
| Eq n1 n2 => Eq_case n1 n2
| And f1 f2 => And_case (formula_ind' f1) (formula_ind' f2)
| Forall f' => Forall_case f' (fun n => formula_ind' (f' n))
end.
End formula_ind'.
(** It is apparent that induction principle implementations involve some tedium but not terribly much creativity. *)
(** * Nested Inductive Types *)
(** Suppose we want to extend our earlier type of binary trees to trees with arbitrary finite branching. We can use lists to give a simple definition. *)
Inductive nat_tree : Set :=
| NNode' : nat -> list nat_tree -> nat_tree.
(** This is an example of a%\index{nested inductive type}% _nested_ inductive type definition, because we use the type we are defining as an argument to a parameterized type family. Coq will not allow all such definitions; it effectively pretends that we are defining [nat_tree] mutually with a version of [list] specialized to [nat_tree], checking that the resulting expanded definition satisfies the usual rules. For instance, if we replaced [list] with a type family that used its parameter as a function argument, then the definition would be rejected as violating the positivity restriction.
As we encountered with mutual inductive types, we find that the automatically generated induction principle for [nat_tree] is too weak. *)
(* begin hide *)
(* begin thide *)
Check Forall.
(* end thide *)
(* end hide *)
Check nat_tree_ind.
(** %\vspace{-.15in}% [[
nat_tree_ind
: forall P : nat_tree -> Prop,
(forall (n : nat) (l : list nat_tree), P (NNode' n l)) ->
forall n : nat_tree, P n
]]
There is no command like [Scheme] that will implement an improved principle for us. In general, it takes creativity to figure out _good_ ways to incorporate nested uses of different type families. Now that we know how to implement induction principles manually, we are in a position to apply just such creativity to this problem.
Many induction principles for types with nested used of [list] could benefit from a unified predicate capturing the idea that some property holds of every element in a list. By defining this generic predicate once, we facilitate reuse of library theorems about it. (Here, we are actually duplicating the standard library's [Forall] predicate, with a different implementation, for didactic purposes.) *)
Section All.
Variable T : Set.
Variable P : T -> Prop.
Fixpoint All (ls : list T) : Prop :=
match ls with
| Nil => True
| Cons h t => P h /\ All t
end.
End All.
(** It will be useful to review the definitions of [True] and [/\], since we will want to write manual proofs of them below. *)
Print True.
(** %\vspace{-.15in}%[[
Inductive True : Prop := I : True
]]
That is, [True] is a proposition with exactly one proof, [I], which we may always supply trivially.
Finding the definition of [/\] takes a little more work. Coq supports user registration of arbitrary parsing rules, and it is such a rule that is letting us write [/\] instead of an application of some inductive type family. We can find the underlying inductive type with the %\index{Vernacular commands!Locate}%[Locate] command, whose argument may be a parsing token.%\index{Gallina terms!and}% *)
Locate "/\".
(** %\vspace{-.15in}%[[
"A /\ B" := and A B : type_scope (default interpretation)
]]
*)
Print and.
(** %\vspace{-.15in}%[[
Inductive and (A : Prop) (B : Prop) : Prop := conj : A -> B -> A /\ B
]]
%\vspace{-.1in}%
<<
For conj: Arguments A, B are implicit
>>
In addition to the definition of [and] itself, we get information on %\index{implicit arguments}%implicit arguments (and some other information that we omit here). The implicit argument information tells us that we build a proof of a conjunction by calling the constructor [conj] on proofs of the conjuncts, with no need to include the types of those proofs as explicit arguments.
%\medskip%
Now we create a section for our induction principle, following the same basic plan as in the previous section of this chapter. *)
Section nat_tree_ind'.
Variable P : nat_tree -> Prop.
Hypothesis NNode'_case : forall (n : nat) (ls : list nat_tree),
All P ls -> P (NNode' n ls).
(* begin hide *)
(* begin thide *)
Definition list_nat_tree_ind := O.
(* end thide *)
(* end hide *)
(** A first attempt at writing the induction principle itself follows the intuition that nested inductive type definitions are expanded into mutual inductive definitions.
%\vspace{-.15in}%[[
Fixpoint nat_tree_ind' (tr : nat_tree) : P tr :=
match tr with
| NNode' n ls => NNode'_case n ls (list_nat_tree_ind ls)
end
with list_nat_tree_ind (ls : list nat_tree) : All P ls :=
match ls with
| Nil => I
| Cons tr rest => conj (nat_tree_ind' tr) (list_nat_tree_ind rest)
end.
]]
Coq rejects this definition, saying
<<
Recursive call to nat_tree_ind' has principal argument equal to "tr"
instead of rest.
>>
There is no deep theoretical reason why this program should be rejected; Coq applies incomplete termination-checking heuristics, and it is necessary to learn a few of the most important rules. The term "nested inductive type" hints at the solution to this particular problem. Just as mutually inductive types require mutually recursive induction principles, nested types require nested recursion. *)
Fixpoint nat_tree_ind' (tr : nat_tree) : P tr :=
match tr with
| NNode' n ls => NNode'_case n ls
((fix list_nat_tree_ind (ls : list nat_tree) : All P ls :=
match ls with
| Nil => I
| Cons tr' rest => conj (nat_tree_ind' tr') (list_nat_tree_ind rest)
end) ls)
end.
(** We include an anonymous [fix] version of [list_nat_tree_ind] that is literally _nested_ inside the definition of the recursive function corresponding to the inductive definition that had the nested use of [list]. *)
End nat_tree_ind'.
(** We can try our induction principle out by defining some recursive functions on [nat_tree] and proving a theorem about them. First, we define some helper functions that operate on lists. *)
Section map.
Variables T T' : Set.
Variable F : T -> T'.
Fixpoint map (ls : list T) : list T' :=
match ls with
| Nil => Nil
| Cons h t => Cons (F h) (map t)
end.
End map.
Fixpoint sum (ls : list nat) : nat :=
match ls with
| Nil => O
| Cons h t => plus h (sum t)
end.
(** Now we can define a size function over our trees. *)
Fixpoint ntsize (tr : nat_tree) : nat :=
match tr with
| NNode' _ trs => S (sum (map ntsize trs))
end.
(** Notice that Coq was smart enough to expand the definition of [map] to verify that we are using proper nested recursion, even through a use of a higher-order function. *)
Fixpoint ntsplice (tr1 tr2 : nat_tree) : nat_tree :=
match tr1 with
| NNode' n Nil => NNode' n (Cons tr2 Nil)
| NNode' n (Cons tr trs) => NNode' n (Cons (ntsplice tr tr2) trs)
end.
(** We have defined another arbitrary notion of tree splicing, similar to before, and we can prove an analogous theorem about its relationship with tree size. We start with a useful lemma about addition. *)
(* begin thide *)
Lemma plus_S : forall n1 n2 : nat,
plus n1 (S n2) = S (plus n1 n2).
induction n1; crush.
Qed.
(* end thide *)
(** Now we begin the proof of the theorem, adding the lemma [plus_S] as a hint. *)
Hint Rewrite plus_S.
Theorem ntsize_ntsplice : forall tr1 tr2 : nat_tree, ntsize (ntsplice tr1 tr2)
= plus (ntsize tr2) (ntsize tr1).
(* begin thide *)
(** We know that the standard induction principle is insufficient for the task, so we need to provide a %\index{tactics!using}%[using] clause for the [induction] tactic to specify our alternate principle. *)
induction tr1 using nat_tree_ind'; crush.
(** One subgoal remains: [[
n : nat
ls : list nat_tree
H : All
(fun tr1 : nat_tree =>
forall tr2 : nat_tree,
ntsize (ntsplice tr1 tr2) = plus (ntsize tr2) (ntsize tr1)) ls
tr2 : nat_tree
============================
ntsize
match ls with
| Nil => NNode' n (Cons tr2 Nil)
| Cons tr trs => NNode' n (Cons (ntsplice tr tr2) trs)
end = S (plus (ntsize tr2) (sum (map ntsize ls)))
]]
After a few moments of squinting at this goal, it becomes apparent that we need to do a case analysis on the structure of [ls]. The rest is routine. *)
destruct ls; crush.
(** We can go further in automating the proof by exploiting the hint mechanism.%\index{Vernacular commands!Hint Extern}% *)
Restart.
Hint Extern 1 (ntsize (match ?LS with Nil => _ | Cons _ _ => _ end) = _) =>
destruct LS; crush.
induction tr1 using nat_tree_ind'; crush.
Qed.
(* end thide *)
(** We will go into great detail on hints in a later chapter, but the only important thing to note here is that we register a pattern that describes a conclusion we expect to encounter during the proof. The pattern may contain unification variables, whose names are prefixed with question marks, and we may refer to those bound variables in a tactic that we ask to have run whenever the pattern matches.
The advantage of using the hint is not very clear here, because the original proof was so short. However, the hint has fundamentally improved the readability of our proof. Before, the proof referred to the local variable [ls], which has an automatically generated name. To a human reading the proof script without stepping through it interactively, it was not clear where [ls] came from. The hint explains to the reader the process for choosing which variables to case analyze, and the hint can continue working even if the rest of the proof structure changes significantly. *)
(** * Manual Proofs About Constructors *)
(** It can be useful to understand how tactics like %\index{tactics!discriminate}%[discriminate] and %\index{tactics!injection}%[injection] work, so it is worth stepping through a manual proof of each kind. We will start with a proof fit for [discriminate]. *)
Theorem true_neq_false : true <> false.
(* begin thide *)
(** We begin with the tactic %\index{tactics!red}%[red], which is short for "one step of reduction," to unfold the definition of logical negation. *)
red.
(** %\vspace{-.15in}%[[
============================
true = false -> False
]]
The negation is replaced with an implication of falsehood. We use the tactic %\index{tactics!intro}%[intro H] to change the assumption of the implication into a hypothesis named [H]. *)
intro H.
(** %\vspace{-.15in}%[[
H : true = false
============================
False
]]
This is the point in the proof where we apply some creativity. We define a function whose utility will become clear soon. *)
Definition toProp (b : bool) := if b then True else False.
(** It is worth recalling the difference between the lowercase and uppercase versions of truth and falsehood: [True] and [False] are logical propositions, while [true] and [false] are Boolean values that we can case-analyze. We have defined [toProp] such that our conclusion of [False] is computationally equivalent to [toProp false]. Thus, the %\index{tactics!change}%[change] tactic will let us change the conclusion to [toProp false]. The general form [change e] replaces the conclusion with [e], whenever Coq's built-in computation rules suffice to establish the equivalence of [e] with the original conclusion. *)
change (toProp false).
(** %\vspace{-.15in}%[[
H : true = false
============================
toProp false
]]
Now the righthand side of [H]'s equality appears in the conclusion, so we can rewrite, using the notation [<-] to request to replace the righthand side of the equality with the lefthand side.%\index{tactics!rewrite}% *)
rewrite <- H.
(** %\vspace{-.15in}%[[
H : true = false
============================
toProp true
]]
We are almost done. Just how close we are to done is revealed by computational simplification. *)
simpl.
(** %\vspace{-.15in}%[[
H : true = false
============================
True
]]
*)
trivial.
Qed.
(* end thide *)
(** I have no trivial automated version of this proof to suggest, beyond using [discriminate] or [congruence] in the first place.
%\medskip%
We can perform a similar manual proof of injectivity of the constructor [S]. I leave a walk-through of the details to curious readers who want to run the proof script interactively. *)
Theorem S_inj' : forall n m : nat, S n = S m -> n = m.
(* begin thide *)
intros n m H.
change (pred (S n) = pred (S m)).
rewrite H.
reflexivity.
Qed.
(* end thide *)
(** The key piece of creativity in this theorem comes in the use of the natural number predecessor function [pred]. Embodied in the implementation of [injection] is a generic recipe for writing such type-specific functions.
The examples in this section illustrate an important aspect of the design philosophy behind Coq. We could certainly design a Gallina replacement that built in rules for constructor discrimination and injectivity, but a simpler alternative is to include a few carefully chosen rules that enable the desired reasoning patterns and many others. A key benefit of this philosophy is that the complexity of proof checking is minimized, which bolsters our confidence that proved theorems are really true. *)
|
/*
* NAME
* ----
*
* decoder - specialized decoder
*
* DESCRIPTION
* -----------
*
* This is a specialized decoder designed
* to map the 7-bit addresses to the following
* active low enable signals.
*
* Full address decoding is used so devices cannot
* be inadvertly addressed using out of bounds addresses.
*
* address (hex) | device
* ----------------+---------------
* 0x74 | switch_ce_n
* 0x6C | bar_led_ce_n
* 0x50 - 0x5F | mem2_ce_n
* 0x2F | board_led_ce_n
* 0x00 - 0x0F | mem1_ce_n
*
* AUTHOR
* ------
*
* Jeremiah Mahler <[email protected]>
*
*/
module decoder(
input [6:0] address,
output reg bar_led_ce_n,
board_led_ce_n,
switch_ce_n,
mem1_ce_n,
mem2_ce_n);
always @(address) begin
// default, disabled
switch_ce_n = 1'b1;
bar_led_ce_n = 1'b1;
mem2_ce_n = 1'b1;
board_led_ce_n = 1'b1;
mem1_ce_n = 1'b1;
casex (address)
7'h74: switch_ce_n = 1'b0;
7'h6C: bar_led_ce_n = 1'b0;
7'h5?: mem2_ce_n = 1'b0;
7'h2F: board_led_ce_n = 1'b0;
7'h0?: mem1_ce_n = 1'b0;
endcase
end
endmodule
|
// megafunction wizard: %ROM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: rominout2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rominout2 (
address_a,
address_b,
clock,
q_a,
q_b);
input [8:0] address_a;
input [8:0] address_b;
input clock;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire sub_wire2 = 1'h0;
wire [31:0] sub_wire3 = 32'h0;
wire [31:0] q_b = sub_wire0[31:0];
wire [31:0] q_a = sub_wire1[31:0];
altsyncram altsyncram_component (
.clock0 (clock),
.wren_a (sub_wire2),
.address_b (address_b),
.data_b (sub_wire3),
.wren_b (sub_wire2),
.address_a (address_a),
.data_a (sub_wire3),
.q_b (sub_wire0),
.q_a (sub_wire1)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.eccstatus (),
.rden_a (),
.rden_b ()
// synopsys translate_on
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "./MIF/rominit.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.numwords_b = 512,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 9,
altsyncram_component.widthad_b = 9,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./MIF/rominit.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INIT_FILE STRING "./MIF/rominit.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 GND 0 0 32 0
// Retrieval info: CONNECT: @data_b 0 0 32 0 GND 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rominout2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rominout2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rominout2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rominout2.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rominout2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rominout2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2_1_V
`define SKY130_FD_SC_HD__AND2_1_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2AI_4_V
`define SKY130_FD_SC_LS__O2BB2AI_4_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o2bb2ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2bb2ai_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2bb2ai_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2AI_4_V
|
// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
// Date : Wed Apr 16 15:53:33 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/lab_5/part_1/ip/fir/fir_stub.v
// Design : fir
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module fir(aclk, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[39:0]" */;
input aclk;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [15:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [39:0]m_axis_data_tdata;
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Clamp_block1.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Clamp_block1
// Source Path: velocityControlHdl/Control_Velocity/Rotor_Velocity_Control/Clamp
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Clamp_block1
(
preSat,
saturated,
preIntegrator,
Clamp
);
input signed [35:0] preSat; // sfix36_En22
input saturated;
input signed [35:0] preIntegrator; // sfix36_En35
output Clamp;
wire Compare_To_Zero_out1;
wire Compare_To_Zero1_out1;
wire Compare_To_Zero_out1_1;
wire Logical_Operator_out1;
// <S26>/Compare To Zero
assign Compare_To_Zero_out1 = (preIntegrator <= 36'sh000000000 ? 1'b1 :
1'b0);
// <S26>/Compare To Zero1
assign Compare_To_Zero1_out1 = (preSat <= 36'sh000000000 ? 1'b1 :
1'b0);
// <S26>/Logical Operator
assign Compare_To_Zero_out1_1 = ~ (Compare_To_Zero_out1 ^ Compare_To_Zero1_out1);
// <S26>/AND
assign Logical_Operator_out1 = Compare_To_Zero_out1_1 & saturated;
assign Clamp = Logical_Operator_out1;
endmodule // velocityControlHdl_Clamp_block1
|
`timescale 1ns / 1ps
// @module
// decode 8421 bcd code to segment code
// seg_data[7:0]a: dp-G-F-E-D-C-B-A
// @input
// bcd_data: raw bcd(8421) code
// @output
// seg_data: 8 bit seg_data binding to board
module bcd_to_segment
(
input [3:0] bcd_data,
output reg [7:0] seg_data
);
always @(bcd_data) begin
case (bcd_data)
4'b0000: seg_data <= 8'b11000000; // 0
4'b0001: seg_data <= 8'b11111001; // 1
4'b0010: seg_data <= 8'b10100100; // 2
4'b0011: seg_data <= 8'b10110000; // 3
4'b0100: seg_data <= 8'b10011001; // 4
4'b0101: seg_data <= 8'b10010010; // 5
4'b0110: seg_data <= 8'b10000010; // 6
4'b0111: seg_data <= 8'b11111000; // 7
4'b1000: seg_data <= 8'b10000000; // 8
4'b1001: seg_data <= 8'b10010000; // 9
4'b1010: seg_data <= 8'b01111111; // dp
default: seg_data <= 8'b11111111; // off
endcase
end
endmodule |
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)fpuassign.v 1.1 4/7/92
//
`define NoSlices 4
`define BitsInFracSN 24
`define BitsInFracDB 53
`define FracWidth 58 /* `BitsInFracDB + 7 */
`define FracWidthM1 57
`define FracWidthM3 55 /* `BitsInFracDB + 7 */
`define FracMSB 57 /* `FracWidth - 1 */
`define FracMSBM1 56 /* `FracWidth - 2 */
`define FracMSBM3Pos 55'h20_0000_0000_0000
`define FracMSBM3Mask 55'h100_0000_0000_0000
`define FracMSBM5Pos 53'h40_0000_0000_0000
`define ExpWidth 13
`define ExpWidthM3 10
`define ExpWidthM4 9
`define ExpWidthM8 5
`define ExpWidthM11 2
`define ExpMSB 12 /* ExpWidth - 1 */
`define ExpFPMSBSN 7
`define ExpFPMSBDB 10
`define NoMwords 256
`define FPMSBP1 56
`define FPMSB 55 /* (`BitsInFracDB - 1) + 5 */
`define FPMSBM1 54 /* (`BitsInFracDB - 1) + 5 */
`define FPLSBSN 32 /* `FPMSB - (`BitsInFracSN - 1) */
`define FPLSBDB 3 /* FPMSB - (`BitsInFracDB - 1) */
`define NoOfBitsAboveMSB 2
`define NormMSB 16
`define SN 0
`define DB 1
`define MIAddrWidth 8 /* fb_field_width */
`define MIMSB 7 /* MIAddrWidth -1 */
`define MIptrWidth 8 /* MIAddrWidth */
`define MIptrMSB 7 /* MIptrWidth - 1 */
`define MulCarry 1
`define MulSticky 0
`define NoSlices 4
`define MultipLSBDBM1 1
`define MultipLSBDB 0
`define MultipMSBDB 8
`define MultipLSBSN 32
`define MultipMSBSN 40
// follows define list of frac module line 2450
`define start_rom_outputs 0
`define start_control_fields 0
`define start_micontrol_field 0
`define u_MIptrFromInstructionN 0
`define u_MIptrFromInstructionB 1
`define u_NullifyOnBranchOr 2
`define end_micontrol_field 2
`define fb_field_width 8
`define start_fb_field 3
`define end_fb_field 10
`define u_start_fb_field 3
`define u_end_fb_field 10
`define condition_field_width 5
`define start_condition_field 11
`define fbandcondwidth 13
`define end_condition_field 15
`define u_Cond_LengthSingle 1
`define u_Cond_SignsDiffer 2
`define u_Cond_ExpResultNegative 3
`define u_Cond_ExpAregOdd 4
`define u_Cond_SignAregNegative 5
`define u_Cond_RoundMinus 6
`define u_Cond_MonadicException 7
`define u_Cond_notFracResultZero 8
`define u_Cond_FracResultZero 9
`define u_Cond_FracOverflow 10
`define u_Cond_FracResultNegative 11
`define u_Cond_ExpResultZero 12
`define u_Cond_notFracAregSignaling 13
`define u_Cond_TrueForSubSignsCase 14
`define u_Cond_notRoundingCondition 15
`define start_swap_control_field 16
`define u_PreventSwapIfBgtA 16
`define end_swap_control_field 16
`define start_control_field 17
`define u_OprExc 17
`define end_control_field 17
`define start_shifter_field 18
`define u_LeftnotRight 18
`define u_ShiftForInt 19
`define u_ShiftBy8 20
`define u_ShiftForAlign 21
`define end_shifter_field 21
`define end_control_fields 21
`define width_control_fields 22
`define start_status_field 22
`define u_status0 22
`define u_status1 23
`define u_status2 24
`define u_status3 25
`define u_Unimplemented 26
`define end_status_field 26
`define start_exp_field 27
`define start_exp_result_field 27
`define u_ExpALUOpSub 27
`define u_ExpALUCin 27
`define u_ExpALUCinFromRound 28
`define start_exp_xbus_field 29
`define u_ExpXbusFromFunc0 29
`define u_ExpXbusFromFunc1 30
`define end_exp_xbus_field 30
`define start_exp_ybus_field 31
`define u_ExpYbusFromFunc0 31
`define u_ExpYbusFromFunc1 32
`define end_exp_ybus_field 32
`define start_constant_field 33
`define u_ConstantFromFunc0 33
`define u_ConstantFromFunc1 34
`define end_constant_field 34
`define end_exp_result_field 34
`define start_exp_areg_field 35
`define u_ExpAregFromFunc0 35
`define u_ExpAregFromFunc1 36
`define end_exp_areg_field 36
`define start_exp_breg_field 37
`define u_ExpBregFromFunc0 37
`define u_ExpBregFromFunc1 38
`define end_exp_breg_field 38
`define start_sign_field 39
`define u_SignResultFromFunction0 39
`define u_SignResultFromFunction1 40
`define u_SignAregFromResult 41
`define u_SetRoundingModeToMinus 42
`define u_ToggleLength 43
`define end_sign_field 43
`define end_exp_field 43
`define start_frac_field 44
`define start_frac_result_field 44
`define start_frac_alu_field 44
`define u_FracALUOpSub 44
`define end_frac_alu_field 44
`define start_frac_xbus_field 45
`define u_FracXbusFromDest0 45
`define u_FracXbusFromDest1 46
`define u_FracXbusFromDest2 47
`define end_frac_xbus_field 47
`define start_frac_ybus_field 48
`define u_FracYbusOrSticky 48
`define u_FracYbusFromAregSR1 49
`define u_FracYbusFromAreg 50
`define u_FracYbusFromTreg 51
`define u_FracYbusFromFunc0 52
`define u_FracYbusFromFunc1 53
`define u_FracYbusFromFunc2 54
`define u_FracALUOpForDivOrSQRTStep 55
`define end_frac_ybus_field 55
`define end_frac_result_field 55
`define start_frac_areg_field 56
`define u_FracAregFromFunc0 56
`define u_FracAregFromFunc1 57
`define u_FracAregFromFunc2 58
`define end_frac_areg_field 58
`define start_frac_breg_field 59
`define u_FracBregFromFunc0 59
`define u_FracBregFromFunc1 60
`define end_frac_breg_field 60
`define start_frac_creg_field 61
`define u_FracCregFromFunc0 61
`define u_FracCregFromFunc1 62
`define end_frac_creg_field 62
`define start_frac_treg_field 63
`define u_FracTregFromResult 63
`define u_ResetMul 63
`define end_frac_treg_field 63
`define end_frac_field 63
`define no_of_rom_outputs 64
`define RomWidthM1 63
`define RomWidth 64
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)fpufpc_2.0.v 1.17 4/15/93
//
// **************************************************************
// High Level model of FPU/FPC
//
// This module is the top level module for the FPU/FPC. It defines
// the interface signals and instantiates the following seven modules:
//
// fp_fpc, fp_rf, fp_ctl, fp_exp, fp_frac, fp_rom
//
// **************************************************************
/*
module fpufpc (ss_clock, ss_reset, ld_fpu_w, inst_for_int,
iu_epc, hld_dirreg, ext_valid_decode, fold_annul_e,
ext_flush, ext_hold, ext_hold1, ext_fxack, ext_fhold,
ext_fexc, ext_fcc, ext_fccv, fhold_d1, fhold_fqfull_d1,
fload_wait_w, fp_dout_e,
fp_fpc_scan_in, fprf_scan_out, ss_scan_mode );
input [63:0] ld_fpu_w; // Data-cache output bus
input [31:0] inst_for_int; // Input to D-stage instruction register
input [31:2] iu_epc; // tap from IU E-stage pc (30-bits)
input ss_clock; // Floating pt. unit clock inputs
input ss_reset, // Floating pt. unit reset input
hld_dirreg, // inverted load signal for decode register
ext_valid_decode, // Valid instr in decode
fold_annul_e, // inst in E is annuled
ext_flush; // FPU flush (IU trap)
input [2:0] ext_hold; // IU pipeline held (frozen) from mhold, etc.
input ext_hold1, // duplicate of ext_hold
ext_fxack, // Floating pt. exception acknowledge
fp_fpc_scan_in, // scan data input
ss_scan_mode; // scan enable
output ext_fhold, // Floating point hold (interlocks the IU)
ext_fexc; // Floating point exception signal
output [1:0] ext_fcc; // Floating point condition codes
output ext_fccv, // Floating point condition codes valid
fhold_d1, // delayed ext_fhold used by perf counter
fhold_fqfull_d1, // delayed fq_full used by perf counter
fload_wait_w; // FPop is currently executing, and may trap
output [63:0] fp_dout_e; // Data Out Bus
output fprf_scan_out; // scan data output
// FPP Operand & Result busses, reg file input/output busses,
wire [54:3] FracResult ;
wire [10:0] ExpResult ;
wire SignResult, SNnotDB ;
wire [63:0] fprf_dout1, fprf_dout2, fprf_dout3, fprf_din ;
// input data (from Data-cache) for the FSR register
wire [18:0] fsr_data_in = {ld_fpu_w[31:30], ld_fpu_w[27:23], ld_fpu_w[11:0]} ;
// FPP status: cond. codes and exception bits
wire [1:0] ConditionCodes;
wire [5:0] Excep;
wire fpm_inx, fpm_unfin ;
// Reg file read and write addresses, and control
wire [3:0] fprf_ra1;
wire [3:0] fprf_ra2;
wire [3:0] fprf_ra3;
wire [3:0] fprf_wa;
wire [5:0] fprf_byp1, fprf_byp2, fprf_byp3;
wire [1:0] fprf_algn1, fprf_algn2;
wire [1:0] fprf_hold_din;
wire [1:0] fprf_we;
// FP instruction and rounding mode bits for Meiko core
wire [9:0] FpInst;
wire [1:0] RoundingMode;
// exception status from Meiko core
wire [7:0] fpstat = {ConditionCodes, Excep};
// Datapath and FPP control signals
wire fpm_start, fpp_fop, fpp_ld, fpp_reset ;
wire [1:0] res_select, fpm_inst ;
wire rfin_select ;
wire FpBusyPhi2; // FPP status signal (busy)
// scan signals
wire fp_fpc_scan_in, fp_fpc_scan_out;
wire fprf_scan_out, fp_fpm_scan_out, fp_rom_scan_out;
wire fp_exp_scan_out, fp_ctl_scan_out, fp_frac_scan_out;
// Floating Point Control unit module instance
fp_fpc fpfpc (.ss_clock(ss_clock), .ss_reset(ss_reset),
.ext_valid_decode(ext_valid_decode),
.fold_annul_e(fold_annul_e),
.ext_flush(ext_flush), .ext_hold(ext_hold[2:0]),
.ext_fxack(ext_fxack),
.hld_dirreg(hld_dirreg), .FpBusyPhi2(FpBusyPhi2),
.fpm_inx(fpm_inx), .fpm_unfin(fpm_unfin),
.fpstat(fpstat), .fsr_data_in(fsr_data_in),
.inst_for_int(inst_for_int), .iu_epc(iu_epc),
.fprf_dout3(fprf_dout3), .fp_dout_e(fp_dout_e),
.FpInst(FpInst), .fpm_inst(fpm_inst),
.RoundingMode(RoundingMode),.ext_fcc(ext_fcc),
.ext_fhold(ext_fhold), .fpm_start(fpm_start),
.fpp_fop(fpp_fop),
.fpp_ld(fpp_ld), .fpp_reset(fpp_reset), .ext_fexc(ext_fexc),
.fhold_d1(fhold_d1), .fhold_fqfull_d1(fhold_fqfull_d1),
.res_select(res_select), .rfin_select(rfin_select),
.fprf_wa(fprf_wa), .fprf_ra1(fprf_ra1), .fprf_ra2(fprf_ra2),
.fprf_ra3(fprf_ra3), .fprf_hold_din(fprf_hold_din),
.fprf_we(fprf_we),
.fprf_byp1(fprf_byp1), .fprf_byp2(fprf_byp2),
.fprf_byp3(fprf_byp3), .fprf_algn1(fprf_algn1),
.fprf_algn2(fprf_algn2), .ext_fccv(ext_fccv),
.fload_wait_w(fload_wait_w),
.ss_scan_mode(ss_scan_mode),
.fp_fpc_scan_in(fp_fpc_scan_in),
.fp_fpc_scan_out(fp_fpc_scan_out) );
// FPU Register File module instance
fp_rf fprf (.ss_clock(ss_clock), .ss_scan_mode(ss_scan_mode),
.fp_scan_in(fp_fpm_scan_out),
.hold_din(fprf_hold_din), .fp_hold_ra3(ext_hold1),
.fp_we(fprf_we),
.fp_algn1(fprf_algn1), .fp_algn2(fprf_algn2),
.fp_byp1(fprf_byp1), .fp_byp2(fprf_byp2), .fp_byp3(fprf_byp3),
.fp_wa(fprf_wa), .fp_ra1(fprf_ra1), .fp_ra2(fprf_ra2),
.fp_ra3(fprf_ra3),
.fp_din(fprf_din), .fp_dout1(fprf_dout1), .fp_dout2(fprf_dout2),
.fp_dout3(fprf_dout3), .fp_scan_out(fprf_scan_out) );
// **********************************************************
// all modules below this line are part of the Meiko FPU core
// **********************************************************
//-----------------------------------------------------------------------------
wire FpOp, FpLd, Reset, FpBusy;
assign FpOp = fpp_fop ;
assign FpLd = fpp_ld ;
assign Reset = fpp_reset ;
assign FpBusyPhi2 = FpBusy ;
*/
// This module header is used when testing the FPU core by itself.
// Meiko FPU top-level interconnect module
//
// This interconnect module was produced by Synopsys grouping and then edited
// by hand () to remove hierarchy from signal names and make
// things more readable.
// * ***********************
module FPU ( ss_clock, FpInst, FpOp, FpLd, Reset,
fprf_dout1, fprf_dout2, RoundingMode,
FpBusy, FracResult, ExpResult, SignResult, SNnotDB,
Excep, ConditionCodes,
ss_scan_mode, fp_ctl_scan_in, fp_ctl_scan_out );
input ss_clock, FpOp, FpLd, Reset, ss_scan_mode, fp_ctl_scan_in;
input [9:0] FpInst;
output [1:0] ConditionCodes;
input [63:0] fprf_dout1;
input [63:0] fprf_dout2;
output [5:0] Excep;
input [1:0] RoundingMode;
output [54:3] FracResult;
output [10:0] ExpResult;
output FpBusy, SignResult, SNnotDB, fp_ctl_scan_out;
// ************************** */
wire FracAregLoadEn, FracBregLoadEn, FracCregLoadEn, FracCregLC,
FracTregLoadEn, SROneMore, SRToSticky, notStickyInForSR,
InitialMulStep, InitialCarryBit, SumCarryLoadEn, SumOut0,
CarryOut0, CarryOut3, RomOutputs_18, RomOutputs_55, notFracYFromD1A,
notFracYFromD2A, notFracYFromD3A, notSticky1, FracBregSign,
BregFPMSBM1, notAM31_3, notAM2_0, StickyForSR1, AregMaster_32,
notAregMasterFPMSBP1, CALSB, CBLSB, CCLSB, notFracZero, FracZero,
FracAgtB, SubResultNorm, Conditionals_10, notPossibleOv, notNO_1,
RomOutputs_20, ExpAregLoadEn, ExpAregLC0, ExpAregLC1, ExpBregLoadEn,
ExpBregLC0, ExpBregLC1, RomOutputs_27, CarryIn, Constantb, Constantc,
Constantd, Constante, Constantf, Constantg, Constanth, Conditionals_12,
Conditionals_3, notAInfNAN, notAZeroDenorm, notBInfNAN, notBZeroDenorm,
notExpUnderflow, notExpOverflow, notExpException, OprSNnotDB ;
wire [2:0] FracAregLC ;
wire [2:0] FracBregLC ;
wire [1:0] FracYbusLSBs ;
wire [1:0] InFromCregOr0 ;
wire [1:0] InForCreg ;
wire [1:0] InForCregDB ;
wire [32:29] RomOutputs_32_29 ;
wire [46:44] RomOutputs_46_44 ;
wire [4:0] FracRound ;
wire [3:0] SRControl ;
wire [3:0] SLControl ;
wire [2:0] LIB ;
wire [8:0] TopBitsIn ;
wire [3:0] Shift ;
wire [3:0] Pos ;
wire [3:0] Zero ;
wire [4:0] MulLenSel ;
wire [3:0] notSticky4 ;
wire [1:0] Sticky2 ;
wire [1:0] StickyExtra ;
wire [1:0] CregSNBits ;
wire [1:0] CregInSL2SQRT ;
wire [8:0] notMultip ;
wire [57:40] AregMaster_57_40 ;
wire [7:0] AregMaster_7_0 ;
wire [1:0] TregLSBs ;
wire [2:0] SumInLSBs ;
wire [2:0] CarryInLSBs ;
wire [1:0] SALSBs ;
wire [1:0] SBLSBs ;
wire [1:0] SCLSBs ;
wire [3:0] StepRemBits ;
wire [3:1] notsh ;
wire [7:0] ExpIn ;
wire [12:0] notExpShiftResult ;
wire [7:0] SelectedMIptr ;
wire [63:0] U_RomOutputs ;
// Meiko FPU core control logic
fp_ctl fpctl ( .ss_clock (ss_clock), .AregMaster_32 (AregMaster_32),
.BregFPMSBM1 (BregFPMSBM1), .CALSB (CALSB), .CBLSB (CBLSB),
.CCLSB (CCLSB), .Conditionals_3 (Conditionals_3),
.Conditionals_10 (Conditionals_10), .Conditionals_12 (Conditionals_12),
.FpLd (FpLd), .FpOp (FpOp), .FracAgtB (FracAgtB),
.FracBregSign (FracBregSign), .FracZero (FracZero),
.notAInfNAN (notAInfNAN), .notAM31_3 (notAM31_3),
.notAM2_0 (notAM2_0), .notAregMasterFPMSBP1 (notAregMasterFPMSBP1),
.notAZeroDenorm (notAZeroDenorm), .notBInfNAN (notBInfNAN),
.notBZeroDenorm (notBZeroDenorm), .notExpUnderflow (notExpUnderflow),
.notExpOverflow (notExpOverflow), .notExpException (notExpException),
.notPossibleOv (notPossibleOv), .notFracZero (notFracZero),
.notSticky1 (notSticky1), .ResetIn (Reset), .RS2_63 (fprf_dout2[63] ),
.RS1_63 (fprf_dout1[63] ), .StickyForSR1 (StickyForSR1),
.SubResultNorm (SubResultNorm), .AregMaster_57_40 (AregMaster_57_40),
.AregMaster_7_0 (AregMaster_7_0), .CarryInLSBs (CarryInLSBs),
.CregInSL2SQRT (CregInSL2SQRT), .CregSNBits (CregSNBits),
.ExpIn (ExpIn), .FpInst (FpInst),
.notExpShiftResult (notExpShiftResult), .notMultip (notMultip),
.notSticky4 (notSticky4), .RoundingMode (RoundingMode),
.SALSBs (SALSBs), .SBLSBs (SBLSBs), .SCLSBs (SCLSBs),
.StepRemBits (StepRemBits), .Sticky2 (Sticky2),
.StickyExtra (StickyExtra), .SumInLSBs (SumInLSBs),
.TregLSBs (TregLSBs), .U_RomOutputs (U_RomOutputs ),
.CarryIn (CarryIn), .CarryOut0 (CarryOut0), .CarryOut3 (CarryOut3),
.Constantb (Constantb), .Constantc (Constantc), .Constantd (Constantd),
.Constante (Constante), .Constantf (Constantf), .Constantg (Constantg),
.Constanth (Constanth), .ExpAregLC0 (ExpAregLC0),
.ExpAregLC1 (ExpAregLC1), .ExpAregLoadEn (ExpAregLoadEn),
.ExpBregLC0 (ExpBregLC0), .ExpBregLC1 (ExpBregLC1),
.ExpBregLoadEn (ExpBregLoadEn), .FracAregLoadEn (FracAregLoadEn),
.FracBregLoadEn (FracBregLoadEn), .FracCregLC (FracCregLC),
.FracCregLoadEn (FracCregLoadEn), .FracTregLoadEn (FracTregLoadEn),
.FpBusy (FpBusy), .InitialCarryBit (InitialCarryBit),
.InitialMulStep (InitialMulStep), .notFracYFromD1A (notFracYFromD1A),
.notFracYFromD2A (notFracYFromD2A), .notFracYFromD3A (notFracYFromD3A),
.notNO_1 (notNO_1), .notStickyInForSR (notStickyInForSR),
.OprSNnotDB (OprSNnotDB), .RomOutputs_18 (RomOutputs_18),
.RomOutputs_20 (RomOutputs_20), .RomOutputs_27 (RomOutputs_27),
.RomOutputs_55 (RomOutputs_55), .SignResult (SignResult),
.SNnotDB (SNnotDB), .SROneMore (SROneMore), .SRToSticky (SRToSticky),
.SumCarryLoadEn (SumCarryLoadEn), .SumOut0 (SumOut0),
.ConditionCodes (ConditionCodes), .Excep (Excep),
.FracAregLC (FracAregLC), .FracBregLC (FracBregLC),
.FracRound (FracRound), .FracYbusLSBs (FracYbusLSBs),
.InForCreg (InForCreg), .InForCregDB (InForCregDB),
.InFromCregOr0 (InFromCregOr0), .LIB (LIB), .MulLenSel (MulLenSel),
.notsh (notsh), .Pos (Pos), .RomOutputs_32_29 (RomOutputs_32_29),
.RomOutputs_46_44 (RomOutputs_46_44), .SelectedMIptr(SelectedMIptr ),
.Shift (Shift), .SRControl (SRControl), .TopBitsIn (TopBitsIn),
.Zero (Zero),
.ss_scan_mode (ss_scan_mode),
.fp_ctl_scan_in (fp_exp_scan_out),
.fp_ctl_scan_out (fp_ctl_scan_out) );
// Instance of the ROM Megacell
fp_rom fprom ( .ss_clock(ss_clock),
.rom_adr(SelectedMIptr),
.rom_dout(U_RomOutputs),
.rom_scan_out(fp_rom_scan_out),
.rom_scan_in(fp_ctl_scan_out),
.ss_scan_mode(ss_scan_mode) );
// exponent datapath
fp_exp fpexp ( .ss_clock (ss_clock ), .SNnotDB (SNnotDB ),
.OprSNnotDB (OprSNnotDB ), .RS2_exp (fprf_dout2[62:52] ),
.RS1_exp (fprf_dout1[62:52] ), .FracAregForInt (AregMaster_57_40[54:47] ),
.notSLFromNorm ({notNO_1, notsh[3:1]} ), .ShiftBy8 (RomOutputs_20 ),
.ExpAregLoadEn (ExpAregLoadEn ), .ExpAregLC0 (ExpAregLC0 ),
.ExpAregLC1 (ExpAregLC1 ), .ExpBregLoadEn (ExpBregLoadEn ),
.ExpBregLC0 (ExpBregLC0 ), .ExpBregLC1 (ExpBregLC1 ),
.ExpXCtl0 (RomOutputs_32_29[29] ), .ExpXCtl1 (RomOutputs_32_29[30] ),
.ExpYCtl0 (RomOutputs_32_29[31] ), .ExpYCtl1 (RomOutputs_32_29[32] ),
.Sub(RomOutputs_27 ), .CarryIn (CarryIn ), .Constantb (Constantb ),
.Constantc (Constantc ), .Constantd (Constantd ),
.Constante (Constante ), .Constantf (Constantf ),
.Constantg (Constantg ), .Constanth (Constanth ),
.AregMasterBufOut (ExpIn ), .ExpResultBuf (ExpResult ),
.notExpShiftResult (notExpShiftResult[12:0] ),
.ExpZero (Conditionals_12 ), .ExpResult_12 (Conditionals_3 ),
.SLControl (SLControl ), .notAInfNaN (notAInfNAN ),
.notAZeroDenorm (notAZeroDenorm ), .notBInfNaN (notBInfNAN ),
.notBZeroDenorm (notBZeroDenorm ), .notUnderflow (notExpUnderflow ),
.notOverflow (notExpOverflow ), .notExpException (notExpException ),
.ss_scan_mode (ss_scan_mode),
.fp_exp_scan_in (fp_fpc_scan_out),
.fp_exp_scan_out (fp_exp_scan_out) );
// fraction datapath
fp_frac fpfrac (.ss_clock (ss_clock ), .FracAregLoadEn (FracAregLoadEn),
.FracAregLC (FracAregLC ), .FracBregLoadEn (FracBregLoadEn ),
.FracBregLC (FracBregLC ), .FracCregLoadEn (FracCregLoadEn ),
.FracCregLC (FracCregLC ), .FracTregLoadEn (FracTregLoadEn ),
.FracYbusLSBs (FracYbusLSBs ), .InFromCregOr0 (InFromCregOr0 ),
.InForCreg (InForCreg ), .InForCregDB (InForCregDB ),
.Constantb (RomOutputs_46_44[45] ), .Constantd (FracRound[4] ),
.Constante (FracRound[3] ), .Constantf (FracRound[2] ),
.Constantg (FracRound[1] ), .Constanth (FracRound[0] ),
.RS2_frac (fprf_dout2[54:0] ), .RS1_frac (fprf_dout1[54:0] ),
.SNnotDB (SNnotDB ), .OprSNnotDB(OprSNnotDB), .SRControl (SRControl ),
.SROneMore (SROneMore ), .SRToSticky (SRToSticky ),
.SLControl (SLControl ), .LIB (LIB ), .TopBitsIn (TopBitsIn ),
.notStickyInForSR (notStickyInForSR ), .Shift (Shift ),
.Pos (Pos ), .Zero (Zero ), .InitialMulStep (InitialMulStep ),
.InitialCarryBit (InitialCarryBit ),
.SumCarryLoadEn (SumCarryLoadEn ), .MulLenSel (MulLenSel ),
.SumOut0 (SumOut0 ), .CarryOut0 (CarryOut0 ), .CarryOut3 (CarryOut3 ),
.LeftnotRight (RomOutputs_18 ), .FracALUOpSub (RomOutputs_46_44[44] ),
.FracALUOpDiv (RomOutputs_55 ), .notFracYFromD1 (notFracYFromD1A ),
.notFracYFromD2 (notFracYFromD2A ), .notFracYFromD3 (notFracYFromD3A),
.FracXFromB (RomOutputs_46_44[46] ), .notSticky4 (notSticky4 ),
.Sticky2 (Sticky2 ), .notSticky1 (notSticky1 ),
.StickyExtra (StickyExtra ), .Creg_30_29 (CregSNBits ),
.Creg_56_55 (CregInSL2SQRT ), .BregMaster_57 (FracBregSign ),
.BregMaster_54 (BregFPMSBM1 ), .notMultip (notMultip ),
.notAM31_3 (notAM31_3 ), .notAM2_0 (notAM2_0 ),
.StickyForSR1 (StickyForSR1 ),
.AregMaster_57_40 (AregMaster_57_40[57:40] ),
.AregMaster_32 (AregMaster_32 ),
.AregMaster_7_0 (AregMaster_7_0[7:0] ),
.notAregMasterFPMSBP1 (notAregMasterFPMSBP1 ),
.Treg_1_0 (TregLSBs ), .SumInLSBs (SumInLSBs ),
.CarryInLSBs (CarryInLSBs ), .SALSBs (SALSBs ), .SBLSBs (SBLSBs ),
.SCLSBs (SCLSBs ), .CALSB (CALSB ), .CBLSB (CBLSB ), .CCLSB (CCLSB ),
.notFracZero (notFracZero ), .FracZero (FracZero ),
.FracResult_57 (FracAgtB ), .SubResultNorm (SubResultNorm ),
.FracResult_56 (Conditionals_10 ),
.FracResult_55_52 (StepRemBits ), .notPossibleOv (notPossibleOv ),
.FracResultBufout (FracResult ),
.ss_scan_mode (ss_scan_mode),
.fp_frac_scan_in (fp_rom_scan_out),
.fp_frac_scan_out (fp_frac_scan_out) );
/*
fp_fpm fpfpm (.fprf_din( fprf_din[63:0] ),
.fpm_inx(fpm_inx), .fpm_unfin(fpm_unfin),
.fprf_dout1( fprf_dout1[63:0] ), .fprf_dout2( fprf_dout2[63:0] ),
.ld_fpu_w( ld_fpu_w[63:0] ),
.FracResult( FracResult[54:3] ),
.ExpResult( ExpResult[10:0] ),
.SignResult(SignResult),
.fpm_inst( fpm_inst[1:0] ),
.rnd_mode( RoundingMode[1:0] ),
.res_select( res_select[1:0] ),
.rfin_select(rfin_select),
.fpm_start(fpm_start),
.ss_clock(ss_clock),
.ss_scan_mode (ss_scan_mode),
.fp_fpm_scan_in(fp_frac_scan_out),
.fp_fpm_scan_out(fp_fpm_scan_out) );
// Added spare cells
spares fpufpc_spares ();
*/
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)areginexact.v 1.1 4/7/92
//
module AregInexact (RomInexactRound, SNnotDB,
AMCBit, AM32, AM3, notAM31_3, notAM2_0,
Inexact);
input RomInexactRound;
input SNnotDB;
input AMCBit, AM32, AM3, notAM31_3, notAM2_0;
output Inexact;
//Inexact = (AM[0:2] != 0) or (SNnotDB and ((AM[32] & AMCbit) or AM[31:3]))
// or (DBnotSN and ((AM[3] & AMCbit)))
// InexactSN = PostNormBy1SNBit | AM31_19 | AM18_3 | AM2_0
// InexactDB = PostNormBy1DBBit | AM2_0
ME_NAND2 aig2 (AMCBit, AM32, notPostNormBy1SNBit);
ME_NAND2 aig3 (AMCBit, AM3, notPostNormBy1DBBit);
ME_NAND2 aig12 (notPostNormBy1DBBit, notAM2_0, UInexactDB);
ME_NAND2 g_0 (UInexactDB, RomInexactRound, notInexactDB);
ME_NAND3 aig13 (notPostNormBy1SNBit, notAM2_0, notAM31_3, UInexactSN);
ME_NAND2 g_1 (UInexactSN, RomInexactRound, notInexactSN);
ME_NMUX2B aig14 (SNnotDB, notInexactDB, notInexactSN, Inexact);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)aregloadctl.v 1.1 4/7/92
//
module AregLoadCtl (ROM,
LoadOprs,
notAbortWB,
PreventSwap,
FracAregLC, FracAregLoadEn,
LoadFromMult, // Export to Breg
SelInitRemBits);
input [`end_frac_areg_field:`start_frac_areg_field] ROM;
input LoadOprs,
notAbortWB,
PreventSwap;
output [2:0] FracAregLC;
output FracAregLoadEn,
LoadFromMult,
SelInitRemBits;
ME_TIEOFF toff (vdd, gnd);
ME_INVA iopl (LoadOprs, notLoadOprs);
ME_AND2 alcn1 (ROM[`u_FracAregFromFunc2], notLoadOprs,
FracAregLC[2]);
ME_AND2 alcn2 (ROM[`u_FracAregFromFunc1], notLoadOprs,
FracAregLC[1]);
ME_AND2 alcn3 (ROM[`u_FracAregFromFunc0], notLoadOprs,
FracAregLC[0]);
ME_OR4 alcne (ROM[`u_FracAregFromFunc0],
ROM[`u_FracAregFromFunc1],
ROM[`u_FracAregFromFunc2],
LoadOprs,
LoadEn);
//ME_AND3 alcni (LoadEn, notAbortWB, notPreventSwap, FracAregLoadEn);
ME_AND2 alcni (LoadEn, notAbortWB, FracAregLoadEn_p);
ME_NMUX2B_B alcn0 (FracAregLoadEn_p, vdd, PreventSwap, FracAregLoadEn);
ME_AND3 alcnf (ROM[`u_FracAregFromFunc0],
ROM[`u_FracAregFromFunc1],
ROM[`u_FracAregFromFunc2],
LoadFromMult); // 1 1 1
ME_INVA alcn7 (ROM[`u_FracAregFromFunc0], notFunc0);
ME_INVA alcn8 (ROM[`u_FracAregFromFunc2], notFunc2);
ME_AND3_B alcnh (notFunc0,
ROM[`u_FracAregFromFunc1],
notFunc2,
SelInitRemBits); // 0 1 0 ie FracAregFromFracBreg
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)bregloadctl.v 1.1 4/7/92
//
module BregLoadCtl (RomFracBregLC,
RomBSL2InFromC,
LoadOprs,
notAbortWB,
PreventSwap,
LoadFromMult,
CregInSL2SQRT,
FracBregLC, FracBregLoadEn,
InFromCregOr0);
input [`end_frac_breg_field:`start_frac_breg_field] RomFracBregLC;
input LoadFromMult;
input LoadOprs;
input RomBSL2InFromC,
notAbortWB, PreventSwap;
input [1:0] CregInSL2SQRT;
output [2:0] FracBregLC;
output FracBregLoadEn;
output [1:0] InFromCregOr0;
ME_TIEOFF toff (vdd, gnd);
// SQRT Logic
ME_AND2 ssg81 (CregInSL2SQRT[1], RomBSL2InFromC, InFromCregOr0[1]);
ME_AND2 ssg80 (CregInSL2SQRT[0], RomBSL2InFromC, InFromCregOr0[0]);
// Breg Load Control
ME_INVA iopl (LoadOprs, notLoadOprs);
ME_AND2 alcn3 (LoadFromMult, notLoadOprs, FracBregLC[2]);
ME_AND2 alcn2 (RomFracBregLC[`u_FracBregFromFunc1], notLoadOprs, FracBregLC[1]);
ME_AND2 alcn1 (RomFracBregLC[`u_FracBregFromFunc0], notLoadOprs, FracBregLC[0]);
ME_OR4 alcne (RomFracBregLC[`u_FracBregFromFunc0],
RomFracBregLC[`u_FracBregFromFunc1],
LoadFromMult,
LoadOprs,
LoadEn);
//ME_AND3 brme (LoadEn, notAbortWB, notPreventSwap, FracBregLoadEn);
ME_AND2 alcni (LoadEn, notAbortWB, FracBregLoadEn_p);
ME_NMUX2B_B alcn0 (FracBregLoadEn_p, vdd, PreventSwap, FracBregLoadEn);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)carrysavereglsb.v 1.1 4/7/92
//
module carrysaveregslsb (Rom_ResetMul,
notMultip0,
notAbortWB,
SumCarryLoadEn,
InitialMulStep,
/* dhn--01/10/90 notInitialSumZero, */
InitialCarryBit);
input Rom_ResetMul,
notAbortWB,
notMultip0;
output InitialCarryBit,
SumCarryLoadEn,
InitialMulStep;
/*** dhn--01/10/90 output notInitialSumZero ;
//wire notInitialSumZero = InitialCarryBit;
con1 g0 (InitialCarryBit, notInitialSumZero);
*** dhn--01/10/90 ***/
ME_BUFF g00 (notAbortWB, SumCarryLoadEn);
ME_INV_B g01 (notMultip0, InitialCarryBit);
ME_BUFF g02 (Rom_ResetMul, InitialMulStep);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)casegeneration.v 1.1 4/7/92
//
module CaseGeneration (
Rom_Feedback,
Rom_Condition,
SubResultNorm,
Cond_SignsDiffer,
notExpUnderflow, notExpOverflow, notExpException, notPossibleOv, notFracZero,
RCondition,
Feedback);
input [4:0]Rom_Feedback;
input [3:0]Rom_Condition;
input SubResultNorm;
input Cond_SignsDiffer;
input notExpUnderflow, notExpOverflow, notExpException, notPossibleOv, notFracZero;
output [4:0]Feedback;
output RCondition; // Speed critical signal
// ***************************************//
// Case Generation //
// ***************************************//
ME_INV_A cnsb (Rom_Condition[0], notCondSel0);
ME_AND3 cqsb (Rom_Condition[1], Rom_Condition[2], Rom_Condition[3],
Rom_Case);
ME_AND2 ril (Rom_Case, notCondSel0, Rom_Sub_Sign_Case);
ME_AND2_B ris (Rom_Case, Rom_Condition[0], RomRoundCase);
// ***************************************//
// Rounding Case Address Generation //
// ***************************************//
wire [4:0] notUFeedback;
//ME_INVA g1_0 (ExpUnderflow, notExpUnderflow);
//ME_INVA g1_1 (ExpOverflow, notExpOverflow);
//ME_AND2 fzfz (notExpUnderflow, notExpOverflow, notExpException);
// Note SubResultNorm and notPossibleOv are time critical
ME_NAND3_B nrc (SubResultNorm, notExpException, notPossibleOv,
RCondition);
//ME_NAND4 nrc (SubResultNorm, notExpUnderflow, notExpOverflow, notPossibleOv,
// RCondition);
//
// notRCondition(e)
// Ye Olde Criticale Pathe
//
// ***************************************//
// Sign Case Bits //
// ***************************************//
ME_NMUX2B vbxb (Rom_Sub_Sign_Case,
Rom_Feedback[1],
Cond_SignsDiffer,
notUFeedback[1]);
// *********************************************************//
// Generate Feedback address including CASE logic //
// *********************************************************//
ME_INV_A g0_0 (Rom_Feedback[0], notUFeedback[0]);
ME_INV_A g0_2 (Rom_Feedback[2], notUFeedback[2]);
ME_INV_A g0_3 (Rom_Feedback[3], notUFeedback[3]);
ME_INV_A g0_4 (Rom_Feedback[4], notUFeedback[4]);
// Assign rounding case bits
ME_NMUX2B_B ufb0 (RomRoundCase, notUFeedback[0], notExpOverflow, Feedback[0]);
ME_NMUX2B_B ufb1 (RomRoundCase, notUFeedback[1], notExpUnderflow, Feedback[1]);
ME_NMUX2B_B ufb2 (RomRoundCase, notUFeedback[2], SubResultNorm, Feedback[2]);
ME_NMUX2B_B ufb3 (RomRoundCase, notUFeedback[3], notFracZero, Feedback[3]);
ME_NMUX2B_B ufb4 (RomRoundCase, notUFeedback[4], notPossibleOv, Feedback[4]);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)condmux.v 1.1 4/7/92
//
module CondMux (C,
CS,
notReset,
notAbortNulExc,
DyadicOprExc,
notBrTakenMIS,
notBrTaken);
input [15:0] C;
input [4:0] CS;
input notAbortNulExc,
DyadicOprExc,
notReset;
output notBrTakenMIS;
output notBrTaken;
ME_TIEOFF toff (vdd, gnd);
wire [3:0] T;
wire [4:0] CoS;
ME_INVA h_1 (DyadicOprExc, notDyadicOprExc);
ME_AND3_B h_0 (notAbortNulExc, notReset,
notDyadicOprExc,
notPreventBr);
ME_AND2_B c_0(CS[0], notPreventBr, CoS[0]);
ME_AND2_B c_1(CS[1], notPreventBr, CoS[1]);
ME_AND2 c_2(CS[2], notPreventBr, CoS[2]);
ME_AND2 c_3(CS[3], notPreventBr, CoS[3]);
ME_AND2 c_4(CS[4], notPreventBr, CoS[4]);
// C[15] takes different route
ME_MUX4B vx_3 (CoS[0], CoS[1], C[12],C[13],C[14],gnd, T[3]);
ME_MUX4B vx_2 (CoS[0], CoS[1], C[8],C[9],C[10],C[11], T[2]);
ME_MUX8B vx_0 (CoS[0], CoS[1], CoS[2], C[0],C[1],C[2],C[3],C[4],C[5],C[6],C[7],C0_7);
ME_NMUX2B vc_1 (CoS[3], C0_7, T[3], notC0_11);
ME_XOR2_B vd_0 (notC0_11, CoS[4], notBrTakenNoFrac);
ME_INVA vc_2 (CoS[2], notCoS2);
ME_NAND2 vc_3 (notCoS2, CoS[3], notSelFracConds);
ME_NMUX2B vc_4 (notSelFracConds, T[2], notBrTakenNoFrac,
BrTakenSlowRC);
// Make a special case of RoundingCondition CoS = {1, 1, 1, 1, 1} ie invert not Rounding condition
ME_AND4 sp_0 (CoS[0], CoS[1], CoS[2], CoS[3], RCSelected);
ME_AND2 sp_1 (CoS[4], RCSelected, ControlForRCPos);
ME_NMUX2B_B sp_2 (ControlForRCPos, BrTakenSlowRC, C[15], notBrTaken);
ME_NMUX2B_B sp_3 (ControlForRCPos, BrTakenSlowRC, C[15], notBrTakenMIS);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)control.v 1.1 4/7/92
//
module Control (Phi, ResetIn,
notExpAgtB,
notAInfNan, notAZeroDenorm, notBInfNan, notBZeroDenorm,
notExpUnderflow, notExpOverflow, notExpException,
notWaitForShifter, notNO,
SubResultNorm,
notPossibleOv,
Conditionals_14_8, Conditionals_6_0,
FpInst, FpOp, FpLd,
PreventSwap,
PreventSwapExp,
RCondition,
SelectedMIptr,
U_RomOutputs,
RomOutputs,
YDest,
XDest,
CMPDecoded, CMPEDecoded,
AregOprExc,
notAbortWB, Reset,
Busy, NegateOprSign,
UnimpOut );
input Phi, ResetIn;
input notExpAgtB,
notAInfNan, notAZeroDenorm,
notBInfNan, notBZeroDenorm,
notExpUnderflow, notExpOverflow, notExpException,
notWaitForShifter;
input [1:0] notNO;
input SubResultNorm;
input notPossibleOv;
input [14:8] Conditionals_14_8; // Conditional bits (input)
input [ 6:0] Conditionals_6_0; // Conditional bits (input)
input [9:0] FpInst; // FPOP field of instruction
input FpOp, FpLd;
input [`RomWidthM1:0] U_RomOutputs;
output PreventSwap, PreventSwapExp,
RCondition;
output [`MIptrMSB:0] SelectedMIptr;
output [`RomWidthM1:0] RomOutputs;
output [6:0] YDest;
output XDest;
output CMPDecoded, CMPEDecoded;
output AregOprExc,
notAbortWB, Reset,
Busy, NegateOprSign,
UnimpOut;
wire [2:0] ExMIptrLSBs;
wire AregOprExc, RCondition;
wire [15:0] Conditionals;
assign Conditionals = {RCondition, Conditionals_14_8, AregOprExc,
Conditionals_6_0} ;
PreventSwapCtl psc (Conditionals[`u_Cond_FracResultNegative],
notExpAgtB, Conditionals[`u_Cond_ExpResultZero],
RomOutputs[`u_PreventSwapIfBgtA], FpLd,
PreventSwap,
PreventSwapExp);
SampleReset sr (Phi, ResetIn, ResetAbortInst,
ResetImp, Reset, notReset);
NullExcepLogic nel (Phi, notReset,
RomOutputs[`u_NullifyOnBranchOr],
RomOutputs[`u_OprExc],
BTLatched,
notSampledWait,
FpLd,
notAInfNan, notAZeroDenorm,
notBInfNan, notBZeroDenorm,
ExMIptrLSBs,
AregOprExc,
DyadicOprExc,
notAbortNulExc,
notAbortWB);
wire [4:0] Feedback;
CaseGeneration cg (
RomOutputs[`start_fb_field+4:`start_fb_field],
RomOutputs[`start_condition_field+3:`start_condition_field],
SubResultNorm,
Conditionals[`u_Cond_SignsDiffer],
notExpUnderflow, notExpOverflow, notExpException,
notPossibleOv, Conditionals[`u_Cond_notFracResultZero],
RCondition,
Feedback[4:0]);
CondMux cm (Conditionals,
RomOutputs[4+`start_condition_field:`start_condition_field],
notReset,
notAbortNulExc,
DyadicOprExc,
notBranchTakenMIS,
notBranchTaken);
SampledWaitCtl swc (
RomOutputs[`u_ShiftForAlign],
RomOutputs[`u_ShiftForInt],
RomOutputs[`u_LeftnotRight],
notReset,
notAbortNulExc,
notWaitForShifter,
notNO[1:0],
notIdleLatched,
UpdateOutputs,
notSampledWait);
MISelect smi (Phi, notReset,
notBranchTaken,
notDecodedUnimp,
RomOutputs[`u_MIptrFromInstructionN],
RomOutputs[`u_MIptrFromInstructionB],
notAbortInst, notAbortNulExc,
notResetOrUnimp,
DyadicOprExc, notSampledWait,
FpOp,
notSingleCycInst,
BTLatched,
Busy, notIdleLatched,
notInstAndNoExc,
MIptrLoadEnable);
// ***************************************//
// MIptr :- Micro Instruction Pointer //
// ***************************************//
wire [`MIptrMSB:0] RomMIptr, notRomMIptr;
// ***************************************//
// unregistered version of RomMIptr //
// ***************************************//
wire [`MIptrMSB:0] SelectedMIptr;
wire [`RomWidthM1:0] U_RomOutputs; // unbuffered output from ME_UROM
MIptr mip (Phi,
ExMIptrLSBs,
DyadicOprExc,
notInstAndNoExc,
notBranchTakenMIS,
notResetOrUnimp,
MIptrLoadEnable,
{RomOutputs[`end_fb_field:`start_fb_field+5], Feedback[4:0]},
FpInst[7:0],
SelectedMIptr,
RomMIptr,
notRomMIptr);
MicrocodeRom mrom (Phi,
UpdateOutputs,
U_RomOutputs,
RomOutputs,
XDest,
YDest );
EntryCheck ec (notRomMIptr, EntryPoint, notSingleCycInst);
ImplementedCheck ich (Phi, ResetImp, // Can't be Reset
notReset,
FpOp,
EntryPoint, FpInst[9:4],
notDecodedUnimp,
notResetOrUnimp,
notAbortInst, ResetAbortInst,
FPOP2Map,
UnimpOut);
DecodeCmpAndNeg dcs (Phi,
FpInst[2], FpInst[3], FpInst[6], FpInst[7],
FPOP2Map,
CMPDecoded, CMPEDecoded,
NegateOprSign);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)cregloadctl.v 1.1 4/7/92
//
module CregLoadCtl (
// inputs
RomCregCtl,
QuoBits,
notAbortWB,
SNnotDB,
CregSNBits,
// outputs
InForCreg,
InForCregDB,
RomFracBSL2FromC,
FracCregLoadCtl0,
FracCregLoadEn);
input [`end_frac_creg_field:`start_frac_creg_field] RomCregCtl;
input [1:0] QuoBits;
input [1:0] CregSNBits;
input notAbortWB,
SNnotDB;
output [1:0] InForCreg, InForCregDB;
output RomFracBSL2FromC;
output FracCregLoadCtl0,
FracCregLoadEn;
wire [1:0] InForCregSN;
/* *********************************************************
Control Logic For Creg
********************************************************* */
ME_INVA g100 (SNnotDB, DBnotSN);
ME_AND2 fg1s (QuoBits[1], RomCregCtl[`u_FracCregFromFunc0],
InForCregSN[1]);
ME_AND2 fg0s (QuoBits[0], RomCregCtl[`u_FracCregFromFunc0],
InForCregSN[0]);
ME_AND3 fg1d (QuoBits[1], DBnotSN, RomCregCtl[`u_FracCregFromFunc0],
InForCregDB[1]);
ME_AND3 fg0d (QuoBits[0], DBnotSN, RomCregCtl[`u_FracCregFromFunc0],
InForCregDB[0]);
ME_MUX2B fg1 (SNnotDB, CregSNBits[1], InForCregSN[1], InForCreg[1]);
ME_MUX2B fg0 (SNnotDB, CregSNBits[0], InForCregSN[0], InForCreg[0]);
ME_INVA fg9s (RomCregCtl[`u_FracCregFromFunc0], notResultOrQuoBits);
ME_AND2 icr9 (RomCregCtl[`u_FracCregFromFunc1], notResultOrQuoBits,
RomFracBSL2FromC); // 1 0 ie SQRT
ME_INVA fgg (notAbortWB, AbortWB);
ME_NOR2 icr (RomCregCtl[`u_FracCregFromFunc0],
RomCregCtl[`u_FracCregFromFunc1],
notEn);
ME_NOR2 rct (notEn,
AbortWB,
FracCregLoadEn);
/* Feedthroughs */
ME_BUFF g00 (RomCregCtl[`u_FracCregFromFunc1], FracCregLoadCtl0);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)decodecomparesandneg.v 1.1 4/7/92
//
/* Negate sign for the following entries
Inst 045 N
Inst 046 N
Inst 151 N
Inst 152 N
Inst 155 N
Inst 156 N
N = FPOP2Map | x 01xx 01xx
*/
module DecodeCmpAndNeg (
Phi,
FpInst2, FpInst3, FpInst6, FpInst7,
FPOP2Map,
CMPDecoded, CMPEDecoded, NegateOprSign);
input Phi,
FpInst2, FpInst3, FpInst6, FpInst7, FPOP2Map;
output CMPDecoded, CMPEDecoded;
output NegateOprSign;
ME_INVA dcep1 (FpInst2, notFpInst2);
ME_NAND2 dcep2 (FPOP2Map, notFpInst2, notCMP);
ME_NAND2 dcep3 (FPOP2Map, FpInst2, notCMPE);
ME_FD1 dcep4 (Phi, notCMP, , CMPDecoded);
ME_FD1 dcep5 (Phi, notCMPE, , CMPEDecoded);
ME_INVA dcep9 (FpInst3, notFpInst3);
ME_INVA dcep6 (FpInst7, notFpInst7);
ME_AND4 dcep7 (FpInst6, notFpInst7, FpInst2, notFpInst3, DyadicSub);
ME_NOR2 decep8 (FPOP2Map, DyadicSub, s_0);
ME_FD1 iggypop (Phi, s_0, , NegateOprSign);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)decodestatus.v 1.1 4/7/92
//
module DecodeStatus (RomCtl[3:0], StatusControl[6:0]);
input [3:0] RomCtl;
output [6:0] StatusControl;
// A-L are ouputs required // Recoded into patterns
// A 010_0000 // 1101
// B 110_0000 // 1111
// C 000_0100 // 1100
// D 100_0000 // 1110
// E 000_1000 // 1011
// F 100_1000 // 1010
// G 001_0000 // 1001
// H 101_0000 // 1000
// I 010_0011 // 0111
// J 000_0011 // 0110
// K 000_0010 // 0100
// L 000_0000 // 0000
ME_INV_A i0 (RomCtl[3], notRomCtl3);
ME_INV_A i1 (RomCtl[2], notRomCtl2);
ME_INV_A i2 (RomCtl[1], notRomCtl1);
ME_INV_A i3 (RomCtl[0], notRomCtl0);
ME_AND3 b0 (notRomCtl3, RomCtl[2], RomCtl[1], StatusControl[0]);
ME_AND2 b1 (notRomCtl3, RomCtl[2], StatusControl[1]);
ME_AND4 b2 (RomCtl[3], RomCtl[2], notRomCtl1, notRomCtl0, StatusControl[2]);
ME_AND3 b3 (RomCtl[3], notRomCtl2, RomCtl[1], StatusControl[3]);
ME_AND3 b4 (RomCtl[3], notRomCtl2, notRomCtl1, StatusControl[4]);
ME_NAND4 p0 (notRomCtl3, RomCtl[2], RomCtl[1], RomCtl[0], t0);
ME_NAND3 p1 (RomCtl[3], RomCtl[2], RomCtl[0], t1);
ME_NAND2 b5 (t0, t1, StatusControl[5]);
ME_NAND3 p2 (RomCtl[3], RomCtl[2], RomCtl[1], t2);
ME_NAND3 p3 (RomCtl[3], notRomCtl2, notRomCtl0, t3);
ME_NAND2 b6 (t2, t3, StatusControl[6]);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)divlog.v 1.1 4/7/92
//
/* ############################################################
divlog.v 1.0 6th September 1989
DivLog Generation
############################################################ */
/* Divlog requires generation of DivMultiple From RemBits.
The RemBits are signed.
Pos Neg
Div Multiple 0 1 2 2 3 3 3 3 3 3 3 3 2 2 1 0 Divisor 1.1
0 1 2 3 3 3 3 3 3 3 3 3 3 2 1 0 Divisor 1.0
RemBits 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RemBits[3]
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RemBits[2]
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RemBits[1]
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RemBits[0]
Therfore
DivMultiple [3] 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
Divisor=1 [2] 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0
[1] 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0
DivMultiple [3] 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0
Divisor=0 [2] 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0
[1] 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Which can be expressed
DivMultiple [1] = ~RemBit[3].~RemBit[2].~RemBit[1].RemBit[0] +
RemBit[3].RemBit[2].RemBit[1].~RemBit[0];
DivMultiple [2] = ~RemBit[3].~RemBit[2].RemBit[1].~RemBit[0] +
~RemBit[3].~RemBit[2].RemBit[1].DivisorBit +
RemBit[3]. RemBit[2].~RemBit[1].RemBit[0] +
RemBit[3]. RemBit[2].~RemBit[1].DivisorBit;
DivMultiple [3] = ~RemBit[3]. RemBit[2] +
~RemBit[2]. RemBit[1]. RemBit[0].~DivisorBit +
RemBit[3].~RemBit[2] +
RemBit[2].~RemBit[1].~RemBit[0].~DivisorBit;
The Quotient selection is made based on the previous trial multiple and the sign of the result of the trial
The div multiple is recreated from the notDivMultiple[3:1] lines
Div Multiple -3 -2 -1 -0 0 1 2 3
Sign of trial result + - + - + - + - + - + - + - + -
Quotient bits generated 1 0 2 1 3 2 x 3 0 x 1 0 2 1 3 2
Which can be expressed
QuotientBit[1] = OldSign.DivMultiple[1].~DivMultiple[0].~NewSign +
OldSign.~DivMultiple[1] +
~OldSign.DivMultiple[1].DivMultiple[0] +
~OldSign.DivMultiple[1].~DivMultiple[0].~NewSign;
QuotientBit[0] = DivMultiple[0] XOR NewSign;
By multiplexing on the new sign
QuotientBit0[1] = OldSign.DivMultiple[1].~DivMultiple[0] +
OldSign.~DivMultiple[1] +
~OldSign.DivMultiple[1].DivMultiple[0] +
~OldSign.DivMultiple[1].~DivMultiple[0].~NewSign;
QuotientBit0[0] = DivMultiple[0];
QuotientBit1[1] = OldSign.~DivMultiple +
~OldSign.DivMultiple[1].DivMultiple[0];
QuotientBit[0] = ~DivMultiple[0];
*/
module DivLog (Phi,
AregFPMSBM1, // Divisor Bit
BregFPMSBM1, // On first step divisor is in B
StepRemBits, // RemBits used during step
InitialRemBits, // RemBits used on first step
SelectInitial, // Select First step
FracSign, // Sign of result after operation
DivMultiple, // Latched version of Divide Step Multiple
QuotientBits); // Quotient bits, valid on cycle after
// operation
// notFracSign); // inv FracSign -- generate inside fdp (dhn 03/27/91)
input Phi; // System Clock
input AregFPMSBM1, BregFPMSBM1, FracSign;
input [3:0] StepRemBits, InitialRemBits;
input SelectInitial;
output [3:1] DivMultiple;
output [1:0] QuotientBits;
// output notFracSign; // -- generate inside fdp (dhn 03/27/91)
// ME_INVA ifs (FracSign, notFracSign); // --generate inside fdp (dhn 03/27/91)
wire [3:1] notDivMultiple, DivMultipleU;
wire [3:0] notRemBits;
wire [3:0] RemBits;
ME_NMUX2B msld (SelectInitial, AregFPMSBM1, BregFPMSBM1, notDivisorBit);
ME_NMUX2B msl0 (SelectInitial, StepRemBits[0], InitialRemBits[0], notRemBits[0]);
ME_NMUX2B msl1 (SelectInitial, StepRemBits[1], InitialRemBits[1], notRemBits[1]);
ME_NMUX2B msl2 (SelectInitial, StepRemBits[2], InitialRemBits[2], notRemBits[2]);
ME_NMUX2B msl3 (SelectInitial, StepRemBits[3], InitialRemBits[3], notRemBits[3]);
ME_INV_B ir3 (notRemBits[3], RemBits[3]);
ME_INV_B ir2 (notRemBits[2], RemBits[2]);
ME_INV_B ir1 (notRemBits[1], RemBits[1]);
ME_INV_B ir0 (notRemBits[0], RemBits[0]);
ME_INV_B id0 (notDivisorBit, DivisorBit);
// DivMultiple [1] = ~RemBit[3].~RemBit[2].~RemBit[1].RemBit[0] +
// RemBit[3].RemBit[2].RemBit[1].~RemBit[0];
ME_NAND4 ds10 (notRemBits[3], notRemBits[2], notRemBits[1], RemBits[0], dm1t0);
ME_NAND4 ds11 (RemBits[3], RemBits[2], RemBits[1], notRemBits[0], dm1t1);
ME_NAND2 ds1m (dm1t1, dm1t0, DivMultipleU[1]);
// DivMultiple [2] = ~RemBit[3].~RemBit[2].RemBit[1].~RemBit[0] +
// ~RemBit[3].~RemBit[2].RemBit[1].DivisorBit +
// RemBit[3]. RemBit[2].~RemBit[1].RemBit[0] +
// RemBit[3]. RemBit[2].~RemBit[1].DivisorBit;
ME_NAND4 ds20 (notRemBits[3], notRemBits[2], RemBits[1], notRemBits[0], dm2t0);
ME_NAND4 ds21 (notRemBits[3], notRemBits[2], RemBits[1], DivisorBit, dm2t1);
ME_NAND4 ds22 (RemBits[3], RemBits[2], notRemBits[1], RemBits[0], dm2t2);
ME_NAND4 ds23 (RemBits[3], RemBits[2], notRemBits[1], DivisorBit, dm2t3);
ME_NAND4 ds2m (dm2t1, dm2t0, dm2t2, dm2t3, DivMultipleU[2]);
// DivMultiple [3] = ~RemBit[3]. RemBit[2] +
// ~RemBit[2]. RemBit[1]. RemBit[0].~DivisorBit +
// RemBit[3].~RemBit[2] +
// RemBit[2].~RemBit[1].~RemBit[0].~DivisorBit;
ME_NAND2 ds30 (notRemBits[3], RemBits[2], dm3t0);
ME_NAND4 ds31 (notRemBits[2], RemBits[1], RemBits[0], notDivisorBit, dm3t1);
ME_NAND2 ds32 (RemBits[3], notRemBits[2], dm3t2);
ME_NAND4 ds33 (RemBits[2], notRemBits[1], notRemBits[0], notDivisorBit, dm3t3);
ME_NAND4 ds3m (dm3t1, dm3t0, dm3t2, dm3t3, DivMultipleU[3]);
/* ************************************************
Latch next Div Multiple
************************************************ */
ME_FD1_B dv1 (Phi, DivMultipleU[1], DivMultiple[1], notDivMultiple[1]);
ME_FD1_B dv2 (Phi, DivMultipleU[2], DivMultiple[2], notDivMultiple[2]);
ME_FD1_B dv3 (Phi, DivMultipleU[3], DivMultiple[3], notDivMultiple[3]);
ME_FD1_B dv0 (Phi, notRemBits[3], notOldSign, OldSign);
/* ************************************************
Quotient bit generation
End of Result QuoBit Generation calculation
************************************************ */
/* Not time critical so use buffered DivMultiple */
/* Also use the encoded version of DivMultiple ie DivMultipleC */
wire [1:0] DivMultipleC, notDivMultipleC;
ME_NAND2 dedv0 (notDivMultiple[1], notDivMultiple[3], DivMultipleC[0]);
ME_NAND2 dedv1 (notDivMultiple[2], notDivMultiple[3], DivMultipleC[1]);
ME_INV_A dmb0 (DivMultipleC[0], notDivMultipleC[0]);
ME_INV_A dmb1 (DivMultipleC[1], notDivMultipleC[1]);
// QuotientBit0[1] = OldSign.DivMultiple[1].~DivMultiple[0] +
// OldSign.~DivMultiple[1] +
// ~OldSign.DivMultiple[1];
// QuotientBit1[1] = OldSign.~DivMultiple[1] +
// ~OldSign.DivMultiple[1].DivMultiple[0];
// QuotientBit0[0] = DivMultiple[0];
// QuotientBit1[0] = ~DivMultiple[0];
ME_NAND3 qb1t0 (OldSign, DivMultipleC[1], notDivMultipleC[0], t0);
ME_NAND2 qb1t1 (OldSign, notDivMultipleC[1], t1);
ME_NAND2 qb1t2 (notOldSign, DivMultipleC[1], t2);
ME_NAND3 qb1t3 (t0, t1, t2, t3);
ME_NAND3 qb1t4 (notOldSign, DivMultipleC[1], DivMultipleC[0], t4);
ME_NAND2 qb1t5 (t4, t1, t5);
ME_MUX2B qb1m (FracSign, t3, t5, QuotientBits[1]);
ME_NMUX2B qb0m (FracSign, notDivMultipleC[0], DivMultipleC[0], QuotientBits[0]);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)entrycheck.v 1.1 4/7/92
//
module EntryCheck (notRomMIptr, EntryPoint, s_mov);
input [7:0] notRomMIptr;
output EntryPoint, s_mov;
wire [7:0] RomMIptr;
ME_INV_B i_0 (notRomMIptr[0], RomMIptr[0]);
ME_INV_B i_1 (notRomMIptr[1], RomMIptr[1]);
ME_INV_B i_2 (notRomMIptr[2], RomMIptr[2]);
ME_INV_B i_3 (notRomMIptr[3], RomMIptr[3]);
ME_INV_B i_4 (notRomMIptr[4], RomMIptr[4]);
ME_INV_B i_5 (notRomMIptr[5], RomMIptr[5]);
ME_INV_B i_6 (notRomMIptr[6], RomMIptr[6]);
ME_INV_B i_7 (notRomMIptr[7], RomMIptr[7]);
ME_NOR3 g_1 (RomMIptr[7], RomMIptr[1], RomMIptr[0], s_0);
ME_NOR2 g_2 (RomMIptr[4], RomMIptr[3], s_1);
ME_NAND2 g_3 (RomMIptr[6], RomMIptr[2], s_2);
ME_NAND4 g_4 (RomMIptr[5], s_0, s_1, s_2, s_mov);
ME_XOR2 g_5 (RomMIptr[4], RomMIptr[5], s_3);
ME_NAND3 g_6 (RomMIptr[3], s_0, s_3, s_dyadic);
ME_NOR4 g_7 (RomMIptr[7], RomMIptr[3], RomMIptr[2], RomMIptr[1], s_4);
ME_AND2 g_8 (RomMIptr[6], RomMIptr[0], s_5);
ME_NAND3 g_9 (s_4, s_5, s_3, s_sqrt);
ME_NOR3 g_0 (RomMIptr[7], RomMIptr[6], RomMIptr[0], s_6);
ME_AND2 h_1 (RomMIptr[3], RomMIptr[1], s_7);
ME_NAND3 h_2 (s_6, s_7, s_3, s_cmp);
ME_NOR3 h_3 (RomMIptr[6], RomMIptr[5], RomMIptr[1], s_8);
ME_NAND2 h_4 (s_8, RomMIptr[2], s_9);
ME_NOR3 h_5 (RomMIptr[4], RomMIptr[2], RomMIptr[1], s_10);
ME_NAND2 h_6 (s_10, RomMIptr[6], s_11);
ME_NOR2 h_7 (RomMIptr[6], RomMIptr[2], s_12);
ME_NAND3 h_8 (s_12, s_3, RomMIptr[1], s_13);
ME_NAND3 h_9 (s_13, s_11, s_9, s_14);
//ME_INVA h_0 (RomMIptr[0], s_15);
ME_NAND4 j_1 (notRomMIptr[0], s_14, RomMIptr[3], RomMIptr[7], s_conv);
ME_AND4 j_2 (s_mov, s_dyadic, s_sqrt, s_cmp, s_16);
ME_NAND2 j_3 (s_conv, s_16, EntryPoint);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)exp_ctl.v 1.1 4/7/92
//
// Top-level interconnect module for the exponent datapath control modules.
//
// This interconnect module was produced by Synopsys grouping and then edited
// by hand to remove hierarchy from signal names and make
// things more readable.
module exp_ctl ( Phi, DBnotSN, FracAregMSB1, LoadOprs, notAbortWB, PreventSwap,
ShiftBy8, ShiftForAl, SNnotDB, notExpShiftResult, Rom_28_27,
Rom_38_33,
CarryIn, Constantb, Constantc, Constantd, Constante,
Constantf, Constantg, Constanth, ExpAregLoadEn, ExpAregLC0,
ExpAregLC1, ExpBregLC0, ExpBregLC1, ExpBregLoadEn,
notSignAFromB, notSignBFromA, notWaitForShifter, SROneMore,
SRToSticky, SRControl );
input Phi, DBnotSN, FracAregMSB1, LoadOprs, notAbortWB, PreventSwap,
ShiftBy8, ShiftForAl, SNnotDB ;
input [12:0] notExpShiftResult ;
input [28:27] Rom_28_27 ;
input [38:33] Rom_38_33 ;
output CarryIn, Constantb, Constantc, Constantd, Constante, Constantf,
Constantg, Constanth, ExpAregLoadEn, ExpAregLC0, ExpAregLC1,
ExpBregLC0, ExpBregLC1, ExpBregLoadEn, notSignAFromB, notSignBFromA,
notWaitForShifter, SROneMore, SRToSticky ;
output [3:0] SRControl ;
ExpAdderLSB alsb ( .CinFromRound(Rom_28_27[28] ), .Sub(Rom_28_27[27] ),
.FracAregMSB1(FracAregMSB1), .CarryIn(CarryIn) );
ExpConstantCtl ecs ( .SNnotDB(SNnotDB), .DBnotSN(DBnotSN), .RomExpConCtl(
Rom_38_33[34:33] ), .Constantb(Constantb), .Constantc(Constantc),
.Constantd(Constantd), .Constante(Constante), .Constantf(Constantf),
.Constantg(Constantg), .Constanth(Constanth) );
ExpRegLoadCtl alc ( .RomExpBregLC( Rom_38_33[36:35] ), .LoadOprs(LoadOprs),
.notAbortWB(notAbortWB), .PreventSwap(PreventSwap),
.notSignBFromA(notSignAFromB), .ExpBregLC0(ExpAregLC0),
.ExpBregLC1(ExpAregLC1), .ExpBregLoadEn(ExpAregLoadEn) );
ExpRegLoadCtl blc ( .RomExpBregLC(Rom_38_33[38:37]), .LoadOprs(LoadOprs),
.notAbortWB(notAbortWB), .PreventSwap(PreventSwap), .notSignBFromA(
notSignBFromA), .ExpBregLC0(ExpBregLC0), .ExpBregLC1(ExpBregLC1),
.ExpBregLoadEn(ExpBregLoadEn) );
ExpShifter sr ( .Phi(Phi), .notExpResult(notExpShiftResult), .Rom_ShBy8(
ShiftBy8), .Rom_ShiftForAl(ShiftForAl), .SRControl(SRControl),
.SROneMore(SROneMore), .SRToSticky(SRToSticky), .notWaitForShifter(
notWaitForShifter) );
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)expadderlsb.v 1.1 4/7/92
//
module ExpAdderLSB (CinFromRound, Sub, FracAregMSB1,
CarryIn);
input CinFromRound, // rom control to set carry from Areg MSB
Sub, // rom control Subtract not add
FracAregMSB1;
output CarryIn;
/* Notes
// always subtracting when notCarrryInfromNorm is used
// always adding when CinFrom Round is used
// Carry is equivalent to notBorrow for this adder.*/
ME_MUX2B g12 ( CinFromRound, Sub, FracAregMSB1,
CarryIn);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)expconstantctl.v 1.1 4/7/92
//
module ExpConstantCtl (SNnotDB, DBnotSN,
RomExpConCtl,
Constantb, Constantc, Constantd, Constante,
Constantf, Constantg, Constanth);
input SNnotDB, DBnotSN ;
input [`end_constant_field:`start_constant_field] RomExpConCtl;
output Constantb, Constantc, Constantd, Constante,
Constantf, Constantg, Constanth;
/* ************************************************************
Length Dependant Constant Selection
************************************************************
a b c d e f g h ROMbit f1 f0 SNnotBD
DivLoopSN 0|00 00|0 00 0 | 0 1 1 0 0 1 1
DivLoopDB 0|00 00|0 00 0 | 1 1 0 1 0 1 0
BiasSN 0|00 00|0 11 1 | 1 1 1 1 1 1 1
BiasDB 0|00 11|1 11 1 | 1 1 1 1 1 1 0
1 0|00 00|0 00 0 | 0 0 0 1 0 0 ?
IntToReal 0|00 00|0 00 1 | 1 1 1 1 1 0 ?
Constantb = Func1 & Func0 & DB;
Constantc = Func1 & Func0;
Constantd = Func1;
Constante = Func1 | (Func0 & DBnotSN);
Constantf = Func1 | Func0;
Constantg = Func1 | ~Constanth;
Constanth = ~(~Func1 & Func0 & SNnotDB); */
//ME_INVA z90 (SNnotDB, DBnotSN );
ME_AND3_B z00 (RomExpConCtl[`u_ConstantFromFunc1],
RomExpConCtl[`u_ConstantFromFunc0],
DBnotSN, Constantb);
ME_AND2_B z01 (RomExpConCtl[`u_ConstantFromFunc1],
RomExpConCtl[`u_ConstantFromFunc0],
Constantc);
ME_AND2_B z02 (RomExpConCtl[`u_ConstantFromFunc0], DBnotSN, Func0andDB);
ME_OR2_B z03 (RomExpConCtl[`u_ConstantFromFunc1], Func0andDB, Constante);
ME_OR2_B z04 (RomExpConCtl[`u_ConstantFromFunc1],
RomExpConCtl[`u_ConstantFromFunc0],
Constantf);
ME_INVA z05 (RomExpConCtl[`u_ConstantFromFunc1], notFunc1);
ME_NAND2_B z07 (notFunc1, Constanth, Constantg);
ME_NAND3_B z06 (notFunc1, RomExpConCtl[`u_ConstantFromFunc0], SNnotDB, Constanth);
//wire Constantd = RomExpConCtl[`u_ConstantFromFunc1];
con1 ep (RomExpConCtl[`u_ConstantFromFunc1], Constantd);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)expregloadctl.v 1.1 4/7/92
//
module ExpRegLoadCtl (RomExpBregLC,
LoadOprs,
notAbortWB,
PreventSwap,
notSignBFromA,
ExpBregLC0,
ExpBregLC1,
ExpBregLoadEn);
input [`u_ExpBregFromFunc1:`u_ExpBregFromFunc0] RomExpBregLC;
input notAbortWB,
PreventSwap,
LoadOprs;
output notSignBFromA;
output ExpBregLC0,
ExpBregLC1,
ExpBregLoadEn;
ME_TIEOFF toff (vdd, );
ME_INVA iopl (LoadOprs, notLoadOprs);
ME_AND2 alcn1 (RomExpBregLC[`u_ExpBregFromFunc1], notLoadOprs, ExpBregLC1);
ME_AND2 alcn2 (RomExpBregLC[`u_ExpBregFromFunc0], notLoadOprs, ExpBregLC0);
ME_OR3 alcne (RomExpBregLC[`u_ExpBregFromFunc0],
RomExpBregLC[`u_ExpBregFromFunc1],
LoadOprs,
LoadEn);
ME_NAND2 alc4 (RomExpBregLC[`u_ExpBregFromFunc0],
RomExpBregLC[`u_ExpBregFromFunc1],
notSignBFromA);
//ME_AND3 en (LoadEn, notAbortWB, notPreventSwap, ExpBregLoadEn);
ME_NAND2 en0 (LoadEn, notAbortWB, notExpBregLoadEn_p);
ME_NMUX2B en1 (notExpBregLoadEn_p, PreventSwap, vdd, ExpBregLoadEn);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)expshifter.v 1.1 4/7/92
//
module ShiftDec ( Phi, FS, notFS, Res,
notShiftCount1 );
input Phi, FS, notFS;
input[1:0] Res;
output notShiftCount1 ;
// shift count decrementer.
// Load counter from Res on FS
// decrement works either loading or counting
wire [1:0] notSC, ShCnt, notShCnt ;
ME_NMUX2BA mu1 (FS, notFS, Res[1], ShCnt[0], notSC[1]);
ME_NMUX2BA mu0 (FS, notFS, Res[0], notShCnt[0], notSC[0]);
ME_FD1 ma1 (Phi, notSC[1], notShCnt[1], ShCnt[1]);
ME_FD1 ma0 (Phi, notSC[0], notShCnt[0], ShCnt[0]);
ME_NAND3 g20 (notFS, notShCnt[1], ShCnt[0], notShiftCount1 );
endmodule
/* ******** main module ******************** */
module ExpShifter ( Phi,
notExpResult,
Rom_ShBy8,
Rom_ShiftForAl,
SRControl,
SROneMore,
SRToSticky,
notWaitForShifter);
input Phi; // master clock
input [12:0] notExpResult; // fraction add result only use 5:0
input Rom_ShBy8, // for either int or mul
Rom_ShiftForAl; // alignment
output [3:0] SRControl; // Shift right size ( 0 to 15 )
// Delay for this is
// MUX2B
output SROneMore, // extra one to give shift of 16
SRToSticky; // Massive shift reduce to sticky
output notWaitForShifter; // Need to generate this quickly
// delay is NOR4, NAND3, AND4
// Dont care unless ShiftforAl asserted
ME_TIEOFF toff (,gnd);
// generate correct shift right value. This may be either forced to 8
// for mul or INT stuff, or 0 to 16 for first step of align, or
// further shifts by 16 if required
// Generate wait if additional shift is required
// Note shift by 16 is a delayed shift wait except on first shift
// SRToSticky Being asserted means the rest of the shifter doesnt
// matter. Note since in the shifter the sticky is set to one this
// must NOT be applied to zero fraction parts.
// Wait is only valid while Rom_ShiftforAl is asserted
ME_NAND3 g12 ( notExpResult[5], notExpResult[4], FS, notSmallShift );
ME_NAND6_B gxz ( notExpResult[11], notExpResult[10], notExpResult[9], notExpResult[8], notExpResult[7], notExpResult[6], BigShift);
ME_NMUX2B_B sm4 ( FS, gnd, BigShift, notSRToSticky);
ME_INV_B g19 ( notSRToSticky, SRToSticky );
// Can align in 1 for BigShift or small shift 00xxxx or exact 010000
ME_AND2 gr5 ( notSmallShift, notShiftCount1, bozoid );
ME_NAND2 g15 ( notSRToSticky, bozoid, notWaitForShifter );
// note shift by 8 is dominant so dont worry about FS on shift by 8
ME_FD1 err ( Phi, Rom_ShiftForAl, , notPrevShift);
ME_NAND2 g32 ( Rom_ShiftForAl, notPrevShift, notFS );
ME_INVA g33 ( notFS, FS );
wire [5:4] ExpResult;
// Decrement on notFS, OR ShBy16first
ME_INV_A g16 ( notExpResult[5], ExpResult[5] );
ME_INV_A g17 ( notExpResult[4], ExpResult[4] );
ShiftDec d ( Phi, FS, notFS, ExpResult[5:4], notShiftCount1 );
// Set correct shift value
ME_NOR2 sby8 (Rom_ShBy8, Rom_ShiftForAl, notShiftBy8);
ME_INV_A sbfa (Rom_ShiftForAl, notRom_ShiftForAl);
ME_NMUX2B_B sm3 (FS, notShiftBy8, notExpResult[3], SRControl[3]);
ME_NMUX2B_B sm2 (FS, notRom_ShiftForAl, notExpResult[2], SRControl[2]);
ME_NMUX2B_B sm1 (FS, notRom_ShiftForAl, notExpResult[1], SRControl[1]);
ME_NMUX2B_B sm0 (FS, notRom_ShiftForAl, notExpResult[0], SRControl[0]);
ME_AND2_B a90 (Rom_ShiftForAl, notFS, SROneMore);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)fp_ctl.v 1.1 4/7/92
//
// FPU core control top-level interconnect module.
//
// This interconnect module was produced by Synopsys grouping and then edited
// by hand to remove hierarchy from signal names and make
// things more readable.
module fp_ctl ( ss_clock, AregMaster_32, BregFPMSBM1, CALSB, CBLSB, CCLSB,
Conditionals_3, Conditionals_10, Conditionals_12,
FpLd, FpOp, FracAgtB, FracBregSign, FracZero,
notAInfNAN, notAM31_3, notAM2_0, notAregMasterFPMSBP1, notAZeroDenorm,
notBInfNAN, notBZeroDenorm, notExpUnderflow, notExpOverflow,
notExpException, notPossibleOv, notFracZero, notSticky1, ResetIn,
RS2_63, RS1_63, StickyForSR1, SubResultNorm, AregMaster_57_40,
AregMaster_7_0, CarryInLSBs, CregInSL2SQRT, CregSNBits, ExpIn,
FpInst, notExpShiftResult, notMultip, notSticky4, RoundingMode,
SALSBs, SBLSBs, SCLSBs, StepRemBits, Sticky2, StickyExtra, SumInLSBs,
TregLSBs, U_RomOutputs,
CarryIn, CarryOut0, CarryOut3, Constantb, Constantc, Constantd,
Constante, Constantf, Constantg, Constanth, ExpAregLC0, ExpAregLC1,
ExpAregLoadEn, ExpBregLC0, ExpBregLC1, ExpBregLoadEn, FracAregLoadEn,
FracBregLoadEn, FracCregLC, FracCregLoadEn, FracTregLoadEn, FpBusy,
InitialCarryBit, InitialMulStep, notFracYFromD1A, notFracYFromD2A,
notFracYFromD3A, notNO_1, notStickyInForSR, OprSNnotDB, RomOutputs_18,
RomOutputs_20, RomOutputs_27, RomOutputs_55, SignResult, SNnotDB,
SROneMore, SRToSticky, SumCarryLoadEn, SumOut0, ConditionCodes, Excep,
FracAregLC, FracBregLC, FracRound, FracYbusLSBs, InForCreg,
InForCregDB, InFromCregOr0, LIB, MulLenSel, notsh, Pos,
RomOutputs_32_29, RomOutputs_46_44, SelectedMIptr, Shift, SRControl,
TopBitsIn, Zero,
ss_scan_mode, fp_ctl_scan_in, fp_ctl_scan_out);
input ss_clock, AregMaster_32, BregFPMSBM1, CALSB, CBLSB, CCLSB,
Conditionals_3, Conditionals_10, Conditionals_12,
FpLd, FpOp, FracAgtB, FracBregSign, FracZero,
notAInfNAN, notAM31_3, notAM2_0, notAregMasterFPMSBP1, notAZeroDenorm,
notBInfNAN, notBZeroDenorm, notExpUnderflow, notExpOverflow,
notExpException, notPossibleOv, notFracZero, notSticky1, ResetIn,
RS2_63, RS1_63, StickyForSR1, SubResultNorm,
ss_scan_mode, fp_ctl_scan_in ;
input [57:40] AregMaster_57_40 ;
input [7:0] AregMaster_7_0 ;
input [2:0] CarryInLSBs ;
input [1:0] CregInSL2SQRT ;
input [1:0] CregSNBits ;
input [7:0] ExpIn ;
input [9:0] FpInst ;
input [12:0] notExpShiftResult ;
input [8:0] notMultip ;
input [3:0] notSticky4 ;
input [1:0] RoundingMode ;
input [1:0] SALSBs ;
input [1:0] SBLSBs ;
input [1:0] SCLSBs ;
input [3:0] StepRemBits ;
input [1:0] Sticky2 ;
input [1:0] StickyExtra ;
input [2:0] SumInLSBs ;
input [1:0] TregLSBs ;
input [63:0] U_RomOutputs ; // unbuffered ROM data output
output CarryIn, CarryOut0, CarryOut3, Constantb, Constantc, Constantd,
Constante, Constantf, Constantg, Constanth, ExpAregLC0, ExpAregLC1,
ExpAregLoadEn, ExpBregLC0, ExpBregLC1, ExpBregLoadEn, FracAregLoadEn,
FracBregLoadEn, FracCregLC, FracCregLoadEn, FracTregLoadEn, FpBusy,
InitialCarryBit, InitialMulStep, notFracYFromD1A, notFracYFromD2A,
notFracYFromD3A, notNO_1, notStickyInForSR, OprSNnotDB, RomOutputs_18,
RomOutputs_20, RomOutputs_27, RomOutputs_55, SignResult, SNnotDB,
SROneMore, SRToSticky, SumCarryLoadEn, SumOut0,
fp_ctl_scan_out ;
output [1:0] ConditionCodes;
output [5:0] Excep ;
output [2:0] FracAregLC ;
output [2:0] FracBregLC ;
output [4:0] FracRound ;
output [1:0] FracYbusLSBs ;
output [1:0] InForCreg ;
output [1:0] InForCregDB ;
output [1:0] InFromCregOr0 ;
output [2:0] LIB ;
output [4:0] MulLenSel ;
output [3:1] notsh ;
output [3:0] Pos ;
output [32:29] RomOutputs_32_29 ;
output [46:44] RomOutputs_46_44 ;
output [7:0] SelectedMIptr ; // unregistered ROM address
output [3:0] Shift ;
output [3:0] SRControl ;
output [8:0] TopBitsIn ;
output [3:0] Zero ;
wire notWaitForShifter, SignAreg, PreventSwap, PreventSwapExp, XDest,
CMPDecoded, CMPEDecoded, notAbortWB, NegateOprSign, Unimplemented,
Status_6, notSignAFromB, notSignBFromA, DBnotSN,
Conditionals_2, Conditionals_6, Conditionals_7, Conditionals_15 ;
wire [6:0] YDest ;
wire [1:0] notNO ;
wire [63:0] RomOutputs ;
assign notNO_1 = notNO[1] ;
assign RomOutputs_18 = RomOutputs[18] ;
assign RomOutputs_20 = RomOutputs[20] ;
assign RomOutputs_27 = RomOutputs[27] ;
assign RomOutputs_55 = RomOutputs[55] ;
assign RomOutputs_32_29 = RomOutputs[32:29] ;
assign RomOutputs_46_44 = RomOutputs[46:44] ;
ME_TIEOFF toff (vdd, gnd);
Control cl ( .Phi (ss_clock ), .ResetIn (ResetIn ),
.notExpAgtB (notExpShiftResult[12] ),
.notAInfNan (notAInfNAN ), .notAZeroDenorm (notAZeroDenorm ),
.notBInfNan (notBInfNAN ), .notBZeroDenorm (notBZeroDenorm ),
.notExpUnderflow (notExpUnderflow ), .notExpOverflow (notExpOverflow ),
.notExpException (notExpException ),
.notWaitForShifter (notWaitForShifter ), .notNO (notNO ),
.SubResultNorm (SubResultNorm ), .notPossibleOv (notPossibleOv ),
.Conditionals_14_8 ({vdd, AregMaster_57_40[54], Conditionals_12,
FracAgtB, Conditionals_10, FracZero, notFracZero }),
.Conditionals_6_0 ( {Conditionals_6, SignAreg, ExpIn[0],
Conditionals_3, Conditionals_2 , SNnotDB, gnd} ),
.FpInst (FpInst ), .FpOp (FpOp ), .FpLd (FpLd ),
.PreventSwap (PreventSwap ), .PreventSwapExp (PreventSwapExp ),
.RCondition (Conditionals_15 ),
.SelectedMIptr (SelectedMIptr ),
.U_RomOutputs (U_RomOutputs ),
.RomOutputs (RomOutputs[63:0] ),
.YDest (YDest[6:0] ), .XDest (XDest ), .CMPDecoded (CMPDecoded ),
.CMPEDecoded (CMPEDecoded ), .AregOprExc (Conditionals_7 ),
.notAbortWB (notAbortWB ),
.Reset (Reset ), .Busy (FpBusy ), .NegateOprSign (NegateOprSign ),
.UnimpOut (Unimplemented ) );
frac_ctl fracctl ( .Phi(ss_clock), .AregMaster_32 (AregMaster_32 ),
.BregFPMSBM1 (BregFPMSBM1 ), .CALSB (CALSB), .CBLSB (CBLSB ),
.CCLSB (CCLSB ), .FracBregSign (FracBregSign ), .FracSign (FracAgtB ),
.LoadForInt (RomOutputs[19] ), .LoadOprs (FpLd ),
.notAbortWB (notAbortWB ), .notAM31_3 (notAM31_3 ),
.notAM2_0 (notAM2_0), .notAregMasterFPMSBP1 (notAregMasterFPMSBP1 ),
.notSticky1 (notSticky1), .PreventSwap (PreventSwap ),
.Rom_Inexact (Status_6 ), .RomShForAlign (RomOutputs[21] ),
.SNnotDB(SNnotDB), .SROneMore (SROneMore), .SRToSticky (SRToSticky ),
.StickyForSR1 (StickyForSR1),
.AregMaster_57_40 ( AregMaster_57_40[57:40] ),
.AregMaster_7_0 (AregMaster_7_0[7:0] ),
.CarryInLSBs (CarryInLSBs ), .CregInSL2SQRT ( CregInSL2SQRT ),
.CregSNBits (CregSNBits ), .ExpIn ({SignAreg, ExpIn}),
.notMultip (notMultip ), .notSticky4 (notSticky4 ),
.Rom_63_48 (RomOutputs[63:48] ), .SALSBs (SALSBs ), .SBLSBs (SBLSBs ),
.SCLSBs (SCLSBs ), .SRControl (SRControl ), .StepRemBits (StepRemBits),
.Sticky2 (Sticky2 ), .StickyExtra (StickyExtra ),
.SumInLSBs (SumInLSBs ), .TregLSBs (TregLSBs ), .YDest (YDest[6:0] ),
.CarryOut0 (CarryOut0 ), .CarryOut3 (CarryOut3 ),
.FracAregLoadEn (FracAregLoadEn ), .FracBregLoadEn (FracBregLoadEn ),
.FracCregLoadEn (FracCregLoadEn ), .FracCregLC (FracCregLC ),
.FracTregLoadEn (FracTregLoadEn ), .Inexact (Excep[0] ),
.InitialCarryBit (InitialCarryBit ), .InitialMulStep (InitialMulStep ),
.notFracYFromD1A (notFracYFromD1A ),
.notFracYFromD2A (notFracYFromD2A ),
.notFracYFromD3A (notFracYFromD3A ),
.notStickyInForSR (notStickyInForSR ),
.SumCarryLoadEn (SumCarryLoadEn ), .SumOut0 (SumOut0 ),
.FracAregLC (FracAregLC ), .FracBregLC (FracBregLC ),
.FracYbusLSBs (FracYbusLSBs ), .InForCreg (InForCreg ),
.InForCregDB (InForCregDB ), .InFromCregOr0 (InFromCregOr0 ),
.LIB ( LIB ), .notNO (notNO ), .notsh (notsh ), .Pos (Pos ),
.Shift (Shift ), .TopBitsIn (TopBitsIn ), .Zero (Zero ) );
SignDp sdp ( .Phi (ss_clock ), .Reset (Reset ),
.RomSignLength ( RomOutputs[43:39] ),
.RomStatus ( RomOutputs[26:22] ), .FracXFromRound (RomOutputs[47] ),
.XDest (XDest ), .CMPDecoded (CMPDecoded ),
.CMPEDecoded (CMPEDecoded ), .SignOpA (RS2_63 ), .SignOpB (RS1_63 ),
.notAbortWB (notAbortWB ), .PreventSwap (PreventSwap ), .FpLd (FpLd ),
.FpOp (FpOp ), .NegateOprSign (NegateOprSign ),
.notSignAFromB (notSignAFromB ), .notSignBFromA (notSignBFromA ),
.OprRoundMode (RoundingMode ), .FpInst1 ( FpInst[1] ),
.Unimplemented (Unimplemented ), .SignResult (SignResult ),
.AregSign (SignAreg ), .AregXORBreg (Conditionals_2 ),
.FpExc_Unimp (Excep[5] ), .Status_6_2 ({Status_6 , Excep[4:1] }),
.ConditionCodes (ConditionCodes ), .OprSNnotDB (OprSNnotDB ),
.SNnotDB (SNnotDB ), .DBnotSN (DBnotSN ), .MulLenSel (MulLenSel ),
.RModeMinus (Conditionals_6 ), .FracRoundOut (FracRound ) );
exp_ctl expctl ( .Phi (ss_clock), .DBnotSN (DBnotSN),
.FracAregMSB1 (AregMaster_57_40[56] ), .LoadOprs (FpLd),
.notAbortWB (notAbortWB ), .PreventSwap (PreventSwapExp ),
.ShiftBy8 (RomOutputs[20] ), .ShiftForAl (RomOutputs[21] ),
.SNnotDB (SNnotDB ), .notExpShiftResult (notExpShiftResult ),
.Rom_28_27 (RomOutputs[28:27] ), .Rom_38_33 (RomOutputs[38:33] ),
.CarryIn (CarryIn ), .Constantb (Constantb ), .Constantc (Constantc ),
.Constantd (Constantd ), .Constante (Constante ),
.Constantf (Constantf ), .Constantg (Constantg ),
.Constanth (Constanth ), .ExpAregLoadEn (ExpAregLoadEn ),
.ExpAregLC0 (ExpAregLC0 ), .ExpAregLC1 (ExpAregLC1 ),
.ExpBregLC0 (ExpBregLC0 ), .ExpBregLC1 (ExpBregLC1 ),
.ExpBregLoadEn (ExpBregLoadEn ), .notSignAFromB (notSignAFromB ),
.notSignBFromA (notSignBFromA ),
.notWaitForShifter (notWaitForShifter ), .SROneMore (SROneMore ),
.SRToSticky (SRToSticky ), .SRControl (SRControl) );
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)fpuromhdr.v 1.1 4/7/92
//
// original place of define list at the beginning LA 28.02.02
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)frac_ctl.v 1.1 4/7/92
//
// Top-level interconnect module for the fraction datapath control modules.
//
// This interconnect module was produced by Synopsys grouping and then edited
// by hand to remove hierarchy from signal names and make
// things more readable..
module frac_ctl ( Phi, AregMaster_32, BregFPMSBM1, CALSB, CBLSB, CCLSB,
FracBregSign, FracSign, LoadForInt, LoadOprs, notAbortWB,
notAM31_3, notAM2_0, notAregMasterFPMSBP1, notSticky1,
PreventSwap, Rom_Inexact, RomShForAlign, SNnotDB, SROneMore,
SRToSticky, StickyForSR1, AregMaster_57_40,
AregMaster_7_0,
CarryInLSBs, CregInSL2SQRT, CregSNBits, ExpIn, notMultip, notSticky4,
Rom_63_48, SALSBs, SBLSBs, SCLSBs, SRControl, StepRemBits, Sticky2,
StickyExtra, SumInLSBs, TregLSBs, YDest,
CarryOut0, CarryOut3, FracAregLoadEn, FracBregLoadEn,
FracCregLoadEn, FracCregLC, FracTregLoadEn, Inexact,
InitialCarryBit, InitialMulStep, notFracYFromD1A,
notFracYFromD2A, notFracYFromD3A, notStickyInForSR,
SumCarryLoadEn, SumOut0, FracAregLC, FracBregLC, FracYbusLSBs,
InForCreg, InForCregDB, InFromCregOr0, LIB, notNO, notsh, Pos, Shift,
TopBitsIn, Zero );
input Phi, AregMaster_32, BregFPMSBM1, CALSB, CBLSB, CCLSB,
FracBregSign, FracSign, LoadForInt, LoadOprs, notAbortWB,
notAM31_3, notAM2_0, notAregMasterFPMSBP1, notSticky1,
PreventSwap, Rom_Inexact, RomShForAlign, SNnotDB, SROneMore,
SRToSticky, StickyForSR1 ;
input [57:40] AregMaster_57_40 ;
input [7:0] AregMaster_7_0 ;
input [2:0] CarryInLSBs ;
input [1:0] CregInSL2SQRT ;
input [1:0] CregSNBits ;
input [8:0] ExpIn ;
input [8:0] notMultip ;
input [3:0] notSticky4 ;
input [63:48] Rom_63_48 ;
input [1:0] SALSBs ;
input [1:0] SBLSBs ;
input [1:0] SCLSBs ;
input [3:0] SRControl ;
input [3:0] StepRemBits ;
input [1:0] Sticky2 ;
input [1:0] StickyExtra ;
input [2:0] SumInLSBs ;
input [1:0] TregLSBs ;
input [6:0] YDest ;
output CarryOut0, CarryOut3, FracAregLoadEn, FracBregLoadEn,
FracCregLoadEn, FracCregLC, FracTregLoadEn, Inexact,
InitialCarryBit, InitialMulStep, notFracYFromD1A,
notFracYFromD2A, notFracYFromD3A, notStickyInForSR,
SumCarryLoadEn, SumOut0 ;
output [2:0] FracAregLC ;
output [2:0] FracBregLC ;
output [1:0] FracYbusLSBs ;
output [1:0] InForCreg ;
output [1:0] InForCregDB ;
output [1:0] InFromCregOr0 ;
output [2:0] LIB ;
output [1:0] notNO ;
output [3:1] notsh ;
output [3:0] Pos ;
output [3:0] Shift ;
output [8:0] TopBitsIn ;
output [3:0] Zero ;
wire LoadFromMult, RomFracBSL2FromC, SelInitRemBits ;
wire [3:1] DivMultiple ;
wire [1:0] QuoBits ;
BregLoadCtl fblc ( .RomFracBregLC( Rom_63_48[60:59] ), .RomBSL2InFromC(
RomFracBSL2FromC), .LoadOprs(LoadOprs), .notAbortWB(notAbortWB),
.PreventSwap(PreventSwap), .LoadFromMult(LoadFromMult), .CregInSL2SQRT(
CregInSL2SQRT[1:0] ), .FracBregLC( FracBregLC[2:0] ), .FracBregLoadEn(
FracBregLoadEn), .InFromCregOr0( InFromCregOr0[1:0] ) );
ShiftLeftCtl slc ( .NI_49_47( AregMaster_57_40[49:47] ), .LoadForInt(
LoadForInt), .LIB( LIB[2:0] ) );
AregLoadCtl falc ( .ROM( Rom_63_48[58:56] ), .LoadOprs(LoadOprs),
.notAbortWB(notAbortWB), .PreventSwap(PreventSwap), .FracAregLC(
FracAregLC[2:0] ), .FracAregLoadEn(FracAregLoadEn), .LoadFromMult(
LoadFromMult), .SelInitRemBits(SelInitRemBits) );
TregLoadCtl tlc ( .RomFracTFromRes(Rom_63_48[63] ),
.notAbortWB(notAbortWB), .FracTregLoadEn(FracTregLoadEn) );
NormCalSlice an ( .NI( AregMaster_57_40[55:40] ), .notsh( notsh[3:1] ),
.notNO( notNO[1:0] ) );
AregInexact aic ( .RomInexactRound(Rom_Inexact), .SNnotDB(SNnotDB),
.AMCBit(AregMaster_57_40[56] ), .AM32(AregMaster_32), .AM3(
AregMaster_7_0[3] ), .notAM31_3(notAM31_3), .notAM2_0(notAM2_0),
.Inexact(Inexact) );
MultiplierLSB mlsb ( .Rom_ResetMul(Rom_63_48[63] ), .notMultip(
notMultip[8:0] ), .notAbortWB(notAbortWB), .SumInLSBs(SumInLSBs[2:0] ),
.CarryInLSBs( CarryInLSBs[2:0] ), .SCLSBs( SCLSBs[1:0] ), .SBLSBs(
SBLSBs[1:0] ), .SALSBs( SALSBs[1:0] ), .CCLSB(CCLSB), .CBLSB(CBLSB),
.CALSB(CALSB), .Shift( Shift[3:0] ), .Pos( Pos[3:0] ), .Zero(
Zero[3:0] ), .CarryOut0(CarryOut0), .CarryOut3(CarryOut3), .SumOut0(
SumOut0), .SumCarryLoadEn(SumCarryLoadEn), .InitialMulStep(
InitialMulStep), .InitialCarryBit(InitialCarryBit) );
DivLog divl ( .Phi(Phi), .AregFPMSBM1(AregMaster_57_40[54] ),
.BregFPMSBM1(BregFPMSBM1), .StepRemBits( StepRemBits[3:0] ),
.InitialRemBits( AregMaster_57_40[57:54] ), .SelectInitial(
SelInitRemBits), .FracSign(FracSign), .DivMultiple( DivMultiple[3:1] ),
.QuotientBits( QuoBits[1:0] ) );
CregLoadCtl fclc ( .RomCregCtl(Rom_63_48[62:61] ), .QuoBits(QuoBits[1:0] ),
.notAbortWB(notAbortWB), .SNnotDB(SNnotDB), .CregSNBits(
CregSNBits[1:0] ), .InForCreg( InForCreg[1:0] ), .InForCregDB(
InForCregDB[1:0] ), .RomFracBSL2FromC(RomFracBSL2FromC),
.FracCregLoadCtl0(FracCregLC), .FracCregLoadEn(FracCregLoadEn) );
ShiftRightCtl src ( .LoadForInt(LoadForInt), .AregMasterBuf_57_55(
AregMaster_57_40[57:55] ), .ExpIn( ExpIn[8:0] ), .SRControl(
SRControl[3:0] ), .SROneMore(SROneMore), .SRToStky(SRToSticky),
.Stky8( AregMaster_7_0[7:0] ), .notStky4( notSticky4[3:0] ),
.Stky2( Sticky2[1:0] ), .notStky1(notSticky1), .StkyExtra(
StickyExtra[1:0] ), .RomShForAl(RomShForAlign), .notStkyInForSR(
notStickyInForSR), .TopBitsIn( TopBitsIn[8:0] ) );
YMuxCtl fymc ( .RomYMuxCtl( Rom_63_48[55:48] ), .YFunc( YDest[6:0] ),
.FracAregFPMSBP1( AregMaster_57_40[56] ), .notFracAregFPMSBP1(
notAregMasterFPMSBP1), .FracBregSign(FracBregSign), .DivMultiple(
DivMultiple[3:1] ), .AregLSBs( AregMaster_7_0[2:0] ),
.StickyForSR1(StickyForSR1), .TregLSBs( TregLSBs[1:0] ),
.notFracYFromD1A(notFracYFromD1A), .notFracYFromD2A(notFracYFromD2A),
.notFracYFromD3A(notFracYFromD3A), .FracYLSBs( FracYbusLSBs[1:0] ) );
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)implementedcheck.v 1.1 4/7/92
//
module ImplementedCheck (Phi,
// input
ResetImp,
notReset,
FpOp,
EntryPoint,
FpInst, // sparc FP inst field
// outputs
notDecodedUnImp,
notUnimpOrReset,
notAbortInst, ResetAbortInst,
FPOP2Map,
UnImpOut);
input Phi,
ResetImp, // Reset beore modification
notReset, // Reset After modification
FpOp,
EntryPoint;
input [9:4] FpInst;
output notDecodedUnImp; // Go busy quickly
output notUnimpOrReset,
notAbortInst, // Aborting so remain busy for two extra cycles
ResetAbortInst,
FPOP2Map,
UnImpOut;
// ***************************************//
// Imp Check //
// ***************************************//
ME_NAND2 idg0 (FpInst[4], FpInst[6], notFpInst4and6);
ME_OR2 idg1 (FpInst[7], notFpInst4and6, notFPOP2Map);
ME_INV_B idg2 (notFPOP2Map, FPOP2Map);
ME_XOR2 idg3 (FpInst[9], FPOP2Map, notEntryMap);
ME_OR2 idg4 (notEntryMap, FpInst[8], UnImpMap);
ME_INV_A rrr7 (notReset, Reset);
ME_OR2 ggh3 (FpOp, Reset, UnImpMapEn);
ME_FD1E ggh1 (Phi, UnImpMapEn, UnImpMap, , ImpMap);
ME_FD1 rrr6 (Phi, FpOp, FpOpHeld, notFpOpHeld);
ME_INVA ggh2 (ResetImp, notResetImp);
ME_NAND3 ggh4 (ImpMap, EntryPoint, notReset, notImpStart);
ME_NAND3 ddfd (notImpStart, notResetImp, FpOpHeld, notDecodedUnImp);
ME_NAND2 g_1 (notFpOpHeld, notReset, FpOpHeldOrReset);
ME_NAND2_B g_3 (FpOpHeldOrReset, notImpStart, notUnimpOrReset);
ME_OR2 icor (FpOpHeld, ResetImp, NewInsOrReset);
ME_FD1E ni (Phi, NewInsOrReset, notDecodedUnImp, , UnImpOut );
// ***************************************//
// Kill UnImp Inst //
// ***************************************//
// KillUnImp is used to abort loading of MIptr
// In addition it is used to cause at least three busy cycles
// after which the FPU will accept new Insts
// The FPU is kept in reset until the last busy cycle
ME_FD1 ggh11 (Phi, notDecodedUnImp, notRemainBusy1, RemainBusy1);
ME_FD1 ggh12 (Phi, notRemainBusy1, notRemainBusy2, RemainBusy2);
ME_NAND2 ggh5 (notDecodedUnImp, notRemainBusy1,
ResetAbortInst);
ME_AND2 ggh6 (notRemainBusy1, notRemainBusy2, notAbortInst);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)lengthlogic.v 1.1 4/7/92
//
module LengthLogic (Phi, Reset,
FpInst1,
FpLd,
FpOp,
RomToggleLength,
notAbortWB,
OprSNnotDB,
BuffSNnotDB,
U_SNnotDB,
DBnotSN,
MulLenSel);
input Phi, Reset,
FpInst1, FpLd, FpOp, RomToggleLength, notAbortWB;
output OprSNnotDB,
U_SNnotDB,
DBnotSN,
BuffSNnotDB;
output [4:0]MulLenSel;
/* *************************************** */
/* Operand Length Logic */
/* *************************************** */
// MUX to FpInst if FpOp
// else used FpInst from previous cycle (original code)
// ME_FD1_B crg1 (Phi, FpInst1, notOprSNnotDBL, );
// ME_MUX2B_B mlen (FpOp, notOprSNnotDBL, FpInst1, notOprSNnotDB);
// timing fix -- dhn 04/15/91 -- this will only work if FpLd is
// always asserted 1 cycle after FpOp, never simultaneously
ME_FD1_B crg1 (Phi, FpInst1, notOprSNnotDB, );
ME_INV_C new0 (notOprSNnotDB, OprSNnotDB);
/* *************************************** */
/* Length Latch */
/* *************************************** */
ME_AND2 rmg3 (RomToggleLength, notAbortWB, LenFromnotLen);
ME_OR3 ell (FpLd, LenFromnotLen, Reset, Enable);
ME_NOR2 cllr (SNnotDB, Reset, notResetSNnotDB);
ME_NMUX2B lm (FpLd, notResetSNnotDB, OprSNnotDB, notMuxedLength);
ME_NMUX2B llm (Enable, DBnotSNb, notMuxedLength, U_SNnotDB);
ME_INVA lli (U_SNnotDB, U_DBnotSN);
ME_FD1_B llf (Phi, U_SNnotDB, SNnotDB, DBnotSNb);
ME_FD1_B lif (Phi, U_DBnotSN, DBnotSN, );
ME_FD1_B lig (Phi, U_DBnotSN, DBnotSNa, ); // goes only to
ME_INV_C llb (DBnotSNa, BuffSNnotDB); // High drive version
ME_FD1_B llf0 (Phi, U_SNnotDB, MulLenSel[0], );
ME_FD1_B llf1 (Phi, U_SNnotDB, MulLenSel[1], );
ME_FD1_B llf2 (Phi, U_SNnotDB, MulLenSel[2], );
ME_FD1_B llf3 (Phi, U_SNnotDB, MulLenSel[3], );
ME_FD1_B llf4 (Phi, U_SNnotDB, MulLenSel[4], );
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)microcoderom.v 1.1 4/7/92
//
module MicrocodeRom (Phi, int_UpdateOutputs, U_RomOutputs,
RomOutputs,
XDest,
YDest );
input Phi;
input int_UpdateOutputs;
input [`RomWidthM1:0] U_RomOutputs; // unbuffered output from ME_UROM
output [`RomWidthM1:0] RomOutputs; // latched version of U_RomOutputs
output [6:0] YDest;
output XDest;
ME_TIEOFF toff (, gnd);
// This flip-flop is only used during scan operations (to allow
// scan testing of the rom). It will be connected by the
// scan-stitcher when this block is routed.
ME_FD1 scanloadrom_ff (.cp(Phi), .d(gnd), .q(scanloadrom) );
ME_OR2 Uscanloadrom (int_UpdateOutputs, scanloadrom, UpdateOutputs);
// ***************************************//
// ROM :- ROM outputs latched //
// ***************************************//
// Rom outputs are held while waiting, Aborting the instruction,
// Nullifiying and in exceptions.
// The FB and control bits are only held on abort and wait.
ME_FREGA_1_64 romor (Phi, UpdateOutputs, U_RomOutputs, RomOutputs);
ME_FD1E_B romor540 (Phi, UpdateOutputs, U_RomOutputs[`u_FracYbusFromFunc0], YDest[0],);
ME_FD1E_B romor551 (Phi, UpdateOutputs, U_RomOutputs[`u_FracYbusFromFunc1], YDest[1],);
ME_FD1E_B romor542 (Phi, UpdateOutputs, U_RomOutputs[`u_FracYbusFromFunc2], YDest[2],);
ME_FD1E_B romor553 (Phi, UpdateOutputs, U_RomOutputs[`u_FracYbusFromFunc0], YDest[3],);
ME_FD1E_B romor554 (Phi, UpdateOutputs, U_RomOutputs[`u_FracYbusFromFunc1], YDest[4],);
ME_FD1E_B romor555 (Phi, UpdateOutputs, U_RomOutputs[`u_FracYbusFromFunc2], YDest[5],);
ME_FD1E_B romor556 (Phi, UpdateOutputs, U_RomOutputs[`u_FracYbusFromFunc0], YDest[6],); // SQRT bit
ME_FD1E_B romor557 (Phi, UpdateOutputs, U_RomOutputs[`u_FracXbusFromDest2], XDest,); // Round bit
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)miptr.v 1.1 4/7/92
//
module MIptr (Phi,
ExMIptrLSBs,
DyadicExc,
notInstAndNoExc,
notBranchTakenMIS,
notResetOrUnimp,
MIptrLoadEnable,
Feedback, FpInst,
SelectedMIptr,
RomMIptr, notRomMIptr);
input [2:0] ExMIptrLSBs;
input [`MIptrMSB:0] Feedback;
input [7:0] FpInst;
input Phi;
input DyadicExc,
notInstAndNoExc,
notBranchTakenMIS,
notResetOrUnimp,
MIptrLoadEnable;
output [`MIptrMSB:0] SelectedMIptr, RomMIptr, notRomMIptr;
ME_TIEOFF toff (vdd, gnd);
/* ****************************************************** *
* *
* 1) Enable has been removed from MIptr *
* *
* *
* *
* ****************************************************** */
wire [`MIptrMSB:0] NextMIptr;
// ***************************************//
// Operand Exception Address Generation //
// ***************************************//
ME_OR2 om2n6 (RomMIptr[2], notRomMIptr[6], MI2ornotMI6);
ME_NAND2 om16 (notRomMIptr[1], notRomMIptr[6], MI6orMI1);
MiptrIncrement mii (RomMIptr, NextMIptr);
MIptrMultiplexor mim
(Phi,
DyadicExc,
notInstAndNoExc,
notBranchTakenMIS,
notResetOrUnimp,
MIptrLoadEnable,
{FpInst[7], FpInst[3], FpInst[0], FpInst[1],
FpInst[6], FpInst[2], FpInst[4], FpInst[5]}, // RomEntry := SPARC code to ROM entry point mapping //
NextMIptr,
{RomMIptr[1], MI2ornotMI6, RomMIptr[6], MI6orMI1, gnd, ExMIptrLSBs}, // ExMIptr
Feedback,
SelectedMIptr,
RomMIptr,
notRomMIptr);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)miptrincrement.v 1.1 4/7/92
//
module MiptrIncrement (RomMIptr, NextMIptr);
input [7:0] RomMIptr;
output [7:0] NextMIptr;
// Increment of MI required (8 bits)
// always @MIptr NextMIptr = MIptr + 1;
ME_XOR2 ha_7 (RomMIptr[7], B7, NextMIptr[7] );
ME_ADD2 ha_6 (RomMIptr[6], B6, NextMIptr[6], B7);
ME_ADD2 ha_5 (RomMIptr[5], B5, NextMIptr[5], B6);
ME_ADD2 ha_4 (RomMIptr[4], B4, NextMIptr[4], B5);
ME_ADD2 ha_3 (RomMIptr[3], B3, NextMIptr[3], B4);
ME_ADD2 ha_2 (RomMIptr[2], B2, NextMIptr[2], B3);
ME_ADD2 ha_1 (RomMIptr[1], RomMIptr[0], NextMIptr[1], B2);
ME_INVA ha_0 (RomMIptr[0], NextMIptr[0]);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)miptrmultiplexor.v 1.1 4/7/92
//
module MIptrMultiplexor
(Phi,
DyadicExc,
notInstAndNoExc,
notBranchTakenMIS,
notResetOrUnimp,
MIptrLoadEnable,
RomEntry,
NextMIptr,
ExMIptr,
Feedback,
SelectedMIptr, // unregistered version of RomMIptr
RomMIptr,
notRomMIptr);
input Phi;
input DyadicExc,
notInstAndNoExc,
notBranchTakenMIS,
notResetOrUnimp,
MIptrLoadEnable;
input [7:0] RomEntry, NextMIptr,
ExMIptr, Feedback;
output [7:0] SelectedMIptr, RomMIptr, notRomMIptr;
wire [7:0] Z1, Z2, Z5, Z3, notFeedbackW;
ME_INV_C ble (MIptrLoadEnable, _MIptrLoadEnable);
ME_NMUX_2B_8 g2 (DyadicExc, NextMIptr, ExMIptr, Z1);
ME_MUX_2B_8 g3 (notInstAndNoExc, RomEntry, Z5, Z2);
ME_NMUX_2B_8 g4 (_MIptrLoadEnable, Z2, RomMIptr, Z3);
ME_NAND2 g6_0 (notResetOrUnimp, Z1[0], Z5[0]);
ME_NAND2 g6_1 (notResetOrUnimp, Z1[1], Z5[1]);
ME_NAND2 g6_2 (notResetOrUnimp, Z1[2], Z5[2]);
ME_NAND2 g6_3 (notResetOrUnimp, Z1[3], Z5[3]);
ME_NAND2 g6_4 (notResetOrUnimp, Z1[4], Z5[4]);
ME_NAND2 g6_5 (notResetOrUnimp, Z1[5], Z5[5]);
ME_NAND2 g6_6 (notResetOrUnimp, Z1[6], Z5[6]);
ME_NAND2 g6_7 (notResetOrUnimp, Z1[7], Z5[7]);
ME_NMUX_2B_8 g5 (_MIptrLoadEnable, Feedback, RomMIptr, notFeedbackW);
/* ********************************************************* */
// This bit should be converted into MUX and LATCH
/* ********************************************************* */
ME_NMUX2B g10 (notBranchTakenMIS, notFeedbackW[0], Z3[0], SelectedMIptr[0] );
ME_NMUX2B g11 (notBranchTakenMIS, notFeedbackW[1], Z3[1], SelectedMIptr[1] );
ME_NMUX2B g12 (notBranchTakenMIS, notFeedbackW[2], Z3[2], SelectedMIptr[2] );
ME_NMUX2B g13 (notBranchTakenMIS, notFeedbackW[3], Z3[3], SelectedMIptr[3] );
ME_NMUX2B g14 (notBranchTakenMIS, notFeedbackW[4], Z3[4], SelectedMIptr[4] );
ME_NMUX2B g15 (notBranchTakenMIS, notFeedbackW[5], Z3[5], SelectedMIptr[5] );
ME_NMUX2B g16 (notBranchTakenMIS, notFeedbackW[6], Z3[6], SelectedMIptr[6] );
ME_NMUX2B g17 (notBranchTakenMIS, notFeedbackW[7], Z3[7], SelectedMIptr[7] );
ME_FD1 mib0 (Phi, SelectedMIptr[0], RomMIptr[0], notRomMIptr[0]) ;
ME_FD1 mib1 (Phi, SelectedMIptr[1], RomMIptr[1], notRomMIptr[1]) ;
ME_FD1 mib2 (Phi, SelectedMIptr[2], RomMIptr[2], notRomMIptr[2]) ;
ME_FD1 mib3 (Phi, SelectedMIptr[3], RomMIptr[3], notRomMIptr[3]) ;
ME_FD1 mib4 (Phi, SelectedMIptr[4], RomMIptr[4], notRomMIptr[4]) ;
ME_FD1 mib5 (Phi, SelectedMIptr[5], RomMIptr[5], notRomMIptr[5]) ;
ME_FD1 mib6 (Phi, SelectedMIptr[6], RomMIptr[6], notRomMIptr[6]) ;
ME_FD1 mib7 (Phi, SelectedMIptr[7], RomMIptr[7], notRomMIptr[7]) ;
/*ME_FD2_B mib0 (Phi, notBranchTakenMIS, notFeedbackW[0], Z3[0], notRomMIptr[0], RomMIptr[0]) ;
ME_FD2_B mib1 (Phi, notBranchTakenMIS, notFeedbackW[1], Z3[1], notRomMIptr[1], RomMIptr[1]) ;
ME_FD2_B mib2 (Phi, notBranchTakenMIS, notFeedbackW[2], Z3[2], notRomMIptr[2], RomMIptr[2]) ;
ME_FD2_B mib3 (Phi, notBranchTakenMIS, notFeedbackW[3], Z3[3], notRomMIptr[3], RomMIptr[3]) ;
ME_FD2_B mib4 (Phi, notBranchTakenMIS, notFeedbackW[4], Z3[4], notRomMIptr[4], RomMIptr[4]) ;
ME_FD2_B mib5 (Phi, notBranchTakenMIS, notFeedbackW[5], Z3[5], notRomMIptr[5], RomMIptr[5]) ;
ME_FD2_B mib6 (Phi, notBranchTakenMIS, notFeedbackW[6], Z3[6], notRomMIptr[6], RomMIptr[6]) ;
ME_FD2_B mib7 (Phi, notBranchTakenMIS, notFeedbackW[7], Z3[7], notRomMIptr[7], RomMIptr[7]) ; */
/*CSL_FD1SP mib0 (notFeedbackW[0], Phi, Z3[0], notBranchTakenMIS, notRomMIptr[0], RomMIptr[0]);
CSL_FD1SP mib1 (notFeedbackW[1], Phi, Z3[1], notBranchTakenMIS, notRomMIptr[1], RomMIptr[1]);
CSL_FD1SP mib2 (notFeedbackW[2], Phi, Z3[2], notBranchTakenMIS, notRomMIptr[2], RomMIptr[2]);
CSL_FD1SP mib3 (notFeedbackW[3], Phi, Z3[3], notBranchTakenMIS, notRomMIptr[3], RomMIptr[3]);
CSL_FD1SP mib4 (notFeedbackW[4], Phi, Z3[4], notBranchTakenMIS, notRomMIptr[4], RomMIptr[4]);
CSL_FD1SP mib5 (notFeedbackW[5], Phi, Z3[5], notBranchTakenMIS, notRomMIptr[5], RomMIptr[5]);
CSL_FD1SP mib6 (notFeedbackW[6], Phi, Z3[6], notBranchTakenMIS, notRomMIptr[6], RomMIptr[6]);
CSL_FD1SP mib7 (notFeedbackW[7], Phi, Z3[7], notBranchTakenMIS, notRomMIptr[7], RomMIptr[7]);*/
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)miselect.v 1.1 4/7/92
//
module MISelect (Phi,
notReset,
notBrTaken,
notDecodedUnimp,
MIFromInstN, MIFromInstB,
notAbortInst, notAbortNulExc,
notResetOrUnimp,
DyadicOprExc, notSampledWait,
FpOp,
notSingleCycInst,
// outputs
BTHeld,
Busy, notIdleHeld,
notInstAndNoExc,
MILoadEnable);
input Phi, notReset;
input notBrTaken,
notDecodedUnimp,
MIFromInstN, MIFromInstB,
notAbortInst, notAbortNulExc,
notResetOrUnimp,
DyadicOprExc, notSampledWait,
FpOp,
notSingleCycInst; // Is single cycle
output BTHeld;
output Busy, notIdleHeld,
notInstAndNoExc,
MILoadEnable;
ME_TIEOFF toff (vdd, gnd);
ME_INVA iecepl (DyadicOprExc, notDyadicOprExc);
// ***************************************//
// Decide if next is new Inst //
// ***************************************//
// MIFromInstN Execute Inst if Br not taken
// MIFromInstB Execute Inst Br taken
// Note delay cycle
ME_NAND3 g4_0 (MIFromInstN, notAbortNulExc, notSampledWait,
notMIFromInstNExc);
ME_NAND2 g4_1 (MIFromInstN, notAbortNulExc, // notSampledWait, Shouldnt be a function of this
notMIFromInstNExcNS);
ME_NAND2 g4_2 (MIFromInstB, notSampledWait, notMIFromInstBW);
ME_FD1 g4_3 (Phi, notMIFromInstBW, , MIFromInstBHeld);
ME_NAND2 g4_4 (BTHeld, MIFromInstBHeld, s_0);
ME_FD1 g4_5 (Phi, notResetOrUnimp, nots_1, );
ME_AND4 g4_6 (s_0, nots_1, notSingleCycInst, notIdleHeld, notZZTop);
ME_NAND2 g4_7 (notZZTop, notMIFromInstNExc, MIFromInst);
ME_NAND2 g4_8 (notZZTop, notMIFromInstNExcNS, MIFromInstNS);
// ***************************************//
// Are we going to be idle //
// ***************************************//
ME_INVA g5_0 (FpOp, notFpOp);
ME_NAND2 g5_1 (MIFromInst, notFpOp, notIdleIfNotBred);
ME_FD1 g5_3 (Phi, notIdleIfNotBred, notIIfNotBredHld, );
ME_NMUX2B g5_2 (notBTHeld, vdd, notIIfNotBredHld, IdleHeldNR);
ME_NAND2 g5_4 (IdleHeldNR, notReset, notIdleHeld);
// ***************************************//
// Select next MI for ROM to decode //
// ***************************************//
// Combine Wait Exception and Br logic into ROM control
//
ME_BUF_B mie0 (notSampledWait, MILoadEnable); // Buff over 8 bits
//
ME_NAND3_B g0_0 (MIFromInstNS, notDyadicOprExc, notResetOrUnimp,
notInstAndNoExc);
// ***************************************//
// Started New Inst //
// ***************************************//
// Requirement for testing for implemented entry points.
// These need to be qualified as being the first Inst
// since garbage code may jump through an entry point
// thus setting the implemented flag.
// Optimise
// Latch BT
ME_FD1 g2_1 (Phi, notBrTaken, notBTHeld, BTHeld);
// ***************************************//
// FPU Busy //
// ***************************************//
// Remain busy while aborting an Unimp
ME_AND4 ggh7 (notAbortInst, notDyadicOprExc,
MIFromInst, notSampledWait,
notMIsBusyBT0);
ME_AND2 ggh8 (notMIsBusyBT0, notDecodedUnimp, notBusyBT0);
ME_NMUX2B_B ggh9 (notBrTaken, gnd, notBusyBT0, Busy);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)mullsblog.v 1.1 4/7/92
//
module StickyPairNC (StkIn, notCin, X, Y, StkOut, notCout);
input StkIn, notCin ;
input [1:0] X, Y ;
output StkOut, notCout ;
ME_XNOR2_B g10 ( X[0], Y[0], notZ0 );
ME_XNOR2_B g11 ( X[1], Y[1], notZ1 );
ME_OR2_B g13 ( notZ0, notZ1, notProp );
// generate logic
//ME_NMUX2B g12 ( Z1, x[1], x[0], notglo ) ;
ME_NAND3 g20 ( X[0], Y[0], X[1], g1 );
ME_NAND3 g21 ( X[0], Y[0], Y[1], g2 );
ME_NAND2 g22 ( X[1], Y[1], g3 );
ME_NAND3 g23 ( g1, g2, g3, generate );
// local sticky
ME_NAND2 g14 ( X[0], Y[0], notgenlo);
ME_XOR3_B g26 ( notgenlo, X[1], Y[1], bit1);
ME_NAND3 g24 ( notZ0, bit1, notCin, StkGen);
ME_NMUX2B g28 ( notProp, notCin, StkGen, notStk ) ;
// bypasses
ME_INV_A g31 ( StkIn, notStkIn );
ME_NAND2 g32 ( notStkIn, notStk, StkOut );
ME_INVA g27 ( notCin, Cin );
ME_NMUX2B_B g34 ( notProp, Cin, generate, notCout );
endmodule
module StickyPairNCI (StkIn, notCin, X, Y, StkOut, Cout);
input StkIn, notCin ;
input [1:0] X, Y ;
output StkOut, Cout ;
ME_XNOR2_B g10 ( X[0], Y[0], notZ0 );
ME_XNOR2_B g11 ( X[1], Y[1], notZ1 );
ME_OR2_B g13 ( notZ0, notZ1, notProp );
// generate logic
//ME_NMUX2B g12 ( Z1, x[1], x[0], notglo ) ;
ME_NAND3 g20 ( X[0], Y[0], X[1], g1 );
ME_NAND3 g21 ( X[0], Y[0], Y[1], g2 );
ME_NAND2 g22 ( X[1], Y[1], g3 );
ME_NAND3 g23 ( g1, g2, g3, generate );
// local sticky
ME_NAND2 g14 (X[0], Y[0], notgenlo);
ME_XOR3_B g26 ( notgenlo, X[1], Y[1], bit1);
ME_NAND3_B g25 ( notZ0, bit1, notCin, StkGen);
ME_NMUX2B g28 ( notProp, notCin, StkGen, notStk ) ;
// bypasses
ME_INVA g31 ( StkIn, notStkIn );
ME_NAND2_B g32 ( notStkIn, notStk, StkOut );
ME_INVA g27 ( notCin, Cin );
ME_MUX2B g34 ( notProp, Cin, generate, Cout );
endmodule
module MulLSBlog (SIn, CIn, SInA, CInA, LSBCarryIn, StickyIn,
LSBCarryOut, StickyOut);
input [1:0] SIn, CIn;
input [5:0] SInA, CInA;
input LSBCarryIn, StickyIn;
output LSBCarryOut, StickyOut;
// wire [2:0] Sticky;
// wire [7:0] SS;
// wire [7:1] CO;
ME_INVA g27 ( LSBCarryIn, notLSBCarryIn );
StickyPairNC m0 (StickyIn, notLSBCarryIn, CIn, SIn, SS0, notC0);
StickyPairNC m1 (SS0, notC0, CInA[1:0], SInA[1:0], SS1, notC1);
StickyPairNC m2 (SS1, notC1, CInA[3:2], SInA[3:2], SS2, notC2);
StickyPairNCI m3 (SS2, notC2, CInA[5:4], SInA[5:4], StickyOut, LSBCarryOut);
// ME_ADD3 a0 (CIn[0], SIn[0], LSBCarryIn, SS[0], CO[1]);
// ME_ADD3 a1 (CIn[1], SIn[1], CO[1], SS[1], CO[2]);
// ME_OR3 o1 (SS[0], SS[1], StickyIn, Sticky[0]);
// ME_ADD3 a2 (CInA[0], SInA[0], CO[2], SS[2], CO[3]);
// ME_ADD3 a3 (CInA[1], SInA[1], CO[3], SS[3], CO[4]);
// ME_OR3 o2 (SS[2], SS[3], Sticky[0], Sticky[1]);
// ME_ADD3 a4 (CInA[2], SInA[2], CO[4], SS[4], CO[5]);
// ME_ADD3 a5 (CInA[3], SInA[3], CO[5], SS[5], CO[6]);
// ME_OR3 o3 (SS[4], SS[5], Sticky[1], Sticky[2]);
// ME_ADD3 a6 (CInA[4], SInA[4], CO[6], SS[6], CO[7]);
// ME_ADD3 a7 (CInA[5], SInA[5], CO[7], SS[7], LSBCarryOut);
// ME_OR3 o4 (SS[6], SS[7], Sticky[2], StickyOut);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)mulselctl.v 1.1 4/7/92
//
module MulSelCtl (notMult, Shifted, Pos, Zero, ACI);
input [2:0] notMult;
output Shifted, Zero, Pos, ACI;
//
// Mult 0 0 0
// ACI is Actual Carry In
// Shifted is 1
ME_XOR2_B xnr7 (notMult[1], notMult[0], Shifted);
/* Feedthrough */
/* wire Negative = Mult[2]; */
con1 g00 (notMult[2], Pos);
ME_INV_A g01 (notMult[2], Negative);
// assert ACI if subtracting
ME_OR2_B cz1 (notMult[0], notMult[1], notSwig);
ME_AND2 cz2 (Negative, notSwig, ACI); // 2 gates
//ME_INV_B g02 (Negative, notMult2);
// all ones or all zeros gives zero
ME_OR3_B nzr5 (notMult[2], notMult[0], notMult[1], notPos0);
ME_NAND3 nzr6 (notMult[2], notMult[1], notMult[0], notNeg0);
ME_NAND2_B nzr8 (notNeg0, notPos0, Zero);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)multiplierlsb.v 1.1 4/7/92
//
module MultiplierLSB (
// inputs
Rom_ResetMul,
notMultip,
notAbortWB,
SumInLSBs, CarryInLSBs,
SCLSBs, SBLSBs, SALSBs,
CCLSB, CBLSB, CALSB,
// outputs
Shift,
Pos,
Zero,
CarryOut0,
CarryOut3,
SumOut0,
SumCarryLoadEn,
InitialMulStep,
/* dhn--01/10/91 notInitialSumZero, */
InitialCarryBit);
input notAbortWB, Rom_ResetMul;
input [2:0] SumInLSBs, CarryInLSBs;
input [1:0] SCLSBs, SBLSBs, SALSBs;
input CCLSB, CBLSB, CALSB;
input [8:0] notMultip;
output [3:0] Shift, Pos, Zero;
output CarryOut0,
CarryOut3,
SumOut0;
output InitialCarryBit,
SumCarryLoadEn,
InitialMulStep;
/* dhn--01/10/91 notInitialSumZero; */
/* *************************************************
Multipler Selection Decoding
************************************************* */
MulSelCtl m13 (notMultip[8:6], Shift[3], Pos[3], Zero[3], CarryOut3);
MulSelCtl m12 (notMultip[6:4], Shift[2], Pos[2], Zero[2], CCIn);
MulSelCtl m11 (notMultip[4:2], Shift[1], Pos[1], Zero[1], CBIn);
MulSelCtl m10 (notMultip[2:0], Shift[0], Pos[0], Zero[0], CAIn);
/* *************************************************
Full Add over LSBs and OR result
************************************************* */
MulLSBlog lbg (SumInLSBs[2:1], CarryInLSBs[2:1],
{SCLSBs, SBLSBs, SALSBs},
{CCLSB, CCIn, CBLSB, CBIn, CALSB, CAIn},
//ArraySStk,
//ArrayCStk,
CarryInLSBs[0], SumInLSBs[0],
CarryOut0, SumOut0);
carrysaveregslsb csrl (Rom_ResetMul,
notMultip[0],
notAbortWB,
SumCarryLoadEn,
InitialMulStep,
/* dhn--01/10/91 notInitialSumZero, */
InitialCarryBit);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)normcalslice.v 1.1 4/7/92
//
module NormCalSlice (NI, notsh, notNO);
input [15:0] NI;
output [3:1] notsh;
output [1:0] notNO;
wire [3:0] notNR ;
twosch m1 (NI[7:0], sh1a, sh2a, notNR[1:0]);
twosch_top m2 (NI[15:8], sh1b, sh2b, notNR[3:2], NR1and0);
onesch_sp m3 (notNR[3:0], notsh[3], notNO[1:0]);
// anything set on top then take s1 , s2 from top
ME_NMUX2B m4 (NR1and0, sh1a, sh1b, notsh[1]);
ME_NMUX2B m6 (NR1and0, sh2a, sh2b, notsh[2]);
endmodule
module twosch (NI[7:0],sh1,sh2,notNO[1:0] );
input [7:0] NI ;
output sh1, sh2 ;
output [1:0] notNO ; // true OR value here
wire [3:0] notNR ;
onesch m1 (NI[3:0], notsh1a, notNR[1:0]);
onesch m2 (NI[7:4], notsh1b, notNR[3:2]);
notonesch m3 (notNR[3:0], sh2, notNO[1:0]);
// anything set on top then take s1 from top
ME_NMUX2B m4 (notNO[1], notsh1b, notsh1a, sh1 );
endmodule
module twosch_top (NI[7:0],sh1,sh2,notNO[1:0], NO1and0 );
input [7:0] NI ;
output sh1, sh2 ;
output [1:0] notNO ; // true OR value here
output NO1and0 ;
wire [3:0] notNR ;
onesch m1 (NI[3:0], notsh1a, notNR[1:0]);
onesch m2 (NI[7:4], notsh1b, notNR[3:2]);
notonesch m3 (notNR[3:0], sh2, notNO[1:0]);
// anything set on top then take s1 from top
ME_NMUX2B_B m4 (notNO[1], notsh1b, notsh1a, sh1 );
ME_NAND4 m5 (notNR[0], notNR[1], notNR[2], notNR[3], NO1and0);
// Special
endmodule
module onesch (NI[3:0], notsh1, notNR[1:0]);
input [3:0] NI;
output notsh1;
output [1:0] notNR ;
ME_INV_A i1 (NI[1], notNI1);
ME_NOR2 i2 (NI[2], notNI1, notBornotC);
ME_OR2 i3 (NI[3], notBornotC, notsh1);
// ME_INV_A i1 (NI[1], notNI1);
// ME_INV_A i2 (NI[3], notNI3);
// ME_O2A1I i3 (notNI1, NI[2], notNI3, notsh1);
ME_NOR2_B r4 (NI[0], NI[1], notNR[0] );
ME_NOR2_B r5 (NI[2], NI[3], notNR[1] );
endmodule
module notonesch (notNI[3:0], sh1, notND[1:0]);
input [3:0] notNI;
output sh1;
output [1:0] notND ;
ME_INV_A i1 (notNI[1], NI1);
ME_NAND2_B i2 (NI1, notNI[2], notBornotC);
ME_AND2_B i3 (notNI[3], notBornotC, sh1);
// ME_INV_A i1 (notNI[1], NI1);
// ME_INV_A i2 (notNI[3], NI3);
// ME_A2O1I i3 (NI1, notNI[2], NI3, sh1);
ME_AND2_B r4 (notNI[0], notNI[1], notND[0] );
ME_AND2_B r5 (notNI[2], notNI[3], notND[1] );
endmodule
module onesch_sp (notNI[3:0], notsh1, notND[1:0]);
input [3:0] notNI;
output notsh1;
output [1:0] notND ;
ME_INV_A i1 (notNI[1], NI1);
ME_NAND2_B i2 (NI1, notNI[2], notBornotC);
ME_NAND2_B i3 (notNI[3], notBornotC, notsh1);
// ME_INV_A i1 (NI[2], notNI2);
// ME_O2A1I i2 (notNI[1], NI2, notNI[3], notsh1);
ME_NAND2 r4 (notNI[0], notNI[1], notND[0] );
ME_NAND2_B r5 (notNI[2], notNI[3], notND[1] );
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)nullifyexceptionlogic.v 1.1 4/7/92
//
module NullExcepLogic (Phi, notReset,
RomNullifyOnBrOr,
RomOprExc,
BTLatched, notSampledWait,
FpLd,
notAInfNan, notAZeroDenorm,
notBInfNan, notBZeroDenorm,
ExMIptrLSBs,
AregOprExc,
DyadicOprExc,
notAbortNulExc,
notAbortWB);
input Phi, notReset, // System Clock Reset
RomNullifyOnBrOr, // Nullify if we Br
RomOprExc, // Check for Op Exception
BTLatched, // We have Bring
notSampledWait, // Don't nullify if waiting
FpLd, // FpLd Force write back
notAInfNan, notAZeroDenorm,
notBInfNan, notBZeroDenorm;
output [2:0] ExMIptrLSBs;
output notAbortNulExc,
AregOprExc,
DyadicOprExc,
notAbortWB;
// ***************************************//
// Nullification for Br //
// ***************************************//
// An unwaited output is used to prevent locking in the NULL state
// NullEx is fedback to prevent locking
// ie only one NULL cycle will occur.
// The signal notNullifyOnBr is therefore 'If the Br is
// taken
//
ME_AND2 rb (RomNullifyOnBrOr, notNullEx, NullifyOnBr);
// ME_INVA sx (SampledWait, notSampledWait);
// Optimise
// ME_NAND3 re (notSampledWait, BrTaken, NullifyOnBr, notND);
// These ROM outputs occur on Phi and then cause write back events
// themselves.
// ME_FD1 rf (Phi, notND, notNullEx, NullEx);
ME_NAND2 re (notSampledWait, NullifyOnBr, notNDBTMiss);
ME_FD1 rf (Phi, notNDBTMiss, , NullExBTMiss);
ME_NAND2 g_1 (BTLatched, NullExBTMiss, notNullEx);
ME_INVA g_0 (notNullEx, NullEx);
// NullEx is used to clear the Nullify
// This is used to generate the abort for the write back of
// the nullified cycle. It is combined with the ExcCycle
// and DyadicOprExc signals and to produce AbortWB
// ***************************************//
// Check Opr Exception //
// ***************************************//
ME_NAND2 exg1 (notAInfNan, notAZeroDenorm, AregOprExc);
ME_NAND2 exg2 (notBInfNan, notBZeroDenorm, BregOprExc);
ME_OR2_B exg3 (AregOprExc, BregOprExc, OprExc);
// ***************************************//
// Operand Exception Address Generation //
// ***************************************//
// quick
ME_AND2 eag1 (AregOprExc, BregOprExc, ExMIptrLSBs[2]);
ME_NAND2 eag2 (AregOprExc, notBInfNan, ExMIptrLSBs[1]);
ME_OR2 eag3 (AregOprExc, notBInfNan, notAnormandBin);
ME_NAND2 eag5 (notAnormandBin, notAInfNan, ExMIptrLSBs[0]);
// ***************************************//
// Control Operand Exception //
// ***************************************//
// Ignore Exception if Nullified on previous
ME_AND4 ssss (RomOprExc, notNullEx, notReset, notExcCycle, OprExcEtc);
ME_AND2_B cko (OprExc, OprExcEtc, DyadicOprExc);
ME_FD1 zrd (Phi, DyadicOprExc, ExcCycle, notExcCycle);
// ***************************************//
// Aborting //
// ***************************************//
// Exc and NullEx require next operation to be aborted.
// In addition Exception requires current operation to be aborted.
// Aborting is acheived by preventing results of this cycle to
// be written back.
ME_OR2 yyy (ExcCycle, NullEx, AbortNulExc);
ME_INVA yyc (AbortNulExc, notAbortNulExc);
ME_OR2_B yyb (DyadicOprExc, AbortNulExc, AbortWBNoLoad);
ME_NAND2_B yyd (AbortWBNoLoad, notFpLd, notAbortWB); // Drives a few
ME_INVA yye (FpLd, notFpLd);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)preventswapctl.v 1.1 4/7/92
//
module PreventSwapCtl (FracAgtB, notExpAgtB, ExpZero,
RomPrevIfBgtA, FpLd,
PreventSwap,
PreventSwapExp);
input FracAgtB, notExpAgtB, ExpZero,
FpLd, RomPrevIfBgtA;
output PreventSwap;
output PreventSwapExp;
// Preventing swap on add
// Use seperate line for Exp
ME_INV_A psg0 (FpLd, notFpLd); // On FpLd remove prevent swap
ME_INV_A psg3 (ExpZero, notExpZero);
ME_NAND3_B psg4 (notFpLd, RomPrevIfBgtA, notExpAgtB, notPrevSwap_F0);
ME_NAND4 psg5 (notFpLd, RomPrevIfBgtA, notExpAgtB, notExpZero, notPrevSwap_F1);
ME_NMUX2B_B psg6 (FracAgtB, notPrevSwap_F0, notPrevSwap_F1, PreventSwap);
// Add seperate PreventSwap for Exp
ME_INV_B psg7 (notPrevSwap_F0, PreventSwapExp);
//ME_XOR psg8 (PreventSwapExp, PreventSwap, WrongSwap);
//ME_FD1 psg8 (Phi, WrongSwap, L_WrongSwap, ); // So swap back !!
/* **************************************************** /
/ We know that we've done the wrong swap. Since the
/ swap is only done at the begining of add we can be sure
/ that FracAreg is going to be loaded from the shifter on
/ the subsequent cycle. So we can force it to be loaded from
/ Breg and also force Breg to be loaded from Areg. So that
/ if a swap was prevented it can be redone
* **************************************************** */
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)roundingmodelogic.v 1.1 4/7/92
//
module RoundModeLogic (Phi,
OprRoundMode,
LoadOprs,
notAbortWB,
CMPDecoded, CMPEDecoded,
RomSetRModeMinus,
RModeMinus,
U_RoundingMode);
input Phi;
input [1:0] OprRoundMode;
input LoadOprs,
notAbortWB,
CMPDecoded, CMPEDecoded,
RomSetRModeMinus;
output RModeMinus;
output [1:0] U_RoundingMode;
/* *************************************** */
/* Rounding Mode Latch */
/* *************************************** */
/* In addition to being the rounding mode this latch is also used in
the compares to signal between the two different types Invalid/Vailid
on unordered. This is TACKY but saves a lot of code
Additional inputs CMPE and CMP distinguish between the two types
It isnt a big problem because RMode is part of the instruction not
ME_ROM and so no timing problems will occur */
wire [1:0] notModifiedRMode, notRoundingMode, RoundingMode;
ME_INVA cmpbits (CMPDecoded, notCMPDecoded);
ME_AND2 rmcmp1 (OprRoundMode[1], notCMPDecoded, CMPRMode1);
ME_AND2_B fgf (RomSetRModeMinus, notAbortWB, RModeFromMinus);
ME_NOR3 rmcmpe1 (CMPRMode1, CMPEDecoded, RModeFromMinus, notModifiedRMode[1]);
ME_NOR3 rmcmpe0 (OprRoundMode[0], CMPEDecoded, RModeFromMinus, notModifiedRMode[0]);
/* RoundingMode is latched from status register at the begining of
a new instruction. It is transient therefore. */
ME_OR2_B fgfo (RModeFromMinus, LoadOprs, RMLatchEnable);
ME_NMUX2B rm0m (RMLatchEnable, notRoundingMode[0], notModifiedRMode[0], U_RoundingMode[0]);
ME_FD1 rm0f (Phi, U_RoundingMode[0], RoundingMode[0], notRoundingMode[0]);
ME_NMUX2B rm1m (RMLatchEnable, notRoundingMode[1], notModifiedRMode[1], U_RoundingMode[1]);
ME_FD1 rm1f (Phi, U_RoundingMode[1], RoundingMode[1], notRoundingMode[1]);
ME_AND2 rmc (RoundingMode[0], RoundingMode[1], RModeMinus);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)sampledwaitctl.v 1.1 4/7/92
//
module SampledWaitCtl (
RomShiftAlign, RomShiftForInt, RomLeftnotRight,
notReset,
notAbortNulExc,
notWaitForShifter,
notNO[1:0],
notIdleLatched,
UpdateOutputs,
notSampledWait);
input RomShiftAlign, RomShiftForInt, RomLeftnotRight;
input notReset, notAbortNulExc;
input notWaitForShifter;
input [1:0] notNO;
input notIdleLatched;
output UpdateOutputs, notSampledWait;
// Cycle maybe nullifed ie AbortNulExc
ME_INVA swrb2 (RomLeftnotRight, RightnotLeft);
ME_OR2_B n0 ( notNO[1], notNO[0], notWaitForNorm ) ;
ME_NMUX2B swrb3 (RomLeftnotRight, notWaitForShifter, notWaitForNorm, WaitQ);
ME_NOR2 swmzs (RomShiftForInt, RightnotLeft, RomWaitForNorm);
ME_OR2 swmis (RomShiftAlign, RomWaitForNorm, RomWaitForShifter);
ME_AND3 g1_0 (notReset, notAbortNulExc, RomWaitForShifter, notPreventWait);
// Add muxes
ME_NAND2_B sweb (WaitQ, notPreventWait, notSampledWait);
ME_AND2 wwpp2 (notSampledWait, notIdleLatched, UpdateOutputs);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)samplereset.v 1.1 4/7/92
//
module SampleReset (Phi, ResetIn, ResetAbortInst,
ResetImp, Reset, notReset);
input ResetIn, ResetAbortInst, Phi;
output ResetImp, Reset, notReset;
ME_FD1 rs (Phi, ResetIn, ResetImp, );
ME_OR2 cva (ResetImp, ResetAbortInst, ResetInorAbort);
ME_FD1 rva (Phi, ResetInorAbort, Reset, notReset);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)shiftleftctl.v 1.1 4/7/92
//
// This module provides the top bits in for the left shift (frac or const)
module ShiftLeftCtl (NI_49_47,
LoadForInt,
LIB);
input [2:0] NI_49_47;
input LoadForInt;
output [2:0] LIB;
ME_TIEOFF toff (vdd, gnd);
ME_MUX2B g20 (LoadForInt, NI_49_47[2], gnd, LIB[2]);
ME_MUX2B g21 (LoadForInt, NI_49_47[1], gnd, LIB[1]);
ME_MUX2B g22 (LoadForInt, NI_49_47[0], vdd, LIB[0]);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)shiftrightctl.v 1.1 4/7/92
//
module ShiftRightCtl (
LoadForInt,
AregMasterBuf_57_55,
ExpIn,
SRControl,
SROneMore,
SRToStky,
Stky8,
notStky4,
Stky2,
notStky1,
StkyExtra,
RomShForAl,
notStkyInForSR,
TopBitsIn);
input LoadForInt;
input [2:0] AregMasterBuf_57_55;
input [8:0] ExpIn;
input [7:0] Stky8; // 8 Stky bits from 8 bit stage
input [3:0] notStky4; // 4 inv Stky bits from 4 bit stage
input [1:0] Stky2; // 2 Stky bits from 2 bit stage
input notStky1; // 1 inv Stky bits from 1 bit stage
input [1:0] StkyExtra; // 2 Stky bits from extra 1 bit stage
input [3:0] SRControl;
input SROneMore, SRToStky;
input RomShForAl;
output notStkyInForSR;
output [8:0] TopBitsIn;
// select TopBitsIn
ME_MUX_2B_9 g69 (LoadForInt,
{AregMasterBuf_57_55[2], AregMasterBuf_57_55[2],
AregMasterBuf_57_55[2], AregMasterBuf_57_55[2],
AregMasterBuf_57_55[2], AregMasterBuf_57_55[2],
AregMasterBuf_57_55[2:0]},
ExpIn[8:0],
TopBitsIn);
ME_OR8 g80 (Stky8[0], Stky8[1], Stky8[2], Stky8[3],
Stky8[4], Stky8[5], Stky8[6], Stky8[7], StkyOR8);
ME_NAND2 g8d (StkyOR8, SRControl[3], notStkyA);
ME_NAND4 g81 (notStky4[0], notStky4[1], notStky4[2], notStky4[3], StkyOR4);
ME_NAND2 g8c (StkyOR4, SRControl[2], notStkyB);
ME_O2A1I g82 (Stky2[0], Stky2[1], SRControl[1], notStkyC);
//ME_OR2 g82 (Stky2[0], Stky2[1], StkyOR2);
//ME_NAND2 g84 (StkyOR2, SRControl[1], notStkyC);
ME_INVA g86 (SRControl[0], notSRC0);
ME_OR2 g85 (notStky1, notSRC0, notStkyD);
ME_INVA g89 (RomShForAl, notRomShForAl);
ME_NAND2 gxa (StkyExtra[1], SROneMore, notStkyE);
ME_NAND2 g8x (notRomShForAl, SROneMore, notgoop);
ME_NAND2 gxx (notgoop, StkyExtra[0], notLSB);
//ME_O2A1I g8x (StkyExtra[0], StkyExtra[1], SROneMore, notStkyE);
ME_AND2 g12 (notStkyA, notStkyB, notStkyAB);
ME_NAND3 g13 (notStkyAB, notStkyC, notStkyD, StkyABCD);
// When multiplying the last thing we want is the sticky bit getting
// set. The sticky only gets set therefore if we're shifting right
// for align or stifting right to sticky in one go
ME_INVA g90 (SRToStky, notSRToStky);
ME_NAND2 g91 (notSRToStky, RomShForAl, notSelectStkyABCD);
ME_NMUX2B g92 (notSelectStkyABCD, StkyABCD, SRToStky, notStkyABCDS);
ME_AND3 g88 (notStkyE, notLSB, notStkyABCDS, notStkyInForSR);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)signdp.v 1.1 4/7/92
//
module SignDp ( Phi, Reset,
RomSignLength,
RomStatus,
FracXFromRound,
XDest,
CMPDecoded, CMPEDecoded,
SignOpA, SignOpB,
notAbortWB, PreventSwap,
FpLd, FpOp,
NegateOprSign,
notSignAFromB, notSignBFromA,
OprRoundMode,
FpInst1,
Unimplemented,
SignResult,
AregSign, AregXORBreg,
FpExc_Unimp,
Status_6_2,
ConditionCodes,
OprSNnotDB, SNnotDB, DBnotSN,
MulLenSel,
RModeMinus,
FracRoundOut );
input Phi, Reset;
input [`end_sign_field:`start_sign_field] RomSignLength;
input [`end_status_field:`start_status_field] RomStatus;
input FracXFromRound; // Optimised signal
input XDest;
input SignOpA, SignOpB,
notAbortWB, PreventSwap,
FpLd, FpOp, NegateOprSign;
input notSignAFromB,
notSignBFromA,
FpInst1,
Unimplemented;
input [1:0] OprRoundMode;
input CMPDecoded, CMPEDecoded;
output SignResult, AregSign, AregXORBreg;
output FpExc_Unimp;
output [1:0] ConditionCodes;
output OprSNnotDB, SNnotDB, DBnotSN;
output [4:0]MulLenSel;
output RModeMinus;
output [4:0] FracRoundOut ;
output [6:2] Status_6_2;
wire notRN ;
wire [4:1] FracRound;
assign FracRoundOut = {FracRound[4:1], notRN} ;
wire [6:0] Status;
assign Status_6_2 = Status[6:2] ;
wire [1:0] U_RoundingMode;
SignLogic sl (Phi, Reset,
RomSignLength [`u_SignAregFromResult:`u_SignResultFromFunction0],
RomStatus[`u_Unimplemented],
Status[0], Status[1],
SignOpA, SignOpB,
NegateOprSign,
FpLd,
notAbortWB, PreventSwap,
U_RoundingMode[0],
Unimplemented,
notSignAFromB, notSignBFromA,
AregSign, AregXORBreg,
U_CouldBeRI_0, // Bent place to do but needs a lot of sign stuff
FpExc_Unimp,
ConditionCodes,
SignResult);
RoundModeLogic rml (Phi,
OprRoundMode,
FpLd,
notAbortWB,
CMPDecoded, CMPEDecoded,
RomSignLength [`u_SetRoundingModeToMinus],
RModeMinus,
U_RoundingMode);
LengthLogic ll (Phi, Reset,
FpInst1,
FpLd, FpOp,
RomSignLength[`u_ToggleLength],
notAbortWB,
OprSNnotDB,
SNnotDB,
U_SNnotDB,
DBnotSN,
MulLenSel);
DecodeStatus ds (RomStatus[`u_status3:`u_status0],
Status);
/* For the Rounding cycles make some of controls faster */
ME_AND2 v2 (U_RoundingMode[1], U_CouldBeRI_0, U_CouldBeRI);
ME_FD1_B x1 (Phi, U_CouldBeRI, CouldBeRI, );
ME_AND3_B s2 (U_RoundingMode[1], U_CouldBeRI_0, U_SNnotDB, U_CouldBeRISN);
ME_FD1_B x4 (Phi, U_CouldBeRISN, CouldBeRISN, );
ME_NOR2 v3 (U_RoundingMode[1], U_RoundingMode[0], U_CouldBeRN);
ME_FD1_B x2 (Phi, U_CouldBeRN, CouldBeRN, );
ME_AND2_B s1 (U_CouldBeRN, U_SNnotDB, U_CouldBeRNSN);
ME_FD1_B x3 (Phi, U_CouldBeRNSN, CouldBeRNSN, );
// FracXbus comes from Breg or a constant
// want to constuct constant as fields
// ie
// 2 1 23 1 28 1 2
//
// 00 0 000_00..00_0000 0 0000_00..00_0000 0 00 Zero
// 00 1 000_00..00_0000 0 0000_00..00_0000 0 00 One
// 00 0 000_00..00_0000 1 1111_11..11_1111 1 11 RC SN 2
// 00 0 000_00..00_0000 0 1111_11..11_1111 1 11 RC SN 1
// 00 0 000_00..00_0000 0 0000_00..00_0000 1 11 RC DB 2
// 00 0 000_00..00_0000 0 0000_00..00_0000 0 11 RC DB 1
// Field Names
// a b c d e f g
//
// a == 0
// b == FracXbusFrom1
// c == 0
// d == RI & SN
// e == (RI | RN) & SN
// f == RI | (RN & SN)
// g == RI | RN
// 00 = Round Nearest
// 01 = Round Zero ( Truncate )
// 10 = Round positive infinity
// 11 = Round negative infinity
// Round Nearest
ME_NAND2 rg4 (CouldBeRN, FracXFromRound, notRN);
ME_NAND2 rzz1s (CouldBeRNSN, FracXFromRound, notRNSN);
// Round Infinities //
ME_NAND2 rv2 (CouldBeRI, FracXFromRound, notRI);
ME_NAND2 rv3 (CouldBeRISN, FracXFromRound, notRISN);
// Constant d
ME_INV_B rlokout (notRISN, FracRound[4]);
// Constant e
ME_AND2_B s3 (U_RoundingMode[1], U_SNnotDB, U_RMode1SN);
ME_AND2_B s4 (U_RMode1SN, U_CouldBeRI_0, U_CouldBeRISNa);
ME_OR2 rc0 (U_CouldBeRNSN, U_CouldBeRISNa, U_constante);
ME_FD1_B rc1 (Phi, U_constante, r_constante, );
ME_NAND2_B rv03 (r_constante, XDest, notConstante);
//ME_AND2_B rvo3 (notRNSN, notRISN, notConstante);
ME_INV_D rvo4 (notConstante, FracRound[3]); // Has fanout of 28
// Constant f
ME_NAND2_B rvo2 (notRNSN, notRI, FracRound[2]);
// Constant g
ME_NAND2_B rvo1 (notRI, notRN, FracRound[1]);
// FracRound[4:1] Constantd, Constante, Constantf, Constantg,
// FracRound[0] = notRN
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)signlogic.v 1.1 4/7/92
//
module SignLogic (Phi, Reset,
RomSignLength,
Rom_Unimplemented,
Rom_StatusCCBit0, Rom_StatusCCBit1,
SignOpA, SignOpB,
NegateOprSign,
LoadOprs,
notAbortWB, PreventSwap,
U_RoundingMode0,
Unimplemented,
notSignAFromB, notSignBFromA,
AregSign, AregXORBreg,
U_CouldBeRI_0,
FpExc_Unimp,
ConditionCodes,
SignResult);
input Phi, Reset;
input [`u_SignAregFromResult:`u_SignResultFromFunction0]RomSignLength;
input Rom_StatusCCBit0, Rom_StatusCCBit1, Rom_Unimplemented;
input SignOpA, SignOpB,
LoadOprs,
notAbortWB,
PreventSwap,
U_RoundingMode0, // Unlatched rounding mode bit 0
NegateOprSign;
input Unimplemented;
input notSignAFromB,
notSignBFromA;
output AregSign,
AregXORBreg,
U_CouldBeRI_0, // Unlatched for next cycle
SignResult;
output FpExc_Unimp;
output [1:0] ConditionCodes;
ME_TIEOFF toff (vdd, gnd);
// ***************************************//
// Sign function //
// ***************************************//
// Bits Function
// 0 0 Areg
// 0 1 Positive // Forced on reset
// 1 0 notAreg
// 1 1 AregXORBreg
ME_OR2 orr (Reset, RomSignLength[`u_SignResultFromFunction0],
SignResCtl0);
ME_XOR2 xorabs (AregSign, BregSign, AregXORBreg);
ME_MUX4B msc0 (SignResCtl0, RomSignLength[`u_SignResultFromFunction1],
AregSign, gnd, notAregSign, AregXORBreg,
SignResult);
// ***************************************//
// Sign Registers //
// ***************************************//
ME_XOR2 xorop (SignOpA, NegateOprSign, SignedSignOpA);
ME_INV_A salc (notSignAFromB, SignAFromB);
ME_OR4 ggdf (RomSignLength[`u_SignAregFromResult], Reset,
SignAFromB, LoadOprs, PosAEn);
ME_NAND2 sae1 ( PosAEn, notAbortWB, notAregLoadEn_p);
//ME_OR2_B sae2 ( notAregLoadEn_p, PreventSwap, notSignAregLoadEn);
ME_MUX2B saop ( RomSignLength[`u_SignAregFromResult], BregSign, SignResult, JSign);
ME_NMUX2B saxp ( LoadOprs, JSign, SignedSignOpA, notSignAInput);
ME_MUX2B_B asmp ( notAregLoadEn_p, notSignAInput, notAregSign, notSignAInput_p );
ME_NMUX2B_B asm ( notPreventSwap, notAregSign, notSignAInput_p, U_AregSign );
ME_FD1_B asf ( Phi, U_AregSign, AregSign, notAregSign );
// Added a bit of tack to see the rounding mode earlier
ME_XNOR2_B u0_v1 ( U_RoundingMode0, notSignAInput_p, U_RM0_notSAI);
ME_XNOR2_B u0_v2 ( U_RoundingMode0, notAregSign, U_RM0_notSA);
ME_NMUX2B_B asmv ( PreventSwap, U_RM0_notSAI, U_RM0_notSA, U_CouldBeRI_0 );
ME_INV_A sblc ( notSignBFromA, SignBFromA);
ME_OR2 gbdf ( SignBFromA, LoadOprs, PosBEn);
ME_INV_A sbe2 ( PreventSwap, notPreventSwap);
ME_NAND3 sbe ( PosBEn, notAbortWB, notPreventSwap, notSignBregLoadEn);
ME_NMUX2B sbxp ( LoadOprs, AregSign, SignOpB, notSignBInput);
ME_NMUX2B bsm ( notSignBregLoadEn, notSignBInput, notBregSign, U_BregSign );
ME_FD1 bsf ( Phi, U_BregSign, BregSign, notBregSign );
// ***************************************//
// Exception and Condition Code //
// ***************************************//
ME_OR2 codie (Unimplemented, Rom_Unimplemented, FpExc_Unimp);
ME_NOR2 stg7 (Rom_StatusCCBit0, Rom_StatusCCBit1,
Equals);
ME_NOR2 stg8 (Rom_StatusCCBit0, BregSign, notNegative);
ME_NOR2 stg9 (Rom_StatusCCBit0, notBregSign, notPositive);
ME_NOR2 stgA (Equals, notPositive, ConditionCodes[1]);
ME_NOR2 stgB (Equals, notNegative, ConditionCodes[0]);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)tregloadctl.v 1.1 4/7/92
//
module TregLoadCtl (RomFracTFromRes, notAbortWB,
FracTregLoadEn);
input RomFracTFromRes, notAbortWB;
output FracTregLoadEn;
ME_AND2 ftlt (RomFracTFromRes, notAbortWB, FracTregLoadEn);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)ymuxctl.v 1.1 4/7/92
//
module YMuxCtl (RomYMuxCtl,
YFunc,
FracAregFPMSBP1,
notFracAregFPMSBP1,
FracBregSign,
DivMultiple,
AregLSBs,
StickyForSR1,
TregLSBs,
/* dhn--01/10/91 notFracYFromD1, notFracYFromD2, notFracYFromD3, */
notFracYFromD1A, notFracYFromD2A, notFracYFromD3A,
FracYLSBs);
input FracAregFPMSBP1, notFracAregFPMSBP1, FracBregSign;
input [`end_frac_ybus_field:`start_frac_ybus_field] RomYMuxCtl;
input [6:0] YFunc;
input [2:0] AregLSBs;
input StickyForSR1;
input [1:0] TregLSBs;
input [3:1] DivMultiple;
/* dhn--01/10/91 output notFracYFromD3, notFracYFromD2, notFracYFromD1; */
output notFracYFromD1A, notFracYFromD2A, notFracYFromD3A;
output [1:0] FracYLSBs;
ME_TIEOFF toff (vdd, gnd);
/* Function Coding on
Func1 Func0
0 0 ROM Ybus From ROM
0 1 ROM SQRT Ybus From ROM Note we dont do anything with the Ybus here
1 0 Round Ybus from Areg or AregSR1 dependant on FracAregFPMSBP1
1 1 Div Ybus From Div Multiple
*/
//YFunc[6] and RomYMuxCtl[`u_FracALUOpForDivOrSQRTStep] mean SQRT step
ME_AND3_B fs3 (YFunc[6], RomYMuxCtl[`u_FracALUOpForDivOrSQRTStep], FracBregSign, RomYFromSQRTBNeg);
/* *************************************************************
YMux Drivers
************************************************************* */
//ME_INV_A ifp (FracAregFPMSBP1, notFracAregFPMSBP1);
/*ME_MUX4B_B ym0 (RomYMuxCtl[`u_FracYbusFromFunc0], RomYMuxCtl[`u_FracYbusFromFunc1],
RomYMuxCtl[`u_FracYbusFromRomDest0],
RomYMuxCtl[`u_FracYbusFromRomDest0],
FracAregFPMSBP1,
DivMultiple[0], FracYFromD0);
ME_MUX4B_B ym1 (RomYMuxCtl[`u_FracYbusFromFunc0], RomYMuxCtl[`u_FracYbusFromFunc1],
RomYMuxCtl[`u_FracYbusFromRomDest1],
RomYMuxCtl[`u_FracYbusFromRomDest1],
notFracAregFPMSBP1,
DivMultiple[1], FracYFromD1);*/
/*ME_MUX4B_B ym0 (YFunc[0], YFunc[1],
RomYMuxCtl[`u_FracYbusFromRomDest0],
RomYMuxCtl[`u_FracYbusFromRomDest0],
FracAregFPMSBP1,
DivMultiple[0], FracYFromD0);
ME_MUX4B_B ym1 (YFunc[2], YFunc[3],
RomYMuxCtl[`u_FracYbusFromRomDest1],
RomYMuxCtl[`u_FracYbusFromRomDest1],
notFracAregFPMSBP1,
DivMultiple[1], FracYFromD1);*/
/*** dhn--01/10/91
ME_A222OI_B ym1 (YFunc[0],
RomYMuxCtl[`u_FracYbusFromAregSR1],
YFunc[1],
FracAregFPMSBP1,
YFunc[2],
DivMultiple[1],
notFracYFromD1);
ME_A222OI_B ym2 (YFunc[3],
RomYMuxCtl[`u_FracYbusFromAreg],
YFunc[4],
notFracAregFPMSBP1,
YFunc[5],
DivMultiple[2],
notFracYFromD2);
ME_A222OI_B ym3 (RomYMuxCtl[`u_FracYbusFromFunc0],
RomYMuxCtl[`u_FracYbusFromTreg],
RomYMuxCtl[`u_FracYbusFromFunc1],
gnd,
RomYMuxCtl[`u_FracYbusFromFunc2],
DivMultiple[3],
notFracYFromD3);
*** dhn--01/10/91 ***/
ME_A222OI_B ym4 (YFunc[0],
RomYMuxCtl[`u_FracYbusFromAregSR1],
YFunc[1],
FracAregFPMSBP1,
YFunc[2],
DivMultiple[1],
notFracYFromD1A);
ME_A222OI_B ym5 (YFunc[3],
RomYMuxCtl[`u_FracYbusFromAreg],
YFunc[4],
notFracAregFPMSBP1,
YFunc[5],
DivMultiple[2],
notFracYFromD2A);
ME_A222OI_B ym6 (RomYMuxCtl[`u_FracYbusFromFunc0],
RomYMuxCtl[`u_FracYbusFromTreg],
RomYMuxCtl[`u_FracYbusFromFunc1],
gnd,
RomYMuxCtl[`u_FracYbusFromFunc2],
DivMultiple[3],
notFracYFromD3A);
/* ****************************************************************************
Modify FracYbus LSBs for Negative SQRT step and Sticky
**************************************************************************** */
ME_INV_A ymlb1 (notFracYFromD1A, FracYFromD1); // Minimalist light load
ME_INV_A ymlb2 (notFracYFromD2A, FracYFromD2); // Minimalist light load
ME_INV_A ymlb3 (notFracYFromD3A, FracYFromD3); // Minimalist light load
/*ME_OR2 ymd0 (FracYFromD1, FracYFromD3, FracYFromD0C);
ME_OR2 ymd1 (FracYFromD2, FracYFromD3, FracYFromD1C);*/
// Do OR before MUX
wire [1:0] OR_AregLSBsSR1, OR_AregLSBs, OR_TregLSBs;
// Bit 0
ME_INVA i00 (RomYMuxCtl[`u_FracYbusOrSticky], notRomFracYbusOrSticky);
/*ME_OR2 i00 (StickyInForSR1, RomYMuxCtl[`u_FracYbusOrSticky], OR_AregLSBsSR1[0]);
ME_OR2 i01 (AregLSBs[0], RomYMuxCtl[`u_FracYbusOrSticky], OR_AregLSBs[0]);
ME_OR2 i02 (TregLSBs[0], RomYMuxCtl[`u_FracYbusOrSticky], OR_TregLSBs[0]);*/
// Bit 1
ME_INVA i10 (RomYFromSQRTBNeg, notRomYFromSQRTBNeg);
/*ME_OR2 i10 (AregLSBs[2], RomYFromSQRTBNeg, OR_AregLSBsSR1[1]);
ME_OR2 i11 (AregLSBs[1], RomYFromSQRTBNeg, OR_AregLSBs[1]);
ME_OR2 i12 (TregLSBs[1], RomYFromSQRTBNeg, OR_TregLSBs[1]);*/
// Use buffered inverse of mux controls
ME_NAND2 ymlsbs1 (FracYFromD1, StickyForSR1, t0);
ME_NAND2 ymlsbs2 (FracYFromD2, AregLSBs[0], t1);
ME_NAND2 ymlsbs3 (FracYFromD3, TregLSBs[0], t2);
ME_NAND4 ymlsbs4 (t0, t1, t2, notRomFracYbusOrSticky, FracYLSBs[0]);
ME_NAND2 ymlsbs5 (FracYFromD1, AregLSBs[2], t3);
ME_NAND2 ymlsbs6 (FracYFromD2, AregLSBs[1], t4);
ME_NAND2 ymlsbs7 (FracYFromD3, TregLSBs[1], t5);
ME_NAND4 ymlsbs8 (t3, t4, t5, notRomYFromSQRTBNeg, FracYLSBs[1]);
/*ME_MUX4B yb0 (FracYFromD0C, FracYFromD1C,
RomYMuxCtl[`u_FracYbusOrSticky],
OR_AregLSBsSR1[0],
OR_AregLSBs[0],
OR_TregLSBs[0],
FracYLSBs[0]);
ME_MUX4B yb1 (FracYFromD0C, FracYFromD1C,
RomYFromSQRTBNeg,
OR_AregLSBsSR1[1],
OR_AregLSBs[1],
OR_TregLSBs[1],
FracYLSBs[1]);*/
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)dp.v 1.1 4/7/92
//
module fp_exp ( ss_clock, SNnotDB, OprSNnotDB,
RS2_exp, RS1_exp,
FracAregForInt,
notSLFromNorm,
ShiftBy8,
ExpAregLoadEn, ExpAregLC0, ExpAregLC1,
ExpBregLoadEn, ExpBregLC0, ExpBregLC1,
ExpXCtl0, ExpXCtl1,
ExpYCtl0, ExpYCtl1,
Sub, CarryIn,
Constantb, Constantc, Constantd, Constante,
Constantf, Constantg, Constanth,
// output start here
AregMasterBufOut,
ExpResultBuf, notExpShiftResult,
ExpZero, ExpResult_12,
SLControl,
notAInfNaN, notAZeroDenorm,
notBInfNaN, notBZeroDenorm,
notUnderflow, notOverflow, notExpException,
ss_scan_mode, fp_exp_scan_in, fp_exp_scan_out);
input ss_clock, SNnotDB, OprSNnotDB ;
input [10:0] RS2_exp, RS1_exp ;
input [7:0] FracAregForInt;
input ExpAregLoadEn, ExpAregLC0, ExpAregLC1;
input ExpBregLoadEn, ExpBregLC0, ExpBregLC1;
input ExpXCtl0, ExpXCtl1 ;
input ExpYCtl0, ExpYCtl1 ;
input Sub, CarryIn;
input Constantb, Constantc, Constantd, Constante,
Constantf, Constantg, Constanth;
input [3:0] notSLFromNorm ;
input ShiftBy8;
input ss_scan_mode, fp_exp_scan_in;
output [3:0] SLControl ;
output [7:0] AregMasterBufOut;
output [10:0] ExpResultBuf ;
output [12:0] notExpShiftResult ;
output ExpZero;
output ExpResult_12;
output notAInfNaN, notAZeroDenorm;
output notBInfNaN, notBZeroDenorm;
output notUnderflow, notOverflow, notExpException;
output fp_exp_scan_out;
ME_TIEOFF toff (vdd, gnd);
assign fp_exp_scan_out = 1'bx ;
wire [12:0] int_ExpResultBuf ;
assign ExpResultBuf = int_ExpResultBuf[10:0] ;
wire [12:0] AregMaster, AregMasterBuf, BregMaster, BregMasterBuf,
ExpXbus, ExpYbus, ExpResult;
wire [3:0] ExpYbusS;
assign ExpResult_12 = ExpResult[12] ;
// extended internal format operands
wire [12:0] OprA, OprB ;
wire [10:0] ExpOpA, ExpOpB ;
// Operand select (single/double) muxes
ME_MUX_2B_11 opifaxe (OprSNnotDB,
RS2_exp[10:0],
{gnd, gnd, gnd, RS2_exp[10:3]},
ExpOpA[10:0]);
assign OprA = {gnd, gnd, ExpOpA};
ME_MUX_2B_11 opifbxe (OprSNnotDB,
RS1_exp[10:0],
{gnd, gnd, gnd, RS1_exp[10:3]},
ExpOpB[10:0]);
assign OprB = {gnd, gnd, ExpOpB};
NormCalLog nmcl (notSLFromNorm,
ShiftBy8,
ExpYCtl0, ExpYCtl1,
ExpYbus[3:0],
ExpYbusS[3:0],
SLControl);
//wire [7:0] AregMasterBufOut = AregMasterBuf[7:0];
con1 g0 (AregMasterBuf[0], AregMasterBufOut[0]);
con1 g1 (AregMasterBuf[1], AregMasterBufOut[1]);
con1 g2 (AregMasterBuf[2], AregMasterBufOut[2]);
con1 g3 (AregMasterBuf[3], AregMasterBufOut[3]);
con1 g4 (AregMasterBuf[4], AregMasterBufOut[4]);
con1 g5 (AregMasterBuf[5], AregMasterBufOut[5]);
con1 g6 (AregMasterBuf[6], AregMasterBufOut[6]);
con1 g7 (AregMasterBuf[7], AregMasterBufOut[7]);
ME_FREGA_S_4_13 Areg ( ss_clock,
ExpAregLoadEn, ExpAregLC0, ExpAregLC1,
OprA,
{gnd, gnd, gnd, gnd, gnd, FracAregForInt[7:0]}, // AIntVal
int_ExpResultBuf, BregMasterBuf,
AregMaster, AregMasterBuf);
Exception ae ( AregMasterBuf, SNnotDB, notAInfNaN, notAZeroDenorm);
ME_MUX_4B_13 Ymux (ExpYCtl0, ExpYCtl1,
{gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}, // Zero
{gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, vdd, gnd, gnd, gnd}, // Normaliser value of 8
AregMasterBuf,
{gnd, gnd, gnd, Constantb, Constantb, Constantb, Constantc,
Constantc, Constantd, Constante, Constantf, Constantg, Constanth}, // Constant
ExpYbus );
ME_FREGA_S_4_13 Breg (ss_clock,
ExpBregLoadEn, ExpBregLC0, ExpBregLC1,
OprB,
{int_ExpResultBuf[12], int_ExpResultBuf[12:1]}, // ExpResultSR1
int_ExpResultBuf, AregMasterBuf,
BregMaster, BregMasterBuf);
Exception be (BregMasterBuf, SNnotDB, notBInfNaN, notBZeroDenorm);
ME_MUX_4B_13 Xmux (ExpXCtl0, ExpXCtl1,
{gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}, // Zero
{gnd, gnd, gnd, Constantb, Constantb, Constantb, Constantc,
Constantc, Constantd, Constante, Constantf, Constantg, Constanth}, // Constant
AregMasterBuf, BregMasterBuf,
ExpXbus );
ME_ADD_13 add ( Sub, CarryIn, ExpXbus, {ExpYbus[12:4], ExpYbusS[3:0]}, ExpResult, int_ExpResultBuf, ExpZero);
// original Meiko code (changed 11/7/90 -- dhn):
// shiftsub adds ( BregMaster, AregMaster, notExpShiftResult);
//
//ME_ADD_13 adds ( 1'b1, 1'b0, AregMaster, BregMaster, notExpShiftResult,,);
// just use the subtractor, don't need the condition codes, etc.
ME_SUB_13 subtract13 ( 1'b1, 1'b0, AregMaster, BregMaster, notExpShiftResult );
ResultException re (ExpResult, SNnotDB, ExpZero, notUnderflow, notOverflow, notExpException);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)exception.v 1.1 4/7/92
//
module Exception (BM, SNnotDB, notBInfNaN, notBZeroDenorm);
input [12:0] BM;
input SNnotDB;
output notBInfNaN, notBZeroDenorm;
// Check the Master for InfNan or ZeroDenorm
// Inf or nan should also be set for any overflow, either single or
// double length, as this check is also used in rounding
ME_OR11 g10 (BM[10], BM[9], BM[8], BM[7], BM[6], BM[5],
BM[4], BM[3], BM[2], BM[1], BM[0], notBZeroDenorm );
// Force bits 10 to 8 high when single and AND them
ME_INVA g13 ( SNnotDB, DBnotSN );
ME_NAND3 g12 ( BM[10], BM[9], BM[8], n10 ) ;
ME_NAND2 g11 ( DBnotSN, n10, doublebits1 ) ;
ME_AND8 zxd ( BM[7], BM[6], BM[5], BM[4],
BM[3], BM[2], BM[1], BM[0], All1s7to0);
ME_OR3 zxe ( BM[10], BM[9], BM[8], Bit10Or8);
ME_NAND2 g23 ( SNnotDB, Bit10Or8, notSNGrossOv ) ;
ME_NAND2 g22 ( doublebits1, All1s7to0, notAll1s ) ;
ME_INV_A g21 ( BM[11], notBit11 ) ;
ME_AND3_B g20 ( notSNGrossOv, notAll1s, notBit11, notBInfNaN ) ;
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)normcallog.v 1.1 4/7/92
//
module NormCalLog (notSLFromNorm[3:0],
ShiftBy8,
ExpYCtl0, ExpYCtl1,
ExpYbus[3:0],
ExpYbusS[3:0],
SLControl);
input [3:0] notSLFromNorm;
input ShiftBy8;
input ExpYCtl0, ExpYCtl1;
input [3:0] ExpYbus;
output [3:0] ExpYbusS;
output [3:0]SLControl;
wire [3:0] notExpYbus;
wire [3:0] notSLControl ;
ME_INVA i0 (ExpYCtl1, notExpYCtl1);
ME_INVA i1 (ShiftBy8, notShiftBy8);
ME_NAND3 n0 (ExpYCtl0, notExpYCtl1, notShiftBy8, notUseFastNorm);
ME_INV_B i2 (ExpYbus[0], notExpYbus[0]);
ME_INV_B i3 (ExpYbus[1], notExpYbus[1]);
ME_INV_B i4 (ExpYbus[2], notExpYbus[2]);
ME_INV_B i5 (ExpYbus[3], notExpYbus[3]);
ME_NMUX2B_B i33 (notUseFastNorm, notSLFromNorm[3], notExpYbus[3], ExpYbusS[3]);
ME_NMUX2B_B i32 (notUseFastNorm, notSLFromNorm[2], notExpYbus[2], ExpYbusS[2]);
ME_NMUX2B_B i31 (notUseFastNorm, notSLFromNorm[1], notExpYbus[1], ExpYbusS[1]);
ME_NMUX2B_B i30 (notUseFastNorm, notSLFromNorm[0], notExpYbus[0], ExpYbusS[0]);
ME_INV_A i6 (ExpYbusS[0], notSLControl[0]);
ME_INV_A i7 (ExpYbusS[1], notSLControl[1]);
ME_INV_A i8 (ExpYbusS[2], notSLControl[2]);
ME_INV_A i9 (ExpYbusS[3], notSLControl[3]);
ME_INV_A ia (notSLControl[0], SLControl[0]);
ME_INV_A ib (notSLControl[1], SLControl[1]);
ME_INV_A ic (notSLControl[2], SLControl[2]);
ME_INV_A id (notSLControl[3], SLControl[3]);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)resultexception.v 1.1 4/7/92
//
module ResultException (Result, SNnotDB, ExpZero, notUnderflow, notOverflow, notExpException);
input [`ExpMSB:0] Result;
input ExpZero;
input SNnotDB;
output notUnderflow, notOverflow, notExpException;
ME_TIEOFF toff (vdd, );
ME_INV_B g30 ( Result[12], positive ) ;
ME_INV_A g31 ( SNnotDB, DBnotSN ) ;
// underflow condition is -ve or all zero.
// Note that exp must be subtracting for zero to work !
ME_NMUX2B zq1 (positive, vdd, ExpZero, notUnderflow );
// overflow condition is positive and all ones with LSB dont care.
// or positive with bit 11 set.
// n.b all ones applies only over required length.
// Force bits 10 to 8 high when single and AND them
ME_NAND3 g10 (Result[10], Result[9], Result[8], n10 ) ;
ME_NAND2 g11 (DBnotSN, n10, doublebits1 ) ;
ME_AND4 zzd (Result[7], Result[6], Result[5], Result[4], All1s7to4);
ME_AND4_B zze (positive, Result[3], Result[2], Result[1], PAll1s3to1);
ME_OR3_B zzf ( Result[10], Result[9], Result[8], Bit10Or8);
ME_NAND3_B g23 ( positive, SNnotDB, Bit10Or8, notSNGrossOv ) ;
ME_NAND3_B g22 ( doublebits1, All1s7to4, PAll1s3to1, notAll1s ) ;
ME_NAND2 g21 ( positive, Result[11], notBit11 ) ;
ME_AND3_B g20 ( notSNGrossOv, notAll1s, notBit11, notOverflow ) ;
ME_AND4_B g24 ( notUnderflow, notSNGrossOv, notAll1s, notBit11, notExpException ) ;
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)adderlsblog.v 1.1 4/7/92
//
module AdderLSBlog ( Rom_Sub,
Rom_DivStepSQRT,
notBregSign, Eqv,
notFracRNearest,
TrueIEEEAregLSB,
notSub, AdderCarryIn,
notFracZero, FracZero);
input Rom_Sub,
Rom_DivStepSQRT,
notBregSign, Eqv;
input notFracRNearest,
TrueIEEEAregLSB;
output notSub, AdderCarryIn,
notFracZero, FracZero;
ME_TIEOFF toff (vdd, gnd);
ME_NMUX2B_B g12 (Rom_DivStepSQRT, Rom_Sub, notBregSign, notSub);
ME_INV_A g13 (notSub, Sub);
ME_MUX2B g15 (notFracRNearest, TrueIEEEAregLSB, Sub, AdderCarryIn);
// Optimise
// ME_AND2 g14 (Eqv, Sub, notFracZero); // this is neccessary for no-zero on add
ME_NMUX2B g16 (notSub, Eqv, gnd, notFracZero); // this is neccessary for no-zero on add
ME_INVA g17 (notFracZero, FracZero);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)areginexactslice.v 1.1 4/7/92
//
module AregInexactSlice (AM, notAM31_3, notAM2_0);
input [31:0] AM;
output notAM31_3, notAM2_0;
wire [11:4] notAORed;
ME_NOR3 aig0 (AM[0], AM[1], AM[2], notAM2_0);
ME_NOR2 aig5 (AM[30], AM[31], notAORed[11]);
ME_NOR3 aig6 (AM[27], AM[28], AM[29], notAORed[10]);
ME_NOR4 ai54 (AM[25], AM[26], AM[23], AM[24], notAORed[9]);
ME_NOR4 ai44 (AM[21], AM[22], AM[19], AM[20], notAORed[8]);
ME_NOR4 ai34 (AM[17], AM[18], AM[15], AM[16], notAORed[7]);
ME_NOR4 ai24 (AM[13], AM[14], AM[11], AM[12], notAORed[6]);
ME_NOR4 ai14 (AM[9], AM[10], AM[7], AM[8], notAORed[5]);
ME_NOR4 ai04 (AM[5], AM[6], AM[3], AM[4], notAORed[4]);
ME_NAND4 ai27 (notAORed[8], notAORed[9], notAORed[10], notAORed[11], AM31_19);
ME_NAND4 ai17 (notAORed[4], notAORed[5], notAORed[6], notAORed[7], AM18_3);
ME_NOR2 aizz (AM31_19, AM18_3, notAM31_3);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)areglsblog.v 1.1 4/7/92
//
module AregLSBLog (AregSticky,
AregLSBSN,
AregLSBDB,
AregFPMSBP1,
SNnotDB,
TrueIEEEAregLSB,
StickyForSR1);
input [1:0] AregSticky; // Two LSBs of Areg
input [1:0] AregLSBSN; // Two LSBs of Areg for IEEE single length
input [1:0] AregLSBDB; // Two LSBs of Areg for IEEE double length
input AregFPMSBP1; // Fraction overflow bit (ie 4.0 < Areg =< 2.0)
input SNnotDB;
output TrueIEEEAregLSB;
output StickyForSR1;
ME_OR2 v1 (AregSticky[1], AregSticky[0], StickyForSR1);
ME_MUX4B asdf (SNnotDB, AregFPMSBP1,
AregLSBDB[0], AregLSBSN[0],
AregLSBDB[1], AregLSBSN[1],
TrueIEEEAregLSB);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)checkoverflow.v 1.1 4/7/92
//
module CheckOverflow (FracResult, notPossibleOv, SubResultNorm);
input [10:1] FracResult;
output notPossibleOv, SubResultNorm;
// PossibleOv = (AResult[8:1] == 8'hFF)
// Check that an overflow is not possible on rounding cycle
// This can only occur if a large number of ones occur in the
// unrounded result
ME_NAND8_B g10 (FracResult[8], FracResult[7], FracResult[6], FracResult[5], FracResult[4],
FracResult[3], FracResult[2], FracResult[1], notPossibleOv);
ME_OR3_B srgx (FracResult[10], FracResult[9], FracResult[8], SubResultNorm);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)csarray.v 1.1 4/7/92
//
/**********************/
/* Carry Save Array */
/**********************/
module CSArray (
// ctl inputs
Shift,
Pos,
Zero,
// inputs
SumIn,
CarryIn,
Breg,
// ctl output
SALSBs, SBLSBs, SCLSBs,
CALSB, CBLSB, CCLSB,
// outputs
SD,
CD[`FracMSB:2]);
input [3:0] Shift, Pos, Zero;
input [`FracMSB:3] CarryIn, SumIn;
input [`FracMSB:1] Breg;
output [2:1] SALSBs, SBLSBs, SCLSBs;
output CALSB, CBLSB, CCLSB;
output [`FracMSB:1] SD;
output [1+`FracMSB:2] CD;
wire [`FracMSB:1] SA, SB, SC; // For cs in line expansion
wire [1+`FracMSB:2] CA, CB, CC;
CS_STAGE_57 asdc ({SumIn[`FracMSB], SumIn[`FracMSB], SumIn[`FracMSB:3]},
{CarryIn[`FracMSB], CarryIn[`FracMSB], CarryIn[`FracMSB:3]},
Breg, Shift[0], Pos[0], Zero[0],
{SA[`FracMSB:3], SALSBs[2:1]}, {CA[1+`FracMSB:3], CALSB});
CS_STAGE_57 asdd ({SA[`FracMSB], SA[`FracMSB], SA[`FracMSB:3]},
{CA[`FracMSB], CA[`FracMSB], CA[`FracMSB:3]},
Breg, Shift[1], Pos[1], Zero[1],
{SB[`FracMSB:3], SBLSBs[2:1]}, {CB[1+`FracMSB:3], CBLSB});
CS_STAGE_57 asde ({SB[`FracMSB], SB[`FracMSB], SB[`FracMSB:3]},
{CB[`FracMSB], CB[`FracMSB], CB[`FracMSB:3]},
Breg, Shift[2], Pos[2], Zero[2],
{SC[`FracMSB:3], SCLSBs[2:1]}, {CC[1+`FracMSB:3], CCLSB});
CS_STAGE_57 asdf ({SC[`FracMSB], SC[`FracMSB], SC[`FracMSB:3]},
{CC[`FracMSB], CC[`FracMSB], CC[`FracMSB:3]},
Breg, Shift[3], Pos[3], Zero[3],
SD, CD);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)csregslice.v 1.1 4/7/92
//
module CSRegSlice (Phi,
InitialMulStep,
/* notInitialSumZero, */
InitialCarryBit,
SumCarryLoadEn,
SumOut, CarryOut,
BregIn,
SumIn, CarryIn);
input Phi;
input InitialMulStep,
/* notInitialSumZero, */
InitialCarryBit,
SumCarryLoadEn;
input [`FracMSB:0] SumOut, CarryOut;
input [`FracMSB:1] BregIn;
output [`FracMSB:0] SumIn, CarryIn;
wire [`FracMSB:0] SumReg, CarryReg, InitialSum;
ME_TIEOFF toff (vdd, gnd);
ME_FREGA_1_58 sr (Phi, SumCarryLoadEn, SumOut, SumReg);
ME_FREGA_1_58 cr (Phi, SumCarryLoadEn, CarryOut, CarryReg);
/* ME_NMUX_2B_58 iz (notInitialSumZero, */
ME_NMUX_2B_58 iz (InitialCarryBit,
{vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd,
vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd,
vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd,
vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd,
vdd, vdd}, // 58'h3FF_FFFF_FFFF_FFFF
{BregIn, vdd},
InitialSum);
ME_MUX_2B_58 si (InitialMulStep, SumReg, InitialSum, SumIn);
ME_MUX_2B_58 ci (InitialMulStep,
CarryReg,
{gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, // 56'h0
InitialCarryBit, gnd},
CarryIn);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)fdp.v 1.1 4/7/92
//
module fp_frac
(ss_clock,
FracAregLoadEn, FracAregLC,
FracBregLoadEn, FracBregLC,
FracCregLoadEn, FracCregLC,
FracTregLoadEn,
FracYbusLSBs,
InFromCregOr0, InForCreg, InForCregDB,
Constantb, Constantd, Constante, Constantf, Constantg, Constanth,
RS2_frac, RS1_frac,
SNnotDB, OprSNnotDB,
SRControl, SROneMore, SRToSticky,
SLControl,
LIB,
TopBitsIn,
notStickyInForSR, // For right
Shift, Pos, Zero, InitialMulStep,
/* notInitialSumZero, */
InitialCarryBit,
SumCarryLoadEn,
MulLenSel,
SumOut0, CarryOut0, CarryOut3,
LeftnotRight, FracALUOpSub, FracALUOpDiv,
notFracYFromD1, notFracYFromD2, notFracYFromD3,
/* notFracYFromD1A, notFracYFromD2A, notFracYFromD3A, */ //Copies
FracXFromB,
//ctl outputs
notSticky4, Sticky2, notSticky1, StickyExtra,
Creg_30_29, // CregSNBits = Creg[30:29]
Creg_56_55, // CregInSL2SQRT = Creg[56:55]
BregMaster_57, // FracBregSign
BregMaster_54, // BregFPMSBM1
notMultip,
notAM31_3, notAM2_0, // Inexact parts
StickyForSR1,
AregMaster_57_40, // AregMaster[57:40]
AregMaster_32, // AregMaster[32]
AregMaster_7_0, // AregMaster[7:0]
/* duplicate port--AregMasterFPMSBP1, */ // AregMasterBuf[56]
notAregMasterFPMSBP1,
Treg_1_0, // TregLSBs
SumInLSBs, CarryInLSBs,
SALSBs, SBLSBs, SCLSBs, // LSBs for cs array
CALSB , CBLSB , CCLSB ,
notFracZero, FracZero,
FracResult_57, // FracSign
SubResultNorm,
FracResult_56, // FracOverflow
FracResult_55_52, // StepRemBits
notPossibleOv,
FracResultBufout, // only bits [54:3] are used in result
ss_scan_mode, fp_frac_scan_in, fp_frac_scan_out);
input ss_clock;
input FracAregLoadEn;
input [2:0] FracAregLC;
input FracBregLoadEn;
input [2:0] FracBregLC;
input [1:0] FracYbusLSBs;
input FracCregLoadEn, FracCregLC,
FracTregLoadEn;
input [54:0] RS2_frac, RS1_frac;
input SNnotDB, OprSNnotDB;
input Constantb, Constantd, Constante, Constantf, Constantg, Constanth;
input [1:0] InFromCregOr0;
input [1:0] InForCreg,
InForCregDB;
input [3:0] SRControl, SLControl;
input [2:0] LIB;
input SROneMore, SRToSticky;
input [8:0] TopBitsIn;
input notStickyInForSR;
input [3:0] Shift, Pos, Zero;
input InitialMulStep,
/* notInitialSumZero, */
InitialCarryBit,
SumCarryLoadEn;
input LeftnotRight, FracALUOpSub, FracALUOpDiv;
input [4:0] MulLenSel;
input SumOut0, CarryOut0, CarryOut3;
input notFracYFromD1, notFracYFromD2, notFracYFromD3,
/* input notFracYFromD1A, notFracYFromD2A, notFracYFromD3A, */
FracXFromB;
input ss_scan_mode, fp_frac_scan_in;
output [3:0] notSticky4;
output [1:0] Sticky2;
output notSticky1;
output [1:0] StickyExtra;
output [8:0] notMultip;
output [1:0] Treg_1_0;
output [1:0] Creg_30_29;
output [1:0] Creg_56_55;
output StickyForSR1;
output [17:0] AregMaster_57_40;
output AregMaster_32;
output [ 7:0] AregMaster_7_0;
output notAM31_3, notAM2_0;
output BregMaster_54;
output BregMaster_57;
output notFracZero, FracZero;
output [3:0] FracResult_55_52;
output FracResult_57, FracResult_56;
output notAregMasterFPMSBP1;
output SubResultNorm;
output [54:3] FracResultBufout;
output [2:0] SumInLSBs,
CarryInLSBs;
output [1:0] SALSBs, SBLSBs, SCLSBs;
output CALSB , CBLSB , CCLSB ;
output notPossibleOv ;
output fp_frac_scan_out;
ME_TIEOFF toff (vdd, gnd);
// commented this out --
//assign fp_frac_scan_out = 1'bx ;
wire AregMasterFPMSBP1;
wire [57:0] AregMaster, AregMasterBuf;
assign AregMaster_57_40 = AregMaster[57:40] ;
assign AregMaster_32 = AregMaster[32] ;
assign AregMaster_7_0 = AregMaster[7:0] ;
wire [57:0] BregMaster;
assign BregMaster_54 = BregMaster[54] ;
assign BregMaster_57 = BregMaster[57] ;
wire [57:0] Creg;
assign Creg_30_29 = Creg[30:29] ;
assign Creg_56_55 = Creg[56:55] ;
wire [57:0] FracResult;
assign FracResult_55_52 = FracResult[55:52] ;
assign FracResult_57 = FracResult[57] ;
assign FracResult_56 = FracResult[56] ;
wire [57:0] FracResultBuf;
assign FracResultBufout = FracResultBuf[54:3] ;
wire [57:0] Treg;
assign Treg_1_0 = Treg[1:0];
// internal bus on fractions datapath
wire [57:1] SRResult;
wire [57:0] SLResult;
wire [57:0] SResult, BregMasterBuf, FracXbus;
wire [57:2] FracYbus;
wire [57-1:1] SD;
wire [57-1:2] CD;
// extended internal format operands
wire [57:0] OprA, OprB;
wire [51:0] FracOpA, FracOpB;
// note order of items is suggested order of functional units on datapath.
// Operand select (single/double) muxes
ME_MUX_2B_52 opifaxf (OprSNnotDB,
RS2_frac[51:0],
{RS2_frac[54:32],
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd},
FracOpA[51:0]);
assign OprA = {gnd, gnd, vdd, FracOpA, gnd, gnd, gnd};
ME_MUX_2B_52 opifbxf (OprSNnotDB,
RS1_frac[51:0],
{RS1_frac[54:32],
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd},
FracOpB[51:0]);
assign OprB = {gnd, gnd, vdd, FracOpB, gnd, gnd, gnd};
// Breg Input stuff
ME_FREGA_5_58 B (ss_clock,
FracBregLoadEn,
FracBregLC[0], FracBregLC[1], FracBregLC[2],
OprB, AregMasterBuf,
FracResultBuf,
{FracResultBuf[57-2:0], InFromCregOr0}, // FracResultSL2
{CD[57-1:2], CarryOut3, CarryOut0, gnd}, // MulResCarry For Breg
BregMaster,
BregMasterBuf,
notBregMSB);
MultiplierSlice mu (ss_clock,
InitialMulStep,
// dhn--01/10/91 notInitialSumZero, //
InitialCarryBit,
SumCarryLoadEn,
Shift, Pos, Zero,
SumOut0, CarryOut0, CarryOut3,
BregMasterBuf[57:1], SumInLSBs, CarryInLSBs,
SALSBs, SBLSBs, SCLSBs,
CALSB, CBLSB, CCLSB,
SD[57-1:1],
CD[57-1:2]);
ME_FREGA_2_58 C (ss_clock,
FracCregLoadEn, FracCregLC,
FracResultBuf,
{Creg[57-2:31],InForCreg, Creg[28:1], InForCregDB, gnd}, // CregSL2SQTDIV
Creg);
// ******** AREG *********************************
ME_INVA ifs (FracResult_57, notFracSign); // used to be in divlog
ME_FREGA_8_58 A (ss_clock,
FracAregLoadEn,
FracAregLC[0], FracAregLC[1], FracAregLC[2],
OprA,
Creg,
BregMasterBuf, // 2 Allow speedy swapping
SResult, // 3
FracResultBuf,
{FracResultBuf[56:0], gnd}, // FracResultSL1
{AregMasterBuf[56:2], notFracSign, gnd, gnd},
{SD[57-1:1], CarryOut0, SumOut0}, // MulResSum ForAreg
AregMaster,
AregMasterBuf,
AregMasterFPMSBP1,
notAregMasterFPMSBP1);
// logic on output of areg in datapath
AregInexactSlice ax (AregMasterBuf[31:0], notAM31_3, notAM2_0);
MulSelSlice snmultip ( MulLenSel, AregMaster[8:0], AregMaster[40:32], notMultip );
// *************** end of Areg ************************************ //
// Shifter logic
ShiftRight shr (AregMasterBuf, SRControl, SROneMore,
SRToSticky, TopBitsIn,
notSticky4, Sticky2, notSticky1, StickyExtra,
SRResult[57:1]);
ShiftLeft shl (AregMasterBuf, SLControl, LIB,
SLResult);
ME_NMUX_2B_58 Smux (LeftnotRight, {SRResult[57:1], notStickyInForSR}, SLResult,
SResult);
ME_FREGA_1_58 T (ss_clock, FracTregLoadEn, FracResultBuf, Treg);
// *************** end of Treg ************************************ //
/*ME_MUX_4B_56 Ymux (notFracYFromD0,
notFracYFromD1,
{gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}, // 56'h0
{AregMasterBuf[57], AregMasterBuf[57:3]}, // AregMasterSR1[57:2]
AregMasterBuf[57:2],
Treg[57:2],
FracYbus[57:2]);*/
ME_YmuxSlice Ymux (notFracYFromD1, notFracYFromD2, notFracYFromD3,
/* dhn--01/10/91 notFracYFromD1A, notFracYFromD2A, notFracYFromD3A, */
{AregMasterBuf[57], AregMasterBuf[57:3]}, // AregMasterSR1[57:2]
AregMasterBuf[57:2],
Treg[57:2],
FracYbus[57:2]);
// send bottom two bits of Y to control logic
// assign FracYbusBSLSBs = FracYbus[1:0]; // ignored taken from AregMaster[2:0] and Treg[1:0]
// insert two bits from control logic into the low end of Ybus here
// *************** end of Ymux ************************************ //
ME_MUX_2B_B_58 Xbus (FracXFromB,
{ gnd, gnd, Constantb,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
Constantd,
Constante, Constante, Constante, Constante,
Constante, Constante, Constante, Constante,
Constante, Constante, Constante, Constante,
Constante, Constante, Constante, Constante,
Constante, Constante, Constante, Constante,
Constante, Constante, Constante, Constante,
Constante, Constante, Constante, Constante,
Constantf,
Constantg, Constantg}, // FracXConstant
BregMasterBuf, FracXbus);
AregLSBLog alsb (AregMaster[1:0], // AregLSBs[1:0]
AregMaster[33:32], // AregLSBSN
AregMaster[4:3], // AregLSBDB
AregMaster[56], // AregFPMSBP1
SNnotDB,
TrueIEEEAregLSB,
StickyForSR1);
wire Eqv;
AdderLSBlog fals (FracALUOpSub,
FracALUOpDiv,
notBregMSB, // notFracBregSign
Eqv,
Constanth, // notFracRNearest
TrueIEEEAregLSB,
Sub, AdderCarryIn,
notFracZero, FracZero);
ME_ADD_58 adr (Sub, AdderCarryIn,
FracXbus,
{FracYbus, FracYbusLSBs},
FracResult, FracResultBuf, Eqv);
/* ***************************** */
/* Deal with special result bits */
/* ***************************** */
CheckOverflow ov (FracResult[55+1:55-8], notPossibleOv, SubResultNorm);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)mulselslice.v 1.1 4/7/92
//
module MulSelSlice (MulLenSel, MDB, MSN, Multip);
input [4:0] MulLenSel;
input [8:0] MDB, MSN;
output [8:0] Multip;
wire [1:0] BMulLenSel;
// MulLenSel is {SNnotDB, SNnotDB, SNnotDB}
// these are buffered singly to give maximum speed for
// the multiplier select
// Note : BMulLenSel is inverse
ME_NMUX2B_B s0 ( MulLenSel[0], MDB[0], MSN[0], Multip[0]);
ME_NMUX2B_B s1 ( MulLenSel[1], MDB[1], MSN[1], Multip[1]);
ME_NMUX2B_B s2 ( MulLenSel[2], MDB[2], MSN[2], Multip[2]);
ME_NMUX2B_B s3 ( MulLenSel[3], MDB[3], MSN[3], Multip[3]);
ME_NMUX2B_B s4 ( MulLenSel[3], MDB[4], MSN[4], Multip[4]);
ME_NMUX2B_B s5 ( MulLenSel[4], MDB[5], MSN[5], Multip[5]);
ME_NMUX2B_B s6 ( MulLenSel[3], MDB[6], MSN[6], Multip[6]);
ME_NMUX2B_B s7 ( MulLenSel[4], MDB[7], MSN[7], Multip[7]);
ME_NMUX2B_B s8 ( MulLenSel[4], MDB[8], MSN[8], Multip[8]);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)multiplierslice.v 1.1 4/7/92
//
module MultiplierSlice (Phi,
// ctl inputs
InitialMulStep,
// notInitialSumZero, /
InitialCarryBit,
SumCarryLoadEn,
Shift,
Pos,
Zero,
SumOut0,
CarryOut0,
CarryOut3,
// inputs
Breg,
// ctl outputs
SumIn[2:0],
CarryIn[2:0],
SALSBs, SBLSBs, SCLSBs,
CALSB, CBLSB, CCLSB,
// outputs //*************************
SD[56:1], // SumForAreg
CD[56:2]);
// SD['FracMSB-1:1], // SumForAreg
// CD['FracMSB-1:2]);
// Note that 'FracMSB=57
// this lines causes: Range of port in module definition and body are reversed
//**************************
input Phi;
input
// notInitialSumZero, /
InitialMulStep,
InitialCarryBit,
SumCarryLoadEn;
input [3:0] Shift,
Pos,
Zero;
input SumOut0,
CarryOut0,
CarryOut3;
input [`FracMSB:1] Breg;
output [`FracMSB:0] SumIn, CarryIn;
output [1:0] SALSBs, SBLSBs, SCLSBs;
output CALSB, CBLSB, CCLSB;
output [`FracMSB:1]SD; // original lines
output [`FracMSB:2]CD; // original lines
//output [`FracMSB:2]CD;
//output [`FracMSB:1]SD;
CSRegSlice csr (Phi,
InitialMulStep,
// notInitialSumZero, /
InitialCarryBit,
SumCarryLoadEn,
{SD[`FracMSB:1], SumOut0},
{CD[`FracMSB:2], CarryOut3, CarryOut0},
Breg [`FracMSB:1],
SumIn[`FracMSB:0],
CarryIn[`FracMSB:0]);
CSArray csa ( Shift,
Pos,
Zero,
SumIn[`FracMSB:3],
CarryIn[`FracMSB:3],
Breg [`FracMSB:1],
SALSBs, SBLSBs, SCLSBs,
CALSB, CBLSB, CCLSB,
SD[`FracMSB:1],
CD[`FracMSB:2]);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)shiftleft.v 1.1 4/7/92
//
module ShiftLeft (NI,
SLControl,
LIB,
SLResult);
input [`FracMSB:0] NI;
input [3:0] SLControl;
input [2:0] LIB; // shifted operand for int or frac
output [`FracMSB:0] SLResult;
wire [`FracMSB:0] N8, N4, N2, N1;
ME_TIEOFF toff (vdd, gnd);
ME_NMUX_2B_58 g23 (SLControl[3],
NI,
{LIB[2], LIB[1], LIB[0], NI[`FracMSB-11:0],
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd},
N8); // False
ME_NMUX_2B_58 g24 (SLControl[2],
N8,
{N8[`FracMSB-4:0], vdd, vdd, vdd, vdd}, N4);
ME_NMUX_2B_58 g25 (SLControl[1],
N4,
{N4[`FracMSB-2:0], gnd, gnd},
N2); // False
ME_NMUX_2B_58 g26 (SLControl[0], N2, {N2[`FracMSB-1:0], vdd}, N1); // true
ME_INV_A_58 g27 (N1, SLResult); // false
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)shiftright.v 1.1 4/7/92
//
module ShiftRight (Areg,
SRControl,
SROneMore,
SRToSticky,
TopBitsIn,
// outputs
S8_3_0,
S4_1_0,
S2_0,
S1_1_0,
notSRResult);
input [`FracMSB:0] Areg;
input [3:0] SRControl;
input SROneMore,
SRToSticky;
input [8:0] TopBitsIn;
output [3:0] S8_3_0;
output [1:0] S4_1_0;
output S2_0;
output [1:0] S1_1_0;
output [`FracMSB:1] notSRResult;
wire [`FracMSB:0] S8, S4, S2, S1;
wire [`FracMSB:0] SE;
assign S8_3_0 = S8[3:0] ;
assign S4_1_0 = S4[1:0] ;
assign S2_0 = S2[0] ;
assign S1_1_0 = S1[1:0] ;
ME_NMUX2B_B g87 (SRControl[3], // Buffer MSB seperately
Areg[`FracMSB],
TopBitsIn[8],
S8[`FracMSB]); // False
ME_NMUX_2B_57 g86 (SRControl[3],
Areg[`FracMSB-1:0],
{TopBitsIn[8], TopBitsIn[8:0], Areg[`FracMSB-3:8]},
S8[`FracMSB-1:0]); // False
ME_NMUX_2B_58 g21 (SRControl[2],
S8,
{S8[`FracMSB], S8[`FracMSB],S8[`FracMSB],S8[`FracMSB],
S8[`FracMSB:4]},
S4); // True
ME_NMUX_2B_58 g23 (SRControl[1],
S4,
{S4[`FracMSB], S4[`FracMSB],S4[`FracMSB:2]},
S2); // False
ME_NMUX_2B_58 g24 (SRControl[0],
S2,
{S2[`FracMSB], S2[`FracMSB:1]},
S1); // True
ME_NMUX_2B_58 g25 (SROneMore,
S1,
{S1[`FracMSB], S1[`FracMSB:1]},
SE); // False
ME_INV_B g50 (SRToSticky, notSRToSticky);
ME_INV_C g51 (notSRToSticky, BSRToSticky);
ME_OR2_B h01 (BSRToSticky, SE[01], notSRResult[01]);
ME_OR2_B h02 (BSRToSticky, SE[02], notSRResult[02]);
ME_OR2_B h03 (BSRToSticky, SE[03], notSRResult[03]);
ME_OR2_B h04 (BSRToSticky, SE[04], notSRResult[04]);
ME_OR2_B h05 (BSRToSticky, SE[05], notSRResult[05]);
ME_OR2_B h06 (BSRToSticky, SE[06], notSRResult[06]);
ME_OR2_B h07 (BSRToSticky, SE[07], notSRResult[07]);
ME_OR2_B h08 (BSRToSticky, SE[08], notSRResult[08]);
ME_OR2_B h09 (BSRToSticky, SE[09], notSRResult[09]);
ME_OR2_B h10 (BSRToSticky, SE[10], notSRResult[10]);
ME_OR2_B h11 (BSRToSticky, SE[11], notSRResult[11]);
ME_OR2_B h12 (BSRToSticky, SE[12], notSRResult[12]);
ME_OR2_B h13 (BSRToSticky, SE[13], notSRResult[13]);
ME_OR2_B h14 (BSRToSticky, SE[14], notSRResult[14]);
ME_OR2_B h15 (BSRToSticky, SE[15], notSRResult[15]);
ME_OR2_B h16 (BSRToSticky, SE[16], notSRResult[16]);
ME_OR2_B h17 (BSRToSticky, SE[17], notSRResult[17]);
ME_OR2_B h18 (BSRToSticky, SE[18], notSRResult[18]);
ME_OR2_B h19 (BSRToSticky, SE[19], notSRResult[19]);
ME_OR2_B h20 (BSRToSticky, SE[20], notSRResult[20]);
ME_OR2_B h21 (BSRToSticky, SE[21], notSRResult[21]);
ME_OR2_B h22 (BSRToSticky, SE[22], notSRResult[22]);
ME_OR2_B h23 (BSRToSticky, SE[23], notSRResult[23]);
ME_OR2_B h24 (BSRToSticky, SE[24], notSRResult[24]);
ME_OR2_B h25 (BSRToSticky, SE[25], notSRResult[25]);
ME_OR2_B h26 (BSRToSticky, SE[26], notSRResult[26]);
ME_OR2_B h27 (BSRToSticky, SE[27], notSRResult[27]);
ME_OR2_B h28 (BSRToSticky, SE[28], notSRResult[28]);
ME_OR2_B h29 (BSRToSticky, SE[29], notSRResult[29]);
ME_OR2_B h30 (BSRToSticky, SE[30], notSRResult[30]);
ME_OR2_B h31 (BSRToSticky, SE[31], notSRResult[31]);
ME_OR2_B h32 (BSRToSticky, SE[32], notSRResult[32]);
ME_OR2_B h33 (BSRToSticky, SE[33], notSRResult[33]);
ME_OR2_B h34 (BSRToSticky, SE[34], notSRResult[34]);
ME_OR2_B h35 (BSRToSticky, SE[35], notSRResult[35]);
ME_OR2_B h36 (BSRToSticky, SE[36], notSRResult[36]);
ME_OR2_B h37 (BSRToSticky, SE[37], notSRResult[37]);
ME_OR2_B h38 (BSRToSticky, SE[38], notSRResult[38]);
ME_OR2_B h39 (BSRToSticky, SE[39], notSRResult[39]);
ME_OR2_B h40 (BSRToSticky, SE[40], notSRResult[40]);
ME_OR2_B h41 (BSRToSticky, SE[41], notSRResult[41]);
ME_OR2_B h42 (BSRToSticky, SE[42], notSRResult[42]);
ME_OR2_B h43 (BSRToSticky, SE[43], notSRResult[43]);
ME_OR2_B h44 (BSRToSticky, SE[44], notSRResult[44]);
ME_OR2_B h45 (BSRToSticky, SE[45], notSRResult[45]);
ME_OR2_B h46 (BSRToSticky, SE[46], notSRResult[46]);
ME_OR2_B h47 (BSRToSticky, SE[47], notSRResult[47]);
ME_OR2_B h48 (BSRToSticky, SE[48], notSRResult[48]);
ME_OR2_B h49 (BSRToSticky, SE[49], notSRResult[49]);
ME_OR2_B h50 (BSRToSticky, SE[50], notSRResult[50]);
ME_OR2_B h51 (BSRToSticky, SE[51], notSRResult[51]);
ME_OR2_B h52 (BSRToSticky, SE[52], notSRResult[52]);
ME_OR2_B h53 (BSRToSticky, SE[53], notSRResult[53]);
ME_OR2_B h54 (BSRToSticky, SE[54], notSRResult[54]);
ME_OR2_B h55 (BSRToSticky, SE[55], notSRResult[55]);
ME_OR2_B h56 (BSRToSticky, SE[56], notSRResult[56]);
ME_OR2_B h57 (BSRToSticky, SE[57], notSRResult[57]);
endmodule
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)fp_rom.v
***
****************************************************************************
****************************************************************************/
// **************************************************************
// @(#)fp_rom.v 1.7 1/8/93
//
// High-level verilog model of the fpu 256x64 rom.
// **************************************************************
// simulates a clocked ROM with an internal address register
module fp_rom ( ss_clock, rom_adr, rom_dout,
rom_scan_out, rom_scan_in, ss_scan_mode);
input ss_clock ;
input rom_scan_in, ss_scan_mode ;
input [7:0] rom_adr ;
output rom_scan_out ;
output [63:0] rom_dout ;
wire [63:0] data ;
wire [7:0] reg_rom_adr ; // registered version of the address
Mflipflop_noop rmad7(reg_rom_adr[7], rom_adr[7], ss_clock);
Mflipflop_noop rmad6(reg_rom_adr[6], rom_adr[6], ss_clock);
Mflipflop_noop rmad5(reg_rom_adr[5], rom_adr[5], ss_clock);
Mflipflop_noop rmad4(reg_rom_adr[4], rom_adr[4], ss_clock);
Mflipflop_noop rmad3(reg_rom_adr[3], rom_adr[3], ss_clock);
Mflipflop_noop rmad2(reg_rom_adr[2], rom_adr[2], ss_clock);
Mflipflop_noop rmad1(reg_rom_adr[1], rom_adr[1], ss_clock);
Mflipflop_noop rmad0(reg_rom_adr[0], rom_adr[0], ss_clock);
RR256X64 ROM_256x64 (
.DO63(rom_dout[63]),
.DO62(rom_dout[62]),
.DO61(rom_dout[61]),
.DO60(rom_dout[60]),
.DO59(rom_dout[59]),
.DO58(rom_dout[58]),
.DO57(rom_dout[57]),
.DO56(rom_dout[56]),
.DO55(rom_dout[55]),
.DO54(rom_dout[54]),
.DO53(rom_dout[53]),
.DO52(rom_dout[52]),
.DO51(rom_dout[51]),
.DO50(rom_dout[50]),
.DO49(rom_dout[49]),
.DO48(rom_dout[48]),
.DO47(rom_dout[47]),
.DO46(rom_dout[46]),
.DO45(rom_dout[45]),
.DO44(rom_dout[44]),
.DO43(rom_dout[43]),
.DO42(rom_dout[42]),
.DO41(rom_dout[41]),
.DO40(rom_dout[40]),
.DO39(rom_dout[39]),
.DO38(rom_dout[38]),
.DO37(rom_dout[37]),
.DO36(rom_dout[36]),
.DO35(rom_dout[35]),
.DO34(rom_dout[34]),
.DO33(rom_dout[33]),
.DO32(rom_dout[32]),
.DO31(rom_dout[31]),
.DO30(rom_dout[30]),
.DO29(rom_dout[29]),
.DO28(rom_dout[28]),
.DO27(rom_dout[27]),
.DO26(rom_dout[26]),
.DO25(rom_dout[25]),
.DO24(rom_dout[24]),
.DO23(rom_dout[23]),
.DO22(rom_dout[22]),
.DO21(rom_dout[21]),
.DO20(rom_dout[20]),
.DO19(rom_dout[19]),
.DO18(rom_dout[18]),
.DO17(rom_dout[17]),
.DO16(rom_dout[16]),
.DO15(rom_dout[15]),
.DO14(rom_dout[14]),
.DO13(rom_dout[13]),
.DO12(rom_dout[12]),
.DO11(rom_dout[11]),
.DO10(rom_dout[10]),
.DO9(rom_dout[9]),
.DO8(rom_dout[8]),
.DO7(rom_dout[7]),
.DO6(rom_dout[6]),
.DO5(rom_dout[5]),
.DO4(rom_dout[4]),
.DO3(rom_dout[3]),
.DO2(rom_dout[2]),
.DO1(rom_dout[1]),
.DO0(rom_dout[0]),
.OE(1'b1),
.ADR7(reg_rom_adr[7]),
.ADR6(reg_rom_adr[6]),
.ADR5(reg_rom_adr[5]),
.ADR4(reg_rom_adr[4]),
.ADR3(reg_rom_adr[3]),
.ADR2(reg_rom_adr[2]),
.ADR1(reg_rom_adr[1]),
.ADR0(reg_rom_adr[0])
);
endmodule
module RR256X64 (
DO63,DO62,DO61,DO60,DO59,DO58,DO57,DO56,
DO55,DO54,DO53,DO52,DO51,DO50,DO49,DO48,
DO47,DO46,DO45,DO44,DO43,DO42,DO41,DO40,
DO39,DO38,DO37,DO36,DO35,DO34,DO33,DO32,
DO31,DO30,DO29,DO28,DO27,DO26,DO25,DO24,
DO23,DO22,DO21,DO20,DO19,DO18,DO17,DO16,
DO15,DO14,DO13,DO12,DO11,DO10,DO9,DO8,
DO7,DO6,DO5,DO4,DO3,DO2,DO1,DO0,
OE,
ADR7,ADR6,ADR5,ADR4,ADR3,ADR2,ADR1,ADR0);
input OE,
ADR7,ADR6,ADR5,ADR4,ADR3,ADR2,ADR1,ADR0;
output DO63,DO62,DO61,DO60,DO59,DO58,DO57,DO56,
DO55,DO54,DO53,DO52,DO51,DO50,DO49,DO48,
DO47,DO46,DO45,DO44,DO43,DO42,DO41,DO40,
DO39,DO38,DO37,DO36,DO35,DO34,DO33,DO32,
DO31,DO30,DO29,DO28,DO27,DO26,DO25,DO24,
DO23,DO22,DO21,DO20,DO19,DO18,DO17,DO16,
DO15,DO14,DO13,DO12,DO11,DO10,DO9,DO8,
DO7,DO6,DO5,DO4,DO3,DO2,DO1,DO0;
wire [7:0] reg_rom_adr = {
ADR7,ADR6,ADR5,ADR4,ADR3,ADR2,ADR1,ADR0 };
reg [63:0] data;
assign {
DO63,DO62,DO61,DO60,DO59,DO58,DO57,DO56,
DO55,DO54,DO53,DO52,DO51,DO50,DO49,DO48,
DO47,DO46,DO45,DO44,DO43,DO42,DO41,DO40,
DO39,DO38,DO37,DO36,DO35,DO34,DO33,DO32,
DO31,DO30,DO29,DO28,DO27,DO26,DO25,DO24,
DO23,DO22,DO21,DO20,DO19,DO18,DO17,DO16,
DO15,DO14,DO13,DO12,DO11,DO10,DO9,DO8,
DO7,DO6,DO5,DO4,DO3,DO2,DO1,DO0 } = data[63:0];
always @(reg_rom_adr) begin
case (reg_rom_adr)
8'd000: data = 64'h0000000000000000 ;
8'd001: data = 64'h00000011100085c4 ;
8'd002: data = 64'h00000041100085a4 ;
8'd003: data = 64'h0000000000000000 ;
8'd004: data = 64'h03103010c804f865 ;
8'd005: data = 64'h0020800113800000 ;
8'd006: data = 64'h00000000000085ac ;
8'd007: data = 64'h121200000000806c ;
8'd008: data = 64'h041440404800f865 ;
8'd009: data = 64'h0020800113800000 ;
8'd010: data = 64'h05145051c800f865 ;
8'd011: data = 64'h0020800113800000 ;
8'd012: data = 64'h000000100000860c ;
8'd013: data = 64'h121200512000807c ;
8'd014: data = 64'h000000100000860c ;
8'd015: data = 64'h12120000000081dc ;
8'd016: data = 64'h00000000000080a4 ;
8'd017: data = 64'h00000000000087dc ;
8'd018: data = 64'h0000004110000000 ;
8'd019: data = 64'h00000001e8001dac ;
8'd020: data = 64'h002080111000d57f ;
8'd021: data = 64'h0020800123800000 ;
8'd022: data = 64'h001430000000c9cd ;
8'd023: data = 64'h0010300188000000 ;
8'd024: data = 64'h0a14507968037040 ;
8'd025: data = 64'h0300001968200000 ;
8'd026: data = 64'h0a145079680371f0 ;
8'd027: data = 64'h0300000168200000 ;
8'd028: data = 64'h0a14507968037040 ;
8'd029: data = 64'h0300001968200000 ;
8'd030: data = 64'h0a145079680371f0 ;
8'd031: data = 64'h0300000168200000 ;
8'd032: data = 64'h0014000048000000 ;
8'd033: data = 64'h0a1430000000c1cc ;
8'd034: data = 64'h0a000000000069cc ;
8'd035: data = 64'h0200000000008254 ;
8'd036: data = 64'h0014010048000000 ;
8'd037: data = 64'h0c1850518000c2f4 ;
8'd038: data = 64'h0c1850000000c83c ;
8'd039: data = 64'h02000018000082fe ;
8'd040: data = 64'h0a14507968037040 ;
8'd041: data = 64'h0300001968200000 ;
8'd042: data = 64'h0a145079680371f0 ;
8'd043: data = 64'h0300000168200000 ;
8'd044: data = 64'h0a14507968037040 ;
8'd045: data = 64'h0300001968200000 ;
8'd046: data = 64'h0a145079680371f0 ;
8'd047: data = 64'h0300000168200000 ;
8'd048: data = 64'h8a1030000000842c ;
8'd049: data = 64'h80103380000080b4 ;
8'd050: data = 64'h801030780000842c ;
8'd051: data = 64'h82103390680080b4 ;
8'd052: data = 64'h801033800000866c ;
8'd053: data = 64'h8a103380000086c4 ;
8'd054: data = 64'h80103380000086c4 ;
8'd055: data = 64'h0a1433800000c90c ;
8'd056: data = 64'h001430000000c77e ;
8'd057: data = 64'h801030000000ea55 ;
8'd058: data = 64'h0014008188000000 ;
8'd059: data = 64'h1212005120008624 ;
8'd060: data = 64'h0000000000000001 ;
8'd061: data = 64'h0000000001000000 ;
8'd062: data = 64'h001450000000c737 ;
8'd063: data = 64'h0000000001000000 ;
8'd064: data = 64'h8a1030780000861c ;
8'd065: data = 64'h80103000000080b4 ;
8'd066: data = 64'h801030000000861c ;
8'd067: data = 64'h82103018000080b4 ;
8'd068: data = 64'h801030000000812c ;
8'd069: data = 64'h00000000000080b4 ;
8'd070: data = 64'h82103018000080b4 ;
8'd071: data = 64'h0a1430000000c90c ;
8'd072: data = 64'h001430000000c9cc ;
8'd073: data = 64'h000000000000977e ;
8'd074: data = 64'h04100017a0000000 ;
8'd075: data = 64'h0300029188180001 ;
8'd076: data = 64'h001400004b400000 ;
8'd077: data = 64'h5e10001140000000 ;
8'd078: data = 64'h5810501140000000 ;
8'd079: data = 64'h5e95501120008470 ;
8'd080: data = 64'h5e95500000000000 ;
8'd081: data = 64'h80103027c8003cfc ;
8'd082: data = 64'h10100047e00022a4 ;
8'd083: data = 64'h0514000000000000 ;
8'd084: data = 64'h0a000011a0008268 ;
8'd085: data = 64'h2018501140000000 ;
8'd086: data = 64'h5e10001140008470 ;
8'd087: data = 64'h5810500000000000 ;
8'd088: data = 64'h8300039160128350 ;
8'd089: data = 64'h03000017c8100000 ;
8'd090: data = 64'h0000028000000000 ;
8'd091: data = 64'h0000007800008244 ;
8'd092: data = 64'haa120391680283f0 ;
8'd093: data = 64'hca18401720000000 ;
8'd094: data = 64'h0c1850518000c605 ;
8'd095: data = 64'h0020800002800000 ;
8'd096: data = 64'h0014008048000000 ;
8'd097: data = 64'h80103027c8003cfc ;
8'd098: data = 64'h10100047e0002324 ;
8'd099: data = 64'h0514000000000000 ;
8'd100: data = 64'h0a000011a00082b0 ;
8'd101: data = 64'h2018501140000000 ;
8'd102: data = 64'h0300000000108448 ;
8'd103: data = 64'h0300000000100000 ;
8'd104: data = 64'h8300039160120c48 ;
8'd105: data = 64'h03000017c8100000 ;
8'd106: data = 64'h0300000000108330 ;
8'd107: data = 64'h0300000000100000 ;
8'd108: data = 64'haa120391680283f8 ;
8'd109: data = 64'hca18401720000000 ;
8'd110: data = 64'h001430000000c9cd ;
8'd111: data = 64'h0010300003800000 ;
8'd112: data = 64'h8a103380000083d4 ;
8'd113: data = 64'h8010338000008374 ;
8'd114: data = 64'h801033800000870c ;
8'd115: data = 64'h82103380000080b4 ;
8'd116: data = 64'h8a103078000086dc ;
8'd117: data = 64'h8010338000008374 ;
8'd118: data = 64'h82103380000080b4 ;
8'd119: data = 64'h0a1433800000c90c ;
8'd120: data = 64'h001430000000c254 ;
8'd121: data = 64'h00000000000081cc ;
8'd122: data = 64'h0c1850118000c6ee ;
8'd123: data = 64'h03000010c8040000 ;
8'd124: data = 64'haa12001168000bf8 ;
8'd125: data = 64'hca18401720000000 ;
8'd126: data = 64'h78c0400000000000 ;
8'd127: data = 64'h78c0404380000000 ;
8'd128: data = 64'h78c04041e800e400 ;
8'd129: data = 64'h78c0400000000000 ;
8'd130: data = 64'h01105011c800c454 ;
8'd131: data = 64'h041500004800f865 ;
8'd132: data = 64'h0020800113800000 ;
8'd133: data = 64'h0c1853918000c37e ;
8'd134: data = 64'h03000010c8040000 ;
8'd135: data = 64'h8300001160108b4c ;
8'd136: data = 64'h03000017c8100000 ;
8'd137: data = 64'h0700000000000000 ;
8'd138: data = 64'h041440104800f865 ;
8'd139: data = 64'h0020800113800000 ;
8'd140: data = 64'h0b0000158018ae4c ;
8'd141: data = 64'h0414101720008654 ;
8'd142: data = 64'h5e95500000002a54 ;
8'd143: data = 64'h5e955011c800e470 ;
8'd144: data = 64'hde95500000000000 ;
8'd145: data = 64'h101800106800dc9c ;
8'd146: data = 64'h1013400000000000 ;
8'd147: data = 64'h03105000c804c454 ;
8'd148: data = 64'h041500004800f865 ;
8'd149: data = 64'h0020800113800000 ;
8'd150: data = 64'h001850000000ccc4 ;
8'd151: data = 64'h001430000000c736 ;
8'd152: data = 64'h0a145079680171f0 ;
8'd153: data = 64'h0300000168200000 ;
8'd154: data = 64'h88103877c8009d5c ;
8'd155: data = 64'h00000000000087b4 ;
8'd156: data = 64'h8810387728003f6c ;
8'd157: data = 64'h041400172800f865 ;
8'd158: data = 64'h0020800113800000 ;
8'd159: data = 64'h080000604800e2d4 ;
8'd160: data = 64'h041850118000c37e ;
8'd161: data = 64'h03000010c8040000 ;
8'd162: data = 64'h00000027c8008a94 ;
8'd163: data = 64'h0000000000008314 ;
8'd164: data = 64'h001850000000c724 ;
8'd165: data = 64'h001430000000c54c ;
8'd166: data = 64'h0000000000003546 ;
8'd167: data = 64'h0000000000006d4d ;
8'd168: data = 64'h0000000001c00000 ;
8'd169: data = 64'h020000000000858c ;
8'd170: data = 64'h88103077c8001fb4 ;
8'd171: data = 64'h00000015c8009f9c ;
8'd172: data = 64'h0000004000000000 ;
8'd173: data = 64'h0300000168202e34 ;
8'd174: data = 64'h03000408c81c0001 ;
8'd175: data = 64'h002080004b800000 ;
8'd176: data = 64'h001430600000c1fe ;
8'd177: data = 64'h0000000000003546 ;
8'd178: data = 64'h000000000000ed47 ;
8'd179: data = 64'h0000000001800000 ;
8'd180: data = 64'h00000001e800985e ;
8'd181: data = 64'h0000004180000000 ;
8'd182: data = 64'h0300000168200000 ;
8'd183: data = 64'h04142000000087cc ;
8'd184: data = 64'h000000000000bd7e ;
8'd185: data = 64'h0411101188000000 ;
8'd186: data = 64'h00208011c800d73f ;
8'd187: data = 64'h002080004a000000 ;
8'd188: data = 64'h0c1850158000c5fe ;
8'd189: data = 64'h03000010c8040000 ;
8'd190: data = 64'h0200000048009fad ;
8'd191: data = 64'h0014000003800000 ;
8'd192: data = 64'h041030100000977e ;
8'd193: data = 64'h000002800000b77e ;
8'd194: data = 64'h000003000000877e ;
8'd195: data = 64'h101850418000c77e ;
8'd196: data = 64'h0a14507968017040 ;
8'd197: data = 64'h0300001968200000 ;
8'd198: data = 64'h04141400000080a0 ;
8'd199: data = 64'h03000008c81c0000 ;
8'd200: data = 64'h0b00081580182c6c ;
8'd201: data = 64'h001410172000c37e ;
8'd202: data = 64'h03000010c8040000 ;
8'd203: data = 64'h001400004800f865 ;
8'd204: data = 64'h0020800113800000 ;
8'd205: data = 64'h021430000000c37e ;
8'd206: data = 64'h001430100000c37e ;
8'd207: data = 64'h04110000000085bc ;
8'd208: data = 64'h00000000000081fe ;
8'd209: data = 64'h8010300000008584 ;
8'd210: data = 64'h00000060000081fe ;
8'd211: data = 64'h8210301800008584 ;
8'd212: data = 64'h80103000000084b4 ;
8'd213: data = 64'h8010300000008584 ;
8'd214: data = 64'h8210301800008584 ;
8'd215: data = 64'h8010300000008524 ;
8'd216: data = 64'h0a1850000000c9cc ;
8'd217: data = 64'h001850000000c8be ;
8'd218: data = 64'h0000000000008254 ;
8'd219: data = 64'h0c1853800000cef4 ;
8'd220: data = 64'h0c1850000000c255 ;
8'd221: data = 64'h001030018b000000 ;
8'd222: data = 64'h0c1850518000c37e ;
8'd223: data = 64'h03000010c8040000 ;
8'd224: data = 64'h0a000070680083dc ;
8'd225: data = 64'h0c1850718000c37e ;
8'd226: data = 64'h03000010c8040000 ;
8'd227: data = 64'h0a000070680083e4 ;
8'd228: data = 64'h001430000000cd8c ;
8'd229: data = 64'h00000000000091ff ;
8'd230: data = 64'h0000000000000000 ;
8'd231: data = 64'h0020800122000000 ;
8'd232: data = 64'h00000877c8003f55 ;
8'd233: data = 64'h0014000723800000 ;
8'd234: data = 64'h881030786800e0b4 ;
8'd235: data = 64'h04185011e000c37e ;
8'd236: data = 64'h0000001720008654 ;
8'd237: data = 64'h801030106800e784 ;
8'd238: data = 64'h001850100000ce7d ;
8'd239: data = 64'h001400004b800000 ;
8'd240: data = 64'h001430000000c0be ;
8'd241: data = 64'h04100017a000ea54 ;
8'd242: data = 64'h030002918818877e ;
8'd243: data = 64'h03000468c81cafec ;
8'd244: data = 64'h80103000680065e4 ;
8'd245: data = 64'h0410301000008266 ;
8'd246: data = 64'h000002806800e7c4 ;
8'd247: data = 64'h001850100000c37e ;
8'd248: data = 64'h041100100000877e ;
8'd249: data = 64'h002080000000d2ff ;
8'd250: data = 64'h0020800182800000 ;
8'd251: data = 64'h002080111000d5c4 ;
8'd252: data = 64'h00000011200085c4 ;
8'd253: data = 64'h0410001188000001 ;
8'd254: data = 64'h001110004bc00000 ;
8'd255: data = 64'h0000000000000000 ;
endcase
end
endmodule
|
/*
* usb_ulpi.v Drive the ULPI interface of the Microchip USB3300
*
* Drives the USB2 physical interface
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017 [email protected]
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
* Registers
* +===+=========================+=========================+
* | # | Read | Write |
* +===+=========================+=========================+
* | 0 | Get Register Data | Set Register Data |
* | 1 | Get Register ID | Set Register ID |
* | 8 | Read Buffered Data | Write Buffered Data |
* | C | Read RXD CMD | Set PID for write |
* | F | Last operation status | Module Control |
* | | B0 - ACK(1) / NAK(0) | B0 - Reg Write |
* | | B1 - | B1 - Reg Read |
* | | B2 - | B2 - |
* | | B3 - | B3 - |
* | | B4 - Operation Done | B4 - Transmit |
* | | B5 - | B5 - |
* | | B6 - | B6 - |
* | | B7 - Data In Buffer | B7 - Clear Buffer |
* +===+=========================+=========================+
*
*/
`timescale 1ns/1ns
`default_nettype none
module usb_ulpi (
// Bus interface
input wire clk_i,
input wire reset_i,
input wire [3:0] A,
input wire [7:0] D_i,
output reg [7:0] D_o,
input wire wr_i,
input wire rd_i,
// Phy Interface
input usb_clkin,
input usb_dir,
input usb_nxt,
output reg usb_stp = 1'b1,
output reg usb_reset = 1'b0,
input [7:0] usb_data_i,
output reg [7:0] usb_data_o = 8'd0,
output wire usb_data_oe
);
parameter STATE_INIT = 4'd0, STATE_IDLE = 4'd1, STATE_WAITDIRL = 4'd2, STATE_SETD = 4'd3, STATE_WAITNXT = 4'd4,
STATE_WAITDIRH = 4'd5, STATE_WAITREAD = 4'd6, STATE_SETSTP = 4'd7, STATE_RECEIVE = 4'd8;
parameter OP_IDLE = 2'd0, OP_REGREAD = 2'd1, OP_REGWRITE = 2'd2, OP_XVR = 2'd3;
// Wire definitions ===========================================================================
wire regread_sig, regwrite_sig, transmit_sig;
wire [7:0] status_register;
wire [4:0] crc5_out;
wire [15:0] crc16_out;
wire crc_en;
// Registers ==================================================================================
// Bus Domain Registers
reg [7:0] bus_reg_data, bus_reg_in;
reg [5:0] bus_reg_id;
reg bus_domain_regread = 1'b0;
reg bus_domain_regwrite = 1'b0;
reg bus_domain_transmit = 1'b0;
reg [3:0] bus_pid = 1'b0;
reg [5:0] tx_buffer_write_ptr = 6'd0;
reg [1:0] track_crc = 2'd0;
// Synchronisers for cross-domain signals
reg [3:0] sync_reset = 4'd0;
reg [2:0] phy_regread = 3'd0;
reg [2:0] phy_regwrite = 3'd0;
reg [2:0] phy_transmit = 3'd0;
reg [2:0] bus_regread = 3'd0;
reg [2:0] bus_regwrite = 3'd0;
reg [2:0] bus_transmit = 3'd0;
reg [2:0] sync_active = 3'd0;
reg [7:0] rx_buffer[0:63]; // Cross domain data buffer
reg [7:0] tx_buffer[0:63]; // Cross domain data buffer
reg [2:0] data_in_buffer = 3'd0;
// USB PHY Domain Registers
reg [3:0] state = STATE_INIT;
reg [5:0] state_cntr = 6'd1;
reg phy_domain_regread = 1'b0;
reg phy_domain_regwrite = 1'b0;
reg phy_domain_transmit = 1'b0;
reg [5:0] phy_reg_id = 6'd0;
reg [7:0] phy_reg_data = 8'd0;
reg delayed_oe = 1'b0;
reg [1:0] phy_operation = 2'd0;
reg [7:0] rxd_cmd = 8'd0;
reg [5:0] rx_buffer_write_ptr = 6'd0;
reg [5:0] tx_buffer_read_ptr = 6'd0;
reg [3:0] phy_pid = 4'd0;
// Assignments ================================================================================
assign regread_sig = (bus_domain_regread != phy_domain_regread);
assign regwrite_sig = (bus_domain_regwrite != phy_domain_regwrite);
assign transmit_sig = (bus_domain_transmit != phy_domain_transmit);
assign usb_data_oe = ~(delayed_oe | usb_dir);
assign status_register = {data_in_buffer[2], 2'd0, ~sync_active[2], 4'd0};
assign crc_en = (track_crc == 2'b01);
// Module connections =========================================================================
crc5 crc5_instance (D_i,crc_en,crc5_out,reset_i,clk_i);
crc16 crc16_instance (D_i,crc_en,crc16_out,reset_i,clk_i);
// Simulation branches and control ============================================================
// Other logic ================================================================================
// Synchronizer chains PHY
always @(posedge usb_clkin) sync_reset <= {sync_reset[2:0],reset_i}; // Bus Reset to PHY
always @(posedge usb_clkin) phy_regread <= {phy_regread[1:0],regread_sig};
always @(posedge usb_clkin) phy_regwrite <= {phy_regwrite[1:0],regwrite_sig};
always @(posedge usb_clkin) phy_transmit <= {phy_transmit[1:0],transmit_sig};
// Synchronizer chains BUS
always @(posedge clk_i) bus_regread <= {bus_regread[1:0],regread_sig};
always @(posedge clk_i) bus_regwrite <= {bus_regwrite[1:0],regwrite_sig};
always @(posedge clk_i) bus_transmit <= {bus_transmit[1:0],transmit_sig};
always @(posedge clk_i) sync_active <= {sync_active[1:0],(phy_operation[1] | phy_operation[0])};
always @(posedge clk_i) data_in_buffer <= {data_in_buffer[1:0], rx_buffer_write_ptr != 6'd0 }; // TODO: This isn't sufficient synchronising
// Track signal edges
always @(posedge clk_i) track_crc <= {track_crc[0],wr_i};
// Bus domain logic ===========================================================================
always @(posedge clk_i or posedge reset_i)
begin
if( reset_i )
begin
bus_reg_data <= 8'd0;
bus_reg_id <= 6'd0;
bus_reg_in <= 8'd0;
bus_domain_regread <= 1'b0;
bus_domain_regwrite <= 1'b0;
tx_buffer_write_ptr <= 6'b0;
end
else case(A)
4'h0 : begin
if( rd_i ) D_o <= phy_reg_data;
else
if( wr_i ) bus_reg_data <= D_i;
end
4'h1 : begin
if( rd_i ) D_o <= {2'd0, bus_reg_id};
else
if( wr_i ) bus_reg_id <= D_i[5:0];
end
4'h8 : begin
if( rd_i ) ;
else
if( wr_i ) begin
tx_buffer[tx_buffer_write_ptr] <= D_i;
tx_buffer_write_ptr <= tx_buffer_write_ptr + 1'b1;
end
end
4'hc : begin
// USB domain register rxd_cmd doesn't need synchronizer as status should be checked before reading
if( rd_i ) D_o <= rxd_cmd;
else if( wr_i ) bus_pid <= D_i[3:0];
end
// Control
4'hf : begin
if( rd_i ) D_o <= status_register;
else
if( wr_i ) begin
if( D_i[1] ) // Reg read
begin
if( ~bus_regread[2] ) bus_domain_regread <= ~bus_domain_regread;
end
else
if( D_i[0] ) // Reg write
begin
if( ~bus_regwrite[2] ) bus_domain_regwrite <= ~bus_domain_regwrite;
end
else
if( D_i[7] ) // Clear buffer
begin
tx_buffer_write_ptr <= 6'd0;
end
else
if( D_i[4] ) // Begin transmit
begin
if( ~bus_transmit[2] ) bus_domain_transmit <= ~bus_domain_transmit;
end
end
end
default: D_o <= 8'hff;
endcase
end
// USB domain logic ===========================================================================
// Set the OE
always @(posedge usb_clkin) delayed_oe <= usb_dir;
// USB State Machine
always @(posedge usb_clkin or posedge sync_reset[3])
begin
if( sync_reset[3] )
begin
state <= STATE_INIT;
state_cntr <= 6'd1;
end
else
begin
case( state )
STATE_INIT:
begin
usb_reset = 1'b1;
usb_stp <= 1'b1;
usb_data_o <= 8'd0;
if( state_cntr != 6'd0 ) state_cntr <= state_cntr + 1'b1;
else state <= STATE_IDLE;
end
STATE_IDLE:
begin
usb_reset <= 1'b0;
usb_data_o <= 8'd0;
usb_stp <= 1'b0;
// Incoming read
if( usb_dir ) begin
phy_operation <= OP_XVR;
rx_buffer_write_ptr <= 6'd0;
state <= STATE_RECEIVE;
end else
// Read register
if( phy_regread[2] ) begin
phy_operation <= OP_REGREAD;
// Capture command params
phy_reg_id <= bus_reg_id;
phy_domain_regread <= ~phy_domain_regread;
if( usb_dir ) state <= STATE_WAITDIRL;
else state <= STATE_SETD;
end else // Write register
if( phy_regwrite[2] ) begin
phy_operation <= OP_REGWRITE;
// Capture command params
phy_reg_id <= bus_reg_id;
phy_reg_data <= bus_reg_data;
phy_domain_regwrite <= ~phy_domain_regwrite;
if( usb_dir ) state <= STATE_WAITDIRL;
else state <= STATE_SETD;
end else // Transmit
if( phy_transmit[2] ) begin
phy_operation <= OP_XVR;
// Capture command params
phy_pid <= bus_pid;
tx_buffer_read_ptr <= 6'd0;
phy_domain_transmit <= ~phy_domain_transmit;
if( usb_dir ) state <= STATE_WAITDIRL;
else state <= STATE_SETD;
end else phy_operation = OP_IDLE;
end
STATE_WAITDIRL:
begin
if( ~usb_dir ) state <= STATE_SETD;
end
STATE_SETD:
begin
case( phy_operation )
OP_REGREAD:
usb_data_o <= {2'b11, phy_reg_id};
OP_REGWRITE:
usb_data_o <= {2'b10, phy_reg_id};
OP_XVR:
usb_data_o <= {4'b0100, phy_pid};
endcase
state <= STATE_WAITNXT;
end
STATE_WAITNXT:
begin
if( usb_nxt ) begin
usb_data_o <= 8'd0; // Safety - set to NOP
case( phy_operation )
OP_REGREAD: state <= STATE_WAITDIRH;
OP_REGWRITE: begin
usb_data_o <= phy_reg_data;
state <= STATE_SETSTP;
end
OP_XVR: begin
usb_data_o <= tx_buffer[tx_buffer_read_ptr];
tx_buffer_read_ptr <= tx_buffer_read_ptr + 1'b1;
// Set STP if everything delivered
if( tx_buffer_read_ptr + 1'b1 == tx_buffer_write_ptr ) state <= STATE_SETSTP;
end
default: state <= STATE_INIT;
endcase
end
end
STATE_WAITDIRH:
if( usb_dir ) begin
state <= STATE_WAITREAD;
end
STATE_WAITREAD:
begin
phy_reg_data <= usb_data_i;
state <= STATE_IDLE;
end
STATE_SETSTP:
begin
usb_data_o <= 8'd0;
usb_stp <= 1'b1;
state <= STATE_IDLE;
end
STATE_RECEIVE:
begin
if( ~usb_dir ) begin // TODO: Set signals
state <= STATE_IDLE;
end else begin
if( ~usb_nxt )
rxd_cmd <= usb_data_i;
else begin
rx_buffer[rx_buffer_write_ptr] <= usb_data_i;
rx_buffer_write_ptr <= rx_buffer_write_ptr + 1'd1;
end
end
end
default:
state <= STATE_INIT;
endcase
end
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nco_sine_lut_V_rom (
addr0, ce0, q0, clk);
parameter DWIDTH = 16;
parameter AWIDTH = 12;
parameter MEM_SIZE = 4096;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./nco_sine_lut_V_rom.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module nco_sine_lut_V(
reset,
clk,
address0,
ce0,
q0);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
nco_sine_lut_V_rom nco_sine_lut_V_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DIODE_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DIODE_PP_BLACKBOX_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DIODE_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
module fifo_test();
parameter IN_WIDTH = 32;
parameter OUT_WIDTH = 4;
reg reset;
reg [IN_WIDTH-1:0] data_in;
reg data_in_clock;
reg data_in_enable;
wire [OUT_WIDTH-1:0] data_out;
reg data_out_clock;
reg data_out_enable;
reg [OUT_WIDTH-1:0] tempdata;
integer i;
fifo #(
.DATA_IN_WIDTH (IN_WIDTH),
.DATA_OUT_WIDTH (OUT_WIDTH),
.FIFO_DEPTH (12)
)
ff (
.reset(reset),
// IN PORT
.data_in(data_in),
.data_in_clock(data_in_clock),
.data_in_enable(data_in_enable),
// OUT PORT
.data_out(data_out),
.data_out_clock(data_out_clock),
.data_out_enable(data_out_enable)
);
initial
begin
reset = 1;
data_in = 0;
data_in_clock = 0;
data_in_enable = 0;
data_out_clock = 0;
data_out_enable = 0;
tempdata = 0;
#15 reset = 0;
if (OUT_WIDTH > IN_WIDTH)
begin
for ( i = 0; i < (OUT_WIDTH/IN_WIDTH); i = i + 1)
begin
push(i);
end
pop(tempdata);
end
else
begin
push(1);
for ( i = 0; i < (IN_WIDTH/OUT_WIDTH); i = i + 1)
begin
pop(tempdata);
end
end
$finish;
end
always
#5 data_in_clock = ~data_in_clock;
always
#40 data_out_clock = ~data_out_clock;
task push;
input[IN_WIDTH-1:0] data;
begin
data_in = data;
data_in_enable = 1;
@(posedge data_in_clock);
#1 data_in_enable = 0;
$display("Pushed %x",data );
end
endtask
task pop;
output [OUT_WIDTH-1:0] data;
begin
data_out_enable = 1;
@(posedge data_out_clock);
#1 data_out_enable = 0;
data = data_out;
$display("Popped %x", data);
end
endtask
endmodule
|
(** * Imp_J: 単純な命令型プログラム *)
(* $Date: 2011-06-22 14:56:13 -0400 (Wed, 22 Jun 2011) $ *)
(* In this chapter, we begin a new direction that we'll
continue for the rest of the course: up to now we've been mostly
studying Coq itself, but from now on we'll mostly be using Coq to
formalize other things.
...
This chapter looks at how to define the _syntax_ and _semantics_
of Imp; the chapters that follow develop a theory of _program
equivalence_ and introduce _Hoare Logic_, the best known logic for
reasoning about imperative programs. *)
(** この章では、コースの残りに続く新しい方向へ進み始めます。
ここまではもっぱらCoq自身について学習してきましたが、ここからは、
主として別のものを形式化するためにCoqを使います。
はじめの例は、Imp と呼ばれる単純な命令型プログラミング言語です。
下の例は、おなじみの数学的関数を Imp で書いたものです。
[[
Z ::= X;
Y ::= 1;
WHILE not (Z = 0) DO
Y ::= Y * Z;
Z ::= Z - 1
END
]]
この章ではImpの構文(_syntax_)と意味(_semantics_)をどのように定義するかを見ます。
続く章では、プログラムの同値性(_program equivalence_)の理論を展開し、
命令型プログラムについての推論のための論理として一番知られているホーア論理
(_Hoare Logic_)を紹介します。 *)
(* ####################################################### *)
(* *** Sflib *)
(** *** Sflib *)
(* A minor technical point: Instead of asking Coq to import our
earlier definitions from [Logic.v], we import a small library
called [Sflib.v], containing just a few definitions and theorems
from earlier chapters that we'll actually use in the rest of the
course. You won't notice much difference, since most of what's
missing from Sflib has identical definitions in the Coq standard
library. The main reason for doing this is to tidy the global Coq
environment so that, for example, it is easier to search for
relevant theorems. *)
(** マイナーな技術的ポイント: ここまでの定義を[Logic_J.v]からインポートする代わりに、
[Sflib_J.v]という小さなライブラリをインポートします。
このライブラリは、前の章の定義や定理のうち、残りの章で実際に使うものだけを集めたものです。
読者はそれほど違うものとは感じないでしょう。というのは、
Sflib で抜けているもののほとんどは、Coqの標準ライブラリの定義と同じものだからです。
こうする主な理由は、Coqのグローバルな環境を整理して、例えば、
関係する定理を探すのを容易にするためです。 *)
Require Export SfLib_J.
(* ####################################################### *)
(* * Arithmetic and Boolean Expressions *)
(** * 算術式とブール式 *)
(* We'll present Imp in three parts: first a core language of
_arithmetic and boolean expressions_, then an extension of these
expressions with _variables_, and finally a language of _commands_
including assignment, conditions, sequencing, and loops. *)
(** Impを三つの部分に分けて示します: 最初に算術式(_arithmetic expressions_)
とブール式(_boolean expressions_)、次にこれらの式に変数(_variables_)を加えたもの、
そして最後に代入(assignment)、条件分岐(conditions)、コマンド合成(sequencing)、
ループ(loops)を持つコマンド(_commands_)の言語です。*)
Module AExp.
(* ####################################################### *)
(* ** Syntax *)
(** ** 構文 *)
(* These two definitions specify the _abstract syntax_ of
arithmetic and boolean expressions. *)
(** 次の2つの定義は、算術式とブール式の抽象構文(_abstract syntax_)を定めます。*)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
(* In this chapter, we'll elide the translation from the
concrete syntax that a programmer would actually write to these
abstract syntax trees -- the process that, for example, would
translate the string ["1+2*3"] to the AST [APlus (ANum
1) (AMult (ANum 2) (ANum 3))]. The file [ImpParser.v] develops a
simple implementation of a lexical analyzer and parser that can
perform this translation. You do _not_ need to understand that
file to understand this one, but if you haven't taken a course
where these techniques are covered (e.g., a compilers course) you
may want to skim it. *)
(** この章では、プログラマが実際に書く具象構文から抽象構文木への変換は省略します。
例えば、文字列["1+2*3"]をAST(Abstract Syntax Tree, 抽象構文木)
[APlus (ANum 1) (AMult (ANum 2) (ANum 3))] にする変換のことです。
この変換ができる字句解析器と構文解析器をファイル[ImpParser_J.v]で簡単に実装します。
このファイル([Imp_J.v])を理解するには[ImpParser_J.v]の理解は必要ではありませんが、
もしそれらの技術についてのコース(例えばコンパイラコース)を受講していないならば、
ざっと見てみるのも良いでしょう。 *)
(* For comparison, here's a conventional BNF (Backus-Naur Form)
grammar defining the same abstract syntax:
[[
aexp ::= nat
| aexp '+' aexp
| aexp '-' aexp
| aexp '*' aexp
bexp ::= true
| false
| aexp '=' aexp
| aexp '<=' aexp
| bexp 'and' bexp
| 'not' bexp
]]
*)
(** 比較のため、同じ抽象構文を定義する慣習的なBNF(Backus-Naur Form)
文法を以下に示します:
[[
aexp ::= nat
| aexp '+' aexp
| aexp '-' aexp
| aexp '*' aexp
bexp ::= true
| false
| aexp '=' aexp
| aexp '<=' aexp
| bexp 'and' bexp
| 'not' bexp
]]
*)
(* Compared to the Coq version above...
- The BNF is more informal -- for example, it gives some
suggestions about the surface syntax of expressions (like the
fact that the addition operation is written [+] and is an
infix symbol) while leaving other aspects of lexical analysis
and parsing (like the relative precedence of [+], [-], and
[*]) unspecified. Some additional information -- and human
intelligence -- would be required to turn this description
into a formal definition (when implementing a compiler, for
example).
The Coq version consistently omits all this information and
concentrates on the abstract syntax only.
- On the other hand, the BNF version is lighter and arguably
easier to read. Its informality makes it flexible, which is
a huge advantage in situations like discussions at the
blackboard, where conveying general ideas is more important
than getting every detail nailed down precisely.
Indeed, there are dozens of BNF-like notations and people
switch freely among them, usually without bothering to which
form of BNF they're using because there is no need to: a
rough-and-ready informal understanding is all that's
needed. *)
(** 上述のCoq版と比較して...
- BNFはより非形式的です。例えば、
BNFは式の表面的な構文についていくらかの情報を与えています
(可算は[+]と記述され、それは中置記号であるという事実などです)が、
字句解析と構文解析の他の面は定めないままになっています([+]、[-]、[*]
の相対的優先順位などです)。
(例えばコンパイラを実装するときに)この記述を形式的定義にするためには、
追加の情報、および人間の知性が必要でしょう。
Coq版はこれらの情報を整合的に省略し、抽象構文だけに集中します。
- 一方、BNF版はより軽くて、おそらく読むのがより簡単です。
非形式的であることで柔軟性を持っているので、
黒板を使って議論する場面などでは特段に有効です。
そういう場面では、細部をいちいち正確に確定させていくことより、
全体的アイデアを伝えることが重要だからです。
実際、BNFのような記法は山ほどあり、人は皆、それらの間を自由に行き来しますし、
通常はそれらのうちのどのBNFを使っているかを気にしません。
その必要がないからです。おおざっぱな非形式的な理解だけが必要なのです。 *)
(* It's good to be comfortable with both sorts of notations: informal
ones for communicating between humans and formal ones for carrying
out implementations and proofs. *)
(** 両方の記法に通じているのは良いことです。
非形式的なものは人間とのコミュニケーションのために、
形式的なものは実装と証明のためにです。 *)
(* ####################################################### *)
(* ** Evaluation *)
(** ** 評価 *)
(* _Evaluating_ an arithmetic expression reduces it to a single number. *)
(** 算術式を評価する(_evaluating_)とその式を1つの数に簡約します。 *)
Fixpoint aeval (e : aexp) : nat :=
match e with
| ANum n => n
| APlus a1 a2 => (aeval a1) + (aeval a2)
| AMinus a1 a2 => (aeval a1) - (aeval a2)
| AMult a1 a2 => (aeval a1) * (aeval a2)
end.
Example test_aeval1:
aeval (APlus (ANum 2) (ANum 2)) = 4.
Proof. reflexivity. Qed.
(* Similarly, evaluating a boolean expression yields a boolean. *)
(** 同様に、ブール式を評価するとブール値になります。*)
Fixpoint beval (e : bexp) : bool :=
match e with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval a1) (aeval a2)
| BLe a1 a2 => ble_nat (aeval a1) (aeval a2)
| BNot b1 => negb (beval b1)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
(* ####################################################### *)
(* ** Optimization *)
(** ** 最適化(Optimization) *)
(* We haven't defined very much yet, but we can already get
some mileage out of the definitions. Suppose we define a function
that takes an arithmetic expression and slightly simplifies it,
changing every occurrence of [0+e] (i.e., [(APlus (ANum 0) e])
into just [e]. *)
(** ここまで定義したものはわずかですが、その定義から既にいくらかのものを得ることができます。
算術式をとって、それを少し簡単化する関数を定義するとします。
すべての [0+e] (つまり [(APlus (ANum 0) e)])を単に[e]にするものです。 *)
Fixpoint optimize_0plus (e:aexp) : aexp :=
match e with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
(* To make sure our optimization is doing the right thing we
can test it on some examples and see if the output looks OK. *)
(** この最適化が正しいことをすることを確認するために、
いくつかの例についてテストして出力がよさそうかを見てみることができます。 *)
Example test_optimize_0plus:
optimize_0plus (APlus (ANum 2)
(APlus (ANum 0)
(APlus (ANum 0) (ANum 1))))
= APlus (ANum 2) (ANum 1).
Proof. reflexivity. Qed.
(* But if we want to be sure the optimization is correct --
i.e., that evaluating an optimized expression gives the same
result as the original -- we should prove it. *)
(** しかし、もし最適化が正しいことを確認したいならば、
-- つまり、最適化した式がオリジナルの式と同じ評価結果を返すことを確認したいならば、
証明すべきです。 *)
Theorem optimize_0plus_sound: forall e,
aeval (optimize_0plus e) = aeval e.
Proof.
intros e. induction e.
Case "ANum". reflexivity.
Case "APlus". destruct e1.
SCase "e1 = ANum n". destruct n.
SSCase "n = 0". simpl. apply IHe2.
SSCase "n <> 0". simpl. rewrite IHe2. reflexivity.
SCase "e1 = APlus e1_1 e1_2".
simpl. simpl in IHe1. rewrite IHe1.
rewrite IHe2. reflexivity.
SCase "e1 = AMinus e1_1 e1_2".
simpl. simpl in IHe1. rewrite IHe1.
rewrite IHe2. reflexivity.
SCase "e1 = AMult e1_1 e1_2".
simpl. simpl in IHe1. rewrite IHe1.
rewrite IHe2. reflexivity.
Case "AMinus".
simpl. rewrite IHe1. rewrite IHe2. reflexivity.
Case "AMult".
simpl. rewrite IHe1. rewrite IHe2. reflexivity. Qed.
(* ####################################################### *)
(* * Coq Automation *)
(** * Coq の自動化 *)
(* The repetition in this last proof is starting to be a little
annoying. It's still just about bearable, but if either the
language of arithmetic expressions or the optimization being
proved sound were significantly more complex, it would begin to be
a real problem.
So far, we've been doing all our proofs using just a small handful
of Coq's tactics and completely ignoring its very powerful
facilities for constructing proofs automatically. This section
introduces some of these facilities, and we will see more over the
next several chapters. Getting used to them will take some
energy -- Coq's automation is a power tool -- but it will allow us to
scale up our efforts to more complex definitions and more
interesting properties without becoming overwhelmed by boring,
repetitive, or low-level details. *)
(** 前の証明の最後の繰り返しはちょっと面倒です。今のところまだ耐えられますが、
証明対象の言語や算術式や最適化が今に比べて著しく複雑だったら、現実的に問題になるでしょう。
ここまで、Coq のタクティックのほんのひとつかみだけですべての証明をしてきていて、
証明を自動的に構成する非常に強力な機構を完全に無視してきました。
このセクションではこれらの機構のいくつかを紹介します。
それ以上のものを、以降のいくつかの章で次第に見ることになるでしょう。
それらに慣れるには多少エネルギーが必要でしょう。
-- Coq の自動化は電動工具です。--
しかし自動化機構を使うことで、より複雑な定義や、より興味深い性質について、
退屈で繰り返しの多いローレベルな詳細に飲み込まれることなく、
作業をスケールアップできます。 *)
(* ####################################################### *)
(* ** Tacticals *)
(** ** タクティカル(Tacticals) *)
(* _Tactical_ is Coq's term for tactics that take other tactics as
arguments -- "higher-order tactics," if you will. *)
(** タクティカル(_tactical_)は Coq の用語で、
他のタクティックを引数に取るタクティックのことです。
「高階タクティック」("higher-order tactics")と言っても良いでしょう。 *)
(* ####################################################### *)
(* *** The [try] Tactical *)
(** *** [try]タクティカル *)
(* One very simple tactical is [try]: If [T] is a tactic, then [try
T] is a tactic that is just like [T] except that, if [T] fails,
[try T] does nothing at all (instead of failing). *)
(** 非常にシンプルなタクティカルの1つが[try]です。[T]がタクティックのとき、
タクティック [try T] は[T]と同様ですが、[T]が失敗するとき
[try T] は(失敗せずに)何もしない点が違います。 *)
(* ####################################################### *)
(* *** The [;] Tactical *)
(** *** [;]タクティカル *)
(* Another very basic tactical is written [;]. If [T], [T1], ...,
[Tn] are tactics, then
[[
T; [T1 | T2 | ... | Tn]
]]
is a tactic that first performs [T] and then performs [T1] on the
first subgoal generated by [T], performs [T2] on the second
subgoal, etc.
In the special case where all of the [Ti]'s are the same tactic
[T'], we can just write [T;T'] instead of:
[[
T; [T' | T' | ... | T']
]]
That is, if [T] and [T'] are tactics, then [T;T'] is a tactic that
first performs [T] and then performs [T'] on _each subgoal_
generated by [T]. This is the form of [;] that is used most often
in practice. *)
(** 別の非常に基本的なタクティカルは[;]と書かれます。
[T], [T1], ..., [Tn] がタクティックのとき、
[[
T; [T1 | T2 | ... | Tn]
]]
はタクティックで、最初に[T]を行ない、
[T]によって生成された最初のサブゴールに[T1]を行ない、
二番目のサブゴールに[T2]を行ない、... という処理をします。
すべての[Ti]が同じタクティック[T']であるという特別な場合、
[[
T; [T' | T' | ... | T']
]]
と書く代わりに [T;T'] と書くだけで済ますことができます。
つまり、[T]と[T']がタクティックのとき、
[T;T'] はタクティックで、最初に[T]を行ない、
[T]が生成したそれぞれのサブゴールに[T']を行ないます。
これが[;]の実際に一番よく使われる形です。*)
(* For example, consider the following trivial lemma: *)
(** 例えば、次の簡単な補題を考えます: *)
Lemma foo : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n.
(* Leaves two subgoals... *)
Case "n=0". simpl. reflexivity.
Case "n=Sn'". simpl. reflexivity.
(* ... which are discharged similarly *)
Qed.
(* We can simplify the proof above using the [;] tactical. *)
(** 上の証明を[;]タクティカルを使って簡単化できます。 *)
Lemma foo' : forall n, ble_nat 0 n = true.
Proof.
intros.
(* Apply [destruct] to the current goal *)
destruct n;
(* then apply [simpl] to each resulting subgoal *)
simpl;
(* then apply [reflexivity] to each resulting subgoal *)
reflexivity.
Qed.
(* Using [try] and [;] together, we can get rid of the repetition in
the proof that was bothering us a little while ago. *)
(** [try]と[;]の両方を使うと、
ちょっと前に悩まされた証明の繰り返しを取り除くことができます。 *)
Theorem optimize_0plus_sound': forall e,
aeval (optimize_0plus e) = aeval e.
Proof.
intros e.
induction e;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHe1; rewrite IHe2; reflexivity).
Case "ANum". reflexivity.
Case "APlus".
destruct e1;
(* Most cases follow directly by the IH *)
try (simpl; simpl in IHe1; rewrite IHe1; rewrite IHe2; reflexivity).
(* The interesting case, on which the above fails, is
when [e1 = ANum n]. In this case, we have to destruct [n]
(to see whether the optimization applies) and rewrite
with the induction hypothesis. *)
SCase "e1 = ANum n". destruct n;
simpl; rewrite IHe2; reflexivity. Qed.
(* In practice, Coq experts often use [try] with a tactic like
[induction] to take care of many similar "straightforward" cases
all at once. Naturally, this practice has an analog in informal
proofs. *)
(** 実際的にはCoqの専門家は、[try]を[induction]のようなタクティックと一緒に使うことで、
多くの似たような「簡単な」場合を一度に処理します。
これは自然に非形式的な証明に対応します。*)
(* Here is an informal proof of this theorem that
matches the structure of the formal one:
_Theorem_: For all arithmetic expressions [e],
[[
aeval (optimize_0plus e) = aeval e.
]]
_Proof_: By induction on [e]. The [AMinus] and [AMult] cases
follow directly from the IH. The remaining cases are as follows:
- Suppose [e = ANum n] for some [n]. We must show
[[
aeval (optimize_0plus (ANum n)) = aeval (ANum n).
]]
This is immediate from the definition of [optimize_0plus].
- Suppose [e = APlus e1 e2] for some [e1] and [e2]. We
must show
[[
aeval (optimize_0plus (APlus e1 e2))
= aeval (APlus e1 e2).
]]
Consider the possible forms of [e1]. For most of them,
[optimize_0plus] simply calls itself recursively for the
subexpressions and rebuilds a new expression of the same form
as [e1]; in these cases, the result follows directly from the
IH.
The interesting case is when [e1 = ANum n] for some [n].
If [n = ANum 0], then
[[
optimize_0plus (APlus e1 e2) = optimize_0plus e2
]]
and the IH for [e2] is exactly what we need. On the other
hand, if [n = S n'] for some [n'], then again [optimize_0plus]
simply calls itself recursively, and the result follows from
the IH. [] *)
(** この定理の形式的な証明の構造にマッチする非形式的な証明は次の通りです:
「定理」: すべての算術式[e]について
[[
aeval (optimize_0plus e) = aeval e.
]]
「証明」: [e]についての帰納法を使う。
[AMinus]と[AMult]の場合は帰納仮定から直接得られる。
残るのは以下の場合である:
- ある[n]について [e = ANum n] とする。示すべきことは次の通りである:
[[
aeval (optimize_0plus (ANum n)) = aeval (ANum n).
]]
これは[optimize_0plus]の定義からすぐに得られる。
- ある[e1]と[e2]について [e = APlus e1 e2] とする。
示すべきことは次の通りである:
[[
aeval (optimize_0plus (APlus e1 e2))
= aeval (APlus e1 e2).
]]
[e1]のとり得る形を考える。そのほとんどの場合、
[optimize_0plus]は部分式について単に自分自身を再帰的に呼び出し、
[e1]と同じ形の新しい式を再構成する。
これらの場合、結果は帰納仮定からすぐに得られる。
興味深い場合は、ある[n]について [e1 = ANum n] であるときである。
このとき [n = ANum 0] ならば次が成立する:
[[
optimize_0plus (APlus e1 e2) = optimize_0plus e2
]]
そして[e2]についての帰納仮定がまさに求めるものである。
一方、ある[n']について [n = S n'] ならば、
[optimize_0plus]はやはり自分自身を再帰的に呼び出し、
結果は帰納仮定から得られる。 [] *)
(* This proof can still be improved: the first case (for [e = ANum
n]) is very trivial -- even more trivial than the cases that we
said simply followed from the IH -- yet we have chosen to write it
out in full. It would be better and clearer to drop it and just
say, at the top, "Most cases are either immediate or direct from
the IH. The only interesting case is the one for [APlus]..." We
can make the same improvement in our formal proof too. Here's how
it looks: *)
(** この証明はさらに改良できます。最初の場合([e = ANum n] のとき)はかなり自明です。
帰納仮定からすぐに得られると言ったものより自明でしょう。
それなのに完全に記述しています。
これを消して、単に最初に「ほとんどの場合、すぐに、あるいは帰納仮定から直接得られる。
興味深いのは[APlus]の場合だけである...」
と言った方がより良く、より明快でしょう。
同じ改良を形式的な証明にも行うことができます。以下のようになります: *)
Theorem optimize_0plus_sound'': forall e,
aeval (optimize_0plus e) = aeval e.
Proof.
intros e.
induction e;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHe1; rewrite IHe2; reflexivity);
(* ... or are immediate by definition *)
try reflexivity.
(* The interesting case is when e = APlus e1 e2. *)
Case "APlus".
destruct e1; try (simpl; simpl in IHe1; rewrite IHe1;
rewrite IHe2; reflexivity).
SCase "e1 = ANum n". destruct n;
simpl; rewrite IHe2; reflexivity. Qed.
(* ####################################################### *)
(* ** Defining New Tactic Notations *)
(** ** 新しいタクティック記法を定義する *)
(* Coq also provides several ways of "programming" tactic scripts.
- The [Tactic Notation] command gives a handy way to define
"shorthand tactics" that, when invoked, apply several tactics
at the same time.
- For more sophisticated programming, Coq offers a small
built-in programming language called [Ltac] with primitives
that can examine and modify the proof state. The details are
a bit too complicated to get into here (and it is generally
agreed that [Ltac] is not the most beautiful part of Coq's
design!), but they can be found in the reference manual, and
there are many examples of [Ltac] definitions in the Coq
standard library that you can use as examples.
- There is also an OCaml API that can be used to build new
tactics that access Coq's internal structures at a lower
level, but this is seldom worth the trouble for ordinary Coq
users.
The [Tactic Notation] mechanism is the easiest to come to grips with,
and it offers plenty of power for many purposes. Here's an example.
*)
(** Coqはまた、タクティックスクリプトを「プログラミングする」いろいろな方法も提供します。
- [Tactic Notation] コマンドは、「略記法タクティック」("shorthand tactics")
を定義する簡単な方法を提供します。
「略記法タクティック」は、呼ばれると、いろいろなタクティックを一度に適用します。
- より洗練されたプログラミングのために、
Coqは[Ltac]と呼ばれる小さなビルトインのプログラミング言語と、
証明の状態を調べたり変更したりするための[Ltac]のプリミティブを提供します。
その詳細はここで説明するにはちょっと複雑過ぎます
(しかも、[Ltac]がCoqの設計の一番美しくない部分だというのは共通見解です!)。
しかし、詳細はリファレンスマニュアルにありますし、
Coqの標準ライブラリには、読者が参考にできる[Ltac]の定義のたくさんの例があります。
- Coqの内部構造のより深いレベルにアクセスする新しいタクティックを作ることができる
OCaml API も存在します。しかしこれは、普通のCoqユーザにとっては、
苦労が報われることはほとんどありません。
[Tactic Notation] 機構は取り組むのに一番簡単で、多くの目的に十分なパワーを発揮します。
例を挙げます。
*)
Tactic Notation "simpl_and_try" tactic(c) :=
simpl;
try c.
(* This defines a new tactical called [simpl_and_try] which
takes one tactic [c] as an argument, and is defined to be
equivalent to the tactic [simpl; try c]. For example, writing
"[simpl_and_try reflexivity.]" in a proof would be the same as
writing "[simpl; try reflexivity.]" *)
(** これは1つのタクティック[c]を引数としてとる[simpl_and_try]
という新しいタクティカルを定義しています。
そして、タクティック [simpl; try c] と同値なものとして定義されます。
例えば、証明内で"[simpl_and_try reflexivity.]"と書くことは
"[simpl; try reflexivity.]"と書くことと同じでしょう。 *)
(* The next subsection gives a more sophisticated use of this
feature... *)
(** 次のサブセクションでは、この機構のより洗練された使い方を見ます... *)
(* ####################################################### *)
(* *** Bulletproofing Case Analyses *)
(** *** 場合分けを万全にする *)
(* Being able to deal with most of the cases of an [induction] or
[destruct] all at the same time is very convenient, but it can
also be a little confusing. One problem that often comes up is
that _maintaining_ proofs written in this style can be difficult.
For example, suppose that, later, we extended the definition of
[aexp] with another constructor that also required a special
argument. The above proof might break because Coq generated the
subgoals for this constructor before the one for [APlus], so that,
at the point when we start working on the [APlus] case, Coq is
actually expecting the argument for a completely different
constructor. What we'd like is to get a sensible error message
saying "I was expecting the [AFoo] case at this point, but the
proof script is talking about [APlus]." Here's a nice little
trick that smoothly achieves this. *)
(** [induction]や[destruct]で、ほとんどの場合を一度に扱えるのはとても便利ですが、
またちょっと混乱もします。よく起こる問題は、
このスタイルで記述された証明をメンテナンスすることが難しいということです。
例えば、後で、[aexp]の定義を拡張して、
やはり特別な引数をとるコンストラクタを追加したとします。
このとき上述の証明は成立しなくなっているでしょう。
なぜなら、
Coqは[APlus]についてのサブゴールの前にこのコンストラクタに対応するサブゴールを生成し、
その結果、[APlus]の場合に取りかかる時には、
Coqは実際にはまったく別のコンストラクタを待っていることになるからです。
ここで欲しいのは、「この場所で[AFoo]の場合を期待していましたが、
証明スクリプトは[APlus]について話しています。」という賢いエラーメッセージです。
以下は、これを難なく可能にするちょっとしたトリックです。 *)
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(* ([Case_aux] implements the common functionality of [Case],
[SCase], [SSCase], etc. For example, [Case "foo"] is defined as
[Case_aux Case "foo".) *)
(** ([Case_aux]は[Case]、[SCase]、[SSCase]等の共通機能を実装します。
例えば、[Case "foo"]は [Case_aux Case "foo"] と定義されます。) *)
(* For example, if [e] is a variable of type [aexp], then doing
[[
aexp_cases (induction e) Case
]]
will perform an induction on [e] (the same as if we had just typed
[induction e]) and _also_ add a [Case] tag to each subgoal
generated by the [induction], labeling which constructor it comes
from. For example, here is yet another proof of
optimize_0plus_sound, using [aexp_cases]: *)
(** 例えば、[e]が型[aexp]の変数のとき、
[[
aexp_cases (induction e) Case
]]
と書くと[e]についての帰納法を実行し(単に [induction e] と書いたのと同じです)、
そして、「その上に」、[induction]によって生成されたそれぞれのサブゴールに[Case]
タグを付加します。このタグは、そのサブゴールがどのコンストラクタから来たかのラベルです。
例えば、[aexp_cases]を使った、[optimize_0plus_sound]のさらに別証です: *)
Theorem optimize_0plus_sound''': forall e,
aeval (optimize_0plus e) = aeval e.
Proof.
intros e.
aexp_cases (induction e) Case;
try (simpl; rewrite IHe1; rewrite IHe2; reflexivity);
try reflexivity.
(* At this point, there is already an ["APlus"] case name in the
context. The [Case "APlus"] here in the proof text has the
effect of a sanity check: if the "Case" string in the context is
anything _other_ than ["APlus"] (for example, because we added a
clause to the definition of [aexp] and forgot to change the
proof) we'll get a helpful error at this point telling us that
this is now the wrong case. *)
Case "APlus".
aexp_cases (destruct e1) SCase;
try (simpl; simpl in IHe1; rewrite IHe1; rewrite IHe2; reflexivity).
SCase "ANum". destruct n;
simpl; rewrite IHe2; reflexivity. Qed.
(* **** Exercise: 3 stars (optimize_0plus_b) *)
(** **** 練習問題: ★★★ (optimize_0plus_b) *)
(* Since the [optimize_0plus] tranformation doesn't change the value
of [aexp]s, we should be able to apply it to all the [aexp]s that
appear in a [bexp] without changing the [bexp]'s value. Write a
function which performs that transformation on [bexp]s, and prove
it is sound. Use the tacticals we've just seen to make the proof
as elegant as possible. *)
(** [optimize_0plus]の変換が[aexp]の値を変えないことから、
[bexp]の値を変えずに、[bexp]に現れる[aexp]をすべて変換するために
[optimize_0plus]が適用できるべきでしょう。
[bexp]についてこの変換をする関数を記述しなさい。そして、
それが健全であることを証明しなさい。
ここまで見てきたタクティカルを使って証明を可能な限りエレガントにしなさい。*)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 4 stars, optional (optimizer) *)
(** **** 練習問題: ★★★★, optional (optimizer) *)
(* _Design exercise_: The optimization implemented by our
[optimize_0plus] function is only one of many imaginable
optimizations on arithmetic and boolean expressions. Write a more
sophisticated optimizer and prove it correct.
(* FILL IN HERE *)
*)
(** 設計練習: 定義した[optimize_0plus]関数で実装された最適化は、
算術式やブール式に対して考えられるいろいろな最適化の単なる1つに過ぎません。
より洗練された最適化関数を記述し、その正しさを証明しなさい。
(* FILL IN HERE *)
*)
(** [] *)
(* ####################################################### *)
(* ** The [omega] Tactic *)
(** ** [omega]タクティック *)
(* The [omega] tactic implements a decision procedure for a subset of
first-order logic called _Presburger arithmetic_. It is based on
the Omega algorithm invented in 1992 by William Pugh.
If the goal is a universally quantified formula made out of
- numeric constants, addition ([+] and [S]), subtraction ([-]
and [pred]), and multiplication by constants (this is what
makes it Presburger arithmetic),
- equality ([=] and [<>]) and inequality ([<=]), and
- the logical connectives [/\], [\/], [~], and [->],
then invoking [omega] will either solve the goal or tell you that
it is actually false. *)
(** [omega]タクティックは「プレスバーガー算術」
(_Presburger arithmetic_、「プレスブルガー算術」とも)
と呼ばれる一階述語論理のサブセットの決定手続き(decision procedure)を実装します。
William Pugh が1992年に発明したOmegaアルゴリズムに基いています。
ゴールが以下の要素から構成された全称限量された論理式とします。以下の要素とは:
- 数値定数、加算([+]と[S])、減算([-]と[pred])、
定数の積算(これがプレスバーガー算術である条件です)、
- 等式([=]と[<>])および不等式([<=])、
- 論理演算子[/\], [\/], [~], [->]
です。このとき、[omega]を呼ぶと、ゴールを解くか、
そのゴールが偽であると告げるか、いずれかになります。 *)
Example silly_presburger_example : forall m n o p,
m + n <= n + o /\ o + 3 = p + 3 ->
m <= p.
Proof.
intros. omega.
Qed.
(* Andrew Appel calls this the "Santa Claus tactic." *)
(** Andrew Appel は[omega]を「サンタクロース・タクティック」と呼んでいます。 *)
(* ####################################################### *)
(* ** A Few More Handy Tactics *)
(** ** 便利なタクティックをさらにいくつか *)
(* Finally, here are some miscellaneous tactics that you may find
convenient.
- [clear H]: Delete hypothesis [H] from the context.
- [subst x]: Find an assumption [x = e] or [e = x] in the
context, replace [x] with [e] throughout the context and
current goal, and clear the assumption.
- [subst]: Substitute away _all_ assumptions of the form [x = e]
or [e = x].
- [rename... into...]: Change the name of a hypothesis in the
proof context. For example, if the context includes a variable
named [x], then [rename x into y] will change all occurrences
of [x] to [y].
- [assumption]: Try to find a hypothesis [H] in the context that
exactly matches the goal; if one is found, behave just like
[apply H].
- [contradiction]: Try to find a hypothesis [H] in the current
context that is equivalent to [False]. If one is found, solve
the goal.
- [constructor]: Try to find a constructor [c] (from some
[Inductive] definition in the current environment) that can be
applied to solve the current goal. If one is found, behave
like [apply c].
We'll see many examples of these in the proofs below. *)
(** 最後に、役に立ちそうないろいろなタクティックをいくつか紹介します。
- [clear H]: 仮定[H]をコンテキストから消去します。
- [subst x]: コンテキストから仮定 [x = e] または [e = x] を発見し、
[x]をコンテキストおよび現在のゴールのすべての場所で[e]に置き換え、
この仮定を消去します。
- [subst]: [x = e] および [e = x] の形のすべての仮定を置換します。
- [rename... into...]: 証明コンテキストの仮定の名前を変更します。
例えば、コンテキストが[x]という名前の変数を含んでいるとき、
[rename x into y] は、すべての[x]の出現を[y]に変えます。
- [assumption]: ゴールにちょうどマッチする仮定[H]をコンテキストから探そうとします。
発見されたときは [apply H] と同様に振る舞います。
- [contradiction]: [False]と同値の仮定[H]をコンテキストから探そうとします。
発見されたときはゴールを解きます。
- [constructor]: 現在のゴールを解くのに使えるコンストラクタ[c]を
(現在の環境の[Inductive]による定義から)探そうとします。
発見されたときは [apply c] と同様に振る舞います。
以降の証明でこれらのたくさんの例を見るでしょう。 *)
(* ####################################################### *)
(* * Evaluation as a Relation *)
(** * 関係としての評価 *)
(* We have presented [aeval] and [beval] as functions defined by
[Fixpoints]. An alternative way to think about evaluation is as a
_relation_ between expressions and their values.
This leads naturally to Coq [Inductive] definitions like the
following one for arithmetic expressions... *)
(** [aeval]と[beval]を[Fixpoints]によって定義された関数として示しました。
評価について考える別の方法は、それを式と値との間の関係(_relation_)と見ることです。
この考えに立つと、
算術式についてCoqの[Inductive]による以下の定義が自然に出てきます... *)
Module aevalR_first_try.
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n: nat),
aevalR (ANum n) n
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus: forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMult e1 e2) (n1 * n2).
(* As is often the case with relations, we'll find it
convenient to define infix notation for [aevalR]. We'll write [e
|| n] to mean that arithmetic expression [e] evaluates to value
[n]. (This notation is one place where the limitation to ascii
symbols becomes a little bothersome. The standard notation for
the evaluation relation is a double down-arrow. We'll typeset it
like this in the HTML version of the notes and use a double
vertical bar as the closest approximation in ascii .v files.) *)
(** 関係についてよく行うように、[aevalR]の中置記法を定義するのが便利です。
算術式[e]が値[n]に評価されることを [e || n] と書きます。
(この記法は煩わしいascii記号の限界の1つです。評価関係の標準記法は二重の下向き矢印です。
HTML版ではそのようにタイプセットしますが、ascii の
.v ファイルでは可能な近似として縦棒二本を使います。) *)
Notation "e '||' n" := (aevalR e n) : type_scope.
End aevalR_first_try.
(* In fact, Coq provides a way to use this notation in the definition
of [aevalR] itself. This avoids situations where we're working on
a proof involving statements in the form [e || n] but we have to
refer back to a definition written using the form [aevalR e n].
We do this by first "reserving" the notation, then giving the
definition together with a declaration of what the notation
means. *)
(** 実際は、Coqでは[aevalR]自身の定義中でこの記法を使うことができます。
これにより、[e || n] の形の主張を含む証明で、[aevalR e n]
という形の定義に戻らなければならない状況にならずに済みます。
このためには、最初に記法を「予約」し、
それから定義と、記法が何を意味するかの宣言とを一緒に行います。*)
Reserved Notation "e '||' n" (at level 50, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (APlus e1 e2) || (n1 + n2)
| E_AMinus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMinus e1 e2) || (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMult e1 e2) || (n1 * n2)
where "e '||' n" := (aevalR e n) : type_scope.
Tactic Notation "aevalR_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_ANum" | Case_aux c "E_APlus"
| Case_aux c "E_AMinus" | Case_aux c "E_AMult" ].
(* It is straightforward to prove that the relational and functional
definitions of evaluation agree on all possible arithmetic
expressions... *)
(** 評価の、関係による定義と関数による定義が、
すべての算術式について一致することを証明するのは簡単です... *)
Theorem aeval_iff_aevalR : forall a n,
(a || n) <-> aeval a = n.
Proof.
split.
Case "->".
intros H.
aevalR_cases (induction H) SCase; simpl.
SCase "E_ANum".
reflexivity.
SCase "E_APlus".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "E_AMinus".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "E_AMult".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
Case "<-".
generalize dependent n.
aexp_cases (induction a) SCase;
simpl; intros; subst.
SCase "ANum".
apply E_ANum.
SCase "APlus".
apply E_APlus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
SCase "AMinus".
apply E_AMinus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
SCase "AMult".
apply E_AMult.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
Qed.
(* A shorter proof making more aggressive use of tacticals: *)
(** タクティカルをより積極的に使ったより短い証明です: *)
Theorem aeval_iff_aevalR' : forall a n,
(a || n) <-> aeval a = n.
Proof.
(* WORKED IN CLASS *)
split.
Case "->".
intros H; induction H; subst; reflexivity.
Case "<-".
generalize dependent n.
induction a; simpl; intros; subst; constructor;
try apply IHa1; try apply IHa2; reflexivity.
Qed.
(* **** Exercise: 2 stars, optional (bevalR) *)
(** **** 練習問題: ★★, optional (bevalR) *)
(* Write a relation [bevalR] in the same style as
[aevalR], and prove that it is equivalent to [beval].*)
(** 関係[bevalR]を[aevalR]と同じスタイルで記述し、
それが[beval]と同値であることを証明しなさい。 *)
(*
Inductive bevalR:
(* FILL IN HERE *)
(** [] *)
*)
(* For the definitions of evaluation for arithmetic and boolean
expressions, the choice of whether to use functional or relational
definitions is mainly a matter of taste. In general, Coq has
somewhat better support for working with relations; in particular,
we can more readily do induction over them. On the other hand, in
some sense function definitions carry more information, because
functions are necessarily deterministic and defined on all
arguments; for a relation we have to show these properties
explicitly if we need them.
However, there are circumstances where relational definitions of
evaluation are greatly preferable to functional ones, as we'll see
shortly. *)
(** 算術式とブール式の評価の定義について、関数を使うか関係を使うかはほとんど趣味の問題です。
一般に、Coqは関係を扱う方がいくらかサポートが厚いです。
特に帰納法についてはそうです。一方、
ある意味で関数による定義の方がより多くの情報を持っています。
なぜなら、関数は決定的でなければならず、
またすべての引数について定義されていなければなりません。
関係については、必要ならばこれらの性質を明示的に示さなければなりません。
しかしながら、評価の定義として、
関係による定義が関数による定義よりはるかに望ましい状況があります。
以下で簡単に見ます。 *)
(* ####################################################### *)
(* ** Inference Rule Notation *)
(** ** 推論規則記法 *)
(* In informal discussions, it is convenient write the rules for
[aevalR] and similar relations in a more readable "graphical" form
called _inference rules_, where the premises above the line allow
you to derive the conclusion below the line. For example, the
constructor [E_APlus]...
[[
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
]]
...would be written like this as an inference rule:
[[[
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
]]]
Formally, there is nothing very deep about inference rules: they
are just implications. You can read the rule name on the right as
the name of the constructor and read each of the linebreaks
between the premises above the line and the line itself as [->].
All the variables mentioned in the rule ([e1], [n1], etc.) are
implicitly bound by universal quantifiers at the beginning. The
whole collection of rules is understood as being wrapped in an
[Inductive] declaration (this is either left completely implicit
or else indicated informally by saying something like "Let
[aevalR] be the smallest relation closed under the following
rules...").
For example, [||] is the smallest relation closed under these
rules:
[[[
----------- (E_ANum)
ANum n || n
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
e1 || n1
e2 || n2
--------------------- (E_AMinus)
AMinus e1 e2 || n1-n2
e1 || n1
e2 || n2
-------------------- (E_AMult)
AMult e1 e2 || n1*n2
]]]
*)
(** 非形式的な議論には、[aevalR]や似たような関係についての規則を、
推論規則(_inference rules_)と呼ばれる、
より読みやすいグラフィカルな形で書くのが便利です。
推論規則は、横線の上の前提から、横線の下の結論を導出できることを述べます。
例えば、コンストラクタ[E_APlus]...
[[
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
]]
...は推論規則として次のように書けるでしょう:
[[
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
]]
形式的には、推論規則について何も深いものはありません。単なる含意です。
右に書かれた規則名はコンストラクタで、
横線より上の前提の間の各改行と横線自体は[->]と読むことができます。
規則で言及されるすべての変数([e1]、[n1]等)
は暗黙のうちに冒頭で全称限量子に束縛されています。
規則の集合全体は[Inductive]宣言で囲われていると理解されます
(これは完全に暗黙のまま置かれるか、非形式的に
「[aevalR]は以下の規則について閉じた最小の関係とします...」
などと述べられるかします)。
例えば、[||]は以下の規則について閉じた最小の関係です:
[[
----------- (E_ANum)
ANum n || n
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
e1 || n1
e2 || n2
--------------------- (E_AMinus)
AMinus e1 e2 || n1-n2
e1 || n1
e2 || n2
-------------------- (E_AMult)
AMult e1 e2 || n1*n2
]]
*)
End AExp.
(* ####################################################### *)
(* * Expressions With Variables *)
(** * 変数を持つ式 *)
(* Now let's turn our attention back to defining Imp. The next thing
we need to do is to enrich our arithmetic and boolean expressions
with variables. To keep things simple, we'll assume that all
variables are global and that they only hold numbers. *)
(** さて、Impの定義に戻りましょう。次にしなければならないことは、
算術式とブール式に変数を拡張することです。
話を単純にするため、すべての変数はグローバルで、数値だけを持つとしましょう。 *)
(* ##################################################### *)
(* ** Identifiers *)
(** ** 識別子 *)
(* To begin, we'll need to formalize _identifiers_, such as program
variables. We could use strings for this, or (in a real compiler)
some kind of fancier structures like pointers into a symbol table.
But for simplicity let's just use natural numbers as identifiers.
(We hide this section in a module because these definitions are
actually in [SfLib.v], but we want to repeat them here so that we
can explain them.) *)
(** 始めに、プログラム変数などの識別子(_identifiers_)を形式化しなければなりません。
このために文字列を使うこともできるでしょうし、(実際のコンパイラでは)
シンボルテーブルへのポインタのようなある種の特別な構造を使うこともできるでしょう。
しかし、簡単にするため、識別子に単に自然数を使います。
(このセクションをモジュールに隠します。それは、これらの定義が実際には[SfLib_J.v]
にあるからです。しかし説明のためにここで繰り返します。) *)
Module Id.
(* We define a new inductive datatype [Id] so that we won't confuse
identifiers and numbers. *)
(** 新しいデータタイプ[Id]を定義して、識別子と数値を混乱しないようにします。 *)
Inductive id : Type :=
Id : nat -> id.
Definition beq_id X1 X2 :=
match (X1, X2) with
(Id n1, Id n2) => beq_nat n1 n2
end.
(* Now, having "wrapped" numbers as identifiers in this way, it
is convenient to recapitulate a few properties of numbers as
analogous properties of identifiers, so that we can work with
identifiers in definitions and proofs abstractly, without
unwrapping them to expose the underlying numbers. Since all we
need to know about identifiers is whether they are the same or
different, just a few basic facts are all we need. *)
(** さて、この方法で「覆った」数値を識別子としたので、
数値のいくつかの性質を、対応する識別子の性質として繰り返しておくのが便利です。
そうすると、定義や証明の中の識別子を、
覆いを開いて中の数値を晒すことなく抽象的に扱うことができます。
識別子について知らなければならないことは、識別子同士が同じか違うかだけなので、
本当に2、3のことだけが必要です。 *)
Theorem beq_id_refl : forall X,
true = beq_id X X.
Proof.
intros. destruct X.
apply beq_nat_refl. Qed.
(* **** Exercise: 1 star, optional (beq_id_eq) *)
(** **** 練習問題: ★, optional (beq_id_eq) *)
(* For this and the following exercises, do not use induction, but
rather apply similar results already proved for natural numbers.
Some of the tactics mentioned above may prove useful. *)
(** この問題とそれに続く練習問題では、帰納法を使わずに、
既に証明した自然数の同様の結果を適用しなさい。
上述したいくつかのタクティックが使えるかもしれません。 *)
Theorem beq_id_eq : forall i1 i2,
true = beq_id i1 i2 -> i1 = i2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 1 star, optional (beq_id_false_not_eq) *)
(** **** 練習問題: ★, optional (beq_id_false_not_eq) *)
Theorem beq_id_false_not_eq : forall i1 i2,
beq_id i1 i2 = false -> i1 <> i2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 1 star, optional (not_eq_beq_id_false) *)
(** **** 練習問題: ★, optional (not_eq_beq_id_false) *)
Theorem not_eq_beq_id_false : forall i1 i2,
i1 <> i2 -> beq_id i1 i2 = false.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 1 star, optional (beq_id_sym) *)
(** **** 練習問題: ★, optional (beq_id_sym) *)
Theorem beq_id_sym: forall i1 i2,
beq_id i1 i2 = beq_id i2 i1.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Id.
(* ####################################################### *)
(* ** States *)
(** ** 状態 *)
(* A _state_ represents the current values of all the variables at
some point in the execution of a program. *)
(** 状態(_state_)はプログラムの実行のある時点のすべての変数の現在値を表します。 *)
(* For simplicity (to avoid dealing with partial functions), we
let the state be defined for _all_ variables, even though any
given program is only going tomention a finite number of them. *)
(** 簡単にするため(部分関数を扱うのを避けるため)、
どのようなプログラムも有限個の変数しか使わないにもかかわらず、
状態はすべての変数について値を定義しているものとします。 *)
Definition state := id -> nat.
Definition empty_state : state :=
fun _ => 0.
Definition update (st : state) (X:id) (n : nat) : state :=
fun X' => if beq_id X X' then n else st X'.
(* We'll need a few simple properties of [update]. *)
(** [update]についての単純な性質が必要です。 *)
(* **** Exercise: 2 stars, optional (update_eq) *)
(** **** 練習問題: ★★, optional (update_eq) *)
Theorem update_eq : forall n X st,
(update st X n) X = n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 2 stars, optional (update_neq) *)
(** **** 練習問題: ★★, optional (update_neq) *)
Theorem update_neq : forall V2 V1 n st,
beq_id V2 V1 = false ->
(update st V2 n) V1 = (st V1).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 2 stars, optional (update_example) *)
(** **** 練習問題: ★★, optional (update_example) *)
(* Before starting to play with tactics, make sure you understand
exactly what the theorem is saying! *)
(** タクティックを使って遊び始める前に、
定理が言っていることを正確に理解していることを確認しなさい! *)
Theorem update_example : forall (n:nat),
(update empty_state (Id 2) n) (Id 3) = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 2 stars (update_shadow) *)
(** **** 練習問題: ★★ (update_shadow) *)
Theorem update_shadow : forall x1 x2 k1 k2 (f : state),
(update (update f k2 x1) k2 x2) k1 = (update f k2 x2) k1.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 2 stars, optional (update_same) *)
(** **** 練習問題: ★★, optional (update_same) *)
Theorem update_same : forall x1 k1 k2 (f : state),
f k1 = x1 ->
(update f k1 x1) k2 = f k2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 2 stars, optional (update_permute) *)
(** **** 練習問題: ★★, optional (update_permute) *)
Theorem update_permute : forall x1 x2 k1 k2 k3 f,
beq_id k2 k1 = false ->
(update (update f k2 x1) k1 x2) k3 = (update (update f k1 x2) k2 x1) k3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################### *)
(* ** Syntax *)
(** ** 構文 *)
(* We can add variables to the arithmetic expressions we had before by
simply adding one more constructor: *)
(** 前に定義した算術式に、単にもう1つコンストラクタを追加することで変数を追加できます: *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| AId : id -> aexp (* <----- NEW *)
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "AId" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(* Shorthands for variables: *)
(** 変数の略記法: *)
Definition X : id := Id 0.
Definition Y : id := Id 1.
Definition Z : id := Id 2.
(* (This convention for naming program variables ([X], [Y],
[Z]) clashes a bit with our earlier use of uppercase letters for
types. Since we're not using polymorphism heavily in this part of
the course, this overloading should not cause confusion.) *)
(** (プログラム変数のこの慣習([X], [Y], [Z])は、
型に大文字の記号を使うという以前の使用法と衝突します。
コースのこの部分では多相性を多用はしないので、このことが混乱を招くことはないはずです。) *)
(* The definition of [bexp]s is the same as before (using the new
[aexp]s): *)
(** [bexp]の定義は前と同じです(ただし新しい[aexp]を使います): *)
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
Tactic Notation "bexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "BTrue" | Case_aux c "BFalse" | Case_aux c "BEq"
| Case_aux c "BLe" | Case_aux c "BNot" | Case_aux c "BAnd" ].
(* ################################################### *)
(* ** Evaluation *)
(** ** 評価 *)
(* The arith and boolean evaluators are extended to handle
variables in the obvious way: *)
(** 算術とブールの評価器は、自明な方法で変数を扱うように拡張されます: *)
Fixpoint aeval (st : state) (e : aexp) : nat :=
match e with
| ANum n => n
| AId X => st X (* <----- NEW *)
| APlus a1 a2 => (aeval st a1) + (aeval st a2)
| AMinus a1 a2 => (aeval st a1) - (aeval st a2)
| AMult a1 a2 => (aeval st a1) * (aeval st a2)
end.
Fixpoint beval (st : state) (e : bexp) : bool :=
match e with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval st a1) (aeval st a2)
| BLe a1 a2 => ble_nat (aeval st a1) (aeval st a2)
| BNot b1 => negb (beval st b1)
| BAnd b1 b2 => andb (beval st b1) (beval st b2)
end.
Example aexp1 :
aeval (update empty_state X 5)
(APlus (ANum 3) (AMult (AId X) (ANum 2)))
= 13.
Proof. reflexivity. Qed.
Example bexp1 :
beval (update empty_state X 5)
(BAnd BTrue (BNot (BLe (AId X) (ANum 4))))
= true.
Proof. reflexivity. Qed.
(* ####################################################### *)
(* * Commands *)
(** * コマンド *)
(* Now we are ready define the syntax and behavior of Imp
_commands_ (or _statements_). *)
(** さて、Imp コマンド (または主張) の構文と挙動を定義する準備が出来ました *)
(* ################################################### *)
(* ** Syntax *)
(** ** 構文 *)
(* Informally, commands are described by the following BNF
grammar:
[[
com ::= 'SKIP'
| X '::=' aexp
| com ';' com
| 'WHILE' bexp 'DO' com 'END'
| 'IFB' bexp 'THEN' com 'ELSE' com 'FI'
]]
For example, here's the factorial function in Imp.
[[
Z ::= X;
Y ::= 1;
WHILE not (Z = 0) DO
Y ::= Y * Z;
Z ::= Z - 1
END
]]
When this command terminates, the variable [Y] will contain the
factorial of the variable [X].
*)
(** 非形式的には、コマンドは以下の BNF で表現されます。
構文:
[[
com ::= 'SKIP'
| X '::=' aexp
| com ';' com
| 'WHILE' bexp 'DO' com 'END'
| 'IFB' bexp 'THEN' com 'ELSE' com 'FI'
]]
例えば、Imp における階乗関数は以下のようになります。
[[
Z ::= X;
Y ::= 1;
WHILE not (Z = 0) DO
Y ::= Y * Z;
Z ::= Z - 1
END
]]
このコマンドが終わったとき、変数 [Y] は変数 [X] の階乗の値を持つでしょう。
*)
(* Here is the formal definition of the syntax of commands: *)
(** 以下に、コマンドの構文の形式的な定義を示します。 *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
(* As usual, we can use a few [Notation] declarations to make things
more readable. However, we need to be a bit careful to avoid
conflicts with Coq's built-in notations, so we'll keep this
light -- in particular, we won't introduce any notations for
[aexps] and [bexps] to avoid confusion with the numerical and
boolean operators we've already defined. (We use the keyword
[IFB] for conditionals instead of the usual [IF] for similar
reasons.) *)
(** いつものとおり、より読みやすいよう、いくつかの [Notation] 宣言が使えます。
しかし、Coq の組み込みの表記と衝突しないよう、少し気をつける必要があります
(手軽さを維持しつつ！)。
特に、[aexp] と [bexp] については、
すでに定義した数値演算子やブール演算子との混同を避けるために、
新しい表記は導入しません。
(同様の理由により、条件文に対しては通常使われる [IF] の代わりに
[IFB] というキーワードを使います。) *)
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
(* For example, here is the factorial function again, written as a
formal definition to Coq: *)
(** 例えば先の階乗関数を Coq での形式的な定義として記述し直すと、
以下のようになります。*)
Definition fact_in_coq : com :=
Z ::= AId X;
Y ::= ANum 1;
WHILE BNot (BEq (AId Z) (ANum 0)) DO
Y ::= AMult (AId Y) (AId Z);
Z ::= AMinus (AId Z) (ANum 1)
END.
(* ####################################################### *)
(* ** Examples *)
(** ** 例 *)
(* Here are some more examples... *)
(** 以下に、さらなる例を挙げます。 *)
(* Assignment: *)
(** 割り当て: *)
Definition plus2 : com :=
X ::= (APlus (AId X) (ANum 2)).
Definition XtimesYinZ : com :=
Z ::= (AMult (AId X) (AId Y)).
Definition subtract_slowly_body : com :=
Z ::= AMinus (AId Z) (ANum 1) ;
X ::= AMinus (AId X) (ANum 1).
(* Loops: *)
(** ループ: *)
Definition subtract_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
subtract_slowly_body
END.
Definition subtract_3_from_5_slowly : com :=
X ::= ANum 3 ;
Z ::= ANum 5 ;
subtract_slowly.
(* An infinite loop: *)
(** 無限ループ: *)
Definition loop : com :=
WHILE BTrue DO
SKIP
END.
(* Factorial again (broken up into smaller pieces this time, for
convenience when we come back to proving things about it
later). *)
(** 階乗関数再び (あとで戻って証明するとき便利なように、
細かい部品に分割してあります)。 *)
Definition fact_body : com :=
Y ::= AMult (AId Y) (AId Z) ;
Z ::= AMinus (AId Z) (ANum 1).
Definition fact_loop : com :=
WHILE BNot (BEq (AId Z) (ANum 0)) DO
fact_body
END.
Definition fact_com : com :=
Z ::= AId X ;
Y ::= ANum 1 ;
fact_loop.
(* ################################################################ *)
(* * Evaluation *)
(** * 評価 *)
(* Next we need to define what it means to evaluate an Imp command.
[WHILE] loops actually make this a bit tricky... *)
(** 次に、Imp のコマンドの実行が何を意味するかを定義する必要があります。
[WHILE] ループは、これを少々扱いにくいものにしています ... *)
(* #################################### *)
(* ** Evaluation Function *)
(** ** 評価関数 *)
(* Here's a first try at an evaluation function for commands,
omitting [WHILE]. *)
(** 以下は [WHILE] 以外のコマンドの評価関数を得ようとした、最初の試みです。 *)
Fixpoint ceval_step1 (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ; c2 =>
let st' := ceval_step1 st c1 in
ceval_step1 st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step1 st c1
else ceval_step1 st c2
| WHILE b1 DO c1 END =>
st (* bogus *)
end.
(* Second try, using an extra numeric argument as a "step index" to
ensure that evaluation always terminates. *)
(** 次の試みでは、評価が常に停止することを保証するため、
数の引数を追加して「ステップ指数」として用いています。*)
Fixpoint ceval_step2 (st : state) (c : com) (i : nat) : state :=
match i with
| O => empty_state
| S i' =>
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ; c2 =>
let st' := ceval_step2 st c1 i' in
ceval_step2 st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step2 st c1 i'
else ceval_step2 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then let st' := ceval_step2 st c1 i' in
ceval_step2 st' c i'
else st
end
end.
(* _Note_: It is tempting to think that the index [i] here is
counting the "number of steps of evaluation." But if you look
closely you'll see that this is not the case: for example, in the
rule for sequencing, the same [i] is passed to both recursive
calls. Understanding the exact way that [i] is treated will be
important in the proof of [ceval__ceval_step], which is given as
an exercise below. *)
(** 注: ここでの指数 [i] は「評価のステップ数」を数えるものだろうか？
という点が気になります。しかしよく見ると、そうではないと分かります。
例えば、直列実行に対する規則では、2 つの再帰呼び出しに同じ [i] が渡されています。
[i] がどのように扱われているのかを正確に理解することは、
以下で演習問題として与えられている [ceval__ceval_step] の証明で重要となるでしょう。 *)
(* Third try, returning an [option state] instead of just a [state]
so that we can distinguish between normal and abnormal
termination. *)
(** 3 つ目の試みでは、単なる [state] の代わりに [option state] を返すようにしています。
こうすると、通常終了と異常終了を区別出来ます。*)
Fixpoint ceval_step3 (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ; c2 =>
match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c2 i'
| None => None
end
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step3 st c1 i'
else ceval_step3 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c i'
| None => None
end
else Some st
end
end.
(* We can improve the readability of this definition by introducing a
bit of auxiliary notation to hide the "plumbing" involved in
repeatedly matching against optional states. *)
(** オプション状態に対する場合分けに繰り返し含まれている「配管」を隠すための、
補助的なちょっとした記法を導入すると、この定義の読みやすさは改善出来ます。*)
Notation "'LETOPT' x <== e1 'IN' e2"
:= (match e1 with
| Some x => e2
| None => None
end)
(right associativity, at level 60).
Fixpoint ceval_step (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ; c2 =>
LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step st c1 i'
else ceval_step st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c i'
else Some st
end
end.
Definition test_ceval (st:state) (c:com) :=
match ceval_step st c 500 with
| None => None
| Some st => Some (st X, st Y, st Z)
end.
(*
Eval compute in
(test_ceval empty_state
(X ::= ANum 2;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)).
====>
Some (2, 0, 4)
*)
(* **** Exercise: 2 stars, recommended (pup_to_n) *)
(** **** 練習問題: ★★, recommended (pup_to_n) *)
(* Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y]. Make sure
your solution satisfies the test that follows. *)
(** [1] から [X] までの整数を変数 [Y] に足す (つまり [1 + 2 + ... + X])
Imp プログラムを書きなさい。下に示したテストを満たすことを確認しなさい。 *)
Definition pup_to_n : com :=
(* FILL IN HERE *) admit.
(*
Example pup_to_n_1 :
test_ceval (update empty_state X 5) pup_to_n
= Some (0, 15, 0).
Proof. reflexivity. Qed.
*)
(** [] *)
(* **** Exercise: 2 stars, optional (peven) *)
(** **** 練習問題: ★★, optional (peven) *)
(* Write a [While] program that sets [Z] to [0] if [X] is even and
sets [Z] to [1] otherwise. Use [ceval_test] to test your
program. *)
(** [X] が偶数だったら [Z] に [0] を、そうでなければ [Z] に [1] をセットする
[While] プログラムを書きなさい。テストには [ceval_test] を使いなさい。 *)
(* FILL IN HERE *)
(** [] *)
(* #################################### *)
(* ** Evaluation as a Relation *)
(** ** 関係としての評価 *)
(* Here's a better way: define [ceval] as a _relation_ rather than a
_function_ -- i.e., define it in [Prop] instead of [Type], as we
did for [aevalR] and [bevalR] above.
This is an important change. Besides freeing us from the
silliness of passing around step indices all over the place, it
gives us a lot more flexibility in the definition. For example,
if we added concurrency features to the language, we'd want the
definition of evaluation to be non-deterministic -- i.e., not only
would it not be total, it would not even be a partial function! *)
(** ここに改善策があります: [ceval] を関数ではなく関係 (_relation_) として定義しましょう。
つまり、上の [aevalR] と [bevalR] と同様に [Type] ではなく [Prop] で定義しましょう。
これは重要な変更です。
ステップ指数をすべての場所で引き回す馬鹿馬鹿しさから解放してくれるのに加え、
定義での柔軟性を与えてくれます。
例えば、もし言語に並行性の要素を導入したら、評価の定義を非決定的に書きたくなるでしょう。
つまり、その関数は全関数でないだけでなく、部分関数ですらないかも知れません！*)
(* We'll use the notation [c / st || st'] for our [ceval] relation,
that is [c / st || st'] means that executing program [c] in a
starting state [st] results in an ending state [st']. This can be
pronounced "[c] takes state [st] to [st']".
[[[
---------------- (E_Skip)
SKIP / st || st
aeval st a1 = n
-------------------------------- (E_Ass)
l := a1 / st || (update st l n)
c1 / st || st'
c2 / st' || st''
------------------- (E_Seq)
c1;c2 / st || st''
beval st b1 = true
c1 / st || st'
------------------------------------- (E_IfTrue)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
c2 / st || st'
------------------------------------- (E_IfFalse)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
------------------------------ (E_WhileEnd)
WHILE b1 DO c1 END / st || st
beval st b1 = true
c1 / st || st'
WHILE b1 DO c1 END / st' || st''
--------------------------------- (E_WhileLoop)
WHILE b1 DO c1 END / st || st''
]]]
*)
(** [ceavl] 関係に対する表記として [c / st || st'] を使います。
正確に言うと、[c / st || st'] と書いたらプログラム [c] を初期状態 [st] で評価すると、
その結果は最終状態 [st'] になる、ということを意味します。
これは「[c] は状態 [st] を [st'] に持っていく」とも言えます。
[[
---------------- (E_Skip)
SKIP / st || st
aeval st a1 = n
-------------------------------- (E_Ass)
l := a1 / st || (update st l n)
c1 / st || st'
c2 / st' || st''
------------------- (E_Seq)
c1;c2 / st || st''
beval st b1 = true
c1 / st || st'
------------------------------------- (E_IfTrue)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
c2 / st || st'
------------------------------------- (E_IfFalse)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
------------------------------ (E_WhileEnd)
WHILE b1 DO c1 END / st || st
beval st b1 = true
c1 / st || st'
WHILE b1 DO c1 END / st' || st''
--------------------------------- (E_WhileLoop)
WHILE b1 DO c1 END / st || st''
]]
*)
(* Here is the formal definition. (Make sure you understand
how it corresponds to the inference rules.) *)
(** 以下に形式的な定義を挙げます。
(上の推論規則とどのように対応するか、確認しておきましょう。) *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
SKIP / st || st
| E_Ass : forall st a1 n l,
aeval st a1 = n ->
(l ::= a1) / st || (update st l n)
| E_Seq : forall c1 c2 st st' st'',
c1 / st || st' ->
c2 / st' || st'' ->
(c1 ; c2) / st || st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
c1 / st || st' ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
c2 / st || st' ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
(WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop" ].
(* The cost of defining evaluation as a relation instead of a
function is that we now need to construct _proofs_ that some
program evaluates to some result state, rather than just letting
Coq's computation mechanism do it for us. *)
(** 評価を関数ではなく関係として定義することのコストは、
あるプログラムを実行した結果がとある状態になる、
というのを Coq の計算機構にやってもらうだけではなく、
その「証明」を構築する必要がある、ということです。*)
Example ceval_example1:
(X ::= ANum 2;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)
/ empty_state
|| (update (update empty_state X 2) Z 4).
Proof.
(* We must supply the intermediate state *)
apply E_Seq with (update empty_state X 2).
Case "assignment command".
apply E_Ass. reflexivity.
Case "if command".
apply E_IfFalse.
reflexivity.
apply E_Ass. reflexivity. Qed.
(* **** Exercise: 2 stars (ceval_example2) *)
(** **** 練習問題: ★★ (ceval_example2) *)
Example ceval_example2:
(X ::= ANum 0; Y ::= ANum 1; Z ::= ANum 2) / empty_state ||
(update (update (update empty_state X 0) Y 1) Z 2).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################ *)
(* ** Equivalence of Relational and Step-Indexed Evaluation *)
(** ** 関係による評価とステップ指数を利用した評価の等価性 *)
(* As with arithmetic and boolean expressions, we'd hope that
the two alternative definitions of evaluation actually boil down
to the same thing. This section shows that this is the case.
Make sure you understand the statements of the theorems and can
follow the structure of the proofs. *)
(** 算術式とブール式で行ったように、2 つの評価の定義が本当に、
結局のところ同じものになるのかを確認したくなるでしょう。
この章では、それを確認します。定理の主張を理解して、
証明の構造を追えることを確認しておいて下さい。*)
Theorem ceval_step__ceval: forall c st st',
(exists i, ceval_step st c i = Some st') ->
c / st || st'.
Proof.
intros c st st' H.
inversion H as [i E].
clear H.
generalize dependent st'.
generalize dependent st.
generalize dependent c.
induction i as [| i' ].
Case "i = 0 -- contradictory".
intros c st st' H. inversion H.
Case "i = S i'".
intros c st st' H.
com_cases (destruct c) SCase;
simpl in H; inversion H; subst; clear H.
SCase "SKIP". apply E_Skip.
SCase "::=". apply E_Ass. reflexivity.
SCase ";".
remember (ceval_step st c1 i') as r1. destruct r1.
SSCase "Evaluation of r1 terminates normally".
apply E_Seq with s.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSCase "Otherwise -- contradiction".
inversion H1.
SCase "IFB".
remember (beval st b) as r. destruct r.
SSCase "r = true".
apply E_IfTrue. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SSCase "r = false".
apply E_IfFalse. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SCase "WHILE". remember (beval st b) as r. destruct r.
SSCase "r = true".
remember (ceval_step st c i') as r1. destruct r1.
SSSCase "r1 = Some s".
apply E_WhileLoop with s. rewrite Heqr. reflexivity.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSSCase "r1 = None".
inversion H1.
SSCase "r = false".
inversion H1.
apply E_WhileEnd.
rewrite Heqr. subst. reflexivity. Qed.
(* **** Exercise: 4 stars (ceval_step__ceval_inf) *)
(** **** 練習問題: ★★★★ (ceval_step__ceval_inf) *)
(* Write an informal proof of [ceval_step__ceval], following the
usual template. (The template for case analysis on an inductively
defined value should look the same as for induction, except that
there is no induction hypothesis.) Make your proof communicate
the main ideas to a human reader; do not simply transcribe the
steps of the formal proof.
(* FILL IN HERE *)
[]
*)
(** いつものテンプレートにのっとって、
[ceval_step__ceval] の形式的でない証明を書きましょう。
(帰納的に定義された値の場合分けに対するテンプレートは、
帰納法の仮定がないこと以外は帰納法と同じ見た目になるはずです。)
単に形式的な証明のステップを書き写すだけでなく、
人間の読者に主要な考えが伝わるようにしなさい。
(* FILL IN HERE *)
[]
*)
Theorem ceval_step_more: forall i1 i2 st st' c,
i1 <= i2 ->
ceval_step st c i1 = Some st' ->
ceval_step st c i2 = Some st'.
Proof.
induction i1 as [|i1']; intros i2 st st' c Hle Hceval.
Case "i1 = 0".
inversion Hceval.
Case "i1 = S i1'".
destruct i2 as [|i2']. inversion Hle.
assert (Hle': i1' <= i2') by omega.
com_cases (destruct c) SCase.
SCase "SKIP".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase "::=".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase ";".
simpl in Hceval. simpl.
remember (ceval_step st c1 i1') as st1'o.
destruct st1'o.
SSCase "st1'o = Some".
symmetry in Heqst1'o.
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "st1'o = None".
inversion Hceval.
SCase "IFB".
simpl in Hceval. simpl.
remember (beval st b) as bval.
destruct bval; apply (IHi1' i2') in Hceval; assumption.
SCase "WHILE".
simpl in Hceval. simpl.
destruct (beval st b); try assumption.
remember (ceval_step st c i1') as st1'o.
destruct st1'o.
SSCase "st1'o = Some".
symmetry in Heqst1'o.
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite -> Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "i1'o = None".
simpl in Hceval. inversion Hceval. Qed.
(* **** Exercise: 3 stars, recommended (ceval__ceval_step) *)
(** **** 練習問題: ★★★, recommended (ceval__ceval_step) *)
(* Finish the following proof. You'll need [ceval_step_more] in a
few places, as well as some basic facts about [<=] and [plus]. *)
(** 以下の証明を完成させなさい。何度か [ceval_step_more] が必要となり、
さらに [<=] と [plus] に関するいくつかの基本的な事実が必要となるでしょう。*)
Theorem ceval__ceval_step: forall c st st',
c / st || st' ->
exists i, ceval_step st c i = Some st'.
Proof.
intros c st st' Hce.
ceval_cases (induction Hce) Case.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem ceval_and_ceval_step_coincide: forall c st st',
c / st || st'
<-> exists i, ceval_step st c i = Some st'.
Proof.
intros c st st'.
split. apply ceval__ceval_step. apply ceval_step__ceval.
Qed.
(* ####################################################### *)
(* ** Determinacy of Evaluation *)
(** ** 実行の決定性 *)
(* Changing from a computational to a relational definition of
evaluation is a good move because it allows us to escape from the
artificial requirement (imposed by Coq's restrictions on Fixpoint
definitions) that evaluation should be a total function. But it
also raises a question: Is the second definition of evaluation
actually a partial function? That is, is it possible that,
beginning from the same state [st], we could evaluate some command
[c] in different ways to reach two different output states [st']
and [st'']?
In fact, this cannot happen: the evaluation relation [ceval] is a
partial function. Here's the proof: *)
(** 評価の定義を計算的なものから関係的なものに変更するのは、
評価は全関数であるべきという (Fixpoint の定義における
Coq の制限によって課せられる) 不自然な要求から逃れさせてくれる良い変更です。
しかしこれは、2 つ目の評価の定義は本当に部分関数なのか？という疑問ももたらします。
つまり、同じ状態 [st] から始めて、あるコマンド [c] を違った方法で評価し、
2 つの異なる出力状態 [st'] と [st''] に至るのは可能か？ということです。
実際には、こうなることはありません。評価関係 [ceval] は部分関数です。
以下に証明を挙げます: *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
ceval_cases (induction E1) Case;
intros st2 E2; inversion E2; subst.
Case "E_Skip". reflexivity.
Case "E_Ass". reflexivity.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Case "E_IfTrue".
SCase "b1 evaluates to true".
apply IHE1. assumption.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
SCase "b1 evaluates to false".
apply IHE1. assumption.
Case "E_WhileEnd".
SCase "b1 evaluates to true".
reflexivity.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H4. inversion H4.
SCase "b1 evaluates to false".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption. Qed.
(* Here's a slicker proof, using the fact that the relational and
step-indexed definition of evaluation are the same. *)
(** 以下に、より巧みな証明を示します。
これは関係による定義と指数を利用した定義の評価が同じである事実を利用しています。*)
Theorem ceval_deterministic' : forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 He1 He2.
apply ceval__ceval_step in He1.
apply ceval__ceval_step in He2.
inversion He1 as [i1 E1].
inversion He2 as [i2 E2].
apply ceval_step_more with (i2 := i1 + i2) in E1.
apply ceval_step_more with (i2 := i1 + i2) in E2.
rewrite E1 in E2. inversion E2. reflexivity.
omega. omega. Qed.
(* ####################################################### *)
(* * Reasoning About Programs *)
(** * プログラムの検証 *)
(* We'll get much deeper into systematic techniques for reasoning
about programs in Imp in the following chapters, but we can do
quite a bit just working with the bare definitions. This section
explores some examples. *)
(** ここから Imp におけるプログラムの検証に対する系統だったテクニックに深く関わっていきます。
しかし、その多くはむき出しの (もとの) 定義を扱うだけで出来ます。
この章では、いくつかの例を探します。*)
(* ** Basic Examples *)
(** ** 基本的な例 *)
Theorem plus2_spec : forall st n st',
st X = n ->
plus2 / st || st' ->
st' X = n + 2.
Proof.
intros st n st' HX Heval.
(* Inverting Heval essentially forces Coq to expand one
step of the ceval computation - in this case revealing
that st' must be st extended with the new value of X,
since plus2 is an assignment *)
inversion Heval. subst.
apply update_eq. Qed.
(* **** Exercise: 3 stars, recommended (XtimesYinZ_spec) *)
(** **** 練習問題: ★★★, recommended (XtimesYinZ_spec) *)
(* State and prove a specification of the XtimesYinZ Imp program. *)
(** XtimesYinZ の Imp プログラムの仕様を書いて証明しなさい。*)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 3 stars, recommended (loop_never_stops) *)
(** **** 練習問題: ★★★, recommended (loop_never_stops) *)
Theorem loop_never_stops : forall st st',
~(loop / st || st').
Proof.
intros st st' contra. unfold loop in contra.
remember (WHILE BTrue DO SKIP END) as loopdef.
(* Proceed by induction on the assumed derivation showing that
loopdef terminates. Most of the cases are immediately
contradictory (and so can be solved in one step with
[inversion]). *)
(* FILL IN HERE *) Admitted.
(** [] *)
Fixpoint no_whiles (c : com) : bool :=
match c with
| SKIP => true
| _ ::= _ => true
| c1 ; c2 => andb (no_whiles c1) (no_whiles c2)
| IFB _ THEN ct ELSE cf FI => andb (no_whiles ct) (no_whiles cf)
| WHILE _ DO _ END => false
end.
(* **** Exercise: 2 stars, optional (no_whilesR) *)
(** **** 練習問題: ★★, optional (no_whilesR) *)
(* The [no_whiles] property yields [true] on just those programs that
have no while loops. Using [Inductive], write a property
[no_whilesR] such that [no_whilesR c] is provable exactly when [c]
is a program with no while loops. Then prove its equivalence
with [no_whiles]. *)
(** 性質 [no_whiles] はプログラムが while ループを含まない場合 [true] を返します。
Inductive を使って [c] が while ループのないプログラムのとき証明可能な性質 [no_whilesR] を書きなさい。
さらに、それが [no_whiles] と等価であることを示しなさい。*)
Inductive no_whilesR: com -> Prop :=
(* FILL IN HERE *)
.
Theorem no_whiles_eqv:
forall c, no_whiles c = true <-> no_whilesR c.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 4 stars, optional (no_whiles_terminating) *)
(** **** 練習問題: ★★★★, optional (no_whiles_terminating) *)
(* Imp programs that don't involve while loops always terminate.
State and prove a theorem that says this. *)
(** while ループを含まない Imp プログラムは必ず停止します。
これを定理として記述し、証明しなさい。*)
(* (Use either [no_whiles] or [no_whilesR], as you prefer.) *)
(** ([no_whiles] と [no_whilesR] のどちらでも好きなほうを使いなさい。) *)
(* FILL IN HERE *)
(** [] *)
(* ** Proving a Program Correct (Optional) *)
(** ** プログラム正当性 (Optional) *)
(* Recall the factorial program: *)
(** 階乗のプログラムを思い出しましょう: *)
Print fact_body. Print fact_loop. Print fact_com.
(* Here is an alternative "mathematical" definition of the factorial
function: *)
(** 階乗関数の別の「数学的な」定義を以下に示します: *)
Fixpoint real_fact (n:nat) : nat :=
match n with
| O => 1
| S n' => n * (real_fact n')
end.
(* We would like to show that they agree -- if we start [fact_com] in
a state where variable [X] contains some number [x], then it will
terminate in a state where variable [Y] contains the factorial of
[x].
To show this, we rely on the critical idea of a _loop
invariant_. *)
(** 変数 [X] がある数 [x] を持つ状態で [fact_com] を実行すると、
変数 [Y] が [x] の階乗の値を持つ状態で停止する、ということを示したくなります。
これを示すため、ループ不変式 (_loop invariant_) という重要な概念を使います。 *)
Definition fact_invariant (x:nat) (st:state) :=
(st Y) * (real_fact (st Z)) = real_fact x.
Theorem fact_body_preserves_invariant: forall st st' x,
fact_invariant x st ->
st Z <> 0 ->
fact_body / st || st' ->
fact_invariant x st'.
Proof.
unfold fact_invariant, fact_body.
intros st st' x Hm HZnz He.
inversion He; subst; clear He.
inversion H1; subst; clear H1.
inversion H4; subst; clear H4.
unfold update. simpl.
(* Show that st Z = S z' for some z' *)
destruct (st Z) as [| z'].
apply ex_falso_quodlibet. apply HZnz. reflexivity.
rewrite <- Hm. rewrite <- mult_assoc.
replace (S z' - 1) with z' by omega.
reflexivity. Qed.
Theorem fact_loop_preserves_invariant : forall st st' x,
fact_invariant x st ->
fact_loop / st || st' ->
fact_invariant x st'.
Proof.
intros st st' x H Hce.
remember fact_loop as c.
ceval_cases (induction Hce) Case;
inversion Heqc; subst; clear Heqc.
Case "E_WhileEnd".
(* trivial when the loop doesn't run... *)
assumption.
Case "E_WhileLoop".
(* if the loop does run, we know that fact_body preserves
fact_invariant -- we just need to assemble the pieces *)
apply IHHce2.
apply fact_body_preserves_invariant with st;
try assumption.
intros Contra. simpl in H0; subst.
rewrite Contra in H0. inversion H0.
reflexivity. Qed.
Theorem guard_false_after_loop: forall b c st st',
(WHILE b DO c END) / st || st' ->
beval st' b = false.
Proof.
intros b c st st' Hce.
remember (WHILE b DO c END) as cloop.
ceval_cases (induction Hce) Case;
inversion Heqcloop; subst; clear Heqcloop.
Case "E_WhileEnd".
assumption.
Case "E_WhileLoop".
apply IHHce2. reflexivity. Qed.
(* Patching it all together... *)
(** これらをすべてつなぎ合わせましょう... *)
Theorem fact_com_correct : forall st st' x,
st X = x ->
fact_com / st || st' ->
st' Y = real_fact x.
Proof.
intros st st' x HX Hce.
inversion Hce; subst; clear Hce.
inversion H1; subst; clear H1.
inversion H4; subst; clear H4.
inversion H1; subst; clear H1.
rename st' into st''. simpl in H5.
(* The invariant is true before the loop runs... *)
remember (update (update st Z (st X)) Y 1) as st'.
assert (fact_invariant (st X) st').
subst. unfold fact_invariant, update. simpl. omega.
(* ...so when the loop is done running, the invariant
is maintained *)
assert (fact_invariant (st X) st'').
apply fact_loop_preserves_invariant with st'; assumption.
unfold fact_invariant in H0.
(* Finally, if the loop terminated, then Z is 0; so Y must be
factorial of X *)
apply guard_false_after_loop in H5. simpl in H5.
destruct (st'' Z).
Case "st'' Z = 0". simpl in H0. omega.
Case "st'' Z > 0 (impossible)". inversion H5.
Qed.
(* One might wonder whether all this work with poking at states and
unfolding definitions could be ameliorated with some more powerful
lemmas and/or more uniform reasoning principles... Indeed, this is
exactly the topic of the next chapter ([Hoare.v])! *)
(** この、状態をつっついて定義を展開するような全体のやり方を、何かより強力な補題や、
より一貫性のある推論原理で改善できないのかと思う人もいるかもしれません。
実は、それがまさに次の章([Hoare_J.v])の主題です! *)
(* **** Exercise: 4 stars, optional (subtract_slowly_spec) *)
(** **** 練習問題: ★★★★, optional (subtract_slowly_spec) *)
(** 上の [fact_com] の仕様、および以下の不変式をガイドとして、
subtract_slowly の仕様を証明しなさい。 *)
Definition ss_invariant (x:nat) (z:nat) (st:state) :=
minus (st Z) (st X) = minus z x.
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(* * Additional Exercises *)
(** * 追加の練習問題 *)
(* **** Exercise: 4 stars, optional (add_for_loop) *)
(** **** 練習問題: ★★★★, optional (add_for_loop) *)
(* Add C-style [for] loops to the language of commands, update the
[ceval] definition to define the semantics of [for] loops, and add
cases for [for] loops as needed so that all the proofs in this file
are accepted by Coq.
A [for] loop should be parameterized by (a) a statement executed
initially, (b) a test that is run on each iteration of the loop to
determine whether the loop should continue, (c) a statement
executed at the end of each loop iteration, and (d) a statement
that makes up the body of the loop. (You don't need to worry
about making up a concrete Notation for [for] loops, but feel free
to play with this too if you like.) *)
(** C 風の [for] ループをコマンドの言語に追加し、[ceval] の定義を
[for] ループの意味も与えるよう更新して、
このファイルにあるすべての証明が Coq に通るよう、
必要なところへ [for] ループに対する場合分けを追加しなさい。
[for] ループは (a) 初めに実行される主張、
(b) 各繰り返しで実行される、ループを続けてよいか決定するテスト、
(c) 各ループの繰り返しの最後に実行される主張、および
(d) ループの本体を構成する主張によってパラメタ化されていなければなりません。
([for] ループに対する具体的な表記の構成を気にする必要はありませんが、
やりたければ自由にやって構いません。) *)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 3 stars, optional (short_circuit) *)
(** **** 練習問題: ★★★, optional (short_circuit) *)
(* Most modern programming languages use a "short-circuit" evaluation
rule for boolean [and]: to evaluate [BAnd b1 b2], first evaluate
[b1]. If it evaluates to [false], then the entire [BAnd]
expression evaluates to [false] immediately, without evaluating
[b2]. Otherwise, [b2] is evaluated to determine the result of the
[BAnd] expression.
Write an alternate version of [beval] that performs short-circuit
evaluation of [BAnd] in this manner, and prove that it is
equivalent to [beval]. *)
(** 多くのモダンなプログラミング言語はブール演算子 [and] に対し、
「省略した」実行を使っています。
[BAnd b1 b2] を実行するには、まず [b1] を評価します。
それが [false] に評価されるならば、[b2] の評価はせず、
すぐに [BAnd] 式全体の結果を [false] に評価します。
そうでなければ、[BAnd] 式の結果を決定するため、[b2] が評価されます。
このように [BAnd] を省略して評価する、別のバージョンの [beval] を書き、
それが [beavl] と等価であることを証明しなさい。 *)
(* FILL IN HERE *)
(* **** Exercise: 4 stars, recommended (stack_compiler) *)
(** **** 練習問題: ★★★★, recommended (stack_compiler) *)
(* HP Calculators, programming languages like Forth and Postscript,
and abstract machines like the Java Virtual Machine all evaluate
arithmetic expressions using a stack. For instance, the expression
<<
(2*3)+(3*(4-2))
>>
would be entered as
<<
2 3 * 3 4 2 - * +
>>
and evaluated like this:
<<
[] | 2 3 * 3 4 2 - * +
[2] | 3 * 3 4 2 - * +
[3, 2] | * 3 4 2 - * +
[6] | 3 4 2 - * +
[3, 6] | 4 2 - * +
[4, 3, 6] | 2 - * +
[2, 4, 3, 6] | - * +
[2, 3, 6] | * +
[6, 6] | +
[12] |
>>
The task of this exercise is to write a small compiler that
translates [aexp]s into stack machine instructions, and to prove its
correctness.
The instruction set for our stack language will consist of the
following instructions:
- [SPush n]: Push the number [n] on the stack.
- [SLoad X]: Load the identifier [X] from the store and push it
on the stack
- [SPlus]: Pop the two top numbers from the stack, add them, and
push the result onto the stack.
- [SMinus]: Similar, but subtract.
- [SMult]: Similar, but multiply.
*)
(** HP の電卓、Forth や Postscript などのプログラミング言語、
および Java Virtual Machine などの抽象機械はすべて、スタックを使って算術式を評価します。
例えば、
<<
(2*3)+(3*(4-2))
>>
という式は
<<
2 3 * 3 4 2 - * +
>>
と入力され、以下のように実行されるでしょう:
<<
[] | 2 3 * 3 4 2 - * +
[2] | 3 * 3 4 2 - * +
[3, 2] | * 3 4 2 - * +
[6] | 3 4 2 - * +
[3, 6] | 4 2 - * +
[4, 3, 6] | 2 - * +
[2, 4, 3, 6] | - * +
[2, 3, 6] | * +
[6, 6] | +
[12] |
>>
この練習問題のタスクは、[aexp] をスタック機械の命令列に変換する小さなコンパイラを書き、その正当性を証明することです。
スタック言語の命令セットは、以下の命令から構成されます:
- [SPush n]: 数 [n] をスタックにプッシュする。
- [SLoad X]: ストアから識別子 [X] に対応する値を読み込み、スタックにプッシュする。
- [SPlus]: スタックの先頭の 2 つの数をポップし、それらを足して、
結果をスタックにプッシュする。
- [SMinus]: 上と同様。ただし引く。
- [SMult]: 上と同様。ただし掛ける。
*)
Inductive sinstr : Type :=
| SPush : nat -> sinstr
| SLoad : id -> sinstr
| SPlus : sinstr
| SMinus : sinstr
| SMult : sinstr.
(* Write a function to evaluate programs in the stack language. It
takes as input a state, a stack represented as a list of
numbers (top stack item is the head of the list), and a program
represented as a list of instructions, and returns the stack after
executing the program. Test your function on the examples below.
Note that the specification leaves unspecified what to do when
encountering an [SPlus], [SMinus], or [SMult] instruction if the
stack contains less than two elements. In a sense it is
immaterial, since our compiler will never emit such a malformed
program. However, when you do the correctness proof you may find
some choices makes the proof easier than others. *)
(** スタック言語のプログラムを評価するための関数を書きなさい。
入力として、状態、数のリストとして表現されたスタック
(スタックの先頭要素はリストの先頭)、
および命令のリストとして表現されたプログラムを受け取り、
受け取ったプログラムの実行した後のスタックを返します。
下にある例で、その関数のテストをしなさい。
上の仕様では、スタックが 2 つ未満の要素しか含まずに [SPlus] や [SMinus]、
[SMult] 命令に至った場合を明示していないままなことに注意しましょう。
我々のコンパイラはそのような奇形のプログラムは生成しないので、
これは重要でないという意味です。
しかし正当性の証明をするときは、いくつかの選択のほうが証明をより簡単にすることに気づくかもしれません。*)
Fixpoint s_execute (st : state) (stack : list nat)
(prog : list sinstr)
: list nat :=
(* FILL IN HERE *) admit.
Example s_execute1 :
s_execute empty_state []
[SPush 5, SPush 3, SPush 1, SMinus]
= [2, 5].
(* FILL IN HERE *) Admitted.
Example s_execute2 :
s_execute (update empty_state X 3) [3,4]
[SPush 4, SLoad X, SMult, SPlus]
= [15, 4].
(* FILL IN HERE *) Admitted.
(* Next, write a function which compiles an [aexp] into a stack
machine program. The effect of running the program should be the
same as pushing the value of the expression on the stack. *)
(** 次に、[aexp] をスタック機械のプログラムにコンパイルする関数を書きなさい。
このプログラムを実行する影響は、もとの式の値をスタックに積むことと同じでなければなりません。*)
Fixpoint s_compile (e : aexp) : list sinstr :=
(* FILL IN HERE *) admit.
(*
Example s_compile1 :
s_compile (AMinus (AId X) (AMult (ANum 2) (AId Y)))
= [SLoad X, SPush 2, SLoad Y, SMult, SMinus].
Proof. reflexivity. Qed.
*)
(* Finally, prove the following theorem, stating that the [compile]
function behaves correctly. You will need to start by stating a
more general lemma to get a usable induction hypothesis. *)
(** 最後に、[compile] 関数が正しく振る舞うことを述べている以下の定理を証明しなさい。
まずは使える帰納法の仮定を得るため、より一般的な補題を述べる必要があるでしょう。*)
(* FILL IN HERE *)
Theorem s_compile_correct : forall (st : state) (e : aexp),
s_execute st [] (s_compile e) = [ aeval st e ].
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Base Mixed Mode Clock Manager (MMCM)
// /___/ /\ Filename : MMCME2_BASE.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 05/27/10 - Initial version
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module MMCME2_BASE (
CLKFBOUT,
CLKFBOUTB,
CLKOUT0,
CLKOUT0B,
CLKOUT1,
CLKOUT1B,
CLKOUT2,
CLKOUT2B,
CLKOUT3,
CLKOUT3B,
CLKOUT4,
CLKOUT5,
CLKOUT6,
LOCKED,
CLKFBIN,
CLKIN1,
PWRDWN,
RST
);
parameter BANDWIDTH = "OPTIMIZED";
parameter real CLKFBOUT_MULT_F = 5.000;
parameter real CLKFBOUT_PHASE = 0.000;
parameter real CLKIN1_PERIOD = 0.000;
parameter real CLKOUT0_DIVIDE_F = 1.000;
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
parameter real CLKOUT0_PHASE = 0.000;
parameter integer CLKOUT1_DIVIDE = 1;
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
parameter real CLKOUT1_PHASE = 0.000;
parameter integer CLKOUT2_DIVIDE = 1;
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
parameter real CLKOUT2_PHASE = 0.000;
parameter integer CLKOUT3_DIVIDE = 1;
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
parameter real CLKOUT3_PHASE = 0.000;
parameter CLKOUT4_CASCADE = "FALSE";
parameter integer CLKOUT4_DIVIDE = 1;
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
parameter real CLKOUT4_PHASE = 0.000;
parameter integer CLKOUT5_DIVIDE = 1;
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
parameter real CLKOUT5_PHASE = 0.000;
parameter integer CLKOUT6_DIVIDE = 1;
parameter real CLKOUT6_DUTY_CYCLE = 0.500;
parameter real CLKOUT6_PHASE = 0.000;
parameter integer DIVCLK_DIVIDE = 1;
parameter real REF_JITTER1 = 0.010;
parameter STARTUP_WAIT = "FALSE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output CLKFBOUT;
output CLKFBOUTB;
output CLKOUT0;
output CLKOUT0B;
output CLKOUT1;
output CLKOUT1B;
output CLKOUT2;
output CLKOUT2B;
output CLKOUT3;
output CLKOUT3B;
output CLKOUT4;
output CLKOUT5;
output CLKOUT6;
output LOCKED;
input CLKFBIN;
input CLKIN1;
input PWRDWN;
input RST;
// define constants
localparam MODULE_NAME = "MMCME2_BASE";
wire OPEN_DRDY;
wire OPEN_PSDONE;
wire OPEN_FBS;
wire OPEN_INS;
wire [15:0] OPEN_DO;
MMCME2_ADV #(
.BANDWIDTH(BANDWIDTH),
.CLKFBOUT_MULT_F(CLKFBOUT_MULT_F),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.CLKIN2_PERIOD(10),
.CLKOUT0_DIVIDE_F(CLKOUT0_DIVIDE_F),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_CASCADE(CLKOUT4_CASCADE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE(CLKOUT5_PHASE),
.CLKOUT6_DIVIDE(CLKOUT6_DIVIDE),
.CLKOUT6_DUTY_CYCLE(CLKOUT6_DUTY_CYCLE),
.CLKOUT6_PHASE(CLKOUT6_PHASE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.REF_JITTER1(REF_JITTER1),
.STARTUP_WAIT(STARTUP_WAIT)
) mmcm_adv_1 (
.CLKFBOUT (CLKFBOUT),
.CLKFBOUTB (CLKFBOUTB),
.CLKFBSTOPPED(OPEN_FBS),
.CLKINSTOPPED(OPEN_INS),
.CLKOUT0 (CLKOUT0),
.CLKOUT0B (CLKOUT0B),
.CLKOUT1 (CLKOUT1),
.CLKOUT1B (CLKOUT1B),
.CLKOUT2 (CLKOUT2),
.CLKOUT2B (CLKOUT2B),
.CLKOUT3 (CLKOUT3),
.CLKOUT3B (CLKOUT3B),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.CLKOUT6 (CLKOUT6),
.DO (OPEN_DO),
.DRDY (OPEN_DRDY),
.LOCKED (LOCKED),
.PSDONE(OPEN_PSDONE),
.CLKFBIN (CLKFBIN),
.CLKIN1 (CLKIN1),
.CLKIN2 (1'b0),
.CLKINSEL(1'b1),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(PWRDWN),
.RST (RST)
);
endmodule
`endcelldefine
|
// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
`timescale 1ns/100ps
module RAM(
i_addr,
i_enable_x,
i_write_x,
i_data,
o_data);
parameter delay = 10;
parameter depth = 16;
parameter width = 8;
input [depth - 1:0] i_addr;
input i_enable_x;
input i_write_x;
input [width - 1:0] i_data;
output [width - 1:0] o_data;
reg [width - 1:0] o_data;
reg [width - 1:0] r_ram[0:2**depth];
reg [depth - 1:0] r_addr;
reg r_enable_x;
reg r_write_x;
reg [width - 1:0] r_data;
always r_addr = #delay i_addr;
always r_enable_x = #delay i_enable_x;
always r_write_x = #delay i_write_x;
always r_data = #delay i_data;
always @ (r_addr or r_enable_x or r_write_x or r_data) begin
if (r_enable_x) begin
o_data <= {width{1'bz}};
end else if (r_write_x) begin
o_data <= r_ram[r_addr];
end else begin
o_data <= {width{1'bx}};
r_ram[r_addr] <= r_data;
end
end
endmodule // module RAM
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : EP_MEM.v
// Version : 1.3
//--
//-- Description: Endpoint Memory: 8KB organized as 4 x (512 DW) BlockRAM banks.
//-- Block RAM Port A: Read Port
//-- Block RAM Port B: Write Port
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module EP_MEM (
clk,
a_rd_a_i_0, // [8:0] Port A Read Address Bank 0
a_rd_d_o_0, // [31:0] Port A Read Data Bank 0
a_rd_en_i_0, // Port A Read Enable Bank 0
b_wr_a_i_0, // [8:0] Port B Write Address Bank 0
b_wr_d_i_0, // [31:0] Port B Write Data Bank 0
b_wr_en_i_0, // Port B Write Enable Bank 0
b_rd_d_o_0, // [31:0] Port B Read Data Bank 0
b_rd_en_i_0, // Port B Read Enable Bank 0
a_rd_a_i_1, // [8:0] Port A Read Address Bank 1
a_rd_d_o_1, // [31:0] Port A Read Data Bank 1
a_rd_en_i_1,
b_wr_a_i_1, // [8:0] Port B Write Address Bank 1
b_wr_d_i_1, // [31:0] Port B Write Data Bank 1
b_wr_en_i_1, // Port B Write Enable Bank 1
b_rd_d_o_1, // [31:0] Port B Read Data Bank 1
b_rd_en_i_1, // Port B Read Enable Bank 1
a_rd_a_i_2, // [8:0] Port A Read Address Bank 2
a_rd_d_o_2, // [31:0] Port A Read Data Bank 2
a_rd_en_i_2,
b_wr_a_i_2, // [8:0] Port B Write Address Bank 2
b_wr_d_i_2, // [31:0] Port B Write Data Bank 2
b_wr_en_i_2, // Port B Write Enable Bank 2
b_rd_d_o_2, // [31:0] Port B Read Data Bank 2
b_rd_en_i_2, // Port B Read Enable Bank 2
a_rd_a_i_3, // [8:0] Port A Read Address Bank 3
a_rd_d_o_3, // [31:0] Port A Read Data Bank 3
a_rd_en_i_3,
b_wr_a_i_3, // [8:0] Port B Write Address Bank 3
b_wr_d_i_3, // [31:0] Port B Write Data Bank 3
b_wr_en_i_3, // Port B Write Enable Bank 3
b_rd_d_o_3, // [31:0] Port B Read Data Bank 3
b_rd_en_i_3 // Port B Read Enable Bank 3
);
input clk;
input [08:00] a_rd_a_i_0;
output [31:00] a_rd_d_o_0;
input a_rd_en_i_0;
input [08:00] b_wr_a_i_0;
input [31:00] b_wr_d_i_0;
input b_wr_en_i_0;
output [31:00] b_rd_d_o_0;
input b_rd_en_i_0;
input [08:00] a_rd_a_i_1;
output [31:00] a_rd_d_o_1;
input a_rd_en_i_1;
input [08:00] b_wr_a_i_1;
input [31:00] b_wr_d_i_1;
input b_wr_en_i_1;
output [31:00] b_rd_d_o_1;
input b_rd_en_i_1;
input [08:00] a_rd_a_i_2;
output [31:00] a_rd_d_o_2;
input a_rd_en_i_2;
input [08:00] b_wr_a_i_2;
input [31:00] b_wr_d_i_2;
input b_wr_en_i_2;
output [31:00] b_rd_d_o_2;
input b_rd_en_i_2;
input [08:00] a_rd_a_i_3;
output [31:00] a_rd_d_o_3;
input a_rd_en_i_3;
input [08:00] b_wr_a_i_3;
input [31:00] b_wr_d_i_3;
input b_wr_en_i_3;
output [31:00] b_rd_d_o_3;
input b_rd_en_i_3;
//----------------------------------------------------------------
//
// 4 x 512 DWs Buffer Banks (512 x 32 bits + 512 x 4 bits)
// 1 each for IO, Mem32, Mem64 and EROM
//----------------------------------------------------------------
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_io_mem_inst (
.DOA(a_rd_d_o_0[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_0[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_0[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_0[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk), // 1-bit A port clock input
.CLKB(clk), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_0[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_0), // 1-bit A port enable input
.ENB(b_rd_en_i_0), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_0, b_wr_en_i_0, b_wr_en_i_0, b_wr_en_i_0}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_mem32_inst (
.DOA(a_rd_d_o_1[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_1[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_1[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_1[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk), // 1-bit A port clock input
.CLKB(clk), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_1[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_1), // 1-bit A port enable input
.ENB(b_rd_en_i_1), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_1, b_wr_en_i_1, b_wr_en_i_1, b_wr_en_i_1}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_mem64_inst (
.DOA(a_rd_d_o_2[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_2[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_2[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_2[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk), // 1-bit A port clock input
.CLKB(clk), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_2[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_2), // 1-bit A port enable input
.ENB(b_rd_en_i_2), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_2, b_wr_en_i_2, b_wr_en_i_2, b_wr_en_i_2}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_mem_erom_inst (
.DOA(a_rd_d_o_3[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_3[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_3[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_3[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk), // 1-bit A port clock input
.CLKB(clk), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_3[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_3), // 1-bit A port enable input
.ENB(b_rd_en_i_3), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_3, b_wr_en_i_3, b_wr_en_i_3, b_wr_en_i_3}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
endmodule
|
//
// Designed by Qiang Wu
// 16K bytes, 32bit interface
`timescale 1ns/1ps
module lr0(clk, addr, data_in, data_out, we, en, reset);
input clk;
input [13:2] addr;
input [31:0] data_in;
output [31:0] data_out;
input [3:0] we;
input en;
input reset;
RAMB16_S4_altera localram0(
.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[3:0]),
.wren (we[0]),
.q (data_out[3:0])
);
defparam localram0.init_file = "lr_00.mif";
RAMB16_S4_altera localram1(
.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[7:4]),
.wren (we[0]),
.q (data_out[7:4])
);
defparam localram1.init_file = "lr_11.mif";
RAMB16_S4_altera localram2(
.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[11:8]),
.wren (we[1]),
.q (data_out[11:8])
);
defparam localram2.init_file = "lr_22.mif";
RAMB16_S4_altera localram3(
.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[15:12]),
.wren (we[1]),
.q (data_out[15:12])
);
defparam localram3.init_file = "lr_33.mif";
RAMB16_S4_altera localram4(
.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[19:16]),
.wren (we[2]),
.q (data_out[19:16])
);
defparam localram4.init_file = "lr_44.mif";
RAMB16_S4_altera localram5(
.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[23:20]),
.wren (we[2]),
.q (data_out[23:20])
);
defparam localram5.init_file = "lr_55.mif";
RAMB16_S4_altera localram6(
.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[27:24]),
.wren (we[3]),
.q (data_out[27:24])
);
defparam localram6.init_file = "lr_66.mif";
RAMB16_S4_altera localram7(
.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[31:28]),
.wren (we[3]),
.q (data_out[31:28])
);
defparam localram7.init_file = "lr_77.mif";
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2O_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A2BB2O_PP_SYMBOL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a2bb2o (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2O_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BAI_2_V
`define SKY130_FD_SC_HS__O21BAI_2_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21bai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o21bai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
sky130_fd_sc_hs__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BAI_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR3_BLACKBOX_V
`define SKY130_FD_SC_LS__XNOR3_BLACKBOX_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__xnor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR3_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BA_1_V
`define SKY130_FD_SC_HDLL__O21BA_1_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21ba_1 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21ba_1 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BA_1_V
|
`default_nettype none
module scheduler1_commit_entry #(
parameter ENTRY_ID = 6'h00
)(
//System
input wire iCLOCK,
input wire inRESET,
//LOCK
input wire iLOCK,
//Exception
input wire iRESTART_VALID,
//Regist
input wire [5:0] iREGIST_POINTER,
input wire iREGIST_0_VALID,
input wire iREGIST_0_MAKE_FLAGS,
input wire iREGIST_0_WRITEBACK,
input wire [3:0] iREGIST_0_FLAGS_PREG_POINTER,
input wire [5:0] iREGIST_0_DEST_PREG_POINTER,
input wire [4:0] iREGIST_0_DEST_LREG_POINTER,
input wire iREGIST_0_DEST_SYSREG,
input wire iREGIST_0_EX_BRANCH,
input wire iREGIST_1_VALID,
input wire iREGIST_1_MAKE_FLAGS,
input wire iREGIST_1_WRITEBACK,
input wire [3:0] iREGIST_1_FLAGS_PREG_POINTER,
input wire [5:0] iREGIST_1_DEST_PREG_POINTER,
input wire [4:0] iREGIST_1_DEST_LREG_POINTER,
input wire iREGIST_1_DEST_SYSREG,
input wire iREGIST_1_EX_BRANCH,
input wire [31:0] iREGIST_PC,
//Commit Pointer
input wire iCOMMIT_VALID,
//EX-END
input wire iEXEND_ALU0_VALID,
input wire [5:0] iEXEND_ALU0_COMMIT_TAG,
input wire iEXEND_ALU1_VALID,
input wire [5:0] iEXEND_ALU1_COMMIT_TAG,
input wire iEXEND_ALU2_VALID,
input wire [5:0] iEXEND_ALU2_COMMIT_TAG,
input wire iEXEND_ALU3_VALID,
input wire [5:0] iEXEND_ALU3_COMMIT_TAG,
//Infomation
output wire oINFO_VALID,
output wire oINFO_MAKE_FLAGS_VALID,
output wire oINFO_WRITEBACK_VALID,
output wire [31:0] oINFO_PC,
output wire [3:0] oINFO_FLAGS_PREG_POINTER,
output wire [5:0] oINFO_DEST_PREG_POINTER,
output wire [4:0] oINFO_DEST_LREG_POINTER,
output wire oINFO_DEST_SYSREG,
output wire oINFO_EX_BRANCH,
output wire oINFO_EX_END,
output wire oINFO_FREE
);
/****************************************
Previous <-> This
****************************************/
/*List Format
PC, EX_END(LDST_END)
*/
reg [1:0] b_state;
reg [31:0] b_pc;
reg b_make_flags_validl;
reg b_writeback;
reg [3:0] b_flags_preg_pointer;
reg [5:0] b_destination_regname;
reg [4:0] b_logic_destination;
reg b_dest_sysreg;
reg b_ex_branch;
wire [5:0] w_regist_pointer0;
wire [5:0] w_regist_pointer1;
assign w_regist_pointer0 = iREGIST_POINTER;
assign w_regist_pointer1 = iREGIST_POINTER + 6'h1;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= 2'h0;
b_pc <= {32{1'b0}};
b_make_flags_validl <= 1'b0;
b_writeback <= 1'b0;
b_flags_preg_pointer <= 4'h0;
b_destination_regname <= {6{1'b0}};
b_logic_destination <= {5{1'b0}};
b_dest_sysreg <= 1'b0;
b_ex_branch <= 1'b0;
end
else if(b_state == 2'h3 || iRESTART_VALID)begin
b_state <= 2'h0;
b_pc <= {32{1'b0}};
b_make_flags_validl <= 1'b0;
b_writeback <= 1'b0;
b_flags_preg_pointer <= 4'h0;
b_destination_regname <= {6{1'b0}};
b_logic_destination <= {5{1'b0}};
b_dest_sysreg <= 1'b0;
b_ex_branch <= 1'b0;
end
else begin
case(b_state)
2'h0 : //Entry Regist Wait
begin
if(!iLOCK)begin
if(iREGIST_0_VALID && ENTRY_ID[5:0] == w_regist_pointer0)begin
b_state <= 2'h1;
b_pc <= iREGIST_PC;
b_make_flags_validl <= iREGIST_0_MAKE_FLAGS;
b_writeback <= iREGIST_0_WRITEBACK;
b_flags_preg_pointer <= iREGIST_0_FLAGS_PREG_POINTER;
b_destination_regname <= iREGIST_0_DEST_PREG_POINTER;
b_logic_destination <= iREGIST_0_DEST_LREG_POINTER;
b_dest_sysreg <= iREGIST_0_DEST_SYSREG;
b_ex_branch <= iREGIST_0_EX_BRANCH;
end
else if(iREGIST_1_VALID && ENTRY_ID[5:0] == w_regist_pointer1)begin
b_state <= 2'h1;
b_pc <= iREGIST_PC + 32'h4;
b_make_flags_validl <= iREGIST_1_MAKE_FLAGS;
b_writeback <= iREGIST_1_WRITEBACK;
b_flags_preg_pointer <= iREGIST_1_FLAGS_PREG_POINTER;
b_destination_regname <= iREGIST_1_DEST_PREG_POINTER;
b_logic_destination <= iREGIST_1_DEST_LREG_POINTER;
b_dest_sysreg <= iREGIST_1_DEST_SYSREG;
b_ex_branch <= iREGIST_1_EX_BRANCH;
end
end
end
2'h1 : //Execution End Wait
begin
if(iEXEND_ALU0_VALID && iEXEND_ALU0_COMMIT_TAG == ENTRY_ID[5:0])begin
b_state <= 2'h2;
end
else if(iEXEND_ALU1_VALID && iEXEND_ALU1_COMMIT_TAG == ENTRY_ID[5:0])begin
b_state <= 2'h2;
end
else if(iEXEND_ALU2_VALID && iEXEND_ALU2_COMMIT_TAG == ENTRY_ID[5:0])begin
b_state <= 2'h2;
end
else if(iEXEND_ALU3_VALID && iEXEND_ALU3_COMMIT_TAG == ENTRY_ID[5:0])begin
b_state <= 2'h2;
end
end
default :
begin
if(iCOMMIT_VALID)begin
b_state [1:0] <= 2'h0;
//b_pc <= {32{1'b0}};
b_make_flags_validl <= 1'b0;
b_writeback <= 1'b0;
b_flags_preg_pointer <= 4'h0;
b_destination_regname <= {6{1'b0}};
b_logic_destination <= {5{1'b0}};
b_dest_sysreg <= 1'b0;
b_ex_branch <= b_ex_branch;
end
end
endcase
//end
end
end //always
assign oINFO_VALID = (b_state == 2'h1 || b_state == 2'h2)? 1'b1 : 1'b0;
assign oINFO_MAKE_FLAGS_VALID = b_make_flags_validl;
assign oINFO_WRITEBACK_VALID = b_writeback;
assign oINFO_PC = b_pc;
assign oINFO_FLAGS_PREG_POINTER = b_flags_preg_pointer;
assign oINFO_DEST_PREG_POINTER = b_destination_regname;
assign oINFO_DEST_LREG_POINTER = b_logic_destination;
assign oINFO_DEST_SYSREG = b_dest_sysreg;
assign oINFO_EX_BRANCH = b_ex_branch;
assign oINFO_EX_END = (b_state == 2'h2)? 1'b1 : 1'b0;
assign oINFO_FREE = (iRESTART_VALID && ((b_state == 2'h1) || (b_state == 2'h2)))? 1'b1 : 1'b0;
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__O32AI_BEHAVIORAL_PP_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o32ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
// Local signals
wire B1 nor0_out ;
wire B1 nor1_out ;
wire or0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32AI_BEHAVIORAL_PP_V |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ae
//
// Generated
// by: wig
// on: Tue Jul 4 08:39:13 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ae.v,v 1.3 2007/03/05 13:33:59 wig Exp $
// $Date: 2007/03/05 13:33:59 $
// $Log: ent_ae.v,v $
// Revision 1.3 2007/03/05 13:33:59 wig
// Updated testcase output (only comments)!
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ae
//
// No user `defines in this module
module ent_ae
//
// Generated Module inst_ae
//
(
port_ae_2, // Use internally test2, no port generated
port_ae_5, // Bus, single bits go to outside
port_ae_6, // Conflicting definition
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_i_ae, // Input Bus
sig_o_ae // Output Bus
);
// Generated Module Inputs:
input [4:0] port_ae_2;
input [3:0] port_ae_5;
input [3:0] port_ae_6;
input [5:0] sig_07;
input [8:2] sig_08;
input [6:0] sig_i_ae;
// Generated Module Outputs:
output [7:0] sig_o_ae;
// Generated Wires:
wire [4:0] port_ae_2;
wire [3:0] port_ae_5;
wire [3:0] port_ae_6;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [6:0] sig_i_ae;
reg [7:0] sig_o_ae;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ae
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module alt_mem_ddrx_buffer_manager
# (
parameter
CFG_BUFFER_ADDR_WIDTH = 6
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
writeif_ready,
writeif_valid,
writeif_address,
writeif_address_blocked,
// buffer write interface
buffwrite_valid,
buffwrite_address,
// read interface
readif_valid,
readif_address,
// buffer read interface
buffread_valid,
buffread_datavalid,
buffread_address
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CTL_BUFFER_DEPTH = two_pow_N(CFG_BUFFER_ADDR_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
output writeif_ready;
input writeif_valid;
input [CFG_BUFFER_ADDR_WIDTH-1:0] writeif_address;
input writeif_address_blocked;
// buffer write interface
output buffwrite_valid;
output [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
// read data interface
input readif_valid;
input [CFG_BUFFER_ADDR_WIDTH-1:0] readif_address;
// buffer read interface
output buffread_valid;
output buffread_datavalid;
output [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
reg writeif_ready;
wire writeif_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] writeif_address;
wire writeif_address_blocked;
// buffer write interface
wire buffwrite_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
// read data interface
wire readif_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] readif_address;
// buffer read interface
wire buffread_valid;
reg buffread_datavalid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
// -----------------------------
// signal declaration
// -----------------------------
wire writeif_accepted;
reg [CTL_BUFFER_DEPTH-1:0] mux_writeif_ready;
reg [CTL_BUFFER_DEPTH-1:0] buffer_valid_array;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_valid_counter;
reg err_buffer_valid_counter_overflow;
// -----------------------------
// module definition
// -----------------------------
assign writeif_accepted = writeif_ready & writeif_valid;
assign buffwrite_address = writeif_address;
assign buffwrite_valid = writeif_accepted;
assign buffread_address = readif_address;
assign buffread_valid = readif_valid;
always @ (*)
begin
if (writeif_address_blocked)
begin
// can't write ahead of lowest address currently tracked by dataid array
writeif_ready = 1'b0;
end
else
begin
// buffer is full when every location has been written
writeif_ready = ~&buffer_valid_counter;
end
end
// generate buffread_datavalid.
// data is valid one cycle after adddress is presented to the buffer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffread_datavalid <= 0;
end
else
begin
buffread_datavalid <= buffread_valid;
end
end
// genvar i;
// generate
// for (i = 0; i < CTL_BUFFER_DEPTH; i = i + 1)
// begin : gen_mux_buffer_valid_array_signals
// wire [CFG_BUFFER_ADDR_WIDTH-1:0] gen_buffer_address = i;
// always @ (posedge ctl_clk or negedge ctl_reset_n)
// begin
// if (~ctl_reset_n)
// begin
// //reset state ...
// buffer_valid_array [i] <= 0;
// end
// else
// begin
// //active state ...
// // write & read to same location won't happen on same time
// // write
// if ( (writeif_address == gen_buffer_address) & writeif_accepted)
// begin
// buffer_valid_array[i] <= 1;
// end
// // read
// if ( (readif_address== gen_buffer_address) & readif_valid)
// begin
// buffer_valid_array[i] <= 0;
// end
// end
// end
// always @ (*)
// begin
// // mano - fmax !
// if ( (writeif_address == gen_buffer_address) & buffer_valid_array[i] )
// begin
// mux_writeif_ready[i] = 0;
// end
// else
// begin
// mux_writeif_ready[i] = 1;
// end
// end
// end
// endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_valid_counter <= 0;
err_buffer_valid_counter_overflow <= 0;
end
else
begin
if (writeif_accepted & readif_valid)
begin
// write & read at same time
buffer_valid_counter <= buffer_valid_counter;
end
else if (writeif_accepted)
begin
// write only
{err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
end
else if (readif_valid)
begin
// read only
buffer_valid_counter <= buffer_valid_counter - 1;
end
else
begin
buffer_valid_counter <= buffer_valid_counter;
end
end
end
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
//
// assert
//
// - write & read to same location happen on same time
|
// ======================================================================
// BLE_ADC.v generated from TopDesign.cysch
// 10/08/2017 at 17:20
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4G 2
`define CYDEV_CHIP_REVISION_4G_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4G_ES 17
`define CYDEV_CHIP_REVISION_4G_ES2 33
`define CYDEV_CHIP_MEMBER_4U 3
`define CYDEV_CHIP_REVISION_4U_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4E 4
`define CYDEV_CHIP_REVISION_4E_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4O 5
`define CYDEV_CHIP_REVISION_4O_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4N 6
`define CYDEV_CHIP_REVISION_4N_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4D 7
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4J 8
`define CYDEV_CHIP_REVISION_4J_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4K 9
`define CYDEV_CHIP_REVISION_4K_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4H 10
`define CYDEV_CHIP_REVISION_4H_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4A 11
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4F 12
`define CYDEV_CHIP_REVISION_4F_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0
`define CYDEV_CHIP_MEMBER_4F 13
`define CYDEV_CHIP_REVISION_4F_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0
`define CYDEV_CHIP_MEMBER_4M 14
`define CYDEV_CHIP_REVISION_4M_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4L 15
`define CYDEV_CHIP_REVISION_4L_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4I 16
`define CYDEV_CHIP_REVISION_4I_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4C 17
`define CYDEV_CHIP_REVISION_4C_PRODUCTION 0
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5B 18
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_MEMBER_5A 19
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_FAMILY_USED 2
`define CYDEV_CHIP_MEMBER_USED 13
`define CYDEV_CHIP_REVISION_USED 0
// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif
// Component: or_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`endif
// Component: cy_analog_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v"
`endif
// Component: Bus_Connect_v2_40
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_40"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_40\Bus_Connect_v2_40.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_40"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_40\Bus_Connect_v2_40.v"
`endif
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// ADC_SAR_SEQ_P4_v2_40(AdcAClock=4, AdcAdjust=0, AdcAlternateResolution=0, AdcAvgMode=1, AdcAvgSamplesNum=0, AdcBClock=4, AdcCClock=4, AdcChannelsEnConf=1, AdcChannelsModeConf=0, AdcClock=1, AdcClockFrequency=2999988, AdcCompareMode=0, AdcDataFormatJustification=0, AdcDClock=4, AdcDedicatedExtVref=true, AdcDifferentialResultFormat=1, AdcHighLimit=2047, AdcInjChannelEnabled=false, AdcInputBufGain=0, AdcLowLimit=0, AdcMaxResolution=12, AdcSampleMode=0, AdcSarMuxChannelConfig=0, AdcSequencedChannels=1, AdcSingleEndedNegativeInput=0, AdcSingleResultFormat=1, AdcSymbolHasSingleEndedInputChannel=false, AdcTotalChannels=1, AdcVrefSelect=3, AdcVrefVoltage_mV=1024, rm_int=false, SeqChannelsConfigTable=<?xml version="1.0" encoding="utf-16"?><CyChannelsConfigTable xmlns:Version="2_40"><m_channelsConfigTable><CyChannelsConfigTableRow><m_enabled>false</m_enabled><m_resolution>Twelve</m_resolution><m_mode>Diff</m_mode><m_averaged>false</m_averaged><m_acqTime>AClocks</m_acqTime><m_limitsDetectIntrEnabled>false</m_limitsDetectIntrEnabled><m_saturationIntrEnabled>false</m_saturationIntrEnabled></CyChannelsConfigTableRow><CyChannelsConfigTableRow><m_enabled>true</m_enabled><m_resolution>Twelve</m_resolution><m_mode>Single</m_mode><m_averaged>false</m_averaged><m_acqTime>AClocks</m_acqTime><m_limitsDetectIntrEnabled>false</m_limitsDetectIntrEnabled><m_saturationIntrEnabled>false</m_saturationIntrEnabled></CyChannelsConfigTableRow></m_channelsConfigTable></CyChannelsConfigTable>, TermMode_aclk=0, TermMode_eoc=0, TermMode_sdone=0, TermMode_soc=0, TermMode_vinMinus0=0, TermMode_vinMinus1=0, TermMode_vinMinus10=0, TermMode_vinMinus11=0, TermMode_vinMinus12=0, TermMode_vinMinus13=0, TermMode_vinMinus14=0, TermMode_vinMinus15=0, TermMode_vinMinus2=0, TermMode_vinMinus3=0, TermMode_vinMinus4=0, TermMode_vinMinus5=0, TermMode_vinMinus6=0, TermMode_vinMinus7=0, TermMode_vinMinus8=0, TermMode_vinMinus9=0, TermMode_vinMinusINJ=0, TermMode_vinNeg=0, TermMode_vinPlus0=0, TermMode_vinPlus1=0, TermMode_vinPlus10=0, TermMode_vinPlus11=0, TermMode_vinPlus12=0, TermMode_vinPlus13=0, TermMode_vinPlus14=0, TermMode_vinPlus15=0, TermMode_vinPlus2=0, TermMode_vinPlus3=0, TermMode_vinPlus4=0, TermMode_vinPlus5=0, TermMode_vinPlus6=0, TermMode_vinPlus7=0, TermMode_vinPlus8=0, TermMode_vinPlus9=0, TermMode_vinPlusINJ=0, TermMode_Vref=0, TermVisibility_aclk=false, TermVisibility_eoc=true, TermVisibility_sdone=true, TermVisibility_soc=false, TermVisibility_vinMinus0=false, TermVisibility_vinMinus1=false, TermVisibility_vinMinus10=false, TermVisibility_vinMinus11=false, TermVisibility_vinMinus12=false, TermVisibility_vinMinus13=false, TermVisibility_vinMinus14=false, TermVisibility_vinMinus15=false, TermVisibility_vinMinus2=false, TermVisibility_vinMinus3=false, TermVisibility_vinMinus4=false, TermVisibility_vinMinus5=false, TermVisibility_vinMinus6=false, TermVisibility_vinMinus7=false, TermVisibility_vinMinus8=false, TermVisibility_vinMinus9=false, TermVisibility_vinMinusINJ=false, TermVisibility_vinNeg=false, TermVisibility_vinPlus0=true, TermVisibility_vinPlus1=false, TermVisibility_vinPlus10=false, TermVisibility_vinPlus11=false, TermVisibility_vinPlus12=false, TermVisibility_vinPlus13=false, TermVisibility_vinPlus14=false, TermVisibility_vinPlus15=false, TermVisibility_vinPlus2=false, TermVisibility_vinPlus3=false, TermVisibility_vinPlus4=false, TermVisibility_vinPlus5=false, TermVisibility_vinPlus6=false, TermVisibility_vinPlus7=false, TermVisibility_vinPlus8=false, TermVisibility_vinPlus9=false, TermVisibility_vinPlusINJ=false, TermVisibility_Vref=false, CY_API_CALLBACK_HEADER_INCLUDE=#include "cyapicallbacks.h", CY_COMPONENT_NAME=ADC_SAR_SEQ_P4_v2_40, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=<:default:>, CY_FITTER_NAME=ADC_SAR, CY_INSTANCE_SHORT_NAME=ADC_SAR, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=40, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 3.3 CP3, INSTANCE_NAME=ADC_SAR, )
module ADC_SAR_SEQ_P4_v2_40_0 (
soc,
aclk,
Vref,
sdone,
eoc,
vinPlus0);
input soc;
input aclk;
inout Vref;
electrical Vref;
output sdone;
output eoc;
inout vinPlus0;
electrical vinPlus0;
wire Net_3209;
electrical Net_3164;
wire Net_3128;
wire [11:0] Net_3111;
wire Net_3110;
wire [3:0] Net_3109;
wire Net_3108;
electrical Net_3166;
electrical Net_3167;
electrical Net_3168;
electrical Net_3169;
electrical Net_3170;
electrical Net_3171;
electrical Net_3172;
electrical Net_3173;
electrical Net_3174;
electrical Net_3175;
electrical Net_3176;
electrical Net_3177;
electrical Net_3178;
electrical Net_3179;
electrical Net_3180;
electrical muxout_plus;
electrical Net_3181;
electrical muxout_minus;
electrical Net_3227;
electrical Net_3113;
electrical Net_3225;
electrical [16:0] mux_bus_minus;
electrical [16:0] mux_bus_plus;
electrical Net_3226;
wire Net_3103;
wire Net_3104;
wire Net_3105;
wire Net_3106;
wire Net_3107;
electrical Net_3165;
electrical Net_3182;
electrical Net_3183;
electrical Net_3184;
electrical Net_3185;
electrical Net_3186;
electrical Net_3187;
electrical Net_3188;
electrical Net_3189;
electrical Net_3190;
electrical Net_3191;
electrical Net_3192;
electrical Net_3193;
electrical Net_3194;
electrical Net_3195;
electrical Net_3196;
electrical Net_3197;
electrical Net_3198;
electrical Net_3132;
electrical Net_3133;
electrical Net_3134;
electrical Net_3135;
electrical Net_3136;
electrical Net_3137;
electrical Net_3138;
electrical Net_3139;
electrical Net_3140;
electrical Net_3141;
electrical Net_3142;
electrical Net_3143;
electrical Net_3144;
electrical Net_3145;
electrical Net_3146;
electrical Net_3147;
electrical Net_3148;
electrical Net_3149;
electrical Net_3150;
electrical Net_3151;
electrical Net_3152;
electrical Net_3153;
electrical Net_3154;
electrical Net_3159;
electrical Net_3157;
electrical Net_3158;
electrical Net_3160;
electrical Net_3161;
electrical Net_3162;
electrical Net_3163;
electrical Net_3156;
electrical Net_3155;
wire Net_3120;
electrical Net_3119;
electrical Net_3118;
wire Net_3124;
electrical Net_3122;
electrical Net_3117;
electrical Net_3121;
electrical Net_3123;
wire Net_3112;
wire Net_3126;
wire Net_3125;
electrical Net_2793;
electrical Net_2794;
electrical Net_1851;
electrical Net_2580;
electrical [0:0] Net_2375;
electrical [0:0] Net_1450;
electrical Net_3046;
electrical Net_3016;
wire Net_3235;
electrical Net_2099;
wire Net_17;
wire Net_1845;
electrical Net_2020;
electrical Net_124;
electrical Net_2102;
wire [1:0] Net_3207;
electrical Net_8;
electrical Net_43;
ZeroTerminal ZeroTerminal_8 (
.z(Net_3125));
assign Net_3126 = Net_1845 | Net_3125;
cy_isr_v1_0
#(.int_type(2'b10))
IRQ
(.int_signal(Net_3112));
cy_analog_noconnect_v1_0 cy_analog_noconnect_44 (
.noconnect(Net_3123));
cy_analog_noconnect_v1_0 cy_analog_noconnect_40 (
.noconnect(Net_3121));
cy_analog_noconnect_v1_0 cy_analog_noconnect_39 (
.noconnect(Net_3117));
// cy_analog_virtualmux_43 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_43_connect(Net_124, muxout_minus);
defparam cy_analog_virtualmux_43_connect.sig_width = 1;
// cy_analog_virtualmux_42 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_42_connect(Net_2020, muxout_plus);
defparam cy_analog_virtualmux_42_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_38 (
.noconnect(Net_3118));
cy_analog_noconnect_v1_0 cy_analog_noconnect_41 (
.noconnect(Net_3119));
cy_analog_noconnect_v1_0 cy_analog_noconnect_43 (
.noconnect(Net_3122));
// adc_plus_in_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 adc_plus_in_sel_connect(muxout_plus, mux_bus_plus[0]);
defparam adc_plus_in_sel_connect.sig_width = 1;
Bus_Connect_v2_40 Connect_1 (
.in_bus(mux_bus_plus[16:0]),
.out_bus(Net_1450[0:0]));
defparam Connect_1.in_width = 17;
defparam Connect_1.out_width = 1;
// adc_minus_in_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 adc_minus_in_sel_connect(muxout_minus, mux_bus_minus[0]);
defparam adc_minus_in_sel_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_3 (
.noconnect(Net_1851));
// cy_analog_virtualmux_37 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_37_connect(Net_3016, mux_bus_plus[1]);
defparam cy_analog_virtualmux_37_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_21 (
.noconnect(Net_3147));
cy_analog_noconnect_v1_0 cy_analog_noconnect_20 (
.noconnect(Net_3146));
cy_analog_noconnect_v1_0 cy_analog_noconnect_19 (
.noconnect(Net_3145));
cy_analog_noconnect_v1_0 cy_analog_noconnect_18 (
.noconnect(Net_3144));
cy_analog_noconnect_v1_0 cy_analog_noconnect_17 (
.noconnect(Net_3143));
cy_analog_noconnect_v1_0 cy_analog_noconnect_16 (
.noconnect(Net_3142));
cy_analog_noconnect_v1_0 cy_analog_noconnect_15 (
.noconnect(Net_3141));
cy_analog_noconnect_v1_0 cy_analog_noconnect_14 (
.noconnect(Net_3140));
cy_analog_noconnect_v1_0 cy_analog_noconnect_13 (
.noconnect(Net_3139));
cy_analog_noconnect_v1_0 cy_analog_noconnect_12 (
.noconnect(Net_3138));
cy_analog_noconnect_v1_0 cy_analog_noconnect_11 (
.noconnect(Net_3137));
cy_analog_noconnect_v1_0 cy_analog_noconnect_10 (
.noconnect(Net_3136));
cy_analog_noconnect_v1_0 cy_analog_noconnect_9 (
.noconnect(Net_3135));
cy_analog_noconnect_v1_0 cy_analog_noconnect_8 (
.noconnect(Net_3134));
cy_analog_noconnect_v1_0 cy_analog_noconnect_7 (
.noconnect(Net_3133));
cy_analog_noconnect_v1_0 cy_analog_noconnect_6 (
.noconnect(Net_3132));
// cy_analog_virtualmux_36 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_36_connect(Net_3046, mux_bus_minus[1]);
defparam cy_analog_virtualmux_36_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_37 (
.noconnect(Net_3165));
ZeroTerminal ZeroTerminal_5 (
.z(Net_3107));
ZeroTerminal ZeroTerminal_4 (
.z(Net_3106));
ZeroTerminal ZeroTerminal_3 (
.z(Net_3105));
ZeroTerminal ZeroTerminal_2 (
.z(Net_3104));
ZeroTerminal ZeroTerminal_1 (
.z(Net_3103));
cy_analog_noconnect_v1_0 cy_analog_noconnect_1 (
.noconnect(Net_3113));
// ext_vref_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 ext_vref_sel_connect(Net_43, Net_3227);
defparam ext_vref_sel_connect.sig_width = 1;
Bus_Connect_v2_40 Connect_2 (
.in_bus(mux_bus_minus[16:0]),
.out_bus(Net_2375[0:0]));
defparam Connect_2.in_width = 17;
defparam Connect_2.out_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_35 (
.noconnect(Net_3181));
cy_analog_noconnect_v1_0 cy_analog_noconnect_34 (
.noconnect(Net_3180));
cy_analog_noconnect_v1_0 cy_analog_noconnect_33 (
.noconnect(Net_3179));
cy_analog_noconnect_v1_0 cy_analog_noconnect_32 (
.noconnect(Net_3178));
cy_analog_noconnect_v1_0 cy_analog_noconnect_31 (
.noconnect(Net_3177));
cy_analog_noconnect_v1_0 cy_analog_noconnect_30 (
.noconnect(Net_3176));
cy_analog_noconnect_v1_0 cy_analog_noconnect_29 (
.noconnect(Net_3175));
cy_analog_noconnect_v1_0 cy_analog_noconnect_28 (
.noconnect(Net_3174));
cy_analog_noconnect_v1_0 cy_analog_noconnect_27 (
.noconnect(Net_3173));
cy_analog_noconnect_v1_0 cy_analog_noconnect_26 (
.noconnect(Net_3172));
cy_analog_noconnect_v1_0 cy_analog_noconnect_25 (
.noconnect(Net_3171));
cy_analog_noconnect_v1_0 cy_analog_noconnect_24 (
.noconnect(Net_3170));
cy_analog_noconnect_v1_0 cy_analog_noconnect_23 (
.noconnect(Net_3169));
cy_analog_noconnect_v1_0 cy_analog_noconnect_22 (
.noconnect(Net_3168));
cy_analog_noconnect_v1_0 cy_analog_noconnect_4 (
.noconnect(Net_3167));
cy_analog_noconnect_v1_0 cy_analog_noconnect_2 (
.noconnect(Net_3166));
// int_vref_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 int_vref_sel_connect(Net_8, Net_3113);
defparam int_vref_sel_connect.sig_width = 1;
// clk_src_sel (cy_virtualmux_v1_0)
assign Net_17 = Net_1845;
cy_psoc4_sar_v1_0 cy_psoc4_sar (
.vplus(Net_2020),
.vminus(Net_124),
.vref(Net_8),
.ext_vref(Net_43),
.clock(Net_17),
.sw_negvref(Net_3103),
.cfg_st_sel(Net_3207[1:0]),
.cfg_average(Net_3104),
.cfg_resolution(Net_3105),
.cfg_differential(Net_3106),
.trigger(Net_3235),
.data_hilo_sel(Net_3107),
.sample_done(sdone),
.chan_id_valid(Net_3108),
.chan_id(Net_3109[3:0]),
.data_valid(Net_3110),
.eos_intr(eoc),
.data(Net_3111[11:0]),
.irq(Net_3112));
// ext_vneg_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 ext_vneg_sel_connect(Net_2580, Net_1851);
defparam ext_vneg_sel_connect.sig_width = 1;
// VMux_soc (cy_virtualmux_v1_0)
assign Net_3235 = soc;
ZeroTerminal ZeroTerminal_6 (
.z(Net_3207[0]));
ZeroTerminal ZeroTerminal_7 (
.z(Net_3207[1]));
// cy_analog_virtualmux_vplus0 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus0_connect(mux_bus_plus[0], vinPlus0);
defparam cy_analog_virtualmux_vplus0_connect.sig_width = 1;
// cy_analog_virtualmux_vplus1 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus1_connect(mux_bus_plus[1], Net_3132);
defparam cy_analog_virtualmux_vplus1_connect.sig_width = 1;
// cy_analog_virtualmux_vplus2 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus2_connect(mux_bus_plus[2], Net_3133);
defparam cy_analog_virtualmux_vplus2_connect.sig_width = 1;
// cy_analog_virtualmux_vplus3 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus3_connect(mux_bus_plus[3], Net_3134);
defparam cy_analog_virtualmux_vplus3_connect.sig_width = 1;
// cy_analog_virtualmux_vplus4 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus4_connect(mux_bus_plus[4], Net_3135);
defparam cy_analog_virtualmux_vplus4_connect.sig_width = 1;
// cy_analog_virtualmux_vplus5 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus5_connect(mux_bus_plus[5], Net_3136);
defparam cy_analog_virtualmux_vplus5_connect.sig_width = 1;
// cy_analog_virtualmux_vplus6 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus6_connect(mux_bus_plus[6], Net_3137);
defparam cy_analog_virtualmux_vplus6_connect.sig_width = 1;
// cy_analog_virtualmux_vplus7 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus7_connect(mux_bus_plus[7], Net_3138);
defparam cy_analog_virtualmux_vplus7_connect.sig_width = 1;
// cy_analog_virtualmux_vplus8 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus8_connect(mux_bus_plus[8], Net_3139);
defparam cy_analog_virtualmux_vplus8_connect.sig_width = 1;
// cy_analog_virtualmux_vplus9 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus9_connect(mux_bus_plus[9], Net_3140);
defparam cy_analog_virtualmux_vplus9_connect.sig_width = 1;
// cy_analog_virtualmux_vplus10 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus10_connect(mux_bus_plus[10], Net_3141);
defparam cy_analog_virtualmux_vplus10_connect.sig_width = 1;
// cy_analog_virtualmux_vplus11 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus11_connect(mux_bus_plus[11], Net_3142);
defparam cy_analog_virtualmux_vplus11_connect.sig_width = 1;
// cy_analog_virtualmux_vplus12 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus12_connect(mux_bus_plus[12], Net_3143);
defparam cy_analog_virtualmux_vplus12_connect.sig_width = 1;
// cy_analog_virtualmux_vplus13 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus13_connect(mux_bus_plus[13], Net_3144);
defparam cy_analog_virtualmux_vplus13_connect.sig_width = 1;
// cy_analog_virtualmux_vplus14 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus14_connect(mux_bus_plus[14], Net_3145);
defparam cy_analog_virtualmux_vplus14_connect.sig_width = 1;
// cy_analog_virtualmux_vplus15 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus15_connect(mux_bus_plus[15], Net_3146);
defparam cy_analog_virtualmux_vplus15_connect.sig_width = 1;
// cy_analog_virtualmux_vplus_inj (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus_inj_connect(Net_3016, Net_3147);
defparam cy_analog_virtualmux_vplus_inj_connect.sig_width = 1;
// cy_analog_virtualmux_vminus0 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus0_connect(mux_bus_minus[0], Net_3166);
defparam cy_analog_virtualmux_vminus0_connect.sig_width = 1;
// cy_analog_virtualmux_vminus1 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus1_connect(mux_bus_minus[1], Net_3167);
defparam cy_analog_virtualmux_vminus1_connect.sig_width = 1;
// cy_analog_virtualmux_vminus2 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus2_connect(mux_bus_minus[2], Net_3168);
defparam cy_analog_virtualmux_vminus2_connect.sig_width = 1;
// cy_analog_virtualmux_vminus3 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus3_connect(mux_bus_minus[3], Net_3169);
defparam cy_analog_virtualmux_vminus3_connect.sig_width = 1;
// cy_analog_virtualmux_vminus4 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus4_connect(mux_bus_minus[4], Net_3170);
defparam cy_analog_virtualmux_vminus4_connect.sig_width = 1;
// cy_analog_virtualmux_vminus5 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus5_connect(mux_bus_minus[5], Net_3171);
defparam cy_analog_virtualmux_vminus5_connect.sig_width = 1;
// cy_analog_virtualmux_vminus6 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus6_connect(mux_bus_minus[6], Net_3172);
defparam cy_analog_virtualmux_vminus6_connect.sig_width = 1;
// cy_analog_virtualmux_vminus7 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus7_connect(mux_bus_minus[7], Net_3173);
defparam cy_analog_virtualmux_vminus7_connect.sig_width = 1;
// cy_analog_virtualmux_vminus8 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus8_connect(mux_bus_minus[8], Net_3174);
defparam cy_analog_virtualmux_vminus8_connect.sig_width = 1;
// cy_analog_virtualmux_vminus9 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus9_connect(mux_bus_minus[9], Net_3175);
defparam cy_analog_virtualmux_vminus9_connect.sig_width = 1;
// cy_analog_virtualmux_vminus10 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus10_connect(mux_bus_minus[10], Net_3176);
defparam cy_analog_virtualmux_vminus10_connect.sig_width = 1;
// cy_analog_virtualmux_vminus11 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus11_connect(mux_bus_minus[11], Net_3177);
defparam cy_analog_virtualmux_vminus11_connect.sig_width = 1;
// cy_analog_virtualmux_vminus12 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus12_connect(mux_bus_minus[12], Net_3178);
defparam cy_analog_virtualmux_vminus12_connect.sig_width = 1;
// cy_analog_virtualmux_vminus13 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus13_connect(mux_bus_minus[13], Net_3179);
defparam cy_analog_virtualmux_vminus13_connect.sig_width = 1;
// cy_analog_virtualmux_vminus14 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus14_connect(mux_bus_minus[14], Net_3180);
defparam cy_analog_virtualmux_vminus14_connect.sig_width = 1;
// cy_analog_virtualmux_vminus15 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus15_connect(mux_bus_minus[15], Net_3181);
defparam cy_analog_virtualmux_vminus15_connect.sig_width = 1;
// cy_analog_virtualmux_vminus_inj (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus_inj_connect(Net_3046, Net_3165);
defparam cy_analog_virtualmux_vminus_inj_connect.sig_width = 1;
cy_clock_v1_0
#(.id("2c8f831a-eb04-4562-a197-2a3531daa1f2/5c71752a-e182-47ca-942c-9cb20adbdf2f"),
.source_clock_id(""),
.divisor(0),
.period("333334666.672"),
.is_direct(0),
.is_digital(0))
intClock
(.clock_out(Net_1845));
cy_analog_noconnect_v1_0 cy_analog_noconnect_5 (
.noconnect(Net_3227));
endmodule
// Component: cy_constant_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`endif
// BLE_v3_10(AutopopulateWhitelist=true, EnableExternalPAcontrol=false, EnableExternalPrepWriteBuff=false, EnableL2capLogicalChannels=true, EnableLinkLayerPrivacy=false, GapConfig=<?xml version="1.0" encoding="utf-16"?>\r\n<CyGapConfiguration xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema">\r\n <DevAddress>00A050000000</DevAddress>\r\n <SiliconGeneratedAddress>true</SiliconGeneratedAddress>\r\n <MtuSize>23</MtuSize>\r\n <MaxTxPayloadSize>27</MaxTxPayloadSize>\r\n <MaxRxPayloadSize>27</MaxRxPayloadSize>\r\n <TxPowerLevel>0</TxPowerLevel>\r\n <TxPowerLevelConnection>0</TxPowerLevelConnection>\r\n <TxPowerLevelAdvScan>0</TxPowerLevelAdvScan>\r\n <SecurityConfig>\r\n <SecurityMode>SECURITY_MODE_1</SecurityMode>\r\n <SecurityLevel>NO_SECURITY</SecurityLevel>\r\n <StrictPairing>false</StrictPairing>\r\n <KeypressNotifications>false</KeypressNotifications>\r\n <IOCapability>NO_INPUT_NO_OUTPUT</IOCapability>\r\n <PairingMethod>JUST_WORKS</PairingMethod>\r\n <Bonding>NO_BOND</Bonding>\r\n <MaxBondedDevices>4</MaxBondedDevices>\r\n <AutoPopWhitelistBondedDev>true</AutoPopWhitelistBondedDev>\r\n <MaxWhitelistSize>8</MaxWhitelistSize>\r\n <EnableLinkLayerPrivacy>false</EnableLinkLayerPrivacy>\r\n <MaxResolvableDevices>8</MaxResolvableDevices>\r\n <EncryptionKeySize>16</EncryptionKeySize>\r\n </SecurityConfig>\r\n <AdvertisementConfig>\r\n <AdvScanMode>FAST_CONNECTION</AdvScanMode>\r\n <AdvFastScanInterval>\r\n <Minimum>80</Minimum>\r\n <Maximum>100</Maximum>\r\n </AdvFastScanInterval>\r\n <AdvReducedScanInterval>\r\n <Minimum>1000</Minimum>\r\n <Maximum>1000</Maximum>\r\n </AdvReducedScanInterval>\r\n <AdvDiscoveryMode>GENERAL</AdvDiscoveryMode>\r\n <AdvType>CONNECTABLE_UNDIRECTED</AdvType>\r\n <AdvFilterPolicy>SCAN_REQUEST_ANY_CONNECT_REQUEST_ANY</AdvFilterPolicy>\r\n <AdvChannelMap>ALL</AdvChannelMap>\r\n <AdvFastTimeout>30</AdvFastTimeout>\r\n <AdvReducedTimeout>0</AdvReducedTimeout>\r\n <ConnectionInterval>\r\n <Minimum>7.5</Minimum>\r\n <Maximum>50</Maximum>\r\n </ConnectionInterval>\r\n <ConnectionSlaveLatency>0</ConnectionSlaveLatency>\r\n <ConnectionTimeout>10000</ConnectionTimeout>\r\n </AdvertisementConfig>\r\n <ScanConfig>\r\n <ScanFastWindow>30</ScanFastWindow>\r\n <ScanFastInterval>30</ScanFastInterval>\r\n <ScanTimeout>30</ScanTimeout>\r\n <ScanReducedWindow>1125</ScanReducedWindow>\r\n <ScanReducedInterval>1280</ScanReducedInterval>\r\n <ScanReducedTimeout>150</ScanReducedTimeout>\r\n <EnableReducedScan>true</EnableReducedScan>\r\n <ScanDiscoveryMode>GENERAL</ScanDiscoveryMode>\r\n <ScanningState>ACTIVE</ScanningState>\r\n <ScanFilterPolicy>ACCEPT_ALL_ADV_PACKETS</ScanFilterPolicy>\r\n <DuplicateFiltering>false</DuplicateFiltering>\r\n <ConnectionInterval>\r\n <Minimum>7.5</Minimum>\r\n <Maximum>50</Maximum>\r\n </ConnectionInterval>\r\n <ConnectionSlaveLatency>0</ConnectionSlaveLatency>\r\n <ConnectionTimeout>10000</ConnectionTimeout>\r\n </ScanConfig>\r\n <AdvertisementPacket>\r\n <PacketType>ADVERTISEMENT</PacketType>\r\n <Items>\r\n <CyADStructure>\r\n <ADType>1</ADType>\r\n <ADData>06</ADData>\r\n </CyADStructure>\r\n <CyADStructure>\r\n <ADType>9</ADType>\r\n <ADData>4D:4D:5F:54:68:65:72:6D:69:73:74:6F:72</ADData>\r\n </CyADStructure>\r\n </Items>\r\n <IncludedServicesServiceUuid />\r\n <IncludedServicesServiceSolicitation />\r\n <IncludedServicesServiceData />\r\n </AdvertisementPacket>\r\n <ScanResponsePacket>\r\n <PacketType>SCAN_RESPONSE</PacketType>\r\n <Items />\r\n <IncludedServicesServiceUuid />\r\n <IncludedServicesServiceSolicitation />\r\n <IncludedServicesServiceData />\r\n </ScanResponsePacket>\r\n</CyGapConfiguration>, HalBaudRate=115200, ImportFilePath=, KeypressNotifications=false, L2capMpsSize=23, L2capMtuSize=23, L2capNumChannels=1, L2capNumPsm=1, LLMaxRxPayloadSize=27, LLMaxTxPayloadSize=27, MaxAttrNoOfBuffer=1, MaxBondedDevices=4, MaxResolvableDevices=8, MaxWhitelistSize=8, Mode=0, ProfileConfig=<?xml version="1.0" encoding="utf-16"?>\r\n<Profile xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema" ID="1" DisplayName="Custom" Name="Custom" Type="org.bluetooth.profile.custom">\r\n <CyProfileRole ID="2" DisplayName="Server" Name="Server">\r\n <CyService ID="3" DisplayName="Generic Access" Name="Generic Access" Type="org.bluetooth.service.generic_access" UUID="1800">\r\n <CyCharacteristic ID="4" DisplayName="Device Name" Name="Device Name" Type="org.bluetooth.characteristic.gap.device_name" UUID="2A00">\r\n <Field Name="Name">\r\n <DataFormat>utf8s</DataFormat>\r\n <ByteLength>13</ByteLength>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>MM_Thermistor</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <CyCharacteristic ID="5" DisplayName="Appearance" Name="Appearance" Type="org.bluetooth.characteristic.gap.appearance" UUID="2A01">\r\n <Field Name="Category">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>ENUM</ValueType>\r\n <EnumValue>768</EnumValue>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <CyCharacteristic ID="6" DisplayName="Peripheral Preferred Connection Parameters" Name="Peripheral Preferred Connection Parameters" Type="org.bluetooth.characteristic.gap.peripheral_preferred_connection_parameters" UUID="2A04">\r\n <Field Name="Minimum Connection Interval">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>6</Minimum>\r\n <Maximum>3200</Maximum>\r\n </Range>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>0x0006</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="Maximum Connection Interval">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>6</Minimum>\r\n <Maximum>3200</Maximum>\r\n </Range>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>0x0028</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="Slave Latency">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>0</Minimum>\r\n <Maximum>1000</Maximum>\r\n </Range>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>0</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="Connection Supervision Timeout Multiplier">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>10</Minimum>\r\n <Maximum>3200</Maximum>\r\n </Range>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>0x03E8</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <CyCharacteristic ID="7" DisplayName="Central Address Resolution" Name="Central Address Resolution" Type="org.bluetooth.characteristic.gap.central_address_resolution" UUID="2AA6">\r\n <Field Name="Central Address Resolution Support">\r\n <DataFormat>uint8</DataFormat>\r\n <ByteLength>1</ByteLength>\r\n <ValueType>ENUM</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <Declaration>Primary</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <CyService ID="8" DisplayName="Generic Attribute" Name="Generic Attribute" Type="org.bluetooth.service.generic_attribute" UUID="1801">\r\n <CyCharacteristic ID="9" DisplayName="Service Changed" Name="Service Changed" Type="org.bluetooth.characteristic.gatt.service_changed" UUID="2A05">\r\n <CyDescriptor ID="10" DisplayName="Client Characteristic Configuration" Name="Client Characteristic Configuration" Type="org.bluetooth.descriptor.gatt.client_characteristic_configuration" UUID="2902">\r\n <Field Name="Properties">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>0</Minimum>\r\n <Maximum>3</Maximum>\r\n </Range>\r\n <ValueType>BITFIELD</ValueType>\r\n <Bit>\r\n <Index>0</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Notifications disabled" />\r\n <Enumeration key="1" value="Notifications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <Bit>\r\n <Index>1</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Indications disabled" />\r\n <Enumeration key="1" value="Indications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="WRITE" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>READ_WRITE</AccessPermission>\r\n </Permission>\r\n </CyDescriptor>\r\n <Field Name="Start of Affected Attribute Handle Range">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>1</Minimum>\r\n <Maximum>65535</Maximum>\r\n </Range>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="End of Affected Attribute Handle Range">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>1</Minimum>\r\n <Maximum>65535</Maximum>\r\n </Range>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="INDICATE" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>NONE</AccessPermission>\r\n </Permission>\r\n </CyCharacteristic>\r\n <Declaration>Primary</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <CyService ID="11" DisplayName="Thermometer" Name="Custom Service" Type="org.bluetooth.service.custom" UUID="0000000000001000800000805F9B34FB">\r\n <CyCharacteristic ID="12" DisplayName="Temperature" Name="Custom Characteristic" Type="org.bluetooth.characteristic.custom" UUID="0000000000001000800000805F9B34FB">\r\n <CyDescriptor ID="13" DisplayName="Characteristic User Description" Name="Characteristic User Description" Type="org.bluetooth.descriptor.gatt.characteristic_user_description" UUID="2901">\r\n <Field Name="User Description">\r\n <DataFormat>utf8s</DataFormat>\r\n <ByteLength>22</ByteLength>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>Thermistor Temperature</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="false" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyDescriptor>\r\n <CyDescriptor ID="14" DisplayName="Client Characteristic Configuration" Name="Client Characteristic Configuration" Type="org.bluetooth.descriptor.gatt.client_characteristic_configuration" UUID="2902">\r\n <Field Name="Properties">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>0</Minimum>\r\n <Maximum>3</Maximum>\r\n </Range>\r\n <ValueType>BITFIELD</ValueType>\r\n <Bit>\r\n <Index>0</Index>\r\n <Size>1</Size>\r\n <Value>1</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Notifications disabled" />\r\n <Enumeration key="1" value="Notifications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <Bit>\r\n <Index>1</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Indications disabled" />\r\n <Enumeration key="1" value="Indications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="false" />\r\n <Property Type="WRITE" Present="true" Mandatory="false" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>READ_WRITE</AccessPermission>\r\n </Permission>\r\n </CyDescriptor>\r\n <Field Name="Temperature">\r\n <DataFormat>uint8_array</DataFormat>\r\n <ByteLength>4</ByteLength>\r\n <ValueType>ARRAY</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="BROADCAST" Present="false" Mandatory="false" />\r\n <Property Type="READ" Present="true" Mandatory="false" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n <Property Type="WRITE_WITHOUT_RESPONSE" Present="false" Mandatory="false" />\r\n <Property Type="NOTIFY" Present="true" Mandatory="false" />\r\n <Property Type="INDICATE" Present="false" Mandatory="false" />\r\n <Property Type="AUTHENTICATED_SIGNED_WRITES" Present="false" Mandatory="false" />\r\n <Property Type="RELIABLE_WRITE" Present="false" Mandatory="false" />\r\n <Property Type="WRITABLE_AUXILIARIES" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <Declaration>PrimarySingleInstance</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <ProfileRoleIndex>0</ProfileRoleIndex>\r\n <RoleType>SERVER</RoleType>\r\n </CyProfileRole>\r\n <GapRole>PERIPHERAL</GapRole>\r\n</Profile>, SharingMode=0, StackMode=3, StrictPairing=false, UseDeepSleep=true, CY_API_CALLBACK_HEADER_INCLUDE=#include "cyapicallbacks.h", CY_COMPONENT_NAME=BLE_v3_10, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=BLE_v3_10.pdf, CY_FITTER_NAME=BLE, CY_INSTANCE_SHORT_NAME=BLE, CY_MAJOR_VERSION=3, CY_MINOR_VERSION=10, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 3.3 CP3, INSTANCE_NAME=BLE, )
module BLE_v3_10_1 (
clk,
pa_en);
output clk;
output pa_en;
wire Net_55;
wire Net_60;
wire Net_53;
wire Net_72;
wire Net_71;
wire Net_70;
wire Net_15;
wire Net_14;
cy_m0s8_ble_v1_0 cy_m0s8_ble (
.interrupt(Net_15),
.rf_ext_pa_en(pa_en));
cy_isr_v1_0
#(.int_type(2'b10))
bless_isr
(.int_signal(Net_15));
cy_clock_v1_0
#(.id("e1fabf2a-6555-450d-b095-7b11ed8011cc/5ae6fa4d-f41a-4a35-8821-7ce70389cb0c"),
.source_clock_id("9A908CA6-5BB3-4db0-B098-959E5D90882B"),
.divisor(0),
.period("0"),
.is_direct(1),
.is_digital(0))
LFCLK
(.clock_out(Net_53));
assign clk = Net_53 | Net_55;
assign Net_55 = 1'h0;
endmodule
// top
module top ;
wire Net_183;
wire Net_182;
wire Net_175;
wire Net_174;
wire Net_173;
wire Net_172;
electrical Net_171;
electrical Net_45;
ADC_SAR_SEQ_P4_v2_40_0 ADC_SAR (
.Vref(Net_171),
.sdone(Net_172),
.eoc(Net_173),
.aclk(1'b0),
.soc(1'b0),
.vinPlus0(Net_45));
wire [0:0] tmpOE__THERMISTOR_net;
wire [0:0] tmpFB_0__THERMISTOR_net;
wire [0:0] tmpIO_0__THERMISTOR_net;
wire [0:0] tmpINTERRUPT_0__THERMISTOR_net;
electrical [0:0] tmpSIOVREF__THERMISTOR_net;
cy_psoc3_pins_v1_10
#(.id("77715107-f8d5-47e5-a629-0fb83101ac6b"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("A"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
THERMISTOR
(.oe(tmpOE__THERMISTOR_net),
.y({1'b0}),
.fb({tmpFB_0__THERMISTOR_net[0:0]}),
.analog({Net_45}),
.io({tmpIO_0__THERMISTOR_net[0:0]}),
.siovref(tmpSIOVREF__THERMISTOR_net),
.interrupt({tmpINTERRUPT_0__THERMISTOR_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__THERMISTOR_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
BLE_v3_10_1 BLE (
.clk(Net_182),
.pa_en(Net_183));
wire [0:0] tmpOE__GREEN_LED_net;
wire [0:0] tmpFB_0__GREEN_LED_net;
wire [0:0] tmpIO_0__GREEN_LED_net;
wire [0:0] tmpINTERRUPT_0__GREEN_LED_net;
electrical [0:0] tmpSIOVREF__GREEN_LED_net;
cy_psoc3_pins_v1_10
#(.id("e851a3b9-efb8-48be-bbb8-b303b216c393"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
GREEN_LED
(.oe(tmpOE__GREEN_LED_net),
.y({1'b0}),
.fb({tmpFB_0__GREEN_LED_net[0:0]}),
.io({tmpIO_0__GREEN_LED_net[0:0]}),
.siovref(tmpSIOVREF__GREEN_LED_net),
.interrupt({tmpINTERRUPT_0__GREEN_LED_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__GREEN_LED_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
endmodule
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_asynch_rst_ff.v
// Version : v2.0
// Description: D-FF with asychronous reset, for syncing in the start/stop
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
module axi_traffic_gen_v2_0_7_asynch_rst_ff (
data ,
clk ,
reset ,
q
);
input data, clk, reset ;
output q;
(*ASYNC_REG = "TRUE" *) reg q;
always @ ( posedge clk or posedge reset) begin
if (reset) begin
q <= 1'b1;
end else begin
q <= data;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//deco que pasa de BCD a la salida del display, cada caso es la salida
module bcd_to_display(
input clk,
input rst,
input [3:0] BCD,
output reg[7:0] DISPLAY
);
initial begin
DISPLAY = 8'b11111111;
#10 DISPLAY = 8'b00000000;
end
always @ (posedge clk)
begin
if (rst)
begin
DISPLAY = 8'b11111111;
#10 DISPLAY = 8'b00000000;
end
else
begin
case (BCD)
4'b0000: DISPLAY = 8'b11111110;// ---- espera
4'b0001: DISPLAY = 8'b11001111;// Piso 1
4'b0010: DISPLAY = 8'b10010010;// Piso 2
4'b0011: DISPLAY = 8'b10000110;// Piso 3
4'b0100: DISPLAY = 8'b11001100;// Piso 4
4'b0101: DISPLAY = 8'b10100100;// Sube
4'b0110: DISPLAY = 8'b10001000;// Abierto
4'b0111: DISPLAY = 8'b10110001;// Cerrado
4'b1000: DISPLAY = 8'b10000000;// Baja
4'b1001: DISPLAY = 8'b10011000;// indica el Piso
default: DISPLAY = 8'b0;
endcase
end
end
endmodule
|
// file: clk_166M_83M_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module clk_166M_83M_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 40.000*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [3:1] COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_166M_83M_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ebc_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:29 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ebc_e.v,v 1.1 2004/04/06 10:50:26 wig Exp $
// $Date: 2004/04/06 10:50:26 $
// $Log: inst_ebc_e.v,v $
// Revision 1.1 2004/04/06 10:50:26 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ebc_e
//
// No `defines in this module
module inst_ebc_e
//
// Generated module inst_ebc
//
(
nreset,
nreset_s
);
// Generated Module Inputs:
input nreset;
input nreset_s;
// Generated Wires:
wire nreset;
wire nreset_s;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ebc_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
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