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// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: TX_PLL.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module TX_PLL (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.843200"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "1.84320000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "TX_PLL.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "15625"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "576"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL TX_PLL.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL TX_PLL.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL TX_PLL.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL TX_PLL.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL TX_PLL.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL TX_PLL_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL TX_PLL_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/////////////////////////////////////////////////////////////////////
// This file is part of the GOST 28147-89 CryptoCore project //
// //
// Copyright (c) 2016 Dmitry Murzinov ([email protected]) //
/////////////////////////////////////////////////////////////////////
module gost28147 (
input clk, // Input clock signal for synchronous design
input rst, // Syncronous Reset input
input mode, // 0 - encrypt, 1 - decrypt
input [255:0] key, // cipher key
input [63:0] pdata, // plain text data input
input pvalid, // plain text valid input
output reg pready, // plain text ready handshake
output reg [63:0] cdata, // cipher text data output
output reg cvalid, // cipher text valid (ready for output read)
input cready // cipher text ready handshake
);
`include "sbox.vh"
////////////////////////////////////////////////////////////////////////////////
//// Crypto Stream state machine ////
////////////////////////////////////////////////////////////////////////////////
reg [1:0] state;
reg [1:0] next_state;
localparam IDLE = 2'b00,
RUN = 2'b01,
READY = 2'b10;
always @(posedge clk) begin: stream_fsm
if (rst)
state <= IDLE;
else
state <= next_state;
end
always @(*) begin
case (state)
IDLE : begin : idle_state
if (pvalid && pready)
next_state = RUN;
else
next_state = IDLE;
end : idle_state
RUN : begin : run_state
if (&i)
next_state = READY;
else
next_state = RUN;
end : run_state
READY : begin : ready_state
if (cready == 1)
next_state = IDLE;
else
next_state = READY;
end : ready_state
default : next_state = IDLE;
endcase
end
////////////////////////////////////////////////////////////////////////////////
//// Crypto Engine ////
////////////////////////////////////////////////////////////////////////////////
reg [4:0] i; // cipher cycles counter: 0..31;
always @(posedge clk)
if((state == IDLE) || (state == READY))
i <= 5'h0;
else
i <= i + 1;
wire [2:0] enc_index = (&i[4:3]) ? ~i[2:0] : i[2:0]; // cipher key index for encrypt
wire [2:0] dec_index = (|i[4:3]) ? ~i[2:0] : i[2:0]; // cipher key index for decrypt
wire [2:0] kindex = mode ? dec_index : enc_index; // cipher key index
wire [31:0] K [0:7]; // cipher key storage
assign {K[0],K[1],K[2],K[3],K[4],K[5],K[6],K[7]} = key;
reg [31:0] b, a; // MSB, LSB of input data
wire [31:0] addmod32 = a + K[kindex]; // Adding by module 32
wire [31:0] sbox = `Sbox(addmod32); // S-box replacing
wire [31:0] shift11 = {sbox[20:0],sbox[31:21]}; // <<11
always @(posedge clk)
if(rst)
{b,a} <= {64{1'b0}};
else if (pvalid && pready) // load plain text and start cipher cycles
{b,a} <= pdata;
else if (state == RUN)
{b,a} <= {a, b^shift11};
always @(posedge clk)
if (state == READY)
cdata <= {a,b};
always @(posedge clk)
if (state == READY)
cvalid <= 1'b1;
else
cvalid <= 1'b0;
always @(posedge clk)
if ((state == RUN) || (state == READY))
pready <= 1'b0;
else if (cready)
pready <= 1'b1;
/// else if (state == RUN)
/// pready <= 1'b0;
////////////////////////////////////////////////////////////////////////////////
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BA_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__O21BA_BEHAVIORAL_PP_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X , B1_N, nor0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BA_BEHAVIORAL_PP_V |
// file: sdram_clk_gen_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module sdram_clk_gen_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Create reset for the counters
wire reset_int = COUNTER_RESET;
reg rst_sync;
reg rst_sync_int;
reg rst_sync_int1;
reg rst_sync_int2;
// Declare the clocks and counter
wire clk_int;
wire clk_n;
wire clk;
reg [C_W-1:0] counter;
// Instantiation of the clocking network
//--------------------------------------
sdram_clk_gen clknetwork
(// Clock in ports
.clk_in (CLK_IN1),
// Clock out ports
.clk_out (clk_int));
assign clk_n = ~clk;
ODDR2 clkout_oddr
(.Q (CLK_OUT[1]),
.C0 (clk),
.C1 (clk_n),
.CE (1'b1),
.D0 (1'b1),
.D1 (1'b0),
.R (1'b0),
.S (1'b0));
// Connect the output clocks to the design
//-----------------------------------------
assign clk = clk_int;
// Reset synchronizer
//-----------------------------------
always @(posedge reset_int or posedge clk) begin
if (reset_int) begin
rst_sync <= 1'b1;
rst_sync_int <= 1'b1;
rst_sync_int1 <= 1'b1;
rst_sync_int2 <= 1'b1;
end
else begin
rst_sync <= 1'b0;
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end
end
// Output clock sampling
//-----------------------------------
always @(posedge clk or posedge rst_sync_int2) begin
if (rst_sync_int2) begin
counter <= #TCQ { C_W { 1'b 0 } };
end else begin
counter <= #TCQ counter + 1'b 1;
end
end
// alias the high bit to the output
assign COUNT = counter[C_W-1];
endmodule
|
// megafunction wizard: %ROM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: rom_shared.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rom_shared_ipv4 (
aclr,
address_a,
address_b,
clock,
rden_a,
rden_b,
q_a,
q_b);
input aclr;
input [11:0] address_a;
input [11:0] address_b;
input clock;
input rden_a;
input rden_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
tri1 rden_a;
tri1 rden_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire sub_wire2 = 1'h0;
wire [31:0] sub_wire3 = 32'h0;
wire [31:0] q_a = sub_wire0[31:0];
wire [31:0] q_b = sub_wire1[31:0];
altsyncram altsyncram_component (
.clock0 (clock),
.wren_a (sub_wire2),
.address_b (address_b),
.data_b (sub_wire3),
.rden_a (rden_a),
.wren_b (sub_wire2),
.aclr0 (aclr),
.address_a (address_a),
.data_a (sub_wire3),
.rden_b (rden_b),
.q_a (sub_wire0),
.q_b (sub_wire1)
// synopsys translate_off
,
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.eccstatus ()
// synopsys translate_on
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "output_IPV4.mif",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 4096,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "CLEAR0",
altsyncram_component.outdata_aclr_b = "CLEAR0",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "1"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "output_IPV4.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INIT_FILE STRING "output_IPV4.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL "address_a[11..0]"
// Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL "address_b[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
// Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a"
// Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b"
// Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0
// Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 GND 0 0 32 0
// Retrieval info: CONNECT: @data_b 0 0 32 0 GND 0 0 32 0
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0
// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_shared.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_shared.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_shared.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_shared.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_shared_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_shared_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="feedforward,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=18,HLS_SYN_DSP=39,HLS_SYN_FF=8096,HLS_SYN_LUT=11564}" *)
module feedforward (
ap_clk,
ap_rst_n,
P_config_V_TDATA,
P_config_V_TVALID,
P_config_V_TREADY,
P_WandB_TDATA,
P_WandB_TVALID,
P_WandB_TREADY,
P_uOut_TDATA,
P_uOut_TVALID,
P_uOut_TREADY,
P_netIn_TDATA,
P_netIn_TVALID,
P_netIn_TREADY,
P_netOut_V_TDATA,
P_netOut_V_TVALID,
P_netOut_V_TREADY,
s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_WVALID,
s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB,
s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_ARADDR,
s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY,
s_axi_AXILiteS_RDATA,
s_axi_AXILiteS_RRESP,
s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_BRESP,
interrupt
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 149'b1;
parameter ap_ST_st2_fsm_1 = 149'b10;
parameter ap_ST_st3_fsm_2 = 149'b100;
parameter ap_ST_st4_fsm_3 = 149'b1000;
parameter ap_ST_st5_fsm_4 = 149'b10000;
parameter ap_ST_st6_fsm_5 = 149'b100000;
parameter ap_ST_st7_fsm_6 = 149'b1000000;
parameter ap_ST_st8_fsm_7 = 149'b10000000;
parameter ap_ST_st9_fsm_8 = 149'b100000000;
parameter ap_ST_st10_fsm_9 = 149'b1000000000;
parameter ap_ST_st11_fsm_10 = 149'b10000000000;
parameter ap_ST_st12_fsm_11 = 149'b100000000000;
parameter ap_ST_st13_fsm_12 = 149'b1000000000000;
parameter ap_ST_st14_fsm_13 = 149'b10000000000000;
parameter ap_ST_st15_fsm_14 = 149'b100000000000000;
parameter ap_ST_st16_fsm_15 = 149'b1000000000000000;
parameter ap_ST_st17_fsm_16 = 149'b10000000000000000;
parameter ap_ST_st18_fsm_17 = 149'b100000000000000000;
parameter ap_ST_st19_fsm_18 = 149'b1000000000000000000;
parameter ap_ST_st20_fsm_19 = 149'b10000000000000000000;
parameter ap_ST_st21_fsm_20 = 149'b100000000000000000000;
parameter ap_ST_st22_fsm_21 = 149'b1000000000000000000000;
parameter ap_ST_st23_fsm_22 = 149'b10000000000000000000000;
parameter ap_ST_st24_fsm_23 = 149'b100000000000000000000000;
parameter ap_ST_st25_fsm_24 = 149'b1000000000000000000000000;
parameter ap_ST_st26_fsm_25 = 149'b10000000000000000000000000;
parameter ap_ST_st27_fsm_26 = 149'b100000000000000000000000000;
parameter ap_ST_st28_fsm_27 = 149'b1000000000000000000000000000;
parameter ap_ST_st29_fsm_28 = 149'b10000000000000000000000000000;
parameter ap_ST_st30_fsm_29 = 149'b100000000000000000000000000000;
parameter ap_ST_st31_fsm_30 = 149'b1000000000000000000000000000000;
parameter ap_ST_st32_fsm_31 = 149'b10000000000000000000000000000000;
parameter ap_ST_st33_fsm_32 = 149'b100000000000000000000000000000000;
parameter ap_ST_st34_fsm_33 = 149'b1000000000000000000000000000000000;
parameter ap_ST_st35_fsm_34 = 149'b10000000000000000000000000000000000;
parameter ap_ST_st36_fsm_35 = 149'b100000000000000000000000000000000000;
parameter ap_ST_st37_fsm_36 = 149'b1000000000000000000000000000000000000;
parameter ap_ST_st38_fsm_37 = 149'b10000000000000000000000000000000000000;
parameter ap_ST_st39_fsm_38 = 149'b100000000000000000000000000000000000000;
parameter ap_ST_st40_fsm_39 = 149'b1000000000000000000000000000000000000000;
parameter ap_ST_st41_fsm_40 = 149'b10000000000000000000000000000000000000000;
parameter ap_ST_st42_fsm_41 = 149'b100000000000000000000000000000000000000000;
parameter ap_ST_st43_fsm_42 = 149'b1000000000000000000000000000000000000000000;
parameter ap_ST_st44_fsm_43 = 149'b10000000000000000000000000000000000000000000;
parameter ap_ST_st45_fsm_44 = 149'b100000000000000000000000000000000000000000000;
parameter ap_ST_st46_fsm_45 = 149'b1000000000000000000000000000000000000000000000;
parameter ap_ST_st47_fsm_46 = 149'b10000000000000000000000000000000000000000000000;
parameter ap_ST_st48_fsm_47 = 149'b100000000000000000000000000000000000000000000000;
parameter ap_ST_st49_fsm_48 = 149'b1000000000000000000000000000000000000000000000000;
parameter ap_ST_st50_fsm_49 = 149'b10000000000000000000000000000000000000000000000000;
parameter ap_ST_st51_fsm_50 = 149'b100000000000000000000000000000000000000000000000000;
parameter ap_ST_st52_fsm_51 = 149'b1000000000000000000000000000000000000000000000000000;
parameter ap_ST_st53_fsm_52 = 149'b10000000000000000000000000000000000000000000000000000;
parameter ap_ST_st54_fsm_53 = 149'b100000000000000000000000000000000000000000000000000000;
parameter ap_ST_st55_fsm_54 = 149'b1000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st56_fsm_55 = 149'b10000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st57_fsm_56 = 149'b100000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st58_fsm_57 = 149'b1000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st59_fsm_58 = 149'b10000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st60_fsm_59 = 149'b100000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st61_fsm_60 = 149'b1000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st62_fsm_61 = 149'b10000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st63_fsm_62 = 149'b100000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st64_fsm_63 = 149'b1000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st65_fsm_64 = 149'b10000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st66_fsm_65 = 149'b100000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st67_fsm_66 = 149'b1000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st68_fsm_67 = 149'b10000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st69_fsm_68 = 149'b100000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st70_fsm_69 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st71_fsm_70 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st72_fsm_71 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st73_fsm_72 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st74_fsm_73 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st75_fsm_74 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st76_fsm_75 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st77_fsm_76 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st78_fsm_77 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st79_fsm_78 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st80_fsm_79 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st81_fsm_80 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st82_fsm_81 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st83_fsm_82 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st84_fsm_83 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st85_fsm_84 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st86_fsm_85 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st87_fsm_86 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st88_fsm_87 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st89_fsm_88 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st90_fsm_89 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st91_fsm_90 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st92_fsm_91 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st93_fsm_92 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st94_fsm_93 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st95_fsm_94 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st96_fsm_95 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st97_fsm_96 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st98_fsm_97 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st99_fsm_98 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st100_fsm_99 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st101_fsm_100 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st102_fsm_101 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st103_fsm_102 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st104_fsm_103 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st105_fsm_104 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st106_fsm_105 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st107_fsm_106 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st108_fsm_107 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st109_fsm_108 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st110_fsm_109 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st111_fsm_110 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st112_fsm_111 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st113_fsm_112 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st114_fsm_113 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st115_fsm_114 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st116_fsm_115 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st117_fsm_116 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st118_fsm_117 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st119_fsm_118 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st120_fsm_119 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st121_fsm_120 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st122_fsm_121 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st123_fsm_122 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st124_fsm_123 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st125_fsm_124 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st126_fsm_125 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st127_fsm_126 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st128_fsm_127 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st129_fsm_128 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st130_fsm_129 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st131_fsm_130 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st132_fsm_131 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st133_fsm_132 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st134_fsm_133 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st135_fsm_134 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st136_fsm_135 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st137_fsm_136 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st138_fsm_137 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st139_fsm_138 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st140_fsm_139 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st141_fsm_140 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st142_fsm_141 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st143_fsm_142 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st144_fsm_143 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st145_fsm_144 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st146_fsm_145 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st147_fsm_146 = 149'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st148_fsm_147 = 149'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st149_fsm_148 = 149'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv8_0 = 8'b00000000;
parameter C_S_AXI_AXILITES_DATA_WIDTH = 32;
parameter ap_const_int64_8 = 8;
parameter C_S_AXI_AXILITES_ADDR_WIDTH = 5;
parameter C_S_AXI_DATA_WIDTH = 32;
parameter ap_const_lv32_5 = 32'b101;
parameter ap_const_lv32_4F = 32'b1001111;
parameter ap_const_lv32_78 = 32'b1111000;
parameter ap_const_lv32_8B = 32'b10001011;
parameter ap_const_lv32_E = 32'b1110;
parameter ap_const_lv32_58 = 32'b1011000;
parameter ap_const_lv32_8 = 32'b1000;
parameter ap_const_lv32_52 = 32'b1010010;
parameter ap_const_lv32_D = 32'b1101;
parameter ap_const_lv32_57 = 32'b1010111;
parameter ap_const_lv32_13 = 32'b10011;
parameter ap_const_lv32_5D = 32'b1011101;
parameter ap_const_lv32_14 = 32'b10100;
parameter ap_const_lv32_5E = 32'b1011110;
parameter ap_const_lv32_26 = 32'b100110;
parameter ap_const_lv32_70 = 32'b1110000;
parameter ap_const_lv32_4B = 32'b1001011;
parameter ap_const_lv32_71 = 32'b1110001;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv32_4 = 32'b100;
parameter ap_const_lv32_2B = 32'b101011;
parameter ap_const_lv32_4A = 32'b1001010;
parameter ap_const_lv32_4D = 32'b1001101;
parameter ap_const_lv32_4E = 32'b1001110;
parameter ap_const_lv32_76 = 32'b1110110;
parameter ap_const_lv32_77 = 32'b1110111;
parameter ap_const_lv32_88 = 32'b10001000;
parameter ap_const_lv32_8A = 32'b10001010;
parameter ap_const_lv32_8C = 32'b10001100;
parameter ap_const_lv32_8D = 32'b10001101;
parameter ap_const_lv32_8E = 32'b10001110;
parameter ap_const_lv32_90 = 32'b10010000;
parameter ap_const_lv32_91 = 32'b10010001;
parameter ap_const_lv2_2 = 2'b10;
parameter ap_const_lv2_1 = 2'b1;
parameter ap_const_lv32_92 = 32'b10010010;
parameter ap_const_lv32_93 = 32'b10010011;
parameter ap_const_lv32_94 = 32'b10010100;
parameter ap_const_lv8_1 = 8'b1;
parameter ap_const_lv32_4C = 32'b1001100;
parameter ap_const_lv32_89 = 32'b10001001;
parameter ap_const_lv14_0 = 14'b00000000000000;
parameter ap_const_lv32_8F = 32'b10001111;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv32_72 = 32'b1110010;
parameter ap_const_lv32_9 = 32'b1001;
parameter ap_const_lv32_F = 32'b1111;
parameter ap_const_lv32_53 = 32'b1010011;
parameter ap_const_lv32_59 = 32'b1011001;
parameter ap_const_lv64_3FF0000000000000 = 64'b11111111110000000000000000000000000000000000000000000000000000;
parameter ap_const_lv8_2 = 8'b10;
parameter ap_const_lv15_23 = 15'b100011;
parameter ap_const_lv8_FF = 8'b11111111;
parameter ap_const_lv9_23 = 9'b100011;
parameter ap_const_lv9_1FF = 9'b111111111;
parameter ap_const_lv16_23 = 16'b100011;
parameter ap_const_lv9_1FE = 9'b111111110;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv32_80000000 = 32'b10000000000000000000000000000000;
parameter ap_const_lv8_3 = 8'b11;
parameter ap_const_lv14_23 = 14'b100011;
parameter ap_const_lv32_17 = 32'b10111;
parameter ap_const_lv32_1E = 32'b11110;
parameter ap_const_lv23_0 = 23'b00000000000000000000000;
parameter ap_const_lv2_3 = 2'b11;
parameter ap_const_lv9_1 = 9'b1;
parameter ap_const_lv5_2 = 5'b10;
parameter ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter ap_true = 1'b1;
parameter C_S_AXI_AXILITES_WSTRB_WIDTH = (C_S_AXI_AXILITES_DATA_WIDTH / ap_const_int64_8);
parameter C_S_AXI_WSTRB_WIDTH = (C_S_AXI_DATA_WIDTH / ap_const_int64_8);
input ap_clk;
input ap_rst_n;
input [7:0] P_config_V_TDATA;
input P_config_V_TVALID;
output P_config_V_TREADY;
input [31:0] P_WandB_TDATA;
input P_WandB_TVALID;
output P_WandB_TREADY;
output [31:0] P_uOut_TDATA;
output P_uOut_TVALID;
input P_uOut_TREADY;
input [31:0] P_netIn_TDATA;
input P_netIn_TVALID;
output P_netIn_TREADY;
output [7:0] P_netOut_V_TDATA;
output P_netOut_V_TVALID;
input P_netOut_V_TREADY;
input s_axi_AXILiteS_AWVALID;
output s_axi_AXILiteS_AWREADY;
input [C_S_AXI_AXILITES_ADDR_WIDTH - 1 : 0] s_axi_AXILiteS_AWADDR;
input s_axi_AXILiteS_WVALID;
output s_axi_AXILiteS_WREADY;
input [C_S_AXI_AXILITES_DATA_WIDTH - 1 : 0] s_axi_AXILiteS_WDATA;
input [C_S_AXI_AXILITES_WSTRB_WIDTH - 1 : 0] s_axi_AXILiteS_WSTRB;
input s_axi_AXILiteS_ARVALID;
output s_axi_AXILiteS_ARREADY;
input [C_S_AXI_AXILITES_ADDR_WIDTH - 1 : 0] s_axi_AXILiteS_ARADDR;
output s_axi_AXILiteS_RVALID;
input s_axi_AXILiteS_RREADY;
output [C_S_AXI_AXILITES_DATA_WIDTH - 1 : 0] s_axi_AXILiteS_RDATA;
output [1:0] s_axi_AXILiteS_RRESP;
output s_axi_AXILiteS_BVALID;
input s_axi_AXILiteS_BREADY;
output [1:0] s_axi_AXILiteS_BRESP;
output interrupt;
reg P_config_V_TREADY;
reg P_WandB_TREADY;
reg P_uOut_TVALID;
reg P_netIn_TREADY;
reg P_netOut_V_TVALID;
reg ap_rst_n_inv;
wire ap_start;
reg ap_done;
reg ap_idle;
(* fsm_encoding = "none" *) reg [148:0] ap_CS_fsm = 149'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_167;
reg ap_ready;
wire [7:0] P_mode_V;
reg [7:0] ST_numLayer_V = 8'b00000000;
reg [7:0] ST_layerSize_V_0 = 8'b00000000;
reg [7:0] ST_layerSize_V_1 = 8'b00000000;
reg [7:0] ST_layerSize_V_2 = 8'b00000000;
reg [7:0] ST_layerSize_V_3 = 8'b00000000;
reg [12:0] ST_WandB_address0;
reg ST_WandB_ce0;
reg ST_WandB_we0;
wire [31:0] ST_WandB_d0;
wire [31:0] ST_WandB_q0;
wire feedforward_AXILiteS_s_axi_U_ap_dummy_ce;
wire [31:0] p_uOut_q0;
reg [31:0] reg_565;
reg ap_sig_cseq_ST_st6_fsm_5;
reg ap_sig_bdd_249;
reg ap_sig_cseq_ST_st80_fsm_79;
reg ap_sig_bdd_256;
reg ap_sig_cseq_ST_st121_fsm_120;
reg ap_sig_bdd_264;
reg ap_sig_cseq_ST_st140_fsm_139;
reg ap_sig_bdd_272;
reg [31:0] reg_572;
reg ap_sig_cseq_ST_st15_fsm_14;
reg ap_sig_bdd_281;
reg ap_sig_cseq_ST_st89_fsm_88;
reg ap_sig_bdd_290;
wire [31:0] grp_fu_513_p2;
reg [31:0] reg_578;
reg ap_sig_cseq_ST_st9_fsm_8;
reg ap_sig_bdd_300;
reg ap_sig_cseq_ST_st83_fsm_82;
reg ap_sig_bdd_307;
wire [31:0] grp_fu_506_p2;
reg ap_sig_cseq_ST_st14_fsm_13;
reg ap_sig_bdd_317;
reg ap_sig_cseq_ST_st88_fsm_87;
reg ap_sig_bdd_324;
reg [31:0] reg_589;
reg ap_sig_cseq_ST_st20_fsm_19;
reg ap_sig_bdd_333;
reg ap_sig_cseq_ST_st94_fsm_93;
reg ap_sig_bdd_340;
wire [63:0] grp_fu_527_p1;
reg [63:0] reg_594;
reg ap_sig_cseq_ST_st21_fsm_20;
reg ap_sig_bdd_350;
reg ap_sig_cseq_ST_st95_fsm_94;
reg ap_sig_bdd_357;
wire [63:0] grp_fu_544_p2;
reg [63:0] reg_599;
reg ap_sig_cseq_ST_st39_fsm_38;
reg ap_sig_bdd_367;
reg ap_sig_cseq_ST_st113_fsm_112;
reg ap_sig_bdd_374;
wire [31:0] grp_fu_524_p1;
reg [31:0] reg_605;
reg ap_sig_cseq_ST_st76_fsm_75;
reg ap_sig_bdd_384;
reg ap_sig_cseq_ST_st114_fsm_113;
reg ap_sig_bdd_391;
reg [7:0] P_mode_V_read_reg_1437;
wire [0:0] tmp_fu_611_p2;
reg ap_sig_bdd_404;
reg [0:0] tmp_reg_1442;
reg [7:0] ST_numLayer_V_load_reg_1446;
wire [0:0] tmp_1_fu_621_p2;
reg [0:0] tmp_1_reg_1454;
reg [7:0] ST_layerSize_V_0_load_reg_1458;
reg [7:0] P_config_V_read_reg_1463;
wire [7:0] i_8_fu_638_p2;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_428;
wire [0:0] exitcond1_fu_633_p2;
reg ap_sig_bdd_434;
wire [31:0] tmp_62_cast_fu_664_p1;
reg [31:0] tmp_62_cast_reg_1479;
reg ap_sig_cseq_ST_st3_fsm_2;
reg ap_sig_bdd_444;
wire [0:0] tmp_7_fu_649_p2;
wire [1:0] tmp_6_fu_668_p1;
reg [1:0] tmp_6_reg_1484;
wire [8:0] tmp_16_fu_682_p2;
reg [8:0] tmp_16_reg_1489;
wire [1:0] tmp_20_fu_688_p1;
reg [1:0] tmp_20_reg_1494;
wire [8:0] tmp_24_fu_711_p1;
reg [8:0] tmp_24_reg_1499;
wire signed [32:0] tmp_64_cast_fu_715_p1;
reg signed [32:0] tmp_64_cast_reg_1506;
wire [1:0] tmp_26_fu_719_p1;
reg [1:0] tmp_26_reg_1511;
wire [8:0] tmp_33_fu_729_p2;
reg [8:0] tmp_33_reg_1516;
wire [1:0] tmp_35_fu_735_p1;
reg [1:0] tmp_35_reg_1521;
wire [31:0] j_5_fu_762_p2;
reg [31:0] j_5_reg_1529;
reg ap_sig_cseq_ST_st4_fsm_3;
reg ap_sig_bdd_474;
wire [7:0] tmp_19_fu_768_p6;
reg [7:0] tmp_19_reg_1534;
wire [0:0] tmp_14_fu_756_p2;
wire [13:0] tmp_60_fu_815_p2;
reg [13:0] tmp_60_reg_1540;
reg [7:0] p_uOut_addr_1_reg_1546;
wire [7:0] i_10_fu_821_p2;
wire [7:0] k_3_fu_832_p2;
reg [7:0] k_3_reg_1559;
reg ap_sig_cseq_ST_st5_fsm_4;
reg ap_sig_bdd_496;
wire [0:0] exitcond2_fu_827_p2;
wire [63:0] grp_fu_534_p2;
reg [63:0] tmp_30_reg_1579;
reg ap_sig_cseq_ST_st44_fsm_43;
reg ap_sig_bdd_516;
wire [63:0] grp_fu_539_p2;
reg [63:0] tmp_31_reg_1584;
reg ap_sig_cseq_ST_st75_fsm_74;
reg ap_sig_bdd_525;
wire [7:0] tmp_15_fu_894_p6;
reg [7:0] tmp_15_reg_1589;
reg ap_sig_cseq_ST_st78_fsm_77;
reg ap_sig_bdd_534;
wire [31:0] i_12_fu_917_p2;
reg [31:0] i_12_reg_1598;
wire [7:0] tmp_23_fu_923_p6;
reg [7:0] tmp_23_reg_1603;
wire [0:0] tmp_18_fu_911_p2;
wire [13:0] tmp_64_fu_974_p2;
reg [13:0] tmp_64_reg_1609;
reg [7:0] p_uOut_addr_3_reg_1615;
wire [7:0] j_6_fu_985_p2;
reg [7:0] j_6_reg_1623;
reg ap_sig_cseq_ST_st79_fsm_78;
reg ap_sig_bdd_555;
wire [0:0] exitcond3_fu_980_p2;
reg ap_sig_cseq_ST_st119_fsm_118;
reg ap_sig_bdd_574;
wire [7:0] i_11_fu_1037_p2;
reg [7:0] i_11_reg_1651;
reg ap_sig_cseq_ST_st120_fsm_119;
reg ap_sig_bdd_583;
reg [7:0] p_uOut_addr_5_reg_1656;
wire [0:0] exitcond4_fu_1032_p2;
wire [0:0] tmp_41_fu_1057_p2;
reg [0:0] tmp_41_reg_1661;
wire [31:0] grp_fu_519_p2;
reg [31:0] tmp_43_reg_1665;
reg ap_sig_cseq_ST_st137_fsm_136;
reg ap_sig_bdd_601;
reg ap_sig_cseq_ST_st139_fsm_138;
reg ap_sig_bdd_610;
wire [0:0] tmp_44_fu_1062_p2;
reg ap_sig_ioackin_P_netOut_V_TREADY;
wire [8:0] tmp_74_fu_1095_p1;
reg [8:0] tmp_74_reg_1683;
wire [13:0] next_mul_fu_1099_p2;
reg [13:0] next_mul_reg_1688;
wire [7:0] i_14_fu_1110_p2;
reg [7:0] i_14_reg_1696;
wire [1:0] tmp_75_fu_1116_p1;
reg [1:0] tmp_75_reg_1701;
wire [0:0] exitcond_fu_1105_p2;
wire [31:0] p_uOut_q1;
reg [31:0] p_uOut_load_4_reg_1706;
wire [0:0] tmp_56_fu_1197_p2;
reg [0:0] tmp_56_reg_1712;
reg ap_sig_cseq_ST_st141_fsm_140;
reg ap_sig_bdd_654;
wire [7:0] p_netOut_V_1_fu_1203_p3;
reg ap_sig_cseq_ST_st142_fsm_141;
reg ap_sig_bdd_663;
wire [7:0] i_15_fu_1210_p2;
wire [31:0] j_7_fu_1239_p2;
reg [31:0] j_7_reg_1730;
reg ap_sig_cseq_ST_st143_fsm_142;
reg ap_sig_bdd_674;
wire [0:0] tmp_59_fu_1233_p2;
wire [0:0] tmp_9_fu_1259_p2;
reg [0:0] tmp_9_reg_1740;
reg ap_sig_cseq_ST_st145_fsm_144;
reg ap_sig_bdd_689;
wire [31:0] tmp_61_cast_fu_1274_p1;
reg [31:0] tmp_61_cast_reg_1744;
wire [1:0] tmp_4_fu_1278_p1;
reg [1:0] tmp_4_reg_1749;
wire [1:0] tmp_7_t_fu_1282_p2;
reg [1:0] tmp_7_t_reg_1753;
wire [31:0] j_4_fu_1288_p2;
reg [31:0] j_4_reg_1758;
reg ap_sig_cseq_ST_st146_fsm_145;
reg ap_sig_bdd_707;
wire [13:0] tmp_46_fu_1333_p2;
reg [13:0] tmp_46_reg_1781;
reg ap_sig_cseq_ST_st147_fsm_146;
reg ap_sig_bdd_732;
wire [0:0] tmp_11_fu_1298_p2;
wire [7:0] i_9_fu_1339_p2;
wire [31:0] k_2_fu_1392_p2;
reg ap_sig_cseq_ST_st148_fsm_147;
reg ap_sig_bdd_748;
wire [0:0] tmp_22_fu_1386_p2;
reg ap_sig_bdd_755;
wire [0:0] exitcond5_fu_1398_p2;
reg [0:0] exitcond5_reg_1799;
reg ap_sig_cseq_ST_st149_fsm_148;
reg ap_sig_bdd_765;
reg ap_sig_bdd_769;
wire [7:0] i_7_fu_1403_p2;
reg [7:0] p_uOut_address0;
reg p_uOut_ce0;
reg p_uOut_we0;
reg [31:0] p_uOut_d0;
reg [7:0] p_uOut_address1;
reg p_uOut_ce1;
reg [7:0] i_2_reg_277;
reg [7:0] i_3_reg_288;
reg [31:0] j_1_reg_300;
reg ap_sig_cseq_ST_st77_fsm_76;
reg ap_sig_bdd_800;
reg [31:0] sum_reg_311;
reg [7:0] k_1_reg_323;
reg [31:0] sumsoft_reg_334;
reg [31:0] i_4_reg_346;
reg [31:0] sum_1_reg_357;
reg [7:0] j_2_reg_369;
reg [7:0] i_5_reg_380;
reg ap_sig_cseq_ST_st138_fsm_137;
reg ap_sig_bdd_821;
reg [7:0] p_s_reg_391;
reg [7:0] p_netOut_V_reg_404;
reg [7:0] i_6_reg_416;
reg [13:0] phi_mul_reg_427;
reg [31:0] j_3_reg_438;
reg ap_sig_cseq_ST_st144_fsm_143;
reg ap_sig_bdd_847;
reg ap_sig_ioackin_P_uOut_TREADY;
reg [7:0] i_1_reg_449;
reg [31:0] j_reg_461;
reg [7:0] ST_layerSize_V_load_1_phi_reg_473;
reg [31:0] k_reg_484;
reg [7:0] i_reg_495;
wire [63:0] tmp_8_fu_644_p1;
wire signed [63:0] tmp_70_cast_fu_786_p1;
wire [63:0] tmp_80_cast_fu_851_p1;
wire signed [63:0] tmp_81_cast_fu_861_p1;
wire [63:0] tmp_79_cast_fu_874_p1;
wire signed [63:0] tmp_74_cast_fu_945_p1;
wire [63:0] tmp_83_cast_fu_1004_p1;
wire signed [63:0] tmp_84_cast_fu_1014_p1;
wire [63:0] tmp_82_cast_fu_1027_p1;
wire signed [63:0] tmp_85_cast_fu_1052_p1;
wire signed [63:0] tmp_87_cast_fu_1076_p1;
wire signed [63:0] tmp_88_cast_fu_1090_p1;
wire [63:0] tmp_89_cast_fu_1254_p1;
wire [63:0] tmp_78_cast_fu_1354_p1;
wire [1:0] tmp_2_fu_1409_p1;
reg ap_reg_ioackin_P_netOut_V_TREADY = 1'b0;
reg ap_reg_ioackin_P_uOut_TREADY = 1'b0;
reg ap_sig_cseq_ST_st115_fsm_114;
reg ap_sig_bdd_963;
reg [31:0] grp_fu_506_p0;
reg [31:0] grp_fu_506_p1;
reg ap_sig_cseq_ST_st10_fsm_9;
reg ap_sig_bdd_987;
reg ap_sig_cseq_ST_st16_fsm_15;
reg ap_sig_bdd_994;
reg ap_sig_cseq_ST_st84_fsm_83;
reg ap_sig_bdd_1002;
reg ap_sig_cseq_ST_st90_fsm_89;
reg ap_sig_bdd_1009;
reg [63:0] grp_fu_524_p0;
reg [31:0] grp_fu_527_p0;
wire [31:0] tmp_27_fu_889_p1;
wire [7:0] tmp_5_fu_658_p1;
wire [14:0] tmp_5_fu_658_p2;
wire [7:0] tmp_3_fu_672_p2;
wire [7:0] tmp_16_fu_682_p1;
wire [8:0] lhs_V_1_cast_fu_692_p1;
wire [8:0] r_V_1_fu_695_p2;
wire signed [8:0] tmp_21_fu_705_p1;
wire [15:0] tmp_21_fu_705_p2;
wire signed [8:0] r_V_2_fu_723_p2;
wire [7:0] tmp_12_fu_739_p6;
wire [31:0] tmp_13_fu_752_p1;
wire [31:0] tmp_47_fu_781_p2;
wire [8:0] tmp_49_fu_791_p1;
wire [11:0] tmp_51_fu_803_p1;
wire [13:0] p_shl2_cast_fu_795_p3;
wire [13:0] p_shl3_cast_fu_807_p3;
wire [13:0] tmp_33_cast_fu_842_p1;
wire [13:0] tmp_69_fu_846_p2;
wire [8:0] tmp_33_cast7_fu_838_p1;
wire [8:0] tmp_70_fu_856_p2;
wire [13:0] tmp_26_cast_fu_866_p1;
wire [13:0] tmp_68_fu_869_p2;
wire [31:0] tmp_35_to_int_fu_879_p1;
wire [31:0] tmp_35_neg_fu_883_p2;
wire [31:0] tmp_17_fu_907_p1;
wire signed [32:0] tmp_24_cast_fu_936_p1;
wire [32:0] tmp_61_fu_940_p2;
wire [8:0] tmp_62_fu_950_p1;
wire [11:0] tmp_63_fu_962_p1;
wire [13:0] p_shl4_cast_fu_954_p3;
wire [13:0] p_shl5_cast_fu_966_p3;
wire [13:0] tmp_39_cast_fu_995_p1;
wire [13:0] tmp_72_fu_999_p2;
wire [8:0] tmp_39_cast6_fu_991_p1;
wire [8:0] tmp_73_fu_1009_p2;
wire [13:0] tmp_35_cast_fu_1019_p1;
wire [13:0] tmp_71_fu_1022_p2;
wire [8:0] tmp_42_cast_fu_1043_p1;
wire [8:0] tmp_67_fu_1047_p2;
wire [8:0] tmp_46_cast_fu_1067_p1;
wire [8:0] tmp_76_fu_1071_p2;
wire [8:0] tmp_47_cast_fu_1081_p1;
wire [8:0] tmp_77_fu_1085_p2;
wire [31:0] p_uOut_load_3_to_int_fu_1120_p1;
wire [31:0] p_uOut_load_4_to_int_fu_1138_p1;
wire [7:0] tmp_48_fu_1124_p4;
wire [22:0] tmp_78_fu_1134_p1;
wire [0:0] notrhs_fu_1161_p2;
wire [0:0] notlhs_fu_1155_p2;
wire [7:0] tmp_50_fu_1141_p4;
wire [22:0] tmp_79_fu_1151_p1;
wire [0:0] notrhs1_fu_1179_p2;
wire [0:0] notlhs1_fu_1173_p2;
wire [0:0] tmp_52_fu_1167_p2;
wire [0:0] tmp_53_fu_1185_p2;
wire [0:0] tmp_54_fu_1191_p2;
wire [0:0] tmp_55_fu_530_p2;
wire [7:0] tmp_57_fu_1216_p6;
wire [31:0] tmp_58_fu_1229_p1;
wire [8:0] tmp_80_fu_1245_p1;
wire [8:0] tmp_81_fu_1249_p2;
wire [7:0] tmp_s_fu_1268_p1;
wire [14:0] tmp_s_fu_1268_p2;
wire [31:0] tmp_10_fu_1294_p1;
wire [31:0] tmp_39_fu_1304_p2;
wire [8:0] tmp_42_fu_1309_p1;
wire [11:0] tmp_45_fu_1321_p1;
wire [13:0] p_shl_cast_fu_1313_p3;
wire [13:0] p_shl1_cast_fu_1325_p3;
wire [13:0] tmp_65_fu_1345_p1;
wire [13:0] tmp_66_fu_1349_p2;
wire [7:0] tmp_25_fu_1359_p6;
wire [8:0] lhs_V_cast_fu_1372_p1;
wire [8:0] r_V_fu_1376_p2;
wire [31:0] tmp_21_cast_fu_1382_p1;
wire grp_fu_506_ce;
wire grp_fu_513_ce;
wire grp_fu_519_ce;
wire [4:0] tmp_55_fu_530_opcode;
wire grp_fu_534_ce;
wire grp_fu_539_ce;
wire grp_fu_544_ce;
reg [148:0] ap_NS_fsm;
wire [8:0] tmp_16_fu_682_p10;
wire [14:0] tmp_5_fu_658_p10;
wire [14:0] tmp_s_fu_1268_p10;
reg ap_sig_bdd_724;
reg ap_sig_bdd_942;
feedforward_ST_WandB #(
.DataWidth( 32 ),
.AddressRange( 5040 ),
.AddressWidth( 13 ))
ST_WandB_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.address0( ST_WandB_address0 ),
.ce0( ST_WandB_ce0 ),
.we0( ST_WandB_we0 ),
.d0( ST_WandB_d0 ),
.q0( ST_WandB_q0 )
);
feedforward_AXILiteS_s_axi #(
.C_S_AXI_ADDR_WIDTH( C_S_AXI_AXILITES_ADDR_WIDTH ),
.C_S_AXI_DATA_WIDTH( C_S_AXI_AXILITES_DATA_WIDTH ))
feedforward_AXILiteS_s_axi_U(
.AWVALID( s_axi_AXILiteS_AWVALID ),
.AWREADY( s_axi_AXILiteS_AWREADY ),
.AWADDR( s_axi_AXILiteS_AWADDR ),
.WVALID( s_axi_AXILiteS_WVALID ),
.WREADY( s_axi_AXILiteS_WREADY ),
.WDATA( s_axi_AXILiteS_WDATA ),
.WSTRB( s_axi_AXILiteS_WSTRB ),
.ARVALID( s_axi_AXILiteS_ARVALID ),
.ARREADY( s_axi_AXILiteS_ARREADY ),
.ARADDR( s_axi_AXILiteS_ARADDR ),
.RVALID( s_axi_AXILiteS_RVALID ),
.RREADY( s_axi_AXILiteS_RREADY ),
.RDATA( s_axi_AXILiteS_RDATA ),
.RRESP( s_axi_AXILiteS_RRESP ),
.BVALID( s_axi_AXILiteS_BVALID ),
.BREADY( s_axi_AXILiteS_BREADY ),
.BRESP( s_axi_AXILiteS_BRESP ),
.ACLK( ap_clk ),
.ARESET( ap_rst_n_inv ),
.ACLK_EN( feedforward_AXILiteS_s_axi_U_ap_dummy_ce ),
.ap_start( ap_start ),
.interrupt( interrupt ),
.ap_ready( ap_ready ),
.ap_done( ap_done ),
.ap_idle( ap_idle ),
.P_mode_V( P_mode_V )
);
feedforward_p_uOut #(
.DataWidth( 32 ),
.AddressRange( 140 ),
.AddressWidth( 8 ))
p_uOut_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.address0( p_uOut_address0 ),
.ce0( p_uOut_ce0 ),
.we0( p_uOut_we0 ),
.d0( p_uOut_d0 ),
.q0( p_uOut_q0 ),
.address1( p_uOut_address1 ),
.ce1( p_uOut_ce1 ),
.q1( p_uOut_q1 )
);
feedforward_fadd_32ns_32ns_32_5_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
feedforward_fadd_32ns_32ns_32_5_full_dsp_U0(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_506_p0 ),
.din1( grp_fu_506_p1 ),
.ce( grp_fu_506_ce ),
.dout( grp_fu_506_p2 )
);
feedforward_fmul_32ns_32ns_32_4_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
feedforward_fmul_32ns_32ns_32_4_max_dsp_U1(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( p_uOut_q0 ),
.din1( ST_WandB_q0 ),
.ce( grp_fu_513_ce ),
.dout( grp_fu_513_p2 )
);
feedforward_fdiv_32ns_32ns_32_16 #(
.ID( 1 ),
.NUM_STAGE( 16 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
feedforward_fdiv_32ns_32ns_32_16_U2(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( reg_565 ),
.din1( sumsoft_reg_334 ),
.ce( grp_fu_519_ce ),
.dout( grp_fu_519_p2 )
);
feedforward_fptrunc_64ns_32_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 64 ),
.dout_WIDTH( 32 ))
feedforward_fptrunc_64ns_32_1_U3(
.din0( grp_fu_524_p0 ),
.dout( grp_fu_524_p1 )
);
feedforward_fpext_32ns_64_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
feedforward_fpext_32ns_64_1_U4(
.din0( grp_fu_527_p0 ),
.dout( grp_fu_527_p1 )
);
feedforward_fcmp_32ns_32ns_1_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
feedforward_fcmp_32ns_32ns_1_1_U5(
.din0( reg_565 ),
.din1( p_uOut_load_4_reg_1706 ),
.opcode( tmp_55_fu_530_opcode ),
.dout( tmp_55_fu_530_p2 )
);
feedforward_dadd_64ns_64ns_64_5_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
feedforward_dadd_64ns_64ns_64_5_full_dsp_U6(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( reg_599 ),
.din1( ap_const_lv64_3FF0000000000000 ),
.ce( grp_fu_534_ce ),
.dout( grp_fu_534_p2 )
);
feedforward_ddiv_64ns_64ns_64_31 #(
.ID( 1 ),
.NUM_STAGE( 31 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
feedforward_ddiv_64ns_64ns_64_31_U7(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( ap_const_lv64_3FF0000000000000 ),
.din1( tmp_30_reg_1579 ),
.ce( grp_fu_539_ce ),
.dout( grp_fu_539_p2 )
);
feedforward_dexp_64ns_64ns_64_18_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 18 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
feedforward_dexp_64ns_64ns_64_18_full_dsp_U8(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( ap_const_lv64_0 ),
.din1( reg_594 ),
.ce( grp_fu_544_ce ),
.dout( grp_fu_544_p2 )
);
feedforward_mux_4to1_sel2_8_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 8 ),
.din2_WIDTH( 8 ),
.din3_WIDTH( 8 ),
.din4_WIDTH( 8 ),
.din5_WIDTH( 2 ),
.dout_WIDTH( 8 ))
feedforward_mux_4to1_sel2_8_1_U9(
.din1( ST_layerSize_V_0 ),
.din2( ST_layerSize_V_1 ),
.din3( ST_layerSize_V_2 ),
.din4( ST_layerSize_V_3 ),
.din5( tmp_6_reg_1484 ),
.dout( tmp_12_fu_739_p6 )
);
feedforward_mux_4to1_sel2_8_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 8 ),
.din2_WIDTH( 8 ),
.din3_WIDTH( 8 ),
.din4_WIDTH( 8 ),
.din5_WIDTH( 2 ),
.dout_WIDTH( 8 ))
feedforward_mux_4to1_sel2_8_1_U10(
.din1( ST_layerSize_V_0 ),
.din2( ST_layerSize_V_1 ),
.din3( ST_layerSize_V_2 ),
.din4( ST_layerSize_V_3 ),
.din5( tmp_20_reg_1494 ),
.dout( tmp_19_fu_768_p6 )
);
feedforward_mux_4to1_sel2_8_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 8 ),
.din2_WIDTH( 8 ),
.din3_WIDTH( 8 ),
.din4_WIDTH( 8 ),
.din5_WIDTH( 2 ),
.dout_WIDTH( 8 ))
feedforward_mux_4to1_sel2_8_1_U11(
.din1( ST_layerSize_V_0 ),
.din2( ST_layerSize_V_1 ),
.din3( ST_layerSize_V_2 ),
.din4( ST_layerSize_V_3 ),
.din5( tmp_26_reg_1511 ),
.dout( tmp_15_fu_894_p6 )
);
feedforward_mux_4to1_sel2_8_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 8 ),
.din2_WIDTH( 8 ),
.din3_WIDTH( 8 ),
.din4_WIDTH( 8 ),
.din5_WIDTH( 2 ),
.dout_WIDTH( 8 ))
feedforward_mux_4to1_sel2_8_1_U12(
.din1( ST_layerSize_V_0 ),
.din2( ST_layerSize_V_1 ),
.din3( ST_layerSize_V_2 ),
.din4( ST_layerSize_V_3 ),
.din5( tmp_35_reg_1521 ),
.dout( tmp_23_fu_923_p6 )
);
feedforward_mux_4to1_sel2_8_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 8 ),
.din2_WIDTH( 8 ),
.din3_WIDTH( 8 ),
.din4_WIDTH( 8 ),
.din5_WIDTH( 2 ),
.dout_WIDTH( 8 ))
feedforward_mux_4to1_sel2_8_1_U13(
.din1( ST_layerSize_V_0 ),
.din2( ST_layerSize_V_1 ),
.din3( ST_layerSize_V_2 ),
.din4( ST_layerSize_V_3 ),
.din5( tmp_75_reg_1701 ),
.dout( tmp_57_fu_1216_p6 )
);
feedforward_mux_4to1_sel2_8_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 8 ),
.din2_WIDTH( 8 ),
.din3_WIDTH( 8 ),
.din4_WIDTH( 8 ),
.din5_WIDTH( 2 ),
.dout_WIDTH( 8 ))
feedforward_mux_4to1_sel2_8_1_U14(
.din1( ST_layerSize_V_0 ),
.din2( ST_layerSize_V_1 ),
.din3( ST_layerSize_V_2 ),
.din4( ST_layerSize_V_3 ),
.din5( tmp_7_t_reg_1753 ),
.dout( tmp_25_fu_1359_p6 )
);
always @ (posedge ap_clk) begin : ap_ret_ap_CS_fsm
if (ap_rst_n_inv == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin : ap_ret_ap_reg_ioackin_P_netOut_V_TREADY
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ioackin_P_netOut_V_TREADY <= ap_const_logic_0;
end else begin
if (ap_sig_bdd_942) begin
if (~((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == tmp_44_fu_1062_p2) & (ap_const_logic_0 == ap_sig_ioackin_P_netOut_V_TREADY))) begin
ap_reg_ioackin_P_netOut_V_TREADY <= ap_const_logic_0;
end else if ((ap_const_logic_1 == P_netOut_V_TREADY)) begin
ap_reg_ioackin_P_netOut_V_TREADY <= ap_const_logic_1;
end
end
end
end
always @ (posedge ap_clk) begin : ap_ret_ap_reg_ioackin_P_uOut_TREADY
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st144_fsm_143)) begin
if (~(ap_const_logic_0 == ap_sig_ioackin_P_uOut_TREADY)) begin
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
end else if ((ap_const_logic_1 == P_uOut_TREADY)) begin
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_1;
end
end
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st146_fsm_145)) begin
if (ap_sig_bdd_724) begin
ST_layerSize_V_load_1_phi_reg_473 <= ST_layerSize_V_3;
end else if ((tmp_4_reg_1749 == ap_const_lv2_2)) begin
ST_layerSize_V_load_1_phi_reg_473 <= ST_layerSize_V_2;
end else if ((tmp_4_reg_1749 == ap_const_lv2_1)) begin
ST_layerSize_V_load_1_phi_reg_473 <= ST_layerSize_V_1;
end
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & (tmp_fu_611_p2 == ap_const_lv1_0) & ~ap_sig_bdd_404 & ~(ap_const_lv1_0 == tmp_1_fu_621_p2))) begin
i_1_reg_449 <= ap_const_lv8_1;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st147_fsm_146) & (ap_const_lv1_0 == tmp_11_fu_1298_p2))) begin
i_1_reg_449 <= i_9_fu_1339_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & (tmp_fu_611_p2 == ap_const_lv1_0) & ~ap_sig_bdd_404 & (ap_const_lv1_0 == tmp_1_fu_621_p2))) begin
i_2_reg_277 <= ap_const_lv8_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond1_fu_633_p2) & ~ap_sig_bdd_434)) begin
i_2_reg_277 <= i_8_fu_638_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~ap_sig_bdd_434 & ~(ap_const_lv1_0 == exitcond1_fu_633_p2))) begin
i_3_reg_288 <= ap_const_lv8_1;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (ap_const_lv1_0 == tmp_14_fu_756_p2))) begin
i_3_reg_288 <= i_10_fu_821_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == tmp_7_fu_649_p2))) begin
i_4_reg_346 <= ap_const_lv32_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st119_fsm_118)) begin
i_4_reg_346 <= i_12_reg_1598;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st78_fsm_77) & (ap_const_lv1_0 == tmp_18_fu_911_p2))) begin
i_5_reg_380 <= ap_const_lv8_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st138_fsm_137)) begin
i_5_reg_380 <= i_11_reg_1651;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st143_fsm_142) & (ap_const_lv1_0 == tmp_59_fu_1233_p2))) begin
i_6_reg_416 <= i_14_reg_1696;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st120_fsm_119) & ~(ap_const_lv1_0 == exitcond4_fu_1032_p2) & ~(ap_const_lv1_0 == tmp_41_fu_1057_p2))) begin
i_6_reg_416 <= ap_const_lv8_0;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st149_fsm_148) & (ap_const_lv1_0 == exitcond5_fu_1398_p2) & ~ap_sig_bdd_769)) begin
i_reg_495 <= i_7_fu_1403_p2;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(tmp_fu_611_p2 == ap_const_lv1_0) & ~ap_sig_bdd_404)) begin
i_reg_495 <= ap_const_lv8_0;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~(ap_const_lv1_0 == tmp_7_fu_649_p2))) begin
j_1_reg_300 <= ap_const_lv32_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st77_fsm_76)) begin
j_1_reg_300 <= j_5_reg_1529;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st78_fsm_77) & ~(ap_const_lv1_0 == tmp_18_fu_911_p2))) begin
j_2_reg_369 <= ap_const_lv8_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st88_fsm_87)) begin
j_2_reg_369 <= j_6_reg_1623;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st139_fsm_138) & (ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & ~((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == tmp_44_fu_1062_p2) & (ap_const_logic_0 == ap_sig_ioackin_P_netOut_V_TREADY)) & ~(ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == exitcond_fu_1105_p2))) begin
j_3_reg_438 <= ap_const_lv32_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st144_fsm_143) & ~(ap_const_logic_0 == ap_sig_ioackin_P_uOut_TREADY))) begin
j_3_reg_438 <= j_7_reg_1730;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st148_fsm_147) & (ap_const_lv1_0 == tmp_22_fu_1386_p2) & ~ap_sig_bdd_755)) begin
j_reg_461 <= j_4_reg_1758;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st145_fsm_144) & ~(ap_const_lv1_0 == tmp_9_fu_1259_p2))) begin
j_reg_461 <= ap_const_lv32_0;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(ap_const_lv1_0 == tmp_14_fu_756_p2))) begin
k_1_reg_323 <= ap_const_lv8_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st14_fsm_13)) begin
k_1_reg_323 <= k_3_reg_1559;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st147_fsm_146) & ~(ap_const_lv1_0 == tmp_11_fu_1298_p2))) begin
k_reg_484 <= ap_const_lv32_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st148_fsm_147) & ~(ap_const_lv1_0 == tmp_22_fu_1386_p2) & ~ap_sig_bdd_755)) begin
k_reg_484 <= k_2_fu_1392_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st120_fsm_119) & ~(ap_const_lv1_0 == exitcond4_fu_1032_p2) & (ap_const_lv1_0 == tmp_41_fu_1057_p2))) begin
p_netOut_V_reg_404 <= ap_const_lv8_1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st142_fsm_141)) begin
p_netOut_V_reg_404 <= i_15_fu_1210_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st120_fsm_119) & ~(ap_const_lv1_0 == exitcond4_fu_1032_p2) & (ap_const_lv1_0 == tmp_41_fu_1057_p2))) begin
p_s_reg_391 <= ap_const_lv8_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st142_fsm_141)) begin
p_s_reg_391 <= p_netOut_V_1_fu_1203_p3;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st143_fsm_142) & (ap_const_lv1_0 == tmp_59_fu_1233_p2))) begin
phi_mul_reg_427 <= next_mul_reg_1688;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st120_fsm_119) & ~(ap_const_lv1_0 == exitcond4_fu_1032_p2) & ~(ap_const_lv1_0 == tmp_41_fu_1057_p2))) begin
phi_mul_reg_427 <= ap_const_lv14_0;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st78_fsm_77) & ~(ap_const_lv1_0 == tmp_18_fu_911_p2))) begin
sum_1_reg_357 <= ap_const_lv32_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st88_fsm_87)) begin
sum_1_reg_357 <= grp_fu_506_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(ap_const_lv1_0 == tmp_14_fu_756_p2))) begin
sum_reg_311 <= ap_const_lv32_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st14_fsm_13)) begin
sum_reg_311 <= grp_fu_506_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == tmp_7_fu_649_p2))) begin
sumsoft_reg_334 <= ap_const_lv32_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st119_fsm_118)) begin
sumsoft_reg_334 <= grp_fu_506_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(tmp_fu_611_p2 == ap_const_lv1_0) & ~ap_sig_bdd_404)) begin
P_config_V_read_reg_1463 <= P_config_V_TDATA;
ST_numLayer_V <= P_config_V_TDATA;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_404)) begin
P_mode_V_read_reg_1437 <= P_mode_V;
ST_numLayer_V_load_reg_1446 <= ST_numLayer_V;
tmp_reg_1442 <= tmp_fu_611_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st149_fsm_148) & (ap_const_lv1_0 == exitcond5_fu_1398_p2) & ~ap_sig_bdd_769 & (tmp_2_fu_1409_p1 == ap_const_lv2_0))) begin
ST_layerSize_V_0 <= P_config_V_TDATA;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & (tmp_fu_611_p2 == ap_const_lv1_0) & ~ap_sig_bdd_404 & (ap_const_lv1_0 == tmp_1_fu_621_p2))) begin
ST_layerSize_V_0_load_reg_1458 <= ST_layerSize_V_0;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st149_fsm_148) & (ap_const_lv1_0 == exitcond5_fu_1398_p2) & ~ap_sig_bdd_769 & (ap_const_lv2_1 == tmp_2_fu_1409_p1))) begin
ST_layerSize_V_1 <= P_config_V_TDATA;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st149_fsm_148) & (ap_const_lv1_0 == exitcond5_fu_1398_p2) & ~ap_sig_bdd_769 & (ap_const_lv2_2 == tmp_2_fu_1409_p1))) begin
ST_layerSize_V_2 <= P_config_V_TDATA;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st149_fsm_148) & (ap_const_lv1_0 == exitcond5_fu_1398_p2) & ~ap_sig_bdd_769 & ~(ap_const_lv2_2 == tmp_2_fu_1409_p1) & ~(ap_const_lv2_1 == tmp_2_fu_1409_p1) & ~(tmp_2_fu_1409_p1 == ap_const_lv2_0))) begin
ST_layerSize_V_3 <= P_config_V_TDATA;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st149_fsm_148) & ~ap_sig_bdd_769)) begin
exitcond5_reg_1799 <= exitcond5_fu_1398_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st120_fsm_119)) begin
i_11_reg_1651 <= i_11_fu_1037_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st78_fsm_77)) begin
i_12_reg_1598 <= i_12_fu_917_p2;
tmp_15_reg_1589 <= tmp_15_fu_894_p6;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st139_fsm_138) & (ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & ~((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == tmp_44_fu_1062_p2) & (ap_const_logic_0 == ap_sig_ioackin_P_netOut_V_TREADY)) & ~(ap_const_lv1_0 == tmp_41_reg_1661))) begin
i_14_reg_1696 <= i_14_fu_1110_p2;
next_mul_reg_1688 <= next_mul_fu_1099_p2;
tmp_74_reg_1683 <= tmp_74_fu_1095_p1;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st146_fsm_145)) begin
j_4_reg_1758 <= j_4_fu_1288_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3)) begin
j_5_reg_1529 <= j_5_fu_762_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st79_fsm_78)) begin
j_6_reg_1623 <= j_6_fu_985_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st143_fsm_142)) begin
j_7_reg_1730 <= j_7_fu_1239_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
k_3_reg_1559 <= k_3_fu_832_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(ap_const_lv1_0 == tmp_14_fu_756_p2))) begin
p_uOut_addr_1_reg_1546 <= tmp_70_cast_fu_786_p1;
tmp_19_reg_1534 <= tmp_19_fu_768_p6;
tmp_60_reg_1540[13 : 2] <= tmp_60_fu_815_p2[13 : 2];
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st78_fsm_77) & ~(ap_const_lv1_0 == tmp_18_fu_911_p2))) begin
p_uOut_addr_3_reg_1615 <= tmp_74_cast_fu_945_p1;
tmp_23_reg_1603 <= tmp_23_fu_923_p6;
tmp_64_reg_1609[13 : 2] <= tmp_64_fu_974_p2[13 : 2];
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st120_fsm_119) & (ap_const_lv1_0 == exitcond4_fu_1032_p2))) begin
p_uOut_addr_5_reg_1656 <= tmp_85_cast_fu_1052_p1;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st140_fsm_139)) begin
p_uOut_load_4_reg_1706 <= p_uOut_q1;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5) | (ap_const_logic_1 == ap_sig_cseq_ST_st80_fsm_79) | (ap_const_logic_1 == ap_sig_cseq_ST_st121_fsm_120) | (ap_const_logic_1 == ap_sig_cseq_ST_st140_fsm_139))) begin
reg_565 <= p_uOut_q0;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5) | (ap_const_logic_1 == ap_sig_cseq_ST_st80_fsm_79) | (ap_const_logic_1 == ap_sig_cseq_ST_st15_fsm_14) | (ap_const_logic_1 == ap_sig_cseq_ST_st89_fsm_88))) begin
reg_572 <= ST_WandB_q0;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_8) | (ap_const_logic_1 == ap_sig_cseq_ST_st83_fsm_82))) begin
reg_578 <= grp_fu_513_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st20_fsm_19) | (ap_const_logic_1 == ap_sig_cseq_ST_st94_fsm_93))) begin
reg_589 <= grp_fu_506_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st21_fsm_20) | (ap_const_logic_1 == ap_sig_cseq_ST_st95_fsm_94))) begin
reg_594 <= grp_fu_527_p1;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st39_fsm_38) | (ap_const_logic_1 == ap_sig_cseq_ST_st113_fsm_112))) begin
reg_599 <= grp_fu_544_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st76_fsm_75) | (ap_const_logic_1 == ap_sig_cseq_ST_st114_fsm_113))) begin
reg_605 <= grp_fu_524_p1;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~(ap_const_lv1_0 == tmp_7_fu_649_p2))) begin
tmp_16_reg_1489 <= tmp_16_fu_682_p2;
tmp_20_reg_1494 <= tmp_20_fu_688_p1;
tmp_62_cast_reg_1479[14 : 0] <= tmp_62_cast_fu_664_p1[14 : 0];
tmp_6_reg_1484 <= tmp_6_fu_668_p1;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & (tmp_fu_611_p2 == ap_const_lv1_0) & ~ap_sig_bdd_404)) begin
tmp_1_reg_1454 <= tmp_1_fu_621_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == tmp_7_fu_649_p2))) begin
tmp_24_reg_1499 <= tmp_24_fu_711_p1;
tmp_26_reg_1511 <= tmp_26_fu_719_p1;
tmp_33_reg_1516 <= tmp_33_fu_729_p2;
tmp_35_reg_1521 <= tmp_35_fu_735_p1;
tmp_64_cast_reg_1506 <= tmp_64_cast_fu_715_p1;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st44_fsm_43)) begin
tmp_30_reg_1579 <= grp_fu_534_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st75_fsm_74)) begin
tmp_31_reg_1584 <= grp_fu_539_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st120_fsm_119) & ~(ap_const_lv1_0 == exitcond4_fu_1032_p2))) begin
tmp_41_reg_1661 <= tmp_41_fu_1057_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st137_fsm_136)) begin
tmp_43_reg_1665 <= grp_fu_519_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st147_fsm_146) & ~(ap_const_lv1_0 == tmp_11_fu_1298_p2))) begin
tmp_46_reg_1781[13 : 2] <= tmp_46_fu_1333_p2[13 : 2];
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st145_fsm_144) & ~(ap_const_lv1_0 == tmp_9_fu_1259_p2))) begin
tmp_4_reg_1749 <= tmp_4_fu_1278_p1;
tmp_61_cast_reg_1744[14 : 0] <= tmp_61_cast_fu_1274_p1[14 : 0];
tmp_7_t_reg_1753 <= tmp_7_t_fu_1282_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st141_fsm_140)) begin
tmp_56_reg_1712 <= tmp_56_fu_1197_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st139_fsm_138) & (ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & ~((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == tmp_44_fu_1062_p2) & (ap_const_logic_0 == ap_sig_ioackin_P_netOut_V_TREADY)) & ~(ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == exitcond_fu_1105_p2))) begin
tmp_75_reg_1701 <= tmp_75_fu_1116_p1;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st145_fsm_144)) begin
tmp_9_reg_1740 <= tmp_9_fu_1259_p2;
end
end
always @ (ap_sig_cseq_ST_st148_fsm_147 or tmp_22_fu_1386_p2 or ap_sig_bdd_755) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st148_fsm_147) & ~(ap_const_lv1_0 == tmp_22_fu_1386_p2) & ~ap_sig_bdd_755)) begin
P_WandB_TREADY = ap_const_logic_1;
end else begin
P_WandB_TREADY = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st1_fsm_0 or tmp_fu_611_p2 or ap_sig_bdd_404 or exitcond5_fu_1398_p2 or ap_sig_cseq_ST_st149_fsm_148 or ap_sig_bdd_769) begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(tmp_fu_611_p2 == ap_const_lv1_0) & ~ap_sig_bdd_404) | ((ap_const_logic_1 == ap_sig_cseq_ST_st149_fsm_148) & (ap_const_lv1_0 == exitcond5_fu_1398_p2) & ~ap_sig_bdd_769))) begin
P_config_V_TREADY = ap_const_logic_1;
end else begin
P_config_V_TREADY = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st2_fsm_1 or exitcond1_fu_633_p2 or ap_sig_bdd_434) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond1_fu_633_p2) & ~ap_sig_bdd_434)) begin
P_netIn_TREADY = ap_const_logic_1;
end else begin
P_netIn_TREADY = ap_const_logic_0;
end
end
always @ (tmp_reg_1442 or tmp_1_reg_1454 or tmp_41_reg_1661 or ap_sig_cseq_ST_st139_fsm_138 or tmp_44_fu_1062_p2 or ap_reg_ioackin_P_netOut_V_TREADY) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st139_fsm_138) & (ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == tmp_44_fu_1062_p2) & (ap_const_logic_0 == ap_reg_ioackin_P_netOut_V_TREADY))) begin
P_netOut_V_TVALID = ap_const_logic_1;
end else begin
P_netOut_V_TVALID = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st144_fsm_143 or ap_reg_ioackin_P_uOut_TREADY) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st144_fsm_143) & (ap_const_logic_0 == ap_reg_ioackin_P_uOut_TREADY))) begin
P_uOut_TVALID = ap_const_logic_1;
end else begin
P_uOut_TVALID = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st5_fsm_4 or exitcond2_fu_827_p2 or ap_sig_cseq_ST_st79_fsm_78 or exitcond3_fu_980_p2 or ap_sig_cseq_ST_st148_fsm_147 or tmp_80_cast_fu_851_p1 or tmp_79_cast_fu_874_p1 or tmp_83_cast_fu_1004_p1 or tmp_82_cast_fu_1027_p1 or tmp_78_cast_fu_1354_p1) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st148_fsm_147)) begin
ST_WandB_address0 = tmp_78_cast_fu_1354_p1;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st79_fsm_78) & ~(ap_const_lv1_0 == exitcond3_fu_980_p2))) begin
ST_WandB_address0 = tmp_82_cast_fu_1027_p1;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st79_fsm_78) & (ap_const_lv1_0 == exitcond3_fu_980_p2))) begin
ST_WandB_address0 = tmp_83_cast_fu_1004_p1;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & ~(ap_const_lv1_0 == exitcond2_fu_827_p2))) begin
ST_WandB_address0 = tmp_79_cast_fu_874_p1;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & (ap_const_lv1_0 == exitcond2_fu_827_p2))) begin
ST_WandB_address0 = tmp_80_cast_fu_851_p1;
end else begin
ST_WandB_address0 = 'bx;
end
end
always @ (ap_sig_cseq_ST_st5_fsm_4 or exitcond2_fu_827_p2 or ap_sig_cseq_ST_st79_fsm_78 or exitcond3_fu_980_p2 or ap_sig_cseq_ST_st148_fsm_147 or ap_sig_bdd_755) begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & (ap_const_lv1_0 == exitcond2_fu_827_p2)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & ~(ap_const_lv1_0 == exitcond2_fu_827_p2)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st79_fsm_78) & (ap_const_lv1_0 == exitcond3_fu_980_p2)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st79_fsm_78) & ~(ap_const_lv1_0 == exitcond3_fu_980_p2)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st148_fsm_147) & ~ap_sig_bdd_755))) begin
ST_WandB_ce0 = ap_const_logic_1;
end else begin
ST_WandB_ce0 = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st148_fsm_147 or tmp_22_fu_1386_p2 or ap_sig_bdd_755) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st148_fsm_147) & ~(ap_const_lv1_0 == tmp_22_fu_1386_p2) & ~ap_sig_bdd_755)) begin
ST_WandB_we0 = ap_const_logic_1;
end else begin
ST_WandB_we0 = ap_const_logic_0;
end
end
always @ (tmp_reg_1442 or tmp_1_reg_1454 or tmp_41_reg_1661 or ap_sig_cseq_ST_st139_fsm_138 or tmp_44_fu_1062_p2 or ap_sig_ioackin_P_netOut_V_TREADY or exitcond_fu_1105_p2 or tmp_9_reg_1740 or exitcond5_reg_1799) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st139_fsm_138) & ~((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == tmp_44_fu_1062_p2) & (ap_const_logic_0 == ap_sig_ioackin_P_netOut_V_TREADY)) & (((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == tmp_44_fu_1062_p2)) | (~(ap_const_lv1_0 == tmp_reg_1442) & ~(ap_const_lv1_0 == exitcond5_reg_1799)) | ((ap_const_lv1_0 == tmp_reg_1442) & ~(ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_9_reg_1740)) | ((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & ~(ap_const_lv1_0 == tmp_41_reg_1661) & ~(ap_const_lv1_0 == exitcond_fu_1105_p2))))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0) begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
always @ (tmp_reg_1442 or tmp_1_reg_1454 or tmp_41_reg_1661 or ap_sig_cseq_ST_st139_fsm_138 or tmp_44_fu_1062_p2 or ap_sig_ioackin_P_netOut_V_TREADY or exitcond_fu_1105_p2 or tmp_9_reg_1740 or exitcond5_reg_1799) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st139_fsm_138) & ~((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == tmp_44_fu_1062_p2) & (ap_const_logic_0 == ap_sig_ioackin_P_netOut_V_TREADY)) & (((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == tmp_44_fu_1062_p2)) | (~(ap_const_lv1_0 == tmp_reg_1442) & ~(ap_const_lv1_0 == exitcond5_reg_1799)) | ((ap_const_lv1_0 == tmp_reg_1442) & ~(ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_9_reg_1740)) | ((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & ~(ap_const_lv1_0 == tmp_41_reg_1661) & ~(ap_const_lv1_0 == exitcond_fu_1105_p2))))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_987) begin
if (ap_sig_bdd_987) begin
ap_sig_cseq_ST_st10_fsm_9 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st10_fsm_9 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_374) begin
if (ap_sig_bdd_374) begin
ap_sig_cseq_ST_st113_fsm_112 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st113_fsm_112 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_391) begin
if (ap_sig_bdd_391) begin
ap_sig_cseq_ST_st114_fsm_113 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st114_fsm_113 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_963) begin
if (ap_sig_bdd_963) begin
ap_sig_cseq_ST_st115_fsm_114 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st115_fsm_114 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_574) begin
if (ap_sig_bdd_574) begin
ap_sig_cseq_ST_st119_fsm_118 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st119_fsm_118 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_583) begin
if (ap_sig_bdd_583) begin
ap_sig_cseq_ST_st120_fsm_119 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st120_fsm_119 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_264) begin
if (ap_sig_bdd_264) begin
ap_sig_cseq_ST_st121_fsm_120 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st121_fsm_120 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_601) begin
if (ap_sig_bdd_601) begin
ap_sig_cseq_ST_st137_fsm_136 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st137_fsm_136 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_821) begin
if (ap_sig_bdd_821) begin
ap_sig_cseq_ST_st138_fsm_137 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st138_fsm_137 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_610) begin
if (ap_sig_bdd_610) begin
ap_sig_cseq_ST_st139_fsm_138 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st139_fsm_138 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_272) begin
if (ap_sig_bdd_272) begin
ap_sig_cseq_ST_st140_fsm_139 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st140_fsm_139 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_654) begin
if (ap_sig_bdd_654) begin
ap_sig_cseq_ST_st141_fsm_140 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st141_fsm_140 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_663) begin
if (ap_sig_bdd_663) begin
ap_sig_cseq_ST_st142_fsm_141 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st142_fsm_141 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_674) begin
if (ap_sig_bdd_674) begin
ap_sig_cseq_ST_st143_fsm_142 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st143_fsm_142 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_847) begin
if (ap_sig_bdd_847) begin
ap_sig_cseq_ST_st144_fsm_143 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st144_fsm_143 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_689) begin
if (ap_sig_bdd_689) begin
ap_sig_cseq_ST_st145_fsm_144 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st145_fsm_144 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_707) begin
if (ap_sig_bdd_707) begin
ap_sig_cseq_ST_st146_fsm_145 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st146_fsm_145 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_732) begin
if (ap_sig_bdd_732) begin
ap_sig_cseq_ST_st147_fsm_146 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st147_fsm_146 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_748) begin
if (ap_sig_bdd_748) begin
ap_sig_cseq_ST_st148_fsm_147 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st148_fsm_147 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_765) begin
if (ap_sig_bdd_765) begin
ap_sig_cseq_ST_st149_fsm_148 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st149_fsm_148 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_317) begin
if (ap_sig_bdd_317) begin
ap_sig_cseq_ST_st14_fsm_13 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st14_fsm_13 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_281) begin
if (ap_sig_bdd_281) begin
ap_sig_cseq_ST_st15_fsm_14 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st15_fsm_14 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_994) begin
if (ap_sig_bdd_994) begin
ap_sig_cseq_ST_st16_fsm_15 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st16_fsm_15 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_167) begin
if (ap_sig_bdd_167) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_333) begin
if (ap_sig_bdd_333) begin
ap_sig_cseq_ST_st20_fsm_19 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st20_fsm_19 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_350) begin
if (ap_sig_bdd_350) begin
ap_sig_cseq_ST_st21_fsm_20 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st21_fsm_20 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_428) begin
if (ap_sig_bdd_428) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_367) begin
if (ap_sig_bdd_367) begin
ap_sig_cseq_ST_st39_fsm_38 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st39_fsm_38 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_444) begin
if (ap_sig_bdd_444) begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_516) begin
if (ap_sig_bdd_516) begin
ap_sig_cseq_ST_st44_fsm_43 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st44_fsm_43 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_474) begin
if (ap_sig_bdd_474) begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_496) begin
if (ap_sig_bdd_496) begin
ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_249) begin
if (ap_sig_bdd_249) begin
ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_525) begin
if (ap_sig_bdd_525) begin
ap_sig_cseq_ST_st75_fsm_74 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st75_fsm_74 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_384) begin
if (ap_sig_bdd_384) begin
ap_sig_cseq_ST_st76_fsm_75 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st76_fsm_75 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_800) begin
if (ap_sig_bdd_800) begin
ap_sig_cseq_ST_st77_fsm_76 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st77_fsm_76 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_534) begin
if (ap_sig_bdd_534) begin
ap_sig_cseq_ST_st78_fsm_77 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st78_fsm_77 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_555) begin
if (ap_sig_bdd_555) begin
ap_sig_cseq_ST_st79_fsm_78 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st79_fsm_78 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_256) begin
if (ap_sig_bdd_256) begin
ap_sig_cseq_ST_st80_fsm_79 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st80_fsm_79 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_307) begin
if (ap_sig_bdd_307) begin
ap_sig_cseq_ST_st83_fsm_82 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st83_fsm_82 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_1002) begin
if (ap_sig_bdd_1002) begin
ap_sig_cseq_ST_st84_fsm_83 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st84_fsm_83 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_324) begin
if (ap_sig_bdd_324) begin
ap_sig_cseq_ST_st88_fsm_87 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st88_fsm_87 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_290) begin
if (ap_sig_bdd_290) begin
ap_sig_cseq_ST_st89_fsm_88 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st89_fsm_88 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_1009) begin
if (ap_sig_bdd_1009) begin
ap_sig_cseq_ST_st90_fsm_89 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st90_fsm_89 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_340) begin
if (ap_sig_bdd_340) begin
ap_sig_cseq_ST_st94_fsm_93 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st94_fsm_93 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_357) begin
if (ap_sig_bdd_357) begin
ap_sig_cseq_ST_st95_fsm_94 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st95_fsm_94 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_300) begin
if (ap_sig_bdd_300) begin
ap_sig_cseq_ST_st9_fsm_8 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st9_fsm_8 = ap_const_logic_0;
end
end
always @ (P_netOut_V_TREADY or ap_reg_ioackin_P_netOut_V_TREADY) begin
if ((ap_const_logic_0 == ap_reg_ioackin_P_netOut_V_TREADY)) begin
ap_sig_ioackin_P_netOut_V_TREADY = P_netOut_V_TREADY;
end else begin
ap_sig_ioackin_P_netOut_V_TREADY = ap_const_logic_1;
end
end
always @ (P_uOut_TREADY or ap_reg_ioackin_P_uOut_TREADY) begin
if ((ap_const_logic_0 == ap_reg_ioackin_P_uOut_TREADY)) begin
ap_sig_ioackin_P_uOut_TREADY = P_uOut_TREADY;
end else begin
ap_sig_ioackin_P_uOut_TREADY = ap_const_logic_1;
end
end
always @ (sum_reg_311 or sumsoft_reg_334 or sum_1_reg_357 or ap_sig_cseq_ST_st115_fsm_114 or ap_sig_cseq_ST_st10_fsm_9 or ap_sig_cseq_ST_st16_fsm_15 or ap_sig_cseq_ST_st84_fsm_83 or ap_sig_cseq_ST_st90_fsm_89) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st115_fsm_114)) begin
grp_fu_506_p0 = sumsoft_reg_334;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st84_fsm_83) | (ap_const_logic_1 == ap_sig_cseq_ST_st90_fsm_89))) begin
grp_fu_506_p0 = sum_1_reg_357;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9) | (ap_const_logic_1 == ap_sig_cseq_ST_st16_fsm_15))) begin
grp_fu_506_p0 = sum_reg_311;
end else begin
grp_fu_506_p0 = 'bx;
end
end
always @ (reg_572 or reg_578 or reg_605 or ap_sig_cseq_ST_st115_fsm_114 or ap_sig_cseq_ST_st10_fsm_9 or ap_sig_cseq_ST_st16_fsm_15 or ap_sig_cseq_ST_st84_fsm_83 or ap_sig_cseq_ST_st90_fsm_89) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st115_fsm_114)) begin
grp_fu_506_p1 = reg_605;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st16_fsm_15) | (ap_const_logic_1 == ap_sig_cseq_ST_st90_fsm_89))) begin
grp_fu_506_p1 = reg_572;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9) | (ap_const_logic_1 == ap_sig_cseq_ST_st84_fsm_83))) begin
grp_fu_506_p1 = reg_578;
end else begin
grp_fu_506_p1 = 'bx;
end
end
always @ (reg_599 or ap_sig_cseq_ST_st76_fsm_75 or ap_sig_cseq_ST_st114_fsm_113 or tmp_31_reg_1584) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st114_fsm_113)) begin
grp_fu_524_p0 = reg_599;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st76_fsm_75)) begin
grp_fu_524_p0 = tmp_31_reg_1584;
end else begin
grp_fu_524_p0 = 'bx;
end
end
always @ (reg_589 or ap_sig_cseq_ST_st21_fsm_20 or ap_sig_cseq_ST_st95_fsm_94 or tmp_27_fu_889_p1) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st95_fsm_94)) begin
grp_fu_527_p0 = reg_589;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st21_fsm_20)) begin
grp_fu_527_p0 = tmp_27_fu_889_p1;
end else begin
grp_fu_527_p0 = 'bx;
end
end
always @ (ap_sig_cseq_ST_st2_fsm_1 or p_uOut_addr_1_reg_1546 or ap_sig_cseq_ST_st5_fsm_4 or p_uOut_addr_3_reg_1615 or ap_sig_cseq_ST_st79_fsm_78 or ap_sig_cseq_ST_st120_fsm_119 or p_uOut_addr_5_reg_1656 or ap_sig_cseq_ST_st139_fsm_138 or ap_sig_cseq_ST_st77_fsm_76 or ap_sig_cseq_ST_st138_fsm_137 or tmp_8_fu_644_p1 or tmp_81_cast_fu_861_p1 or tmp_84_cast_fu_1014_p1 or tmp_85_cast_fu_1052_p1 or tmp_87_cast_fu_1076_p1 or ap_sig_cseq_ST_st115_fsm_114) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st138_fsm_137)) begin
p_uOut_address0 = p_uOut_addr_5_reg_1656;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st115_fsm_114)) begin
p_uOut_address0 = p_uOut_addr_3_reg_1615;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st77_fsm_76)) begin
p_uOut_address0 = p_uOut_addr_1_reg_1546;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
p_uOut_address0 = tmp_8_fu_644_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st139_fsm_138)) begin
p_uOut_address0 = tmp_87_cast_fu_1076_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st120_fsm_119)) begin
p_uOut_address0 = tmp_85_cast_fu_1052_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st79_fsm_78)) begin
p_uOut_address0 = tmp_84_cast_fu_1014_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
p_uOut_address0 = tmp_81_cast_fu_861_p1;
end else begin
p_uOut_address0 = 'bx;
end
end
always @ (ap_sig_cseq_ST_st139_fsm_138 or ap_sig_cseq_ST_st143_fsm_142 or tmp_88_cast_fu_1090_p1 or tmp_89_cast_fu_1254_p1) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st143_fsm_142)) begin
p_uOut_address1 = tmp_89_cast_fu_1254_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st139_fsm_138)) begin
p_uOut_address1 = tmp_88_cast_fu_1090_p1;
end else begin
p_uOut_address1 = 'bx;
end
end
always @ (tmp_reg_1442 or tmp_1_reg_1454 or ap_sig_cseq_ST_st2_fsm_1 or ap_sig_bdd_434 or ap_sig_cseq_ST_st5_fsm_4 or ap_sig_cseq_ST_st79_fsm_78 or ap_sig_cseq_ST_st120_fsm_119 or tmp_41_reg_1661 or ap_sig_cseq_ST_st139_fsm_138 or tmp_44_fu_1062_p2 or ap_sig_ioackin_P_netOut_V_TREADY or ap_sig_cseq_ST_st77_fsm_76 or ap_sig_cseq_ST_st138_fsm_137 or ap_sig_cseq_ST_st115_fsm_114) begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~ap_sig_bdd_434) | (ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) | (ap_const_logic_1 == ap_sig_cseq_ST_st79_fsm_78) | (ap_const_logic_1 == ap_sig_cseq_ST_st120_fsm_119) | ((ap_const_logic_1 == ap_sig_cseq_ST_st139_fsm_138) & ~((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == tmp_44_fu_1062_p2) & (ap_const_logic_0 == ap_sig_ioackin_P_netOut_V_TREADY))) | (ap_const_logic_1 == ap_sig_cseq_ST_st77_fsm_76) | (ap_const_logic_1 == ap_sig_cseq_ST_st138_fsm_137) | (ap_const_logic_1 == ap_sig_cseq_ST_st115_fsm_114))) begin
p_uOut_ce0 = ap_const_logic_1;
end else begin
p_uOut_ce0 = ap_const_logic_0;
end
end
always @ (tmp_reg_1442 or tmp_1_reg_1454 or tmp_41_reg_1661 or ap_sig_cseq_ST_st139_fsm_138 or tmp_44_fu_1062_p2 or ap_sig_ioackin_P_netOut_V_TREADY or ap_sig_cseq_ST_st143_fsm_142) begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st139_fsm_138) & ~((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == tmp_44_fu_1062_p2) & (ap_const_logic_0 == ap_sig_ioackin_P_netOut_V_TREADY))) | (ap_const_logic_1 == ap_sig_cseq_ST_st143_fsm_142))) begin
p_uOut_ce1 = ap_const_logic_1;
end else begin
p_uOut_ce1 = ap_const_logic_0;
end
end
always @ (P_netIn_TDATA or reg_605 or ap_sig_cseq_ST_st2_fsm_1 or tmp_43_reg_1665 or ap_sig_cseq_ST_st77_fsm_76 or ap_sig_cseq_ST_st138_fsm_137 or ap_sig_cseq_ST_st115_fsm_114) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st138_fsm_137)) begin
p_uOut_d0 = tmp_43_reg_1665;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st77_fsm_76) | (ap_const_logic_1 == ap_sig_cseq_ST_st115_fsm_114))) begin
p_uOut_d0 = reg_605;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
p_uOut_d0 = P_netIn_TDATA;
end else begin
p_uOut_d0 = 'bx;
end
end
always @ (ap_sig_cseq_ST_st2_fsm_1 or exitcond1_fu_633_p2 or ap_sig_bdd_434 or ap_sig_cseq_ST_st77_fsm_76 or ap_sig_cseq_ST_st138_fsm_137 or ap_sig_cseq_ST_st115_fsm_114) begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond1_fu_633_p2) & ~ap_sig_bdd_434) | (ap_const_logic_1 == ap_sig_cseq_ST_st77_fsm_76) | (ap_const_logic_1 == ap_sig_cseq_ST_st138_fsm_137) | (ap_const_logic_1 == ap_sig_cseq_ST_st115_fsm_114))) begin
p_uOut_we0 = ap_const_logic_1;
end else begin
p_uOut_we0 = ap_const_logic_0;
end
end
always @ (ap_CS_fsm or tmp_fu_611_p2 or ap_sig_bdd_404 or tmp_reg_1442 or tmp_1_fu_621_p2 or tmp_1_reg_1454 or exitcond1_fu_633_p2 or ap_sig_bdd_434 or tmp_7_fu_649_p2 or tmp_14_fu_756_p2 or exitcond2_fu_827_p2 or tmp_18_fu_911_p2 or exitcond3_fu_980_p2 or exitcond4_fu_1032_p2 or tmp_41_reg_1661 or tmp_44_fu_1062_p2 or ap_sig_ioackin_P_netOut_V_TREADY or exitcond_fu_1105_p2 or tmp_59_fu_1233_p2 or tmp_9_fu_1259_p2 or tmp_9_reg_1740 or tmp_11_fu_1298_p2 or tmp_22_fu_1386_p2 or ap_sig_bdd_755 or exitcond5_fu_1398_p2 or exitcond5_reg_1799 or ap_sig_bdd_769 or ap_sig_ioackin_P_uOut_TREADY) begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if ((~(tmp_fu_611_p2 == ap_const_lv1_0) & ~ap_sig_bdd_404)) begin
ap_NS_fsm = ap_ST_st149_fsm_148;
end else if (((tmp_fu_611_p2 == ap_const_lv1_0) & ~ap_sig_bdd_404 & (ap_const_lv1_0 == tmp_1_fu_621_p2))) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else if (((tmp_fu_611_p2 == ap_const_lv1_0) & ~ap_sig_bdd_404 & ~(ap_const_lv1_0 == tmp_1_fu_621_p2))) begin
ap_NS_fsm = ap_ST_st145_fsm_144;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if (((ap_const_lv1_0 == exitcond1_fu_633_p2) & ~ap_sig_bdd_434)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else if ((~ap_sig_bdd_434 & ~(ap_const_lv1_0 == exitcond1_fu_633_p2))) begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end else begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
end
ap_ST_st3_fsm_2 :
begin
if ((ap_const_lv1_0 == tmp_7_fu_649_p2)) begin
ap_NS_fsm = ap_ST_st78_fsm_77;
end else begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end
end
ap_ST_st4_fsm_3 :
begin
if ((ap_const_lv1_0 == tmp_14_fu_756_p2)) begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end else begin
ap_NS_fsm = ap_ST_st5_fsm_4;
end
end
ap_ST_st5_fsm_4 :
begin
if (~(ap_const_lv1_0 == exitcond2_fu_827_p2)) begin
ap_NS_fsm = ap_ST_st15_fsm_14;
end else begin
ap_NS_fsm = ap_ST_st6_fsm_5;
end
end
ap_ST_st6_fsm_5 :
begin
ap_NS_fsm = ap_ST_st7_fsm_6;
end
ap_ST_st7_fsm_6 :
begin
ap_NS_fsm = ap_ST_st8_fsm_7;
end
ap_ST_st8_fsm_7 :
begin
ap_NS_fsm = ap_ST_st9_fsm_8;
end
ap_ST_st9_fsm_8 :
begin
ap_NS_fsm = ap_ST_st10_fsm_9;
end
ap_ST_st10_fsm_9 :
begin
ap_NS_fsm = ap_ST_st11_fsm_10;
end
ap_ST_st11_fsm_10 :
begin
ap_NS_fsm = ap_ST_st12_fsm_11;
end
ap_ST_st12_fsm_11 :
begin
ap_NS_fsm = ap_ST_st13_fsm_12;
end
ap_ST_st13_fsm_12 :
begin
ap_NS_fsm = ap_ST_st14_fsm_13;
end
ap_ST_st14_fsm_13 :
begin
ap_NS_fsm = ap_ST_st5_fsm_4;
end
ap_ST_st15_fsm_14 :
begin
ap_NS_fsm = ap_ST_st16_fsm_15;
end
ap_ST_st16_fsm_15 :
begin
ap_NS_fsm = ap_ST_st17_fsm_16;
end
ap_ST_st17_fsm_16 :
begin
ap_NS_fsm = ap_ST_st18_fsm_17;
end
ap_ST_st18_fsm_17 :
begin
ap_NS_fsm = ap_ST_st19_fsm_18;
end
ap_ST_st19_fsm_18 :
begin
ap_NS_fsm = ap_ST_st20_fsm_19;
end
ap_ST_st20_fsm_19 :
begin
ap_NS_fsm = ap_ST_st21_fsm_20;
end
ap_ST_st21_fsm_20 :
begin
ap_NS_fsm = ap_ST_st22_fsm_21;
end
ap_ST_st22_fsm_21 :
begin
ap_NS_fsm = ap_ST_st23_fsm_22;
end
ap_ST_st23_fsm_22 :
begin
ap_NS_fsm = ap_ST_st24_fsm_23;
end
ap_ST_st24_fsm_23 :
begin
ap_NS_fsm = ap_ST_st25_fsm_24;
end
ap_ST_st25_fsm_24 :
begin
ap_NS_fsm = ap_ST_st26_fsm_25;
end
ap_ST_st26_fsm_25 :
begin
ap_NS_fsm = ap_ST_st27_fsm_26;
end
ap_ST_st27_fsm_26 :
begin
ap_NS_fsm = ap_ST_st28_fsm_27;
end
ap_ST_st28_fsm_27 :
begin
ap_NS_fsm = ap_ST_st29_fsm_28;
end
ap_ST_st29_fsm_28 :
begin
ap_NS_fsm = ap_ST_st30_fsm_29;
end
ap_ST_st30_fsm_29 :
begin
ap_NS_fsm = ap_ST_st31_fsm_30;
end
ap_ST_st31_fsm_30 :
begin
ap_NS_fsm = ap_ST_st32_fsm_31;
end
ap_ST_st32_fsm_31 :
begin
ap_NS_fsm = ap_ST_st33_fsm_32;
end
ap_ST_st33_fsm_32 :
begin
ap_NS_fsm = ap_ST_st34_fsm_33;
end
ap_ST_st34_fsm_33 :
begin
ap_NS_fsm = ap_ST_st35_fsm_34;
end
ap_ST_st35_fsm_34 :
begin
ap_NS_fsm = ap_ST_st36_fsm_35;
end
ap_ST_st36_fsm_35 :
begin
ap_NS_fsm = ap_ST_st37_fsm_36;
end
ap_ST_st37_fsm_36 :
begin
ap_NS_fsm = ap_ST_st38_fsm_37;
end
ap_ST_st38_fsm_37 :
begin
ap_NS_fsm = ap_ST_st39_fsm_38;
end
ap_ST_st39_fsm_38 :
begin
ap_NS_fsm = ap_ST_st40_fsm_39;
end
ap_ST_st40_fsm_39 :
begin
ap_NS_fsm = ap_ST_st41_fsm_40;
end
ap_ST_st41_fsm_40 :
begin
ap_NS_fsm = ap_ST_st42_fsm_41;
end
ap_ST_st42_fsm_41 :
begin
ap_NS_fsm = ap_ST_st43_fsm_42;
end
ap_ST_st43_fsm_42 :
begin
ap_NS_fsm = ap_ST_st44_fsm_43;
end
ap_ST_st44_fsm_43 :
begin
ap_NS_fsm = ap_ST_st45_fsm_44;
end
ap_ST_st45_fsm_44 :
begin
ap_NS_fsm = ap_ST_st46_fsm_45;
end
ap_ST_st46_fsm_45 :
begin
ap_NS_fsm = ap_ST_st47_fsm_46;
end
ap_ST_st47_fsm_46 :
begin
ap_NS_fsm = ap_ST_st48_fsm_47;
end
ap_ST_st48_fsm_47 :
begin
ap_NS_fsm = ap_ST_st49_fsm_48;
end
ap_ST_st49_fsm_48 :
begin
ap_NS_fsm = ap_ST_st50_fsm_49;
end
ap_ST_st50_fsm_49 :
begin
ap_NS_fsm = ap_ST_st51_fsm_50;
end
ap_ST_st51_fsm_50 :
begin
ap_NS_fsm = ap_ST_st52_fsm_51;
end
ap_ST_st52_fsm_51 :
begin
ap_NS_fsm = ap_ST_st53_fsm_52;
end
ap_ST_st53_fsm_52 :
begin
ap_NS_fsm = ap_ST_st54_fsm_53;
end
ap_ST_st54_fsm_53 :
begin
ap_NS_fsm = ap_ST_st55_fsm_54;
end
ap_ST_st55_fsm_54 :
begin
ap_NS_fsm = ap_ST_st56_fsm_55;
end
ap_ST_st56_fsm_55 :
begin
ap_NS_fsm = ap_ST_st57_fsm_56;
end
ap_ST_st57_fsm_56 :
begin
ap_NS_fsm = ap_ST_st58_fsm_57;
end
ap_ST_st58_fsm_57 :
begin
ap_NS_fsm = ap_ST_st59_fsm_58;
end
ap_ST_st59_fsm_58 :
begin
ap_NS_fsm = ap_ST_st60_fsm_59;
end
ap_ST_st60_fsm_59 :
begin
ap_NS_fsm = ap_ST_st61_fsm_60;
end
ap_ST_st61_fsm_60 :
begin
ap_NS_fsm = ap_ST_st62_fsm_61;
end
ap_ST_st62_fsm_61 :
begin
ap_NS_fsm = ap_ST_st63_fsm_62;
end
ap_ST_st63_fsm_62 :
begin
ap_NS_fsm = ap_ST_st64_fsm_63;
end
ap_ST_st64_fsm_63 :
begin
ap_NS_fsm = ap_ST_st65_fsm_64;
end
ap_ST_st65_fsm_64 :
begin
ap_NS_fsm = ap_ST_st66_fsm_65;
end
ap_ST_st66_fsm_65 :
begin
ap_NS_fsm = ap_ST_st67_fsm_66;
end
ap_ST_st67_fsm_66 :
begin
ap_NS_fsm = ap_ST_st68_fsm_67;
end
ap_ST_st68_fsm_67 :
begin
ap_NS_fsm = ap_ST_st69_fsm_68;
end
ap_ST_st69_fsm_68 :
begin
ap_NS_fsm = ap_ST_st70_fsm_69;
end
ap_ST_st70_fsm_69 :
begin
ap_NS_fsm = ap_ST_st71_fsm_70;
end
ap_ST_st71_fsm_70 :
begin
ap_NS_fsm = ap_ST_st72_fsm_71;
end
ap_ST_st72_fsm_71 :
begin
ap_NS_fsm = ap_ST_st73_fsm_72;
end
ap_ST_st73_fsm_72 :
begin
ap_NS_fsm = ap_ST_st74_fsm_73;
end
ap_ST_st74_fsm_73 :
begin
ap_NS_fsm = ap_ST_st75_fsm_74;
end
ap_ST_st75_fsm_74 :
begin
ap_NS_fsm = ap_ST_st76_fsm_75;
end
ap_ST_st76_fsm_75 :
begin
ap_NS_fsm = ap_ST_st77_fsm_76;
end
ap_ST_st77_fsm_76 :
begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end
ap_ST_st78_fsm_77 :
begin
if (~(ap_const_lv1_0 == tmp_18_fu_911_p2)) begin
ap_NS_fsm = ap_ST_st79_fsm_78;
end else begin
ap_NS_fsm = ap_ST_st120_fsm_119;
end
end
ap_ST_st79_fsm_78 :
begin
if (~(ap_const_lv1_0 == exitcond3_fu_980_p2)) begin
ap_NS_fsm = ap_ST_st89_fsm_88;
end else begin
ap_NS_fsm = ap_ST_st80_fsm_79;
end
end
ap_ST_st80_fsm_79 :
begin
ap_NS_fsm = ap_ST_st81_fsm_80;
end
ap_ST_st81_fsm_80 :
begin
ap_NS_fsm = ap_ST_st82_fsm_81;
end
ap_ST_st82_fsm_81 :
begin
ap_NS_fsm = ap_ST_st83_fsm_82;
end
ap_ST_st83_fsm_82 :
begin
ap_NS_fsm = ap_ST_st84_fsm_83;
end
ap_ST_st84_fsm_83 :
begin
ap_NS_fsm = ap_ST_st85_fsm_84;
end
ap_ST_st85_fsm_84 :
begin
ap_NS_fsm = ap_ST_st86_fsm_85;
end
ap_ST_st86_fsm_85 :
begin
ap_NS_fsm = ap_ST_st87_fsm_86;
end
ap_ST_st87_fsm_86 :
begin
ap_NS_fsm = ap_ST_st88_fsm_87;
end
ap_ST_st88_fsm_87 :
begin
ap_NS_fsm = ap_ST_st79_fsm_78;
end
ap_ST_st89_fsm_88 :
begin
ap_NS_fsm = ap_ST_st90_fsm_89;
end
ap_ST_st90_fsm_89 :
begin
ap_NS_fsm = ap_ST_st91_fsm_90;
end
ap_ST_st91_fsm_90 :
begin
ap_NS_fsm = ap_ST_st92_fsm_91;
end
ap_ST_st92_fsm_91 :
begin
ap_NS_fsm = ap_ST_st93_fsm_92;
end
ap_ST_st93_fsm_92 :
begin
ap_NS_fsm = ap_ST_st94_fsm_93;
end
ap_ST_st94_fsm_93 :
begin
ap_NS_fsm = ap_ST_st95_fsm_94;
end
ap_ST_st95_fsm_94 :
begin
ap_NS_fsm = ap_ST_st96_fsm_95;
end
ap_ST_st96_fsm_95 :
begin
ap_NS_fsm = ap_ST_st97_fsm_96;
end
ap_ST_st97_fsm_96 :
begin
ap_NS_fsm = ap_ST_st98_fsm_97;
end
ap_ST_st98_fsm_97 :
begin
ap_NS_fsm = ap_ST_st99_fsm_98;
end
ap_ST_st99_fsm_98 :
begin
ap_NS_fsm = ap_ST_st100_fsm_99;
end
ap_ST_st100_fsm_99 :
begin
ap_NS_fsm = ap_ST_st101_fsm_100;
end
ap_ST_st101_fsm_100 :
begin
ap_NS_fsm = ap_ST_st102_fsm_101;
end
ap_ST_st102_fsm_101 :
begin
ap_NS_fsm = ap_ST_st103_fsm_102;
end
ap_ST_st103_fsm_102 :
begin
ap_NS_fsm = ap_ST_st104_fsm_103;
end
ap_ST_st104_fsm_103 :
begin
ap_NS_fsm = ap_ST_st105_fsm_104;
end
ap_ST_st105_fsm_104 :
begin
ap_NS_fsm = ap_ST_st106_fsm_105;
end
ap_ST_st106_fsm_105 :
begin
ap_NS_fsm = ap_ST_st107_fsm_106;
end
ap_ST_st107_fsm_106 :
begin
ap_NS_fsm = ap_ST_st108_fsm_107;
end
ap_ST_st108_fsm_107 :
begin
ap_NS_fsm = ap_ST_st109_fsm_108;
end
ap_ST_st109_fsm_108 :
begin
ap_NS_fsm = ap_ST_st110_fsm_109;
end
ap_ST_st110_fsm_109 :
begin
ap_NS_fsm = ap_ST_st111_fsm_110;
end
ap_ST_st111_fsm_110 :
begin
ap_NS_fsm = ap_ST_st112_fsm_111;
end
ap_ST_st112_fsm_111 :
begin
ap_NS_fsm = ap_ST_st113_fsm_112;
end
ap_ST_st113_fsm_112 :
begin
ap_NS_fsm = ap_ST_st114_fsm_113;
end
ap_ST_st114_fsm_113 :
begin
ap_NS_fsm = ap_ST_st115_fsm_114;
end
ap_ST_st115_fsm_114 :
begin
ap_NS_fsm = ap_ST_st116_fsm_115;
end
ap_ST_st116_fsm_115 :
begin
ap_NS_fsm = ap_ST_st117_fsm_116;
end
ap_ST_st117_fsm_116 :
begin
ap_NS_fsm = ap_ST_st118_fsm_117;
end
ap_ST_st118_fsm_117 :
begin
ap_NS_fsm = ap_ST_st119_fsm_118;
end
ap_ST_st119_fsm_118 :
begin
ap_NS_fsm = ap_ST_st78_fsm_77;
end
ap_ST_st120_fsm_119 :
begin
if (~(ap_const_lv1_0 == exitcond4_fu_1032_p2)) begin
ap_NS_fsm = ap_ST_st139_fsm_138;
end else begin
ap_NS_fsm = ap_ST_st121_fsm_120;
end
end
ap_ST_st121_fsm_120 :
begin
ap_NS_fsm = ap_ST_st122_fsm_121;
end
ap_ST_st122_fsm_121 :
begin
ap_NS_fsm = ap_ST_st123_fsm_122;
end
ap_ST_st123_fsm_122 :
begin
ap_NS_fsm = ap_ST_st124_fsm_123;
end
ap_ST_st124_fsm_123 :
begin
ap_NS_fsm = ap_ST_st125_fsm_124;
end
ap_ST_st125_fsm_124 :
begin
ap_NS_fsm = ap_ST_st126_fsm_125;
end
ap_ST_st126_fsm_125 :
begin
ap_NS_fsm = ap_ST_st127_fsm_126;
end
ap_ST_st127_fsm_126 :
begin
ap_NS_fsm = ap_ST_st128_fsm_127;
end
ap_ST_st128_fsm_127 :
begin
ap_NS_fsm = ap_ST_st129_fsm_128;
end
ap_ST_st129_fsm_128 :
begin
ap_NS_fsm = ap_ST_st130_fsm_129;
end
ap_ST_st130_fsm_129 :
begin
ap_NS_fsm = ap_ST_st131_fsm_130;
end
ap_ST_st131_fsm_130 :
begin
ap_NS_fsm = ap_ST_st132_fsm_131;
end
ap_ST_st132_fsm_131 :
begin
ap_NS_fsm = ap_ST_st133_fsm_132;
end
ap_ST_st133_fsm_132 :
begin
ap_NS_fsm = ap_ST_st134_fsm_133;
end
ap_ST_st134_fsm_133 :
begin
ap_NS_fsm = ap_ST_st135_fsm_134;
end
ap_ST_st135_fsm_134 :
begin
ap_NS_fsm = ap_ST_st136_fsm_135;
end
ap_ST_st136_fsm_135 :
begin
ap_NS_fsm = ap_ST_st137_fsm_136;
end
ap_ST_st137_fsm_136 :
begin
ap_NS_fsm = ap_ST_st138_fsm_137;
end
ap_ST_st138_fsm_137 :
begin
ap_NS_fsm = ap_ST_st120_fsm_119;
end
ap_ST_st139_fsm_138 :
begin
if ((~((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == tmp_44_fu_1062_p2) & (ap_const_logic_0 == ap_sig_ioackin_P_netOut_V_TREADY)) & (((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == tmp_44_fu_1062_p2)) | (~(ap_const_lv1_0 == tmp_reg_1442) & ~(ap_const_lv1_0 == exitcond5_reg_1799)) | ((ap_const_lv1_0 == tmp_reg_1442) & ~(ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_9_reg_1740)) | ((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & ~(ap_const_lv1_0 == tmp_41_reg_1661) & ~(ap_const_lv1_0 == exitcond_fu_1105_p2))))) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else if (((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & ~((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == tmp_44_fu_1062_p2) & (ap_const_logic_0 == ap_sig_ioackin_P_netOut_V_TREADY)) & ~(ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == exitcond_fu_1105_p2))) begin
ap_NS_fsm = ap_ST_st143_fsm_142;
end else if (((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_41_reg_1661) & ~((ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == tmp_44_fu_1062_p2) & (ap_const_logic_0 == ap_sig_ioackin_P_netOut_V_TREADY)) & ~(ap_const_lv1_0 == tmp_44_fu_1062_p2))) begin
ap_NS_fsm = ap_ST_st140_fsm_139;
end else begin
ap_NS_fsm = ap_ST_st139_fsm_138;
end
end
ap_ST_st140_fsm_139 :
begin
ap_NS_fsm = ap_ST_st141_fsm_140;
end
ap_ST_st141_fsm_140 :
begin
ap_NS_fsm = ap_ST_st142_fsm_141;
end
ap_ST_st142_fsm_141 :
begin
ap_NS_fsm = ap_ST_st139_fsm_138;
end
ap_ST_st143_fsm_142 :
begin
if (~(ap_const_lv1_0 == tmp_59_fu_1233_p2)) begin
ap_NS_fsm = ap_ST_st144_fsm_143;
end else begin
ap_NS_fsm = ap_ST_st139_fsm_138;
end
end
ap_ST_st144_fsm_143 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_P_uOut_TREADY)) begin
ap_NS_fsm = ap_ST_st143_fsm_142;
end else begin
ap_NS_fsm = ap_ST_st144_fsm_143;
end
end
ap_ST_st145_fsm_144 :
begin
if (~(ap_const_lv1_0 == tmp_9_fu_1259_p2)) begin
ap_NS_fsm = ap_ST_st146_fsm_145;
end else begin
ap_NS_fsm = ap_ST_st139_fsm_138;
end
end
ap_ST_st146_fsm_145 :
begin
ap_NS_fsm = ap_ST_st147_fsm_146;
end
ap_ST_st147_fsm_146 :
begin
if ((ap_const_lv1_0 == tmp_11_fu_1298_p2)) begin
ap_NS_fsm = ap_ST_st145_fsm_144;
end else begin
ap_NS_fsm = ap_ST_st148_fsm_147;
end
end
ap_ST_st148_fsm_147 :
begin
if ((~(ap_const_lv1_0 == tmp_22_fu_1386_p2) & ~ap_sig_bdd_755)) begin
ap_NS_fsm = ap_ST_st148_fsm_147;
end else if (((ap_const_lv1_0 == tmp_22_fu_1386_p2) & ~ap_sig_bdd_755)) begin
ap_NS_fsm = ap_ST_st146_fsm_145;
end else begin
ap_NS_fsm = ap_ST_st148_fsm_147;
end
end
ap_ST_st149_fsm_148 :
begin
if (((ap_const_lv1_0 == exitcond5_fu_1398_p2) & ~ap_sig_bdd_769)) begin
ap_NS_fsm = ap_ST_st149_fsm_148;
end else if ((~ap_sig_bdd_769 & ~(ap_const_lv1_0 == exitcond5_fu_1398_p2))) begin
ap_NS_fsm = ap_ST_st139_fsm_138;
end else begin
ap_NS_fsm = ap_ST_st149_fsm_148;
end
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign P_netOut_V_TDATA = p_s_reg_391;
assign P_uOut_TDATA = p_uOut_q1;
assign ST_WandB_d0 = P_WandB_TDATA;
always @ (ap_rst_n) begin
ap_rst_n_inv = ~ap_rst_n;
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_1002 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_53]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_1009 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_59]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_167 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_249 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_256 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4F]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_264 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_78]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_272 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8B]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_281 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_E]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_290 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_58]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_300 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_307 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_52]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_317 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_D]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_324 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_57]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_333 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_13]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_340 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5D]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_350 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_14]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_357 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5E]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_367 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_26]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_374 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_70]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_384 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4B]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_391 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_71]);
end
always @ (ap_start or P_config_V_TVALID or tmp_fu_611_p2) begin
ap_sig_bdd_404 = (((P_config_V_TVALID == ap_const_logic_0) & ~(tmp_fu_611_p2 == ap_const_lv1_0)) | (ap_start == ap_const_logic_0));
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_428 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
always @ (P_netIn_TVALID or exitcond1_fu_633_p2) begin
ap_sig_bdd_434 = ((P_netIn_TVALID == ap_const_logic_0) & (ap_const_lv1_0 == exitcond1_fu_633_p2));
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_444 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_474 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_496 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_516 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2B]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_525 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4A]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_534 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4D]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_555 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4E]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_574 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_76]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_583 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_77]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_601 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_88]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_610 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8A]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_654 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8C]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_663 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8D]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_674 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8E]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_689 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_90]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_707 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_91]);
end
always @ (tmp_4_reg_1749) begin
ap_sig_bdd_724 = (~(tmp_4_reg_1749 == ap_const_lv2_2) & ~(tmp_4_reg_1749 == ap_const_lv2_1));
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_732 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_92]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_748 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_93]);
end
always @ (P_WandB_TVALID or tmp_22_fu_1386_p2) begin
ap_sig_bdd_755 = ((P_WandB_TVALID == ap_const_logic_0) & ~(ap_const_lv1_0 == tmp_22_fu_1386_p2));
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_765 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_94]);
end
always @ (P_config_V_TVALID or exitcond5_fu_1398_p2) begin
ap_sig_bdd_769 = ((P_config_V_TVALID == ap_const_logic_0) & (ap_const_lv1_0 == exitcond5_fu_1398_p2));
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_800 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4C]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_821 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_89]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_847 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8F]);
end
always @ (tmp_reg_1442 or tmp_1_reg_1454 or tmp_41_reg_1661 or ap_sig_cseq_ST_st139_fsm_138 or tmp_44_fu_1062_p2) begin
ap_sig_bdd_942 = ((ap_const_logic_1 == ap_sig_cseq_ST_st139_fsm_138) & (ap_const_lv1_0 == tmp_reg_1442) & (ap_const_lv1_0 == tmp_1_reg_1454) & (ap_const_lv1_0 == tmp_41_reg_1661) & (ap_const_lv1_0 == tmp_44_fu_1062_p2));
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_963 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_72]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_987 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_9]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_994 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_F]);
end
assign exitcond1_fu_633_p2 = (i_2_reg_277 == ST_layerSize_V_0_load_reg_1458? 1'b1: 1'b0);
assign exitcond2_fu_827_p2 = (k_1_reg_323 == tmp_19_reg_1534? 1'b1: 1'b0);
assign exitcond3_fu_980_p2 = (j_2_reg_369 == tmp_23_reg_1603? 1'b1: 1'b0);
assign exitcond4_fu_1032_p2 = (i_5_reg_380 == tmp_15_reg_1589? 1'b1: 1'b0);
assign exitcond5_fu_1398_p2 = (i_reg_495 == P_config_V_read_reg_1463? 1'b1: 1'b0);
assign exitcond_fu_1105_p2 = (i_6_reg_416 == ST_numLayer_V_load_reg_1446? 1'b1: 1'b0);
assign feedforward_AXILiteS_s_axi_U_ap_dummy_ce = ap_const_logic_1;
assign grp_fu_506_ce = ap_const_logic_1;
assign grp_fu_513_ce = ap_const_logic_1;
assign grp_fu_519_ce = ap_const_logic_1;
assign grp_fu_534_ce = ap_const_logic_1;
assign grp_fu_539_ce = ap_const_logic_1;
assign grp_fu_544_ce = ap_const_logic_1;
assign i_10_fu_821_p2 = (i_3_reg_288 + ap_const_lv8_1);
assign i_11_fu_1037_p2 = (i_5_reg_380 + ap_const_lv8_1);
assign i_12_fu_917_p2 = (i_4_reg_346 + ap_const_lv32_1);
assign i_14_fu_1110_p2 = (ap_const_lv8_1 + i_6_reg_416);
assign i_15_fu_1210_p2 = (ap_const_lv8_1 + p_netOut_V_reg_404);
assign i_7_fu_1403_p2 = (i_reg_495 + ap_const_lv8_1);
assign i_8_fu_638_p2 = (i_2_reg_277 + ap_const_lv8_1);
assign i_9_fu_1339_p2 = (i_1_reg_449 + ap_const_lv8_1);
assign j_4_fu_1288_p2 = (j_reg_461 + ap_const_lv32_1);
assign j_5_fu_762_p2 = (j_1_reg_300 + ap_const_lv32_1);
assign j_6_fu_985_p2 = (j_2_reg_369 + ap_const_lv8_1);
assign j_7_fu_1239_p2 = (j_3_reg_438 + ap_const_lv32_1);
assign k_2_fu_1392_p2 = (ap_const_lv32_1 + k_reg_484);
assign k_3_fu_832_p2 = (k_1_reg_323 + ap_const_lv8_1);
assign lhs_V_1_cast_fu_692_p1 = ST_numLayer_V_load_reg_1446;
assign lhs_V_cast_fu_1372_p1 = tmp_25_fu_1359_p6;
assign next_mul_fu_1099_p2 = (ap_const_lv14_23 + phi_mul_reg_427);
assign notlhs1_fu_1173_p2 = (tmp_50_fu_1141_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs_fu_1155_p2 = (tmp_48_fu_1124_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notrhs1_fu_1179_p2 = (tmp_79_fu_1151_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs_fu_1161_p2 = (tmp_78_fu_1134_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign p_netOut_V_1_fu_1203_p3 = ((tmp_56_reg_1712[0:0] === 1'b1) ? p_netOut_V_reg_404 : p_s_reg_391);
assign p_shl1_cast_fu_1325_p3 = {{tmp_45_fu_1321_p1}, {ap_const_lv2_0}};
assign p_shl2_cast_fu_795_p3 = {{tmp_49_fu_791_p1}, {ap_const_lv5_0}};
assign p_shl3_cast_fu_807_p3 = {{tmp_51_fu_803_p1}, {ap_const_lv2_0}};
assign p_shl4_cast_fu_954_p3 = {{tmp_62_fu_950_p1}, {ap_const_lv5_0}};
assign p_shl5_cast_fu_966_p3 = {{tmp_63_fu_962_p1}, {ap_const_lv2_0}};
assign p_shl_cast_fu_1313_p3 = {{tmp_42_fu_1309_p1}, {ap_const_lv5_0}};
assign p_uOut_load_3_to_int_fu_1120_p1 = reg_565;
assign p_uOut_load_4_to_int_fu_1138_p1 = p_uOut_load_4_reg_1706;
assign r_V_1_fu_695_p2 = ($signed(ap_const_lv9_1FF) + $signed(lhs_V_1_cast_fu_692_p1));
assign r_V_2_fu_723_p2 = ($signed(ap_const_lv9_1FE) + $signed(lhs_V_1_cast_fu_692_p1));
assign r_V_fu_1376_p2 = (ap_const_lv9_1 + lhs_V_cast_fu_1372_p1);
assign tmp_10_fu_1294_p1 = ST_layerSize_V_load_1_phi_reg_473;
assign tmp_11_fu_1298_p2 = ($signed(j_reg_461) < $signed(tmp_10_fu_1294_p1)? 1'b1: 1'b0);
assign tmp_13_fu_752_p1 = tmp_12_fu_739_p6;
assign tmp_14_fu_756_p2 = ($signed(j_1_reg_300) < $signed(tmp_13_fu_752_p1)? 1'b1: 1'b0);
assign tmp_16_fu_682_p1 = tmp_16_fu_682_p10;
assign tmp_16_fu_682_p10 = tmp_3_fu_672_p2;
assign tmp_16_fu_682_p2 = (ap_const_lv9_23 * tmp_16_fu_682_p1);
assign tmp_17_fu_907_p1 = tmp_15_fu_894_p6;
assign tmp_18_fu_911_p2 = ($signed(i_4_reg_346) < $signed(tmp_17_fu_907_p1)? 1'b1: 1'b0);
assign tmp_1_fu_621_p2 = (P_mode_V == ap_const_lv8_2? 1'b1: 1'b0);
assign tmp_20_fu_688_p1 = tmp_3_fu_672_p2[1:0];
assign tmp_21_cast_fu_1382_p1 = r_V_fu_1376_p2;
assign tmp_21_fu_705_p1 = r_V_1_fu_695_p2;
assign tmp_21_fu_705_p2 = ($signed({{1'b0}, {ap_const_lv16_23}}) * $signed(tmp_21_fu_705_p1));
assign tmp_22_fu_1386_p2 = ($signed(k_reg_484) < $signed(tmp_21_cast_fu_1382_p1)? 1'b1: 1'b0);
assign tmp_24_cast_fu_936_p1 = $signed(i_4_reg_346);
assign tmp_24_fu_711_p1 = tmp_21_fu_705_p2[8:0];
assign tmp_26_cast_fu_866_p1 = tmp_19_reg_1534;
assign tmp_26_fu_719_p1 = r_V_1_fu_695_p2[1:0];
assign tmp_27_fu_889_p1 = tmp_35_neg_fu_883_p2;
assign tmp_2_fu_1409_p1 = i_reg_495[1:0];
assign tmp_33_cast7_fu_838_p1 = k_1_reg_323;
assign tmp_33_cast_fu_842_p1 = k_1_reg_323;
assign tmp_33_fu_729_p2 = ($signed({{1'b0}, {ap_const_lv9_23}}) * $signed(r_V_2_fu_723_p2));
assign tmp_35_cast_fu_1019_p1 = tmp_23_reg_1603;
assign tmp_35_fu_735_p1 = r_V_2_fu_723_p2[1:0];
assign tmp_35_neg_fu_883_p2 = (tmp_35_to_int_fu_879_p1 ^ ap_const_lv32_80000000);
assign tmp_35_to_int_fu_879_p1 = reg_589;
assign tmp_39_cast6_fu_991_p1 = j_2_reg_369;
assign tmp_39_cast_fu_995_p1 = j_2_reg_369;
assign tmp_39_fu_1304_p2 = (j_reg_461 + tmp_61_cast_reg_1744);
assign tmp_3_fu_672_p2 = ($signed(ap_const_lv8_FF) + $signed(i_3_reg_288));
assign tmp_41_fu_1057_p2 = (P_mode_V_read_reg_1437 == ap_const_lv8_3? 1'b1: 1'b0);
assign tmp_42_cast_fu_1043_p1 = i_5_reg_380;
assign tmp_42_fu_1309_p1 = tmp_39_fu_1304_p2[8:0];
assign tmp_44_fu_1062_p2 = (p_netOut_V_reg_404 < tmp_15_reg_1589? 1'b1: 1'b0);
assign tmp_45_fu_1321_p1 = tmp_39_fu_1304_p2[11:0];
assign tmp_46_cast_fu_1067_p1 = p_netOut_V_reg_404;
assign tmp_46_fu_1333_p2 = (p_shl_cast_fu_1313_p3 + p_shl1_cast_fu_1325_p3);
assign tmp_47_cast_fu_1081_p1 = p_s_reg_391;
assign tmp_47_fu_781_p2 = (j_1_reg_300 + tmp_62_cast_reg_1479);
assign tmp_48_fu_1124_p4 = {{p_uOut_load_3_to_int_fu_1120_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_49_fu_791_p1 = tmp_47_fu_781_p2[8:0];
assign tmp_4_fu_1278_p1 = i_1_reg_449[1:0];
assign tmp_50_fu_1141_p4 = {{p_uOut_load_4_to_int_fu_1138_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_51_fu_803_p1 = tmp_47_fu_781_p2[11:0];
assign tmp_52_fu_1167_p2 = (notrhs_fu_1161_p2 | notlhs_fu_1155_p2);
assign tmp_53_fu_1185_p2 = (notrhs1_fu_1179_p2 | notlhs1_fu_1173_p2);
assign tmp_54_fu_1191_p2 = (tmp_52_fu_1167_p2 & tmp_53_fu_1185_p2);
assign tmp_55_fu_530_opcode = ap_const_lv5_2;
assign tmp_56_fu_1197_p2 = (tmp_54_fu_1191_p2 & tmp_55_fu_530_p2);
assign tmp_58_fu_1229_p1 = tmp_57_fu_1216_p6;
assign tmp_59_fu_1233_p2 = ($signed(j_3_reg_438) < $signed(tmp_58_fu_1229_p1)? 1'b1: 1'b0);
assign tmp_5_fu_658_p1 = tmp_5_fu_658_p10;
assign tmp_5_fu_658_p10 = i_3_reg_288;
assign tmp_5_fu_658_p2 = (ap_const_lv15_23 * tmp_5_fu_658_p1);
assign tmp_60_fu_815_p2 = (p_shl2_cast_fu_795_p3 + p_shl3_cast_fu_807_p3);
assign tmp_61_cast_fu_1274_p1 = tmp_s_fu_1268_p2;
assign tmp_61_fu_940_p2 = ($signed(tmp_24_cast_fu_936_p1) + $signed(tmp_64_cast_reg_1506));
assign tmp_62_cast_fu_664_p1 = tmp_5_fu_658_p2;
assign tmp_62_fu_950_p1 = tmp_61_fu_940_p2[8:0];
assign tmp_63_fu_962_p1 = tmp_61_fu_940_p2[11:0];
assign tmp_64_cast_fu_715_p1 = $signed(tmp_21_fu_705_p2);
assign tmp_64_fu_974_p2 = (p_shl4_cast_fu_954_p3 + p_shl5_cast_fu_966_p3);
assign tmp_65_fu_1345_p1 = k_reg_484[13:0];
assign tmp_66_fu_1349_p2 = (tmp_46_reg_1781 + tmp_65_fu_1345_p1);
assign tmp_67_fu_1047_p2 = (tmp_24_reg_1499 + tmp_42_cast_fu_1043_p1);
assign tmp_68_fu_869_p2 = (tmp_60_reg_1540 + tmp_26_cast_fu_866_p1);
assign tmp_69_fu_846_p2 = (tmp_60_reg_1540 + tmp_33_cast_fu_842_p1);
assign tmp_6_fu_668_p1 = i_3_reg_288[1:0];
assign tmp_70_cast_fu_786_p1 = $signed(tmp_47_fu_781_p2);
assign tmp_70_fu_856_p2 = (tmp_16_reg_1489 + tmp_33_cast7_fu_838_p1);
assign tmp_71_fu_1022_p2 = (tmp_64_reg_1609 + tmp_35_cast_fu_1019_p1);
assign tmp_72_fu_999_p2 = (tmp_64_reg_1609 + tmp_39_cast_fu_995_p1);
assign tmp_73_fu_1009_p2 = (tmp_33_reg_1516 + tmp_39_cast6_fu_991_p1);
assign tmp_74_cast_fu_945_p1 = $signed(tmp_61_fu_940_p2);
assign tmp_74_fu_1095_p1 = phi_mul_reg_427[8:0];
assign tmp_75_fu_1116_p1 = i_6_reg_416[1:0];
assign tmp_76_fu_1071_p2 = (tmp_24_reg_1499 + tmp_46_cast_fu_1067_p1);
assign tmp_77_fu_1085_p2 = (tmp_24_reg_1499 + tmp_47_cast_fu_1081_p1);
assign tmp_78_cast_fu_1354_p1 = tmp_66_fu_1349_p2;
assign tmp_78_fu_1134_p1 = p_uOut_load_3_to_int_fu_1120_p1[22:0];
assign tmp_79_cast_fu_874_p1 = tmp_68_fu_869_p2;
assign tmp_79_fu_1151_p1 = p_uOut_load_4_to_int_fu_1138_p1[22:0];
assign tmp_7_fu_649_p2 = (i_3_reg_288 < ST_numLayer_V_load_reg_1446? 1'b1: 1'b0);
assign tmp_7_t_fu_1282_p2 = ($signed(ap_const_lv2_3) + $signed(tmp_4_fu_1278_p1));
assign tmp_80_cast_fu_851_p1 = tmp_69_fu_846_p2;
assign tmp_80_fu_1245_p1 = j_3_reg_438[8:0];
assign tmp_81_cast_fu_861_p1 = $signed(tmp_70_fu_856_p2);
assign tmp_81_fu_1249_p2 = (tmp_74_reg_1683 + tmp_80_fu_1245_p1);
assign tmp_82_cast_fu_1027_p1 = tmp_71_fu_1022_p2;
assign tmp_83_cast_fu_1004_p1 = tmp_72_fu_999_p2;
assign tmp_84_cast_fu_1014_p1 = $signed(tmp_73_fu_1009_p2);
assign tmp_85_cast_fu_1052_p1 = $signed(tmp_67_fu_1047_p2);
assign tmp_87_cast_fu_1076_p1 = $signed(tmp_76_fu_1071_p2);
assign tmp_88_cast_fu_1090_p1 = $signed(tmp_77_fu_1085_p2);
assign tmp_89_cast_fu_1254_p1 = tmp_81_fu_1249_p2;
assign tmp_8_fu_644_p1 = i_2_reg_277;
assign tmp_9_fu_1259_p2 = (i_1_reg_449 < ST_numLayer_V_load_reg_1446? 1'b1: 1'b0);
assign tmp_fu_611_p2 = (P_mode_V == ap_const_lv8_1? 1'b1: 1'b0);
assign tmp_s_fu_1268_p1 = tmp_s_fu_1268_p10;
assign tmp_s_fu_1268_p10 = i_1_reg_449;
assign tmp_s_fu_1268_p2 = (ap_const_lv15_23 * tmp_s_fu_1268_p1);
always @ (posedge ap_clk) begin
tmp_62_cast_reg_1479[31:15] <= 17'b00000000000000000;
tmp_60_reg_1540[1:0] <= 2'b00;
tmp_64_reg_1609[1:0] <= 2'b00;
tmp_61_cast_reg_1744[31:15] <= 17'b00000000000000000;
tmp_46_reg_1781[1:0] <= 2'b00;
end
endmodule //feedforward
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVKAPWR_8_V
`define SKY130_FD_SC_LP__INVKAPWR_8_V
/**
* invkapwr: Inverter on keep-alive power rail.
*
* Verilog wrapper for invkapwr with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__invkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__invkapwr_8 (
Y ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
sky130_fd_sc_lp__invkapwr base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.KAPWR(KAPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__invkapwr_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__invkapwr base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVKAPWR_8_V
|
// RX
// Copyright 2010 University of Washington
// License: http://creativecommons.org/licenses/by/3.0/
// 2008 Dan Yeager
// RX module converts EPC Class 1 Gen 2 time domain protocol
// to a serial binary data stream
// Sample bitout on bitclk positive edges.
// TR cal measurement provided for TX clock calibration.
// RT cal for debugging purposes and possibly adjustment
// of oscillator frequency if necessary.
module rx (reset, clk, demodin, bitout, bitclk, rx_overflow_reset, trcal, rngbitout);
input reset, clk, demodin;
output bitout, bitclk, rx_overflow_reset, rngbitout;
output [9:0] trcal;
reg bitout, bitclk, rngbitout;
reg [9:0] trcal, rtcal;
// States
parameter STATE_DELIMITER = 5'd0;
parameter STATE_DATA0 = 5'd1;
parameter STATE_RTCAL = 5'd2;
parameter STATE_TRCAL = 5'd4;
parameter STATE_BITS = 5'd8;
reg [4:0] commstate;
parameter STATE_WAIT_DEMOD_LOW = 4'd0;
parameter STATE_WAIT_DEMOD_HIGH = 4'd1;
parameter STATE_EVAL_BIT = 4'd2;
parameter STATE_RESET_COUNTER = 4'd4;
reg [3:0] evalstate;
wire[9:0] count;
wire clkb;
assign clkb = ~clk;
reg counterreset, counterenable;
wire overflow;
wire counter_reset_in;
assign counter_reset_in = counterreset|reset;
counter10 counter (clkb, counter_reset_in, counterenable, count, overflow);
assign rx_overflow_reset = overflow | ((commstate == STATE_BITS) && (count > rtcal));
always @ (posedge clk or posedge reset) begin
if( reset ) begin
bitout <= 0;
bitclk <= 0;
rtcal <= 10'd0;
trcal <= 10'd0;
rngbitout <= 0;
counterreset <= 0;
counterenable <= 0;
commstate <= STATE_DELIMITER;
evalstate <= STATE_WAIT_DEMOD_LOW;
// process normal operation
end else begin
if(evalstate == STATE_WAIT_DEMOD_LOW) begin
if (demodin == 0) begin
evalstate <= STATE_WAIT_DEMOD_HIGH;
if(commstate != STATE_DELIMITER) counterenable <= 1;
else counterenable <= 0;
counterreset <= 0;
end
end else if(evalstate == STATE_WAIT_DEMOD_HIGH) begin
if (demodin == 1) begin
evalstate <= STATE_EVAL_BIT;
counterenable <= 1;
counterreset <= 0;
end
end else if(evalstate == STATE_EVAL_BIT) begin
counterreset <= 1;
evalstate <= STATE_RESET_COUNTER;
bitclk <= 0;
rngbitout <= count[0];
case(commstate)
STATE_DELIMITER: begin
commstate <= STATE_DATA0;
end
STATE_DATA0: begin
commstate <= STATE_RTCAL;
end
STATE_RTCAL: begin
rtcal <= count;
commstate <= STATE_TRCAL;
end
STATE_TRCAL: begin
if(count > rtcal) begin
trcal <= count;
end else if(count[8:0] > rtcal[9:1]) begin // divide rtcal by 2
bitout <= 1;
commstate <= STATE_BITS;
end else begin
bitout <= 0;
commstate <= STATE_BITS;
end
end
STATE_BITS: begin
if(count[8:0] > rtcal[9:1]) begin // data 1 (divide rtcal by 2)
bitout <= 1;
end else begin // data 0
bitout <= 0;
end
end
default: begin
counterreset <= 0;
commstate <= 0;
end
endcase // case(mode)
end else if(evalstate == STATE_RESET_COUNTER) begin
if(commstate == STATE_BITS) begin
bitclk <= 1;
end
counterreset <= 0;
evalstate <= STATE_WAIT_DEMOD_LOW;
end else begin // unknown state, reset.
evalstate <= 0;
end
end // ~reset
end // always @ clk
endmodule //
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MAJ3_SYMBOL_V
`define SKY130_FD_SC_MS__MAJ3_SYMBOL_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__maj3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MAJ3_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0N_TB_V
`define SKY130_FD_SC_HDLL__INPUTISO0N_TB_V
/**
* inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__inputiso0n.v"
module top();
// Inputs are registered
reg A;
reg SLEEP_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hdll__inputiso0n dut (.A(A), .SLEEP_B(SLEEP_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0N_TB_V
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 23-10-2019
*/
module jt51_csr_ch(
input rst,
input clk,
input cen,
input [ 7:0] din,
input up_rl_ch,
input up_fb_ch,
input up_con_ch,
input up_kc_ch,
input up_kf_ch,
input up_ams_ch,
input up_pms_ch,
output [1:0] rl,
output [2:0] fb,
output [2:0] con,
output [6:0] kc,
output [5:0] kf,
output [1:0] ams,
output [2:0] pms
);
wire [1:0] rl_in = din[7:6];
wire [2:0] fb_in = din[5:3];
wire [2:0] con_in = din[2:0];
wire [6:0] kc_in = din[6:0];
wire [5:0] kf_in = din[7:2];
wire [1:0] ams_in = din[1:0];
wire [2:0] pms_in = din[6:4];
wire [25:0] reg_in = {
up_rl_ch ? rl_in : rl,
up_fb_ch ? fb_in : fb,
up_con_ch ? con_in : con,
up_kc_ch ? kc_in : kc,
up_kf_ch ? kf_in : kf,
up_ams_ch ? ams_in : ams,
up_pms_ch ? pms_in : pms };
wire [25:0] reg_out;
assign { rl, fb, con, kc, kf, ams, pms } = reg_out;
jt51_sh #( .width(26), .stages(8)) u_regop(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( reg_in ),
.drop ( reg_out )
);
endmodule |
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____50.000______0.000______50.0______151.636_____98.575
// CLK_OUT2____25.000______0.000______50.0______175.402_____98.575
// CLK_OUT3___200.000______0.000______50.0______114.829_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module clk_wiz_0
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
output clk_out2,
output clk_out3,
// Status and control signals
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_clk_wiz_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (10.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (40),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (5),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_wiz_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_clk_wiz_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clk_out2_clk_wiz_0),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clk_out3_clk_wiz_0),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_wiz_0),
.CLKIN1 (clk_in1_clk_wiz_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_wiz_0),
.I (clkfbout_clk_wiz_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_clk_wiz_0));
BUFG clkout2_buf
(.O (clk_out2),
.I (clk_out2_clk_wiz_0));
BUFG clkout3_buf
(.O (clk_out3),
.I (clk_out3_clk_wiz_0));
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for struct of ent_ab
//
// Generated
// by: wig
// on: Fri Jul 7 06:37:54 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ab.v,v 1.3 2006/07/10 07:30:09 wig Exp $
// $Date: 2006/07/10 07:30:09 $
// $Log: ent_ab.v,v $
// Revision 1.3 2006/07/10 07:30:09 wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module struct of ent_ab
//
// No user `defines in this module
module ent_ab
//
// Generated Module inst_ab
//
(
p_mix_sc_sig_1_go,
p_mix_sc_sig_2_go
);
// Generated Module Outputs:
output p_mix_sc_sig_1_go;
output [31:0] p_mix_sc_sig_2_go;
// Generated Wires:
wire p_mix_sc_sig_1_go;
wire [31:0] p_mix_sc_sig_2_go;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sc_sig_1; // __W_PORT_SIGNAL_MAP_REQ
wire [31:0] sc_sig_2; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign p_mix_sc_sig_1_go = sc_sig_1; // __I_O_BIT_PORT
assign p_mix_sc_sig_2_go = sc_sig_2; // __I_O_BUS_PORT
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_aba
ent_aba inst_aba ( // is i_mic32_top / hier inst_ab inst_aba inst_ab
.sc_p_1(sc_sig_1), // bad conection bits detected
.sc_p_2(sc_sig_2) // reverse orderreverse order
// multiline comments
);
// End of Generated Instance Port Map for inst_aba
endmodule
//
// End of Generated Module struct of ent_ab
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__O22AI_FUNCTIONAL_PP_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22AI_FUNCTIONAL_PP_V |
/***********************************************
Module Name: CORDIC_sin_cos_test
Feature: Testbench for CORDIC (mode 1)
An example for the GEM Projects
Coder: Garfield
Organization: XXXX Group, Department of Architecture
------------------------------------------------------
Variables:
clk: clock for processing
reset: reset flag
------------------------------------------------------
History:
06-21-2016: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignment
`define MODE 1
`define LENGTH 256
`define WIDTH 15
`define ORDER 12
//Insert the modules
module CORDIC_sin_cos_test;
//defination for Variables
reg clk;
reg reset;
reg[7:0] cntr;
//loop for test vectors
reg signed[(`WIDTH-1):0] test_vector_w[(`LENGTH-1):0];
reg signed[(`WIDTH-1):0] test_vector_sin[(`LENGTH-1):0];
reg signed[(`WIDTH-1):0] test_vector_cos[(`LENGTH-1):0];
//Test Vector Value
wire signed[(`WIDTH-1):0] cos_value;
wire signed[(`WIDTH-1):0] sin_value;
//middle signals
wire signed[(`WIDTH-1):0] comp_sin;
wire signed[(`WIDTH-1):0] comp_cos;
//Results right? Comparision results
wire[(`WIDTH*2-1):0] op;
wire[(`WIDTH*2-1):0] res;
wire signed[(`WIDTH-1):0] res_sin;
wire signed[(`WIDTH-1):0] res_cos;
wire [7:0] index;
assign res_sin = res[`WIDTH -1 : 0];
assign res_cos = res[`WIDTH*2 -1 : `WIDTH];
assign op = {{(`WIDTH){1'b0}}, test_vector_w[cntr]};
assign index = (cntr - 1 - `ORDER) % `LENGTH;
assign sin_value = test_vector_sin[index];
assign cos_value = test_vector_cos[index];
assign comp_sin = (res_sin - sin_value);
assign comp_cos = (res_cos - cos_value);
//Connection to the modules
CORDIC #(.MODE(`MODE))
//CORDIC Mode
C (
.CLK(clk), .RESET_n(reset),
.operand(op), .results(res)
);
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
//Load the test vectors
initial
begin
$readmemh("angle_test_vector.txt", test_vector_w);
$readmemh("sin_test_vector.txt", test_vector_sin);
$readmemh("cos_test_vector.txt", test_vector_cos);
end
//Load the input of 0 order element
//Comparision
always @(posedge clk or negedge reset)
begin
if ( !reset)
//reset statement: counter keeps at 0
begin
cntr <= 8'h00;
end
else
begin
cntr <= cntr + 8'h01;
end
end
endmodule |
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
// Date : Fri Jun 3 00:16:36 2016
// Host : Dries007-Arch running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/dries/Projects/Basys3/VGA_text/VGA_text.srcs/sources_1/ip/FrameBuffer/FrameBuffer_sim_netlist.v
// Design : FrameBuffer
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "FrameBuffer,blk_mem_gen_v8_3_1,{}" *) (* core_generation_info = "FrameBuffer,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=FrameBuffer.mif,C_INIT_FILE=FrameBuffer.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=10240,C_READ_DEPTH_A=10240,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=10240,C_READ_DEPTH_B=10240,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.61856 mW}" *) (* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "blk_mem_gen_v8_3_1,Vivado 2015.4" *)
(* NotValidForBitStream *)
module FrameBuffer
(clka,
ena,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [13:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [7:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [7:0]douta;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input clkb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *) input [0:0]web;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [13:0]addrb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *) input [7:0]dinb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [7:0]doutb;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]dinb;
wire [7:0]douta;
wire [7:0]doutb;
wire ena;
wire [0:0]wea;
wire [0:0]web;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [13:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [13:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [7:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "14" *)
(* C_ADDRB_WIDTH = "14" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "8" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "2" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 4.61856 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "1" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "FrameBuffer.mem" *)
(* C_INIT_FILE_NAME = "FrameBuffer.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "2" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "10240" *)
(* C_READ_DEPTH_B = "10240" *)
(* C_READ_WIDTH_A = "8" *)
(* C_READ_WIDTH_B = "8" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "1" *)
(* C_USE_BYTE_WEB = "1" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "10240" *)
(* C_WRITE_DEPTH_B = "10240" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "8" *)
(* C_WRITE_WIDTH_B = "8" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
FrameBuffer_blk_mem_gen_v8_3_1 U0
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.eccpipece(1'b0),
.ena(ena),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[13:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[13:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[7:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module FrameBuffer_blk_mem_gen_generic_cstr
(doutb,
douta,
clka,
clkb,
addra,
addrb,
dina,
dinb,
wea,
web,
ena);
output [7:0]doutb;
output [7:0]douta;
input clka;
input clkb;
input [13:0]addra;
input [13:0]addrb;
input [7:0]dina;
input [7:0]dinb;
input [0:0]wea;
input [0:0]web;
input ena;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]dinb;
wire [7:0]douta;
wire [7:0]doutb;
wire ena;
wire [7:0]ram_douta;
wire [7:0]ram_doutb;
wire \ramloop[1].ram.r_n_0 ;
wire \ramloop[1].ram.r_n_1 ;
wire \ramloop[1].ram.r_n_10 ;
wire \ramloop[1].ram.r_n_11 ;
wire \ramloop[1].ram.r_n_12 ;
wire \ramloop[1].ram.r_n_13 ;
wire \ramloop[1].ram.r_n_14 ;
wire \ramloop[1].ram.r_n_15 ;
wire \ramloop[1].ram.r_n_2 ;
wire \ramloop[1].ram.r_n_3 ;
wire \ramloop[1].ram.r_n_4 ;
wire \ramloop[1].ram.r_n_5 ;
wire \ramloop[1].ram.r_n_6 ;
wire \ramloop[1].ram.r_n_7 ;
wire \ramloop[1].ram.r_n_8 ;
wire \ramloop[1].ram.r_n_9 ;
wire \ramloop[2].ram.r_n_0 ;
wire \ramloop[2].ram.r_n_1 ;
wire \ramloop[2].ram.r_n_10 ;
wire \ramloop[2].ram.r_n_11 ;
wire \ramloop[2].ram.r_n_12 ;
wire \ramloop[2].ram.r_n_13 ;
wire \ramloop[2].ram.r_n_14 ;
wire \ramloop[2].ram.r_n_15 ;
wire \ramloop[2].ram.r_n_2 ;
wire \ramloop[2].ram.r_n_3 ;
wire \ramloop[2].ram.r_n_4 ;
wire \ramloop[2].ram.r_n_5 ;
wire \ramloop[2].ram.r_n_6 ;
wire \ramloop[2].ram.r_n_7 ;
wire \ramloop[2].ram.r_n_8 ;
wire \ramloop[2].ram.r_n_9 ;
wire [0:0]wea;
wire [0:0]web;
FrameBuffer_blk_mem_gen_mux \has_mux_a.A
(.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ({\ramloop[1].ram.r_n_0 ,\ramloop[1].ram.r_n_1 ,\ramloop[1].ram.r_n_2 ,\ramloop[1].ram.r_n_3 ,\ramloop[1].ram.r_n_4 ,\ramloop[1].ram.r_n_5 ,\ramloop[1].ram.r_n_6 ,\ramloop[1].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 (ram_douta),
.DOADO({\ramloop[2].ram.r_n_0 ,\ramloop[2].ram.r_n_1 ,\ramloop[2].ram.r_n_2 ,\ramloop[2].ram.r_n_3 ,\ramloop[2].ram.r_n_4 ,\ramloop[2].ram.r_n_5 ,\ramloop[2].ram.r_n_6 ,\ramloop[2].ram.r_n_7 }),
.addra(addra[13:11]),
.clka(clka),
.douta(douta),
.ena(ena));
FrameBuffer_blk_mem_gen_mux__parameterized0 \has_mux_b.B
(.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ({\ramloop[1].ram.r_n_8 ,\ramloop[1].ram.r_n_9 ,\ramloop[1].ram.r_n_10 ,\ramloop[1].ram.r_n_11 ,\ramloop[1].ram.r_n_12 ,\ramloop[1].ram.r_n_13 ,\ramloop[1].ram.r_n_14 ,\ramloop[1].ram.r_n_15 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 (ram_doutb),
.DOBDO({\ramloop[2].ram.r_n_8 ,\ramloop[2].ram.r_n_9 ,\ramloop[2].ram.r_n_10 ,\ramloop[2].ram.r_n_11 ,\ramloop[2].ram.r_n_12 ,\ramloop[2].ram.r_n_13 ,\ramloop[2].ram.r_n_14 ,\ramloop[2].ram.r_n_15 }),
.addrb(addrb[13:11]),
.clkb(clkb),
.doutb(doutb));
FrameBuffer_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.\douta[7] (ram_douta),
.\doutb[7] (ram_doutb),
.ena(ena),
.wea(wea),
.web(web));
FrameBuffer_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.\douta[7] ({\ramloop[1].ram.r_n_0 ,\ramloop[1].ram.r_n_1 ,\ramloop[1].ram.r_n_2 ,\ramloop[1].ram.r_n_3 ,\ramloop[1].ram.r_n_4 ,\ramloop[1].ram.r_n_5 ,\ramloop[1].ram.r_n_6 ,\ramloop[1].ram.r_n_7 }),
.\doutb[7] ({\ramloop[1].ram.r_n_8 ,\ramloop[1].ram.r_n_9 ,\ramloop[1].ram.r_n_10 ,\ramloop[1].ram.r_n_11 ,\ramloop[1].ram.r_n_12 ,\ramloop[1].ram.r_n_13 ,\ramloop[1].ram.r_n_14 ,\ramloop[1].ram.r_n_15 }),
.ena(ena),
.wea(wea),
.web(web));
FrameBuffer_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.DOADO({\ramloop[2].ram.r_n_0 ,\ramloop[2].ram.r_n_1 ,\ramloop[2].ram.r_n_2 ,\ramloop[2].ram.r_n_3 ,\ramloop[2].ram.r_n_4 ,\ramloop[2].ram.r_n_5 ,\ramloop[2].ram.r_n_6 ,\ramloop[2].ram.r_n_7 }),
.DOBDO({\ramloop[2].ram.r_n_8 ,\ramloop[2].ram.r_n_9 ,\ramloop[2].ram.r_n_10 ,\ramloop[2].ram.r_n_11 ,\ramloop[2].ram.r_n_12 ,\ramloop[2].ram.r_n_13 ,\ramloop[2].ram.r_n_14 ,\ramloop[2].ram.r_n_15 }),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.ena(ena),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_mux" *)
module FrameBuffer_blk_mem_gen_mux
(douta,
DOADO,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ,
addra,
ena,
clka);
output [7:0]douta;
input [7:0]DOADO;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ;
input [2:0]addra;
input ena;
input clka;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ;
wire [7:0]DOADO;
wire [2:0]addra;
wire clka;
wire [7:0]douta;
wire ena;
wire \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0 ;
wire \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0 ;
wire \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1_n_0 ;
wire [2:0]sel_pipe;
LUT6 #(
.INIT(64'h02FF020F02F00200))
\douta[0]_INST_0
(.I0(DOADO[0]),
.I1(sel_pipe[0]),
.I2(sel_pipe[1]),
.I3(sel_pipe[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [0]),
.O(douta[0]));
LUT6 #(
.INIT(64'h02FF020F02F00200))
\douta[1]_INST_0
(.I0(DOADO[1]),
.I1(sel_pipe[0]),
.I2(sel_pipe[1]),
.I3(sel_pipe[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [1]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [1]),
.O(douta[1]));
LUT6 #(
.INIT(64'h02FF020F02F00200))
\douta[2]_INST_0
(.I0(DOADO[2]),
.I1(sel_pipe[0]),
.I2(sel_pipe[1]),
.I3(sel_pipe[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [2]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [2]),
.O(douta[2]));
LUT6 #(
.INIT(64'h02FF020F02F00200))
\douta[3]_INST_0
(.I0(DOADO[3]),
.I1(sel_pipe[0]),
.I2(sel_pipe[1]),
.I3(sel_pipe[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [3]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [3]),
.O(douta[3]));
LUT6 #(
.INIT(64'h02FF020F02F00200))
\douta[4]_INST_0
(.I0(DOADO[4]),
.I1(sel_pipe[0]),
.I2(sel_pipe[1]),
.I3(sel_pipe[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [4]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [4]),
.O(douta[4]));
LUT6 #(
.INIT(64'h02FF020F02F00200))
\douta[5]_INST_0
(.I0(DOADO[5]),
.I1(sel_pipe[0]),
.I2(sel_pipe[1]),
.I3(sel_pipe[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [5]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [5]),
.O(douta[5]));
LUT6 #(
.INIT(64'h02FF020F02F00200))
\douta[6]_INST_0
(.I0(DOADO[6]),
.I1(sel_pipe[0]),
.I2(sel_pipe[1]),
.I3(sel_pipe[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [6]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [6]),
.O(douta[6]));
LUT6 #(
.INIT(64'h02FF020F02F00200))
\douta[7]_INST_0
(.I0(DOADO[7]),
.I1(sel_pipe[0]),
.I2(sel_pipe[1]),
.I3(sel_pipe[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [7]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [7]),
.O(douta[7]));
LUT3 #(
.INIT(8'hB8))
\no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1
(.I0(addra[0]),
.I1(ena),
.I2(sel_pipe[0]),
.O(\no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hB8))
\no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1
(.I0(addra[1]),
.I1(ena),
.I2(sel_pipe[1]),
.O(\no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hB8))
\no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1
(.I0(addra[2]),
.I1(ena),
.I2(sel_pipe[2]),
.O(\no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]
(.C(clka),
.CE(1'b1),
.D(\no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0 ),
.Q(sel_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]
(.C(clka),
.CE(1'b1),
.D(\no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0 ),
.Q(sel_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]
(.C(clka),
.CE(1'b1),
.D(\no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1_n_0 ),
.Q(sel_pipe[2]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_mux" *)
module FrameBuffer_blk_mem_gen_mux__parameterized0
(doutb,
DOBDO,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ,
addrb,
clkb);
output [7:0]doutb;
input [7:0]DOBDO;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ;
input [2:0]addrb;
input clkb;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ;
wire [7:0]DOBDO;
wire [2:0]addrb;
wire clkb;
wire [7:0]doutb;
wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0] ;
wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1] ;
wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[2] ;
wire [2:0]sel_pipe_d1;
LUT6 #(
.INIT(64'h02FF020F02F00200))
\doutb[0]_INST_0
(.I0(DOBDO[0]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(sel_pipe_d1[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [0]),
.O(doutb[0]));
LUT6 #(
.INIT(64'h02FF020F02F00200))
\doutb[1]_INST_0
(.I0(DOBDO[1]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(sel_pipe_d1[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [1]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [1]),
.O(doutb[1]));
LUT6 #(
.INIT(64'h02FF020F02F00200))
\doutb[2]_INST_0
(.I0(DOBDO[2]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(sel_pipe_d1[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [2]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [2]),
.O(doutb[2]));
LUT6 #(
.INIT(64'h02FF020F02F00200))
\doutb[3]_INST_0
(.I0(DOBDO[3]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(sel_pipe_d1[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [3]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [3]),
.O(doutb[3]));
LUT6 #(
.INIT(64'h02FF020F02F00200))
\doutb[4]_INST_0
(.I0(DOBDO[4]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(sel_pipe_d1[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [4]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [4]),
.O(doutb[4]));
LUT6 #(
.INIT(64'h02FF020F02F00200))
\doutb[5]_INST_0
(.I0(DOBDO[5]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(sel_pipe_d1[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [5]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [5]),
.O(doutb[5]));
LUT6 #(
.INIT(64'h02FF020F02F00200))
\doutb[6]_INST_0
(.I0(DOBDO[6]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(sel_pipe_d1[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [6]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [6]),
.O(doutb[6]));
LUT6 #(
.INIT(64'h02FF020F02F00200))
\doutb[7]_INST_0
(.I0(DOBDO[7]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(sel_pipe_d1[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [7]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [7]),
.O(doutb[7]));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]
(.C(clkb),
.CE(1'b1),
.D(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0] ),
.Q(sel_pipe_d1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]
(.C(clkb),
.CE(1'b1),
.D(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1] ),
.Q(sel_pipe_d1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[2]
(.C(clkb),
.CE(1'b1),
.D(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[2] ),
.Q(sel_pipe_d1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]
(.C(clkb),
.CE(1'b1),
.D(addrb[0]),
.Q(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]
(.C(clkb),
.CE(1'b1),
.D(addrb[1]),
.Q(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]
(.C(clkb),
.CE(1'b1),
.D(addrb[2]),
.Q(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[2] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module FrameBuffer_blk_mem_gen_prim_width
(\douta[7] ,
\doutb[7] ,
clka,
clkb,
addra,
addrb,
dina,
dinb,
wea,
web,
ena);
output [7:0]\douta[7] ;
output [7:0]\doutb[7] ;
input clka;
input clkb;
input [13:0]addra;
input [13:0]addrb;
input [7:0]dina;
input [7:0]dinb;
input [0:0]wea;
input [0:0]web;
input ena;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]dinb;
wire [7:0]\douta[7] ;
wire [7:0]\doutb[7] ;
wire ena;
wire [0:0]wea;
wire [0:0]web;
FrameBuffer_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.\douta[7] (\douta[7] ),
.\doutb[7] (\doutb[7] ),
.ena(ena),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module FrameBuffer_blk_mem_gen_prim_width__parameterized0
(\douta[7] ,
\doutb[7] ,
clka,
clkb,
addra,
addrb,
dina,
dinb,
wea,
web,
ena);
output [7:0]\douta[7] ;
output [7:0]\doutb[7] ;
input clka;
input clkb;
input [13:0]addra;
input [13:0]addrb;
input [7:0]dina;
input [7:0]dinb;
input [0:0]wea;
input [0:0]web;
input ena;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]dinb;
wire [7:0]\douta[7] ;
wire [7:0]\doutb[7] ;
wire ena;
wire [0:0]wea;
wire [0:0]web;
FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.\douta[7] (\douta[7] ),
.\doutb[7] (\doutb[7] ),
.ena(ena),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module FrameBuffer_blk_mem_gen_prim_width__parameterized1
(DOADO,
DOBDO,
clka,
clkb,
addra,
addrb,
dina,
dinb,
wea,
web,
ena);
output [7:0]DOADO;
output [7:0]DOBDO;
input clka;
input clkb;
input [13:0]addra;
input [13:0]addrb;
input [7:0]dina;
input [7:0]dinb;
input [0:0]wea;
input [0:0]web;
input ena;
wire [7:0]DOADO;
wire [7:0]DOBDO;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]dinb;
wire ena;
wire [0:0]wea;
wire [0:0]web;
FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1 \prim_init.ram
(.DOADO(DOADO),
.DOBDO(DOBDO),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.ena(ena),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module FrameBuffer_blk_mem_gen_prim_wrapper_init
(\douta[7] ,
\doutb[7] ,
clka,
clkb,
addra,
addrb,
dina,
dinb,
wea,
web,
ena);
output [7:0]\douta[7] ;
output [7:0]\doutb[7] ;
input clka;
input clkb;
input [13:0]addra;
input [13:0]addrb;
input [7:0]dina;
input [7:0]dinb;
input [0:0]wea;
input [0:0]web;
input ena;
wire \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92 ;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]dinb;
wire [7:0]\douta[7] ;
wire [7:0]\doutb[7] ;
wire ena;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h2020202020202020202020202020202020202020202020202020202020202B80),
.INIT_01(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_02(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_03(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_04(256'h802B202020202020202020202020202020202020202020202020202020202020),
.INIT_05(256'h4646464646464646464646464646464646464620202020202020202020202B2B),
.INIT_06(256'h4720202020202020202020205050505050505050505050505050505050464646),
.INIT_07(256'h2020414141202020202020202020202020202020474747474747474747474747),
.INIT_08(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_09(256'h2B2B202020202020202020202047474747474747474747474747202020202020),
.INIT_0A(256'h3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A4620202020202020202020202020),
.INIT_0B(256'h3A47474720202020202020503A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A50463A3A),
.INIT_0C(256'h20413A3A3A412020202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A),
.INIT_0D(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_0E(256'h20202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A3A474747202020),
.INIT_0F(256'h3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A4620202020202020202020202020),
.INIT_10(256'h3A3A3A3A474720202020503A3A3A3A3A5050505050503A3A3A3A3A3A50463A3A),
.INIT_11(256'h413A3A3A3A3A4120202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A),
.INIT_12(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_13(256'h20202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A3A3A3A3A474720),
.INIT_14(256'h3A3A4646464646464646463A3A3A3A3A3A464620202020202020202020202020),
.INIT_15(256'h473A3A3A3A3A472020503A3A3A3A3A502020202020503A3A3A3A3A5050463A3A),
.INIT_16(256'h3A3A3A3A3A3A3A41202020202020202020202020473A3A3A3A47474747474747),
.INIT_17(256'h2020202020202020202020202020202020202020202020202020202020202041),
.INIT_18(256'h20202020202020202020202020473A3A3A3A47474747474747473A3A3A3A3A47),
.INIT_19(256'h46464620202020202020463A3A3A3A3A46202020202020202020202020202020),
.INIT_1A(256'h20473A3A3A3A3A4720503A3A3A3A3A502020202020503A3A3A3A502020464646),
.INIT_1B(256'h3A3A3A3A3A3A3A3A412020202020202020202020474747474747202020202020),
.INIT_1C(256'h472020202020202020202020202020202020202020202020202020202020413A),
.INIT_1D(256'h2020202020202020202020202047474747474720202020202020473A3A3A3A3A),
.INIT_1E(256'h20202020202020202020463A3A3A3A3A46202020202020202020202020202020),
.INIT_1F(256'h2020473A3A3A3A3A47503A3A3A3A3A502020202020503A3A3A3A502020202020),
.INIT_20(256'h3A3A3A413A3A3A3A3A4120202020202020202020202020202020202020202020),
.INIT_21(256'h3A47202020202020202020202020202020202020202020202020202020413A3A),
.INIT_22(256'h202020202020202020202020202020202020202020202020202020473A3A3A3A),
.INIT_23(256'h464646464646464646463A3A3A3A3A3A46202020202020202020202020202020),
.INIT_24(256'h2020473A3A3A3A3A4720503A3A3A3A3A5050505050503A3A3A3A502020202020),
.INIT_25(256'h3A3A4120413A3A3A3A3A41202020202020202020202020202020202020202020),
.INIT_26(256'h3A472020202020202020202020202020202020202020202020202020413A3A3A),
.INIT_27(256'h202020202020202020202020202020202020202020202020202020473A3A3A3A),
.INIT_28(256'h463A3A3A3A3A3A3A3A3A3A3A3A3A3A3A46202020202020202020202020202020),
.INIT_29(256'h2020473A3A3A3A3A47202050503A3A3A3A3A3A3A3A3A3A3A3A3A502020202020),
.INIT_2A(256'h3A41202020413A3A3A3A3A412020202020202020474747474747474747472020),
.INIT_2B(256'h3A47202D2D2D2D2D2D2D2D2D2D2D2D2D2D2D202020202020202020413A3A3A3A),
.INIT_2C(256'h202020202020202020202020204747474747474747474720202020473A3A3A3A),
.INIT_2D(256'h463A3A3A3A3A3A3A3A3A3A3A3A3A3A3A46202020202020202020202020202020),
.INIT_2E(256'h2020473A3A3A3A3A47202020205050505050505050503A3A3A3A502020202020),
.INIT_2F(256'h412020202020413A3A3A3A3A4120202020202020473A3A3A3A3A3A3A3A472020),
.INIT_30(256'h3A47202D3A3A3A3A3A3A3A3A3A3A3A3A3A2D2020202020202020413A3A3A3A3A),
.INIT_31(256'h20202020202020202020202020473A3A3A3A3A3A3A3A4720202020473A3A3A3A),
.INIT_32(256'h464646464646464646463A3A3A3A3A3A46202020202020202020202020202020),
.INIT_33(256'h2020473A3A3A3A3A47202020202020202020202020503A3A3A3A502020202020),
.INIT_34(256'h41414141414141413A3A3A3A3A41202020202020473A3A3A3A47474747472020),
.INIT_35(256'h3A47202D2D2D2D2D2D2D2D2D2D2D2D2D2D2D20202020202020413A3A3A3A3A41),
.INIT_36(256'h20202020202020202020202020473A3A3A3A474747474720202020473A3A3A3A),
.INIT_37(256'h20202020202020202020463A3A3A3A3A46202020202020202020202020202020),
.INIT_38(256'h2020473A3A3A3A3A47202020202020202020202020503A3A3A3A502020202020),
.INIT_39(256'h3A3A3A3A3A3A3A3A3A3A3A3A3A3A412020202020473A3A3A3A47202020202020),
.INIT_3A(256'h3A4720202020202020202020202020202020202020202020413A3A3A3A3A3A3A),
.INIT_3B(256'h20202020202020202020202020473A3A3A3A472020202020202020473A3A3A3A),
.INIT_3C(256'h20202020202020202020463A3A3A3A3A46202020202020202020202020202020),
.INIT_3D(256'h20473A3A3A3A3A4720202020202020202020202020503A3A3A3A502020202020),
.INIT_3E(256'h414141414141414141413A3A3A3A3A4120202020473A3A3A3A47202020202020),
.INIT_3F(256'h4720202020202020202020202020202020202020202020413A3A3A3A3A414141),
.INIT_40(256'h20202020202020202020202020473A3A3A3A4720202020202020473A3A3A3A3A),
.INIT_41(256'h202020202020202046463A3A3A3A3A3A3A464620202020202020202020202020),
.INIT_42(256'h473A3A3A3A3A4720202020202020202020202050503A3A3A3A3A3A5050202020),
.INIT_43(256'h20202020202020202020413A3A3A3A3A41202020473A3A3A3A47474747474747),
.INIT_44(256'h20202020202020202020202020202020202020202020413A3A3A3A3A41202020),
.INIT_45(256'h20202020202020202020202020473A3A3A3A47474747474747473A3A3A3A3A47),
.INIT_46(256'h202020202020202046463A3A3A3A3A3A3A3A4620202020202020202020202020),
.INIT_47(256'h3A3A3A3A474720202020202020202020202020503A3A3A3A3A3A3A3A50202020),
.INIT_48(256'h2020202020202020202020413A3A3A3A3A412020473A3A3A3A3A3A3A3A3A3A3A),
.INIT_49(256'h202020202020202020202020202020202020202020413A3A3A3A3A4120202020),
.INIT_4A(256'h20202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A3A3A3A3A474720),
.INIT_4B(256'h202020202020202046463A3A3A3A3A3A3A3A4620202020202020202020202020),
.INIT_4C(256'h3A474747202020202020202020202020202020503A3A3A3A3A3A3A3A50202020),
.INIT_4D(256'h202020202020202020202020413A3A3A3A3A4120473A3A3A4747473A3A3A3A3A),
.INIT_4E(256'h2020202020202020202020202020202020202020413A3A3A3A3A412020202020),
.INIT_4F(256'h20202020202020202020202020473A3A3A4747473A3A3A3A3A3A474747202020),
.INIT_50(256'h2020202020202020464646464646464646464620202020202020202020202020),
.INIT_51(256'h4720202020202020202020202020202020202050505050505050505050202020),
.INIT_52(256'h2020202020202020202020202041414141414141474747472020204747474747),
.INIT_53(256'h2020202020202020202020202020202020202041414141414141202020202020),
.INIT_54(256'h2020202020202020202020202047474747202020474747474747202020202020),
.INIT_55(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_56(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_57(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_58(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_59(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_5A(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_5B(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_5C(256'h6F6E6973616320696E696D206465736162204C444856202F2041475046206E41),
.INIT_5D(256'h202020202020202020202020202020202020202020202020202020202020202E),
.INIT_5E(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_5F(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_60(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_61(256'h20217475706E69207478657420726F662064616F6279656B2061206573552020),
.INIT_62(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_63(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_64(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_65(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_66(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_67(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_68(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_69(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_6A(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_6B(256'h202020203A656B696C206427756F7920656D61672061206B6369502020202020),
.INIT_6C(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_6D(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_6E(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_6F(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_70(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_71(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_72(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_73(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_74(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_75(256'h2020202020202020202020657474656C756F5220202020202020202020202020),
.INIT_76(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_77(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_78(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_79(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_7A(256'h2020202020202020207265776F6C207265686769482020202020202020202020),
.INIT_7B(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_7C(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_7D(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_7E(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_7F(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\douta[7] }),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[7] }),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0 ),
.ENBWREN(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0 ),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
LUT3 #(
.INIT(8'h02))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1
(.I0(ena),
.I1(addra[12]),
.I2(addra[13]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0 ));
LUT2 #(
.INIT(4'h1))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2
(.I0(addrb[12]),
.I1(addrb[13]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0 ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0
(\douta[7] ,
\doutb[7] ,
clka,
clkb,
addra,
addrb,
dina,
dinb,
wea,
web,
ena);
output [7:0]\douta[7] ;
output [7:0]\doutb[7] ;
input clka;
input clkb;
input [13:0]addra;
input [13:0]addrb;
input [7:0]dina;
input [7:0]dinb;
input [0:0]wea;
input [0:0]web;
input ena;
wire \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92 ;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]dinb;
wire [7:0]\douta[7] ;
wire [7:0]\doutb[7] ;
wire ena;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_01(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_02(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_03(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_04(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_05(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_06(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_07(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_08(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_09(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_0A(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_0B(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_0C(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_0D(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_0E(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_0F(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_10(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_11(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_12(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_13(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_14(256'h2020202020202020202020202020202020202020202020202020202020202020),
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.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
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.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
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.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\douta[7] }),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[7] }),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0_n_0 ),
.ENBWREN(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0_n_0 ),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
LUT3 #(
.INIT(8'h08))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0
(.I0(addra[12]),
.I1(ena),
.I2(addra[13]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0_n_0 ));
LUT2 #(
.INIT(4'h4))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0
(.I0(addrb[13]),
.I1(addrb[12]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0_n_0 ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1
(DOADO,
DOBDO,
clka,
clkb,
addra,
addrb,
dina,
dinb,
wea,
web,
ena);
output [7:0]DOADO;
output [7:0]DOBDO;
input clka;
input clkb;
input [13:0]addra;
input [13:0]addrb;
input [7:0]dina;
input [7:0]dinb;
input [0:0]wea;
input [0:0]web;
input ena;
wire \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_33 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_35 ;
wire [7:0]DOADO;
wire [7:0]DOBDO;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]dinb;
wire ena;
wire ram_ena;
wire ram_enb;
wire [0:0]wea;
wire [0:0]web;
wire [15:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(1),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_01(256'h2020202020202020202020202020202020202020202020202020202020202020),
.INIT_02(256'h2020202020202020202020202020202020202020202020202020202020202020),
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.SRVAL_A(18'h00000),
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.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({addra[10:0],1'b0,1'b0,1'b0}),
.ADDRBWRADDR({addrb[10:0],1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
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.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:8],DOADO}),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:8],DOBDO}),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1],\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_33 }),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1],\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_35 }),
.ENARDEN(ram_ena),
.ENBWREN(ram_enb),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,web,web}));
LUT4 #(
.INIT(16'h1000))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_i_1
(.I0(addra[12]),
.I1(addra[11]),
.I2(addra[13]),
.I3(ena),
.O(ram_ena));
LUT3 #(
.INIT(8'h04))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_i_2
(.I0(addrb[11]),
.I1(addrb[13]),
.I2(addrb[12]),
.O(ram_enb));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module FrameBuffer_blk_mem_gen_top
(doutb,
douta,
clka,
clkb,
addra,
addrb,
dina,
dinb,
wea,
web,
ena);
output [7:0]doutb;
output [7:0]douta;
input clka;
input clkb;
input [13:0]addra;
input [13:0]addrb;
input [7:0]dina;
input [7:0]dinb;
input [0:0]wea;
input [0:0]web;
input ena;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]dinb;
wire [7:0]douta;
wire [7:0]doutb;
wire ena;
wire [0:0]wea;
wire [0:0]web;
FrameBuffer_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.wea(wea),
.web(web));
endmodule
(* C_ADDRA_WIDTH = "14" *) (* C_ADDRB_WIDTH = "14" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "8" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "2" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 4.61856 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "1" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "FrameBuffer.mem" *)
(* C_INIT_FILE_NAME = "FrameBuffer.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "2" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "10240" *) (* C_READ_DEPTH_B = "10240" *) (* C_READ_WIDTH_A = "8" *)
(* C_READ_WIDTH_B = "8" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "1" *) (* C_USE_BYTE_WEB = "1" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "10240" *) (* C_WRITE_DEPTH_B = "10240" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "8" *) (* C_WRITE_WIDTH_B = "8" *)
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_1" *) (* downgradeipidentifiedwarnings = "yes" *)
module FrameBuffer_blk_mem_gen_v8_3_1
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [13:0]addra;
input [7:0]dina;
output [7:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [13:0]addrb;
input [7:0]dinb;
output [7:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [13:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [7:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [7:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [13:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]dinb;
wire [7:0]douta;
wire [7:0]doutb;
wire eccpipece;
wire ena;
wire enb;
wire injectdbiterr;
wire injectsbiterr;
wire regcea;
wire regceb;
wire rsta;
wire rstb;
wire s_aclk;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_injectdbiterr;
wire s_axi_injectsbiterr;
wire s_axi_rready;
wire [7:0]s_axi_wdata;
wire s_axi_wlast;
wire [0:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sleep;
wire [0:0]wea;
wire [0:0]web;
assign dbiterr = \<const0> ;
assign rdaddrecc[13] = \<const0> ;
assign rdaddrecc[12] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[13] = \<const0> ;
assign s_axi_rdaddrecc[12] = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
FrameBuffer_blk_mem_gen_v8_3_1_synth inst_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_1_synth" *)
module FrameBuffer_blk_mem_gen_v8_3_1_synth
(doutb,
douta,
clka,
clkb,
addra,
addrb,
dina,
dinb,
wea,
web,
ena);
output [7:0]doutb;
output [7:0]douta;
input clka;
input clkb;
input [13:0]addra;
input [13:0]addrb;
input [7:0]dina;
input [7:0]dinb;
input [0:0]wea;
input [0:0]web;
input ena;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]dinb;
wire [7:0]douta;
wire [7:0]doutb;
wire ena;
wire [0:0]wea;
wire [0:0]web;
FrameBuffer_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.wea(wea),
.web(web));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// -*- Mode: Verilog -*-
// Filename : testbench.v
// Description : Basic Picoblaze TB
// Author : Philip Tracton
// Created On : Thu May 21 22:35:48 2015
// Last Modified By: Philip Tracton
// Last Modified On: Thu May 21 22:35:48 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`timescale 1ns/1ns
`include "includes.v"
module testbench (/*AUTOARG*/) ;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] ANODE; // From dut of display_top.v
wire [7:0] CATHODE; // From dut of display_top.v
wire TX; // From dut of display_top.v
// End of automatics
/*AUTOREG*/
//
// Free Running 100 MHz clock
//
reg CLK_IN = 0;
initial begin
forever begin
#5 CLK_IN <= ~CLK_IN;
end
end
//
// Free Running 50 MHz Clock
//
reg clk_tb;
parameter _clk_50mhz_high = 10,
_clk_50mhz_low = 10,
_clk_50mhz_period = _clk_50mhz_high + _clk_50mhz_low;
initial
begin
clk_tb <= 'b0;
forever
begin
#(_clk_50mhz_low) clk_tb = 1;
#(_clk_50mhz_high) clk_tb = 0;
end
end
//
// Reset
//
reg RESET_IN = 0;
initial begin
#100 RESET_IN <= 1;
#1000 RESET_IN <= 0;
end
//
// Asynch. Reset to device
//
reg reset_tb;
initial
begin
reset_tb = 0;
#1 reset_tb = 1;
#200 reset_tb = 0;
end
reg [31:0] read_word;
display_top dut(/*AUTOINST*/
// Outputs
.TX (TX),
.ANODE (ANODE[3:0]),
.CATHODE (CATHODE[7:0]),
// Inputs
.CLK_IN (CLK_IN),
.RESET_IN (RESET_IN),
.RX (RX));
/****************************************************************************
UART 0
The WB UART16550 from opencores is used here to simulate a UART on the other end
of the cable. It will allow us to send/receive characters to the NGMCU firmware
***************************************************************************/
wire [31:0] uart0_adr;
wire [31:0] uart0_dat_o;
wire [31:0] uart0_dat_i;
wire [3:0] uart0_sel;
wire uart0_cyc;
wire uart0_stb;
wire uart0_we;
wire uart0_ack;
wire uart0_int;
assign uart0_dat_o[31:8] = 'b0;
uart_top uart0(
.wb_clk_i(CLK_IN),
.wb_rst_i(reset_tb),
.wb_adr_i(uart0_adr[4:0]),
.wb_dat_o(uart0_dat_o),
.wb_dat_i(uart0_dat_i),
.wb_sel_i(uart0_sel),
.wb_cyc_i(uart0_cyc),
.wb_stb_i(uart0_stb),
.wb_we_i(uart0_we),
.wb_ack_o(uart0_ack),
.int_o(uart0_int),
.stx_pad_o(RX),
.srx_pad_i(TX),
.rts_pad_o(),
.cts_pad_i(1'b0),
.dtr_pad_o(),
.dsr_pad_i(1'b0),
.ri_pad_i(1'b0),
.dcd_pad_i(1'b0),
.baud_o()
);
wb_mast uart_master0(
.clk (CLK_IN),
.rst (reset_tb),
.adr (uart0_adr),
.din (uart0_dat_o),
.dout(uart0_dat_i),
.cyc (uart0_cyc),
.stb (uart0_stb),
.sel (uart0_sel),
.we (uart0_we ),
.ack (uart0_ack),
.err (1'b0),
.rty (1'b0)
);
uart_tasks uart_tasks();
test_tools test_tools();
//
// Test Case
//
initial begin
@(posedge RESET_IN);
$display("RESET: Asserted @ %d", $time);
@(negedge RESET_IN);
$display("RESET: De-Asserted @ %d", $time);
repeat(100) @(posedge CLK_IN);
`UART_CONFIG;
`UART_WRITE_CHAR("3");
`UART_WRITE_CHAR("4");
`UART_WRITE_CHAR("5");
`UART_WRITE_CHAR("6");
`UART_WRITE_CHAR("7");
repeat(100)@(posedge clk_tb);
`UART_READ_CHAR("3");
`UART_READ_CHAR("4");
`UART_READ_CHAR("5");
`UART_READ_CHAR("6");
`UART_READ_CHAR("7");
repeat(100) @(posedge CLK_IN);
`TEST_PASSED = 1;
end
endmodule // Basic
|
/*
* Copyright 2020-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
(* whitebox *)
module ADDER (
a, b, cin,
sum, cout
);
input wire a;
input wire b;
(* carry = "ADDER" *)
input wire cin;
(* DELAY_CONST_a = "300e-12" *)
(* DELAY_CONST_b = "300e-12" *)
(* DELAY_CONST_cin = "300e-12" *)
output wire sum;
(* carry = "ADDER" *)
(* DELAY_CONST_a = "300e-12" *)
(* DELAY_CONST_b = "300e-12" *)
(* DELAY_CONST_cin = "10e-12" *)
output wire cout;
// Full adder combinational logic
assign sum = a ^ b ^ cin;
assign cout = ((a ^ b) & cin) | (a & b);
// Timing parameters, not supported by Yosys at the moment.
`ifndef YOSYS
`timescale 1ps/1ps
specify
specparam T1 300;
specparam T2 10;
// (input->output) min:typ:max
(a => sum) = T1;
(b => sum) = T1;
(cin => sum) = T1;
(a => cout) = T1;
(b => cout) = T1;
(cin => cout) = T2;
endspecify
`endif
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_transition (clock, reset, enable, test_expr, start_state, next_state, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr, start_state, next_state;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_TRANSITION";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_transition_logic.v"
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endif
`ifdef OVL_SVA
`include "./sva05/assert_transition_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_transition_psl_logic.v"
`else
`endmodule // ovl_transition
`endif
|
module step_id(inst, ena_, cond_dout,
rdy_nop_, rdy_cpf_, rdy_cpt_, rdy_ld_, rdy_st_, rdy_clr_, rdy_im_, rdy_tce_, rdy_ts_, rdy_add_, rdy_sub_);
input[7:0] inst;
input ena_;
input cond_dout;
output rdy_nop_, rdy_cpf_, rdy_cpt_, rdy_ld_, rdy_st_, rdy_clr_, rdy_im_, rdy_tce_, rdy_ts_, rdy_add_, rdy_sub_;
wire cond_ = inst[7] ^ cond_dout;
wire[6:0] inst_cond = inst[6:0] & {7{~(cond_ | ena_)}};
assign rdy_nop_ = inst_cond[6:0] != 7'b0000000 || ena_;
assign rdy_cpf_ = inst_cond[6:4] != 3'b010 || inst_cond[3:0] == 4'b0000;
assign rdy_cpt_ = inst_cond[6:4] != 3'b011 || inst_cond[3:0] == 4'b0000;
assign rdy_ld_ = {inst_cond[6:2], inst_cond[0]} != {5'b10001, 1'b0};
assign rdy_st_ = {inst_cond[6:2], inst_cond[0]} != {5'b10001, 1'b1};
assign rdy_clr_ = inst_cond != 7'b1010000;
assign rdy_im_ = inst_cond[6:5] != 2'b11;
assign rdy_tce_ = inst_cond != 7'b0001100;
assign rdy_ts_ = {inst_cond[6], inst_cond[3:0]} != {1'b0, 4'b0000} || inst_cond[5:4] == 2'b00;
assign rdy_add_ = inst_cond != 7'b1010110;
assign rdy_sub_ = inst_cond != 7'b1010111;
endmodule
|
// file: bclk_dll_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module bclk_dll_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 7.518*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
bclk_dll_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
// Freq Check
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD3_SYMBOL_V
`define SKY130_FD_SC_MS__DLYGATE4SD3_SYMBOL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlygate4sd3 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD3_SYMBOL_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1
// IP Revision: 10
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_auto_cc_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_aclk,
m_axi_aresetn,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [3 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [3 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [3 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [3 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 MI_CLK CLK" *)
input wire m_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 MI_RST RST" *)
input wire m_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [3 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [3 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [3 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [3 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_clock_converter_v2_1_10_axi_clock_converter #(
.C_FAMILY("artix7"),
.C_AXI_ID_WIDTH(4),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(1),
.C_AXI_PROTOCOL(0),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(4'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(m_axi_aclk),
.m_axi_aresetn(m_axi_aresetn),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31O_1_V
`define SKY130_FD_SC_HD__A31O_1_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a31o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a31o_1 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31O_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S2S_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DLYMETAL6S2S_BEHAVIORAL_PP_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__dlymetal6s2s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S2S_BEHAVIORAL_PP_V |
module alu_datapath(clk, alu_data, opcode_value, store_a, store_b, start, alu_done, result, overflow_def);
parameter DATA_WIDTH = 8;
input clk;
input alu_data;
input opcode_value;
input store_a;
input store_b;
input start;
output alu_done;
output result;
output overflow_def;
reg overflow_def;
wire clk;
wire [DATA_WIDTH-1:0] alu_data;
wire [1:0] opcode_value;
wire store_a;
wire store_b;
wire start;
reg alu_done;
reg start_def;
reg [DATA_WIDTH-1:0] result;
parameter ON = 1'b1;
parameter OFF = 1'b0;
parameter ADD = 2'b00;
parameter SUB = 2'b01;
parameter PAR = 2'b10;
parameter COMP = 2'b11;
reg [DATA_WIDTH-1:0] buf_a;
reg [DATA_WIDTH-1:0] buf_b;
wire done;
reg [DATA_WIDTH-1:0] add_a;
reg [DATA_WIDTH-1:0] add_b;
wire [DATA_WIDTH-1:0] add_sum;
reg add_carry_in;
wire add_overflow;
reg [DATA_WIDTH-1:0] sub_a;
reg [DATA_WIDTH-1:0] sub_b;
wire [DATA_WIDTH-1:0] sub_diff;
reg sub_borrow_in;
wire sub_borrow_out;
reg [DATA_WIDTH-1:0] par_a;
reg [DATA_WIDTH-1:0] par_b;
wire [DATA_WIDTH-1:0] par_parity;
reg [DATA_WIDTH-1:0] comp_a;
reg [DATA_WIDTH-1:0] comp_b;
wire [DATA_WIDTH-1:0] comp_comp;
always @(posedge clk or store_a or store_b or start)
begin
if(store_a)
begin
buf_a = alu_data;
end
else if(store_b)
begin
buf_b = alu_data;
end
else if(start)
begin
case(opcode_value)
ADD:
begin
add_a = buf_a;
add_b = buf_b;
add_carry_in = 1'b0;
start_def = 1'b1;
end
SUB:
begin
sub_a = buf_a;
sub_b = buf_b;
sub_borrow_in = 1'b0;
start_def = 1'b1;
end
PAR:
begin
par_a = buf_a;
par_b = buf_b;
start_def = 1'b1;
end
COMP:
begin
comp_a = buf_a;
comp_b = buf_b;
start_def = 1'b1;
end
endcase
end
end
always @(posedge clk or done)
begin
if(done)
begin
case(opcode_value)
ADD:
begin
result = add_sum;
overflow_def = add_overflow;
alu_done = ON;
end
SUB:
begin
result = sub_diff;
overflow_def = sub_borrow_out;
alu_done = ON;
end
PAR:
begin
result = par_parity;
alu_done = ON;
overflow_def = OFF;
end
COMP:
begin
result = comp_a ^~ comp_b;
alu_done = ON;
overflow_def = OFF;
end
endcase
end
else
begin
result = 0;
overflow_def = 0;
alu_done = OFF;
end
end
byte_adder #(DATA_WIDTH) adder_ex(
.byte_a(add_a),
.byte_b(add_b),
.byte_carry_in(add_carry_in),
.byte_sum(add_sum),
.byte_overflow(add_overflow),
.start(start_def),
.done(done)
);
byte_subtractor #(DATA_WIDTH) subtractor_ex(
.byte_a(sub_a),
.byte_b(sub_b),
.byte_borrow_in(sub_borrow_in),
.byte_diff(sub_diff),
.byte_borrow_out(sub_borrow_out),
.start(start_def),
.done(done)
);
byte_parity #(DATA_WIDTH) parity_ex(
.byte_a(par_a),
.byte_b(par_b),
.byte_parity(par_parity),
.start(start_def),
.done(done)
);
byte_comp #(DATA_WIDTH) comp_ex(
.byte_a(comp_a),
.byte_b(comp_b),
.byte_comp(comp_comp),
.start(start_def),
.done(done)
);
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_181x128a.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1.191 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_181x128a (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrempty,
wrusedw);
input aclr;
input [180:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [180:0] q;
output rdempty;
output wrempty;
output [6:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "181"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "181"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "181"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 181 0 INPUT NODEFVAL "data[180..0]"
// Retrieval info: USED_PORT: q 0 0 181 0 OUTPUT NODEFVAL "q[180..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 7 0 OUTPUT NODEFVAL "wrusedw[6..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 181 0 data 0 0 181 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 181 0 @q 0 0 181 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 7 0 @wrusedw 0 0 7 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_181x128a.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_181x128a.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_181x128a.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_181x128a.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_181x128a_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_181x128a_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`default_nettype none
`timescale 1ns / 1ps
module timer_controller (
input wire clock,
input wire reset,
input wire int_ack,
output reg int_req,
input wire [15:0] A,
input wire [7:0] Di,
output wire [7:0] Do,
input wire wr_n,
input wire rd_n,
input wire cs
);
////////////////////////////////////////////////
// Timer Registers
//
// DIV - Divider Register (FF04)
// Increments 16384 times a second
//
// TIMA - Timer Counter (FF05)
// Increments at frequency specified by TAC
//
// TMA - Timer Modulo (FF06)
// Value to load into TIMA on overflow
//
// TAC - Timer Control (FF07)
// Bit 2: 0 <= stop, 1 <= start
// Bit 1-0: 00 <= 4.096 KHz
// 01 <= 262.144 KHz
// 10 <= 65.536 KHz
// 11 <= 16.384 KHz
////////////////////////////////////////////////
reg[7:0] DIV;
reg[7:0] TIMA;
reg[7:0] TMA;
reg[7:0] TAC;
reg[7:0] reg_out;
parameter MAX_TIMER = 8'hFF;
wire enable;
wire e0, e1, e2, e3;
divider #(1024) d0(reset, clock, e0);
divider #(16) d1(reset, clock, e1);
divider #(64) d2(reset, clock, e2);
divider #(256) d3(reset, clock, e3);
always @(posedge clock)
begin
if (reset)
begin
DIV <= 8'h0;
TIMA <= 8'h0;
TMA <= 8'h0;
TAC <= 8'h0;
int_req <= 1'b0;
reg_out <= 8'h0;
end
else
begin
// Read / Write for registers
if (cs)
begin
if (!wr_n)
begin
case (A)
16'hFF04: DIV <= 8'h0;
16'hFF05: TIMA <= Di;
16'hFF06: TMA <= Di;
16'hFF07: TAC <= Di;
endcase
end
else if (!rd_n)
begin
case (A)
16'hFF04: reg_out <= DIV;
16'hFF05: reg_out <= TIMA;
16'hFF06: reg_out <= TMA;
16'hFF07: reg_out <= TAC;
endcase
end
end
// Clear overflow interrupt
if (int_ack)
int_req <= 1'b0;
// Increment timers
if (enable)
begin
if (TIMA == MAX_TIMER)
int_req <= 1'b1;
TIMA <= (TIMA == MAX_TIMER) ? TMA : TIMA + 1'b1;
end
if (e3)
begin
DIV <= DIV + 1'b1;
end
end
end
assign Do = (cs) ? reg_out : 8'hZZ;
assign enable =
(TAC[2] == 0) ? 1'b0 :
(TAC[1:0] == 0) ? e0 :
(TAC[1:0] == 1) ? e1 :
(TAC[1:0] == 2) ? e2 :
(TAC[1:0] == 3) ? e3 : 1'b0;
endmodule
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
// All pins listed ok. REF, DIVI and DIVO only used on AES for video PLL hack
// Video mode pin is the VMODE parameter
module lspc2_a2(
input CLK_24M,
input RESET,
output [15:0] PBUS_OUT,
inout [23:16] PBUS_IO,
input [3:1] M68K_ADDR,
inout [15:0] M68K_DATA,
input LSPOE, LSPWE,
input DOTA, DOTB,
output CA4,
output S2H1,
output S1H1,
output LOAD,
output H, EVEN1, EVEN2, // For ZMC2
output IPL0, IPL1,
output CHG, // Also called TMS0
output LD1, LD2, // Buffer address load
output PCK1, PCK2,
output [3:0] WE,
output [3:0] CK,
output SS1, SS2, // Buffer pair selection for B1
output RESETP,
output SYNC,
output CHBL,
output BNKB,
output VCS, // LO ROM output enable
output LSPC_8M,
output LSPC_4M
);
parameter VMODE = 1'b0; // NTSC
wire [8:0] PIXELC;
wire [3:0] PIXEL_HPLUS;
wire [8:0] RASTERC;
wire [7:0] AA_SPEED;
wire [2:0] AA_COUNT; // Auto-animation tile #
wire [15:0] CPU_DATA_OUT;
wire [15:0] VRAM_LOW_READ;
wire [15:0] VRAM_HIGH_READ;
wire [15:0] REG_VRAMADDR;
wire [15:0] VRAM_ADDR;
wire [15:0] VRAM_ADDR_MUX;
wire [15:0] VRAM_ADDR_AUTOINC;
wire [15:0] REG_VRAMRW;
wire [15:0] VRAM_WRITE;
wire [15:0] REG_VRAMMOD;
wire [15:0] REG_LSPCMODE;
wire [2:0] TIMER_MODE;
wire [3:0] T31_P;
wire [3:0] U24_P;
wire [3:0] O227_Q;
wire [7:0] P_MUX_HIGH;
wire [7:0] P_MUX_LOW;
wire [23:0] P_OUT_MUX;
wire [3:0] VSHRINK_INDEX;
wire [3:0] VSHRINK_LINE;
wire [8:0] XPOS;
wire [7:0] XPOS_ROUND_UP;
wire [2:0] SPR_TILE_AA;
wire [3:0] G233_Q;
wire [7:0] SPR_Y_LOOKAHEAD;
wire [8:0] SPR_Y_ADD;
wire [7:0] SPR_TILE_A; // This should be called SPR_Y_RENDER or something similar
wire [7:0] SPR_TILE_AB; // This should be called SPR_Y_RENDER_LOOP or something similar
wire [8:0] SPR_Y_SHRINK;
wire [3:0] SPR_LINE;
wire [7:0] SPR_LINE_MUX;
wire [19:0] SPR_TILE;
wire [7:0] YSHRINK;
wire [8:0] SPR_Y;
wire [7:0] SPR_PAL;
wire [3:0] FIX_PAL;
wire [11:0] FIX_TILE;
wire [3:0] HSHRINK;
wire [15:0] PIPE_C;
wire [3:0] SPR_TILEMAP;
wire [7:0] ACTIVE_RD;
wire [3:0] P201_Q;
assign S1H1 = LSPC_3M;
assign S2H1 = LSPC_1_5M;
// PCK1, PCK2, H
FD2 T168A(CLK_24M, T160A_OUT, PCK1, nPCK1);
FD2 T162A(CLK_24M, T160B_OUT, PCK2, );
FD2 U167(~PCK2, T172_Q, H, );
FDM T172(nPCK1, SPR_TILE_HFLIP, T172_Q, );
assign CA4 = T172_Q ^ LSPC_1_5M;
// EVEN1, EVEN2
assign U105A_OUT = ~&{nHSHRINK_OUT_A, nHSHRINK_OUT_B, nEVEN_ODD};
assign U107_OUT = ~&{nHSHRINK_OUT_A, EVEN_nODD, HSHRINK_OUT_B};
assign U109_OUT = ~&{HSHRINK_OUT_A, nEVEN_ODD};
assign U112_OUT = ~&{U105A_OUT, U107_OUT, U109_OUT};
//assign #13 EVEN1 = U112_OUT; // BD5 U162
assign EVEN1 = U112_OUT;
FD2 U144A(CLK_24M, U112_OUT, EVEN2, );
// Pixel parity select
assign nPARITY_INIT = ~&{nCHAINED, S53A_OUT}; // R42A
assign nXPOS_ZERO = ~PIPE_C[0];
assign S58A_OUT = ~|{nXPOS_ZERO, nPARITY_INIT};
assign ONE_PIXEL = HSHRINK_OUT_A ^ HSHRINK_OUT_B; // U83
assign U72_OUT = ONE_PIXEL ^ nEVEN_ODD;
assign U57B_OUT = nPARITY_INIT & U72_OUT;
assign U56A_OUT = ~|{S58A_OUT, U57B_OUT};
FD2 U68A(CLK_24MB, ~LSPC_12M, CK_HSHRINK_REG, U68A_nQ);
FD2 U74A(~U68A_nQ, U56A_OUT, EVEN_nODD, nEVEN_ODD);
// CPU VRAM address update select
// $3C0000 REG_VRAMADDR 0 (update with written value)
// $3C0002 REG_VRAMRW 1 (update with REG_VRAMMOD)
assign C22A_OUT = ~&{WR_VRAM_RW, WR_VRAM_ADDR};
FDM B18(C22A_OUT, M68K_ADDR[1], VRAM_ADDR_UPD_TYPE, );
// VRAM_ADDR with REG_VRAMMOD applied
// G18 G81 F91 F127
assign VRAM_ADDR_AUTOINC = REG_VRAMMOD + VRAM_ADDR;
// CPU VRAM address update mux
// C144A C142A C140B C138B
// A112B A111A A109A A110B
// D110B D106B D108B D85A
// F10A F12A F26A F12B
assign VRAM_ADDR_MUX = VRAM_ADDR_UPD_TYPE ? VRAM_ADDR_AUTOINC : REG_VRAMADDR;
// VRAM address update FFs
// F14 D48 C105 C164
FDS16bit F14(D112B_OUT, VRAM_ADDR_MUX, VRAM_ADDR);
// ...Second stage
// F165 D178 D141 E196
FDS16bit E196(O108B_OUT, REG_VRAMRW, VRAM_WRITE);
// Pulse for updating internal VRAM address
// nCPU_WR_HIGH and nCPU_WR_LOW are "write done" pulses for both VRAM zones
// Happens when write is done or write to REG_VRAMADDR
assign O108B_OUT = ~&{nCPU_WR_HIGH, nCPU_WR_LOW};
assign D112B_OUT = ~|{~WR_VRAM_ADDR, O108B_OUT};
// CPU read data output. Outputs are not enabled all at once, this is strange.
// After LSPOE goes low, at least 1.5mclk is required for all outputs to be enabled.
FDM C71(CLK_24M, LSPOE, C71_Q, LSPOE_SEQA);
FDM C68(CLK_24MB, C71_Q, C68_Q, LSPOE_SEQB);
FDM C75(CLK_24M, C68_Q, , LSPOE_SEQC);
assign M68K_DATA[1:0] = LSPOE ? 2'bzz : CPU_DATA_OUT[1:0]; // No delay
assign B71_OUT = ~&{~LSPOE, LSPOE_SEQA};
assign M68K_DATA[7:2] = B71_OUT ? 6'bzzzzzz : CPU_DATA_OUT[7:2]; // t+1
assign B75A_OUT = ~&{~LSPOE, LSPOE_SEQB};
assign M68K_DATA[9:8] = B75A_OUT ? 2'bzz : CPU_DATA_OUT[9:8]; // t+2
assign B74_OUT = ~&{~LSPOE, LSPOE_SEQC};
assign M68K_DATA[15:10] = B74_OUT ? 6'bzzzzzz : CPU_DATA_OUT[15:10]; // t+3
// Auto-animation bit enables
// C184A
assign AUTOANIM3_EN = SPR_AA_3 & ~AA_DISABLE;
assign C186A_OUT = SPR_AA_2 & ~AA_DISABLE;
// B180B
assign AUTOANIM2_EN = AUTOANIM3_EN | C186A_OUT;
// Timing/sequencing stuff
// This doesn't mean anything special, it just outputs periodic signals to get everything moving
assign T56A_OUT = ~&{LSPC_6M, LSPC_3M};
assign T58A_OUT = ~&{LSPC_6M, LSPC_3M};
FDM T53(LSPC_12M, T56A_OUT, T53_Q, );
FDM U53(CLK_24M, T53_Q, U53_Q, );
assign nPBUS_OUT_EN = U53_Q & T53_Q;
FDPCell T69(LSPC_12M, LSPC_3M, RESETP, 1'b1, , T69_nQ);
assign T73A_OUT = LSPC_3M | T69_nQ;
FJD T140(CLK_24M, T134_nQ, 1'b1, T73A_OUT, T140_Q, );
FJD T134(CLK_24M, T140_Q, 1'b1, T73A_OUT, , T134_nQ);
FD2 U129A(CLK_24M, T134_nQ, U129A_Q, U129A_nQ);
assign T125A_OUT = U129A_nQ | T140_Q;
BD3 P198A(Q174B_OUT, P198A_OUT);
FS1 P201(LSPC_12M, P198A_OUT, P201_Q);
assign P219A_OUT = ~|{O159_QB, ~P201_Q[0]};
assign P222A_OUT = ~&{P219A_OUT, ~P201_Q[1]};
assign CLK_SPR_TILE = P201_Q[1];
assign R94A_OUT = ~&{P201_Q[2], R91_Q};
assign D208B_OUT = ~P201_Q[3];
// NEO-B1 control signals
// Latch for CK1/2 and WE1/2
LT4 T31(LSPC_12M, {T38A_OUT, T28_OUT, T29A_OUT, T20B_OUT}, T31_P, );
// Latch for CK3/4 and WE3/4
LT4 U24(LSPC_12M, {U37B_OUT, U21B_OUT, U35A_OUT, U31A_OUT}, U24_P, );
// CKs and WEs can only be low when LSPC_12M is high
assign WE1 = ~&{T31_P[0], LSPC_12M};
assign WE2 = ~&{T31_P[1], LSPC_12M};
assign CK1 = ~&{T31_P[2], LSPC_12M};
assign CK2 = ~&{T31_P[3], LSPC_12M};
assign WE3 = ~&{U24_P[2], LSPC_12M};
assign WE4 = ~&{U24_P[3], LSPC_12M};
assign CK3 = ~&{U24_P[0], LSPC_12M};
assign CK4 = ~&{U24_P[1], LSPC_12M};
assign WE = {WE4, WE3, WE2, WE1};
assign CK = {CK4, CK3, CK2, CK1};
// Most of the following NAND gates are making 2:1 muxes like on the Alpha68k
// For buffer A:
// Clearing write pulses gates
assign T22A_OUT = ~&{T50B_OUT, SS1};
assign T40B_OUT = ~&{T48A_OUT, SS1};
// WRITEPX* gates
assign T50A_OUT = ~&{WRITEPX_A, CHG_D};
assign T40A_OUT = ~&{WRITEPX_B, CHG_D};
// Enable writes for opaque pixels only
assign T17A_OUT = ~&{DOTA, ~T50A_OUT};
assign T22B_OUT = ~&{DOTB, ~T40A_OUT};
// Merge writes with clearing write pulses
assign T20B_OUT = ~&{T22A_OUT, T17A_OUT};
assign T29A_OUT = ~&{T40B_OUT, T22B_OUT};
// Merge clocks with LD1_D pulses
assign T28_OUT = ~&{T22A_OUT, LD1_D, T50A_OUT};
assign T38A_OUT = ~&{T40B_OUT, T40A_OUT, LD1_D};
// For buffer B:
// Clearing write pulses gates
assign U33B_OUT = ~&{T48A_OUT, SS2};
assign T20A_OUT = ~&{T50B_OUT, SS2};
// WRITEPX* gates
assign U51B_OUT = ~&{WRITEPX_A, nCHG_D};
assign U39B_OUT = ~&{WRITEPX_B, nCHG_D};
// Enable writes for opaque pixels only
assign U18A_OUT = ~&{DOTA, ~U51B_OUT};
assign U38A_OUT = ~&{DOTB, ~U39B_OUT};
// Merge writes with clearing write pulses
assign U21B_OUT = ~&{T20A_OUT, U18A_OUT};
assign U37B_OUT = ~&{U33B_OUT, U38A_OUT};
// Merge clocks with LD1_D pulses
assign U35A_OUT = ~&{LD2_D, U33B_OUT, U39B_OUT};
assign U31A_OUT = ~&{LD2_D, T20A_OUT, U51B_OUT};
// Buffer shift-out clocks, alternates between odd/even
assign T50B_OUT = LSPC_3M & LSPC_6M;
assign T48A_OUT = ~LSPC_3M & LSPC_6M;
// Pixel write pulse selection (odd/even)
assign U89A_OUT = ~&{nHSHRINK_OUT_B, nEVEN_ODD, HSHRINK_OUT_A};
assign U92A_OUT = ~&{nHSHRINK_OUT_A, nEVEN_ODD, HSHRINK_OUT_B};
assign U91_OUT = ~&{nHSHRINK_OUT_B, EVEN_nODD, HSHRINK_OUT_A};
assign U94_OUT = ~&{nHSHRINK_OUT_A, EVEN_nODD, HSHRINK_OUT_B};
// Enabled write pulses only if pixel is not skipped for h-shrink
assign U88B_OUT = HSHRINK_OUT_A | HSHRINK_OUT_B;
assign U85_OUT = &{U89A_OUT, U92A_OUT, U88B_OUT};
assign U86A_OUT = &{U88B_OUT, U94_OUT, U91_OUT};
// Final FFs
FD2 T82A(CLK_24M, U85_OUT, WRITEPX_A, );
FD2 T86(CLK_24M, U86A_OUT, WRITEPX_B, );
// LD1/2 signal generation. Those are used to tell NEO-B1 to reload the write address (X position)
// Get which buffer should have the rendering pulses, and which should have the reset pulse
FDM R50(LSPC_3M, FLIP_nQ, R50_Q, R50_nQ);
// Periodic signals
FDM R69(LSPC_3M, LSPC_1_5M, R69_Q, R69_nQ);
FDM S55(LSPC_12M, LSPC_3M, S55_Q, );
assign S53A_OUT = S55_Q & LSPC_6M;
// LOAD output
FD2 R35A(CLK_24MB, S53A_OUT, LOAD, );
// For LD1:
// Gate with chain bit (prevents address reload)
assign nCHAINED = ~|{PIPE_C[13], R69_nQ};
// Gate reset LD pulse (once at start of line being shifted out)
assign R44B_OUT = ~&{R50_nQ, R53_Q};
// Gate rendering LD pulses
assign R48B_OUT = ~&{nCHAINED, R50_Q};
// Merge
assign R42B_OUT = ~&{R44B_OUT, R48B_OUT};
// Sync
assign LD1_D = ~&{R42B_OUT, S53A_OUT};
FD2 R32(CLK_24MB, LD1_D, LD1, );
// For LD2:
// Gate reset LD pulse (once at start of line being shifted out)
assign R44A_OUT = ~&{R53_Q, R50_Q};
// Gate rendering LD pulses
assign R46A_OUT = ~&{R50_nQ, nCHAINED};
// Merge
assign R46B_OUT = ~&{R44A_OUT, R46A_OUT};
// Sync
assign LD2_D = ~&{R46B_OUT, S53A_OUT};
FD2 R28A(CLK_24MB, LD2_D, LD2, );
// Reset LD pulse generation. This tells NEO-B1 to reload the address before shifting out a buffer
// At this very moment, the address should be 000 on the P bus
// Triggers at pixel #264
FDPCell O62(PIXELC[3], PIXELC[8], 1'b1, RESETP, O62_Q, );
// Triggers at pixel #268
FDPCell P74(PIXELC[2], O62_Q, 1'b1, RESETP, P74_Q, );
// Make unique pulse
FDM R53(LSPC_3M, R67A_OUT, R53_Q, );
assign R67A_OUT = R74_nQ & P74_Q;
FDPCell R74(LSPC_1_5M, P74_Q, 1'b1, RESETP, , R74_nQ);
// Reload pulse for the h-shrink shift registers
// Perdiodic as all sprites take the same time to render regardless of h-shrink value
assign R48A_OUT = ~&{S53A_OUT, R69_Q};
FD2 R56A(CLK_24MB, R48A_OUT, LD_HSHRINK_REG, );
// CHG output
FDPCell S137(LSPC_1_5M, CHG_D, 1'b1, RESETP, CHG, );
// SS1/2 outputs, periodic
FDPCell O69(CLK_24MB, nFLIP, RESETP, 1'b1, , FLIP_nQ);
FDPCell R63(PIXELC[2], FLIP_nQ, 1'b1, RESETP, CHG_D, nCHG_D);
FDM S48(LSPC_3M, R15_QD, , S48_nQ);
// S40A
assign SS1 = ~|{S48_nQ, CHG_D};
// S39
assign SS2 = ~|{nCHG_D, S48_nQ};
// 16-pixel lookahead for fix tiles
assign J20A_OUT = ~&{PIXELC[8:7]};
// I51
assign PIXEL_HPLUS = 5'd15 + {~J20A_OUT, PIXELC[6:4]} + PIXELC[3];
// V-shrink mirroring and pipeline
FDM R179(VCS, SPR_CONTINUOUS, R179_Q, );
// Mirror V-shrink values for second half of sprite if needed
assign S186_OUT = ~(~P235_OUT ^ R179_Q);
assign SPRITEMAP_ADDR_MSB = ~S186_OUT;
assign S166_OUT = VSHRINK_LINE[3] ^ ~S186_OUT;
assign S164_OUT = VSHRINK_LINE[2] ^ ~S186_OUT;
assign S162_OUT = VSHRINK_LINE[1] ^ ~S186_OUT;
assign S168_OUT = VSHRINK_LINE[0] ^ ~S186_OUT;
FDSCell O227(P222A_OUT, {S166_OUT, S164_OUT, S162_OUT, S168_OUT}, O227_Q);
FDSCell G233(~P201_Q[1], O227_Q, G233_Q);
assign SPR_LINE[0] = SPR_TILE_VFLIP ^ G233_Q[0];
assign SPR_LINE[1] = SPR_TILE_VFLIP ^ G233_Q[1];
assign SPR_LINE[2] = SPR_TILE_VFLIP ^ G233_Q[2];
assign SPR_LINE[3] = SPR_TILE_VFLIP ^ G233_Q[3];
assign Q184_OUT = VSHRINK_INDEX[3] ^ ~S186_OUT;
assign Q182_OUT = VSHRINK_INDEX[2] ^ ~S186_OUT;
assign Q186_OUT = VSHRINK_INDEX[1] ^ ~S186_OUT;
assign Q172_OUT = VSHRINK_INDEX[0] ^ ~S186_OUT;
FDSCell O175(P222A_OUT, {Q184_OUT, Q182_OUT, Q186_OUT, Q172_OUT}, SPR_TILEMAP);
// P bus stuff
// Lookup ROM data latch
FDSCell Q87(VCS, PBUS_IO[23:20], VSHRINK_INDEX);
FDSCell S141(VCS, PBUS_IO[19:16], VSHRINK_LINE);
FDM R88(CLK_24M, R94A_OUT, R88_Q, R88_nQ);
assign VCS = ~R88_nQ;
assign T185B_OUT = PCK1 | PCK2;
// Data select lines
FDM S183(T185B_OUT, S171_Q, S183_Q, );
BD3 P196(S183_Q, S183_Q_DELAYED);
FDM S171(U53_Q, LSPC_1_5M, S171_Q, S171_nQ);
assign XPOS = PIPE_C[8:0];
assign SPR_TILE_AA[2] = AUTOANIM3_EN ? AA_COUNT[2] : SPR_TILE[2];
assign SPR_TILE_AA[1:0] = AUTOANIM2_EN ? AA_COUNT[1:0] : SPR_TILE[1:0];
// Q125 R120
assign XPOS_ROUND_UP = XPOS[8:1] + XPOS[0];
// K143A K145A K147A K149A
// Q111A Q113B Q113A Q111B
assign P_MUX_HIGH = R88_Q ? XPOS[8:1] : YSHRINK;
// R185A R185B R183A R183B
// R277A R277B R275A R275B
assign SPR_LINE_MUX = SPR_CONTINUOUS ? ~SPR_TILE_AB : SPR_TILE_A; // Might be swapped
// R149A R149B R147A R147B
// Q149A Q120A Q121B Q149B
assign P_MUX_LOW = R88_Q ? XPOS_ROUND_UP : SPR_LINE_MUX;
// Output mux
// C250 A238A A232 A234A
// E271 E273A E268A D255
assign P_OUT_MUX[23:16] = ~S183_Q_DELAYED ?
~S171_nQ ?
{SPR_PAL}
:
{SPR_TILE[19:16], SPR_LINE}
:
~S171_nQ ?
{8'b00000000}
:
{4'b0000, FIX_PAL};
// J39A M230A L228A L247A
// C256 B269A B273A B276A
// B220 C248 B217A B215
// B197A B130A B128 B148A
assign P_OUT_MUX[15:0] = ~S183_Q_DELAYED ?
~S171_nQ ?
{P_MUX_HIGH, P_MUX_LOW}
:
{SPR_TILE[15:8], SPR_TILE[7:3], SPR_TILE_AA}
:
~S171_nQ ?
{PIXELC[2], RASTERC[2:1], FLIP, FIX_TILE[11:8], FIX_TILE[7:0]}
:
{8'b00000000, 8'b00000000};
assign PBUS_IO = nPBUS_OUT_EN ? 8'bzzzzzzzz : P_OUT_MUX[23:16];
assign PBUS_OUT = P_OUT_MUX[15:0];
// Y position stuff
// O268 O237
assign SPR_Y_LOOKAHEAD = {RASTERC[7:1], FLIP} + 1'b1;
// P261 P237
assign SPR_Y_ADD = SPR_Y_LOOKAHEAD + SPR_Y[7:0];
// R216 R218 R238 R241
// R281 R283 Q289 Q291
assign SPR_TILE_A = SPR_Y_ADD[7:0] ^ {8{~P235_OUT}};
assign P235_OUT = ~(SPR_Y[8] ^ SPR_Y_ADD[8]);
// Q237 R189
assign SPR_Y_SHRINK = SPR_TILE_A + ~YSHRINK;
// Q265 R151
assign SPR_TILE_AB = SPR_TILE_A + {~YSHRINK[6:0], 1'b0};
// Special #33 height detection
// R222A
assign SPR_CONTINUOUS = &{SPR_SIZE0, SPR_SIZE5, SPR_Y_SHRINK[8]};
lspc_regs REGS(RESET, RESETP, M68K_ADDR, M68K_DATA, LSPOE, LSPWE, VMODE, RASTERC, AA_COUNT, VRAM_LOW_READ,
VRAM_HIGH_READ, WR_VRAM_ADDR, WR_VRAM_RW, WR_TIMER_HIGH, WR_TIMER_LOW, WR_IRQ_ACK, REG_VRAMADDR,
REG_VRAMMOD, REG_VRAMRW, REG_LSPCMODE, CPU_DATA_OUT, AA_SPEED, TIMER_MODE, TIMER_IRQ_EN,
AA_DISABLE, TIMER_STOP, nVRAM_WRITE_REQ, D112B_OUT);
lspc_timer TIMER(LSPC_6M, RESETP, M68K_DATA, WR_TIMER_HIGH, WR_TIMER_LOW, VMODE, TIMER_MODE, TIMER_STOP,
RASTERC, TIMER_IRQ_EN, R74_nQ, BNKB, D46A_OUT);
resetp RSTP(CLK_24MB, RESET, RESETP);
irq IRQ(WR_IRQ_ACK, M68K_DATA[2:0], RESET, D46A_OUT, BNK, LSPC_6M, IPL0, IPL1);
videosync VS(CLK_24MB, LSPC_3M, LSPC_1_5M, Q53_CO, RESETP, VMODE, PIXELC, RASTERC, SYNC, BNK,
BNKB, CHBL, R15_QD, FLIP, nFLIP, P50_CO);
lspc2_clk LSPCCLK(CLK_24M, RESETP, CLK_24MB, LSPC_12M, LSPC_8M, LSPC_6M, LSPC_4M, LSPC_3M, LSPC_1_5M,
Q53_CO);
slow_cycle SCY(CLK_24M, CLK_24MB, LSPC_12M, LSPC_6M, LSPC_3M, LSPC_1_5M, RESETP, VRAM_ADDR[14:0], VRAM_WRITE,
REG_VRAMADDR[15], PIXELC[3], PIXELC[8], RASTERC[7:3], PIXEL_HPLUS, ACTIVE_RD,
nVRAM_WRITE_REQ, SPR_TILEMAP, SPR_TILE_VFLIP, SPR_TILE_HFLIP, SPR_AA_3, SPR_AA_2,
FIX_TILE, FIX_PAL, SPR_TILE, SPR_PAL, VRAM_LOW_READ, nCPU_WR_LOW, R91_nQ,
CLK_CPU_READ_LOW, T160A_OUT, T160B_OUT, CLK_ACTIVE_RD, ACTIVE_RD_PRE8, Q174B_OUT,
D208B_OUT, SPRITEMAP_ADDR_MSB, CLK_SPR_TILE, P222A_OUT, ~P201_Q[1]);
fast_cycle FCY(CLK_24M, LSPC_12M, LSPC_6M, LSPC_3M, LSPC_1_5M, RESETP, nVRAM_WRITE_REQ,
VRAM_ADDR, VRAM_WRITE, REG_VRAMADDR[15], FLIP, nFLIP,
PIXELC, RASTERC, P50_CO, nCPU_WR_HIGH, HSHRINK, PIPE_C, VRAM_HIGH_READ,
ACTIVE_RD, R91_Q, R91_nQ, T140_Q, T58A_OUT, T73A_OUT, U129A_Q, T125A_OUT,
CLK_ACTIVE_RD, ACTIVE_RD_PRE8, SPR_Y, YSHRINK, SPR_SIZE0, SPR_SIZE5, O159_QB);
autoanim AA(RASTERC[8], RESETP, AA_SPEED, AA_COUNT);
hshrink HSH(HSHRINK, CK_HSHRINK_REG, LD_HSHRINK_REG, HSHRINK_OUT_A, HSHRINK_OUT_B);
assign nHSHRINK_OUT_A = ~HSHRINK_OUT_A;
assign nHSHRINK_OUT_B = ~HSHRINK_OUT_B;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_adc (
clk,
// control ports
control,
status,
// FIFO interface
src_adc_enable,
src_adc_valid,
src_adc_data,
dst_adc_enable,
dst_adc_valid,
dst_adc_data
);
localparam RP_ID = 8'hA1;
parameter CHANNEL_ID = 0;
input clk;
input [31:0] control;
output [31:0] status;
input src_adc_enable;
input src_adc_valid;
input [15:0] src_adc_data;
output dst_adc_enable;
output dst_adc_valid;
output [15:0] dst_adc_data;
reg dst_adc_enable;
reg dst_adc_valid;
reg [15:0] dst_adc_data;
reg [31:0] status = 0;
reg [15:0] adc_pn_data = 0;
reg [ 3:0] mode;
reg [ 3:0] channel_sel;
wire adc_dvalid;
wire [15:0] adc_pn_data_s;
wire adc_pn_oos_s;
wire adc_pn_err_s;
// prbs function
function [15:0] pn;
input [15:0] din;
reg [15:0] dout;
begin
dout[15] = din[14] ^ din[15];
dout[14] = din[13] ^ din[14];
dout[13] = din[12] ^ din[13];
dout[12] = din[11] ^ din[12];
dout[11] = din[10] ^ din[11];
dout[10] = din[ 9] ^ din[10];
dout[ 9] = din[ 8] ^ din[ 9];
dout[ 8] = din[ 7] ^ din[ 8];
dout[ 7] = din[ 6] ^ din[ 7];
dout[ 6] = din[ 5] ^ din[ 6];
dout[ 5] = din[ 4] ^ din[ 5];
dout[ 4] = din[ 3] ^ din[ 4];
dout[ 3] = din[ 2] ^ din[ 3];
dout[ 2] = din[ 1] ^ din[ 2];
dout[ 1] = din[ 0] ^ din[ 1];
dout[ 0] = din[14] ^ din[15] ^ din[ 0];
pn = dout;
end
endfunction
assign adc_dvalid = src_adc_enable & src_adc_valid;
always @(posedge clk) begin
channel_sel <= control[3:0];
mode <= control[7:4];
end
// prbs generation
always @(posedge clk) begin
if(adc_dvalid == 1'b1) begin
adc_pn_data <= pn(adc_pn_data_s);
end
end
assign adc_pn_data_s = (adc_pn_oos_s == 1'b1) ? src_adc_ddata : adc_pn_data;
ad_pnmon #(
.DATA_WIDTH(32)
) i_pn_mon (
.adc_clk(clk),
.adc_valid_in(adc_dvalid),
.adc_data_in(src_adc_ddata),
.adc_data_pn(adc_pn_data),
.adc_pn_oos(adc_pn_oos_s),
.adc_pn_err(adc_pn_err_s));
// rx path are passed through on test mode
always @(posedge clk) begin
dst_adc_enable <= src_adc_enable;
dst_adc_data <= src_adc_data;
dst_adc_valid <= src_adc_valid;
end
// setup status bits for gpio_out
always @(posedge clk) begin
if((mode == 3'd2) && (channel_sel == CHANNEL_ID)) begin
status <= {22'h0, adc_pn_err_s, adc_pn_oos_s, RP_ID};
end else begin
status <= {24'h0, RP_ID};
end
end
endmodule
|
module opicorv32_alu (
reg_op2,
reg_op1,
instr,
is,
alu_out,
alu_out_0
);
input [31:0] reg_op2;
input [31:0] reg_op1;
input [47:0] instr;
input [14:0] is;
output [31:0] alu_out;
output alu_out_0;
/* signal declarations */
wire [31:0] _1209;
wire [31:0] _1207;
wire [31:0] _1215;
wire _1172;
wire _1169;
wire _1170;
wire _1178;
wire [30:0] _1158;
wire _1159;
wire _1160;
wire [31:0] _1161;
wire [30:0] _1162;
wire _1163;
wire _1164;
wire [31:0] _1165;
wire _1166;
wire _1167;
wire _1155;
wire _1156;
wire _1176;
wire _1180;
wire [30:0] _1145;
wire _1146;
wire _1147;
wire [31:0] _1148;
wire [30:0] _1149;
wire _1150;
wire _1151;
wire [31:0] _1152;
wire _1153;
wire _1143;
wire _1154;
wire _1174;
wire _1157;
wire _1168;
wire _1177;
wire _1171;
wire _1173;
wire _1179;
wire _1181;
wire _1182;
wire [30:0] _1203 = 31'b0000000000000000000000000000000;
wire [31:0] _1205;
wire [31:0] _1192;
wire [31:0] _1213;
wire [31:0] _1217;
wire [31:0] _1188;
wire [31:0] _1184;
wire _1189;
wire _1190;
wire _1191;
wire [31:0] _1211;
wire _1193;
wire _1194;
wire _1195;
wire _1206;
wire _1214;
wire _1208;
wire _1210;
wire _1216;
wire _1218;
wire [31:0] _1219;
/* logic */
assign _1209 = reg_op1 + reg_op2;
assign _1207 = reg_op1 - reg_op2;
assign _1215 = _1210 ? _1209 : _1207;
assign _1172 = reg_op1 == reg_op2;
assign _1169 = reg_op1 == reg_op2;
assign _1170 = ~ _1169;
assign _1178 = _1173 ? _1172 : _1170;
assign _1158 = reg_op2[30:0];
assign _1159 = reg_op2[31:31];
assign _1160 = ~ _1159;
assign _1161 = { _1160, _1158 };
assign _1162 = reg_op1[30:0];
assign _1163 = reg_op1[31:31];
assign _1164 = ~ _1163;
assign _1165 = { _1164, _1162 };
assign _1166 = _1165 < _1161;
assign _1167 = ~ _1166;
assign _1155 = reg_op1 < reg_op2;
assign _1156 = ~ _1155;
assign _1176 = _1168 ? _1167 : _1156;
assign _1180 = _1179 ? _1178 : _1176;
assign _1145 = reg_op2[30:0];
assign _1146 = reg_op2[31:31];
assign _1147 = ~ _1146;
assign _1148 = { _1147, _1145 };
assign _1149 = reg_op1[30:0];
assign _1150 = reg_op1[31:31];
assign _1151 = ~ _1150;
assign _1152 = { _1151, _1149 };
assign _1153 = _1152 < _1148;
assign _1143 = reg_op1 < reg_op2;
assign _1154 = is[7:7];
assign _1174 = _1154 ? _1153 : _1143;
assign _1157 = instr[9:9];
assign _1168 = instr[7:7];
assign _1177 = _1168 | _1157;
assign _1171 = instr[5:5];
assign _1173 = instr[4:4];
assign _1179 = _1173 | _1171;
assign _1181 = _1179 | _1177;
assign _1182 = _1181 ? _1180 : _1174;
assign _1205 = { _1203, _1182 };
assign _1192 = reg_op1 ^ reg_op2;
assign _1213 = _1206 ? _1205 : _1192;
assign _1217 = _1216 ? _1215 : _1213;
assign _1188 = reg_op1 | reg_op2;
assign _1184 = reg_op1 & reg_op2;
assign _1189 = instr[35:35];
assign _1190 = instr[22:22];
assign _1191 = _1190 | _1189;
assign _1211 = _1191 ? _1188 : _1184;
assign _1193 = instr[32:32];
assign _1194 = instr[21:21];
assign _1195 = _1194 | _1193;
assign _1206 = is[13:13];
assign _1214 = _1206 | _1195;
assign _1208 = instr[28:28];
assign _1210 = is[6:6];
assign _1216 = _1210 | _1208;
assign _1218 = _1216 | _1214;
assign _1219 = _1218 ? _1217 : _1211;
/* aliases */
/* output assignments */
assign alu_out = _1219;
assign alu_out_0 = _1182;
endmodule
|
// -------------------------------------------------------------
//
// File Name: moore_rtl\Stateflow_Moore_example\Moore_Chart.v
//
// Generated by MATLAB 8.3 and HDL Coder 3.4
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Moore_Chart
// Source Path: Stateflow_Moore_example/Moore_Subsystem/Moore_Chart
// Hierarchy Level: 1
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Moore_Chart
(
clk,
rst_n,
enb,
a,
b
);
input clk;
input rst_n;
input enb;
output [63:0] a; // double
output [63:0] b; // double
parameter IN_FINAL = 3'd0, IN_IDLE = 3'd1, IN_INITIAL = 3'd2, IN_SEQ1 = 3'd3, IN_SEQ2 = 3'd4;
reg [2:0] is_Moore_Chart; // uint8
real a_1; // double
real b_1; // double
real a_reg; // double
real b_reg; // double
reg [2:0] is_Moore_Chart_next; // enum type state_type_is_Moore_Chart (5 enums)
real a_reg_next; // double
real b_reg_next; // double
always @(posedge clk or negedge rst_n)
begin : Moore_Chart_1_process
if (rst_n == 1'b0) begin
is_Moore_Chart <= IN_INITIAL;
end
else begin
if (enb) begin
is_Moore_Chart <= is_Moore_Chart_next;
a_reg <= a_reg_next;
b_reg <= b_reg_next;
end
end
end
always @* begin
is_Moore_Chart_next = is_Moore_Chart;
a_reg_next = a_reg;
b_reg_next = b_reg;
case ( is_Moore_Chart)
IN_FINAL :
begin
end
IN_IDLE :
begin
a_reg_next = 0.0;
end
IN_INITIAL :
begin
a_reg_next = 0.0;
b_reg_next = 0.0;
end
IN_SEQ1 :
begin
a_reg_next = 1.0;
b_reg_next = b_reg + 1.0;
end
endcase
case ( is_Moore_Chart)
IN_FINAL :
begin
is_Moore_Chart_next = IN_IDLE;
end
IN_IDLE :
begin
is_Moore_Chart_next = IN_SEQ1;
end
IN_INITIAL :
begin
is_Moore_Chart_next = IN_IDLE;
end
IN_SEQ1 :
begin
is_Moore_Chart_next = IN_SEQ2;
end
default :
begin
is_Moore_Chart_next = IN_FINAL;
end
endcase
end
always @* a_1 = a_reg_next;
always @* b_1 = b_reg_next;
assign a = $realtobits(a_1);
assign b = $realtobits(b_1);
endmodule // Moore_Chart
|
module rx #(
parameter STATE_IDLE = 3'h0,
parameter STATE_PREAMBLE = 3'h1,
parameter STATE_DATA = 3'h2,
parameter STATE_OK = 3'h3,
parameter STATE_DROP = 3'h4,
parameter STATE_ERROR = 3'h5
)(
input reset,
input clock,
input rx_data_valid,
input [7:0] rx_data,
input rx_error,
output reg [7:0] data_out,
output reg data_out_enable,
output reg data_out_start,
output reg data_out_end,
input wire fifo_full,
output reg error
);
localparam CRC_RESIDUE = 32'hC704DD7B;
localparam CRC_POLYNOMIAL = 32'h04C11DB7;
localparam CRC_SEED = 32'hFFFFFFFF;
localparam MAX_SIZE = 1518;
localparam MIN_SIZE = 64;
reg [2:0] state;
reg [2:0] next_state;
reg [15:0] frame_length_counter;
reg [15:0] data_counter;
reg too_long;
reg too_short;
reg crc_init;
reg data_enable;
wire [31:0] crc_out;
reg [39:0] data;
// RX State Machine
always @ (posedge clock)
if (reset)
state <= STATE_IDLE;
else
state <= next_state;
always @ (*)
case (state)
STATE_IDLE:
if (rx_data_valid && rx_data == 8'h55)
next_state = STATE_PREAMBLE;
else
next_state = STATE_IDLE;
STATE_PREAMBLE:
if (!rx_data_valid)
next_state = STATE_ERROR;
else if (rx_error)
next_state = STATE_DROP;
else if (rx_data == 8'hd5)
next_state = STATE_DATA;
else if (rx_data == 8'h55)
next_state = STATE_PREAMBLE;
else
next_state = STATE_DROP;
STATE_DATA:
if (!rx_data_valid && !too_short && !too_long && crc_out == CRC_RESIDUE)
next_state = STATE_OK;
else if ((!rx_data_valid && (too_short || too_long)) || (!rx_data_valid && crc_out != CRC_RESIDUE))
next_state = STATE_ERROR;
else if (fifo_full)
next_state = STATE_DROP;
else if (rx_error || too_long)
next_state = STATE_DROP;
else
next_state = STATE_DATA;
STATE_DROP:
if (!rx_data_valid)
next_state = STATE_ERROR;
else
next_state = STATE_DROP;
STATE_OK:
next_state = STATE_IDLE;
STATE_ERROR:
next_state = STATE_IDLE;
default:
next_state = STATE_IDLE;
endcase
always @(posedge clock)
data_out <= data[39-:8];
always @(posedge clock)
begin
if (reset)
begin
data <= 32'h00000000;
end
else if (state == STATE_IDLE)
begin
data <= 32'h00000000;
end
else
begin
data[39-:8] <= data[31-:8];
data[31-:8] <= data[23-:8];
data[23-:8] <= data[15-:8];
data[15-:8] <= data[7-:8];
data[7-:8] <= rx_data;
end
end
always @ (posedge clock)
if (reset)
data_counter <= 0;
else if (state == STATE_DATA)
data_counter = data_counter + 1;
else
data_counter = 0;
always @ (*)
if (data_counter > 5 && (state == STATE_DATA || state == STATE_OK || state == STATE_ERROR))
data_out_enable = 1;
else
data_out_enable = 0;
always @(*)
if (data_counter == 6)
data_out_start = 1;
else
data_out_start = 0;
always @(*)
if (state == STATE_OK || state == STATE_ERROR)
data_out_end = 1;
else
data_out_end = 0;
always @(*)
if (state == STATE_ERROR)
error = 1;
else
error = 0;
// CRC Interface
always @(*)
if (state == STATE_DATA)
data_enable = 1;
else
data_enable = 0;
always @(*)
if (state == STATE_PREAMBLE && next_state == STATE_DATA)
crc_init = 1;
else
crc_init = 0;
always @ (posedge clock)
if (reset)
frame_length_counter <= 0;
else if (state == STATE_DATA)
frame_length_counter = frame_length_counter + 1;
else
frame_length_counter = 0;
always @ (*)
if (frame_length_counter < MIN_SIZE)
too_short = 1;
else
too_short = 0;
always @ (*)
if (frame_length_counter > MAX_SIZE)
too_long = 1;
else
too_long = 0;
// CRC
crc #( .POLYNOMIAL(CRC_POLYNOMIAL),
.DATA_WIDTH(8),
.CRC_WIDTH(32),
.SEED(CRC_SEED))
U_crc(
.reset(reset),
.clock(clock),
.init(crc_init),
.data(rx_data),
.data_enable(data_enable),
.crc_out(crc_out)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__TAP_PP_SYMBOL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__tap (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAP_PP_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2016 by Andrew Bardsley.
// bug1071
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [3:0] array_1 [2:0];
reg [3:0] array_2 [2:0];
reg [3:0] array_3 [3:1];
reg [3:0] elem;
reg array_1_ne_array_2;
reg array_1_eq_array_2;
reg array_1_ne_array_3;
reg array_1_eq_array_3;
initial begin
array_1[0] = 4'b1000;
array_1[1] = 4'b1000;
array_1[2] = 4'b1000;
array_2[0] = 4'b1000;
array_2[1] = 4'b1000;
array_2[2] = 4'b1000;
array_3[1] = 4'b1000;
array_3[2] = 4'b0100;
array_3[3] = 4'b0100;
array_1_ne_array_2 = array_1 != array_2; // 0
array_1_eq_array_2 = array_1 == array_2; // 0
array_1_ne_array_3 = array_1 != array_3; // 1
array_1_eq_array_3 = array_1 == array_3; // 1
//Not legal: array_rxor = ^ array_1;
//Not legal: array_rxnor = ^~ array_1;
//Not legal: array_ror = | array_1;
//Not legal: array_rand = & array_1;
`ifdef TEST_VERBOSE
$write("array_1_ne_array2==%0d\n", array_1_ne_array_2);
$write("array_1_ne_array3==%0d\n", array_1_ne_array_3);
`endif
if (array_1_ne_array_2 !== 0) $stop;
if (array_1_eq_array_2 !== 1) $stop;
if (array_1_ne_array_3 !== 1) $stop;
if (array_1_eq_array_3 !== 0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AXI4Lite Upizer
// Converts 32-bit AXI4Lite on Slave Interface to 64-bit AXI4Lite on Master Interface.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi4lite_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_9_axi4lite_upsizer #
(
parameter C_FAMILY = "none",
// FPGA Family.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI.
// Range 3 - 64.
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1
)
(
// Global Signals
input wire aresetn,
input wire aclk,
// Slave Interface Write Address Ports
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [3-1:0] s_axi_awprot,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [32-1:0] s_axi_wdata,
input wire [32/8-1:0] s_axi_wstrb,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [2-1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [3-1:0] s_axi_arprot,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [32-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [3-1:0] m_axi_awprot,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [64-1:0] m_axi_wdata,
output wire [64/8-1:0] m_axi_wstrb,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [2-1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [3-1:0] m_axi_arprot,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [64-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rvalid,
output wire m_axi_rready
);
reg s_axi_arready_i ;
reg m_axi_arvalid_i ;
reg m_axi_rready_i ;
reg s_axi_rvalid_i ;
reg ar_done ;
reg araddr2 ;
reg s_axi_awready_i ;
reg s_axi_bvalid_i ;
reg m_axi_awvalid_i ;
reg m_axi_wvalid_i ;
reg m_axi_bready_i ;
reg aw_done ;
reg w_done ;
generate
if (C_AXI_SUPPORTS_READ != 0) begin : gen_read
always @(posedge aclk) begin
if (~aresetn) begin
s_axi_arready_i <= 1'b0 ;
m_axi_arvalid_i <= 1'b0 ;
s_axi_rvalid_i <= 1'b0;
m_axi_rready_i <= 1'b1;
ar_done <= 1'b0 ;
araddr2 <= 1'b0 ;
end else begin
s_axi_arready_i <= 1'b0 ; // end single-cycle pulse
m_axi_rready_i <= 1'b0; // end single-cycle pulse
if (s_axi_rvalid_i) begin
if (s_axi_rready) begin
s_axi_rvalid_i <= 1'b0;
m_axi_rready_i <= 1'b1; // begin single-cycle pulse
ar_done <= 1'b0;
end
end else if (m_axi_rvalid & ar_done) begin
s_axi_rvalid_i <= 1'b1;
end else if (m_axi_arvalid_i) begin
if (m_axi_arready) begin
m_axi_arvalid_i <= 1'b0;
s_axi_arready_i <= 1'b1 ; // begin single-cycle pulse
araddr2 <= s_axi_araddr[2];
ar_done <= 1'b1;
end
end else if (s_axi_arvalid & ~ar_done) begin
m_axi_arvalid_i <= 1'b1;
end
end
end
assign m_axi_arvalid = m_axi_arvalid_i ;
assign s_axi_arready = s_axi_arready_i ;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arprot = s_axi_arprot;
assign s_axi_rvalid = s_axi_rvalid_i ;
assign m_axi_rready = m_axi_rready_i ;
assign s_axi_rdata = araddr2 ? m_axi_rdata[63:32] : m_axi_rdata[31:0];
assign s_axi_rresp = m_axi_rresp;
end else begin : gen_noread
assign m_axi_arvalid = 1'b0 ;
assign s_axi_arready = 1'b0 ;
assign m_axi_araddr = {C_AXI_ADDR_WIDTH{1'b0}} ;
assign m_axi_arprot = 3'b0 ;
assign s_axi_rvalid = 1'b0 ;
assign m_axi_rready = 1'b0 ;
assign s_axi_rresp = 2'b0 ;
assign s_axi_rdata = 32'b0 ;
end
if (C_AXI_SUPPORTS_WRITE != 0) begin : gen_write
always @(posedge aclk) begin
if (~aresetn) begin
m_axi_awvalid_i <= 1'b0 ;
s_axi_awready_i <= 1'b0 ;
m_axi_wvalid_i <= 1'b0 ;
s_axi_bvalid_i <= 1'b0 ;
m_axi_bready_i <= 1'b0 ;
aw_done <= 1'b0 ;
w_done <= 1'b0 ;
end else begin
m_axi_bready_i <= 1'b0; // end single-cycle pulse
if (s_axi_bvalid_i) begin
if (s_axi_bready) begin
s_axi_bvalid_i <= 1'b0;
m_axi_bready_i <= 1'b1; // begin single-cycle pulse
aw_done <= 1'b0;
w_done <= 1'b0;
end
end else if (s_axi_awready_i) begin
s_axi_awready_i <= 1'b0; // end single-cycle pulse
s_axi_bvalid_i <= 1'b1;
end else if (aw_done & w_done) begin
if (m_axi_bvalid) begin
s_axi_awready_i <= 1'b1; // begin single-cycle pulse
end
end else begin
if (m_axi_awvalid_i) begin
if (m_axi_awready) begin
m_axi_awvalid_i <= 1'b0;
aw_done <= 1'b1;
end
end else if (s_axi_awvalid & ~aw_done) begin
m_axi_awvalid_i <= 1'b1;
end
if (m_axi_wvalid_i) begin
if (m_axi_wready) begin
m_axi_wvalid_i <= 1'b0;
w_done <= 1'b1;
end
end else if (s_axi_wvalid & (m_axi_awvalid_i | aw_done) & ~w_done) begin
m_axi_wvalid_i <= 1'b1;
end
end
end
end
assign m_axi_awvalid = m_axi_awvalid_i ;
assign s_axi_awready = s_axi_awready_i ;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_wvalid = m_axi_wvalid_i ;
assign s_axi_wready = s_axi_awready_i ;
assign m_axi_wdata = {s_axi_wdata,s_axi_wdata};
assign m_axi_wstrb = s_axi_awaddr[2] ? {s_axi_wstrb, 4'b0} : {4'b0, s_axi_wstrb};
assign s_axi_bvalid = s_axi_bvalid_i ;
assign m_axi_bready = m_axi_bready_i ;
assign s_axi_bresp = m_axi_bresp;
end else begin : gen_nowrite
assign m_axi_awvalid = 1'b0 ;
assign s_axi_awready = 1'b0 ;
assign m_axi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}} ;
assign m_axi_awprot = 3'b0 ;
assign m_axi_wvalid = 1'b0 ;
assign s_axi_wready = 1'b0 ;
assign m_axi_wdata = 64'b0 ;
assign m_axi_wstrb = 8'b0 ;
assign s_axi_bvalid = 1'b0 ;
assign m_axi_bready = 1'b0 ;
assign s_axi_bresp = 2'b0 ;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_TB_V
`define SKY130_FD_SC_HD__TAPVPWRVGND_TB_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__tapvpwrvgnd.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hd__tapvpwrvgnd dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVPWRVGND_TB_V
|
`timescale 1ns / 1ps
// pwm_ctl.v ver 1.0
// Kazushi Yamashina
// [email protected]
//
// para_in <= 0 ~ 19999
// -Interval of asserting "en_out" will change
// depending on the value of the "para_in".
// -The more you increase the value the interval will increase.
//
// dir_in <= 1: positive rotate, 0: negative rotate
module pwm_ctl(
input clk,
input rst,
input [14:0] para_in,
input [0:0] dir_in,
output [0:0] dir_out,
output [0:0] en_out
);
// //copy this instance to top module
//pwm_ctl pwm_ctl
//(
//.clk(bus_clk),
// .rst(rst),
// .para_in(para_in),
// .dir_out(dir_out),
// .en_out(en_out)
//);
parameter MAX = 19999;
reg dir;
reg dir_;
reg en;
reg [14:0] in_;
reg [31:0] counter;
wire [31:0] divflag;
reg [31:0] PWMctl_clk;
initial PWMctl_clk = MAX;
initial in_ = MAX;
assign divflag = PWMctl_clk - in_;
assign dir_out = dir;
assign en_out = en;
always @(posedge clk)begin
if(rst)begin
in_ <= 19999;
dir_ <= 0;
end
else if(0 < para_in && para_in < PWMctl_clk)begin
in_ <= para_in;
dir_ <= dir_in;
end
else
in_ <= MAX;
end
always @(posedge clk)begin
if(rst)begin
dir <= 0;
en <= 0;
end
else if(divflag > counter)begin
dir <= dir_;
en <= 1;
end
else begin
en <= 0;
end
end
always @(posedge clk)begin
if(rst)begin
counter <= 0;
end
else if(PWMctl_clk == counter)
counter <= 0;
else
counter <= counter + 1;
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:19:42 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23,
n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37,
n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51,
n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65,
n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79,
n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93,
n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116,
n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127,
n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138,
n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149,
n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160,
n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171,
n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182,
n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193,
n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204,
n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, n215,
n216, n217, n218, n219, n220, n221, n222, n223, n224, n225, n226,
n227, n228, n229, n230, n231, n232, n233, n234, n235, n236, n237,
n238, n239, n240, n241, n242, n243, n244, n245, n246, n247, n248,
n249, n250, n251, n252, n253, n254, n255, n256, n257, n258, n259,
n260, n261, n262, n263, n264, n265, n266, n267, n268, n269, n270,
n271, n272, n273, n274, n275, n276, n277, n278, n279, n280, n281,
n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, n292,
n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303,
n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314,
n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325,
n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336,
n337, n338;
XNOR2X1TS U44 ( .A(n226), .B(n225), .Y(res[26]) );
XOR2X1TS U45 ( .A(n255), .B(n254), .Y(res[22]) );
NAND2X1TS U46 ( .A(n76), .B(n220), .Y(n221) );
NAND2XLTS U47 ( .A(n80), .B(n274), .Y(n275) );
AND3X1TS U48 ( .A(n33), .B(n274), .C(n32), .Y(n18) );
NAND2X4TS U49 ( .A(n73), .B(n193), .Y(n200) );
NAND2XLTS U50 ( .A(n79), .B(n202), .Y(n203) );
NAND2X1TS U51 ( .A(n213), .B(n212), .Y(n214) );
NAND2XLTS U52 ( .A(n257), .B(n256), .Y(n258) );
NAND2X1TS U53 ( .A(n229), .B(n228), .Y(n230) );
NAND2X1TS U54 ( .A(n246), .B(n245), .Y(n247) );
NAND2X1TS U55 ( .A(n205), .B(n204), .Y(n206) );
NAND2XLTS U56 ( .A(n263), .B(n262), .Y(n264) );
NAND2XLTS U57 ( .A(n239), .B(n238), .Y(n240) );
CLKAND2X2TS U58 ( .A(n74), .B(n199), .Y(n75) );
OAI21X2TS U59 ( .A0(n231), .A1(n210), .B0(n209), .Y(n215) );
OAI21X2TS U60 ( .A0(n231), .A1(n219), .B0(n218), .Y(n222) );
OAI21X1TS U61 ( .A0(n270), .A1(n266), .B0(n267), .Y(n265) );
NAND2X1TS U62 ( .A(n253), .B(n252), .Y(n254) );
CLKINVX2TS U63 ( .A(n251), .Y(n253) );
INVX4TS U64 ( .A(n208), .Y(n231) );
OAI21X1TS U65 ( .A0(n234), .A1(n244), .B0(n245), .Y(n235) );
CLKMX2X4TS U66 ( .A(in2[31]), .B(n197), .S0(n196), .Y(n198) );
NAND2X2TS U67 ( .A(n189), .B(in1[29]), .Y(n204) );
CLKMX2X2TS U68 ( .A(in2[30]), .B(n186), .S0(n196), .Y(n190) );
CLKMX2X2TS U69 ( .A(in2[29]), .B(n188), .S0(n196), .Y(n189) );
OR2X2TS U70 ( .A(n195), .B(in2[30]), .Y(n19) );
OAI21X2TS U71 ( .A0(n245), .A1(n237), .B0(n238), .Y(n162) );
NAND2X1TS U72 ( .A(n141), .B(in1[20]), .Y(n262) );
NAND2X2TS U73 ( .A(n177), .B(in1[25]), .Y(n228) );
NAND2X2TS U74 ( .A(n160), .B(in1[23]), .Y(n245) );
NAND2X1TS U75 ( .A(n161), .B(in1[24]), .Y(n238) );
NAND2X2TS U76 ( .A(n180), .B(in1[27]), .Y(n220) );
NOR2X4TS U77 ( .A(n160), .B(in1[23]), .Y(n244) );
XNOR2X1TS U78 ( .A(n154), .B(in2[20]), .Y(n138) );
MXI2X2TS U79 ( .A(n131), .B(n130), .S0(n317), .Y(n132) );
CLKMX2X3TS U80 ( .A(in2[21]), .B(n152), .S0(n196), .Y(n158) );
NOR2X4TS U81 ( .A(n178), .B(in1[26]), .Y(n179) );
NAND2X4TS U82 ( .A(n274), .B(n32), .Y(n16) );
NOR2X2TS U83 ( .A(n133), .B(in2[18]), .Y(n134) );
XNOR2X1TS U84 ( .A(n133), .B(in2[18]), .Y(n130) );
NAND2X2TS U85 ( .A(n148), .B(n137), .Y(n133) );
INVX2TS U86 ( .A(n280), .Y(n12) );
OR2X1TS U87 ( .A(n175), .B(in2[27]), .Y(n184) );
NOR2X2TS U88 ( .A(n154), .B(in2[20]), .Y(n151) );
NAND2XLTS U89 ( .A(n173), .B(n172), .Y(n175) );
NAND2X2TS U90 ( .A(n126), .B(in1[16]), .Y(n276) );
NAND2X1TS U91 ( .A(n107), .B(in1[12]), .Y(n294) );
NAND2X1TS U92 ( .A(n51), .B(in2[17]), .Y(n58) );
INVX2TS U93 ( .A(in2[26]), .Y(n172) );
NAND2X6TS U94 ( .A(n148), .B(n147), .Y(n185) );
INVX4TS U95 ( .A(n300), .Y(n13) );
NAND2X2TS U96 ( .A(n118), .B(n108), .Y(n109) );
NAND2X2TS U97 ( .A(n94), .B(in1[9]), .Y(n305) );
NAND2X6TS U98 ( .A(n99), .B(in1[10]), .Y(n301) );
NAND2X2TS U99 ( .A(n137), .B(n136), .Y(n146) );
OR2X2TS U100 ( .A(in2[21]), .B(in2[20]), .Y(n153) );
NOR2X1TS U101 ( .A(in2[19]), .B(in2[18]), .Y(n136) );
NAND2X6TS U102 ( .A(n86), .B(n85), .Y(n21) );
BUFX6TS U103 ( .A(add_sub), .Y(n196) );
OR2X4TS U104 ( .A(n335), .B(n83), .Y(n86) );
INVX8TS U105 ( .A(in2[10]), .Y(n104) );
CLKINVX6TS U106 ( .A(in2[6]), .Y(n64) );
INVX12TS U107 ( .A(in2[5]), .Y(n313) );
INVX2TS U108 ( .A(in2[11]), .Y(n35) );
OAI21X2TS U109 ( .A0(in2[7]), .A1(n336), .B0(in1[7]), .Y(n82) );
CLKINVX6TS U110 ( .A(in2[7]), .Y(n63) );
NAND2X4TS U111 ( .A(n64), .B(n63), .Y(n62) );
NOR3X2TS U112 ( .A(n154), .B(in2[22]), .C(n153), .Y(n144) );
INVX12TS U113 ( .A(in2[4]), .Y(n312) );
CLKMX2X4TS U114 ( .A(in2[13]), .B(n110), .S0(add_sub), .Y(n112) );
CLKMX2X2TS U115 ( .A(in2[28]), .B(n176), .S0(n196), .Y(n182) );
NAND2X1TS U116 ( .A(n182), .B(in1[28]), .Y(n212) );
OAI21XLTS U117 ( .A0(n302), .A1(n300), .B0(n301), .Y(n298) );
NAND2X1TS U118 ( .A(n268), .B(n267), .Y(n269) );
NAND2X1TS U119 ( .A(n224), .B(n223), .Y(n225) );
NAND2X2TS U120 ( .A(n113), .B(in1[14]), .Y(n10) );
AND2X4TS U121 ( .A(n40), .B(n294), .Y(n11) );
NAND2X2TS U122 ( .A(n129), .B(in1[17]), .Y(n274) );
NAND2X4TS U123 ( .A(n216), .B(n76), .Y(n210) );
NAND2X1TS U124 ( .A(n23), .B(n276), .Y(n278) );
NAND2X1TS U125 ( .A(n14), .B(n294), .Y(n296) );
INVX8TS U126 ( .A(in2[8]), .Y(n97) );
OR2X6TS U127 ( .A(n164), .B(n67), .Y(n72) );
NOR2X6TS U128 ( .A(n210), .B(n211), .Y(n183) );
CLKINVX6TS U129 ( .A(n165), .Y(n65) );
NOR2X6TS U130 ( .A(n244), .B(n237), .Y(n163) );
INVX2TS U131 ( .A(n220), .Y(n181) );
OR2X6TS U132 ( .A(n180), .B(in1[27]), .Y(n76) );
MXI2X4TS U133 ( .A(n150), .B(n149), .S0(n317), .Y(n161) );
XOR2X2TS U134 ( .A(n15), .B(in2[28]), .Y(n176) );
XOR2X2TS U135 ( .A(n166), .B(in2[25]), .Y(n168) );
OR2X4TS U136 ( .A(n185), .B(n184), .Y(n15) );
OR2X2TS U137 ( .A(n185), .B(n175), .Y(n20) );
NOR2X4TS U138 ( .A(n185), .B(in2[24]), .Y(n166) );
NAND2X6TS U139 ( .A(n80), .B(n54), .Y(n32) );
NAND2X2TS U140 ( .A(n79), .B(n205), .Y(n194) );
NAND2X4TS U141 ( .A(n44), .B(n43), .Y(n42) );
NAND2X4TS U142 ( .A(n140), .B(in1[19]), .Y(n267) );
NOR2X4TS U143 ( .A(n182), .B(in1[28]), .Y(n211) );
INVX2TS U144 ( .A(n237), .Y(n239) );
OR2X4TS U145 ( .A(n132), .B(in1[18]), .Y(n27) );
NAND2X4TS U146 ( .A(n56), .B(n23), .Y(n55) );
NAND2BX2TS U147 ( .AN(in2[29]), .B(n187), .Y(n195) );
XNOR2X2TS U148 ( .A(n151), .B(in2[21]), .Y(n152) );
NOR3X4TS U149 ( .A(n185), .B(in2[28]), .C(n184), .Y(n187) );
NAND2X4TS U150 ( .A(n13), .B(n77), .Y(n45) );
NAND2X6TS U151 ( .A(n48), .B(n47), .Y(n77) );
NOR2X4TS U152 ( .A(n107), .B(in1[12]), .Y(n293) );
AND2X4TS U153 ( .A(n91), .B(n97), .Y(n61) );
BUFX16TS U154 ( .A(add_sub), .Y(n317) );
NOR2X4TS U155 ( .A(in2[13]), .B(in2[12]), .Y(n117) );
INVX2TS U156 ( .A(in2[25]), .Y(n167) );
NOR2X2TS U157 ( .A(n266), .B(n261), .Y(n143) );
OR2X4TS U158 ( .A(n190), .B(in1[30]), .Y(n79) );
INVX2TS U159 ( .A(n244), .Y(n246) );
NAND2X4TS U160 ( .A(n158), .B(in1[21]), .Y(n256) );
NOR2X4TS U161 ( .A(n158), .B(in1[21]), .Y(n249) );
NAND2X4TS U162 ( .A(n59), .B(n58), .Y(n129) );
NAND2X6TS U163 ( .A(n276), .B(n55), .Y(n54) );
INVX6TS U164 ( .A(n302), .Y(n43) );
NAND2X4TS U165 ( .A(n12), .B(n23), .Y(n57) );
CLKINVX6TS U166 ( .A(n301), .Y(n50) );
NOR2X6TS U167 ( .A(n88), .B(in1[8]), .Y(n307) );
NAND2X4TS U168 ( .A(n88), .B(in1[8]), .Y(n308) );
MXI2X4TS U169 ( .A(n108), .B(n106), .S0(n317), .Y(n107) );
INVX8TS U170 ( .A(n21), .Y(n88) );
NAND2X6TS U171 ( .A(n96), .B(n97), .Y(n103) );
XNOR2X1TS U172 ( .A(n265), .B(n264), .Y(res[20]) );
XOR2X1TS U173 ( .A(n279), .B(n282), .Y(res[15]) );
XOR2X1TS U174 ( .A(n272), .B(n18), .Y(res[18]) );
OAI21X1TS U175 ( .A0(n279), .A1(n57), .B0(n53), .Y(n273) );
OAI21X1TS U176 ( .A0(n279), .A1(n280), .B0(n281), .Y(n277) );
XOR2X1TS U177 ( .A(n292), .B(n291), .Y(res[13]) );
OAI21X1TS U178 ( .A0(n292), .A1(n288), .B0(n289), .Y(n287) );
NAND2X2TS U179 ( .A(n198), .B(in1[31]), .Y(n199) );
NAND2X2TS U180 ( .A(n190), .B(in1[30]), .Y(n202) );
XOR2X1TS U181 ( .A(n296), .B(n295), .Y(res[12]) );
NOR2X4TS U182 ( .A(n177), .B(in1[25]), .Y(n227) );
NOR2X1TS U183 ( .A(n302), .B(n45), .Y(n39) );
MXI2X4TS U184 ( .A(n168), .B(n167), .S0(n51), .Y(n177) );
XOR2X1TS U185 ( .A(n303), .B(n302), .Y(res[10]) );
NAND2X4TS U186 ( .A(n60), .B(add_sub), .Y(n59) );
NAND2X2TS U187 ( .A(n132), .B(in1[18]), .Y(n271) );
NAND2X6TS U188 ( .A(n49), .B(n297), .Y(n41) );
XNOR2X2TS U189 ( .A(n144), .B(in2[23]), .Y(n145) );
INVX4TS U190 ( .A(n293), .Y(n14) );
NAND2BXLTS U191 ( .AN(in1[6]), .B(n334), .Y(res[6]) );
NAND2BXLTS U192 ( .AN(in1[7]), .B(n326), .Y(res[7]) );
NAND2BXLTS U193 ( .AN(in1[5]), .B(n316), .Y(res[5]) );
NAND2BXLTS U194 ( .AN(in1[4]), .B(n338), .Y(res[4]) );
NAND2BXLTS U195 ( .AN(in1[3]), .B(n322), .Y(res[3]) );
NAND2BXLTS U196 ( .AN(in1[2]), .B(n329), .Y(res[2]) );
NAND2BXLTS U197 ( .AN(in1[1]), .B(n319), .Y(res[1]) );
NOR4X2TS U198 ( .A(n146), .B(n153), .C(in2[23]), .D(in2[22]), .Y(n147) );
NOR2X6TS U199 ( .A(n320), .B(in2[3]), .Y(n335) );
INVX4TS U200 ( .A(n196), .Y(n51) );
OR2X1TS U201 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
BUFX16TS U202 ( .A(add_sub), .Y(n336) );
NOR2X2TS U203 ( .A(in2[25]), .B(in2[24]), .Y(n173) );
MXI2X4TS U204 ( .A(n97), .B(n87), .S0(n317), .Y(n310) );
XNOR2X2TS U205 ( .A(n105), .B(in2[8]), .Y(n87) );
NOR2X4TS U206 ( .A(n127), .B(in2[16]), .Y(n128) );
NOR2X6TS U207 ( .A(n227), .B(n179), .Y(n216) );
NAND2X2TS U208 ( .A(n169), .B(n173), .Y(n170) );
OR2X4TS U209 ( .A(n94), .B(in1[9]), .Y(n78) );
XNOR2X2TS U210 ( .A(n92), .B(in2[9]), .Y(n93) );
NOR2X6TS U211 ( .A(n113), .B(in1[14]), .Y(n284) );
NOR2X2TS U212 ( .A(n288), .B(n284), .Y(n115) );
XOR2X2TS U213 ( .A(n119), .B(in2[15]), .Y(n120) );
NAND2X4TS U214 ( .A(n121), .B(in1[15]), .Y(n281) );
NOR2X6TS U215 ( .A(n249), .B(n251), .Y(n243) );
XOR2X2TS U216 ( .A(n20), .B(in2[27]), .Y(n174) );
NAND2X8TS U217 ( .A(n11), .B(n42), .Y(n283) );
NAND2X2TS U218 ( .A(n327), .B(n81), .Y(n320) );
NAND2X8TS U219 ( .A(n17), .B(n33), .Y(n31) );
INVX6TS U220 ( .A(n16), .Y(n17) );
NOR2X4TS U221 ( .A(n99), .B(in1[10]), .Y(n300) );
XNOR2X4TS U222 ( .A(n128), .B(in2[17]), .Y(n60) );
NAND2X4TS U223 ( .A(n41), .B(n14), .Y(n40) );
XOR2X1TS U224 ( .A(n19), .B(in2[31]), .Y(n197) );
NAND2X8TS U225 ( .A(n31), .B(n27), .Y(n30) );
MX2X4TS U226 ( .A(in2[15]), .B(n120), .S0(n196), .Y(n121) );
INVX2TS U227 ( .A(n281), .Y(n56) );
XNOR2X2TS U228 ( .A(n222), .B(n221), .Y(res[27]) );
NAND2BX4TS U229 ( .AN(n146), .B(n148), .Y(n154) );
NOR2X8TS U230 ( .A(in2[3]), .B(in2[2]), .Y(n91) );
MX2X4TS U231 ( .A(in2[23]), .B(n145), .S0(n196), .Y(n160) );
XOR2X4TS U232 ( .A(n109), .B(in2[13]), .Y(n110) );
NAND2X4TS U233 ( .A(n36), .B(n26), .Y(n34) );
OAI21X4TS U234 ( .A0(n267), .A1(n261), .B0(n262), .Y(n142) );
MX2X4TS U235 ( .A(in2[27]), .B(n174), .S0(n196), .Y(n180) );
OAI21X4TS U236 ( .A0(n231), .A1(n227), .B0(n228), .Y(n226) );
NAND2X8TS U237 ( .A(n30), .B(n271), .Y(n260) );
MXI2X4TS U238 ( .A(n116), .B(n111), .S0(n336), .Y(n113) );
OA21X4TS U239 ( .A0(n193), .A1(n69), .B0(n199), .Y(n68) );
XNOR2X4TS U240 ( .A(n170), .B(in2[26]), .Y(n171) );
MXI2X4TS U241 ( .A(n96), .B(n93), .S0(n317), .Y(n94) );
NAND2X4TS U242 ( .A(n183), .B(n65), .Y(n24) );
XNOR2X2TS U243 ( .A(n215), .B(n214), .Y(res[28]) );
AND2X6TS U244 ( .A(n105), .B(n84), .Y(n85) );
INVX2TS U245 ( .A(n114), .Y(n29) );
OAI21X2TS U246 ( .A0(n284), .A1(n289), .B0(n10), .Y(n114) );
XNOR2X1TS U247 ( .A(n187), .B(in2[29]), .Y(n188) );
OR2X6TS U248 ( .A(n129), .B(in1[17]), .Y(n80) );
NAND2X2TS U249 ( .A(n178), .B(in1[26]), .Y(n223) );
INVX2TS U250 ( .A(n201), .Y(n205) );
NOR2X2TS U251 ( .A(n189), .B(in1[29]), .Y(n201) );
CLKINVX6TS U252 ( .A(in2[9]), .Y(n96) );
NAND3X1TS U253 ( .A(n90), .B(n61), .C(n327), .Y(n92) );
XNOR2X1TS U254 ( .A(in2[14]), .B(n122), .Y(n111) );
MXI2X4TS U255 ( .A(n125), .B(n124), .S0(n336), .Y(n126) );
INVX2TS U256 ( .A(in2[16]), .Y(n125) );
NAND3X1TS U257 ( .A(n118), .B(n117), .C(n116), .Y(n119) );
INVX2TS U258 ( .A(in2[18]), .Y(n131) );
INVX2TS U259 ( .A(in2[20]), .Y(n139) );
MXI2X4TS U260 ( .A(n172), .B(n171), .S0(n317), .Y(n178) );
INVX2TS U261 ( .A(n185), .Y(n169) );
INVX2TS U262 ( .A(in2[2]), .Y(n81) );
NOR2X2TS U263 ( .A(in2[6]), .B(n330), .Y(n323) );
INVX2TS U264 ( .A(n310), .Y(n89) );
AOI21X1TS U265 ( .A0(n51), .A1(in2[11]), .B0(in1[11]), .Y(n47) );
NAND2X4TS U266 ( .A(n22), .B(in1[11]), .Y(n297) );
NAND2X2TS U267 ( .A(n112), .B(in1[13]), .Y(n289) );
NOR2X2TS U268 ( .A(n112), .B(in1[13]), .Y(n288) );
INVX2TS U269 ( .A(n283), .Y(n292) );
NOR2X4TS U270 ( .A(n121), .B(in1[15]), .Y(n280) );
NOR2X4TS U271 ( .A(n159), .B(in1[22]), .Y(n251) );
NAND2X2TS U272 ( .A(n159), .B(in1[22]), .Y(n252) );
INVX2TS U273 ( .A(n217), .Y(n218) );
OR2X4TS U274 ( .A(n198), .B(in1[31]), .Y(n74) );
INVX2TS U275 ( .A(n202), .Y(n191) );
INVX2TS U276 ( .A(n204), .Y(n192) );
NOR2X4TS U277 ( .A(in2[17]), .B(in2[16]), .Y(n137) );
NAND2X2TS U278 ( .A(in2[7]), .B(n336), .Y(n83) );
OR2X4TS U279 ( .A(n103), .B(n105), .Y(n100) );
NOR2X4TS U280 ( .A(n45), .B(n293), .Y(n44) );
INVX2TS U281 ( .A(n103), .Y(n36) );
INVX2TS U282 ( .A(n57), .Y(n52) );
MXI2X4TS U283 ( .A(n157), .B(n156), .S0(n317), .Y(n159) );
XOR2X2TS U284 ( .A(n155), .B(in2[22]), .Y(n156) );
INVX2TS U285 ( .A(in2[24]), .Y(n150) );
NAND2X4TS U286 ( .A(n163), .B(n243), .Y(n165) );
INVX2TS U287 ( .A(n183), .Y(n67) );
NOR2X4TS U288 ( .A(n141), .B(in1[20]), .Y(n261) );
NOR2X4TS U289 ( .A(n140), .B(in1[19]), .Y(n266) );
INVX2TS U290 ( .A(n260), .Y(n270) );
INVX2TS U291 ( .A(n249), .Y(n257) );
INVX2TS U292 ( .A(n256), .Y(n250) );
NOR2X4TS U293 ( .A(n161), .B(in1[24]), .Y(n237) );
NOR2X1TS U294 ( .A(n233), .B(n244), .Y(n236) );
INVX2TS U295 ( .A(n243), .Y(n233) );
INVX2TS U296 ( .A(n232), .Y(n259) );
XNOR2X1TS U297 ( .A(n335), .B(in2[4]), .Y(n337) );
NOR2XLTS U298 ( .A(n331), .B(n330), .Y(n332) );
NAND2X1TS U299 ( .A(n335), .B(n323), .Y(n324) );
NAND2X1TS U300 ( .A(n309), .B(n308), .Y(n311) );
INVX2TS U301 ( .A(n307), .Y(n309) );
NAND2X1TS U302 ( .A(n78), .B(n305), .Y(n306) );
NAND2X1TS U303 ( .A(n77), .B(n297), .Y(n299) );
NAND2X1TS U304 ( .A(n290), .B(n289), .Y(n291) );
INVX2TS U305 ( .A(n288), .Y(n290) );
NAND2X1TS U306 ( .A(n285), .B(n10), .Y(n286) );
INVX2TS U307 ( .A(n284), .Y(n285) );
NAND2X1TS U308 ( .A(n12), .B(n281), .Y(n282) );
INVX2TS U309 ( .A(n54), .Y(n53) );
XOR2X1TS U310 ( .A(n270), .B(n269), .Y(res[19]) );
INVX2TS U311 ( .A(n266), .Y(n268) );
XNOR2X1TS U312 ( .A(n259), .B(n258), .Y(res[21]) );
XOR2X1TS U313 ( .A(n231), .B(n230), .Y(res[25]) );
INVX2TS U314 ( .A(n227), .Y(n229) );
INVX2TS U315 ( .A(n179), .Y(n224) );
INVX2TS U316 ( .A(n216), .Y(n219) );
INVX2TS U317 ( .A(n211), .Y(n213) );
XNOR2X1TS U318 ( .A(n207), .B(n206), .Y(res[29]) );
INVX2TS U319 ( .A(n74), .Y(n69) );
XOR2X2TS U320 ( .A(n118), .B(in2[12]), .Y(n106) );
NAND2X1TS U321 ( .A(n27), .B(n271), .Y(n272) );
NAND2X6TS U322 ( .A(n77), .B(n50), .Y(n49) );
OAI21X1TS U323 ( .A0(n73), .A1(n69), .B0(n68), .Y(res[32]) );
NAND2X4TS U324 ( .A(n102), .B(add_sub), .Y(n48) );
NAND3X8TS U325 ( .A(n52), .B(n80), .C(n28), .Y(n33) );
NOR2X2TS U326 ( .A(n24), .B(n232), .Y(n70) );
OAI21X2TS U327 ( .A0(n232), .A1(n165), .B0(n164), .Y(n208) );
OAI2BB1X4TS U328 ( .A0N(n283), .A1N(n115), .B0(n29), .Y(n28) );
OA22X4TS U329 ( .A0(n102), .A1(n51), .B0(in2[11]), .B1(add_sub), .Y(n22) );
OR2X4TS U330 ( .A(n126), .B(in1[16]), .Y(n23) );
OA21X4TS U331 ( .A0(n209), .A1(n211), .B0(n212), .Y(n25) );
AND2X2TS U332 ( .A(n35), .B(n104), .Y(n26) );
INVX2TS U333 ( .A(n28), .Y(n279) );
NOR2XLTS U334 ( .A(n39), .B(n41), .Y(n295) );
NOR2X8TS U335 ( .A(n105), .B(n34), .Y(n118) );
NAND2X8TS U336 ( .A(n37), .B(n90), .Y(n105) );
NOR2X8TS U337 ( .A(n330), .B(n62), .Y(n90) );
AND2X8TS U338 ( .A(n327), .B(n91), .Y(n37) );
NOR2X8TS U339 ( .A(in2[0]), .B(in2[1]), .Y(n327) );
XNOR2X1TS U340 ( .A(n38), .B(n203), .Y(res[30]) );
OAI21X4TS U341 ( .A0(n66), .A1(n201), .B0(n204), .Y(n38) );
NOR2X8TS U342 ( .A(n71), .B(n70), .Y(n66) );
NAND2X8TS U343 ( .A(n118), .B(n117), .Y(n122) );
MXI2X4TS U344 ( .A(n139), .B(n138), .S0(n317), .Y(n141) );
NOR3X8TS U345 ( .A(n122), .B(in2[15]), .C(in2[14]), .Y(n123) );
BUFX20TS U346 ( .A(n123), .Y(n148) );
NOR2X8TS U347 ( .A(n46), .B(n95), .Y(n302) );
AND2X8TS U348 ( .A(n304), .B(n78), .Y(n46) );
NAND2X8TS U349 ( .A(n313), .B(n312), .Y(n330) );
OR2X8TS U350 ( .A(n66), .B(n194), .Y(n73) );
NAND2X8TS U351 ( .A(n72), .B(n25), .Y(n71) );
XOR2X1TS U352 ( .A(n248), .B(n247), .Y(res[23]) );
XOR2X1TS U353 ( .A(n241), .B(n240), .Y(res[24]) );
XNOR2X1TS U354 ( .A(n311), .B(n310), .Y(res[8]) );
XNOR2X4TS U355 ( .A(n101), .B(in2[11]), .Y(n102) );
NOR2X8TS U356 ( .A(n100), .B(in2[10]), .Y(n101) );
XOR2X4TS U357 ( .A(n148), .B(in2[16]), .Y(n124) );
NOR2X2TS U358 ( .A(n154), .B(n153), .Y(n155) );
INVX2TS U359 ( .A(n242), .Y(n234) );
INVX2TS U360 ( .A(n305), .Y(n95) );
NAND2X1TS U361 ( .A(n13), .B(n301), .Y(n303) );
AOI2BB1X4TS U362 ( .A0N(n323), .A1N(n83), .B0(n82), .Y(n84) );
OAI21X4TS U363 ( .A0(n307), .A1(n89), .B0(n308), .Y(n304) );
XNOR2X4TS U364 ( .A(n100), .B(in2[10]), .Y(n98) );
MXI2X8TS U365 ( .A(n104), .B(n98), .S0(n317), .Y(n99) );
INVX2TS U366 ( .A(in2[12]), .Y(n108) );
INVX2TS U367 ( .A(in2[14]), .Y(n116) );
INVX2TS U368 ( .A(n148), .Y(n127) );
XNOR2X1TS U369 ( .A(n134), .B(in2[19]), .Y(n135) );
MX2X4TS U370 ( .A(in2[19]), .B(n135), .S0(add_sub), .Y(n140) );
AOI21X4TS U371 ( .A0(n260), .A1(n143), .B0(n142), .Y(n232) );
XNOR2X1TS U372 ( .A(n185), .B(in2[24]), .Y(n149) );
INVX2TS U373 ( .A(in2[22]), .Y(n157) );
OAI21X4TS U374 ( .A0(n251), .A1(n256), .B0(n252), .Y(n242) );
AOI21X4TS U375 ( .A0(n163), .A1(n242), .B0(n162), .Y(n164) );
OAI21X4TS U376 ( .A0(n228), .A1(n179), .B0(n223), .Y(n217) );
AOI21X4TS U377 ( .A0(n76), .A1(n217), .B0(n181), .Y(n209) );
XOR2X1TS U378 ( .A(n195), .B(in2[30]), .Y(n186) );
AOI21X4TS U379 ( .A0(n79), .A1(n192), .B0(n191), .Y(n193) );
XOR2X4TS U380 ( .A(n200), .B(n75), .Y(res[31]) );
INVX2TS U381 ( .A(n66), .Y(n207) );
AOI21X4TS U382 ( .A0(n259), .A1(n236), .B0(n235), .Y(n241) );
AOI21X4TS U383 ( .A0(n259), .A1(n243), .B0(n242), .Y(n248) );
AOI21X4TS U384 ( .A0(n259), .A1(n257), .B0(n250), .Y(n255) );
INVX2TS U385 ( .A(n261), .Y(n263) );
XNOR2X1TS U386 ( .A(n273), .B(n275), .Y(res[17]) );
XNOR2X1TS U387 ( .A(n278), .B(n277), .Y(res[16]) );
XNOR2X1TS U388 ( .A(n287), .B(n286), .Y(res[14]) );
XNOR2X1TS U389 ( .A(n299), .B(n298), .Y(res[11]) );
XNOR2X1TS U390 ( .A(n304), .B(n306), .Y(res[9]) );
NAND2X1TS U391 ( .A(n335), .B(n312), .Y(n314) );
XNOR2X1TS U392 ( .A(n314), .B(n313), .Y(n315) );
MXI2X1TS U393 ( .A(in2[5]), .B(n315), .S0(n336), .Y(n316) );
XOR2X1TS U394 ( .A(in2[0]), .B(in2[1]), .Y(n318) );
MXI2X1TS U395 ( .A(in2[1]), .B(n318), .S0(n317), .Y(n319) );
XOR2X1TS U396 ( .A(in2[3]), .B(n320), .Y(n321) );
MXI2X1TS U397 ( .A(in2[3]), .B(n321), .S0(n336), .Y(n322) );
XOR2X1TS U398 ( .A(n324), .B(in2[7]), .Y(n325) );
MXI2X1TS U399 ( .A(in2[7]), .B(n325), .S0(n336), .Y(n326) );
XNOR2X1TS U400 ( .A(n327), .B(in2[2]), .Y(n328) );
MXI2X1TS U401 ( .A(in2[2]), .B(n328), .S0(n336), .Y(n329) );
INVX2TS U402 ( .A(n335), .Y(n331) );
XNOR2X1TS U403 ( .A(n332), .B(in2[6]), .Y(n333) );
MXI2X1TS U404 ( .A(in2[6]), .B(n333), .S0(n336), .Y(n334) );
MXI2X1TS U405 ( .A(in2[4]), .B(n337), .S0(n336), .Y(n338) );
initial $sdf_annotate("Approx_adder_LOALPL8_syn.sdf");
endmodule
|
/*
* Copyright (c) 2015-2017 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Long integer multiplication
*/
`include "uparc_cpu_config.vh"
`include "uparc_cpu_common.vh"
`include "uparc_cpu_const.vh"
/* Multiplication */
module uparc_long_imul(
clk,
nrst,
multiplicand,
multiplier,
start,
signd,
ready,
product
);
input wire clk;
input wire nrst;
input wire [`UPARC_REG_WIDTH-1:0] multiplicand;
input wire [`UPARC_REG_WIDTH-1:0] multiplier;
input wire start;
input wire signd;
output wire ready;
output wire [2*`UPARC_REG_WIDTH-1:0] product;
/* Local registers */
reg [5:0] nbit;
reg [2*`UPARC_REG_WIDTH-1:0] prod;
reg [`UPARC_REG_WIDTH-1:0] abs_multiplicand;
assign ready = !nbit && !start;
assign product = (signd && (multiplicand[`UPARC_REG_WIDTH-1] ^ multiplier[`UPARC_REG_WIDTH-1])) ?
-prod : prod;
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
nbit <= 6'b0;
prod <= {(2*`UPARC_REG_WIDTH){1'b0}};
abs_multiplicand <= {(`UPARC_REG_WIDTH){1'b0}};
end
else if(start)
begin
if(!multiplicand || !multiplier)
begin
nbit <= 6'b0;
prod <= {(2*`UPARC_REG_WIDTH){1'b0}};
end
else
begin
nbit <= 6'd`UPARC_REG_WIDTH;
prod <= { {(`UPARC_REG_WIDTH){1'b0}}, signd && multiplier[`UPARC_REG_WIDTH-1] ?
-multiplier : multiplier };
abs_multiplicand <= signd && multiplicand[`UPARC_REG_WIDTH-1] ?
-multiplicand : multiplicand;
end
end
else if(nbit)
begin
nbit <= nbit - 1'b1;
if(prod[0])
begin
prod[2*`UPARC_REG_WIDTH-1:`UPARC_REG_WIDTH-1] <=
prod[2*`UPARC_REG_WIDTH-1:`UPARC_REG_WIDTH] + abs_multiplicand;
prod[`UPARC_REG_WIDTH-2:0] <= prod[`UPARC_REG_WIDTH-1:1];
end
else
prod <= { 1'b0, prod[2*`UPARC_REG_WIDTH-1:1] };
end
end
endmodule /* uparc_long_imul */
|
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for wb_drp
*/
module test_wb_drp;
// Parameters
parameter ADDR_WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wb_adr_i = 0;
reg [15:0] wb_dat_i = 0;
reg wb_we_i = 0;
reg wb_stb_i = 0;
reg wb_cyc_i = 0;
reg [15:0] drp_di = 0;
reg drp_rdy = 0;
// Outputs
wire [15:0] wb_dat_o;
wire wb_ack_o;
wire [ADDR_WIDTH-1:0] drp_addr;
wire [15:0] drp_do;
wire drp_en;
wire drp_we;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
wb_adr_i,
wb_dat_i,
wb_we_i,
wb_stb_i,
wb_cyc_i,
drp_di,
drp_rdy
);
$to_myhdl(
wb_dat_o,
wb_ack_o,
drp_addr,
drp_do,
drp_en,
drp_we
);
// dump file
$dumpfile("test_wb_drp.lxt");
$dumpvars(0, test_wb_drp);
end
wb_drp #(
.ADDR_WIDTH(ADDR_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_we_i(wb_we_i),
.wb_stb_i(wb_stb_i),
.wb_ack_o(wb_ack_o),
.wb_cyc_i(wb_cyc_i),
.drp_addr(drp_addr),
.drp_do(drp_do),
.drp_di(drp_di),
.drp_en(drp_en),
.drp_we(drp_we),
.drp_rdy(drp_rdy)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3_BLACKBOX_V
`define SKY130_FD_SC_HDLL__AND3_BLACKBOX_V
/**
* and3: 3-input AND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1N_SYMBOL_V
`define SKY130_FD_SC_LP__INPUTISO1N_SYMBOL_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inputiso1n (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1N_SYMBOL_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:18:54 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_FSM_Add_Subtract_83 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W11_82 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W55_1_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W55_1_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W64_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W64_0_5 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module FPU_Add_Subtract_Function_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_FSM,
ack_FSM, Data_X, Data_Y, add_subt, r_mode, overflow_flag,
underflow_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
input [1:0] r_mode;
output [63:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM, add_subt;
output overflow_flag, underflow_flag, ready;
wire FSM_selector_C, add_overflow_flag, FSM_exp_operation_load_diff,
FSM_barrel_shifter_load, FSM_Add_Subt_Sgf_load, FSM_LZA_load,
FSM_Final_Result_load, FSM_selector_D, sign_final_result,
FS_Module_net3849879, final_result_ieee_Module_Sign_S_mux,
YRegister_net3849802, Exp_Operation_Module_exp_result_net3849843,
Leading_Zero_Detector_Module_Output_Reg_net3849807,
final_result_ieee_Module_Final_Result_IEEE_net3849802,
Add_Subt_Sgf_module_Add_Subt_Result_net3849825,
Oper_Start_in_module_MRegister_net3849861,
Barrel_Shifter_module_Output_Reg_net3849825, n86, n860, n861, n864,
n865, n866, n867, n871, n872, n873, n881, n882, n883, n884, n885,
n886, n887, n888, n889, n890, n891, n892, n893, n894, n895, n896,
n897, n898, n899, n900, n901, n902, n903, n904, n905, n906, n907,
n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918,
n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929,
n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940,
n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951,
n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962,
n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973,
n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984,
n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995,
n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005,
n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015,
n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026,
n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036,
n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046,
n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056,
n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066,
n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076,
n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086,
n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096,
n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106,
n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116,
n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126,
n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136,
n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146,
n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156,
n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166,
n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176,
n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186,
n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196,
n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206,
n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216,
n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226,
n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236,
n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246,
n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256,
n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266,
n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276,
n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286,
n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296,
n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306,
n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316,
n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326,
n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336,
n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346,
n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356,
n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366,
n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376,
n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386,
n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396,
n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406,
n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416,
n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426,
n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436,
n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446,
n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456,
n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466,
n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476,
n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486,
n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496,
n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506,
n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516,
n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526,
n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536,
n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546,
n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556,
n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566,
n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576,
n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586,
n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596,
n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606,
n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616,
n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626,
n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636,
n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706,
n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716,
n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1725, n1726, n1727,
n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737,
n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747,
n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757,
n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767,
n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777,
n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787,
n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797,
n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807,
n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817,
n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827,
n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837,
n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847,
n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857,
n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867,
n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877,
n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887,
n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897,
n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907,
n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917,
n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927,
n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937,
n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947,
n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957,
n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967,
n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977,
n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987,
n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997,
n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007,
n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017,
n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027,
n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037,
n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047,
n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057,
n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067,
n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077,
n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087,
n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097,
n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107,
n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117,
n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2126, n2127, n2128,
n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138,
n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148,
n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158,
n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168,
n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178,
n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188,
n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198,
n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208,
n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218,
n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228,
n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238,
n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248,
n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258,
n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268,
n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278,
n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288,
n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298,
n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308,
n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318,
n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328,
n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338,
n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348,
n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358,
n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368,
n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378,
n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388,
n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398,
n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408,
n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418,
n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428,
n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438,
n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448,
n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458,
n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468,
n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478,
n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488,
n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498,
n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508,
n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518,
n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528,
n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538,
n2539, n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548,
n2549, n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558,
n2559, n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568,
n2569, n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578,
n2579, n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588,
n2589, n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598,
n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608,
n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618,
n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628,
n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638,
n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648,
n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658,
n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668,
n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678,
n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688,
n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698,
n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708,
n2709, n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718,
n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728,
n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738,
n2739, n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748,
n2749, n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758,
n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768,
n2769, n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778,
n2779, n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788,
n2789, n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798,
n2799, n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808,
n2809, n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818,
n2819, n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828,
n2829, n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838,
n2839, n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848,
n2849, n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858,
n2859, n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868,
n2869, n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878,
n2879, n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888,
n2889, n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898,
n2899, n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908,
n2909, n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918,
n2919, n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928,
n2929, n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938,
n2939, n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948,
n2949, n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958,
n2959, n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968,
n2969, n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978,
n2979, n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988,
n2989, n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998,
n2999, n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008,
n3009, n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018,
n3019, n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028,
n3029, n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038,
n3039, n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048,
n3049, n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058,
n3059, n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068,
n3069, n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078,
n3079, n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088,
n3089, n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098,
n3099, n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108,
n3109, n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118,
n3119, n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128,
n3129, n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138,
n3139, n3140;
wire [1:0] FSM_selector_B;
wire [63:0] intDX;
wire [62:0] intDY;
wire [62:0] DMP;
wire [62:0] DmP;
wire [10:0] exp_oper_result;
wire [5:0] LZA_output;
wire [54:0] Add_Subt_result;
wire [54:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_next;
wire [3:0] FS_Module_state_reg;
wire [62:0] Oper_Start_in_module_intm;
wire [62:0] Oper_Start_in_module_intM;
wire [10:0] Exp_Operation_Module_Data_S;
wire [54:0] Barrel_Shifter_module_Data_Reg;
wire [55:0] Add_Subt_Sgf_module_S_to_D;
wire [5:0] Leading_Zero_Detector_Module_Codec_to_Reg;
wire [51:0] final_result_ieee_Module_Sgf_S_mux;
wire [10:0] final_result_ieee_Module_Exp_S_mux;
wire [109:0] Barrel_Shifter_module_Mux_Array_Data_array;
SNPS_CLOCK_GATE_HIGH_FSM_Add_Subtract_83 FS_Module_clk_gate_state_reg_reg (
.CLK(clk), .EN(n872), .ENCLK(FS_Module_net3849879), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W64_0_5 YRegister_clk_gate_Q_reg ( .CLK(clk), .EN(n871), .ENCLK(YRegister_net3849802), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W11_82 Exp_Operation_Module_exp_result_clk_gate_Q_reg (
.CLK(clk), .EN(FSM_exp_operation_load_diff), .ENCLK(
Exp_Operation_Module_exp_result_net3849843), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W6 Leading_Zero_Detector_Module_Output_Reg_clk_gate_Q_reg (
.CLK(clk), .EN(FSM_LZA_load), .ENCLK(
Leading_Zero_Detector_Module_Output_Reg_net3849807), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W64_0_4 final_result_ieee_Module_Final_Result_IEEE_clk_gate_Q_reg (
.CLK(clk), .EN(FSM_Final_Result_load), .ENCLK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W55_1_2 Add_Subt_Sgf_module_Add_Subt_Result_clk_gate_Q_reg (
.CLK(clk), .EN(FSM_Add_Subt_Sgf_load), .ENCLK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_6 Oper_Start_in_module_MRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n873), .ENCLK(Oper_Start_in_module_MRegister_net3849861), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W55_1_3 Barrel_Shifter_module_Output_Reg_clk_gate_Q_reg (
.CLK(clk), .EN(FSM_barrel_shifter_load), .ENCLK(
Barrel_Shifter_module_Output_Reg_net3849825), .TE(1'b0) );
DFFRX4TS FS_Module_state_reg_reg_1_ ( .D(FS_Module_state_next[1]), .CK(
FS_Module_net3849879), .RN(n3081), .Q(FS_Module_state_reg[1]), .QN(
n925) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_10_ ( .D(
Exp_Operation_Module_Data_S[10]), .CK(
Exp_Operation_Module_exp_result_net3849843), .RN(n3096), .Q(
exp_oper_result[10]) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_9_ ( .D(
Exp_Operation_Module_Data_S[9]), .CK(
Exp_Operation_Module_exp_result_net3849843), .RN(n3095), .Q(
exp_oper_result[9]) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_8_ ( .D(
Exp_Operation_Module_Data_S[8]), .CK(
Exp_Operation_Module_exp_result_net3849843), .RN(n3095), .Q(
exp_oper_result[8]) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(
Exp_Operation_Module_Data_S[7]), .CK(
Exp_Operation_Module_exp_result_net3849843), .RN(n3095), .Q(
exp_oper_result[7]) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(
Exp_Operation_Module_Data_S[6]), .CK(
Exp_Operation_Module_exp_result_net3849843), .RN(n3095), .Q(
exp_oper_result[6]) );
DFFRX4TS FS_Module_state_reg_reg_3_ ( .D(FS_Module_state_next[3]), .CK(
FS_Module_net3849879), .RN(n3081), .Q(FS_Module_state_reg[3]), .QN(
n922) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_62_ ( .D(
Oper_Start_in_module_intM[62]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3096), .Q(DMP[62]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_61_ ( .D(
Oper_Start_in_module_intM[61]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3096), .Q(DMP[61]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_60_ ( .D(
Oper_Start_in_module_intM[60]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3095), .Q(DMP[60]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_59_ ( .D(
Oper_Start_in_module_intM[59]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3095), .Q(DMP[59]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_58_ ( .D(
Oper_Start_in_module_intM[58]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3095), .Q(DMP[58]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_57_ ( .D(
Oper_Start_in_module_intM[57]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3095), .Q(DMP[57]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_56_ ( .D(
Oper_Start_in_module_intM[56]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3095), .Q(DMP[56]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_55_ ( .D(
Oper_Start_in_module_intM[55]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3094), .Q(DMP[55]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_54_ ( .D(
Oper_Start_in_module_intM[54]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3094), .Q(DMP[54]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_53_ ( .D(
Oper_Start_in_module_intM[53]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3094), .Q(DMP[53]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_52_ ( .D(
Oper_Start_in_module_intM[52]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3094), .Q(DMP[52]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_51_ ( .D(
Oper_Start_in_module_intM[51]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3101), .Q(DMP[51]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_50_ ( .D(
Oper_Start_in_module_intM[50]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3101), .Q(DMP[50]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_49_ ( .D(
Oper_Start_in_module_intM[49]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3101), .Q(DMP[49]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_48_ ( .D(
Oper_Start_in_module_intM[48]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3100), .Q(DMP[48]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_47_ ( .D(
Oper_Start_in_module_intM[47]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3100), .Q(DMP[47]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_46_ ( .D(
Oper_Start_in_module_intM[46]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3100), .Q(DMP[46]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_45_ ( .D(
Oper_Start_in_module_intM[45]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3100), .Q(DMP[45]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_44_ ( .D(
Oper_Start_in_module_intM[44]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3100), .Q(DMP[44]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_43_ ( .D(
Oper_Start_in_module_intM[43]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3090), .Q(DMP[43]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_42_ ( .D(
Oper_Start_in_module_intM[42]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3090), .Q(DMP[42]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_41_ ( .D(
Oper_Start_in_module_intM[41]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3090), .Q(DMP[41]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_40_ ( .D(
Oper_Start_in_module_intM[40]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3089), .Q(DMP[40]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_39_ ( .D(
Oper_Start_in_module_intM[39]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3089), .Q(DMP[39]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_38_ ( .D(
Oper_Start_in_module_intM[38]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3089), .Q(DMP[38]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_37_ ( .D(
Oper_Start_in_module_intM[37]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3089), .Q(DMP[37]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_36_ ( .D(
Oper_Start_in_module_intM[36]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3089), .Q(DMP[36]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_35_ ( .D(
Oper_Start_in_module_intM[35]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3088), .Q(DMP[35]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_34_ ( .D(
Oper_Start_in_module_intM[34]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3088), .Q(DMP[34]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_33_ ( .D(
Oper_Start_in_module_intM[33]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3088), .Q(DMP[33]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_32_ ( .D(
Oper_Start_in_module_intM[32]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3088), .Q(DMP[32]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_31_ ( .D(
Oper_Start_in_module_intM[31]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3088), .Q(DMP[31]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(
Oper_Start_in_module_intM[30]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3087), .Q(DMP[30]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(
Oper_Start_in_module_intM[29]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3087), .Q(DMP[29]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(
Oper_Start_in_module_intM[28]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3087), .Q(DMP[28]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(
Oper_Start_in_module_intM[27]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3087), .Q(DMP[27]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(
Oper_Start_in_module_intM[26]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3087), .Q(DMP[26]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(
Oper_Start_in_module_intM[25]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3086), .Q(DMP[25]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(
Oper_Start_in_module_intM[24]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3086), .Q(DMP[24]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(
Oper_Start_in_module_intM[23]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3086), .Q(DMP[23]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(
Oper_Start_in_module_intM[22]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3086), .Q(DMP[22]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(
Oper_Start_in_module_intM[21]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3086), .Q(DMP[21]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(
Oper_Start_in_module_intM[20]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3085), .Q(DMP[20]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(
Oper_Start_in_module_intM[19]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3085), .Q(DMP[19]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(
Oper_Start_in_module_intM[18]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3085), .Q(DMP[18]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(
Oper_Start_in_module_intM[17]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3085), .Q(DMP[17]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(
Oper_Start_in_module_intM[16]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3085), .Q(DMP[16]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(
Oper_Start_in_module_intM[15]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3084), .Q(DMP[15]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(
Oper_Start_in_module_intM[14]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3084), .Q(DMP[14]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(
Oper_Start_in_module_intM[13]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3084), .Q(DMP[13]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(
Oper_Start_in_module_intM[12]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3084), .Q(DMP[12]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(
Oper_Start_in_module_intM[11]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3084), .Q(DMP[11]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(
Oper_Start_in_module_intM[10]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3083), .Q(DMP[10]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(
Oper_Start_in_module_intM[9]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3083), .Q(DMP[9]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(
Oper_Start_in_module_intM[8]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3083), .Q(DMP[8]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(
Oper_Start_in_module_intM[7]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3083), .Q(DMP[7]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(
Oper_Start_in_module_intM[6]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3083), .Q(DMP[6]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(
Oper_Start_in_module_intM[5]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3082), .Q(DMP[5]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(
Oper_Start_in_module_intM[4]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3082), .Q(DMP[4]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(
Oper_Start_in_module_intM[3]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3082), .Q(DMP[3]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(
Oper_Start_in_module_intM[2]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3082), .Q(DMP[2]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(
Oper_Start_in_module_intM[1]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3082), .Q(DMP[1]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(
Oper_Start_in_module_intM[0]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3081), .Q(DMP[0]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_62_ ( .D(
Oper_Start_in_module_intm[62]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3094), .Q(DmP[62]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_61_ ( .D(
Oper_Start_in_module_intm[61]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3094), .Q(DmP[61]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_60_ ( .D(
Oper_Start_in_module_intm[60]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3093), .Q(DmP[60]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_59_ ( .D(
Oper_Start_in_module_intm[59]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3093), .Q(DmP[59]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_58_ ( .D(
Oper_Start_in_module_intm[58]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3093), .Q(DmP[58]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_57_ ( .D(
Oper_Start_in_module_intm[57]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3093), .Q(DmP[57]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_56_ ( .D(
Oper_Start_in_module_intm[56]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3093), .Q(DmP[56]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_55_ ( .D(
Oper_Start_in_module_intm[55]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3092), .Q(DmP[55]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_54_ ( .D(
Oper_Start_in_module_intm[54]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3091), .Q(DmP[54]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_53_ ( .D(
Oper_Start_in_module_intm[53]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3091), .Q(DmP[53]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_52_ ( .D(
Oper_Start_in_module_intm[52]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3090), .Q(DmP[52]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_51_ ( .D(
Oper_Start_in_module_intm[51]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3064), .Q(DmP[51]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_50_ ( .D(
Oper_Start_in_module_intm[50]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3064), .Q(DmP[50]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_49_ ( .D(
Oper_Start_in_module_intm[49]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3064), .Q(DmP[49]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_48_ ( .D(
Oper_Start_in_module_intm[48]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3064), .Q(DmP[48]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_47_ ( .D(
Oper_Start_in_module_intm[47]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3064), .Q(DmP[47]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_46_ ( .D(
Oper_Start_in_module_intm[46]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3064), .Q(DmP[46]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_45_ ( .D(
Oper_Start_in_module_intm[45]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3064), .Q(DmP[45]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_44_ ( .D(
Oper_Start_in_module_intm[44]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3064), .Q(DmP[44]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_43_ ( .D(
Oper_Start_in_module_intm[43]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3064), .Q(DmP[43]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_42_ ( .D(
Oper_Start_in_module_intm[42]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3064), .Q(DmP[42]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_41_ ( .D(
Oper_Start_in_module_intm[41]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3065), .Q(DmP[41]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_40_ ( .D(
Oper_Start_in_module_intm[40]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3065), .Q(DmP[40]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_39_ ( .D(
Oper_Start_in_module_intm[39]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3065), .Q(DmP[39]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_38_ ( .D(
Oper_Start_in_module_intm[38]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3065), .Q(DmP[38]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_37_ ( .D(
Oper_Start_in_module_intm[37]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3065), .Q(DmP[37]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_36_ ( .D(
Oper_Start_in_module_intm[36]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3065), .Q(DmP[36]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_35_ ( .D(
Oper_Start_in_module_intm[35]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3065), .Q(DmP[35]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_34_ ( .D(
Oper_Start_in_module_intm[34]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3065), .Q(DmP[34]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_33_ ( .D(
Oper_Start_in_module_intm[33]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3065), .Q(DmP[33]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_32_ ( .D(
Oper_Start_in_module_intm[32]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3065), .Q(DmP[32]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_31_ ( .D(
Oper_Start_in_module_intm[31]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3066), .Q(DmP[31]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(
Oper_Start_in_module_intm[30]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3066), .Q(DmP[30]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(
Oper_Start_in_module_intm[29]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3066), .Q(DmP[29]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(
Oper_Start_in_module_intm[28]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3066), .Q(DmP[28]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(
Oper_Start_in_module_intm[27]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3066), .Q(DmP[27]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(
Oper_Start_in_module_intm[26]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3066), .Q(DmP[26]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(
Oper_Start_in_module_intm[25]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3066), .Q(DmP[25]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(
Oper_Start_in_module_intm[24]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3066), .Q(DmP[24]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(
Oper_Start_in_module_intm[23]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3066), .Q(DmP[23]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(
Oper_Start_in_module_intm[22]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3066), .Q(DmP[22]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(
Oper_Start_in_module_intm[21]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3067), .Q(DmP[21]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(
Oper_Start_in_module_intm[20]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3067), .Q(DmP[20]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(
Oper_Start_in_module_intm[19]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3067), .Q(DmP[19]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(
Oper_Start_in_module_intm[18]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3067), .Q(DmP[18]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(
Oper_Start_in_module_intm[17]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3067), .Q(DmP[17]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(
Oper_Start_in_module_intm[16]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3067), .Q(DmP[16]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(
Oper_Start_in_module_intm[15]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3067), .Q(DmP[15]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(
Oper_Start_in_module_intm[14]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3067), .Q(DmP[14]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(
Oper_Start_in_module_intm[13]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3067), .Q(DmP[13]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(
Oper_Start_in_module_intm[12]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3067), .Q(DmP[12]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(
Oper_Start_in_module_intm[11]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3068), .Q(DmP[11]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(
Oper_Start_in_module_intm[10]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3068), .Q(DmP[10]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(
Oper_Start_in_module_intm[9]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3068), .Q(DmP[9]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(
Oper_Start_in_module_intm[8]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3068), .Q(DmP[8]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(
Oper_Start_in_module_intm[7]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3068), .Q(DmP[7]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(
Oper_Start_in_module_intm[6]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3068), .Q(DmP[6]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(
Oper_Start_in_module_intm[5]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3068), .Q(DmP[5]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(
Oper_Start_in_module_intm[4]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3068), .Q(DmP[4]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(
Oper_Start_in_module_intm[3]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3068), .Q(DmP[3]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(
Oper_Start_in_module_intm[2]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3068), .Q(DmP[2]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(
Oper_Start_in_module_intm[1]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3069), .Q(DmP[1]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(
Oper_Start_in_module_intm[0]), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3069), .Q(DmP[0]) );
DFFRX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_49_ ( .D(
Add_Subt_Sgf_module_S_to_D[49]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3098), .Q(
Add_Subt_result[49]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_47_ ( .D(
Add_Subt_Sgf_module_S_to_D[47]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3081), .Q(
Add_Subt_result[47]), .QN(n3022) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_45_ ( .D(
Add_Subt_Sgf_module_S_to_D[45]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3098), .Q(
Add_Subt_result[45]), .QN(n3054) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_43_ ( .D(
Add_Subt_Sgf_module_S_to_D[43]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3097), .Q(
Add_Subt_result[43]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_41_ ( .D(
Add_Subt_Sgf_module_S_to_D[41]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3099), .Q(
Add_Subt_result[41]), .QN(n2918) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_40_ ( .D(
Add_Subt_Sgf_module_S_to_D[40]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3099), .Q(
Add_Subt_result[40]), .QN(n2912) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_39_ ( .D(
Add_Subt_Sgf_module_S_to_D[39]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3099), .Q(
Add_Subt_result[39]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_38_ ( .D(
Add_Subt_Sgf_module_S_to_D[38]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3093), .Q(
Add_Subt_result[38]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_37_ ( .D(
Add_Subt_Sgf_module_S_to_D[37]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3093), .Q(
Add_Subt_result[37]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_36_ ( .D(
Add_Subt_Sgf_module_S_to_D[36]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3093), .Q(
Add_Subt_result[36]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_35_ ( .D(
Add_Subt_Sgf_module_S_to_D[35]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3093), .Q(
Add_Subt_result[35]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_34_ ( .D(
Add_Subt_Sgf_module_S_to_D[34]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3097), .Q(
Add_Subt_result[34]), .QN(n3052) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_33_ ( .D(
Add_Subt_Sgf_module_S_to_D[33]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3097), .Q(
Add_Subt_result[33]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_32_ ( .D(
Add_Subt_Sgf_module_S_to_D[32]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3097), .Q(
Add_Subt_result[32]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_31_ ( .D(
Add_Subt_Sgf_module_S_to_D[31]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3097), .Q(
Add_Subt_result[31]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_28_ ( .D(
Add_Subt_Sgf_module_S_to_D[28]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3096), .Q(
Add_Subt_result[28]), .QN(n3024) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_27_ ( .D(
Add_Subt_Sgf_module_S_to_D[27]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3097), .Q(
Add_Subt_result[27]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(
Add_Subt_Sgf_module_S_to_D[24]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3092), .Q(
Add_Subt_result[24]) );
DFFRX4TS Sel_C_Q_reg_0_ ( .D(n867), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n860), .Q(
FSM_selector_C), .QN(n3023) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ ( .D(
Leading_Zero_Detector_Module_Codec_to_Reg[2]), .CK(
Leading_Zero_Detector_Module_Output_Reg_net3849807), .RN(n3096), .Q(
LZA_output[2]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ ( .D(
Leading_Zero_Detector_Module_Codec_to_Reg[1]), .CK(
Leading_Zero_Detector_Module_Output_Reg_net3849807), .RN(n3091), .Q(
LZA_output[1]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ ( .D(
Leading_Zero_Detector_Module_Codec_to_Reg[0]), .CK(
Leading_Zero_Detector_Module_Output_Reg_net3849807), .RN(n3091), .Q(
LZA_output[0]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[3]), .CK(clk), .RN(n3073),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[58]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[6]), .CK(clk), .RN(n3074),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[61]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[2]), .CK(clk), .RN(n3074),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[57]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[5]), .CK(clk), .RN(n3074),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[60]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[1]), .CK(clk), .RN(n3074),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[56]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[4]), .CK(clk), .RN(n3074),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[59]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[0]), .CK(clk), .RN(n3074),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[55]) );
DFFRX4TS Sel_D_Q_reg_0_ ( .D(n866), .CK(FS_Module_net3849879), .RN(n860),
.Q(FSM_selector_D), .QN(n2920) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_54_ ( .D(
Barrel_Shifter_module_Data_Reg[54]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3101), .Q(
Sgf_normalized_result[54]) );
DFFRXLTS Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(n3113), .CK(
Oper_Start_in_module_MRegister_net3849861), .RN(n3101), .Q(
sign_final_result), .QN(n2911) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_27_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[27]), .CK(clk), .RN(n3071),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[82]), .QN(n3053) );
DFFRX1TS YRegister_Q_reg_38_ ( .D(Data_Y[38]), .CK(YRegister_net3849802),
.RN(n3061), .Q(intDY[38]), .QN(n3051) );
DFFRX1TS XRegister_Q_reg_23_ ( .D(Data_X[23]), .CK(YRegister_net3849802),
.RN(n3102), .Q(intDX[23]), .QN(n3050) );
DFFRX1TS YRegister_Q_reg_5_ ( .D(Data_Y[5]), .CK(YRegister_net3849802), .RN(
n3109), .Q(intDY[5]), .QN(n3048) );
DFFRX1TS YRegister_Q_reg_7_ ( .D(Data_Y[7]), .CK(YRegister_net3849802), .RN(
n3107), .Q(intDY[7]), .QN(n3046) );
DFFRX1TS YRegister_Q_reg_52_ ( .D(Data_Y[52]), .CK(YRegister_net3849802),
.RN(n3060), .Q(intDY[52]), .QN(n3042) );
DFFRX1TS YRegister_Q_reg_42_ ( .D(Data_Y[42]), .CK(YRegister_net3849802),
.RN(n3061), .Q(intDY[42]), .QN(n3034) );
DFFRX1TS YRegister_Q_reg_48_ ( .D(Data_Y[48]), .CK(YRegister_net3849802),
.RN(n3060), .Q(intDY[48]), .QN(n3032) );
DFFRX1TS YRegister_Q_reg_44_ ( .D(Data_Y[44]), .CK(YRegister_net3849802),
.RN(n3060), .Q(intDY[44]), .QN(n3031) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(
Add_Subt_Sgf_module_S_to_D[13]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3096), .Q(
Add_Subt_result[13]), .QN(n3026) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_35_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .CK(clk), .RN(n3071),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[90]), .QN(n3021) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(
Add_Subt_Sgf_module_S_to_D[11]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3096), .Q(
Add_Subt_result[11]), .QN(n3020) );
DFFRX1TS YRegister_Q_reg_16_ ( .D(Data_Y[16]), .CK(YRegister_net3849802),
.RN(n3105), .Q(intDY[16]), .QN(n3006) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(
Add_Subt_Sgf_module_S_to_D[15]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3091), .Q(
Add_Subt_result[15]), .QN(n2999) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(
Add_Subt_Sgf_module_S_to_D[10]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3091), .Q(
Add_Subt_result[10]), .QN(n2996) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_49_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .CK(clk), .RN(n3069),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[104]), .QN(n2982) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_50_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .CK(clk), .RN(n3069),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[105]), .QN(n2981) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_52_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[52]), .CK(clk), .RN(n3069),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[107]), .QN(n2980) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_53_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[53]), .CK(clk), .RN(n3069),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[108]), .QN(n2979) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_54_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[54]), .CK(clk), .RN(n3090),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[109]), .QN(n2978) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_48_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .CK(clk), .RN(n3069),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[103]), .QN(n2977) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_51_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .CK(clk), .RN(n3069),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[106]), .QN(n2976) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(
Add_Subt_Sgf_module_S_to_D[22]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3099), .Q(
Add_Subt_result[22]), .QN(n2975) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_30_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .CK(clk), .RN(n3071),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[85]), .QN(n2972) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_29_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .CK(clk), .RN(n3071),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[84]), .QN(n2971) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_28_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[28]), .CK(clk), .RN(n3071),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[83]), .QN(n2970) );
DFFRX2TS XRegister_Q_reg_3_ ( .D(Data_X[3]), .CK(YRegister_net3849802), .RN(
n3109), .Q(intDX[3]), .QN(n2966) );
DFFRX2TS XRegister_Q_reg_8_ ( .D(Data_X[8]), .CK(YRegister_net3849802), .RN(
n3108), .Q(intDX[8]), .QN(n2959) );
DFFRX2TS XRegister_Q_reg_53_ ( .D(Data_X[53]), .CK(YRegister_net3849802),
.RN(n3062), .QN(n2948) );
DFFRX2TS XRegister_Q_reg_60_ ( .D(Data_X[60]), .CK(YRegister_net3849802),
.RN(n3061), .QN(n2947) );
DFFRX2TS XRegister_Q_reg_49_ ( .D(Data_X[49]), .CK(YRegister_net3849802),
.RN(n3062), .QN(n2946) );
DFFRX2TS XRegister_Q_reg_45_ ( .D(Data_X[45]), .CK(YRegister_net3849802),
.RN(n3063), .QN(n2945) );
DFFRX2TS XRegister_Q_reg_43_ ( .D(Data_X[43]), .CK(YRegister_net3849802),
.RN(n3063), .QN(n2944) );
DFFRX2TS XRegister_Q_reg_50_ ( .D(Data_X[50]), .CK(YRegister_net3849802),
.RN(n3062), .QN(n2943) );
DFFRX1TS XRegister_Q_reg_20_ ( .D(Data_X[20]), .CK(YRegister_net3849802),
.RN(n3104), .Q(intDX[20]), .QN(n2942) );
DFFRX1TS XRegister_Q_reg_28_ ( .D(Data_X[28]), .CK(YRegister_net3849802),
.RN(n3105), .Q(intDX[28]), .QN(n2940) );
DFFRX1TS XRegister_Q_reg_4_ ( .D(Data_X[4]), .CK(YRegister_net3849802), .RN(
n3109), .Q(intDX[4]), .QN(n2938) );
DFFRX1TS XRegister_Q_reg_16_ ( .D(Data_X[16]), .CK(YRegister_net3849802),
.RN(n3105), .Q(intDX[16]), .QN(n2937) );
DFFRX1TS XRegister_Q_reg_12_ ( .D(Data_X[12]), .CK(YRegister_net3849802),
.RN(n3107), .Q(intDX[12]), .QN(n2936) );
DFFRX1TS XRegister_Q_reg_37_ ( .D(Data_X[37]), .CK(YRegister_net3849802),
.RN(n3103), .Q(intDX[37]), .QN(n2934) );
DFFRX1TS XRegister_Q_reg_6_ ( .D(Data_X[6]), .CK(YRegister_net3849802), .RN(
n3108), .Q(intDX[6]), .QN(n2932) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(
Add_Subt_Sgf_module_S_to_D[12]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3096), .Q(
Add_Subt_result[12]), .QN(n2931) );
DFFRX1TS YRegister_Q_reg_23_ ( .D(Data_Y[23]), .CK(YRegister_net3849802),
.RN(n3102), .Q(intDY[23]), .QN(n2930) );
DFFRX1TS XRegister_Q_reg_52_ ( .D(Data_X[52]), .CK(YRegister_net3849802),
.RN(n3062), .Q(intDX[52]), .QN(n2929) );
DFFRX1TS XRegister_Q_reg_48_ ( .D(Data_X[48]), .CK(YRegister_net3849802),
.RN(n3062), .Q(intDX[48]), .QN(n2927) );
DFFRX1TS XRegister_Q_reg_44_ ( .D(Data_X[44]), .CK(YRegister_net3849802),
.RN(n3063), .Q(intDX[44]), .QN(n2925) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(
Exp_Operation_Module_Data_S[5]), .CK(
Exp_Operation_Module_exp_result_net3849843), .RN(n3095), .Q(
exp_oper_result[5]), .QN(n2924) );
DFFRX2TS XRegister_Q_reg_11_ ( .D(Data_X[11]), .CK(YRegister_net3849802),
.RN(n3107), .Q(intDX[11]), .QN(n2923) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(
Add_Subt_Sgf_module_S_to_D[16]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3091), .Q(
Add_Subt_result[16]), .QN(n2921) );
DFFRX1TS YRegister_Q_reg_6_ ( .D(Data_Y[6]), .CK(YRegister_net3849802), .RN(
n3108), .Q(intDY[6]), .QN(n2910) );
DFFRX1TS YRegister_Q_reg_0_ ( .D(Data_Y[0]), .CK(YRegister_net3849802), .RN(
n3109), .Q(intDY[0]), .QN(n2907) );
DFFRX1TS XRegister_Q_reg_19_ ( .D(Data_X[19]), .CK(YRegister_net3849802),
.RN(n3104), .Q(intDX[19]), .QN(n2904) );
DFFRX1TS XRegister_Q_reg_27_ ( .D(Data_X[27]), .CK(YRegister_net3849802),
.RN(n3105), .Q(intDX[27]), .QN(n2903) );
DFFRX1TS XRegister_Q_reg_22_ ( .D(Data_X[22]), .CK(YRegister_net3849802),
.RN(n3106), .Q(intDX[22]), .QN(n2902) );
DFFRX1TS XRegister_Q_reg_14_ ( .D(Data_X[14]), .CK(YRegister_net3849802),
.RN(n3104), .Q(intDX[14]), .QN(n2901) );
DFFRX1TS XRegister_Q_reg_2_ ( .D(Data_X[2]), .CK(YRegister_net3849802), .RN(
n3108), .Q(intDX[2]), .QN(n2900) );
DFFRX1TS XRegister_Q_reg_30_ ( .D(Data_X[30]), .CK(YRegister_net3849802),
.RN(n3106), .Q(intDX[30]), .QN(n2899) );
DFFRX1TS XRegister_Q_reg_24_ ( .D(Data_X[24]), .CK(YRegister_net3849802),
.RN(n3106), .Q(intDX[24]), .QN(n2898) );
DFFRX1TS XRegister_Q_reg_39_ ( .D(Data_X[39]), .CK(YRegister_net3849802),
.RN(n3063), .Q(intDX[39]), .QN(n2897) );
DFFRX1TS XRegister_Q_reg_9_ ( .D(Data_X[9]), .CK(YRegister_net3849802), .RN(
n3108), .Q(intDX[9]), .QN(n2896) );
DFFRX1TS XRegister_Q_reg_34_ ( .D(Data_X[34]), .CK(YRegister_net3849802),
.RN(n3103), .Q(intDX[34]), .QN(n2895) );
DFFRX1TS XRegister_Q_reg_32_ ( .D(Data_X[32]), .CK(YRegister_net3849802),
.RN(n3103), .Q(intDX[32]), .QN(n2894) );
DFFRX1TS XRegister_Q_reg_38_ ( .D(Data_X[38]), .CK(YRegister_net3849802),
.RN(n3063), .Q(intDX[38]), .QN(n2893) );
DFFRX1TS XRegister_Q_reg_5_ ( .D(Data_X[5]), .CK(YRegister_net3849802), .RN(
n3109), .Q(intDX[5]), .QN(n2892) );
DFFRX1TS XRegister_Q_reg_7_ ( .D(Data_X[7]), .CK(YRegister_net3849802), .RN(
n3108), .Q(intDX[7]), .QN(n2891) );
DFFRX1TS XRegister_Q_reg_47_ ( .D(Data_X[47]), .CK(YRegister_net3849802),
.RN(n3063), .Q(intDX[47]), .QN(n2888) );
DFFRX1TS XRegister_Q_reg_10_ ( .D(Data_X[10]), .CK(YRegister_net3849802),
.RN(n3107), .Q(intDX[10]), .QN(n2887) );
DFFRX1TS XRegister_Q_reg_40_ ( .D(Data_X[40]), .CK(YRegister_net3849802),
.RN(n3063), .Q(intDX[40]), .QN(n2885) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ ( .D(
final_result_ieee_Module_Sign_S_mux), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3074),
.Q(final_result_ieee[63]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ ( .D(
final_result_ieee_Module_Exp_S_mux[0]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3074),
.Q(final_result_ieee[52]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ ( .D(
final_result_ieee_Module_Exp_S_mux[1]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3075),
.Q(final_result_ieee[53]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ ( .D(
final_result_ieee_Module_Exp_S_mux[2]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3075),
.Q(final_result_ieee[54]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ ( .D(
final_result_ieee_Module_Exp_S_mux[3]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3075),
.Q(final_result_ieee[55]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ ( .D(
final_result_ieee_Module_Exp_S_mux[4]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3075),
.Q(final_result_ieee[56]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ ( .D(
final_result_ieee_Module_Exp_S_mux[5]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3075),
.Q(final_result_ieee[57]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ ( .D(
final_result_ieee_Module_Exp_S_mux[6]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3075),
.Q(final_result_ieee[58]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ ( .D(
final_result_ieee_Module_Exp_S_mux[7]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3075),
.Q(final_result_ieee[59]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ ( .D(
final_result_ieee_Module_Exp_S_mux[8]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3075),
.Q(final_result_ieee[60]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ ( .D(
final_result_ieee_Module_Exp_S_mux[9]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3075),
.Q(final_result_ieee[61]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ ( .D(
final_result_ieee_Module_Exp_S_mux[10]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3075),
.Q(final_result_ieee[62]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
final_result_ieee_Module_Sgf_S_mux[0]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3081),
.Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
final_result_ieee_Module_Sgf_S_mux[1]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3081),
.Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
final_result_ieee_Module_Sgf_S_mux[2]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3080),
.Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
final_result_ieee_Module_Sgf_S_mux[3]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3080),
.Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
final_result_ieee_Module_Sgf_S_mux[4]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3080),
.Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
final_result_ieee_Module_Sgf_S_mux[5]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3080),
.Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
final_result_ieee_Module_Sgf_S_mux[6]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3080),
.Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
final_result_ieee_Module_Sgf_S_mux[7]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3080),
.Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
final_result_ieee_Module_Sgf_S_mux[8]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3080),
.Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
final_result_ieee_Module_Sgf_S_mux[9]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3080),
.Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
final_result_ieee_Module_Sgf_S_mux[10]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3080),
.Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
final_result_ieee_Module_Sgf_S_mux[11]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3080),
.Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
final_result_ieee_Module_Sgf_S_mux[12]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3079),
.Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
final_result_ieee_Module_Sgf_S_mux[13]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3079),
.Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
final_result_ieee_Module_Sgf_S_mux[14]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3079),
.Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
final_result_ieee_Module_Sgf_S_mux[15]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3079),
.Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
final_result_ieee_Module_Sgf_S_mux[16]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3079),
.Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
final_result_ieee_Module_Sgf_S_mux[17]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3079),
.Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
final_result_ieee_Module_Sgf_S_mux[18]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3079),
.Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
final_result_ieee_Module_Sgf_S_mux[19]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3079),
.Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
final_result_ieee_Module_Sgf_S_mux[21]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3079),
.Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
final_result_ieee_Module_Sgf_S_mux[22]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3078),
.Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
final_result_ieee_Module_Sgf_S_mux[23]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3078),
.Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
final_result_ieee_Module_Sgf_S_mux[24]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3078),
.Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
final_result_ieee_Module_Sgf_S_mux[25]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3078),
.Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
final_result_ieee_Module_Sgf_S_mux[26]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3078),
.Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
final_result_ieee_Module_Sgf_S_mux[27]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3078),
.Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
final_result_ieee_Module_Sgf_S_mux[28]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3078),
.Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
final_result_ieee_Module_Sgf_S_mux[29]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3078),
.Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
final_result_ieee_Module_Sgf_S_mux[31]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3078),
.Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ ( .D(
final_result_ieee_Module_Sgf_S_mux[32]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3077),
.Q(final_result_ieee[32]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ ( .D(
final_result_ieee_Module_Sgf_S_mux[33]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3077),
.Q(final_result_ieee[33]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ ( .D(
final_result_ieee_Module_Sgf_S_mux[34]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3077),
.Q(final_result_ieee[34]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ ( .D(
final_result_ieee_Module_Sgf_S_mux[35]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3077),
.Q(final_result_ieee[35]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ ( .D(
final_result_ieee_Module_Sgf_S_mux[36]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3077),
.Q(final_result_ieee[36]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ ( .D(
final_result_ieee_Module_Sgf_S_mux[37]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3077),
.Q(final_result_ieee[37]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ ( .D(
final_result_ieee_Module_Sgf_S_mux[38]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3076),
.Q(final_result_ieee[38]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ ( .D(
final_result_ieee_Module_Sgf_S_mux[39]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3076),
.Q(final_result_ieee[39]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ ( .D(
final_result_ieee_Module_Sgf_S_mux[40]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3076),
.Q(final_result_ieee[40]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ ( .D(
final_result_ieee_Module_Sgf_S_mux[41]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3076),
.Q(final_result_ieee[41]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ ( .D(
final_result_ieee_Module_Sgf_S_mux[42]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3076),
.Q(final_result_ieee[42]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ ( .D(
final_result_ieee_Module_Sgf_S_mux[43]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3076),
.Q(final_result_ieee[43]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ ( .D(
final_result_ieee_Module_Sgf_S_mux[44]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3076),
.Q(final_result_ieee[44]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ ( .D(
final_result_ieee_Module_Sgf_S_mux[45]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3076),
.Q(final_result_ieee[45]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ ( .D(
final_result_ieee_Module_Sgf_S_mux[46]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3076),
.Q(final_result_ieee[46]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ ( .D(
final_result_ieee_Module_Sgf_S_mux[47]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3076),
.Q(final_result_ieee[47]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ ( .D(
final_result_ieee_Module_Sgf_S_mux[48]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3077),
.Q(final_result_ieee[48]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ ( .D(
final_result_ieee_Module_Sgf_S_mux[49]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3077),
.Q(final_result_ieee[49]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ ( .D(
final_result_ieee_Module_Sgf_S_mux[50]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3077),
.Q(final_result_ieee[50]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ ( .D(
final_result_ieee_Module_Sgf_S_mux[51]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3077),
.Q(final_result_ieee[51]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
final_result_ieee_Module_Sgf_S_mux[20]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3079),
.Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
final_result_ieee_Module_Sgf_S_mux[30]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3849802), .RN(n3078),
.Q(final_result_ieee[30]) );
DFFRX1TS YRegister_Q_reg_54_ ( .D(Data_Y[54]), .CK(YRegister_net3849802),
.RN(n3059), .Q(intDY[54]), .QN(n3039) );
DFFRX1TS YRegister_Q_reg_45_ ( .D(Data_Y[45]), .CK(YRegister_net3849802),
.RN(n3060), .Q(intDY[45]), .QN(n3028) );
DFFRX1TS YRegister_Q_reg_46_ ( .D(Data_Y[46]), .CK(YRegister_net3849802),
.RN(n3060), .Q(intDY[46]), .QN(n3027) );
DFFRX1TS YRegister_Q_reg_1_ ( .D(Data_Y[1]), .CK(YRegister_net3849802), .RN(
n3109), .Q(intDY[1]), .QN(n3049) );
DFFRX1TS YRegister_Q_reg_56_ ( .D(Data_Y[56]), .CK(YRegister_net3849802),
.RN(n3059), .Q(intDY[56]), .QN(n3041) );
DFFRX1TS YRegister_Q_reg_58_ ( .D(Data_Y[58]), .CK(YRegister_net3849802),
.RN(n3059), .Q(intDY[58]), .QN(n3040) );
DFFRX1TS YRegister_Q_reg_60_ ( .D(Data_Y[60]), .CK(YRegister_net3849802),
.RN(n3059), .Q(intDY[60]), .QN(n3038) );
DFFRX1TS YRegister_Q_reg_57_ ( .D(Data_Y[57]), .CK(YRegister_net3849802),
.RN(n3059), .Q(intDY[57]), .QN(n3037) );
DFFRX2TS YRegister_Q_reg_55_ ( .D(Data_Y[55]), .CK(YRegister_net3849802),
.RN(n3059), .Q(intDY[55]), .QN(n3019) );
DFFRX2TS YRegister_Q_reg_53_ ( .D(Data_Y[53]), .CK(YRegister_net3849802),
.RN(n3059), .Q(intDY[53]), .QN(n3018) );
DFFRX2TS YRegister_Q_reg_43_ ( .D(Data_Y[43]), .CK(YRegister_net3849802),
.RN(n3060), .Q(intDY[43]), .QN(n3016) );
DFFRX2TS YRegister_Q_reg_41_ ( .D(Data_Y[41]), .CK(YRegister_net3849802),
.RN(n3061), .Q(intDY[41]), .QN(n3017) );
DFFRX2TS YRegister_Q_reg_39_ ( .D(Data_Y[39]), .CK(YRegister_net3849802),
.RN(n3061), .Q(intDY[39]), .QN(n3008) );
DFFRX2TS YRegister_Q_reg_36_ ( .D(Data_Y[36]), .CK(YRegister_net3849802),
.RN(n3102), .Q(intDY[36]), .QN(n2994) );
DFFRX2TS YRegister_Q_reg_35_ ( .D(Data_Y[35]), .CK(YRegister_net3849802),
.RN(n3102), .Q(intDY[35]), .QN(n2987) );
DFFRX2TS YRegister_Q_reg_34_ ( .D(Data_Y[34]), .CK(YRegister_net3849802),
.RN(n3103), .Q(intDY[34]), .QN(n3004) );
DFFRX2TS YRegister_Q_reg_33_ ( .D(Data_Y[33]), .CK(YRegister_net3849802),
.RN(n3103), .Q(intDY[33]), .QN(n2985) );
DFFRX2TS YRegister_Q_reg_32_ ( .D(Data_Y[32]), .CK(YRegister_net3849802),
.RN(n3103), .Q(intDY[32]), .QN(n3007) );
DFFRX2TS YRegister_Q_reg_31_ ( .D(Data_Y[31]), .CK(YRegister_net3849802),
.RN(n3103), .Q(intDY[31]), .QN(n2986) );
DFFRX2TS YRegister_Q_reg_30_ ( .D(Data_Y[30]), .CK(YRegister_net3849802),
.RN(n3106), .Q(intDY[30]), .QN(n3010) );
DFFRX2TS YRegister_Q_reg_29_ ( .D(Data_Y[29]), .CK(YRegister_net3849802),
.RN(n3105), .Q(intDY[29]), .QN(n2991) );
DFFRX2TS YRegister_Q_reg_28_ ( .D(Data_Y[28]), .CK(YRegister_net3849802),
.RN(n3105), .Q(intDY[28]), .QN(n2997) );
DFFRX2TS YRegister_Q_reg_27_ ( .D(Data_Y[27]), .CK(YRegister_net3849802),
.RN(n3105), .Q(intDY[27]), .QN(n3014) );
DFFRX2TS YRegister_Q_reg_26_ ( .D(Data_Y[26]), .CK(YRegister_net3849802),
.RN(n3106), .Q(intDY[26]), .QN(n2998) );
DFFRX2TS YRegister_Q_reg_25_ ( .D(Data_Y[25]), .CK(YRegister_net3849802),
.RN(n3106), .Q(intDY[25]), .QN(n3005) );
DFFRX2TS YRegister_Q_reg_24_ ( .D(Data_Y[24]), .CK(YRegister_net3849802),
.RN(n3106), .Q(intDY[24]), .QN(n3003) );
DFFRX2TS YRegister_Q_reg_22_ ( .D(Data_Y[22]), .CK(YRegister_net3849802),
.RN(n3106), .Q(intDY[22]), .QN(n3013) );
DFFRX2TS YRegister_Q_reg_21_ ( .D(Data_Y[21]), .CK(YRegister_net3849802),
.RN(n3104), .Q(intDY[21]), .QN(n2990) );
DFFRX2TS YRegister_Q_reg_20_ ( .D(Data_Y[20]), .CK(YRegister_net3849802),
.RN(n3104), .Q(intDY[20]), .QN(n3000) );
DFFRX2TS YRegister_Q_reg_19_ ( .D(Data_Y[19]), .CK(YRegister_net3849802),
.RN(n3104), .Q(intDY[19]), .QN(n3011) );
DFFRX2TS YRegister_Q_reg_18_ ( .D(Data_Y[18]), .CK(YRegister_net3849802),
.RN(n3103), .Q(intDY[18]), .QN(n3001) );
DFFRX2TS YRegister_Q_reg_17_ ( .D(Data_Y[17]), .CK(YRegister_net3849802),
.RN(n3105), .Q(intDY[17]), .QN(n3002) );
DFFRX2TS YRegister_Q_reg_15_ ( .D(Data_Y[15]), .CK(YRegister_net3849802),
.RN(n3104), .Q(intDY[15]), .QN(n2989) );
DFFRX2TS YRegister_Q_reg_14_ ( .D(Data_Y[14]), .CK(YRegister_net3849802),
.RN(n3104), .Q(intDY[14]), .QN(n3012) );
DFFRX2TS YRegister_Q_reg_13_ ( .D(Data_Y[13]), .CK(YRegister_net3849802),
.RN(n3107), .Q(intDY[13]), .QN(n2988) );
DFFRX2TS YRegister_Q_reg_12_ ( .D(Data_Y[12]), .CK(YRegister_net3849802),
.RN(n3107), .Q(intDY[12]), .QN(n2992) );
DFFRX2TS YRegister_Q_reg_11_ ( .D(Data_Y[11]), .CK(YRegister_net3849802),
.RN(n3107), .Q(intDY[11]), .QN(n2995) );
DFFRX2TS YRegister_Q_reg_9_ ( .D(Data_Y[9]), .CK(YRegister_net3849802), .RN(
n3108), .Q(intDY[9]), .QN(n3009) );
DFFRX2TS YRegister_Q_reg_8_ ( .D(Data_Y[8]), .CK(YRegister_net3849802), .RN(
n3108), .Q(intDY[8]), .QN(n2993) );
DFFRX2TS YRegister_Q_reg_3_ ( .D(Data_Y[3]), .CK(YRegister_net3849802), .RN(
n3108), .Q(intDY[3]), .QN(n2984) );
DFFRX2TS YRegister_Q_reg_2_ ( .D(Data_Y[2]), .CK(YRegister_net3849802), .RN(
n3108), .Q(intDY[2]), .QN(n3015) );
DFFRX2TS XRegister_Q_reg_59_ ( .D(Data_X[59]), .CK(YRegister_net3849802),
.RN(n3061), .Q(intDX[59]), .QN(n2908) );
DFFRX2TS XRegister_Q_reg_58_ ( .D(Data_X[58]), .CK(YRegister_net3849802),
.RN(n3061), .QN(n3112) );
DFFRX2TS XRegister_Q_reg_57_ ( .D(Data_X[57]), .CK(YRegister_net3849802),
.RN(n3062), .QN(n3058) );
DFFRX2TS XRegister_Q_reg_55_ ( .D(Data_X[55]), .CK(YRegister_net3849802),
.RN(n3062), .QN(n3111) );
DFFRX2TS XRegister_Q_reg_54_ ( .D(Data_X[54]), .CK(YRegister_net3849802),
.RN(n3062), .Q(intDX[54]), .QN(n2890) );
DFFRX2TS XRegister_Q_reg_51_ ( .D(Data_X[51]), .CK(YRegister_net3849802),
.RN(n3062), .Q(intDX[51]), .QN(n2909) );
DFFRX2TS XRegister_Q_reg_46_ ( .D(Data_X[46]), .CK(YRegister_net3849802),
.RN(n3063), .Q(intDX[46]), .QN(n2926) );
DFFRX2TS XRegister_Q_reg_42_ ( .D(Data_X[42]), .CK(YRegister_net3849802),
.RN(n3063), .Q(intDX[42]), .QN(n2905) );
DFFRX2TS XRegister_Q_reg_41_ ( .D(Data_X[41]), .CK(YRegister_net3849802),
.RN(n3063), .Q(intDX[41]), .QN(n2928) );
DFFRX2TS XRegister_Q_reg_36_ ( .D(Data_X[36]), .CK(YRegister_net3849802),
.RN(n3102), .Q(intDX[36]), .QN(n2960) );
DFFRX2TS XRegister_Q_reg_35_ ( .D(Data_X[35]), .CK(YRegister_net3849802),
.RN(n3102), .Q(intDX[35]), .QN(n2963) );
DFFRX2TS XRegister_Q_reg_33_ ( .D(Data_X[33]), .CK(YRegister_net3849802),
.RN(n3103), .Q(intDX[33]), .QN(n2962) );
DFFRX2TS XRegister_Q_reg_31_ ( .D(Data_X[31]), .CK(YRegister_net3849802),
.RN(n3103), .Q(intDX[31]), .QN(n2961) );
DFFRX2TS XRegister_Q_reg_29_ ( .D(Data_X[29]), .CK(YRegister_net3849802),
.RN(n3106), .Q(intDX[29]), .QN(n2941) );
DFFRX2TS XRegister_Q_reg_26_ ( .D(Data_X[26]), .CK(YRegister_net3849802),
.RN(n3107), .Q(intDX[26]), .QN(n2965) );
DFFRX2TS XRegister_Q_reg_25_ ( .D(Data_X[25]), .CK(YRegister_net3849802),
.RN(n3106), .Q(intDX[25]), .QN(n2969) );
DFFRX2TS XRegister_Q_reg_21_ ( .D(Data_X[21]), .CK(YRegister_net3849802),
.RN(n3104), .Q(intDX[21]), .QN(n2939) );
DFFRX2TS XRegister_Q_reg_18_ ( .D(Data_X[18]), .CK(YRegister_net3849802),
.RN(n3104), .Q(intDX[18]), .QN(n2968) );
DFFRX2TS XRegister_Q_reg_17_ ( .D(Data_X[17]), .CK(YRegister_net3849802),
.RN(n3105), .Q(intDX[17]), .QN(n2964) );
DFFRX2TS XRegister_Q_reg_15_ ( .D(Data_X[15]), .CK(YRegister_net3849802),
.RN(n3105), .Q(intDX[15]), .QN(n2967) );
DFFRX2TS XRegister_Q_reg_13_ ( .D(Data_X[13]), .CK(YRegister_net3849802),
.RN(n3107), .Q(intDX[13]), .QN(n2935) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_51_ ( .D(
Add_Subt_Sgf_module_S_to_D[51]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3098), .Q(
Add_Subt_result[51]) );
DFFRX1TS YRegister_Q_reg_59_ ( .D(Data_Y[59]), .CK(YRegister_net3849802),
.RN(n3059), .Q(intDY[59]), .QN(n3043) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[23]), .CK(clk), .RN(n3072),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[78]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[24]), .CK(clk), .RN(n3072),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[79]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_38_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .CK(clk), .RN(n3070),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[93]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_33_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[33]), .CK(clk), .RN(n3071),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[88]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_34_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .CK(clk), .RN(n3071),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[89]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_36_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .CK(clk), .RN(n3070),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[91]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_37_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .CK(clk), .RN(n3070),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[92]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(
Add_Subt_Sgf_module_S_to_D[4]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3098), .Q(
Add_Subt_result[4]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(
Add_Subt_Sgf_module_S_to_D[2]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3093), .Q(
Add_Subt_result[2]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(
Add_Subt_Sgf_module_S_to_D[20]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3099), .Q(
Add_Subt_result[20]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(
Add_Subt_Sgf_module_S_to_D[9]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3092), .Q(
Add_Subt_result[9]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(
Add_Subt_Sgf_module_S_to_D[14]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3096), .Q(
Add_Subt_result[14]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(
Add_Subt_Sgf_module_S_to_D[1]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3092), .Q(
Add_Subt_result[1]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(
Add_Subt_Sgf_module_S_to_D[23]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3092), .Q(
Add_Subt_result[23]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(
Add_Subt_Sgf_module_S_to_D[7]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3092), .Q(
Add_Subt_result[7]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(
Add_Subt_Sgf_module_S_to_D[18]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3091), .Q(
Add_Subt_result[18]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(
Add_Subt_Sgf_module_S_to_D[17]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3091), .Q(
Add_Subt_result[17]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[22]), .CK(clk), .RN(n3072),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[77]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(
Add_Subt_Sgf_module_S_to_D[5]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3097), .Q(
Add_Subt_result[5]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(
Add_Subt_Sgf_module_S_to_D[21]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3099), .Q(
Add_Subt_result[21]) );
DFFRX1TS YRegister_Q_reg_4_ ( .D(Data_Y[4]), .CK(YRegister_net3849802), .RN(
n3109), .Q(intDY[4]), .QN(n923) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[19]), .CK(clk), .RN(n3072),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[74]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[16]), .CK(clk), .RN(n3072),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[71]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_29_ ( .D(
Add_Subt_Sgf_module_S_to_D[29]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3096), .Q(
Add_Subt_result[29]) );
DFFRX1TS YRegister_Q_reg_37_ ( .D(Data_Y[37]), .CK(YRegister_net3849802),
.RN(n3102), .Q(intDY[37]), .QN(n924) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(
Add_Subt_Sgf_module_S_to_D[0]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3099), .Q(
Add_Subt_result[0]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[7]), .CK(clk), .RN(n3073),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[62]) );
DFFRX1TS XRegister_Q_reg_61_ ( .D(Data_X[61]), .CK(YRegister_net3849802),
.RN(n3061), .Q(intDX[61]), .QN(n888) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[9]), .CK(clk), .RN(n3073),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[64]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[10]), .CK(clk), .RN(n3073),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[65]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[12]), .CK(clk), .RN(n3073),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[67]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[13]), .CK(clk), .RN(n3073),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[68]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(
Barrel_Shifter_module_Data_Reg[2]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3081), .Q(
Sgf_normalized_result[2]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(
Exp_Operation_Module_Data_S[0]), .CK(
Exp_Operation_Module_exp_result_net3849843), .RN(n3094), .Q(
exp_oper_result[0]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(
Exp_Operation_Module_Data_S[1]), .CK(
Exp_Operation_Module_exp_result_net3849843), .RN(n3094), .Q(
exp_oper_result[1]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(
Exp_Operation_Module_Data_S[2]), .CK(
Exp_Operation_Module_exp_result_net3849843), .RN(n3090), .Q(
exp_oper_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(
Barrel_Shifter_module_Data_Reg[0]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3081), .Q(
Sgf_normalized_result[0]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(
Barrel_Shifter_module_Data_Reg[1]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3081), .Q(
Sgf_normalized_result[1]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(
Barrel_Shifter_module_Data_Reg[32]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3087), .Q(
Sgf_normalized_result[32]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(
Barrel_Shifter_module_Data_Reg[22]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3085), .Q(
Sgf_normalized_result[22]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(
Barrel_Shifter_module_Data_Reg[50]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3100), .Q(
Sgf_normalized_result[50]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(
Barrel_Shifter_module_Data_Reg[4]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3082), .Q(
Sgf_normalized_result[4]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_53_ ( .D(
Barrel_Shifter_module_Data_Reg[53]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3101), .Q(
Sgf_normalized_result[53]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(
Barrel_Shifter_module_Data_Reg[49]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3100), .Q(
Sgf_normalized_result[49]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(
Barrel_Shifter_module_Data_Reg[5]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3082), .Q(
Sgf_normalized_result[5]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(
Barrel_Shifter_module_Data_Reg[52]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3101), .Q(
Sgf_normalized_result[52]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(
Barrel_Shifter_module_Data_Reg[48]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3100), .Q(
Sgf_normalized_result[48]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(
Barrel_Shifter_module_Data_Reg[6]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3082), .Q(
Sgf_normalized_result[6]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(
Barrel_Shifter_module_Data_Reg[51]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3100), .Q(
Sgf_normalized_result[51]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(
Barrel_Shifter_module_Data_Reg[3]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3082), .Q(
Sgf_normalized_result[3]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(n3114), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3100), .Q(
Sgf_normalized_result[47]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n3115), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3082), .Q(
Sgf_normalized_result[7]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(n3116), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3090), .Q(
Sgf_normalized_result[46]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n3117), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3083), .Q(
Sgf_normalized_result[8]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(n3118), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3090), .Q(
Sgf_normalized_result[45]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n3119), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3083), .Q(
Sgf_normalized_result[9]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(n3120), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3090), .Q(
Sgf_normalized_result[44]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n3121), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3083), .Q(
Sgf_normalized_result[10]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(n3122), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3090), .Q(
Sgf_normalized_result[43]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n3123), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3083), .Q(
Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(n3124), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3089), .Q(
Sgf_normalized_result[42]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n3125), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3083), .Q(
Sgf_normalized_result[12]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(n3126), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3089), .Q(
Sgf_normalized_result[41]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n3127), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3084), .Q(
Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(n3128), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3089), .Q(
Sgf_normalized_result[40]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n3129), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3084), .Q(
Sgf_normalized_result[14]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(n3130), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3089), .Q(
Sgf_normalized_result[39]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n3131), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3084), .Q(
Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(
Barrel_Shifter_module_Data_Reg[38]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3089), .Q(
Sgf_normalized_result[38]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(
Barrel_Shifter_module_Data_Reg[16]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3084), .Q(
Sgf_normalized_result[16]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(
Barrel_Shifter_module_Data_Reg[37]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3088), .Q(
Sgf_normalized_result[37]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(
Barrel_Shifter_module_Data_Reg[17]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3084), .Q(
Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(
Barrel_Shifter_module_Data_Reg[36]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3088), .Q(
Sgf_normalized_result[36]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(
Barrel_Shifter_module_Data_Reg[18]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3085), .Q(
Sgf_normalized_result[18]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(
Barrel_Shifter_module_Data_Reg[35]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3088), .Q(
Sgf_normalized_result[35]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(
Barrel_Shifter_module_Data_Reg[19]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3085), .Q(
Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(
Barrel_Shifter_module_Data_Reg[34]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3088), .Q(
Sgf_normalized_result[34]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(
Barrel_Shifter_module_Data_Reg[20]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3085), .Q(
Sgf_normalized_result[20]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(
Barrel_Shifter_module_Data_Reg[33]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3088), .Q(
Sgf_normalized_result[33]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(
Barrel_Shifter_module_Data_Reg[21]), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3085), .Q(
Sgf_normalized_result[21]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n3133), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3086), .Q(
Sgf_normalized_result[23]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(n3134), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3087), .Q(
Sgf_normalized_result[30]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(n3136), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3087), .Q(
Sgf_normalized_result[29]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n3137), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3086), .Q(
Sgf_normalized_result[25]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(n3138), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3087), .Q(
Sgf_normalized_result[28]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(n3140), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3086), .Q(
Sgf_normalized_result[27]) );
DFFRX1TS XRegister_Q_reg_62_ ( .D(Data_X[62]), .CK(YRegister_net3849802),
.RN(n3061), .Q(intDX[62]), .QN(n887) );
DFFRX1TS Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n86), .CK(
Exp_Operation_Module_exp_result_net3849843), .RN(n3074), .Q(
overflow_flag) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_39_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .CK(clk), .RN(n3070),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[94]), .QN(n2956) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_47_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .CK(clk), .RN(n3069),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[102]), .QN(n2957) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(
Add_Subt_Sgf_module_S_to_D[25]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3092), .Q(
Add_Subt_result[25]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_30_ ( .D(
Add_Subt_Sgf_module_S_to_D[30]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3097), .Q(
Add_Subt_result[30]) );
DFFRX1TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_5_ ( .D(
Leading_Zero_Detector_Module_Codec_to_Reg[5]), .CK(
Leading_Zero_Detector_Module_Output_Reg_net3849807), .RN(n3081), .Q(
LZA_output[5]), .QN(n2922) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_32_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .CK(clk), .RN(n3071),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[87]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(
Add_Subt_Sgf_module_S_to_D[3]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3099), .Q(
Add_Subt_result[3]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(
Add_Subt_Sgf_module_S_to_D[8]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3092), .Q(
Add_Subt_result[8]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[15]), .CK(clk), .RN(n3073),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[70]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[8]), .CK(clk), .RN(n3073),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[63]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(
Add_Subt_Sgf_module_S_to_D[19]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3099), .Q(
Add_Subt_result[19]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(
Add_Subt_Sgf_module_S_to_D[6]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3097), .Q(
Add_Subt_result[6]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[18]), .CK(clk), .RN(n3072),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[73]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[17]), .CK(clk), .RN(n3072),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[72]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[21]), .CK(clk), .RN(n3072),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[76]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[20]), .CK(clk), .RN(n3072),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[75]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[14]), .CK(clk), .RN(n3073),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[69]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[11]), .CK(clk), .RN(n3073),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[66]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(n3139), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3086), .Q(
Sgf_normalized_result[26]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n3135), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3086), .Q(
Sgf_normalized_result[24]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(n3132), .CK(
Barrel_Shifter_module_Output_Reg_net3849825), .RN(n3087), .Q(
Sgf_normalized_result[31]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_31_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .CK(clk), .RN(n3071),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[86]), .QN(n2886) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_40_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .CK(clk), .RN(n3070),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[95]), .QN(n2949) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[25]), .CK(clk), .RN(n3072),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[80]), .QN(n2974) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_26_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[26]), .CK(clk), .RN(n3071),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[81]), .QN(n2973) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_44_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .CK(clk), .RN(n3070),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[99]), .QN(n2951) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_45_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .CK(clk), .RN(n3070),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[100]), .QN(n2950) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_46_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .CK(clk), .RN(n3069),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[101]), .QN(n2952) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_41_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .CK(clk), .RN(n3070),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[96]), .QN(n2954) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_42_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .CK(clk), .RN(n3070),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[97]), .QN(n2953) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_43_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .CK(clk), .RN(n3070),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[98]), .QN(n2955) );
DFFRX1TS Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n861), .CK(
Exp_Operation_Module_exp_result_net3849843), .RN(n3074), .Q(
underflow_flag), .QN(n3056) );
DFFRX4TS Sel_B_Q_reg_1_ ( .D(n864), .CK(FS_Module_net3849879), .RN(n860),
.Q(FSM_selector_B[1]), .QN(n2914) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(
Exp_Operation_Module_Data_S[3]), .CK(
Exp_Operation_Module_exp_result_net3849843), .RN(n3094), .Q(
exp_oper_result[3]), .QN(n882) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(FS_Module_state_next[2]), .CK(
FS_Module_net3849879), .RN(n3101), .Q(FS_Module_state_reg[2]), .QN(
n2983) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_54_ ( .D(
Add_Subt_Sgf_module_S_to_D[54]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3099), .Q(
Add_Subt_result[54]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_53_ ( .D(
Add_Subt_Sgf_module_S_to_D[53]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3098), .Q(
Add_Subt_result[53]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_52_ ( .D(
Add_Subt_Sgf_module_S_to_D[52]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3098), .Q(
Add_Subt_result[52]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_46_ ( .D(
Add_Subt_Sgf_module_S_to_D[46]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3098), .Q(
Add_Subt_result[46]), .QN(n2913) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_44_ ( .D(
Add_Subt_Sgf_module_S_to_D[44]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3098), .Q(
Add_Subt_result[44]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_42_ ( .D(
Add_Subt_Sgf_module_S_to_D[42]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3097), .Q(
Add_Subt_result[42]), .QN(n3055) );
DFFRX2TS Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ ( .D(
Add_Subt_Sgf_module_S_to_D[55]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3101), .Q(
add_overflow_flag), .QN(n2915) );
DFFSX1TS R_0 ( .D(n3057), .CK(YRegister_net3849802), .SN(n3102), .Q(n3110)
);
DFFRX1TS XRegister_Q_reg_0_ ( .D(Data_X[0]), .CK(YRegister_net3849802), .RN(
n3109), .Q(intDX[0]), .QN(n2958) );
DFFRX1TS XRegister_Q_reg_1_ ( .D(Data_X[1]), .CK(YRegister_net3849802), .RN(
n3109), .Q(intDX[1]), .QN(n2933) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_26_ ( .D(
Add_Subt_Sgf_module_S_to_D[26]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3092), .Q(
Add_Subt_result[26]), .QN(n2916) );
DFFRX2TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ ( .D(
Leading_Zero_Detector_Module_Codec_to_Reg[4]), .CK(
Leading_Zero_Detector_Module_Output_Reg_net3849807), .RN(n3092), .Q(
LZA_output[4]), .QN(n2919) );
DFFRX1TS YRegister_Q_reg_62_ ( .D(Data_Y[62]), .CK(YRegister_net3849802),
.RN(n3059), .Q(intDY[62]), .QN(n3044) );
DFFRX1TS YRegister_Q_reg_61_ ( .D(Data_Y[61]), .CK(YRegister_net3849802),
.RN(n3059), .Q(intDY[61]), .QN(n3045) );
DFFRX1TS YRegister_Q_reg_51_ ( .D(Data_Y[51]), .CK(YRegister_net3849802),
.RN(n3060), .Q(intDY[51]), .QN(n3033) );
DFFRX1TS YRegister_Q_reg_50_ ( .D(Data_Y[50]), .CK(YRegister_net3849802),
.RN(n3060), .Q(intDY[50]), .QN(n3030) );
DFFRX1TS YRegister_Q_reg_49_ ( .D(Data_Y[49]), .CK(YRegister_net3849802),
.RN(n3060), .Q(intDY[49]), .QN(n3029) );
DFFRX1TS YRegister_Q_reg_47_ ( .D(Data_Y[47]), .CK(YRegister_net3849802),
.RN(n3060), .Q(intDY[47]), .QN(n3036) );
DFFRX1TS YRegister_Q_reg_40_ ( .D(Data_Y[40]), .CK(YRegister_net3849802),
.RN(n3061), .Q(intDY[40]), .QN(n3035) );
DFFRX1TS YRegister_Q_reg_10_ ( .D(Data_Y[10]), .CK(YRegister_net3849802),
.RN(n3107), .Q(intDY[10]), .QN(n3047) );
DFFRX1TS XRegister_Q_reg_56_ ( .D(Data_X[56]), .CK(YRegister_net3849802),
.RN(n3062), .Q(intDX[56]), .QN(n2889) );
DFFRX2TS Sel_B_Q_reg_0_ ( .D(n865), .CK(FS_Module_net3849879), .RN(n860),
.Q(FSM_selector_B[0]), .QN(n2917) );
DFFRX4TS FS_Module_state_reg_reg_0_ ( .D(FS_Module_state_next[0]), .CK(
FS_Module_net3849879), .RN(n3101), .Q(FS_Module_state_reg[0]), .QN(
n2906) );
DFFRX2TS XRegister_Q_reg_63_ ( .D(Data_X[63]), .CK(YRegister_net3849802),
.RN(n3102), .Q(intDX[63]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_48_ ( .D(
Add_Subt_Sgf_module_S_to_D[48]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3098), .Q(
Add_Subt_result[48]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_50_ ( .D(
Add_Subt_Sgf_module_S_to_D[50]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3849825), .RN(n3098), .Q(
Add_Subt_result[50]), .QN(n3025) );
DFFRX4TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ ( .D(
Leading_Zero_Detector_Module_Codec_to_Reg[3]), .CK(
Leading_Zero_Detector_Module_Output_Reg_net3849807), .RN(n3091), .Q(
LZA_output[3]), .QN(n881) );
DFFRX4TS Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(
Exp_Operation_Module_Data_S[4]), .CK(
Exp_Operation_Module_exp_result_net3849843), .RN(n3094), .Q(
exp_oper_result[4]) );
OR3X4TS U1327 ( .A(n2156), .B(Exp_Operation_Module_Data_S[10]), .C(n1020),
.Y(n1022) );
CLKBUFX2TS U1328 ( .A(n1026), .Y(n902) );
BUFX3TS U1329 ( .A(n2634), .Y(n2632) );
BUFX3TS U1330 ( .A(n2634), .Y(n2637) );
NAND2X2TS U1331 ( .A(n1646), .B(n2126), .Y(n1026) );
NAND2X1TS U1332 ( .A(n1240), .B(n1239), .Y(n2677) );
BUFX3TS U1333 ( .A(n2303), .Y(n2634) );
ADDFHX2TS U1334 ( .A(n1001), .B(n1000), .CI(n999), .CO(n1013), .S(
Exp_Operation_Module_Data_S[9]) );
ADDFHX2TS U1335 ( .A(n997), .B(n996), .CI(n995), .CO(n999), .S(
Exp_Operation_Module_Data_S[8]) );
CMPR32X2TS U1336 ( .A(n1004), .B(n1003), .C(n1002), .CO(n995), .S(
Exp_Operation_Module_Data_S[7]) );
INVX4TS U1337 ( .A(n1950), .Y(n2391) );
INVX2TS U1338 ( .A(n2392), .Y(n2494) );
NAND3X1TS U1339 ( .A(n2281), .B(n2290), .C(n2161), .Y(n2298) );
CMPR32X2TS U1340 ( .A(n1007), .B(n1006), .C(n1005), .CO(n982), .S(
Exp_Operation_Module_Data_S[4]) );
CMPR32X2TS U1341 ( .A(n1010), .B(n1009), .C(n1008), .CO(n978), .S(
Exp_Operation_Module_Data_S[2]) );
NAND2XLTS U1342 ( .A(n2394), .B(n1517), .Y(n1519) );
NAND2X1TS U1343 ( .A(n1930), .B(n1944), .Y(n2343) );
CMPR32X2TS U1344 ( .A(n987), .B(n986), .C(n985), .CO(n1008), .S(
Exp_Operation_Module_Data_S[1]) );
OAI21X2TS U1345 ( .A0(n2513), .A1(n1380), .B0(n1379), .Y(n1450) );
CMPR32X2TS U1346 ( .A(n1012), .B(n970), .C(n1011), .CO(n985), .S(
Exp_Operation_Module_Data_S[0]) );
NAND2X1TS U1347 ( .A(n1809), .B(n1798), .Y(n1929) );
NAND2X4TS U1348 ( .A(n1116), .B(n935), .Y(n1099) );
AOI21X1TS U1349 ( .A0(n1407), .A1(n1395), .B0(n1394), .Y(n1447) );
NOR2X1TS U1350 ( .A(n1410), .B(n1412), .Y(n1395) );
NOR2X1TS U1351 ( .A(n2429), .B(n2424), .Y(n1503) );
NOR2X1TS U1352 ( .A(n2521), .B(n2516), .Y(n1378) );
NOR2X1TS U1353 ( .A(n1437), .B(n1441), .Y(n1443) );
NOR2X1TS U1354 ( .A(n2508), .B(n2503), .Y(n1406) );
NOR2X1TS U1355 ( .A(n2417), .B(n2412), .Y(n2400) );
NOR2X1TS U1356 ( .A(n2440), .B(n2435), .Y(n2423) );
NOR2X1TS U1357 ( .A(n2467), .B(n2462), .Y(n2450) );
NOR2X1TS U1358 ( .A(n2484), .B(n2486), .Y(n2473) );
OAI211X4TS U1359 ( .A0(FS_Module_state_reg[1]), .A1(FS_Module_state_reg[2]),
.B0(n969), .C0(n1237), .Y(n970) );
NOR2X1TS U1360 ( .A(n1429), .B(n1428), .Y(n1437) );
NAND2X1TS U1361 ( .A(n1537), .B(n1536), .Y(n1673) );
NOR2X1TS U1362 ( .A(n1680), .B(n1679), .Y(n1770) );
NOR2X1TS U1363 ( .A(n1398), .B(n1397), .Y(n1420) );
NOR2X1TS U1364 ( .A(n1529), .B(n1528), .Y(n1549) );
NOR2X1TS U1365 ( .A(n1537), .B(n1536), .Y(n1671) );
INVX4TS U1366 ( .A(n1984), .Y(n1952) );
INVX4TS U1367 ( .A(n1984), .Y(n1454) );
INVX4TS U1368 ( .A(n1984), .Y(n1382) );
INVX4TS U1369 ( .A(n1984), .Y(n1788) );
INVX2TS U1370 ( .A(n1969), .Y(n1964) );
INVX2TS U1371 ( .A(n1641), .Y(n2553) );
NOR2XLTS U1372 ( .A(n2193), .B(intDX[10]), .Y(n2194) );
OAI21XLTS U1373 ( .A0(intDY[43]), .A1(n2944), .B0(intDY[42]), .Y(n2250) );
OAI21XLTS U1374 ( .A0(intDY[53]), .A1(n2948), .B0(intDY[52]), .Y(n2278) );
NOR2XLTS U1375 ( .A(n933), .B(n1081), .Y(n934) );
NAND2X1TS U1376 ( .A(n1087), .B(n928), .Y(n929) );
OAI21XLTS U1377 ( .A0(n2424), .A1(n2430), .B0(n2425), .Y(n1502) );
OAI21XLTS U1378 ( .A0(n2516), .A1(n2522), .B0(n2517), .Y(n1377) );
CLKINVX3TS U1379 ( .A(n2920), .Y(n1535) );
CLKINVX3TS U1380 ( .A(n2920), .Y(n1786) );
NOR2XLTS U1381 ( .A(n2280), .B(n2279), .Y(n2293) );
AOI211XLTS U1382 ( .A0(n2129), .A1(n2128), .B0(n2127), .C0(n2126), .Y(n2130)
);
NOR2X1TS U1383 ( .A(n1391), .B(n1390), .Y(n1410) );
OR2X2TS U1384 ( .A(n2842), .B(n2841), .Y(n2766) );
OR2X1TS U1385 ( .A(n1661), .B(n2726), .Y(n884) );
NAND2X1TS U1386 ( .A(n1090), .B(n2916), .Y(n1081) );
XOR2X1TS U1387 ( .A(n1788), .B(n1534), .Y(n1537) );
XOR2X1TS U1388 ( .A(n1952), .B(n1783), .Y(n1790) );
NOR2X1TS U1389 ( .A(n1801), .B(n1800), .Y(n1927) );
NOR2XLTS U1390 ( .A(n922), .B(n2983), .Y(n1023) );
CLKINVX3TS U1391 ( .A(n2152), .Y(n2842) );
OAI21XLTS U1392 ( .A0(n2048), .A1(n2087), .B0(n1702), .Y(n1703) );
OAI21XLTS U1393 ( .A0(n2017), .A1(n2087), .B0(n1719), .Y(n1720) );
OAI21XLTS U1394 ( .A0(n2915), .A1(FS_Module_state_reg[0]), .B0(n1298), .Y(
n1299) );
AOI21X2TS U1395 ( .A0(n1450), .A1(n1449), .B0(n1448), .Y(n2392) );
NAND2X1TS U1396 ( .A(n1525), .B(n1524), .Y(n2388) );
OAI21X2TS U1397 ( .A0(n2391), .A1(n1782), .B0(n1781), .Y(n2364) );
OAI21XLTS U1398 ( .A0(n2391), .A1(n2343), .B0(n2342), .Y(n2348) );
OAI21XLTS U1399 ( .A0(n2525), .A1(n2521), .B0(n2522), .Y(n2520) );
OAI21XLTS U1400 ( .A0(n2512), .A1(n2508), .B0(n2509), .Y(n2507) );
AND4X1TS U1401 ( .A(Exp_Operation_Module_Data_S[9]), .B(
Exp_Operation_Module_Data_S[8]), .C(Exp_Operation_Module_Data_S[7]),
.D(n2154), .Y(n2155) );
OAI211XLTS U1402 ( .A0(n1885), .A1(n2048), .B0(n1320), .C0(n1319), .Y(n1321)
);
OAI21XLTS U1403 ( .A0(n2483), .A1(n2479), .B0(n2480), .Y(n2478) );
AND3X1TS U1404 ( .A(n1158), .B(n1105), .C(n1104), .Y(n1129) );
OAI211XLTS U1405 ( .A0(n2043), .A1(n2141), .B0(n2024), .C0(n2023), .Y(n3139)
);
AND3X1TS U1406 ( .A(n2156), .B(Exp_Operation_Module_Data_S[10]), .C(n2155),
.Y(n86) );
OAI211XLTS U1407 ( .A0(n2579), .A1(n2114), .B0(n902), .C0(n2105), .Y(
Barrel_Shifter_module_Data_Reg[34]) );
OAI211XLTS U1408 ( .A0(n1723), .A1(n920), .B0(n1722), .C0(n1721), .Y(n3125)
);
OAI211XLTS U1409 ( .A0(n2571), .A1(n2152), .B0(n2151), .C0(n902), .Y(
Barrel_Shifter_module_Data_Reg[32]) );
OAI211XLTS U1410 ( .A0(n2726), .A1(n1900), .B0(n1899), .C0(n1898), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[24]) );
OAI21XLTS U1411 ( .A0(n2647), .A1(n2711), .B0(n1650), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[52]) );
NAND4BX1TS U1412 ( .AN(n1108), .B(n1129), .C(n1107), .D(n1131), .Y(
Leading_Zero_Detector_Module_Codec_to_Reg[3]) );
XOR2X1TS U1413 ( .A(n1808), .B(n1807), .Y(Add_Subt_Sgf_module_S_to_D[44]) );
XOR2X1TS U1414 ( .A(n1819), .B(n1818), .Y(Add_Subt_Sgf_module_S_to_D[42]) );
XOR2X1TS U1415 ( .A(n2410), .B(n2409), .Y(Add_Subt_Sgf_module_S_to_D[29]) );
XOR2X1TS U1416 ( .A(n2353), .B(n1835), .Y(Add_Subt_Sgf_module_S_to_D[43]) );
XOR2X1TS U1417 ( .A(n2460), .B(n2459), .Y(Add_Subt_Sgf_module_S_to_D[21]) );
OAI21X1TS U1418 ( .A0(n2433), .A1(n2429), .B0(n2430), .Y(n2428) );
XOR2X1TS U1419 ( .A(n1436), .B(n1435), .Y(Add_Subt_Sgf_module_S_to_D[14]) );
AO22X1TS U1420 ( .A0(n2115), .A1(n1348), .B0(n2152), .B1(n2116), .Y(
Barrel_Shifter_module_Data_Reg[16]) );
XOR2X1TS U1421 ( .A(n1555), .B(n1554), .Y(Add_Subt_Sgf_module_S_to_D[34]) );
XOR2X1TS U1422 ( .A(n1677), .B(n1563), .Y(Add_Subt_Sgf_module_S_to_D[35]) );
XOR2X1TS U1423 ( .A(n1544), .B(n1543), .Y(Add_Subt_Sgf_module_S_to_D[36]) );
INVX2TS U1424 ( .A(n1561), .Y(n1677) );
OAI21X1TS U1425 ( .A0(n2602), .A1(n908), .B0(n2147), .Y(n2148) );
OAI211X1TS U1426 ( .A0(n2725), .A1(n2568), .B0(n1560), .C0(n1559), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[53]) );
INVX4TS U1427 ( .A(n2637), .Y(n2633) );
OAI211X1TS U1428 ( .A0(n2070), .A1(n2141), .B0(n2057), .C0(n2056), .Y(n3135)
);
INVX4TS U1429 ( .A(n2637), .Y(n2635) );
OAI21X1TS U1430 ( .A0(n1745), .A1(n3053), .B0(n1744), .Y(n3140) );
INVX4TS U1431 ( .A(n2634), .Y(n2563) );
NAND3X1TS U1432 ( .A(n2606), .B(n965), .C(Add_Subt_result[16]), .Y(n966) );
AOI211X1TS U1433 ( .A0(n2092), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[79]), .B0(n2055), .C0(n2054), .Y(n2056) );
INVX2TS U1434 ( .A(n2606), .Y(n1150) );
OAI21X1TS U1435 ( .A0(n2138), .A1(n2141), .B0(n2081), .Y(n2091) );
OAI211X1TS U1436 ( .A0(n2066), .A1(n2065), .B0(n2064), .C0(n2081), .Y(n2067)
);
OAI211X1TS U1437 ( .A0(n2039), .A1(n2065), .B0(n2038), .C0(n2081), .Y(n2040)
);
OAI211X1TS U1438 ( .A0(n2030), .A1(n2065), .B0(n2029), .C0(n2081), .Y(n2031)
);
OAI21X1TS U1439 ( .A0(n2036), .A1(n2087), .B0(n1752), .Y(n1753) );
AO22XLTS U1440 ( .A0(n2860), .A1(Add_Subt_result[1]), .B0(n896), .B1(
Add_Subt_result[53]), .Y(n2864) );
OAI21X1TS U1441 ( .A0(n2027), .A1(n2087), .B0(n1765), .Y(n1766) );
AOI211X1TS U1442 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[63]), .A1(
FSM_selector_B[1]), .B0(n1865), .C0(n1864), .Y(n1871) );
INVX4TS U1443 ( .A(n2787), .Y(n1651) );
OAI21X1TS U1444 ( .A0(n2005), .A1(n2087), .B0(n1693), .Y(n1696) );
INVX4TS U1445 ( .A(n2787), .Y(n1244) );
OAI211X1TS U1446 ( .A0(n2017), .A1(n2074), .B0(n2016), .C0(n2015), .Y(n2035)
);
NOR2X4TS U1447 ( .A(n1207), .B(n2726), .Y(n2645) );
BUFX4TS U1448 ( .A(n2766), .Y(n2787) );
AND2X2TS U1449 ( .A(n908), .B(n2842), .Y(n1348) );
INVX4TS U1450 ( .A(n1558), .Y(n2726) );
OAI21X1TS U1451 ( .A0(n1674), .A1(n1673), .B0(n1672), .Y(n1777) );
OAI211X1TS U1452 ( .A0(n1643), .A1(n2559), .B0(n1642), .C0(n2550), .Y(
FS_Module_state_next[3]) );
CLKBUFX2TS U1453 ( .A(n1692), .Y(n907) );
NAND2BX1TS U1454 ( .AN(n1100), .B(Add_Subt_result[43]), .Y(n1079) );
CLKBUFX2TS U1455 ( .A(n2058), .Y(n906) );
BUFX6TS U1456 ( .A(n2114), .Y(n2152) );
NAND2X2TS U1457 ( .A(n1688), .B(n1694), .Y(n1025) );
XOR2X1TS U1458 ( .A(n1454), .B(n1400), .Y(n1402) );
BUFX3TS U1459 ( .A(n970), .Y(n917) );
OR2X4TS U1460 ( .A(add_overflow_flag), .B(n1040), .Y(n2114) );
INVX3TS U1461 ( .A(n973), .Y(n2129) );
NOR2X1TS U1462 ( .A(n2225), .B(intDX[24]), .Y(n2168) );
AOI2BB2X1TS U1463 ( .B0(intDY[53]), .B1(n2948), .A0N(intDX[52]), .A1N(n2278),
.Y(n2280) );
OAI21X1TS U1464 ( .A0(r_mode[1]), .A1(n1565), .B0(sign_final_result), .Y(
n1566) );
OAI21X1TS U1465 ( .A0(r_mode[0]), .A1(n1564), .B0(n2911), .Y(n1567) );
NAND2BX1TS U1466 ( .AN(intDY[13]), .B(intDX[13]), .Y(n2178) );
OAI21X1TS U1467 ( .A0(intDY[29]), .A1(n2941), .B0(intDY[28]), .Y(n2166) );
OAI21X1TS U1468 ( .A0(intDY[23]), .A1(n3050), .B0(intDY[22]), .Y(n2220) );
OAI21X1TS U1469 ( .A0(n2410), .A1(n2406), .B0(n2407), .Y(n2405) );
OAI211X1TS U1470 ( .A0(n2119), .A1(n2118), .B0(n2117), .C0(n902), .Y(
Barrel_Shifter_module_Data_Reg[38]) );
OAI21X1TS U1471 ( .A0(n2411), .A1(n2417), .B0(n2418), .Y(n2416) );
OAI21X1TS U1472 ( .A0(n2460), .A1(n2456), .B0(n2457), .Y(n2455) );
OAI211X1TS U1473 ( .A0(n2665), .A1(n2711), .B0(n1663), .C0(n1662), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[49]) );
OAI211X1TS U1474 ( .A0(n2659), .A1(n2711), .B0(n1670), .C0(n1669), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[50]) );
OAI21X1TS U1475 ( .A0(n2652), .A1(n2711), .B0(n1657), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[51]) );
OAI211X1TS U1476 ( .A0(n1885), .A1(n2060), .B0(n1884), .C0(n1883), .Y(n3116)
);
INVX1TS U1477 ( .A(n1125), .Y(n1082) );
OAI211X1TS U1478 ( .A0(n2070), .A1(n2137), .B0(n2069), .C0(n2068), .Y(n3134)
);
OAI211X1TS U1479 ( .A0(n2034), .A1(n2137), .B0(n2033), .C0(n2032), .Y(n3136)
);
OAI211X1TS U1480 ( .A0(n2576), .A1(n2152), .B0(n902), .C0(n2101), .Y(
Barrel_Shifter_module_Data_Reg[33]) );
OAI211X1TS U1481 ( .A0(n2043), .A1(n2137), .B0(n2042), .C0(n2041), .Y(n3138)
);
OAI211X1TS U1482 ( .A0(n1769), .A1(n920), .B0(n1768), .C0(n1767), .Y(n3119)
);
NAND3BX1TS U1483 ( .AN(n2729), .B(n2728), .C(n2727), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[20]) );
OAI21X1TS U1484 ( .A0(n2391), .A1(n2387), .B0(n2388), .Y(n2386) );
OAI211X1TS U1485 ( .A0(n2676), .A1(n1921), .B0(n1920), .C0(n1919), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[27]) );
OAI211X1TS U1486 ( .A0(n1699), .A1(n920), .B0(n1698), .C0(n1697), .Y(n3127)
);
OAI21X1TS U1487 ( .A0(n2461), .A1(n2467), .B0(n2468), .Y(n2466) );
OAI211X1TS U1488 ( .A0(n1706), .A1(n920), .B0(n1705), .C0(n1704), .Y(n3129)
);
OAI211X1TS U1489 ( .A0(n1885), .A1(n2017), .B0(n1838), .C0(n1837), .Y(n3124)
);
OAI211X1TS U1490 ( .A0(n1741), .A1(n920), .B0(n1740), .C0(n1739), .Y(n3123)
);
OAI211X1TS U1491 ( .A0(n1885), .A1(n1843), .B0(n1842), .C0(n1841), .Y(n3122)
);
OAI211X1TS U1492 ( .A0(n2586), .A1(n2114), .B0(n902), .C0(n2113), .Y(
Barrel_Shifter_module_Data_Reg[36]) );
OAI211X1TS U1493 ( .A0(n1885), .A1(n2036), .B0(n1856), .C0(n1855), .Y(n3120)
);
OAI211X1TS U1494 ( .A0(n2589), .A1(n2152), .B0(n902), .C0(n2109), .Y(
Barrel_Shifter_module_Data_Reg[37]) );
OAI211X1TS U1495 ( .A0(n1756), .A1(n920), .B0(n1755), .C0(n1754), .Y(n3121)
);
OAI211X1TS U1496 ( .A0(n2582), .A1(n2114), .B0(n902), .C0(n2097), .Y(
Barrel_Shifter_module_Data_Reg[35]) );
OAI211X1TS U1497 ( .A0(n1885), .A1(n2027), .B0(n1852), .C0(n1851), .Y(n3118)
);
OAI211X1TS U1498 ( .A0(n2726), .A1(n1915), .B0(n1914), .C0(n1913), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[19]) );
OAI211XLTS U1499 ( .A0(n2610), .A1(n1120), .B0(n1119), .C0(n1118), .Y(n1126)
);
OAI211X1TS U1500 ( .A0(n2005), .A1(n1885), .B0(n1306), .C0(n1305), .Y(n1307)
);
OAI21X1TS U1501 ( .A0(n2142), .A1(n2137), .B0(n2093), .Y(n3133) );
OAI211X1TS U1502 ( .A0(n2075), .A1(n1885), .B0(n1346), .C0(n1345), .Y(n1347)
);
ADDFHX2TS U1503 ( .A(n993), .B(n992), .CI(n991), .CO(n1002), .S(
Exp_Operation_Module_Data_S[6]) );
OAI211X1TS U1504 ( .A0(n2726), .A1(n1905), .B0(n1904), .C0(n1903), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[25]) );
AOI21X2TS U1505 ( .A0(n2494), .A1(n2394), .B0(n2393), .Y(n2434) );
NAND3BX1TS U1506 ( .AN(n2722), .B(n2721), .C(n2720), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[21]) );
OAI211X1TS U1507 ( .A0(n2034), .A1(n2141), .B0(n2013), .C0(n2012), .Y(n3137)
);
NOR2X1TS U1508 ( .A(n1123), .B(n1122), .Y(n1124) );
OAI21X1TS U1509 ( .A0(n1845), .A1(n2137), .B0(n1832), .Y(n3115) );
OAI211X1TS U1510 ( .A0(n2142), .A1(n2141), .B0(n2140), .C0(n2139), .Y(n3132)
);
INVX3TS U1511 ( .A(n2634), .Y(n2629) );
ADDFHX2TS U1512 ( .A(n984), .B(n983), .CI(n982), .CO(n991), .S(
Exp_Operation_Module_Data_S[5]) );
OAI211X1TS U1513 ( .A0(n2060), .A1(n2087), .B0(n1874), .C0(n1873), .Y(n1875)
);
AOI222X1TS U1514 ( .A0(n2710), .A1(n2678), .B0(n2709), .B1(n2680), .C0(n1328), .C1(n2669), .Y(n1900) );
AOI211X2TS U1515 ( .A0(n2302), .A1(n2301), .B0(n2300), .C0(n2299), .Y(n2303)
);
OAI211X1TS U1516 ( .A0(n2005), .A1(n2074), .B0(n2000), .C0(n1999), .Y(n2025)
);
OAI21X1TS U1517 ( .A0(n2075), .A1(n2087), .B0(n1993), .Y(n1994) );
OAI21X2TS U1518 ( .A0(n1447), .A1(n1446), .B0(n1445), .Y(n1448) );
OAI21X1TS U1519 ( .A0(n2546), .A1(n2547), .B0(n2540), .Y(n2545) );
AO22XLTS U1520 ( .A0(n2860), .A1(Add_Subt_result[0]), .B0(n896), .B1(
Add_Subt_result[54]), .Y(n2862) );
OAI21X2TS U1521 ( .A0(n2446), .A1(n1493), .B0(n1492), .Y(n2393) );
OR2X2TS U1522 ( .A(n1667), .B(n2726), .Y(n885) );
NOR2X4TS U1523 ( .A(n1661), .B(n1558), .Y(n2757) );
NAND2X1TS U1524 ( .A(n2515), .B(n1378), .Y(n1380) );
INVX1TS U1525 ( .A(n944), .Y(n1084) );
INVX3TS U1526 ( .A(n1207), .Y(n2679) );
NAND2X1TS U1527 ( .A(n1406), .B(n1395), .Y(n1439) );
CLKBUFX3TS U1528 ( .A(n2149), .Y(n905) );
NAND2X1TS U1529 ( .A(n1545), .B(n1533), .Y(n1772) );
OAI221X1TS U1530 ( .A0(n2298), .A1(n2297), .B0(n2296), .B1(n2295), .C0(n2294), .Y(n2299) );
OAI21X1TS U1531 ( .A0(n2451), .A1(n2457), .B0(n2452), .Y(n1490) );
NAND3BX1TS U1532 ( .AN(n2218), .B(n2211), .C(n2210), .Y(n2231) );
NOR2X4TS U1533 ( .A(n1667), .B(n1558), .Y(n2743) );
INVX2TS U1534 ( .A(n2706), .Y(n2676) );
INVX2TS U1535 ( .A(n2706), .Y(n2708) );
NAND3BX1TS U1536 ( .AN(n2554), .B(n873), .C(n1641), .Y(n2550) );
OAI211X2TS U1537 ( .A0(n2886), .A1(n1337), .B0(n1336), .C0(n1335), .Y(n1988)
);
NAND2BX1TS U1538 ( .AN(n2088), .B(n1303), .Y(n1304) );
NAND3X1TS U1539 ( .A(n2623), .B(n2622), .C(n2621), .Y(
FS_Module_state_next[1]) );
NAND3X1TS U1540 ( .A(n1142), .B(n1087), .C(n3022), .Y(n1100) );
NOR2X4TS U1541 ( .A(n2141), .B(n2914), .Y(n1692) );
OAI2BB2X1TS U1542 ( .B0(n2245), .B1(n2244), .A0N(n2243), .A1N(n2242), .Y(
n2300) );
OAI21X1TS U1543 ( .A0(n2257), .A1(n2256), .B0(n2255), .Y(n2259) );
OAI21X1TS U1544 ( .A0(FS_Module_state_reg[0]), .A1(n1040), .B0(n1569), .Y(
n883) );
NAND3X1TS U1545 ( .A(n1569), .B(n2884), .C(n1040), .Y(n1024) );
INVX1TS U1546 ( .A(n1121), .Y(n1142) );
INVX3TS U1547 ( .A(n886), .Y(n899) );
NOR2X1TS U1548 ( .A(n940), .B(Add_Subt_result[30]), .Y(n941) );
OAI211XLTS U1549 ( .A0(intDY[8]), .A1(n2959), .B0(n2195), .C0(n2198), .Y(
n2207) );
NAND2BX1TS U1550 ( .AN(Sgf_normalized_result[54]), .B(n1933), .Y(n2307) );
INVX1TS U1551 ( .A(n2281), .Y(n2287) );
OAI211X1TS U1552 ( .A0(intDX[61]), .A1(n3045), .B0(n2241), .C0(n2240), .Y(
n2242) );
OAI211X1TS U1553 ( .A0(n2962), .A1(intDY[33]), .B0(n2164), .C0(n2267), .Y(
n2165) );
OAI211X2TS U1554 ( .A0(intDY[28]), .A1(n2940), .B0(n2176), .C0(n2167), .Y(
n2227) );
NOR2X1TS U1555 ( .A(n2247), .B(intDX[44]), .Y(n2248) );
OAI211X2TS U1556 ( .A0(intDY[12]), .A1(n2936), .B0(n2205), .C0(n2178), .Y(
n2209) );
OAI211X2TS U1557 ( .A0(intDY[20]), .A1(n2942), .B0(n2224), .C0(n2177), .Y(
n2218) );
NOR2BX1TS U1558 ( .AN(Sgf_normalized_result[12]), .B(n1461), .Y(n1400) );
NAND3X1TS U1559 ( .A(n2947), .B(n2239), .C(intDY[60]), .Y(n2240) );
NOR2X1TS U1560 ( .A(n2233), .B(intDX[56]), .Y(n2234) );
NOR2X4TS U1561 ( .A(n2919), .B(LZA_output[3]), .Y(n1035) );
NAND3X1TS U1562 ( .A(n1138), .B(n1163), .C(n946), .Y(n930) );
NOR2X1TS U1563 ( .A(n2948), .B(intDY[53]), .Y(n2159) );
INVX3TS U1564 ( .A(n2920), .Y(n1931) );
NAND2BX1TS U1565 ( .AN(intDY[41]), .B(intDX[41]), .Y(n2163) );
INVX3TS U1566 ( .A(n2920), .Y(n1955) );
INVX3TS U1567 ( .A(n2920), .Y(n1981) );
XNOR2X2TS U1568 ( .A(n3110), .B(intDX[63]), .Y(n1641) );
NOR2X1TS U1569 ( .A(n922), .B(n925), .Y(n1021) );
NAND2BX1TS U1570 ( .AN(intDY[19]), .B(intDX[19]), .Y(n2215) );
OAI21X1TS U1571 ( .A0(intDY[55]), .A1(n3111), .B0(intDY[54]), .Y(n2289) );
OAI21X1TS U1572 ( .A0(intDY[31]), .A1(n2961), .B0(intDY[30]), .Y(n2172) );
NAND2BX1TS U1573 ( .AN(intDY[29]), .B(intDX[29]), .Y(n2167) );
NAND2BX1TS U1574 ( .AN(intDY[27]), .B(intDX[27]), .Y(n2169) );
NAND2BX1TS U1575 ( .AN(intDY[32]), .B(intDX[32]), .Y(n2164) );
NAND2BX1TS U1576 ( .AN(intDY[62]), .B(intDX[62]), .Y(n2243) );
NAND2BX1TS U1577 ( .AN(intDX[62]), .B(intDY[62]), .Y(n2241) );
NAND2BX1TS U1578 ( .AN(intDY[59]), .B(intDX[59]), .Y(n2235) );
NAND2BX1TS U1579 ( .AN(intDY[47]), .B(intDX[47]), .Y(n2246) );
NAND2BX1TS U1580 ( .AN(intDY[51]), .B(intDX[51]), .Y(n2284) );
NAND2BX1TS U1581 ( .AN(intDY[40]), .B(intDX[40]), .Y(n2162) );
INVX3TS U1582 ( .A(n2920), .Y(n1461) );
NAND2BX1TS U1583 ( .AN(intDY[21]), .B(intDX[21]), .Y(n2177) );
OAI21X1TS U1584 ( .A0(n2906), .A1(FSM_selector_C), .B0(add_overflow_flag),
.Y(n1297) );
NOR2X4TS U1585 ( .A(underflow_flag), .B(overflow_flag), .Y(n1236) );
XOR2X1TS U1586 ( .A(n1687), .B(n1686), .Y(Add_Subt_Sgf_module_S_to_D[38]) );
NAND2BX2TS U1587 ( .AN(n2158), .B(FSM_selector_C), .Y(n1040) );
OAI21X4TS U1588 ( .A0(n2314), .A1(n2310), .B0(n2311), .Y(n2309) );
AOI21X2TS U1589 ( .A0(n1810), .A1(n1798), .B0(n1797), .Y(n1942) );
XOR2X2TS U1590 ( .A(n1017), .B(n917), .Y(n2156) );
ADDFHX4TS U1591 ( .A(n1015), .B(n1014), .CI(n1013), .CO(n1017), .S(
Exp_Operation_Module_Data_S[10]) );
NAND2X6TS U1592 ( .A(n2606), .B(n937), .Y(n2610) );
NAND4X1TS U1593 ( .A(n1173), .B(n1172), .C(n1171), .D(n1170), .Y(
Leading_Zero_Detector_Module_Codec_to_Reg[4]) );
AOI2BB1X4TS U1594 ( .A0N(n2611), .A1N(Add_Subt_result[1]), .B0(n951), .Y(
n1173) );
OR3X2TS U1595 ( .A(n1125), .B(Add_Subt_result[11]), .C(Add_Subt_result[10]),
.Y(n953) );
NOR2X8TS U1596 ( .A(n1099), .B(n936), .Y(n2606) );
XOR2X1TS U1597 ( .A(n1985), .B(n1984), .Y(Add_Subt_Sgf_module_S_to_D[55]) );
AOI21X2TS U1598 ( .A0(n2309), .A1(n2307), .B0(n2305), .Y(n1985) );
MX2X1TS U1599 ( .A(DMP[55]), .B(n901), .S0(n1973), .Y(n979) );
NAND2BXLTS U1600 ( .AN(intDX[9]), .B(intDY[9]), .Y(n2196) );
NAND3XLTS U1601 ( .A(n2959), .B(n2195), .C(intDY[8]), .Y(n2197) );
OA22X1TS U1602 ( .A0(n2901), .A1(intDY[14]), .B0(n2967), .B1(intDY[15]), .Y(
n2205) );
NAND2X1TS U1603 ( .A(n1031), .B(n1303), .Y(n1036) );
OA22X1TS U1604 ( .A0(n2899), .A1(intDY[30]), .B0(n2961), .B1(intDY[31]), .Y(
n2176) );
OA22X1TS U1605 ( .A0(n2902), .A1(intDY[22]), .B0(n3050), .B1(intDY[23]), .Y(
n2224) );
MX2X1TS U1606 ( .A(DMP[15]), .B(Sgf_normalized_result[17]), .S0(n1458), .Y(
n1476) );
MX2X1TS U1607 ( .A(DMP[23]), .B(Sgf_normalized_result[25]), .S0(n1471), .Y(
n1498) );
MX2X1TS U1608 ( .A(DMP[24]), .B(Sgf_normalized_result[26]), .S0(n1471), .Y(
n1500) );
INVX2TS U1609 ( .A(n1922), .Y(n2725) );
MX2X1TS U1610 ( .A(DMP[54]), .B(exp_oper_result[2]), .S0(n1933), .Y(n1009)
);
MX2X1TS U1611 ( .A(DMP[57]), .B(exp_oper_result[5]), .S0(n1933), .Y(n983) );
MX2X1TS U1612 ( .A(DMP[60]), .B(exp_oper_result[8]), .S0(n1933), .Y(n996) );
CLKAND2X2TS U1613 ( .A(n988), .B(DmP[60]), .Y(n989) );
AOI2BB2XLTS U1614 ( .B0(intDX[1]), .B1(n3049), .A0N(intDY[0]), .A1N(n2181),
.Y(n2182) );
OAI21XLTS U1615 ( .A0(intDX[1]), .A1(n3049), .B0(intDX[0]), .Y(n2181) );
NAND2BXLTS U1616 ( .AN(intDY[2]), .B(intDX[2]), .Y(n2183) );
INVX2TS U1617 ( .A(n2263), .Y(n2269) );
OAI21XLTS U1618 ( .A0(intDY[33]), .A1(n2962), .B0(intDY[32]), .Y(n2264) );
OAI21XLTS U1619 ( .A0(intDY[41]), .A1(n2928), .B0(intDY[40]), .Y(n2249) );
NAND4XLTS U1620 ( .A(n1632), .B(n1631), .C(n1630), .D(n1629), .Y(n1633) );
OAI2BB2XLTS U1621 ( .B0(n2200), .B1(n2209), .A0N(n2199), .A1N(n2198), .Y(
n2203) );
NAND2X1TS U1622 ( .A(n924), .B(intDX[37]), .Y(n2261) );
MX2X1TS U1623 ( .A(DMP[6]), .B(Sgf_normalized_result[8]), .S0(n1535), .Y(
n1388) );
MX2X1TS U1624 ( .A(DMP[27]), .B(Sgf_normalized_result[29]), .S0(n1471), .Y(
n1508) );
MX2X1TS U1625 ( .A(DMP[5]), .B(Sgf_normalized_result[7]), .S0(n1535), .Y(
n1386) );
MX2X1TS U1626 ( .A(DMP[12]), .B(Sgf_normalized_result[14]), .S0(n1458), .Y(
n1432) );
MX2X1TS U1627 ( .A(DMP[17]), .B(Sgf_normalized_result[19]), .S0(n1458), .Y(
n1482) );
MX2X1TS U1628 ( .A(DMP[18]), .B(Sgf_normalized_result[20]), .S0(n1458), .Y(
n1484) );
CLKAND2X2TS U1629 ( .A(n1981), .B(Sgf_normalized_result[1]), .Y(n2538) );
MX2X1TS U1630 ( .A(DMP[0]), .B(Sgf_normalized_result[2]), .S0(n1535), .Y(
n1361) );
MX2X1TS U1631 ( .A(DMP[2]), .B(Sgf_normalized_result[4]), .S0(n1535), .Y(
n1371) );
MX2X1TS U1632 ( .A(DMP[10]), .B(Sgf_normalized_result[12]), .S0(n1458), .Y(
n1401) );
INVX2TS U1633 ( .A(n1667), .Y(n2667) );
MX2X1TS U1634 ( .A(DMP[19]), .B(Sgf_normalized_result[21]), .S0(n1471), .Y(
n1486) );
MX2X1TS U1635 ( .A(DMP[20]), .B(Sgf_normalized_result[22]), .S0(n1471), .Y(
n1488) );
INVX2TS U1636 ( .A(n1661), .Y(n2666) );
MX2X1TS U1637 ( .A(DMP[8]), .B(Sgf_normalized_result[10]), .S0(n1535), .Y(
n1392) );
MX2X1TS U1638 ( .A(DMP[9]), .B(Sgf_normalized_result[11]), .S0(n1458), .Y(
n1397) );
INVX2TS U1639 ( .A(n1042), .Y(n1077) );
INVX2TS U1640 ( .A(n2144), .Y(n1350) );
INVX2TS U1641 ( .A(n2787), .Y(n2806) );
MX2X1TS U1642 ( .A(DMP[21]), .B(Sgf_normalized_result[23]), .S0(n1471), .Y(
n1494) );
MX2X1TS U1643 ( .A(DMP[22]), .B(Sgf_normalized_result[24]), .S0(n1471), .Y(
n1496) );
MX2X1TS U1644 ( .A(DMP[25]), .B(Sgf_normalized_result[27]), .S0(n1471), .Y(
n1504) );
MX2X1TS U1645 ( .A(DMP[26]), .B(Sgf_normalized_result[28]), .S0(n1471), .Y(
n1506) );
MX2X1TS U1646 ( .A(DMP[29]), .B(Sgf_normalized_result[31]), .S0(n1786), .Y(
n1524) );
MX2X1TS U1647 ( .A(DMP[30]), .B(Sgf_normalized_result[32]), .S0(n1786), .Y(
n1526) );
MX2X1TS U1648 ( .A(DMP[32]), .B(Sgf_normalized_result[34]), .S0(n1786), .Y(
n1530) );
MX2X1TS U1649 ( .A(DMP[33]), .B(Sgf_normalized_result[35]), .S0(n1535), .Y(
n1536) );
MX2X1TS U1650 ( .A(DMP[34]), .B(Sgf_normalized_result[36]), .S0(n1786), .Y(
n1540) );
MX2X1TS U1651 ( .A(DMP[36]), .B(Sgf_normalized_result[38]), .S0(n1786), .Y(
n1683) );
MX2X1TS U1652 ( .A(DMP[37]), .B(Sgf_normalized_result[39]), .S0(n1786), .Y(
n1789) );
MX2X1TS U1653 ( .A(DMP[38]), .B(Sgf_normalized_result[40]), .S0(n1786), .Y(
n1791) );
MX2X1TS U1654 ( .A(DMP[40]), .B(Sgf_normalized_result[42]), .S0(n1964), .Y(
n1795) );
MX2X1TS U1655 ( .A(DMP[41]), .B(Sgf_normalized_result[43]), .S0(n1964), .Y(
n1800) );
MX2X1TS U1656 ( .A(DMP[42]), .B(Sgf_normalized_result[44]), .S0(n1964), .Y(
n1804) );
MX2X1TS U1657 ( .A(DMP[44]), .B(Sgf_normalized_result[46]), .S0(n1964), .Y(
n1946) );
OAI211X1TS U1658 ( .A0(intDY[36]), .A1(n2960), .B0(n2272), .C0(n2261), .Y(
n2263) );
NAND2X1TS U1659 ( .A(n922), .B(FS_Module_state_reg[1]), .Y(n1237) );
NAND2X1TS U1660 ( .A(n965), .B(n2921), .Y(n2607) );
INVX2TS U1661 ( .A(n2072), .Y(n2144) );
OAI2BB2XLTS U1662 ( .B0(n2061), .B1(n2036), .A0N(n907), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(n2037) );
OAI2BB2XLTS U1663 ( .B0(n2061), .B1(n2027), .A0N(n907), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(n2028) );
NOR2XLTS U1664 ( .A(n2957), .B(n2079), .Y(n2080) );
OAI21XLTS U1665 ( .A0(n2075), .A1(n2074), .B0(n2073), .Y(n2076) );
AO22XLTS U1666 ( .A0(n1846), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(n1070), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[104]), .Y(n1055) );
AO22XLTS U1667 ( .A0(n1846), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .B0(n1070), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[105]), .Y(n1065) );
AO22XLTS U1668 ( .A0(n1846), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .B0(n1070), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[106]), .Y(n1045) );
AO22XLTS U1669 ( .A0(n1846), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(n1070), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[107]), .Y(n1033) );
AO22XLTS U1670 ( .A0(n1846), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .B0(n1070), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[108]), .Y(n1050) );
AO22XLTS U1671 ( .A0(n1846), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[93]), .B0(n1070), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[109]), .Y(n1060) );
OAI21XLTS U1672 ( .A0(n2136), .A1(n2074), .B0(n1338), .Y(n1339) );
AOI2BB1XLTS U1673 ( .A0N(n1868), .A1N(n2060), .B0(n1700), .Y(n1314) );
AOI2BB1XLTS U1674 ( .A0N(n1868), .A1N(n2027), .B0(n1689), .Y(n1293) );
NAND3XLTS U1675 ( .A(n908), .B(n1846), .C(
Barrel_Shifter_module_Mux_Array_Data_array[102]), .Y(n1844) );
CLKAND2X2TS U1676 ( .A(n1829), .B(n1827), .Y(n1845) );
AO22XLTS U1677 ( .A0(n1846), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[87]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[103]), .B1(n1070), .Y(n1073) );
AOI21X1TS U1678 ( .A0(n2494), .A1(n2448), .B0(n2447), .Y(n2461) );
OAI21XLTS U1679 ( .A0(n1161), .A1(n1160), .B0(n1159), .Y(n1167) );
CLKAND2X2TS U1680 ( .A(n1134), .B(Add_Subt_result[33]), .Y(n1164) );
AND3X1TS U1681 ( .A(n1649), .B(n1648), .C(n1647), .Y(n2647) );
NAND2X2TS U1682 ( .A(n1180), .B(n1179), .Y(n1922) );
OAI211XLTS U1683 ( .A0(n962), .A1(n1121), .B0(n1079), .C0(n961), .Y(n963) );
NOR2XLTS U1684 ( .A(Add_Subt_result[53]), .B(Add_Subt_result[54]), .Y(n959)
);
NAND4BXLTS U1685 ( .AN(Add_Subt_result[25]), .B(n1089), .C(n1161), .D(
Add_Subt_result[24]), .Y(n1091) );
OAI21XLTS U1686 ( .A0(Add_Subt_result[4]), .A1(n2605), .B0(n2604), .Y(n1104)
);
OAI21X1TS U1687 ( .A0(n2373), .A1(n1812), .B0(n1811), .Y(n2361) );
OR2X1TS U1688 ( .A(n1958), .B(n1957), .Y(n2334) );
INVX2TS U1689 ( .A(n973), .Y(n1178) );
OR2X1TS U1690 ( .A(n2560), .B(n2559), .Y(n2623) );
MX2X1TS U1691 ( .A(DMP[53]), .B(exp_oper_result[1]), .S0(n1973), .Y(n986) );
XOR2XLTS U1692 ( .A(n2525), .B(n2524), .Y(Add_Subt_Sgf_module_S_to_D[5]) );
XOR2XLTS U1693 ( .A(n2490), .B(n2489), .Y(Add_Subt_Sgf_module_S_to_D[16]) );
MX2X1TS U1694 ( .A(DMP[58]), .B(exp_oper_result[6]), .S0(n1973), .Y(n992) );
CLKAND2X2TS U1695 ( .A(n2129), .B(DmP[58]), .Y(n981) );
MX2X1TS U1696 ( .A(DMP[61]), .B(exp_oper_result[9]), .S0(n1964), .Y(n1000)
);
CLKAND2X2TS U1697 ( .A(n2129), .B(DmP[61]), .Y(n994) );
NOR2X1TS U1698 ( .A(n2406), .B(n2401), .Y(n1513) );
AOI2BB2XLTS U1699 ( .B0(intDY[3]), .B1(n2966), .A0N(intDX[2]), .A1N(n2184),
.Y(n2185) );
OAI21XLTS U1700 ( .A0(intDY[3]), .A1(n2966), .B0(intDY[2]), .Y(n2184) );
OAI21XLTS U1701 ( .A0(intDY[15]), .A1(n2967), .B0(intDY[14]), .Y(n2201) );
OAI21XLTS U1702 ( .A0(intDY[13]), .A1(n2935), .B0(intDY[12]), .Y(n2192) );
INVX2TS U1703 ( .A(n1857), .Y(n2078) );
NOR2X1TS U1704 ( .A(n2479), .B(n2474), .Y(n1481) );
INVX2TS U1705 ( .A(n1846), .Y(n1041) );
NAND2X1TS U1706 ( .A(n1041), .B(n1646), .Y(n1042) );
NOR2X1TS U1707 ( .A(n1113), .B(n939), .Y(n947) );
NOR2X1TS U1708 ( .A(n2456), .B(n2451), .Y(n1491) );
NAND2X1TS U1709 ( .A(n2450), .B(n1491), .Y(n1493) );
INVX4TS U1710 ( .A(n1984), .Y(n1467) );
NOR2X1TS U1711 ( .A(n1549), .B(n1551), .Y(n1533) );
NOR2X1TS U1712 ( .A(n1770), .B(n1774), .Y(n1776) );
NOR2X1TS U1713 ( .A(n1813), .B(n1815), .Y(n1798) );
NAND2X1TS U1714 ( .A(n1771), .B(n1776), .Y(n1779) );
NAND2X1TS U1715 ( .A(n2400), .B(n1513), .Y(n1515) );
NAND2BXLTS U1716 ( .AN(intDY[9]), .B(intDX[9]), .Y(n2195) );
OAI21XLTS U1717 ( .A0(intDY[21]), .A1(n2939), .B0(intDY[20]), .Y(n2212) );
OAI2BB1X1TS U1718 ( .A0N(n2272), .A1N(n2271), .B0(n2270), .Y(n2277) );
OAI21XLTS U1719 ( .A0(intDX[37]), .A1(n924), .B0(n2262), .Y(n2271) );
NAND3XLTS U1720 ( .A(n2960), .B(n2261), .C(intDY[36]), .Y(n2262) );
MX2X1TS U1721 ( .A(DMP[4]), .B(Sgf_normalized_result[6]), .S0(n1535), .Y(
n1375) );
MX2X1TS U1722 ( .A(DMP[1]), .B(Sgf_normalized_result[3]), .S0(n1535), .Y(
n1369) );
MX2X1TS U1723 ( .A(DMP[28]), .B(Sgf_normalized_result[30]), .S0(n1471), .Y(
n1510) );
AOI222X1TS U1724 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[81]), .A1(
n1861), .B0(Barrel_Shifter_module_Mux_Array_Data_array[73]), .B1(n1860), .C0(Barrel_Shifter_module_Mux_Array_Data_array[89]), .C1(n2123), .Y(n1746)
);
AOI222X1TS U1725 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[80]), .A1(
n1861), .B0(Barrel_Shifter_module_Mux_Array_Data_array[72]), .B1(n1860), .C0(Barrel_Shifter_module_Mux_Array_Data_array[88]), .C1(n2123), .Y(n1757)
);
NOR2X4TS U1726 ( .A(n891), .B(LZA_output[4]), .Y(n1857) );
CLKAND2X2TS U1727 ( .A(n1981), .B(Sgf_normalized_result[0]), .Y(n1358) );
MX2X1TS U1728 ( .A(DMP[3]), .B(Sgf_normalized_result[5]), .S0(n1535), .Y(
n1373) );
NOR2X1TS U1729 ( .A(n2526), .B(n2528), .Y(n2515) );
MX2X1TS U1730 ( .A(DMP[16]), .B(Sgf_normalized_result[18]), .S0(n1458), .Y(
n1478) );
MX2X1TS U1731 ( .A(DMP[7]), .B(Sgf_normalized_result[9]), .S0(n1535), .Y(
n1390) );
NAND2X1TS U1732 ( .A(n2473), .B(n1481), .Y(n2445) );
INVX2TS U1733 ( .A(n1895), .Y(n1897) );
MX2X1TS U1734 ( .A(DmP[25]), .B(Add_Subt_result[27]), .S0(FSM_selector_C),
.Y(n1896) );
MX2X1TS U1735 ( .A(DMP[49]), .B(Sgf_normalized_result[51]), .S0(n1933), .Y(
n1970) );
MX2X1TS U1736 ( .A(DMP[14]), .B(Sgf_normalized_result[16]), .S0(n1458), .Y(
n1474) );
MX2X1TS U1737 ( .A(DMP[13]), .B(Sgf_normalized_result[15]), .S0(n1458), .Y(
n1472) );
NOR2X1TS U1738 ( .A(n1439), .B(n1446), .Y(n1449) );
NAND2X1TS U1739 ( .A(n1438), .B(n1443), .Y(n1446) );
MX2X1TS U1740 ( .A(DMP[11]), .B(Sgf_normalized_result[13]), .S0(n1458), .Y(
n1428) );
NOR2X1TS U1741 ( .A(n1420), .B(n1423), .Y(n1438) );
NAND4XLTS U1742 ( .A(n1580), .B(n1579), .C(n1578), .D(n1577), .Y(n1581) );
NAND4XLTS U1743 ( .A(n1608), .B(n1607), .C(n1606), .D(n1605), .Y(n1636) );
NAND4XLTS U1744 ( .A(n1616), .B(n1615), .C(n1614), .D(n1613), .Y(n1635) );
NAND4XLTS U1745 ( .A(n1624), .B(n1623), .C(n1622), .D(n1621), .Y(n1634) );
AOI31XLTS U1746 ( .A0(n1142), .A1(Add_Subt_result[45]), .A2(n2913), .B0(
n1141), .Y(n1143) );
NOR2XLTS U1747 ( .A(n1140), .B(Add_Subt_result[54]), .Y(n1141) );
AOI2BB1XLTS U1748 ( .A0N(n1139), .A1N(Add_Subt_result[52]), .B0(
Add_Subt_result[53]), .Y(n1140) );
INVX2TS U1749 ( .A(n1137), .Y(n1094) );
NAND2X1TS U1750 ( .A(n1134), .B(n934), .Y(n944) );
NAND4XLTS U1751 ( .A(n1112), .B(n932), .C(n1083), .D(n931), .Y(n933) );
OR2X1TS U1752 ( .A(Add_Subt_result[53]), .B(Add_Subt_result[52]), .Y(n927)
);
INVX2TS U1753 ( .A(n1099), .Y(n1102) );
NAND2X1TS U1754 ( .A(n2423), .B(n1503), .Y(n2395) );
MX2X1TS U1755 ( .A(DMP[31]), .B(Sgf_normalized_result[33]), .S0(n1786), .Y(
n1528) );
NOR2X1TS U1756 ( .A(n2387), .B(n2382), .Y(n1545) );
MX2X1TS U1757 ( .A(DMP[35]), .B(Sgf_normalized_result[37]), .S0(n1786), .Y(
n1679) );
NOR2X1TS U1758 ( .A(n1671), .B(n1674), .Y(n1771) );
MX2X1TS U1759 ( .A(DMP[39]), .B(Sgf_normalized_result[41]), .S0(n1786), .Y(
n1793) );
NOR2X1TS U1760 ( .A(n2362), .B(n2365), .Y(n1809) );
MX2X1TS U1761 ( .A(DMP[43]), .B(Sgf_normalized_result[45]), .S0(n1964), .Y(
n1937) );
MX2X1TS U1762 ( .A(DMP[45]), .B(Sgf_normalized_result[47]), .S0(n1933), .Y(
n1953) );
MX2X1TS U1763 ( .A(DMP[46]), .B(Sgf_normalized_result[48]), .S0(n1933), .Y(
n1957) );
MX2X1TS U1764 ( .A(DMP[47]), .B(Sgf_normalized_result[49]), .S0(n1933), .Y(
n1961) );
MX2X1TS U1765 ( .A(DMP[48]), .B(Sgf_normalized_result[50]), .S0(n1973), .Y(
n1965) );
MX2X1TS U1766 ( .A(DMP[50]), .B(Sgf_normalized_result[52]), .S0(n1933), .Y(
n1974) );
MX2X1TS U1767 ( .A(DMP[51]), .B(Sgf_normalized_result[53]), .S0(n1981), .Y(
n1978) );
CLKINVX3TS U1768 ( .A(n1984), .Y(n1983) );
OR2X1TS U1769 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[2]), .Y(
n1238) );
AND3X1TS U1770 ( .A(n2656), .B(n2655), .C(n2654), .Y(n2686) );
AND3X1TS U1771 ( .A(n2662), .B(n2661), .C(n2660), .Y(n2691) );
OAI21XLTS U1772 ( .A0(exp_oper_result[4]), .A1(n2136), .B0(n2124), .Y(n2128)
);
OAI21XLTS U1773 ( .A0(n2122), .A1(n2121), .B0(n897), .Y(n2131) );
AOI222X1TS U1774 ( .A0(n2019), .A1(n2082), .B0(n2018), .B1(n2084), .C0(n921),
.C1(Barrel_Shifter_module_Mux_Array_Data_array[89]), .Y(n2020) );
AND3X1TS U1775 ( .A(n1264), .B(n1263), .C(n1262), .Y(n2699) );
AOI222X1TS U1776 ( .A0(n2008), .A1(n2082), .B0(n2007), .B1(n2084), .C0(n921),
.C1(Barrel_Shifter_module_Mux_Array_Data_array[88]), .Y(n2009) );
AO22XLTS U1777 ( .A0(n2146), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(n905), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .Y(n2099) );
AO22XLTS U1778 ( .A0(n2146), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .B0(n905), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .Y(n2103) );
AO22XLTS U1779 ( .A0(n905), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .B0(n2146), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .Y(n2095) );
AO22XLTS U1780 ( .A0(n905), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .B0(n2146), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .Y(n2111) );
AO22XLTS U1781 ( .A0(n905), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(n2146), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .Y(n2107) );
AO22XLTS U1782 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[87]), .A1(
n2149), .B0(n904), .B1(Barrel_Shifter_module_Mux_Array_Data_array[71]),
.Y(n1349) );
AOI2BB2XLTS U1783 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[95]),
.B1(n907), .A0N(n1764), .A1N(n2060), .Y(n1702) );
AOI2BB2XLTS U1784 ( .B0(n1692), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[96]), .A0N(n1764), .A1N(
n2027), .Y(n1693) );
AOI2BB2XLTS U1785 ( .B0(n1692), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[97]), .A0N(n1764), .A1N(
n2036), .Y(n1719) );
AOI2BB1XLTS U1786 ( .A0N(n1868), .A1N(n2036), .B0(n1713), .Y(n1714) );
AO22XLTS U1787 ( .A0(n1839), .A1(n1992), .B0(n1692), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[98]), .Y(n1738) );
AOI2BB1XLTS U1788 ( .A0N(n1868), .A1N(n1843), .B0(n1733), .Y(n1734) );
AOI2BB2XLTS U1789 ( .B0(n1692), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[99]), .A0N(n1764), .A1N(
n2017), .Y(n1752) );
MX2X1TS U1790 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[99]), .B(
Barrel_Shifter_module_Mux_Array_Data_array[107]), .S0(LZA_output[3]),
.Y(n1853) );
AOI2BB2XLTS U1791 ( .B0(n1692), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[100]), .A0N(n1764), .A1N(
n2005), .Y(n1765) );
MX2X1TS U1792 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[100]), .B(
Barrel_Shifter_module_Mux_Array_Data_array[108]), .S0(LZA_output[3]),
.Y(n1849) );
MX2X1TS U1793 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[101]), .B(
Barrel_Shifter_module_Mux_Array_Data_array[109]), .S0(LZA_output[3]),
.Y(n1878) );
AO22XLTS U1794 ( .A0(n904), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[58]), .B0(n2149), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .Y(n1047) );
AO22XLTS U1795 ( .A0(n2146), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[61]), .B0(n905), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .Y(n1062) );
AO22XLTS U1796 ( .A0(n904), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[60]), .B0(n2149), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .Y(n1052) );
AO22XLTS U1797 ( .A0(n2146), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[59]), .B0(n2149), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .Y(n1039) );
AO22XLTS U1798 ( .A0(n904), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[56]), .B0(n2149), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .Y(n1057) );
AO22XLTS U1799 ( .A0(n904), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[57]), .B0(n905), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .Y(n1068) );
AND3X1TS U1800 ( .A(n1283), .B(n1282), .C(n1281), .Y(n2690) );
AND3X1TS U1801 ( .A(n1243), .B(n1242), .C(n1241), .Y(n2693) );
AND3X1TS U1802 ( .A(n1206), .B(n1205), .C(n1204), .Y(n1286) );
AND3X1TS U1803 ( .A(n1217), .B(n1216), .C(n1215), .Y(n2705) );
AND3X1TS U1804 ( .A(n2683), .B(n2682), .C(n2681), .Y(n2707) );
AND3X1TS U1805 ( .A(n1198), .B(n1197), .C(n1196), .Y(n1324) );
AND3X1TS U1806 ( .A(n1210), .B(n1209), .C(n1208), .Y(n1229) );
AND3X1TS U1807 ( .A(n1220), .B(n1219), .C(n1218), .Y(n1332) );
AND3X1TS U1808 ( .A(n1666), .B(n1665), .C(n1664), .Y(n2659) );
AND3X1TS U1809 ( .A(n1274), .B(n1273), .C(n1272), .Y(n2698) );
AND3X1TS U1810 ( .A(n1279), .B(n1278), .C(n1277), .Y(n1327) );
AO22XLTS U1811 ( .A0(n2143), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[79]), .B0(n1350), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[63]), .Y(n1075) );
AO22XLTS U1812 ( .A0(n2149), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[71]), .B0(n904), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[55]), .Y(n1074) );
NOR2X4TS U1813 ( .A(n944), .B(Add_Subt_result[23]), .Y(n1116) );
OR2X1TS U1814 ( .A(n1938), .B(n1937), .Y(n2355) );
NOR2X1TS U1815 ( .A(n1927), .B(n1936), .Y(n2349) );
OR2X1TS U1816 ( .A(n1966), .B(n1965), .Y(n2325) );
OR2X1TS U1817 ( .A(n1975), .B(n1974), .Y(n2316) );
NOR4X1TS U1818 ( .A(n2298), .B(n2263), .C(n2296), .D(n2165), .Y(n2302) );
BUFX3TS U1819 ( .A(n2632), .Y(n2590) );
BUFX3TS U1820 ( .A(n2632), .Y(n2599) );
BUFX3TS U1821 ( .A(n2632), .Y(n2583) );
AOI2BB2XLTS U1822 ( .B0(n2882), .B1(ready), .A0N(beg_FSM), .A1N(n860), .Y(
n872) );
NAND4BXLTS U1823 ( .AN(n2558), .B(n2557), .C(n2559), .D(n2556), .Y(
FS_Module_state_next[0]) );
OAI21XLTS U1824 ( .A0(n2554), .A1(n2553), .B0(n873), .Y(n2557) );
OAI21XLTS U1825 ( .A0(n2561), .A1(n2914), .B0(n1353), .Y(n864) );
AOI2BB2XLTS U1826 ( .B0(n2781), .B1(n1902), .A0N(n2719), .A1N(n1901), .Y(
n1903) );
NAND4XLTS U1827 ( .A(n2785), .B(n2784), .C(n2783), .D(n2782), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[11]) );
NAND4XLTS U1828 ( .A(n2763), .B(n2762), .C(n2761), .D(n2760), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[14]) );
OAI31X1TS U1829 ( .A0(n2726), .A1(n2725), .A2(n2724), .B0(n2723), .Y(n2729)
);
NAND4XLTS U1830 ( .A(n2742), .B(n2741), .C(n2740), .D(n2739), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[17]) );
NAND4XLTS U1831 ( .A(n2735), .B(n2734), .C(n2733), .D(n2732), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[18]) );
NAND4XLTS U1832 ( .A(n2804), .B(n2803), .C(n2802), .D(n2801), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[8]) );
NAND4XLTS U1833 ( .A(n2756), .B(n2755), .C(n2754), .D(n2753), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[15]) );
NAND4BXLTS U1834 ( .AN(n2614), .B(n2613), .C(n2612), .D(n2611), .Y(
Leading_Zero_Detector_Module_Codec_to_Reg[5]) );
OAI211XLTS U1835 ( .A0(n2610), .A1(n2996), .B0(n2609), .C0(n2608), .Y(n2614)
);
XOR2XLTS U1836 ( .A(n2433), .B(n2432), .Y(Add_Subt_Sgf_module_S_to_D[25]) );
AOI31XLTS U1837 ( .A0(n1991), .A1(n1990), .A2(n1989), .B0(n2088), .Y(n1995)
);
AO21XLTS U1838 ( .A0(n1996), .A1(n2058), .B0(n1347), .Y(n3130) );
AO21XLTS U1839 ( .A0(n1701), .A1(n2058), .B0(n1321), .Y(n3128) );
AO21XLTS U1840 ( .A0(n1690), .A1(n906), .B0(n1307), .Y(n3126) );
AOI31XLTS U1841 ( .A0(n908), .A1(n1846), .A2(n2957), .B0(n920), .Y(n1847) );
MX2X1TS U1842 ( .A(DMP[52]), .B(exp_oper_result[0]), .S0(n1980), .Y(n1012)
);
NAND4XLTS U1843 ( .A(n2771), .B(n2770), .C(n2769), .D(n2768), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[13]) );
NAND4XLTS U1844 ( .A(n2777), .B(n2776), .C(n2775), .D(n2774), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[12]) );
NAND4XLTS U1845 ( .A(n2792), .B(n2791), .C(n2790), .D(n2789), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[10]) );
NAND4XLTS U1846 ( .A(n2798), .B(n2797), .C(n2796), .D(n2795), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[9]) );
NAND4XLTS U1847 ( .A(n2811), .B(n2810), .C(n2809), .D(n2808), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[7]) );
NAND4XLTS U1848 ( .A(n2750), .B(n2749), .C(n2748), .D(n2747), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[16]) );
AO22XLTS U1849 ( .A0(n2850), .A1(n2773), .B0(n2874), .B1(n2717), .Y(n1912)
);
NAND4XLTS U1850 ( .A(n2716), .B(n2715), .C(n2714), .D(n2713), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[22]) );
XOR2XLTS U1851 ( .A(n2483), .B(n2482), .Y(Add_Subt_Sgf_module_S_to_D[17]) );
XOR2XLTS U1852 ( .A(n2512), .B(n2511), .Y(Add_Subt_Sgf_module_S_to_D[7]) );
XOR2XLTS U1853 ( .A(n2547), .B(n2546), .Y(Add_Subt_Sgf_module_S_to_D[1]) );
XOR2XLTS U1854 ( .A(n2532), .B(n2531), .Y(Add_Subt_Sgf_module_S_to_D[4]) );
AOI2BB2XLTS U1855 ( .B0(n2645), .B1(n1916), .A0N(n2724), .A1N(n1901), .Y(
n1898) );
OAI211XLTS U1856 ( .A0(n1915), .A1(n2711), .B0(n1894), .C0(n1893), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[23]) );
XOR2XLTS U1857 ( .A(n2323), .B(n2322), .Y(Add_Subt_Sgf_module_S_to_D[51]) );
CLKAND2X2TS U1858 ( .A(n2626), .B(Sgf_normalized_result[32]), .Y(
final_result_ieee_Module_Sgf_S_mux[30]) );
CLKAND2X2TS U1859 ( .A(n2625), .B(Sgf_normalized_result[22]), .Y(
final_result_ieee_Module_Sgf_S_mux[20]) );
CLKAND2X2TS U1860 ( .A(n2881), .B(Sgf_normalized_result[53]), .Y(
final_result_ieee_Module_Sgf_S_mux[51]) );
CLKAND2X2TS U1861 ( .A(n2881), .B(Sgf_normalized_result[52]), .Y(
final_result_ieee_Module_Sgf_S_mux[50]) );
CLKAND2X2TS U1862 ( .A(n2881), .B(Sgf_normalized_result[51]), .Y(
final_result_ieee_Module_Sgf_S_mux[49]) );
CLKAND2X2TS U1863 ( .A(n2881), .B(Sgf_normalized_result[50]), .Y(
final_result_ieee_Module_Sgf_S_mux[48]) );
CLKAND2X2TS U1864 ( .A(n2880), .B(Sgf_normalized_result[49]), .Y(
final_result_ieee_Module_Sgf_S_mux[47]) );
CLKAND2X2TS U1865 ( .A(n2881), .B(Sgf_normalized_result[48]), .Y(
final_result_ieee_Module_Sgf_S_mux[46]) );
CLKAND2X2TS U1866 ( .A(n2880), .B(Sgf_normalized_result[47]), .Y(
final_result_ieee_Module_Sgf_S_mux[45]) );
CLKAND2X2TS U1867 ( .A(n1236), .B(Sgf_normalized_result[46]), .Y(
final_result_ieee_Module_Sgf_S_mux[44]) );
CLKAND2X2TS U1868 ( .A(n1236), .B(Sgf_normalized_result[45]), .Y(
final_result_ieee_Module_Sgf_S_mux[43]) );
CLKAND2X2TS U1869 ( .A(n1236), .B(Sgf_normalized_result[44]), .Y(
final_result_ieee_Module_Sgf_S_mux[42]) );
CLKAND2X2TS U1870 ( .A(n1236), .B(Sgf_normalized_result[43]), .Y(
final_result_ieee_Module_Sgf_S_mux[41]) );
CLKAND2X2TS U1871 ( .A(n2880), .B(Sgf_normalized_result[42]), .Y(
final_result_ieee_Module_Sgf_S_mux[40]) );
CLKAND2X2TS U1872 ( .A(n2881), .B(Sgf_normalized_result[41]), .Y(
final_result_ieee_Module_Sgf_S_mux[39]) );
CLKAND2X2TS U1873 ( .A(n2879), .B(Sgf_normalized_result[40]), .Y(
final_result_ieee_Module_Sgf_S_mux[38]) );
CLKAND2X2TS U1874 ( .A(n2626), .B(Sgf_normalized_result[39]), .Y(
final_result_ieee_Module_Sgf_S_mux[37]) );
CLKAND2X2TS U1875 ( .A(n2626), .B(Sgf_normalized_result[38]), .Y(
final_result_ieee_Module_Sgf_S_mux[36]) );
CLKAND2X2TS U1876 ( .A(n2626), .B(Sgf_normalized_result[37]), .Y(
final_result_ieee_Module_Sgf_S_mux[35]) );
CLKAND2X2TS U1877 ( .A(n2626), .B(Sgf_normalized_result[36]), .Y(
final_result_ieee_Module_Sgf_S_mux[34]) );
CLKAND2X2TS U1878 ( .A(n2626), .B(Sgf_normalized_result[35]), .Y(
final_result_ieee_Module_Sgf_S_mux[33]) );
CLKAND2X2TS U1879 ( .A(n2626), .B(Sgf_normalized_result[34]), .Y(
final_result_ieee_Module_Sgf_S_mux[32]) );
CLKAND2X2TS U1880 ( .A(n2626), .B(Sgf_normalized_result[33]), .Y(
final_result_ieee_Module_Sgf_S_mux[31]) );
CLKAND2X2TS U1881 ( .A(n2626), .B(Sgf_normalized_result[31]), .Y(
final_result_ieee_Module_Sgf_S_mux[29]) );
CLKAND2X2TS U1882 ( .A(n2625), .B(Sgf_normalized_result[30]), .Y(
final_result_ieee_Module_Sgf_S_mux[28]) );
CLKAND2X2TS U1883 ( .A(n2625), .B(Sgf_normalized_result[29]), .Y(
final_result_ieee_Module_Sgf_S_mux[27]) );
CLKAND2X2TS U1884 ( .A(n2625), .B(Sgf_normalized_result[28]), .Y(
final_result_ieee_Module_Sgf_S_mux[26]) );
CLKAND2X2TS U1885 ( .A(n2625), .B(Sgf_normalized_result[27]), .Y(
final_result_ieee_Module_Sgf_S_mux[25]) );
CLKAND2X2TS U1886 ( .A(n2625), .B(Sgf_normalized_result[26]), .Y(
final_result_ieee_Module_Sgf_S_mux[24]) );
CLKAND2X2TS U1887 ( .A(n2625), .B(Sgf_normalized_result[25]), .Y(
final_result_ieee_Module_Sgf_S_mux[23]) );
CLKAND2X2TS U1888 ( .A(n2625), .B(Sgf_normalized_result[24]), .Y(
final_result_ieee_Module_Sgf_S_mux[22]) );
CLKAND2X2TS U1889 ( .A(n2625), .B(Sgf_normalized_result[23]), .Y(
final_result_ieee_Module_Sgf_S_mux[21]) );
CLKAND2X2TS U1890 ( .A(n2624), .B(Sgf_normalized_result[21]), .Y(
final_result_ieee_Module_Sgf_S_mux[19]) );
CLKAND2X2TS U1891 ( .A(n2624), .B(Sgf_normalized_result[20]), .Y(
final_result_ieee_Module_Sgf_S_mux[18]) );
CLKAND2X2TS U1892 ( .A(n2624), .B(Sgf_normalized_result[19]), .Y(
final_result_ieee_Module_Sgf_S_mux[17]) );
CLKAND2X2TS U1893 ( .A(n2624), .B(Sgf_normalized_result[18]), .Y(
final_result_ieee_Module_Sgf_S_mux[16]) );
CLKAND2X2TS U1894 ( .A(n2624), .B(Sgf_normalized_result[17]), .Y(
final_result_ieee_Module_Sgf_S_mux[15]) );
CLKAND2X2TS U1895 ( .A(n2624), .B(Sgf_normalized_result[16]), .Y(
final_result_ieee_Module_Sgf_S_mux[14]) );
CLKAND2X2TS U1896 ( .A(n2624), .B(Sgf_normalized_result[15]), .Y(
final_result_ieee_Module_Sgf_S_mux[13]) );
CLKAND2X2TS U1897 ( .A(n2624), .B(Sgf_normalized_result[14]), .Y(
final_result_ieee_Module_Sgf_S_mux[12]) );
CLKAND2X2TS U1898 ( .A(n2624), .B(Sgf_normalized_result[13]), .Y(
final_result_ieee_Module_Sgf_S_mux[11]) );
CLKAND2X2TS U1899 ( .A(n2624), .B(Sgf_normalized_result[12]), .Y(
final_result_ieee_Module_Sgf_S_mux[10]) );
CLKAND2X2TS U1900 ( .A(n2879), .B(Sgf_normalized_result[11]), .Y(
final_result_ieee_Module_Sgf_S_mux[9]) );
CLKAND2X2TS U1901 ( .A(n2879), .B(Sgf_normalized_result[10]), .Y(
final_result_ieee_Module_Sgf_S_mux[8]) );
CLKAND2X2TS U1902 ( .A(n2879), .B(Sgf_normalized_result[9]), .Y(
final_result_ieee_Module_Sgf_S_mux[7]) );
CLKAND2X2TS U1903 ( .A(n2879), .B(Sgf_normalized_result[8]), .Y(
final_result_ieee_Module_Sgf_S_mux[6]) );
CLKAND2X2TS U1904 ( .A(n2879), .B(Sgf_normalized_result[7]), .Y(
final_result_ieee_Module_Sgf_S_mux[5]) );
CLKAND2X2TS U1905 ( .A(n2879), .B(Sgf_normalized_result[6]), .Y(
final_result_ieee_Module_Sgf_S_mux[4]) );
CLKAND2X2TS U1906 ( .A(n2879), .B(Sgf_normalized_result[5]), .Y(
final_result_ieee_Module_Sgf_S_mux[3]) );
CLKAND2X2TS U1907 ( .A(n2879), .B(Sgf_normalized_result[4]), .Y(
final_result_ieee_Module_Sgf_S_mux[2]) );
CLKAND2X2TS U1908 ( .A(n2879), .B(Sgf_normalized_result[3]), .Y(
final_result_ieee_Module_Sgf_S_mux[1]) );
CLKAND2X2TS U1909 ( .A(n2625), .B(Sgf_normalized_result[2]), .Y(
final_result_ieee_Module_Sgf_S_mux[0]) );
NAND2BXLTS U1910 ( .AN(exp_oper_result[10]), .B(n2626), .Y(
final_result_ieee_Module_Exp_S_mux[10]) );
NAND2BXLTS U1911 ( .AN(exp_oper_result[9]), .B(n2628), .Y(
final_result_ieee_Module_Exp_S_mux[9]) );
NAND2BXLTS U1912 ( .AN(exp_oper_result[8]), .B(n2628), .Y(
final_result_ieee_Module_Exp_S_mux[8]) );
NAND2BXLTS U1913 ( .AN(exp_oper_result[7]), .B(n2628), .Y(
final_result_ieee_Module_Exp_S_mux[7]) );
NAND2BXLTS U1914 ( .AN(exp_oper_result[6]), .B(n2628), .Y(
final_result_ieee_Module_Exp_S_mux[6]) );
NAND2BXLTS U1915 ( .AN(exp_oper_result[2]), .B(n2628), .Y(
final_result_ieee_Module_Exp_S_mux[2]) );
NAND2BXLTS U1916 ( .AN(exp_oper_result[1]), .B(n2628), .Y(
final_result_ieee_Module_Exp_S_mux[1]) );
NAND2BXLTS U1917 ( .AN(exp_oper_result[0]), .B(n2628), .Y(
final_result_ieee_Module_Exp_S_mux[0]) );
XOR2XLTS U1918 ( .A(n1405), .B(n1404), .Y(Add_Subt_Sgf_module_S_to_D[12]) );
XOR2XLTS U1919 ( .A(n1416), .B(n1415), .Y(Add_Subt_Sgf_module_S_to_D[10]) );
INVX2TS U1920 ( .A(n1412), .Y(n1414) );
XOR2XLTS U1921 ( .A(n1426), .B(n1419), .Y(Add_Subt_Sgf_module_S_to_D[11]) );
NAND4XLTS U1922 ( .A(n2878), .B(n2877), .C(n2876), .D(n2875), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[0]) );
NAND4XLTS U1923 ( .A(n2830), .B(n2829), .C(n2828), .D(n2827), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[4]) );
NAND4XLTS U1924 ( .A(n2858), .B(n2857), .C(n2856), .D(n2855), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[1]) );
NAND4XLTS U1925 ( .A(n2824), .B(n2823), .C(n2822), .D(n2821), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[5]) );
NAND4XLTS U1926 ( .A(n2849), .B(n2848), .C(n2847), .D(n2846), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[2]) );
NAND4XLTS U1927 ( .A(n2817), .B(n2816), .C(n2815), .D(n2814), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[6]) );
NAND4XLTS U1928 ( .A(n2838), .B(n2837), .C(n2836), .D(n2835), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[3]) );
NAND4XLTS U1929 ( .A(n1158), .B(n2613), .C(n1157), .D(n1156), .Y(
Leading_Zero_Detector_Module_Codec_to_Reg[0]) );
NAND3BXLTS U1930 ( .AN(Add_Subt_result[6]), .B(n2604), .C(Add_Subt_result[5]), .Y(n1156) );
NOR2XLTS U1931 ( .A(n1135), .B(n1138), .Y(n964) );
NAND4BXLTS U1932 ( .AN(n1152), .B(n1093), .C(n1092), .D(n1091), .Y(n1108) );
AOI31XLTS U1933 ( .A0(n1090), .A1(n1089), .A2(Add_Subt_result[26]), .B0(
n1088), .Y(n1092) );
OAI21XLTS U1934 ( .A0(n2434), .A1(n2440), .B0(n2441), .Y(n2439) );
XOR2XLTS U1935 ( .A(n2391), .B(n2390), .Y(Add_Subt_Sgf_module_S_to_D[31]) );
XOR2XLTS U1936 ( .A(n2373), .B(n2372), .Y(Add_Subt_Sgf_module_S_to_D[39]) );
XOR2XLTS U1937 ( .A(n2369), .B(n2368), .Y(Add_Subt_Sgf_module_S_to_D[40]) );
XOR2XLTS U1938 ( .A(n2341), .B(n2340), .Y(Add_Subt_Sgf_module_S_to_D[47]) );
XOR2XLTS U1939 ( .A(n2332), .B(n2331), .Y(Add_Subt_Sgf_module_S_to_D[49]) );
XOR2XLTS U1940 ( .A(n2314), .B(n2313), .Y(Add_Subt_Sgf_module_S_to_D[53]) );
MX2X1TS U1941 ( .A(intDY[0]), .B(intDX[0]), .S0(n2599), .Y(
Oper_Start_in_module_intM[0]) );
MX2X1TS U1942 ( .A(intDY[1]), .B(intDX[1]), .S0(n2599), .Y(
Oper_Start_in_module_intM[1]) );
MX2X1TS U1943 ( .A(intDY[2]), .B(intDX[2]), .S0(n2599), .Y(
Oper_Start_in_module_intM[2]) );
MX2X1TS U1944 ( .A(intDY[3]), .B(intDX[3]), .S0(n2599), .Y(
Oper_Start_in_module_intM[3]) );
MX2X1TS U1945 ( .A(intDY[4]), .B(intDX[4]), .S0(n2590), .Y(
Oper_Start_in_module_intM[4]) );
MX2X1TS U1946 ( .A(intDY[5]), .B(intDX[5]), .S0(n2599), .Y(
Oper_Start_in_module_intM[5]) );
MX2X1TS U1947 ( .A(intDY[6]), .B(intDX[6]), .S0(n2599), .Y(
Oper_Start_in_module_intM[6]) );
MX2X1TS U1948 ( .A(intDY[7]), .B(intDX[7]), .S0(n2599), .Y(
Oper_Start_in_module_intM[7]) );
MX2X1TS U1949 ( .A(intDY[8]), .B(intDX[8]), .S0(n2599), .Y(
Oper_Start_in_module_intM[8]) );
MX2X1TS U1950 ( .A(intDY[9]), .B(intDX[9]), .S0(n2590), .Y(
Oper_Start_in_module_intM[9]) );
MX2X1TS U1951 ( .A(intDY[10]), .B(intDX[10]), .S0(n2590), .Y(
Oper_Start_in_module_intM[10]) );
MX2X1TS U1952 ( .A(intDY[11]), .B(intDX[11]), .S0(n2590), .Y(
Oper_Start_in_module_intM[11]) );
MX2X1TS U1953 ( .A(intDY[12]), .B(intDX[12]), .S0(n2590), .Y(
Oper_Start_in_module_intM[12]) );
MX2X1TS U1954 ( .A(intDY[13]), .B(intDX[13]), .S0(n2590), .Y(
Oper_Start_in_module_intM[13]) );
MX2X1TS U1955 ( .A(intDY[14]), .B(intDX[14]), .S0(n2590), .Y(
Oper_Start_in_module_intM[14]) );
MX2X1TS U1956 ( .A(intDY[15]), .B(intDX[15]), .S0(n2590), .Y(
Oper_Start_in_module_intM[15]) );
MX2X1TS U1957 ( .A(intDY[16]), .B(intDX[16]), .S0(n2583), .Y(
Oper_Start_in_module_intM[16]) );
MX2X1TS U1958 ( .A(intDY[17]), .B(intDX[17]), .S0(n2583), .Y(
Oper_Start_in_module_intM[17]) );
MX2X1TS U1959 ( .A(intDY[18]), .B(intDX[18]), .S0(n2583), .Y(
Oper_Start_in_module_intM[18]) );
MX2X1TS U1960 ( .A(intDY[19]), .B(intDX[19]), .S0(n2583), .Y(
Oper_Start_in_module_intM[19]) );
MX2X1TS U1961 ( .A(intDY[20]), .B(intDX[20]), .S0(n2583), .Y(
Oper_Start_in_module_intM[20]) );
MX2X1TS U1962 ( .A(intDY[21]), .B(intDX[21]), .S0(n2583), .Y(
Oper_Start_in_module_intM[21]) );
MX2X1TS U1963 ( .A(intDY[22]), .B(intDX[22]), .S0(n2590), .Y(
Oper_Start_in_module_intM[22]) );
MX2X1TS U1964 ( .A(intDY[23]), .B(intDX[23]), .S0(n2583), .Y(
Oper_Start_in_module_intM[23]) );
MX2X1TS U1965 ( .A(intDY[24]), .B(intDX[24]), .S0(n2583), .Y(
Oper_Start_in_module_intM[24]) );
MX2X1TS U1966 ( .A(intDY[25]), .B(intDX[25]), .S0(n2599), .Y(
Oper_Start_in_module_intM[25]) );
MX2X1TS U1967 ( .A(intDY[26]), .B(intDX[26]), .S0(n2590), .Y(
Oper_Start_in_module_intM[26]) );
MX2X1TS U1968 ( .A(intDY[27]), .B(intDX[27]), .S0(n2599), .Y(
Oper_Start_in_module_intM[27]) );
MX2X1TS U1969 ( .A(intDY[28]), .B(intDX[28]), .S0(n2569), .Y(
Oper_Start_in_module_intM[28]) );
MX2X1TS U1970 ( .A(intDY[29]), .B(intDX[29]), .S0(n2632), .Y(
Oper_Start_in_module_intM[29]) );
MX2X1TS U1971 ( .A(intDY[30]), .B(intDX[30]), .S0(n2583), .Y(
Oper_Start_in_module_intM[30]) );
MX2X1TS U1972 ( .A(intDY[31]), .B(intDX[31]), .S0(n2634), .Y(
Oper_Start_in_module_intM[31]) );
MX2X1TS U1973 ( .A(intDY[32]), .B(intDX[32]), .S0(n2583), .Y(
Oper_Start_in_module_intM[32]) );
MX2X1TS U1974 ( .A(intDY[33]), .B(intDX[33]), .S0(n2569), .Y(
Oper_Start_in_module_intM[33]) );
MX2X1TS U1975 ( .A(intDY[34]), .B(intDX[34]), .S0(n2569), .Y(
Oper_Start_in_module_intM[34]) );
MX2X1TS U1976 ( .A(intDY[35]), .B(intDX[35]), .S0(n2569), .Y(
Oper_Start_in_module_intM[35]) );
MX2X1TS U1977 ( .A(intDY[36]), .B(intDX[36]), .S0(n2569), .Y(
Oper_Start_in_module_intM[36]) );
MX2X1TS U1978 ( .A(intDY[37]), .B(intDX[37]), .S0(n2569), .Y(
Oper_Start_in_module_intM[37]) );
MX2X1TS U1979 ( .A(intDY[38]), .B(intDX[38]), .S0(n2569), .Y(
Oper_Start_in_module_intM[38]) );
MX2X1TS U1980 ( .A(intDY[39]), .B(intDX[39]), .S0(n2569), .Y(
Oper_Start_in_module_intM[39]) );
MX2X1TS U1981 ( .A(DMP[56]), .B(exp_oper_result[4]), .S0(n1964), .Y(n1006)
);
OAI2BB1X1TS U1982 ( .A0N(n2129), .A1N(DmP[56]), .B0(n2132), .Y(n977) );
MX2X1TS U1983 ( .A(DMP[59]), .B(exp_oper_result[7]), .S0(n1964), .Y(n1003)
);
CLKAND2X2TS U1984 ( .A(n1178), .B(DmP[59]), .Y(n990) );
MX2X1TS U1985 ( .A(DMP[62]), .B(exp_oper_result[10]), .S0(n1973), .Y(n1014)
);
CLKAND2X2TS U1986 ( .A(n1178), .B(DmP[62]), .Y(n998) );
ADDFHX2TS U1987 ( .A(n980), .B(n979), .CI(n978), .CO(n1005), .S(
Exp_Operation_Module_Data_S[3]) );
INVX2TS U1988 ( .A(n901), .Y(n1729) );
INVX2TS U1989 ( .A(n2146), .Y(n903) );
INVX2TS U1990 ( .A(n1745), .Y(n2146) );
NAND2X2TS U1991 ( .A(n2129), .B(n2924), .Y(n1034) );
BUFX3TS U1992 ( .A(n1025), .Y(n2126) );
INVX2TS U1993 ( .A(n2079), .Y(n2149) );
INVX2TS U1994 ( .A(LZA_output[3]), .Y(n891) );
NOR2X4TS U1995 ( .A(LZA_output[4]), .B(n892), .Y(n1027) );
CLKBUFX2TS U1996 ( .A(FS_Module_state_reg[0]), .Y(n2620) );
CLKBUFX2TS U1997 ( .A(exp_oper_result[3]), .Y(n1730) );
BUFX3TS U1998 ( .A(n2114), .Y(n2573) );
AND2X2TS U1999 ( .A(n2120), .B(n2922), .Y(n886) );
INVX2TS U2000 ( .A(n2141), .Y(n2058) );
OAI21X1TS U2001 ( .A0(n2353), .A1(n2352), .B0(n2351), .Y(n2357) );
INVX2TS U2002 ( .A(n2573), .Y(n1909) );
INVX2TS U2003 ( .A(n1027), .Y(n889) );
INVX2TS U2004 ( .A(n889), .Y(n890) );
INVX2TS U2005 ( .A(n891), .Y(n892) );
INVX2TS U2006 ( .A(n1034), .Y(n893) );
INVX2TS U2007 ( .A(n893), .Y(n894) );
INVX2TS U2008 ( .A(n2573), .Y(n895) );
INVX2TS U2009 ( .A(n2573), .Y(n896) );
INVX2TS U2010 ( .A(n1334), .Y(n897) );
NOR2X4TS U2011 ( .A(n2917), .B(FSM_selector_B[1]), .Y(n2120) );
INVX2TS U2012 ( .A(n886), .Y(n898) );
INVX2TS U2013 ( .A(n1730), .Y(n900) );
INVX2TS U2014 ( .A(n900), .Y(n901) );
INVX2TS U2015 ( .A(n903), .Y(n904) );
INVX2TS U2016 ( .A(n2126), .Y(n908) );
INVX2TS U2017 ( .A(n884), .Y(n909) );
INVX2TS U2018 ( .A(n884), .Y(n910) );
INVX2TS U2019 ( .A(n884), .Y(n911) );
INVX2TS U2020 ( .A(n885), .Y(n912) );
INVX2TS U2021 ( .A(n885), .Y(n913) );
INVX2TS U2022 ( .A(n885), .Y(n914) );
OAI221X1TS U2023 ( .A0(n2939), .A1(intDY[21]), .B0(n2942), .B1(intDY[20]),
.C0(n1595), .Y(n1598) );
OAI221X1TS U2024 ( .A0(n2899), .A1(intDY[30]), .B0(n2941), .B1(intDY[29]),
.C0(n1587), .Y(n1590) );
NAND4X1TS U2025 ( .A(n1173), .B(n2612), .C(n967), .D(n966), .Y(
Leading_Zero_Detector_Module_Codec_to_Reg[1]) );
INVX2TS U2026 ( .A(n1969), .Y(n1980) );
NOR2X4TS U2027 ( .A(n1309), .B(n1308), .Y(n2060) );
OAI21X2TS U2028 ( .A0(n1077), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[109]), .B0(n1076), .Y(n2602) );
AOI22X2TS U2029 ( .A0(n1897), .A1(n1896), .B0(n2709), .B1(n1895), .Y(n2719)
);
OAI2BB1X2TS U2030 ( .A0N(Add_Subt_result[28]), .A1N(n1907), .B0(n1322), .Y(
n2709) );
OA22X1TS U2031 ( .A0(n2592), .A1(n2573), .B0(n2591), .B1(n2118), .Y(n1063)
);
OAI21X2TS U2032 ( .A0(n1077), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[103]), .B0(n1076), .Y(n2591) );
OAI21X2TS U2033 ( .A0(n1077), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[106]), .B0(n1076), .Y(n2597) );
OAI21X2TS U2034 ( .A0(n1077), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[108]), .B0(n1076), .Y(n2615) );
OAI21X2TS U2035 ( .A0(n1077), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[107]), .B0(n1076), .Y(n2600) );
OA22X1TS U2036 ( .A0(n2596), .A1(n2152), .B0(n2595), .B1(n2118), .Y(n1043)
);
OAI21X2TS U2037 ( .A0(n1077), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[105]), .B0(n1076), .Y(n2595) );
OA22X1TS U2038 ( .A0(n2594), .A1(n2114), .B0(n2593), .B1(n2118), .Y(n1053)
);
OAI21X2TS U2039 ( .A0(n1077), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[104]), .B0(n1076), .Y(n2593) );
OAI21X4TS U2040 ( .A0(n2787), .A1(n1226), .B0(n1225), .Y(n2710) );
INVX2TS U2041 ( .A(n1348), .Y(n915) );
INVX2TS U2042 ( .A(n1348), .Y(n916) );
OAI211XLTS U2043 ( .A0(n2676), .A1(n1926), .B0(n1925), .C0(n1924), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[26]) );
NOR2X4TS U2044 ( .A(n901), .B(exp_oper_result[4]), .Y(n2002) );
AOI222X1TS U2045 ( .A0(n921), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .B0(n2085), .B1(n2084), .C0(n2083), .C1(n2082), .Y(n2089) );
MXI2X4TS U2046 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[86]), .B(
Barrel_Shifter_module_Mux_Array_Data_array[94]), .S0(n1730), .Y(n2136)
);
AOI222X1TS U2047 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[91]), .A1(
n2123), .B0(Barrel_Shifter_module_Mux_Array_Data_array[83]), .B1(n1861), .C0(Barrel_Shifter_module_Mux_Array_Data_array[75]), .C1(n1860), .Y(n1707)
);
AOI222X1TS U2048 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[92]), .A1(
n2123), .B0(Barrel_Shifter_module_Mux_Array_Data_array[84]), .B1(n1861), .C0(Barrel_Shifter_module_Mux_Array_Data_array[76]), .C1(n1860), .Y(n1289)
);
NOR2X1TS U2049 ( .A(Add_Subt_result[5]), .B(Add_Subt_result[6]), .Y(n1103)
);
NOR2X1TS U2050 ( .A(Add_Subt_result[20]), .B(Add_Subt_result[19]), .Y(n950)
);
NOR2X1TS U2051 ( .A(Add_Subt_result[9]), .B(Add_Subt_result[8]), .Y(n954) );
AOI222X1TS U2052 ( .A0(n2051), .A1(n2082), .B0(n2050), .B1(n2084), .C0(n921),
.C1(Barrel_Shifter_module_Mux_Array_Data_array[87]), .Y(n2053) );
XOR2X1TS U2053 ( .A(n970), .B(n975), .Y(n1011) );
XOR2X1TS U2054 ( .A(n970), .B(n977), .Y(n1007) );
INVX2TS U2055 ( .A(n2137), .Y(n918) );
INVX2TS U2056 ( .A(n2137), .Y(n2049) );
OAI221X1TS U2057 ( .A0(intDX[0]), .A1(n2907), .B0(n2958), .B1(intDY[0]),
.C0(n1571), .Y(n1584) );
OAI221X1TS U2058 ( .A0(n2965), .A1(intDY[26]), .B0(n2969), .B1(intDY[25]),
.C0(n1585), .Y(n1592) );
OAI221X1TS U2059 ( .A0(n2964), .A1(intDY[17]), .B0(n2937), .B1(intDY[16]),
.C0(n1593), .Y(n1600) );
AOI211X1TS U2060 ( .A0(n2176), .A1(n2175), .B0(n2174), .C0(n2173), .Y(n2232)
);
CLKINVX3TS U2061 ( .A(rst), .Y(n1231) );
NAND2X1TS U2062 ( .A(n2120), .B(LZA_output[5]), .Y(n919) );
NOR2X4TS U2063 ( .A(n1712), .B(n1711), .Y(n2036) );
NOR2X4TS U2064 ( .A(n1288), .B(n1287), .Y(n2027) );
AOI222X4TS U2065 ( .A0(n1902), .A1(n1890), .B0(n1328), .B1(n1889), .C0(n1923), .C1(n2653), .Y(n1921) );
AOI222X4TS U2066 ( .A0(n1916), .A1(n2666), .B0(n2710), .B1(n2667), .C0(n1328), .C1(n2653), .Y(n1905) );
AOI22X2TS U2067 ( .A0(n1897), .A1(n2717), .B0(n1896), .B1(n1895), .Y(n2724)
);
NOR2X2TS U2068 ( .A(Add_Subt_result[34]), .B(Add_Subt_result[33]), .Y(n1112)
);
NOR2X4TS U2069 ( .A(n1718), .B(n1717), .Y(n2017) );
NOR2X4TS U2070 ( .A(n1296), .B(n1295), .Y(n2005) );
NOR2XLTS U2071 ( .A(Add_Subt_result[27]), .B(Add_Subt_result[25]), .Y(n932)
);
OAI21XLTS U2072 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[102]), .A1(
n1987), .B0(n1986), .Y(n1990) );
INVX2TS U2073 ( .A(n2133), .Y(n920) );
BUFX3TS U2074 ( .A(n1297), .Y(n2088) );
OR2X1TS U2075 ( .A(n1848), .B(n1847), .Y(n3114) );
OAI211X1TS U2076 ( .A0(Sgf_normalized_result[0]), .A1(
Sgf_normalized_result[1]), .B0(n1567), .C0(n1566), .Y(n2560) );
OR2X1TS U2077 ( .A(Sgf_normalized_result[2]), .B(n1973), .Y(n1356) );
NOR4X2TS U2078 ( .A(FS_Module_state_reg[1]), .B(n2983), .C(n922), .D(n2906),
.Y(FSM_Final_Result_load) );
INVX2TS U2079 ( .A(n2026), .Y(n921) );
OAI22X2TS U2080 ( .A0(n1334), .A1(n2078), .B0(n973), .B1(n1037), .Y(n2086)
);
AOI22X2TS U2081 ( .A0(n2077), .A1(n2049), .B0(n2133), .B1(n2084), .Y(n2065)
);
NOR2X4TS U2082 ( .A(n899), .B(n2919), .Y(n2077) );
NAND2X4TS U2083 ( .A(n1294), .B(n2620), .Y(n2141) );
OAI221X1TS U2084 ( .A0(n2892), .A1(intDY[5]), .B0(n2938), .B1(intDY[4]),
.C0(n1572), .Y(n1583) );
AOI222X1TS U2085 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[93]), .A1(
n2123), .B0(Barrel_Shifter_module_Mux_Array_Data_array[77]), .B1(n1860), .C0(Barrel_Shifter_module_Mux_Array_Data_array[85]), .C1(n1861), .Y(n1310)
);
NOR2X1TS U2086 ( .A(Add_Subt_result[17]), .B(Add_Subt_result[18]), .Y(n965)
);
AND3X1TS U2087 ( .A(n1106), .B(n954), .C(Add_Subt_result[7]), .Y(n1154) );
OAI21XLTS U2088 ( .A0(Add_Subt_result[1]), .A1(Add_Subt_result[2]), .B0(
n1169), .Y(n1170) );
AOI211X1TS U2089 ( .A0(n2092), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(n2091), .C0(n2090), .Y(n2093) );
BUFX3TS U2090 ( .A(n2634), .Y(n2569) );
INVX2TS U2091 ( .A(n1969), .Y(n1973) );
BUFX3TS U2092 ( .A(n2706), .Y(n1558) );
NOR2XLTS U2093 ( .A(n2923), .B(intDY[11]), .Y(n2193) );
OAI21XLTS U2094 ( .A0(intDY[35]), .A1(n2963), .B0(intDY[34]), .Y(n2265) );
NOR2XLTS U2095 ( .A(n2282), .B(intDX[48]), .Y(n2283) );
NOR2XLTS U2096 ( .A(n2213), .B(intDX[16]), .Y(n2214) );
NOR2XLTS U2097 ( .A(Add_Subt_result[30]), .B(Add_Subt_result[24]), .Y(n931)
);
NAND2X1TS U2098 ( .A(n2132), .B(n2006), .Y(n1303) );
NAND2X1TS U2099 ( .A(n2349), .B(n2355), .Y(n1941) );
OAI211XLTS U2100 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[102]),
.A1(n889), .B0(n897), .C0(n1988), .Y(n1989) );
NAND2X2TS U2101 ( .A(n2120), .B(LZA_output[4]), .Y(n2132) );
INVX2TS U2102 ( .A(n1423), .Y(n1403) );
NAND2X1TS U2103 ( .A(n1387), .B(n1386), .Y(n2509) );
OAI21X1TS U2104 ( .A0(n2391), .A1(n1772), .B0(n1780), .Y(n1561) );
NAND2X1TS U2105 ( .A(FS_Module_state_reg[2]), .B(n2555), .Y(n2158) );
AND3X1TS U2106 ( .A(n2672), .B(n2671), .C(n2670), .Y(n2694) );
AND3X1TS U2107 ( .A(n1257), .B(n1256), .C(n1255), .Y(n2651) );
AND3X1TS U2108 ( .A(n2644), .B(n2643), .C(n2642), .Y(n2675) );
AND3X1TS U2109 ( .A(n1660), .B(n1659), .C(n1658), .Y(n2665) );
OA22X1TS U2110 ( .A0(n2603), .A1(n2114), .B0(n2602), .B1(n2118), .Y(n1078)
);
OA22X1TS U2111 ( .A0(n2617), .A1(n2152), .B0(n2615), .B1(n2118), .Y(n1058)
);
OA22X1TS U2112 ( .A0(n2601), .A1(n2152), .B0(n2600), .B1(n2118), .Y(n1069)
);
OA22X1TS U2113 ( .A0(n2598), .A1(n2114), .B0(n2597), .B1(n2118), .Y(n1048)
);
AND3X1TS U2114 ( .A(n1189), .B(n1188), .C(n1187), .Y(n1248) );
INVX2TS U2115 ( .A(n1450), .Y(n2512) );
INVX2TS U2116 ( .A(n2434), .Y(n2444) );
INVX2TS U2117 ( .A(n2364), .Y(n2373) );
NOR3X1TS U2118 ( .A(Add_Subt_result[50]), .B(Add_Subt_result[48]), .C(
Add_Subt_result[49]), .Y(n1111) );
OR2X2TS U2119 ( .A(Add_Subt_result[51]), .B(Add_Subt_result[54]), .Y(n926)
);
NOR2X2TS U2120 ( .A(n927), .B(n926), .Y(n1109) );
NAND2X2TS U2121 ( .A(n1111), .B(n1109), .Y(n1121) );
NOR3X2TS U2122 ( .A(Add_Subt_result[46]), .B(Add_Subt_result[44]), .C(
Add_Subt_result[45]), .Y(n1087) );
NOR3X1TS U2123 ( .A(Add_Subt_result[47]), .B(Add_Subt_result[43]), .C(
Add_Subt_result[42]), .Y(n928) );
NOR2X4TS U2124 ( .A(n1121), .B(n929), .Y(n1137) );
NAND2X4TS U2125 ( .A(n1137), .B(n2918), .Y(n1135) );
NOR2X2TS U2126 ( .A(Add_Subt_result[39]), .B(Add_Subt_result[40]), .Y(n1138)
);
NOR2X2TS U2127 ( .A(Add_Subt_result[38]), .B(Add_Subt_result[37]), .Y(n1163)
);
NOR2X1TS U2128 ( .A(Add_Subt_result[36]), .B(Add_Subt_result[35]), .Y(n946)
);
NOR2X4TS U2129 ( .A(n1135), .B(n930), .Y(n1134) );
NOR2X2TS U2130 ( .A(Add_Subt_result[32]), .B(Add_Subt_result[31]), .Y(n1083)
);
NOR2X1TS U2131 ( .A(Add_Subt_result[29]), .B(Add_Subt_result[28]), .Y(n1090)
);
NOR2X1TS U2132 ( .A(Add_Subt_result[22]), .B(Add_Subt_result[21]), .Y(n935)
);
INVX2TS U2133 ( .A(n950), .Y(n936) );
NOR2X1TS U2134 ( .A(n2607), .B(Add_Subt_result[15]), .Y(n937) );
NOR2X1TS U2135 ( .A(Add_Subt_result[14]), .B(Add_Subt_result[13]), .Y(n1120)
);
INVX2TS U2136 ( .A(n1120), .Y(n938) );
NOR2X4TS U2137 ( .A(n2610), .B(n938), .Y(n1127) );
NAND2X4TS U2138 ( .A(n1127), .B(n2931), .Y(n1125) );
NOR3BX4TS U2139 ( .AN(n954), .B(n953), .C(Add_Subt_result[7]), .Y(n2604) );
NAND2X2TS U2140 ( .A(n2604), .B(n1103), .Y(n952) );
NOR2X4TS U2141 ( .A(n952), .B(Add_Subt_result[4]), .Y(n1098) );
NAND2BX2TS U2142 ( .AN(Add_Subt_result[3]), .B(n1098), .Y(n1168) );
NOR2X2TS U2143 ( .A(n1168), .B(Add_Subt_result[2]), .Y(n1133) );
NAND2X2TS U2144 ( .A(n1133), .B(Add_Subt_result[0]), .Y(n2611) );
INVX2TS U2145 ( .A(n1134), .Y(n1113) );
INVX2TS U2146 ( .A(n1112), .Y(n939) );
INVX2TS U2147 ( .A(n1083), .Y(n940) );
NAND2X2TS U2148 ( .A(n947), .B(n941), .Y(n1160) );
NAND2X1TS U2149 ( .A(n3024), .B(Add_Subt_result[27]), .Y(n942) );
NOR2X1TS U2150 ( .A(n1160), .B(n942), .Y(n1122) );
INVX2TS U2151 ( .A(Add_Subt_result[29]), .Y(n1226) );
INVX2TS U2152 ( .A(n1163), .Y(n945) );
INVX2TS U2153 ( .A(n1135), .Y(n943) );
NAND2X1TS U2154 ( .A(n943), .B(n1138), .Y(n1162) );
NAND2X1TS U2155 ( .A(n1084), .B(Add_Subt_result[23]), .Y(n1080) );
OAI31X1TS U2156 ( .A0(n946), .A1(n945), .A2(n1162), .B0(n1080), .Y(n948) );
INVX2TS U2157 ( .A(n947), .Y(n1146) );
NOR2X1TS U2158 ( .A(n1146), .B(n1083), .Y(n1115) );
AOI211X1TS U2159 ( .A0(n1122), .A1(n1226), .B0(n948), .C0(n1115), .Y(n949)
);
NOR2X2TS U2160 ( .A(n1160), .B(Add_Subt_result[27]), .Y(n1089) );
INVX2TS U2161 ( .A(n1081), .Y(n1161) );
OAI211X1TS U2162 ( .A0(n950), .A1(n1099), .B0(n949), .C0(n1091), .Y(n951) );
AOI2BB1X1TS U2163 ( .A0N(Add_Subt_result[3]), .A1N(Add_Subt_result[4]), .B0(
n952), .Y(n958) );
INVX2TS U2164 ( .A(n953), .Y(n1106) );
NOR3BX1TS U2165 ( .AN(Add_Subt_result[8]), .B(Add_Subt_result[10]), .C(
Add_Subt_result[9]), .Y(n955) );
OAI31X1TS U2166 ( .A0(Add_Subt_result[12]), .A1(Add_Subt_result[11]), .A2(
n955), .B0(n1127), .Y(n956) );
OAI31X1TS U2167 ( .A0(n2607), .A1(n1150), .A2(n2999), .B0(n956), .Y(n957) );
NOR3X1TS U2168 ( .A(n958), .B(n1154), .C(n957), .Y(n2612) );
NOR2BX1TS U2169 ( .AN(Add_Subt_result[28]), .B(n1160), .Y(n1117) );
AOI31XLTS U2170 ( .A0(n2913), .A1(Add_Subt_result[44]), .A2(n3054), .B0(
Add_Subt_result[47]), .Y(n962) );
NOR3BX1TS U2171 ( .AN(Add_Subt_result[48]), .B(Add_Subt_result[50]), .C(
Add_Subt_result[49]), .Y(n960) );
OAI31X1TS U2172 ( .A0(n960), .A1(Add_Subt_result[52]), .A2(
Add_Subt_result[51]), .B0(n959), .Y(n961) );
AOI211X1TS U2173 ( .A0(n1117), .A1(n1226), .B0(n964), .C0(n963), .Y(n967) );
AOI21X1TS U2174 ( .A0(n922), .A1(FSM_selector_C), .B0(FS_Module_state_reg[0]), .Y(n968) );
AOI211X2TS U2175 ( .A0(n2620), .A1(FS_Module_state_reg[2]), .B0(n968), .C0(
n2915), .Y(n969) );
NOR2X2TS U2176 ( .A(FSM_selector_B[1]), .B(FSM_selector_B[0]), .Y(n988) );
INVX2TS U2177 ( .A(n988), .Y(n973) );
NAND2X1TS U2178 ( .A(n2120), .B(n892), .Y(n1029) );
OAI2BB1X1TS U2179 ( .A0N(n1178), .A1N(DmP[55]), .B0(n1029), .Y(n971) );
XOR2X1TS U2180 ( .A(n970), .B(n971), .Y(n980) );
INVX4TS U2181 ( .A(FSM_selector_D), .Y(n1969) );
INVX4TS U2182 ( .A(n1969), .Y(n1933) );
NAND2X1TS U2183 ( .A(n2120), .B(LZA_output[2]), .Y(n1175) );
OAI2BB1X1TS U2184 ( .A0N(n1178), .A1N(DmP[54]), .B0(n1175), .Y(n972) );
XOR2X1TS U2185 ( .A(n917), .B(n972), .Y(n1010) );
NAND2X1TS U2186 ( .A(n2120), .B(LZA_output[1]), .Y(n1180) );
OAI2BB1X1TS U2187 ( .A0N(n2129), .A1N(DmP[53]), .B0(n1180), .Y(n974) );
XOR2X1TS U2188 ( .A(n917), .B(n974), .Y(n987) );
AOI2BB2X1TS U2189 ( .B0(n2120), .B1(LZA_output[0]), .A0N(FSM_selector_B[0]),
.A1N(n2914), .Y(n1177) );
OAI2BB1X1TS U2190 ( .A0N(DmP[52]), .A1N(n2917), .B0(n1177), .Y(n975) );
NAND2X1TS U2191 ( .A(n2120), .B(LZA_output[5]), .Y(n1688) );
OAI2BB1X1TS U2192 ( .A0N(n1178), .A1N(DmP[57]), .B0(n1688), .Y(n976) );
XOR2X1TS U2193 ( .A(n970), .B(n976), .Y(n984) );
XOR2X1TS U2194 ( .A(n970), .B(n981), .Y(n993) );
XOR2X1TS U2195 ( .A(n970), .B(n989), .Y(n997) );
XOR2X1TS U2196 ( .A(n970), .B(n990), .Y(n1004) );
XOR2X1TS U2197 ( .A(n970), .B(n994), .Y(n1001) );
XOR2X1TS U2198 ( .A(n917), .B(n998), .Y(n1015) );
OR4X2TS U2199 ( .A(Exp_Operation_Module_Data_S[3]), .B(
Exp_Operation_Module_Data_S[2]), .C(Exp_Operation_Module_Data_S[1]),
.D(Exp_Operation_Module_Data_S[0]), .Y(n1018) );
OR4X2TS U2200 ( .A(Exp_Operation_Module_Data_S[6]), .B(
Exp_Operation_Module_Data_S[5]), .C(Exp_Operation_Module_Data_S[4]),
.D(n1018), .Y(n1019) );
OR4X2TS U2201 ( .A(Exp_Operation_Module_Data_S[9]), .B(
Exp_Operation_Module_Data_S[8]), .C(Exp_Operation_Module_Data_S[7]),
.D(n1019), .Y(n1020) );
NOR2X2TS U2202 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[3]), .Y(
n2555) );
NOR2X1TS U2203 ( .A(n2906), .B(FS_Module_state_reg[2]), .Y(n1568) );
NAND2X1TS U2204 ( .A(n1568), .B(n1021), .Y(n1569) );
MXI2X4TS U2205 ( .A(n3056), .B(n1022), .S0(n883), .Y(n861) );
NOR2X1TS U2206 ( .A(FS_Module_state_reg[1]), .B(n2620), .Y(n1354) );
NAND2X1TS U2207 ( .A(n1023), .B(n1354), .Y(n2884) );
NAND2X2TS U2208 ( .A(n1024), .B(add_overflow_flag), .Y(n2568) );
INVX2TS U2209 ( .A(n2568), .Y(n1646) );
NAND2X1TS U2210 ( .A(n1178), .B(exp_oper_result[5]), .Y(n1694) );
INVX2TS U2211 ( .A(n2002), .Y(n1987) );
AOI22X4TS U2212 ( .A0(n2120), .A1(n889), .B0(n1987), .B1(n2129), .Y(n1846)
);
NAND2X1TS U2213 ( .A(n1178), .B(exp_oper_result[4]), .Y(n2006) );
INVX2TS U2214 ( .A(n1303), .Y(n1030) );
NAND2X1TS U2215 ( .A(n1178), .B(n901), .Y(n1028) );
NAND2X1TS U2216 ( .A(n1029), .B(n1028), .Y(n1031) );
NOR2X4TS U2217 ( .A(n1030), .B(n1031), .Y(n1070) );
INVX2TS U2218 ( .A(n2120), .Y(n1334) );
NOR2X4TS U2219 ( .A(n900), .B(exp_oper_result[4]), .Y(n1860) );
INVX2TS U2220 ( .A(n1860), .Y(n1037) );
NOR2X4TS U2221 ( .A(n2568), .B(n1036), .Y(n1071) );
AOI21X1TS U2222 ( .A0(n921), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[99]), .B0(n1071), .Y(n1032)
);
NAND2BX1TS U2223 ( .AN(n1033), .B(n1032), .Y(n2584) );
OAI21X4TS U2224 ( .A0(n894), .A1(n1987), .B0(n2914), .Y(n1758) );
AOI21X1TS U2225 ( .A0(n886), .A1(n890), .B0(n1758), .Y(n1745) );
INVX2TS U2226 ( .A(exp_oper_result[4]), .Y(n2627) );
NOR2X4TS U2227 ( .A(n2627), .B(n901), .Y(n1861) );
AOI22X1TS U2228 ( .A0(n893), .A1(n1861), .B0(n886), .B1(n1035), .Y(n2079) );
NOR2X4TS U2229 ( .A(n1025), .B(n1036), .Y(n2143) );
INVX2TS U2230 ( .A(n2143), .Y(n1066) );
OAI22X4TS U2231 ( .A0(n894), .A1(n1037), .B0(n898), .B1(n2078), .Y(n2072) );
OAI2BB2XLTS U2232 ( .B0(n1066), .B1(n2970), .A0N(n1350), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[67]), .Y(n1038) );
AOI211X1TS U2233 ( .A0(n2126), .A1(n2584), .B0(n1039), .C0(n1038), .Y(n2596)
);
NAND2X2TS U2234 ( .A(n1042), .B(n1041), .Y(n1076) );
NAND2X2TS U2235 ( .A(n908), .B(n2152), .Y(n2118) );
NAND2X1TS U2236 ( .A(n1026), .B(n1043), .Y(
Barrel_Shifter_module_Data_Reg[50]) );
AOI21X1TS U2237 ( .A0(n921), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[98]), .B0(n1071), .Y(n1044)
);
NAND2BX1TS U2238 ( .AN(n1045), .B(n1044), .Y(n2580) );
OAI2BB2XLTS U2239 ( .B0(n1066), .B1(n3053), .A0N(n1350), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[66]), .Y(n1046) );
AOI211X1TS U2240 ( .A0(n1025), .A1(n2580), .B0(n1047), .C0(n1046), .Y(n2598)
);
NAND2X1TS U2241 ( .A(n1026), .B(n1048), .Y(
Barrel_Shifter_module_Data_Reg[51]) );
AOI21X1TS U2242 ( .A0(n921), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[100]), .B0(n1071), .Y(n1049) );
NAND2BX1TS U2243 ( .AN(n1050), .B(n1049), .Y(n2587) );
OAI2BB2XLTS U2244 ( .B0(n1066), .B1(n2971), .A0N(n1350), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[68]), .Y(n1051) );
AOI211X1TS U2245 ( .A0(n2126), .A1(n2587), .B0(n1052), .C0(n1051), .Y(n2594)
);
NAND2X1TS U2246 ( .A(n1026), .B(n1053), .Y(
Barrel_Shifter_module_Data_Reg[49]) );
AOI21X1TS U2247 ( .A0(n2086), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[96]), .B0(n1071), .Y(n1054)
);
NAND2BX1TS U2248 ( .AN(n1055), .B(n1054), .Y(n2574) );
OAI2BB2XLTS U2249 ( .B0(n1066), .B1(n2974), .A0N(n1350), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[64]), .Y(n1056) );
AOI211X1TS U2250 ( .A0(n2126), .A1(n2574), .B0(n1057), .C0(n1056), .Y(n2617)
);
NAND2X1TS U2251 ( .A(n1026), .B(n1058), .Y(
Barrel_Shifter_module_Data_Reg[53]) );
AOI21X1TS U2252 ( .A0(n921), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[101]), .B0(n1071), .Y(n1059) );
NAND2BX1TS U2253 ( .AN(n1060), .B(n1059), .Y(n2115) );
OAI2BB2XLTS U2254 ( .B0(n1066), .B1(n2972), .A0N(n1350), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[69]), .Y(n1061) );
AOI211X1TS U2255 ( .A0(n2126), .A1(n2115), .B0(n1062), .C0(n1061), .Y(n2592)
);
NAND2X1TS U2256 ( .A(n1026), .B(n1063), .Y(
Barrel_Shifter_module_Data_Reg[48]) );
AOI21X1TS U2257 ( .A0(n2086), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[97]), .B0(n1071), .Y(n1064)
);
NAND2BX1TS U2258 ( .AN(n1065), .B(n1064), .Y(n2577) );
OAI2BB2XLTS U2259 ( .B0(n1066), .B1(n2973), .A0N(n1350), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[65]), .Y(n1067) );
AOI211X1TS U2260 ( .A0(n2126), .A1(n2577), .B0(n1068), .C0(n1067), .Y(n2601)
);
NAND2X1TS U2261 ( .A(n1026), .B(n1069), .Y(
Barrel_Shifter_module_Data_Reg[52]) );
AOI21X1TS U2262 ( .A0(n2086), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[95]), .B0(n1071), .Y(n1072)
);
NAND2BX1TS U2263 ( .AN(n1073), .B(n1072), .Y(n2570) );
AOI211X1TS U2264 ( .A0(n1025), .A1(n2570), .B0(n1075), .C0(n1074), .Y(n2603)
);
NAND2X1TS U2265 ( .A(n1026), .B(n1078), .Y(
Barrel_Shifter_module_Data_Reg[54]) );
AND3X1TS U2266 ( .A(n2555), .B(n2983), .C(FS_Module_state_reg[0]), .Y(n871)
);
NAND2X1TS U2267 ( .A(n1089), .B(Add_Subt_result[25]), .Y(n1171) );
OAI211X1TS U2268 ( .A0(n1171), .A1(n1081), .B0(n1080), .C0(n1079), .Y(n1152)
);
OAI211XLTS U2269 ( .A0(Add_Subt_result[10]), .A1(Add_Subt_result[8]), .B0(
n1082), .C0(n3020), .Y(n1093) );
NAND2X1TS U2270 ( .A(n1083), .B(Add_Subt_result[30]), .Y(n1085) );
OAI2BB2X1TS U2271 ( .B0(n1146), .B1(n1085), .A0N(Add_Subt_result[22]), .A1N(
n1084), .Y(n1166) );
INVX2TS U2272 ( .A(n1166), .Y(n1086) );
OAI31X1TS U2273 ( .A0(n1087), .A1(Add_Subt_result[47]), .A2(n1121), .B0(
n1086), .Y(n1088) );
NOR3BX1TS U2274 ( .AN(Add_Subt_result[19]), .B(n1099), .C(
Add_Subt_result[20]), .Y(n1097) );
NAND2X1TS U2275 ( .A(n1116), .B(Add_Subt_result[21]), .Y(n1159) );
AOI21X1TS U2276 ( .A0(n2912), .A1(Add_Subt_result[39]), .B0(
Add_Subt_result[41]), .Y(n1095) );
OAI22X1TS U2277 ( .A0(n1159), .A1(Add_Subt_result[22]), .B0(n1095), .B1(
n1094), .Y(n1096) );
AOI211X1TS U2278 ( .A0(n1098), .A1(Add_Subt_result[3]), .B0(n1097), .C0(
n1096), .Y(n1158) );
AOI211X1TS U2279 ( .A0(n3055), .A1(n2912), .B0(n1100), .C0(
Add_Subt_result[43]), .Y(n1101) );
AOI21X1TS U2280 ( .A0(n1102), .A1(Add_Subt_result[20]), .B0(n1101), .Y(n1105) );
INVX2TS U2281 ( .A(n1103), .Y(n2605) );
INVX2TS U2282 ( .A(n1154), .Y(n1107) );
NAND2X1TS U2283 ( .A(n1106), .B(Add_Subt_result[9]), .Y(n1131) );
INVX2TS U2284 ( .A(n1109), .Y(n1110) );
OAI22X1TS U2285 ( .A0(n1113), .A1(n1112), .B0(n1111), .B1(n1110), .Y(n1114)
);
AOI211X1TS U2286 ( .A0(n1116), .A1(Add_Subt_result[22]), .B0(n1115), .C0(
n1114), .Y(n1119) );
INVX2TS U2287 ( .A(n1117), .Y(n1118) );
OAI22X1TS U2288 ( .A0(n1160), .A1(n1226), .B0(n1121), .B1(n3022), .Y(n1123)
);
OAI21X1TS U2289 ( .A0(n1125), .A1(n3020), .B0(n1124), .Y(n1153) );
AOI211X1TS U2290 ( .A0(n1127), .A1(Add_Subt_result[12]), .B0(n1126), .C0(
n1153), .Y(n1128) );
NAND2X1TS U2291 ( .A(n1129), .B(n1128), .Y(
Leading_Zero_Detector_Module_Codec_to_Reg[2]) );
NOR2X2TS U2292 ( .A(n1238), .B(n922), .Y(n2561) );
INVX2TS U2293 ( .A(n2561), .Y(n1130) );
NOR2XLTS U2294 ( .A(FS_Module_state_reg[1]), .B(n1130), .Y(FSM_LZA_load) );
OAI31X1TS U2295 ( .A0(Add_Subt_result[14]), .A1(n2610), .A2(n3026), .B0(
n1131), .Y(n1132) );
AOI21X1TS U2296 ( .A0(n1133), .A1(Add_Subt_result[1]), .B0(n1132), .Y(n2613)
);
AOI21X1TS U2297 ( .A0(n2921), .A1(Add_Subt_result[15]), .B0(
Add_Subt_result[17]), .Y(n1151) );
NOR3BX1TS U2298 ( .AN(Add_Subt_result[35]), .B(n1135), .C(
Add_Subt_result[36]), .Y(n1136) );
AOI21X1TS U2299 ( .A0(Add_Subt_result[37]), .A1(n1137), .B0(n1136), .Y(n1145) );
INVX2TS U2300 ( .A(n1138), .Y(n1144) );
AOI21X1TS U2301 ( .A0(n3025), .A1(Add_Subt_result[49]), .B0(
Add_Subt_result[51]), .Y(n1139) );
OAI31X1TS U2302 ( .A0(n1145), .A1(Add_Subt_result[38]), .A2(n1144), .B0(
n1143), .Y(n1148) );
NOR3BX1TS U2303 ( .AN(Add_Subt_result[31]), .B(n1146), .C(
Add_Subt_result[32]), .Y(n1147) );
AOI211X1TS U2304 ( .A0(n1164), .A1(n3052), .B0(n1148), .C0(n1147), .Y(n1149)
);
OAI31X1TS U2305 ( .A0(Add_Subt_result[18]), .A1(n1151), .A2(n1150), .B0(
n1149), .Y(n1155) );
NOR4X1TS U2306 ( .A(n1155), .B(n1154), .C(n1153), .D(n1152), .Y(n1157) );
AOI21X1TS U2307 ( .A0(n1163), .A1(n3052), .B0(n1162), .Y(n1165) );
NOR4X1TS U2308 ( .A(n1167), .B(n1166), .C(n1165), .D(n1164), .Y(n1172) );
INVX2TS U2309 ( .A(n1168), .Y(n1169) );
NAND2X1TS U2310 ( .A(n2129), .B(exp_oper_result[2]), .Y(n1174) );
NAND2X4TS U2311 ( .A(n1175), .B(n1174), .Y(n2706) );
INVX2TS U2312 ( .A(n1558), .Y(n1333) );
NAND2X1TS U2313 ( .A(n2917), .B(exp_oper_result[0]), .Y(n1176) );
NAND2X2TS U2314 ( .A(n1177), .B(n1176), .Y(n1895) );
NAND2X1TS U2315 ( .A(n1178), .B(exp_oper_result[1]), .Y(n1179) );
NAND2X2TS U2316 ( .A(n1895), .B(n2725), .Y(n1661) );
INVX2TS U2317 ( .A(n1661), .Y(n2678) );
INVX2TS U2318 ( .A(FSM_selector_C), .Y(n2736) );
BUFX3TS U2319 ( .A(n2736), .Y(n2841) );
NAND2X1TS U2320 ( .A(n1244), .B(Add_Subt_result[37]), .Y(n1182) );
INVX2TS U2321 ( .A(n2573), .Y(n2744) );
AOI22X1TS U2322 ( .A0(n895), .A1(Add_Subt_result[17]), .B0(DmP[35]), .B1(
n3023), .Y(n1181) );
NAND2X2TS U2323 ( .A(n1182), .B(n1181), .Y(n1329) );
NAND2X1TS U2324 ( .A(n2678), .B(n1329), .Y(n1189) );
OR2X2TS U2325 ( .A(n1895), .B(n1922), .Y(n1667) );
INVX2TS U2326 ( .A(n1667), .Y(n2680) );
NAND2X1TS U2327 ( .A(n1244), .B(Add_Subt_result[36]), .Y(n1184) );
AOI22X1TS U2328 ( .A0(n1265), .A1(Add_Subt_result[18]), .B0(DmP[34]), .B1(
n3023), .Y(n1183) );
NAND2X2TS U2329 ( .A(n1184), .B(n1183), .Y(n1275) );
NAND2X1TS U2330 ( .A(n2680), .B(n1275), .Y(n1188) );
AND2X2TS U2331 ( .A(n1895), .B(n1922), .Y(n2669) );
NAND2X1TS U2332 ( .A(n1244), .B(Add_Subt_result[39]), .Y(n1186) );
AOI22X1TS U2333 ( .A0(n1909), .A1(Add_Subt_result[15]), .B0(DmP[37]), .B1(
n2736), .Y(n1185) );
NAND2X1TS U2334 ( .A(n1186), .B(n1185), .Y(n1271) );
NAND2X1TS U2335 ( .A(n2669), .B(n1271), .Y(n1187) );
BUFX3TS U2336 ( .A(n2706), .Y(n1331) );
INVX2TS U2337 ( .A(n1661), .Y(n1890) );
INVX2TS U2338 ( .A(n2766), .Y(n2860) );
NAND2X1TS U2339 ( .A(n2860), .B(Add_Subt_result[33]), .Y(n1191) );
BUFX3TS U2340 ( .A(n2736), .Y(n1891) );
AOI22X1TS U2341 ( .A0(n2859), .A1(Add_Subt_result[21]), .B0(DmP[31]), .B1(
n1891), .Y(n1190) );
NAND2X2TS U2342 ( .A(n1191), .B(n1190), .Y(n1923) );
NAND2X1TS U2343 ( .A(n1890), .B(n1923), .Y(n1198) );
INVX2TS U2344 ( .A(n1667), .Y(n1889) );
NAND2X1TS U2345 ( .A(n2860), .B(Add_Subt_result[32]), .Y(n1193) );
AOI22X1TS U2346 ( .A0(n1265), .A1(Add_Subt_result[22]), .B0(DmP[30]), .B1(
n1891), .Y(n1192) );
NAND2X2TS U2347 ( .A(n1193), .B(n1192), .Y(n1902) );
NAND2X1TS U2348 ( .A(n2667), .B(n1902), .Y(n1197) );
NAND2X1TS U2349 ( .A(n1244), .B(Add_Subt_result[35]), .Y(n1195) );
AOI22X1TS U2350 ( .A0(n1909), .A1(Add_Subt_result[19]), .B0(DmP[33]), .B1(
n1891), .Y(n1194) );
NAND2X1TS U2351 ( .A(n1195), .B(n1194), .Y(n1276) );
NAND2X1TS U2352 ( .A(n2669), .B(n1276), .Y(n1196) );
OR2X2TS U2353 ( .A(n1895), .B(n2725), .Y(n1207) );
NAND2X1TS U2354 ( .A(n1244), .B(Add_Subt_result[38]), .Y(n1200) );
AOI22X1TS U2355 ( .A0(n1265), .A1(Add_Subt_result[16]), .B0(DmP[36]), .B1(
n3023), .Y(n1199) );
NAND2X2TS U2356 ( .A(n1200), .B(n1199), .Y(n1325) );
NOR2X2TS U2357 ( .A(n1207), .B(n1558), .Y(n2868) );
BUFX3TS U2358 ( .A(n2868), .Y(n2844) );
NAND2X1TS U2359 ( .A(n1244), .B(Add_Subt_result[34]), .Y(n1202) );
AOI22X1TS U2360 ( .A0(n1265), .A1(Add_Subt_result[20]), .B0(DmP[32]), .B1(
n1891), .Y(n1201) );
NAND2X2TS U2361 ( .A(n1202), .B(n1201), .Y(n1917) );
AOI22X1TS U2362 ( .A0(n2645), .A1(n1325), .B0(n2844), .B1(n1917), .Y(n1203)
);
OAI221XLTS U2363 ( .A0(n1333), .A1(n1248), .B0(n1331), .B1(n1324), .C0(n1203), .Y(Barrel_Shifter_module_Mux_Array_Data_array[32]) );
NAND2X1TS U2364 ( .A(n1890), .B(n1325), .Y(n1206) );
NAND2X1TS U2365 ( .A(n2679), .B(n1271), .Y(n1205) );
NAND2X1TS U2366 ( .A(n1889), .B(n1329), .Y(n1204) );
NAND2X1TS U2367 ( .A(n2678), .B(n1917), .Y(n1210) );
INVX2TS U2368 ( .A(n1207), .Y(n2653) );
NAND2X1TS U2369 ( .A(n2653), .B(n1276), .Y(n1209) );
NAND2X1TS U2370 ( .A(n2680), .B(n1923), .Y(n1208) );
INVX2TS U2371 ( .A(n2669), .Y(n1211) );
BUFX3TS U2372 ( .A(n2706), .Y(n2711) );
NOR2X4TS U2373 ( .A(n1211), .B(n2711), .Y(n2779) );
BUFX3TS U2374 ( .A(n2779), .Y(n2703) );
NOR2X2TS U2375 ( .A(n1211), .B(n2726), .Y(n2648) );
BUFX3TS U2376 ( .A(n2648), .Y(n2701) );
NAND2X1TS U2377 ( .A(n1244), .B(Add_Subt_result[40]), .Y(n1213) );
INVX2TS U2378 ( .A(n2573), .Y(n1265) );
AOI22X1TS U2379 ( .A0(n2616), .A1(Add_Subt_result[14]), .B0(DmP[38]), .B1(
n3023), .Y(n1212) );
NAND2X2TS U2380 ( .A(n1213), .B(n1212), .Y(n1284) );
AOI22X1TS U2381 ( .A0(n2703), .A1(n1275), .B0(n2701), .B1(n1284), .Y(n1214)
);
OAI221XLTS U2382 ( .A0(n1333), .A1(n1286), .B0(n1331), .B1(n1229), .C0(n1214), .Y(Barrel_Shifter_module_Mux_Array_Data_array[33]) );
NAND2X1TS U2383 ( .A(n2666), .B(n1271), .Y(n1217) );
NAND2X1TS U2384 ( .A(n2653), .B(n1284), .Y(n1216) );
NAND2X1TS U2385 ( .A(n2667), .B(n1325), .Y(n1215) );
NAND2X1TS U2386 ( .A(n2666), .B(n1276), .Y(n1220) );
NAND2X1TS U2387 ( .A(n2679), .B(n1275), .Y(n1219) );
NAND2X1TS U2388 ( .A(n2667), .B(n1917), .Y(n1218) );
NAND2X1TS U2389 ( .A(n1244), .B(Add_Subt_result[41]), .Y(n1222) );
AOI22X1TS U2390 ( .A0(n2859), .A1(Add_Subt_result[13]), .B0(DmP[39]), .B1(
n2736), .Y(n1221) );
NAND2X2TS U2391 ( .A(n1222), .B(n1221), .Y(n2702) );
AOI22X1TS U2392 ( .A0(n2703), .A1(n1329), .B0(n2701), .B1(n2702), .Y(n1223)
);
OAI221XLTS U2393 ( .A0(n1333), .A1(n2705), .B0(n1331), .B1(n1332), .C0(n1223), .Y(Barrel_Shifter_module_Mux_Array_Data_array[34]) );
INVX2TS U2394 ( .A(n2766), .Y(n1907) );
AOI22X1TS U2395 ( .A0(n1265), .A1(Add_Subt_result[24]), .B0(n1891), .B1(
DmP[28]), .Y(n1224) );
OAI2BB1X2TS U2396 ( .A0N(Add_Subt_result[30]), .A1N(n1907), .B0(n1224), .Y(
n1916) );
AOI22X1TS U2397 ( .A0(n2744), .A1(Add_Subt_result[25]), .B0(n1891), .B1(
DmP[27]), .Y(n1225) );
AOI22X1TS U2398 ( .A0(n2616), .A1(Add_Subt_result[23]), .B0(n1891), .B1(
DmP[29]), .Y(n1227) );
OAI2BB1X1TS U2399 ( .A0N(Add_Subt_result[31]), .A1N(n2860), .B0(n1227), .Y(
n1328) );
BUFX3TS U2400 ( .A(n2779), .Y(n2854) );
AOI22X1TS U2401 ( .A0(n2854), .A1(n1902), .B0(n2701), .B1(n1275), .Y(n1228)
);
OAI221XLTS U2402 ( .A0(n1333), .A1(n1229), .B0(n1331), .B1(n1905), .C0(n1228), .Y(Barrel_Shifter_module_Mux_Array_Data_array[29]) );
CLKBUFX3TS U2403 ( .A(n1231), .Y(n1233) );
BUFX3TS U2404 ( .A(n1233), .Y(n3064) );
CLKBUFX3TS U2405 ( .A(n1231), .Y(n1230) );
BUFX3TS U2406 ( .A(n1230), .Y(n3082) );
BUFX3TS U2407 ( .A(n1233), .Y(n3093) );
CLKBUFX3TS U2408 ( .A(n1231), .Y(n1232) );
BUFX3TS U2409 ( .A(n1232), .Y(n3097) );
BUFX3TS U2410 ( .A(n1232), .Y(n3098) );
CLKBUFX3TS U2411 ( .A(n1231), .Y(n1235) );
BUFX3TS U2412 ( .A(n1235), .Y(n3068) );
BUFX3TS U2413 ( .A(n1231), .Y(n3067) );
BUFX3TS U2414 ( .A(n1230), .Y(n3084) );
BUFX3TS U2415 ( .A(n1233), .Y(n3073) );
BUFX3TS U2416 ( .A(n1231), .Y(n3066) );
BUFX3TS U2417 ( .A(n1230), .Y(n3083) );
BUFX3TS U2418 ( .A(n1230), .Y(n3065) );
CLKBUFX3TS U2419 ( .A(n1231), .Y(n1234) );
BUFX3TS U2420 ( .A(n1234), .Y(n3100) );
BUFX3TS U2421 ( .A(n1231), .Y(n3080) );
BUFX3TS U2422 ( .A(n1234), .Y(n3101) );
BUFX3TS U2423 ( .A(n1232), .Y(n3094) );
BUFX3TS U2424 ( .A(n1230), .Y(n3077) );
BUFX3TS U2425 ( .A(n1232), .Y(n3079) );
BUFX3TS U2426 ( .A(n1234), .Y(n3078) );
BUFX3TS U2427 ( .A(n1235), .Y(n3060) );
BUFX3TS U2428 ( .A(n1235), .Y(n3081) );
BUFX3TS U2429 ( .A(n1232), .Y(n3059) );
BUFX3TS U2430 ( .A(n1233), .Y(n3076) );
BUFX3TS U2431 ( .A(n1232), .Y(n3099) );
BUFX3TS U2432 ( .A(n1232), .Y(n3072) );
BUFX3TS U2433 ( .A(n1230), .Y(n3086) );
BUFX3TS U2434 ( .A(n1230), .Y(n3087) );
BUFX3TS U2435 ( .A(n1230), .Y(n3069) );
BUFX3TS U2436 ( .A(n1233), .Y(n3088) );
BUFX3TS U2437 ( .A(n1231), .Y(n3070) );
BUFX3TS U2438 ( .A(n1230), .Y(n3085) );
BUFX3TS U2439 ( .A(n1232), .Y(n3096) );
CLKBUFX3TS U2440 ( .A(n1234), .Y(n3102) );
BUFX3TS U2441 ( .A(n1231), .Y(n3071) );
BUFX3TS U2442 ( .A(n1232), .Y(n3095) );
BUFX3TS U2443 ( .A(n1235), .Y(n3074) );
BUFX3TS U2444 ( .A(n1233), .Y(n3091) );
BUFX3TS U2445 ( .A(n1233), .Y(n3089) );
BUFX3TS U2446 ( .A(n1233), .Y(n3092) );
BUFX3TS U2447 ( .A(n1235), .Y(n3108) );
BUFX3TS U2448 ( .A(n1235), .Y(n3061) );
BUFX3TS U2449 ( .A(n1234), .Y(n3104) );
BUFX3TS U2450 ( .A(n1234), .Y(n3105) );
BUFX3TS U2451 ( .A(n1235), .Y(n3107) );
BUFX3TS U2452 ( .A(n1233), .Y(n3090) );
BUFX3TS U2453 ( .A(n1235), .Y(n3106) );
BUFX3TS U2454 ( .A(n1234), .Y(n3075) );
BUFX3TS U2455 ( .A(n1235), .Y(n3062) );
BUFX3TS U2456 ( .A(n1234), .Y(n3103) );
BUFX3TS U2457 ( .A(n1234), .Y(n3063) );
CLKBUFX3TS U2458 ( .A(n1235), .Y(n3109) );
BUFX3TS U2459 ( .A(n1236), .Y(n2628) );
NAND2X1TS U2460 ( .A(n2628), .B(n2924), .Y(
final_result_ieee_Module_Exp_S_mux[5]) );
NAND2X1TS U2461 ( .A(n2628), .B(n1729), .Y(
final_result_ieee_Module_Exp_S_mux[3]) );
NOR2X2TS U2462 ( .A(n1238), .B(n1237), .Y(n873) );
NAND2X1TS U2463 ( .A(n1890), .B(n2702), .Y(n1243) );
NAND2X1TS U2464 ( .A(n2667), .B(n1284), .Y(n1242) );
NAND2X1TS U2465 ( .A(n1244), .B(Add_Subt_result[43]), .Y(n1240) );
AOI22X1TS U2466 ( .A0(n1909), .A1(Add_Subt_result[11]), .B0(DmP[41]), .B1(
n2736), .Y(n1239) );
NAND2X1TS U2467 ( .A(n2669), .B(n2677), .Y(n1241) );
BUFX3TS U2468 ( .A(n2868), .Y(n2832) );
BUFX3TS U2469 ( .A(n2645), .Y(n2870) );
NAND2X1TS U2470 ( .A(n1244), .B(Add_Subt_result[42]), .Y(n1246) );
AOI22X1TS U2471 ( .A0(n2859), .A1(Add_Subt_result[12]), .B0(DmP[40]), .B1(
n3023), .Y(n1245) );
NAND2X2TS U2472 ( .A(n1246), .B(n1245), .Y(n2696) );
AOI22X1TS U2473 ( .A0(n2832), .A1(n1325), .B0(n2870), .B1(n2696), .Y(n1247)
);
OAI221XLTS U2474 ( .A0(n2708), .A1(n2693), .B0(n1331), .B1(n1248), .C0(n1247), .Y(Barrel_Shifter_module_Mux_Array_Data_array[36]) );
NAND2X1TS U2475 ( .A(n1651), .B(Add_Subt_result[48]), .Y(n1250) );
BUFX3TS U2476 ( .A(n2736), .Y(n2818) );
AOI22X1TS U2477 ( .A0(n2859), .A1(Add_Subt_result[6]), .B0(DmP[46]), .B1(
n2818), .Y(n1249) );
NAND2X2TS U2478 ( .A(n1250), .B(n1249), .Y(n2687) );
NAND2X1TS U2479 ( .A(n1890), .B(n2687), .Y(n1257) );
NAND2X1TS U2480 ( .A(n1651), .B(Add_Subt_result[49]), .Y(n1252) );
AOI22X1TS U2481 ( .A0(n895), .A1(Add_Subt_result[5]), .B0(DmP[47]), .B1(
n2818), .Y(n1251) );
NAND2X2TS U2482 ( .A(n1252), .B(n1251), .Y(n2684) );
NAND2X1TS U2483 ( .A(n2679), .B(n2684), .Y(n1256) );
NAND2X1TS U2484 ( .A(n1651), .B(Add_Subt_result[47]), .Y(n1254) );
AOI22X1TS U2485 ( .A0(n1909), .A1(Add_Subt_result[7]), .B0(DmP[45]), .B1(
n2818), .Y(n1253) );
NAND2X1TS U2486 ( .A(n1254), .B(n1253), .Y(n2668) );
NAND2X1TS U2487 ( .A(n2667), .B(n2668), .Y(n1255) );
NAND2X1TS U2488 ( .A(n1651), .B(Add_Subt_result[44]), .Y(n1259) );
AOI22X1TS U2489 ( .A0(n2859), .A1(Add_Subt_result[10]), .B0(DmP[42]), .B1(
n2818), .Y(n1258) );
NAND2X2TS U2490 ( .A(n1259), .B(n1258), .Y(n2688) );
NAND2X1TS U2491 ( .A(n2678), .B(n2688), .Y(n1264) );
NAND2X1TS U2492 ( .A(n1651), .B(Add_Subt_result[45]), .Y(n1261) );
AOI22X1TS U2493 ( .A0(n2744), .A1(Add_Subt_result[9]), .B0(DmP[43]), .B1(
n2818), .Y(n1260) );
NAND2X2TS U2494 ( .A(n1261), .B(n1260), .Y(n2700) );
NAND2X1TS U2495 ( .A(n2653), .B(n2700), .Y(n1263) );
NAND2X1TS U2496 ( .A(n2680), .B(n2677), .Y(n1262) );
NAND2X1TS U2497 ( .A(n1651), .B(Add_Subt_result[46]), .Y(n1267) );
AOI22X1TS U2498 ( .A0(n2616), .A1(Add_Subt_result[8]), .B0(DmP[44]), .B1(
n2818), .Y(n1266) );
NAND2X2TS U2499 ( .A(n1267), .B(n1266), .Y(n2695) );
NAND2X1TS U2500 ( .A(n1651), .B(Add_Subt_result[50]), .Y(n1269) );
INVX2TS U2501 ( .A(n2573), .Y(n2616) );
AOI22X1TS U2502 ( .A0(n2744), .A1(Add_Subt_result[4]), .B0(DmP[48]), .B1(
n2818), .Y(n1268) );
NAND2X2TS U2503 ( .A(n1269), .B(n1268), .Y(n2673) );
AOI22X1TS U2504 ( .A0(n2703), .A1(n2695), .B0(n2701), .B1(n2673), .Y(n1270)
);
OAI221XLTS U2505 ( .A0(n2708), .A1(n2651), .B0(n1558), .B1(n2699), .C0(n1270), .Y(Barrel_Shifter_module_Mux_Array_Data_array[43]) );
NAND2X1TS U2506 ( .A(n1890), .B(n1284), .Y(n1274) );
NAND2X1TS U2507 ( .A(n2679), .B(n2702), .Y(n1273) );
NAND2X1TS U2508 ( .A(n1889), .B(n1271), .Y(n1272) );
NAND2X1TS U2509 ( .A(n2678), .B(n1275), .Y(n1279) );
NAND2X1TS U2510 ( .A(n2653), .B(n1329), .Y(n1278) );
NAND2X1TS U2511 ( .A(n1889), .B(n1276), .Y(n1277) );
AOI22X1TS U2512 ( .A0(n2703), .A1(n1325), .B0(n2701), .B1(n2696), .Y(n1280)
);
OAI221XLTS U2513 ( .A0(n2676), .A1(n2698), .B0(n1331), .B1(n1327), .C0(n1280), .Y(Barrel_Shifter_module_Mux_Array_Data_array[35]) );
NAND2X1TS U2514 ( .A(n2678), .B(n2696), .Y(n1283) );
NAND2X1TS U2515 ( .A(n2653), .B(n2677), .Y(n1282) );
NAND2X1TS U2516 ( .A(n2680), .B(n2702), .Y(n1281) );
AOI22X1TS U2517 ( .A0(n2703), .A1(n1284), .B0(n2701), .B1(n2688), .Y(n1285)
);
OAI221XLTS U2518 ( .A0(n2708), .A1(n2690), .B0(n1331), .B1(n1286), .C0(n1285), .Y(Barrel_Shifter_module_Mux_Array_Data_array[37]) );
INVX2TS U2519 ( .A(n1849), .Y(n2030) );
NOR2X2TS U2520 ( .A(n919), .B(LZA_output[4]), .Y(n1866) );
INVX2TS U2521 ( .A(n1866), .Y(n1735) );
INVX2TS U2522 ( .A(n1694), .Y(n1986) );
NAND2X2TS U2523 ( .A(n1986), .B(n2627), .Y(n1868) );
NOR2X1TS U2524 ( .A(n2979), .B(n1729), .Y(n1288) );
NOR2X1TS U2525 ( .A(n2950), .B(n1730), .Y(n1287) );
AOI22X1TS U2526 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[76]), .A1(
n1857), .B0(Barrel_Shifter_module_Mux_Array_Data_array[68]), .B1(n1027), .Y(n1292) );
NOR2X4TS U2527 ( .A(n2627), .B(n1729), .Y(n2123) );
AOI2BB2X1TS U2528 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[68]),
.B1(n1758), .A0N(n1289), .A1N(n894), .Y(n1291) );
NOR2X4TS U2529 ( .A(n2919), .B(n881), .Y(n2122) );
AOI22X1TS U2530 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[92]), .A1(
n2122), .B0(Barrel_Shifter_module_Mux_Array_Data_array[84]), .B1(n1035), .Y(n1290) );
AOI32X1TS U2531 ( .A0(n1292), .A1(n1291), .A2(n1290), .B0(n899), .B1(n1291),
.Y(n1689) );
OAI21X1TS U2532 ( .A0(n2030), .A1(n1735), .B0(n1293), .Y(n1690) );
NOR2X1TS U2533 ( .A(n2841), .B(add_overflow_flag), .Y(n1294) );
NOR2X1TS U2534 ( .A(n2982), .B(n882), .Y(n1296) );
NOR2X1TS U2535 ( .A(n2954), .B(n1730), .Y(n1295) );
NAND2X1TS U2536 ( .A(n2620), .B(FSM_selector_C), .Y(n1298) );
BUFX3TS U2537 ( .A(n1299), .Y(n2137) );
NOR2X1TS U2538 ( .A(n894), .B(exp_oper_result[4]), .Y(n1691) );
NAND2X1TS U2539 ( .A(n2049), .B(n1691), .Y(n2135) );
OA21X2TS U2540 ( .A0(n2088), .A1(n973), .B0(n2135), .Y(n1885) );
INVX2TS U2541 ( .A(n2088), .Y(n2133) );
NAND2X1TS U2542 ( .A(n2133), .B(n897), .Y(n1300) );
OAI31X4TS U2543 ( .A0(n899), .A1(n2137), .A2(LZA_output[4]), .B0(n1300), .Y(
n1879) );
NAND2X1TS U2544 ( .A(n891), .B(
Barrel_Shifter_module_Mux_Array_Data_array[96]), .Y(n1302) );
NAND2X1TS U2545 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[104]), .B(
LZA_output[3]), .Y(n1301) );
NAND2X2TS U2546 ( .A(n1302), .B(n1301), .Y(n2007) );
NAND2X1TS U2547 ( .A(n1879), .B(n2007), .Y(n1306) );
NAND2X1TS U2548 ( .A(n2141), .B(FSM_selector_B[1]), .Y(n2003) );
INVX2TS U2549 ( .A(n2003), .Y(n1882) );
NAND2X2TS U2550 ( .A(n1025), .B(n2133), .Y(n2081) );
NAND2X2TS U2551 ( .A(n2081), .B(n1304), .Y(n1881) );
AOI21X1TS U2552 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[96]), .A1(
n1882), .B0(n1881), .Y(n1305) );
INVX2TS U2553 ( .A(n1878), .Y(n2066) );
NOR2X1TS U2554 ( .A(n2978), .B(n882), .Y(n1309) );
NOR2X1TS U2555 ( .A(n2952), .B(exp_oper_result[3]), .Y(n1308) );
AOI22X1TS U2556 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[77]), .A1(
n1857), .B0(Barrel_Shifter_module_Mux_Array_Data_array[69]), .B1(n1027), .Y(n1313) );
AOI2BB2X1TS U2557 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[69]),
.B1(n1758), .A0N(n1310), .A1N(n894), .Y(n1312) );
AOI22X1TS U2558 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[93]), .A1(
n2122), .B0(Barrel_Shifter_module_Mux_Array_Data_array[85]), .B1(n1035), .Y(n1311) );
AOI32X1TS U2559 ( .A0(n1313), .A1(n1312), .A2(n1311), .B0(n899), .B1(n1312),
.Y(n1700) );
OAI21X1TS U2560 ( .A0(n2066), .A1(n1735), .B0(n1314), .Y(n1701) );
NOR2X1TS U2561 ( .A(n2977), .B(n882), .Y(n1316) );
NOR2X1TS U2562 ( .A(n2949), .B(n901), .Y(n1315) );
NOR2X2TS U2563 ( .A(n1316), .B(n1315), .Y(n2048) );
NAND2X1TS U2564 ( .A(n891), .B(
Barrel_Shifter_module_Mux_Array_Data_array[95]), .Y(n1318) );
NAND2X1TS U2565 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[103]), .B(
LZA_output[3]), .Y(n1317) );
NAND2X2TS U2566 ( .A(n1318), .B(n1317), .Y(n2050) );
NAND2X1TS U2567 ( .A(n1879), .B(n2050), .Y(n1320) );
AOI21X1TS U2568 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[95]), .A1(
n1882), .B0(n1881), .Y(n1319) );
AOI22X1TS U2569 ( .A0(n2616), .A1(Add_Subt_result[26]), .B0(n1891), .B1(
DmP[26]), .Y(n1322) );
AOI22X1TS U2570 ( .A0(n2870), .A1(n1917), .B0(n2868), .B1(n1916), .Y(n1323)
);
OAI221XLTS U2571 ( .A0(n2676), .A1(n1324), .B0(n1331), .B1(n1900), .C0(n1323), .Y(Barrel_Shifter_module_Mux_Array_Data_array[28]) );
BUFX3TS U2572 ( .A(n2648), .Y(n2781) );
AOI22X1TS U2573 ( .A0(n2781), .A1(n1325), .B0(n2779), .B1(n1917), .Y(n1326)
);
OAI221XLTS U2574 ( .A0(n1333), .A1(n1327), .B0(n1331), .B1(n1921), .C0(n1326), .Y(Barrel_Shifter_module_Mux_Array_Data_array[31]) );
AOI222X1TS U2575 ( .A0(n1328), .A1(n2678), .B0(n1916), .B1(n2680), .C0(n1902), .C1(n2679), .Y(n1926) );
AOI22X1TS U2576 ( .A0(n2854), .A1(n1923), .B0(n2701), .B1(n1329), .Y(n1330)
);
OAI221XLTS U2577 ( .A0(n1333), .A1(n1332), .B0(n1331), .B1(n1926), .C0(n1330), .Y(Barrel_Shifter_module_Mux_Array_Data_array[30]) );
NOR2X1TS U2578 ( .A(n1334), .B(n889), .Y(n2001) );
INVX2TS U2579 ( .A(n1035), .Y(n1337) );
AOI21X1TS U2580 ( .A0(n2122), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[94]), .B0(LZA_output[5]),
.Y(n1336) );
AOI22X1TS U2581 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[70]), .A1(
n1027), .B0(Barrel_Shifter_module_Mux_Array_Data_array[78]), .B1(n1857), .Y(n1335) );
AOI22X1TS U2582 ( .A0(n1986), .A1(n2002), .B0(n2001), .B1(n1988), .Y(n1340)
);
NAND2X2TS U2583 ( .A(n893), .B(exp_oper_result[4]), .Y(n2074) );
AOI22X1TS U2584 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[70]), .A1(
n1758), .B0(n886), .B1(n1988), .Y(n1338) );
AOI31X1TS U2585 ( .A0(n893), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .A2(n1860), .B0(n1339), .Y(n1991) );
OAI21X1TS U2586 ( .A0(n1340), .A1(n2957), .B0(n1991), .Y(n1996) );
NOR2X1TS U2587 ( .A(n2957), .B(n882), .Y(n1342) );
NOR2X1TS U2588 ( .A(n2956), .B(n1730), .Y(n1341) );
NOR2X2TS U2589 ( .A(n1342), .B(n1341), .Y(n2075) );
NAND2X1TS U2590 ( .A(n891), .B(
Barrel_Shifter_module_Mux_Array_Data_array[94]), .Y(n1344) );
NAND2X1TS U2591 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[102]), .B(
LZA_output[3]), .Y(n1343) );
NAND2X2TS U2592 ( .A(n1344), .B(n1343), .Y(n2085) );
AOI22X1TS U2593 ( .A0(n1879), .A1(n2085), .B0(n1882), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[94]), .Y(n1346) );
INVX2TS U2594 ( .A(n1881), .Y(n1345) );
AOI21X1TS U2595 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[95]), .A1(
n2143), .B0(n1349), .Y(n1352) );
NAND2X1TS U2596 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[79]), .B(
n1350), .Y(n1351) );
OAI211X1TS U2597 ( .A0(n2591), .A1(n908), .B0(n1352), .C0(n1351), .Y(n2116)
);
OAI21XLTS U2598 ( .A0(FS_Module_state_reg[1]), .A1(add_overflow_flag), .B0(
n2561), .Y(n1353) );
NAND3X2TS U2599 ( .A(n1354), .B(n922), .C(n2983), .Y(n860) );
NOR4X1TS U2600 ( .A(FS_Module_state_reg[0]), .B(n925), .C(n2983), .D(n922),
.Y(ready) );
NOR3X2TS U2601 ( .A(FS_Module_state_reg[3]), .B(n925), .C(n2983), .Y(
FSM_Add_Subt_Sgf_load) );
OR2X8TS U2602 ( .A(n2553), .B(n1980), .Y(n1984) );
NOR2BX1TS U2603 ( .AN(Sgf_normalized_result[1]), .B(n1973), .Y(n1355) );
XOR2X1TS U2604 ( .A(n1382), .B(n1355), .Y(n2539) );
NOR2X2TS U2605 ( .A(n2539), .B(n2538), .Y(n2547) );
XOR2X1TS U2606 ( .A(n1382), .B(n1356), .Y(n1362) );
NOR2X1TS U2607 ( .A(n1362), .B(n1361), .Y(n2541) );
NOR2X1TS U2608 ( .A(n2547), .B(n2541), .Y(n1364) );
NOR2BX1TS U2609 ( .AN(Sgf_normalized_result[0]), .B(n1973), .Y(n1357) );
XOR2X1TS U2610 ( .A(n1983), .B(n1357), .Y(n2548) );
INVX2TS U2611 ( .A(n2548), .Y(n1360) );
NOR2X1TS U2612 ( .A(n1983), .B(n1358), .Y(n2549) );
NAND2X1TS U2613 ( .A(n1983), .B(n1358), .Y(n1359) );
OAI21X1TS U2614 ( .A0(n1360), .A1(n2549), .B0(n1359), .Y(n2537) );
NAND2X1TS U2615 ( .A(n1362), .B(n1361), .Y(n2542) );
INVX2TS U2616 ( .A(n2542), .Y(n1363) );
AOI21X2TS U2617 ( .A0(n1364), .A1(n2537), .B0(n1363), .Y(n2513) );
NOR2BX1TS U2618 ( .AN(Sgf_normalized_result[3]), .B(n1980), .Y(n1365) );
XOR2X1TS U2619 ( .A(n1382), .B(n1365), .Y(n1370) );
NOR2X1TS U2620 ( .A(n1370), .B(n1369), .Y(n2526) );
NOR2BX1TS U2621 ( .AN(Sgf_normalized_result[4]), .B(n1980), .Y(n1366) );
XOR2X1TS U2622 ( .A(n1382), .B(n1366), .Y(n1372) );
NOR2X2TS U2623 ( .A(n1372), .B(n1371), .Y(n2528) );
NOR2BX1TS U2624 ( .AN(Sgf_normalized_result[5]), .B(n1964), .Y(n1367) );
XOR2X1TS U2625 ( .A(n1382), .B(n1367), .Y(n1374) );
NOR2X2TS U2626 ( .A(n1374), .B(n1373), .Y(n2521) );
NOR2BX1TS U2627 ( .AN(Sgf_normalized_result[6]), .B(n1933), .Y(n1368) );
XOR2X1TS U2628 ( .A(n1382), .B(n1368), .Y(n1376) );
NOR2X2TS U2629 ( .A(n1376), .B(n1375), .Y(n2516) );
NAND2X1TS U2630 ( .A(n1370), .B(n1369), .Y(n2533) );
NAND2X1TS U2631 ( .A(n1372), .B(n1371), .Y(n2529) );
OAI21X1TS U2632 ( .A0(n2528), .A1(n2533), .B0(n2529), .Y(n2514) );
NAND2X1TS U2633 ( .A(n1374), .B(n1373), .Y(n2522) );
NAND2X1TS U2634 ( .A(n1376), .B(n1375), .Y(n2517) );
AOI21X1TS U2635 ( .A0(n2514), .A1(n1378), .B0(n1377), .Y(n1379) );
NOR2BX1TS U2636 ( .AN(Sgf_normalized_result[7]), .B(n1461), .Y(n1381) );
XOR2X1TS U2637 ( .A(n1382), .B(n1381), .Y(n1387) );
NOR2X2TS U2638 ( .A(n1387), .B(n1386), .Y(n2508) );
NOR2BX1TS U2639 ( .AN(Sgf_normalized_result[8]), .B(n1461), .Y(n1383) );
XOR2X1TS U2640 ( .A(n1454), .B(n1383), .Y(n1389) );
NOR2X2TS U2641 ( .A(n1389), .B(n1388), .Y(n2503) );
NOR2BX1TS U2642 ( .AN(Sgf_normalized_result[9]), .B(n1461), .Y(n1384) );
XOR2X1TS U2643 ( .A(n1454), .B(n1384), .Y(n1391) );
NOR2BX1TS U2644 ( .AN(Sgf_normalized_result[10]), .B(n1461), .Y(n1385) );
XOR2X1TS U2645 ( .A(n1454), .B(n1385), .Y(n1393) );
NOR2X2TS U2646 ( .A(n1393), .B(n1392), .Y(n1412) );
NAND2X1TS U2647 ( .A(n1389), .B(n1388), .Y(n2504) );
OAI21X1TS U2648 ( .A0(n2503), .A1(n2509), .B0(n2504), .Y(n1407) );
NAND2X1TS U2649 ( .A(n1391), .B(n1390), .Y(n2499) );
NAND2X1TS U2650 ( .A(n1393), .B(n1392), .Y(n1413) );
OAI21X1TS U2651 ( .A0(n1412), .A1(n2499), .B0(n1413), .Y(n1394) );
OAI21X1TS U2652 ( .A0(n2512), .A1(n1439), .B0(n1447), .Y(n1417) );
NOR2BX1TS U2653 ( .AN(Sgf_normalized_result[11]), .B(n1980), .Y(n1396) );
XOR2X1TS U2654 ( .A(n1454), .B(n1396), .Y(n1398) );
INVX4TS U2655 ( .A(n2920), .Y(n1458) );
INVX2TS U2656 ( .A(n1420), .Y(n1418) );
NAND2X1TS U2657 ( .A(n1398), .B(n1397), .Y(n1422) );
INVX2TS U2658 ( .A(n1422), .Y(n1399) );
AOI21X1TS U2659 ( .A0(n1417), .A1(n1418), .B0(n1399), .Y(n1405) );
NOR2X2TS U2660 ( .A(n1402), .B(n1401), .Y(n1423) );
NAND2X1TS U2661 ( .A(n1402), .B(n1401), .Y(n1421) );
NAND2X1TS U2662 ( .A(n1403), .B(n1421), .Y(n1404) );
INVX2TS U2663 ( .A(n1406), .Y(n1409) );
INVX2TS U2664 ( .A(n1407), .Y(n1408) );
OAI21X1TS U2665 ( .A0(n2512), .A1(n1409), .B0(n1408), .Y(n2502) );
INVX2TS U2666 ( .A(n1410), .Y(n2500) );
INVX2TS U2667 ( .A(n2499), .Y(n1411) );
AOI21X1TS U2668 ( .A0(n2502), .A1(n2500), .B0(n1411), .Y(n1416) );
NAND2X1TS U2669 ( .A(n1414), .B(n1413), .Y(n1415) );
INVX2TS U2670 ( .A(n1417), .Y(n1426) );
NAND2X1TS U2671 ( .A(n1418), .B(n1422), .Y(n1419) );
INVX2TS U2672 ( .A(n1438), .Y(n1425) );
OAI21X1TS U2673 ( .A0(n1423), .A1(n1422), .B0(n1421), .Y(n1444) );
INVX2TS U2674 ( .A(n1444), .Y(n1424) );
OAI21X1TS U2675 ( .A0(n1426), .A1(n1425), .B0(n1424), .Y(n2498) );
NOR2BX1TS U2676 ( .AN(Sgf_normalized_result[13]), .B(n1461), .Y(n1427) );
XOR2X1TS U2677 ( .A(n1454), .B(n1427), .Y(n1429) );
INVX2TS U2678 ( .A(n1437), .Y(n2496) );
NAND2X1TS U2679 ( .A(n1429), .B(n1428), .Y(n2495) );
INVX2TS U2680 ( .A(n2495), .Y(n1430) );
AOI21X1TS U2681 ( .A0(n2498), .A1(n2496), .B0(n1430), .Y(n1436) );
NOR2BX1TS U2682 ( .AN(Sgf_normalized_result[14]), .B(n1461), .Y(n1431) );
XOR2X1TS U2683 ( .A(n1454), .B(n1431), .Y(n1433) );
NOR2X2TS U2684 ( .A(n1433), .B(n1432), .Y(n1441) );
INVX2TS U2685 ( .A(n1441), .Y(n1434) );
NAND2X1TS U2686 ( .A(n1433), .B(n1432), .Y(n1440) );
NAND2X1TS U2687 ( .A(n1434), .B(n1440), .Y(n1435) );
OAI21X1TS U2688 ( .A0(n1441), .A1(n2495), .B0(n1440), .Y(n1442) );
AOI21X1TS U2689 ( .A0(n1444), .A1(n1443), .B0(n1442), .Y(n1445) );
NOR2BX1TS U2690 ( .AN(Sgf_normalized_result[15]), .B(n1461), .Y(n1451) );
XOR2X1TS U2691 ( .A(n1454), .B(n1451), .Y(n1473) );
NOR2X1TS U2692 ( .A(n1473), .B(n1472), .Y(n2484) );
NOR2BX1TS U2693 ( .AN(Sgf_normalized_result[16]), .B(n1461), .Y(n1452) );
XOR2X1TS U2694 ( .A(n1454), .B(n1452), .Y(n1475) );
NOR2X2TS U2695 ( .A(n1475), .B(n1474), .Y(n2486) );
NOR2BX1TS U2696 ( .AN(Sgf_normalized_result[17]), .B(FSM_selector_D), .Y(
n1453) );
XOR2X1TS U2697 ( .A(n1454), .B(n1453), .Y(n1477) );
NOR2X2TS U2698 ( .A(n1477), .B(n1476), .Y(n2479) );
NOR2BX1TS U2699 ( .AN(Sgf_normalized_result[18]), .B(FSM_selector_D), .Y(
n1455) );
XOR2X1TS U2700 ( .A(n1467), .B(n1455), .Y(n1479) );
NOR2X2TS U2701 ( .A(n1479), .B(n1478), .Y(n2474) );
NOR2BX1TS U2702 ( .AN(Sgf_normalized_result[19]), .B(FSM_selector_D), .Y(
n1456) );
XOR2X1TS U2703 ( .A(n1467), .B(n1456), .Y(n1483) );
NOR2X2TS U2704 ( .A(n1483), .B(n1482), .Y(n2467) );
NOR2BX1TS U2705 ( .AN(Sgf_normalized_result[20]), .B(FSM_selector_D), .Y(
n1457) );
XOR2X1TS U2706 ( .A(n1467), .B(n1457), .Y(n1485) );
NOR2X2TS U2707 ( .A(n1485), .B(n1484), .Y(n2462) );
NOR2BX1TS U2708 ( .AN(Sgf_normalized_result[21]), .B(n1980), .Y(n1459) );
XOR2X1TS U2709 ( .A(n1467), .B(n1459), .Y(n1487) );
INVX4TS U2710 ( .A(n2920), .Y(n1471) );
NOR2X2TS U2711 ( .A(n1487), .B(n1486), .Y(n2456) );
NOR2BX1TS U2712 ( .AN(Sgf_normalized_result[22]), .B(FSM_selector_D), .Y(
n1460) );
XOR2X1TS U2713 ( .A(n1467), .B(n1460), .Y(n1489) );
NOR2X2TS U2714 ( .A(n1489), .B(n1488), .Y(n2451) );
NOR2X2TS U2715 ( .A(n2445), .B(n1493), .Y(n2394) );
NOR2BX1TS U2716 ( .AN(Sgf_normalized_result[23]), .B(n1461), .Y(n1462) );
XOR2X1TS U2717 ( .A(n1467), .B(n1462), .Y(n1495) );
NOR2X2TS U2718 ( .A(n1495), .B(n1494), .Y(n2440) );
NOR2BX1TS U2719 ( .AN(Sgf_normalized_result[24]), .B(FSM_selector_D), .Y(
n1463) );
XOR2X1TS U2720 ( .A(n1467), .B(n1463), .Y(n1497) );
NOR2X2TS U2721 ( .A(n1497), .B(n1496), .Y(n2435) );
NOR2BX1TS U2722 ( .AN(Sgf_normalized_result[25]), .B(FSM_selector_D), .Y(
n1464) );
XOR2X1TS U2723 ( .A(n1467), .B(n1464), .Y(n1499) );
NOR2X2TS U2724 ( .A(n1499), .B(n1498), .Y(n2429) );
NOR2BX1TS U2725 ( .AN(Sgf_normalized_result[26]), .B(FSM_selector_D), .Y(
n1465) );
XOR2X1TS U2726 ( .A(n1467), .B(n1465), .Y(n1501) );
NOR2X2TS U2727 ( .A(n1501), .B(n1500), .Y(n2424) );
NOR2BX1TS U2728 ( .AN(Sgf_normalized_result[27]), .B(n1931), .Y(n1466) );
XOR2X1TS U2729 ( .A(n1467), .B(n1466), .Y(n1505) );
NOR2X2TS U2730 ( .A(n1505), .B(n1504), .Y(n2417) );
NOR2BX1TS U2731 ( .AN(Sgf_normalized_result[28]), .B(n1931), .Y(n1468) );
XOR2X1TS U2732 ( .A(n1788), .B(n1468), .Y(n1507) );
NOR2X2TS U2733 ( .A(n1507), .B(n1506), .Y(n2412) );
NOR2BX1TS U2734 ( .AN(Sgf_normalized_result[29]), .B(n1931), .Y(n1469) );
XOR2X1TS U2735 ( .A(n1788), .B(n1469), .Y(n1509) );
NOR2X2TS U2736 ( .A(n1509), .B(n1508), .Y(n2406) );
NOR2BX1TS U2737 ( .AN(Sgf_normalized_result[30]), .B(n1931), .Y(n1470) );
XOR2X1TS U2738 ( .A(n1788), .B(n1470), .Y(n1511) );
NOR2X2TS U2739 ( .A(n1511), .B(n1510), .Y(n2401) );
NOR2X2TS U2740 ( .A(n2395), .B(n1515), .Y(n1517) );
NAND2X1TS U2741 ( .A(n1473), .B(n1472), .Y(n2491) );
NAND2X1TS U2742 ( .A(n1475), .B(n1474), .Y(n2487) );
OAI21X1TS U2743 ( .A0(n2486), .A1(n2491), .B0(n2487), .Y(n2472) );
NAND2X1TS U2744 ( .A(n1477), .B(n1476), .Y(n2480) );
NAND2X1TS U2745 ( .A(n1479), .B(n1478), .Y(n2475) );
OAI21X1TS U2746 ( .A0(n2474), .A1(n2480), .B0(n2475), .Y(n1480) );
AOI21X2TS U2747 ( .A0(n2472), .A1(n1481), .B0(n1480), .Y(n2446) );
NAND2X1TS U2748 ( .A(n1483), .B(n1482), .Y(n2468) );
NAND2X1TS U2749 ( .A(n1485), .B(n1484), .Y(n2463) );
OAI21X1TS U2750 ( .A0(n2462), .A1(n2468), .B0(n2463), .Y(n2449) );
NAND2X1TS U2751 ( .A(n1487), .B(n1486), .Y(n2457) );
NAND2X1TS U2752 ( .A(n1489), .B(n1488), .Y(n2452) );
AOI21X1TS U2753 ( .A0(n2449), .A1(n1491), .B0(n1490), .Y(n1492) );
NAND2X1TS U2754 ( .A(n1495), .B(n1494), .Y(n2441) );
NAND2X1TS U2755 ( .A(n1497), .B(n1496), .Y(n2436) );
OAI21X1TS U2756 ( .A0(n2435), .A1(n2441), .B0(n2436), .Y(n2422) );
NAND2X1TS U2757 ( .A(n1499), .B(n1498), .Y(n2430) );
NAND2X1TS U2758 ( .A(n1501), .B(n1500), .Y(n2425) );
AOI21X1TS U2759 ( .A0(n2422), .A1(n1503), .B0(n1502), .Y(n2396) );
NAND2X1TS U2760 ( .A(n1505), .B(n1504), .Y(n2418) );
NAND2X1TS U2761 ( .A(n1507), .B(n1506), .Y(n2413) );
OAI21X1TS U2762 ( .A0(n2412), .A1(n2418), .B0(n2413), .Y(n2399) );
NAND2X1TS U2763 ( .A(n1509), .B(n1508), .Y(n2407) );
NAND2X1TS U2764 ( .A(n1511), .B(n1510), .Y(n2402) );
OAI21X1TS U2765 ( .A0(n2401), .A1(n2407), .B0(n2402), .Y(n1512) );
AOI21X1TS U2766 ( .A0(n2399), .A1(n1513), .B0(n1512), .Y(n1514) );
OAI21X1TS U2767 ( .A0(n2396), .A1(n1515), .B0(n1514), .Y(n1516) );
AOI21X2TS U2768 ( .A0(n2393), .A1(n1517), .B0(n1516), .Y(n1518) );
OAI21X4TS U2769 ( .A0(n2392), .A1(n1519), .B0(n1518), .Y(n1950) );
NOR2BX1TS U2770 ( .AN(Sgf_normalized_result[31]), .B(n1931), .Y(n1520) );
XOR2X1TS U2771 ( .A(n1788), .B(n1520), .Y(n1525) );
NOR2X2TS U2772 ( .A(n1525), .B(n1524), .Y(n2387) );
NOR2BX1TS U2773 ( .AN(Sgf_normalized_result[32]), .B(n1931), .Y(n1521) );
XOR2X1TS U2774 ( .A(n1788), .B(n1521), .Y(n1527) );
NOR2X2TS U2775 ( .A(n1527), .B(n1526), .Y(n2382) );
NOR2BX1TS U2776 ( .AN(Sgf_normalized_result[33]), .B(n1931), .Y(n1522) );
XOR2X1TS U2777 ( .A(n1788), .B(n1522), .Y(n1529) );
NOR2BX1TS U2778 ( .AN(Sgf_normalized_result[34]), .B(FSM_selector_D), .Y(
n1523) );
XOR2X1TS U2779 ( .A(n1788), .B(n1523), .Y(n1531) );
NOR2X2TS U2780 ( .A(n1531), .B(n1530), .Y(n1551) );
NAND2X1TS U2781 ( .A(n1527), .B(n1526), .Y(n2383) );
OAI21X1TS U2782 ( .A0(n2382), .A1(n2388), .B0(n2383), .Y(n1546) );
NAND2X1TS U2783 ( .A(n1529), .B(n1528), .Y(n2378) );
NAND2X1TS U2784 ( .A(n1531), .B(n1530), .Y(n1552) );
OAI21X1TS U2785 ( .A0(n1551), .A1(n2378), .B0(n1552), .Y(n1532) );
AOI21X2TS U2786 ( .A0(n1546), .A1(n1533), .B0(n1532), .Y(n1780) );
NOR2BX1TS U2787 ( .AN(Sgf_normalized_result[35]), .B(n1931), .Y(n1534) );
INVX2TS U2788 ( .A(n1671), .Y(n1562) );
INVX2TS U2789 ( .A(n1673), .Y(n1538) );
AOI21X1TS U2790 ( .A0(n1561), .A1(n1562), .B0(n1538), .Y(n1544) );
NOR2BX1TS U2791 ( .AN(Sgf_normalized_result[36]), .B(n1931), .Y(n1539) );
XOR2X1TS U2792 ( .A(n1788), .B(n1539), .Y(n1541) );
NOR2X2TS U2793 ( .A(n1541), .B(n1540), .Y(n1674) );
INVX2TS U2794 ( .A(n1674), .Y(n1542) );
NAND2X1TS U2795 ( .A(n1541), .B(n1540), .Y(n1672) );
NAND2X1TS U2796 ( .A(n1542), .B(n1672), .Y(n1543) );
INVX2TS U2797 ( .A(n1545), .Y(n1548) );
INVX2TS U2798 ( .A(n1546), .Y(n1547) );
OAI21X1TS U2799 ( .A0(n2391), .A1(n1548), .B0(n1547), .Y(n2381) );
INVX2TS U2800 ( .A(n1549), .Y(n2379) );
INVX2TS U2801 ( .A(n2378), .Y(n1550) );
AOI21X1TS U2802 ( .A0(n2381), .A1(n2379), .B0(n1550), .Y(n1555) );
INVX2TS U2803 ( .A(n1551), .Y(n1553) );
NAND2X1TS U2804 ( .A(n1553), .B(n1552), .Y(n1554) );
BUFX3TS U2805 ( .A(n2743), .Y(n2863) );
NAND2X1TS U2806 ( .A(n1651), .B(Add_Subt_result[53]), .Y(n1557) );
AOI22X1TS U2807 ( .A0(n2744), .A1(Add_Subt_result[1]), .B0(DmP[51]), .B1(
n3023), .Y(n1556) );
NAND2X2TS U2808 ( .A(n1557), .B(n1556), .Y(n2657) );
BUFX3TS U2809 ( .A(n2757), .Y(n2839) );
OA22X2TS U2810 ( .A0(n2787), .A1(Add_Subt_result[54]), .B0(
Add_Subt_result[0]), .B1(n2152), .Y(n2649) );
AOI22X1TS U2811 ( .A0(n2863), .A1(n2657), .B0(n2839), .B1(n2649), .Y(n1560)
);
NOR2X2TS U2812 ( .A(n2726), .B(n2568), .Y(n1668) );
INVX2TS U2813 ( .A(n1668), .Y(n1559) );
NAND2X1TS U2814 ( .A(n1562), .B(n1673), .Y(n1563) );
INVX2TS U2815 ( .A(r_mode[1]), .Y(n1564) );
INVX2TS U2816 ( .A(r_mode[0]), .Y(n1565) );
INVX2TS U2817 ( .A(n2560), .Y(n1643) );
NOR2X1TS U2818 ( .A(n922), .B(FS_Module_state_reg[1]), .Y(n2551) );
NAND2X1TS U2819 ( .A(n2551), .B(n1568), .Y(n2559) );
NAND2BX1TS U2820 ( .AN(n2158), .B(FS_Module_state_reg[0]), .Y(n2883) );
NAND2X1TS U2821 ( .A(FS_Module_state_reg[1]), .B(n2561), .Y(n2619) );
OAI211X1TS U2822 ( .A0(n3023), .A1(n2883), .B0(n2884), .C0(n2619), .Y(n2558)
);
NOR4BX1TS U2823 ( .AN(n1569), .B(n2558), .C(FSM_Add_Subt_Sgf_load), .D(
FSM_Final_Result_load), .Y(n1642) );
OAI22X1TS U2824 ( .A0(n2933), .A1(intDY[1]), .B0(n887), .B1(intDY[62]), .Y(
n1570) );
AOI221X1TS U2825 ( .A0(n2933), .A1(intDY[1]), .B0(intDY[62]), .B1(n887),
.C0(n1570), .Y(n1571) );
AOI22X1TS U2826 ( .A0(n2892), .A1(intDY[5]), .B0(n2938), .B1(intDY[4]), .Y(
n1572) );
AOI22X1TS U2827 ( .A0(n2966), .A1(intDY[3]), .B0(n2900), .B1(intDY[2]), .Y(
n1573) );
OAI221XLTS U2828 ( .A0(n2966), .A1(intDY[3]), .B0(n2900), .B1(intDY[2]),
.C0(n1573), .Y(n1582) );
OAI22X1TS U2829 ( .A0(n2959), .A1(intDY[8]), .B0(n2896), .B1(intDY[9]), .Y(
n1574) );
AOI221X1TS U2830 ( .A0(n2959), .A1(intDY[8]), .B0(intDY[9]), .B1(n2896),
.C0(n1574), .Y(n1580) );
OAI22X1TS U2831 ( .A0(n2932), .A1(intDY[6]), .B0(n2891), .B1(intDY[7]), .Y(
n1575) );
AOI221X1TS U2832 ( .A0(n2932), .A1(intDY[6]), .B0(intDY[7]), .B1(n2891),
.C0(n1575), .Y(n1579) );
OAI22X1TS U2833 ( .A0(n2936), .A1(intDY[12]), .B0(n2935), .B1(intDY[13]),
.Y(n1576) );
AOI221X1TS U2834 ( .A0(n2936), .A1(intDY[12]), .B0(intDY[13]), .B1(n2935),
.C0(n1576), .Y(n1578) );
OAI22X1TS U2835 ( .A0(n2887), .A1(intDY[10]), .B0(n2923), .B1(intDY[11]),
.Y(n2191) );
AOI221X1TS U2836 ( .A0(n2887), .A1(intDY[10]), .B0(intDY[11]), .B1(n2923),
.C0(n2191), .Y(n1577) );
NOR4X1TS U2837 ( .A(n1584), .B(n1582), .C(n1583), .D(n1581), .Y(n1640) );
AOI22X1TS U2838 ( .A0(n2965), .A1(intDY[26]), .B0(n2969), .B1(intDY[25]),
.Y(n1585) );
AOI22X1TS U2839 ( .A0(n2898), .A1(intDY[24]), .B0(n2902), .B1(intDY[22]),
.Y(n1586) );
OAI221XLTS U2840 ( .A0(n2898), .A1(intDY[24]), .B0(n2902), .B1(intDY[22]),
.C0(n1586), .Y(n1591) );
AOI22X1TS U2841 ( .A0(n2899), .A1(intDY[30]), .B0(n2941), .B1(intDY[29]),
.Y(n1587) );
AOI22X1TS U2842 ( .A0(n2940), .A1(intDY[28]), .B0(n2903), .B1(intDY[27]),
.Y(n1588) );
OAI221XLTS U2843 ( .A0(n2940), .A1(intDY[28]), .B0(n2903), .B1(intDY[27]),
.C0(n1588), .Y(n1589) );
NOR4X1TS U2844 ( .A(n1592), .B(n1591), .C(n1590), .D(n1589), .Y(n1639) );
AOI22X1TS U2845 ( .A0(n2964), .A1(intDY[17]), .B0(n2937), .B1(intDY[16]),
.Y(n1593) );
AOI22X1TS U2846 ( .A0(n2967), .A1(intDY[15]), .B0(n2901), .B1(intDY[14]),
.Y(n1594) );
OAI221XLTS U2847 ( .A0(n2967), .A1(intDY[15]), .B0(n2901), .B1(intDY[14]),
.C0(n1594), .Y(n1599) );
AOI22X1TS U2848 ( .A0(n2939), .A1(intDY[21]), .B0(n2942), .B1(intDY[20]),
.Y(n1595) );
AOI22X1TS U2849 ( .A0(n2904), .A1(intDY[19]), .B0(n2968), .B1(intDY[18]),
.Y(n1596) );
OAI221XLTS U2850 ( .A0(n2904), .A1(intDY[19]), .B0(n2968), .B1(intDY[18]),
.C0(n1596), .Y(n1597) );
NOR4X1TS U2851 ( .A(n1600), .B(n1599), .C(n1598), .D(n1597), .Y(n1638) );
OAI22X1TS U2852 ( .A0(n2928), .A1(intDY[41]), .B0(n2905), .B1(intDY[42]),
.Y(n1601) );
AOI221X1TS U2853 ( .A0(n2928), .A1(intDY[41]), .B0(intDY[42]), .B1(n2905),
.C0(n1601), .Y(n1608) );
OAI22X1TS U2854 ( .A0(n2897), .A1(intDY[39]), .B0(n2885), .B1(intDY[40]),
.Y(n1602) );
AOI221X1TS U2855 ( .A0(n2897), .A1(intDY[39]), .B0(intDY[40]), .B1(n2885),
.C0(n1602), .Y(n1607) );
OAI22X1TS U2856 ( .A0(n2945), .A1(intDY[45]), .B0(n2926), .B1(intDY[46]),
.Y(n1603) );
AOI221X1TS U2857 ( .A0(n2945), .A1(intDY[45]), .B0(intDY[46]), .B1(n2926),
.C0(n1603), .Y(n1606) );
OAI22X1TS U2858 ( .A0(n2944), .A1(intDY[43]), .B0(n2925), .B1(intDY[44]),
.Y(n1604) );
AOI221X1TS U2859 ( .A0(n2944), .A1(intDY[43]), .B0(intDY[44]), .B1(n2925),
.C0(n1604), .Y(n1605) );
OAI22X1TS U2860 ( .A0(n2962), .A1(intDY[33]), .B0(n2895), .B1(intDY[34]),
.Y(n1609) );
AOI221X1TS U2861 ( .A0(n2962), .A1(intDY[33]), .B0(intDY[34]), .B1(n2895),
.C0(n1609), .Y(n1616) );
OAI22X1TS U2862 ( .A0(n2961), .A1(intDY[31]), .B0(n2894), .B1(intDY[32]),
.Y(n1610) );
AOI221X1TS U2863 ( .A0(n2961), .A1(intDY[31]), .B0(intDY[32]), .B1(n2894),
.C0(n1610), .Y(n1615) );
OAI22X1TS U2864 ( .A0(n2934), .A1(intDY[37]), .B0(n2893), .B1(intDY[38]),
.Y(n1611) );
AOI221X1TS U2865 ( .A0(n2934), .A1(intDY[37]), .B0(intDY[38]), .B1(n2893),
.C0(n1611), .Y(n1614) );
OAI22X1TS U2866 ( .A0(n2963), .A1(intDY[35]), .B0(n2960), .B1(intDY[36]),
.Y(n1612) );
AOI221X1TS U2867 ( .A0(n2963), .A1(intDY[35]), .B0(intDY[36]), .B1(n2960),
.C0(n1612), .Y(n1613) );
OAI22X1TS U2868 ( .A0(n3058), .A1(intDY[57]), .B0(n3112), .B1(intDY[58]),
.Y(n1617) );
AOI221X1TS U2869 ( .A0(n3058), .A1(intDY[57]), .B0(intDY[58]), .B1(n3112),
.C0(n1617), .Y(n1624) );
OAI22X1TS U2870 ( .A0(n3111), .A1(intDY[55]), .B0(n2889), .B1(intDY[56]),
.Y(n1618) );
AOI221X1TS U2871 ( .A0(n3111), .A1(intDY[55]), .B0(intDY[56]), .B1(n2889),
.C0(n1618), .Y(n1623) );
OAI22X1TS U2872 ( .A0(n2930), .A1(intDX[23]), .B0(n888), .B1(intDY[61]), .Y(
n1619) );
AOI221X1TS U2873 ( .A0(n2930), .A1(intDX[23]), .B0(intDY[61]), .B1(n888),
.C0(n1619), .Y(n1622) );
OAI22X1TS U2874 ( .A0(n2908), .A1(intDY[59]), .B0(n2947), .B1(intDY[60]),
.Y(n1620) );
AOI221X1TS U2875 ( .A0(n2908), .A1(intDY[59]), .B0(intDY[60]), .B1(n2947),
.C0(n1620), .Y(n1621) );
OAI22X1TS U2876 ( .A0(n2946), .A1(intDY[49]), .B0(n2943), .B1(intDY[50]),
.Y(n1625) );
AOI221X1TS U2877 ( .A0(n2946), .A1(intDY[49]), .B0(intDY[50]), .B1(n2943),
.C0(n1625), .Y(n1632) );
OAI22X1TS U2878 ( .A0(n2888), .A1(intDY[47]), .B0(n2927), .B1(intDY[48]),
.Y(n1626) );
AOI221X1TS U2879 ( .A0(n2888), .A1(intDY[47]), .B0(intDY[48]), .B1(n2927),
.C0(n1626), .Y(n1631) );
OAI22X1TS U2880 ( .A0(n2948), .A1(intDY[53]), .B0(n2890), .B1(intDY[54]),
.Y(n1627) );
AOI221X1TS U2881 ( .A0(n2948), .A1(intDY[53]), .B0(intDY[54]), .B1(n2890),
.C0(n1627), .Y(n1630) );
OAI22X1TS U2882 ( .A0(n2909), .A1(intDY[51]), .B0(n2929), .B1(intDY[52]),
.Y(n1628) );
AOI221X1TS U2883 ( .A0(n2909), .A1(intDY[51]), .B0(intDY[52]), .B1(n2929),
.C0(n1628), .Y(n1629) );
NOR4X1TS U2884 ( .A(n1636), .B(n1635), .C(n1634), .D(n1633), .Y(n1637) );
NAND4X1TS U2885 ( .A(n1640), .B(n1639), .C(n1638), .D(n1637), .Y(n2554) );
NAND2X1TS U2886 ( .A(n1890), .B(n2657), .Y(n1649) );
NAND2X1TS U2887 ( .A(n1651), .B(Add_Subt_result[52]), .Y(n1645) );
AOI22X1TS U2888 ( .A0(n2744), .A1(Add_Subt_result[2]), .B0(DmP[50]), .B1(
n3023), .Y(n1644) );
NAND2X2TS U2889 ( .A(n1645), .B(n1644), .Y(n2663) );
NAND2X1TS U2890 ( .A(n1889), .B(n2663), .Y(n1648) );
NAND2X1TS U2891 ( .A(n2669), .B(n1646), .Y(n1647) );
BUFX3TS U2892 ( .A(n2868), .Y(n2851) );
AOI21X1TS U2893 ( .A0(n2851), .A1(n2649), .B0(n1668), .Y(n1650) );
NAND2X1TS U2894 ( .A(n2678), .B(n2663), .Y(n1656) );
NAND2X1TS U2895 ( .A(n2653), .B(n2657), .Y(n1655) );
NAND2X1TS U2896 ( .A(n1651), .B(Add_Subt_result[51]), .Y(n1653) );
AOI22X1TS U2897 ( .A0(n1909), .A1(Add_Subt_result[3]), .B0(DmP[49]), .B1(
n3023), .Y(n1652) );
NAND2X1TS U2898 ( .A(n1653), .B(n1652), .Y(n2641) );
NAND2X1TS U2899 ( .A(n1889), .B(n2641), .Y(n1654) );
AND3X2TS U2900 ( .A(n1656), .B(n1655), .C(n1654), .Y(n2652) );
BUFX3TS U2901 ( .A(n2779), .Y(n2833) );
AOI21X1TS U2902 ( .A0(n2833), .A1(n2649), .B0(n1668), .Y(n1657) );
NAND2X1TS U2903 ( .A(n2666), .B(n2673), .Y(n1660) );
NAND2X1TS U2904 ( .A(n2679), .B(n2641), .Y(n1659) );
NAND2X1TS U2905 ( .A(n2680), .B(n2684), .Y(n1658) );
AOI22X1TS U2906 ( .A0(n913), .A1(n2657), .B0(n1668), .B1(n1922), .Y(n1663)
);
AOI22X1TS U2907 ( .A0(n909), .A1(n2649), .B0(n2833), .B1(n2663), .Y(n1662)
);
NAND2X1TS U2908 ( .A(n2666), .B(n2641), .Y(n1666) );
NAND2X1TS U2909 ( .A(n2679), .B(n2663), .Y(n1665) );
NAND2X1TS U2910 ( .A(n2680), .B(n2673), .Y(n1664) );
AOI22X1TS U2911 ( .A0(n2703), .A1(n2657), .B0(n1668), .B1(n1667), .Y(n1670)
);
NAND2X1TS U2912 ( .A(n912), .B(n2649), .Y(n1669) );
INVX2TS U2913 ( .A(n1771), .Y(n1676) );
INVX2TS U2914 ( .A(n1777), .Y(n1675) );
OAI21X2TS U2915 ( .A0(n1677), .A1(n1676), .B0(n1675), .Y(n2377) );
NOR2BX1TS U2916 ( .AN(Sgf_normalized_result[37]), .B(n1955), .Y(n1678) );
XOR2X1TS U2917 ( .A(n1952), .B(n1678), .Y(n1680) );
INVX2TS U2918 ( .A(n1770), .Y(n2375) );
NAND2X1TS U2919 ( .A(n1680), .B(n1679), .Y(n2374) );
INVX2TS U2920 ( .A(n2374), .Y(n1681) );
AOI21X1TS U2921 ( .A0(n2377), .A1(n2375), .B0(n1681), .Y(n1687) );
NOR2BX1TS U2922 ( .AN(Sgf_normalized_result[38]), .B(n1955), .Y(n1682) );
XOR2X1TS U2923 ( .A(n1952), .B(n1682), .Y(n1684) );
NOR2X2TS U2924 ( .A(n1684), .B(n1683), .Y(n1774) );
INVX2TS U2925 ( .A(n1774), .Y(n1685) );
NAND2X1TS U2926 ( .A(n1684), .B(n1683), .Y(n1773) );
NAND2X1TS U2927 ( .A(n1685), .B(n1773), .Y(n1686) );
INVX2TS U2928 ( .A(n919), .Y(n1869) );
AOI21X1TS U2929 ( .A0(n1869), .A1(n1849), .B0(n1689), .Y(n1699) );
NAND2X1TS U2930 ( .A(n1690), .B(n2049), .Y(n1698) );
NOR3X4TS U2931 ( .A(n899), .B(LZA_output[4]), .C(n2141), .Y(n1992) );
NAND2X2TS U2932 ( .A(n1691), .B(n906), .Y(n2087) );
NAND2X2TS U2933 ( .A(n2133), .B(n1986), .Y(n1764) );
OAI22X1TS U2934 ( .A0(n2132), .A1(n2922), .B0(n1694), .B1(n2627), .Y(n1695)
);
AND2X2TS U2935 ( .A(n1695), .B(n2133), .Y(n1872) );
AOI211X1TS U2936 ( .A0(n1992), .A1(n2007), .B0(n1696), .C0(n1872), .Y(n1697)
);
AOI21X1TS U2937 ( .A0(n1869), .A1(n1878), .B0(n1700), .Y(n1706) );
NAND2X1TS U2938 ( .A(n1701), .B(n2049), .Y(n1705) );
AOI211X1TS U2939 ( .A0(n1992), .A1(n2050), .B0(n1703), .C0(n1872), .Y(n1704)
);
AOI22X1TS U2940 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[75]), .A1(
n1857), .B0(Barrel_Shifter_module_Mux_Array_Data_array[67]), .B1(n1027), .Y(n1710) );
AOI2BB2X1TS U2941 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[67]),
.B1(n1758), .A0N(n1707), .A1N(n894), .Y(n1709) );
AOI22X1TS U2942 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[91]), .A1(
n2122), .B0(Barrel_Shifter_module_Mux_Array_Data_array[83]), .B1(n1035), .Y(n1708) );
AOI32X1TS U2943 ( .A0(n1710), .A1(n1709), .A2(n1708), .B0(n899), .B1(n1709),
.Y(n1713) );
AOI21X1TS U2944 ( .A0(n1869), .A1(n1853), .B0(n1713), .Y(n1723) );
INVX2TS U2945 ( .A(n1853), .Y(n2039) );
NOR2X1TS U2946 ( .A(n2980), .B(n1729), .Y(n1712) );
NOR2X1TS U2947 ( .A(n2951), .B(exp_oper_result[3]), .Y(n1711) );
OAI21X1TS U2948 ( .A0(n2039), .A1(n1735), .B0(n1714), .Y(n1836) );
NAND2X1TS U2949 ( .A(n1836), .B(n918), .Y(n1722) );
NAND2X1TS U2950 ( .A(n891), .B(
Barrel_Shifter_module_Mux_Array_Data_array[97]), .Y(n1716) );
NAND2X1TS U2951 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[105]), .B(
LZA_output[3]), .Y(n1715) );
NAND2X2TS U2952 ( .A(n1716), .B(n1715), .Y(n2018) );
NOR2X1TS U2953 ( .A(n2981), .B(n1729), .Y(n1718) );
NOR2X1TS U2954 ( .A(n2953), .B(n901), .Y(n1717) );
AOI211X1TS U2955 ( .A0(n1992), .A1(n2018), .B0(n1720), .C0(n1872), .Y(n1721)
);
CLKMX2X2TS U2956 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[98]), .B(
Barrel_Shifter_module_Mux_Array_Data_array[106]), .S0(LZA_output[3]),
.Y(n1839) );
AOI22X1TS U2957 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[74]), .A1(
n1857), .B0(Barrel_Shifter_module_Mux_Array_Data_array[66]), .B1(n1027), .Y(n1728) );
AOI222X1TS U2958 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[82]), .A1(
n1861), .B0(Barrel_Shifter_module_Mux_Array_Data_array[74]), .B1(n1860), .C0(Barrel_Shifter_module_Mux_Array_Data_array[90]), .C1(n2123), .Y(n1725)
);
AOI2BB2X1TS U2959 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[66]),
.B1(n1758), .A0N(n1725), .A1N(n1034), .Y(n1727) );
AOI22X1TS U2960 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[82]), .A1(
n1035), .B0(Barrel_Shifter_module_Mux_Array_Data_array[90]), .B1(n2122), .Y(n1726) );
AOI32X1TS U2961 ( .A0(n1728), .A1(n1727), .A2(n1726), .B0(n899), .B1(n1727),
.Y(n1733) );
AOI21X1TS U2962 ( .A0(n1869), .A1(n1839), .B0(n1733), .Y(n1741) );
INVX2TS U2963 ( .A(n1839), .Y(n1736) );
NOR2X1TS U2964 ( .A(n2976), .B(n1729), .Y(n1732) );
NOR2X1TS U2965 ( .A(n2955), .B(n901), .Y(n1731) );
NOR2X2TS U2966 ( .A(n1732), .B(n1731), .Y(n1843) );
OAI21X1TS U2967 ( .A0(n1736), .A1(n1735), .B0(n1734), .Y(n1840) );
NAND2X1TS U2968 ( .A(n1840), .B(n918), .Y(n1740) );
AOI21X1TS U2969 ( .A0(n1764), .A1(n2087), .B0(n1843), .Y(n1737) );
NOR3X1TS U2970 ( .A(n1738), .B(n1872), .C(n1737), .Y(n1739) );
INVX2TS U2971 ( .A(n2081), .Y(n1743) );
OAI22X1TS U2972 ( .A0(n2074), .A1(n1843), .B0(n3021), .B1(n2144), .Y(n1742)
);
AOI211X1TS U2973 ( .A0(n2077), .A1(n1839), .B0(n1743), .C0(n1742), .Y(n1744)
);
AOI22X1TS U2974 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[73]), .A1(
n1857), .B0(Barrel_Shifter_module_Mux_Array_Data_array[65]), .B1(n1027), .Y(n1749) );
AOI2BB2X1TS U2975 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[65]),
.B1(n1758), .A0N(n1746), .A1N(n1034), .Y(n1748) );
AOI22X1TS U2976 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[81]), .A1(
n1035), .B0(Barrel_Shifter_module_Mux_Array_Data_array[89]), .B1(n2122), .Y(n1747) );
AOI32X1TS U2977 ( .A0(n1749), .A1(n1748), .A2(n1747), .B0(n899), .B1(n1748),
.Y(n1750) );
AOI21X1TS U2978 ( .A0(n1869), .A1(n2018), .B0(n1750), .Y(n1756) );
AOI21X1TS U2979 ( .A0(n1866), .A1(n2018), .B0(n1750), .Y(n1751) );
OAI21X1TS U2980 ( .A0(n2017), .A1(n1868), .B0(n1751), .Y(n1854) );
NAND2X1TS U2981 ( .A(n1854), .B(n918), .Y(n1755) );
AOI211X1TS U2982 ( .A0(n1992), .A1(n1853), .B0(n1753), .C0(n1872), .Y(n1754)
);
AOI22X1TS U2983 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[72]), .A1(
n1857), .B0(Barrel_Shifter_module_Mux_Array_Data_array[64]), .B1(n1027), .Y(n1761) );
AOI2BB2X1TS U2984 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[64]),
.B1(n1758), .A0N(n1757), .A1N(n894), .Y(n1760) );
AOI22X1TS U2985 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[80]), .A1(
n1035), .B0(Barrel_Shifter_module_Mux_Array_Data_array[88]), .B1(n2122), .Y(n1759) );
AOI32X1TS U2986 ( .A0(n1761), .A1(n1760), .A2(n1759), .B0(n899), .B1(n1760),
.Y(n1762) );
AOI21X1TS U2987 ( .A0(n1869), .A1(n2007), .B0(n1762), .Y(n1769) );
AOI21X1TS U2988 ( .A0(n1866), .A1(n2007), .B0(n1762), .Y(n1763) );
OAI21X1TS U2989 ( .A0(n2005), .A1(n1868), .B0(n1763), .Y(n1850) );
NAND2X1TS U2990 ( .A(n1850), .B(n918), .Y(n1768) );
AOI211X1TS U2991 ( .A0(n1992), .A1(n1849), .B0(n1766), .C0(n1872), .Y(n1767)
);
NOR2X2TS U2992 ( .A(n1772), .B(n1779), .Y(n1930) );
INVX2TS U2993 ( .A(n1930), .Y(n1782) );
OAI21X1TS U2994 ( .A0(n1774), .A1(n2374), .B0(n1773), .Y(n1775) );
AOI21X1TS U2995 ( .A0(n1777), .A1(n1776), .B0(n1775), .Y(n1778) );
OAI21X2TS U2996 ( .A0(n1780), .A1(n1779), .B0(n1778), .Y(n1945) );
INVX2TS U2997 ( .A(n1945), .Y(n1781) );
NOR2BX1TS U2998 ( .AN(Sgf_normalized_result[39]), .B(n1955), .Y(n1783) );
NOR2X1TS U2999 ( .A(n1790), .B(n1789), .Y(n2362) );
NOR2BX1TS U3000 ( .AN(Sgf_normalized_result[40]), .B(n1955), .Y(n1784) );
XOR2X1TS U3001 ( .A(n1952), .B(n1784), .Y(n1792) );
NOR2X2TS U3002 ( .A(n1792), .B(n1791), .Y(n2365) );
NOR2BX1TS U3003 ( .AN(Sgf_normalized_result[41]), .B(n1955), .Y(n1785) );
XOR2X1TS U3004 ( .A(n1952), .B(n1785), .Y(n1794) );
NOR2X1TS U3005 ( .A(n1794), .B(n1793), .Y(n1813) );
NOR2BX1TS U3006 ( .AN(Sgf_normalized_result[42]), .B(n1955), .Y(n1787) );
XOR2X1TS U3007 ( .A(n1788), .B(n1787), .Y(n1796) );
NOR2X2TS U3008 ( .A(n1796), .B(n1795), .Y(n1815) );
NAND2X1TS U3009 ( .A(n1790), .B(n1789), .Y(n2370) );
NAND2X1TS U3010 ( .A(n1792), .B(n1791), .Y(n2366) );
OAI21X1TS U3011 ( .A0(n2365), .A1(n2370), .B0(n2366), .Y(n1810) );
NAND2X1TS U3012 ( .A(n1794), .B(n1793), .Y(n2358) );
NAND2X1TS U3013 ( .A(n1796), .B(n1795), .Y(n1816) );
OAI21X1TS U3014 ( .A0(n1815), .A1(n2358), .B0(n1816), .Y(n1797) );
OAI21X2TS U3015 ( .A0(n2373), .A1(n1929), .B0(n1942), .Y(n1833) );
NOR2BX1TS U3016 ( .AN(Sgf_normalized_result[43]), .B(n1955), .Y(n1799) );
XOR2X1TS U3017 ( .A(n1952), .B(n1799), .Y(n1801) );
INVX2TS U3018 ( .A(n1927), .Y(n1834) );
NAND2X1TS U3019 ( .A(n1801), .B(n1800), .Y(n1935) );
INVX2TS U3020 ( .A(n1935), .Y(n1802) );
AOI21X1TS U3021 ( .A0(n1833), .A1(n1834), .B0(n1802), .Y(n1808) );
NOR2BX1TS U3022 ( .AN(Sgf_normalized_result[44]), .B(n1955), .Y(n1803) );
XOR2X1TS U3023 ( .A(n1952), .B(n1803), .Y(n1805) );
NOR2X2TS U3024 ( .A(n1805), .B(n1804), .Y(n1936) );
INVX2TS U3025 ( .A(n1936), .Y(n1806) );
NAND2X1TS U3026 ( .A(n1805), .B(n1804), .Y(n1934) );
NAND2X1TS U3027 ( .A(n1806), .B(n1934), .Y(n1807) );
INVX2TS U3028 ( .A(n1809), .Y(n1812) );
INVX2TS U3029 ( .A(n1810), .Y(n1811) );
INVX2TS U3030 ( .A(n1813), .Y(n2359) );
INVX2TS U3031 ( .A(n2358), .Y(n1814) );
AOI21X1TS U3032 ( .A0(n2361), .A1(n2359), .B0(n1814), .Y(n1819) );
INVX2TS U3033 ( .A(n1815), .Y(n1817) );
NAND2X1TS U3034 ( .A(n1817), .B(n1816), .Y(n1818) );
AOI22X1TS U3035 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[70]), .A1(
n1857), .B0(n1027), .B1(Barrel_Shifter_module_Mux_Array_Data_array[62]), .Y(n1821) );
AOI22X1TS U3036 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[86]), .A1(
n2122), .B0(n1035), .B1(Barrel_Shifter_module_Mux_Array_Data_array[78]), .Y(n1820) );
AOI21X1TS U3037 ( .A0(n1821), .A1(n1820), .B0(n899), .Y(n1825) );
AOI22X1TS U3038 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[70]), .A1(
n1860), .B0(n2002), .B1(Barrel_Shifter_module_Mux_Array_Data_array[62]), .Y(n1823) );
AOI22X1TS U3039 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[86]), .A1(
n2123), .B0(Barrel_Shifter_module_Mux_Array_Data_array[78]), .B1(n1861), .Y(n1822) );
AOI21X1TS U3040 ( .A0(n1823), .A1(n1822), .B0(n1034), .Y(n1824) );
AOI211X1TS U3041 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[62]), .A1(
FSM_selector_B[1]), .B0(n1825), .C0(n1824), .Y(n1829) );
INVX2TS U3042 ( .A(n1868), .Y(n1826) );
INVX2TS U3043 ( .A(n2075), .Y(n2083) );
AOI22X1TS U3044 ( .A0(n1826), .A1(n2083), .B0(n1866), .B1(n2085), .Y(n1827)
);
INVX2TS U3045 ( .A(n1844), .Y(n1831) );
AOI22X1TS U3046 ( .A0(n1869), .A1(n2085), .B0(n2083), .B1(n1986), .Y(n1828)
);
AOI21X1TS U3047 ( .A0(n1829), .A1(n1828), .B0(n2088), .Y(n1830) );
AOI211X1TS U3048 ( .A0(n906), .A1(n1831), .B0(n1830), .C0(n1872), .Y(n1832)
);
INVX2TS U3049 ( .A(n1833), .Y(n2353) );
NAND2X1TS U3050 ( .A(n1834), .B(n1935), .Y(n1835) );
AOI22X1TS U3051 ( .A0(n2058), .A1(n1836), .B0(n1879), .B1(n2018), .Y(n1838)
);
AOI21X1TS U3052 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[97]), .A1(
n1882), .B0(n1881), .Y(n1837) );
AOI22X1TS U3053 ( .A0(n2058), .A1(n1840), .B0(n1879), .B1(n1839), .Y(n1842)
);
AOI21X1TS U3054 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[98]), .A1(
n1882), .B0(n1881), .Y(n1841) );
OAI22X1TS U3055 ( .A0(n1845), .A1(n2141), .B0(n2137), .B1(n1844), .Y(n1848)
);
AOI22X1TS U3056 ( .A0(n2058), .A1(n1850), .B0(n1879), .B1(n1849), .Y(n1852)
);
AOI21X1TS U3057 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[100]), .A1(
n1882), .B0(n1881), .Y(n1851) );
AOI22X1TS U3058 ( .A0(n906), .A1(n1854), .B0(n1879), .B1(n1853), .Y(n1856)
);
AOI21X1TS U3059 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[99]), .A1(
n1882), .B0(n1881), .Y(n1855) );
AOI22X1TS U3060 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[71]), .A1(
n1857), .B0(Barrel_Shifter_module_Mux_Array_Data_array[63]), .B1(n890),
.Y(n1859) );
AOI22X1TS U3061 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[79]), .A1(
n1035), .B0(Barrel_Shifter_module_Mux_Array_Data_array[87]), .B1(n2122), .Y(n1858) );
AOI21X1TS U3062 ( .A0(n1859), .A1(n1858), .B0(n898), .Y(n1865) );
AOI22X1TS U3063 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[71]), .A1(
n1860), .B0(Barrel_Shifter_module_Mux_Array_Data_array[63]), .B1(n2002), .Y(n1863) );
AOI22X1TS U3064 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[79]), .A1(
n1861), .B0(Barrel_Shifter_module_Mux_Array_Data_array[87]), .B1(n2123), .Y(n1862) );
AOI21X1TS U3065 ( .A0(n1863), .A1(n1862), .B0(n1034), .Y(n1864) );
NAND2X1TS U3066 ( .A(n1866), .B(n2050), .Y(n1867) );
OAI211X1TS U3067 ( .A0(n2048), .A1(n1868), .B0(n1871), .C0(n1867), .Y(n1880)
);
INVX2TS U3068 ( .A(n2048), .Y(n2051) );
AOI22X1TS U3069 ( .A0(n1869), .A1(n2050), .B0(n2051), .B1(n1986), .Y(n1870)
);
AOI21X1TS U3070 ( .A0(n1871), .A1(n1870), .B0(n920), .Y(n1876) );
INVX2TS U3071 ( .A(n1872), .Y(n1874) );
AOI22X1TS U3072 ( .A0(n1992), .A1(n1878), .B0(n907), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[101]), .Y(n1873) );
AOI211X1TS U3073 ( .A0(n1880), .A1(n2049), .B0(n1876), .C0(n1875), .Y(n1877)
);
INVX2TS U3074 ( .A(n1877), .Y(n3117) );
AOI22X1TS U3075 ( .A0(n2058), .A1(n1880), .B0(n1879), .B1(n1878), .Y(n1884)
);
AOI21X1TS U3076 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[101]), .A1(
n1882), .B0(n1881), .Y(n1883) );
BUFX3TS U3077 ( .A(n2736), .Y(n2764) );
AOI22X1TS U3078 ( .A0(n2859), .A1(Add_Subt_result[30]), .B0(n2764), .B1(
DmP[22]), .Y(n1886) );
OAI2BB1X2TS U3079 ( .A0N(Add_Subt_result[24]), .A1N(n1907), .B0(n1886), .Y(
n2738) );
AOI22X1TS U3080 ( .A0(n2744), .A1(Add_Subt_result[31]), .B0(n2764), .B1(
DmP[21]), .Y(n1887) );
OAI2BB1X2TS U3081 ( .A0N(Add_Subt_result[23]), .A1N(n1907), .B0(n1887), .Y(
n2746) );
AOI22X1TS U3082 ( .A0(n895), .A1(Add_Subt_result[29]), .B0(n1891), .B1(
DmP[23]), .Y(n1888) );
OAI2BB1X2TS U3083 ( .A0N(Add_Subt_result[25]), .A1N(n1907), .B0(n1888), .Y(
n2731) );
AOI222X1TS U3084 ( .A0(n2738), .A1(n2666), .B0(n2746), .B1(n2667), .C0(n2731), .C1(n2679), .Y(n1915) );
BUFX3TS U3085 ( .A(n2779), .Y(n2872) );
AOI22X1TS U3086 ( .A0(n1909), .A1(Add_Subt_result[28]), .B0(n1891), .B1(
DmP[24]), .Y(n1892) );
OAI2BB1X2TS U3087 ( .A0N(Add_Subt_result[26]), .A1N(n1907), .B0(n1892), .Y(
n2717) );
AOI22X1TS U3088 ( .A0(n2870), .A1(n2710), .B0(n2872), .B1(n2717), .Y(n1894)
);
NOR2X1TS U3089 ( .A(n1922), .B(n2719), .Y(n1918) );
AOI22X1TS U3090 ( .A0(n2781), .A1(n1916), .B0(n1918), .B1(n2711), .Y(n1893)
);
BUFX3TS U3091 ( .A(n2743), .Y(n2850) );
BUFX3TS U3092 ( .A(n2757), .Y(n2865) );
AOI22X1TS U3093 ( .A0(n2850), .A1(n2738), .B0(n2865), .B1(n2731), .Y(n1899)
);
NAND2X1TS U3094 ( .A(n2708), .B(n1922), .Y(n1901) );
AOI22X1TS U3095 ( .A0(n2850), .A1(n2731), .B0(n2865), .B1(n2717), .Y(n1904)
);
AOI22X1TS U3096 ( .A0(n896), .A1(Add_Subt_result[33]), .B0(n2764), .B1(
DmP[19]), .Y(n1906) );
OAI2BB1X2TS U3097 ( .A0N(Add_Subt_result[21]), .A1N(n1907), .B0(n1906), .Y(
n2759) );
AOI22X1TS U3098 ( .A0(n895), .A1(Add_Subt_result[34]), .B0(n2764), .B1(
DmP[18]), .Y(n1908) );
OAI2BB1X2TS U3099 ( .A0N(Add_Subt_result[20]), .A1N(n2806), .B0(n1908), .Y(
n2767) );
AOI22X1TS U3100 ( .A0(n2851), .A1(n2759), .B0(n2865), .B1(n2767), .Y(n1914)
);
AOI22X1TS U3101 ( .A0(n1265), .A1(Add_Subt_result[32]), .B0(n2764), .B1(
DmP[20]), .Y(n1910) );
OAI21X4TS U3102 ( .A0(n2787), .A1(n2975), .B0(n1910), .Y(n2752) );
AOI22X1TS U3103 ( .A0(n2616), .A1(Add_Subt_result[35]), .B0(DmP[17]), .B1(
n2736), .Y(n1911) );
OAI2BB1X2TS U3104 ( .A0N(Add_Subt_result[19]), .A1N(n2806), .B0(n1911), .Y(
n2773) );
BUFX3TS U3105 ( .A(n2648), .Y(n2874) );
AOI21X1TS U3106 ( .A0(n2779), .A1(n2752), .B0(n1912), .Y(n1913) );
AOI22X1TS U3107 ( .A0(n2851), .A1(n2710), .B0(n2779), .B1(n1916), .Y(n1920)
);
AOI22X1TS U3108 ( .A0(n2676), .A1(n1918), .B0(n2781), .B1(n1917), .Y(n1919)
);
AOI22X1TS U3109 ( .A0(n2851), .A1(n2709), .B0(n2872), .B1(n2710), .Y(n1925)
);
NOR2X1TS U3110 ( .A(n1922), .B(n2724), .Y(n2712) );
AOI22X1TS U3111 ( .A0(n2708), .A1(n2712), .B0(n2781), .B1(n1923), .Y(n1924)
);
NOR2BX1TS U3112 ( .AN(Sgf_normalized_result[45]), .B(n1955), .Y(n1928) );
XOR2X1TS U3113 ( .A(n1952), .B(n1928), .Y(n1938) );
NOR2X2TS U3114 ( .A(n1929), .B(n1941), .Y(n1944) );
NOR2BX1TS U3115 ( .AN(Sgf_normalized_result[46]), .B(n1931), .Y(n1932) );
XOR2X1TS U3116 ( .A(n1952), .B(n1932), .Y(n1947) );
NOR2X2TS U3117 ( .A(n1947), .B(n1946), .Y(n2344) );
NOR2X2TS U3118 ( .A(n2343), .B(n2344), .Y(n1949) );
OAI21X1TS U3119 ( .A0(n1936), .A1(n1935), .B0(n1934), .Y(n2350) );
NAND2X1TS U3120 ( .A(n1938), .B(n1937), .Y(n2354) );
INVX2TS U3121 ( .A(n2354), .Y(n1939) );
AOI21X1TS U3122 ( .A0(n2350), .A1(n2355), .B0(n1939), .Y(n1940) );
OAI21X1TS U3123 ( .A0(n1942), .A1(n1941), .B0(n1940), .Y(n1943) );
AOI21X2TS U3124 ( .A0(n1945), .A1(n1944), .B0(n1943), .Y(n2342) );
NAND2X1TS U3125 ( .A(n1947), .B(n1946), .Y(n2345) );
OAI21X2TS U3126 ( .A0(n2342), .A1(n2344), .B0(n2345), .Y(n1948) );
AOI21X4TS U3127 ( .A0(n1950), .A1(n1949), .B0(n1948), .Y(n2341) );
NOR2BX1TS U3128 ( .AN(Sgf_normalized_result[47]), .B(n1981), .Y(n1951) );
XOR2X1TS U3129 ( .A(n1952), .B(n1951), .Y(n1954) );
NOR2X1TS U3130 ( .A(n1954), .B(n1953), .Y(n2337) );
NAND2X1TS U3131 ( .A(n1954), .B(n1953), .Y(n2338) );
OAI21X4TS U3132 ( .A0(n2341), .A1(n2337), .B0(n2338), .Y(n2336) );
NOR2BX1TS U3133 ( .AN(Sgf_normalized_result[48]), .B(n1955), .Y(n1956) );
XOR2X1TS U3134 ( .A(n1983), .B(n1956), .Y(n1958) );
NAND2X1TS U3135 ( .A(n1958), .B(n1957), .Y(n2333) );
INVX2TS U3136 ( .A(n2333), .Y(n1959) );
AOI21X4TS U3137 ( .A0(n2336), .A1(n2334), .B0(n1959), .Y(n2332) );
NOR2BX1TS U3138 ( .AN(Sgf_normalized_result[49]), .B(n1981), .Y(n1960) );
XOR2X1TS U3139 ( .A(n1983), .B(n1960), .Y(n1962) );
NOR2X1TS U3140 ( .A(n1962), .B(n1961), .Y(n2328) );
NAND2X1TS U3141 ( .A(n1962), .B(n1961), .Y(n2329) );
OAI21X4TS U3142 ( .A0(n2332), .A1(n2328), .B0(n2329), .Y(n2327) );
NOR2BX1TS U3143 ( .AN(Sgf_normalized_result[50]), .B(n1981), .Y(n1963) );
XOR2X1TS U3144 ( .A(n1983), .B(n1963), .Y(n1966) );
NAND2X1TS U3145 ( .A(n1966), .B(n1965), .Y(n2324) );
INVX2TS U3146 ( .A(n2324), .Y(n1967) );
AOI21X4TS U3147 ( .A0(n2327), .A1(n2325), .B0(n1967), .Y(n2323) );
NOR2BX1TS U3148 ( .AN(Sgf_normalized_result[51]), .B(n1981), .Y(n1968) );
XOR2X1TS U3149 ( .A(n1983), .B(n1968), .Y(n1971) );
NOR2X1TS U3150 ( .A(n1971), .B(n1970), .Y(n2319) );
NAND2X1TS U3151 ( .A(n1971), .B(n1970), .Y(n2320) );
OAI21X4TS U3152 ( .A0(n2323), .A1(n2319), .B0(n2320), .Y(n2318) );
NOR2BX1TS U3153 ( .AN(Sgf_normalized_result[52]), .B(n1981), .Y(n1972) );
XOR2X1TS U3154 ( .A(n1983), .B(n1972), .Y(n1975) );
NAND2X1TS U3155 ( .A(n1975), .B(n1974), .Y(n2315) );
INVX2TS U3156 ( .A(n2315), .Y(n1976) );
AOI21X4TS U3157 ( .A0(n2318), .A1(n2316), .B0(n1976), .Y(n2314) );
NOR2BX1TS U3158 ( .AN(Sgf_normalized_result[53]), .B(n1981), .Y(n1977) );
XOR2X1TS U3159 ( .A(n1983), .B(n1977), .Y(n1979) );
NOR2X1TS U3160 ( .A(n1979), .B(n1978), .Y(n2310) );
NAND2X1TS U3161 ( .A(n1979), .B(n1978), .Y(n2311) );
NOR2BX1TS U3162 ( .AN(Sgf_normalized_result[54]), .B(n1981), .Y(n1982) );
XOR2X1TS U3163 ( .A(n1983), .B(n1982), .Y(n2305) );
AOI22X1TS U3164 ( .A0(n1992), .A1(n2085), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[94]), .B1(n1692), .Y(n1993)
);
AOI211X1TS U3165 ( .A0(n2049), .A1(n1996), .B0(n1995), .C0(n1994), .Y(n1997)
);
INVX2TS U3166 ( .A(n1997), .Y(n3131) );
AOI22X2TS U3167 ( .A0(n893), .A1(n2002), .B0(n886), .B1(n1027), .Y(n2044) );
OAI22X1TS U3168 ( .A0(n2027), .A1(n2074), .B0(n2044), .B1(n2971), .Y(n1998)
);
AOI21X1TS U3169 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[92]), .A1(
n2072), .B0(n1998), .Y(n2034) );
INVX2TS U3170 ( .A(n2044), .Y(n2071) );
AOI22X1TS U3171 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[80]), .A1(
n2071), .B0(Barrel_Shifter_module_Mux_Array_Data_array[88]), .B1(n2072), .Y(n2000) );
NAND2X1TS U3172 ( .A(n2077), .B(n2007), .Y(n1999) );
NAND2X1TS U3173 ( .A(n2025), .B(n918), .Y(n2013) );
AOI21X1TS U3174 ( .A0(n2002), .A1(n2129), .B0(n2001), .Y(n2004) );
OAI21X4TS U3175 ( .A0(n2004), .A1(n2088), .B0(n2003), .Y(n2092) );
OAI2BB1X1TS U3176 ( .A0N(n1692), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(n2081), .Y(n2011)
);
INVX2TS U3177 ( .A(n2005), .Y(n2008) );
INVX2TS U3178 ( .A(n2006), .Y(n2082) );
INVX2TS U3179 ( .A(n2132), .Y(n2084) );
NAND2X1TS U3180 ( .A(n2077), .B(n906), .Y(n2052) );
OAI22X1TS U3181 ( .A0(n2009), .A1(n2088), .B0(n2030), .B1(n2052), .Y(n2010)
);
AOI211X1TS U3182 ( .A0(n2092), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .B0(n2011), .C0(n2010), .Y(n2012) );
OAI22X1TS U3183 ( .A0(n2036), .A1(n2074), .B0(n2044), .B1(n2970), .Y(n2014)
);
AOI21X1TS U3184 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[91]), .A1(
n2072), .B0(n2014), .Y(n2043) );
AOI22X1TS U3185 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[81]), .A1(
n2071), .B0(Barrel_Shifter_module_Mux_Array_Data_array[89]), .B1(n2072), .Y(n2016) );
NAND2X1TS U3186 ( .A(n2077), .B(n2018), .Y(n2015) );
NAND2X1TS U3187 ( .A(n2035), .B(n2049), .Y(n2024) );
OAI2BB1X1TS U3188 ( .A0N(n1692), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .B0(n2081), .Y(n2022)
);
INVX2TS U3189 ( .A(n2017), .Y(n2019) );
OAI22X1TS U3190 ( .A0(n2020), .A1(n2088), .B0(n2039), .B1(n2052), .Y(n2021)
);
AOI211X1TS U3191 ( .A0(n2092), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .B0(n2022), .C0(n2021), .Y(n2023) );
NAND2X1TS U3192 ( .A(n2025), .B(n2058), .Y(n2033) );
INVX2TS U3193 ( .A(n2086), .Y(n2026) );
NOR2X2TS U3194 ( .A(n2026), .B(n2088), .Y(n2063) );
NAND2X1TS U3195 ( .A(n2133), .B(n2082), .Y(n2061) );
AOI21X1TS U3196 ( .A0(n2063), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .B0(n2028), .Y(n2029)
);
AOI21X1TS U3197 ( .A0(n2092), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(n2031), .Y(n2032)
);
NAND2X1TS U3198 ( .A(n2035), .B(n2058), .Y(n2042) );
AOI21X1TS U3199 ( .A0(n2063), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(n2037), .Y(n2038)
);
AOI21X1TS U3200 ( .A0(n2092), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .B0(n2040), .Y(n2041)
);
OAI22X1TS U3201 ( .A0(n2060), .A1(n2074), .B0(n2044), .B1(n2972), .Y(n2045)
);
AOI21X1TS U3202 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[93]), .A1(
n2072), .B0(n2045), .Y(n2070) );
AOI22X1TS U3203 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[79]), .A1(
n2071), .B0(Barrel_Shifter_module_Mux_Array_Data_array[87]), .B1(n2072), .Y(n2047) );
NAND2X1TS U3204 ( .A(n2077), .B(n2050), .Y(n2046) );
OAI211X1TS U3205 ( .A0(n2048), .A1(n2074), .B0(n2047), .C0(n2046), .Y(n2059)
);
NAND2X1TS U3206 ( .A(n2059), .B(n2049), .Y(n2057) );
OAI2BB1X1TS U3207 ( .A0N(n907), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .B0(n2081), .Y(n2055)
);
OAI22X1TS U3208 ( .A0(n2053), .A1(n2088), .B0(n2066), .B1(n2052), .Y(n2054)
);
NAND2X1TS U3209 ( .A(n2059), .B(n906), .Y(n2069) );
OAI2BB2XLTS U3210 ( .B0(n2061), .B1(n2060), .A0N(n907), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(n2062) );
AOI21X1TS U3211 ( .A0(n2063), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[93]), .B0(n2062), .Y(n2064)
);
AOI21X1TS U3212 ( .A0(n2092), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .B0(n2067), .Y(n2068)
);
AOI22X1TS U3213 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[86]), .A1(
n2072), .B0(Barrel_Shifter_module_Mux_Array_Data_array[78]), .B1(n2071), .Y(n2073) );
AOI21X1TS U3214 ( .A0(n2077), .A1(n2085), .B0(n2076), .Y(n2142) );
OAI22X1TS U3215 ( .A0(n2078), .A1(n2956), .B0(n889), .B1(n2886), .Y(n2121)
);
NOR2X1TS U3216 ( .A(n2914), .B(n2886), .Y(n2127) );
AOI211X1TS U3217 ( .A0(n2121), .A1(n886), .B0(n2127), .C0(n2080), .Y(n2138)
);
OAI22X1TS U3218 ( .A0(n2089), .A1(n920), .B0(n2136), .B1(n2087), .Y(n2090)
);
INVX2TS U3219 ( .A(n2597), .Y(n2096) );
OAI2BB2XLTS U3220 ( .B0(n2144), .B1(n3053), .A0N(n2143), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[98]), .Y(n2094) );
AOI211X1TS U3221 ( .A0(n2096), .A1(n2126), .B0(n2095), .C0(n2094), .Y(n2582)
);
INVX2TS U3222 ( .A(n2118), .Y(n2150) );
NAND2X1TS U3223 ( .A(n2580), .B(n2150), .Y(n2097) );
INVX2TS U3224 ( .A(n2615), .Y(n2100) );
OAI2BB2XLTS U3225 ( .B0(n2144), .B1(n2971), .A0N(n2143), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[100]), .Y(n2098) );
AOI211X1TS U3226 ( .A0(n2100), .A1(n1025), .B0(n2099), .C0(n2098), .Y(n2576)
);
NAND2X1TS U3227 ( .A(n2574), .B(n2150), .Y(n2101) );
INVX2TS U3228 ( .A(n2600), .Y(n2104) );
OAI2BB2XLTS U3229 ( .B0(n2144), .B1(n2970), .A0N(n2143), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[99]), .Y(n2102) );
AOI211X1TS U3230 ( .A0(n2104), .A1(n1025), .B0(n2103), .C0(n2102), .Y(n2579)
);
NAND2X1TS U3231 ( .A(n2577), .B(n2150), .Y(n2105) );
INVX2TS U3232 ( .A(n2593), .Y(n2108) );
OAI2BB2XLTS U3233 ( .B0(n2144), .B1(n2974), .A0N(n2143), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[96]), .Y(n2106) );
AOI211X1TS U3234 ( .A0(n2108), .A1(n1025), .B0(n2107), .C0(n2106), .Y(n2589)
);
NAND2X1TS U3235 ( .A(n2587), .B(n2150), .Y(n2109) );
INVX2TS U3236 ( .A(n2595), .Y(n2112) );
OAI2BB2XLTS U3237 ( .B0(n2144), .B1(n2973), .A0N(n2143), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[97]), .Y(n2110) );
AOI211X1TS U3238 ( .A0(n2112), .A1(n2126), .B0(n2111), .C0(n2110), .Y(n2586)
);
NAND2X1TS U3239 ( .A(n2584), .B(n2150), .Y(n2113) );
INVX2TS U3240 ( .A(n2115), .Y(n2119) );
NAND2X1TS U3241 ( .A(n2116), .B(n2842), .Y(n2117) );
AOI21X1TS U3242 ( .A0(exp_oper_result[4]), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[102]), .B0(n2123), .Y(n2124) );
OAI211XLTS U3243 ( .A0(n2132), .A1(n2957), .B0(n2131), .C0(n2130), .Y(n2134)
);
AOI22X1TS U3244 ( .A0(n2134), .A1(n2133), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .B1(n1692), .Y(n2140)
);
OA22X1TS U3245 ( .A0(n2138), .A1(n2137), .B0(n2136), .B1(n2135), .Y(n2139)
);
OAI2BB2XLTS U3246 ( .B0(n2144), .B1(n2972), .A0N(n2143), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[101]), .Y(n2145) );
AOI21X1TS U3247 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[77]), .A1(
n904), .B0(n2145), .Y(n2147) );
AOI21X1TS U3248 ( .A0(n905), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[93]), .B0(n2148), .Y(n2571)
);
NAND2X1TS U3249 ( .A(n2570), .B(n2150), .Y(n2151) );
AND4X1TS U3250 ( .A(Exp_Operation_Module_Data_S[3]), .B(
Exp_Operation_Module_Data_S[2]), .C(Exp_Operation_Module_Data_S[1]),
.D(Exp_Operation_Module_Data_S[0]), .Y(n2153) );
AND4X1TS U3251 ( .A(Exp_Operation_Module_Data_S[6]), .B(
Exp_Operation_Module_Data_S[5]), .C(Exp_Operation_Module_Data_S[4]),
.D(n2153), .Y(n2154) );
AOI21X1TS U3252 ( .A0(n2983), .A1(FS_Module_state_reg[1]), .B0(n2906), .Y(
n2157) );
AOI21X1TS U3253 ( .A0(n2158), .A1(n2906), .B0(n2157), .Y(
FSM_exp_operation_load_diff) );
OAI22X1TS U3254 ( .A0(n3111), .A1(intDY[55]), .B0(intDY[54]), .B1(n2890),
.Y(n2279) );
AOI211X1TS U3255 ( .A0(intDX[52]), .A1(n3042), .B0(n2159), .C0(n2279), .Y(
n2281) );
NOR2BX1TS U3256 ( .AN(intDX[56]), .B(intDY[56]), .Y(n2160) );
NOR2X1TS U3257 ( .A(n3058), .B(intDY[57]), .Y(n2233) );
NAND2X1TS U3258 ( .A(n3045), .B(intDX[61]), .Y(n2239) );
OAI211X1TS U3259 ( .A0(intDY[60]), .A1(n2947), .B0(n2243), .C0(n2239), .Y(
n2245) );
OAI21X1TS U3260 ( .A0(intDY[58]), .A1(n3112), .B0(n2235), .Y(n2237) );
NOR4X2TS U3261 ( .A(n2160), .B(n2233), .C(n2245), .D(n2237), .Y(n2290) );
NOR2X1TS U3262 ( .A(n2946), .B(intDY[49]), .Y(n2282) );
OAI21X1TS U3263 ( .A0(intDY[50]), .A1(n2943), .B0(n2284), .Y(n2288) );
AOI211X1TS U3264 ( .A0(intDX[48]), .A1(n3032), .B0(n2282), .C0(n2288), .Y(
n2161) );
NOR2BX1TS U3265 ( .AN(intDX[39]), .B(intDY[39]), .Y(n2273) );
AOI21X1TS U3266 ( .A0(intDX[38]), .A1(n3051), .B0(n2273), .Y(n2272) );
NOR2X1TS U3267 ( .A(n2945), .B(intDY[45]), .Y(n2247) );
OAI21X1TS U3268 ( .A0(intDY[46]), .A1(n2926), .B0(n2246), .Y(n2256) );
AOI211X2TS U3269 ( .A0(intDX[44]), .A1(n3031), .B0(n2247), .C0(n2256), .Y(
n2254) );
OA22X1TS U3270 ( .A0(n2905), .A1(intDY[42]), .B0(n2944), .B1(intDY[43]), .Y(
n2252) );
NAND4X1TS U3271 ( .A(n2254), .B(n2252), .C(n2163), .D(n2162), .Y(n2296) );
OA22X1TS U3272 ( .A0(n2895), .A1(intDY[34]), .B0(n2963), .B1(intDY[35]), .Y(
n2267) );
OAI2BB2XLTS U3273 ( .B0(intDX[28]), .B1(n2166), .A0N(intDY[29]), .A1N(n2941),
.Y(n2175) );
OAI21X1TS U3274 ( .A0(intDY[26]), .A1(n2965), .B0(n2169), .Y(n2228) );
NOR2X1TS U3275 ( .A(n2969), .B(intDY[25]), .Y(n2225) );
AOI22X1TS U3276 ( .A0(n2168), .A1(intDY[24]), .B0(intDY[25]), .B1(n2969),
.Y(n2171) );
AOI32X1TS U3277 ( .A0(n2965), .A1(n2169), .A2(intDY[26]), .B0(intDY[27]),
.B1(n2903), .Y(n2170) );
OAI32X1TS U3278 ( .A0(n2228), .A1(n2227), .A2(n2171), .B0(n2170), .B1(n2227),
.Y(n2174) );
OAI2BB2XLTS U3279 ( .B0(intDX[30]), .B1(n2172), .A0N(intDY[31]), .A1N(n2961),
.Y(n2173) );
OAI2BB1X1TS U3280 ( .A0N(n3048), .A1N(intDX[5]), .B0(intDY[4]), .Y(n2179) );
OAI22X1TS U3281 ( .A0(intDX[4]), .A1(n2179), .B0(n3048), .B1(intDX[5]), .Y(
n2190) );
OAI2BB1X1TS U3282 ( .A0N(n3046), .A1N(intDX[7]), .B0(intDY[6]), .Y(n2180) );
OAI22X1TS U3283 ( .A0(intDX[6]), .A1(n2180), .B0(n3046), .B1(intDX[7]), .Y(
n2189) );
OAI211X1TS U3284 ( .A0(n2966), .A1(intDY[3]), .B0(n2183), .C0(n2182), .Y(
n2186) );
AOI222X1TS U3285 ( .A0(intDX[4]), .A1(n923), .B0(intDX[5]), .B1(n3048), .C0(
n2186), .C1(n2185), .Y(n2188) );
AOI22X1TS U3286 ( .A0(intDX[7]), .A1(n3046), .B0(intDX[6]), .B1(n2910), .Y(
n2187) );
OAI32X1TS U3287 ( .A0(n2190), .A1(n2189), .A2(n2188), .B0(n2187), .B1(n2189),
.Y(n2208) );
INVX2TS U3288 ( .A(n2191), .Y(n2198) );
OAI2BB2XLTS U3289 ( .B0(intDX[12]), .B1(n2192), .A0N(intDY[13]), .A1N(n2935),
.Y(n2204) );
AOI22X1TS U3290 ( .A0(intDY[11]), .A1(n2923), .B0(intDY[10]), .B1(n2194),
.Y(n2200) );
AOI21X1TS U3291 ( .A0(n2197), .A1(n2196), .B0(n2209), .Y(n2199) );
OAI2BB2XLTS U3292 ( .B0(intDX[14]), .B1(n2201), .A0N(intDY[15]), .A1N(n2967),
.Y(n2202) );
AOI211X1TS U3293 ( .A0(n2205), .A1(n2204), .B0(n2203), .C0(n2202), .Y(n2206)
);
OAI31X1TS U3294 ( .A0(n2209), .A1(n2208), .A2(n2207), .B0(n2206), .Y(n2211)
);
NOR2X1TS U3295 ( .A(n2964), .B(intDY[17]), .Y(n2213) );
OAI21X1TS U3296 ( .A0(intDY[18]), .A1(n2968), .B0(n2215), .Y(n2219) );
AOI211X1TS U3297 ( .A0(intDX[16]), .A1(n3006), .B0(n2213), .C0(n2219), .Y(
n2210) );
OAI2BB2XLTS U3298 ( .B0(intDX[20]), .B1(n2212), .A0N(intDY[21]), .A1N(n2939),
.Y(n2223) );
AOI22X1TS U3299 ( .A0(n2214), .A1(intDY[16]), .B0(intDY[17]), .B1(n2964),
.Y(n2217) );
AOI32X1TS U3300 ( .A0(n2968), .A1(n2215), .A2(intDY[18]), .B0(intDY[19]),
.B1(n2904), .Y(n2216) );
OAI32X1TS U3301 ( .A0(n2219), .A1(n2218), .A2(n2217), .B0(n2216), .B1(n2218),
.Y(n2222) );
OAI2BB2XLTS U3302 ( .B0(intDX[22]), .B1(n2220), .A0N(intDY[23]), .A1N(n3050),
.Y(n2221) );
AOI211X1TS U3303 ( .A0(n2224), .A1(n2223), .B0(n2222), .C0(n2221), .Y(n2230)
);
NOR2BX1TS U3304 ( .AN(intDX[24]), .B(intDY[24]), .Y(n2226) );
OR4X2TS U3305 ( .A(n2228), .B(n2227), .C(n2226), .D(n2225), .Y(n2229) );
AOI32X1TS U3306 ( .A0(n2232), .A1(n2231), .A2(n2230), .B0(n2229), .B1(n2232),
.Y(n2301) );
AOI22X1TS U3307 ( .A0(intDY[57]), .A1(n3058), .B0(intDY[56]), .B1(n2234),
.Y(n2238) );
AOI32X1TS U3308 ( .A0(n3112), .A1(n2235), .A2(intDY[58]), .B0(intDY[59]),
.B1(n2908), .Y(n2236) );
OA21XLTS U3309 ( .A0(n2238), .A1(n2237), .B0(n2236), .Y(n2244) );
NOR2BX1TS U3310 ( .AN(n2246), .B(intDX[46]), .Y(n2260) );
AOI22X1TS U3311 ( .A0(intDY[45]), .A1(n2945), .B0(intDY[44]), .B1(n2248),
.Y(n2257) );
OAI2BB2XLTS U3312 ( .B0(intDX[40]), .B1(n2249), .A0N(intDY[41]), .A1N(n2928),
.Y(n2253) );
OAI2BB2XLTS U3313 ( .B0(intDX[42]), .B1(n2250), .A0N(intDY[43]), .A1N(n2944),
.Y(n2251) );
AOI32X1TS U3314 ( .A0(n2254), .A1(n2253), .A2(n2252), .B0(n2251), .B1(n2254),
.Y(n2255) );
NOR2BX1TS U3315 ( .AN(intDY[47]), .B(intDX[47]), .Y(n2258) );
AOI211X1TS U3316 ( .A0(intDY[46]), .A1(n2260), .B0(n2259), .C0(n2258), .Y(
n2297) );
OAI2BB2XLTS U3317 ( .B0(intDX[32]), .B1(n2264), .A0N(intDY[33]), .A1N(n2962),
.Y(n2268) );
OAI2BB2XLTS U3318 ( .B0(intDX[34]), .B1(n2265), .A0N(intDY[35]), .A1N(n2963),
.Y(n2266) );
AOI32X1TS U3319 ( .A0(n2269), .A1(n2268), .A2(n2267), .B0(n2266), .B1(n2269),
.Y(n2270) );
NOR2BX1TS U3320 ( .AN(intDY[39]), .B(intDX[39]), .Y(n2276) );
NOR3X1TS U3321 ( .A(n3051), .B(n2273), .C(intDX[38]), .Y(n2275) );
INVX2TS U3322 ( .A(n2298), .Y(n2274) );
OAI31X1TS U3323 ( .A0(n2277), .A1(n2276), .A2(n2275), .B0(n2274), .Y(n2295)
);
AOI22X1TS U3324 ( .A0(intDY[49]), .A1(n2946), .B0(intDY[48]), .B1(n2283),
.Y(n2286) );
AOI32X1TS U3325 ( .A0(n2943), .A1(n2284), .A2(intDY[50]), .B0(intDY[51]),
.B1(n2909), .Y(n2285) );
OAI32X1TS U3326 ( .A0(n2288), .A1(n2287), .A2(n2286), .B0(n2285), .B1(n2287),
.Y(n2292) );
OAI2BB2XLTS U3327 ( .B0(intDX[54]), .B1(n2289), .A0N(intDY[55]), .A1N(n3111),
.Y(n2291) );
OAI31X1TS U3328 ( .A0(n2293), .A1(n2292), .A2(n2291), .B0(n2290), .Y(n2294)
);
INVX4TS U3329 ( .A(n2634), .Y(n2639) );
AOI21X1TS U3330 ( .A0(n2639), .A1(n2554), .B0(intDX[63]), .Y(n2304) );
OAI2BB2XLTS U3331 ( .B0(n2304), .B1(n3110), .A0N(intDX[63]), .A1N(n2569),
.Y(n3113) );
XNOR2X1TS U3332 ( .A(add_subt), .B(Data_Y[63]), .Y(n3057) );
INVX2TS U3333 ( .A(n2305), .Y(n2306) );
NAND2X1TS U3334 ( .A(n2307), .B(n2306), .Y(n2308) );
XNOR2X1TS U3335 ( .A(n2309), .B(n2308), .Y(Add_Subt_Sgf_module_S_to_D[54])
);
INVX2TS U3336 ( .A(n2310), .Y(n2312) );
NAND2X1TS U3337 ( .A(n2312), .B(n2311), .Y(n2313) );
NAND2X1TS U3338 ( .A(n2316), .B(n2315), .Y(n2317) );
XNOR2X1TS U3339 ( .A(n2318), .B(n2317), .Y(Add_Subt_Sgf_module_S_to_D[52])
);
INVX2TS U3340 ( .A(n2319), .Y(n2321) );
NAND2X1TS U3341 ( .A(n2321), .B(n2320), .Y(n2322) );
NAND2X1TS U3342 ( .A(n2325), .B(n2324), .Y(n2326) );
XNOR2X1TS U3343 ( .A(n2327), .B(n2326), .Y(Add_Subt_Sgf_module_S_to_D[50])
);
INVX2TS U3344 ( .A(n2328), .Y(n2330) );
NAND2X1TS U3345 ( .A(n2330), .B(n2329), .Y(n2331) );
NAND2X1TS U3346 ( .A(n2334), .B(n2333), .Y(n2335) );
XNOR2X1TS U3347 ( .A(n2336), .B(n2335), .Y(Add_Subt_Sgf_module_S_to_D[48])
);
INVX2TS U3348 ( .A(n2337), .Y(n2339) );
NAND2X1TS U3349 ( .A(n2339), .B(n2338), .Y(n2340) );
INVX2TS U3350 ( .A(n2344), .Y(n2346) );
NAND2X1TS U3351 ( .A(n2346), .B(n2345), .Y(n2347) );
XNOR2X1TS U3352 ( .A(n2348), .B(n2347), .Y(Add_Subt_Sgf_module_S_to_D[46])
);
INVX2TS U3353 ( .A(n2349), .Y(n2352) );
INVX2TS U3354 ( .A(n2350), .Y(n2351) );
NAND2X1TS U3355 ( .A(n2355), .B(n2354), .Y(n2356) );
XNOR2X1TS U3356 ( .A(n2357), .B(n2356), .Y(Add_Subt_Sgf_module_S_to_D[45])
);
NAND2X1TS U3357 ( .A(n2359), .B(n2358), .Y(n2360) );
XNOR2X1TS U3358 ( .A(n2361), .B(n2360), .Y(Add_Subt_Sgf_module_S_to_D[41])
);
INVX2TS U3359 ( .A(n2362), .Y(n2371) );
INVX2TS U3360 ( .A(n2370), .Y(n2363) );
AOI21X1TS U3361 ( .A0(n2364), .A1(n2371), .B0(n2363), .Y(n2369) );
INVX2TS U3362 ( .A(n2365), .Y(n2367) );
NAND2X1TS U3363 ( .A(n2367), .B(n2366), .Y(n2368) );
NAND2X1TS U3364 ( .A(n2371), .B(n2370), .Y(n2372) );
NAND2X1TS U3365 ( .A(n2375), .B(n2374), .Y(n2376) );
XNOR2X1TS U3366 ( .A(n2377), .B(n2376), .Y(Add_Subt_Sgf_module_S_to_D[37])
);
NAND2X1TS U3367 ( .A(n2379), .B(n2378), .Y(n2380) );
XNOR2X1TS U3368 ( .A(n2381), .B(n2380), .Y(Add_Subt_Sgf_module_S_to_D[33])
);
INVX2TS U3369 ( .A(n2382), .Y(n2384) );
NAND2X1TS U3370 ( .A(n2384), .B(n2383), .Y(n2385) );
XNOR2X1TS U3371 ( .A(n2386), .B(n2385), .Y(Add_Subt_Sgf_module_S_to_D[32])
);
INVX2TS U3372 ( .A(n2387), .Y(n2389) );
NAND2X1TS U3373 ( .A(n2389), .B(n2388), .Y(n2390) );
INVX2TS U3374 ( .A(n2395), .Y(n2398) );
INVX2TS U3375 ( .A(n2396), .Y(n2397) );
AOI21X2TS U3376 ( .A0(n2444), .A1(n2398), .B0(n2397), .Y(n2411) );
INVX2TS U3377 ( .A(n2411), .Y(n2421) );
AOI21X2TS U3378 ( .A0(n2421), .A1(n2400), .B0(n2399), .Y(n2410) );
INVX2TS U3379 ( .A(n2401), .Y(n2403) );
NAND2X1TS U3380 ( .A(n2403), .B(n2402), .Y(n2404) );
XNOR2X1TS U3381 ( .A(n2405), .B(n2404), .Y(Add_Subt_Sgf_module_S_to_D[30])
);
INVX2TS U3382 ( .A(n2406), .Y(n2408) );
NAND2X1TS U3383 ( .A(n2408), .B(n2407), .Y(n2409) );
INVX2TS U3384 ( .A(n2412), .Y(n2414) );
NAND2X1TS U3385 ( .A(n2414), .B(n2413), .Y(n2415) );
XNOR2X1TS U3386 ( .A(n2416), .B(n2415), .Y(Add_Subt_Sgf_module_S_to_D[28])
);
INVX2TS U3387 ( .A(n2417), .Y(n2419) );
NAND2X1TS U3388 ( .A(n2419), .B(n2418), .Y(n2420) );
XNOR2X1TS U3389 ( .A(n2421), .B(n2420), .Y(Add_Subt_Sgf_module_S_to_D[27])
);
AOI21X1TS U3390 ( .A0(n2444), .A1(n2423), .B0(n2422), .Y(n2433) );
INVX2TS U3391 ( .A(n2424), .Y(n2426) );
NAND2X1TS U3392 ( .A(n2426), .B(n2425), .Y(n2427) );
XNOR2X1TS U3393 ( .A(n2428), .B(n2427), .Y(Add_Subt_Sgf_module_S_to_D[26])
);
INVX2TS U3394 ( .A(n2429), .Y(n2431) );
NAND2X1TS U3395 ( .A(n2431), .B(n2430), .Y(n2432) );
INVX2TS U3396 ( .A(n2435), .Y(n2437) );
NAND2X1TS U3397 ( .A(n2437), .B(n2436), .Y(n2438) );
XNOR2X1TS U3398 ( .A(n2439), .B(n2438), .Y(Add_Subt_Sgf_module_S_to_D[24])
);
INVX2TS U3399 ( .A(n2440), .Y(n2442) );
NAND2X1TS U3400 ( .A(n2442), .B(n2441), .Y(n2443) );
XNOR2X1TS U3401 ( .A(n2444), .B(n2443), .Y(Add_Subt_Sgf_module_S_to_D[23])
);
INVX2TS U3402 ( .A(n2445), .Y(n2448) );
INVX2TS U3403 ( .A(n2446), .Y(n2447) );
INVX2TS U3404 ( .A(n2461), .Y(n2471) );
AOI21X1TS U3405 ( .A0(n2471), .A1(n2450), .B0(n2449), .Y(n2460) );
INVX2TS U3406 ( .A(n2451), .Y(n2453) );
NAND2X1TS U3407 ( .A(n2453), .B(n2452), .Y(n2454) );
XNOR2X1TS U3408 ( .A(n2455), .B(n2454), .Y(Add_Subt_Sgf_module_S_to_D[22])
);
INVX2TS U3409 ( .A(n2456), .Y(n2458) );
NAND2X1TS U3410 ( .A(n2458), .B(n2457), .Y(n2459) );
INVX2TS U3411 ( .A(n2462), .Y(n2464) );
NAND2X1TS U3412 ( .A(n2464), .B(n2463), .Y(n2465) );
XNOR2X1TS U3413 ( .A(n2466), .B(n2465), .Y(Add_Subt_Sgf_module_S_to_D[20])
);
INVX2TS U3414 ( .A(n2467), .Y(n2469) );
NAND2X1TS U3415 ( .A(n2469), .B(n2468), .Y(n2470) );
XNOR2X1TS U3416 ( .A(n2471), .B(n2470), .Y(Add_Subt_Sgf_module_S_to_D[19])
);
AOI21X1TS U3417 ( .A0(n2494), .A1(n2473), .B0(n2472), .Y(n2483) );
INVX2TS U3418 ( .A(n2474), .Y(n2476) );
NAND2X1TS U3419 ( .A(n2476), .B(n2475), .Y(n2477) );
XNOR2X1TS U3420 ( .A(n2478), .B(n2477), .Y(Add_Subt_Sgf_module_S_to_D[18])
);
INVX2TS U3421 ( .A(n2479), .Y(n2481) );
NAND2X1TS U3422 ( .A(n2481), .B(n2480), .Y(n2482) );
INVX2TS U3423 ( .A(n2484), .Y(n2492) );
INVX2TS U3424 ( .A(n2491), .Y(n2485) );
AOI21X1TS U3425 ( .A0(n2494), .A1(n2492), .B0(n2485), .Y(n2490) );
INVX2TS U3426 ( .A(n2486), .Y(n2488) );
NAND2X1TS U3427 ( .A(n2488), .B(n2487), .Y(n2489) );
NAND2X1TS U3428 ( .A(n2492), .B(n2491), .Y(n2493) );
XNOR2X1TS U3429 ( .A(n2494), .B(n2493), .Y(Add_Subt_Sgf_module_S_to_D[15])
);
NAND2X1TS U3430 ( .A(n2496), .B(n2495), .Y(n2497) );
XNOR2X1TS U3431 ( .A(n2498), .B(n2497), .Y(Add_Subt_Sgf_module_S_to_D[13])
);
NAND2X1TS U3432 ( .A(n2500), .B(n2499), .Y(n2501) );
XNOR2X1TS U3433 ( .A(n2502), .B(n2501), .Y(Add_Subt_Sgf_module_S_to_D[9]) );
INVX2TS U3434 ( .A(n2503), .Y(n2505) );
NAND2X1TS U3435 ( .A(n2505), .B(n2504), .Y(n2506) );
XNOR2X1TS U3436 ( .A(n2507), .B(n2506), .Y(Add_Subt_Sgf_module_S_to_D[8]) );
INVX2TS U3437 ( .A(n2508), .Y(n2510) );
NAND2X1TS U3438 ( .A(n2510), .B(n2509), .Y(n2511) );
INVX2TS U3439 ( .A(n2513), .Y(n2536) );
AOI21X1TS U3440 ( .A0(n2536), .A1(n2515), .B0(n2514), .Y(n2525) );
INVX2TS U3441 ( .A(n2516), .Y(n2518) );
NAND2X1TS U3442 ( .A(n2518), .B(n2517), .Y(n2519) );
XNOR2X1TS U3443 ( .A(n2520), .B(n2519), .Y(Add_Subt_Sgf_module_S_to_D[6]) );
INVX2TS U3444 ( .A(n2521), .Y(n2523) );
NAND2X1TS U3445 ( .A(n2523), .B(n2522), .Y(n2524) );
INVX2TS U3446 ( .A(n2526), .Y(n2534) );
INVX2TS U3447 ( .A(n2533), .Y(n2527) );
AOI21X1TS U3448 ( .A0(n2536), .A1(n2534), .B0(n2527), .Y(n2532) );
INVX2TS U3449 ( .A(n2528), .Y(n2530) );
NAND2X1TS U3450 ( .A(n2530), .B(n2529), .Y(n2531) );
NAND2X1TS U3451 ( .A(n2534), .B(n2533), .Y(n2535) );
XNOR2X1TS U3452 ( .A(n2536), .B(n2535), .Y(Add_Subt_Sgf_module_S_to_D[3]) );
INVX2TS U3453 ( .A(n2537), .Y(n2546) );
NAND2X1TS U3454 ( .A(n2539), .B(n2538), .Y(n2540) );
INVX2TS U3455 ( .A(n2541), .Y(n2543) );
NAND2X1TS U3456 ( .A(n2543), .B(n2542), .Y(n2544) );
XNOR2X1TS U3457 ( .A(n2545), .B(n2544), .Y(Add_Subt_Sgf_module_S_to_D[2]) );
XNOR2X1TS U3458 ( .A(n2549), .B(n2548), .Y(Add_Subt_Sgf_module_S_to_D[0]) );
INVX2TS U3459 ( .A(n2550), .Y(n2552) );
NOR2X1TS U3460 ( .A(FSM_selector_C), .B(n2883), .Y(n2618) );
OR4X2TS U3461 ( .A(n2552), .B(n2551), .C(n2618), .D(
FSM_exp_operation_load_diff), .Y(FS_Module_state_next[2]) );
NAND2X1TS U3462 ( .A(n2906), .B(n2555), .Y(n2556) );
NAND2X1TS U3463 ( .A(n2623), .B(n2920), .Y(n866) );
MXI2X1TS U3464 ( .A(n2909), .B(n3033), .S0(n2562), .Y(
Oper_Start_in_module_intM[51]) );
MXI2X1TS U3465 ( .A(n2943), .B(n3030), .S0(n2563), .Y(
Oper_Start_in_module_intM[50]) );
MXI2X1TS U3466 ( .A(n2946), .B(n3029), .S0(n2564), .Y(
Oper_Start_in_module_intM[49]) );
MXI2X1TS U3467 ( .A(n2927), .B(n3032), .S0(n2563), .Y(
Oper_Start_in_module_intM[48]) );
MXI2X1TS U3468 ( .A(n2888), .B(n3036), .S0(n2563), .Y(
Oper_Start_in_module_intM[47]) );
MXI2X1TS U3469 ( .A(n2926), .B(n3027), .S0(n2563), .Y(
Oper_Start_in_module_intM[46]) );
MXI2X1TS U3470 ( .A(n2945), .B(n3028), .S0(n2638), .Y(
Oper_Start_in_module_intM[45]) );
MXI2X1TS U3471 ( .A(n2925), .B(n3031), .S0(n2563), .Y(
Oper_Start_in_module_intM[44]) );
OAI2BB1X1TS U3472 ( .A0N(FSM_Add_Subt_Sgf_load), .A1N(n2906), .B0(n3023),
.Y(n867) );
MXI2X1TS U3473 ( .A(n2917), .B(add_overflow_flag), .S0(n2561), .Y(n865) );
MXI2X1TS U3474 ( .A(n887), .B(n3044), .S0(n2638), .Y(
Oper_Start_in_module_intM[62]) );
BUFX3TS U3475 ( .A(n2563), .Y(n2564) );
MXI2X1TS U3476 ( .A(n888), .B(n3045), .S0(n2564), .Y(
Oper_Start_in_module_intM[61]) );
BUFX3TS U3477 ( .A(n2563), .Y(n2562) );
MXI2X1TS U3478 ( .A(n2947), .B(n3038), .S0(n2562), .Y(
Oper_Start_in_module_intM[60]) );
MXI2X1TS U3479 ( .A(n2908), .B(n3043), .S0(n2563), .Y(
Oper_Start_in_module_intM[59]) );
MXI2X1TS U3480 ( .A(n3112), .B(n3040), .S0(n2562), .Y(
Oper_Start_in_module_intM[58]) );
MXI2X1TS U3481 ( .A(n3058), .B(n3037), .S0(n2564), .Y(
Oper_Start_in_module_intM[57]) );
MXI2X1TS U3482 ( .A(n2889), .B(n3041), .S0(n2562), .Y(
Oper_Start_in_module_intM[56]) );
MXI2X1TS U3483 ( .A(n3111), .B(n3019), .S0(n2564), .Y(
Oper_Start_in_module_intM[55]) );
MXI2X1TS U3484 ( .A(n2890), .B(n3039), .S0(n2562), .Y(
Oper_Start_in_module_intM[54]) );
MXI2X1TS U3485 ( .A(n2948), .B(n3018), .S0(n2564), .Y(
Oper_Start_in_module_intM[53]) );
MXI2X1TS U3486 ( .A(n2929), .B(n3042), .S0(n2562), .Y(
Oper_Start_in_module_intM[52]) );
BUFX3TS U3487 ( .A(n2563), .Y(n2566) );
MXI2X1TS U3488 ( .A(n3044), .B(n887), .S0(n2566), .Y(
Oper_Start_in_module_intm[62]) );
BUFX3TS U3489 ( .A(n2563), .Y(n2565) );
MXI2X1TS U3490 ( .A(n3045), .B(n888), .S0(n2565), .Y(
Oper_Start_in_module_intm[61]) );
MXI2X1TS U3491 ( .A(n3038), .B(n2947), .S0(n2566), .Y(
Oper_Start_in_module_intm[60]) );
MXI2X1TS U3492 ( .A(n3043), .B(n2908), .S0(n2565), .Y(
Oper_Start_in_module_intm[59]) );
MXI2X1TS U3493 ( .A(n3040), .B(n3112), .S0(n2564), .Y(
Oper_Start_in_module_intm[58]) );
MXI2X1TS U3494 ( .A(n3037), .B(n3058), .S0(n2565), .Y(
Oper_Start_in_module_intm[57]) );
MXI2X1TS U3495 ( .A(n3041), .B(n2889), .S0(n2566), .Y(
Oper_Start_in_module_intm[56]) );
MXI2X1TS U3496 ( .A(n3019), .B(n3111), .S0(n2565), .Y(
Oper_Start_in_module_intm[55]) );
MXI2X1TS U3497 ( .A(n3039), .B(n2890), .S0(n2566), .Y(
Oper_Start_in_module_intm[54]) );
MXI2X1TS U3498 ( .A(n3018), .B(n2948), .S0(n2565), .Y(
Oper_Start_in_module_intm[53]) );
MXI2X1TS U3499 ( .A(n3042), .B(n2929), .S0(n2566), .Y(
Oper_Start_in_module_intm[52]) );
INVX2TS U3500 ( .A(n2649), .Y(n2567) );
MXI2X1TS U3501 ( .A(n2568), .B(n2567), .S0(n2863), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[54]) );
MXI2X1TS U3502 ( .A(n2944), .B(n3016), .S0(n2639), .Y(
Oper_Start_in_module_intM[43]) );
MXI2X1TS U3503 ( .A(n2905), .B(n3034), .S0(n2639), .Y(
Oper_Start_in_module_intM[42]) );
MXI2X1TS U3504 ( .A(n2928), .B(n3017), .S0(n2639), .Y(
Oper_Start_in_module_intM[41]) );
MXI2X1TS U3505 ( .A(n2885), .B(n3035), .S0(n2639), .Y(
Oper_Start_in_module_intM[40]) );
INVX2TS U3506 ( .A(n2570), .Y(n2572) );
OAI22X1TS U3507 ( .A0(n2572), .A1(n916), .B0(n2859), .B1(n2571), .Y(
Barrel_Shifter_module_Data_Reg[22]) );
INVX2TS U3508 ( .A(n2573), .Y(n2859) );
INVX2TS U3509 ( .A(n2574), .Y(n2575) );
OAI22X1TS U3510 ( .A0(n2576), .A1(n2616), .B0(n2575), .B1(n916), .Y(
Barrel_Shifter_module_Data_Reg[21]) );
INVX2TS U3511 ( .A(n2577), .Y(n2578) );
OAI22X1TS U3512 ( .A0(n2579), .A1(n1265), .B0(n2578), .B1(n916), .Y(
Barrel_Shifter_module_Data_Reg[20]) );
INVX2TS U3513 ( .A(n2580), .Y(n2581) );
OAI22X1TS U3514 ( .A0(n2582), .A1(n2744), .B0(n2581), .B1(n916), .Y(
Barrel_Shifter_module_Data_Reg[19]) );
INVX2TS U3515 ( .A(n2584), .Y(n2585) );
OAI22X1TS U3516 ( .A0(n2586), .A1(n896), .B0(n2585), .B1(n916), .Y(
Barrel_Shifter_module_Data_Reg[18]) );
INVX2TS U3517 ( .A(n2587), .Y(n2588) );
OAI22X1TS U3518 ( .A0(n2589), .A1(n1265), .B0(n2588), .B1(n916), .Y(
Barrel_Shifter_module_Data_Reg[17]) );
OAI22X1TS U3519 ( .A0(n2592), .A1(n896), .B0(n2591), .B1(n916), .Y(
Barrel_Shifter_module_Data_Reg[6]) );
OAI22X1TS U3520 ( .A0(n2594), .A1(n895), .B0(n2593), .B1(n915), .Y(
Barrel_Shifter_module_Data_Reg[5]) );
OAI22X1TS U3521 ( .A0(n2596), .A1(n895), .B0(n2595), .B1(n915), .Y(
Barrel_Shifter_module_Data_Reg[4]) );
OAI22X1TS U3522 ( .A0(n2598), .A1(n2616), .B0(n2597), .B1(n915), .Y(
Barrel_Shifter_module_Data_Reg[3]) );
OAI22X1TS U3523 ( .A0(n2601), .A1(n896), .B0(n2600), .B1(n915), .Y(
Barrel_Shifter_module_Data_Reg[2]) );
OAI22X1TS U3524 ( .A0(n2603), .A1(n1909), .B0(n915), .B1(n2602), .Y(
Barrel_Shifter_module_Data_Reg[0]) );
OAI21XLTS U3525 ( .A0(Add_Subt_result[2]), .A1(n2605), .B0(n2604), .Y(n2609)
);
OAI21XLTS U3526 ( .A0(Add_Subt_result[14]), .A1(n2607), .B0(n2606), .Y(n2608) );
OAI22X1TS U3527 ( .A0(n2617), .A1(n2744), .B0(n2615), .B1(n916), .Y(
Barrel_Shifter_module_Data_Reg[1]) );
NOR3BX1TS U3528 ( .AN(n2619), .B(n2618), .C(FSM_Final_Result_load), .Y(n2622) );
AOI211X1TS U3529 ( .A0(FS_Module_state_reg[0]), .A1(FSM_Add_Subt_Sgf_load),
.B0(n873), .C0(n871), .Y(n2621) );
CLKBUFX2TS U3530 ( .A(n1236), .Y(n2880) );
BUFX3TS U3531 ( .A(n2880), .Y(n2625) );
BUFX3TS U3532 ( .A(n2880), .Y(n2879) );
BUFX3TS U3533 ( .A(n2880), .Y(n2624) );
BUFX3TS U3534 ( .A(n1236), .Y(n2626) );
NAND2X1TS U3535 ( .A(n2628), .B(n2627), .Y(
final_result_ieee_Module_Exp_S_mux[4]) );
AOI21X1TS U3536 ( .A0(n2911), .A1(n3056), .B0(overflow_flag), .Y(
final_result_ieee_Module_Sign_S_mux) );
AOI22X1TS U3537 ( .A0(n2634), .A1(n2907), .B0(n2958), .B1(n2633), .Y(
Oper_Start_in_module_intm[0]) );
AOI22X1TS U3538 ( .A0(n2632), .A1(n3049), .B0(n2933), .B1(n2639), .Y(
Oper_Start_in_module_intm[1]) );
AOI22X1TS U3539 ( .A0(n2632), .A1(n3015), .B0(n2900), .B1(n2639), .Y(
Oper_Start_in_module_intm[2]) );
AOI22X1TS U3540 ( .A0(n2634), .A1(n2984), .B0(n2966), .B1(n2639), .Y(
Oper_Start_in_module_intm[3]) );
AOI22X1TS U3541 ( .A0(n2632), .A1(n923), .B0(n2938), .B1(n2639), .Y(
Oper_Start_in_module_intm[4]) );
BUFX3TS U3542 ( .A(n2632), .Y(n2630) );
AOI22X1TS U3543 ( .A0(n2630), .A1(n3048), .B0(n2892), .B1(n2629), .Y(
Oper_Start_in_module_intm[5]) );
AOI22X1TS U3544 ( .A0(n2630), .A1(n2910), .B0(n2932), .B1(n2629), .Y(
Oper_Start_in_module_intm[6]) );
AOI22X1TS U3545 ( .A0(n2630), .A1(n3046), .B0(n2891), .B1(n2629), .Y(
Oper_Start_in_module_intm[7]) );
AOI22X1TS U3546 ( .A0(n2630), .A1(n2993), .B0(n2959), .B1(n2629), .Y(
Oper_Start_in_module_intm[8]) );
AOI22X1TS U3547 ( .A0(n2630), .A1(n3009), .B0(n2896), .B1(n2629), .Y(
Oper_Start_in_module_intm[9]) );
AOI22X1TS U3548 ( .A0(n2630), .A1(n3047), .B0(n2887), .B1(n2629), .Y(
Oper_Start_in_module_intm[10]) );
AOI22X1TS U3549 ( .A0(n2630), .A1(n2995), .B0(n2923), .B1(n2629), .Y(
Oper_Start_in_module_intm[11]) );
AOI22X1TS U3550 ( .A0(n2630), .A1(n2992), .B0(n2936), .B1(n2629), .Y(
Oper_Start_in_module_intm[12]) );
AOI22X1TS U3551 ( .A0(n2630), .A1(n2988), .B0(n2935), .B1(n2629), .Y(
Oper_Start_in_module_intm[13]) );
AOI22X1TS U3552 ( .A0(n2630), .A1(n3012), .B0(n2901), .B1(n2629), .Y(
Oper_Start_in_module_intm[14]) );
BUFX3TS U3553 ( .A(n2632), .Y(n2631) );
AOI22X1TS U3554 ( .A0(n2631), .A1(n2989), .B0(n2967), .B1(n2566), .Y(
Oper_Start_in_module_intm[15]) );
AOI22X1TS U3555 ( .A0(n2631), .A1(n3006), .B0(n2937), .B1(n2564), .Y(
Oper_Start_in_module_intm[16]) );
AOI22X1TS U3556 ( .A0(n2631), .A1(n3002), .B0(n2964), .B1(n2565), .Y(
Oper_Start_in_module_intm[17]) );
AOI22X1TS U3557 ( .A0(n2631), .A1(n3001), .B0(n2968), .B1(n2566), .Y(
Oper_Start_in_module_intm[18]) );
AOI22X1TS U3558 ( .A0(n2631), .A1(n3011), .B0(n2904), .B1(n2565), .Y(
Oper_Start_in_module_intm[19]) );
AOI22X1TS U3559 ( .A0(n2631), .A1(n3000), .B0(n2942), .B1(n2564), .Y(
Oper_Start_in_module_intm[20]) );
AOI22X1TS U3560 ( .A0(n2631), .A1(n2990), .B0(n2939), .B1(n2562), .Y(
Oper_Start_in_module_intm[21]) );
AOI22X1TS U3561 ( .A0(n2631), .A1(n3013), .B0(n2902), .B1(n2566), .Y(
Oper_Start_in_module_intm[22]) );
AOI22X1TS U3562 ( .A0(n2631), .A1(n2930), .B0(n3050), .B1(n2562), .Y(
Oper_Start_in_module_intm[23]) );
AOI22X1TS U3563 ( .A0(n2631), .A1(n3003), .B0(n2898), .B1(n2565), .Y(
Oper_Start_in_module_intm[24]) );
BUFX3TS U3564 ( .A(n2632), .Y(n2640) );
AOI22X1TS U3565 ( .A0(n2640), .A1(n3005), .B0(n2969), .B1(n2633), .Y(
Oper_Start_in_module_intm[25]) );
AOI22X1TS U3566 ( .A0(n2640), .A1(n2998), .B0(n2965), .B1(n2633), .Y(
Oper_Start_in_module_intm[26]) );
AOI22X1TS U3567 ( .A0(n2640), .A1(n3014), .B0(n2903), .B1(n2633), .Y(
Oper_Start_in_module_intm[27]) );
AOI22X1TS U3568 ( .A0(n2640), .A1(n2997), .B0(n2940), .B1(n2633), .Y(
Oper_Start_in_module_intm[28]) );
AOI22X1TS U3569 ( .A0(n2640), .A1(n2991), .B0(n2941), .B1(n2633), .Y(
Oper_Start_in_module_intm[29]) );
AOI22X1TS U3570 ( .A0(n2640), .A1(n3010), .B0(n2899), .B1(n2633), .Y(
Oper_Start_in_module_intm[30]) );
AOI22X1TS U3571 ( .A0(n2640), .A1(n2986), .B0(n2961), .B1(n2633), .Y(
Oper_Start_in_module_intm[31]) );
AOI22X1TS U3572 ( .A0(n2640), .A1(n3007), .B0(n2894), .B1(n2633), .Y(
Oper_Start_in_module_intm[32]) );
AOI22X1TS U3573 ( .A0(n2640), .A1(n2985), .B0(n2962), .B1(n2633), .Y(
Oper_Start_in_module_intm[33]) );
BUFX3TS U3574 ( .A(n2634), .Y(n2636) );
AOI22X1TS U3575 ( .A0(n2636), .A1(n3004), .B0(n2895), .B1(n2635), .Y(
Oper_Start_in_module_intm[34]) );
AOI22X1TS U3576 ( .A0(n2636), .A1(n2987), .B0(n2963), .B1(n2635), .Y(
Oper_Start_in_module_intm[35]) );
AOI22X1TS U3577 ( .A0(n2636), .A1(n2994), .B0(n2960), .B1(n2635), .Y(
Oper_Start_in_module_intm[36]) );
AOI22X1TS U3578 ( .A0(n2636), .A1(n924), .B0(n2934), .B1(n2635), .Y(
Oper_Start_in_module_intm[37]) );
AOI22X1TS U3579 ( .A0(n2636), .A1(n3051), .B0(n2893), .B1(n2635), .Y(
Oper_Start_in_module_intm[38]) );
AOI22X1TS U3580 ( .A0(n2636), .A1(n3008), .B0(n2897), .B1(n2635), .Y(
Oper_Start_in_module_intm[39]) );
AOI22X1TS U3581 ( .A0(n2636), .A1(n3035), .B0(n2885), .B1(n2635), .Y(
Oper_Start_in_module_intm[40]) );
AOI22X1TS U3582 ( .A0(n2636), .A1(n3017), .B0(n2928), .B1(n2635), .Y(
Oper_Start_in_module_intm[41]) );
AOI22X1TS U3583 ( .A0(n2636), .A1(n3034), .B0(n2905), .B1(n2635), .Y(
Oper_Start_in_module_intm[42]) );
AOI22X1TS U3584 ( .A0(n2636), .A1(n3016), .B0(n2944), .B1(n2635), .Y(
Oper_Start_in_module_intm[43]) );
INVX2TS U3585 ( .A(n2637), .Y(n2638) );
AOI22X1TS U3586 ( .A0(n2569), .A1(n3031), .B0(n2925), .B1(n2638), .Y(
Oper_Start_in_module_intm[44]) );
AOI22X1TS U3587 ( .A0(n2637), .A1(n3028), .B0(n2945), .B1(n2638), .Y(
Oper_Start_in_module_intm[45]) );
AOI22X1TS U3588 ( .A0(n2637), .A1(n3027), .B0(n2926), .B1(n2638), .Y(
Oper_Start_in_module_intm[46]) );
AOI22X1TS U3589 ( .A0(n2637), .A1(n3036), .B0(n2888), .B1(n2638), .Y(
Oper_Start_in_module_intm[47]) );
AOI22X1TS U3590 ( .A0(n2637), .A1(n3032), .B0(n2927), .B1(n2638), .Y(
Oper_Start_in_module_intm[48]) );
AOI22X1TS U3591 ( .A0(n2303), .A1(n3029), .B0(n2946), .B1(n2638), .Y(
Oper_Start_in_module_intm[49]) );
AOI22X1TS U3592 ( .A0(n2637), .A1(n3030), .B0(n2943), .B1(n2638), .Y(
Oper_Start_in_module_intm[50]) );
AOI22X1TS U3593 ( .A0(n2640), .A1(n3033), .B0(n2909), .B1(n2639), .Y(
Oper_Start_in_module_intm[51]) );
NAND2X1TS U3594 ( .A(n2678), .B(n2684), .Y(n2644) );
NAND2X1TS U3595 ( .A(n2680), .B(n2687), .Y(n2643) );
NAND2X1TS U3596 ( .A(n2669), .B(n2641), .Y(n2642) );
BUFX3TS U3597 ( .A(n2645), .Y(n2840) );
AOI22X1TS U3598 ( .A0(n2649), .A1(n2840), .B0(n2851), .B1(n2673), .Y(n2646)
);
OAI221XLTS U3599 ( .A0(n2676), .A1(n2647), .B0(n2711), .B1(n2675), .C0(n2646), .Y(Barrel_Shifter_module_Mux_Array_Data_array[48]) );
BUFX3TS U3600 ( .A(n2648), .Y(n2853) );
AOI22X1TS U3601 ( .A0(n2649), .A1(n2853), .B0(n2833), .B1(n2673), .Y(n2650)
);
OAI221XLTS U3602 ( .A0(n2676), .A1(n2652), .B0(n1558), .B1(n2651), .C0(n2650), .Y(Barrel_Shifter_module_Mux_Array_Data_array[47]) );
NAND2X1TS U3603 ( .A(n2666), .B(n2668), .Y(n2656) );
NAND2X1TS U3604 ( .A(n2653), .B(n2687), .Y(n2655) );
NAND2X1TS U3605 ( .A(n2667), .B(n2695), .Y(n2654) );
AOI22X1TS U3606 ( .A0(n2703), .A1(n2684), .B0(n2853), .B1(n2657), .Y(n2658)
);
OAI221XLTS U3607 ( .A0(n2676), .A1(n2659), .B0(n1558), .B1(n2686), .C0(n2658), .Y(Barrel_Shifter_module_Mux_Array_Data_array[46]) );
NAND2X1TS U3608 ( .A(n1890), .B(n2695), .Y(n2662) );
NAND2X1TS U3609 ( .A(n2679), .B(n2668), .Y(n2661) );
NAND2X1TS U3610 ( .A(n1889), .B(n2700), .Y(n2660) );
AOI22X1TS U3611 ( .A0(n2833), .A1(n2687), .B0(n2781), .B1(n2663), .Y(n2664)
);
OAI221XLTS U3612 ( .A0(n2676), .A1(n2665), .B0(n2711), .B1(n2691), .C0(n2664), .Y(Barrel_Shifter_module_Mux_Array_Data_array[45]) );
NAND2X1TS U3613 ( .A(n2666), .B(n2700), .Y(n2672) );
NAND2X1TS U3614 ( .A(n1889), .B(n2688), .Y(n2671) );
NAND2X1TS U3615 ( .A(n2669), .B(n2668), .Y(n2670) );
AOI22X1TS U3616 ( .A0(n2832), .A1(n2695), .B0(n2870), .B1(n2673), .Y(n2674)
);
OAI221XLTS U3617 ( .A0(n2676), .A1(n2675), .B0(n1558), .B1(n2694), .C0(n2674), .Y(Barrel_Shifter_module_Mux_Array_Data_array[44]) );
NAND2X1TS U3618 ( .A(n2666), .B(n2677), .Y(n2683) );
NAND2X1TS U3619 ( .A(n2679), .B(n2688), .Y(n2682) );
NAND2X1TS U3620 ( .A(n2667), .B(n2696), .Y(n2681) );
AOI22X1TS U3621 ( .A0(n2703), .A1(n2700), .B0(n2701), .B1(n2684), .Y(n2685)
);
OAI221XLTS U3622 ( .A0(n2708), .A1(n2686), .B0(n2706), .B1(n2707), .C0(n2685), .Y(Barrel_Shifter_module_Mux_Array_Data_array[42]) );
AOI22X1TS U3623 ( .A0(n2833), .A1(n2688), .B0(n2781), .B1(n2687), .Y(n2689)
);
OAI221XLTS U3624 ( .A0(n2708), .A1(n2691), .B0(n2706), .B1(n2690), .C0(n2689), .Y(Barrel_Shifter_module_Mux_Array_Data_array[41]) );
AOI22X1TS U3625 ( .A0(n2832), .A1(n2696), .B0(n2870), .B1(n2695), .Y(n2692)
);
OAI221XLTS U3626 ( .A0(n2708), .A1(n2694), .B0(n2706), .B1(n2693), .C0(n2692), .Y(Barrel_Shifter_module_Mux_Array_Data_array[40]) );
AOI22X1TS U3627 ( .A0(n2703), .A1(n2696), .B0(n2701), .B1(n2695), .Y(n2697)
);
OAI221XLTS U3628 ( .A0(n2708), .A1(n2699), .B0(n2706), .B1(n2698), .C0(n2697), .Y(Barrel_Shifter_module_Mux_Array_Data_array[39]) );
AOI22X1TS U3629 ( .A0(n2703), .A1(n2702), .B0(n2701), .B1(n2700), .Y(n2704)
);
OAI221XLTS U3630 ( .A0(n2708), .A1(n2707), .B0(n2706), .B1(n2705), .C0(n2704), .Y(Barrel_Shifter_module_Mux_Array_Data_array[38]) );
AOI22X1TS U3631 ( .A0(n2870), .A1(n2709), .B0(n2865), .B1(n2746), .Y(n2716)
);
AOI22X1TS U3632 ( .A0(n2833), .A1(n2731), .B0(n2850), .B1(n2752), .Y(n2715)
);
AOI22X1TS U3633 ( .A0(n2851), .A1(n2738), .B0(n2781), .B1(n2710), .Y(n2714)
);
NAND2X1TS U3634 ( .A(n2712), .B(n2711), .Y(n2713) );
AOI22X1TS U3635 ( .A0(n2865), .A1(n2752), .B0(n909), .B1(n2717), .Y(n2718)
);
OAI31X1TS U3636 ( .A0(n2726), .A1(n2725), .A2(n2719), .B0(n2718), .Y(n2722)
);
AOI22X1TS U3637 ( .A0(n2833), .A1(n2738), .B0(n2850), .B1(n2759), .Y(n2721)
);
AOI22X1TS U3638 ( .A0(n2851), .A1(n2746), .B0(n913), .B1(n2731), .Y(n2720)
);
AOI22X1TS U3639 ( .A0(n2851), .A1(n2752), .B0(n2850), .B1(n2767), .Y(n2723)
);
AOI22X1TS U3640 ( .A0(n914), .A1(n2738), .B0(n910), .B1(n2731), .Y(n2728) );
AOI22X1TS U3641 ( .A0(n2833), .A1(n2746), .B0(n2865), .B1(n2759), .Y(n2727)
);
AOI22X1TS U3642 ( .A0(n914), .A1(n2752), .B0(n911), .B1(n2746), .Y(n2735) );
AOI22X1TS U3643 ( .A0(n2840), .A1(n2738), .B0(n2839), .B1(n2773), .Y(n2734)
);
AOI22X1TS U3644 ( .A0(n896), .A1(Add_Subt_result[36]), .B0(n2764), .B1(
DmP[16]), .Y(n2730) );
OAI2BB1X2TS U3645 ( .A0N(Add_Subt_result[18]), .A1N(n2806), .B0(n2730), .Y(
n2780) );
AOI22X1TS U3646 ( .A0(n2844), .A1(n2767), .B0(n2850), .B1(n2780), .Y(n2733)
);
AOI22X1TS U3647 ( .A0(n2874), .A1(n2731), .B0(n2872), .B1(n2759), .Y(n2732)
);
AOI22X1TS U3648 ( .A0(n913), .A1(n2759), .B0(n910), .B1(n2752), .Y(n2742) );
AOI22X1TS U3649 ( .A0(n2870), .A1(n2746), .B0(n2865), .B1(n2780), .Y(n2741)
);
AOI22X1TS U3650 ( .A0(n2744), .A1(Add_Subt_result[37]), .B0(DmP[15]), .B1(
n2736), .Y(n2737) );
OAI2BB1X2TS U3651 ( .A0N(Add_Subt_result[17]), .A1N(n2806), .B0(n2737), .Y(
n2788) );
AOI22X1TS U3652 ( .A0(n2832), .A1(n2773), .B0(n2863), .B1(n2788), .Y(n2740)
);
AOI22X1TS U3653 ( .A0(n2781), .A1(n2738), .B0(n2872), .B1(n2767), .Y(n2739)
);
AOI22X1TS U3654 ( .A0(n914), .A1(n2767), .B0(n911), .B1(n2759), .Y(n2750) );
AOI22X1TS U3655 ( .A0(n2840), .A1(n2752), .B0(n2839), .B1(n2788), .Y(n2749)
);
AOI22X1TS U3656 ( .A0(n896), .A1(Add_Subt_result[38]), .B0(n2764), .B1(
DmP[14]), .Y(n2745) );
OAI2BB1X2TS U3657 ( .A0N(Add_Subt_result[16]), .A1N(n2806), .B0(n2745), .Y(
n2794) );
AOI22X1TS U3658 ( .A0(n2844), .A1(n2780), .B0(n2743), .B1(n2794), .Y(n2748)
);
AOI22X1TS U3659 ( .A0(n2854), .A1(n2773), .B0(n2853), .B1(n2746), .Y(n2747)
);
AOI22X1TS U3660 ( .A0(n913), .A1(n2773), .B0(n910), .B1(n2767), .Y(n2756) );
AOI22X1TS U3661 ( .A0(n2870), .A1(n2759), .B0(n2865), .B1(n2794), .Y(n2755)
);
AOI22X1TS U3662 ( .A0(n2859), .A1(Add_Subt_result[39]), .B0(n2764), .B1(
DmP[13]), .Y(n2751) );
OAI21X4TS U3663 ( .A0(n2787), .A1(n2999), .B0(n2751), .Y(n2800) );
AOI22X1TS U3664 ( .A0(n2832), .A1(n2788), .B0(n2863), .B1(n2800), .Y(n2754)
);
AOI22X1TS U3665 ( .A0(n2874), .A1(n2752), .B0(n2872), .B1(n2780), .Y(n2753)
);
AOI22X1TS U3666 ( .A0(n913), .A1(n2780), .B0(n910), .B1(n2773), .Y(n2763) );
AOI22X1TS U3667 ( .A0(n2870), .A1(n2767), .B0(n2757), .B1(n2800), .Y(n2762)
);
AOI22X1TS U3668 ( .A0(n2616), .A1(Add_Subt_result[40]), .B0(n2764), .B1(
DmP[12]), .Y(n2758) );
OAI2BB1X2TS U3669 ( .A0N(Add_Subt_result[14]), .A1N(n2806), .B0(n2758), .Y(
n2807) );
AOI22X1TS U3670 ( .A0(n2844), .A1(n2794), .B0(n2743), .B1(n2807), .Y(n2761)
);
AOI22X1TS U3671 ( .A0(n2854), .A1(n2788), .B0(n2853), .B1(n2759), .Y(n2760)
);
AOI22X1TS U3672 ( .A0(n914), .A1(n2788), .B0(n911), .B1(n2780), .Y(n2771) );
AOI22X1TS U3673 ( .A0(n2840), .A1(n2773), .B0(n2839), .B1(n2807), .Y(n2770)
);
AOI22X1TS U3674 ( .A0(n1265), .A1(Add_Subt_result[41]), .B0(n2764), .B1(
DmP[11]), .Y(n2765) );
OAI21X4TS U3675 ( .A0(n2766), .A1(n3026), .B0(n2765), .Y(n2813) );
AOI22X1TS U3676 ( .A0(n2844), .A1(n2800), .B0(n2743), .B1(n2813), .Y(n2769)
);
AOI22X1TS U3677 ( .A0(n2874), .A1(n2767), .B0(n2872), .B1(n2794), .Y(n2768)
);
AOI22X1TS U3678 ( .A0(n913), .A1(n2794), .B0(n910), .B1(n2788), .Y(n2777) );
AOI22X1TS U3679 ( .A0(n2645), .A1(n2780), .B0(n2757), .B1(n2813), .Y(n2776)
);
AOI22X1TS U3680 ( .A0(n2616), .A1(Add_Subt_result[42]), .B0(n2841), .B1(
DmP[10]), .Y(n2772) );
OAI2BB1X2TS U3681 ( .A0N(Add_Subt_result[12]), .A1N(n2806), .B0(n2772), .Y(
n2820) );
AOI22X1TS U3682 ( .A0(n2844), .A1(n2807), .B0(n2743), .B1(n2820), .Y(n2775)
);
AOI22X1TS U3683 ( .A0(n2854), .A1(n2800), .B0(n2853), .B1(n2773), .Y(n2774)
);
AOI22X1TS U3684 ( .A0(n913), .A1(n2800), .B0(n910), .B1(n2794), .Y(n2785) );
AOI22X1TS U3685 ( .A0(n2840), .A1(n2788), .B0(n2839), .B1(n2820), .Y(n2784)
);
AOI22X1TS U3686 ( .A0(n1909), .A1(Add_Subt_result[43]), .B0(n2841), .B1(
DmP[9]), .Y(n2778) );
OAI21X4TS U3687 ( .A0(n2787), .A1(n3020), .B0(n2778), .Y(n2826) );
AOI22X1TS U3688 ( .A0(n2844), .A1(n2813), .B0(n2743), .B1(n2826), .Y(n2783)
);
AOI22X1TS U3689 ( .A0(n2781), .A1(n2780), .B0(n2779), .B1(n2807), .Y(n2782)
);
AOI22X1TS U3690 ( .A0(n914), .A1(n2807), .B0(n911), .B1(n2800), .Y(n2792) );
AOI22X1TS U3691 ( .A0(n2645), .A1(n2794), .B0(n2757), .B1(n2826), .Y(n2791)
);
AOI22X1TS U3692 ( .A0(n896), .A1(Add_Subt_result[44]), .B0(n2841), .B1(
DmP[8]), .Y(n2786) );
OAI21X4TS U3693 ( .A0(n2787), .A1(n2996), .B0(n2786), .Y(n2834) );
AOI22X1TS U3694 ( .A0(n2844), .A1(n2820), .B0(n2743), .B1(n2834), .Y(n2790)
);
AOI22X1TS U3695 ( .A0(n2854), .A1(n2813), .B0(n2853), .B1(n2788), .Y(n2789)
);
AOI22X1TS U3696 ( .A0(n914), .A1(n2813), .B0(n910), .B1(n2807), .Y(n2798) );
AOI22X1TS U3697 ( .A0(n2645), .A1(n2800), .B0(n2757), .B1(n2834), .Y(n2797)
);
AOI22X1TS U3698 ( .A0(n2859), .A1(Add_Subt_result[45]), .B0(DmP[7]), .B1(
n2818), .Y(n2793) );
OAI2BB1X2TS U3699 ( .A0N(Add_Subt_result[9]), .A1N(n2806), .B0(n2793), .Y(
n2845) );
AOI22X1TS U3700 ( .A0(n2832), .A1(n2826), .B0(n2863), .B1(n2845), .Y(n2796)
);
AOI22X1TS U3701 ( .A0(n2874), .A1(n2794), .B0(n2872), .B1(n2820), .Y(n2795)
);
AOI22X1TS U3702 ( .A0(n914), .A1(n2820), .B0(n911), .B1(n2813), .Y(n2804) );
AOI22X1TS U3703 ( .A0(n2840), .A1(n2807), .B0(n2839), .B1(n2845), .Y(n2803)
);
AOI22X1TS U3704 ( .A0(n2842), .A1(Add_Subt_result[46]), .B0(DmP[6]), .B1(
n2818), .Y(n2799) );
OAI2BB1X2TS U3705 ( .A0N(Add_Subt_result[8]), .A1N(n2806), .B0(n2799), .Y(
n2852) );
AOI22X1TS U3706 ( .A0(n2832), .A1(n2834), .B0(n2863), .B1(n2852), .Y(n2802)
);
AOI22X1TS U3707 ( .A0(n2874), .A1(n2800), .B0(n2872), .B1(n2826), .Y(n2801)
);
AOI22X1TS U3708 ( .A0(n913), .A1(n2826), .B0(n911), .B1(n2820), .Y(n2811) );
AOI22X1TS U3709 ( .A0(n2840), .A1(n2813), .B0(n2839), .B1(n2852), .Y(n2810)
);
AOI22X1TS U3710 ( .A0(n2842), .A1(Add_Subt_result[47]), .B0(n2841), .B1(
DmP[5]), .Y(n2805) );
OAI2BB1X2TS U3711 ( .A0N(Add_Subt_result[7]), .A1N(n2806), .B0(n2805), .Y(
n2873) );
AOI22X1TS U3712 ( .A0(n2832), .A1(n2845), .B0(n2863), .B1(n2873), .Y(n2809)
);
AOI22X1TS U3713 ( .A0(n2874), .A1(n2807), .B0(n2833), .B1(n2834), .Y(n2808)
);
AOI22X1TS U3714 ( .A0(n914), .A1(n2834), .B0(n911), .B1(n2826), .Y(n2817) );
AOI22X1TS U3715 ( .A0(n2645), .A1(n2820), .B0(n2757), .B1(n2873), .Y(n2816)
);
AOI22X1TS U3716 ( .A0(n2842), .A1(Add_Subt_result[48]), .B0(n2841), .B1(
DmP[4]), .Y(n2812) );
OAI2BB1X2TS U3717 ( .A0N(Add_Subt_result[6]), .A1N(n2860), .B0(n2812), .Y(
n2869) );
AOI22X1TS U3718 ( .A0(n2832), .A1(n2852), .B0(n2863), .B1(n2869), .Y(n2815)
);
AOI22X1TS U3719 ( .A0(n2854), .A1(n2845), .B0(n2853), .B1(n2813), .Y(n2814)
);
AOI22X1TS U3720 ( .A0(n912), .A1(n2845), .B0(n909), .B1(n2834), .Y(n2824) );
AOI22X1TS U3721 ( .A0(n2645), .A1(n2826), .B0(n2757), .B1(n2869), .Y(n2823)
);
AOI22X1TS U3722 ( .A0(n2842), .A1(Add_Subt_result[49]), .B0(DmP[3]), .B1(
n2818), .Y(n2819) );
OAI2BB1X2TS U3723 ( .A0N(Add_Subt_result[5]), .A1N(n2860), .B0(n2819), .Y(
n2861) );
AOI22X1TS U3724 ( .A0(n2851), .A1(n2873), .B0(n2863), .B1(n2861), .Y(n2822)
);
AOI22X1TS U3725 ( .A0(n2854), .A1(n2852), .B0(n2853), .B1(n2820), .Y(n2821)
);
AOI22X1TS U3726 ( .A0(n912), .A1(n2852), .B0(n909), .B1(n2845), .Y(n2830) );
AOI22X1TS U3727 ( .A0(n2840), .A1(n2834), .B0(n2839), .B1(n2861), .Y(n2829)
);
AOI22X1TS U3728 ( .A0(n2842), .A1(Add_Subt_result[50]), .B0(n2841), .B1(
DmP[2]), .Y(n2825) );
OAI2BB1X2TS U3729 ( .A0N(Add_Subt_result[4]), .A1N(n2860), .B0(n2825), .Y(
n2866) );
AOI22X1TS U3730 ( .A0(n2844), .A1(n2869), .B0(n2743), .B1(n2866), .Y(n2828)
);
AOI22X1TS U3731 ( .A0(n2874), .A1(n2826), .B0(n2872), .B1(n2873), .Y(n2827)
);
AOI22X1TS U3732 ( .A0(n912), .A1(n2873), .B0(n909), .B1(n2852), .Y(n2838) );
AOI22X1TS U3733 ( .A0(n2840), .A1(n2845), .B0(n2839), .B1(n2866), .Y(n2837)
);
AOI22X1TS U3734 ( .A0(n2842), .A1(Add_Subt_result[51]), .B0(n2841), .B1(
DmP[1]), .Y(n2831) );
OAI2BB1X1TS U3735 ( .A0N(Add_Subt_result[3]), .A1N(n2860), .B0(n2831), .Y(
n2871) );
AOI22X1TS U3736 ( .A0(n2832), .A1(n2861), .B0(n2850), .B1(n2871), .Y(n2836)
);
AOI22X1TS U3737 ( .A0(n2874), .A1(n2834), .B0(n2833), .B1(n2869), .Y(n2835)
);
AOI22X1TS U3738 ( .A0(n912), .A1(n2869), .B0(n909), .B1(n2873), .Y(n2849) );
AOI22X1TS U3739 ( .A0(n2840), .A1(n2852), .B0(n2839), .B1(n2871), .Y(n2848)
);
AOI22X1TS U3740 ( .A0(n2842), .A1(Add_Subt_result[52]), .B0(n2841), .B1(
DmP[0]), .Y(n2843) );
OAI2BB1X1TS U3741 ( .A0N(Add_Subt_result[2]), .A1N(n2860), .B0(n2843), .Y(
n2867) );
AOI22X1TS U3742 ( .A0(n2844), .A1(n2866), .B0(n2850), .B1(n2867), .Y(n2847)
);
AOI22X1TS U3743 ( .A0(n2854), .A1(n2861), .B0(n2853), .B1(n2845), .Y(n2846)
);
AOI22X1TS U3744 ( .A0(n912), .A1(n2861), .B0(n910), .B1(n2869), .Y(n2858) );
AOI22X1TS U3745 ( .A0(n2645), .A1(n2873), .B0(n2865), .B1(n2867), .Y(n2857)
);
AOI22X1TS U3746 ( .A0(n2851), .A1(n2871), .B0(n2850), .B1(n2864), .Y(n2856)
);
AOI22X1TS U3747 ( .A0(n2854), .A1(n2866), .B0(n2853), .B1(n2852), .Y(n2855)
);
AOI22X1TS U3748 ( .A0(n2863), .A1(n2862), .B0(n911), .B1(n2861), .Y(n2878)
);
AOI22X1TS U3749 ( .A0(n912), .A1(n2866), .B0(n2865), .B1(n2864), .Y(n2877)
);
AOI22X1TS U3750 ( .A0(n2870), .A1(n2869), .B0(n2868), .B1(n2867), .Y(n2876)
);
AOI22X1TS U3751 ( .A0(n2874), .A1(n2873), .B0(n2872), .B1(n2871), .Y(n2875)
);
CLKBUFX2TS U3752 ( .A(n2880), .Y(n2881) );
INVX2TS U3754 ( .A(ack_FSM), .Y(n2882) );
NAND2X1TS U3755 ( .A(n2884), .B(n2883), .Y(FSM_barrel_shifter_load) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of lp
//
// Generated
// by: lutscher
// on: Fri Jun 26 13:24:43 2009
// cmd: /tools/mix/1.9//mix_1.pl -vinc global_project.i -nodelta LP-blue-pin-list.xls LP-paris-pin-list.xls LP-reallity-pin-list.xls LP-HIER.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author$
// $Id$
// $Date$
// $Log$
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.109 2008/04/01 12:48:34 wig Exp
//
// Generator: mix_1.pl Revision: 1.3 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of lp
//
// No user `defines in this module
module lp
//
// Generated Module lp_i1
//
(
vec_in_5,
vec_in_0,
vec_in_6,
vec_in_3,
ext0,
vec_in_4,
vec_in_2,
vec_in_1,
vec_in_7,
ext1,
vec_out_0,
ext2,
vec_out_1,
vec_out_2,
vec_out_3,
bidi
);
// Generated Module In/Outputs:
inout vec_in_5;
inout vec_in_0;
inout vec_in_6;
inout vec_in_3;
inout ext0;
inout vec_in_4;
inout vec_in_2;
inout vec_in_1;
inout vec_in_7;
inout ext1;
inout vec_out_0;
inout ext2;
inout vec_out_1;
inout vec_out_2;
inout vec_out_3;
inout bidi;
// Generated Wires:
wire vec_in_5;
wire vec_in_0;
wire vec_in_6;
wire vec_in_3;
wire ext0;
wire vec_in_4;
wire vec_in_2;
wire vec_in_1;
wire vec_in_7;
wire ext1;
wire vec_out_0;
wire ext2;
wire vec_out_1;
wire vec_out_2;
wire vec_out_3;
wire bidi;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire bidi_pad_di;
wire bidi_pad_do;
wire bidi_pad_en;
wire ext0_pad_di;
wire ext1_pad_do;
wire ext2_pad_do;
wire vec_in_0_pad_di;
wire vec_in_1_pad_di;
wire vec_in_2_pad_di;
wire vec_in_3_pad_di;
wire vec_in_4_pad_di;
wire vec_in_5_pad_di;
wire vec_in_6_pad_di;
wire vec_in_7_pad_di;
wire vec_out_0_pad_do;
wire vec_out_1_pad_do;
wire vec_out_2_pad_do;
wire vec_out_3_pad_do;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for lp_bs_i1
lp_bs lp_bs_i1 ( // LP bs
.bidi_pad_di(bidi_pad_di), // from EXTERNALPAD <-> Iocell connect (IO)
.bidi_pad_do(bidi_pad_do), // to EXTERNALPAD <-> Iocell connect (IO)
.bidi_pad_en(bidi_pad_en), // to EXTERNALPAD <-> Iocell connect (IO)
.ext0_pad_di(ext0_pad_di), // from EXTERNALPAD <-> Iocell connect (IO)
.ext1_pad_do(ext1_pad_do), // from bluePAD <-> Iocell connect (IO)
.ext2_pad_do(ext2_pad_do), // from bluePAD <-> Iocell connect (IO)
.vec_in_0_pad_di(vec_in_0_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_1_pad_di(vec_in_1_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_2_pad_di(vec_in_2_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_3_pad_di(vec_in_3_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_4_pad_di(vec_in_4_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_5_pad_di(vec_in_5_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_6_pad_di(vec_in_6_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_7_pad_di(vec_in_7_pad_di), // testPAD <-> Iocell connect (IO)
.vec_out_0_pad_do(vec_out_0_pad_do), // testPAD <-> Iocell connect (IO)
.vec_out_1_pad_do(vec_out_1_pad_do), // testPAD <-> Iocell connect (IO)
.vec_out_2_pad_do(vec_out_2_pad_do), // testPAD <-> Iocell connect (IO)
.vec_out_3_pad_do(vec_out_3_pad_do) // testPAD <-> Iocell connect (IO)
);
// End of Generated Instance Port Map for lp_bs_i1
// Generated Instance Port Map for lp_padframe_i1
lp_padframe lp_padframe_i1 ( // LP padframe
.bidi(bidi), // PAD <-> Iocell connect (IO)
.bidi_pad_di(bidi_pad_di), // from EXTERNALPAD <-> Iocell connect (IO)
.bidi_pad_do(bidi_pad_do), // to EXTERNALPAD <-> Iocell connect (IO)
.bidi_pad_en(bidi_pad_en), // to EXTERNALPAD <-> Iocell connect (IO)
.ext0(ext0), // PAD <-> Iocell connect (IO)
.ext0_pad_di(ext0_pad_di), // from EXTERNALPAD <-> Iocell connect (IO)
.ext1(ext1), // PAD <-> Iocell connect (IO)
.ext1_pad_do(ext1_pad_do), // from bluePAD <-> Iocell connect (IO)
.ext2(ext2), // PAD <-> Iocell connect (IO)
.ext2_pad_do(ext2_pad_do), // from bluePAD <-> Iocell connect (IO)
.vec_in_0(vec_in_0), // PAD <-> Iocell connect (IO)
.vec_in_0_pad_di(vec_in_0_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_1(vec_in_1), // PAD <-> Iocell connect (IO)
.vec_in_1_pad_di(vec_in_1_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_2(vec_in_2), // PAD <-> Iocell connect (IO)
.vec_in_2_pad_di(vec_in_2_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_3(vec_in_3), // PAD <-> Iocell connect (IO)
.vec_in_3_pad_di(vec_in_3_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_4(vec_in_4), // PAD <-> Iocell connect (IO)
.vec_in_4_pad_di(vec_in_4_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_5(vec_in_5), // PAD <-> Iocell connect (IO)
.vec_in_5_pad_di(vec_in_5_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_6(vec_in_6), // PAD <-> Iocell connect (IO)
.vec_in_6_pad_di(vec_in_6_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_7(vec_in_7), // PAD <-> Iocell connect (IO)
.vec_in_7_pad_di(vec_in_7_pad_di), // testPAD <-> Iocell connect (IO)
.vec_out_0(vec_out_0), // PAD <-> Iocell connect (IO)
.vec_out_0_pad_do(vec_out_0_pad_do), // testPAD <-> Iocell connect (IO)
.vec_out_1(vec_out_1), // PAD <-> Iocell connect (IO)
.vec_out_1_pad_do(vec_out_1_pad_do), // testPAD <-> Iocell connect (IO)
.vec_out_2(vec_out_2), // PAD <-> Iocell connect (IO)
.vec_out_2_pad_do(vec_out_2_pad_do), // testPAD <-> Iocell connect (IO)
.vec_out_3(vec_out_3), // PAD <-> Iocell connect (IO)
.vec_out_3_pad_do(vec_out_3_pad_do) // testPAD <-> Iocell connect (IO)
);
// End of Generated Instance Port Map for lp_padframe_i1
endmodule
//
// End of Generated Module rtl of lp
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// test-bench for the ALU
`timescale 1 ns / 100 ps
module alu_testbench ();
reg [15:0] A, B;
reg [4:0] Op;
reg Swap;
wire [15:0] Q;
wire Carry, Zero, Sign;
BitsliceALU DUT (A, B, Op, Q, Flags);
task test_vector;
input [4:0] testOp;
input [15:0] testA, testB;
input [15:0] expectQ;
input expectCarry, expectZero, expectMinus1;
begin
$display($time, "M=%b, S=%h, Cn=%b, A = %h, B = %h", testOp, testSwap, testA, testB);
A = testA;
B = testB;
Op = testOp;
Swap = testSwap;
#10 if ( (Q==expectQ) && (Carry==expectCarry) && (Zero==expectZero) && (Minus1==expectMinus1) )
$display($time, " passed.");
else
begin
if (Q != expectQ)
$display($time, " ... FAILED with Q = %h", Q);
if (Carry != expectCarry)
$display($time, " ... FAILED with Carry = %h", Carry);
if (Zero != expectZero)
$display($time, " ... FAILED with Zero = %h", Zero);
if (Minus1 != expectMinus1)
$display($time, " ... FAILED with Minus1 = %h", Minus1);
end
end
endtask
initial
begin
$display($time, " ##### Testing addition... #####");
// MSSSS AAAA BBBB QQQQ C Z M1
#10 test_vector(5'b01001,1'b1,16'h4444,16'h2345,16'h8967,1'b0,1'b0,1'b0);
#10 test_vector(5'b01001,1'b0,16'hf00f,16'hc7c8,16'hb7d7,1'b1,1'b0,1'b0);
#10 test_vector(5'b01001,1'b1,16'h3cc3,16'h7cc7,16'h8ab9,1'b0,1'b0,1'b0);
#10 test_vector(5'b01001,1'b0,16'hff00,16'h0100,16'h0000,1'b1,1'b1,1'b0);
#10 test_vector(5'b01001,1'b1,16'h0000,16'h0000,16'h0000,1'b0,1'b1,1'b0);
#10 test_vector(5'b01001,1'b0,16'h7777,16'h8888,16'hffff,1'b0,1'b0,1'b1);
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32A_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O32A_BEHAVIORAL_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o32a (
X ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32A_BEHAVIORAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_div_exp_dp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// Divide pipeline exponent datapath.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_div_exp_dp (
inq_in1,
inq_in2,
d1stg_step,
d234stg_fdiv,
div_expadd1_in1_dbl,
div_expadd1_in1_sng,
div_expadd1_in2_exp_in2_dbl,
div_expadd1_in2_exp_in2_sng,
d3stg_fdiv,
d4stg_fdiv,
div_shl_cnt,
div_exp1_expadd1,
div_exp1_0835,
div_exp1_0118,
div_exp1_zero,
div_exp1_load,
div_expadd2_in1_exp_out,
d5stg_fdiva,
d5stg_fdivd,
d5stg_fdivs,
d6stg_fdiv,
d7stg_fdiv,
div_expadd2_no_decr_inv,
div_expadd2_cin,
div_exp_out_expadd2,
div_exp_out_expadd22_inv,
div_exp_out_of,
d7stg_to_0_inv,
d7stg_fdivd,
div_exp_out_exp_out,
d7stg_rndup_inv,
div_frac_add_52_inv,
div_exp_out_load,
fdiv_clken_l,
rclk,
div_exp1,
div_expadd2_12,
div_exp_out,
div_exp_outa,
se,
si,
so
);
input [62:52] inq_in1; // request operand 1 to op pipes
input [62:52] inq_in2; // request operand 2 to op pipes
input d1stg_step; // divide pipe load
input d234stg_fdiv; // select line to div_expadd1
input div_expadd1_in1_dbl; // select line to div_expadd1
input div_expadd1_in1_sng; // select line to div_expadd1
input div_expadd1_in2_exp_in2_dbl; // select line to div_expadd1
input div_expadd1_in2_exp_in2_sng; //select line to div_expadd1
input d3stg_fdiv; // divide operation- divide stage 3
input d4stg_fdiv; // divide operation- divide stage 4
input [5:0] div_shl_cnt; // divide left shift amount
input div_exp1_expadd1; // select line to div_exp1
input div_exp1_0835; // select line to div_exp1
input div_exp1_0118; // select line to div_exp1
input div_exp1_zero; // select line to div_exp1
input div_exp1_load; // load enable to div_exp1
input div_expadd2_in1_exp_out; // select line to div_expadd2
input d5stg_fdiva; // divide operation- divide stage 5
input d5stg_fdivd; // divide double- divide stage 5
input d5stg_fdivs; // divide single- divide stage 5
input d6stg_fdiv; // divide operation- divide stage 6
input d7stg_fdiv; // divide operation- divide stage 7
input div_expadd2_no_decr_inv; // no exponent decrement
input div_expadd2_cin; // carry in to 2nd exponent adder
input div_exp_out_expadd2; // select line to div_exp_out
input div_exp_out_expadd22_inv; // select line to div_exp_out
input div_exp_out_of; // overflow to exponent output
input d7stg_to_0_inv; // result to infinity on overflow
input d7stg_fdivd; // divide double- divide stage 7
input div_exp_out_exp_out; // select line to div_exp_out
input d7stg_rndup_inv; // no rounding increment
input div_frac_add_52_inv; // div_frac_add bit[52] inverted
input div_exp_out_load; // load enable to div_exp_out
input fdiv_clken_l; // div pipe clk enable - asserted low
input rclk; // global clock
output [12:0] div_exp1; // divide exponent- intermediate value
output div_expadd2_12; // divide exponent- 2nd adder output
output [12:0] div_exp_out; // divide exponent output
output [10:0] div_exp_outa; // divide exponent output- buffered copy
input se; // scan_enable
input si; // scan in
output so; // scan out
wire [10:0] div_exp_in1;
wire [10:0] div_exp_in2;
wire [12:0] div_expadd1_in1;
wire [12:0] div_expadd1_in2;
wire [12:0] div_expadd1;
wire [12:0] div_exp1_in;
wire [12:0] div_exp1;
wire [12:0] div_expadd2_in1;
wire [12:0] div_expadd2_in2;
wire [12:0] div_expadd2;
wire div_expadd2_12;
wire [12:0] div_exp_out_in;
wire [12:0] div_exp_out;
wire [10:0] div_exp_outa;
wire se_l;
assign se_l = ~se;
clken_buf ckbuf_div_exp_dp (
.clk(clk),
.rclk(rclk),
.enb_l(fdiv_clken_l),
.tmb_l(se_l)
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide exponent inputs.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(11) i_div_exp_in1 (
.din (inq_in1[62:52]),
.en (d1stg_step),
.clk (clk),
.q (div_exp_in1[10:0]),
.se (se),
.si (),
.so ()
);
dffe #(11) i_div_exp_in2 (
.din (inq_in2[62:52]),
.en (d1stg_step),
.clk (clk),
.q (div_exp_in2[10:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide exponent adder in the front end of the divide pipe.
//
///////////////////////////////////////////////////////////////////////////////
assign div_expadd1_in1[12:0]= ({13{d234stg_fdiv}}
& div_exp1[12:0])
| ({13{div_expadd1_in1_dbl}}
& {2'b0, div_exp_in1[10:0]})
| ({13{div_expadd1_in1_sng}}
& {5'b0, div_exp_in1[10:3]});
assign div_expadd1_in2[12:0]= ({13{div_expadd1_in1_dbl}}
& 13'h0436)
| ({13{div_expadd1_in1_sng}}
& 13'h0099)
| ({13{div_expadd1_in2_exp_in2_dbl}}
& (~{2'b0, div_exp_in2[10:0]}))
| ({13{div_expadd1_in2_exp_in2_sng}}
& (~{5'b0, div_exp_in2[10:3]}))
| ({13{d3stg_fdiv}}
& (~{7'b0, div_shl_cnt[5:0]}))
| ({13{d4stg_fdiv}}
& {7'b0, div_shl_cnt[5:0]});
assign div_expadd1[12:0]= (div_expadd1_in1[12:0]
+ div_expadd1_in2[12:0]);
assign div_exp1_in[12:0]= ({13{div_exp1_expadd1}}
& div_expadd1[12:0])
| ({13{div_exp1_0835}}
& 13'h0835)
| ({13{div_exp1_0118}}
& 13'h0118)
| ({13{div_exp1_zero}}
& 13'h0000);
dffe #(13) i_div_exp1 (
.din (div_exp1_in[12:0]),
.en (div_exp1_load),
.clk (clk),
.q (div_exp1[12:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide exponent adder in the back end of the divide pipe.
//
///////////////////////////////////////////////////////////////////////////////
assign div_expadd2_in1[12:0]= ({13{div_expadd2_in1_exp_out}}
& div_exp_out[12:0])
| ({13{d5stg_fdiva}}
& div_exp1[12:0]);
assign div_expadd2_in2[12:0]= ({13{d5stg_fdiva}}
& {7'h7f, d5stg_fdivs, 1'b0, d5stg_fdivd,
d5stg_fdivs, 1'b1, d5stg_fdivs})
| ({13{d6stg_fdiv}}
& {13{div_expadd2_no_decr_inv}})
| ({13{d7stg_fdiv}}
& 13'h0000);
assign div_expadd2[12:0]= (div_expadd2_in1[12:0]
+ div_expadd2_in2[12:0]
+ {12'b0, div_expadd2_cin});
assign div_expadd2_12 = div_expadd2[12];
assign div_exp_out_in[12:0]= ({13{(div_exp_out_expadd2
&& (!(div_frac_add_52_inv
&& div_exp_out_expadd22_inv)))}}
& div_expadd2[12:0])
| ({13{div_exp_out_of}}
& {2'b00, {3{d7stg_fdivd}}, 7'h7f, d7stg_to_0_inv})
| ({13{(div_exp_out_exp_out
&& (div_frac_add_52_inv || d7stg_rndup_inv))}}
& div_exp_out[12:0]);
dffe #(13) i_div_exp_out (
.din (div_exp_out_in[12:0]),
.en (div_exp_out_load),
.clk (clk),
.q (div_exp_out[12:0]),
.se (se),
.si (),
.so ()
);
assign div_exp_outa[10:0]= div_exp_out[10:0];
endmodule
|
(** * Hoare: Hoare Logic *)
(* $Date: 2011-10-10 12:42:15 -0400 (Mon, 10 Oct 2011) $ *)
(* Alexandre Pilkiewicz suggests the following alternate type for the
decorated WHILE construct:
| DCWhile : bexp -> Assertion -> dcom -> Assertion -> dcom
This leads to a simpler rule in the VC generator, which is much
easier to explain:
| DCWhile b P' c => ((fun st => post c st /\ bassn b st) ~~> P')
/\ (P ~~> post c) (* post c is the loop invariant *)
/\ verification_conditions P' c
His full development (based on an old version of our formalized
decorated programs, unfortunately), can be found in the file
/underconstruction/PilkiewiczFormalizedDecorated.v *)
Require Export ImpList.
(** We've begun applying the mathematical tools developed in the
first part of the course to studying the theory of a small
programming language, Imp.
- We defined a type of _abstract syntax trees_ for Imp, together
with an _evaluation relation_ (a partial function on states)
that specifies the _operational semantics_ of programs.
The language we defined, though small, captures some of the key
features of full-blown languages like C, C++, and Java,
including the fundamental notion of mutable state and some
common control structures.
- We proved a number of _metatheoretic properties_ -- "meta" in
the sense that they are properties of the language as a whole,
rather than properties of particular programs in the language.
These included:
- determinacy of evaluation
- equivalence of some different ways of writing down the
definition
- guaranteed termination of certain classes of programs
- correctness (in the sense of preserving meaning) of a number
of useful program transformations
- behavioral equivalence of programs (in the optional chapter
[Equiv.v]).
If we stopped here, we would still have something useful: a set
of tools for defining and discussing programming languages and
language features that are mathematically precise, flexible, and
easy to work with, applied to a set of key properties.
All of these properties are things that language designers,
compiler writers, and users might care about knowing. Indeed,
many of them are so fundamental to our understanding of the
programming languages we deal with that we might not consciously
recognize them as "theorems." But properties that seem
intuitively obvious can sometimes be quite subtle -- or, in some
cases, actually even wrong!
We'll return to this theme later in the course when we discuss
_types_ and _type soundness_.
- We saw a couple of examples of _program verification_ -- using
the precise definition of Imp to prove formally that certain
particular programs (e.g., factorial and slow subtraction)
satisfied particular specifications of their behavior. *)
(** In this chapter, we'll take this last idea further. We'll
develop a reasoning system called _Floyd-Hoare Logic_ -- commonly,
if somewhat unfairly, shortened to just _Hoare Logic_ -- in which
each of the syntactic constructs of Imp is equipped with a single,
generic "proof rule" that can be used to reason about programs
involving this construct.
Hoare Logic originates in the 1960s, and it continues to be the
subject of intensive research right up to the present day. It
lies at the core of a huge variety of tools that are now being
used to specify and verify real software systems. *)
(* ####################################################### *)
(** * Hoare Logic *)
(** Hoare Logic offers two important things: a natural way of
writing down _specifications_ of programs, and a _compositional
proof technique_ for proving that these specifications are met --
where by "compositional" we mean that the structure of proofs
directly mirrors the structure of the programs that they are
about. *)
(* ####################################################### *)
(** ** Assertions *)
(** If we're going to talk about specifications of programs, the first
thing we'll want is a way of making _assertions_ about properties
that hold at particular points in time -- i.e., properties that
may or may not be true of a given state of the memory. *)
Definition Assertion := state -> Prop.
(** **** Exercise: 1 star (assertions) *)
(** Paraphrase the following assertions in English.
[[
fun st => asnat (st X) = 3
fun st => asnat (st X) = x
fun st => asnat (st X) <= asnat (st Y)
fun st => asnat (st X) = 3 \/ asnat (st X) <= asnat (st Y)
fun st => (asnat (st Z)) * (asnat (st Z)) <= x
/\ ~ (((S (asnat (st Z))) * (S (asnat (st Z)))) <= x)
fun st => True
fun st => False
]]
[] *)
(** This way of writing assertions is formally correct -- it
precisely captures what we mean, and it is exactly what we will
use in Coq proofs -- but it is a bit heavy to look at, for several
reasons. First, every single assertion that we ever write is
going to begin with [fun st => ]; (2) this state [st] is the only
one that we ever use to look up variables (we never need to talk
about two different states at the same time); and (3) all the
variable lookups in assertions are cluttered with [asnat] or
[aslist] coercions. When we are writing down assertions
informally, we can make some simplifications: drop the initial
[fun st =>], write just [X] instead of [st X], and elide [asnat]
and [aslist]. *)
(** Informally, instead of writing
[[
fun st => (asnat (st Z)) * (asnat (st Z)) <= x
/\ ~ ((S (asnat (st Z))) * (S (asnat (st Z))) <= x)
]]
we'll write just
[[
Z * Z <= x
/\ ~((S Z) * (S Z) <= x).
]]
*)
(* ####################################################### *)
(** ** Hoare Triples *)
(** Next, we need a way of specifying -- making claims about -- the
behavior of commands. *)
(** Since we've defined assertions as a way of making claims about the
properties of states, and since the behavior of a command is to
transform one state to another, a claim about a command takes the
following form:
- "If [c] is started in a state satisfying assertion [P], and if
[c] eventually terminates, then the final state is guaranteed
to satisfy the assertion [Q]."
Such a claim is called a _Hoare Triple_. The property [P] is
called the _precondition_ of [c]; [Q] is the _postcondition_ of
[c]. *)
(** (Traditionally, Hoare triples are written [{P} c {Q}], but single
braces are already used for other things in Coq.) *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
(** Since we'll be working a lot with Hoare triples, it's useful to
have a compact notation:
[[
{{P}} c {{Q}}.
]]
*)
Notation "{{ P }} c" := (hoare_triple P c (fun st => True)) (at level 90)
: hoare_spec_scope.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q) (at level 90, c at next level)
: hoare_spec_scope.
Open Scope hoare_spec_scope.
(** (The [hoare_spec_scope] annotation here tells Coq that this
notation is not global but is intended to be used in particular
contexts. The [Open Scope] tells Coq that this file is one such
context. The first notation -- with missing postcondition -- will
not actually be used here; it's just a placeholder for a notation
that we'll want to define later, when we discuss decorated
programs.) *)
(** **** Exercise: 1 star (triples) *)
(** Paraphrase the following Hoare triples in English.
[[
{{True}} c {{X = 5}}
{{X = x}} c {{X = x + 5)}}
{{X <= Y}} c {{Y <= X}}
{{True}} c {{False}}
{{X = x}}
c
{{Y = real_fact x}}.
{{True}}
c
{{(Z * Z) <= x /\ ~ (((S Z) * (S Z)) <= x)}}
]]
*)
(** [] *)
(** **** Exercise: 1 star (valid_triples) *)
(** Which of the following Hoare triples are _valid_ -- i.e., the
claimed relation between [P], [c], and [Q] is true?
[[
{{True}} X ::= 5 {{X = 5}}
{{X = 2}} X ::= X + 1 {{X = 3}}
{{True}} X ::= 5; Y ::= 0 {{X = 5}}
{{X = 2 /\ X = 3}} X ::= 5 {{X = 0}}
{{True}} SKIP {{False}}
{{False}} SKIP {{True}}
{{True}} WHILE True DO SKIP END {{False}}
{{X = 0}}
WHILE X == 0 DO X ::= X + 1 END
{{X = 1}}
{{X = 1}}
WHILE X <> 0 DO X ::= X + 1 END
{{X = 100}}
]]
*)
(** (Note that we're using informal mathematical notations for
expressions inside of commands, for readability. We'll continue
doing so throughout the chapter.) *)
(** [] *)
(** To get us warmed up, here are two simple facts about Hoare
triples. *)
Theorem hoare_post_true : forall (P Q : Assertion) c,
(forall st, Q st) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
apply H. Qed.
Theorem hoare_pre_false : forall (P Q : Assertion) c,
(forall st, ~(P st)) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
unfold not in H. apply H in HP.
inversion HP. Qed.
(* ####################################################### *)
(** ** Weakest Preconditions *)
(** Some Hoare triples are more interesting than others. For example,
[[
{{ False }} X ::= Y + 1 {{ X <= 5 }}
]]
is _not_ very interesting: it is perfectly valid, but it tells us
nothing useful. Since the precondition isn't satisfied by any
state, it doesn't describe any situations where we can use the
command [X ::= Y + 1] to achieve the postcondition [X <= 5].
By contrast,
[[
{{ Y <= 4 /\ Z = 0 }} X ::= Y + 1 {{ X <= 5 }}
]]
is useful: it tells us that, if we can somehow create a situation
in which we know that [Y <= 4 /\ Z = 0], then running this command
will produce a state satisfying the postcondition. However, this
triple is still not as useful as it could be, because the [Z = 0]
clause in the precondition actually has nothing to do with the
postcondition [X <= 5]. The _most_ useful triple (with the same
command and postcondition) is this one:
[[
{{ Y <= 4 }} X ::= Y + 1 {{ X <= 5 }}
]]
In other words, [Y <= 4] is the _weakest_ valid precondition of
the command [X ::= Y + 1] for the postcondition [X <= 5]. *)
(** In general, we say that "[P] is the weakest precondition of
[c] for [Q]" if
- [{{P}} c {{Q}}], and
- whenever [P'] is an assertion such that [{{P'}} c {{Q}}], we
have [P' st] implies [P st] for all states [st]. *)
(** That is, [P] is the weakest precondition of [c] for [Q]
if (a) [P] _is_ a precondition for [Q] and [c], and (b) [P] is the
_weakest_ (easiest to satisfy) assertion that guarantees [Q] after
[c]. *)
(** **** Exercise: 1 star (wp) *)
(** What are the weakest preconditions of the following commands
for the following postconditions?
[[
{{ ? }} SKIP {{ X = 5 }}
{{ ? }} X ::= Y + Z {{ X = 5 }}
{{ ? }} X ::= Y {{ X = Y }}
{{ ? }}
IFB X == 0 THEN Y ::= Z + 1 ELSE Y ::= W + 2 FI
{{ Y = 5 }}
{{ ? }}
X ::= 5
{{ X = 0 }}
{{ ? }}
WHILE True DO X ::= 0 END
{{ X = 0 }}
]]
*)
(** [] *)
(* ####################################################### *)
(** ** Proof Rules *)
(** The goal of Hoare logic is to provide a _compositional_
method for proving the validity of Hoare triples. That is, the
structure of a program's correctness proof should mirror the
structure of the program itself. To this end, in the sections
below, we'll introduce one rule for reasoning about each of the
different syntactic forms of commands in Imp -- one for
assignment, one for sequencing, one for conditionals, etc. -- plus
a couple of "structural" rules that are useful for gluing things
together. *)
(* ####################################################### *)
(** *** Assignment *)
(** The rule for assignment is the most fundamental of the Hoare logic
proof rules. Here's how it works.
Consider this (valid) Hoare triple:
[[
{{ Y = 1 }} X ::= Y {{ X = 1 }}
]]
In English: if we start out in a state where the value of [Y]
is [1] and we assign [Y] to [X], then we'll finish in a
state where [X] is [1]. That is, the property of being equal
to [1] gets transferred from [Y] to [X].
Similarly, in
[[
{{ Y + Z = 1 }} X ::= Y + Z {{ X = 1 }}
]]
the same property (being equal to one) gets transferred to
[X] from the expression [Y + Z] on the right-hand side of
the assignment.
More generally, if [a] is _any_ arithmetic expression, then
[[
{{ a = 1 }} X ::= a {{ X = 1 }}
]]
is a valid Hoare triple.
Even more generally, [a] is _any_ arithmetic expression and [Q] is
_any_ property of numbers, then
[[
{{ Q(a) }} X ::= a {{ Q(X) }}
]]
is a valid Hoare triple.
Rephrasing this a bit gives us the general Hoare rule for
assignment:
[[
{{ Q where a is substituted for X }} X ::= a {{ Q }}
]]
For example, these are valid applications of the assignment
rule:
[[
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 3 = 3 }} X ::= 3 {{ X = 3 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
]]
*)
(** We could try to formalize the assignment rule directly in Coq by
treating [Q] as a family of assertions indexed by arithmetic
expressions -- something like this:
[[
Theorem hoare_asgn_firsttry :
forall (Q : aexp -> Assertion) V a,
{{fun st => Q a st}} (V ::= a) {{fun st => Q (AId V) st}}.
]]
But this formulation is not very nice, for two reasons.
First, it is not quite true! (As a counterexample, consider
a [Q] that inspects the _syntax_ of its argument, such as
[[
Definition Q (a:aexp) : Prop :=
match a with
| AID (Id 0) => fun st => False
| _ => fun st => True
end.
]]
together with any [V = Id 0] because a precondition that reduces
to [True] leads to a postcondition that is [False].) And second,
even if we could prove something similar to this, it would be
awkward to use. *)
(** A much smoother way of formalizing the rule arises from the
following observation:
- "[Q] where a is substituted for [X]" holds in a state [st] iff
[Q] holds in the state [update st X (aeval st a)]. *)
(** That is, asserting that a substituted variant of [Q] holds in
some state is the same as asserting that [Q] itself holds in
a substituted variant of the state. *)
(** Here is the definition of substitution in a state: *)
Definition assn_sub V a Q : Assertion :=
fun (st : state) =>
Q (update st V (aeval st a)).
(** This gives us the formal proof rule for assignment:
[[[
------------------------------ (hoare_asgn)
{{assn_sub V a Q}} V::=a {{Q}}
]]]
*)
Theorem hoare_asgn : forall Q V a,
{{assn_sub V a Q}} (V ::= a) {{Q}}.
Proof.
unfold hoare_triple.
intros Q V a st st' HE HQ.
inversion HE. subst.
unfold assn_sub in HQ. assumption. Qed.
(** Here's a first formal proof using this rule. *)
Example assn_sub_example :
{{fun st => 3 = 3}}
(X ::= (ANum 3))
{{fun st => asnat (st X) = 3}}.
Proof.
assert ((fun st => 3 = 3) =
(assn_sub X (ANum 3) (fun st => asnat (st X) = 3))).
Case "Proof of assertion".
unfold assn_sub. reflexivity.
rewrite -> H. apply hoare_asgn. Qed.
(** This proof is a little clunky because the [hoare_asgn] rule
doesn't literally apply to the initial goal: it only works with
triples whose precondition has precisely the form [assn_sub Q V a]
for some [Q], [V], and [a]. So we have to start with asserting a
little lemma to get the goal into this form.
Doing this kind of fiddling with the goal state every time we
want to use [hoare_asgn] would get tiresome pretty quickly.
Fortunately, there are easier alternatives. One simple one is
to state a slightly more general theorem that introduces an
explicit equality hypothesis: *)
Theorem hoare_asgn_eq : forall Q Q' V a,
Q' = assn_sub V a Q ->
{{Q'}} (V ::= a) {{Q}}.
Proof.
intros Q Q' V a H. rewrite H. apply hoare_asgn. Qed.
(** With this version of [hoare_asgn], we can do the proof much
more smoothly. *)
Example assn_sub_example' :
{{fun st => 3 = 3}}
(X ::= (ANum 3))
{{fun st => asnat (st X) = 3}}.
Proof.
apply hoare_asgn_eq. reflexivity. Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples) *)
(** Translate these informal Hoare triples...
[[
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
]]
...into formal statements and use [hoare_asgn_eq] to prove
them. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (hoarestate2) *)
(** The assignment rule looks backward to almost everyone the first
time they see it. If it still seems backward to you, it may help
to think a little about alternative "forward" rules. Here is a
seemingly natural one:
[[
{{ True }} X ::= a {{ X = a }}
]]
Explain what is wrong with this rule.
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 3 stars, optional (hoare_asgn_weakest) *)
(** Show that the precondition in the rule [hoare_asgn] is in fact the
weakest precondition. *)
Theorem hoare_asgn_weakest : forall P V a Q,
{{P}} (V ::= a) {{Q}} ->
forall st, P st -> assn_sub V a Q st.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** *** Consequence *)
(** The discussion above about the awkwardness of applying the
assignment rule illustrates a more general point: sometimes the
preconditions and postconditions we get from the Hoare rules won't
quite be the ones we want -- they may (as in the above example) be
logically equivalent but have a different syntactic form that
fails to unify with the goal we are trying to prove, or they
actually may be logically weaker (for preconditions) or
stronger (for postconditions) than what we need.
For instance, while
[[
{{3 = 3}} X ::= 3 {{X = 3}},
]]
follows directly from the assignment rule, the more natural triple
[[
{{True}} X ::= 3 {{X = 3}}.
]]
does not. This triple is also valid, but it is not an instance of
[hoare_asgn] (or [hoare_asgn_eq]) because [True] and [3 = 3] are
not syntactically equal assertions.
In general, if we can derive [{{P}} c {{Q}}], it is valid to
change [P] to [P'] as long as [P'] is strong enough to imply [P],
and change [Q] to [Q'] as long as [Q] implies [Q'].
This observation is captured by the following _Rule of
Consequence_.
[[[
{{P'}} c {{Q'}}
P implies P' (in every state)
Q' implies Q (in every state)
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
]]]
For convenience, we can state two more consequence rules -- one for
situations where we want to just strengthen the precondition, and
one for when we want to just weaken the postcondition.
[[[
{{P'}} c {{Q}}
P implies P' (in every state)
----------------------------- (hoare_consequence_pre)
{{P}} c {{Q}}
{{P}} c {{Q'}}
Q' implies Q (in every state)
----------------------------- (hoare_consequence_post)
{{P}} c {{Q}}
]]]
*)
(** Here are the formal versions: *)
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
(forall st, P st -> P' st) ->
(forall st, Q' st -> Q st) ->
{{P}} c {{Q}}.
Proof.
intros P P' Q Q' c Hht HPP' HQ'Q.
intros st st' Hc HP.
apply HQ'Q. apply (Hht st st'). assumption.
apply HPP'. assumption. Qed.
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
(forall st, P st -> P' st) ->
{{P}} c {{Q}}.
Proof.
intros P P' Q c Hhoare Himp.
apply hoare_consequence with (P' := P') (Q' := Q);
try assumption.
intros st H. apply H. Qed.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
(forall st, Q' st -> Q st) ->
{{P}} c {{Q}}.
Proof.
intros P Q Q' c Hhoare Himp.
apply hoare_consequence with (P' := P) (Q' := Q');
try assumption.
intros st H. apply H. Qed.
(** For example, we might use (the "[_pre]" version of) the
consequence rule like this:
[[
{{ True }} =>
{{ 1 = 1 }}
X ::= 1
{{ X = 1 }}
]]
Or, formally...
*)
Example hoare_asgn_example1 :
{{fun st => True}} (X ::= (ANum 1)) {{fun st => asnat (st X) = 1}}.
Proof.
apply hoare_consequence_pre with (P' := (fun st => 1 = 1)).
apply hoare_asgn_eq. reflexivity.
intros st H. reflexivity. Qed.
(* ####################################################### *)
(** *** Digression: The [eapply] Tactic *)
(** This is a good moment to introduce another convenient feature
of Coq. Having to write [P'] explicitly in the example above
is a bit annoying because the very next thing we are going to
do -- applying the [hoare_asgn] rule -- is going to determine
exactly what it should be. We can use [eapply] instead of
[apply] to tell Coq, essentially, "The missing part is going
to be filled in later." *)
Example hoare_asgn_example1' :
{{fun st => True}}
(X ::= (ANum 1))
{{fun st => asnat (st X) = 1}}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn_eq. reflexivity. (* or just [apply hoare_asgn.] *)
intros st H. reflexivity. Qed.
(** In general, [eapply H] tactic works just like [apply H]
except that, instead of failing if unifying the goal with the
conclusion of [H] does not determine how to instantiate all
of the variables appearing in the premises of [H], [eapply H]
will replace these variables with _existential variables_
(written [?nnn]) as placeholders for expressions that will be
determined (by further unification) later in the proof.
There is also an [eassumption] tactic that works similarly. *)
(* ####################################################### *)
(** *** Skip *)
(** Since [SKIP] doesn't change the state, it preserves any
property P:
[[[
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
]]]
*)
Theorem hoare_skip : forall P,
{{P}} SKIP {{P}}.
Proof.
intros P st st' H HP. inversion H. subst.
assumption. Qed.
(* ####################################################### *)
(** *** Sequencing *)
(** More interestingly, if the command [c1] takes any state where
[P] holds to a state where [Q] holds, and if [c2] takes any
state where [Q] holds to one where [R] holds, then doing [c1]
followed by [c2] will take any state where [P] holds to one
where [R] holds:
[[[
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;c2 {{ R }}
]]]
*)
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1;c2 {{R}}.
Proof.
intros P Q R c1 c2 H1 H2 st st' H12 Pre.
inversion H12; subst.
apply (H1 st'0 st'); try assumption.
apply (H2 st st'0); try assumption. Qed.
(** Note that, in the formal rule [hoare_seq], the premises are
given in "backwards" order ([c2] before [c1]). This matches the
natural flow of information in many of the situations where we'll
use the rule. *)
(** Informally, a nice way of recording a proof using this rule
is as a "decorated program" where the intermediate assertion
[Q] is written between [c1] and [c2]:
[[
{{ a = n }}
X ::= a;
{{ X = n }} <---- decoration for Q
SKIP
{{ X = n }}
]]
*)
Example hoare_asgn_example3 : forall a n,
{{fun st => aeval st a = n}}
(X ::= a; SKIP)
{{fun st => st X = n}}.
Proof.
intros a n. eapply hoare_seq.
Case "right part of seq".
apply hoare_skip.
Case "left part of seq".
eapply hoare_consequence_pre. apply hoare_asgn.
intros st H. subst. reflexivity. Qed.
(** **** Exercise: 2 stars (hoare_asgn_example4) *)
(** Translate this decorated program into a formal proof:
[[
{{ True }} =>
{{ 1 = 1 }}
X ::= 1;
{{ X = 1 }} =>
{{ X = 1 /\ 2 = 2 }}
Y ::= 2
{{ X = 1 /\ Y = 2 }}
]]
*)
Example hoare_asgn_example4 :
{{fun st => True}} (X ::= (ANum 1); Y ::= (ANum 2))
{{fun st => asnat (st X) = 1 /\ asnat (st Y) = 2}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (swap_exercise) *)
(** Write an Imp program [c] that swaps the values of [X] and [Y]
and show (in Coq) that it satisfies the following
specification:
[[
{{X <= Y}} c {{Y <= X}}
]]
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (hoarestate1) *)
(** Explain why the following proposition can't be proven:
[[
forall (a : aexp) (n : nat),
{{fun st => aeval st a = n}} (X ::= (ANum 3); Y ::= a)
{{fun st => asnat (st Y) = n}}.
]]
*)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** *** Conditionals *)
(** What sort of rule do we want for reasoning about conditional
commands? Certainly, if the same assertion [Q] holds after
executing either branch, then it holds after the whole
conditional. So we might be tempted to write:
[[[
{{P}} c1 {{Q}}
{{P}} c2 {{Q}}
--------------------------------
{{P}} IFB b THEN c1 ELSE c2 {{Q}}
]]]
However, this is rather weak. For example, using this rule,
we cannot show that:
[[
{{True}}
IFB X == 0
THEN Y ::= 2
ELSE Y ::= X + 1
FI
{{ X <= Y }}
]]
since the rule tells us nothing about the state in which the
assignments take place in the "then" and "else" branches.
But, actually, we can say something more precise. In the "then"
branch, we know that the boolean expression [b] evaluates to
[true], and in the "else" branch, we know it evaluates to [false].
Making this information available in the premises of the lemma
gives us more information to work with when reasoning about the
behavior of [c1] and [c2] (i.e., the reasons why they establish the
postcondtion [Q]).
[[[
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
]]]
*)
(** To interpret this rule formally, we need to do a little work.
Strictly speaking, the assertion we've written, [P /\ b], is the
conjunction of an assertion and a boolean expression, which
doesn't typecheck. To fix this, we need a way of formally
"lifting" any bexp [b] to an assertion. We'll write [bassn b] for
the assertion "the boolean expression [b] evaluates to [true] (in
the given state)." *)
Definition bassn b : Assertion :=
fun st => (beval st b = true).
(** A couple of useful facts about [bassn]: *)
Lemma bexp_eval_true : forall b st,
beval st b = true -> (bassn b) st.
Proof.
intros b st Hbe.
unfold bassn. assumption. Qed.
Lemma bexp_eval_false : forall b st,
beval st b = false -> ~ ((bassn b) st).
Proof.
intros b st Hbe contra.
unfold bassn in contra.
rewrite -> contra in Hbe. inversion Hbe. Qed.
(** Now we can formalize the Hoare proof rule for conditionals
and prove it correct. *)
Theorem hoare_if : forall P Q b c1 c2,
{{fun st => P st /\ bassn b st}} c1 {{Q}} ->
{{fun st => P st /\ ~(bassn b st)}} c2 {{Q}} ->
{{P}} (IFB b THEN c1 ELSE c2 FI) {{Q}}.
Proof.
intros P Q b c1 c2 HTrue HFalse st st' HE HP.
inversion HE; subst.
Case "b is true".
apply (HTrue st st').
assumption.
split. assumption.
apply bexp_eval_true. assumption.
Case "b is false".
apply (HFalse st st').
assumption.
split. assumption.
apply bexp_eval_false. assumption. Qed.
(** Here is a formal proof that the program we used to motivate the
rule satisfies the specification we gave. *)
Example if_example :
{{fun st => True}}
IFB (BEq (AId X) (ANum 0))
THEN (Y ::= (ANum 2))
ELSE (Y ::= APlus (AId X) (ANum 1))
FI
{{fun st => asnat (st X) <= asnat (st Y)}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_if.
Case "Then".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, update. simpl. intros.
inversion H.
symmetry in H1; apply beq_nat_eq in H1.
rewrite H1. omega.
Case "Else".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assn_sub, update; simpl; intros. omega.
Qed.
(* ####################################################### *)
(** *** Loops *)
(** Finally, we need a rule for reasoning about while loops. Suppose
we have a loop
[[
WHILE b DO c END
]]
and we want to find a pre-condition [P] and a post-condition
[Q] such that
[[
{{P}} WHILE b DO c END {{Q}}
]]
is a valid triple.
First of all, let's think about the case where [b] is false
at the beginning, so that the loop body never executes at
all. In this case, the loop behaves like [SKIP], so we might
be tempted to write
[[
{{P}} WHILE b DO c END {{P}}.
]]
But, as we remarked above for the conditional, we know a
little more at the end -- not just [P], but also the fact
that [b] is false in the current state. So we can enrich the
postcondition a little:
[[
{{P}} WHILE b DO c END {{P /\ ~b}}
]]
What about the case where the loop body _does_ get executed?
In order to ensure that [P] holds when the loop finally
exits, we certainly need to make sure that the command [c]
guarantees that [P] holds whenever [c] is finished.
Moreover, since [P] holds at the beginning of the first
execution of [c], and since each execution of [c]
re-establishes [P] when it finishes, we can always assume
that [P] holds at the beginning of [c]. This leads us to the
following rule:
[[[
{{P}} c {{P}}
-----------------------------------
{{P}} WHILE b DO c END {{P /\ ~b}}
]]]
The proposition [P] is called an _invariant_.
This is almost the rule we want, but again it can be improved
a little: at the beginning of the loop body, we know not only
that [P] holds, but also that the guard [b] is true in the
current state. This gives us a little more information to
use in reasoning about [c]. Here is the final version of the
rule:
[[[
{{P /\ b}} c {{P}}
----------------------------------- [hoare_while]
{{P}} WHILE b DO c END {{P /\ ~b}}
]]]
*)
Lemma hoare_while : forall P b c,
{{fun st => P st /\ bassn b st}} c {{P}} ->
{{P}} WHILE b DO c END {{fun st => P st /\ ~ (bassn b st)}}.
Proof.
intros P b c Hhoare st st' He HP.
(* Like we've seen before, we need to reason by induction
on He, because, in the "keep looping" case, its hypotheses
talk about the whole loop instead of just c *)
remember (WHILE b DO c END) as wcom.
ceval_cases (induction He) Case; try (inversion Heqwcom); subst.
Case "E_WhileEnd".
split. assumption. apply bexp_eval_false. assumption.
Case "E_WhileLoop".
apply IHHe2. reflexivity.
apply (Hhoare st st'); try assumption.
split. assumption. apply bexp_eval_true. assumption. Qed.
Example while_example :
{{fun st => asnat (st X) <= 3}}
WHILE (BLe (AId X) (ANum 2))
DO X ::= APlus (AId X) (ANum 1) END
{{fun st => asnat (st X) = 3}}.
Proof.
eapply hoare_consequence_post.
apply hoare_while.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold bassn, assn_sub. intros. rewrite update_eq. simpl.
inversion H as [_ H0]. simpl in H0. apply ble_nat_true in H0.
omega.
unfold bassn. intros. inversion H as [Hle Hb]. simpl in Hb.
remember (ble_nat (asnat (st X)) 2) as le. destruct le.
apply ex_falso_quodlibet. apply Hb; reflexivity.
symmetry in Heqle. apply ble_nat_false in Heqle. omega.
Qed.
(** We can also use the while rule to prove the following Hoare
triple, which may seem surprising at first... *)
Theorem always_loop_hoare : forall P Q,
{{P}} WHILE BTrue DO SKIP END {{Q}}.
Proof.
intros P Q.
apply hoare_consequence_pre with (P' := fun st : state => True).
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
apply hoare_post_true. intros st. apply I.
Case "Loop invariant and negated guard imply postcondition".
simpl. intros st [Hinv Hguard].
apply ex_falso_quodlibet. apply Hguard. reflexivity.
Case "Precondition implies invariant".
intros st H. constructor. Qed.
(** Actually, this result shouldn't be surprising. If we look back at
the definition of [hoare_triple], we can see that it asserts
something meaningful _only_ when the command terminates. *)
Print hoare_triple.
(** If the command doesn't terminate, we can prove anything we like
about the post-condition. Here's a more direct proof of the same
fact: *)
Theorem always_loop_hoare' : forall P Q,
{{P}} WHILE BTrue DO SKIP END {{Q}}.
Proof.
unfold hoare_triple. intros P Q st st' contra.
apply loop_never_stops in contra. inversion contra.
Qed.
(** Hoare rules that only talk about terminating commands are often
said to describe a logic of "partial" correctness. It is also
possible to give Hoare rules for "total" correctness, which build
in the fact that the commands terminate. *)
(* ####################################################### *)
(** *** Exercise: Hoare Rules for [REPEAT] *)
Module RepeatExercise.
(** **** Exercise: 4 stars (hoare_repeat) *)
(** In this exercise, we'll add a new constructor to our language of
commands: [CRepeat]. You will write the evaluation rule for
[repeat] and add a new hoare logic theorem to the language for
programs involving it.
We recommend that you do this exercise before the ones that
follow, as it should help solidify your understanding of the
material. *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "CRepeat" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
(** Add new rules for [REPEAT] to [ceval] below. You can use the rules
for [WHILE] as a guide, but remember that the body of a [REPEAT]
should always execute at least once, and that the loop ends when
the guard becomes true. Then update the [ceval_cases] tactic to
handle these added cases. *)
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n V,
aeval st a1 = n ->
ceval st (V ::= a1) (update st V n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
(* FILL IN HERE *)
.
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
(* FILL IN HERE *)
].
(** A couple of definitions from above, copied here so they use the
new [ceval]. *)
Notation "c1 '/' st '||' st'" := (ceval st c1 st')
(at level 40, st at level 39).
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion)
: Prop :=
forall st st', (c / st || st') -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q) (at level 90, c at next level).
(** Now state and prove a theorem, [hoare_repeat], that expresses an
appropriate proof rule for [repeat] commands. Use [hoare_while]
as a model. *)
(* FILL IN HERE *)
End RepeatExercise.
(** [] *)
(* ####################################################### *)
(** ** Decorated Programs *)
(** The whole point of Hoare Logic is that it is compositional -- the
structure of proofs exactly follows the structure of programs.
This fact suggests that we we could record the essential ideas of
a proof informally (leaving out some low-level calculational
details) by decorating programs with appropriate assertions around
each statement. Such a _decorated program_ carries with it
an (informal) proof of its own correctness.
For example, here is a complete decorated program:
[[
{{ True }} =>
{{ x = x }}
X ::= x;
{{ X = x }} =>
{{ X = x /\ z = z }}
Z ::= z;
{{ X = x /\ Z = z }} =>
{{ Z - X = z - x }}
WHILE X <> 0 DO
{{ Z - X = z - x /\ X <> 0 }} =>
{{ (Z - 1) - (X - 1) = z - x }}
Z ::= Z - 1;
{{ Z - (X - 1) = z - x }}
X ::= X - 1
{{ Z - X = z - x }}
END;
{{ Z - X = z - x /\ ~ (X <> 0) }} =>
{{ Z = z - x }} =>
{{ Z + 1 = z - x + 1 }}
Z ::= Z + 1
{{ Z = z - x + 1 }}
]]
*)
(** Concretely, a decorated program consists of the program text
interleaved with assertions. To check that a decorated program
represents a valid proof, we check that each individual command is
_locally_ consistent with its accompanying assertions in the
following sense:
- [SKIP] is locally consistent if its precondition and
postcondition are the same
[[
{{ P }}
SKIP
{{ P }}
]]
- The sequential composition of commands [c1] and [c2] is locally
consistent (with respect to assertions [P] and [R]) if [c1]
is (with respect to [P] and [Q]) and [c2] is (with respect to
[Q] and [R]):
[[
{{ P }}
c1;
{{ Q }}
c2
{{ R }}
]]
- An assignment is locally consistent if its precondition is
the appropriate substitution of its postcondition:
[[
{{ P where a is substituted for X }}
X ::= a
{{ P }}
]]
- A conditional is locally consistent (with respect to assertions
[P] and [Q]) if the assertions at the top of its "then" and
"else" branches are exactly [P/\b] and [P/\~b] and if its "then"
branch is locally consistent (with respect to [P/\b] and [Q])
and its "else" branch is locally consistent (with respect to
[P/\~b] and [Q]):
[[
{{ P }}
IFB b THEN
{{ P /\ b }}
c1
{{ Q }}
ELSE
{{ P /\ ~b }}
c2
{{ Q }}
FI
]]
- A while loop is locally consistent if its postcondition is
[P/\~b] (where [P] is its precondition) and if the pre- and
postconditions of its body are exactly [P/\b] and [P]:
[[
{{ P }}
WHILE b DO
{{ P /\ b }}
c1
{{ P }}
END
{{ P /\ ~b }}
]]
- A pair of assertions separated by [=>] is locally consistent if
the first implies the second (in all states):
[[
{{ P }} =>
{{ P' }}
]]
*)
(* ####################################################### *)
(** * Reasoning About Programs with Hoare Logic *)
(* ####################################################### *)
(** ** Example: Slow Subtraction *)
(** Informally:
[[
{{ X = x /\ Z = z }} =>
{{ Z - X = z - x }}
WHILE X <> 0 DO
{{ Z - X = z - x /\ X <> 0 }} =>
{{ (Z - 1) - (X - 1) = z - x }}
Z ::= Z - 1;
{{ Z - (X - 1) = z - x }}
X ::= X - 1
{{ Z - X = z - x }}
END
{{ Z - X = z - x /\ ~ (X <> 0) }} =>
{{ Z = z - x }}
]]
*)
(** Formally: *)
Definition subtract_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
Z ::= AMinus (AId Z) (ANum 1);
X ::= AMinus (AId X) (ANum 1)
END.
Definition subtract_slowly_invariant x z :=
fun st => minus (asnat (st Z)) (asnat (st X)) = minus z x.
Theorem subtract_slowly_correct : forall x z,
{{fun st => asnat (st X) = x /\ asnat (st Z) = z}}
subtract_slowly
{{fun st => asnat (st Z) = minus z x}}.
Proof.
(* Note that we do NOT unfold the definition of hoare_triple
anywhere in this proof! The goal is to use only the hoare
rules. Your proofs should do the same. *)
intros x z. unfold subtract_slowly.
(* First we need to transform the pre and postconditions so
that hoare_while will apply. In particular, the
precondition should be the loop invariant. *)
eapply hoare_consequence with (P' := subtract_slowly_invariant x z).
apply hoare_while.
Case "Loop body preserves invariant".
(* Split up the two assignments with hoare_seq - using eapply
lets us solve the second one immediately with hoare_asgn *)
eapply hoare_seq. apply hoare_asgn.
(* Now for the first assignment, transform the precondition
so we can use hoare_asgn *)
eapply hoare_consequence_pre. apply hoare_asgn.
(* Finally, we need to justify the implication generated by
hoare_consequence_pre (this bit of reasoning is elided in the
informal proof) *)
unfold subtract_slowly_invariant, assn_sub, update, bassn. simpl.
intros st [Inv GuardTrue].
(* There are several ways to do the case analysis here...this
one is fairly general: *)
remember (beq_nat (asnat (st X)) 0) as Q; destruct Q.
inversion GuardTrue.
symmetry in HeqQ. apply beq_nat_false in HeqQ.
omega. (* slow but effective! *)
Case "Initial state satisfies invariant".
(* This is the subgoal generated by the precondition part of our
first use of hoare_consequence. It's the first implication
written in the decorated program (though we elided the actual
proof there). *)
unfold subtract_slowly_invariant.
intros st [HX HZ]. omega.
Case "Invariant and negated guard imply postcondition".
(* This is the subgoal generated by the postcondition part of
out first use of hoare_consequence. This implication is
the one written after the while loop in the informal proof. *)
intros st [Inv GuardFalse].
unfold subtract_slowly_invariant in Inv.
unfold bassn in GuardFalse. simpl in GuardFalse.
(* Here's a slightly different alternative for the case analysis that
works out well here (but is less general)... *)
destruct (asnat (st X)).
omega.
apply ex_falso_quodlibet. apply GuardFalse. reflexivity.
Qed.
(* ####################################################### *)
(** ** Exercise: Reduce to Zero *)
(** Here is a while loop that is so simple it needs no invariant:
[[
{{ True }}
WHILE X <> 0 DO
{{ True /\ X <> 0 }} =>
{{ True }}
X ::= X - 1
{{ True }}
END
{{ True /\ X = 0 }} =>
{{ X = 0 }}
]]
Your job is to translate this proof to Coq. It may help to look
at the [slow_subtraction] proof for ideas.
*)
(** **** Exercise: 2 stars (reduce_to_zero_correct) *)
Definition reduce_to_zero : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
X ::= AMinus (AId X) (ANum 1)
END.
Theorem reduce_to_zero_correct :
{{fun st => True}}
reduce_to_zero
{{fun st => asnat (st X) = 0}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** ** Exercise: Slow Addition *)
(** The following program adds the variable X into the variable Z
by repeatedly decrementing X and incrementing Z. *)
Definition add_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
Z ::= APlus (AId Z) (ANum 1);
X ::= AMinus (AId X) (ANum 1)
END.
(** **** Exercise: 3 stars (add_slowly_decoration) *)
(** Following the pattern of the [subtract_slowly] example above, pick
a precondition and postcondition that give an appropriate
specification of [add_slowly]; then (informally) decorate the
program accordingly. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (add_slowly_formal) *)
(** Now write down your specification of [add_slowly] formally, as a
Coq [Hoare_triple], and prove it valid. *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** ** Example: Parity *)
(** Here's another, slightly trickier example. Make sure you
understand the decorated program completely. Understanding
all the details of the Coq proof is not required, though it
is not actually very hard -- all the required ideas are
already in the informal version. *)
(**
[[
{{ X = x }} =>
{{ X = x /\ 0 = 0 }}
Y ::= 0;
{{ X = x /\ Y = 0 }} =>
{{ (Y=0 <-> ev (x-X)) /\ X<=x }}
WHILE X <> 0 DO
{{ (Y=0 <-> ev (x-X)) /\ X<=x /\ X<>0 }} =>
{{ (1-Y)=0 <-> ev (x-(X-1)) /\ X-1<=x }}
Y ::= 1 - Y;
{{ Y=0 <-> ev (x-(X-1)) /\ X-1<=x }}
X ::= X - 1
{{ Y=0 <-> ev (x-X) /\ X<=x }}
END
{{ (Y=0 <-> ev (x-X)) /\ X<=x /\ ~(X<>0) }} =>
{{ Y=0 <-> ev x }}
]]
*)
Definition find_parity : com :=
Y ::= (ANum 0);
WHILE (BNot (BEq (AId X) (ANum 0))) DO
Y ::= AMinus (ANum 1) (AId Y);
X ::= AMinus (AId X) (ANum 1)
END.
Definition find_parity_invariant x :=
fun st =>
asnat (st X) <= x
/\ (asnat (st Y) = 0 /\ ev (x - asnat (st X)) \/ asnat (st Y) = 1 /\ ~ev (x - asnat (st X))).
(* It turns out that we'll need the following lemma... *)
Lemma not_ev_ev_S_gen: forall n,
(~ ev n -> ev (S n)) /\
(~ ev (S n) -> ev (S (S n))).
Proof.
induction n as [| n'].
Case "n = 0".
split; intros H.
SCase "->".
apply ex_falso_quodlibet. apply H. apply ev_0.
SCase "<-".
apply ev_SS. apply ev_0.
Case "n = S n'".
inversion IHn' as [Hn HSn]. split; intros H.
SCase "->".
apply HSn. apply H.
SCase "<-".
apply ev_SS. apply Hn. intros contra.
apply H. apply ev_SS. apply contra. Qed.
Lemma not_ev_ev_S : forall n,
~ ev n -> ev (S n).
Proof.
intros n.
destruct (not_ev_ev_S_gen n) as [H _].
apply H.
Qed.
Theorem find_parity_correct : forall x,
{{fun st => asnat (st X) = x}}
find_parity
{{fun st => asnat (st Y) = 0 <-> ev x}}.
Proof.
intros x. unfold find_parity.
apply hoare_seq with (Q := find_parity_invariant x).
eapply hoare_consequence.
apply hoare_while with (P := find_parity_invariant x).
Case "Loop body preserves invariant".
eapply hoare_seq.
apply hoare_asgn.
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st [[Inv1 Inv2] GuardTrue].
unfold find_parity_invariant, bassn, assn_sub, aeval in *.
rewrite update_eq.
rewrite (update_neq Y X); auto.
rewrite (update_neq X Y); auto.
rewrite update_eq.
simpl in GuardTrue. destruct (asnat (st X)).
inversion GuardTrue. simpl.
split. omega.
inversion Inv2 as [[H1 H2] | [H1 H2]]; rewrite H1;
[right|left]; (split; simpl; [omega |]).
apply ev_not_ev_S in H2.
replace (S (x - S n)) with (x-n) in H2 by omega.
rewrite <- minus_n_O. assumption.
apply not_ev_ev_S in H2.
replace (S (x - S n)) with (x - n) in H2 by omega.
rewrite <- minus_n_O. assumption.
Case "Precondition implies invariant".
intros st H. assumption.
Case "Invariant implies postcondition".
unfold bassn, find_parity_invariant. simpl.
intros st [[Inv1 Inv2] GuardFalse].
destruct (asnat (st X)).
split; intro.
inversion Inv2.
inversion H0 as [_ H1]. replace (x-0) with x in H1 by omega.
assumption.
inversion H0 as [H0' _]. rewrite H in H0'. inversion H0'.
inversion Inv2.
inversion H0. assumption.
inversion H0 as [_ H1]. replace (x-0) with x in H1 by omega.
apply ex_falso_quodlibet. apply H1. assumption.
apply ex_falso_quodlibet. apply GuardFalse. reflexivity.
Case "invariant established before loop".
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st H.
unfold assn_sub, find_parity_invariant, update. simpl.
subst.
split.
omega.
replace (asnat (st X) - asnat (st X)) with 0 by omega.
left. split. reflexivity.
apply ev_0. Qed.
(** **** Exercise: 3 stars (wrong_find_parity_invariant) *)
(** A plausible first attempt at stating an invariant for [find_parity]
is the following. *)
Definition find_parity_invariant' x :=
fun st =>
(asnat (st Y)) = 0 <-> ev (x - asnat (st X)).
(** Why doesn't this work? (Hint: Don't waste time trying to answer
this exercise by attempting a formal proof and seeing where it
goes wrong. Just think about whether the loop body actually
preserves the property.) *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** ** Example: Finding Square Roots *)
Definition sqrt_loop : com :=
WHILE BLe (AMult (APlus (ANum 1) (AId Z))
(APlus (ANum 1) (AId Z)))
(AId X) DO
Z ::= APlus (ANum 1) (AId Z)
END.
Definition sqrt_com : com :=
Z ::= ANum 0;
sqrt_loop.
Definition sqrt_spec (x : nat) : Assertion :=
fun st =>
((asnat (st Z)) * (asnat (st Z))) <= x
/\ ~ (((S (asnat (st Z))) * (S (asnat (st Z)))) <= x).
Definition sqrt_inv (x : nat) : Assertion :=
fun st =>
asnat (st X) = x
/\ ((asnat (st Z)) * (asnat (st Z))) <= x.
Theorem random_fact_1 : forall st,
(S (asnat (st Z))) * (S (asnat (st Z))) <= asnat (st X) ->
bassn (BLe (AMult (APlus (ANum 1) (AId Z))
(APlus (ANum 1) (AId Z)))
(AId X)) st.
Proof.
intros st Hle. unfold bassn. simpl.
destruct (asnat (st X)) as [|x'].
Case "asnat (st X) = 0".
inversion Hle.
Case "asnat (st X) = S x'".
simpl in Hle. apply le_S_n in Hle.
remember (ble_nat (plus (asnat (st Z))
((asnat (st Z)) * (S (asnat (st Z))))) x')
as ble.
destruct ble. reflexivity.
symmetry in Heqble. apply ble_nat_false in Heqble.
unfold not in Heqble. apply Heqble in Hle. inversion Hle.
Qed.
Theorem random_fact_2 : forall st,
bassn (BLe (AMult (APlus (ANum 1) (AId Z))
(APlus (ANum 1) (AId Z)))
(AId X)) st ->
asnat (aeval st (APlus (ANum 1) (AId Z)))
* asnat (aeval st (APlus (ANum 1) (AId Z)))
<= asnat (st X).
Proof.
intros st Hble. unfold bassn in Hble. simpl in *.
destruct (asnat (st X)) as [| x'].
Case "asnat (st X) = 0".
inversion Hble.
Case "asnat (st X) = S x'".
apply ble_nat_true in Hble. omega. Qed.
Theorem sqrt_com_correct : forall x,
{{fun st => True}} (X ::= ANum x; sqrt_com) {{sqrt_spec x}}.
Proof.
intros x.
apply hoare_seq with (Q := fun st => asnat (st X) = x).
Case "sqrt_com".
unfold sqrt_com.
apply hoare_seq with (Q := fun st => asnat (st X) = x
/\ asnat (st Z) = 0).
SCase "sqrt_loop".
unfold sqrt_loop.
eapply hoare_consequence.
apply hoare_while with (P := sqrt_inv x).
SSCase "loop preserves invariant".
eapply hoare_consequence_pre.
apply hoare_asgn. intros st H.
unfold assn_sub. unfold sqrt_inv in *.
inversion H as [[HX HZ] HP]. split.
SSSCase "X is preserved".
rewrite update_neq; auto.
SSSCase "Z is updated correctly".
rewrite (update_eq (aeval st (APlus (ANum 1) (AId Z))) Z st).
subst. apply random_fact_2. assumption.
SSCase "invariant is true initially".
intros st H. inversion H as [HX HZ].
unfold sqrt_inv. split. assumption.
rewrite HZ. simpl. omega.
SSCase "after loop, spec is satisfied".
intros st H. unfold sqrt_spec.
inversion H as [HX HP].
unfold sqrt_inv in HX. inversion HX as [HX' Harith].
split. assumption.
intros contra. apply HP. clear HP.
simpl. simpl in contra.
apply random_fact_1. subst x. assumption.
SCase "Z set to 0".
eapply hoare_consequence_pre. apply hoare_asgn.
intros st HX.
unfold assn_sub. split.
rewrite update_neq; auto.
rewrite update_eq; auto.
Case "assignment of X".
eapply hoare_consequence_pre. apply hoare_asgn.
intros st H.
unfold assn_sub. rewrite update_eq; auto. Qed.
(** **** Exercise: 3 stars, optional (sqrt_informal) *)
(** Write a decorated program corresponding to the above
correctness proof. *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Factorial *)
Module Factorial.
Fixpoint real_fact (n:nat) : nat :=
match n with
| O => 1
| S n' => n * (real_fact n')
end.
(** Recall the factorial Imp program: *)
Definition fact_body : com :=
Y ::= AMult (AId Y) (AId Z);
Z ::= AMinus (AId Z) (ANum 1).
Definition fact_loop : com :=
WHILE BNot (BEq (AId Z) (ANum 0)) DO
fact_body
END.
Definition fact_com : com :=
Z ::= (AId X);
Y ::= ANum 1;
fact_loop.
(** **** Exercise: 3 stars, optional (fact_informal) *)
(** Decorate the [fact_com] program to show that it satisfies the
specification given by the pre and postconditions below. Just as
we have done above, you may elide the algebraic reasoning about
arithmetic, the less-than relation, etc., that is (formally)
required by the rule of consequence:
(* FILL IN HERE *)
[[
{{ X = x }}
Z ::= X;
Y ::= 1;
WHILE Z <> 0 DO
Y ::= Y * Z;
Z ::= Z - 1
END
{{ Y = real_fact x }}
]]
*)
(** [] *)
(** **** Exercise: 4 stars, optional (fact_formal) *)
(** Prove formally that fact_com satisfies this specification,
using your informal proof as a guide. You may want to state
the loop invariant separately (as we did in the examples). *)
Theorem fact_com_correct : forall x,
{{fun st => asnat (st X) = x}} fact_com
{{fun st => asnat (st Y) = real_fact x}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Factorial.
(* ####################################################### *)
(** ** Reasoning About Programs with Lists *)
(** **** Exercise: 3 stars (list_sum) *)
(** Here is a direct definition of the sum of the elements of a list,
and an Imp program that computes the sum. *)
Definition sum l := fold_right plus 0 l.
Definition sum_program :=
Y ::= ANum 0;
WHILE (BIsCons (AId X)) DO
Y ::= APlus (AId Y) (AHead (AId X)) ;
X ::= ATail (AId X)
END.
(** Provide an _informal_ proof of the following specification of
[sum_program] in the form of a decorated version of the
program. *)
Definition sum_program_spec := forall l,
{{ fun st => aslist (st X) = l }}
sum_program
{{ fun st => asnat (st Y) = sum l }}.
(* FILL IN HERE *)
(** [] **)
(** Next, let's look at a _formal_ Hoare Logic proof for a program
that deals with lists. We will verify the following program,
which checks if the number [Y] occurs in the list [X], and if so sets
[Z] to [1].
*)
Definition list_member :=
WHILE BIsCons (AId X) DO
IFB (BEq (AId Y) (AHead (AId X))) THEN
Z ::= (ANum 1)
ELSE
SKIP
FI;
X ::= ATail (AId X)
END.
Definition list_member_spec := forall l n,
{{ fun st => st X = VList l /\ st Y = VNat n /\ st Z = VNat 0 }}
list_member
{{ fun st => st Z = VNat 1 <-> appears_in n l }}.
(** The proof we will use, written informally, looks as follows:
[[
{{ X = l /\ Y = n /\ Z = 0 }} =>
{{ Y = n /\ exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p) }}
WHILE (BIsCons X)
DO
{{ Y = n /\ (exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p))
/\ (BIsCons X) }}
IFB (Y == head X) THEN
{{ Y = n
/\ (exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p))
/\ (BIsCons X)
/\ Y == AHead X }} =>
{{ Y = n /\ (exists p, p ++ tail X = l
/\ (1 = 1 <-> appears_in n p)) }}
Z ::= 1
{{ Y = n /\ (exists p, p ++ tail X = l
/\ (Z = 1 <-> appears_in n p)) }}
ELSE
{{ Y = n
/\ (exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p))
/\ (BIsCons X)
/\ ~ (Y == head X) }} =>
{{ Y = n
/\ (exists p, p ++ tail X = l /\ (Z = 1 <-> appears_in n p)) }}
SKIP
{{ Y = n
/\ (exists p, p ++ tail X = l /\ (Z = 1 <-> appears_in n p)) }}
FI;
X ::= ATail X
{{ Y = n
/\ (exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p)) }}
END
{{ Y = n
/\ (exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p))
/\ ~ (BIsCons X) }} =>
{{ Z = 1 <-> appears_in n l }}
]]
The only interesting part of the proof is the choice of loop invariant:
[[
exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p)
]]
This states that at each iteration of the loop, the original list
[l] is equal to the append of the current value of [X] and some
other list [p] which is not the value of any variable in the
program, but keeps track of enough information from the original
state to make the proof go through. (Such a [p] is sometimes called
a "ghost variable").
In order to show that such a list [p] exists, in each iteration we
add the head of [X] to the _end_ of [p]. This needs the function
[snoc], from Poly.v. *)
Fixpoint snoc {X:Type} (l:list X) (v:X) : (list X) :=
match l with
| nil => [ v ]
| cons h t => h :: (snoc t v)
end.
Lemma snoc_equation : forall (A : Type) (h:A) (x y : list A),
snoc x h ++ y = x ++ h :: y.
Proof.
intros A h x y.
induction x.
Case "x = []". reflexivity.
Case "x = cons". simpl. rewrite IHx. reflexivity.
Qed.
(** The main proof uses various lemmas. *)
Lemma appears_in_snoc1 : forall a l,
appears_in a (snoc l a).
Proof.
induction l.
Case "l = []". apply ai_here.
Case "l = cons". simpl. apply ai_later. apply IHl.
Qed.
Lemma appears_in_snoc2 : forall a b l,
appears_in a l ->
appears_in a (snoc l b).
Proof.
induction l; intros H; inversion H; subst; simpl.
Case "l = []". apply ai_here.
Case "l = cons". apply ai_later. apply IHl. assumption.
Qed.
Lemma appears_in_snoc3 : forall a b l,
appears_in a (snoc l b) ->
(appears_in a l \/ a = b).
Proof.
induction l; intros H.
Case "l = []". inversion H.
SCase "ai_here". right. reflexivity.
SCase "ai_later". left. assumption.
Case "l = cons". inversion H; subst.
SCase "ai_here". left. apply ai_here.
SCase "ai_later". destruct (IHl H1).
left. apply ai_later. assumption.
right. assumption.
Qed.
Lemma append_singleton_equation : forall (x : nat) l l',
(l ++ [x]) ++ l' = l ++ x :: l'.
Proof.
intros x l l'.
induction l.
reflexivity.
simpl. rewrite IHl. reflexivity.
Qed.
Lemma append_nil : forall (A : Type) (l : list A),
l ++ [] = l.
Proof.
induction l.
reflexivity.
simpl. rewrite IHl. reflexivity.
Qed.
Lemma beq_true__eq : forall n n',
beq_nat n n' = true ->
n = n'.
Proof.
induction n; destruct n'.
Case "n = 0, n' = 0". reflexivity.
Case "n = 0, n' = S _". simpl. intros H. inversion H.
Case "n = S, n' = 0". simpl. intros H. inversion H.
Case "n = S, n' = S". simpl. intros H.
rewrite (IHn n' H). reflexivity.
Qed.
Lemma beq_nat_refl : forall n,
beq_nat n n = true.
Proof.
induction n.
reflexivity.
simpl. assumption.
Qed.
Theorem list_member_correct : forall l n,
{{ fun st => st X = VList l /\ st Y = VNat n /\ st Z = VNat 0 }}
list_member
{{ fun st => st Z = VNat 1 <-> appears_in n l }}.
Proof.
intros l n.
eapply hoare_consequence.
apply hoare_while with (P := fun st =>
st Y = VNat n
/\ exists p, p ++ aslist (st X) = l
/\ (st Z = VNat 1 <-> appears_in n p)).
(* The loop body preserves the invariant: *)
eapply hoare_seq.
apply hoare_asgn.
apply hoare_if.
Case "If taken".
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st [[[H1 [p [H2 H3]]] H9] H10].
unfold assn_sub. split.
(* (st Y) is still n *)
rewrite update_neq; try reflexivity.
rewrite update_neq; try reflexivity.
assumption.
(* and the interesting part of the invariant is preserved: *)
(* X has to be a cons *)
remember (aslist (st X)) as x.
destruct x as [|h x'].
unfold bassn in H9. unfold beval in H9. unfold aeval in H9.
rewrite <- Heqx in H9. inversion H9.
exists (snoc p h).
rewrite update_eq.
unfold aeval. rewrite update_neq; try reflexivity.
rewrite <- Heqx.
split.
rewrite snoc_equation. assumption.
rewrite update_neq; try reflexivity.
rewrite update_eq.
split.
simpl.
unfold bassn in H10. unfold beval in H10.
unfold aeval in H10. rewrite H1 in H10.
rewrite <- Heqx in H10. simpl in H10.
rewrite (beq_true__eq _ _ H10).
intros. apply appears_in_snoc1.
intros. reflexivity.
Case "If not taken".
eapply hoare_consequence_pre. apply hoare_skip.
unfold assn_sub.
intros st [[[H1 [p [H2 H3]]] H9] H10].
split.
(* (st Y) is still n *)
rewrite update_neq; try reflexivity.
assumption.
(* and the interesting part of the invariant is preserved: *)
(* X has to be a cons *)
remember (aslist (st X)) as x.
destruct x as [|h x'].
unfold bassn in H9. unfold beval in H9. unfold aeval in H9.
rewrite <- Heqx in H9. inversion H9.
exists (snoc p h).
split.
rewrite update_eq.
unfold aeval. rewrite <- Heqx.
rewrite snoc_equation. assumption.
rewrite update_neq; try reflexivity.
split.
intros. apply appears_in_snoc2. apply H3. assumption.
intros. destruct (appears_in_snoc3 _ _ _ H).
SCase "later".
inversion H3 as [_ H3'].
apply H3'. assumption.
SCase "here (absurd)".
subst.
unfold bassn in H10. unfold beval in H10. unfold aeval in H10.
rewrite <- Heqx in H10. rewrite H1 in H10.
simpl in H10. rewrite beq_nat_refl in H10.
apply ex_falso_quodlibet. apply H10. reflexivity.
(* The invariant holds at the start of the loop: *)
intros st [H1 [H2 H3]].
rewrite H1. rewrite H2. rewrite H3.
split.
reflexivity.
exists []. split.
reflexivity.
split; intros H; inversion H.
(* At the end of the loop the invariant implies the right thing. *)
simpl. intros st [[H1 [p [H2 H3]]] H5].
(* x must be [] *)
unfold bassn in H5. unfold beval in H5. unfold aeval in H5.
destruct (aslist (st X)) as [|h x'].
rewrite append_nil in H2.
rewrite <- H2.
assumption.
apply ex_falso_quodlibet. apply H5. reflexivity.
Qed.
(** **** Exercise: 4 stars, optional (list_reverse) *)
(** Recall the function [rev] from Poly.v, for reversing lists. *)
Fixpoint rev {X:Type} (l:list X) : list X :=
match l with
| nil => []
| cons h t => snoc (rev t) h
end.
(** Write an Imp program [list_reverse_program] that reverses
lists. Formally prove that it satisfies the following
specification:
[[
forall l : list nat,
{{ X = l /\ Y = nil }}
list_reverse_program
{{ Y = rev l }}.
]]
You may find the lemmas [append_nil] and [rev_equation] useful.
*)
Lemma rev_equation : forall (A : Type) (h : A) (x y : list A),
rev (h :: x) ++ y = rev x ++ h :: y.
Proof.
intros. simpl. apply snoc_equation.
Qed.
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** * Formalizing Decorated Programs *)
(** The informal conventions for decorated programs amount to a way of
displaying Hoare triples in which commands are annotated with
enough embedded assertions that checking the validity of the
triple is reduced to simple algebraic calculations showing that
some assertions were stronger than others.
In this section, we show that this informal presentation style can
actually be made completely formal. *)
(** ** Syntax *)
(** The first thing we need to do is to formalize a variant of the
syntax of commands that includes embedded assertions. We call the
new commands _decorated commands_, or [dcom]s. *)
Inductive dcom : Type :=
| DCSkip : Assertion -> dcom
| DCSeq : dcom -> dcom -> dcom
| DCAsgn : id -> aexp -> Assertion -> dcom
| DCIf : bexp -> Assertion -> dcom -> Assertion -> dcom -> dcom
| DCWhile : bexp -> Assertion -> dcom -> Assertion -> dcom
| DCPre : Assertion -> dcom -> dcom
| DCPost : dcom -> Assertion -> dcom.
Tactic Notation "dcom_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Skip" | Case_aux c "Seq" | Case_aux c "Asgn"
| Case_aux c "If" | Case_aux c "While"
| Case_aux c "Pre" | Case_aux c "Post" ].
Notation "'SKIP' {{ P }}"
:= (DCSkip P)
(at level 10) : dcom_scope.
Notation "l '::=' a {{ P }}"
:= (DCAsgn l a P)
(at level 60, a at next level) : dcom_scope.
Notation "'WHILE' b 'DO' {{ Pbody }} d 'END' {{ Ppost }}"
:= (DCWhile b Pbody d Ppost)
(at level 80, right associativity) : dcom_scope.
Notation "'IFB' b 'THEN' {{ P }} d 'ELSE' {{ P' }} d' 'FI'"
:= (DCIf b P d P' d')
(at level 80, right associativity) : dcom_scope.
Notation "'=>' {{ P }} d"
:= (DCPre P d)
(at level 90, right associativity) : dcom_scope.
Notation "{{ P }} d"
:= (DCPre P d)
(at level 90) : dcom_scope.
Notation "d '=>' {{ P }}"
:= (DCPost d P)
(at level 91, right associativity) : dcom_scope.
Notation " d ; d' "
:= (DCSeq d d')
(at level 80, right associativity) : dcom_scope.
Delimit Scope dcom_scope with dcom.
(** To avoid clashing with the existing [Notation] definitions
for ordinary [com]mands, we introduce these notations in a special
scope called [dcom_scope], and we wrap examples with the
declaration [% dcom] to signal that we want the notations to be
interpreted in this scope.
Careful readers will note that we've defined two notations for the
[DCPre] constructor, one with and one without a [=>]. The
"without" version is intended to be used to supply the initial
precondition at the very top of the program. *)
Example dec_while : dcom := (
{{ fun st => True }}
WHILE (BNot (BEq (AId X) (ANum 0)))
DO
{{ fun st => ~(asnat (st X) = 0) }}
X ::= (AMinus (AId X) (ANum 1))
{{ fun _ => True }}
END
{{ fun st => asnat (st X) = 0 }}
) % dcom.
(** It is easy to go from a [dcom] to a [com] by erasing all
annotations. *)
Fixpoint extract (d:dcom) : com :=
match d with
| DCSkip _ => SKIP
| DCSeq d1 d2 => (extract d1 ; extract d2)
| DCAsgn V a _ => V ::= a
| DCIf b _ d1 _ d2 => IFB b THEN extract d1 ELSE extract d2 FI
| DCWhile b _ d _ => WHILE b DO extract d END
| DCPre _ d => extract d
| DCPost d _ => extract d
end.
(** The choice of exactly where to put assertions in the definition of
[dcom] is a bit subtle. The simplest thing to do would be to
annotate every [dcom] with a precondition and postcondition. But
this would result in very verbose programs with a lot of repeated
annotations: for example, a program like [SKIP;SKIP] would have to
be annotated as
[[
{{P}} ({{P}} SKIP {{P}}) ; ({{P}} SKIP {{P}}) {{P}},
]]
with pre- and post-conditions on each [SKIP], plus identical pre-
and post-conditions on the semicolon!
Instead, the rule we've followed is this:
- The _post_-condition expected by each [dcom] [d] is embedded in [d]
- The _pre_-condition is supplied by the context. *)
(** In other words, the invariant of the representation is that a
[dcom] [d] together with a precondition [P] determines a Hoare
triple [{{P}} (extract d) {{post d}}], where [post] is defined as
follows: *)
Fixpoint post (d:dcom) : Assertion :=
match d with
| DCSkip P => P
| DCSeq d1 d2 => post d2
| DCAsgn V a Q => Q
| DCIf _ _ d1 _ d2 => post d1
| DCWhile b Pbody c Ppost => Ppost
| DCPre _ d => post d
| DCPost c Q => Q
end.
(** We can define a similar function that extracts the "initial
precondition" from a decorated program. *)
Fixpoint pre (d:dcom) : Assertion :=
match d with
| DCSkip P => fun st => True
| DCSeq c1 c2 => pre c1
| DCAsgn V a Q => fun st => True
| DCIf _ _ t _ e => fun st => True
| DCWhile b Pbody c Ppost => fun st => True
| DCPre P c => P
| DCPost c Q => pre c
end.
(** This function is not doing anything sophisticated like calculating
a weakest precondition; it just recursively searches for an
explicit annotation at the very beginning of the program,
returning default answers for programs that lack an explicit
precondition (like a bare assignment or [SKIP]).
Using [pre] and [post], and assuming that we adopt the convention
of always supplying an explicit precondition annotation at the
very beginning of our decorated programs, we can express what it
means for a decorated program to be correct as follows: *)
Definition dec_correct (d:dcom) :=
{{pre d}} (extract d) {{post d}}.
(** To check whether this Hoare triple is _valid_, we need a way to
extract the "proof obligations" from a decorated program. These
obligations are often called _verification conditions_, because
they are the facts that must be verified (by some process looking
at the decorated program) to see that the decorations are
logically consistent and thus add up to a proof of correctness. *)
(** ** Extracting Verification Conditions *)
(** First, a bit of notation: *)
Definition assert_implies (P Q : Assertion) : Prop :=
forall st, P st -> Q st.
(** We will write [P ~~> Q] (in ASCII, [P ~][~> Q]) for [assert_implies
P Q]. *)
Notation "P ~~> Q" := (assert_implies P Q) (at level 80).
Notation "P <~~> Q" := (P ~~> Q /\ Q ~~> P) (at level 80).
(** Next, the key definition. The function [verification_conditions]
takes a [dcom] [d] together with a precondition [P] and returns a
_proposition_ that, if it can be proved, implies that the triple
[{{P}} (extract d) {{post d}}] is valid. It does this by walking
over [d] and generating a big conjunction including all the "local
checks" that we listed when we described the informal rules for
decorated programs. (Strictly speaking, we need to massage the
informal rules a little bit to add some uses of the rule of
consequence, but the correspondence should be clear.) *)
Fixpoint verification_conditions (P : Assertion) (d:dcom) : Prop :=
match d with
| DCSkip Q =>
(P ~~> Q)
| DCSeq d1 d2 =>
verification_conditions P d1
/\ verification_conditions (post d1) d2
| DCAsgn V a Q =>
(P ~~> assn_sub V a Q)
| DCIf b P1 t P2 e =>
((fun st => P st /\ bassn b st) ~~> P1)
/\ ((fun st => P st /\ ~ (bassn b st)) ~~> P2)
/\ (post t = post e)
/\ verification_conditions P1 t
/\ verification_conditions P2 e
| DCWhile b Pbody d Ppost =>
(* post d is the loop invariant and the initial precondition *)
(P ~~> post d)
/\ ((fun st => post d st /\ bassn b st) <~~> Pbody)
/\ ((fun st => post d st /\ ~(bassn b st)) <~~> Ppost)
/\ verification_conditions (fun st => post d st /\ bassn b st) d
| DCPre P' d =>
(P ~~> P') /\ verification_conditions P' d
| DCPost d Q =>
verification_conditions P d /\ (post d ~~> Q)
end.
(** And now, the key theorem, which captures the claim that the
[verification_conditions] function does its job correctly. Not
surprisingly, we need all of the Hoare Logic rules in the
proof. *)
(** We have used _in_ variants of several tactics before to
apply them to values in the context rather than the goal. An
extension of this idea is the syntax [tactic in *], which applies
[tactic] in the goal and every hypothesis in the context. We most
commonly use this facility in conjunction with the [simpl] tactic,
as below. *)
Theorem verification_correct : forall d P,
verification_conditions P d -> {{P}} (extract d) {{post d}}.
Proof.
dcom_cases (induction d) Case; intros P H; simpl in *.
Case "Skip".
eapply hoare_consequence_pre.
apply hoare_skip.
assumption.
Case "Seq".
inversion H as [H1 H2]. clear H.
eapply hoare_seq.
apply IHd2. apply H2.
apply IHd1. apply H1.
Case "Asgn".
eapply hoare_consequence_pre.
apply hoare_asgn.
assumption.
Case "If".
inversion H as [HPre1 [HPre2 [HQeq [HThen HElse]]]]; clear H.
apply hoare_if.
eapply hoare_consequence_pre. apply IHd1. apply HThen. assumption.
simpl. rewrite HQeq.
eapply hoare_consequence_pre. apply IHd2. apply HElse. assumption.
Case "While".
rename a into Pbody. rename a0 into Ppost.
inversion H as [Hpre [Hbody [Hpost Hd]]]; clear H.
eapply hoare_consequence.
apply hoare_while with (P := post d).
apply IHd. apply Hd.
assumption. apply Hpost.
Case "Pre".
inversion H as [HP Hd]; clear H.
eapply hoare_consequence_pre. apply IHd. apply Hd. assumption.
Case "Post".
inversion H as [Hd HQ]; clear H.
eapply hoare_consequence_post. apply IHd. apply Hd. assumption.
Qed.
(** ** Examples *)
(** The propositions generated by [verification_conditions] are fairly
big, and they contain many conjuncts that are essentially trivial. *)
Eval simpl in (verification_conditions (fun st => True) dec_while).
(* ====>
((fun _ : state => True) ~~> (fun _ : state => True)) /\
((fun _ : state => True) ~~> (fun _ : state => True)) /\
((fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st)
<~~> (fun st : state => asnat (st X) <> 0)) /\
((fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st)
<~~> (fun st : state => asnat (st X) = 0)) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st)
~~> assn_sub X (AMinus (AId X) (ANum 1)) (fun _ : state => True) *)
(** We can certainly work with them using just the tactics we have so
far, but we can make things much smoother with a bit of
automation. We first define a custom [verify] tactic that applies
splitting repeatedly to turn all the conjunctions into separate
subgoals and then uses [omega] and [eauto] (a handy
general-purpose automation tactic that we'll discuss in detail
later) to deal with as many of them as possible. *)
Tactic Notation "verify" :=
try apply verification_correct;
repeat split;
simpl; unfold assert_implies;
unfold bassn in *; unfold beval in *; unfold aeval in *;
unfold assn_sub; simpl in *;
intros;
repeat match goal with [H : _ /\ _ |- _] => destruct H end;
try eauto; try omega.
(** What's left after [verify] does its thing is "just the interesting
parts" of checking that the decorations are correct. For example: *)
Theorem dec_while_correct :
dec_correct dec_while.
Proof.
verify; destruct (asnat (st X)).
inversion H0.
unfold not. intros. inversion H1.
apply ex_falso_quodlibet. apply H. reflexivity.
reflexivity.
reflexivity.
apply ex_falso_quodlibet. apply H0. reflexivity.
unfold not. intros. inversion H0.
inversion H.
Qed.
(** Another example (formalizing a decorated program we've seen
before): *)
Example subtract_slowly_dec (x:nat) (z:nat) : dcom := (
{{ fun st => asnat (st X) = x /\ asnat (st Z) = z }}
WHILE BNot (BEq (AId X) (ANum 0))
DO {{ fun st => asnat (st Z) - asnat (st X) = z - x
/\ bassn (BNot (BEq (AId X) (ANum 0))) st }}
Z ::= AMinus (AId Z) (ANum 1)
{{ fun st => asnat (st Z) - (asnat (st X) - 1) = z - x }} ;
X ::= AMinus (AId X) (ANum 1)
{{ fun st => asnat (st Z) - asnat (st X) = z - x }}
END
{{ fun st => asnat (st Z)
- asnat (st X)
= z - x
/\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st }}
=>
{{ fun st => asnat (st Z) = z - x }}
) % dcom.
Theorem subtract_slowly_dec_correct : forall x z,
dec_correct (subtract_slowly_dec x z).
Proof.
intros. verify.
rewrite <- H.
assert (H1: update st Z (VNat (asnat (st Z) - 1)) X = st X).
apply update_neq. reflexivity.
rewrite -> H1. destruct (asnat (st X)) as [| X'].
inversion H0. simpl. rewrite <- minus_n_O. omega.
destruct (asnat (st X)).
omega.
apply ex_falso_quodlibet. apply H0. reflexivity.
Qed.
(** **** Exercise: 3 stars (slow_assignment_dec) *)
(** A roundabout way of assigning a number currently stored in [X] to
the variable [Y] is to start [Y] at [0], then decrement [X] until it
hits [0], incrementing [Y] at each step.
Here is an informal decorated program that implements this idea
given a parameter [x]: *)
(**
[[
{{ True }}
X ::= x
{{ X = x }} ;
Y ::= 0
{{ X = x /\ Y = 0 }} ;
WHILE X <> 0 DO
{{ X + Y = x /\ X > 0 }}
X ::= X - 1
{{ Y + X + 1 = x }} ;
Y ::= Y + 1
{{ Y + X = x }}
END
{{ Y = x /\ X = 0 }}
]]
*)
(** Write a corresponding function that returns a value of type [dcom]
and prove it correct. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, optional (factorial_dec) *)
(** Remember the factorial function we worked with before: *)
Fixpoint real_fact (n:nat) : nat :=
match n with
| O => 1
| S n' => n * (real_fact n')
end.
(** Following the pattern of [subtract_slowly_dec], write a decorated
Imp program that implements the factorial function, and prove it
correct. *)
(* FILL IN HERE *)
(** [] *)
(** Finally, for a bigger example, let's redo the proof of
[list_member_correct] from above using our new tools.
Notice that the [verify] tactic leaves subgoals for each use of
[hoare_consequence] -- that is, for each [=>] that occurs in the
decorated program. Each of these implications relies on a fact
about lists, for example that [l ++ [] = l]. In other words, the
Hoare logic infrastructure has taken care of the boilerplate
reasoning about the execution of imperative programs, while the
user has to prove lemmas that are specific to the problem
domain (e.g. lists or numbers). *)
Definition list_member_dec (n : nat) (l : list nat) : dcom := (
{{ fun st => st X = VList l /\ st Y = VNat n /\ st Z = VNat 0 }}
WHILE BIsCons (AId X)
DO {{ fun st => st Y = VNat n
/\ (exists p, p ++ aslist (st X) = l
/\ (st Z = VNat 1 <-> appears_in n p))
/\ bassn (BIsCons (AId X)) st }}
IFB (BEq (AId Y) (AHead (AId X))) THEN
{{ fun st =>
((st Y = VNat n
/\ (exists p, p ++ aslist (st X) = l
/\ (st Z = VNat 1 <-> appears_in n p)))
/\ bassn (BIsCons (AId X)) st)
/\ bassn (BEq (AId Y) (AHead (AId X))) st }}
=>
{{ fun st =>
st Y = VNat n
/\ (exists p, p ++ tail (aslist (st X)) = l
/\ (VNat 1 = VNat 1 <-> appears_in n p)) }}
Z ::= ANum 1
{{ fun st => st Y = VNat n
/\ (exists p, p ++ tail (aslist (st X)) = l
/\ (st Z = VNat 1 <-> appears_in n p)) }}
ELSE
{{ fun st =>
((st Y = VNat n
/\ (exists p, p ++ aslist (st X) = l
/\ (st Z = VNat 1 <-> appears_in n p)))
/\ bassn (BIsCons (AId X)) st)
/\ ~bassn (BEq (AId Y) (AHead (AId X))) st }}
=>
{{ fun st =>
st Y = VNat n
/\ (exists p, p ++ tail (aslist (st X)) = l
/\ (st Z = VNat 1 <-> appears_in n p)) }}
SKIP
{{ fun st => st Y = VNat n
/\ (exists p, p ++ tail (aslist (st X)) = l
/\ (st Z = VNat 1 <-> appears_in n p)) }}
FI ;
X ::= (ATail (AId X))
{{ fun st =>
st Y = VNat n /\
(exists p : list nat, p ++ aslist (st X) = l
/\ (st Z = VNat 1 <-> appears_in n p)) }}
END
{{ fun st =>
(st Y = VNat n
/\ (exists p, p ++ aslist (st X) = l
/\ (st Z = VNat 1 <-> appears_in n p)))
/\ ~bassn (BIsCons (AId X)) st }}
=>
{{ fun st => st Z = VNat 1 <-> appears_in n l }}
) %dcom.
Theorem list_member_correct' : forall n l,
dec_correct (list_member_dec n l).
Proof.
intros n l.
verify.
Case "The loop precondition holds.".
exists []. simpl. split.
rewrite H. reflexivity.
rewrite H1. split; inversion 1.
Case "IF taken".
destruct H2 as [p [H3 H4]].
(* We know X is non-nil. *)
remember (aslist (st X)) as x.
destruct x as [|h x'].
inversion H1.
exists (snoc p h).
simpl. split.
rewrite snoc_equation. assumption.
split.
rewrite H in H0.
simpl in H0.
rewrite (beq_true__eq _ _ H0).
intros. apply appears_in_snoc1.
intros. reflexivity.
Case "If not taken".
destruct H2 as [p [H3 H4]].
(* We know X is non-nil. *)
remember (aslist (st X)) as x.
destruct x as [|h x'].
inversion H1.
exists (snoc p h).
split.
rewrite snoc_equation. assumption.
split.
intros. apply appears_in_snoc2. apply H4. assumption.
intros Hai. destruct (appears_in_snoc3 _ _ _ Hai).
SCase "later". apply H4. assumption.
SCase "here (absurd)".
subst.
simpl in H0. rewrite H in H0. rewrite beq_nat_refl in H0.
apply ex_falso_quodlibet. apply H0. reflexivity.
Case "Loop postcondition implies desired conclusion (->)".
destruct H2 as [p [H3 H4]].
unfold bassn in H1. simpl in H1.
destruct (aslist (st X)) as [|h x'].
rewrite append_nil in H3. subst. apply H4. assumption.
apply ex_falso_quodlibet. apply H1. reflexivity.
Case "loop postcondition implies desired conclusion (<-)".
destruct H2 as [p [H3 H4]].
unfold bassn in H1. simpl in H1.
destruct (aslist (st X)) as [|h x'].
rewrite append_nil in H3. subst. apply H4. assumption.
apply ex_falso_quodlibet. apply H1. reflexivity.
Qed.
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:10:17 05/08/2017
// Design Name: axi_spi_if
// Module Name: D:/Projects/Rendszerarch/axi_spi_master_if/axi_spi/axi_spi_test.v
// Project Name: axi_spi
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: axi_spi_if
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module axi_spi_test;
// Inputs
reg clk_i;
reg reset_n_i;
reg awvalid_i;
reg [27:0] awaddr_i;
reg awprot_i;
reg wvalid_i;
reg [31:0] wdata_i;
reg [3:0] wstrb_i;
reg bready_i;
reg arvalid_i;
reg [27:0] araddr_i;
reg [2:0] arprot_i;
reg rready_i;
reg spi_miso_i;
// Outputs
wire awready_o;
wire wready_o;
wire bvalid_o;
wire [1:0] bresp_o;
wire arready_o;
wire rvalid_o;
wire [31:0] rdata_o;
wire [1:0] rresp_o;
wire [3:0] spi_ssel_o;
wire spi_sck_o;
wire spi_mosi_o;
// Instantiate the Unit Under Test (UUT)
axi_spi_if uut (
.clk_i(clk_i),
.reset_n_i(reset_n_i),
.awvalid_i(awvalid_i),
.awready_o(awready_o),
.awaddr_i(awaddr_i),
.awprot_i(awprot_i),
.wvalid_i(wvalid_i),
.wready_o(wready_o),
.wdata_i(wdata_i),
.wstrb_i(wstrb_i),
.bvalid_o(bvalid_o),
.bready_i(bready_i),
.bresp_o(bresp_o),
.arvalid_i(arvalid_i),
.arready_o(arready_o),
.araddr_i(araddr_i),
.arprot_i(arprot_i),
.rvalid_o(rvalid_o),
.rready_i(rready_i),
.rdata_o(rdata_o),
.rresp_o(rresp_o),
.spi_ssel_o(spi_ssel_o),
.spi_sck_o(spi_sck_o),
.spi_mosi_o(spi_mosi_o),
.spi_miso_i(spi_miso_i)
);
initial begin
// Initialize Inputs
clk_i = 0;
reset_n_i = 0;
awvalid_i = 0;
awaddr_i = 0;
awprot_i = 0;
wvalid_i = 0;
wdata_i = 0;
wstrb_i = 0;
bready_i = 0;
arvalid_i = 0;
araddr_i = 0;
arprot_i = 0;
rready_i = 0;
spi_miso_i = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset_n_i = 1;
spi_miso_i = 1;
/*
reg_control_i = 32'h0000_0602;
reg_trans_ctrl_i = 32'h0000_0002;
*/
wdata_i = 32'h0000_0602;
awaddr_i = 0;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#1000;
wdata_i = 32'h0000_0002;
awaddr_i = 1;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
wdata_i = 32'h0000_0073;
awaddr_i = 3;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
wdata_i = 32'h0000_0073;
awaddr_i = 4;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
end
always #5 clk_i = ~clk_i;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4B_BEHAVIORAL_V
`define SKY130_FD_SC_LP__OR4B_BEHAVIORAL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__or4b (
X ,
A ,
B ,
C ,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X, not0_out, C, B, A);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4B_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__OR3_BEHAVIORAL_PP_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A, C );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__ISOBUFSRC_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__ISOBUFSRC_BEHAVIORAL_PP_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg_s/sky130_fd_sc_hdll__udp_pwrgood_pp_pg_s.v"
`celldefine
module sky130_fd_sc_hdll__isobufsrc (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , SLEEP );
and and0 (and0_out_X , not0_out, A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG$S pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND, SLEEP);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__ISOBUFSRC_BEHAVIORAL_PP_V |
// spw_babasu_hps_0.v
// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.1 593
`timescale 1 ps / 1 ps
module spw_babasu_hps_0 #(
parameter F2S_Width = 0,
parameter S2F_Width = 1
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire h2f_axi_clk, // h2f_axi_clock.clk
output wire [11:0] h2f_AWID, // h2f_axi_master.awid
output wire [29:0] h2f_AWADDR, // .awaddr
output wire [3:0] h2f_AWLEN, // .awlen
output wire [2:0] h2f_AWSIZE, // .awsize
output wire [1:0] h2f_AWBURST, // .awburst
output wire [1:0] h2f_AWLOCK, // .awlock
output wire [3:0] h2f_AWCACHE, // .awcache
output wire [2:0] h2f_AWPROT, // .awprot
output wire h2f_AWVALID, // .awvalid
input wire h2f_AWREADY, // .awready
output wire [11:0] h2f_WID, // .wid
output wire [31:0] h2f_WDATA, // .wdata
output wire [3:0] h2f_WSTRB, // .wstrb
output wire h2f_WLAST, // .wlast
output wire h2f_WVALID, // .wvalid
input wire h2f_WREADY, // .wready
input wire [11:0] h2f_BID, // .bid
input wire [1:0] h2f_BRESP, // .bresp
input wire h2f_BVALID, // .bvalid
output wire h2f_BREADY, // .bready
output wire [11:0] h2f_ARID, // .arid
output wire [29:0] h2f_ARADDR, // .araddr
output wire [3:0] h2f_ARLEN, // .arlen
output wire [2:0] h2f_ARSIZE, // .arsize
output wire [1:0] h2f_ARBURST, // .arburst
output wire [1:0] h2f_ARLOCK, // .arlock
output wire [3:0] h2f_ARCACHE, // .arcache
output wire [2:0] h2f_ARPROT, // .arprot
output wire h2f_ARVALID, // .arvalid
input wire h2f_ARREADY, // .arready
input wire [11:0] h2f_RID, // .rid
input wire [31:0] h2f_RDATA, // .rdata
input wire [1:0] h2f_RRESP, // .rresp
input wire h2f_RLAST, // .rlast
input wire h2f_RVALID, // .rvalid
output wire h2f_RREADY, // .rready
output wire [12:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [7:0] mem_dq, // .mem_dq
inout wire mem_dqs, // .mem_dqs
inout wire mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire mem_dm, // .mem_dm
input wire oct_rzqin // .oct_rzqin
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
spw_babasu_hps_0_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.h2f_axi_clk (h2f_axi_clk), // h2f_axi_clock.clk
.h2f_AWID (h2f_AWID), // h2f_axi_master.awid
.h2f_AWADDR (h2f_AWADDR), // .awaddr
.h2f_AWLEN (h2f_AWLEN), // .awlen
.h2f_AWSIZE (h2f_AWSIZE), // .awsize
.h2f_AWBURST (h2f_AWBURST), // .awburst
.h2f_AWLOCK (h2f_AWLOCK), // .awlock
.h2f_AWCACHE (h2f_AWCACHE), // .awcache
.h2f_AWPROT (h2f_AWPROT), // .awprot
.h2f_AWVALID (h2f_AWVALID), // .awvalid
.h2f_AWREADY (h2f_AWREADY), // .awready
.h2f_WID (h2f_WID), // .wid
.h2f_WDATA (h2f_WDATA), // .wdata
.h2f_WSTRB (h2f_WSTRB), // .wstrb
.h2f_WLAST (h2f_WLAST), // .wlast
.h2f_WVALID (h2f_WVALID), // .wvalid
.h2f_WREADY (h2f_WREADY), // .wready
.h2f_BID (h2f_BID), // .bid
.h2f_BRESP (h2f_BRESP), // .bresp
.h2f_BVALID (h2f_BVALID), // .bvalid
.h2f_BREADY (h2f_BREADY), // .bready
.h2f_ARID (h2f_ARID), // .arid
.h2f_ARADDR (h2f_ARADDR), // .araddr
.h2f_ARLEN (h2f_ARLEN), // .arlen
.h2f_ARSIZE (h2f_ARSIZE), // .arsize
.h2f_ARBURST (h2f_ARBURST), // .arburst
.h2f_ARLOCK (h2f_ARLOCK), // .arlock
.h2f_ARCACHE (h2f_ARCACHE), // .arcache
.h2f_ARPROT (h2f_ARPROT), // .arprot
.h2f_ARVALID (h2f_ARVALID), // .arvalid
.h2f_ARREADY (h2f_ARREADY), // .arready
.h2f_RID (h2f_RID), // .rid
.h2f_RDATA (h2f_RDATA), // .rdata
.h2f_RRESP (h2f_RRESP), // .rresp
.h2f_RLAST (h2f_RLAST), // .rlast
.h2f_RVALID (h2f_RVALID), // .rvalid
.h2f_RREADY (h2f_RREADY) // .rready
);
spw_babasu_hps_0_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin) // .oct_rzqin
);
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file ramcart.v when simulating
// the core, ramcart. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module ramcart(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [14 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input [0 : 0] web;
input [12 : 0] addrb;
input [31 : 0] dinb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(15),
.C_ADDRB_WIDTH(13),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("ramcart.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(32768),
.C_READ_DEPTH_B(8192),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(32768),
.C_WRITE_DEPTH_B(8192),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
`include "../mem/im.v"
`include "../RF/reg_file2.v"
`include "../ALU/alu.v"
`include "../lib/mux5bit_2to1_2.v"
`include "../lib/mux32bit_4to1.v"
`include "../lib/mux32bit_2to1.v"
`include "../lib/mux32bit_2to1_2.v"
`include "../lib/sign_extend.v"
`include "../control/control2.v"
`include "../ALU/alu_control2.v"
`include "../mem/dm.v"
`include "../lib/shift_left_2.v"
`include "../lib/jump_addr.v"
module cpu(input clk,
output [31:0] alu_output, data, nxt_pc);
reg [31:0] pc;
wire [31:0] readData1, readData2, b;
wire regDest0, regDst1, regWrite, aluSrc, zero, memToReg0, memToReg1;
wire memRead, memWrite, branch, branch_ne, s_branch, jump;
wire [31:0] sExtended, alu_output, memData, writeData, j_addr, mux3_output, mux4_output;
wire [3:0] alu_ctrl;
wire [2:0] alu_op;
wire [4:0] writeReg;
wire [31:0] fa1_output, ex_shifted, pc_4;
initial pc <= 32'd0;
im i_mem(.clk(clk),
.data(data),
.addr(pc));
mux5bit_4to1 mux0(.i0(data[20:16]),
.i1(data[15:11]),
.i2(5'd31),
.s({regDst1, regDst0}),
.z(writeReg));
reg_file rf(.readReg1(data[25:21]),
.readReg2(data[20:16]),
.writeReg(writeReg),
.clk(clk),
.regWrite(regWrite),
.readData1(readData1),
.readData2(readData2),
.writeData(writeData));
sign_extend se(.a(data[15:0]), .b(sExtended));
mux32bit_2to1 mux1(.i0(readData2),
.i1(sExtended),
.s(aluSrc),
.z(b));
alu main_alu(.op(alu_ctrl), .a(readData1), .b(b), .z(alu_output), .zero(zero));
alu_control ac (.funct(data[5:0]), .alu_op(alu_op), .aluctrl(alu_ctrl));
control c(.op(data[31:26]),
.alu_op(alu_op),
.regDst0(regDst0),
.regDst1(regDst1),
.aluSrc(aluSrc),
.memToReg0(memToReg0),
.memToReg1(memToReg1),
.regWrite(regWrite),
.memRead(memRead),
.memWrite(memWrite),
.branch(branch),
.branch_ne(branch_ne),
.jump(jump));
dm mem(.clk(clk), .addr(alu_output), .writeData(readData2), .memWrite(memWrite), .memRead(memRead), .readData(memData));
mux32bit_4to1 mux2(.i0(alu_output), .i1(memData), .i2(pc_4), .s({memToReg1, memToReg0}), .z(writeData));
shift_left_2 sll2(.a(sExtended), .b(ex_shifted));
//alu fa1(.op(4'd2), .a(pc_4), .b(ex_shifted), .z(fa1_output));
alu fa1(.op(4'd2), .a(pc_4), .b(sExtended), .z(fa1_output));
wire int0, int1;
and (int0, branch, zero);
and (int1, branch_ne, ~zero);
or (s_branch, int0, int1);
wire jr;
and and1(jr , ~data[5], ~data[4], data[3], ~data[2], ~data[1], ~data[0]
, ~data[26], ~data[27],~data[28], ~data[29], ~data[30], ~data[31] );
//always @(*) jr = ~data[26] & ~data[27] & data[28] & ~data[29] & ~data[30] & ~data[31];
jump_addr ja(.inst(data[25:0]), .pc_4(pc_4[31:28]), .j_addr(j_addr));
//mux32bit_2to1 mux3(.i0(pc_4), .i1(fa1_output), .s(s_branch), .z(nxt_pc));
mux32bit_2to1_2 mux3(.i0(pc_4), .i1(fa1_output), .s(s_branch), .z(mux3_output));
mux32bit_2to1_2 mux4(.i0(mux3_output), .i1(j_addr), .s(jump), .z(mux4_output));
mux32bit_2to1_2 mux5(.i1(readData1), .i0(mux4_output), .z(nxt_pc), .s(jr));
//mux32bit_2to1 mux4(.i1(j_addr), .i0(mux3_output), .z(nxt_pc), .s(jump));
alu fa2(.op(4'd2), .a(pc), .b(32'd1), .z(pc_4));
always @(posedge clk) begin
pc <= nxt_pc;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200 Top Level ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// OR1200 Top Level ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.10.4.9 2004/02/11 01:40:11 lampret
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
//
// Revision 1.10.4.8 2004/01/17 21:14:14 simons
// Errors fixed.
//
// Revision 1.10.4.7 2004/01/17 19:06:38 simons
// Error fixed.
//
// Revision 1.10.4.6 2004/01/17 18:39:48 simons
// Error fixed.
//
// Revision 1.10.4.5 2004/01/15 06:46:38 markom
// interface to debug changed; no more opselect; stb-ack protocol
//
// Revision 1.10.4.4 2003/12/09 11:46:49 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.10.4.3 2003/12/05 00:08:44 lampret
// Fixed instantiation name.
//
// Revision 1.10.4.2 2003/07/11 01:10:35 lampret
// Added three missing wire declarations. No functional changes.
//
// Revision 1.10.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.10 2002/12/08 08:57:56 lampret
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
//
// Revision 1.9 2002/10/17 20:04:41 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.8 2002/08/18 19:54:22 lampret
// Added store buffer.
//
// Revision 1.7 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.6 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4 2002/02/01 19:56:55 lampret
// Fixed combinational loops.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/18 07:56:00 lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.13 2001/11/23 08:38:51 lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.12 2001/11/20 00:57:22 lampret
// Fixed width of du_except.
//
// Revision 1.11 2001/11/18 08:36:28 lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.10 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.9 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.4 2001/08/13 03:36:20 lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.3 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/22 03:31:54 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:21 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_top(
openRISC_pc,
// System
clk_i, rst_i, pic_ints_i, clmode_i,
// Instruction WISHBONE INTERFACE
iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
`ifdef OR1200_WB_CAB
iwb_cab_o,
`endif
`ifdef OR1200_WB_B3
iwb_cti_o, iwb_bte_o,
`endif
// Data WISHBONE INTERFACE
dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
`ifdef OR1200_WB_CAB
dwb_cab_o,
`endif
`ifdef OR1200_WB_B3
dwb_cti_o, dwb_bte_o,
`endif
// External Debug Interface
dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Power Management
pm_cpustall_i,
pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
parameter ppic_ints = `OR1200_PIC_INTS;
//
// I/O
//
//
// System
//
output [31:0] openRISC_pc;
input clk_i;
input rst_i;
input [1:0] clmode_i; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
input [ppic_ints-1:0] pic_ints_i;
//
// Instruction WISHBONE interface
//
input iwb_clk_i; // clock input
input iwb_rst_i; // reset input
input iwb_ack_i; // normal termination
input iwb_err_i; // termination w/ error
input iwb_rty_i; // termination w/ retry
input [dw-1:0] iwb_dat_i; // input data bus
output iwb_cyc_o; // cycle valid output
output [aw-1:0] iwb_adr_o; // address bus outputs
output iwb_stb_o; // strobe output
output iwb_we_o; // indicates write transfer
output [3:0] iwb_sel_o; // byte select outputs
output [dw-1:0] iwb_dat_o; // output data bus
`ifdef OR1200_WB_CAB
output iwb_cab_o; // indicates consecutive address burst
`endif
`ifdef OR1200_WB_B3
output [2:0] iwb_cti_o; // cycle type identifier
output [1:0] iwb_bte_o; // burst type extension
`endif
//
// Data WISHBONE interface
//
input dwb_clk_i; // clock input
input dwb_rst_i; // reset input
input dwb_ack_i; // normal termination
input dwb_err_i; // termination w/ error
input dwb_rty_i; // termination w/ retry
input [dw-1:0] dwb_dat_i; // input data bus
output dwb_cyc_o; // cycle valid output
output [aw-1:0] dwb_adr_o; // address bus outputs
output dwb_stb_o; // strobe output
output dwb_we_o; // indicates write transfer
output [3:0] dwb_sel_o; // byte select outputs
output [dw-1:0] dwb_dat_o; // output data bus
`ifdef OR1200_WB_CAB
output dwb_cab_o; // indicates consecutive address burst
`endif
`ifdef OR1200_WB_B3
output [2:0] dwb_cti_o; // cycle type identifier
output [1:0] dwb_bte_o; // burst type extension
`endif
//
// External Debug Interface
//
input dbg_stall_i; // External Stall Input
input dbg_ewt_i; // External Watchpoint Trigger Input
output [3:0] dbg_lss_o; // External Load/Store Unit Status
output [1:0] dbg_is_o; // External Insn Fetch Status
output [10:0] dbg_wp_o; // Watchpoints Outputs
output dbg_bp_o; // Breakpoint Output
input dbg_stb_i; // External Address/Data Strobe
input dbg_we_i; // External Write Enable
input [aw-1:0] dbg_adr_i; // External Address Input
input [dw-1:0] dbg_dat_i; // External Data Input
output [dw-1:0] dbg_dat_o; // External Data Output
output dbg_ack_o; // External Data Acknowledge (not WB compatible)
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Power Management
//
input pm_cpustall_i;
output [3:0] pm_clksd_o;
output pm_dc_gate_o;
output pm_ic_gate_o;
output pm_dmmu_gate_o;
output pm_immu_gate_o;
output pm_tt_gate_o;
output pm_cpu_gate_o;
output pm_wakeup_o;
output pm_lvolt_o;
//
// Internal wires and regs
//
//
// DC to SB
//
wire [dw-1:0] dcsb_dat_dc;
wire [aw-1:0] dcsb_adr_dc;
wire dcsb_cyc_dc;
wire dcsb_stb_dc;
wire dcsb_we_dc;
wire [3:0] dcsb_sel_dc;
wire dcsb_cab_dc;
wire [dw-1:0] dcsb_dat_sb;
wire dcsb_ack_sb;
wire dcsb_err_sb;
//
// SB to BIU
//
wire [dw-1:0] sbbiu_dat_sb;
wire [aw-1:0] sbbiu_adr_sb;
wire sbbiu_cyc_sb;
wire sbbiu_stb_sb;
wire sbbiu_we_sb;
wire [3:0] sbbiu_sel_sb;
wire sbbiu_cab_sb;
wire [dw-1:0] sbbiu_dat_biu;
wire sbbiu_ack_biu;
wire sbbiu_err_biu;
//
// IC to BIU
//
wire [dw-1:0] icbiu_dat_ic;
wire [aw-1:0] icbiu_adr_ic;
wire icbiu_cyc_ic;
wire icbiu_stb_ic;
wire icbiu_we_ic;
wire [3:0] icbiu_sel_ic;
wire [3:0] icbiu_tag_ic;
wire icbiu_cab_ic;
wire [dw-1:0] icbiu_dat_biu;
wire icbiu_ack_biu;
wire icbiu_err_biu;
wire [3:0] icbiu_tag_biu;
//
// CPU's SPR access to various RISC units (shared wires)
//
wire supv;
wire [aw-1:0] spr_addr;
wire [dw-1:0] spr_dat_cpu;
wire [31:0] spr_cs;
wire spr_we;
//
// DMMU and CPU
//
wire dmmu_en;
wire [31:0] spr_dat_dmmu;
//
// DMMU and QMEM
//
wire qmemdmmu_err_qmem;
wire [3:0] qmemdmmu_tag_qmem;
wire [aw-1:0] qmemdmmu_adr_dmmu;
wire qmemdmmu_cycstb_dmmu;
wire qmemdmmu_ci_dmmu;
//
// CPU and data memory subsystem
//
wire dc_en;
wire [31:0] dcpu_adr_cpu;
wire dcpu_cycstb_cpu;
wire dcpu_we_cpu;
wire [3:0] dcpu_sel_cpu;
wire [3:0] dcpu_tag_cpu;
wire [31:0] dcpu_dat_cpu;
wire [31:0] dcpu_dat_qmem;
wire dcpu_ack_qmem;
wire dcpu_rty_qmem;
wire dcpu_err_dmmu;
wire [3:0] dcpu_tag_dmmu;
//
// IMMU and CPU
//
wire immu_en;
wire [31:0] spr_dat_immu;
//
// CPU and insn memory subsystem
//
wire ic_en;
wire [31:0] icpu_adr_cpu;
wire icpu_cycstb_cpu;
wire [3:0] icpu_sel_cpu;
wire [3:0] icpu_tag_cpu;
wire [31:0] icpu_dat_qmem;
wire icpu_ack_qmem;
wire [31:0] icpu_adr_immu;
wire icpu_err_immu;
wire [3:0] icpu_tag_immu;
wire icpu_rty_immu;
//
// IMMU and QMEM
//
wire [aw-1:0] qmemimmu_adr_immu;
wire qmemimmu_rty_qmem;
wire qmemimmu_err_qmem;
wire [3:0] qmemimmu_tag_qmem;
wire qmemimmu_cycstb_immu;
wire qmemimmu_ci_immu;
//
// QMEM and IC
//
wire [aw-1:0] icqmem_adr_qmem;
wire icqmem_rty_ic;
wire icqmem_err_ic;
wire [3:0] icqmem_tag_ic;
wire icqmem_cycstb_qmem;
wire icqmem_ci_qmem;
wire [31:0] icqmem_dat_ic;
wire icqmem_ack_ic;
//
// QMEM and DC
//
wire [aw-1:0] dcqmem_adr_qmem;
wire dcqmem_rty_dc;
wire dcqmem_err_dc;
wire [3:0] dcqmem_tag_dc;
wire dcqmem_cycstb_qmem;
wire dcqmem_ci_qmem;
wire [31:0] dcqmem_dat_dc;
wire [31:0] dcqmem_dat_qmem;
wire dcqmem_we_qmem;
wire [3:0] dcqmem_sel_qmem;
wire dcqmem_ack_dc;
//
// Connection between CPU and PIC
//
wire [dw-1:0] spr_dat_pic;
wire pic_wakeup;
wire sig_int;
//
// Connection between CPU and PM
//
wire [dw-1:0] spr_dat_pm;
//
// CPU and TT
//
wire [dw-1:0] spr_dat_tt;
wire sig_tick;
//
// Debug port and caches/MMUs
//
wire [dw-1:0] spr_dat_du;
wire du_stall;
wire [dw-1:0] du_addr;
wire [dw-1:0] du_dat_du;
wire du_read;
wire du_write;
wire [12:0] du_except;
wire [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
wire [dw-1:0] du_dat_cpu;
wire du_hwbkpt;
wire ex_freeze;
wire [31:0] ex_insn;
wire [31:0] id_pc;
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
wire [31:0] spr_dat_npc;
wire [31:0] rf_dataw;
`ifdef OR1200_BIST
//
// RAM BIST
//
wire mbist_immu_so;
wire mbist_ic_so;
wire mbist_dmmu_so;
wire mbist_dc_so;
wire mbist_qmem_so;
wire mbist_immu_si = mbist_si_i;
wire mbist_ic_si = mbist_immu_so;
wire mbist_qmem_si = mbist_ic_so;
wire mbist_dmmu_si = mbist_qmem_so;
wire mbist_dc_si = mbist_dmmu_so;
assign mbist_so_o = mbist_dc_so;
`endif
wire [3:0] icqmem_sel_qmem;
wire [3:0] icqmem_tag_qmem;
wire [3:0] dcqmem_tag_qmem;
//
// Instantiation of Instruction WISHBONE BIU
//
or1200_iwb_biu iwb_biu(
// RISC clk, rst and clock control
.clk(clk_i),
.rst(rst_i),
.clmode(clmode_i),
// WISHBONE interface
.wb_clk_i(iwb_clk_i),
.wb_rst_i(iwb_rst_i),
.wb_ack_i(iwb_ack_i),
.wb_err_i(iwb_err_i),
.wb_rty_i(iwb_rty_i),
.wb_dat_i(iwb_dat_i),
.wb_cyc_o(iwb_cyc_o),
.wb_adr_o(iwb_adr_o),
.wb_stb_o(iwb_stb_o),
.wb_we_o(iwb_we_o),
.wb_sel_o(iwb_sel_o),
.wb_dat_o(iwb_dat_o),
`ifdef OR1200_WB_CAB
.wb_cab_o(iwb_cab_o),
`endif
`ifdef OR1200_WB_B3
.wb_cti_o(iwb_cti_o),
.wb_bte_o(iwb_bte_o),
`endif
// Internal RISC bus
.biu_dat_i(icbiu_dat_ic),
.biu_adr_i(icbiu_adr_ic),
.biu_cyc_i(icbiu_cyc_ic),
.biu_stb_i(icbiu_stb_ic),
.biu_we_i(icbiu_we_ic),
.biu_sel_i(icbiu_sel_ic),
.biu_cab_i(icbiu_cab_ic),
.biu_dat_o(icbiu_dat_biu),
.biu_ack_o(icbiu_ack_biu),
.biu_err_o(icbiu_err_biu)
);
//
// Instantiation of Data WISHBONE BIU
//
or1200_wb_biu dwb_biu(
// RISC clk, rst and clock control
.clk(clk_i),
.rst(rst_i),
.clmode(clmode_i),
// WISHBONE interface
.wb_clk_i(dwb_clk_i),
.wb_rst_i(dwb_rst_i),
.wb_ack_i(dwb_ack_i),
.wb_err_i(dwb_err_i),
.wb_rty_i(dwb_rty_i),
.wb_dat_i(dwb_dat_i),
.wb_cyc_o(dwb_cyc_o),
.wb_adr_o(dwb_adr_o),
.wb_stb_o(dwb_stb_o),
.wb_we_o(dwb_we_o),
.wb_sel_o(dwb_sel_o),
.wb_dat_o(dwb_dat_o),
`ifdef OR1200_WB_CAB
.wb_cab_o(dwb_cab_o),
`endif
`ifdef OR1200_WB_B3
.wb_cti_o(dwb_cti_o),
.wb_bte_o(dwb_bte_o),
`endif
// Internal RISC bus
.biu_dat_i(sbbiu_dat_sb),
.biu_adr_i(sbbiu_adr_sb),
.biu_cyc_i(sbbiu_cyc_sb),
.biu_stb_i(sbbiu_stb_sb),
.biu_we_i(sbbiu_we_sb),
.biu_sel_i(sbbiu_sel_sb),
.biu_cab_i(sbbiu_cab_sb),
.biu_dat_o(sbbiu_dat_biu),
.biu_ack_o(sbbiu_ack_biu),
.biu_err_o(sbbiu_err_biu)
);
//
// Instantiation of IMMU
//
or1200_immu_top or1200_immu_top(
// Rst and clk
.clk(clk_i),
.rst(rst_i),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_immu_si),
.mbist_so_o(mbist_immu_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// CPU and IMMU
.ic_en(ic_en),
.immu_en(immu_en),
.supv(supv),
.icpu_adr_i(icpu_adr_cpu),
.icpu_cycstb_i(icpu_cycstb_cpu),
.icpu_adr_o(icpu_adr_immu),
.icpu_tag_o(icpu_tag_immu),
.icpu_rty_o(icpu_rty_immu),
.icpu_err_o(icpu_err_immu),
// SPR access
.spr_cs(spr_cs[`OR1200_SPR_GROUP_IMMU]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_immu),
// QMEM and IMMU
.qmemimmu_rty_i(qmemimmu_rty_qmem),
.qmemimmu_err_i(qmemimmu_err_qmem),
.qmemimmu_tag_i(qmemimmu_tag_qmem),
.qmemimmu_adr_o(qmemimmu_adr_immu),
.qmemimmu_cycstb_o(qmemimmu_cycstb_immu),
.qmemimmu_ci_o(qmemimmu_ci_immu)
);
//
// Instantiation of Instruction Cache
//
or1200_ic_top or1200_ic_top(
.clk(clk_i),
.rst(rst_i),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_ic_si),
.mbist_so_o(mbist_ic_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// IC and QMEM
.ic_en(ic_en),
.icqmem_adr_i(icqmem_adr_qmem),
.icqmem_cycstb_i(icqmem_cycstb_qmem),
.icqmem_ci_i(icqmem_ci_qmem),
.icqmem_sel_i(icqmem_sel_qmem),
.icqmem_tag_i(icqmem_tag_qmem),
.icqmem_dat_o(icqmem_dat_ic),
.icqmem_ack_o(icqmem_ack_ic),
.icqmem_rty_o(icqmem_rty_ic),
.icqmem_err_o(icqmem_err_ic),
.icqmem_tag_o(icqmem_tag_ic),
// SPR access
.spr_cs(spr_cs[`OR1200_SPR_GROUP_IC]),
.spr_write(spr_we),
.spr_dat_i(spr_dat_cpu),
// IC and BIU
.icbiu_dat_o(icbiu_dat_ic),
.icbiu_adr_o(icbiu_adr_ic),
.icbiu_cyc_o(icbiu_cyc_ic),
.icbiu_stb_o(icbiu_stb_ic),
.icbiu_we_o(icbiu_we_ic),
.icbiu_sel_o(icbiu_sel_ic),
.icbiu_cab_o(icbiu_cab_ic),
.icbiu_dat_i(icbiu_dat_biu),
.icbiu_ack_i(icbiu_ack_biu),
.icbiu_err_i(icbiu_err_biu)
);
//
// Instantiation of Instruction Cache
//
or1200_cpu or1200_cpu(
.clk(clk_i),
.rst(rst_i),
// Connection QMEM and IFETCHER inside CPU
.ic_en(ic_en),
.icpu_adr_o(icpu_adr_cpu),
.icpu_cycstb_o(icpu_cycstb_cpu),
.icpu_sel_o(icpu_sel_cpu),
.icpu_tag_o(icpu_tag_cpu),
.icpu_dat_i(icpu_dat_qmem),
.icpu_ack_i(icpu_ack_qmem),
.icpu_rty_i(icpu_rty_immu),
.icpu_adr_i(icpu_adr_immu),
.icpu_err_i(icpu_err_immu),
.icpu_tag_i(icpu_tag_immu),
// Connection CPU to external Debug port
.ex_freeze(ex_freeze),
.ex_insn(ex_insn),
.id_pc(id_pc),
.branch_op(branch_op),
.du_stall(du_stall),
.du_addr(du_addr),
.du_dat_du(du_dat_du),
.du_read(du_read),
.du_write(du_write),
.du_dsr(du_dsr),
.du_except(du_except),
.du_dat_cpu(du_dat_cpu),
.du_hwbkpt(du_hwbkpt),
.rf_dataw(rf_dataw),
// Connection IMMU and CPU internally
.immu_en(immu_en),
// Connection QMEM and CPU
.dc_en(dc_en),
.dcpu_adr_o(dcpu_adr_cpu),
.dcpu_cycstb_o(dcpu_cycstb_cpu),
.dcpu_we_o(dcpu_we_cpu),
.dcpu_sel_o(dcpu_sel_cpu),
.dcpu_tag_o(dcpu_tag_cpu),
.dcpu_dat_o(dcpu_dat_cpu),
.dcpu_dat_i(dcpu_dat_qmem),
.dcpu_ack_i(dcpu_ack_qmem),
.dcpu_rty_i(dcpu_rty_qmem),
.dcpu_err_i(dcpu_err_dmmu),
.dcpu_tag_i(dcpu_tag_dmmu),
// Connection DMMU and CPU internally
.dmmu_en(dmmu_en),
// Connection PIC and CPU's EXCEPT
.sig_int(sig_int),
.sig_tick(sig_tick),
// SPRs
.supv(supv),
.spr_addr(spr_addr),
.spr_dat_cpu(spr_dat_cpu),
.spr_dat_pic(spr_dat_pic),
.spr_dat_tt(spr_dat_tt),
.spr_dat_pm(spr_dat_pm),
.spr_dat_dmmu(spr_dat_dmmu),
.spr_dat_immu(spr_dat_immu),
.spr_dat_du(spr_dat_du),
.spr_dat_npc(spr_dat_npc),
.spr_cs(spr_cs),
.spr_we(spr_we)
);
//
// Instantiation of DMMU
//
or1200_dmmu_top or1200_dmmu_top(
// Rst and clk
.clk(clk_i),
.rst(rst_i),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_dmmu_si),
.mbist_so_o(mbist_dmmu_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// CPU i/f
.dc_en(dc_en),
.dmmu_en(dmmu_en),
.supv(supv),
.dcpu_adr_i(dcpu_adr_cpu),
.dcpu_cycstb_i(dcpu_cycstb_cpu),
.dcpu_we_i(dcpu_we_cpu),
.dcpu_tag_o(dcpu_tag_dmmu),
.dcpu_err_o(dcpu_err_dmmu),
// SPR access
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DMMU]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_dmmu),
// QMEM and DMMU
.qmemdmmu_err_i(qmemdmmu_err_qmem),
.qmemdmmu_tag_i(qmemdmmu_tag_qmem),
.qmemdmmu_adr_o(qmemdmmu_adr_dmmu),
.qmemdmmu_cycstb_o(qmemdmmu_cycstb_dmmu),
.qmemdmmu_ci_o(qmemdmmu_ci_dmmu)
);
//
// Instantiation of Data Cache
//
or1200_dc_top or1200_dc_top(
.clk(clk_i),
.rst(rst_i),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_dc_si),
.mbist_so_o(mbist_dc_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// DC and QMEM
.dc_en(dc_en),
.dcqmem_adr_i(dcqmem_adr_qmem),
.dcqmem_cycstb_i(dcqmem_cycstb_qmem),
.dcqmem_ci_i(dcqmem_ci_qmem),
.dcqmem_we_i(dcqmem_we_qmem),
.dcqmem_sel_i(dcqmem_sel_qmem),
.dcqmem_tag_i(dcqmem_tag_qmem),
.dcqmem_dat_i(dcqmem_dat_qmem),
.dcqmem_dat_o(dcqmem_dat_dc),
.dcqmem_ack_o(dcqmem_ack_dc),
.dcqmem_rty_o(dcqmem_rty_dc),
.dcqmem_err_o(dcqmem_err_dc),
.dcqmem_tag_o(dcqmem_tag_dc),
// SPR access
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DC]),
.spr_write(spr_we),
.spr_dat_i(spr_dat_cpu),
// DC and BIU
.dcsb_dat_o(dcsb_dat_dc),
.dcsb_adr_o(dcsb_adr_dc),
.dcsb_cyc_o(dcsb_cyc_dc),
.dcsb_stb_o(dcsb_stb_dc),
.dcsb_we_o(dcsb_we_dc),
.dcsb_sel_o(dcsb_sel_dc),
.dcsb_cab_o(dcsb_cab_dc),
.dcsb_dat_i(dcsb_dat_sb),
.dcsb_ack_i(dcsb_ack_sb),
.dcsb_err_i(dcsb_err_sb)
);
//
// Instantiation of embedded memory - qmem
//
or1200_qmem_top or1200_qmem_top(
.clk(clk_i),
.rst(rst_i),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_qmem_si),
.mbist_so_o(mbist_qmem_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// QMEM and CPU/IMMU
.qmemimmu_adr_i(qmemimmu_adr_immu),
.qmemimmu_cycstb_i(qmemimmu_cycstb_immu),
.qmemimmu_ci_i(qmemimmu_ci_immu),
.qmemicpu_sel_i(icpu_sel_cpu),
.qmemicpu_tag_i(icpu_tag_cpu),
.qmemicpu_dat_o(icpu_dat_qmem),
.qmemicpu_ack_o(icpu_ack_qmem),
.qmemimmu_rty_o(qmemimmu_rty_qmem),
.qmemimmu_err_o(qmemimmu_err_qmem),
.qmemimmu_tag_o(qmemimmu_tag_qmem),
// QMEM and IC
.icqmem_adr_o(icqmem_adr_qmem),
.icqmem_cycstb_o(icqmem_cycstb_qmem),
.icqmem_ci_o(icqmem_ci_qmem),
.icqmem_sel_o(icqmem_sel_qmem),
.icqmem_tag_o(icqmem_tag_qmem),
.icqmem_dat_i(icqmem_dat_ic),
.icqmem_ack_i(icqmem_ack_ic),
.icqmem_rty_i(icqmem_rty_ic),
.icqmem_err_i(icqmem_err_ic),
.icqmem_tag_i(icqmem_tag_ic),
// QMEM and CPU/DMMU
.qmemdmmu_adr_i(qmemdmmu_adr_dmmu),
.qmemdmmu_cycstb_i(qmemdmmu_cycstb_dmmu),
.qmemdmmu_ci_i(qmemdmmu_ci_dmmu),
.qmemdcpu_we_i(dcpu_we_cpu),
.qmemdcpu_sel_i(dcpu_sel_cpu),
.qmemdcpu_tag_i(dcpu_tag_cpu),
.qmemdcpu_dat_i(dcpu_dat_cpu),
.qmemdcpu_dat_o(dcpu_dat_qmem),
.qmemdcpu_ack_o(dcpu_ack_qmem),
.qmemdcpu_rty_o(dcpu_rty_qmem),
.qmemdmmu_err_o(qmemdmmu_err_qmem),
.qmemdmmu_tag_o(qmemdmmu_tag_qmem),
// QMEM and DC
.dcqmem_adr_o(dcqmem_adr_qmem),
.dcqmem_cycstb_o(dcqmem_cycstb_qmem),
.dcqmem_ci_o(dcqmem_ci_qmem),
.dcqmem_we_o(dcqmem_we_qmem),
.dcqmem_sel_o(dcqmem_sel_qmem),
.dcqmem_tag_o(dcqmem_tag_qmem),
.dcqmem_dat_o(dcqmem_dat_qmem),
.dcqmem_dat_i(dcqmem_dat_dc),
.dcqmem_ack_i(dcqmem_ack_dc),
.dcqmem_rty_i(dcqmem_rty_dc),
.dcqmem_err_i(dcqmem_err_dc),
.dcqmem_tag_i(dcqmem_tag_dc)
);
//
// Instantiation of Store Buffer
//
or1200_sb or1200_sb(
// RISC clock, reset
.clk(clk_i),
.rst(rst_i),
// Internal RISC bus (DC<->SB)
.dcsb_dat_i(dcsb_dat_dc),
.dcsb_adr_i(dcsb_adr_dc),
.dcsb_cyc_i(dcsb_cyc_dc),
.dcsb_stb_i(dcsb_stb_dc),
.dcsb_we_i(dcsb_we_dc),
.dcsb_sel_i(dcsb_sel_dc),
.dcsb_cab_i(dcsb_cab_dc),
.dcsb_dat_o(dcsb_dat_sb),
.dcsb_ack_o(dcsb_ack_sb),
.dcsb_err_o(dcsb_err_sb),
// SB and BIU
.sbbiu_dat_o(sbbiu_dat_sb),
.sbbiu_adr_o(sbbiu_adr_sb),
.sbbiu_cyc_o(sbbiu_cyc_sb),
.sbbiu_stb_o(sbbiu_stb_sb),
.sbbiu_we_o(sbbiu_we_sb),
.sbbiu_sel_o(sbbiu_sel_sb),
.sbbiu_cab_o(sbbiu_cab_sb),
.sbbiu_dat_i(sbbiu_dat_biu),
.sbbiu_ack_i(sbbiu_ack_biu),
.sbbiu_err_i(sbbiu_err_biu)
);
//
// Instantiation of Debug Unit
//
or1200_du or1200_du(
// RISC Internal Interface
.clk(clk_i),
.rst(rst_i),
.dcpu_cycstb_i(dcpu_cycstb_cpu),
.dcpu_we_i(dcpu_we_cpu),
.dcpu_adr_i(dcpu_adr_cpu),
.dcpu_dat_lsu(dcpu_dat_cpu),
.dcpu_dat_dc(dcpu_dat_qmem),
.icpu_cycstb_i(icpu_cycstb_cpu),
.ex_freeze(ex_freeze),
.branch_op(branch_op),
.ex_insn(ex_insn),
.id_pc(id_pc),
.du_dsr(du_dsr),
// For Trace buffer
.spr_dat_npc(spr_dat_npc),
.rf_dataw(rf_dataw),
// DU's access to SPR unit
.du_stall(du_stall),
.du_addr(du_addr),
.du_dat_i(du_dat_cpu),
.du_dat_o(du_dat_du),
.du_read(du_read),
.du_write(du_write),
.du_except(du_except),
.du_hwbkpt(du_hwbkpt),
// Access to DU's SPRs
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DU]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_du),
// External Debug Interface
.dbg_stall_i(dbg_stall_i),
.dbg_ewt_i(dbg_ewt_i),
.dbg_lss_o(dbg_lss_o),
.dbg_is_o(dbg_is_o),
.dbg_wp_o(dbg_wp_o),
.dbg_bp_o(dbg_bp_o),
.dbg_stb_i(dbg_stb_i),
.dbg_we_i(dbg_we_i),
.dbg_adr_i(dbg_adr_i),
.dbg_dat_i(dbg_dat_i),
.dbg_dat_o(dbg_dat_o),
.dbg_ack_o(dbg_ack_o)
);
//
// Programmable interrupt controller
//
or1200_pic or1200_pic(
// RISC Internal Interface
.clk(clk_i),
.rst(rst_i),
.spr_cs(spr_cs[`OR1200_SPR_GROUP_PIC]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_pic),
.pic_wakeup(pic_wakeup),
.intr(sig_int),
// PIC Interface
.pic_int(pic_ints_i)
);
//
// Instantiation of Tick timer
//
or1200_tt or1200_tt(
// RISC Internal Interface
.clk(clk_i),
.rst(rst_i),
.du_stall(du_stall),
.spr_cs(spr_cs[`OR1200_SPR_GROUP_TT]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_tt),
.intr(sig_tick)
);
//
// Instantiation of Power Management
//
or1200_pm or1200_pm(
// RISC Internal Interface
.clk(clk_i),
.rst(rst_i),
.pic_wakeup(pic_wakeup),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_pm),
// Power Management Interface
.pm_cpustall(pm_cpustall_i),
.pm_clksd(pm_clksd_o),
.pm_dc_gate(pm_dc_gate_o),
.pm_ic_gate(pm_ic_gate_o),
.pm_dmmu_gate(pm_dmmu_gate_o),
.pm_immu_gate(pm_immu_gate_o),
.pm_tt_gate(pm_tt_gate_o),
.pm_cpu_gate(pm_cpu_gate_o),
.pm_wakeup(pm_wakeup_o),
.pm_lvolt(pm_lvolt_o)
);
assign openRISC_pc = id_pc;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: scbuf_evict.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
`include "iop.h"
module scbuf_evict
(/*AUTOARG*/
// Outputs
so, scbuf_dram_wr_data_r5_pb, scbuf_dram_data_vld_r5_pb,
scbuf_dram_data_mecc_r5_pb, scbuf_sctag_ev_uerr_r5_pb,
scbuf_sctag_ev_cerr_r5_pb, sctag_scbuf_wbrd_en_r1_v1,
sctag_scbuf_wbrd_en_r1_v2, sctag_scbuf_wbrd_en_r1_v3,
sctag_scbuf_wbrd_en_r1_v4, sctag_scbuf_wbrd_wl_r1_v1,
sctag_scbuf_wbrd_wl_r1_v2, sctag_scbuf_wbrd_wl_r1_v3,
sctag_scbuf_wbrd_wl_r1_v4, sctag_scbuf_wbwr_wen_c8_v1,
sctag_scbuf_wbwr_wen_c8_v2, sctag_scbuf_wbwr_wen_c8_v3,
sctag_scbuf_wbwr_wen_c8_v4, sctag_scbuf_wbwr_wl_c8_v1,
sctag_scbuf_wbwr_wl_c8_v2, sctag_scbuf_wbwr_wl_c8_v3,
sctag_scbuf_wbwr_wl_c8_v4, sctag_scbuf_rdma_rden_r1_v1,
sctag_scbuf_rdma_rden_r1_v2, sctag_scbuf_rdma_rden_r1_v3,
sctag_scbuf_rdma_rden_r1_v4, sctag_scbuf_rdma_rdwl_r1_v1,
sctag_scbuf_rdma_rdwl_r1_v2, sctag_scbuf_rdma_rdwl_r1_v3,
sctag_scbuf_rdma_rdwl_r1_v4, sctag_scbuf_rdma_wren_s3,
sctag_scbuf_rdma_wren_s3_v4, sctag_scbuf_rdma_wren_s3_v3,
sctag_scbuf_rdma_wren_s3_v2, sctag_scbuf_rdma_wren_s3_v1,
sctag_scbuf_rdma_wrwl_s3_v1, sctag_scbuf_rdma_wrwl_s3_v2,
sctag_scbuf_rdma_wrwl_s3_v3, sctag_scbuf_rdma_wrwl_s3_v4,
rdma_array_din,
// Inputs
rclk, arst_l, grst_l, se, sehold, si, sctag_scbuf_wbrd_en_r0,
wb_array_dout, sctag_scbuf_evict_en_r0, sctag_scbuf_ev_dword_r0,
sctag_scbuf_rdma_rden_r0, rdma_array_dout, sctag_scbuf_wbrd_wl_r0,
sctag_scbuf_wbwr_wen_c6, sctag_scbuf_wbwr_wl_c6,
sctag_scbuf_rdma_rdwl_r0, sctag_scbuf_rdma_wren_s2,
sctag_scbuf_rdma_wrwl_s2, jbi_sctag_req, jbi_scbuf_ecc
) ;
// Inputs
input rclk;
input arst_l;
input grst_l;
input se, sehold, si;
input sctag_scbuf_wbrd_en_r0;
input [623:0] wb_array_dout;
input sctag_scbuf_evict_en_r0;
input [2:0] sctag_scbuf_ev_dword_r0;
input sctag_scbuf_rdma_rden_r0;
input [623:0] rdma_array_dout;
input [2:0] sctag_scbuf_wbrd_wl_r0;
input sctag_scbuf_wbwr_wen_c6;
input [2:0] sctag_scbuf_wbwr_wl_c6;
input [1:0] sctag_scbuf_rdma_rdwl_r0;
input [15:0] sctag_scbuf_rdma_wren_s2;
input [1:0] sctag_scbuf_rdma_wrwl_s2;
input [31:0] jbi_sctag_req ;
input [6:0] jbi_scbuf_ecc ;
// Outputs
output so;
output [63:0] scbuf_dram_wr_data_r5_pb;
output scbuf_dram_data_vld_r5_pb;
output scbuf_dram_data_mecc_r5_pb;
output scbuf_sctag_ev_uerr_r5_pb;
output scbuf_sctag_ev_cerr_r5_pb;
output sctag_scbuf_wbrd_en_r1_v1;
output sctag_scbuf_wbrd_en_r1_v2;
output sctag_scbuf_wbrd_en_r1_v3;
output sctag_scbuf_wbrd_en_r1_v4;
output [2:0] sctag_scbuf_wbrd_wl_r1_v1;
output [2:0] sctag_scbuf_wbrd_wl_r1_v2;
output [2:0] sctag_scbuf_wbrd_wl_r1_v3;
output [2:0] sctag_scbuf_wbrd_wl_r1_v4;
output sctag_scbuf_wbwr_wen_c8_v1;
output sctag_scbuf_wbwr_wen_c8_v2;
output sctag_scbuf_wbwr_wen_c8_v3;
output sctag_scbuf_wbwr_wen_c8_v4;
output [2:0] sctag_scbuf_wbwr_wl_c8_v1;
output [2:0] sctag_scbuf_wbwr_wl_c8_v2;
output [2:0] sctag_scbuf_wbwr_wl_c8_v3;
output [2:0] sctag_scbuf_wbwr_wl_c8_v4;
output sctag_scbuf_rdma_rden_r1_v1;
output sctag_scbuf_rdma_rden_r1_v2;
output sctag_scbuf_rdma_rden_r1_v3;
output sctag_scbuf_rdma_rden_r1_v4;
output [1:0] sctag_scbuf_rdma_rdwl_r1_v1;
output [1:0] sctag_scbuf_rdma_rdwl_r1_v2;
output [1:0] sctag_scbuf_rdma_rdwl_r1_v3;
output [1:0] sctag_scbuf_rdma_rdwl_r1_v4;
output [15:0] sctag_scbuf_rdma_wren_s3;
output sctag_scbuf_rdma_wren_s3_v4 ;
output sctag_scbuf_rdma_wren_s3_v3 ;
output sctag_scbuf_rdma_wren_s3_v2 ;
output sctag_scbuf_rdma_wren_s3_v1 ;
output [1:0] sctag_scbuf_rdma_wrwl_s3_v1;
output [1:0] sctag_scbuf_rdma_wrwl_s3_v2;
output [1:0] sctag_scbuf_rdma_wrwl_s3_v3;
output [1:0] sctag_scbuf_rdma_wrwl_s3_v4;
output [623:0] rdma_array_din ;
////////////////////////////////////////////////////////////////////////////////
wire sctag_scbuf_wbrd_en_r2;
wire sctag_scbuf_rdma_rden_r1;
wire sctag_scbuf_rdma_rden_r2;
wire wb_or_rdma_rden_r2;
wire [623:0] wb_rdma_mux_out;
wire [623:0] wb_array_dout_r3;
wire [ 77:0] wb_array_dout_r4;
wire [ 63:0] wb_array_dout_r5;
wire [ 2:0] sctag_scbuf_ev_dword_r1;
wire [ 2:0] sctag_scbuf_ev_dword_r2;
wire [ 2:0] sctag_scbuf_ev_dword_r3;
wire sel_in0;
wire sel_in1;
wire sel_in2;
wire sel_in3;
wire [155:0] wb_array_dout_r3_4t1;
wire [ 77:0] wb_array_dout_r3_8t1;
wire [ 63:0] wb_array_dout_ecc_r4;
wire [ 5:0] check0_r4;
wire [ 5:0] check1_r4;
wire evict_uncorr_err_r4;
wire evict_corr_err_r4;
wire sctag_scbuf_wbwr_wen_c7;
wire [ 2:0] sctag_scbuf_wbwr_wl_c7;
wire [38:0] jbi_sctag_req_ecc_s2 ;
wire [38:0] jbi_sctag_req_ecc_s3;
wire [2:0] sctag_scbuf_wbrd_wl_r1;
wire sctag_scbuf_wbwr_wen_c8;
wire [2:0] sctag_scbuf_wbwr_wl_c8;
wire [1:0] sctag_scbuf_rdma_rdwl_r1;
wire [1:0] sctag_scbuf_rdma_wrwl_s3;
wire sctag_scbuf_evict_en_r3;
wire evict_uncorr_err_unqual_r4;
wire error_qual_in;
wire error_qual;
dffrl_async #(1) reset_flop
(.q (dbb_rst_l),
.clk (rclk),
.rst_l (arst_l),
.din (grst_l),
.se (se), .si(), .so());
////////////////////////////////////////////////////////////////////////////////
// Data arriving from jbus is flopped and fanned out to 624 bits here.
////////////////////////////////////////////////////////////////////////////////
assign jbi_sctag_req_ecc_s2 = {jbi_sctag_req[31:0], jbi_scbuf_ecc[6:0]} ;
dff_s #(39) ff_jbi_sctag_req_ecc_s3 (.din(jbi_sctag_req_ecc_s2[38:0]),
.clk(rclk),
.q(jbi_sctag_req_ecc_s3[38:0]), .se(1'b0), .si(), .so());
assign rdma_array_din = {16{jbi_sctag_req_ecc_s3[38:0]}} ;
////////////////////////////////////////////////////////////////////////////////
dff_s #(1) ff_sctag_scbuf_wbwr_wen_c7
(.q (sctag_scbuf_wbwr_wen_c7),
.din (sctag_scbuf_wbwr_wen_c6),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
dff_s #(1) ff_sctag_scbuf_wbwr_wen_c8
(.q (sctag_scbuf_wbwr_wen_c8),
.din (sctag_scbuf_wbwr_wen_c7),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
assign sctag_scbuf_wbwr_wen_c8_v1 = sctag_scbuf_wbwr_wen_c8 ;
assign sctag_scbuf_wbwr_wen_c8_v2 = sctag_scbuf_wbwr_wen_c8 ;
assign sctag_scbuf_wbwr_wen_c8_v3 = sctag_scbuf_wbwr_wen_c8 ;
assign sctag_scbuf_wbwr_wen_c8_v4 = sctag_scbuf_wbwr_wen_c8 ;
dff_s #(3) ff_sctag_scbuf_wbwr_wl_c7
(.q (sctag_scbuf_wbwr_wl_c7[2:0]),
.din (sctag_scbuf_wbwr_wl_c6[2:0]),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
dff_s #(3) ff_sctag_scbuf_wbwr_wl_c8
(.q (sctag_scbuf_wbwr_wl_c8[2:0]),
.din (sctag_scbuf_wbwr_wl_c7[2:0]),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
assign sctag_scbuf_wbwr_wl_c8_v1[2:0] = sctag_scbuf_wbwr_wl_c8[2:0] ;
assign sctag_scbuf_wbwr_wl_c8_v2[2:0] = sctag_scbuf_wbwr_wl_c8[2:0] ;
assign sctag_scbuf_wbwr_wl_c8_v3[2:0] = sctag_scbuf_wbwr_wl_c8[2:0] ;
assign sctag_scbuf_wbwr_wl_c8_v4[2:0] = sctag_scbuf_wbwr_wl_c8[2:0] ;
dff_s #(3) ff_sctag_scbuf_wbrd_wl_r1
(.q (sctag_scbuf_wbrd_wl_r1[2:0]),
.din (sctag_scbuf_wbrd_wl_r0[2:0]),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
assign sctag_scbuf_wbrd_wl_r1_v1[2:0] = sctag_scbuf_wbrd_wl_r1[2:0] ;
assign sctag_scbuf_wbrd_wl_r1_v2[2:0] = sctag_scbuf_wbrd_wl_r1[2:0] ;
assign sctag_scbuf_wbrd_wl_r1_v3[2:0] = sctag_scbuf_wbrd_wl_r1[2:0] ;
assign sctag_scbuf_wbrd_wl_r1_v4[2:0] = sctag_scbuf_wbrd_wl_r1[2:0] ;
dff_s #(2) ff_sctag_scbuf_rdma_rdwl_r1
(.q (sctag_scbuf_rdma_rdwl_r1[1:0]),
.din (sctag_scbuf_rdma_rdwl_r0[1:0]),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
assign sctag_scbuf_rdma_rdwl_r1_v1[1:0] = sctag_scbuf_rdma_rdwl_r1[1:0] ;
assign sctag_scbuf_rdma_rdwl_r1_v2[1:0] = sctag_scbuf_rdma_rdwl_r1[1:0] ;
assign sctag_scbuf_rdma_rdwl_r1_v3[1:0] = sctag_scbuf_rdma_rdwl_r1[1:0] ;
assign sctag_scbuf_rdma_rdwl_r1_v4[1:0] = sctag_scbuf_rdma_rdwl_r1[1:0] ;
dff_s #(16) ff_sctag_scbuf_rdma_wren_s3
(.q (sctag_scbuf_rdma_wren_s3[15:0]),
.din (sctag_scbuf_rdma_wren_s2[15:0]),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
assign sctag_scbuf_rdma_wren_s3_v4 = (sctag_scbuf_rdma_wren_s3[6] |
sctag_scbuf_rdma_wren_s3[4] |
sctag_scbuf_rdma_wren_s3[2] |
sctag_scbuf_rdma_wren_s3[0]) ;
assign sctag_scbuf_rdma_wren_s3_v3 = (sctag_scbuf_rdma_wren_s3[7] |
sctag_scbuf_rdma_wren_s3[5] |
sctag_scbuf_rdma_wren_s3[3] |
sctag_scbuf_rdma_wren_s3[1]) ;
assign sctag_scbuf_rdma_wren_s3_v2 = (sctag_scbuf_rdma_wren_s3[14] |
sctag_scbuf_rdma_wren_s3[12] |
sctag_scbuf_rdma_wren_s3[10] |
sctag_scbuf_rdma_wren_s3[8]) ;
assign sctag_scbuf_rdma_wren_s3_v1 = (sctag_scbuf_rdma_wren_s3[15] |
sctag_scbuf_rdma_wren_s3[13] |
sctag_scbuf_rdma_wren_s3[11] |
sctag_scbuf_rdma_wren_s3[9]) ;
dff_s #(2) ff_sctag_scbuf_rdma_wrwl_s3
(.q (sctag_scbuf_rdma_wrwl_s3[1:0]),
.din (sctag_scbuf_rdma_wrwl_s2[1:0]),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
assign sctag_scbuf_rdma_wrwl_s3_v1[1:0] = sctag_scbuf_rdma_wrwl_s3[1:0] ;
assign sctag_scbuf_rdma_wrwl_s3_v2[1:0] = sctag_scbuf_rdma_wrwl_s3[1:0] ;
assign sctag_scbuf_rdma_wrwl_s3_v3[1:0] = sctag_scbuf_rdma_wrwl_s3[1:0] ;
assign sctag_scbuf_rdma_wrwl_s3_v4[1:0] = sctag_scbuf_rdma_wrwl_s3[1:0] ;
////////////////////////////////////////////////////////////////////////////////
dff_s #(1) ff_sctag_scbuf_wbrd_en_r1
(.q (sctag_scbuf_wbrd_en_r1),
.din (sctag_scbuf_wbrd_en_r0),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
assign sctag_scbuf_wbrd_en_r1_v1 = sctag_scbuf_wbrd_en_r1 ;
assign sctag_scbuf_wbrd_en_r1_v2 = sctag_scbuf_wbrd_en_r1 ;
assign sctag_scbuf_wbrd_en_r1_v3 = sctag_scbuf_wbrd_en_r1 ;
assign sctag_scbuf_wbrd_en_r1_v4 = sctag_scbuf_wbrd_en_r1 ;
mux2ds #(1) mux_wbrd_en_r1_in
(.dout (sctag_scbuf_wbrd_en_r1_in),
.in0 (sctag_scbuf_wbrd_en_r1), .sel0 (~sehold),
.in1 (sctag_scbuf_wbrd_en_r2), .sel1 (sehold)) ;
dff_s #(1) ff_sctag_scbuf_wbrd_en_r2
(.q (sctag_scbuf_wbrd_en_r2),
.din (sctag_scbuf_wbrd_en_r1_in),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
dff_s #(1) ff_sctag_scbuf_rdma_rden_r1
(.q (sctag_scbuf_rdma_rden_r1),
.din (sctag_scbuf_rdma_rden_r0),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
assign sctag_scbuf_rdma_rden_r1_v1 = sctag_scbuf_rdma_rden_r1 ;
assign sctag_scbuf_rdma_rden_r1_v2 = sctag_scbuf_rdma_rden_r1 ;
assign sctag_scbuf_rdma_rden_r1_v3 = sctag_scbuf_rdma_rden_r1 ;
assign sctag_scbuf_rdma_rden_r1_v4 = sctag_scbuf_rdma_rden_r1 ;
dff_s #(1) ff_sctag_scbuf_rdma_rden_r2
(.q (sctag_scbuf_rdma_rden_r2),
.din (sctag_scbuf_rdma_rden_r1),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
dff_s #(1) ff_sctag_scbuf_rdma_rden_r3
(.q (sctag_scbuf_rdma_rden_r3),
.din (sctag_scbuf_rdma_rden_r2),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
assign error_qual_in = sctag_scbuf_rdma_rden_r3 | (error_qual & sctag_scbuf_evict_en_r3) ;
dffrl_s #(1) ff_array_rd_ptr
(.q (error_qual),
.din (error_qual_in),
.clk (rclk), .rst_l (dbb_rst_l),
.se (se), .si (), .so ()) ;
assign wb_or_rdma_rden_r2 = (sctag_scbuf_wbrd_en_r2 | sctag_scbuf_rdma_rden_r2) | sehold ;
clken_buf clk_buf_r2 (.clk(en_clk_r2), .rclk(rclk),
.enb_l(~wb_or_rdma_rden_r2), .tmb_l(~se));
clken_buf clk_buf_r3 (.clk(en_clk_r3), .rclk(rclk),
.enb_l(~sctag_scbuf_evict_en_r3), .tmb_l(~se));
mux2ds #(624) mux_wb_rdma_mux_out
(.dout (wb_rdma_mux_out[623:0]),
.in0 (wb_array_dout[623:0]), .sel0 (sctag_scbuf_wbrd_en_r2),
.in1 (rdma_array_dout[623:0]), .sel1 (~sctag_scbuf_wbrd_en_r2)) ;
dff_s #(624) ff_wb_array_dout_r3
(.q (wb_array_dout_r3[623:0]),
.din (wb_rdma_mux_out[623:0]),
.clk (en_clk_r2),
.se (1'b0), .si (), .so ()) ;
////////////////////////////////////////////////////////////////////////////////
dff_s #(1) ff_sctag_scbuf_evict_en_r1
(.q (sctag_scbuf_evict_en_r1),
.din (sctag_scbuf_evict_en_r0),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
dff_s #(1) ff_sctag_scbuf_evict_en_r2
(.q (sctag_scbuf_evict_en_r2),
.din (sctag_scbuf_evict_en_r1),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
dff_s #(1) ff_sctag_scbuf_evict_en_r3
(.q (sctag_scbuf_evict_en_r3),
.din (sctag_scbuf_evict_en_r2),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
dff_s #(1) ff_sctag_scbuf_evict_en_r4
(.q (sctag_scbuf_evict_en_r4),
.din (sctag_scbuf_evict_en_r3),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
dff_s #(1) ff_sctag_scbuf_evict_en_r5
(.q (sctag_scbuf_evict_en_r5),
.din (sctag_scbuf_evict_en_r4),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
dff_s #(3) ff_ev_dword_r1
(.q (sctag_scbuf_ev_dword_r1[2:0]),
.din (sctag_scbuf_ev_dword_r0[2:0]),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
dff_s #(3) ff_ev_dword_r2
(.q (sctag_scbuf_ev_dword_r2[2:0]),
.din (sctag_scbuf_ev_dword_r1[2:0]),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
dff_s #(3) ff_ev_dword_r3
(.q (sctag_scbuf_ev_dword_r3[2:0]),
.din (sctag_scbuf_ev_dword_r2[2:0]),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
assign sel_in0 = (sctag_scbuf_ev_dword_r3[1:0] == 2'b00) ;
assign sel_in1 = (sctag_scbuf_ev_dword_r3[1:0] == 2'b01) ;
assign sel_in2 = (sctag_scbuf_ev_dword_r3[1:0] == 2'b10) ;
assign sel_in3 = ~(sel_in0 | sel_in1 | sel_in2) ;
mux4ds #(78) mux_wb_array_dout_1
(.dout (wb_array_dout_r3_4t1[77:0]),
.in0 (wb_array_dout_r3[ 77: 0]), .sel0 (sel_in3),
.in1 (wb_array_dout_r3[155: 78]), .sel1 (sel_in2),
.in2 (wb_array_dout_r3[233:156]), .sel2 (sel_in1),
.in3 (wb_array_dout_r3[311:234]), .sel3 (sel_in0)) ;
mux4ds #(78) mux_wb_array_dout_2
(.dout (wb_array_dout_r3_4t1[155:78]),
.in0 (wb_array_dout_r3[389:312]), .sel0 (sel_in3),
.in1 (wb_array_dout_r3[467:390]), .sel1 (sel_in2),
.in2 (wb_array_dout_r3[545:468]), .sel2 (sel_in1),
.in3 (wb_array_dout_r3[623:546]), .sel3 (sel_in0)) ;
mux2ds #(78) mux_wb_array_dout_8t1
(.dout (wb_array_dout_r3_8t1[77:0]),
.in0 (wb_array_dout_r3_4t1[ 77: 0]), .sel0 (sctag_scbuf_ev_dword_r3[2]),
.in1 (wb_array_dout_r3_4t1[155:78]), .sel1 (~sctag_scbuf_ev_dword_r3[2])) ;
dff_s #(78) ff_wb_array_dout_r4
(.q (wb_array_dout_r4[77:0]),
.din (wb_array_dout_r3_8t1[77:0]),
.clk (en_clk_r3),
.se (1'b0), .si (), .so ()) ;
////////////////////////////////////////////////////////////////////////////////
zzecc_sctag_ecc39 u_ecctree_39b_1
(.dout (wb_array_dout_ecc_r4[31:0]),
.cflag (check0_r4[5:0]),
.pflag (parity0_r4),
.parity (wb_array_dout_r4[6:0]),
.din (wb_array_dout_r4[38:7])) ;
zzecc_sctag_ecc39 u_ecctree_39b_2
(.dout (wb_array_dout_ecc_r4[63:32]),
.cflag (check1_r4[5:0]),
.pflag (parity1_r4),
.parity (wb_array_dout_r4[45:39]),
.din (wb_array_dout_r4[77:46])) ;
assign evict_uncorr_err_r4 = (sctag_scbuf_evict_en_r4 & !error_qual) &
(((|check0_r4[5:0]) & ~parity0_r4) |
((|check1_r4[5:0]) & ~parity1_r4)) ;
assign evict_uncorr_err_unqual_r4 = sctag_scbuf_evict_en_r4 &
(((|check0_r4[5:0]) & ~parity0_r4) |
((|check1_r4[5:0]) & ~parity1_r4)) ;
assign evict_corr_err_r4 = (sctag_scbuf_evict_en_r4 & !error_qual) &
(parity0_r4 | parity1_r4) ;
dff_s #(64) ff_wb_array_dout_r5
(.q (wb_array_dout_r5[63:0]),
.din (wb_array_dout_ecc_r4[63:0]),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
dff_s #(1) ff_evict_uncorr_err_r5
(.q (evict_uncorr_err_r5),
.din (evict_uncorr_err_r4),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
dff_s #(1) ff_evict_uncorr_err_unqual_r5
(.q (evict_uncorr_err_unqual_r5),
.din (evict_uncorr_err_unqual_r4),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
dff_s #(1) ff_evict_corr_err_r5
(.q (evict_corr_err_r5),
.din (evict_corr_err_r4),
.clk (rclk),
.se (1'b0), .si (), .so ()) ;
////////////////////////////////////////////////////////////////////////////////
assign scbuf_dram_wr_data_r5_pb = wb_array_dout_r5[63:0] ;
assign scbuf_dram_data_vld_r5_pb = sctag_scbuf_evict_en_r5 ;
assign scbuf_dram_data_mecc_r5_pb = evict_uncorr_err_unqual_r5 ;
assign scbuf_sctag_ev_uerr_r5_pb = evict_uncorr_err_r5 ;
assign scbuf_sctag_ev_cerr_r5_pb = evict_corr_err_r5 ;
////////////////////////////////////////////////////////////////////////////////
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: N/A
// Engineer: Ari Sundholm <[email protected]>
//
// Create Date: 23:24:07 02/01/2015
// Design Name:
// Module Name: gsu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies: gsu_cache
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module gsu(
input clkin,
input [7:0] DI,
output [7:0] DO,
input [23:0] ADDR,
input CS,
input reg_we_rising,
input [7:0] ROM_BUS_DI,
output [23:0] ROM_BUS_ADDR,
output ROM_BUS_RRQ,
input ROM_BUS_RDY,
input [7:0] RAM_BUS_DI,
input [7:0] RAM_BUS_DO,
output [18:0] RAM_BUS_ADDR,
output RAM_BUS_RRQ,
output RAM_BUS_WRQ,
input RAM_BUS_RDY,
output gsu_active,
output ron,
output ran
);
wire mmio_enable = CS & !ADDR[22] & (ADDR[15:12] == 4'b0011) & (ADDR[15:0] < 16'h3040);
wire MMIO_WR_EN = mmio_enable & reg_we_rising;
reg [7:0] MMIO_DOr;
wire [7:0] MMIO_DO;
assign MMIO_DO = MMIO_DOr;
wire cache_enable = CS & !ADDR[22] & (ADDR[15:12] == 4'b0011) & (ADDR[9] ^ ADDR[8]) & (ADDR[15:0] < 16'h3300);
wire CACHE_WR_EN = cache_enable & reg_we_rising;
reg [7:0] CACHE_DOr;
wire [7:0] CACHE_DO;
assign CACHE_DO = CACHE_DOr;
assign DO = mmio_enable ? MMIO_DO
: cache_enable ? CACHE_DO
: 8'h00;
reg [15:0] regs [15:0]; // General purpose registers R0~R15
parameter
RAP = 4'd14,
PC = 4'd15
;
// Status/flag register flags
reg [15:0] sfr;
wire z = sfr[1]; // Zero
wire cy = sfr[2]; // Carry
wire s = sfr[3]; // Sign
wire ov = sfr[4]; // Overflow
wire g = sfr[5]; // Go
wire r = sfr[6]; // Reading ROM using R14
wire alt1 = sfr[8]; // Mode flag for next insn
wire alt2 = sfr[9]; // Mode flag for next insn
wire il = sfr[10]; // Immediate lower
wire ih = sfr[11]; // Immediate higher
wire b = sfr[12]; // Instruction executed with WITH
wire irq = sfr[15]; // Interrupt
parameter
Z = 4'd1,
CY = 4'd2,
S = 4'd3,
OV = 4'd4,
G = 4'd5,
R = 4'd6,
ALT1 = 4'd8,
ALT2 = 4'd9,
IL = 4'd10,
IH = 4'd11,
B = 4'd12,
IRQ = 4'd15
;
reg [7:0] pbr; // Program bank register
reg [7:0] rombr; // Game Pak ROM bank register
reg rambr; // Game Pak RAM bank register
reg [15:0] cbr; // Cache base register. [3:0] are always 0.
// TODO: why not make the register only 12 bits wide?
reg [7:0] scbr; // Screen base register
reg [5:0] scmr; // Screen mode register
reg [7:0] colr; // Color register
reg [4:0] por; // Plot option register
reg bramr; // Back-up RAM register
reg [7:0] vcr; // Version code register
reg [7:0] cfgr; // Config register
reg clsr; // Clock select register
reg [7:0] pipeline;
reg [3:0] src_reg;
reg [15:0] src_reg_reg;
reg [3:0] dst_reg;
reg [3:0] dst1;
reg [15:0] dst1_reg;
reg dst1_reg_assigned;
initial dst1_reg_assigned = 1'b0;
/*
reg [3:0] dst2;
reg [15:0] dst2_reg;
reg dst2_reg_assigned;
initial dst2_reg_assigned = 1'b0;
*/
reg [16:0] res17;
/* ROM/RAM bus access flags */
assign ron = scmr[4];
assign ran = scmr[3];
/* Cache RAM and cache flags */
reg [31:0] cache_flags;
initial cache_flags = 32'h00000000;
wire [7:0] cache_outa;
wire [7:0] cache_in;
wire [8:0] cache_addra;
wire cache_we;
wire [7:0] cache_byte;
wire [7:0] cache_outb;
wire [8:0] cache_addrb;
gsu_cache cache (
.douta(cache_outa),
.dina(cache_in),
.addra(cache_addra),
.wea(cache_we),
.doutb(cache_outb),
.addrb(cache_addrb),
.clk(clkin)
);
wire [8:0] RESOLVED_CACHE_ADDR = (ADDR[9:0] + cbr) & 9'h1ff;
wire [8:0] RESOLVED_CACHE_PC = (regs[PC][9:0] + cbr) & 9'h1ff;
assign cache_addrb = RESOLVED_CACHE_ADDR;
assign cache_byte = cache_outa;
/* Cache flag of byte in cache pointed to by the program counter */
wire cache_flag = cache_flags[RESOLVED_CACHE_PC[8:4]];
/* Bytes of the current instruction */
reg [7:0] curr_inst [2:0];
reg [2:0] curr_inst_valid;
reg [2:0] curr_inst_fetches;
/* Byte in pipeline */
reg [7:0] pipeline_byte;
/* Immediate parts of current instruction */
wire [3:0] imm = cache_byte[3:0];
reg [3:0] immr4;
reg [7:0] immr8 [1:0];
/* For plotting, two pixel caches. */
reg[7:0] primary_pcache [7:0];
reg[7:0] primary_pcache_flags;
reg[7:0] secondary_pcache [7:0];
reg[7:0] secondary_pcache_flags;
reg fetch_cached_insn;
reg[7:0] state;
parameter STATE_IDLE = 8'b00000001;
parameter STATE_CPU1 = 8'b00000010;
parameter STATE_CPU2 = 8'b00000100;
parameter STATE_CPU3 = 8'b00001000;
parameter STATE_CPU4 = 8'b00010000;
parameter OP_ALT1 = 8'b00111101;
parameter OP_ALT2 = 8'b00111110;
parameter OP_ALT3 = 8'b00111111;
parameter OP_FROM = 8'b1011xxxx;
parameter OP_TO = 8'b0001xxxx;
parameter OP_ADX = 8'b0101xxxx;
parameter OP_BEQ = 8'b00001001;
parameter OP_NOP = 8'b00000001;
parameter OP_IWT = 8'b1111xxxx; // Also LM, SM
reg [7:0] curr_op;
initial begin: initial_blk
reg [4:0] i;
state = STATE_IDLE;
for (i = 5'h0; i <= PC; i = i + 5'h1) begin
regs[i] = 16'h0000;
end
curr_op = OP_NOP;
curr_inst[0] = OP_NOP;
curr_inst[1] = 8'b0;
curr_inst[2] = 8'b0;
for (i = 2'h0; i < 2'h3; i = i + 2'h1) begin
curr_inst_valid[i] = 1'b0;
end
pipeline_byte = OP_NOP;
end
reg [2:0] gsu_busy;
parameter BUSY_CACHE = 2'b00;
parameter BUSY_CACHE_SCPU = 2'b01;
parameter BUSY_CPU = 2'b10;
//assign gsu_busy_out = gsu_busy;
assign gsu_active = |gsu_busy;
reg [7:0] scpu_di_r;
initial scpu_di_r = 8'h00;
reg [8:0] gsu_cache_addra;
initial gsu_cache_addra = 9'h000;
reg [8:0] scpu_cache_addra;
initial scpu_cache_addra = 9'h000;
reg gsu_cache_we;
initial gsu_cache_we = 1'b0;
reg scpu_cache_we;
initial scpu_cache_we = 1'b0;
assign cache_in = gsu_busy[BUSY_CACHE] ? ROM_BUS_DI
: gsu_busy[BUSY_CACHE_SCPU] ? scpu_di_r
: 8'h00;
assign cache_addra = gsu_busy[BUSY_CACHE] ? gsu_cache_addra
: gsu_busy[BUSY_CACHE_SCPU] ? scpu_cache_addra
: RESOLVED_CACHE_PC;
assign cache_we = gsu_busy[BUSY_CACHE] ? gsu_cache_we
: gsu_busy[BUSY_CACHE_SCPU] ? scpu_cache_we
: 1'b0;
reg [23:0] CACHE_SRC_ADDRr;
wire [22:0] MAPPED_CACHE_ROM_ADDR = (~|CACHE_SRC_ADDRr[23:22] & CACHE_SRC_ADDRr[15])
? /* Bank 0x00-0x3f, Offset 8000-ffff */
({3'b000, CACHE_SRC_ADDRr[21:16], CACHE_SRC_ADDRr[14:0]})
: /* Bank 0x40-0x5f, Offset 0000-ffff */
({3'b000, CACHE_SRC_ADDRr[20:0]});
reg CACHE_ROM_BUS_RRQr;
initial CACHE_ROM_BUS_RRQr = 1'b0;
/* CPU ROM bus access related flags and registers */
reg cpu_rom_bus_rq;
reg [7:0] cpu_rombusdata;
reg [23:0] cpu_rombusaddr;
assign MAPPED_CPU_ROM_ADDR = (~|cpu_rombusaddr[23:22] & cpu_rombusaddr[15])
? /* Bank 0x00-0x3f, Offset 8000-ffff */
({3'b000, cpu_rombusaddr[21:16], cpu_rombusaddr[14:0]})
: /* Bank 0x40-0x5f, Offset 0000-ffff */
({3'b000, cpu_rombusaddr[20:0]});
assign ROM_BUS_RRQ = CACHE_ROM_BUS_RRQr | cpu_rom_bus_rq;
assign ROM_BUS_ADDR = gsu_busy[BUSY_CACHE] ? MAPPED_CACHE_ROM_ADDR
: MAPPED_CPU_ROM_ADDR;
reg [4:0] CACHE_ST;
parameter ST_CACHE_IDLE = 5'b00001;
parameter ST_CACHE_START = 5'b00010;
parameter ST_CACHE_WAIT = 5'b00100;
parameter ST_CACHE_ADDR = 5'b01000;
parameter ST_CACHE_END = 5'b10000;
initial CACHE_ST = ST_CACHE_IDLE;
reg CACHE_TRIG_ENr;
reg CACHE_TRIG_EN2r;
reg cpu_cache_en;
initial begin
CACHE_TRIG_ENr = 1'b0;
CACHE_TRIG_EN2r = 1'b0;
cpu_cache_en = 1'b0;
end
always @(posedge clkin) CACHE_TRIG_EN2r <= CACHE_TRIG_ENr;
wire CACHE_TRIG_EN = CACHE_TRIG_EN2r;
/* FSM for writing to cache. There are two paths:
1) Filling a non-resident cache block from ROM through internal operation
- Source address: program counter
- Address in cache: (cache base + program counter) & 0x1f0
- Total bytes read and written: 16
2) Writing to the cache from the S-CPU
- Source data: wire DI from main.v
- Address in cache: (cache base + ADDR[9:0]) & 0x1ff
- Total bytes read and written: 1
Filling non-resident cache blocks has priority. */
reg [3:0] cache_count;
initial cache_count = 4'b0;
always @(posedge clkin) begin
case(CACHE_ST)
ST_CACHE_IDLE: begin
if(CACHE_TRIG_EN & ~cache_flags[RESOLVED_CACHE_PC[8:4] /* XXX */]) begin
CACHE_ST <= ST_CACHE_START;
gsu_busy[BUSY_CACHE] <= 1'b1;
end
else if(cpu_cache_en & ~cache_flags[RESOLVED_CACHE_PC[8:4] /* XXX */]) begin
CACHE_ST <= ST_CACHE_START;
gsu_busy[BUSY_CACHE] <= 1'b1;
end
else if (CACHE_WR_EN) begin
CACHE_ST <= ST_CACHE_START;
gsu_busy[BUSY_CACHE_SCPU] <= 1'b1;
end else CACHE_ST <= ST_CACHE_IDLE;
end
ST_CACHE_START: begin
if (gsu_busy[BUSY_CACHE]) begin
CACHE_ST <= ST_CACHE_WAIT;
CACHE_SRC_ADDRr <= regs[PC] /* XXX */;
gsu_cache_addra <= {RESOLVED_CACHE_PC[8:4], 4'h0} /* XXX */;
cache_count <= 4'b0;
CACHE_ROM_BUS_RRQr <= 1'b1;
end
else if (gsu_busy[BUSY_CACHE_SCPU]) begin
CACHE_ST <= ST_CACHE_WAIT;
scpu_cache_addra <= RESOLVED_CACHE_ADDR;
scpu_di_r <= DI;
end else CACHE_ST <= ST_CACHE_IDLE;
end
ST_CACHE_WAIT: begin
if (gsu_busy[BUSY_CACHE]) begin
CACHE_ROM_BUS_RRQr <= 1'b0;
if(~CACHE_ROM_BUS_RRQr & ROM_BUS_RDY) begin
CACHE_ST <= ST_CACHE_ADDR;
gsu_cache_we <= 1'b1;
end else CACHE_ST <= ST_CACHE_WAIT;
end
else if (gsu_busy[BUSY_CACHE_SCPU]) begin
CACHE_ST <= ST_CACHE_ADDR;
scpu_cache_we <= 1'b1;
end
else CACHE_ST <= ST_CACHE_IDLE;
end
ST_CACHE_ADDR: begin
if (gsu_busy[BUSY_CACHE]) begin
gsu_cache_we <= 1'b0;
CACHE_SRC_ADDRr <= CACHE_SRC_ADDRr + 1;
cache_count <= cache_count + 1;
gsu_cache_addra <= (gsu_cache_addra + 10'b1) & 9'h1ff;
if (cache_count == 4'hf) begin
// Set the cache flag, as the last byte in the cache block was written
cache_flags[gsu_cache_addra[8:4]] <= 1'b1;
gsu_busy[BUSY_CACHE] <= 1'b0;
CACHE_ST <= ST_CACHE_IDLE;
end
else begin
CACHE_ROM_BUS_RRQr <= 1'b1;
CACHE_ST <= ST_CACHE_WAIT;
end
end
else if (gsu_busy[BUSY_CACHE_SCPU]) begin
CACHE_ST <= ST_CACHE_IDLE;
gsu_busy[BUSY_CACHE_SCPU] <= 1'b0;
scpu_cache_we <= 1'b0;
// Set the cache flag if the last byte in the cache block was written
if (&scpu_cache_addra[3:0]) begin
cache_flags[scpu_cache_addra[8:4]] <= 1'b1;
end
// the write will have hit the cache by the next cycle
end else CACHE_ST <= ST_CACHE_IDLE;
end
endcase
end
reg [3:0] PIPELINE_ST;
parameter ST_PIPELINE_IDLE = 4'b0001;
parameter ST_PIPELINE_START = 4'b0010;
parameter ST_PIPELINE_WAIT = 4'b0100;
parameter ST_PIPELINE_END = 4'b1000;
initial PIPELINE_ST = ST_PIPELINE_IDLE;
reg [3:0] pipeline_delay;
reg pipeline_cache_wait;
initial pipeline_cache_wait = 0;
/* Process to read instructions from either the cache or the gamepak ROM. */
// XXX: take into account interaction with cache write operations
always @(posedge clkin) begin
case (PIPELINE_ST)
ST_PIPELINE_IDLE: begin
PIPELINE_ST <= ST_PIPELINE_IDLE;
if (sfr[G]) begin
PIPELINE_ST <= ST_PIPELINE_START;
end
end
ST_PIPELINE_START: begin
PIPELINE_ST <= ST_PIPELINE_START;
CACHE_TRIG_ENr <= 1'b0;
if ((cbr[15:4] == regs[PC][15:4]) & cache_flags[RESOLVED_CACHE_PC[8:4]]) begin
PIPELINE_ST <= ST_PIPELINE_END;
pipeline_cache_wait <= 1'b0;
pipeline_byte <= cache_outa;
pipeline_delay <= 3; // XXX
end
else if (cbr[15:4] == regs[PC][15:4]) begin
// Pull the block into cache. Then the branch above takes over.
if (~pipeline_cache_wait) begin
CACHE_TRIG_ENr <= 1'b1;
pipeline_cache_wait <= 1'b1;
end
end
else begin
// Read the block from gamepak ROM
PIPELINE_ST <= ST_PIPELINE_WAIT;
cpu_rom_bus_rq <= 1'b1;
cpu_rombusaddr <= {pbr, regs[PC]};
end
end
ST_PIPELINE_WAIT: begin
PIPELINE_ST <= ST_PIPELINE_WAIT;
cpu_rom_bus_rq <= 1'b0;
if (~cpu_rom_bus_rq & ROM_BUS_RDY) begin // XXX: what if cache and this are reading at the same time?
PIPELINE_ST <= ST_PIPELINE_END;
pipeline_byte <= ROM_BUS_DI;
pipeline_delay <= 3; // XXX
end
end
ST_PIPELINE_END: begin
PIPELINE_ST <= ST_PIPELINE_END;
pipeline_delay <= pipeline_delay - 1;
if (pipeline_delay == 0)
PIPELINE_ST <= sfr[G] ? ST_PIPELINE_START : ST_PIPELINE_IDLE;
end
endcase
end
// XXX: somehow move pipeline byte to current instruction when necessary
always @(posedge clkin) begin
case (state)
STATE_IDLE: begin
state <= STATE_IDLE;
if (MMIO_WR_EN) begin
casex (ADDR[9:0])
/* GPRs R0~R15
For some reason, unless these are written this way,
the code either fails to synthesize or fails timing
constraints on clkin */
10'h000: regs[0] <= {regs[0][15:8], DI};
10'h001: regs[0] <= {DI, regs[0][7:0]};
10'h002: regs[1] <= {regs[1][15:8], DI};
10'h003: regs[1] <= {DI, regs[1][7:0]};
10'h004: regs[2] <= {regs[2][15:8], DI};
10'h005: regs[2] <= {DI, regs[2][7:0]};
10'h006: regs[3] <= {regs[3][15:8], DI};
10'h007: regs[3] <= {DI, regs[3][7:0]};
10'h008: regs[4] <= {regs[4][15:8], DI};
10'h009: regs[4] <= {DI, regs[4][7:0]};
10'h00a: regs[5] <= {regs[5][15:8], DI};
10'h00b: regs[5] <= {DI, regs[5][7:0]};
10'h00c: regs[6] <= {regs[6][15:8], DI};
10'h00d: regs[6] <= {DI, regs[6][7:0]};
10'h00e: regs[7] <= {regs[7][15:8], DI};
10'h00f: regs[7] <= {DI, regs[7][7:0]};
10'h010: regs[8] <= {regs[8][15:8], DI};
10'h011: regs[8] <= {DI, regs[8][7:0]};
10'h012: regs[9] <= {regs[9][15:8], DI};
10'h013: regs[9] <= {DI, regs[9][7:0]};
10'h014: regs[10] <= {regs[10][15:8], DI};
10'h015: regs[10] <= {DI, regs[10][7:0]};
10'h016: regs[11] <= {regs[11][15:8], DI};
10'h017: regs[11] <= {DI, regs[11][7:0]};
10'h018: regs[12] <= {regs[12][15:8], DI};
10'h019: regs[12] <= {DI, regs[12][7:0]};
10'h01a: regs[13] <= {regs[13][15:8], DI};
10'h01b: regs[13] <= {DI, regs[13][7:0]};
10'h01c: begin
regs[14] <= {regs[14][15:8], DI};
// TODO: should update ROM buffer
end
10'h01d: begin
regs[14] <= {DI, regs[14][7:0]};
// TODO: should update ROM buffer
end
10'h01e: regs[15] <= {regs[15][15:8], DI};
10'h01f: begin
regs[15] <= {DI, regs[15][7:0]};
sfr[G] <= 1'b1;
state <= STATE_CPU1;
end
// Status flag register
10'h030: begin
sfr[7:0] <= {1'b0, DI[6:1], 1'b0};
if (DI[G]) begin
state <= STATE_CPU1;
end
end
10'h031: sfr[15:8] <= {DI[7], 2'b00, DI[4:0]};
//10'h032: Unused
// Back-up RAM register
10'h033: bramr <= DI[0];
// Program bank register
10'h034: pbr <= DI;
// Game Pak ROM bank register: read only
//10'h036: rombr <= DI;
// Config register:
10'h037: cfgr <= {DI[7], 1'b0, DI[5], 5'b00000};
// Screen base register
10'h038: scbr <= DI;
// Clock select register
10'h039: clsr <= DI[0];
// Screen mode register
10'h03a: scmr <= DI[5:0];
// Version code register: read only
//10'h03b: vcr <= DI;
// Game Pak RAM bank register: read only
//10'h03c: rambr <= DI[0];
//10'h03d: Unused
// Cache base register: read only
//10'h03e: cbr[7:0] <= {DI[7:4], 4'b0000};
//10'h03f: cbr[15:8] <= DI;
// Color register: no access from SNES CPU
// Plot option register: no access from SNES CPU
endcase
end
end
STATE_CPU1: begin
state <= STATE_CPU2;
src_reg_reg <= regs[src_reg];
if (curr_inst_valid[0]) begin
// First, read first byte of instruction from cache
curr_op <= curr_inst[0];
casex (cache_byte)
OP_ALT1: begin
sfr[ALT1] <= 1'b1;
sfr[ALT2] <= 1'b0;
regs[PC] <= regs[PC] + 16'h1;
end
OP_ALT2: begin
sfr[ALT1] <= 1'b0;
sfr[ALT2] <= 1'b1;
regs[PC] <= regs[PC] + 16'h1;
end
OP_ALT3: begin
sfr[ALT1] <= 1'b1;
sfr[ALT2] <= 1'b1;
regs[PC] <= regs[PC] + 16'h1;
end
OP_FROM: begin
if (~b) src_reg <= imm;
else begin
dst1 <= dst_reg;
dst1_reg <= regs[imm];
dst1_reg_assigned <= 1'b1;
if (dst_reg != PC) begin
regs[PC] <= regs[PC] + 16'h1;
end
// XXX: need to reset regs
end
end
OP_TO: begin
if (~b) dst_reg <= imm;
else begin
dst1 <= imm;
dst1_reg <= regs[src_reg];
dst1_reg_assigned <= 1'b1;
if (imm != PC) begin
regs[PC] <= regs[PC] + 16'h1;
end
// XXX: need to reset regs
end
end
OP_IWT: begin
immr4 <= imm;
regs[PC] <= regs[PC] + 16'h1;
end
OP_NOP: begin
// Just reset regs.
sfr[B] <= 1'b0;
sfr[ALT1] <= 1'b0;
sfr[ALT2] <= 1'b0;
src_reg <= 4'h0;
dst_reg <= 4'h0;
regs[PC] <= regs[PC] + 16'h1;
end
endcase
end
end
STATE_CPU2: begin
state <= STATE_CPU3;
// Wait until the second byte of the instruction is in the cache
if (cache_flag) begin
casex (curr_op)
OP_ADX: begin
if (!alt1 && !alt2) begin
// ADD Rn
res17 <= src_reg_reg + regs[imm];
end
else if (alt1 && !alt2) begin
// ADC Rn
res17 <= src_reg_reg + regs[imm] + cy;
end
else if (!alt1 && alt2) begin
// ADD #n
res17 <= src_reg_reg + imm;
end
else /* if (alt1 && alt2) */ begin
// ADC #n
res17 <= src_reg_reg + imm + cy;
end
end
OP_BEQ:
begin: op_beq_blk
/*
reg signed [7:0] tmp;
tmp = pipeline;
regs[PC] <= regs[PC] + 16'h1;
//pipeline = 8'b1; // XXX: NOP for now. Should read.
//fetch_next_cached_insn;
if (z) begin
// XXX this is ugly!
regs[PC] <= $unsigned($signed(regs[PC]) + tmp);
end
*/
end
OP_IWT: begin
immr8[0] <= cache_byte;
regs[PC] <= regs[PC] + 16'h1;
end
endcase
end
end
STATE_CPU3: begin
state <= STATE_CPU4;
// Wait until the third byte of the instruction is in the cache
if (cache_flag) begin
casex (curr_op)
OP_ADX: begin
// Set flags
sfr[OV] <= (~(src_reg_reg ^ (alt2 ? regs[imm] : imm))
& ((alt2 ? regs[imm] : imm) ^ res17)
& 16'h8000) != 0;
sfr[S] <= (res17 & 16'h8000) != 0;
sfr[CY] <= res17 >= 17'h10000;
sfr[Z] <= (res17 & 16'hffff) == 0;
// Write the result
dst1 <= dst_reg;
dst1_reg <= res17;
dst1_reg_assigned <= 1'b1;
// Increment program counter if it was not set above
if (dst_reg != PC) begin
regs[PC] <= regs[PC] + 16'h1;
end
end
OP_IWT: begin
regs[immr4] <= {immr8[0], cache_byte};
if (immr4 != PC) begin
regs[PC] <= regs[PC] + 16'h1;
end
end
endcase
end
end
STATE_CPU4: begin
state <= sfr[G] ? STATE_CPU1 : STATE_IDLE;
casex (curr_op)
OP_ADX, OP_IWT: begin
// Register reset
sfr[B] <= 1'b0;
sfr[ALT1] <= 1'b0;
sfr[ALT2] <= 1'b0;
src_reg <= 4'h0;
dst_reg <= 4'h0;
end
endcase
// Move results to destination GPRs.
if (dst1_reg_assigned) begin
regs[dst1] <= dst1_reg;
dst1_reg_assigned <= 1'b0;
end
end
endcase
end
/* MMIO read process */
always @(posedge clkin) begin
casex (ADDR[9:0])
/* GPRs R0~R15 */
10'b00000xxxx0: MMIO_DOr <= regs[ADDR[4:1]][7:0];
10'b00000xxxx1: MMIO_DOr <= regs[ADDR[4:1]][15:8];
// Status flag register
10'h030: MMIO_DOr <= sfr[7:0];
10'h031: MMIO_DOr <= sfr[15:8]; // TODO: should reset IRQ flag
//10'h032: Unused
// Back-up RAM register: write only
//10'h033: MMIO_DOr <= {7'b0000000, bramr};
// Program bank register
10'h034: MMIO_DOr <= pbr;
// Game Pak ROM bank register
10'h036: MMIO_DOr <= rombr;
// Config register: write only
//10'h037: MMIO_DOr <= cfgr;
// Screen base register: write only
//10'h038: MMIO_DOr <= scbr;
// Clock select register: write only
//10'h039: MMIO_DOr <= {7'b0000000, clsr};
// Screen mode register: write only
//10'h03a: MMIO_DOr <= {2'b00, scmr};
// Version code register
10'h03b: MMIO_DOr <= vcr;
// Game Pak RAM bank register
10'h03c: MMIO_DOr <= {7'b0000000, rambr};
//10'h03d: Unused
// Cache base register
10'h03e: MMIO_DOr <= {cbr[7:4], 4'b0000};
10'h03f: MMIO_DOr <= cbr[15:8];
// Color register: no access from SNES CPU
// Plot option register: no access from SNES CPU
default: MMIO_DOr <= 8'hff;
endcase
end
/*
// For some reason, enabling this makes timing constraints start to fail!?
always @(posedge clkin) begin
casex (ADDR[9:0])
// Cache RAM
10'h1xx, 10'h2xx: CACHE_DOr <= cache_outb;
endcase
end
*/
/* State machine for reading the gamepak ROM to CPU */
reg[2:0] ROMBUSRD_STATE;
parameter ST_ROMBUSRD_IDLE = 3'b001;
parameter ST_ROMBUSRD_WAIT = 3'b010;
parameter ST_ROMBUSRD_END = 3'b100;
initial ROMBUSRD_STATE = ST_ROMBUSRD_IDLE;
/* This is just cpu_rom_bus_rq delayed by one cycle. */
reg cpu_rom_bus_rq2;
always @(posedge clkin) cpu_rom_bus_rq2 <= cpu_rom_bus_rq;
/* This is just CACHE_ROM_BUS_RRQr delayed by one cycle. */
reg cache_rom_bus_rq2;
always @(posedge clkin) cache_rom_bus_rq2 <= CACHE_ROM_BUS_RRQr;
always @(posedge clkin) begin
case(ROMBUSRD_STATE)
ST_ROMBUSRD_IDLE: begin
if(cpu_rom_bus_rq2 | cache_rom_bus_rq2) begin
ROMBUSRD_STATE <= ST_ROMBUSRD_WAIT;
end
end
ST_ROMBUSRD_WAIT: begin
if(ROM_BUS_RDY) ROMBUSRD_STATE <= ST_ROMBUSRD_END;
else ROMBUSRD_STATE <= ST_ROMBUSRD_WAIT;
end
ST_ROMBUSRD_END: begin
/*
if(~cpu_rombusaddr[22]) cpu_rombusdata <= ROM_BUS_DI;
else cpu_rombusdata <= 8'h00;
*/
cpu_rombusdata <= ROM_BUS_DI;
/* XXX: Should we have a transition out of this state?
Note that the CX4 core has no such transition. */
ROMBUSRD_STATE <= ST_ROMBUSRD_IDLE;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_BLACKBOX_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD2_BLACKBOX_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv3sd2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD2_BLACKBOX_V
|
`default_nettype none
`include "core.h"
module execute_div(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//FLAG
output wire oFLAG_WAITING_DIV,
//Prev
input wire iPREV_VALID,
input wire iPREV_UDIV,
input wire iPREV_SDIV,
input wire [4:0] iCMD,
//iDATA
input wire [31:0] iDATA_0,
input wire [31:0] iDATA_1,
//oDATA
input wire iBUSY,
output wire oDATA_VALID,
output wire [31:0] oDATA
);
wire divider_condition = iPREV_VALID && (iPREV_UDIV || iPREV_SDIV) && !iBUSY;
wire divider_out_valid;
wire [31:0] divider_out_q;
wire [31:0] divider_out_r;
pipelined_div_radix2 EXE_DIV(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iREMOVE(iRESET_SYNC),
//Source
.oSOURCE_BUSY(/* Not Use*/),
.iSOURCE_VALID(divider_condition),
.iSOURCE_SIGN(iPREV_SDIV),
.iSOURCE_DIVIDEND(iDATA_0),
.iSOURCE_DIVISOR(iDATA_1),
//Output
.iOUT_BUSY(1'b0),
.oOUT_VALID(divider_out_valid),
.oOUT_DATA_Q(divider_out_q),
.oOUT_DATA_R(divider_out_r)
);
reg b_div_wait;
localparam PL_IDLE = 1'b0;
localparam PL_WAIT = 1'b1;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_div_wait <= 1'b0;
end
else if(iRESET_SYNC)begin
b_div_wait <= PL_IDLE;
end
else begin
case(b_div_wait)
PL_IDLE:
begin
if(divider_condition)begin
b_div_wait <= PL_WAIT;
end
end
PL_WAIT:
begin
if(divider_out_valid)begin
b_div_wait <= PL_IDLE;
end
end
endcase
end
end
reg b_div_q_r_condition;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_div_q_r_condition <= 1'b0;
end
else if(iRESET_SYNC)begin
b_div_q_r_condition <= 1'b0;
end
else begin
if(b_div_wait == PL_IDLE)begin
if(divider_condition)begin
b_div_q_r_condition <= ((iPREV_UDIV && iCMD == `EXE_DIV_UMOD || iPREV_SDIV && iCMD == `EXE_DIV_MOD))? 1'b0 : 1'b1; //0:R 1:Q
end
end
end
end
assign oDATA_VALID = divider_out_valid;
assign oDATA = (b_div_q_r_condition)? divider_out_q : divider_out_r;
assign oFLAG_WAITING_DIV = b_div_wait;
endmodule
`default_nettype wire
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_stack (clock, reset, enable, push, push_data, pop, pop_data, full, empty, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter depth = 2;
parameter width = 1;
parameter high_water_mark = 0;
parameter push_latency = 0;
parameter pop_latency = 0;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input pop, push, full, empty;
input [width-1:0] pop_data, push_data;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_STACK";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_stack_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule // ovl_stack
|
// This file has been automatically generated by goFB and should not be edited by hand
// Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
// Verilog support is EXPERIMENTAL ONLY
// This file represents the Composite Function Block for CfbTlNetwork
module FB_CfbTlNetwork
(
input wire clk,
//input events
input wire Tick_eI,
input wire Start_eI,
input wire SpecialInstr_eI,
input wire N_S_PedWaiting_eI,
input wire E_W_PedWaiting_eI,
//output events
output wire N_S_PedLightsChange_eO,
output wire N_S_TrafLightsChange_eO,
output wire E_W_PedLightsChange_eO,
output wire E_W_TrafLightsChange_eO,
//input variables
input wire N_S_HoldGreen_I,
input wire E_W_HoldGreen_I,
//output variables
output wire N_S_PedRed_O ,
output wire N_S_PedFlashRed_O ,
output wire N_S_PedGreen_O ,
output wire N_S_TrafRed_O ,
output wire N_S_TrafYellow_O ,
output wire N_S_TrafGreen_O ,
output wire E_W_PedRed_O ,
output wire E_W_PedFlashRed_O ,
output wire E_W_PedGreen_O ,
output wire E_W_TrafRed_O ,
output wire E_W_TrafYellow_O ,
output wire E_W_TrafGreen_O ,
input reset
);
//Wires needed for event connections
wire Tick_conn;
wire SpecialInstr_conn;
wire Start_conn;
wire mt_N_S_Start_conn;
wire N_S_DoneSeq_conn;
wire mt_E_W_Start_conn;
wire E_W_DoneSeq_conn;
wire N_S_PedWaiting_conn;
wire E_W_PedWaiting_conn;
wire N_S_PedLightsChange_conn;
wire N_S_TrafLightsChange_conn;
wire E_W_PedLightsChange_conn;
wire E_W_TrafLightsChange_conn;
//Wires needed for data connections
wire N_S_HoldGreen_conn;
wire E_W_HoldGreen_conn;
wire N_S_PedRed_conn;
wire N_S_PedFlashRed_conn;
wire N_S_PedGreen_conn;
wire N_S_TrafRed_conn;
wire N_S_TrafYellow_conn;
wire N_S_TrafGreen_conn;
wire E_W_PedRed_conn;
wire E_W_PedFlashRed_conn;
wire E_W_PedGreen_conn;
wire E_W_TrafRed_conn;
wire E_W_TrafYellow_conn;
wire E_W_TrafGreen_conn;
//top level I/O to signals
//input events
assign Tick_conn = Tick_eI;
assign Tick_conn = Tick_eI;
assign Start_conn = Start_eI;
assign SpecialInstr_conn = SpecialInstr_eI;
assign SpecialInstr_conn = SpecialInstr_eI;
assign N_S_PedWaiting_conn = N_S_PedWaiting_eI;
assign E_W_PedWaiting_conn = E_W_PedWaiting_eI;
//output events
assign N_S_PedLightsChange_eO = N_S_PedLightsChange_conn;
assign N_S_TrafLightsChange_eO = N_S_TrafLightsChange_conn;
assign E_W_PedLightsChange_eO = E_W_PedLightsChange_conn;
assign E_W_TrafLightsChange_eO = E_W_TrafLightsChange_conn;
//input variables
assign N_S_HoldGreen_conn = N_S_HoldGreen_I;
assign E_W_HoldGreen_conn = E_W_HoldGreen_I;
//output events
assign N_S_PedRed_O = N_S_PedRed_conn;
assign N_S_PedFlashRed_O = N_S_PedFlashRed_conn;
assign N_S_PedGreen_O = N_S_PedGreen_conn;
assign N_S_TrafRed_O = N_S_TrafRed_conn;
assign N_S_TrafYellow_O = N_S_TrafYellow_conn;
assign N_S_TrafGreen_O = N_S_TrafGreen_conn;
assign E_W_PedRed_O = E_W_PedRed_conn;
assign E_W_PedFlashRed_O = E_W_PedFlashRed_conn;
assign E_W_PedGreen_O = E_W_PedGreen_conn;
assign E_W_TrafRed_O = E_W_TrafRed_conn;
assign E_W_TrafYellow_O = E_W_TrafYellow_conn;
assign E_W_TrafGreen_O = E_W_TrafGreen_conn;
// child I/O to signals
FB_CfbOneLink N_S (
.clk(clk),
//event outputs
.DoneSeq_eO(N_S_DoneSeq_conn),
.PedLightsChange_eO(N_S_PedLightsChange_conn),
.TrafLightsChange_eO(N_S_TrafLightsChange_conn),
//event inputs
.Tick_eI(Tick_conn),
.SpecialInstr_eI(SpecialInstr_conn),
.GoSeq_eI(mt_N_S_Start_conn),
.PedWaiting_eI(N_S_PedWaiting_conn),
//data outputs
.PedRed_O(N_S_PedRed_conn),
.PedFlashRed_O(N_S_PedFlashRed_conn),
.PedGreen_O(N_S_PedGreen_conn),
.TrafRed_O(N_S_TrafRed_conn),
.TrafYellow_O(N_S_TrafYellow_conn),
.TrafGreen_O(N_S_TrafGreen_conn),
//data inputs
.HoldGreen_I(N_S_HoldGreen_conn),
.reset(reset)
);
FB_CfbOneLink E_W (
.clk(clk),
//event outputs
.DoneSeq_eO(E_W_DoneSeq_conn),
.PedLightsChange_eO(E_W_PedLightsChange_conn),
.TrafLightsChange_eO(E_W_TrafLightsChange_conn),
//event inputs
.Tick_eI(Tick_conn),
.SpecialInstr_eI(SpecialInstr_conn),
.GoSeq_eI(mt_E_W_Start_conn),
.PedWaiting_eI(E_W_PedWaiting_conn),
//data outputs
.PedRed_O(E_W_PedRed_conn),
.PedFlashRed_O(E_W_PedFlashRed_conn),
.PedGreen_O(E_W_PedGreen_conn),
.TrafRed_O(E_W_TrafRed_conn),
.TrafYellow_O(E_W_TrafYellow_conn),
.TrafGreen_O(E_W_TrafGreen_conn),
//data inputs
.HoldGreen_I(E_W_HoldGreen_conn),
.reset(reset)
);
FB_BfbIntersectionMutex mt (
.clk(clk),
//event outputs
.N_S_Start_eO(mt_N_S_Start_conn),
.E_W_Start_eO(mt_E_W_Start_conn),
//event inputs
.Start_eI(Start_conn),
.N_S_Done_eI(N_S_DoneSeq_conn),
.E_W_Done_eI(E_W_DoneSeq_conn),
//data outputs
//data inputs
.reset(reset)
);
endmodule |
module ALU (
controlALU, //Código de controle da ALU
rs, //Primeiro registrador fonte
rt, //Segundo registrador fonte
outALU, //Resultado da ALU
outBranch //Controle Branch
);
input [6:0] controlALU;
input [31:0] rs, rt;
output reg [31:0] outALU;
output reg outBranch;
localparam [4:0] ADD = 6'd1, ADDI = 6'd2,
SUB = 6'd3, SUBI = 6'd4,
MUL = 6'd5,
DIV = 6'd6,
MOD = 6'd7,
AND = 6'd8, ANDI = 6'd9,
OR = 6'd10, ORI = 6'd11,
XOR = 6'd12, XORI = 6'd13,
NOT = 6'd14,
SHL = 6'd15,
SHR = 6'd16,
BEQ = 6'd22,
BGT = 6'd23,
BGE = 6'd24,
BLT = 6'd25,
BLE = 6'd26,
BNE = 6'd27,
MOVE = 6'd28;
always @ (controlALU or rs or rt) begin
begin
if(controlALU[5:0] == ADD || controlALU[5:0] == ADDI)
outALU = rs + rt;
else if(controlALU[5:0] == SUB || controlALU[5:0] == SUBI)
outALU = rs - rt;
else if(controlALU[5:0] == MUL || controlALU[5:0] == MUL)
outALU = rs * rt;
else if(controlALU[5:0] == DIV)
outALU = rs / rt;
else if(controlALU[5:0] == MOD)
outALU = rs % rt;
else if(controlALU[5:0] == AND || controlALU[5:0] == ANDI)
outALU = (rs & rt);
else if(controlALU[5:0] == OR || controlALU[5:0] == ORI)
outALU = (rs | rt);
else if(controlALU[5:0] == XOR || controlALU[5:0] == XORI)
outALU = (rs ^ rt);
else if(controlALU[5:0] == NOT)
outALU = ~rs;
else if(controlALU[5:0] == SHL)
outALU = rs << rt;
else if(controlALU[5:0] == SHR)
outALU = rs >> rt;
else if(controlALU[5:0] == BEQ)
outALU = (rs == rt);
else if(controlALU[5:0] == BGT)
outALU = (rs > rt);
else if(controlALU[5:0] == BGE)
outALU = (rs >= rt);
else if(controlALU[5:0] == BLT)
outALU = (rs < rt);
else if(controlALU[5:0] == BLE)
outALU = (rs <= rt);
else if(controlALU[5:0] == BNE)
outALU = (rs != rt);
else if(controlALU[5:0] == MOVE)
outALU = rs;
else
outALU = rs;
end
begin
if(controlALU[5:0] == BEQ ||
controlALU[5:0] == BGT ||
controlALU[5:0] == BGE ||
controlALU[5:0] == BLT ||
controlALU[5:0] == BLE ||
controlALU[5:0] == BNE)
outBranch = 1'b1;
else
outBranch = 1'b0;
end
end
endmodule |
//======================================================================
//
// sha512_core.v
// -------------
// Verilog 2001 implementation of the SHA-512 hash function.
// This is the internal core with wide interfaces.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module sha512_core(
input wire clk,
input wire reset_n,
input wire init,
input wire next,
input wire [1 : 0] mode,
input wire work_factor,
input wire [31 : 0] work_factor_num,
input wire [1023 : 0] block,
output wire ready,
output wire [511 : 0] digest,
output wire digest_valid
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam SHA512_ROUNDS = 79;
localparam CTRL_IDLE = 2'h0;
localparam CTRL_ROUNDS = 2'h1;
localparam CTRL_DONE = 2'h2;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [63 : 0] a_reg;
reg [63 : 0] a_new;
reg [63 : 0] b_reg;
reg [63 : 0] b_new;
reg [63 : 0] c_reg;
reg [63 : 0] c_new;
reg [63 : 0] d_reg;
reg [63 : 0] d_new;
reg [63 : 0] e_reg;
reg [63 : 0] e_new;
reg [63 : 0] f_reg;
reg [63 : 0] f_new;
reg [63 : 0] g_reg;
reg [63 : 0] g_new;
reg [63 : 0] h_reg;
reg [63 : 0] h_new;
reg a_h_we;
reg [63 : 0] H0_reg;
reg [63 : 0] H0_new;
reg [63 : 0] H1_reg;
reg [63 : 0] H1_new;
reg [63 : 0] H2_reg;
reg [63 : 0] H2_new;
reg [63 : 0] H3_reg;
reg [63 : 0] H3_new;
reg [63 : 0] H4_reg;
reg [63 : 0] H4_new;
reg [63 : 0] H5_reg;
reg [63 : 0] H5_new;
reg [63 : 0] H6_reg;
reg [63 : 0] H6_new;
reg [63 : 0] H7_reg;
reg [63 : 0] H7_new;
reg H_we;
reg [6 : 0] round_ctr_reg;
reg [6 : 0] round_ctr_new;
reg round_ctr_we;
reg round_ctr_inc;
reg round_ctr_rst;
reg [31 : 0] work_factor_ctr_reg;
reg [31 : 0] work_factor_ctr_new;
reg work_factor_ctr_rst;
reg work_factor_ctr_inc;
reg work_factor_ctr_we;
reg ready_reg;
reg ready_new;
reg ready_we;
reg digest_valid_reg;
reg digest_valid_new;
reg digest_valid_we;
reg [1 : 0] sha512_ctrl_reg;
reg [1 : 0] sha512_ctrl_new;
reg sha512_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg digest_init;
reg digest_update;
reg state_init;
reg state_update;
reg first_block;
reg [63 : 0] t1;
reg [63 : 0] t2;
wire [63 : 0] k_data;
reg w_init;
reg w_next;
wire [63 : 0] w_data;
wire [63 : 0] H0_0;
wire [63 : 0] H0_1;
wire [63 : 0] H0_2;
wire [63 : 0] H0_3;
wire [63 : 0] H0_4;
wire [63 : 0] H0_5;
wire [63 : 0] H0_6;
wire [63 : 0] H0_7;
//----------------------------------------------------------------
// Module instantiantions.
//----------------------------------------------------------------
sha512_k_constants k_constants_inst(
.addr(round_ctr_reg),
.K(k_data)
);
sha512_h_constants h_constants_inst(
.mode(mode),
.H0(H0_0),
.H1(H0_1),
.H2(H0_2),
.H3(H0_3),
.H4(H0_4),
.H5(H0_5),
.H6(H0_6),
.H7(H0_7)
);
sha512_w_mem w_mem_inst(
.clk(clk),
.reset_n(reset_n),
.block(block),
.init(w_init),
.next(w_next),
.w(w_data)
);
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_reg;
assign digest = {H0_reg, H1_reg, H2_reg, H3_reg,
H4_reg, H5_reg, H6_reg, H7_reg};
assign digest_valid = digest_valid_reg;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
a_reg <= 64'h0;
b_reg <= 64'h0;
c_reg <= 64'h0;
d_reg <= 64'h0;
e_reg <= 64'h0;
f_reg <= 64'h0;
g_reg <= 64'h0;
h_reg <= 64'h0;
H0_reg <= 64'h0;
H1_reg <= 64'h0;
H2_reg <= 64'h0;
H3_reg <= 64'h0;
H4_reg <= 64'h0;
H5_reg <= 64'h0;
H6_reg <= 64'h0;
H7_reg <= 64'h0;
work_factor_ctr_reg <= 32'h0;
ready_reg <= 1'b1;
digest_valid_reg <= 1'b0;
round_ctr_reg <= 7'h0;
sha512_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (a_h_we)
begin
a_reg <= a_new;
b_reg <= b_new;
c_reg <= c_new;
d_reg <= d_new;
e_reg <= e_new;
f_reg <= f_new;
g_reg <= g_new;
h_reg <= h_new;
end
if (H_we)
begin
H0_reg <= H0_new;
H1_reg <= H1_new;
H2_reg <= H2_new;
H3_reg <= H3_new;
H4_reg <= H4_new;
H5_reg <= H5_new;
H6_reg <= H6_new;
H7_reg <= H7_new;
end
if (round_ctr_we)
round_ctr_reg <= round_ctr_new;
if (work_factor_ctr_we)
work_factor_ctr_reg <= work_factor_ctr_new;
if (ready_we)
ready_reg <= ready_new;
if (digest_valid_we)
digest_valid_reg <= digest_valid_new;
if (sha512_ctrl_we)
sha512_ctrl_reg <= sha512_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// digest_logic
//
// The logic needed to init as well as update the digest.
//----------------------------------------------------------------
always @*
begin : digest_logic
H0_new = 64'h0;
H1_new = 64'h0;
H2_new = 64'h0;
H3_new = 64'h0;
H4_new = 64'h0;
H5_new = 64'h0;
H6_new = 64'h0;
H7_new = 64'h0;
H_we = 0;
if (digest_init)
begin
H0_new = H0_0;
H1_new = H0_1;
H2_new = H0_2;
H3_new = H0_3;
H4_new = H0_4;
H5_new = H0_5;
H6_new = H0_6;
H7_new = H0_7;
H_we = 1;
end
if (digest_update)
begin
H0_new = H0_reg + a_reg;
H1_new = H1_reg + b_reg;
H2_new = H2_reg + c_reg;
H3_new = H3_reg + d_reg;
H4_new = H4_reg + e_reg;
H5_new = H5_reg + f_reg;
H6_new = H6_reg + g_reg;
H7_new = H7_reg + h_reg;
H_we = 1;
end
end // digest_logic
//----------------------------------------------------------------
// t1_logic
//
// The logic for the T1 function.
//----------------------------------------------------------------
always @*
begin : t1_logic
reg [63 : 0] sum1;
reg [63 : 0] ch;
sum1 = {e_reg[13 : 0], e_reg[63 : 14]} ^
{e_reg[17 : 0], e_reg[63 : 18]} ^
{e_reg[40 : 0], e_reg[63 : 41]};
ch = (e_reg & f_reg) ^ ((~e_reg) & g_reg);
t1 = h_reg + sum1 + ch + k_data + w_data;
end // t1_logic
//----------------------------------------------------------------
// t2_logic
//
// The logic for the T2 function
//----------------------------------------------------------------
always @*
begin : t2_logic
reg [63 : 0] sum0;
reg [63 : 0] maj;
sum0 = {a_reg[27 : 0], a_reg[63 : 28]} ^
{a_reg[33 : 0], a_reg[63 : 34]} ^
{a_reg[38 : 0], a_reg[63 : 39]};
maj = (a_reg & b_reg) ^ (a_reg & c_reg) ^ (b_reg & c_reg);
t2 = sum0 + maj;
end // t2_logic
//----------------------------------------------------------------
// state_logic
//
// The logic needed to init as well as update the state during
// round processing.
//----------------------------------------------------------------
always @*
begin : state_logic
a_new = 64'h0;
b_new = 64'h0;
c_new = 64'h0;
d_new = 64'h0;
e_new = 64'h0;
f_new = 64'h0;
g_new = 64'h0;
h_new = 64'h0;
a_h_we = 0;
if (state_init)
begin
if (first_block)
begin
a_new = H0_0;
b_new = H0_1;
c_new = H0_2;
d_new = H0_3;
e_new = H0_4;
f_new = H0_5;
g_new = H0_6;
h_new = H0_7;
a_h_we = 1;
end
else
begin
a_new = H0_reg;
b_new = H1_reg;
c_new = H2_reg;
d_new = H3_reg;
e_new = H4_reg;
f_new = H5_reg;
g_new = H6_reg;
h_new = H7_reg;
a_h_we = 1;
end
end
if (state_update)
begin
a_new = t1 + t2;
b_new = a_reg;
c_new = b_reg;
d_new = c_reg;
e_new = d_reg + t1;
f_new = e_reg;
g_new = f_reg;
h_new = g_reg;
a_h_we = 1;
end
end // state_logic
//----------------------------------------------------------------
// round_ctr
//
// Update logic for the round counter, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : round_ctr
round_ctr_new = 7'h00;
round_ctr_we = 0;
if (round_ctr_rst)
begin
round_ctr_new = 7'h00;
round_ctr_we = 1;
end
if (round_ctr_inc)
begin
round_ctr_new = round_ctr_reg + 1'b1;
round_ctr_we = 1;
end
end // round_ctr
//----------------------------------------------------------------
// work_factor_ctr
//
// Work factor counter logic.
//----------------------------------------------------------------
always @*
begin : work_factor_ctr
work_factor_ctr_new = 32'h0;
work_factor_ctr_we = 0;
if (work_factor_ctr_rst)
begin
work_factor_ctr_new = 32'h0;
work_factor_ctr_we = 1;
end
if (work_factor_ctr_inc)
begin
work_factor_ctr_new = work_factor_ctr_reg + 1'b1;
work_factor_ctr_we = 1;
end
end // work_factor_ctr
//----------------------------------------------------------------
// sha512_ctrl_fsm
//
// Logic for the state machine controlling the core behaviour.
//----------------------------------------------------------------
always @*
begin : sha512_ctrl_fsm
digest_init = 1'b0;
digest_update = 1'b0;
state_init = 1'b0;
state_update = 1'b0;
first_block = 1'b0;
w_init = 1'b0;
w_next = 1'b0;
round_ctr_inc = 1'b0;
round_ctr_rst = 1'b0;
digest_valid_new = 1'b0;
digest_valid_we = 1'b0;
work_factor_ctr_rst = 1'b0;
work_factor_ctr_inc = 1'b0;
ready_new = 1'b0;
ready_we = 1'b0;
sha512_ctrl_new = CTRL_IDLE;
sha512_ctrl_we = 1'b0;
case (sha512_ctrl_reg)
CTRL_IDLE:
begin
if (init)
begin
ready_new = 1'b0;
ready_we = 1'b1;
work_factor_ctr_rst = 1;
digest_init = 1;
w_init = 1;
state_init = 1;
first_block = 1;
round_ctr_rst = 1;
digest_valid_new = 0;
digest_valid_we = 1;
sha512_ctrl_new = CTRL_ROUNDS;
sha512_ctrl_we = 1;
end
if (next)
begin
ready_new = 1'b0;
ready_we = 1'b1;
work_factor_ctr_rst = 1;
w_init = 1;
state_init = 1;
round_ctr_rst = 1;
digest_valid_new = 0;
digest_valid_we = 1;
sha512_ctrl_new = CTRL_ROUNDS;
sha512_ctrl_we = 1;
end
end
CTRL_ROUNDS:
begin
w_next = 1;
state_update = 1;
round_ctr_inc = 1;
if (round_ctr_reg == SHA512_ROUNDS)
begin
work_factor_ctr_inc = 1;
sha512_ctrl_new = CTRL_DONE;
sha512_ctrl_we = 1;
end
end
CTRL_DONE:
begin
if (work_factor)
begin
if (work_factor_ctr_reg < work_factor_num)
begin
w_init = 1'b1;
state_init = 1'b1;
round_ctr_rst = 1'b1;
sha512_ctrl_new = CTRL_ROUNDS;
sha512_ctrl_we = 1'b1;
end
else
begin
ready_new = 1'b1;
ready_we = 1'b1;
digest_update = 1'b1;
digest_valid_new = 1'b1;
digest_valid_we = 1'b1;
sha512_ctrl_new = CTRL_IDLE;
sha512_ctrl_we = 1'b1;
end
end
else
begin
ready_new = 1'b1;
ready_we = 1'b1;
digest_update = 1'b1;
digest_valid_new = 1'b1;
digest_valid_we = 1'b1;
sha512_ctrl_new = CTRL_IDLE;
sha512_ctrl_we = 1'b1;
end
end
default:
begin
end
endcase // case (sha512_ctrl_reg)
end // sha512_ctrl_fsm
endmodule // sha512_core
//======================================================================
// EOF sha512_core.v
//======================================================================
|
(** * Rel: Properties of Relations *)
(* $Date: 2012-04-23 14:08:14 -0400 (Mon, 23 Apr 2012) $ *)
Require Export SfLib.
(** A (binary) _relation_ is just a parameterized proposition. As you know
from your undergraduate discrete math course, there are a lot of
ways of discussing and describing relations _in general_ -- ways
of classifying relations (are they reflexive, transitive, etc.),
theorems that can be proved generically about classes of
relations, constructions that build one relation from another,
etc. Let us pause here to review a few that will be useful in
what follows. *)
(** A (binary) relation _on_ a set [X] is a proposition parameterized by two
[X]s -- i.e., it is a logical assertion involving two values from
the set [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Somewhat confusingly, the Coq standard library hijacks the generic
term "relation" for this specific instance. To maintain
consistency with the library, we will do the same. So, henceforth
the Coq identifier [relation] will always refer to a binary
relation between some set and itself, while the English word
"relation" can refer either to the specific Coq concept or the
more general concept of a relation between any number of possibly
different sets. The context of the discussion should always make
clear which is meant. *)
(** An example relation on [nat] is [le], the less-that-or-equal-to
relation which we usually write like this [n1 <= n2]. *)
Print le.
(* ====>
Inductive le (n : nat) : nat -> Prop :=
le_n : n <= n
| le_S : forall m : nat, n <= m -> n <= S m
*)
Check le : nat -> nat -> Prop.
Check le : relation nat.
(* ######################################################### *)
(** * Basic Properties of Relations *)
(** A relation [R] on a set [X] is a _partial function_ if, for every
[x], there is at most one [y] such that [R x y] -- i.e., if [R x
y1] and [R x y2] together imply [y1 = y2]. *)
Definition partial_function {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
(** For example, the [next_nat] relation defined in Logic.v is a
partial function. *)
(* Print next_nat.
(* ====>
Inductive next_nat (n : nat) : nat -> Prop :=
nn : next_nat n (S n)
*)
Check next_nat : relation nat.
Theorem next_nat_partial_function :
partial_function next_nat.
Proof.
unfold partial_function.
intros x y1 y2 H1 H2.
inversion H1. inversion H2.
reflexivity. Qed. *)
(** However, the [<=] relation on numbers is not a partial function.
This can be shown by contradiction. In short: Assume, for a
contradiction, that [<=] is a partial function. But then, since
[0 <= 0] and [0 <= 1], it follows that [0 = 1]. This is nonsense,
so our assumption was contradictory. *)
Theorem le_not_a_partial_function :
~ (partial_function le).
Proof.
unfold not. unfold partial_function. intros Hc.
assert (0 = 1) as Nonsense.
Case "Proof of assertion".
apply Hc with (x := 0).
apply le_n.
apply le_S. apply le_n.
inversion Nonsense. Qed.
(** **** Exercise: 2 stars, optional *)
(** Show that the [total_relation] defined in Logic.v is not a partial
function. *)
Theorem total_not_a_partial_function :
~ (partial_function total_relation).
Proof.
unfold not. unfold partial_function. intros Hc.
assert (0 = 1) as Nonsense.
apply Hc with (x := 0).
apply tot.
apply tot.
inversion Nonsense.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Show that the [empty_relation] defined in Logic.v is a partial
function. *)
Theorem empty_a_partial_function :
partial_function empty_relation.
Proof.
unfold partial_function. intros x y1 y2 H1 H2. inversion H1.
Qed.
(** [] *)
(** A _reflexive_ relation on a set [X] is one for which every element
of [X] is related to itself. *)
Definition reflexive {X: Type} (R: relation X) :=
forall a : X, R a a.
Theorem le_reflexive :
reflexive le.
Proof.
unfold reflexive. intros n. apply le_n. Qed.
(** A relation [R] is _transitive_ if [R a c] holds whenever [R a b]
and [R b c] do. *)
Definition transitive {X: Type} (R: relation X) :=
forall a b c : X, (R a b) -> (R b c) -> (R a c).
Theorem le_trans :
transitive le.
Proof.
intros n m o Hnm Hmo.
induction Hmo.
Case "le_n". apply Hnm.
Case "le_S". apply le_S. apply IHHmo. Qed.
Theorem lt_trans:
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
apply le_S in Hnm.
apply le_trans with (a := (S n)) (b := (S m)) (c := o).
apply Hnm.
apply Hmo. Qed.
(** **** Exercise: 2 stars, optional *)
(** We can also prove [lt_trans] more laboriously by induction,
without using le_trans. Do this.*)
Theorem lt_trans' :
transitive lt.
Proof.
(* Prove this by induction on evidence that [m] is less than [o]. *)
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction Hmo as [| m' Hm'o];
apply le_S; assumption.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Prove the same thing again by induction on [o]. *)
Theorem lt_trans'' :
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction o as [| o'].
inversion Hmo.
inversion Hmo; subst.
apply le_S. assumption.
apply le_S. apply IHo'. assumption.
Qed.
(** [] *)
(** The transitivity of [le], in turn, can be used to prove some facts
that will be useful later (e.g., for the proof of antisymmetry
below)... *)
Theorem le_Sn_le : forall n m, S n <= m -> n <= m.
Proof.
intros n m H. apply le_trans with (S n).
apply le_S. apply le_n.
apply H. Qed.
(** **** Exercise: 1 star, optional *)
Theorem le_S_n : forall n m,
(S n <= S m) -> (n <= m).
Proof.
intros. inversion H; subst.
reflexivity.
apply le_Sn_le. assumption.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (le_Sn_n_inf) *)
(** Provide an informal proof of the following theorem:
Theorem: For every [n], [~(S n <= n)]
A formal proof of this is an optional exercise below, but try
the informal proof without doing the formal proof first.
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 1 star, optional *)
Theorem le_Sn_n : forall n,
~ (S n <= n).
Proof.
unfold not. intros.
induction n as [| n'].
Case "n = 0".
inversion H.
Case "n = S n'".
apply le_S_n in H. apply IHn'. assumption.
Qed.
(** [] *)
(** Reflexivity and transitivity are the main concepts we'll need for
later chapters, but, for a bit of additional practice working with
relations in Coq, here are a few more common ones.
A relation [R] is _symmetric_ if [R a b] implies [R b a]. *)
Definition symmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a).
(** **** Exercise: 2 stars, optional *)
Theorem le_not_symmetric :
~ (symmetric le).
Proof.
unfold not. unfold symmetric. intros.
assert (2 <= 1) by (apply H; omega).
assert (~ (2 <= 1)) by apply le_Sn_n.
contradiction.
Qed.
(** [] *)
(** A relation [R] is _antisymmetric_ if [R a b] and [R b a] together
imply [a = b] -- that is, if the only "cycles" in [R] are trivial
ones. *)
Definition antisymmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a) -> a = b.
(** **** Exercise: 2 stars, optional *)
Theorem le_antisymmetric :
antisymmetric le.
Proof.
unfold antisymmetric. intros. omega.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional *)
Theorem le_step : forall n m p,
n < m ->
m <= S p ->
n <= p.
Proof.
intros. omega.
Qed.
(** [] *)
(** A relation is an _equivalence_ if it's reflexive, symmetric, and
transitive. *)
Definition equivalence {X:Type} (R: relation X) :=
(reflexive R) /\ (symmetric R) /\ (transitive R).
(** A relation is a _partial order_ when it's reflexive,
_anti_-symmetric, and transitive. In the Coq standard library
it's called just "order" for short. *)
Definition order {X:Type} (R: relation X) :=
(reflexive R) /\ (antisymmetric R) /\ (transitive R).
(** A preorder is almost like a partial order, but doesn't have to be
antisymmetric. *)
Definition preorder {X:Type} (R: relation X) :=
(reflexive R) /\ (transitive R).
Theorem le_order :
order le.
Proof.
unfold order. split.
Case "refl". apply le_reflexive.
split.
Case "antisym". apply le_antisymmetric.
Case "transitive.". apply le_trans. Qed.
(* ########################################################### *)
(** * Reflexive, Transitive Closure *)
(** The _reflexive, transitive closure_ of a relation [R] is the
smallest relation that contains [R] and that is both reflexive and
transitive. Formally, it is defined like this in the Relations
module of the Coq standard library: *)
Inductive clos_refl_trans {A: Type} (R: relation A) : relation A :=
| rt_step : forall x y, R x y -> clos_refl_trans R x y
| rt_refl : forall x, clos_refl_trans R x x
| rt_trans : forall x y z,
clos_refl_trans R x y ->
clos_refl_trans R y z ->
clos_refl_trans R x z.
(** For example, the reflexive and transitive closure of the
[next_nat] relation coincides with the [le] relation. *)
Theorem next_nat_closure_is_le : forall n m,
(n <= m) <-> ((clos_refl_trans next_nat) n m).
Proof.
intros n m. split.
Case "->".
intro H. induction H.
SCase "le_n". apply rt_refl.
SCase "le_S".
apply rt_trans with m. apply IHle. apply rt_step. apply nn.
Case "<-".
intro H. induction H.
SCase "rt_step". inversion H. apply le_S. apply le_n.
SCase "rt_refl". apply le_n.
SCase "rt_trans".
apply le_trans with y.
apply IHclos_refl_trans1.
apply IHclos_refl_trans2. Qed.
(** The above definition of reflexive, transitive closure is
natural -- it says, explicitly, that the reflexive and transitive
closure of [R] is the least relation that includes [R] and that is
closed under rules of reflexivity and transitivity. But it turns
out that this definition is not very convenient for doing
proofs -- the "nondeterminism" of the [rt_trans] rule can sometimes
lead to tricky inductions.
Here is a more useful definition... *)
Inductive refl_step_closure {X:Type} (R: relation X) : relation X :=
| rsc_refl : forall (x : X), refl_step_closure R x x
| rsc_step : forall (x y z : X),
R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
(** (Note that, aside from the naming of the constructors, this
definition is the same as the [multi] step relation used in many
other chapters.) *)
(** (The following [Tactic Notation] definitions are explained in
Imp.v. You can ignore them if you haven't read that chapter
yet.) *)
Tactic Notation "rt_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "rt_step" | Case_aux c "rt_refl"
| Case_aux c "rt_trans" ].
Tactic Notation "rsc_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "rsc_refl" | Case_aux c "rsc_step" ].
(** Our new definition of reflexive, transitive closure "bundles"
the [rt_step] and [rt_trans] rules into the single rule step.
The left-hand premise of this step is a single use of [R],
leading to a much simpler induction principle.
Before we go on, we should check that the two definitions do
indeed define the same relation...
First, we prove two lemmas showing that [refl_step_closure] mimics
the behavior of the two "missing" [clos_refl_trans]
constructors. *)
Theorem rsc_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> refl_step_closure R x y.
Proof.
intros X R x y H.
apply rsc_step with y. apply H. apply rsc_refl. Qed.
(** **** Exercise: 2 stars, optional (rsc_trans) *)
Theorem rsc_trans :
forall (X:Type) (R: relation X) (x y z : X),
refl_step_closure R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
Proof.
intros X R x y z Hxy Hyz.
rsc_cases (induction Hxy) Case.
Case "rsc_refl".
assumption.
Case "rsc_step".
apply rsc_step with y.
assumption.
apply IHHxy. assumption.
Qed.
(** [] *)
(** Then we use these facts to prove that the two definitions of
reflexive, transitive closure do indeed define the same
relation. *)
(** **** Exercise: 3 stars, optional (rtc_rsc_coincide) *)
Theorem rtc_rsc_coincide :
forall (X:Type) (R: relation X) (x y : X),
clos_refl_trans R x y <-> refl_step_closure R x y.
Proof.
intros X R x y. split; intro H.
Case "->".
rt_cases (induction H) SCase.
SCase "rt_step".
apply rsc_R. assumption.
SCase "rt_refl".
apply rsc_refl.
SCase "rt_trans".
apply rsc_trans with y; assumption.
Case "<-".
rsc_cases (induction H) SCase.
SCase "rsc_refl".
apply rt_refl.
SCase "rsc_step".
assert (clos_refl_trans R x y) by (apply rt_step; assumption).
apply rt_trans with y; assumption.
Qed.
(** [] *)
|
`timescale 1ns / 1ps
module spi_trx_t;
// ins
reg clk;
parameter TCLK = 20;
initial clk = 0;
always #(TCLK/2) clk = ~clk;
reg sck;
parameter TCLK_SCK = 55;
reg mosi;
reg ss;
reg [7:0] data_i;
reg ack_i;
spi_trx uut(
.clk(clk),
.sck(sck),
.mosi(mosi),
.ss(ss),
.data_i(data_i),
.ack_i(ack_i));
task spi_cycle;
input wire [7:0] data;
begin
mosi = data[7];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[6];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[5];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[4];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[3];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[2];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[1];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[0];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
end
endtask
initial begin
$dumpfile("spi_trx_t.lxt");
$dumpvars(0, spi_trx_t);
sck = 0;
mosi = 0;
ss = 1;
ack_i = 0;
#(TCLK*3);
data_i = 8'b10101011;
ack_i = 1;
#(TCLK);
ack_i = 0;
#(TCLK);
ss = 0;
spi_cycle(8'hab);
spi_cycle(8'hcd);
spi_cycle(8'hef);
#(TCLK*3);
$finish(2);
end
always @(posedge clk) begin
if(uut.ack_pop_o)
$display("uut.data_o: %x", uut.data_o);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__TAPVGND_PP_SYMBOL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__tapvgnd (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND_PP_SYMBOL_V
|
`timescale 1 ns / 1 ps
module MotorFeedback_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 5
)
(
// Users to add ports here
input wire m1_feedback,
input wire m2_feedback,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
MotorFeedback_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) MotorFeedback_v1_0_S00_AXI_inst (
.m1_feedback(m1_feedback),
.m2_feedback(m2_feedback),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:15:16 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61,
n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75,
n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89,
n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102,
n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, n113,
n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124,
n125, n126;
NAND2XLTS U52 ( .A(n108), .B(n107), .Y(n109) );
NAND2X1TS U53 ( .A(n118), .B(n116), .Y(n104) );
OR2X2TS U54 ( .A(n61), .B(in1[11]), .Y(n97) );
OAI21X1TS U55 ( .A0(n37), .A1(in2[14]), .B0(add_sub), .Y(n36) );
XOR2X1TS U56 ( .A(n60), .B(in2[11]), .Y(n61) );
NAND2BX2TS U57 ( .AN(in2[13]), .B(n39), .Y(n37) );
NAND2X1TS U58 ( .A(n56), .B(add_sub), .Y(n57) );
NOR2X1TS U59 ( .A(n44), .B(n34), .Y(n45) );
NOR2X6TS U60 ( .A(n78), .B(in2[4]), .Y(n81) );
NOR2XLTS U61 ( .A(n48), .B(n34), .Y(n49) );
NAND2X1TS U62 ( .A(n63), .B(in1[12]), .Y(n101) );
XOR2X1TS U63 ( .A(n124), .B(n123), .Y(res[15]) );
XOR2X1TS U64 ( .A(n95), .B(n94), .Y(res[10]) );
NOR2X6TS U65 ( .A(n50), .B(in2[6]), .Y(n48) );
AOI21X2TS U66 ( .A0(n119), .A1(n118), .B0(n117), .Y(n124) );
OR2X2TS U67 ( .A(n63), .B(in1[12]), .Y(n43) );
XNOR2X2TS U68 ( .A(n42), .B(in2[12]), .Y(n63) );
XNOR2X2TS U69 ( .A(n38), .B(in2[14]), .Y(n68) );
NOR2X2TS U70 ( .A(n39), .B(n34), .Y(n40) );
NOR2X4TS U71 ( .A(n56), .B(in2[10]), .Y(n59) );
AOI21X2TS U72 ( .A0(n108), .A1(n105), .B0(n65), .Y(n66) );
NAND2X2TS U73 ( .A(n68), .B(in1[14]), .Y(n116) );
NAND2X2TS U74 ( .A(n108), .B(n43), .Y(n67) );
NAND2X2TS U75 ( .A(n41), .B(add_sub), .Y(n42) );
NOR2X4TS U76 ( .A(n53), .B(in1[9]), .Y(n86) );
NOR2X4TS U77 ( .A(n69), .B(in1[15]), .Y(n120) );
XOR2X1TS U78 ( .A(n90), .B(n89), .Y(res[9]) );
XOR2X2TS U79 ( .A(n40), .B(in2[13]), .Y(n64) );
INVX2TS U80 ( .A(n112), .Y(n85) );
XNOR2X2TS U81 ( .A(n47), .B(in2[8]), .Y(n52) );
NAND2BXLTS U82 ( .AN(in1[5]), .B(n83), .Y(res[5]) );
NAND2BXLTS U83 ( .AN(in1[4]), .B(n80), .Y(res[4]) );
XOR2X1TS U84 ( .A(n79), .B(in2[4]), .Y(n80) );
OAI21XLTS U85 ( .A0(in2[2]), .A1(n75), .B0(n74), .Y(res[2]) );
OAI21XLTS U86 ( .A0(in2[1]), .A1(n73), .B0(n72), .Y(res[1]) );
OAI21XLTS U87 ( .A0(in2[3]), .A1(n77), .B0(n76), .Y(res[3]) );
INVX4TS U88 ( .A(add_sub), .Y(n34) );
OR2X1TS U89 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
NOR2X4TS U90 ( .A(n41), .B(in2[12]), .Y(n39) );
AOI21X4TS U91 ( .A0(n55), .A1(n115), .B0(n54), .Y(n95) );
NAND2BX4TS U92 ( .AN(in2[7]), .B(n48), .Y(n46) );
XNOR2X2TS U93 ( .A(n36), .B(in2[15]), .Y(n69) );
XOR2X1TS U94 ( .A(n51), .B(in2[6]), .Y(n111) );
NAND2X1TS U95 ( .A(n113), .B(n112), .Y(n114) );
NAND2X1TS U96 ( .A(n97), .B(n96), .Y(n98) );
NAND2X1TS U97 ( .A(n43), .B(n101), .Y(n102) );
INVX2TS U98 ( .A(n34), .Y(n35) );
NAND2X2TS U99 ( .A(n46), .B(add_sub), .Y(n47) );
ADDFHX2TS U100 ( .A(n126), .B(in1[7]), .CI(n125), .CO(n115), .S(res[7]) );
AOI21X4TS U101 ( .A0(n99), .A1(n97), .B0(n62), .Y(n100) );
NAND2BX4TS U102 ( .AN(in2[9]), .B(n44), .Y(n56) );
XOR2X4TS U103 ( .A(n45), .B(in2[9]), .Y(n53) );
NAND2X2TS U104 ( .A(n37), .B(add_sub), .Y(n38) );
OAI21X4TS U105 ( .A0(n67), .A1(n100), .B0(n66), .Y(n119) );
NOR2XLTS U106 ( .A(n81), .B(n34), .Y(n82) );
OR4X6TS U107 ( .A(in2[3]), .B(in2[2]), .C(in2[1]), .D(in2[0]), .Y(n78) );
NAND2BX4TS U108 ( .AN(in2[5]), .B(n81), .Y(n50) );
NOR2X8TS U109 ( .A(n46), .B(in2[8]), .Y(n44) );
NAND2BX4TS U110 ( .AN(in2[11]), .B(n59), .Y(n41) );
NOR2X2TS U111 ( .A(n68), .B(in1[14]), .Y(n103) );
NOR2X1TS U112 ( .A(n120), .B(n103), .Y(n71) );
OR2X2TS U113 ( .A(n64), .B(in1[13]), .Y(n108) );
NOR2X2TS U114 ( .A(n52), .B(in1[8]), .Y(n84) );
NOR2X1TS U115 ( .A(n86), .B(n84), .Y(n55) );
XOR2X1TS U116 ( .A(n49), .B(in2[7]), .Y(n126) );
NAND2X1TS U117 ( .A(n50), .B(n35), .Y(n51) );
NOR2BX1TS U118 ( .AN(in1[6]), .B(n111), .Y(n125) );
NAND2X2TS U119 ( .A(n52), .B(in1[8]), .Y(n112) );
NAND2X2TS U120 ( .A(n53), .B(in1[9]), .Y(n87) );
OAI21X1TS U121 ( .A0(n86), .A1(n112), .B0(n87), .Y(n54) );
XNOR2X1TS U122 ( .A(n57), .B(in2[10]), .Y(n58) );
NOR2X2TS U123 ( .A(n58), .B(in1[10]), .Y(n91) );
NAND2X2TS U124 ( .A(n58), .B(in1[10]), .Y(n92) );
OAI21X4TS U125 ( .A0(n95), .A1(n91), .B0(n92), .Y(n99) );
NOR2X1TS U126 ( .A(n59), .B(n34), .Y(n60) );
NAND2X2TS U127 ( .A(n61), .B(in1[11]), .Y(n96) );
INVX2TS U128 ( .A(n96), .Y(n62) );
INVX2TS U129 ( .A(n101), .Y(n105) );
NAND2X2TS U130 ( .A(n64), .B(in1[13]), .Y(n107) );
INVX2TS U131 ( .A(n107), .Y(n65) );
NAND2X2TS U132 ( .A(n69), .B(in1[15]), .Y(n121) );
OAI21X1TS U133 ( .A0(n120), .A1(n116), .B0(n121), .Y(n70) );
AO21X2TS U134 ( .A0(n71), .A1(n119), .B0(n70), .Y(res[16]) );
NAND2X1TS U135 ( .A(in2[0]), .B(add_sub), .Y(n73) );
AOI21X1TS U136 ( .A0(in2[1]), .A1(n73), .B0(in1[1]), .Y(n72) );
OAI21X1TS U137 ( .A0(in2[1]), .A1(in2[0]), .B0(add_sub), .Y(n75) );
AOI21X1TS U138 ( .A0(in2[2]), .A1(n75), .B0(in1[2]), .Y(n74) );
OAI31X1TS U139 ( .A0(in2[2]), .A1(in2[1]), .A2(in2[0]), .B0(add_sub), .Y(n77) );
AOI21X1TS U140 ( .A0(in2[3]), .A1(n77), .B0(in1[3]), .Y(n76) );
NAND2X1TS U141 ( .A(n78), .B(add_sub), .Y(n79) );
XNOR2X1TS U142 ( .A(n82), .B(in2[5]), .Y(n83) );
INVX2TS U143 ( .A(n84), .Y(n113) );
AOI21X1TS U144 ( .A0(n115), .A1(n113), .B0(n85), .Y(n90) );
INVX2TS U145 ( .A(n86), .Y(n88) );
NAND2X1TS U146 ( .A(n88), .B(n87), .Y(n89) );
INVX2TS U147 ( .A(n91), .Y(n93) );
NAND2X1TS U148 ( .A(n93), .B(n92), .Y(n94) );
XNOR2X1TS U149 ( .A(n99), .B(n98), .Y(res[11]) );
INVX2TS U150 ( .A(n100), .Y(n106) );
XNOR2X1TS U151 ( .A(n106), .B(n102), .Y(res[12]) );
INVX2TS U152 ( .A(n103), .Y(n118) );
XNOR2X1TS U153 ( .A(n119), .B(n104), .Y(res[14]) );
AOI21X1TS U154 ( .A0(n106), .A1(n43), .B0(n105), .Y(n110) );
XOR2X1TS U155 ( .A(n110), .B(n109), .Y(res[13]) );
NAND2BXLTS U156 ( .AN(in1[6]), .B(n111), .Y(res[6]) );
XNOR2X1TS U157 ( .A(n115), .B(n114), .Y(res[8]) );
INVX2TS U158 ( .A(n116), .Y(n117) );
INVX2TS U159 ( .A(n120), .Y(n122) );
NAND2X2TS U160 ( .A(n122), .B(n121), .Y(n123) );
initial $sdf_annotate("Approx_adder_LOALPL7_syn.sdf");
endmodule
|
module flappy_bird(
//////////////////// Clock Input ////////////////////
CLOCK_27, // On Board 27 MHz
CLOCK_50, // On Board 50 MHz
EXT_CLOCK, // External Clock
//////////////////// Push Button ////////////////////
KEY, // Pushbutton[3:0]
//////////////////// DPDT Switch ////////////////////
SW, // Toggle Switch[17:0]
//////////////////// 7-SEG Dispaly ////////////////////
HEX0, // Seven Segment Digit 0
HEX1, // Seven Segment Digit 1
HEX2, // Seven Segment Digit 2
HEX3, // Seven Segment Digit 3
HEX4, // Seven Segment Digit 4
HEX5, // Seven Segment Digit 5
HEX6, // Seven Segment Digit 6
HEX7, // Seven Segment Digit 7
//////////////////////// LED ////////////////////////
LEDG, // LED Green[8:0]
LEDR, // LED Red[17:0]
//////////////////////// UART ////////////////////////
UART_TXD, // UART Transmitter
UART_RXD, // UART Receiver
//////////////////////// IRDA ////////////////////////
IRDA_TXD, // IRDA Transmitter
IRDA_RXD, // IRDA Receiver
///////////////////// SDRAM Interface ////////////////
DRAM_DQ, // SDRAM Data bus 16 Bits
DRAM_ADDR, // SDRAM Address bus 12 Bits
DRAM_LDQM, // SDRAM Low-byte Data Mask
DRAM_UDQM, // SDRAM High-byte Data Mask
DRAM_WE_N, // SDRAM Write Enable
DRAM_CAS_N, // SDRAM Column Address Strobe
DRAM_RAS_N, // SDRAM Row Address Strobe
DRAM_CS_N, // SDRAM Chip Select
DRAM_BA_0, // SDRAM Bank Address 0
DRAM_BA_1, // SDRAM Bank Address 1
DRAM_CLK, // SDRAM Clock
DRAM_CKE, // SDRAM Clock Enable
//////////////////// Flash Interface ////////////////
FL_DQ, // FLASH Data bus 8 Bits
FL_ADDR, // FLASH Address bus 20 Bits
FL_WE_N, // FLASH Write Enable
FL_RST_N, // FLASH Reset
FL_OE_N, // FLASH Output Enable
FL_CE_N, // FLASH Chip Enable
//////////////////// SRAM Interface ////////////////
SRAM_DQ, // SRAM Data bus 16 Bits
SRAM_ADDR, // SRAM Address bus 18 Bits
SRAM_UB_N, // SRAM High-byte Data Mask
SRAM_LB_N, // SRAM Low-byte Data Mask
SRAM_WE_N, // SRAM Write Enable
SRAM_CE_N, // SRAM Chip Enable
SRAM_OE_N, // SRAM Output Enable
//////////////////// ISP1362 Interface ////////////////
OTG_DATA, // ISP1362 Data bus 16 Bits
OTG_ADDR, // ISP1362 Address 2 Bits
OTG_CS_N, // ISP1362 Chip Select
OTG_RD_N, // ISP1362 Write
OTG_WR_N, // ISP1362 Read
OTG_RST_N, // ISP1362 Reset
OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
OTG_INT0, // ISP1362 Interrupt 0
OTG_INT1, // ISP1362 Interrupt 1
OTG_DREQ0, // ISP1362 DMA Request 0
OTG_DREQ1, // ISP1362 DMA Request 1
OTG_DACK0_N, // ISP1362 DMA Acknowledge 0
OTG_DACK1_N, // ISP1362 DMA Acknowledge 1
//////////////////// LCD Module 16X2 ////////////////
LCD_ON, // LCD Power ON/OFF
LCD_BLON, // LCD Back Light ON/OFF
LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
LCD_EN, // LCD Enable
LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
LCD_DATA, // LCD Data bus 8 bits
//////////////////// SD_Card Interface ////////////////
SD_DAT, // SD Card Data
SD_WP_N, // SD Write protect
SD_CMD, // SD Card Command Signal
SD_CLK, // SD Card Clock
//////////////////// USB JTAG link ////////////////////
TDI, // CPLD -> FPGA (Data in)
TCK, // CPLD -> FPGA (Clock)
TCS, // CPLD -> FPGA (CS)
TDO, // FPGA -> CPLD (Data out)
//////////////////// I2C ////////////////////////////
I2C_SDAT, // I2C Data
I2C_SCLK, // I2C Clock
//////////////////// PS2 ////////////////////////////
PS2_DAT, // PS2 Data
PS2_CLK, // PS2 Clock
//////////////////// VGA ////////////////////////////
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK, // VGA BLANK
VGA_SYNC, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B, // VGA Blue[9:0]
//////////// Ethernet Interface ////////////////////////
ENET_DATA, // DM9000A DATA bus 16Bits
ENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
ENET_CS_N, // DM9000A Chip Select
ENET_WR_N, // DM9000A Write
ENET_RD_N, // DM9000A Read
ENET_RST_N, // DM9000A Reset
ENET_INT, // DM9000A Interrupt
ENET_CLK, // DM9000A Clock 25 MHz
//////////////// Audio CODEC ////////////////////////
AUD_ADCLRCK, // Audio CODEC ADC LR Clock
AUD_ADCDAT, // Audio CODEC ADC Data
AUD_DACLRCK, // Audio CODEC DAC LR Clock
AUD_DACDAT, // Audio CODEC DAC Data
AUD_BCLK, // Audio CODEC Bit-Stream Clock
AUD_XCK, // Audio CODEC Chip Clock
//////////////// TV Decoder ////////////////////////
TD_DATA, // TV Decoder Data bus 8 bits
TD_HS, // TV Decoder H_SYNC
TD_VS, // TV Decoder V_SYNC
TD_RESET, // TV Decoder Reset
TD_CLK, // TV Decoder Line Locked Clock
//iTD_CLK, // TV Decoder Line Locked Clock
//////////////////// GPIO ////////////////////////////
GPIO_0, // GPIO Connection 0
GPIO_1 // GPIO Connection 1
);
//////////////////////// Clock Input ////////////////////////
input CLOCK_27; // On Board 27 MHz
input CLOCK_50; // On Board 50 MHz
input EXT_CLOCK; // External Clock
//////////////////////// Push Button ////////////////////////
input [3:0] KEY; // Pushbutton[3:0]
//////////////////////// DPDT Switch ////////////////////////
input [17:0] SW; // Toggle Switch[17:0]
//////////////////////// 7-SEG Display ////////////////////////
output [6:0] HEX0; // Seven Segment Digit 0
output [6:0] HEX1; // Seven Segment Digit 1
output [6:0] HEX2; // Seven Segment Digit 2
output [6:0] HEX3; // Seven Segment Digit 3
output [6:0] HEX4; // Seven Segment Digit 4
output [6:0] HEX5; // Seven Segment Digit 5
output [6:0] HEX6; // Seven Segment Digit 6
output [6:0] HEX7; // Seven Segment Digit 7
//////////////////////////// LED ////////////////////////////
output [8:0] LEDG; // LED Green[8:0]
output [17:0] LEDR; // LED Red[17:0]
//////////////////////////// UART ////////////////////////////
output UART_TXD; // UART Transmitter
input UART_RXD; // UART Receiver
//////////////////////////// IRDA ////////////////////////////
output IRDA_TXD; // IRDA Transmitter
input IRDA_RXD; // IRDA Receiver
/////////////////////// SDRAM Interface ////////////////////////
inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits
output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits
output DRAM_LDQM; // SDRAM Low-byte Data Mask
output DRAM_UDQM; // SDRAM High-byte Data Mask
output DRAM_WE_N; // SDRAM Write Enable
output DRAM_CAS_N; // SDRAM Column Address Strobe
output DRAM_RAS_N; // SDRAM Row Address Strobe
output DRAM_CS_N; // SDRAM Chip Select
output DRAM_BA_0; // SDRAM Bank Address 0
output DRAM_BA_1; // SDRAM Bank Address 0
output DRAM_CLK; // SDRAM Clock
output DRAM_CKE; // SDRAM Clock Enable
//////////////////////// Flash Interface ////////////////////////
inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
output FL_WE_N; // FLASH Write Enable
output FL_RST_N; // FLASH Reset
output FL_OE_N; // FLASH Output Enable
output FL_CE_N; // FLASH Chip Enable
//////////////////////// SRAM Interface ////////////////////////
inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
output SRAM_UB_N; // SRAM Low-byte Data Mask
output SRAM_LB_N; // SRAM High-byte Data Mask
output SRAM_WE_N; // SRAM Write Enable
output SRAM_CE_N; // SRAM Chip Enable
output SRAM_OE_N; // SRAM Output Enable
//////////////////// ISP1362 Interface ////////////////////////
inout [15:0] OTG_DATA; // ISP1362 Data bus 16 Bits
output [1:0] OTG_ADDR; // ISP1362 Address 2 Bits
output OTG_CS_N; // ISP1362 Chip Select
output OTG_RD_N; // ISP1362 Write
output OTG_WR_N; // ISP1362 Read
output OTG_RST_N; // ISP1362 Reset
output OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable
output OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable
input OTG_INT0; // ISP1362 Interrupt 0
input OTG_INT1; // ISP1362 Interrupt 1
input OTG_DREQ0; // ISP1362 DMA Request 0
input OTG_DREQ1; // ISP1362 DMA Request 1
output OTG_DACK0_N; // ISP1362 DMA Acknowledge 0
output OTG_DACK1_N; // ISP1362 DMA Acknowledge 1
//////////////////// LCD Module 16X2 ////////////////////////////
inout [7:0] LCD_DATA; // LCD Data bus 8 bits
output LCD_ON; // LCD Power ON/OFF
output LCD_BLON; // LCD Back Light ON/OFF
output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN; // LCD Enable
output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
//////////////////// SD Card Interface ////////////////////////
inout [3:0] SD_DAT; // SD Card Data
input SD_WP_N; // SD write protect
inout SD_CMD; // SD Card Command Signal
output SD_CLK; // SD Card Clock
//////////////////////// I2C ////////////////////////////////
inout I2C_SDAT; // I2C Data
output I2C_SCLK; // I2C Clock
//////////////////////// PS2 ////////////////////////////////
input PS2_DAT; // PS2 Data
input PS2_CLK; // PS2 Clock
//////////////////// USB JTAG link ////////////////////////////
input TDI; // CPLD -> FPGA (data in)
input TCK; // CPLD -> FPGA (clk)
input TCS; // CPLD -> FPGA (CS)
output TDO; // FPGA -> CPLD (data out)
//////////////////////// VGA ////////////////////////////
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK; // VGA BLANK
output VGA_SYNC; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
//////////////// Ethernet Interface ////////////////////////////
inout [15:0] ENET_DATA; // DM9000A DATA bus 16Bits
output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
output ENET_CS_N; // DM9000A Chip Select
output ENET_WR_N; // DM9000A Write
output ENET_RD_N; // DM9000A Read
output ENET_RST_N; // DM9000A Reset
input ENET_INT; // DM9000A Interrupt
output ENET_CLK; // DM9000A Clock 25 MHz
//////////////////// Audio CODEC ////////////////////////////
inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
input AUD_ADCDAT; // Audio CODEC ADC Data
inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
output AUD_DACDAT; // Audio CODEC DAC Data
inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
output AUD_XCK; // Audio CODEC Chip Clock
//////////////////// TV Devoder ////////////////////////////
input [7:0] TD_DATA; // TV Decoder Data bus 8 bits
input TD_HS; // TV Decoder H_SYNC
input TD_VS; // TV Decoder V_SYNC
output TD_RESET; // TV Decoder Reset
input TD_CLK; // TV Decoder Line Locked Clock
//input iTD_CLK; // TV Decoder Line Locked Clock
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0; // GPIO Connection 0
inout [35:0] GPIO_1; // GPIO Connection 1
// Flash
assign FL_RST_N = 1'b1;
wire FL_16BIT_IP_A0;
// 16*2 LCD Module
assign LCD_ON = 1'b1; // LCD ON
assign LCD_BLON = 1'b1; // LCD Back Light
// All inout port turn to tri-state
assign SD_DAT[0] = 1'bz;
assign AUD_ADCLRCK = AUD_DACLRCK;
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;
// Disable USB speed select
assign OTG_FSPEED = 1'bz;
assign OTG_LSPEED = 1'bz;
// Turn On TV Decoder
assign TD_RESET = KEY[0];
// Set SD Card to SD Mode
wire [3:1] SD_DAT_dummy;
assign SD_DAT_dummy = 3'bzzz;
assign SD_DAT[3] = 1'b1;
//========== SSRAM
wire [1:0] SRAM_DUMMY_ADDR; // used to ignore the A0/A1 pin from Cypress SSRAM IP core
wire [15:0] SRAM_DUMMY_DQ;
//========== SDRAM
assign DRAM_CLK = pll_c1_memory;
wire CPU_RESET_N;
wire pll_c0_system, pll_c1_memory, pll_c2_audio;
// Reset
Reset_Delay delay1 (.iRST(KEY[0]),.iCLK(CLOCK_50),.oRESET(CPU_RESET_N));
//Example instantiation for system 'kernel'
kernel kernel_inst
(
.SRAM_ADDR_from_the_sram_16bit_512k_0 (SRAM_ADDR),
.SRAM_CE_N_from_the_sram_16bit_512k_0 (SRAM_CE_N),
.SRAM_DQ_to_and_from_the_sram_16bit_512k_0 (SRAM_DQ),
.SRAM_LB_N_from_the_sram_16bit_512k_0 (SRAM_LB_N),
.SRAM_OE_N_from_the_sram_16bit_512k_0 (SRAM_OE_N),
.SRAM_UB_N_from_the_sram_16bit_512k_0 (SRAM_UB_N),
.SRAM_WE_N_from_the_sram_16bit_512k_0 (SRAM_WE_N),
.clk_50 (CLOCK_50),
.VGA_BLANK_from_the_vga_0 (VGA_BLANK),
.VGA_B_from_the_vga_0 (VGA_B),
.VGA_CLK_from_the_vga_0 (VGA_CLK),
.VGA_G_from_the_vga_0 (VGA_G),
.VGA_HS_from_the_vga_0 (VGA_HS),
.VGA_R_from_the_vga_0 (VGA_R),
.VGA_SYNC_from_the_vga_0 (VGA_SYNC),
.VGA_VS_from_the_vga_0 (VGA_VS),
.iCLK_25_to_the_vga_0 (CLOCK_27),
.in_port_to_the_gpio (GPIO_0[0]),
.in_port_to_the_key (~KEY[1]),
.in_port_to_the_hardmodle (SW[3:0]),
.LCD_E_from_the_lcd_0 (LCD_EN),
.LCD_RS_from_the_lcd_0 (LCD_RS),
.LCD_RW_from_the_lcd_0 (LCD_RW),
.LCD_data_to_and_from_the_lcd_0 (LCD_DATA),
//.in_port_to_the_pio_sw (SW[17:0]),
//.out_port_from_the_pio_green (LEDG),
//.out_port_from_the_pio_red (LEDR),
.reset_n (CPU_RESET_N),
.select_n_to_the_cfi_flash (FL_CE_N),
.tri_state_bridge_address (FL_ADDR),
.tri_state_bridge_data (FL_DQ),
.tri_state_bridge_readn (FL_OE_N),
.write_n_to_the_cfi_flash (FL_WE_N)
);
endmodule
module Reset_Delay(iRST,iCLK,oRESET);
input iCLK;
input iRST;
output reg oRESET;
reg [27:0] Cont;
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
oRESET <= 1'b0;
Cont <= 28'h0000000;
end
else
begin
if(Cont!=28'h4FFFFFF) // about 300ms at 50MHz
begin
Cont <= Cont+1;
oRESET <= 1'b0;
end
else
oRESET <= 1'b1;
end
end
endmodule
|
/********************************************/
/* qmem_sram.v */
/* A QMEM (32bit) to SRAM (16bit) interface */
/* Compatible with Altera DE1 board */
/* */
/* 2010, [email protected] */
/********************************************/
// uncomment this for non-regstered sram interface
//`define QMEM_SRAM_ASYNC
module qmem_sram #(
parameter AW = 32,
parameter DW = 32,
parameter SW = DW/8
)(
// system signals
input wire clk50,
input wire clk100,
input wire rst,
// qmem bus
input wire [AW-1:0] adr,
input wire cs,
input wire we,
input wire [SW-1:0] sel,
input wire [DW-1:0] dat_w,
output reg [DW-1:0] dat_r,
output wire ack,
output wire err,
// SRAM interface
output wire [18-1:0] sram_adr,
output wire sram_ce_n,
output wire sram_we_n,
output wire sram_ub_n,
output wire sram_lb_n,
output wire sram_oe_n,
output wire [16-1:0] sram_dat_w,
input wire [16-1:0] sram_dat_r
);
`ifndef QMEM_SRAM_ASYNC
////////////////////////////////////////
// registered outputs variant //
////////////////////////////////////////
/* state */
localparam S_ID = 3'b000; // idle
localparam S_HI1 = 3'b011; // first access, write upper 16 bits
localparam S_HI2 = 3'b111;
localparam S_LO1 = 3'b010; // second access, write lower 16 bits, latch upper 16 bits
localparam S_LO2 = 3'b110;
localparam S_FH = 3'b001; // last read, latch lower 16 bits
reg [2:0] state, next_state;
always @ (*)
begin
case (state)
S_ID : begin if (cs) next_state = S_HI1; else next_state = S_ID; end
S_HI1 : begin if (cs) next_state = S_HI2; else next_state = S_ID; end
S_HI2 : begin if (cs) next_state = S_LO1; else next_state = S_ID; end
S_LO1 : begin if (cs) next_state = S_LO2; else next_state = S_ID; end
S_LO2 : begin if (cs) next_state = S_FH; else next_state = S_ID; end
S_FH : begin next_state = S_ID; end
default : begin next_state = S_ID; end
endcase
end
always @ (posedge clk100 or posedge rst)
begin
if (rst)
state <= #1 S_ID;
else
state <= #1 next_state;
end
/* output registers */
// address
reg [17:0] s_adr;
always @ (posedge clk100)
begin
if (next_state == S_HI1)
s_adr <= #1 {adr[18:2], 1'b0};
else if (next_state == S_LO1)
s_adr <= #1 {adr[18:2], 1'b1};
end
// ce_n
reg s_ce_n;
always @ (posedge clk100 or posedge rst)
begin
if (rst)
s_ce_n <= #1 1'b1;
else if ((next_state == S_HI1) || (next_state == S_HI2) || (next_state == S_LO1) || (next_state == S_LO2))
s_ce_n <= #1 1'b0;
else
s_ce_n <= #1 1'b1;
end
// we_n
reg s_we_n;
always @ (posedge clk100)
begin
if ((next_state == S_HI1) || (next_state == S_HI2) || (next_state == S_LO1) || (next_state == S_LO2))
s_we_n <= #1 !we;
end
// ub_n & lb_n
reg s_ub_n, s_lb_n;
always @ (posedge clk100)
begin
if (next_state == S_HI1)
{s_ub_n, s_lb_n} <= #1 {!sel[3], !sel[2]};
else if (next_state == S_LO1)
{s_ub_n, s_lb_n} <= #1 {!sel[1], !sel[0]};
end
// oe_n
reg s_oe_n;
always @ (posedge clk100)
begin
if ((next_state == S_HI1) || (next_state == S_HI2) || (next_state == S_LO1) || (next_state == S_LO2))
s_oe_n <= #1 we;
else
s_oe_n <= #1 1'b0;
end
// dat_w
reg [15:0] s_dat_w;
always @ (posedge clk100)
begin
if (next_state == S_HI1)
s_dat_w <= #1 dat_w[31:16];
else if (next_state == S_LO1)
s_dat_w <= #1 dat_w[15:0];
end
/* inputs */
// dat_r
reg [31:0] s_dat_r;
always @ (posedge clk100)
begin
if ((next_state == S_LO1) && !we)
dat_r[31:16] <= #1 sram_dat_r;
else if ((next_state == S_FH) && !we)
dat_r[15: 0] <= #1 sram_dat_r;
end
// ack
reg s_ack;
always @ (posedge clk100 or posedge rst)
begin
if (rst)
s_ack <= #1 1'b0;
else if ((state == S_LO2) || (state == S_FH))
s_ack <= #1 1'b1;
else
s_ack <= #1 1'b0;
end
/* output assignments */
assign sram_adr = s_adr;
assign sram_ce_n = s_ce_n;
assign sram_we_n = s_we_n;
assign sram_ub_n = s_ub_n;
assign sram_lb_n = s_lb_n;
assign sram_oe_n = s_oe_n;
assign sram_dat_w = s_dat_w;
assign ack = s_ack;
assign err = 1'b0;
`else
////////////////////////////////////////
// async outputs variant //
////////////////////////////////////////
/* local signals */
reg [ AW-1:0] adr_r;
wire adr_changed;
reg cnt;
reg [ 16-1:0] rdat_r;
/* address change */
always @ (posedge clk50) adr_r <= #1 adr;
assign adr_changed = (adr != adr_r);
/* cs counter */
always @ (posedge clk50 or posedge rst)
begin
if (rst)
cnt <= #1 1'b0;
else if (adr_changed)
cnt <= #1 1'b0;
else if (cs)
cnt <= #1 !cnt;
end
/* read data reg */
always @ (posedge clk50) if (cs && !cnt && !we) rdat_r <= #1 sram_dat_r;
/* qmem outputs */
// TODO dat_r - check if a reg is needed! maybe should use address register!
always @ (posedge clk50) if (cs && cnt && !we) dat_r <= #1 {sram_dat_r, rdat_r};
//assign dat_r = {sram_dat_r, rdat_r};
assign ack = cnt;
assign err = 1'b0;
/* SRAM outputs */
assign sram_adr = (!cnt) ? {adr[18:2], 1'b0} : {adr[18:2], 1'b1};
assign sram_ce_n = !cs;
assign sram_we_n = !we;
assign sram_ub_n = !((!cnt) ? sel[1] : sel[3]);
assign sram_lb_n = !((!cnt) ? sel[0] : sel[2]);
assign sram_oe_n = we;
assign sram_dat_w = (!cnt) ? dat_w[15:0] : dat_w[31:16];
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311OI_1_V
`define SKY130_FD_SC_HD__A311OI_1_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a311oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a311oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a311oi_1 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311OI_1_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Muhammad Ijaz
//
// Create Date: 08/15/2017 01:21:09 AM
// Design Name:
// Module Name: VICTIM_CACHE_SIMULATION
// Project Name: RISC-V
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module VICTIM_CACHE_SIMULATION();
parameter BLOCK_WIDTH = 512 ;
parameter TAG_WIDTH = 26 ;
parameter MEMORY_LATENCY = "HIGH_LATENCY" ;
localparam MEMORY_DEPTH = 4 ;
localparam ADDRESS_WIDTH = $clog2(MEMORY_DEPTH-1) ;
// Inputs
reg clk ;
reg [TAG_WIDTH - 1 : 0] write_tag_address ;
reg [BLOCK_WIDTH - 1 : 0] write_data ;
reg write_enable ;
reg [TAG_WIDTH - 1 : 0] read_tag_address ;
reg read_enble ;
// Outputs
wire read_hit ;
wire [BLOCK_WIDTH - 1 : 0] read_data ;
// Instantiate the Unit Under Test (UUT)
VICTIM_CACHE #(
.BLOCK_WIDTH(BLOCK_WIDTH),
.TAG_WIDTH(TAG_WIDTH),
.MEMORY_LATENCY(MEMORY_LATENCY)
)uut(
.CLK(clk),
.WRITE_TAG_ADDRESS(write_tag_address),
.WRITE_DATA(write_data),
.WRITE_ENABLE(write_enable),
.READ_TAG_ADDRESS(read_tag_address),
.READ_ENBLE(read_enble),
.READ_HIT(read_hit),
.READ_DATA(read_data)
);
initial
begin
// Initialize Inputs
clk = 1'b0 ;
write_tag_address = 26'b1 ;
write_data = 512'b1 ;
write_enable = 1'b1 ;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
clk = 1'b1 ;
#100;
clk = 1'b0 ;
write_tag_address = 26'b10 ;
write_data = 512'b10 ;
write_enable = 1'b1 ;
#100;
clk = 1'b1 ;
#100;
clk = 1'b0 ;
write_tag_address = 26'b0 ;
write_data = 512'b0 ;
write_enable = 1'b0 ;
read_tag_address = 26'b1 ;
read_enble = 1'b1 ;
#100;
clk = 1'b1 ;
#100;
clk = 1'b0 ;
read_tag_address = 26'b10 ;
read_enble = 1'b1 ;
#100;
clk = 1'b1 ;
#100;
clk = 1'b0 ;
read_tag_address = 26'b0 ;
read_enble = 1'b1 ;
#100;
clk = 1'b1 ;
#100;
clk = 1'b0 ;
#100;
clk = 1'b1 ;
end
endmodule
|
// Library - static, Cell - th24w2, View - schematic
// LAST TIME SAVED: May 23 16:48:28 2014
// NETLIST TIME: May 23 16:48:54 2014
`timescale 1ns / 1ns
module th24w2 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th24w2";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N15 ( .d(net051), .g(b), .s(net038), .b(cds_globals.gnd_));
nfet_b N14 ( .d(net051), .g(d), .s(net039), .b(cds_globals.gnd_));
nfet_b N5 ( .d(net051), .g(d), .s(net44), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net039), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N16 ( .d(net038), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N10 ( .d(net051), .g(c), .s(net44), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net44), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N1 ( .d(net051), .g(a), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
pfet_b P7 ( .b(cds_globals.vdd_), .g(b), .s(net49), .d(net032));
pfet_b P13 ( .b(cds_globals.vdd_), .g(y), .s(net041), .d(net051));
pfet_b P5 ( .b(cds_globals.vdd_), .g(d), .s(net032), .d(net041));
pfet_b P12 ( .b(cds_globals.vdd_), .g(c), .s(net49), .d(net032));
pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(net47), .d(net051));
pfet_b P3 ( .b(cds_globals.vdd_), .g(d), .s(net47), .d(net051));
pfet_b P2 ( .b(cds_globals.vdd_), .g(c), .s(net34), .d(net47));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net49), .d(net34));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net051);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// 6.111 FPGA Labkit -- Hex display driver
//
// File: display_16hex.v
// Date: 24-Sep-05
//
// Created: April 27, 2004
// Author: Nathan Ickes
//
// 24-Sep-05 Ike: updated to use new reset-once state machine, remove clear
// 28-Nov-06 CJT: fixed race condition between CE and RS (thanks Javier!)
//
// This verilog module drives the labkit hex dot matrix displays, and puts
// up 16 hexadecimal digits (8 bytes). These are passed to the module
// through a 64 bit wire ("data"), asynchronously.
//
///////////////////////////////////////////////////////////////////////////////
module display_16hex (reset, clock_27mhz, data,
disp_blank, disp_clock, disp_rs, disp_ce_b,
disp_reset_b, disp_data_out);
input reset, clock_27mhz; // clock and reset (active high reset)
input [63:0] data; // 16 hex nibbles to display
output disp_blank, disp_clock, disp_data_out, disp_rs, disp_ce_b,
disp_reset_b;
reg disp_data_out, disp_rs, disp_ce_b, disp_reset_b;
////////////////////////////////////////////////////////////////////////////
//
// Display Clock
//
// Generate a 500kHz clock for driving the displays.
//
////////////////////////////////////////////////////////////////////////////
reg [4:0] count;
reg [7:0] reset_count;
reg clock;
wire dreset;
always @(posedge clock_27mhz)
begin
if (reset)
begin
count = 0;
clock = 0;
end
else if (count == 26)
begin
clock = ~clock;
count = 5'h00;
end
else
count = count+1;
end
always @(posedge clock_27mhz)
if (reset)
reset_count <= 100;
else
reset_count <= (reset_count==0) ? 0 : reset_count-1;
assign dreset = (reset_count != 0);
assign disp_clock = ~clock;
////////////////////////////////////////////////////////////////////////////
//
// Display State Machine
//
////////////////////////////////////////////////////////////////////////////
reg [7:0] state; // FSM state
reg [9:0] dot_index; // index to current dot being clocked out
reg [31:0] control; // control register
reg [3:0] char_index; // index of current character
reg [39:0] dots; // dots for a single digit
reg [3:0] nibble; // hex nibble of current character
assign disp_blank = 1'b0; // low <= not blanked
always @(posedge clock)
if (dreset)
begin
state <= 0;
dot_index <= 0;
control <= 32'h7F7F7F7F;
end
else
casex (state)
8'h00:
begin
// Reset displays
disp_data_out <= 1'b0;
disp_rs <= 1'b0; // dot register
disp_ce_b <= 1'b1;
disp_reset_b <= 1'b0;
dot_index <= 0;
state <= state+1;
end
8'h01:
begin
// End reset
disp_reset_b <= 1'b1;
state <= state+1;
end
8'h02:
begin
// Initialize dot register (set all dots to zero)
disp_ce_b <= 1'b0;
disp_data_out <= 1'b0; // dot_index[0];
if (dot_index == 639)
state <= state+1;
else
dot_index <= dot_index+1;
end
8'h03:
begin
// Latch dot data
disp_ce_b <= 1'b1;
dot_index <= 31; // re-purpose to init ctrl reg
disp_rs <= 1'b1; // Select the control register
state <= state+1;
end
8'h04:
begin
// Setup the control register
disp_ce_b <= 1'b0;
disp_data_out <= control[31];
control <= {control[30:0], 1'b0}; // shift left
if (dot_index == 0)
state <= state+1;
else
dot_index <= dot_index-1;
end
8'h05:
begin
// Latch the control register data / dot data
disp_ce_b <= 1'b1;
dot_index <= 39; // init for single char
char_index <= 15; // start with MS char
state <= state+1;
disp_rs <= 1'b0; // Select the dot register
end
8'h06:
begin
// Load the user's dot data into the dot reg, char by char
disp_ce_b <= 1'b0;
disp_data_out <= dots[dot_index]; // dot data from msb
if (dot_index == 0)
if (char_index == 0)
state <= 5; // all done, latch data
else
begin
char_index <= char_index - 1; // goto next char
dot_index <= 39;
end
else
dot_index <= dot_index-1; // else loop thru all dots
end
endcase
always @ (data or char_index)
case (char_index)
4'h0: nibble <= data[3:0];
4'h1: nibble <= data[7:4];
4'h2: nibble <= data[11:8];
4'h3: nibble <= data[15:12];
4'h4: nibble <= data[19:16];
4'h5: nibble <= data[23:20];
4'h6: nibble <= data[27:24];
4'h7: nibble <= data[31:28];
4'h8: nibble <= data[35:32];
4'h9: nibble <= data[39:36];
4'hA: nibble <= data[43:40];
4'hB: nibble <= data[47:44];
4'hC: nibble <= data[51:48];
4'hD: nibble <= data[55:52];
4'hE: nibble <= data[59:56];
4'hF: nibble <= data[63:60];
endcase
always @(nibble)
case (nibble)
4'h0: dots <= 40'b00111110_01010001_01001001_01000101_00111110;
4'h1: dots <= 40'b00000000_01000010_01111111_01000000_00000000;
4'h2: dots <= 40'b01100010_01010001_01001001_01001001_01000110;
4'h3: dots <= 40'b00100010_01000001_01001001_01001001_00110110;
4'h4: dots <= 40'b00011000_00010100_00010010_01111111_00010000;
4'h5: dots <= 40'b00100111_01000101_01000101_01000101_00111001;
4'h6: dots <= 40'b00111100_01001010_01001001_01001001_00110000;
4'h7: dots <= 40'b00000001_01110001_00001001_00000101_00000011;
4'h8: dots <= 40'b00110110_01001001_01001001_01001001_00110110;
4'h9: dots <= 40'b00000110_01001001_01001001_00101001_00011110;
4'hA: dots <= 40'b01111110_00001001_00001001_00001001_01111110;
4'hB: dots <= 40'b01111111_01001001_01001001_01001001_00110110;
4'hC: dots <= 40'b00111110_01000001_01000001_01000001_00100010;
4'hD: dots <= 40'b01111111_01000001_01000001_01000001_00111110;
4'hE: dots <= 40'b01111111_01001001_01001001_01001001_01000001;
4'hF: dots <= 40'b01111111_00001001_00001001_00001001_00000001;
endcase
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: O.87xd
// \ \ Application: netgen
// / / Filename: fifo_37x512.v
// /___/ /\ Timestamp: Thu Nov 8 18:44:10 2012
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_37x512.ngc /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_37x512.v
// Device : 5vlx330ff1760-1
// Input file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_37x512.ngc
// Output file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_37x512.v
// # of Modules : 1
// Design Name : fifo_37x512
// Xilinx : /remote/Xilinx/13.4/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module fifo_37x512 (
clk, rd_en, empty, wr_en, full, srst, dout, din
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input rd_en;
output empty;
input wr_en;
output full;
input srst;
output [36 : 0] dout;
input [36 : 0] din;
// synthesis translate_off
wire N0;
wire N1;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_24 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_27 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_29 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_31 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_33 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_41 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_90 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_102 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_104 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_106 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_108 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_SBITERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DBITERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<63>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<62>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<61>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<60>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<55>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<54>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<53>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<47>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<46>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<45>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<44>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<39>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<38>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<37>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<31>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<30>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<29>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<28>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<23>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<22>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<21>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<15>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<14>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<13>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<0>_UNCONNECTED ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 ;
wire [7 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy ;
wire [0 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 ;
wire [7 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy ;
wire [0 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 ;
assign
empty = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_24 ,
full = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_90 ;
GND XST_GND (
.G(N0)
);
VCC XST_VCC (
.P(N1)
);
FD #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_24 )
);
FD #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 )
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 )
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_90 )
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [7]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_41 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [8])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [6]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [7])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [6]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [7])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [5]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [6])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [5]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [6])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [4]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [5])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [4]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [5])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [3]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_33 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [4])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_33 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [4])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [2]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_31 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_31 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [3])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [1]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_29 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_29 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [2])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [0]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_27 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_27 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [1])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<0> (
.CI(N0),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<0> (
.CI(N0),
.DI(N1),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2])
);
FDSE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [0]),
.S(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [7]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_108 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [8])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [6]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_106 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [7])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [6]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_106 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [7])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [5]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_104 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [6])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [5]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_104 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [6])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_102 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [5])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_102 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [5])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [4])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<0> (
.CI(N0),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<0> (
.CI(N0),
.DI(N1),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2])
);
FDSE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [0]),
.S(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [0])
);
LUT3 #(
.INIT ( 8'hF4 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en1 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ),
.I1(rd_en),
.I2(srst),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en )
);
LUT2 #(
.INIT ( 4'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 (
.I0(wr_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en )
);
LUT2 #(
.INIT ( 4'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/ram_rd_en_i1 (
.I0(rd_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en )
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0])
);
LUT6 #(
.INIT ( 64'h1110101051505050 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux00001 (
.I0(srst),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 ),
.I3(wr_en),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ),
.I5(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 )
);
LUT6 #(
.INIT ( 64'hAAFEAAFAFAFEFAFA ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux00001 (
.I0(srst),
.I1(rd_en),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ),
.I5(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_33 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_31 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_29 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_27 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_106 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_104 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_102 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_41 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_108 )
);
INV \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut<0>_INV_0 (
.I(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0])
);
INV \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut<0>_INV_0 (
.I(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0])
);
RAMB36SDP_EXP #(
.DO_REG ( 0 ),
.EN_ECC_READ ( "FALSE" ),
.EN_ECC_SCRUB ( "FALSE" ),
.EN_ECC_WRITE ( "FALSE" ),
.INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
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.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
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.INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT ( 72'h000000000000000000 ),
.SRVAL ( 72'h000000000000000000 ),
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
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.INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_FILE ( "NONE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_MODE ( "SAFE" ),
.INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP (
.RDENU(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.RDENL(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.WRENU(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.WRENL(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.SSRU(srst),
.SSRL(srst),
.RDCLKU(clk),
.RDCLKL(clk),
.WRCLKU(clk),
.WRCLKL(clk),
.RDRCLKU(clk),
.RDRCLKL(clk),
.REGCEU(N0),
.REGCEL(N0),
.SBITERR
(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_SBITERR_UNCONNECTED )
,
.DBITERR
(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DBITERR_UNCONNECTED )
,
.DI({N0, N0, N0, N0, din[36], din[35], din[34], din[33], N0, N0, N0, din[32], din[31], din[30], din[29], din[28], N0, N0, N0, N0, din[27], din[26]
, din[25], din[24], N0, N0, N0, din[23], din[22], din[21], din[20], din[19], N0, N0, N0, N0, din[18], din[17], din[16], din[15], N0, N0, N0, din[14],
din[13], din[12], din[11], din[10], N0, N0, N0, din[9], din[8], din[7], din[6], din[5], N0, N0, N0, din[4], din[3], din[2], din[1], din[0]}),
.DIP({N0, N0, N0, N0, N0, N0, N0, N0}),
.RDADDRL({N1, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<0>_UNCONNECTED
}),
.RDADDRU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<0>_UNCONNECTED
}),
.WRADDRL({N1, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<0>_UNCONNECTED
}),
.WRADDRU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<0>_UNCONNECTED
}),
.WEU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }),
.WEL({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }),
.DO({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<63>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<62>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<61>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<60>_UNCONNECTED
, dout[36], dout[35], dout[34], dout[33],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<55>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<54>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<53>_UNCONNECTED
, dout[32], dout[31], dout[30], dout[29], dout[28],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<47>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<46>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<45>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<44>_UNCONNECTED
, dout[27], dout[26], dout[25], dout[24],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<39>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<38>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<37>_UNCONNECTED
, dout[23], dout[22], dout[21], dout[20], dout[19],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<31>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<30>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<29>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<28>_UNCONNECTED
, dout[18], dout[17], dout[16], dout[15],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<23>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<22>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<21>_UNCONNECTED
, dout[14], dout[13], dout[12], dout[11], dout[10],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<15>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<14>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<13>_UNCONNECTED
, dout[9], dout[8], dout[7], dout[6], dout[5],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<7>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<6>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<5>_UNCONNECTED
, dout[4], dout[3], dout[2], dout[1], dout[0]}),
.DOP({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<7>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<6>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<0>_UNCONNECTED
}),
.ECCPARITY({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<7>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<6>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<0>_UNCONNECTED
})
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: VC709_Gen2x8If128_CLK.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
// the Xilinx VC709 Development Board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "functions.vh"
`include "riffa.vh"
`include "ultrascale.vh"
`timescale 1ps / 1ps
module VC709_Gen2x8If128_CLK
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 12,
// Number of PCIe Lanes
parameter C_NUM_LANES = 8,
// Settings from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 6
)
(output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN,
output [7:0] LED,
input PCIE_REFCLK_P,
input PCIE_REFCLK_N,
input PCIE_RESET_N
);
// Clocks, etc
wire user_lnk_up;
wire user_clk;
wire user_reset;
wire pcie_refclk;
wire pcie_reset_n;
wire riffa_5_clk;
wire riffa_10_clk;
wire riffa_25_clk;
wire riffa_50_clk;
wire riffa_75_clk;
wire riffa_100_clk;
wire riffa_125_clk;
wire riffa_150_clk;
wire riffa_175_clk;
wire riffa_200_clk;
wire riffa_225_clk;
wire riffa_250_clk;
// Interface: RQ (TXC)
wire s_axis_rq_tlast;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep;
wire s_axis_rq_tready;
wire s_axis_rq_tvalid;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser;
wire m_axis_rc_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep;
wire m_axis_rc_tvalid;
wire m_axis_rc_tready;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser;
wire m_axis_cq_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep;
wire m_axis_cq_tvalid;
wire m_axis_cq_tready;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser;
wire s_axis_cc_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep;
wire s_axis_cc_tvalid;
wire s_axis_cc_tready;
// Configuration (CFG) Interface
wire [3:0] pcie_rq_seq_num;
wire pcie_rq_seq_num_vld;
wire [5:0] pcie_rq_tag;
wire pcie_rq_tag_vld;
wire pcie_cq_np_req;
wire [5:0] pcie_cq_np_req_count;
wire cfg_phy_link_down;
wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH
wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE
wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD
wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST
wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE
wire [5:0] cfg_function_power_state; // Ignorable but not removable
wire [11:0] cfg_vf_status; // Ignorable but not removable
wire [17:0] cfg_vf_power_state; // Ignorable but not removable
wire [1:0] cfg_link_power_state; // Ignorable but not removable
// Error Reporting Interface
wire cfg_err_cor_out;
wire cfg_err_nonfatal_out;
wire cfg_err_fatal_out;
wire cfg_ltr_enable;
wire [5:0] cfg_ltssm_state;// TODO: Connect to LED's
wire [1:0] cfg_rcb_status;
wire [1:0] cfg_dpa_substate_change;
wire [1:0] cfg_obff_enable;
wire cfg_pl_status_change;
wire [1:0] cfg_tph_requester_enable;
wire [5:0] cfg_tph_st_mode;
wire [5:0] cfg_vf_tph_requester_enable;
wire [17:0] cfg_vf_tph_st_mode;
wire [7:0] cfg_fc_ph;
wire [11:0] cfg_fc_pd;
wire [7:0] cfg_fc_nph;
wire [11:0] cfg_fc_npd;
wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel;
// Interrupt Interface Signals
wire [3:0] cfg_interrupt_int;
wire [1:0] cfg_interrupt_pending;
wire cfg_interrupt_sent;
wire [1:0] cfg_interrupt_msi_enable;
wire [5:0] cfg_interrupt_msi_vf_enable;
wire [5:0] cfg_interrupt_msi_mmenable;
wire cfg_interrupt_msi_mask_update;
wire [31:0] cfg_interrupt_msi_data;
wire [3:0] cfg_interrupt_msi_select;
wire [31:0] cfg_interrupt_msi_int;
wire [63:0] cfg_interrupt_msi_pending_status;
wire cfg_interrupt_msi_sent;
wire cfg_interrupt_msi_fail;
wire [2:0] cfg_interrupt_msi_attr;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [2:0] cfg_interrupt_msi_function_number;
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
genvar chnl;
IBUF
#()
pci_reset_n_ibuf
(.O(pcie_reset_n),
.I(PCIE_RESET_N));
IBUFDS_GTE2
#()
refclk_ibuf
(.O(pcie_refclk),
.ODIV2(),
.I(PCIE_REFCLK_P),
.CEB(1'b0),
.IB(PCIE_REFCLK_N));
OBUF
#()
led_0_obuf
(.O(LED[0]),
.I(cfg_ltssm_state[0]));
OBUF
#()
led_1_obuf
(.O(LED[1]),
.I(cfg_ltssm_state[1]));
OBUF
#()
led_2_obuf
(.O(LED[2]),
.I(cfg_ltssm_state[2]));
OBUF
#()
led_3_obuf
(.O(LED[3]),
.I(cfg_ltssm_state[3]));
OBUF
#()
led_4_obuf
(.O(LED[4]),
.I(cfg_ltssm_state[4]));
OBUF
#()
led_5_obuf
(.O(LED[5]),
.I(cfg_ltssm_state[5]));
OBUF
#()
led_6_obuf
(.O(LED[6]),
.I(pcie_reset_n));
OBUF
#()
led_7_obuf
(.O(LED[7]),
.I(rst_out));
// Core Top Level Wrapper
PCIeGen2x8If128
#()
pcie3_7x_0_i
(//---------------------------------------------------------------------
// PCI Express (pci_exp) Interface
//---------------------------------------------------------------------
.pci_exp_txn ( PCI_EXP_TXN ),
.pci_exp_txp ( PCI_EXP_TXP ),
.pci_exp_rxn ( PCI_EXP_RXN ),
.pci_exp_rxp ( PCI_EXP_RXP ),
//---------------------------------------------------------------------
// AXI Interface
//---------------------------------------------------------------------
.user_clk ( user_clk ),
.user_reset ( user_reset ),
.user_lnk_up ( user_lnk_up ),
.user_app_rdy ( ),
.s_axis_rq_tlast ( s_axis_rq_tlast ),
.s_axis_rq_tdata ( s_axis_rq_tdata ),
.s_axis_rq_tuser ( s_axis_rq_tuser ),
.s_axis_rq_tkeep ( s_axis_rq_tkeep ),
.s_axis_rq_tready ( s_axis_rq_tready ),
.s_axis_rq_tvalid ( s_axis_rq_tvalid ),
.m_axis_rc_tdata ( m_axis_rc_tdata ),
.m_axis_rc_tuser ( m_axis_rc_tuser ),
.m_axis_rc_tlast ( m_axis_rc_tlast ),
.m_axis_rc_tkeep ( m_axis_rc_tkeep ),
.m_axis_rc_tvalid ( m_axis_rc_tvalid ),
.m_axis_rc_tready ( {22{m_axis_rc_tready}} ),
.m_axis_cq_tdata ( m_axis_cq_tdata ),
.m_axis_cq_tuser ( m_axis_cq_tuser ),
.m_axis_cq_tlast ( m_axis_cq_tlast ),
.m_axis_cq_tkeep ( m_axis_cq_tkeep ),
.m_axis_cq_tvalid ( m_axis_cq_tvalid ),
.m_axis_cq_tready ( {22{m_axis_cq_tready}} ),
.s_axis_cc_tdata ( s_axis_cc_tdata ),
.s_axis_cc_tuser ( s_axis_cc_tuser ),
.s_axis_cc_tlast ( s_axis_cc_tlast ),
.s_axis_cc_tkeep ( s_axis_cc_tkeep ),
.s_axis_cc_tvalid ( s_axis_cc_tvalid ),
.s_axis_cc_tready ( s_axis_cc_tready ),
//---------------------------------------------------------------------
// Configuration (CFG) Interface
//---------------------------------------------------------------------
.pcie_rq_seq_num ( pcie_rq_seq_num ),
.pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ),
.pcie_rq_tag ( pcie_rq_tag ),
.pcie_rq_tag_vld ( pcie_rq_tag_vld ),
.pcie_cq_np_req ( pcie_cq_np_req ),
.pcie_cq_np_req_count ( pcie_cq_np_req_count ),
.cfg_phy_link_down ( cfg_phy_link_down ),
.cfg_phy_link_status ( cfg_phy_link_status),
.cfg_negotiated_width ( cfg_negotiated_width ),
.cfg_current_speed ( cfg_current_speed ),
.cfg_max_payload ( cfg_max_payload ),
.cfg_max_read_req ( cfg_max_read_req ),
.cfg_function_status ( cfg_function_status ),
.cfg_function_power_state ( cfg_function_power_state ),
.cfg_vf_status ( cfg_vf_status ),
.cfg_vf_power_state ( cfg_vf_power_state ),
.cfg_link_power_state ( cfg_link_power_state ),
// Error Reporting Interface
.cfg_err_cor_out ( cfg_err_cor_out ),
.cfg_err_nonfatal_out ( cfg_err_nonfatal_out ),
.cfg_err_fatal_out ( cfg_err_fatal_out ),
.cfg_ltr_enable ( cfg_ltr_enable ),
.cfg_ltssm_state ( cfg_ltssm_state ),
.cfg_rcb_status ( cfg_rcb_status ),
.cfg_dpa_substate_change ( cfg_dpa_substate_change ),
.cfg_obff_enable ( cfg_obff_enable ),
.cfg_pl_status_change ( cfg_pl_status_change ),
.cfg_tph_requester_enable ( cfg_tph_requester_enable ),
.cfg_tph_st_mode ( cfg_tph_st_mode ),
.cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ),
.cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ),
.cfg_fc_ph ( cfg_fc_ph ),
.cfg_fc_pd ( cfg_fc_pd ),
.cfg_fc_nph ( cfg_fc_nph ),
.cfg_fc_npd ( cfg_fc_npd ),
.cfg_fc_cplh ( cfg_fc_cplh ),
.cfg_fc_cpld ( cfg_fc_cpld ),
.cfg_fc_sel ( cfg_fc_sel ),
//---------------------------------------------------------------------
// EP Only
//---------------------------------------------------------------------
// Interrupt Interface Signals
.cfg_interrupt_int ( cfg_interrupt_int ),
.cfg_interrupt_pending ( cfg_interrupt_pending ),
.cfg_interrupt_sent ( cfg_interrupt_sent ),
.cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ),
.cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ),
.cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ),
.cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ),
.cfg_interrupt_msi_data ( cfg_interrupt_msi_data ),
.cfg_interrupt_msi_select ( cfg_interrupt_msi_select ),
.cfg_interrupt_msi_int ( cfg_interrupt_msi_int ),
.cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ),
.cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ),
.cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ),
.cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ),
.cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ),
.cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ),
.cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ),
.cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ),
//---------------------------------------------------------------------
// System(SYS) Interface
//---------------------------------------------------------------------
.sys_clk (pcie_refclk),
.sys_reset (~pcie_reset_n));
riffa_wrapper_vc709
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready),
.M_AXIS_RC_TREADY (m_axis_rc_tready),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid),
.S_AXIS_CC_TLAST (s_axis_cc_tlast),
.S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]),
.USER_CLK (user_clk),
.USER_RESET (user_reset),
.CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]),
.CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]),
.CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]),
.CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]),
.CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]),
.CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]),
.CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present),
.CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]),
.CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]),
.CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]),
.CFG_FC_SEL (cfg_fc_sel[2:0]),
.PCIE_CQ_NP_REQ (pcie_cq_np_req),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid),
.M_AXIS_RC_TLAST (m_axis_rc_tlast),
.M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready),
.S_AXIS_RQ_TREADY (s_axis_rq_tready),
.CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]),
.CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update),
.CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]),
.CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent),
.CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail),
.CFG_FC_CPLH (cfg_fc_cplh[7:0]),
.CFG_FC_CPLD (cfg_fc_cpld[11:0]),
.CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]),
.CFG_CURRENT_SPEED (cfg_current_speed[2:0]),
.CFG_MAX_PAYLOAD (cfg_max_payload[2:0]),
.CFG_MAX_READ_REQ (cfg_max_read_req[2:0]),
.CFG_FUNCTION_STATUS (cfg_function_status[7:0]),
.CFG_RCB_STATUS (cfg_rcb_status[1:0]),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
clk_250MIn_1
clkgen
(.user_clk(user_clk),
.riffa_5_clk(riffa_5_clk),
.riffa_10_clk(riffa_10_clk),
.riffa_25_clk(riffa_25_clk),
.riffa_50_clk(riffa_50_clk),
.riffa_75_clk(riffa_75_clk),
.riffa_100_clk(riffa_100_clk));
clk_250MIn_2
clkgen_2
(.user_clk(user_clk),
.riffa_125_clk(riffa_125_clk),
.riffa_150_clk(riffa_150_clk),
.riffa_175_clk(riffa_175_clk),
.riffa_200_clk(riffa_200_clk),
.riffa_225_clk(riffa_225_clk),
.riffa_250_clk(riffa_250_clk));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_5mhz
(.CLK(riffa_5_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[0]),
.CHNL_RX(chnl_rx[0]),
.CHNL_RX_ACK(chnl_rx_ack[0]),
.CHNL_RX_LAST(chnl_rx_last[0]),
.CHNL_RX_LEN(chnl_rx_len[32*0 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*0 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*0 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[0]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[0]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[0]),
.CHNL_TX(chnl_tx[0]),
.CHNL_TX_ACK(chnl_tx_ack[0]),
.CHNL_TX_LAST(chnl_tx_last[0]),
.CHNL_TX_LEN(chnl_tx_len[32*0 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*0 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*0 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[0]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[0]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_10mhz
(.CLK(riffa_10_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[1]),
.CHNL_RX(chnl_rx[1]),
.CHNL_RX_ACK(chnl_rx_ack[1]),
.CHNL_RX_LAST(chnl_rx_last[1]),
.CHNL_RX_LEN(chnl_rx_len[32*1 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*1 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*1 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[1]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[1]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[1]),
.CHNL_TX(chnl_tx[1]),
.CHNL_TX_ACK(chnl_tx_ack[1]),
.CHNL_TX_LAST(chnl_tx_last[1]),
.CHNL_TX_LEN(chnl_tx_len[32*1 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*1 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*1 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[1]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[1]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_25mhz
(.CLK(riffa_25_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[2]),
.CHNL_RX(chnl_rx[2]),
.CHNL_RX_ACK(chnl_rx_ack[2]),
.CHNL_RX_LAST(chnl_rx_last[2]),
.CHNL_RX_LEN(chnl_rx_len[32*2 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*2 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*2 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[2]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[2]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[2]),
.CHNL_TX(chnl_tx[2]),
.CHNL_TX_ACK(chnl_tx_ack[2]),
.CHNL_TX_LAST(chnl_tx_last[2]),
.CHNL_TX_LEN(chnl_tx_len[32*2 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*2 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*2 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[2]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[2]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_50mhz
(.CLK(riffa_50_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[3]),
.CHNL_RX(chnl_rx[3]),
.CHNL_RX_ACK(chnl_rx_ack[3]),
.CHNL_RX_LAST(chnl_rx_last[3]),
.CHNL_RX_LEN(chnl_rx_len[32*3 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*3 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*3 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[3]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[3]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[3]),
.CHNL_TX(chnl_tx[3]),
.CHNL_TX_ACK(chnl_tx_ack[3]),
.CHNL_TX_LAST(chnl_tx_last[3]),
.CHNL_TX_LEN(chnl_tx_len[32*3 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*3 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*3 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[3]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[3]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_75mhz
(.CLK(riffa_75_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[4]),
.CHNL_RX(chnl_rx[4]),
.CHNL_RX_ACK(chnl_rx_ack[4]),
.CHNL_RX_LAST(chnl_rx_last[4]),
.CHNL_RX_LEN(chnl_rx_len[32*4 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*4 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*4 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[4]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[4]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[4]),
.CHNL_TX(chnl_tx[4]),
.CHNL_TX_ACK(chnl_tx_ack[4]),
.CHNL_TX_LAST(chnl_tx_last[4]),
.CHNL_TX_LEN(chnl_tx_len[32*4 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*4 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*4 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[4]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[4]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_100mhz
(.CLK(riffa_100_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[5]),
.CHNL_RX(chnl_rx[5]),
.CHNL_RX_ACK(chnl_rx_ack[5]),
.CHNL_RX_LAST(chnl_rx_last[5]),
.CHNL_RX_LEN(chnl_rx_len[32*5 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*5 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*5 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[5]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[5]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[5]),
.CHNL_TX(chnl_tx[5]),
.CHNL_TX_ACK(chnl_tx_ack[5]),
.CHNL_TX_LAST(chnl_tx_last[5]),
.CHNL_TX_LEN(chnl_tx_len[32*5 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*5 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*5 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[5]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[5]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_125mhz
(.CLK(riffa_125_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[6]),
.CHNL_RX(chnl_rx[6]),
.CHNL_RX_ACK(chnl_rx_ack[6]),
.CHNL_RX_LAST(chnl_rx_last[6]),
.CHNL_RX_LEN(chnl_rx_len[32*6 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*6 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*6 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[6]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[6]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[6]),
.CHNL_TX(chnl_tx[6]),
.CHNL_TX_ACK(chnl_tx_ack[6]),
.CHNL_TX_LAST(chnl_tx_last[6]),
.CHNL_TX_LEN(chnl_tx_len[32*6 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*6 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*6 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[6]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[6]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_150mhz
(.CLK(riffa_150_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[7]),
.CHNL_RX(chnl_rx[7]),
.CHNL_RX_ACK(chnl_rx_ack[7]),
.CHNL_RX_LAST(chnl_rx_last[7]),
.CHNL_RX_LEN(chnl_rx_len[32*7 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*7 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*7 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[7]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[7]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[7]),
.CHNL_TX(chnl_tx[7]),
.CHNL_TX_ACK(chnl_tx_ack[7]),
.CHNL_TX_LAST(chnl_tx_last[7]),
.CHNL_TX_LEN(chnl_tx_len[32*7 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*7 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*7 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[7]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[7]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_175mhz
(.CLK(riffa_175_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[8]),
.CHNL_RX(chnl_rx[8]),
.CHNL_RX_ACK(chnl_rx_ack[8]),
.CHNL_RX_LAST(chnl_rx_last[8]),
.CHNL_RX_LEN(chnl_rx_len[32*8 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*8 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*8 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[8]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[8]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[8]),
.CHNL_TX(chnl_tx[8]),
.CHNL_TX_ACK(chnl_tx_ack[8]),
.CHNL_TX_LAST(chnl_tx_last[8]),
.CHNL_TX_LEN(chnl_tx_len[32*8 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*8 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*8 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[8]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[8]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_200mhz
(.CLK(riffa_200_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[9]),
.CHNL_RX(chnl_rx[9]),
.CHNL_RX_ACK(chnl_rx_ack[9]),
.CHNL_RX_LAST(chnl_rx_last[9]),
.CHNL_RX_LEN(chnl_rx_len[32*9 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*9 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*9 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[9]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[9]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[9]),
.CHNL_TX(chnl_tx[9]),
.CHNL_TX_ACK(chnl_tx_ack[9]),
.CHNL_TX_LAST(chnl_tx_last[9]),
.CHNL_TX_LEN(chnl_tx_len[32*9 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*9 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*9 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[9]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[9]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_225mhz
(.CLK(riffa_225_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[10]),
.CHNL_RX(chnl_rx[10]),
.CHNL_RX_ACK(chnl_rx_ack[10]),
.CHNL_RX_LAST(chnl_rx_last[10]),
.CHNL_RX_LEN(chnl_rx_len[32*10 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*10 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*10 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[10]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[10]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[10]),
.CHNL_TX(chnl_tx[10]),
.CHNL_TX_ACK(chnl_tx_ack[10]),
.CHNL_TX_LAST(chnl_tx_last[10]),
.CHNL_TX_LEN(chnl_tx_len[32*10 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*10 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*10 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[10]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[10]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_250mhz
(.CLK(riffa_250_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[11]),
.CHNL_RX(chnl_rx[11]),
.CHNL_RX_ACK(chnl_rx_ack[11]),
.CHNL_RX_LAST(chnl_rx_last[11]),
.CHNL_RX_LEN(chnl_rx_len[32*11 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*11 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*11 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[11]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[11]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[11]),
.CHNL_TX(chnl_tx[11]),
.CHNL_TX_ACK(chnl_tx_ack[11]),
.CHNL_TX_LAST(chnl_tx_last[11]),
.CHNL_TX_LEN(chnl_tx_len[32*11 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*11 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*11 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[11]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[11]));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../engine/" "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/" "../../../riffa/")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3B_4_V
`define SKY130_FD_SC_MS__NAND3B_4_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand3b_4 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand3b_4 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3B_4_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:18:33 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20,
n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34,
n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48,
n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62,
n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76,
n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90,
n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103,
n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114,
n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125,
n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136,
n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147,
n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158,
n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169,
n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180,
n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191,
n192, n193, n194, n195, n196, n197, n198, n199, n200, n201, n202,
n203, n204, n205, n206, n207, n208, n209, n210, n211, n212, n213,
n214, n215, n216, n217, n218, n219, n220, n221, n222, n223, n224,
n225, n226, n227, n228, n229, n230, n231, n232, n233, n234, n235,
n236, n237, n238, n239, n240, n241, n242, n243, n244, n245, n246,
n247, n248, n249, n250, n251, n252, n253, n254, n255, n256, n257,
n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, n268,
n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279,
n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290,
n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301,
n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312,
n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, n323,
n324, n325, n326, n327, n328, n329, n330, n331, n332, n333, n334,
n335, n336, n337, n338, n339, n340, n341, n342, n343, n344, n345,
n346, n347, n348, n349, n350, n351, n352, n353, n354, n355, n356,
n357, n358, n359, n360, n361, n362, n363, n364, n365, n366, n367,
n368, n369, n370;
XOR2X2TS U40 ( .A(n288), .B(n287), .Y(res[22]) );
NAND2X1TS U41 ( .A(n255), .B(n91), .Y(n256) );
NAND2X1TS U42 ( .A(n89), .B(n259), .Y(n260) );
NAND2X1TS U43 ( .A(n286), .B(n285), .Y(n287) );
NAND2X1TS U44 ( .A(n225), .B(n240), .Y(n221) );
NAND2X1TS U45 ( .A(n250), .B(n84), .Y(n251) );
NAND2X1TS U46 ( .A(n87), .B(n242), .Y(n243) );
NAND2XLTS U47 ( .A(n82), .B(n308), .Y(n310) );
NAND2X1TS U48 ( .A(n279), .B(n278), .Y(n280) );
NAND2X1TS U49 ( .A(n272), .B(n271), .Y(n273) );
NAND2XLTS U50 ( .A(n83), .B(n330), .Y(n331) );
NAND2XLTS U51 ( .A(n263), .B(n262), .Y(n264) );
NAND2XLTS U52 ( .A(n290), .B(n289), .Y(n291) );
NAND2XLTS U53 ( .A(n311), .B(n8), .Y(n309) );
NAND2X1TS U54 ( .A(n301), .B(n300), .Y(n302) );
OA21X2TS U55 ( .A0(n239), .A1(n238), .B0(n237), .Y(n93) );
NAND2XLTS U56 ( .A(n296), .B(n295), .Y(n297) );
NOR2X1TS U57 ( .A(n62), .B(n59), .Y(n317) );
NAND3X6TS U58 ( .A(n73), .B(n78), .C(n65), .Y(n235) );
NAND2X1TS U59 ( .A(n232), .B(in1[31]), .Y(n237) );
NAND2X6TS U60 ( .A(n292), .B(n66), .Y(n65) );
NOR2XLTS U61 ( .A(n61), .B(n60), .Y(n59) );
INVX3TS U62 ( .A(n74), .Y(n67) );
CLKMX2X2TS U63 ( .A(in2[31]), .B(n231), .S0(add_sub), .Y(n232) );
NAND2X1TS U64 ( .A(n220), .B(in1[29]), .Y(n240) );
NOR2X1TS U65 ( .A(n229), .B(in2[30]), .Y(n230) );
NAND2X2TS U66 ( .A(n188), .B(in1[22]), .Y(n285) );
NAND2X2TS U67 ( .A(n189), .B(in1[23]), .Y(n278) );
NAND2X1TS U68 ( .A(n169), .B(in1[20]), .Y(n295) );
OR2X4TS U69 ( .A(n211), .B(in1[27]), .Y(n91) );
OR2X4TS U70 ( .A(n226), .B(in1[30]), .Y(n87) );
NAND2X2TS U71 ( .A(n168), .B(in1[19]), .Y(n300) );
NOR2X4TS U72 ( .A(n189), .B(in1[23]), .Y(n277) );
NOR2X2TS U73 ( .A(n169), .B(in1[20]), .Y(n294) );
CLKMX2X3TS U74 ( .A(in2[25]), .B(n195), .S0(n223), .Y(n207) );
CLKMX2X4TS U75 ( .A(in2[29]), .B(n219), .S0(n223), .Y(n220) );
MXI2X2TS U76 ( .A(n167), .B(n166), .S0(add_sub), .Y(n169) );
NOR2X2TS U77 ( .A(n218), .B(n204), .Y(n202) );
NOR2X2TS U78 ( .A(n218), .B(n217), .Y(n205) );
XNOR2X1TS U79 ( .A(n222), .B(in2[29]), .Y(n219) );
XNOR2X1TS U80 ( .A(n183), .B(in2[20]), .Y(n166) );
XNOR2X1TS U81 ( .A(n184), .B(n186), .Y(n185) );
XOR2X1TS U82 ( .A(n196), .B(in2[24]), .Y(n177) );
INVX2TS U83 ( .A(in2[21]), .Y(n186) );
NOR2X2TS U84 ( .A(n183), .B(in2[20]), .Y(n184) );
NOR2X2TS U85 ( .A(n161), .B(in2[18]), .Y(n162) );
CLKINVX3TS U86 ( .A(n218), .Y(n196) );
NOR3X2TS U87 ( .A(n183), .B(in2[22]), .C(n179), .Y(n172) );
OR2X2TS U88 ( .A(n204), .B(in2[27]), .Y(n217) );
NAND2X2TS U89 ( .A(n176), .B(n165), .Y(n161) );
AOI21X2TS U90 ( .A0(n329), .A1(n83), .B0(n139), .Y(n34) );
NOR2X1TS U91 ( .A(in2[25]), .B(in2[24]), .Y(n201) );
CLKXOR2X2TS U92 ( .A(n176), .B(in2[16]), .Y(n154) );
OR2X2TS U93 ( .A(in2[21]), .B(in2[20]), .Y(n179) );
OR2X4TS U94 ( .A(n138), .B(in1[12]), .Y(n83) );
NOR2X1TS U95 ( .A(in2[19]), .B(in2[18]), .Y(n164) );
NOR2X2TS U96 ( .A(in2[17]), .B(in2[16]), .Y(n165) );
NOR2X4TS U97 ( .A(n131), .B(in1[10]), .Y(n36) );
XOR2X1TS U98 ( .A(n151), .B(in2[15]), .Y(n152) );
OR2X4TS U99 ( .A(n122), .B(in1[8]), .Y(n86) );
CLKMX2X4TS U100 ( .A(in2[7]), .B(n118), .S0(n20), .Y(n119) );
AND2X2TS U101 ( .A(n96), .B(n148), .Y(n33) );
INVX2TS U102 ( .A(in2[14]), .Y(n148) );
OR2X4TS U103 ( .A(n129), .B(n128), .Y(n134) );
INVX2TS U104 ( .A(n198), .Y(n19) );
CLKINVX6TS U105 ( .A(n198), .Y(n20) );
XOR2X2TS U106 ( .A(n124), .B(in2[9]), .Y(n125) );
AOI21X2TS U107 ( .A0(n110), .A1(n115), .B0(n369), .Y(n111) );
INVX6TS U108 ( .A(n9), .Y(n108) );
CLKINVX2TS U109 ( .A(n128), .Y(n29) );
INVX8TS U110 ( .A(n223), .Y(n198) );
NOR2X1TS U111 ( .A(in2[11]), .B(in2[10]), .Y(n28) );
INVX12TS U112 ( .A(n369), .Y(n223) );
INVX4TS U113 ( .A(n109), .Y(n30) );
INVX2TS U114 ( .A(in2[5]), .Y(n10) );
INVX4TS U115 ( .A(in2[8]), .Y(n121) );
NOR2X2TS U116 ( .A(in2[7]), .B(in2[6]), .Y(n31) );
OAI2BB1X2TS U117 ( .A0N(in2[2]), .A1N(add_sub), .B0(in2[3]), .Y(n102) );
CLKINVX3TS U118 ( .A(in2[3]), .Y(n114) );
NOR2X1TS U119 ( .A(n19), .B(in2[12]), .Y(n39) );
NOR2XLTS U120 ( .A(n20), .B(in2[18]), .Y(n51) );
XOR2X1TS U121 ( .A(n180), .B(in2[22]), .Y(n181) );
XNOR2X1TS U122 ( .A(n205), .B(in2[28]), .Y(n206) );
INVX4TS U123 ( .A(in2[2]), .Y(n366) );
NAND2X2TS U124 ( .A(n138), .B(in1[12]), .Y(n330) );
NAND2X1TS U125 ( .A(n226), .B(in1[30]), .Y(n242) );
INVX12TS U126 ( .A(add_sub), .Y(n369) );
NAND2X1TS U127 ( .A(n43), .B(n305), .Y(n306) );
AND2X4TS U128 ( .A(n30), .B(n31), .Y(n6) );
NAND2X2TS U129 ( .A(n108), .B(in1[5]), .Y(n355) );
NAND2X2TS U130 ( .A(n70), .B(n69), .Y(n68) );
INVX3TS U131 ( .A(n236), .Y(n75) );
INVX2TS U132 ( .A(n239), .Y(n233) );
NOR2X4TS U133 ( .A(n13), .B(n314), .Y(n58) );
NAND2X1TS U134 ( .A(n7), .B(n315), .Y(n316) );
NAND2X2TS U135 ( .A(n85), .B(n83), .Y(n35) );
INVX2TS U136 ( .A(n330), .Y(n139) );
INVX4TS U137 ( .A(n342), .Y(n123) );
NOR2X4TS U138 ( .A(n53), .B(n228), .Y(n52) );
NAND3X4TS U139 ( .A(n71), .B(n68), .C(n67), .Y(n73) );
NOR2X4TS U140 ( .A(n193), .B(n74), .Y(n66) );
NAND2X4TS U141 ( .A(n216), .B(n75), .Y(n74) );
NAND2X2TS U142 ( .A(n233), .B(n237), .Y(n234) );
NOR2X4TS U143 ( .A(n25), .B(n304), .Y(n24) );
INVX4TS U144 ( .A(n44), .Y(n25) );
NAND2X4TS U145 ( .A(n47), .B(n45), .Y(n44) );
INVX2TS U146 ( .A(n250), .Y(n213) );
INVX2TS U147 ( .A(n262), .Y(n210) );
INVX4TS U148 ( .A(n158), .Y(n45) );
MX2X2TS U149 ( .A(in2[19]), .B(n163), .S0(n20), .Y(n168) );
INVX4TS U150 ( .A(n308), .Y(n158) );
NOR2X4TS U151 ( .A(n58), .B(n63), .Y(n57) );
NAND2X2TS U152 ( .A(n196), .B(n201), .Y(n197) );
NAND2X1TS U153 ( .A(n321), .B(n320), .Y(n322) );
NOR2X6TS U154 ( .A(n324), .B(n319), .Y(n147) );
INVX2TS U155 ( .A(n315), .Y(n63) );
OR2X4TS U156 ( .A(n137), .B(in1[11]), .Y(n85) );
NAND2X4TS U157 ( .A(n131), .B(in1[10]), .Y(n336) );
NAND2X4TS U158 ( .A(n145), .B(in1[13]), .Y(n325) );
NAND2X4TS U159 ( .A(n122), .B(in1[8]), .Y(n342) );
XOR2X2TS U160 ( .A(n141), .B(in2[13]), .Y(n142) );
NOR2X4TS U161 ( .A(n134), .B(in2[10]), .Y(n135) );
NAND2X6TS U162 ( .A(n150), .B(n149), .Y(n143) );
NAND2X4TS U163 ( .A(n29), .B(n28), .Y(n27) );
NAND3X4TS U164 ( .A(n101), .B(n223), .C(in2[3]), .Y(n104) );
NOR2X4TS U165 ( .A(in2[13]), .B(in2[12]), .Y(n149) );
XOR2X1TS U166 ( .A(n307), .B(n306), .Y(res[18]) );
XOR2X1TS U167 ( .A(n317), .B(n316), .Y(res[15]) );
NAND2BX2TS U168 ( .AN(n191), .B(n72), .Y(n71) );
NAND2X4TS U169 ( .A(n87), .B(n225), .Y(n236) );
AOI21X2TS U170 ( .A0(n84), .A1(n246), .B0(n213), .Y(n214) );
OA21X4TS U171 ( .A0(n300), .A1(n294), .B0(n295), .Y(n170) );
NOR2X6TS U172 ( .A(n284), .B(n282), .Y(n276) );
NAND2X4TS U173 ( .A(n91), .B(n84), .Y(n215) );
NOR2X6TS U174 ( .A(n277), .B(n270), .Y(n192) );
NOR2X2TS U175 ( .A(n299), .B(n294), .Y(n171) );
XOR2X1TS U176 ( .A(n332), .B(n331), .Y(res[12]) );
XOR2X1TS U177 ( .A(n327), .B(n61), .Y(res[13]) );
NAND2X2TS U178 ( .A(n190), .B(in1[24]), .Y(n271) );
OR2X4TS U179 ( .A(n212), .B(in1[28]), .Y(n84) );
NAND2X4TS U180 ( .A(n187), .B(in1[21]), .Y(n289) );
MX2X2TS U181 ( .A(in2[30]), .B(n224), .S0(n223), .Y(n226) );
MX2X4TS U182 ( .A(in2[27]), .B(n203), .S0(n223), .Y(n211) );
NAND2X2TS U183 ( .A(n160), .B(in1[18]), .Y(n305) );
MX2X2TS U184 ( .A(in2[28]), .B(n206), .S0(n223), .Y(n212) );
MX2X4TS U185 ( .A(in2[23]), .B(n173), .S0(add_sub), .Y(n189) );
OR2X4TS U186 ( .A(n157), .B(in1[17]), .Y(n82) );
XNOR2X2TS U187 ( .A(n172), .B(in2[23]), .Y(n173) );
XNOR2X2TS U188 ( .A(n162), .B(in2[19]), .Y(n163) );
NAND2X6TS U189 ( .A(n16), .B(n21), .Y(n338) );
NOR3X6TS U190 ( .A(n218), .B(in2[28]), .C(n217), .Y(n222) );
XOR2X1TS U191 ( .A(n341), .B(n340), .Y(res[9]) );
NAND2BX4TS U192 ( .AN(n174), .B(n176), .Y(n183) );
INVX4TS U193 ( .A(n36), .Y(n90) );
NAND2X2TS U194 ( .A(n15), .B(n123), .Y(n38) );
INVX4TS U195 ( .A(n314), .Y(n7) );
MX2X2TS U196 ( .A(in2[11]), .B(n136), .S0(n19), .Y(n137) );
OR2X6TS U197 ( .A(n127), .B(in1[9]), .Y(n15) );
XNOR2X2TS U198 ( .A(n135), .B(in2[11]), .Y(n136) );
OR2X2TS U199 ( .A(n19), .B(in2[10]), .Y(n12) );
OAI21XLTS U200 ( .A0(n370), .A1(n369), .B0(n368), .Y(res[3]) );
OAI21XLTS U201 ( .A0(n369), .A1(n363), .B0(n362), .Y(res[1]) );
OAI21XLTS U202 ( .A0(n365), .A1(n369), .B0(n364), .Y(res[2]) );
NAND4BX2TS U203 ( .AN(in2[5]), .B(n116), .C(n115), .D(n114), .Y(n117) );
NAND2X2TS U204 ( .A(n201), .B(n200), .Y(n204) );
NOR3X4TS U205 ( .A(n109), .B(in2[0]), .C(in2[3]), .Y(n110) );
OR2X1TS U206 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
NAND2X1TS U207 ( .A(n313), .B(n18), .Y(n8) );
OR2X4TS U208 ( .A(n156), .B(in1[16]), .Y(n18) );
XNOR2X4TS U209 ( .A(n143), .B(in2[14]), .Y(n144) );
NAND3X6TS U210 ( .A(n88), .B(n359), .C(n361), .Y(n41) );
NAND2BX4TS U211 ( .AN(n198), .B(n105), .Y(n106) );
OR2X6TS U212 ( .A(n42), .B(n358), .Y(n40) );
OR2X6TS U213 ( .A(n107), .B(in1[4]), .Y(n359) );
AND4X6TS U214 ( .A(n104), .B(n105), .C(in1[3]), .D(n103), .Y(n107) );
CLKINVX12TS U215 ( .A(n143), .Y(n97) );
NOR2X4TS U216 ( .A(in2[16]), .B(n98), .Y(n99) );
NAND2X6TS U217 ( .A(n107), .B(in1[4]), .Y(n358) );
OAI21X4TS U218 ( .A0(n270), .A1(n278), .B0(n271), .Y(n191) );
NOR2X4TS U219 ( .A(n190), .B(in1[24]), .Y(n270) );
NOR2X8TS U220 ( .A(n108), .B(in1[5]), .Y(n42) );
XNOR2X2TS U221 ( .A(n197), .B(in2[26]), .Y(n199) );
XNOR2X4TS U222 ( .A(n11), .B(n10), .Y(n9) );
AO21X4TS U223 ( .A0(n56), .A1(n95), .B0(n369), .Y(n11) );
AOI21X4TS U224 ( .A0(n133), .A1(n223), .B0(n39), .Y(n138) );
MXI2X4TS U225 ( .A(n178), .B(n177), .S0(add_sub), .Y(n190) );
MXI2X4TS U226 ( .A(n200), .B(n199), .S0(n20), .Y(n208) );
CLKINVX12TS U227 ( .A(n98), .Y(n176) );
XOR2X2TS U228 ( .A(n274), .B(n273), .Y(res[24]) );
NOR2X6TS U229 ( .A(n153), .B(in1[15]), .Y(n314) );
MX2X4TS U230 ( .A(in2[15]), .B(n152), .S0(n19), .Y(n153) );
XOR2X2TS U231 ( .A(n281), .B(n280), .Y(res[23]) );
NOR2X4TS U232 ( .A(n146), .B(in1[14]), .Y(n319) );
NOR2X4TS U233 ( .A(n145), .B(in1[13]), .Y(n324) );
MX2X4TS U234 ( .A(in2[13]), .B(n142), .S0(n19), .Y(n145) );
INVX8TS U235 ( .A(n244), .Y(n265) );
XNOR2X4TS U236 ( .A(n261), .B(n260), .Y(res[26]) );
NOR3X4TS U237 ( .A(in2[0]), .B(in2[4]), .C(in2[6]), .Y(n116) );
NAND2X8TS U238 ( .A(n176), .B(n175), .Y(n218) );
XNOR2X4TS U239 ( .A(n257), .B(n256), .Y(res[27]) );
OR2X8TS U240 ( .A(in2[4]), .B(in2[5]), .Y(n109) );
XOR2X4TS U241 ( .A(n111), .B(in2[6]), .Y(n112) );
XNOR2X2TS U242 ( .A(n252), .B(n251), .Y(res[28]) );
OAI21X2TS U243 ( .A0(n94), .A1(n54), .B0(n93), .Y(res[32]) );
OA21X4TS U244 ( .A0(n319), .A1(n325), .B0(n320), .Y(n13) );
NAND2X2TS U245 ( .A(n146), .B(in1[14]), .Y(n320) );
NOR2X4TS U246 ( .A(n183), .B(n179), .Y(n180) );
MXI2X4TS U247 ( .A(n182), .B(n181), .S0(n20), .Y(n188) );
NOR2X4TS U248 ( .A(n188), .B(in1[22]), .Y(n284) );
INVX4TS U249 ( .A(n37), .Y(n131) );
MXI2X4TS U250 ( .A(n155), .B(n154), .S0(n20), .Y(n156) );
INVX2TS U251 ( .A(in2[16]), .Y(n155) );
NAND2X2TS U252 ( .A(n112), .B(in1[6]), .Y(n350) );
OR2X2TS U253 ( .A(n112), .B(in1[6]), .Y(n92) );
NAND2X2TS U254 ( .A(n156), .B(in1[16]), .Y(n311) );
OR2X4TS U255 ( .A(n208), .B(in1[26]), .Y(n89) );
NAND2X4TS U256 ( .A(n207), .B(in1[25]), .Y(n262) );
NAND2X2TS U257 ( .A(n208), .B(in1[26]), .Y(n259) );
NAND2X2TS U258 ( .A(n165), .B(n164), .Y(n174) );
NOR3X4TS U259 ( .A(in2[2]), .B(in2[4]), .C(in2[3]), .Y(n56) );
XOR2X1TS U260 ( .A(n117), .B(in2[7]), .Y(n118) );
MXI2X4TS U261 ( .A(n121), .B(n120), .S0(add_sub), .Y(n122) );
MXI2X4TS U262 ( .A(n126), .B(n125), .S0(add_sub), .Y(n127) );
NOR2X4TS U263 ( .A(n129), .B(in2[8]), .Y(n124) );
XOR2X1TS U264 ( .A(n150), .B(in2[12]), .Y(n133) );
AOI21X2TS U265 ( .A0(n159), .A1(n20), .B0(n51), .Y(n160) );
INVX2TS U266 ( .A(in2[22]), .Y(n182) );
NOR2X4TS U267 ( .A(n187), .B(in1[21]), .Y(n282) );
INVX2TS U268 ( .A(in2[24]), .Y(n178) );
INVX2TS U269 ( .A(n255), .Y(n246) );
INVX2TS U270 ( .A(n275), .Y(n72) );
NOR2X4TS U271 ( .A(n119), .B(in1[7]), .Y(n345) );
INVX2TS U272 ( .A(n350), .Y(n113) );
NAND2X2TS U273 ( .A(n119), .B(in1[7]), .Y(n346) );
NAND2X2TS U274 ( .A(n127), .B(in1[9]), .Y(n339) );
AND2X4TS U275 ( .A(n137), .B(in1[11]), .Y(n329) );
NOR2X2TS U276 ( .A(n158), .B(n49), .Y(n48) );
INVX2TS U277 ( .A(n311), .Y(n49) );
INVX2TS U278 ( .A(n82), .Y(n47) );
INVX2TS U279 ( .A(n282), .Y(n290) );
INVX2TS U280 ( .A(n289), .Y(n283) );
INVX8TS U281 ( .A(n266), .Y(n292) );
NOR2X1TS U282 ( .A(n267), .B(n277), .Y(n269) );
INVX2TS U283 ( .A(n276), .Y(n267) );
INVX2TS U284 ( .A(n258), .Y(n263) );
NOR2X2TS U285 ( .A(n207), .B(in1[25]), .Y(n258) );
NAND2X2TS U286 ( .A(n211), .B(in1[27]), .Y(n255) );
NAND2X4TS U287 ( .A(n263), .B(n89), .Y(n254) );
INVX2TS U288 ( .A(n259), .Y(n209) );
NAND2X2TS U289 ( .A(n212), .B(in1[28]), .Y(n250) );
INVX2TS U290 ( .A(n254), .Y(n245) );
INVX2TS U291 ( .A(n241), .Y(n225) );
NOR2X4TS U292 ( .A(n220), .B(in1[29]), .Y(n241) );
INVX4TS U293 ( .A(n95), .Y(n101) );
NOR2X4TS U294 ( .A(in2[1]), .B(in2[2]), .Y(n115) );
NAND2X2TS U295 ( .A(n15), .B(n86), .Y(n22) );
NAND2X1TS U296 ( .A(n150), .B(n140), .Y(n141) );
MXI2X2TS U297 ( .A(n148), .B(n144), .S0(n223), .Y(n146) );
NAND3X1TS U298 ( .A(n150), .B(n149), .C(n148), .Y(n151) );
AND2X2TS U299 ( .A(n147), .B(n7), .Y(n17) );
INVX2TS U300 ( .A(in2[20]), .Y(n167) );
MXI2X4TS U301 ( .A(n186), .B(n185), .S0(add_sub), .Y(n187) );
NOR2X4TS U302 ( .A(n254), .B(n215), .Y(n216) );
INVX2TS U303 ( .A(n191), .Y(n70) );
INVX2TS U304 ( .A(n192), .Y(n69) );
INVX2TS U305 ( .A(n147), .Y(n60) );
INVX2TS U306 ( .A(n318), .Y(n61) );
INVX2TS U307 ( .A(n13), .Y(n62) );
NAND2X2TS U308 ( .A(n153), .B(in1[15]), .Y(n315) );
NOR2X2TS U309 ( .A(n168), .B(in1[19]), .Y(n299) );
INVX2TS U310 ( .A(n293), .Y(n303) );
NOR2X4TS U311 ( .A(n14), .B(n241), .Y(n53) );
INVX2TS U312 ( .A(n242), .Y(n227) );
NOR2X4TS U313 ( .A(n232), .B(in1[31]), .Y(n239) );
AOI21X1TS U314 ( .A0(n369), .A1(in2[2]), .B0(in1[2]), .Y(n364) );
NAND2X1TS U315 ( .A(n359), .B(n358), .Y(n360) );
OAI21XLTS U316 ( .A0(n354), .A1(n353), .B0(n358), .Y(n357) );
NAND2X1TS U317 ( .A(n88), .B(n355), .Y(n356) );
INVX2TS U318 ( .A(n359), .Y(n353) );
NAND2X1TS U319 ( .A(n92), .B(n350), .Y(n351) );
NAND2X1TS U320 ( .A(n347), .B(n346), .Y(n348) );
INVX2TS U321 ( .A(n345), .Y(n347) );
NAND2X1TS U322 ( .A(n86), .B(n342), .Y(n344) );
NAND2X1TS U323 ( .A(n15), .B(n339), .Y(n341) );
NAND2X1TS U324 ( .A(n90), .B(n336), .Y(n337) );
NAND2X1TS U325 ( .A(n85), .B(n333), .Y(n335) );
INVX2TS U326 ( .A(n329), .Y(n333) );
NAND2X1TS U327 ( .A(n326), .B(n325), .Y(n327) );
INVX2TS U328 ( .A(n324), .Y(n326) );
NAND2X1TS U329 ( .A(n18), .B(n311), .Y(n312) );
XNOR2X1TS U330 ( .A(n310), .B(n309), .Y(res[17]) );
NAND2X1TS U331 ( .A(n46), .B(n44), .Y(n307) );
XOR2X1TS U332 ( .A(n303), .B(n302), .Y(res[19]) );
INVX2TS U333 ( .A(n299), .Y(n301) );
XNOR2X1TS U334 ( .A(n298), .B(n297), .Y(res[20]) );
OAI21X1TS U335 ( .A0(n303), .A1(n299), .B0(n300), .Y(n298) );
INVX2TS U336 ( .A(n294), .Y(n296) );
XNOR2X1TS U337 ( .A(n292), .B(n291), .Y(res[21]) );
INVX2TS U338 ( .A(n284), .Y(n286) );
INVX2TS U339 ( .A(n277), .Y(n279) );
INVX2TS U340 ( .A(n270), .Y(n272) );
XOR2X1TS U341 ( .A(n265), .B(n264), .Y(res[25]) );
NAND2X1TS U342 ( .A(n245), .B(n91), .Y(n249) );
OR2X2TS U343 ( .A(n239), .B(n236), .Y(n94) );
INVX3TS U344 ( .A(n77), .Y(n266) );
AND2X4TS U345 ( .A(n38), .B(n339), .Y(n16) );
NAND2X4TS U346 ( .A(n157), .B(in1[17]), .Y(n308) );
MX2X4TS U347 ( .A(in2[17]), .B(n100), .S0(n19), .Y(n157) );
XOR2X2TS U348 ( .A(n129), .B(n121), .Y(n120) );
AOI21X1TS U349 ( .A0(n334), .A1(n85), .B0(n329), .Y(n332) );
XNOR2X2TS U350 ( .A(n194), .B(in2[25]), .Y(n195) );
NOR2X4TS U351 ( .A(n218), .B(in2[24]), .Y(n194) );
INVX8TS U352 ( .A(n42), .Y(n88) );
NAND2X8TS U353 ( .A(n50), .B(n305), .Y(n293) );
AOI21X1TS U354 ( .A0(n343), .A1(n86), .B0(n123), .Y(n340) );
OA21X4TS U355 ( .A0(n253), .A1(n215), .B0(n214), .Y(n14) );
INVX2TS U356 ( .A(n240), .Y(n228) );
INVX2TS U357 ( .A(n361), .Y(n354) );
INVX2TS U358 ( .A(n193), .Y(n76) );
NAND2X4TS U359 ( .A(n192), .B(n276), .Y(n193) );
NOR2X2TS U360 ( .A(n160), .B(in1[18]), .Y(n304) );
INVX2TS U361 ( .A(n304), .Y(n43) );
INVX2TS U362 ( .A(in2[12]), .Y(n140) );
OAI21X1TS U363 ( .A0(n61), .A1(n324), .B0(n325), .Y(n323) );
OAI2BB1X2TS U364 ( .A0N(n130), .A1N(n19), .B0(n12), .Y(n37) );
NAND3X6TS U365 ( .A(n41), .B(n40), .C(n355), .Y(n352) );
NAND2X8TS U366 ( .A(n77), .B(n76), .Y(n80) );
NAND2X8TS U367 ( .A(n26), .B(n170), .Y(n77) );
NAND2BX4TS U368 ( .AN(n22), .B(n343), .Y(n21) );
NAND2X6TS U369 ( .A(n318), .B(n17), .Y(n23) );
CLKINVX12TS U370 ( .A(n105), .Y(n32) );
NAND2X8TS U371 ( .A(n23), .B(n57), .Y(n313) );
NOR4X2TS U372 ( .A(n174), .B(n179), .C(in2[23]), .D(in2[22]), .Y(n175) );
NAND2X8TS U373 ( .A(n46), .B(n24), .Y(n50) );
NAND2X8TS U374 ( .A(n64), .B(n48), .Y(n46) );
NAND2X8TS U375 ( .A(n293), .B(n171), .Y(n26) );
NAND2X8TS U376 ( .A(n32), .B(n6), .Y(n129) );
AND2X8TS U377 ( .A(n79), .B(n14), .Y(n54) );
NOR2X8TS U378 ( .A(n27), .B(n129), .Y(n150) );
NAND3X8TS U379 ( .A(n95), .B(n366), .C(n114), .Y(n105) );
NAND2X8TS U380 ( .A(n97), .B(n33), .Y(n98) );
NAND2X8TS U381 ( .A(n80), .B(n81), .Y(n244) );
OAI21X4TS U382 ( .A0(n328), .A1(n35), .B0(n34), .Y(n318) );
AOI21X4TS U383 ( .A0(n338), .A1(n90), .B0(n132), .Y(n328) );
OAI21X4TS U384 ( .A0(n79), .A1(n241), .B0(n52), .Y(n55) );
XNOR2X2TS U385 ( .A(n55), .B(n243), .Y(res[30]) );
NOR2X8TS U386 ( .A(in2[0]), .B(in2[1]), .Y(n95) );
NAND2X8TS U387 ( .A(n313), .B(n18), .Y(n64) );
AOI21X4TS U388 ( .A0(n192), .A1(n275), .B0(n191), .Y(n81) );
NAND2X8TS U389 ( .A(n244), .B(n216), .Y(n79) );
OA21X4TS U390 ( .A0(n14), .A1(n236), .B0(n238), .Y(n78) );
XNOR2X1TS U391 ( .A(n352), .B(n351), .Y(res[6]) );
XNOR2X1TS U392 ( .A(n337), .B(n338), .Y(res[10]) );
XOR2XLTS U393 ( .A(n349), .B(n348), .Y(res[7]) );
XNOR2X1TS U394 ( .A(n312), .B(n313), .Y(res[16]) );
XNOR2X1TS U395 ( .A(n344), .B(n343), .Y(res[8]) );
CLKINVX1TS U396 ( .A(n328), .Y(n334) );
NAND2X4TS U397 ( .A(n121), .B(n126), .Y(n128) );
OAI21X2TS U398 ( .A0(in2[3]), .A1(n369), .B0(n102), .Y(n103) );
INVX2TS U399 ( .A(n336), .Y(n132) );
OAI21X2TS U400 ( .A0(n72), .A1(n277), .B0(n278), .Y(n268) );
INVX2TS U401 ( .A(in2[9]), .Y(n126) );
INVX2TS U402 ( .A(in2[15]), .Y(n96) );
XNOR2X1TS U403 ( .A(n99), .B(in2[17]), .Y(n100) );
XNOR2X4TS U404 ( .A(n106), .B(in2[4]), .Y(n361) );
AOI21X4TS U405 ( .A0(n352), .A1(n92), .B0(n113), .Y(n349) );
OAI21X4TS U406 ( .A0(n349), .A1(n345), .B0(n346), .Y(n343) );
XNOR2X1TS U407 ( .A(n134), .B(in2[10]), .Y(n130) );
XNOR2X1TS U408 ( .A(n161), .B(in2[18]), .Y(n159) );
OAI21X4TS U409 ( .A0(n284), .A1(n289), .B0(n285), .Y(n275) );
INVX2TS U410 ( .A(in2[26]), .Y(n200) );
XNOR2X1TS U411 ( .A(n202), .B(in2[27]), .Y(n203) );
AOI21X4TS U412 ( .A0(n89), .A1(n210), .B0(n209), .Y(n253) );
XOR2X4TS U413 ( .A(n54), .B(n221), .Y(res[29]) );
NAND2BX4TS U414 ( .AN(in2[29]), .B(n222), .Y(n229) );
XOR2X1TS U415 ( .A(n229), .B(in2[30]), .Y(n224) );
AOI21X4TS U416 ( .A0(n87), .A1(n228), .B0(n227), .Y(n238) );
XNOR2X1TS U417 ( .A(n230), .B(in2[31]), .Y(n231) );
XNOR2X4TS U418 ( .A(n235), .B(n234), .Y(res[31]) );
INVX2TS U419 ( .A(n253), .Y(n247) );
AOI21X4TS U420 ( .A0(n247), .A1(n91), .B0(n246), .Y(n248) );
OAI21X4TS U421 ( .A0(n265), .A1(n249), .B0(n248), .Y(n252) );
OAI21X4TS U422 ( .A0(n265), .A1(n254), .B0(n253), .Y(n257) );
OAI21X4TS U423 ( .A0(n265), .A1(n258), .B0(n262), .Y(n261) );
AOI21X4TS U424 ( .A0(n292), .A1(n269), .B0(n268), .Y(n274) );
AOI21X4TS U425 ( .A0(n292), .A1(n276), .B0(n275), .Y(n281) );
AOI21X4TS U426 ( .A0(n292), .A1(n290), .B0(n283), .Y(n288) );
INVX2TS U427 ( .A(n319), .Y(n321) );
XNOR2X1TS U428 ( .A(n323), .B(n322), .Y(res[14]) );
XNOR2X1TS U429 ( .A(n335), .B(n334), .Y(res[11]) );
XNOR2X1TS U430 ( .A(n357), .B(n356), .Y(res[5]) );
XNOR2X1TS U431 ( .A(n361), .B(n360), .Y(res[4]) );
XNOR2X1TS U432 ( .A(in2[0]), .B(in2[1]), .Y(n363) );
AOI21X1TS U433 ( .A0(n369), .A1(in2[1]), .B0(in1[1]), .Y(n362) );
XNOR2X1TS U434 ( .A(n95), .B(n366), .Y(n365) );
NAND2X1TS U435 ( .A(n95), .B(n366), .Y(n367) );
XNOR2X1TS U436 ( .A(n367), .B(in2[3]), .Y(n370) );
AOI21X1TS U437 ( .A0(n369), .A1(in2[3]), .B0(in1[3]), .Y(n368) );
initial $sdf_annotate("Approx_adder_LOALPL4_syn.sdf");
endmodule
|
// MBT 5/1/2017 Fast simulation mastercalibration module
//
// FPGA calibration module (example, only implements Phase 1 and dummy Phase 0,2,3)
//
// See BSG Source Synchronous I/O for specification of this.
//
// everything beginning with "out" is the output channel clock
// everything beginning with "in" is the input channel clock
//
// respect the clock domains!
//
// tests_lp defines the number of real tests; but we have one more "fake"
// test at the end, which causes activation or deactivation of the channel
//
//
`include "bsg_defines.v"
module bsg_source_sync_channel_control_master #(parameter `BSG_INV_PARAM( width_p )
, parameter lg_token_width_p = 6
, parameter lg_out_prepare_hold_cycles_p = 6
// bit vector
, parameter bypass_test_p = 5'b0
, parameter tests_lp = 5
, parameter verbose_lp = 1
)
(// output channel
input out_clk_i
, input out_reset_i // note this is just a synchronized version of core_reset
// we can do calibration in parallel, or channel-by-channel
, input [$clog2(tests_lp+1)-1:0] out_calibration_state_i
, input out_calib_prepare_i // essentially the reset signal
// ignore, we assume all channels are blessed
, input out_channel_blessed_i
// this is used to force data on to the output channel
// (calibration modes 0 and 1)
, output out_override_en_o
, output [width_p+1-1:0] out_override_valid_data_o
// ignore
, input out_override_is_posedge_i
// whether the test passed
, output [tests_lp+1-1:0] out_test_pass_r_o
// ignore
, input in_clk_i
, input in_reset_i
// ignore
, input [width_p+1-1:0] in_snoop_valid_data_neg_i
// ignore
, input [width_p+1-1:0] in_snoop_valid_data_pos_i
// hardwired to zero
, output out_infinite_credits_o
);
assign out_infinite_credits_o = 1'b0;
// memory mapped registers
logic [width_p+1-1:0] valid_data_r; // 0
logic override_r; // 1
logic [tests_lp+1-1:0] out_test_pass_r; // 2
logic [$clog2(tests_lp+1):0] match_reg_r; // 3
assign out_override_valid_data_o = valid_data_r;
assign out_override_en_o = override_r;
assign out_test_pass_r_o = out_test_pass_r;
//
// opcode4 <addr2>, <data14>
//
wire v_lo, v_li;
wire [15:0] data_lo, data_li;
wire yumi_li;
localparam match_size_lp = $clog2(tests_lp+1)+1;
// handle opcode4 -> send
// we convert this into a memory mapped write
always_ff @(posedge out_clk_i)
if (out_reset_i)
begin
valid_data_r <= 0;
override_r <= 0;
out_test_pass_r <= 0;
match_reg_r <= 0;
end
else
begin
if (v_lo)
begin
if (data_lo[15:14] == 0)
valid_data_r <= data_lo[0+:width_p+1];
else
if (data_lo[15:14] == 1)
override_r <= data_lo[0];
else
if (data_lo[15:14] == 2)
out_test_pass_r <= data_lo[0+:tests_lp+1];
else
if (data_lo[15:14] == 3)
match_reg_r <= data_lo[0+:$clog2(tests_lp+1)+1];
end
end // else: !if(out_reset_i)
assign yumi_li = v_lo;
// handle opcode -> receive
assign data_li = 16'b0;
assign v_li = (match_reg_r == {out_calib_prepare_i, out_calibration_state_i});
localparam rom_addr_width_lp = 6;
wire [rom_addr_width_lp-1:0] rom_addr_li;
wire [4+16-1:0] rom_data_lo;
bsg_fsb_node_trace_replay
#(.ring_width_p(16)
,.rom_addr_width_p(rom_addr_width_lp)
) tr
(.clk_i(out_clk_i)
,.reset_i(out_reset_i)
,.en_i(1'b1)
,.v_i (v_li)
,.data_i (data_li)
,.ready_o() // ignored
,.v_o (v_lo)
,.data_o (data_lo)
,.yumi_i (yumi_li)
,.rom_addr_o(rom_addr_li)
,.rom_data_i(rom_data_lo)
,.done_o() // cheeky mapping to done signal
,.error_o()
);
// generated with bsg_fsb_master_rom
bsg_comm_link_master_calib_skip_rom
#(.width_p(4+16)
,.addr_width_p(rom_addr_width_lp)
) comm_link_master_rom
(.addr_i(rom_addr_li)
,.data_o(rom_data_lo)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_source_sync_channel_control_master)
|
/*****************************************************************************/
//
// Module : cae_pers.v
// Last Modified On: 2013/07/22 14:37
// Last Modified By: Osama Attia
//
//-----------------------------------------------------------------------------
//
// Original Author : gedwards
// Created On : Wed Oct 10 09:26:08 2007
// TODO: add author information
//-----------------------------------------------------------------------------
//
// Description : parallelCyGraph personality
//
// Top-level of parallelCyGraph personality. For a complete list of
// optional ports, see
// /opt/convey/pdk/<rev>/<platform>/doc/cae_pers.v
//
//-----------------------------------------------------------------------------
//
// Copyright (c) 2007-2011 : created by Convey Computer Corp. This model is the
// confidential and proprietary property of Convey Computer Corp.
//
/*****************************************************************************/
/* $Id: cae_pers.v,v 1.4.1.4 2012/03/07 15:41:55 ktown Exp ktown $ */
`timescale 1 ns / 1 ps
`include "pdk_fpga_defines.vh"
(* keep_hierarchy = "true" *)
module cae_pers (
input clk_csr,
input clk,
input clk2x,
input i_reset,
input i_csr_reset_n,
input [1:0] i_aeid,
input ppll_reset,
output ppll_locked,
output clk_per,
//
// Dispatch Interface
//
input [31:0] cae_inst,
input [63:0] cae_data,
input cae_inst_vld,
output [17:0] cae_aeg_cnt,
output [15:0] cae_exception,
output [63:0] cae_ret_data,
output cae_ret_data_vld,
output cae_idle,
output cae_stall,
//
// MC Interface(s)
//
output mc0_req_ld_e, mc0_req_ld_o,
output mc0_req_st_e, mc0_req_st_o,
output [1:0] mc0_req_size_e, mc0_req_size_o,
output [47:0] mc0_req_vadr_e, mc0_req_vadr_o,
output [63:0] mc0_req_wrd_rdctl_e, mc0_req_wrd_rdctl_o,
output mc0_rsp_stall_e, mc0_rsp_stall_o,
input mc0_rd_rq_stall_e, mc0_rd_rq_stall_o,
input mc0_wr_rq_stall_e, mc0_wr_rq_stall_o,
input [63:0] mc0_rsp_data_e, mc0_rsp_data_o,
input mc0_rsp_push_e, mc0_rsp_push_o,
input [31:0] mc0_rsp_rdctl_e, mc0_rsp_rdctl_o,
output mc1_req_ld_e, mc1_req_ld_o,
output mc1_req_st_e, mc1_req_st_o,
output [1:0] mc1_req_size_e, mc1_req_size_o,
output [47:0] mc1_req_vadr_e, mc1_req_vadr_o,
output [63:0] mc1_req_wrd_rdctl_e, mc1_req_wrd_rdctl_o,
output mc1_rsp_stall_e, mc1_rsp_stall_o,
input mc1_rd_rq_stall_e, mc1_rd_rq_stall_o,
input mc1_wr_rq_stall_e, mc1_wr_rq_stall_o,
input [63:0] mc1_rsp_data_e, mc1_rsp_data_o,
input mc1_rsp_push_e, mc1_rsp_push_o,
input [31:0] mc1_rsp_rdctl_e, mc1_rsp_rdctl_o,
output mc2_req_ld_e, mc2_req_ld_o,
output mc2_req_st_e, mc2_req_st_o,
output [1:0] mc2_req_size_e, mc2_req_size_o,
output [47:0] mc2_req_vadr_e, mc2_req_vadr_o,
output [63:0] mc2_req_wrd_rdctl_e, mc2_req_wrd_rdctl_o,
output mc2_rsp_stall_e, mc2_rsp_stall_o,
input mc2_rd_rq_stall_e, mc2_rd_rq_stall_o,
input mc2_wr_rq_stall_e, mc2_wr_rq_stall_o,
input [63:0] mc2_rsp_data_e, mc2_rsp_data_o,
input mc2_rsp_push_e, mc2_rsp_push_o,
input [31:0] mc2_rsp_rdctl_e, mc2_rsp_rdctl_o,
output mc3_req_ld_e, mc3_req_ld_o,
output mc3_req_st_e, mc3_req_st_o,
output [1:0] mc3_req_size_e, mc3_req_size_o,
output [47:0] mc3_req_vadr_e, mc3_req_vadr_o,
output [63:0] mc3_req_wrd_rdctl_e, mc3_req_wrd_rdctl_o,
output mc3_rsp_stall_e, mc3_rsp_stall_o,
input mc3_rd_rq_stall_e, mc3_rd_rq_stall_o,
input mc3_wr_rq_stall_e, mc3_wr_rq_stall_o,
input [63:0] mc3_rsp_data_e, mc3_rsp_data_o,
input mc3_rsp_push_e, mc3_rsp_push_o,
input [31:0] mc3_rsp_rdctl_e, mc3_rsp_rdctl_o,
output mc4_req_ld_e, mc4_req_ld_o,
output mc4_req_st_e, mc4_req_st_o,
output [1:0] mc4_req_size_e, mc4_req_size_o,
output [47:0] mc4_req_vadr_e, mc4_req_vadr_o,
output [63:0] mc4_req_wrd_rdctl_e, mc4_req_wrd_rdctl_o,
output mc4_rsp_stall_e, mc4_rsp_stall_o,
input mc4_rd_rq_stall_e, mc4_rd_rq_stall_o,
input mc4_wr_rq_stall_e, mc4_wr_rq_stall_o,
input [63:0] mc4_rsp_data_e, mc4_rsp_data_o,
input mc4_rsp_push_e, mc4_rsp_push_o,
input [31:0] mc4_rsp_rdctl_e, mc4_rsp_rdctl_o,
output mc5_req_ld_e, mc5_req_ld_o,
output mc5_req_st_e, mc5_req_st_o,
output [1:0] mc5_req_size_e, mc5_req_size_o,
output [47:0] mc5_req_vadr_e, mc5_req_vadr_o,
output [63:0] mc5_req_wrd_rdctl_e, mc5_req_wrd_rdctl_o,
output mc5_rsp_stall_e, mc5_rsp_stall_o,
input mc5_rd_rq_stall_e, mc5_rd_rq_stall_o,
input mc5_wr_rq_stall_e, mc5_wr_rq_stall_o,
input [63:0] mc5_rsp_data_e, mc5_rsp_data_o,
input mc5_rsp_push_e, mc5_rsp_push_o,
input [31:0] mc5_rsp_rdctl_e, mc5_rsp_rdctl_o,
output mc6_req_ld_e, mc6_req_ld_o,
output mc6_req_st_e, mc6_req_st_o,
output [1:0] mc6_req_size_e, mc6_req_size_o,
output [47:0] mc6_req_vadr_e, mc6_req_vadr_o,
output [63:0] mc6_req_wrd_rdctl_e, mc6_req_wrd_rdctl_o,
output mc6_rsp_stall_e, mc6_rsp_stall_o,
input mc6_rd_rq_stall_e, mc6_rd_rq_stall_o,
input mc6_wr_rq_stall_e, mc6_wr_rq_stall_o,
input [63:0] mc6_rsp_data_e, mc6_rsp_data_o,
input mc6_rsp_push_e, mc6_rsp_push_o,
input [31:0] mc6_rsp_rdctl_e, mc6_rsp_rdctl_o,
output mc7_req_ld_e, mc7_req_ld_o,
output mc7_req_st_e, mc7_req_st_o,
output [1:0] mc7_req_size_e, mc7_req_size_o,
output [47:0] mc7_req_vadr_e, mc7_req_vadr_o,
output [63:0] mc7_req_wrd_rdctl_e, mc7_req_wrd_rdctl_o,
output mc7_rsp_stall_e, mc7_rsp_stall_o,
input mc7_rd_rq_stall_e, mc7_rd_rq_stall_o,
input mc7_wr_rq_stall_e, mc7_wr_rq_stall_o,
input [63:0] mc7_rsp_data_e, mc7_rsp_data_o,
input mc7_rsp_push_e, mc7_rsp_push_o,
input [31:0] mc7_rsp_rdctl_e, mc7_rsp_rdctl_o,
//
// Write flush
//
output mc0_req_flush_e, mc0_req_flush_o,
input mc0_rsp_flush_cmplt_e, mc0_rsp_flush_cmplt_o,
output mc1_req_flush_e, mc1_req_flush_o,
input mc1_rsp_flush_cmplt_e, mc1_rsp_flush_cmplt_o,
output mc2_req_flush_e, mc2_req_flush_o,
input mc2_rsp_flush_cmplt_e, mc2_rsp_flush_cmplt_o,
output mc3_req_flush_e, mc3_req_flush_o,
input mc3_rsp_flush_cmplt_e, mc3_rsp_flush_cmplt_o,
output mc4_req_flush_e, mc4_req_flush_o,
input mc4_rsp_flush_cmplt_e, mc4_rsp_flush_cmplt_o,
output mc5_req_flush_e, mc5_req_flush_o,
input mc5_rsp_flush_cmplt_e, mc5_rsp_flush_cmplt_o,
output mc6_req_flush_e, mc6_req_flush_o,
input mc6_rsp_flush_cmplt_e, mc6_rsp_flush_cmplt_o,
output mc7_req_flush_e, mc7_req_flush_o,
input mc7_rsp_flush_cmplt_e, mc7_rsp_flush_cmplt_o,
//
// AE-to-AE Interface
//
//`ifdef AE_AE_IF
input [31:0] nxtae_rx_data, prvae_rx_data,
input nxtae_rx_vld, prvae_rx_vld,
output nxtae_rx_stall, prvae_rx_stall,
output [31:0] nxtae_tx_data, prvae_tx_data,
output nxtae_tx_vld, prvae_tx_vld,
input nxtae_tx_stall, prvae_tx_stall,
output [65:0] prvae_nd0_tx_data,
output prvae_nd0_tx_vld,
input prvae_nd0_tx_stall,
input [65:0] nxtae_nd0_rx_data,
input nxtae_nd0_rx_vld,
output nxtae_nd0_rx_stall,
//`endif
//
// Management/Debug Interface
//
input [3:0] cae_ring_ctl_in,
input [15:0] cae_ring_data_in,
output [3:0] cae_ring_ctl_out,
output [15:0] cae_ring_data_out,
input csr_31_31_intlv_dis
);
initial $display("starting cae personality aeid:%d\n", i_aeid);
`include "pdk_fpga_param.vh"
//
// Local clock generation
//
(* KEEP = "true" *) wire reset_per;
cae_clock clock (
.clk(clk),
.i_reset(i_reset),
.ppll_reset(ppll_reset),
.clk_per(clk_per),
.ppll_locked(ppll_locked),
.reset_per(reset_per)
);
//
// Instruction decode
//
wire [4:0] inst_caep;
wire [17:0] inst_aeg_idx;
instdec dec (
.cae_inst(cae_inst),
.cae_data(cae_data),
.cae_inst_vld(cae_inst_vld),
.inst_val(inst_val),
.inst_caep(inst_caep),
.inst_aeg_wr(inst_aeg_wr),
.inst_aeg_rd(inst_aeg_rd),
.inst_aeg_idx(inst_aeg_idx),
.err_unimpl(err_unimpl)
);
//**************************************************************************
// PERSONALITY SPECIFIC LOGIC
//**************************************************************************
//
// AEG[0..NA-1] Registers
//
localparam NA = 51;
localparam NB = 6; // Number of bits to represent NAEG
assign cae_aeg_cnt = NA;
//output of aeg registers
wire [63:0] w_aeg[NA-1:0];
wire cygraph_enable;
wire cygraph_busy;
wire cygraph_done;
wire [63:0] nq_count;
genvar g;
generate for (g=0; g<NA; g=g+1) begin : g0
reg [63:0] c_aeg, r_aeg;
always @* begin
case (g)
//TODO: add cases for registers to be written to
8: begin
if (cygraph_done == 1'b1) begin
c_aeg = nq_count;
end
end
default: c_aeg = r_aeg;
endcase
end
wire c_aeg_we = inst_aeg_wr && inst_aeg_idx[NB-1:0] == g;
always @(posedge clk) begin
if (c_aeg_we) begin
r_aeg <= cae_data;
$display("writing: %x", cae_data);
end
else
r_aeg <= c_aeg;
end
assign w_aeg[g] = r_aeg;
end endgenerate
reg r_ret_val, r_err_unimpl, r_err_aegidx;
reg [63:0] r_ret_data;
wire c_val_aegidx = inst_aeg_idx < NA;
//return logic
always @(posedge clk) begin
r_ret_val <= inst_aeg_rd && c_val_aegidx;
r_ret_data <= w_aeg[inst_aeg_idx[NB-1:0]];
r_err_aegidx <= (inst_aeg_wr || inst_aeg_rd) && !c_val_aegidx;
//TODO: add logic to decide which instructions are implemented -- OSAMA
r_err_unimpl <= err_unimpl || (inst_val && (inst_caep !== 'd0/* && inst_caep !== 'd1 && inst_caep !== 'd2*/));
end
assign cae_ret_data_vld = r_ret_val;
assign cae_ret_data = r_ret_data;
assign cae_exception[1:0] = {r_err_aegidx, r_err_unimpl};
// ISE can have issues with global wires attached to D(flop)/I(lut) inputs
wire r_reset;
FDSE rst (.C(clk_per),.S(reset_per),.CE(r_reset),.D(!r_reset),.Q(r_reset));
//logic for using cae IMPORTANT. cae_idle should be 0 when executing a custom instruction and 1 otherwise.
//cae_stall should be 1 when when exectuting a custom instruction and 0 otherwise.
// assign cae_idle = 1'b1;
// assign cae_stall = 1'b0;
wire c_caep00;
reg r_caep00;
assign c_caep00 = (inst_caep == 5'd0) && inst_val;
always @(posedge clk) begin
r_caep00 <= c_caep00;
end
assign cae_idle = !r_caep00 && !cygraph_busy;
assign cae_stall = c_caep00 || r_caep00 || cygraph_busy;
// start triggering CyGraph
reg cy_en;
always @(posedge clk) begin
if(inst_caep == 5'd0 && inst_val) begin
// start logic for custom instruction
$display("@simulation: Hello World from simulated ae%d", i_aeid);
cy_en <= 1'b1;
$display("@simulation: Grayscale module enabled!");
end
else begin
cy_en <= 1'b0;
end
end
assign cygraph_enable = cy_en;
//
// default state
//
assign cae_ring_ctl_out = cae_ring_ctl_in;
assign cae_ring_data_out = cae_ring_data_in;
assign nxtae_rx_stall = 1'b0;
assign prvae_rx_stall = 1'b0;
// assign nxtae_tx_data = 32'b0;
// assign prvae_tx_data = 32'b0;
// assign nxtae_tx_vld = 1'b0;
// assign prvae_tx_vld = 1'b0;
assign prvae_nd0_tx_data = 66'b0;
assign prvae_nd0_tx_vld = 1'b0;
assign nxtae_nd0_rx_stall = 1'b0;
assign prvae_nd1_tx_data = 66'b0;
assign prvae_nd1_tx_vld = 1'b0;
assign nxtae_nd1_rx_stall = 1'b0;
// assign mc0_req_ld_e = 1'b0;
// assign mc0_req_st_e = 1'b0;
// assign mc0_req_wrd_rdctl_e = 64'd0;
// assign mc0_req_vadr_e = 48'd0;
// assign mc0_req_size_e = 2'd0;
// assign mc0_req_flush_e = 1'b0;
// assign mc0_rsp_stall_e = 1'b0;
// assign mc0_req_ld_o = 1'b0;
// assign mc0_req_st_o = 1'b0;
// assign mc0_req_wrd_rdctl_o = 64'd0;
// assign mc0_req_vadr_o = 48'd0;
// assign mc0_req_size_o = 2'd0;
// assign mc0_req_flush_o = 1'b0;
// assign mc0_rsp_stall_o = 1'b0;
// assign mc1_req_ld_e = 1'b0;
// assign mc1_req_st_e = 1'b0;
// assign mc1_req_wrd_rdctl_e = 64'd0;
// assign mc1_req_vadr_e = 48'd0;
// assign mc1_req_size_e = 2'd0;
// assign mc1_req_flush_e = 1'b0;
// assign mc1_rsp_stall_e = 1'b0;
// assign mc1_req_ld_o = 1'b0;
// assign mc1_req_st_o = 1'b0;
// assign mc1_req_wrd_rdctl_o = 64'd0;
// assign mc1_req_vadr_o = 48'd0;
// assign mc1_req_size_o = 2'd0;
// assign mc1_req_flush_o = 1'b0;
// assign mc1_rsp_stall_o = 1'b0;
// assign mc2_req_ld_e = 1'b0;
// assign mc2_req_st_e = 1'b0;
// assign mc2_req_wrd_rdctl_e = 64'd0;
// assign mc2_req_vadr_e = 48'd0;
// assign mc2_req_size_e = 2'd0;
// assign mc2_req_flush_e = 1'b0;
// assign mc2_rsp_stall_e = 1'b0;
// assign mc2_req_ld_o = 1'b0;
// assign mc2_req_st_o = 1'b0;
// assign mc2_req_wrd_rdctl_o = 64'd0;
// assign mc2_req_vadr_o = 48'd0;
// assign mc2_req_size_o = 2'd0;
// assign mc2_req_flush_o = 1'b0;
// assign mc2_rsp_stall_o = 1'b0;
// assign mc3_req_ld_e = 1'b0;
// assign mc3_req_st_e = 1'b0;
// assign mc3_req_wrd_rdctl_e = 64'd0;
// assign mc3_req_vadr_e = 48'd0;
// assign mc3_req_size_e = 2'd0;
// assign mc3_req_flush_e = 1'b0;
// assign mc3_rsp_stall_e = 1'b0;
// assign mc3_req_ld_o = 1'b0;
// assign mc3_req_st_o = 1'b0;
// assign mc3_req_wrd_rdctl_o = 64'd0;
// assign mc3_req_vadr_o = 48'd0;
// assign mc3_req_size_o = 2'd0;
// assign mc3_req_flush_o = 1'b0;
// assign mc3_rsp_stall_o = 1'b0;
// assign mc4_req_ld_e = 1'b0;
// assign mc4_req_st_e = 1'b0;
// assign mc4_req_wrd_rdctl_e = 64'd0;
// assign mc4_req_vadr_e = 48'd0;
// assign mc4_req_size_e = 2'd0;
// assign mc4_req_flush_e = 1'b0;
// assign mc4_rsp_stall_e = 1'b0;
// assign mc4_req_ld_o = 1'b0;
// assign mc4_req_st_o = 1'b0;
// assign mc4_req_wrd_rdctl_o = 64'd0;
// assign mc4_req_vadr_o = 48'd0;
// assign mc4_req_size_o = 2'd0;
// assign mc4_req_flush_o = 1'b0;
// assign mc4_rsp_stall_o = 1'b0;
// assign mc5_req_ld_e = 1'b0;
// assign mc5_req_st_e = 1'b0;
// assign mc5_req_wrd_rdctl_e = 64'd0;
// assign mc5_req_vadr_e = 48'd0;
// assign mc5_req_size_e = 2'd0;
// assign mc5_req_flush_e = 1'b0;
// assign mc5_rsp_stall_e = 1'b0;
// assign mc5_req_ld_o = 1'b0;
// assign mc5_req_st_o = 1'b0;
// assign mc5_req_wrd_rdctl_o = 64'd0;
// assign mc5_req_vadr_o = 48'd0;
// assign mc5_req_size_o = 2'd0;
// assign mc5_req_flush_o = 1'b0;
// assign mc5_rsp_stall_o = 1'b0;
// assign mc6_req_ld_e = 1'b0;
// assign mc6_req_st_e = 1'b0;
// assign mc6_req_wrd_rdctl_e = 64'd0;
// assign mc6_req_vadr_e = 48'd0;
// assign mc6_req_size_e = 2'd0;
// assign mc6_req_flush_e = 1'b0;
// assign mc6_rsp_stall_e = 1'b0;
// assign mc6_req_ld_o = 1'b0;
// assign mc6_req_st_o = 1'b0;
// assign mc6_req_wrd_rdctl_o = 64'd0;
// assign mc6_req_vadr_o = 48'd0;
// assign mc6_req_size_o = 2'd0;
// assign mc6_req_flush_o = 1'b0;
// assign mc6_rsp_stall_o = 1'b0;
// assign mc7_req_ld_e = 1'b0;
// assign mc7_req_st_e = 1'b0;
// assign mc7_req_wrd_rdctl_e = 64'd0;
// assign mc7_req_vadr_e = 48'd0;
// assign mc7_req_size_e = 2'd0;
// assign mc7_req_flush_e = 1'b0;
// assign mc7_rsp_stall_e = 1'b0;
// assign mc7_req_ld_o = 1'b0;
// assign mc7_req_st_o = 1'b0;
// assign mc7_req_wrd_rdctl_o = 64'd0;
// assign mc7_req_vadr_o = 48'd0;
// assign mc7_req_size_o = 2'd0;
// assign mc7_req_flush_o = 1'b0;
// assign mc7_rsp_stall_o = 1'b0;
wire [63:0] cy_n;
wire [63:0] non_zeros;
wire [63:0] graphData;
wire [63:0] graphInfo;
wire [63:0] queue1_address;
wire [63:0] queue2_address;
wire [63:0] current_level;
wire [63:0] cq_count;
assign cy_n = w_aeg[0];
assign non_zeros = w_aeg[1];
assign graphData = w_aeg[2];
assign graphInfo = w_aeg[3];
assign queue1_address = w_aeg[4];
assign queue2_address = w_aeg[5];
assign current_level = w_aeg[6];
assign cq_count = w_aeg[7];
// Instaintaite CyGraph module
cygraph cygraph_inst (
// control signals
.clk (clk_per), // in
.rst (reset_per), // in
.enable (cygraph_enable), // in
.busy (cygraph_busy), // out
.done (cygraph_done), // out
// ae-to-ae signals
.ae_id (i_aeid), // in
.nxtae_rx_data (nxtae_rx_data), // in 32
.nxtae_rx_vld (nxtae_rx_vld), // in
.prvae_rx_data (prvae_rx_data), // in 32
.prvae_rx_vld (prvae_rx_vld), // in
.nxtae_tx_data (nxtae_tx_data), // out 32
.nxtae_tx_vld (nxtae_tx_vld), // out
.prvae_tx_data (prvae_tx_data), // out 32
.prvae_tx_vld (prvae_tx_vld), // out
// Graph Parameters
.n_in (cy_n), // in 64
.non_zeros_in (non_zeros), // in 64
.current_level_in (current_level), // in 64
.cq_count_in (cq_count), // in 64
.nq_count_out (nq_count), // out 64
// Input Graph Pointers (Represented in Custom CSR)
.graphData_in (graphData), // in 64
.graphInfo_in (graphInfo), // in 64
// Queue pointers
.queue1_address_in (queue1_address), // in 64
.queue2_address_in (queue2_address), // in 64
// MC0 port signals
.mc0_req_ld (mc0_req_ld_e), // out
.mc0_req_st (mc0_req_st_e), // out
.mc0_req_size (mc0_req_size_e), // out2
.mc0_req_vaddr (mc0_req_vadr_e), // out48
.mc0_req_wrd_rdctl (mc0_req_wrd_rdctl_e), // out64
.mc0_req_flush (mc0_req_flush_e), // out
.mc0_rd_rq_stall (mc0_rd_rq_stall_e), // in
.mc0_wr_rq_stall (mc0_wr_rq_stall_e), // in
.mc0_rsp_push (mc0_rsp_push_e), // in
.mc0_rsp_stall (mc0_rsp_stall_e), // out
.mc0_rsp_data (mc0_rsp_data_e), // in 64
.mc0_rsp_rdctl (mc0_rsp_rdctl_e), // in 32
.mc0_rsp_flush_cmplt (mc0_rsp_flush_cmplt_e), // in
// MC1 port signals
.mc1_req_ld (mc0_req_ld_o), // out
.mc1_req_st (mc0_req_st_o), // out
.mc1_req_size (mc0_req_size_o), // out2
.mc1_req_vaddr (mc0_req_vadr_o), // out48
.mc1_req_wrd_rdctl (mc0_req_wrd_rdctl_o), // out64
.mc1_req_flush (mc0_req_flush_o), // out
.mc1_rd_rq_stall (mc0_rd_rq_stall_o), // in
.mc1_wr_rq_stall (mc0_wr_rq_stall_o), // in
.mc1_rsp_push (mc0_rsp_push_o), // in
.mc1_rsp_stall (mc0_rsp_stall_o), // out
.mc1_rsp_data (mc0_rsp_data_o), // in 64
.mc1_rsp_rdctl (mc0_rsp_rdctl_o), // in 32
.mc1_rsp_flush_cmplt (mc0_rsp_flush_cmplt_o), // in
// MC2 port signals
.mc2_req_ld (mc1_req_ld_e), // out
.mc2_req_st (mc1_req_st_e), // out
.mc2_req_size (mc1_req_size_e), // out2
.mc2_req_vaddr (mc1_req_vadr_e), // out48
.mc2_req_wrd_rdctl (mc1_req_wrd_rdctl_e), // out64
.mc2_req_flush (mc1_req_flush_e), // out
.mc2_rd_rq_stall (mc1_rd_rq_stall_e), // in
.mc2_wr_rq_stall (mc1_wr_rq_stall_e), // in
.mc2_rsp_push (mc1_rsp_push_e), // in
.mc2_rsp_stall (mc1_rsp_stall_e), // out
.mc2_rsp_data (mc1_rsp_data_e), // in 64
.mc2_rsp_rdctl (mc1_rsp_rdctl_e), // in 32
.mc2_rsp_flush_cmplt (mc1_rsp_flush_cmplt_e), // in
// MC3 port signals
.mc3_req_ld (mc1_req_ld_o), // out
.mc3_req_st (mc1_req_st_o), // out
.mc3_req_size (mc1_req_size_o), // out2
.mc3_req_vaddr (mc1_req_vadr_o), // out48
.mc3_req_wrd_rdctl (mc1_req_wrd_rdctl_o), // out64
.mc3_req_flush (mc1_req_flush_o), // out
.mc3_rd_rq_stall (mc1_rd_rq_stall_o), // in
.mc3_wr_rq_stall (mc1_wr_rq_stall_o), // in
.mc3_rsp_push (mc1_rsp_push_o), // in
.mc3_rsp_stall (mc1_rsp_stall_o), // out
.mc3_rsp_data (mc1_rsp_data_o), // in 64
.mc3_rsp_rdctl (mc1_rsp_rdctl_o), // in 32
.mc3_rsp_flush_cmplt (mc1_rsp_flush_cmplt_o), // in
// MC4 port signals
.mc4_req_ld (mc2_req_ld_e), // out
.mc4_req_st (mc2_req_st_e), // out
.mc4_req_size (mc2_req_size_e), // out2
.mc4_req_vaddr (mc2_req_vadr_e), // out48
.mc4_req_wrd_rdctl (mc2_req_wrd_rdctl_e), // out64
.mc4_req_flush (mc2_req_flush_e), // out
.mc4_rd_rq_stall (mc2_rd_rq_stall_e), // in
.mc4_wr_rq_stall (mc2_wr_rq_stall_e), // in
.mc4_rsp_push (mc2_rsp_push_e), // in
.mc4_rsp_stall (mc2_rsp_stall_e), // out
.mc4_rsp_data (mc2_rsp_data_e), // in 64
.mc4_rsp_rdctl (mc2_rsp_rdctl_e), // in 32
.mc4_rsp_flush_cmplt (mc2_rsp_flush_cmplt_e), // in
// MC5 port signals
.mc5_req_ld (mc2_req_ld_o), // out
.mc5_req_st (mc2_req_st_o), // out
.mc5_req_size (mc2_req_size_o), // out2
.mc5_req_vaddr (mc2_req_vadr_o), // out48
.mc5_req_wrd_rdctl (mc2_req_wrd_rdctl_o), // out64
.mc5_req_flush (mc2_req_flush_o), // out
.mc5_rd_rq_stall (mc2_rd_rq_stall_o), // in
.mc5_wr_rq_stall (mc2_wr_rq_stall_o), // in
.mc5_rsp_push (mc2_rsp_push_o), // in
.mc5_rsp_stall (mc2_rsp_stall_o), // out
.mc5_rsp_data (mc2_rsp_data_o), // in 64
.mc5_rsp_rdctl (mc2_rsp_rdctl_o), // in 32
.mc5_rsp_flush_cmplt (mc2_rsp_flush_cmplt_o), // in
// MC6 port signals
.mc6_req_ld (mc3_req_ld_e), // out
.mc6_req_st (mc3_req_st_e), // out
.mc6_req_size (mc3_req_size_e), // out2
.mc6_req_vaddr (mc3_req_vadr_e), // out48
.mc6_req_wrd_rdctl (mc3_req_wrd_rdctl_e), // out64
.mc6_req_flush (mc3_req_flush_e), // out
.mc6_rd_rq_stall (mc3_rd_rq_stall_e), // in
.mc6_wr_rq_stall (mc3_wr_rq_stall_e), // in
.mc6_rsp_push (mc3_rsp_push_e), // in
.mc6_rsp_stall (mc3_rsp_stall_e), // out
.mc6_rsp_data (mc3_rsp_data_e), // in 64
.mc6_rsp_rdctl (mc3_rsp_rdctl_e), // in 32
.mc6_rsp_flush_cmplt (mc3_rsp_flush_cmplt_e), // in
// MC7 port signals
.mc7_req_ld (mc3_req_ld_o), // out
.mc7_req_st (mc3_req_st_o), // out
.mc7_req_size (mc3_req_size_o), // out2
.mc7_req_vaddr (mc3_req_vadr_o), // out48
.mc7_req_wrd_rdctl (mc3_req_wrd_rdctl_o), // out64
.mc7_req_flush (mc3_req_flush_o), // out
.mc7_rd_rq_stall (mc3_rd_rq_stall_o), // in
.mc7_wr_rq_stall (mc3_wr_rq_stall_o), // in
.mc7_rsp_push (mc3_rsp_push_o), // in
.mc7_rsp_stall (mc3_rsp_stall_o), // out
.mc7_rsp_data (mc3_rsp_data_o), // in 64
.mc7_rsp_rdctl (mc3_rsp_rdctl_o), // in 32
.mc7_rsp_flush_cmplt (mc3_rsp_flush_cmplt_o), // in
// MC8 port signals
.mc8_req_ld (mc4_req_ld_e), // out
.mc8_req_st (mc4_req_st_e), // out
.mc8_req_size (mc4_req_size_e), // out2
.mc8_req_vaddr (mc4_req_vadr_e), // out48
.mc8_req_wrd_rdctl (mc4_req_wrd_rdctl_e), // out64
.mc8_req_flush (mc4_req_flush_e), // out
.mc8_rd_rq_stall (mc4_rd_rq_stall_e), // in
.mc8_wr_rq_stall (mc4_wr_rq_stall_e), // in
.mc8_rsp_push (mc4_rsp_push_e), // in
.mc8_rsp_stall (mc4_rsp_stall_e), // out
.mc8_rsp_data (mc4_rsp_data_e), // in 64
.mc8_rsp_rdctl (mc4_rsp_rdctl_e), // in 32
.mc8_rsp_flush_cmplt (mc4_rsp_flush_cmplt_e), // in
// MC9 port signals
.mc9_req_ld (mc4_req_ld_o), // out
.mc9_req_st (mc4_req_st_o), // out
.mc9_req_size (mc4_req_size_o), // out2
.mc9_req_vaddr (mc4_req_vadr_o), // out48
.mc9_req_wrd_rdctl (mc4_req_wrd_rdctl_o), // out64
.mc9_req_flush (mc4_req_flush_o), // out
.mc9_rd_rq_stall (mc4_rd_rq_stall_o), // in
.mc9_wr_rq_stall (mc4_wr_rq_stall_o), // in
.mc9_rsp_push (mc4_rsp_push_o), // in
.mc9_rsp_stall (mc4_rsp_stall_o), // out
.mc9_rsp_data (mc4_rsp_data_o), // in 64
.mc9_rsp_rdctl (mc4_rsp_rdctl_o), // in 32
.mc9_rsp_flush_cmplt (mc4_rsp_flush_cmplt_o), // in
// MC10 port signals
.mc10_req_ld (mc5_req_ld_e), // out
.mc10_req_st (mc5_req_st_e), // out
.mc10_req_size (mc5_req_size_e), // out2
.mc10_req_vaddr (mc5_req_vadr_e), // out48
.mc10_req_wrd_rdctl (mc5_req_wrd_rdctl_e), // out64
.mc10_req_flush (mc5_req_flush_e), // out
.mc10_rd_rq_stall (mc5_rd_rq_stall_e), // in
.mc10_wr_rq_stall (mc5_wr_rq_stall_e), // in
.mc10_rsp_push (mc5_rsp_push_e), // in
.mc10_rsp_stall (mc5_rsp_stall_e), // out
.mc10_rsp_data (mc5_rsp_data_e), // in 64
.mc10_rsp_rdctl (mc5_rsp_rdctl_e), // in 32
.mc10_rsp_flush_cmplt (mc5_rsp_flush_cmplt_e), // in
// MC11 port signals
.mc11_req_ld (mc5_req_ld_o), // out
.mc11_req_st (mc5_req_st_o), // out
.mc11_req_size (mc5_req_size_o), // out2
.mc11_req_vaddr (mc5_req_vadr_o), // out48
.mc11_req_wrd_rdctl (mc5_req_wrd_rdctl_o), // out64
.mc11_req_flush (mc5_req_flush_o), // out
.mc11_rd_rq_stall (mc5_rd_rq_stall_o), // in
.mc11_wr_rq_stall (mc5_wr_rq_stall_o), // in
.mc11_rsp_push (mc5_rsp_push_o), // in
.mc11_rsp_stall (mc5_rsp_stall_o), // out
.mc11_rsp_data (mc5_rsp_data_o), // in 64
.mc11_rsp_rdctl (mc5_rsp_rdctl_o), // in 32
.mc11_rsp_flush_cmplt (mc5_rsp_flush_cmplt_o), // in
// MC12 port signals
.mc12_req_ld (mc6_req_ld_e), // out
.mc12_req_st (mc6_req_st_e), // out
.mc12_req_size (mc6_req_size_e), // out2
.mc12_req_vaddr (mc6_req_vadr_e), // out48
.mc12_req_wrd_rdctl (mc6_req_wrd_rdctl_e), // out64
.mc12_req_flush (mc6_req_flush_e), // out
.mc12_rd_rq_stall (mc6_rd_rq_stall_e), // in
.mc12_wr_rq_stall (mc6_wr_rq_stall_e), // in
.mc12_rsp_push (mc6_rsp_push_e), // in
.mc12_rsp_stall (mc6_rsp_stall_e), // out
.mc12_rsp_data (mc6_rsp_data_e), // in 64
.mc12_rsp_rdctl (mc6_rsp_rdctl_e), // in 32
.mc12_rsp_flush_cmplt (mc6_rsp_flush_cmplt_e), // in
// MC13 port signals
.mc13_req_ld (mc6_req_ld_o), // out
.mc13_req_st (mc6_req_st_o), // out
.mc13_req_size (mc6_req_size_o), // out2
.mc13_req_vaddr (mc6_req_vadr_o), // out48
.mc13_req_wrd_rdctl (mc6_req_wrd_rdctl_o), // out64
.mc13_req_flush (mc6_req_flush_o), // out
.mc13_rd_rq_stall (mc6_rd_rq_stall_o), // in
.mc13_wr_rq_stall (mc6_wr_rq_stall_o), // in
.mc13_rsp_push (mc6_rsp_push_o), // in
.mc13_rsp_stall (mc6_rsp_stall_o), // out
.mc13_rsp_data (mc6_rsp_data_o), // in 64
.mc13_rsp_rdctl (mc6_rsp_rdctl_o), // in 32
.mc13_rsp_flush_cmplt (mc6_rsp_flush_cmplt_o), // in
// MC14 port signals
.mc14_req_ld (mc7_req_ld_e), // out
.mc14_req_st (mc7_req_st_e), // out
.mc14_req_size (mc7_req_size_e), // out2
.mc14_req_vaddr (mc7_req_vadr_e), // out48
.mc14_req_wrd_rdctl (mc7_req_wrd_rdctl_e), // out64
.mc14_req_flush (mc7_req_flush_e), // out
.mc14_rd_rq_stall (mc7_rd_rq_stall_e), // in
.mc14_wr_rq_stall (mc7_wr_rq_stall_e), // in
.mc14_rsp_push (mc7_rsp_push_e), // in
.mc14_rsp_stall (mc7_rsp_stall_e), // out
.mc14_rsp_data (mc7_rsp_data_e), // in 64
.mc14_rsp_rdctl (mc7_rsp_rdctl_e), // in 32
.mc14_rsp_flush_cmplt (mc7_rsp_flush_cmplt_e), // in
// MC15 port signals
.mc15_req_ld (mc7_req_ld_o), // out
.mc15_req_st (mc7_req_st_o), // out
.mc15_req_size (mc7_req_size_o), // out2
.mc15_req_vaddr (mc7_req_vadr_o), // out48
.mc15_req_wrd_rdctl (mc7_req_wrd_rdctl_o), // out64
.mc15_req_flush (mc7_req_flush_o), // out
.mc15_rd_rq_stall (mc7_rd_rq_stall_o), // in
.mc15_wr_rq_stall (mc7_wr_rq_stall_o), // in
.mc15_rsp_push (mc7_rsp_push_o), // in
.mc15_rsp_stall (mc7_rsp_stall_o), // out
.mc15_rsp_data (mc7_rsp_data_o), // in 64
.mc15_rsp_rdctl (mc7_rsp_rdctl_o), // in 32
.mc15_rsp_flush_cmplt (mc7_rsp_flush_cmplt_o) // in
);
/* ---------- debug & synopsys off blocks ---------- */
// synopsys translate_off
// Parameters: 1-Severity: Don't Stop, 2-start check only after negedge of reset
//assert_never #(1, 2, "***ERROR ASSERT: unimplemented instruction cracked") a0 (.clk(clk), .reset_n(~reset), .test_expr(r_unimplemented_inst));
// synopsys translate_on
endmodule // cae_pers
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zynq_1_xbar_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST" *)
input wire [0 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST" *)
output wire [0 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI AWID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI AWID [11:0] [35:24]" *)
output wire [35 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]" *)
output wire [95 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI AWLEN [7:0] [23:16]" *)
output wire [23 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE [2:0] [8:6]" *)
output wire [8 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI AWBURST [1:0] [5:4]" *)
output wire [5 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK [0:0] [2:2]" *)
output wire [2 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE [3:0] [11:8]" *)
output wire [11 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]" *)
output wire [8 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWREGION [3:0] [11:8]" *)
output wire [11 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWQOS [3:0] [11:8]" *)
output wire [11 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]" *)
output wire [95 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]" *)
output wire [11 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WLAST [0:0] [2:2]" *)
output wire [2 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI BID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI BID [11:0] [35:24]" *)
input wire [35 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]" *)
input wire [5 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]" *)
input wire [2 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]" *)
output wire [2 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI ARID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI ARID [11:0] [35:24]" *)
output wire [35 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]" *)
output wire [95 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI ARLEN [7:0] [23:16]" *)
output wire [23 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE [2:0] [8:6]" *)
output wire [8 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI ARBURST [1:0] [5:4]" *)
output wire [5 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK [0:0] [2:2]" *)
output wire [2 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE [3:0] [11:8]" *)
output wire [11 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]" *)
output wire [8 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARREGION [3:0] [11:8]" *)
output wire [11 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARQOS [3:0] [11:8]" *)
output wire [11 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI RID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI RID [11:0] [35:24]" *)
input wire [35 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]" *)
input wire [95 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]" *)
input wire [5 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RLAST [0:0] [2:2]" *)
input wire [2 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]" *)
input wire [2 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]" *)
output wire [2 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(3),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(192'H00000000400000000000000041e000000000000041200000),
.C_M_AXI_ADDR_WIDTH(96'H0000000c0000000c00000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H0000000c),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(96'H000000010000000100000001),
.C_M_AXI_READ_CONNECTIVITY(96'H000000010000000100000001),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(32'H00000000),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000008),
.C_S_AXI_READ_ACCEPTANCE(32'H00000008),
.C_M_AXI_WRITE_ISSUING(96'H000000020000000200000002),
.C_M_AXI_READ_ISSUING(96'H000000020000000200000002),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(96'H000000000000000000000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(12'H000),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(3'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(3'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
module i2c_master(
clk, // input
reset_n, // input asynchronous
reset, // input synchronous
sda, // inout
scl, // inout
tx_byte, // input, byte to send to slave, the payload
rx_byte, // output, byte received from slave, the payload
tx_start_condition, // input, high, when i2c master is to send a start signal
tx_stop_condition, // input, high, when i2c master is to send a stop signal
tx_data, // input, high, when i2c master is to send a byte as given in tx_byte
rx_data, // input, high, when i2c master is to receive a byte and output it in rx_byte
start, // input, starts i2c master
done, // output, high when i2c master done
i2c_master_state // output, read by rf
);
`include "parameters_global.v"
input clk;
input reset_n;
input reset;
inout sda, scl;
input [`byte_width-1:0] tx_byte;
output reg [`byte_width-1:0] rx_byte;
input tx_start_condition;
input tx_stop_condition;
input tx_data;
input rx_data;
input start;
output reg done;
output reg [`byte_width-1:0] i2c_master_state;
reg [`byte_width-1:0] i2c_master_state_last, i2c_wait_count;
`define bit_pointer_width 4 // must count up to 9 bits during tx or rx
reg [`bit_pointer_width-1:0] bit_pointer;
parameter bit_pointer_init = `bit_pointer_width'h7;
`define sda_sample_width 3
reg [`sda_sample_width-1:0] sda_sample; // holds 3 samples of sda / before rising scl, after rising scl, after setting scl
parameter all_sda_samples_zero = `sda_sample_width'b000;
parameter i2c_driver_off = 1'b1;
parameter i2c_driver_on = 1'b0;
reg driver_scl;
reg driver_sda;
assign scl = driver_scl ? 1'bz : 1'b0;
assign sda = driver_sda ? 1'bz : 1'b0;
always @(posedge clk or negedge reset_n) begin
if (~reset_n)
begin
done <= #`DEL 1'b0;
i2c_master_state <= #`DEL I2C_MASTER_STATE_IDLE;
i2c_wait_count <= #`DEL i2c_wait_count_init;
driver_scl <= #`DEL i2c_driver_off;
driver_sda <= #`DEL i2c_driver_off;
bit_pointer <= #`DEL bit_pointer_init;
sda_sample <= #`DEL `sda_sample_width'b000;
end
else
begin
if (reset)
begin
done <= #`DEL 1'b0;
i2c_master_state <= #`DEL I2C_MASTER_STATE_IDLE;
i2c_wait_count <= #`DEL i2c_wait_count_init;
driver_scl <= #`DEL i2c_driver_off;
driver_sda <= #`DEL i2c_driver_off;
bit_pointer <= #`DEL bit_pointer_init;
sda_sample <= #`DEL `sda_sample_width'b000;
end
else
begin
case (i2c_master_state) // synthesis parallel_case
// RESET / IDLE
I2C_MASTER_STATE_IDLE:
begin
//i2c_wait_count <= #`DEL i2c_wait_count_init;
done <= #`DEL 1'b0;
if (start)
begin
if (tx_stop_condition)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_STOP_1; // 2h
end
else if (tx_start_condition)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_START_1; // 4h
end
else if (tx_data)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_1; // 6h
end
// else if (rx_data)
// begin
// i2c_master_state <= #`DEL I2C_MASTER_STATE_RX_1;
// end
end
end
// WAIT STATES
I2C_MASTER_STATE_WAIT: // 1h
begin
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL i2c_master_state_last;
end
else
begin
i2c_wait_count <= #`DEL i2c_wait_count - 1;
end
end
// NOTE: FOR THE FOLLOWING STATES THIS RULE APPLIES: ACT,WAIT -> NEXT STATE -> ACT,WAIT -> NEXT STATE ...
// SEND STOP CONDITION
I2C_MASTER_STATE_STOP_1: // 2h
begin
driver_scl <= #`DEL i2c_driver_off;
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_STOP_2; // 03h
i2c_wait_count <= #`DEL i2c_wait_count_init;
end
else
begin
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
end
end
I2C_MASTER_STATE_STOP_2: // 03h
begin
driver_sda <= #`DEL i2c_driver_off;
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_IDLE;
i2c_wait_count <= #`DEL i2c_wait_count_init;
done <= #`DEL 1'b1;
end
else
begin
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT;
end
end
// SEND START CONDITION
I2C_MASTER_STATE_START_1: // 4h
begin
driver_sda <= #`DEL i2c_driver_on;
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_START_2; // 5h
i2c_wait_count <= #`DEL i2c_wait_count_init;
end
else
begin
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
end
end
I2C_MASTER_STATE_START_2: // 5h
begin
driver_scl <= #`DEL i2c_driver_on;
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_IDLE; // 00h
i2c_wait_count <= #`DEL i2c_wait_count_init;
done <= #`DEL 1'b1;
end
else
begin
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
end
end
// DATA TX
I2C_MASTER_STATE_TX_1: // 6h
begin
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_2;
i2c_wait_count <= #`DEL i2c_wait_count_init;
end
else
begin
driver_sda <= #`DEL tx_byte[bit_pointer];
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
end
end
I2C_MASTER_STATE_TX_2:
begin
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_3;
i2c_wait_count <= #`DEL i2c_wait_count_init;
end
else
begin
driver_scl <= #`DEL i2c_driver_off;
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
end
end
I2C_MASTER_STATE_TX_3:
begin
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_4;
i2c_wait_count <= #`DEL i2c_wait_count_init;
end
else
begin
driver_scl <= #`DEL i2c_driver_on;
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
end
end
I2C_MASTER_STATE_TX_4: // 09h
begin
if (bit_pointer == 0) // if last bit processed (LSB)
begin
driver_sda <= #`DEL i2c_driver_off; // release sda
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_5;
end
else
begin // if not last bit processed, advance bit pointer one bit towards LSB (right)
bit_pointer <= #`DEL bit_pointer - 1;
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_1; // start sending next bit
end
end
I2C_MASTER_STATE_TX_5: // 0Ah // wait until sda is stable , slave should be sending acknowledge (zero) already
begin
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_6;
i2c_wait_count <= #`DEL i2c_wait_count_init;
sda_sample[0] <= #`DEL sda; // take sample #1 from sda
end
else
begin
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
end
end
I2C_MASTER_STATE_TX_6: // 0Bh // register acknowledge from slave // acknowledge clock cycle begin
// sample sda while scl posedge
begin
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_7;
i2c_wait_count <= #`DEL i2c_wait_count_init;
end
else
begin
driver_scl <= #`DEL i2c_driver_off; // scl L-H edge
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
sda_sample[1] <= #`DEL sda; // take sample #2 from sda
end
end
I2C_MASTER_STATE_TX_7: // 0Ch // register acknowledge from slave // acknowledge clock cycle end
// sample sda while scl negedge
begin
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_8;
i2c_wait_count <= #`DEL i2c_wait_count_init;
end
else
begin
driver_scl <= #`DEL i2c_driver_on; // scl H-L edge
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
sda_sample[2] <= #`DEL sda; // take sample #2 from sda
end
end
I2C_MASTER_STATE_TX_8: // 0Dh // evaluate acknowledge bit received from slave
begin
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_9; // 0Eh
i2c_wait_count <= #`DEL i2c_wait_count_init;
bit_pointer <= #`DEL bit_pointer_init;
//done <= #`DEL 1'b1;
end
else
begin // all sda samples must be zero, otherwise no acknowledge received -> error
if (sda_sample == all_sda_samples_zero)
begin
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
end
else
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_ERROR;
end
end
end
I2C_MASTER_STATE_TX_9: // 0Eh // finish write cycle by driving sda low
begin
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_IDLE;
i2c_wait_count <= #`DEL i2c_wait_count_init;
//bit_pointer <= #`DEL bit_pointer_init;
done <= #`DEL 1'b1;
end
else
begin // drive sda low
driver_sda <= #`DEL i2c_driver_on; // sda L
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
end
end
endcase
end
end
end
endmodule
|
//altera_mult_add ADDNSUB_MULTIPLIER_PIPELINE_ACLR1="ACLR0" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="UNREGISTERED" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DEVICE_FAMILY="Cyclone IV E" DSP_BLOCK_BALANCING="Auto" INPUT_REGISTER_A0="UNREGISTERED" INPUT_REGISTER_B0="UNREGISTERED" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_B0="DATAB" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_ACLR0="ACLR0" MULTIPLIER_REGISTER0="CLOCK0" NUMBER_OF_MULTIPLIERS=1 OUTPUT_REGISTER="UNREGISTERED" port_addnsub1="PORT_UNUSED" port_addnsub3="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" REPRESENTATION_A="UNSIGNED" REPRESENTATION_B="UNSIGNED" SELECTED_DEVICE_FAMILY="CYCLONEIVE" SIGNED_PIPELINE_ACLR_A="ACLR0" SIGNED_PIPELINE_ACLR_B="ACLR0" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="UNREGISTERED" SIGNED_REGISTER_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_RESULT=32 aclr0 clock0 dataa datab result
//VERSION_BEGIN 14.0 cbx_altera_mult_add 2014:06:17:18:06:03:SJ cbx_altera_mult_add_rtl 2014:06:17:18:06:03:SJ cbx_mgl 2014:06:17:18:10:38:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = altera_mult_add_rtl 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module altera_mult_add_q1u2
(
aclr0,
clock0,
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input aclr0;
input clock0;
input [15:0] dataa;
input [15:0] datab;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr0;
tri1 clock0;
tri0 [15:0] dataa;
tri0 [15:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] wire_altera_mult_add_rtl1_result;
altera_mult_add_rtl altera_mult_add_rtl1
(
.aclr0(aclr0),
.chainout_sat_overflow(),
.clock0(clock0),
.dataa(dataa),
.datab(datab),
.mult0_is_saturated(),
.mult1_is_saturated(),
.mult2_is_saturated(),
.mult3_is_saturated(),
.overflow(),
.result(wire_altera_mult_add_rtl1_result),
.scanouta(),
.scanoutb(),
.accum_sload(1'b0),
.aclr1(1'b0),
.aclr2(1'b0),
.aclr3(1'b0),
.addnsub1(1'b1),
.addnsub1_round(1'b0),
.addnsub3(1'b1),
.addnsub3_round(1'b0),
.chainin({1{1'b0}}),
.chainout_round(1'b0),
.chainout_saturate(1'b0),
.clock1(1'b1),
.clock2(1'b1),
.clock3(1'b1),
.coefsel0({3{1'b0}}),
.coefsel1({3{1'b0}}),
.coefsel2({3{1'b0}}),
.coefsel3({3{1'b0}}),
.datac({22{1'b0}}),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.mult01_round(1'b0),
.mult01_saturation(1'b0),
.mult23_round(1'b0),
.mult23_saturation(1'b0),
.negate(1'b0),
.output_round(1'b0),
.output_saturate(1'b0),
.rotate(1'b0),
.scanina({16{1'b0}}),
.scaninb({16{1'b0}}),
.shift_right(1'b0),
.signa(1'b0),
.signb(1'b0),
.sload_accum(1'b0),
.sourcea({1{1'b0}}),
.sourceb({1{1'b0}}),
.zero_chainout(1'b0),
.zero_loopback(1'b0)
);
defparam
altera_mult_add_rtl1.accum_direction = "ADD",
altera_mult_add_rtl1.accum_sload_aclr = "NONE",
altera_mult_add_rtl1.accum_sload_latency_aclr = "NONE",
altera_mult_add_rtl1.accum_sload_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.accum_sload_register = "UNREGISTERED",
altera_mult_add_rtl1.accumulator = "NO",
altera_mult_add_rtl1.adder1_rounding = "NO",
altera_mult_add_rtl1.adder3_rounding = "NO",
altera_mult_add_rtl1.addnsub1_round_aclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub1_round_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub3_round_aclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub3_round_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_aclr1 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_aclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_latency_aclr1 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_latency_aclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_latency_clock1 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_latency_clock3 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_register1 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_register3 = "UNREGISTERED",
altera_mult_add_rtl1.chainout_aclr = "NONE",
altera_mult_add_rtl1.chainout_adder = "NO",
altera_mult_add_rtl1.chainout_adder_direction = "ADD",
altera_mult_add_rtl1.chainout_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_output_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_output_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_rounding = "NO",
altera_mult_add_rtl1.chainout_saturate_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_output_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_output_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturation = "NO",
altera_mult_add_rtl1.coef0_0 = 0,
altera_mult_add_rtl1.coef0_1 = 0,
altera_mult_add_rtl1.coef0_2 = 0,
altera_mult_add_rtl1.coef0_3 = 0,
altera_mult_add_rtl1.coef0_4 = 0,
altera_mult_add_rtl1.coef0_5 = 0,
altera_mult_add_rtl1.coef0_6 = 0,
altera_mult_add_rtl1.coef0_7 = 0,
altera_mult_add_rtl1.coef1_0 = 0,
altera_mult_add_rtl1.coef1_1 = 0,
altera_mult_add_rtl1.coef1_2 = 0,
altera_mult_add_rtl1.coef1_3 = 0,
altera_mult_add_rtl1.coef1_4 = 0,
altera_mult_add_rtl1.coef1_5 = 0,
altera_mult_add_rtl1.coef1_6 = 0,
altera_mult_add_rtl1.coef1_7 = 0,
altera_mult_add_rtl1.coef2_0 = 0,
altera_mult_add_rtl1.coef2_1 = 0,
altera_mult_add_rtl1.coef2_2 = 0,
altera_mult_add_rtl1.coef2_3 = 0,
altera_mult_add_rtl1.coef2_4 = 0,
altera_mult_add_rtl1.coef2_5 = 0,
altera_mult_add_rtl1.coef2_6 = 0,
altera_mult_add_rtl1.coef2_7 = 0,
altera_mult_add_rtl1.coef3_0 = 0,
altera_mult_add_rtl1.coef3_1 = 0,
altera_mult_add_rtl1.coef3_2 = 0,
altera_mult_add_rtl1.coef3_3 = 0,
altera_mult_add_rtl1.coef3_4 = 0,
altera_mult_add_rtl1.coef3_5 = 0,
altera_mult_add_rtl1.coef3_6 = 0,
altera_mult_add_rtl1.coef3_7 = 0,
altera_mult_add_rtl1.coefsel0_aclr = "NONE",
altera_mult_add_rtl1.coefsel0_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel0_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel1_aclr = "NONE",
altera_mult_add_rtl1.coefsel1_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel1_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel2_aclr = "NONE",
altera_mult_add_rtl1.coefsel2_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel2_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel3_aclr = "NONE",
altera_mult_add_rtl1.coefsel3_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel3_register = "UNREGISTERED",
altera_mult_add_rtl1.dedicated_multiplier_circuitry = "YES",
altera_mult_add_rtl1.double_accum = "NO",
altera_mult_add_rtl1.dsp_block_balancing = "Auto",
altera_mult_add_rtl1.extra_latency = 0,
altera_mult_add_rtl1.input_a0_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_a1_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_a2_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_a3_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_aclr_a0 = "NONE",
altera_mult_add_rtl1.input_aclr_a1 = "NONE",
altera_mult_add_rtl1.input_aclr_a2 = "NONE",
altera_mult_add_rtl1.input_aclr_a3 = "NONE",
altera_mult_add_rtl1.input_aclr_b0 = "NONE",
altera_mult_add_rtl1.input_aclr_b1 = "NONE",
altera_mult_add_rtl1.input_aclr_b2 = "NONE",
altera_mult_add_rtl1.input_aclr_b3 = "NONE",
altera_mult_add_rtl1.input_aclr_c0 = "NONE",
altera_mult_add_rtl1.input_aclr_c1 = "NONE",
altera_mult_add_rtl1.input_aclr_c2 = "NONE",
altera_mult_add_rtl1.input_aclr_c3 = "NONE",
altera_mult_add_rtl1.input_b0_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_b1_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_b2_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_b3_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c0_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c1_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c2_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c3_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a3 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b3 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c3 = "UNREGISTERED",
altera_mult_add_rtl1.input_source_a0 = "DATAA",
altera_mult_add_rtl1.input_source_a1 = "DATAA",
altera_mult_add_rtl1.input_source_a2 = "DATAA",
altera_mult_add_rtl1.input_source_a3 = "DATAA",
altera_mult_add_rtl1.input_source_b0 = "DATAB",
altera_mult_add_rtl1.input_source_b1 = "DATAB",
altera_mult_add_rtl1.input_source_b2 = "DATAB",
altera_mult_add_rtl1.input_source_b3 = "DATAB",
altera_mult_add_rtl1.latency = 0,
altera_mult_add_rtl1.loadconst_control_aclr = "NONE",
altera_mult_add_rtl1.loadconst_control_register = "UNREGISTERED",
altera_mult_add_rtl1.loadconst_value = 64,
altera_mult_add_rtl1.mult01_round_aclr = "NONE",
altera_mult_add_rtl1.mult01_round_register = "UNREGISTERED",
altera_mult_add_rtl1.mult01_saturation_aclr = "ACLR0",
altera_mult_add_rtl1.mult01_saturation_register = "UNREGISTERED",
altera_mult_add_rtl1.mult23_round_aclr = "NONE",
altera_mult_add_rtl1.mult23_round_register = "UNREGISTERED",
altera_mult_add_rtl1.mult23_saturation_aclr = "NONE",
altera_mult_add_rtl1.mult23_saturation_register = "UNREGISTERED",
altera_mult_add_rtl1.multiplier01_rounding = "NO",
altera_mult_add_rtl1.multiplier01_saturation = "NO",
altera_mult_add_rtl1.multiplier1_direction = "ADD",
altera_mult_add_rtl1.multiplier23_rounding = "NO",
altera_mult_add_rtl1.multiplier23_saturation = "NO",
altera_mult_add_rtl1.multiplier3_direction = "ADD",
altera_mult_add_rtl1.multiplier_aclr0 = "ACLR0",
altera_mult_add_rtl1.multiplier_aclr1 = "NONE",
altera_mult_add_rtl1.multiplier_aclr2 = "NONE",
altera_mult_add_rtl1.multiplier_aclr3 = "NONE",
altera_mult_add_rtl1.multiplier_register0 = "CLOCK0",
altera_mult_add_rtl1.multiplier_register1 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_register2 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_register3 = "UNREGISTERED",
altera_mult_add_rtl1.negate_aclr = "NONE",
altera_mult_add_rtl1.negate_latency_aclr = "NONE",
altera_mult_add_rtl1.negate_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.negate_register = "UNREGISTERED",
altera_mult_add_rtl1.number_of_multipliers = 1,
altera_mult_add_rtl1.output_aclr = "NONE",
altera_mult_add_rtl1.output_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_aclr = "NONE",
altera_mult_add_rtl1.output_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.output_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_type = "NEAREST_INTEGER",
altera_mult_add_rtl1.output_rounding = "NO",
altera_mult_add_rtl1.output_saturate_aclr = "NONE",
altera_mult_add_rtl1.output_saturate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.output_saturate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.output_saturate_register = "UNREGISTERED",
altera_mult_add_rtl1.output_saturate_type = "ASYMMETRIC",
altera_mult_add_rtl1.output_saturation = "NO",
altera_mult_add_rtl1.port_addnsub1 = "PORT_UNUSED",
altera_mult_add_rtl1.port_addnsub3 = "PORT_UNUSED",
altera_mult_add_rtl1.port_chainout_sat_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl1.port_negate = "PORT_UNUSED",
altera_mult_add_rtl1.port_output_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl1.port_signa = "PORT_UNUSED",
altera_mult_add_rtl1.port_signb = "PORT_UNUSED",
altera_mult_add_rtl1.preadder_direction_0 = "ADD",
altera_mult_add_rtl1.preadder_direction_1 = "ADD",
altera_mult_add_rtl1.preadder_direction_2 = "ADD",
altera_mult_add_rtl1.preadder_direction_3 = "ADD",
altera_mult_add_rtl1.preadder_mode = "SIMPLE",
altera_mult_add_rtl1.representation_a = "UNSIGNED",
altera_mult_add_rtl1.representation_b = "UNSIGNED",
altera_mult_add_rtl1.rotate_aclr = "NONE",
altera_mult_add_rtl1.rotate_output_aclr = "NONE",
altera_mult_add_rtl1.rotate_output_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.rotate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_register = "UNREGISTERED",
altera_mult_add_rtl1.scanouta_aclr = "NONE",
altera_mult_add_rtl1.scanouta_register = "UNREGISTERED",
altera_mult_add_rtl1.selected_device_family = "Cyclone IV E",
altera_mult_add_rtl1.shift_mode = "NO",
altera_mult_add_rtl1.shift_right_aclr = "NONE",
altera_mult_add_rtl1.shift_right_output_aclr = "NONE",
altera_mult_add_rtl1.shift_right_output_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_pipeline_aclr = "NONE",
altera_mult_add_rtl1.shift_right_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_register = "UNREGISTERED",
altera_mult_add_rtl1.signed_aclr_a = "NONE",
altera_mult_add_rtl1.signed_aclr_b = "NONE",
altera_mult_add_rtl1.signed_latency_aclr_a = "NONE",
altera_mult_add_rtl1.signed_latency_aclr_b = "NONE",
altera_mult_add_rtl1.signed_latency_clock_a = "UNREGISTERED",
altera_mult_add_rtl1.signed_latency_clock_b = "UNREGISTERED",
altera_mult_add_rtl1.signed_register_a = "UNREGISTERED",
altera_mult_add_rtl1.signed_register_b = "UNREGISTERED",
altera_mult_add_rtl1.systolic_aclr1 = "NONE",
altera_mult_add_rtl1.systolic_aclr3 = "NONE",
altera_mult_add_rtl1.systolic_delay1 = "UNREGISTERED",
altera_mult_add_rtl1.systolic_delay3 = "UNREGISTERED",
altera_mult_add_rtl1.use_sload_accum_port = "NO",
altera_mult_add_rtl1.use_subnadd = "NO",
altera_mult_add_rtl1.width_a = 16,
altera_mult_add_rtl1.width_b = 16,
altera_mult_add_rtl1.width_c = 22,
altera_mult_add_rtl1.width_chainin = 1,
altera_mult_add_rtl1.width_coef = 18,
altera_mult_add_rtl1.width_msb = 17,
altera_mult_add_rtl1.width_result = 32,
altera_mult_add_rtl1.width_saturate_sign = 1,
altera_mult_add_rtl1.zero_chainout_output_aclr = "NONE",
altera_mult_add_rtl1.zero_chainout_output_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_output_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_output_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_pipeline_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_register = "UNREGISTERED",
altera_mult_add_rtl1.lpm_type = "altera_mult_add_rtl";
assign
result = wire_altera_mult_add_rtl1_result;
endmodule //altera_mult_add_q1u2
//VALID FILE
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Juan José Rojas Salazar
//
// Create Date: 30.07.2016 10:22:05
// Design Name:
// Module Name: Convert_Float_To_Fixed
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
//////////////////////////////////////////////////////////////////////////////////
module Convert_Float_To_Fixed(
//INPUTS
input wire CLK, //CLOCK
input wire [31:0] FLOAT, //VALOR DEL NUMERO EN PUNTO FLOTANTE
input wire EN_REG1, //ENABLE PARA EL REGISTRO 1 QUE GUARDA EL NUMERO EN PUNTO FLOTANTE
input wire LOAD, //SELECCION CARGA REGISTRO DE DESPLZAMIENTOS
input wire MS_1, //SELECCIONA EL MUX PARA UN VALOR DIFERENTE O IGUAL A 127 SEGUN SEA EL CASO
input wire RST,
input wire EN_REG2,
//OUTPUTS
output wire Exp_out, //INIDICA SI EL EXPONENTE ES MAYOR QUE 127
output wire [31:0] FIXED, //CONTIENE EL RESULTADO EN COMA FIJA
output wire [7:0] Exp //CONTIENE EL VALOR INICIAL DEL EXPONENTE
);
parameter P = 32;
parameter W = 8;
wire [31:0] float;
FF_D #(.P(P)) REG_FLOAT_I (
.CLK(CLK),
.RST(RST),
.EN(EN_REG1),
.D(FLOAT),
.Q(float)
);
Comparador_Mayor EXP127_I(
.CLK(CLK),
.A(float[30:23]),
.B(8'b01111111),
.Out(Exp_out)
);
wire [31:0] IN_BS;
wire [31:0] P_RESULT;
wire [31:0] MUX32;
wire [31:0] MUX32_OUT;
wire [31:0] NORM;
wire [7:0] MUX1;
wire [7:0] MUX2;
wire [7:0] SUBT_1;
wire [7:0] SUBT_2;
assign IN_BS [31:27] = 5'b00000;
assign IN_BS [26] = 1'b1;
assign IN_BS [25:3] = float[22:0];
assign IN_BS [2:0] = 3'b000;
assign Exp = float[30:23];
Barrel_Shifter #(.SWR(32),.EWR(8)) S_REG_I(
.clk(CLK),
.rst(RST),
.load_i(LOAD),
.Shift_Value_i(MUX2),
.Shift_Data_i(IN_BS),
.Left_Right_i(Exp_out),
.Bit_Shift_i(1'b0),
.N_mant_o(P_RESULT)
);
S_SUBT #(.P(W),.W(W)) SUBT_EXP_1_I (
.A(float[30:23]),
.B(8'b01111111),
.Y(SUBT_1)
);
S_SUBT #(.P(W),.W(W)) SUBT_EXP_2_I (
.A(8'b01111111),
.B(float[30:23]),
.Y(SUBT_2)
);
Mux_2x1_8Bits MUX2x1_1_I (
.MS(Exp_out),
.D_0(SUBT_2),
.D_1(SUBT_1),
.D_out(MUX1)
);
Mux_2x1_8Bits MUX2x1_2_I (
.MS(MS_1),
.D_0(8'b00000000),
.D_1(MUX1),
.D_out(MUX2)
);
SUBT_32Bits SUBT_RESULT_I (
.A(32'b00000000000000000000000000000000),
.B(P_RESULT),
.Y(MUX32)
);
Mux_2x1 #(.P(P)) MUX2x1_32Bits (
.MS(float[31]),
.D_0(P_RESULT),
.D_1(MUX32),
.D_out(MUX32_OUT)
);
FF_D #(.P(P)) REG_FIXED (
.CLK(CLK),
.RST(RST),
.EN(EN_REG2),
.D(MUX32_OUT),
.Q(FIXED)
);
endmodule |
`timescale 1ns / 1ps
//this code was generated by cReComp
module sensor_ctl(
input [0:0] clk,
input rst_32,
input [31:0] din_32,
input [0:0] wr_en_32,
input [0:0] rd_en_32,
output [31:0] dout_32,
output [0:0] full_32,
output [0:0] empty_32,
input [0:0] SPI_DI_a,
output [0:0] SPI_SS_a,
output [0:0] SPI_CK_a,
output [0:0] SPI_DO_a,
input [0:0] SPI_DI_g,
output [0:0] SPI_SS_g,
output [0:0] SPI_CK_g,
output [0:0] SPI_DO_g
);
parameter INIT_32 = 0,
READY_RCV_32 = 1,
RCV_DATA_32 = 2,
POSE_32 = 3,
READY_SND_32 = 4,
SND_DATA_32_ax = 5,
SND_DATA_32_ay = 6,
SND_DATA_32_az = 7,
SND_DATA_32_gx = 8,
SND_DATA_32_gy = 9,
SND_DATA_32_gz = 10;
// for input fifo
wire [31:0] rcv_data_32;
wire rcv_en_32;
wire data_empty_32;
// for output fifo
wire [31:0] snd_data_32;
wire snd_en_32;
wire data_full_32;
// state register
reg [3:0] state_32;
wire [15:0] accel_x;
wire [15:0] accel_y;
wire [15:0] accel_z;
wire [15:0] gyro_x;
wire [15:0] gyro_y;
wire [15:0] gyro_z;
reg [15:0] accel_x_reg;
reg [15:0] accel_y_reg;
reg [15:0] accel_z_reg;
reg [15:0] gyro_x_reg;
reg [15:0] gyro_y_reg;
reg [15:0] gyro_z_reg;
wire arm_rd_en_a;
wire arm_rd_en_g;
////fifo 32bit
fifo_32x512 input_fifo_32(
.clk(clk),
.srst(rst_32),
.din(din_32),
.wr_en(wr_en_32),
.full(full_32),
.dout(rcv_data_32),
.rd_en(rcv_en_32),
.empty(data_empty_32)
);
fifo_32x512 output_fifo_32(
.clk(clk),
.srst(rst_32),
.din(snd_data_32),
.wr_en(snd_en_32),
.full(data_full_32),
.dout(dout_32),
.rd_en(rd_en_32),
.empty(empty_32)
);
MPU_gyro_controller MPU_gyro_controller(
.clk(clk),
.reset(rst_32),
.gyro_x(gyro_x),
.gyro_y(gyro_y),
.gyro_z(gyro_z),
.SPI_SS_g(SPI_SS_g), //Sleve select
.SPI_CK_g(SPI_CK_g), //SCLK
.SPI_DO_g(SPI_DO_g), //Master out Sleve in
.SPI_DI_g(SPI_DI_g), //Master in Slave out
.arm_read_enable_g(arm_rd_en_g) //finish sensing accel_xyz
);
MPU_accel_controller MPU_accel_controller(
.clk(clk),
.reset(rst_32),
.accel_x(accel_x),
.accel_y(accel_y),
.accel_z(accel_z),
.SPI_SS_a(SPI_SS_a), //Sleve select
.SPI_CK_a(SPI_CK_a), //SCLK
.SPI_DO_a(SPI_DO_a), //Master out Sleve in
.SPI_DI_a(SPI_DI_a), //Master in Slave out
.arm_read_enable_a(arm_rd_en_a) //finish sensing accel_xyz
);
always @(posedge clk)begin
if(rst_32)
state_32 <= 0;
else
case (state_32)
INIT_32: state_32 <= READY_RCV_32;
READY_RCV_32: if(1) state_32 <= RCV_DATA_32;
RCV_DATA_32: state_32 <= POSE_32;
POSE_32: if(arm_rd_en_a || arm_rd_en_g) state_32 <= READY_SND_32;
// POSE_32: if(1) state_32 <= READY_SND_32;
READY_SND_32: if(data_full_32 == 0) state_32 <= SND_DATA_32_ax;
// READY_SND_32: if(1) state_32 <= SND_DATA_32_x;
SND_DATA_32_ax: state_32 <= SND_DATA_32_ay;
SND_DATA_32_ay: state_32 <= SND_DATA_32_az;
SND_DATA_32_az: state_32 <= SND_DATA_32_gx;
SND_DATA_32_gx: state_32 <= SND_DATA_32_gy;
SND_DATA_32_gy: state_32 <= SND_DATA_32_gz;
SND_DATA_32_gz: state_32 <= READY_RCV_32;
endcase
end
assign rcv_en_32 = (state_32 == RCV_DATA_32);
assign snd_en_32 = (state_32 > READY_SND_32);
assign snd_data_32 = (state_32 == SND_DATA_32_ax)? accel_x_reg:
(state_32 == SND_DATA_32_ay)? accel_y_reg:
(state_32 == SND_DATA_32_az)? accel_z_reg:
(state_32 == SND_DATA_32_gx)? gyro_x_reg:
(state_32 == SND_DATA_32_gy)? gyro_y_reg:
(state_32 == SND_DATA_32_gz)? gyro_z_reg:0;
always @(posedge clk) begin
if (rst_32) begin
accel_x_reg <= 0;
accel_y_reg <= 0;
accel_z_reg <= 0;
gyro_x_reg <= 0;
gyro_y_reg <= 0;
gyro_z_reg <= 0;
end
else
case (state_32)
INIT_32: begin
accel_x_reg <= 0;
accel_y_reg <= 0;
accel_z_reg <= 0;
gyro_x_reg <= 0;
gyro_y_reg <= 0;
gyro_z_reg <= 0;
end
READY_RCV_32: begin
accel_x_reg <= 0;
accel_y_reg <= 0;
accel_z_reg <= 0;
gyro_x_reg <= 0;
gyro_y_reg <= 0;
gyro_z_reg <= 0;
end
POSE_32: begin
accel_x_reg <= accel_x;
accel_y_reg <= accel_y;
accel_z_reg <= accel_z;
gyro_x_reg <= gyro_x;
gyro_y_reg <= gyro_y;
gyro_z_reg <= gyro_z;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211AI_BLACKBOX_V
`define SKY130_FD_SC_HS__O211AI_BLACKBOX_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o211ai (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211AI_BLACKBOX_V
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: acv_hard_memphy.v
// This file instantiates all the main components of the PHY.
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_hard_memphy (
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
afi_reset_n,
pll_locked,
oct_ctl_rs_value,
oct_ctl_rt_value,
afi_addr,
afi_ba,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_we_n,
afi_cas_n,
afi_rst_n,
afi_odt,
afi_mem_clk_disable,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_rdata,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata_valid,
afi_wlat,
afi_rlat,
afi_cal_success,
afi_cal_fail,
avl_read,
avl_write,
avl_address,
avl_writedata,
avl_waitrequest,
avl_readdata,
cfg_addlat,
cfg_bankaddrwidth,
cfg_caswrlat,
cfg_coladdrwidth,
cfg_csaddrwidth,
cfg_devicewidth,
cfg_dramconfig,
cfg_interfacewidth,
cfg_rowaddrwidth,
cfg_tcl,
cfg_tmrd,
cfg_trefi,
cfg_trfc,
cfg_twr,
io_intaddrdout,
io_intbadout,
io_intcasndout,
io_intckdout,
io_intckedout,
io_intckndout,
io_intcsndout,
io_intdmdout,
io_intdqdin,
io_intdqdout,
io_intdqoe,
io_intdqsbdout,
io_intdqsboe,
io_intdqsdout,
io_intdqslogicdqsena,
io_intdqslogicfiforeset,
io_intdqslogicincrdataen,
io_intdqslogicincwrptr,
io_intdqslogicoct,
io_intdqslogicrdatavalid,
io_intdqslogicreadlatency,
io_intdqsoe,
io_intodtdout,
io_intrasndout,
io_intresetndout,
io_intwendout,
io_intafirlat,
io_intafiwlat,
io_intaficalfail,
io_intaficalsuccess,
mem_a,
mem_ba,
mem_cs_n,
mem_cke,
mem_odt,
mem_we_n,
mem_ras_n,
mem_cas_n,
mem_reset_n,
mem_dq,
mem_dm,
mem_ck,
mem_ck_n,
mem_dqs,
mem_dqs_n,
reset_n_scc_clk,
reset_n_avl_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
capture_strobe_tracking,
phy_clk,
ctl_clk,
phy_reset_n,
pll_afi_clk,
pll_afi_half_clk,
pll_addr_cmd_clk,
pll_mem_clk,
pll_mem_phy_clk,
pll_afi_phy_clk,
pll_avl_phy_clk,
pll_write_clk,
pll_write_clk_pre_phy_clk,
pll_dqs_ena_clk,
seq_clk,
pll_avl_clk,
pll_config_clk,
dll_clk,
dll_pll_locked,
dll_phy_delayctrl
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DEVICE_FAMILY = "";
parameter IS_HHP_HPS = "false";
// On-chip termination
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
// PHY-Memory Interface
// Memory device specific parameters, they are set according to the memory spec
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_IF_CS_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
// PHY-Controller (AFI) Interface
// The AFI interface widths are derived from the memory interface widths based on full/half rate operations
// The calculations are done on higher level wrapper
// DLL Interface
// The DLL delay output control is always 6 bits for current existing devices
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter MR1_ODS = "";
parameter MR1_RTT = "";
parameter MR2_RTT_WR = "";
parameter TB_PROTOCOL = "";
parameter TB_MEM_CLK_FREQ = "";
parameter TB_RATE = "";
parameter TB_MEM_DQ_WIDTH = "";
parameter TB_MEM_DQS_WIDTH = "";
parameter TB_PLL_DLL_MASTER = "";
parameter FAST_SIM_MODEL = "";
parameter FAST_SIM_CALIBRATION = "";
// Width of the calibration status register used to control calibration skipping.
parameter CALIB_REG_WIDTH = "";
parameter AC_ROM_INIT_FILE_NAME = "";
parameter INST_ROM_INIT_FILE_NAME = "";
// The number of AFI Resets to generate
localparam NUM_AFI_RESET = 4;
// Addr/cmd clock phase
localparam ADC_PHASE_SETTING = 0;
localparam ADC_INVERT_PHASE = "true";
// END PARAMETER SECTION
// ********************************************************************************************************************************
// ********************************************************************************************************************************
// BEGIN PORT SECTION
// Reset Interface
input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
input soft_reset_n; // Resets (active-low) PHY logic only, PLL is NOT reset
input pll_locked; // Indicates that PLL is locked
output ctl_reset_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output ctl_reset_export_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output afi_reset_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
// PHY-Controller Interface, AFI 2.0
// Control Interface
input [19:0] afi_addr;
input [2:0] afi_ba;
input [1:0] afi_cke;
input [1:0] afi_cs_n;
input [0:0] afi_cas_n;
input [1:0] afi_odt;
input [0:0] afi_ras_n;
input [0:0] afi_we_n;
input [0:0] afi_rst_n;
input [0:0] afi_mem_clk_disable;
input [4:0] afi_dqs_burst;
output [3:0] afi_wlat;
output [4:0] afi_rlat;
// Write data interface
input [79:0] afi_wdata; // write data
input [4:0] afi_wdata_valid; // write data valid, used to maintain write latency required by protocol spec
input [9:0] afi_dm; // write data mask
// Read data interface
output [79:0] afi_rdata; // read data
input [4:0] afi_rdata_en; // read enable, used to maintain the read latency calibrated by PHY
input [4:0] afi_rdata_en_full; // read enable full burst, used to create DQS enable
output [0:0] afi_rdata_valid; // read data valid
// Status interface
output afi_cal_success; // calibration success
output afi_cal_fail; // calibration failure
// Avalon interface to the sequencer
input [15:0] avl_address; //MarkW TODO: the sequencer only uses 13 bits
input avl_read;
output [31:0] avl_readdata;
output avl_waitrequest;
input avl_write;
input [31:0] avl_writedata;
// Configuration interface to the memory controller
input [7:0] cfg_addlat;
input [7:0] cfg_bankaddrwidth;
input [7:0] cfg_caswrlat;
input [7:0] cfg_coladdrwidth;
input [7:0] cfg_csaddrwidth;
input [7:0] cfg_devicewidth;
input [23:0] cfg_dramconfig;
input [7:0] cfg_interfacewidth;
input [7:0] cfg_rowaddrwidth;
input [7:0] cfg_tcl;
input [7:0] cfg_tmrd;
input [15:0] cfg_trefi;
input [7:0] cfg_trfc;
input [7:0] cfg_twr;
// IO/bypass interface to the core (or soft controller)
input [63:0] io_intaddrdout;
input [11:0] io_intbadout;
input [3:0] io_intcasndout;
input [3:0] io_intckdout;
input [7:0] io_intckedout;
input [3:0] io_intckndout;
input [7:0] io_intcsndout;
input [19:0] io_intdmdout;
output [179:0] io_intdqdin;
input [179:0] io_intdqdout;
input [89:0] io_intdqoe;
input [19:0] io_intdqsbdout;
input [9:0] io_intdqsboe;
input [19:0] io_intdqsdout;
input [9:0] io_intdqslogicdqsena;
input [4:0] io_intdqslogicfiforeset;
input [9:0] io_intdqslogicincrdataen;
input [9:0] io_intdqslogicincwrptr;
input [9:0] io_intdqslogicoct;
output [4:0] io_intdqslogicrdatavalid;
input [24:0] io_intdqslogicreadlatency;
input [9:0] io_intdqsoe;
input [7:0] io_intodtdout;
input [3:0] io_intrasndout;
input [3:0] io_intresetndout;
input [3:0] io_intwendout;
output [4:0] io_intafirlat;
output [3:0] io_intafiwlat;
output io_intaficalfail;
output io_intaficalsuccess;
// PHY-Memory Interface
output [MEM_ADDRESS_WIDTH-1:0] mem_a;
output [MEM_BANK_WIDTH-1:0] mem_ba;
output [MEM_IF_CS_WIDTH-1:0] mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] mem_cke;
output [MEM_ODT_WIDTH-1:0] mem_odt;
output [MEM_CONTROL_WIDTH-1:0] mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] mem_cas_n;
output mem_reset_n;
inout [MEM_DQ_WIDTH-1:0] mem_dq;
output [MEM_DM_WIDTH-1:0] mem_dm;
output [MEM_CK_WIDTH-1:0] mem_ck;
output [MEM_CK_WIDTH-1:0] mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
output reset_n_scc_clk;
output reset_n_avl_clk;
// Scan chain configuration manager interface
input scc_data;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH-1:0] scc_dq_ena;
input [MEM_DM_WIDTH-1:0] scc_dm_ena;
input [0:0] scc_upd;
output [MEM_READ_DQS_WIDTH-1:0] capture_strobe_tracking;
output phy_clk;
output ctl_clk;
output phy_reset_n;
// PLL Interface
input pll_afi_clk; // clocks AFI interface logic
input pll_afi_half_clk; //
input pll_addr_cmd_clk; // clocks address/command DDIO
input pll_mem_clk; // output clock to memory
input pll_write_clk; // clocks write data DDIO
input pll_write_clk_pre_phy_clk;
input pll_dqs_ena_clk;
input seq_clk;
input pll_avl_clk;
input pll_config_clk;
input pll_mem_phy_clk;
input pll_afi_phy_clk;
input pll_avl_phy_clk;
// DLL Interface
output dll_clk;
output dll_pll_locked;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl; // dll output used to control the input DQS phase shift
// END PARAMETER SECTION
// ********************************************************************************************************************************
wire [179:0] ddio_phy_dqdin;
wire [4:0] ddio_phy_dqslogic_rdatavalid;
wire [63:0] phy_ddio_address;
wire [11:0] phy_ddio_bank;
wire [3:0] phy_ddio_cas_n;
wire [3:0] phy_ddio_ck;
wire [7:0] phy_ddio_cke;
wire [3:0] phy_ddio_ck_n;
wire [7:0] phy_ddio_cs_n;
wire [19:0] phy_ddio_dmdout;
wire [179:0] phy_ddio_dqdout;
wire [89:0] phy_ddio_dqoe;
wire [9:0] phy_ddio_dqsb_oe;
wire [9:0] phy_ddio_dqslogic_dqsena;
wire [4:0] phy_ddio_dqslogic_fiforeset;
wire [4:0] phy_ddio_dqslogic_aclr_pstamble;
wire [4:0] phy_ddio_dqslogic_aclr_fifoctrl;
wire [9:0] phy_ddio_dqslogic_incrdataen;
wire [9:0] phy_ddio_dqslogic_incwrptr;
wire [9:0] phy_ddio_dqslogic_oct;
wire [24:0] phy_ddio_dqslogic_readlatency;
wire [9:0] phy_ddio_dqs_oe;
wire [19:0] phy_ddio_dqs_dout;
wire [7:0] phy_ddio_odt;
wire [3:0] phy_ddio_ras_n;
wire [3:0] phy_ddio_reset_n;
wire [3:0] phy_ddio_we_n;
wire read_capture_clk;
wire [NUM_AFI_RESET-1:0] reset_n_afi_clk;
wire reset_n_addr_cmd_clk;
wire reset_n_seq_clk;
wire reset_n_scc_clk;
wire reset_n_avl_clk;
wire reset_n_resync_clk;
localparam SKIP_CALIBRATION_STEPS = 7'b1111111;
localparam CALIBRATION_STEPS = SKIP_CALIBRATION_STEPS;
localparam SKIP_MEM_INIT = 1'b1;
localparam SEQ_CALIB_INIT = {CALIBRATION_STEPS, SKIP_MEM_INIT};
generate
if (IS_HHP_HPS != "true") begin
reg [CALIB_REG_WIDTH-1:0] seq_calib_init_reg /* synthesis syn_noprune syn_preserve = 1 */;
// Initialization of the sequencer status register. This register
// is preserved in the netlist so that it can be forced during simulation
always @(posedge pll_afi_clk)
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_off
`endif
seq_calib_init_reg <= SEQ_CALIB_INIT;
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_on
//synthesis read_comments_as_HDL on
`endif
// seq_calib_init_reg <= {CALIB_REG_WIDTH{1'b0}};
`ifdef SYNTH_FOR_SIM
`else
// synthesis read_comments_as_HDL off
`endif
end
endgenerate
// ********************************************************************************************************************************
// The reset scheme used in the UNIPHY is asynchronous assert and synchronous de-assert
// The reset block has 2 main functionalities:
// 1. Keep all the PHY logic in reset state until after the PLL is locked
// 2. Synchronize the reset to each clock domain
// ********************************************************************************************************************************
generate
if (IS_HHP_HPS != "true") begin
hps_sdram_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
end else begin
// synthesis translate_off
hps_sdram_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
// synthesis translate_on
// synthesis read_comments_as_HDL on
// assign reset_n_afi_clk = {NUM_AFI_RESET{global_reset_n}};
// assign reset_n_addr_cmd_clk = global_reset_n;
// assign reset_n_avl_clk = global_reset_n;
// assign reset_n_scc_clk = global_reset_n;
// synthesis read_comments_as_HDL off
end
endgenerate
assign phy_clk = seq_clk;
assign phy_reset_n = reset_n_seq_clk;
assign dll_clk = pll_write_clk_pre_phy_clk;
assign dll_pll_locked = pll_locked;
// PHY clock and LDC
wire afi_clk;
wire avl_clk;
wire adc_clk;
wire adc_clk_cps;
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH (DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING (ADC_PHASE_SETTING),
.ADC_INVERT_PHASE (ADC_INVERT_PHASE),
.IS_HHP_HPS (IS_HHP_HPS)
) memphy_ldc (
.pll_hr_clk (pll_avl_phy_clk),
.pll_dq_clk (pll_write_clk),
.pll_dqs_clk (pll_mem_phy_clk),
.dll_phy_delayctrl (dll_phy_delayctrl),
.afi_clk (afi_clk),
.avl_clk (avl_clk),
.adc_clk (adc_clk),
.adc_clk_cps (adc_clk_cps)
);
assign ctl_clk = afi_clk;
assign afi_reset_n = reset_n_afi_clk;
// ********************************************************************************************************************************
// This is the hard PHY instance
// ********************************************************************************************************************************
cyclonev_mem_phy hphy_inst (
.pllaficlk (afi_clk),
.pllavlclk (avl_clk),
.plllocked (pll_locked),
.plladdrcmdclk (adc_clk),
.globalresetn (global_reset_n),
.softresetn (soft_reset_n),
.phyresetn (phy_reset_n),
.ctlresetn (ctl_reset_n),
.iointaddrdout (io_intaddrdout),
.iointbadout (io_intbadout),
.iointcasndout (io_intcasndout),
.iointckdout (io_intckdout),
.iointckedout (io_intckedout),
.iointckndout (io_intckndout),
.iointcsndout (io_intcsndout),
.iointdmdout (io_intdmdout),
.iointdqdin (io_intdqdin),
.iointdqdout (io_intdqdout),
.iointdqoe (io_intdqoe),
.iointdqsbdout (io_intdqsbdout),
.iointdqsboe (io_intdqsboe),
.iointdqsdout (io_intdqsdout),
.iointdqslogicdqsena (io_intdqslogicdqsena),
.iointdqslogicfiforeset (io_intdqslogicfiforeset),
.iointdqslogicincrdataen (io_intdqslogicincrdataen),
.iointdqslogicincwrptr (io_intdqslogicincwrptr),
.iointdqslogicoct (io_intdqslogicoct),
.iointdqslogicrdatavalid (io_intdqslogicrdatavalid),
.iointdqslogicreadlatency (io_intdqslogicreadlatency),
.iointdqsoe (io_intdqsoe),
.iointodtdout (io_intodtdout),
.iointrasndout (io_intrasndout),
.iointresetndout (io_intresetndout),
.iointwendout (io_intwendout),
.iointafirlat (io_intafirlat),
.iointafiwlat (io_intafiwlat),
.iointaficalfail (io_intaficalfail),
.iointaficalsuccess (io_intaficalsuccess),
.ddiophydqdin (ddio_phy_dqdin),
.ddiophydqslogicrdatavalid (ddio_phy_dqslogic_rdatavalid),
.phyddioaddrdout (phy_ddio_address),
.phyddiobadout (phy_ddio_bank),
.phyddiocasndout (phy_ddio_cas_n),
.phyddiockdout (phy_ddio_ck),
.phyddiockedout (phy_ddio_cke),
.phyddiockndout (),
.phyddiocsndout (phy_ddio_cs_n),
.phyddiodmdout (phy_ddio_dmdout),
.phyddiodqdout (phy_ddio_dqdout),
.phyddiodqoe (phy_ddio_dqoe),
.phyddiodqsbdout (),
.phyddiodqsboe (phy_ddio_dqsb_oe),
.phyddiodqslogicdqsena (phy_ddio_dqslogic_dqsena),
.phyddiodqslogicfiforeset (phy_ddio_dqslogic_fiforeset),
.phyddiodqslogicaclrpstamble (phy_ddio_dqslogic_aclr_pstamble),
.phyddiodqslogicaclrfifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phyddiodqslogicincrdataen (phy_ddio_dqslogic_incrdataen),
.phyddiodqslogicincwrptr (phy_ddio_dqslogic_incwrptr),
.phyddiodqslogicoct (phy_ddio_dqslogic_oct),
.phyddiodqslogicreadlatency (phy_ddio_dqslogic_readlatency),
.phyddiodqsoe (phy_ddio_dqs_oe),
.phyddiodqsdout (phy_ddio_dqs_dout),
.phyddioodtdout (phy_ddio_odt),
.phyddiorasndout (phy_ddio_ras_n),
.phyddioresetndout (phy_ddio_reset_n),
.phyddiowendout (phy_ddio_we_n),
.afiaddr (afi_addr),
.afiba (afi_ba),
.aficalfail (afi_cal_fail),
.aficalsuccess (afi_cal_success),
.aficasn (afi_cas_n),
.aficke (afi_cke),
.aficsn (afi_cs_n),
.afidm (afi_dm),
.afidqsburst (afi_dqs_burst),
.afimemclkdisable (afi_mem_clk_disable),
.afiodt (afi_odt),
.afirasn (afi_ras_n),
.afirdata (afi_rdata),
.afirdataen (afi_rdata_en),
.afirdataenfull (afi_rdata_en_full),
.afirdatavalid (afi_rdata_valid),
.afirlat (afi_rlat),
.afirstn (afi_rst_n),
.afiwdata (afi_wdata),
.afiwdatavalid (afi_wdata_valid),
.afiwen (afi_we_n),
.afiwlat (afi_wlat),
.avladdress (avl_address),
.avlread (avl_read),
.avlreaddata (avl_readdata),
.avlresetn (reset_n_avl_clk),
.avlwaitrequest (avl_waitrequest),
.avlwrite (avl_write),
.avlwritedata (avl_writedata),
.cfgaddlat (cfg_addlat),
.cfgbankaddrwidth (cfg_bankaddrwidth),
.cfgcaswrlat (cfg_caswrlat),
.cfgcoladdrwidth (cfg_coladdrwidth),
.cfgcsaddrwidth (cfg_csaddrwidth),
.cfgdevicewidth (cfg_devicewidth),
.cfgdramconfig (cfg_dramconfig),
.cfginterfacewidth (cfg_interfacewidth),
.cfgrowaddrwidth (cfg_rowaddrwidth),
.cfgtcl (cfg_tcl),
.cfgtmrd (cfg_tmrd),
.cfgtrefi (cfg_trefi),
.cfgtrfc (cfg_trfc),
.cfgtwr (cfg_twr),
.scanen ()
);
defparam hphy_inst.hphy_ac_ddr_disable = "true";
defparam hphy_inst.hphy_datapath_delay = "one_cycle";
defparam hphy_inst.hphy_datapath_ac_delay = "one_and_half_cycles";
defparam hphy_inst.hphy_reset_delay_en = "false";
defparam hphy_inst.m_hphy_ac_rom_init_file = AC_ROM_INIT_FILE_NAME;
defparam hphy_inst.m_hphy_inst_rom_init_file = INST_ROM_INIT_FILE_NAME;
defparam hphy_inst.hphy_wrap_back_en = "false";
defparam hphy_inst.hphy_atpg_en = "false";
defparam hphy_inst.hphy_use_hphy = "true";
defparam hphy_inst.hphy_csr_pipelineglobalenable = "true";
defparam hphy_inst.hphy_hhp_hps = IS_HHP_HPS;
// ********************************************************************************************************************************
// The I/O block is responsible for instantiating all the built-in I/O logic in the FPGA
// ********************************************************************************************************************************
hps_sdram_p0_acv_hard_io_pads #(
.DEVICE_FAMILY(DEVICE_FAMILY),
.FAST_SIM_MODEL(FAST_SIM_MODEL),
.OCT_SERIES_TERM_CONTROL_WIDTH(OCT_SERIES_TERM_CONTROL_WIDTH),
.OCT_PARALLEL_TERM_CONTROL_WIDTH(OCT_PARALLEL_TERM_CONTROL_WIDTH),
.MEM_ADDRESS_WIDTH(MEM_ADDRESS_WIDTH),
.MEM_BANK_WIDTH(MEM_BANK_WIDTH),
.MEM_CHIP_SELECT_WIDTH(MEM_IF_CS_WIDTH),
.MEM_CLK_EN_WIDTH(MEM_CLK_EN_WIDTH),
.MEM_CK_WIDTH(MEM_CK_WIDTH),
.MEM_ODT_WIDTH(MEM_ODT_WIDTH),
.MEM_DQS_WIDTH(MEM_DQS_WIDTH),
.MEM_DM_WIDTH(MEM_DM_WIDTH),
.MEM_CONTROL_WIDTH(MEM_CONTROL_WIDTH),
.MEM_DQ_WIDTH(MEM_DQ_WIDTH),
.MEM_READ_DQS_WIDTH(MEM_READ_DQS_WIDTH),
.MEM_WRITE_DQS_WIDTH(MEM_WRITE_DQS_WIDTH),
.DLL_DELAY_CTRL_WIDTH(DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) uio_pads (
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk[1]),
.oct_ctl_rs_value (oct_ctl_rs_value),
.oct_ctl_rt_value (oct_ctl_rt_value),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_ck (phy_ddio_ck),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_address (mem_a),
.phy_mem_bank (mem_ba),
.phy_mem_cs_n (mem_cs_n),
.phy_mem_cke (mem_cke),
.phy_mem_odt (mem_odt),
.phy_mem_we_n (mem_we_n),
.phy_mem_ras_n (mem_ras_n),
.phy_mem_cas_n (mem_cas_n),
.phy_mem_reset_n (mem_reset_n),
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk (pll_mem_clk),
.pll_afi_phy_clk (pll_afi_phy_clk),
.pll_avl_phy_clk (pll_avl_phy_clk),
.pll_avl_clk (pll_avl_clk),
.avl_clk (avl_clk),
.pll_mem_phy_clk (pll_mem_phy_clk),
.pll_write_clk (pll_write_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.pll_addr_cmd_clk (adc_clk_cps),
.phy_mem_dq (mem_dq),
.phy_mem_dm (mem_dm),
.phy_mem_ck (mem_ck),
.phy_mem_ck_n (mem_ck_n),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.dll_phy_delayctrl (dll_phy_delayctrl),
.scc_clk (pll_config_clk),
.scc_data (scc_data),
.scc_dqs_ena (scc_dqs_ena),
.scc_dqs_io_ena (scc_dqs_io_ena),
.scc_dq_ena (scc_dq_ena),
.scc_dm_ena (scc_dm_ena),
.scc_upd (scc_upd[0]),
.phy_ddio_dmdout (phy_ddio_dmdout),
.phy_ddio_dqdout (phy_ddio_dqdout),
.phy_ddio_dqs_oe (phy_ddio_dqs_oe),
.phy_ddio_dqsdout (phy_ddio_dqs_dout),
.phy_ddio_dqsb_oe (phy_ddio_dqsb_oe),
.phy_ddio_dqslogic_oct (phy_ddio_dqslogic_oct),
.phy_ddio_dqslogic_fiforeset (phy_ddio_dqslogic_fiforeset),
.phy_ddio_dqslogic_aclr_pstamble (phy_ddio_dqslogic_aclr_pstamble),
.phy_ddio_dqslogic_aclr_fifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phy_ddio_dqslogic_incwrptr (phy_ddio_dqslogic_incwrptr),
.phy_ddio_dqslogic_readlatency (phy_ddio_dqslogic_readlatency),
.ddio_phy_dqslogic_rdatavalid (ddio_phy_dqslogic_rdatavalid),
.ddio_phy_dqdin (ddio_phy_dqdin),
.phy_ddio_dqslogic_incrdataen (phy_ddio_dqslogic_incrdataen),
.phy_ddio_dqslogic_dqsena (phy_ddio_dqslogic_dqsena),
.phy_ddio_dqoe (phy_ddio_dqoe),
.capture_strobe_tracking (capture_strobe_tracking)
);
generate
if (IS_HHP_HPS != "true") begin
reg afi_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_clk)
afi_clk_reg <= ~afi_clk_reg;
reg afi_half_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_half_clk)
afi_half_clk_reg <= ~afi_half_clk_reg;
reg avl_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_avl_clk)
avl_clk_reg <= ~avl_clk_reg;
reg config_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_config_clk)
config_clk_reg <= ~config_clk_reg;
end
endgenerate
// Calculate the ceiling of log_2 of the input value
function integer ceil_log2;
input integer value;
begin
value = value - 1;
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
value = value >> 1;
end
endfunction
endmodule
|
Require Import List.
Require Import InfSeqExt.infseq.
Require Import InfSeqExt.map.
Require Import InfSeqExt.exteq.
Require Import StructTact.StructTactics.
Require Import StructTact.Util.
Require Import Cheerios.Cheerios.
Require Import Chord.Chord.
Require Import Chord.ChordSerialized.
Require Import Chord.ChordSerializedSimulations.
(*
Require Import Chord.ChordStabilization.
Require Import Chord.SystemReachable.
Require Import Chord.SystemPointers.
Require Import Chord.QueriesEventuallyStop.
(* useful definitions and lemmas *)
Definition serialize_occurrence (occ : ChordSemantics.occurrence) :=
{| occ_gst := serialize_global_state (ChordSemantics.occ_gst occ);
occ_label := (ChordSemantics.occ_label occ) |}.
Definition revert_occurrence (occ : ChordSerializedSemantics.occurrence) :=
{| ChordSemantics.occ_gst := revert_global_state (ChordSerializedSemantics.occ_gst occ);
ChordSemantics.occ_label := (ChordSerializedSemantics.occ_label occ) |}.
Definition revert_serialize_occurrence o :=
serialize_occurrence (revert_occurrence o).
Inductive reachable_st_serialized : global_state -> Prop :=
reachableInitS : forall gst,
initial_st (revert_global_state gst) -> reachable_st_serialized gst
| reachableStepS : forall gst gst',
reachable_st_serialized gst ->
ChordSerializedSemantics.step_dynamic gst gst' ->
reachable_st_serialized gst'.
Lemma revert_reachable : forall ex : infseq occurrence,
reachable_st_serialized (occ_gst (infseq.hd ex)) ->
reachable_st (ChordSemantics.occ_gst (infseq.hd (map revert_occurrence ex))).
Proof.
intros.
destruct ex.
simpl in *.
induction H.
- constructor.
assumption.
- eapply reachableStep; eauto.
apply step_dynamic_serialized_step_dynamic.
assumption.
Qed.
Lemma revert_lb_execution : forall ex,
lb_execution ex ->
ChordSemantics.lb_execution (map revert_occurrence ex).
Proof.
cofix.
intros.
do 2 (destruct ex; rewrite map_Cons).
constructor; inv H.
- apply serialized_labeled_step_labeled_step.
assumption.
- rewrite <- map_Cons.
apply revert_lb_execution.
assumption.
Qed.
(* rewrite definitions for stabilization property *)
Definition live_node gst h :=
In h (nodes gst) /\
~ In h (failed_nodes gst) /\
(exists st : data, sigma gst h = Some st /\ joined st = true).
Definition correct_succs (gst : global_state) (h : pointer) (st : data) : Prop :=
forall s xs ys s',
wf_ptr h ->
succ_list st = xs ++ s :: ys ->
ptr_between h s' s ->
live_node gst (addr_of s') ->
wf_ptr s' ->
In s' xs.
Definition better_pred (gst : global_state) (h p p' : pointer) : Prop :=
wf_ptr h /\
wf_ptr p /\
wf_ptr p' /\
live_node gst (addr_of p') /\
ptr_between p p' h.
Definition pred_correct (gst : global_state) (h : pointer) (p : option pointer) : Prop :=
exists p0,
p = Some p0 /\
forall p',
p' <> p0 ->
live_node gst (addr_of p') ->
wf_ptr p' ->
better_pred gst h p' p0.
Definition ideal (gst : global_state) : Prop :=
forall h st,
live_node gst (addr_of h) ->
wf_ptr h ->
sigma gst (addr_of h) = Some st ->
correct_succs gst h st /\
length (succ_list st) = Chord.SUCC_LIST_LEN /\
pred_correct gst h (pred st).
(* more helper lemmas *)
Lemma revert_live_node : forall gst h, live_node (serialize_global_state gst) (addr_of h) ->
ConstrainedChord.live_node gst (addr_of h).
Proof.
intuition.
Qed.
Lemma preserves_ideal_gst : forall gst,
ChordStabilization.ideal gst -> ideal (serialize_global_state gst).
Proof.
unfold ChordStabilization.ideal, ideal.
intros.
apply H; assumption.
Qed.
Lemma serialize_ideal : forall occ,
ChordStabilization.ideal (ChordSemantics.occ_gst occ) ->
ideal (occ_gst (serialize_occurrence occ)).
Proof.
destruct occ.
simpl.
apply preserves_ideal_gst.
Qed.
Lemma serialize_continuously_ideal : forall ex : infseq ChordSemantics.occurrence,
continuously (now (fun o => ChordStabilization.ideal (ChordSemantics.occ_gst o))) ex ->
continuously (now (fun o => ideal (occ_gst o)))
(map serialize_occurrence ex).
Proof.
intros.
eapply continuously_map; eauto.
intros.
destruct s. simpl in *.
apply serialize_ideal.
assumption.
Qed.
Lemma ideal_extensional : extensional (continuously (now (fun o => ideal (occ_gst o)))).
Proof.
apply extensional_continuously.
unfold extensional, now.
intros.
do 2 break_match.
find_apply_lem_hyp exteq_inversion.
break_and. subst_max.
assumption.
Qed.
Definition blocked_by (gst : global_state) (s h : addr) : Prop :=
In h (nodes gst) /\
In s (nodes gst) /\
exists st__h st__s dstp q m,
sigma gst h = Some st__h /\
sigma gst s = Some st__s /\
cur_request st__h = Some (dstp, q, m) /\
addr_of dstp = s /\
In (h, m) (delayed_queries st__s).
Definition circular_wait occ :=
has_cycle (blocked_by (occ_gst occ)).
Lemma revert_circular_wait : forall ex,
always (~_ now circular_wait) ex ->
always (~_ now QueriesEventuallyStop.circular_wait) (map revert_occurrence ex).
Proof.
apply always_map.
intros.
eapply not_tl_map; eauto.
unfold now. destruct s0.
rewrite map_Cons.
unfold QueriesEventuallyStop.circular_wait, circular_wait,
QueriesEventuallyStop.blocked_by, blocked_by, has_cycle.
intros. break_exists.
eauto.
Qed.
Lemma revert_serialize_msgs : forall gst,
serialize_global_state (revert_global_state gst) = gst ->
List.map serialize_msg (List.map revert_msg (msgs gst)) = msgs gst.
Proof.
unfold serialize_global_state, revert_global_state. simpl.
intros.
find_reverse_rewrite.
simpl.
rewrite serialize_revert_msgs.
reflexivity.
Qed.
Lemma revert_serialize_trace : forall gst,
serialize_global_state (revert_global_state gst) = gst ->
List.map serialize_event
(List.map revert_event (trace gst)) = trace gst.
Proof.
destruct gst.
unfold serialize_global_state, revert_global_state. simpl.
intros.
find_inversion.
rewrite serialize_revert_events.
reflexivity.
Qed.
Lemma serialize_send_revert_serialize : forall l h,
List.map serialize_event
(List.map revert_event
(List.map e_send (List.map serialize_msg (List.map (ChordSemantics.send h) l)))) =
List.map e_send (List.map serialize_msg (List.map (ChordSemantics.send h) l)).
Proof.
induction l.
- reflexivity.
- intros.
simpl. repeat break_let.
unfold revert_msg, revert_payload.
rewrite serialize_deserialize_top_id.
rewrite IHl.
reflexivity.
Qed.
Lemma revert_serialize_start_handler_msgs : forall h k d l0 l,
start_handler h (k :: nil) = (d, l0, l) ->
List.map serialize_msg (List.map revert_msg (List.map (send h) l0))
= List.map (send h) l0.
Proof.
unfold start_handler.
intros. repeat break_let.
find_inversion.
rewrite map_send_serialize.
rewrite serialize_revert_msgs.
reflexivity.
Qed.
Lemma revert_serialize_start_handler_events : forall h k d l0 l,
start_handler h (k :: nil) = (d, l0, l) ->
List.map serialize_event
(List.map revert_event (List.map e_send (List.map (send h) l0))) =
List.map e_send (List.map (send h) l0).
Proof.
unfold start_handler.
intros. repeat break_let.
find_inversion.
rewrite map_send_serialize.
rewrite serialize_send_revert_serialize.
reflexivity.
Qed.
Lemma revert_serialize_timeout_handler : forall h st t st' ms newts clearedts,
timeout_handler h st t = (st', ms, newts, clearedts) ->
List.map serialize_msg (List.map revert_msg (List.map (send h) ms)) = List.map (send h) ms.
Proof.
unfold timeout_handler, serialize_res.
intros.
repeat break_let.
find_inversion.
rewrite map_send_serialize.
rewrite serialize_revert_msgs.
reflexivity.
Qed.
Lemma revert_serialize_recv_handler : forall a0 a1 d p st ms newts clearedts,
recv_handler a0 a1 d p = (st, ms, newts, clearedts) ->
List.map serialize_msg (List.map revert_msg (List.map (send a1) ms)) = List.map (send a1) ms.
Proof.
unfold recv_handler, serialize_res.
intros.
repeat break_let.
find_inversion.
rewrite map_send_serialize.
rewrite serialize_revert_msgs.
reflexivity.
Qed.
Lemma revert_serialize_msgs_l_aux : forall xs m ys,
List.map serialize_msg (List.map revert_msg (xs ++ m :: ys)) = xs ++ m :: ys ->
List.map serialize_msg (List.map revert_msg xs) = xs.
Proof.
induction xs.
- reflexivity.
- intros. simpl.
rewrite (IHxs m ys); inversion H.
+ repeat find_rewrite.
reflexivity.
+ simpl in *.
repeat find_rewrite.
reflexivity.
Qed.
Lemma revert_serialize_msgs_mid_aux : forall xs m ys,
List.map serialize_msg (List.map revert_msg (xs ++ m :: ys)) = xs ++ m :: ys ->
serialize_msg (revert_msg m) = m.
Proof.
induction xs.
- simpl. intros.
inversion H.
repeat find_rewrite.
reflexivity.
- intros. simpl.
rewrite (IHxs m ys); inversion H.
+ repeat find_rewrite.
reflexivity.
+ simpl in *.
repeat find_rewrite.
reflexivity.
Qed.
Lemma revert_serialize_msgs_r_aux : forall xs m ys,
List.map serialize_msg (List.map revert_msg (xs ++ m :: ys)) = xs ++ m :: ys ->
List.map serialize_msg (List.map revert_msg ys) = ys.
Proof.
induction xs.
- simpl. intros.
inversion H.
repeat find_rewrite.
reflexivity.
- intros. simpl.
rewrite (IHxs m ys); inversion H.
+ repeat find_rewrite.
reflexivity.
+ simpl in *.
repeat find_rewrite.
reflexivity.
Qed.
Lemma revert_serialize_msgs_l : forall gst xs m ys,
serialize_global_state (revert_global_state gst) = gst ->
msgs gst = xs ++ m :: ys ->
List.map serialize_msg (List.map revert_msg xs) = xs.
Proof.
unfold serialize_global_state, revert_global_state. simpl in *.
intros.
destruct gst. simpl in *.
find_inversion.
erewrite revert_serialize_msgs_l_aux; eauto.
Qed.
Lemma revert_serialize_msgs_mid : forall gst xs m ys,
serialize_global_state (revert_global_state gst) = gst ->
msgs gst = xs ++ m :: ys ->
serialize_msg (revert_msg m) = m.
Proof.
unfold serialize_global_state, revert_global_state. simpl in *.
intros.
destruct gst. simpl in *.
find_inversion.
erewrite revert_serialize_msgs_mid_aux; eauto.
Qed.
Lemma revert_serialize_msgs_r : forall gst xs m ys,
serialize_global_state (revert_global_state gst) = gst ->
msgs gst = xs ++ m :: ys ->
List.map serialize_msg (List.map revert_msg ys) = ys.
Proof.
unfold serialize_global_state, revert_global_state. simpl in *.
intros.
destruct gst. simpl in *.
find_inversion.
erewrite revert_serialize_msgs_r_aux; eauto.
Qed.
Lemma reachable_revert_serialize_global_state : forall gst,
reachable_st_serialized gst ->
serialize_global_state (revert_global_state gst) = gst.
Proof.
intros.
induction H.
- unfold initial_st in H.
intuition.
unfold serialize_global_state, revert_global_state.
destruct gst. simpl in *.
do 2 find_apply_lem_hyp map_eq_nil.
subst_max.
reflexivity.
- inv_prop step_dynamic;
subst_max.
+ unfold update_for_start. repeat break_let.
unfold serialize_global_state, revert_global_state. simpl.
repeat rewrite map_app.
erewrite revert_serialize_start_handler_msgs;
eauto.
erewrite revert_serialize_start_handler_events;
eauto.
rewrite revert_serialize_msgs; try assumption.
rewrite revert_serialize_trace; try assumption.
reflexivity.
+ unfold fail_node.
unfold serialize_global_state, revert_global_state. simpl.
rewrite revert_serialize_msgs; try assumption.
rewrite revert_serialize_trace; try assumption.
reflexivity.
+ unfold apply_handler_result, serialize_global_state, revert_global_state.
simpl.
repeat rewrite map_app.
erewrite revert_serialize_timeout_handler;
eauto.
rewrite revert_serialize_msgs; try assumption.
rewrite revert_serialize_trace; try assumption.
reflexivity.
+ unfold apply_handler_result, serialize_global_state, revert_global_state.
simpl.
repeat rewrite map_app.
rewrite (revert_serialize_msgs_l gst xs m ys) at 1; try assumption.
rewrite (revert_serialize_msgs_r gst xs m ys) at 1; try assumption.
erewrite revert_serialize_trace; eauto.
simpl.
erewrite revert_serialize_msgs_mid; eauto.
destruct m. destruct p. simpl in *.
erewrite revert_serialize_recv_handler; eauto.
+ unfold update_msgs_and_trace, serialize_global_state, revert_global_state.
simpl.
repeat rewrite map_app.
erewrite revert_serialize_msgs; eauto.
erewrite revert_serialize_trace; eauto.
simpl.
unfold client_payload in *. break_exists. intuition.
unfold revert_payload.
match goal with
| H : serialize_top _ = _ |- _ => rewrite <- H
end.
rewrite serialize_deserialize_top_id.
reflexivity.
+ unfold update_msgs_and_trace, serialize_global_state, revert_global_state.
simpl.
repeat rewrite map_app. simpl.
erewrite revert_serialize_msgs_l; eauto.
erewrite revert_serialize_msgs_mid; eauto.
erewrite revert_serialize_msgs_r; eauto.
erewrite revert_serialize_trace; eauto.
Qed.
Lemma revert_serialize_exteq : forall ex,
reachable_st_serialized (occ_gst (infseq.hd ex)) ->
lb_execution ex ->
exteq (map serialize_occurrence (map revert_occurrence ex)) ex.
Proof.
cofix.
intros.
destruct ex. do 2 rewrite map_Cons.
unfold serialize_occurrence, revert_occurrence. simpl.
erewrite reachable_revert_serialize_global_state; eauto.
destruct o.
constructor.
apply revert_serialize_exteq.
- destruct ex. simpl in *.
inv_prop lb_execution.
eapply reachableStepS; eauto.
eapply labeled_step_is_unlabeled_step; eauto.
- eapply lb_execution_invar; eauto.
Qed.
Lemma reachable_enabled' : forall l o,
ChordSemantics.l_enabled l o -> l_enabled l (serialize_occurrence o).
Proof.
unfold ChordSemantics.l_enabled, ChordSemantics.enabled, l_enabled, enabled.
intros.
break_exists.
exists (serialize_global_state x).
apply labeled_step_serialized_labeled_step.
assumption.
Qed.
Lemma lb_execution_enabled : forall ex l,
reachable_st_serialized (occ_gst (infseq.hd ex)) ->
lb_execution ex ->
eventually (now (ChordSemantics.l_enabled l)) (map revert_occurrence ex) ->
eventually (now (l_enabled l)) ex.
Proof.
intros.
assert (G : extensional (eventually (now (l_enabled l)))).
{ apply extensional_eventually.
unfold extensional.
intros.
destruct s1, s2.
inv_prop exteq.
subst_max.
unfold now in *. repeat break_match.
assumption. }
unfold extensional in *.
apply (G (map serialize_occurrence (map revert_occurrence ex))).
- eapply revert_serialize_exteq; eauto.
- eapply eventually_map; eauto.
intros.
destruct s. simpl in *.
apply reachable_enabled'.
assumption.
Qed.
Lemma revert_always_eventually_enabled : forall ex l,
reachable_st_serialized (occ_gst (infseq.hd ex)) ->
lb_execution ex ->
always (eventually (now (ChordSemantics.l_enabled l))) (map revert_occurrence ex) ->
always (eventually (now (l_enabled l))) ex.
Proof.
cofix.
constructor.
- inv_prop always.
apply lb_execution_enabled; assumption.
- destruct ex. rewrite map_Cons in *.
apply revert_always_eventually_enabled.
+ simpl.
destruct ex.
simpl in *.
inv_prop lb_execution. simpl in *.
eapply reachableStepS; eauto.
* eapply labeled_step_is_unlabeled_step. eauto.
* eapply lb_execution_invar. eauto.
+ inv_prop always.
assumption.
Qed.
Lemma revert_strong_local_fairness : forall ex,
reachable_st_serialized (occ_gst (infseq.hd ex)) ->
lb_execution ex ->
strong_local_fairness ex ->
ChordSemantics.strong_local_fairness (map revert_occurrence ex).
Proof.
unfold strong_local_fairness, ChordSemantics.strong_local_fairness.
intros.
assert (inf_occurred l ex).
- match goal with
| H : context[inf_occurred] |- _ => apply H
end.
unfold inf_enabled, inf_often.
unfold ChordSemantics.inf_enabled, inf_often in *.
apply revert_always_eventually_enabled;
assumption.
- unfold ChordSemantics.inf_occurred, inf_often.
unfold inf_occurred, inf_often in *.
eapply always_map; eauto.
intros.
eapply eventually_map; eauto.
unfold occurred, ChordSemantics.occurred.
destruct s0. rewrite map_Cons.
tauto.
Qed.
(* top-level correctness property *)
Theorem chord_serialized_stabilization :
forall ex : infseq.infseq occurrence,
reachable_st_serialized (occ_gst (infseq.hd ex)) ->
lb_execution ex ->
strong_local_fairness ex ->
always (~_ (now circular_wait)) ex ->
continuously (now (fun o => ideal (occ_gst o))) ex.
Proof.
intros.
match goal with
| _ : _ |- continuously ?P _ =>
assert (G : extensional (continuously P)) by (exact ideal_extensional)
end.
unfold extensional in G.
apply (G (map serialize_occurrence (map revert_occurrence ex))).
- eapply revert_serialize_exteq; eauto.
- apply serialize_continuously_ideal.
apply ChordStabilization.chord_stabilization.
+ apply revert_reachable.
assumption.
+ apply revert_lb_execution.
assumption.
+ apply revert_strong_local_fairness;
assumption.
+ apply revert_circular_wait. assumption.
Qed.
*) |
// MBT 7/7/2016
//
// 1 read-port, 1 write-port ram
//
// reads are synchronous
//
// although we could merge this with normal bsg_mem_1r1w
// and select with a parameter, we do not do this because
// it's typically a very big change to the instantiating code
// to move to/from sync/async, and we want to reflect this.
//
`include "bsg_defines.v"
module bsg_mem_1r1w_sync #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=0
, parameter disable_collision_warning_p=0
, parameter enable_clock_gating_p=0
)
(input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i
// currently unused
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r_data_o
);
wire clk_lo;
if (enable_clock_gating_p)
begin
bsg_clkgate_optional icg
(.clk_i( clk_i )
,.en_i( w_v_i | r_v_i )
,.bypass_i( 1'b0 )
,.gated_clock_o( clk_lo )
);
end
else
begin
assign clk_lo = clk_i;
end
bsg_mem_1r1w_sync_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
,.harden_p(harden_p)
) synth
(.clk_i( clk_lo )
,.reset_i
,.w_v_i
,.w_addr_i
,.w_data_i
,.r_v_i
,.r_addr_i
,.r_data_o
);
//synopsys translate_off
initial
begin
// we warn if els_p >= 16 because it is a good candidate for hardening
// and we warn for width_p >= 128 because this starts to add up to some real memory
if ((els_p >= 16) || (width_p >= 128) || (width_p*els_p > 256))
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p,harden_p);
if (disable_collision_warning_p)
$display("## %L: disable_collision_warning_p is set; you should not have this on unless you have broken code. fix it!\n");
end
always_ff @(posedge clk_lo)
if (w_v_i)
begin
assert ((reset_i === 'X) || (reset_i === 1'b1) || (w_addr_i < els_p))
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert ((reset_i === 'X) || (reset_i === 1'b1) || ~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p && !disable_collision_warning_p))
else
begin
$error("X'ing matched read address %x (%m)",r_addr_i);
end
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_sync)
|
// hps_design.v
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module hps_design (
input wire clk_clk, // clk.clk
output wire [14:0] hps_ddr_mem_a, // hps_ddr.mem_a
output wire [2:0] hps_ddr_mem_ba, // .mem_ba
output wire hps_ddr_mem_ck, // .mem_ck
output wire hps_ddr_mem_ck_n, // .mem_ck_n
output wire hps_ddr_mem_cke, // .mem_cke
output wire hps_ddr_mem_cs_n, // .mem_cs_n
output wire hps_ddr_mem_ras_n, // .mem_ras_n
output wire hps_ddr_mem_cas_n, // .mem_cas_n
output wire hps_ddr_mem_we_n, // .mem_we_n
output wire hps_ddr_mem_reset_n, // .mem_reset_n
inout wire [31:0] hps_ddr_mem_dq, // .mem_dq
inout wire [3:0] hps_ddr_mem_dqs, // .mem_dqs
inout wire [3:0] hps_ddr_mem_dqs_n, // .mem_dqs_n
output wire hps_ddr_mem_odt, // .mem_odt
output wire [3:0] hps_ddr_mem_dm, // .mem_dm
input wire hps_ddr_oct_rzqin, // .oct_rzqin
inout wire hps_io_hps_io_gpio_inst_GPIO09, // hps_io.hps_io_gpio_inst_GPIO09
inout wire hps_io_hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_io_hps_io_gpio_inst_GPIO48, // .hps_io_gpio_inst_GPIO48
inout wire hps_io_hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_hps_io_gpio_inst_GPIO61, // .hps_io_gpio_inst_GPIO61
output wire ledr_export, // ledr.export
output wire pll_0_sdram_clk, // pll_0_sdram.clk
input wire reset_reset_n // reset.reset_n
);
wire pll_0_outclk0_clk; // pll_0:outclk_0 -> [mm_interconnect_0:pll_0_outclk0_clk, pio_0:clk, rst_controller:clk, rst_controller_001:clk, smp_hps:h2f_lw_axi_clk]
wire [1:0] smp_hps_h2f_lw_axi_master_awburst; // smp_hps:h2f_lw_AWBURST -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_awburst
wire [3:0] smp_hps_h2f_lw_axi_master_arlen; // smp_hps:h2f_lw_ARLEN -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_arlen
wire [3:0] smp_hps_h2f_lw_axi_master_wstrb; // smp_hps:h2f_lw_WSTRB -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_wstrb
wire smp_hps_h2f_lw_axi_master_wready; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_wready -> smp_hps:h2f_lw_WREADY
wire [11:0] smp_hps_h2f_lw_axi_master_rid; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_rid -> smp_hps:h2f_lw_RID
wire smp_hps_h2f_lw_axi_master_rready; // smp_hps:h2f_lw_RREADY -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_rready
wire [3:0] smp_hps_h2f_lw_axi_master_awlen; // smp_hps:h2f_lw_AWLEN -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_awlen
wire [11:0] smp_hps_h2f_lw_axi_master_wid; // smp_hps:h2f_lw_WID -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_wid
wire [3:0] smp_hps_h2f_lw_axi_master_arcache; // smp_hps:h2f_lw_ARCACHE -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_arcache
wire smp_hps_h2f_lw_axi_master_wvalid; // smp_hps:h2f_lw_WVALID -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_wvalid
wire [20:0] smp_hps_h2f_lw_axi_master_araddr; // smp_hps:h2f_lw_ARADDR -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_araddr
wire [2:0] smp_hps_h2f_lw_axi_master_arprot; // smp_hps:h2f_lw_ARPROT -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_arprot
wire [2:0] smp_hps_h2f_lw_axi_master_awprot; // smp_hps:h2f_lw_AWPROT -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_awprot
wire [31:0] smp_hps_h2f_lw_axi_master_wdata; // smp_hps:h2f_lw_WDATA -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_wdata
wire smp_hps_h2f_lw_axi_master_arvalid; // smp_hps:h2f_lw_ARVALID -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_arvalid
wire [3:0] smp_hps_h2f_lw_axi_master_awcache; // smp_hps:h2f_lw_AWCACHE -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_awcache
wire [11:0] smp_hps_h2f_lw_axi_master_arid; // smp_hps:h2f_lw_ARID -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_arid
wire [1:0] smp_hps_h2f_lw_axi_master_arlock; // smp_hps:h2f_lw_ARLOCK -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_arlock
wire [1:0] smp_hps_h2f_lw_axi_master_awlock; // smp_hps:h2f_lw_AWLOCK -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_awlock
wire [20:0] smp_hps_h2f_lw_axi_master_awaddr; // smp_hps:h2f_lw_AWADDR -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_awaddr
wire [1:0] smp_hps_h2f_lw_axi_master_bresp; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_bresp -> smp_hps:h2f_lw_BRESP
wire smp_hps_h2f_lw_axi_master_arready; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_arready -> smp_hps:h2f_lw_ARREADY
wire [31:0] smp_hps_h2f_lw_axi_master_rdata; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_rdata -> smp_hps:h2f_lw_RDATA
wire smp_hps_h2f_lw_axi_master_awready; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_awready -> smp_hps:h2f_lw_AWREADY
wire [1:0] smp_hps_h2f_lw_axi_master_arburst; // smp_hps:h2f_lw_ARBURST -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_arburst
wire [2:0] smp_hps_h2f_lw_axi_master_arsize; // smp_hps:h2f_lw_ARSIZE -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_arsize
wire smp_hps_h2f_lw_axi_master_bready; // smp_hps:h2f_lw_BREADY -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_bready
wire smp_hps_h2f_lw_axi_master_rlast; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_rlast -> smp_hps:h2f_lw_RLAST
wire smp_hps_h2f_lw_axi_master_wlast; // smp_hps:h2f_lw_WLAST -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_wlast
wire [1:0] smp_hps_h2f_lw_axi_master_rresp; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_rresp -> smp_hps:h2f_lw_RRESP
wire [11:0] smp_hps_h2f_lw_axi_master_awid; // smp_hps:h2f_lw_AWID -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_awid
wire [11:0] smp_hps_h2f_lw_axi_master_bid; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_bid -> smp_hps:h2f_lw_BID
wire smp_hps_h2f_lw_axi_master_bvalid; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_bvalid -> smp_hps:h2f_lw_BVALID
wire [2:0] smp_hps_h2f_lw_axi_master_awsize; // smp_hps:h2f_lw_AWSIZE -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_awsize
wire smp_hps_h2f_lw_axi_master_awvalid; // smp_hps:h2f_lw_AWVALID -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_awvalid
wire smp_hps_h2f_lw_axi_master_rvalid; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_rvalid -> smp_hps:h2f_lw_RVALID
wire mm_interconnect_0_pio_0_s1_chipselect; // mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
wire [31:0] mm_interconnect_0_pio_0_s1_readdata; // pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
wire [1:0] mm_interconnect_0_pio_0_s1_address; // mm_interconnect_0:pio_0_s1_address -> pio_0:address
wire mm_interconnect_0_pio_0_s1_write; // mm_interconnect_0:pio_0_s1_write -> pio_0:write_n
wire [31:0] mm_interconnect_0_pio_0_s1_writedata; // mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [mm_interconnect_0:pio_0_reset_reset_bridge_in_reset_reset, pio_0:reset_n]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset
wire smp_hps_h2f_reset_reset; // smp_hps:h2f_rst_n -> rst_controller_001:reset_in0
hps_design_pio_0 pio_0 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_pio_0_s1_address), // s1.address
.write_n (~mm_interconnect_0_pio_0_s1_write), // .write_n
.writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_pio_0_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.out_port (ledr_export) // external_connection.export
);
hps_design_pll_0 pll_0 (
.refclk (clk_clk), // refclk.clk
.rst (~reset_reset_n), // reset.reset
.outclk_0 (pll_0_outclk0_clk), // outclk0.clk
.outclk_1 (), // outclk1.clk
.outclk_2 (pll_0_sdram_clk), // outclk2.clk
.locked () // (terminated)
);
hps_design_smp_hps #(
.F2S_Width (0),
.S2F_Width (0)
) smp_hps (
.mem_a (hps_ddr_mem_a), // memory.mem_a
.mem_ba (hps_ddr_mem_ba), // .mem_ba
.mem_ck (hps_ddr_mem_ck), // .mem_ck
.mem_ck_n (hps_ddr_mem_ck_n), // .mem_ck_n
.mem_cke (hps_ddr_mem_cke), // .mem_cke
.mem_cs_n (hps_ddr_mem_cs_n), // .mem_cs_n
.mem_ras_n (hps_ddr_mem_ras_n), // .mem_ras_n
.mem_cas_n (hps_ddr_mem_cas_n), // .mem_cas_n
.mem_we_n (hps_ddr_mem_we_n), // .mem_we_n
.mem_reset_n (hps_ddr_mem_reset_n), // .mem_reset_n
.mem_dq (hps_ddr_mem_dq), // .mem_dq
.mem_dqs (hps_ddr_mem_dqs), // .mem_dqs
.mem_dqs_n (hps_ddr_mem_dqs_n), // .mem_dqs_n
.mem_odt (hps_ddr_mem_odt), // .mem_odt
.mem_dm (hps_ddr_mem_dm), // .mem_dm
.oct_rzqin (hps_ddr_oct_rzqin), // .oct_rzqin
.hps_io_gpio_inst_GPIO09 (hps_io_hps_io_gpio_inst_GPIO09), // hps_io.hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_io_hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO48 (hps_io_hps_io_gpio_inst_GPIO48), // .hps_io_gpio_inst_GPIO48
.hps_io_gpio_inst_GPIO53 (hps_io_hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_io_hps_io_gpio_inst_GPIO61), // .hps_io_gpio_inst_GPIO61
.h2f_rst_n (smp_hps_h2f_reset_reset), // h2f_reset.reset_n
.h2f_lw_axi_clk (pll_0_outclk0_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (smp_hps_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (smp_hps_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (smp_hps_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (smp_hps_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (smp_hps_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (smp_hps_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (smp_hps_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (smp_hps_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (smp_hps_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (smp_hps_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (smp_hps_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (smp_hps_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (smp_hps_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (smp_hps_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (smp_hps_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (smp_hps_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (smp_hps_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (smp_hps_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (smp_hps_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (smp_hps_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (smp_hps_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (smp_hps_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (smp_hps_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (smp_hps_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (smp_hps_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (smp_hps_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (smp_hps_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (smp_hps_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (smp_hps_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (smp_hps_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (smp_hps_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (smp_hps_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (smp_hps_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (smp_hps_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (smp_hps_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (smp_hps_h2f_lw_axi_master_rready) // .rready
);
hps_design_mm_interconnect_0 mm_interconnect_0 (
.smp_hps_h2f_lw_axi_master_awid (smp_hps_h2f_lw_axi_master_awid), // smp_hps_h2f_lw_axi_master.awid
.smp_hps_h2f_lw_axi_master_awaddr (smp_hps_h2f_lw_axi_master_awaddr), // .awaddr
.smp_hps_h2f_lw_axi_master_awlen (smp_hps_h2f_lw_axi_master_awlen), // .awlen
.smp_hps_h2f_lw_axi_master_awsize (smp_hps_h2f_lw_axi_master_awsize), // .awsize
.smp_hps_h2f_lw_axi_master_awburst (smp_hps_h2f_lw_axi_master_awburst), // .awburst
.smp_hps_h2f_lw_axi_master_awlock (smp_hps_h2f_lw_axi_master_awlock), // .awlock
.smp_hps_h2f_lw_axi_master_awcache (smp_hps_h2f_lw_axi_master_awcache), // .awcache
.smp_hps_h2f_lw_axi_master_awprot (smp_hps_h2f_lw_axi_master_awprot), // .awprot
.smp_hps_h2f_lw_axi_master_awvalid (smp_hps_h2f_lw_axi_master_awvalid), // .awvalid
.smp_hps_h2f_lw_axi_master_awready (smp_hps_h2f_lw_axi_master_awready), // .awready
.smp_hps_h2f_lw_axi_master_wid (smp_hps_h2f_lw_axi_master_wid), // .wid
.smp_hps_h2f_lw_axi_master_wdata (smp_hps_h2f_lw_axi_master_wdata), // .wdata
.smp_hps_h2f_lw_axi_master_wstrb (smp_hps_h2f_lw_axi_master_wstrb), // .wstrb
.smp_hps_h2f_lw_axi_master_wlast (smp_hps_h2f_lw_axi_master_wlast), // .wlast
.smp_hps_h2f_lw_axi_master_wvalid (smp_hps_h2f_lw_axi_master_wvalid), // .wvalid
.smp_hps_h2f_lw_axi_master_wready (smp_hps_h2f_lw_axi_master_wready), // .wready
.smp_hps_h2f_lw_axi_master_bid (smp_hps_h2f_lw_axi_master_bid), // .bid
.smp_hps_h2f_lw_axi_master_bresp (smp_hps_h2f_lw_axi_master_bresp), // .bresp
.smp_hps_h2f_lw_axi_master_bvalid (smp_hps_h2f_lw_axi_master_bvalid), // .bvalid
.smp_hps_h2f_lw_axi_master_bready (smp_hps_h2f_lw_axi_master_bready), // .bready
.smp_hps_h2f_lw_axi_master_arid (smp_hps_h2f_lw_axi_master_arid), // .arid
.smp_hps_h2f_lw_axi_master_araddr (smp_hps_h2f_lw_axi_master_araddr), // .araddr
.smp_hps_h2f_lw_axi_master_arlen (smp_hps_h2f_lw_axi_master_arlen), // .arlen
.smp_hps_h2f_lw_axi_master_arsize (smp_hps_h2f_lw_axi_master_arsize), // .arsize
.smp_hps_h2f_lw_axi_master_arburst (smp_hps_h2f_lw_axi_master_arburst), // .arburst
.smp_hps_h2f_lw_axi_master_arlock (smp_hps_h2f_lw_axi_master_arlock), // .arlock
.smp_hps_h2f_lw_axi_master_arcache (smp_hps_h2f_lw_axi_master_arcache), // .arcache
.smp_hps_h2f_lw_axi_master_arprot (smp_hps_h2f_lw_axi_master_arprot), // .arprot
.smp_hps_h2f_lw_axi_master_arvalid (smp_hps_h2f_lw_axi_master_arvalid), // .arvalid
.smp_hps_h2f_lw_axi_master_arready (smp_hps_h2f_lw_axi_master_arready), // .arready
.smp_hps_h2f_lw_axi_master_rid (smp_hps_h2f_lw_axi_master_rid), // .rid
.smp_hps_h2f_lw_axi_master_rdata (smp_hps_h2f_lw_axi_master_rdata), // .rdata
.smp_hps_h2f_lw_axi_master_rresp (smp_hps_h2f_lw_axi_master_rresp), // .rresp
.smp_hps_h2f_lw_axi_master_rlast (smp_hps_h2f_lw_axi_master_rlast), // .rlast
.smp_hps_h2f_lw_axi_master_rvalid (smp_hps_h2f_lw_axi_master_rvalid), // .rvalid
.smp_hps_h2f_lw_axi_master_rready (smp_hps_h2f_lw_axi_master_rready), // .rready
.pll_0_outclk0_clk (pll_0_outclk0_clk), // pll_0_outclk0.clk
.pio_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // pio_0_reset_reset_bridge_in_reset.reset
.smp_hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // smp_hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.pio_0_s1_address (mm_interconnect_0_pio_0_s1_address), // pio_0_s1.address
.pio_0_s1_write (mm_interconnect_0_pio_0_s1_write), // .write
.pio_0_s1_readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.pio_0_s1_writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.pio_0_s1_chipselect (mm_interconnect_0_pio_0_s1_chipselect) // .chipselect
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (pll_0_outclk0_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~smp_hps_h2f_reset_reset), // reset_in0.reset
.clk (pll_0_outclk0_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_mul_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// Multiply pipeline synthesizable logic
// - special input cases
// - opcode pipeline
// - sign logic
// - exception logic
// - datapath control- select lines and control logic
//
///////////////////////////////////////////////////////////////////////////////
module fpu_mul_ctl (
inq_in1_51,
inq_in1_54,
inq_in1_53_0_neq_0,
inq_in1_50_0_neq_0,
inq_in1_53_32_neq_0,
inq_in1_exp_eq_0,
inq_in1_exp_neq_ffs,
inq_in2_51,
inq_in2_54,
inq_in2_53_0_neq_0,
inq_in2_50_0_neq_0,
inq_in2_53_32_neq_0,
inq_in2_exp_eq_0,
inq_in2_exp_neq_ffs,
inq_op,
inq_mul,
inq_rnd_mode,
inq_id,
inq_in1_63,
inq_in2_63,
mul_dest_rdy,
mul_dest_rdya,
m5stg_exp,
m5stg_fracadd_cout,
m5stg_frac_neq_0,
m5stg_frac_dbl_nx,
m5stg_frac_sng_nx,
m1stg_ld0_1,
m1stg_ld0_2,
m3stg_exp,
m3stg_expadd_eq_0,
m3stg_expadd_lte_0_inv,
m3stg_ld0_inv,
m4stg_exp,
m4stg_frac_105,
m5stg_frac,
arst_l,
grst_l,
rclk,
mul_pipe_active,
m1stg_snan_sng_in1,
m1stg_snan_dbl_in1,
m1stg_snan_sng_in2,
m1stg_snan_dbl_in2,
m1stg_step,
m1stg_sngop,
m1stg_dblop,
m1stg_dblop_inv,
m1stg_fmul,
m1stg_fsmuld,
m2stg_fmuls,
m2stg_fmuld,
m2stg_fsmuld,
m5stg_fmuls,
m5stg_fmuld,
m5stg_fmulda,
m6stg_fmul_in,
m6stg_id_in,
m6stg_fmul_dbl_dst,
m6stg_fmuls,
m6stg_step,
mul_sign_out,
m5stg_in_of,
mul_exc_out,
m2stg_frac1_dbl_norm,
m2stg_frac1_dbl_dnrm,
m2stg_frac1_sng_norm,
m2stg_frac1_sng_dnrm,
m2stg_frac1_inf,
m2stg_frac2_dbl_norm,
m2stg_frac2_dbl_dnrm,
m2stg_frac2_sng_norm,
m2stg_frac2_sng_dnrm,
m2stg_frac2_inf,
m1stg_inf_zero_in,
m1stg_inf_zero_in_dbl,
m2stg_exp_expadd,
m2stg_exp_0bff,
m2stg_exp_017f,
m2stg_exp_04ff,
m2stg_exp_zero,
m3bstg_ld0_inv,
m4stg_sh_cnt_in,
m4stg_inc_exp_54,
m4stg_inc_exp_55,
m4stg_inc_exp_105,
m4stg_left_shift_step,
m4stg_right_shift_step,
m5stg_to_0,
m5stg_to_0_inv,
mul_frac_out_fracadd,
mul_frac_out_frac,
mul_exp_out_exp_plus1,
mul_exp_out_exp,
mula_rst_l,
se,
si,
so
);
parameter
FMULS= 8'h49,
FMULD= 8'h4a,
FSMULD= 8'h69;
input inq_in1_51; // request operand 1[51]
input inq_in1_54; // request operand 1[54]
input inq_in1_53_0_neq_0; // request operand 1[53:0]!=0
input inq_in1_50_0_neq_0; // request operand 1[50:0]!=0
input inq_in1_53_32_neq_0; // request operand 1[53:32]!=0
input inq_in1_exp_eq_0; // request operand 1[62:52]==0
input inq_in1_exp_neq_ffs; // request operand 1[62:52]!=0x7ff
input inq_in2_51; // request operand 2[51]
input inq_in2_54; // request operand 2[54]
input inq_in2_53_0_neq_0; // request operand 2[53:0]!=0
input inq_in2_50_0_neq_0; // request operand 2[50:0]!=0
input inq_in2_53_32_neq_0; // request operand 2[53:32]!=0
input inq_in2_exp_eq_0; // request operand 2[62:52]==0
input inq_in2_exp_neq_ffs; // request operand 2[62:52]!=0x7ff
input [7:0] inq_op; // request opcode to op pipes
input inq_mul; // multiply pipe request
input [1:0] inq_rnd_mode; // request rounding mode to op pipes
input [4:0] inq_id; // request ID to the operation pipes
input inq_in1_63; // request[63] operand 1 to op pipes
input inq_in2_63; // request[63] operand 2 to op pipes
input mul_dest_rdy; // multiply result req accepted for CPX
input mul_dest_rdya; // multiply result req accepted for CPX
input [12:0] m5stg_exp; // exponent input- multiply 5 stage
input m5stg_fracadd_cout; // fraction rounding adder carry out
input m5stg_frac_neq_0; // fraction input to mul 5 stage != 0
input m5stg_frac_dbl_nx; // double precision inexact result
input m5stg_frac_sng_nx; // single precision inexact result
input [5:0] m1stg_ld0_1; // denorm operand 1 leading 0's
input [5:0] m1stg_ld0_2; // denorm operand 2 leading 0's
input [12:0] m3stg_exp; // exponent input- multiply 3 stage
input m3stg_expadd_eq_0; // mul stage 3 exponent adder sum == 0
input m3stg_expadd_lte_0_inv; // mul stage 3 exponent adder sum <= 0
input [5:0] m3stg_ld0_inv; // leading 0's in multiply operands
input [12:0] m4stg_exp; // exponent input- multiply 4 stage
input m4stg_frac_105; // multiply stage 4a fraction input[105]
input [32:0] m5stg_frac; // multiply stage 5 fraction input
input arst_l; // asynchronous global reset- asserted low
input grst_l; // synchronous global reset- asserted low
input rclk; // global clock
output mul_pipe_active; // mul pipe is executing a valid instr
output m1stg_snan_sng_in1; // operand 1 is single signalling NaN
output m1stg_snan_dbl_in1; // operand 1 is double signalling NaN
output m1stg_snan_sng_in2; // operand 2 is single signalling NaN
output m1stg_snan_dbl_in2; // operand 2 is double signalling NaN
output m1stg_step; // multiply pipe load
output m1stg_sngop; // single precision operation- mul 1 stg
output m1stg_dblop; // double precision operation- mul 1 stg
output m1stg_dblop_inv; // single or int operation- mul 1 stg
output m1stg_fmul; // multiply operation- mul 1 stage
output m1stg_fsmuld; // fsmuld- multiply 1 stage
output m2stg_fmuls; // fmuls- multiply 2 stage
output m2stg_fmuld; // fmuld- multiply 2 stage
output m2stg_fsmuld; // fsmuld- multiply 2 stage
output m5stg_fmuls; // fmuls- multiply 5 stage
output m5stg_fmuld; // fmuld- multiply 5 stage
output m5stg_fmulda; // fmuld- multiply 5 stage copy
output m6stg_fmul_in; // mul pipe output request next cycle
output [9:0] m6stg_id_in; // mul pipe output ID next cycle
output m6stg_fmul_dbl_dst; // double precision multiply result
output m6stg_fmuls; // fmuls- multiply 6 stage
output m6stg_step; // advance the multiply pipe
output mul_sign_out; // multiply sign output
output m5stg_in_of; // multiply overflow- select exp out
output [4:0] mul_exc_out; // multiply pipe result- exception flags
output m2stg_frac1_dbl_norm; // select line to m2stg_frac1
output m2stg_frac1_dbl_dnrm; // select line to m2stg_frac1
output m2stg_frac1_sng_norm; // select line to m2stg_frac1
output m2stg_frac1_sng_dnrm; // select line to m2stg_frac1
output m2stg_frac1_inf; // select line to m2stg_frac1
output m2stg_frac2_dbl_norm; // select line to m2stg_frac2
output m2stg_frac2_dbl_dnrm; // select line to m2stg_frac2
output m2stg_frac2_sng_norm; // select line to m2stg_frac2
output m2stg_frac2_sng_dnrm; // select line to m2stg_frac2
output m2stg_frac2_inf; // select line to m2stg_frac2
output m1stg_inf_zero_in; // 1 operand is infinity; other is 0
output m1stg_inf_zero_in_dbl; // 1 opnd is infinity; other is 0- dbl
output m2stg_exp_expadd; // select line to m2stg_exp
output m2stg_exp_0bff; // select line to m2stg_exp
output m2stg_exp_017f; // select line to m2stg_exp
output m2stg_exp_04ff; // select line to m2stg_exp
output m2stg_exp_zero; // select line to m2stg_exp
output [6:0] m3bstg_ld0_inv; // leading 0's in multiply operands
output [5:0] m4stg_sh_cnt_in; // multiply normalization shift count
output m4stg_inc_exp_54; // select line to m5stg_exp
output m4stg_inc_exp_55; // select line to m5stg_exp
output m4stg_inc_exp_105; // select line to m5stg_exp
output m4stg_left_shift_step; // select line to m5stg_frac
output m4stg_right_shift_step; // select line to m5stg_frac
output m5stg_to_0; // result to max finite on overflow
output m5stg_to_0_inv; // result to infinity on overflow
output mul_frac_out_fracadd; // select line to mul_frac_out
output mul_frac_out_frac; // select line to mul_frac_out
output mul_exp_out_exp_plus1; // select line to mul_exp_out
output mul_exp_out_exp; // select line to mul_exp_out
output mula_rst_l; // reset for mul64
input se; // scan_enable
input si; // scan in
output so; // scan out
wire reset;
wire mul_frac_in1_51;
wire mul_frac_in1_54;
wire mul_frac_in1_53_0_neq_0;
wire mul_frac_in1_50_0_neq_0;
wire mul_frac_in1_53_32_neq_0;
wire mul_exp_in1_exp_eq_0;
wire mul_exp_in1_exp_neq_ffs;
wire mul_frac_in2_51;
wire mul_frac_in2_54;
wire mul_frac_in2_53_0_neq_0;
wire mul_frac_in2_50_0_neq_0;
wire mul_frac_in2_53_32_neq_0;
wire mul_exp_in2_exp_eq_0;
wire mul_exp_in2_exp_neq_ffs;
wire m1stg_denorm_sng_in1;
wire m1stg_denorm_dbl_in1;
wire m1stg_denorm_sng_in2;
wire m1stg_denorm_dbl_in2;
wire m1stg_denorm_in1;
wire m1stg_denorm_in2;
wire m1stg_norm_sng_in1;
wire m1stg_norm_dbl_in1;
wire m1stg_norm_sng_in2;
wire m1stg_norm_dbl_in2;
wire m1stg_snan_sng_in1;
wire m1stg_snan_dbl_in1;
wire m1stg_snan_sng_in2;
wire m1stg_snan_dbl_in2;
wire m1stg_qnan_sng_in1;
wire m1stg_qnan_dbl_in1;
wire m1stg_qnan_sng_in2;
wire m1stg_qnan_dbl_in2;
wire m1stg_snan_in1;
wire m1stg_snan_in2;
wire m1stg_qnan_in1;
wire m1stg_qnan_in2;
wire m2stg_snan_in1;
wire m2stg_snan_in2;
wire m2stg_qnan_in1;
wire m2stg_qnan_in2;
wire m1stg_nan_sng_in1;
wire m1stg_nan_dbl_in1;
wire m1stg_nan_sng_in2;
wire m1stg_nan_dbl_in2;
wire m1stg_nan_in1;
wire m1stg_nan_in2;
wire m2stg_nan_in2;
wire m1stg_inf_sng_in1;
wire m1stg_inf_dbl_in1;
wire m1stg_inf_sng_in2;
wire m1stg_inf_dbl_in2;
wire m1stg_inf_in1;
wire m1stg_inf_in2;
wire m1stg_inf_in;
wire m2stg_inf_in1;
wire m2stg_inf_in2;
wire m2stg_inf_in;
wire m1stg_infnan_sng_in1;
wire m1stg_infnan_dbl_in1;
wire m1stg_infnan_sng_in2;
wire m1stg_infnan_dbl_in2;
wire m1stg_infnan_in1;
wire m1stg_infnan_in2;
wire m1stg_infnan_in;
wire m1stg_zero_in1;
wire m1stg_zero_in2;
wire m1stg_zero_in;
wire m2stg_zero_in1;
wire m2stg_zero_in2;
wire m2stg_zero_in;
wire m1stg_step;
wire [7:0] m1stg_op_in;
wire [7:0] m1stg_op;
wire m1stg_mul_in;
wire m1stg_mul;
wire m1stg_sngop;
wire [3:0] m1stg_sngopa;
wire m1stg_dblop;
wire [3:0] m1stg_dblopa;
wire m1stg_dblop_inv_in;
wire m1stg_dblop_inv;
wire [1:0] m1stg_rnd_mode;
wire [4:0] m1stg_id;
wire m1stg_fmul;
wire m1stg_fmul_dbl_dst;
wire m1stg_fmuls;
wire m1stg_fmuld;
wire m1stg_fsmuld;
wire [4:0] m1stg_opdec;
wire [4:0] m2stg_opdec;
wire [1:0] m2stg_rnd_mode;
wire [4:0] m2stg_id;
wire m2stg_fmul;
wire m2stg_fmuls;
wire m2stg_fmuld;
wire m2stg_fsmuld;
wire [4:1] m3astg_opdec;
wire [1:0] m3astg_rnd_mode;
wire [4:0] m3astg_id;
wire [4:1] m3bstg_opdec;
wire [1:0] m3bstg_rnd_mode;
wire [4:0] m3bstg_id;
wire [4:1] m3stg_opdec;
wire [1:0] m3stg_rnd_mode;
wire [4:0] m3stg_id;
wire m3stg_fmul;
wire [4:1] m4stg_opdec;
wire [1:0] m4stg_rnd_mode;
wire [4:0] m4stg_id;
wire m4stg_fmul;
wire m4stg_fmuld;
wire [4:1] m5stg_opdec;
wire [1:0] m5stg_rnd_mode;
wire [4:0] m5stg_id;
wire m5stg_fmul;
wire m5stg_fmuls;
wire m5stg_fmuld;
wire m5stg_fmulda;
wire m6stg_fmul_in;
wire [4:2] m6stg_opdec;
wire [9:0] m6stg_id_in;
wire [9:0] m6stg_id;
wire m6stg_fmul;
wire m6stg_fmul_dbl_dst;
wire m6stg_fmuls;
wire m6stg_hold;
wire m6stg_holda;
wire m6stg_step;
wire m6stg_stepa;
wire m1stg_sign1;
wire m1stg_sign2;
wire m2stg_sign1;
wire m2stg_sign2;
wire m1stg_of_mask;
wire m2stg_of_mask;
wire m2stg_sign;
wire m3astg_sign;
wire m2stg_nv;
wire m3astg_nv;
wire m3astg_of_mask;
wire m3bstg_sign;
wire m3bstg_nv;
wire m3stg_sign;
wire m3stg_nv;
wire m3stg_of_mask;
wire m4stg_sign;
wire m4stg_nv;
wire m4stg_of_mask;
wire m5stg_sign;
wire m5stg_nv;
wire m5stg_of_mask;
wire mul_sign_out;
wire mul_nv_out;
wire m5stg_in_of;
wire mul_of_out_tmp1_in;
wire mul_of_out_tmp1;
wire mul_of_out_tmp2;
wire mul_of_out_cout;
wire mul_of_out;
wire mul_uf_out_in;
wire mul_uf_out;
wire mul_nx_out_in;
wire mul_nx_out;
wire [4:0] mul_exc_out;
wire m2stg_frac1_dbl_norm;
wire m2stg_frac1_dbl_dnrm;
wire m2stg_frac1_sng_norm;
wire m2stg_frac1_sng_dnrm;
wire m2stg_frac1_inf;
wire m2stg_frac2_dbl_norm;
wire m2stg_frac2_dbl_dnrm;
wire m2stg_frac2_sng_norm;
wire m2stg_frac2_sng_dnrm;
wire m2stg_frac2_inf;
wire m1stg_inf_zero_in;
wire m1stg_inf_zero_in_dbl;
wire [5:0] m2stg_ld0_1_in;
wire [5:0] m2stg_ld0_1;
wire [5:0] m2stg_ld0_2_in;
wire [5:0] m2stg_ld0_2;
wire m2stg_exp_expadd;
wire m2stg_exp_0bff;
wire m2stg_exp_017f;
wire m2stg_exp_04ff;
wire m2stg_exp_zero;
wire [6:0] m2stg_ld0;
wire [6:0] m2stg_ld0_inv;
wire [6:0] m3astg_ld0_inv;
wire [6:0] m3bstg_ld0_inv;
wire m4stg_expadd_eq_0;
wire m3stg_exp_lte_0;
wire m4stg_right_shift_in;
wire m4stg_right_shift;
wire [5:0] m3stg_exp_minus1;
wire [5:0] m3stg_exp_inv_plus2;
wire m3stg_exp_lt_neg57;
wire [5:0] m4stg_sh_cnt_in;
wire m4stg_left_shift_step;
wire m4stg_right_shift_step;
wire m4stg_inc_exp_54;
wire m4stg_inc_exp_55;
wire m4stg_inc_exp_105;
wire m5stg_rndup;
wire m5stg_to_0;
wire m5stg_to_0_inv;
wire mul_frac_out_fracadd;
wire mul_frac_out_frac;
wire mul_exp_out_exp_plus1;
wire mul_exp_out_exp;
wire mul_pipe_active_in;
wire mul_pipe_active;
wire mula_rst_l;
dffrl_async #(1) dffrl_mul_ctl (
.din (grst_l),
.clk (rclk),
.rst_l(arst_l),
.q (mul_ctl_rst_l),
.se (se),
.si (),
.so ()
);
assign reset= (!mul_ctl_rst_l);
// 3/14/03 reset signal for mul64
assign mula_rst_l = mul_ctl_rst_l;
///////////////////////////////////////////////////////////////////////////////
//
// Multiply pipeline special input cases.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_mul_frac_in1_51 (
.din (inq_in1_51),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in1_51),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_frac_in1_54 (
.din (inq_in1_54),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in1_54),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_frac_in1_53_0_neq_0 (
.din (inq_in1_53_0_neq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in1_53_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_frac_in1_50_0_neq_0 (
.din (inq_in1_50_0_neq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in1_50_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_frac_in1_53_32_neq_0 (
.din (inq_in1_53_32_neq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in1_53_32_neq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_exp_in1_exp_eq_0 (
.din (inq_in1_exp_eq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_exp_in1_exp_eq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_exp_in1_exp_neq_ffs (
.din (inq_in1_exp_neq_ffs),
.en (m6stg_step),
.clk (rclk),
.q (mul_exp_in1_exp_neq_ffs),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_frac_in2_51 (
.din (inq_in2_51),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in2_51),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_frac_in2_54 (
.din (inq_in2_54),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in2_54),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_frac_in2_53_0_neq_0 (
.din (inq_in2_53_0_neq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in2_53_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_frac_in2_50_0_neq_0 (
.din (inq_in2_50_0_neq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in2_50_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_frac_in2_53_32_neq_0 (
.din (inq_in2_53_32_neq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in2_53_32_neq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_exp_in2_exp_eq_0 (
.din (inq_in2_exp_eq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_exp_in2_exp_eq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_exp_in2_exp_neq_ffs (
.din (inq_in2_exp_neq_ffs),
.en (m6stg_step),
.clk (rclk),
.q (mul_exp_in2_exp_neq_ffs),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Denorm multiply inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_denorm_sng_in1= mul_exp_in1_exp_eq_0 && m1stg_sngopa[0];
assign m1stg_denorm_dbl_in1= mul_exp_in1_exp_eq_0 && m1stg_dblopa[0];
assign m1stg_denorm_sng_in2= mul_exp_in2_exp_eq_0 && m1stg_sngopa[0];
assign m1stg_denorm_dbl_in2= mul_exp_in2_exp_eq_0 && m1stg_dblopa[0];
assign m1stg_denorm_in1= m1stg_denorm_sng_in1 || m1stg_denorm_dbl_in1;
assign m1stg_denorm_in2= m1stg_denorm_sng_in2 || m1stg_denorm_dbl_in2;
///////////////////////////////////////////////////////////////////////////////
//
// Non-denorm multiply inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_norm_sng_in1= (!mul_exp_in1_exp_eq_0) && m1stg_sngopa[0];
assign m1stg_norm_dbl_in1= (!mul_exp_in1_exp_eq_0) && m1stg_dblopa[0];
assign m1stg_norm_sng_in2= (!mul_exp_in2_exp_eq_0) && m1stg_sngopa[0];
assign m1stg_norm_dbl_in2= (!mul_exp_in2_exp_eq_0) && m1stg_dblopa[0];
///////////////////////////////////////////////////////////////////////////////
//
// Nan multiply inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_snan_sng_in1= (!mul_exp_in1_exp_neq_ffs) && (!mul_frac_in1_54)
&& (mul_frac_in1_53_32_neq_0) && m1stg_sngopa[1];
assign m1stg_snan_dbl_in1= (!mul_exp_in1_exp_neq_ffs)
&& (!mul_frac_in1_51) && mul_frac_in1_50_0_neq_0
&& m1stg_dblopa[1];
assign m1stg_snan_sng_in2= (!mul_exp_in2_exp_neq_ffs) && (!mul_frac_in2_54)
&& (mul_frac_in2_53_32_neq_0) && m1stg_sngopa[1];
assign m1stg_snan_dbl_in2= (!mul_exp_in2_exp_neq_ffs)
&& (!mul_frac_in2_51) && mul_frac_in2_50_0_neq_0
&& m1stg_dblopa[1];
assign m1stg_qnan_sng_in1= (!mul_exp_in1_exp_neq_ffs) && mul_frac_in1_54
&& m1stg_sngopa[1];
assign m1stg_qnan_dbl_in1= (!mul_exp_in1_exp_neq_ffs) && mul_frac_in1_51
&& m1stg_dblopa[1];
assign m1stg_qnan_sng_in2= (!mul_exp_in2_exp_neq_ffs) && mul_frac_in2_54
&& m1stg_sngopa[1];
assign m1stg_qnan_dbl_in2= (!mul_exp_in2_exp_neq_ffs) && mul_frac_in2_51
&& m1stg_dblopa[1];
assign m1stg_snan_in1= m1stg_snan_sng_in1 || m1stg_snan_dbl_in1;
assign m1stg_snan_in2= m1stg_snan_sng_in2 || m1stg_snan_dbl_in2;
assign m1stg_qnan_in1= m1stg_qnan_sng_in1 || m1stg_qnan_dbl_in1;
assign m1stg_qnan_in2= m1stg_qnan_sng_in2 || m1stg_qnan_dbl_in2;
dffe_s #(1) i_m2stg_snan_in1 (
.din (m1stg_snan_in1),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_snan_in1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m2stg_snan_in2 (
.din (m1stg_snan_in2),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_snan_in2),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m2stg_qnan_in1 (
.din (m1stg_qnan_in1),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_qnan_in1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m2stg_qnan_in2 (
.din (m1stg_qnan_in2),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_qnan_in2),
.se (se),
.si (),
.so ()
);
assign m1stg_nan_sng_in1= (!mul_exp_in1_exp_neq_ffs)
&& (mul_frac_in1_54 || mul_frac_in1_53_32_neq_0)
&& m1stg_sngopa[2];
assign m1stg_nan_dbl_in1= (!mul_exp_in1_exp_neq_ffs)
&& (mul_frac_in1_51 || mul_frac_in1_50_0_neq_0)
&& m1stg_dblopa[2];
assign m1stg_nan_sng_in2= (!mul_exp_in2_exp_neq_ffs)
&& (mul_frac_in2_54 || mul_frac_in2_53_32_neq_0)
&& m1stg_sngopa[2];
assign m1stg_nan_dbl_in2= (!mul_exp_in2_exp_neq_ffs)
&& (mul_frac_in2_51 || mul_frac_in2_50_0_neq_0)
&& m1stg_dblopa[2];
assign m1stg_nan_in1= m1stg_nan_sng_in1 || m1stg_nan_dbl_in1;
assign m1stg_nan_in2= m1stg_nan_sng_in2 || m1stg_nan_dbl_in2;
dffe_s #(1) i_m2stg_nan_in2 (
.din (m1stg_nan_in2),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_nan_in2),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Infinity multiply inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_inf_sng_in1= (!mul_exp_in1_exp_neq_ffs)
&& (!mul_frac_in1_54) && (!mul_frac_in1_53_32_neq_0)
&& m1stg_sngopa[2];
assign m1stg_inf_dbl_in1= (!mul_exp_in1_exp_neq_ffs)
&& (!mul_frac_in1_51) && (!mul_frac_in1_50_0_neq_0)
&& m1stg_dblopa[2];
assign m1stg_inf_sng_in2= (!mul_exp_in2_exp_neq_ffs)
&& (!mul_frac_in2_54) && (!mul_frac_in2_53_32_neq_0)
&& m1stg_sngopa[2];
assign m1stg_inf_dbl_in2= (!mul_exp_in2_exp_neq_ffs)
&& (!mul_frac_in2_51) && (!mul_frac_in2_50_0_neq_0)
&& m1stg_dblopa[2];
assign m1stg_inf_in1= m1stg_inf_sng_in1 || m1stg_inf_dbl_in1;
assign m1stg_inf_in2= m1stg_inf_sng_in2 || m1stg_inf_dbl_in2;
assign m1stg_inf_in= m1stg_inf_in1 || m1stg_inf_in2;
dffe_s #(1) i_m2stg_inf_in1 (
.din (m1stg_inf_in1),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_inf_in1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m2stg_inf_in2 (
.din (m1stg_inf_in2),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_inf_in2),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m2stg_inf_in (
.din (m1stg_inf_in),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_inf_in),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Infinity/Nan multiply inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_infnan_sng_in1= (!mul_exp_in1_exp_neq_ffs) && m1stg_sngopa[3];
assign m1stg_infnan_dbl_in1= (!mul_exp_in1_exp_neq_ffs) && m1stg_dblopa[3];
assign m1stg_infnan_sng_in2= (!mul_exp_in2_exp_neq_ffs) && m1stg_sngopa[3];
assign m1stg_infnan_dbl_in2= (!mul_exp_in2_exp_neq_ffs) && m1stg_dblopa[3];
assign m1stg_infnan_in1= m1stg_infnan_sng_in1 || m1stg_infnan_dbl_in1;
assign m1stg_infnan_in2= m1stg_infnan_sng_in2 || m1stg_infnan_dbl_in2;
assign m1stg_infnan_in= m1stg_infnan_in1 || m1stg_infnan_in2;
///////////////////////////////////////////////////////////////////////////////
//
// Zero multiply inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_zero_in1= mul_exp_in1_exp_eq_0
&& (!mul_frac_in1_53_0_neq_0) && (!mul_frac_in1_54);
assign m1stg_zero_in2= mul_exp_in2_exp_eq_0
&& (!mul_frac_in2_53_0_neq_0) && (!mul_frac_in2_54);
assign m1stg_zero_in= m1stg_zero_in1 || m1stg_zero_in2;
dffe_s #(1) i_m2stg_zero_in1 (
.din (m1stg_zero_in1),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_zero_in1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m2stg_zero_in2 (
.din (m1stg_zero_in2),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_zero_in2),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m2stg_zero_in (
.din (m1stg_zero_in),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_zero_in),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Floating point multiply control pipeline.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply input stage.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_step= m6stg_stepa && (!m1stg_mul);
assign m1stg_op_in[7:0]= ({8{(m1stg_step && (!reset))}}
& (inq_op[7:0] & {8{inq_mul}}))
| ({8{((!m6stg_step) && (!reset))}}
& m1stg_op[7:0]);
dff_s #(8) i_m1stg_op (
.din (m1stg_op_in[7:0]),
.clk (rclk),
.q (m1stg_op[7:0]),
.se (se),
.si (),
.so ()
);
assign m1stg_mul_in= (m1stg_step && (!reset) && inq_mul)
|| ((!m6stg_step) && (!reset) && m1stg_mul);
dff_s #(1) i_m1stg_mul (
.din (m1stg_mul_in),
.clk (rclk),
.q (m1stg_mul),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m1stg_sngop (
.din (inq_op[0]),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_sngop),
.se (se),
.si (),
.so ()
);
dffe_s #(4) i_m1stg_sngopa (
.din ({4{inq_op[0]}}),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_sngopa[3:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m1stg_dblop (
.din (inq_op[1]),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_dblop),
.se (se),
.si (),
.so ()
);
dffe_s #(4) i_m1stg_dblopa (
.din ({4{inq_op[1]}}),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_dblopa[3:0]),
.se (se),
.si (),
.so ()
);
assign m1stg_dblop_inv_in= (!inq_op[1]);
dffe_s #(1) i_m1stg_dblop_inv (
.din (m1stg_dblop_inv_in),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_dblop_inv),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_m1stg_rnd_mode (
.din (inq_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(5) i_m1stg_id (
.din (inq_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_id[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode decode- multiply stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_fmul= (m1stg_op[7:0]==FMULS) || (m1stg_op[7:0]==FMULD)
|| (m1stg_op[7:0]==FSMULD);
assign m1stg_fmul_dbl_dst= (m1stg_op[7:0]==FMULD) || (m1stg_op[7:0]==FSMULD);
assign m1stg_fmuls= (m1stg_op[7:0]==FMULS);
assign m1stg_fmuld= (m1stg_op[7:0]==FMULD);
assign m1stg_fsmuld= (m1stg_op[7:0]==FSMULD);
assign m1stg_opdec[4:0]= {m1stg_fmul,
m1stg_fmul_dbl_dst,
m1stg_fmuls,
m1stg_fmuld,
m1stg_fsmuld};
dffre_s #(5) i_m2stg_opdec (
.din (m1stg_opdec[4:0]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m2stg_opdec[4:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_m2stg_rnd_mode (
.din (m1stg_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(5) i_m2stg_id (
.din (m1stg_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_id[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign m2stg_fmul= m2stg_opdec[4];
assign m2stg_fmuls= m2stg_opdec[2];
assign m2stg_fmuld= m2stg_opdec[1];
assign m2stg_fsmuld= m2stg_opdec[0];
dffre_s #(4) i_m3astg_opdec (
.din (m2stg_opdec[4:1]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m3astg_opdec[4:1]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_m3astg_rnd_mode (
.din (m2stg_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3astg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(5) i_m3astg_id (
.din (m2stg_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3astg_id[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply stage 3a.
//
///////////////////////////////////////////////////////////////////////////////
dffre_s #(4) i_m3bstg_opdec (
.din (m3astg_opdec[4:1]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m3bstg_opdec[4:1]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_m3bstg_rnd_mode (
.din (m3astg_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3bstg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(5) i_m3bstg_id (
.din (m3astg_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3bstg_id[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply stage 3b.
//
///////////////////////////////////////////////////////////////////////////////
dffre_s #(4) i_m3stg_opdec (
.din (m3bstg_opdec[4:1]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m3stg_opdec[4:1]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_m3stg_rnd_mode (
.din (m3bstg_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(5) i_m3stg_id (
.din (m3bstg_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3stg_id[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply stage 3.
//
///////////////////////////////////////////////////////////////////////////////
assign m3stg_fmul= m3stg_opdec[4];
dffre_s #(4) i_m4stg_opdec (
.din (m3stg_opdec[4:1]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m4stg_opdec[4:1]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_m4stg_rnd_mode (
.din (m3stg_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(5) i_m4stg_id (
.din (m3stg_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_id[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply stage 4.
//
///////////////////////////////////////////////////////////////////////////////
assign m4stg_fmul= m4stg_opdec[4];
assign m4stg_fmuld= m4stg_opdec[1];
dffre_s #(4) i_m5stg_opdec (
.din (m4stg_opdec[4:1]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m5stg_opdec[4:1]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_m5stg_rnd_mode (
.din (m4stg_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m5stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(5) i_m5stg_id (
.din (m4stg_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m5stg_id[4:0]),
.se (se),
.si (),
.so ()
);
dffre_s #(1) i_m5stg_fmulda (
.din (m4stg_fmuld),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m5stg_fmulda),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply stage 5.
//
///////////////////////////////////////////////////////////////////////////////
assign m5stg_fmul= m5stg_opdec[4];
assign m5stg_fmuls= m5stg_opdec[2];
assign m5stg_fmuld= m5stg_opdec[1];
assign m6stg_fmul_in= (m6stg_stepa && (!reset)
&& m5stg_fmul)
|| ((!m6stg_stepa) && (!reset)
&& m6stg_fmul);
dffre_s #(3) i_m6stg_opdec (
.din (m5stg_opdec[4:2]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m6stg_opdec[4:2]),
.se (se),
.si (),
.so ()
);
assign m6stg_id_in[9:0]= ({10{m6stg_stepa}}
& {(m5stg_id[4:2]==3'o7),
(m5stg_id[4:2]==3'o6),
(m5stg_id[4:2]==3'o5),
(m5stg_id[4:2]==3'o4),
(m5stg_id[4:2]==3'o3),
(m5stg_id[4:2]==3'o2),
(m5stg_id[4:2]==3'o1),
(m5stg_id[4:2]==3'o0),
m5stg_id[1:0]})
| ({10{(!m6stg_stepa)}}
& m6stg_id[9:0]);
dffe_s #(10) i_m6stg_id (
.din (m6stg_id_in[9:0]),
.en (m6stg_step),
.clk (rclk),
.q (m6stg_id[9:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply pipeline output.
//
///////////////////////////////////////////////////////////////////////////////
assign m6stg_fmul= m6stg_opdec[4];
assign m6stg_fmul_dbl_dst= m6stg_opdec[3];
assign m6stg_fmuls= m6stg_opdec[2];
assign m6stg_hold= m6stg_fmul && (!mul_dest_rdy);
assign m6stg_holda= m6stg_fmul && (!mul_dest_rdya);
assign m6stg_step= (!m6stg_hold);
assign m6stg_stepa= (!m6stg_holda);
// Austin update
// Power management update
assign mul_pipe_active_in = // mul pipe is executing a valid instr
m1stg_fmul || m2stg_fmul || m3astg_opdec[4] || m3bstg_opdec[4] ||
m3stg_fmul || m4stg_fmul || m5stg_fmul || m6stg_fmul;
dffre_s #(1) i_mul_pipe_active (
.din (mul_pipe_active_in),
.en (1'b1),
.rst (reset),
.clk (rclk),
.q (mul_pipe_active),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exception logic.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign inputs.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_m1stg_sign1 (
.din (inq_in1_63),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_sign1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m1stg_sign2 (
.din (inq_in2_63),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_sign2),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 1.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_m2stg_sign1 (
.din (m1stg_sign1),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_sign1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m2stg_sign2 (
.din (m1stg_sign2),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_sign2),
.se (se),
.si (),
.so ()
);
assign m1stg_of_mask= (!m1stg_infnan_in);
dffe_s #(1) i_m2stg_of_mask (
.din (m1stg_of_mask),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign m2stg_sign= ((m2stg_sign1
&& (!m2stg_snan_in2)
&& (!(m2stg_qnan_in2 && (!m2stg_snan_in1))))
^ (m2stg_sign2
&& (!(m2stg_snan_in1 && (!m2stg_snan_in2)))
&& (!(m2stg_qnan_in1 && (!m2stg_nan_in2)))))
&& (!(m2stg_inf_in && m2stg_zero_in));
dffe_s #(1) i_m3astg_sign (
.din (m2stg_sign),
.en (m6stg_step),
.clk (rclk),
.q (m3astg_sign),
.se (se),
.si (),
.so ()
);
assign m2stg_nv= m2stg_snan_in1
|| m2stg_snan_in2
|| (m2stg_zero_in1 && m2stg_inf_in2)
|| (m2stg_inf_in1 && m2stg_zero_in2);
dffe_s #(1) i_m3astg_nv (
.din (m2stg_nv),
.en (m6stg_step),
.clk (rclk),
.q (m3astg_nv),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m3astg_of_mask (
.din (m2stg_of_mask),
.en (m6stg_step),
.clk (rclk),
.q (m3astg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 3a.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_m3bstg_sign (
.din (m3astg_sign),
.en (m6stg_step),
.clk (rclk),
.q (m3bstg_sign),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m3bstg_nv (
.din (m3astg_nv),
.en (m6stg_step),
.clk (rclk),
.q (m3bstg_nv),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m3bstg_of_mask (
.din (m3astg_of_mask),
.en (m6stg_step),
.clk (rclk),
.q (m3bstg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 3b.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_m3stg_sign (
.din (m3bstg_sign),
.en (m6stg_step),
.clk (rclk),
.q (m3stg_sign),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m3stg_nv (
.din (m3bstg_nv),
.en (m6stg_step),
.clk (rclk),
.q (m3stg_nv),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m3stg_of_mask (
.din (m3bstg_of_mask),
.en (m6stg_step),
.clk (rclk),
.q (m3stg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 3.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_m4stg_sign (
.din (m3stg_sign),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_sign),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m4stg_nv (
.din (m3stg_nv),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_nv),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m4stg_of_mask (
.din (m3stg_of_mask),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 4.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_m5stg_sign (
.din (m4stg_sign),
.en (m6stg_step),
.clk (rclk),
.q (m5stg_sign),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m5stg_nv (
.din (m4stg_nv),
.en (m6stg_step),
.clk (rclk),
.q (m5stg_nv),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m5stg_of_mask (
.din (m4stg_of_mask),
.en (m6stg_step),
.clk (rclk),
.q (m5stg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 5.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_mul_sign_out (
.din (m5stg_sign),
.en (m6stg_step),
.clk (rclk),
.q (mul_sign_out),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_nv_out (
.din (m5stg_nv),
.en (m6stg_step),
.clk (rclk),
.q (mul_nv_out),
.se (se),
.si (),
.so ()
);
assign m5stg_in_of= ((!m5stg_exp[12])
&& m5stg_fmuld
&& (m5stg_exp[11] || (&m5stg_exp[10:0]))
&& m5stg_of_mask)
|| ((!m5stg_exp[12])
&& m5stg_fmuls
&& ((|m5stg_exp[11:8]) || (&m5stg_exp[7:0]))
&& m5stg_of_mask);
assign mul_of_out_tmp1_in= ((!m5stg_exp[12])
&& m5stg_fmuld
&& (&m5stg_exp[10:1])
&& m5stg_rndup
&& m5stg_of_mask)
|| ((!m5stg_exp[12])
&& m5stg_fmuls
&& (&m5stg_exp[7:1])
&& m5stg_rndup
&& m5stg_of_mask);
dffe_s #(1) i_mul_of_out_tmp1 (
.din (mul_of_out_tmp1_in),
.en (m6stg_step),
.clk (rclk),
.q (mul_of_out_tmp1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_of_out_tmp2 (
.din (m5stg_in_of),
.en (m6stg_step),
.clk (rclk),
.q (mul_of_out_tmp2),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_of_out_cout (
.din (m5stg_fracadd_cout),
.en (m6stg_step),
.clk (rclk),
.q (mul_of_out_cout),
.se (se),
.si (),
.so ()
);
assign mul_of_out= mul_of_out_tmp2
|| (mul_of_out_tmp1 && mul_of_out_cout);
assign mul_uf_out_in= (m5stg_exp[12] || (!(|m5stg_exp[11:0])))
&& m5stg_frac_neq_0;
dffe_s #(1) i_mul_uf_out (
.din (mul_uf_out_in),
.en (m6stg_step),
.clk (rclk),
.q (mul_uf_out),
.se (se),
.si (),
.so ()
);
assign mul_nx_out_in= (m5stg_fmuld && m5stg_frac_dbl_nx)
|| (m5stg_fmuls && m5stg_frac_sng_nx);
dffe_s #(1) i_mul_nx_out (
.din (mul_nx_out_in),
.en (m6stg_step),
.clk (rclk),
.q (mul_nx_out),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply exception output.
//
///////////////////////////////////////////////////////////////////////////////
// Austin update
// Overflow is always accompanied by inexact.
// Previously this was handled within the FFU.
// assign mul_exc_out[4:0]= {mul_nv_out, mul_of_out, mul_uf_out, 1'b0, mul_nx_out};
assign mul_exc_out[4:0] =
{mul_nv_out,
mul_of_out,
mul_uf_out,
1'b0,
(mul_nx_out || mul_of_out)}; // Overflow is always accompanied by inexact
///////////////////////////////////////////////////////////////////////////////
//
// Multiply pipeline control logic.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- multiply normalization and special input injection.
//
// Multiply stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign m2stg_frac1_dbl_norm= m1stg_norm_dbl_in1
&& ((!(m1stg_infnan_dbl_in1 || m1stg_infnan_dbl_in2))
|| (m1stg_snan_dbl_in1 && (!m1stg_snan_dbl_in2))
|| (m1stg_qnan_dbl_in1 && (!m1stg_nan_dbl_in2)));
assign m2stg_frac1_dbl_dnrm= m1stg_denorm_dbl_in1
&& (!(m1stg_infnan_dbl_in1 || m1stg_infnan_dbl_in2));
assign m2stg_frac1_sng_norm= m1stg_norm_sng_in1
&& ((!(m1stg_infnan_sng_in1 || m1stg_infnan_sng_in2))
|| (m1stg_snan_sng_in1 && (!m1stg_snan_sng_in2))
|| (m1stg_qnan_sng_in1 && (!m1stg_nan_sng_in2)));
assign m2stg_frac1_sng_dnrm= m1stg_denorm_sng_in1
&& (!(m1stg_infnan_sng_in1 || m1stg_infnan_sng_in2));
assign m2stg_frac1_inf= (m1stg_inf_in && (!m1stg_nan_in1) && (!m1stg_nan_in2))
|| m1stg_snan_in2
|| (m1stg_qnan_in2 && (!m1stg_snan_in1));
assign m2stg_frac2_dbl_norm= m1stg_norm_dbl_in2
&& ((!(m1stg_infnan_dbl_in1 || m1stg_infnan_dbl_in2))
|| m1stg_snan_dbl_in2
|| (m1stg_qnan_dbl_in2 && (!m1stg_snan_dbl_in1)));
assign m2stg_frac2_dbl_dnrm= m1stg_denorm_dbl_in2
&& (!(m1stg_infnan_dbl_in1 || m1stg_infnan_dbl_in2));
assign m2stg_frac2_sng_norm= m1stg_norm_sng_in2
&& ((!(m1stg_infnan_sng_in1 || m1stg_infnan_sng_in2))
|| m1stg_snan_sng_in2
|| (m1stg_qnan_sng_in2 && (!m1stg_snan_sng_in1)));
assign m2stg_frac2_sng_dnrm= m1stg_denorm_sng_in2
&& (!(m1stg_infnan_sng_in1 || m1stg_infnan_sng_in2));
assign m2stg_frac2_inf= (m1stg_inf_in && (!m1stg_nan_in1) && (!m1stg_nan_in2))
|| (m1stg_snan_in1 && (!m1stg_snan_in2))
|| (m1stg_qnan_in1 && (!m1stg_nan_in2));
assign m1stg_inf_zero_in= (m1stg_inf_in1 && m1stg_zero_in2)
|| (m1stg_zero_in1 && m1stg_inf_in2);
assign m1stg_inf_zero_in_dbl= ((m1stg_inf_in1 && m1stg_zero_in2)
|| (m1stg_zero_in1 && m1stg_inf_in2))
&& m1stg_fmul_dbl_dst;
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic- multiply leading 0 counts.
//
// Multiply stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign m2stg_ld0_1_in[5:0]= ({6{(m1stg_denorm_in1 && (!m1stg_infnan_in))}}
& m1stg_ld0_1[5:0]);
dffe_s #(6) i_m2stg_ld0_1 (
.din (m2stg_ld0_1_in[5:0]),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_ld0_1[5:0]),
.se (se),
.si (),
.so ()
);
assign m2stg_ld0_2_in[5:0]= ({6{(m1stg_denorm_in2 && (!m1stg_infnan_in))}}
& m1stg_ld0_2[5:0]);
dffe_s #(6) i_m2stg_ld0_2 (
.din (m2stg_ld0_2_in[5:0]),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_ld0_2[5:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- multiply exponent adder.
//
// Multiply stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign m2stg_exp_expadd= (!m1stg_infnan_in) && (!m1stg_zero_in);
assign m2stg_exp_0bff= m1stg_fmuld && m1stg_infnan_in;
assign m2stg_exp_017f= m1stg_fmuls && m1stg_infnan_in;
assign m2stg_exp_04ff= m1stg_fsmuld && m1stg_infnan_in;
assign m2stg_exp_zero= m1stg_zero_in && (!m1stg_infnan_in);
///////////////////////////////////////////////////////////////////////////////
//
// Total the leading 0's.
//
// Multiply stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign m2stg_ld0[6:0]= {1'b0, m2stg_ld0_1[5:0]}
+ {1'b0, m2stg_ld0_2[5:0]};
assign m2stg_ld0_inv[6:0]= (~m2stg_ld0[6:0]);
dffe_s #(7) i_m3astg_ld0_inv (
.din (m2stg_ld0_inv[6:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3astg_ld0_inv[6:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Leading 0's.
//
// Multiply stage 3a.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(7) i_m3bstg_ld0_inv (
.din (m3astg_ld0_inv[6:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3bstg_ld0_inv[6:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Post-normalization/denormalization shift count and direction.
//
// Multiply stage 3.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_m4stg_expadd_eq_0 (
.din (m3stg_expadd_eq_0),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_expadd_eq_0),
.se (se),
.si (),
.so ()
);
assign m3stg_exp_lte_0= (!(|m3stg_exp[11:0])) || m3stg_exp[12];
assign m4stg_right_shift_in= (!m3stg_expadd_lte_0_inv) && m3stg_exp_lte_0;
dffe_s #(1) i_m4stg_right_shift (
.din (m4stg_right_shift_in),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_right_shift),
.se (se),
.si (),
.so ()
);
assign m3stg_exp_minus1[5:0]= m3stg_exp[5:0]
+ 6'h3f;
assign m3stg_exp_inv_plus2[5:0]= (~m3stg_exp[5:0])
+ 6'h02;
assign m3stg_exp_lt_neg57= ((!(&m3stg_exp[11:6]))
|| (!(|m3stg_exp[5:3])))
&& m3stg_exp[12];
assign m4stg_sh_cnt_in[5:0]= ({6{((!m3stg_expadd_lte_0_inv)
&& (!m3stg_exp_lte_0))}}
& m3stg_exp_minus1[5:0])
| ({6{((!m3stg_expadd_lte_0_inv) && m3stg_exp_lte_0
&& m3stg_exp_lt_neg57)}}
& 6'h39)
| ({6{((!m3stg_expadd_lte_0_inv) && m3stg_exp_lte_0
&& (!m3stg_exp_lt_neg57))}}
& m3stg_exp_inv_plus2[5:0])
| ({6{m3stg_expadd_lte_0_inv}}
& (~m3stg_ld0_inv[5:0]));
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic- multiply shifts for
// post-normalization/denormalization.
//
// Multiply stage 4.
//
///////////////////////////////////////////////////////////////////////////////
assign m4stg_left_shift_step= (!m4stg_right_shift) && m6stg_step;
assign m4stg_right_shift_step= m4stg_right_shift && m6stg_step;
// Austin update
// uarch timing fix
// Endpoint: fpu_mul_exp_dp/i_m5stg_exp_pre2_10
// assign m4stg_inc_exp= (((!(|m4stg_exp[12:0])) && (!m4stg_right_shift)
// && m4stg_shl_54)
// || (m4stg_expadd_eq_0 && m4stg_right_shift
// && m4stg_frac_105)
// || ((!m4stg_right_shift) && m4stg_shl_55))
// && m6stg_step;
//
// assign m4stg_inc_exp_inv= (!m4stg_inc_exp) && m6stg_step;
assign m4stg_inc_exp_54 = (!(|m4stg_exp[12:0])) && (!m4stg_right_shift);
assign m4stg_inc_exp_55 = !m4stg_right_shift;
assign m4stg_inc_exp_105 = m4stg_expadd_eq_0 && m4stg_right_shift && m4stg_frac_105;
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic- multiply rounding.
//
// Multiply stage 5.
//
///////////////////////////////////////////////////////////////////////////////
assign m5stg_rndup= ((((m5stg_rnd_mode[1:0]==2'b10) && (!m5stg_sign)
&& (m5stg_frac[2:0]!=3'b0))
|| ((m5stg_rnd_mode[1:0]==2'b11) && m5stg_sign
&& (m5stg_frac[2:0]!=3'b0))
|| ((m5stg_rnd_mode[1:0]==2'b00)
&& m5stg_frac[2]
&& ((m5stg_frac[1:0]!=2'b0)
|| m5stg_frac[3])))
&& m5stg_fmuld)
|| ((((m5stg_rnd_mode[1:0]==2'b10) && (!m5stg_sign)
&& (m5stg_frac[31:0]!=32'b0))
|| ((m5stg_rnd_mode[1:0]==2'b11) && m5stg_sign
&& (m5stg_frac[31:0]!=32'b0))
|| ((m5stg_rnd_mode[1:0]==2'b00)
&& m5stg_frac[31]
&& ((m5stg_frac[30:0]!=31'b0)
|| m5stg_frac[32])))
&& m5stg_fmuls);
assign m5stg_to_0= (m5stg_rnd_mode[1:0]==2'b01)
|| ((m5stg_rnd_mode[1:0]==2'b10) && m5stg_sign)
|| ((m5stg_rnd_mode[1:0]==2'b11) && (!m5stg_sign));
assign m5stg_to_0_inv= (!m5stg_to_0);
assign mul_frac_out_fracadd= m5stg_rndup && (!m5stg_in_of);
assign mul_frac_out_frac= (!m5stg_rndup) && (!m5stg_in_of);
assign mul_exp_out_exp_plus1= m5stg_rndup && (!m5stg_in_of);
assign mul_exp_out_exp= (!m5stg_rndup) && (!m5stg_in_of);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3_1_V
`define SKY130_FD_SC_LP__AND3_1_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3_1_V
|
/*
########################################################################
Epiphany eLink AXI Master Module
########################################################################
*/
module emaxi(/*autoarg*/
// Outputs
emwr_rd_en, emrq_rd_en, emrr_access, emrr_write, emrr_datamode,
emrr_ctrlmode, emrr_dstaddr, emrr_data, emrr_srcaddr, m_axi_awid,
m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst,
m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos,
m_axi_awvalid, m_axi_wid, m_axi_wdata, m_axi_wstrb, m_axi_wlast,
m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen,
m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache,
m_axi_arprot, m_axi_arqos, m_axi_arvalid, m_axi_rready,
// Inputs
emwr_access, emwr_write, emwr_datamode, emwr_ctrlmode,
emwr_dstaddr, emwr_data, emwr_srcaddr, emrq_access, emrq_write,
emrq_datamode, emrq_ctrlmode, emrq_dstaddr, emrq_data,
emrq_srcaddr, emrr_progfull, m_axi_aclk, m_axi_aresetn,
m_axi_awready, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid,
m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast,
m_axi_rvalid
);
parameter IDW = 12;
// fifo read-master port, writes from rx
input emwr_access;
input emwr_write;
input [1:0] emwr_datamode;
input [3:0] emwr_ctrlmode;
input [31:0] emwr_dstaddr;
input [31:0] emwr_data;
input [31:0] emwr_srcaddr;
output emwr_rd_en; //read ptr update for fifo
// fifo read-master port; read requests from rx
input emrq_access;
input emrq_write;
input [1:0] emrq_datamode;
input [3:0] emrq_ctrlmode;
input [31:0] emrq_dstaddr;
input [31:0] emrq_data;
input [31:0] emrq_srcaddr;
output emrq_rd_en; //read ptr update for fifo
// fifo write-master port; read responses for etx
output emrr_access;
output emrr_write;
output [1:0] emrr_datamode;
output [3:0] emrr_ctrlmode;
output [31:0] emrr_dstaddr;
output [31:0] emrr_data;
output [31:0] emrr_srcaddr;
input emrr_progfull;
/*****************************/
/*axi */
/*****************************/
input m_axi_aclk; // global clock signal.
input m_axi_aresetn; // global reset singal.
//Write address channel
output [IDW-1:0] m_axi_awid; // write address ID
output [31 : 0] m_axi_awaddr; // master interface write address
output [7 : 0] m_axi_awlen; // burst length.
output [2 : 0] m_axi_awsize; // burst size.
output [1 : 0] m_axi_awburst; // burst type.
output [1 : 0] m_axi_awlock; // lock type
output [3 : 0] m_axi_awcache; // memory type.
output [2 : 0] m_axi_awprot; // protection type.
output [3 : 0] m_axi_awqos; // quality of service
output m_axi_awvalid; // write address valid
input m_axi_awready; // write address ready
//Write data channel
output [IDW-1:0] m_axi_wid;
output [63 : 0] m_axi_wdata; // master interface write data.
output [7 : 0] m_axi_wstrb; // byte write strobes
output m_axi_wlast; // indicates last transfer in a write burst.
output m_axi_wvalid; // indicates data is ready to go
input m_axi_wready; // indicates that the slave is ready for data
//Write response channel
input [IDW-1:0] m_axi_bid;
input [1 : 0] m_axi_bresp; // status of the write transaction.
input m_axi_bvalid; // channel is signaling a valid write response
output m_axi_bready; // master can accept write response.
//Read address channel
output [IDW-1:0] m_axi_arid; // read address ID
output [31 : 0] m_axi_araddr; // initial address of a read burst
output [7 : 0] m_axi_arlen; // burst length
output [2 : 0] m_axi_arsize; // burst size
output [1 : 0] m_axi_arburst; // burst type
output [1 : 0] m_axi_arlock; //lock type
output [3 : 0] m_axi_arcache; // memory type
output [2 : 0] m_axi_arprot; // protection type
output [3 : 0] m_axi_arqos; //
output m_axi_arvalid; // valid read address and control information
input m_axi_arready; // slave is ready to accept an address
//Read data channel
input [IDW-1:0] m_axi_rid;
input [63 : 0] m_axi_rdata; // master read data
input [1 : 0] m_axi_rresp; // status of the read transfer
input m_axi_rlast; // signals last transfer in a read burst
input m_axi_rvalid; // signaling the required read data
output m_axi_rready; // master can accept the readback data
//registers
reg [31 : 0] m_axi_awaddr;
reg [7:0] m_axi_awlen;
reg [2:0] m_axi_awsize;
reg m_axi_awvalid;
reg [63 : 0] m_axi_wdata;
reg [7 : 0] m_axi_wstrb;
reg m_axi_wlast;
reg m_axi_wvalid;
reg awvalid_b;
reg [31:0] awaddr_b;
reg [2:0] awsize_b;
reg [7:0] awlen_b;
reg wvalid_b;
reg [63:0] wdata_b;
reg [7:0] wstrb_b;
reg [63 : 0] wdata_aligned;
reg [7 : 0] wstrb_aligned;
reg emrr_access;
reg emrr_access_reg;
reg [31:0] emrr_data;
reg [31:0] emrr_srcaddr;
//wires
wire aw_go;
wire w_go;
wire readinfo_wren;
wire readinfo_rden;
wire readinfo_full;
wire [47:0] readinfo_out;
wire [47:0] readinfo_in;
//i/o connections. write address (aw)
assign m_axi_awburst[1:0] = 2'b01;
assign m_axi_awcache[3:0] = 4'b0010;//TODO??update value to 4'b0011 if coherent accesses to be used via the zynq acp port
assign m_axi_awprot[2:0] = 3'h0;
assign m_axi_awqos[3:0] = 4'h0;
assign m_axi_bready = 1'b1; //TODO? axi_bready, why constant
assign m_axi_arburst[1:0] = 2'b01;
assign m_axi_arcache[3:0] = 4'b0010;
assign m_axi_arprot[2:0] = 3'h0;
assign m_axi_arqos[3:0] = 4'h0;
//--------------------
//write address channel
//--------------------
assign aw_go = m_axi_awvalid & m_axi_awready;
assign w_go = m_axi_wvalid & m_axi_wready;
assign emwr_rd_en = ( emwr_access & ~awvalid_b & ~wvalid_b);
// generate write-address signals
always @( posedge m_axi_aclk )
if(~m_axi_aresetn)
begin
m_axi_awvalid <= 1'b0;
m_axi_awaddr[31:0] <= 32'd0;
m_axi_awlen[7:0] <= 8'd0;
m_axi_awsize[2:0] <= 3'd0;
awvalid_b <= 1'b0;
awaddr_b[31:0] <= 32'd0;
awlen_b[7:0] <= 8'd0;
awsize_b[2:0] <= 3'd0;
end
else
begin
if( ~m_axi_awvalid | aw_go )
begin
if( awvalid_b )
begin
m_axi_awvalid <= 1'b1;
m_axi_awaddr[31:0] <= awaddr_b[31:0];
m_axi_awlen[7:0] <= awlen_b[7:0];
m_axi_awsize[2:0] <= awsize_b[2:0];
end
else
begin
m_axi_awvalid <= emwr_rd_en;
m_axi_awaddr[31:0] <= emwr_dstaddr[31:0];
m_axi_awlen[7:0] <= 8'b0;
m_axi_awsize[2:0] <= { 1'b0, emwr_datamode[1:0]};
end
end
if( emwr_rd_en & m_axi_awvalid & ~aw_go )
awvalid_b <= 1'b1;
else if( aw_go )
awvalid_b <= 1'b0;
//Pipeline stage
if( emwr_rd_en )
begin
awaddr_b[31:0] <= emwr_dstaddr[31:0];
awlen_b[7:0] <= 8'b0;
awsize_b[2:0] <= { 1'b0, emwr_datamode[1:0] };
end
end // else: !if(~m_axi_aresetn)
//--------------------
//write alignment circuit
//--------------------
always @*
case( emwr_datamode[1:0] )
2'd0: wdata_aligned[63:0] = { 8{emwr_data[7:0]}};
2'd1: wdata_aligned[63:0] = { 4{emwr_data[15:0]}};
2'd2: wdata_aligned[63:0] = { 2{emwr_data[31:0]}};
default: wdata_aligned[63:0] = { emwr_srcaddr[31:0], emwr_data[31:0]};
endcase
//TODO: Simplify logic below!!!!!
//Should include separate fields for address/data/datamode!!!!
always @*
begin
case(emwr_datamode[1:0])
2'd0: // byte
case(emwr_dstaddr[2:0])
3'd0: wstrb_aligned[7:0] = 8'h01;
3'd1: wstrb_aligned[7:0] = 8'h02;
3'd2: wstrb_aligned[7:0] = 8'h04;
3'd3: wstrb_aligned[7:0] = 8'h08;
3'd4: wstrb_aligned[7:0] = 8'h10;
3'd5: wstrb_aligned[7:0] = 8'h20;
3'd6: wstrb_aligned[7:0] = 8'h40;
default: wstrb_aligned[7:0] = 8'h80;
endcase
2'd1: // 16b hword
case(emwr_dstaddr[2:1])
2'd0: wstrb_aligned[7:0] = 8'h03;
2'd1: wstrb_aligned[7:0] = 8'h0c;
2'd2: wstrb_aligned[7:0] = 8'h30;
default: wstrb_aligned[7:0] = 8'hc0;
endcase
2'd2: // 32b word
if(emwr_dstaddr[2])
wstrb_aligned[7:0] = 8'hf0;
else
wstrb_aligned[7:0] = 8'h0f;
2'd3:
wstrb_aligned[7:0] = 8'hff;
endcase // case (emwr_datamode[1:0])
end // always @ *
// generate the write-data signals
always @ (posedge m_axi_aclk )
if(~m_axi_aresetn)
begin
m_axi_wvalid <= 1'b0;
m_axi_wdata[63:0] <= 64'b0;
m_axi_wstrb[7:0] <= 8'b0;
m_axi_wlast <= 1'b1; // todo: no bursts for now?
wvalid_b <= 1'b0;
wdata_b[63:0] <= 64'b0;
wstrb_b[7:0] <= 8'b0;
end
else
begin
if( ~m_axi_wvalid | w_go )
begin
if( wvalid_b )
begin
m_axi_wvalid <= 1'b1;
m_axi_wdata[63:0] <= wdata_b[63:0];
m_axi_wstrb[7:0] <= wstrb_b[7:0];
end
else
begin
m_axi_wvalid <= emwr_rd_en;//todo
m_axi_wdata[63:0] <= wdata_aligned[63:0];
m_axi_wstrb[7:0] <= wstrb_aligned[7:0];
end
end // if ( ~axi_wvalid | w_go )
if( emwr_rd_en & m_axi_wvalid & ~w_go )
wvalid_b <= 1'b1;
else if( w_go )
wvalid_b <= 1'b0;
if( emwr_rd_en )
begin
wdata_b[63:0] <= wdata_aligned[63:0];
wstrb_b[7:0] <= wstrb_aligned[7:0];
end
end // else: !if(~m_axi_aresetn)
//----------------------------
// read handler
// elink read requests generate a transaction on the ar channel,
// buffer the src info to generate an elink write when the
// read data comes back.
//----------------------------
//TODO: Can we improve this??
assign readinfo_in[47:0] =
{
7'b0,
emrq_srcaddr[31:0],//40:9
emrq_dstaddr[2:0], //8:6
emrq_ctrlmode[3:0], //5:2
emrq_datamode[1:0]
};
fifo_sync
#(
// parameters
.AW (5),
.DW (48))
fifo_readinfo_i
(
// outputs
.rd_data (readinfo_out[47:0]),
.rd_empty (),
.wr_full (readinfo_full),
// inputs
.clk (m_axi_aclk),
.reset (~m_axi_aresetn),
.wr_data (readinfo_in[47:0]),
.wr_en (emrq_rd_en),
.rd_en (readinfo_rden));
assign emrr_datamode[1:0] = readinfo_out[1:0];
assign emrr_ctrlmode[3:0] = readinfo_out[5:2];
assign emrr_dstaddr[31:0] = readinfo_out[40:9];
//----------------------------
// read address channel
//----------------------------
assign m_axi_araddr[31:0] = emrq_dstaddr[31:0];
assign m_axi_arsize[2:0] = {1'b0, emrq_datamode[1:0]};
assign m_axi_arlen[7:0] = 8'd0;
assign m_axi_arvalid = emrq_access & ~readinfo_full;
assign emrq_rd_en = m_axi_arvalid & m_axi_arready;
//--------------------------------
// read data (and response) channel
//--------------------------------
assign m_axi_rready = ~emrr_progfull;
assign readinfo_rden = ~emrr_progfull & m_axi_rvalid;
assign emrr_write = 1'b1;
always @( posedge m_axi_aclk )
if( ~m_axi_aresetn )
begin
emrr_data[31:0] <= 32'b0;
emrr_srcaddr[31:0] <= 32'b0;
emrr_access_reg <= 1'b0;
emrr_access <= 1'b0;
end
else
begin
emrr_access_reg <= m_axi_rready & m_axi_rvalid;
emrr_access <= emrr_access_reg;//added pipeline stage for data
emrr_srcaddr[31:0] <= m_axi_rdata[63:32];
// steer read data according to size & host address lsbs
//all data needs to be right aligned
//(this is due to the Epiphany right aligning all words)
case(readinfo_out[1:0])//datamode
2'd0: // byte read
case(readinfo_out[8:6])
3'd0: emrr_data[7:0] <= m_axi_rdata[7:0];
3'd1: emrr_data[7:0] <= m_axi_rdata[15:8];
3'd2: emrr_data[7:0] <= m_axi_rdata[23:16];
3'd3: emrr_data[7:0] <= m_axi_rdata[31:24];
3'd4: emrr_data[7:0] <= m_axi_rdata[39:32];
3'd5: emrr_data[7:0] <= m_axi_rdata[47:40];
3'd6: emrr_data[7:0] <= m_axi_rdata[55:48];
default: emrr_data[7:0] <= m_axi_rdata[63:56];
endcase
2'd1: // 16b hword
case( readinfo_out[8:7] )
2'd0: emrr_data[15:0] <= m_axi_rdata[15:0];
2'd1: emrr_data[15:0] <= m_axi_rdata[31:16];
2'd2: emrr_data[15:0] <= m_axi_rdata[47:32];
default: emrr_data[15:0] <= m_axi_rdata[63:48];
endcase
2'd2: // 32b word
if( readinfo_out[8] )
emrr_data[31:0] <= m_axi_rdata[63:32];
else
emrr_data[31:0] <= m_axi_rdata[31:0];
// 64b word already defined by defaults above
2'd3: begin // 64b dword
emrr_data[31:0] <= m_axi_rdata[31:0];
end
endcase
end // else: !if( ~m_axi_aresetn )
endmodule
/*
copyright (c) 2014 adapteva, inc.
contributed by fred huettig <[email protected]>
contributed by andreas olofsson <[email protected]>
this program is free software: you can redistribute it and/or modify
it under the terms of the gnu general public license as published by
the free software foundation, either version 3 of the license, or
(at your option) any later version.
this program is distributed in the hope that it will be useful,
but without any warranty; without even the implied warranty of
merchantability or fitness for a particular purpose. see the
gnu general public license for more details.
you should have received a copy of the gnu general public license
along with this program (see the file copying). if not, see
<http://www.gnu.org/licenses/>.
*/
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
// Date : Mon Nov 03 20:58:05 2014
// Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// C:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/lp_FIR_stub.v
// Design : lp_FIR
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fir_compiler_v7_1,Vivado 2014.2" *)
module lp_FIR(aclk, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[23:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */;
input aclk;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [23:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [23:0]m_axis_data_tdata;
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_keycode (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4B_M_V
`define SKY130_FD_SC_LP__NOR4B_M_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4b_m (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4b_m (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4B_M_V
|
//Copyright 2022 Google LLC
//
//Licensed under the Apache License, Version 2.0 (the "License");
//you may not use this file except in compliance with the License.
//You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
//Unless required by applicable law or agreed to in writing, software
//distributed under the License is distributed on an "AS IS" BASIS,
//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//See the License for the specific language governing permissions and
//limitations under the License.
module adder_reg(
input clk,
input [7:0] x,
input [7:0] y,
input carry_in,
output carry_output_bit,
output [7:0] sum
);
reg [8:0] full_sum_reg;
reg [7:0] x_reg;
reg [7:0] y_reg;
reg carry_in_reg;
assign carry_output_bit = full_sum_reg[8];
assign sum = full_sum_reg[7:0];
always @(posedge clk)
begin
x_reg <= x;
y_reg <= y;
carry_in_reg <= carry_in;
full_sum_reg <= x_reg + y_reg + carry_in_reg;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 15:35:33 09/12/2015
// Design Name: Truth table implementation of 4:3 encoder.
// Module Name: encoder43table
//////////////////////////////////////////////////////////////////////////////////
module encoder43table(A, B, C, D, Y2, Y1, Y0);
input A, B, C, D;
output reg Y2, Y1, Y0;
always@(A, B, C, D)
case({A, B, C, D})
4'b0000: {Y2, Y1, Y0} = 3'b000;
4'b0001: {Y2, Y1, Y0} = 3'b001;
4'b0010: {Y2, Y1, Y0} = 3'b001;
4'b0011: {Y2, Y1, Y0} = 3'b010;
4'b0100: {Y2, Y1, Y0} = 3'b001;
4'b0101: {Y2, Y1, Y0} = 3'b010;
4'b0110: {Y2, Y1, Y0} = 3'b010;
4'b0111: {Y2, Y1, Y0} = 3'b011;
4'b1000: {Y2, Y1, Y0} = 3'b001;
4'b1001: {Y2, Y1, Y0} = 3'b010;
4'b1010: {Y2, Y1, Y0} = 3'b010;
4'b1011: {Y2, Y1, Y0} = 3'b011;
4'b1100: {Y2, Y1, Y0} = 3'b010;
4'b1101: {Y2, Y1, Y0} = 3'b011;
4'b1110: {Y2, Y1, Y0} = 3'b011;
4'b1111: {Y2, Y1, Y0} = 3'b100;
endcase
endmodule
|
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