text
stringlengths 938
1.05M
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// Conditional fork (2 channels)
module fork_cond2_r1_2ph (/*AUTOARG*/
// Outputs
a, r1, r2,
// Inputs
r, a1, cond1, a2, cond2, rstn
);
parameter WIDTH = 8;
input r;
output a;
output r1;
input a1;
input cond1; // =0 , req is not propagated, = 1 : reg is propagated
output r2;
input a2;
input cond2; // =0 , req is not propagated, = 1 : reg is propagated
input rstn;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
wire false1, false2;
wire r1,r2;
wire a;
select U_SELECT1_OUT(
.in(r),
.sel(cond1),
.false(false1),
.true(r1),
.rstn(rstn)
);
mux2 U_MUX1_IN(
.a0(false1),
.a1(a1),
.s(cond1),
.z(a1mux)
);
select U_SELECT2_OUT(
.in(r),
.sel(cond2),
.false(false2),
.true(r2),
.rstn(rstn)
);
mux2 U_MUX2_IN(
.a0(false2),
.a1(a2),
.s(cond2),
.z(a2mux)
);
muller3 U_MULLER3(
.a(r),
.b(a1mux),
.c(a2mux),
.z(a),
.rstn(rstn)
);
endmodule // selector_r1_2ph
/*
Local Variables:
verilog-library-directories:(
"."
)
End:
*/
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_512_7.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_512_7 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q,
usedw);
input aclr;
input clock;
input [6:0] data;
input rdreq;
input wrreq;
output empty;
output [6:0] q;
output [8:0] usedw;
wire sub_wire0;
wire [6:0] sub_wire1;
wire [8:0] sub_wire2;
wire empty = sub_wire0;
wire [6:0] q = sub_wire1[6:0];
wire [8:0] usedw = sub_wire2[8:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.usedw (sub_wire2),
.almost_empty (),
.almost_full (),
.full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 512,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 7,
scfifo_component.lpm_widthu = 9,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "7"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "7"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 7 0 INPUT NODEFVAL "data[6..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: q 0 0 7 0 OUTPUT NODEFVAL "q[6..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 9 0 OUTPUT NODEFVAL "usedw[8..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 7 0 data 0 0 7 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: q 0 0 7 0 @q 0 0 7 0
// Retrieval info: CONNECT: usedw 0 0 9 0 @usedw 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_7.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_7.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_7.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_7.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_7_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_7_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: arriagx_dmem.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module arriagx_dmem (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [9:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Arria GX",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0]
// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0]
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2_4_V
`define SKY130_FD_SC_MS__AND2_4_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and2_4 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2_4_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_clsp_dramgif.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: CTU
// Unit Name: ctu_clsp_dramif
//
//-----------------------------------------------------------------------------
`include "sys.h"
`include "ctu.h"
module ctu_clsp_dramgif(/*AUTOARG*/
// Outputs
dram_grst_out_l, dram_arst_l, dram_gdbginit_out_l, dram_adbginit_l,
ctu_dram02_dram_cken, ctu_dram13_dram_cken, ctu_ddr0_dram_cken,
ctu_ddr1_dram_cken, ctu_ddr2_dram_cken, ctu_ddr3_dram_cken,
// Inputs
io_pwron_rst_l, start_clk_early_jl, testmode_l, dram_gclk,
start_clk_dg, shadreg_div_dmult, de_grst_dsync_edge_dg,
de_dbginit_dsync_edge_dg, a_grst_dg, a_dbginit_dg,
ctu_dram02_dram_cken_dg, ctu_dram13_dram_cken_dg,
ctu_ddr0_dram_cken_dg, ctu_ddr1_dram_cken_dg, ctu_ddr2_dram_cken_dg,
ctu_ddr3_dram_cken_dg, jtag_clsp_force_cken_dram
);
input io_pwron_rst_l;
input start_clk_early_jl;
input testmode_l;
input dram_gclk;
input start_clk_dg;
input [9:0] shadreg_div_dmult;
input de_grst_dsync_edge_dg;
input de_dbginit_dsync_edge_dg;
input a_grst_dg;
input a_dbginit_dg;
input ctu_dram02_dram_cken_dg;
input ctu_dram13_dram_cken_dg;
input ctu_ddr0_dram_cken_dg;
input ctu_ddr1_dram_cken_dg;
input ctu_ddr2_dram_cken_dg;
input ctu_ddr3_dram_cken_dg;
input jtag_clsp_force_cken_dram;
output dram_grst_out_l;
output dram_arst_l;
output dram_gdbginit_out_l;
output dram_adbginit_l;
output ctu_dram02_dram_cken;
output ctu_dram13_dram_cken;
output ctu_ddr0_dram_cken;
output ctu_ddr1_dram_cken;
output ctu_ddr2_dram_cken;
output ctu_ddr3_dram_cken;
wire ctu_dram02_dram_cken_muxed;
wire ctu_dram13_dram_cken_muxed;
wire ctu_ddr0_dram_cken_muxed;
wire ctu_ddr1_dram_cken_muxed;
wire ctu_ddr2_dram_cken_muxed;
wire ctu_ddr3_dram_cken_muxed;
wire force_cken;
// sync edge count
wire [9:0] lcm_cnt_minus_1;
wire [9:0] lcm_cnt_nxt;
wire [9:0] lcm_cnt;
wire lcm_cnt_zero;
wire cnt_ld;
wire dram_grst_l_nxt;
wire dram_dbginit_l_nxt;
wire dbginit_en_window_nxt;
wire dbginit_en_window;
wire grst_en_window_nxt;
wire grst_en_window;
// -----------------------------------------
//
// Negedge flops signals
//
// -----------------------------------------
// -----------------------------------------
//
// Global signals
//
// -----------------------------------------
// The following flops needs to be non-scanable:
assign dram_arst_l = io_pwron_rst_l ;
assign dram_adbginit_l = io_pwron_rst_l ;
assign force_cken = jtag_clsp_force_cken_dram | ~testmode_l;
assign ctu_dram02_dram_cken_muxed = force_cken ? 1'b1: ctu_dram02_dram_cken_dg & start_clk_dg;
assign ctu_dram13_dram_cken_muxed = force_cken ? 1'b1: ctu_dram13_dram_cken_dg & start_clk_dg;
assign ctu_ddr0_dram_cken_muxed = force_cken ? 1'b1: ctu_ddr0_dram_cken_dg & start_clk_dg;
assign ctu_ddr1_dram_cken_muxed = force_cken ? 1'b1: ctu_ddr1_dram_cken_dg & start_clk_dg;
assign ctu_ddr2_dram_cken_muxed = force_cken ? 1'b1: ctu_ddr2_dram_cken_dg & start_clk_dg;
assign ctu_ddr3_dram_cken_muxed = force_cken ? 1'b1: ctu_ddr3_dram_cken_dg & start_clk_dg;
dffrl_async_ns u_ctu_dram02_dram_cken_async_nsr(
.din (ctu_dram02_dram_cken_muxed),
.clk (dram_gclk),
.rst_l(io_pwron_rst_l),
.q (ctu_dram02_dram_cken));
dffrl_async_ns u_ctu_dram13_dram_cken_async_nsr(
.din (ctu_dram13_dram_cken_muxed),
.clk (dram_gclk),
.rst_l(io_pwron_rst_l),
.q (ctu_dram13_dram_cken));
dffrl_async_ns u_ctu_ddr0_dram_cken_async_nsr(
.din (ctu_ddr0_dram_cken_muxed),
.clk (dram_gclk),
.rst_l(io_pwron_rst_l),
.q (ctu_ddr0_dram_cken));
dffrl_async_ns u_ctu_ddr1_dram_cken_async_nsr(
.din (ctu_ddr1_dram_cken_muxed),
.clk (dram_gclk),
.rst_l(io_pwron_rst_l),
.q (ctu_ddr1_dram_cken));
dffrl_async_ns u_ctu_ddr2_dram_cken_async_nsr(
.din (ctu_ddr2_dram_cken_muxed),
.clk (dram_gclk),
.rst_l(io_pwron_rst_l),
.q (ctu_ddr2_dram_cken));
dffrl_async_ns u_ctu_ddr3_dram_cken_async_nsr(
.din (ctu_ddr3_dram_cken_muxed),
.clk (dram_gclk),
.rst_l(io_pwron_rst_l),
.q (ctu_ddr3_dram_cken));
// -----------------------------------------
//
// sync edge logic
//
// -----------------------------------------
dffsl_async_ns u_cnt_ld(
.din (1'b0),
.clk (dram_gclk),
.set_l (start_clk_early_jl),
.q(cnt_ld));
assign lcm_cnt_minus_1 = lcm_cnt - 10'h001;
assign lcm_cnt_nxt = cnt_ld? shadreg_div_dmult[9:0]:
(|(lcm_cnt[9:1])) ? lcm_cnt_minus_1 : shadreg_div_dmult[9:0];
dffrl_async_ns #(10) u_lcm_ff (
.din (lcm_cnt_nxt),
.clk (dram_gclk),
.rst_l (start_clk_early_jl),
.q(lcm_cnt));
assign lcm_cnt_zero = ~(|(lcm_cnt[9:1]));
/************************************************************
* Grst logic
************************************************************/
assign dram_grst_l_nxt = (lcm_cnt == `DRAM_GLOBAL_LATENCY) & grst_en_window? 1'b1:
a_grst_dg? 1'b0:
dram_grst_out_l;
dffrl_async_ns u_dram_grst_jl_l(
.din (dram_grst_l_nxt & start_clk_dg),
.clk (dram_gclk),
.rst_l(io_pwron_rst_l),
.q(dram_grst_out_l));
assign dram_dbginit_l_nxt =
(a_dbginit_dg|a_grst_dg) ? 1'b0:
(lcm_cnt == `DRAM_GLOBAL_LATENCY) & dbginit_en_window? 1'b1:
dram_gdbginit_out_l;
dffrl_async_ns u_dram_dbginit_l(
.din (dram_dbginit_l_nxt & start_clk_dg),
.clk (dram_gclk),
.rst_l(io_pwron_rst_l),
.q(dram_gdbginit_out_l));
assign grst_en_window_nxt = de_grst_dsync_edge_dg & lcm_cnt_zero ? 1'b1:
lcm_cnt_zero & grst_en_window ? 1'b0:
grst_en_window;
dffrl_async_ns u_grst_en_window( .din (grst_en_window_nxt & start_clk_dg),
.clk (dram_gclk),
.rst_l(io_pwron_rst_l),
.q(grst_en_window));
assign dbginit_en_window_nxt = de_dbginit_dsync_edge_dg & lcm_cnt_zero ? 1'b1:
lcm_cnt_zero & dbginit_en_window ? 1'b0:
dbginit_en_window;
dffrl_async_ns u_dbginit_en_window( .din (dbginit_en_window_nxt & start_clk_dg ),
.clk (dram_gclk),
.rst_l(io_pwron_rst_l),
.q(dbginit_en_window));
endmodule // dramif
// Local Variables:
// verilog-library-directories:("." "../common/rtl")
// verilog-auto-sense-defines-constant:t
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLRTP_1_V
`define SKY130_FD_SC_HVL__DLRTP_1_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dlrtp_1 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dlrtp_1 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLRTP_1_V
|
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2018, Darryl Ring.
//
// This program is free software: you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation, either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <https://www.gnu.org/licenses/>.
//
// Additional permission under GNU GPL version 3 section 7:
// If you modify this program, or any covered work, by linking or combining it
// with independent modules provided by the FPGA vendor only (this permission
// does not extend to any 3rd party modules, "soft cores" or macros) under
// different license terms solely for the purpose of generating binary
// "bitstream" files and/or simulating the code, the copyright holders of this
// program give you the right to distribute the covered work without those
// independent modules as long as the source code for them is available from
// the FPGA vendor free of charge, and there is no dependence on any encrypted
// modules for simulating of the combined code. This permission applies to you
// if the distributed code contains all the components and scripts required to
// completely simulate it with at least one of the Free Software programs.
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module ad5545
(
input wire clk,
input wire rstn,
input wire [31:0] data,
input wire valid,
output wire ready,
output wire cs,
output wire din,
output wire ldac,
output wire sclk
);
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_WRITE_DAC1 = 3'd1,
STATE_WRITE_DAC2 = 3'd2,
STATE_LOAD = 3'd3,
STATE_WAIT = 3'd4;
reg [2:0] state_reg, state_next;
reg [6:0] count_reg, count_next;
reg [35:0] data_reg, data_next;
reg ready_reg, ready_next;
reg cs_reg, cs_next;
reg din_reg, din_next;
reg ldac_reg, ldac_next;
reg sclk_reg, sclk_next;
reg sclk_enable;
assign ready = ready_reg;
assign cs = cs_reg;
assign din = din_reg;
assign ldac = ldac_reg;
assign sclk = sclk_reg;
always @* begin
state_next = STATE_IDLE;
cs_next = cs_reg;
din_next = din_reg;
ldac_next = ldac_reg;
sclk_next = sclk_reg;
count_next = count_reg;
data_next = data_reg;
ready_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
if (ready & valid) begin
data_next = {2'b01, data[31:16], 2'b10, data[15:0]};
ready_next = 1'b0;
state_next = STATE_WRITE_DAC1;
end else begin
ready_next = 1'b1;
end
end
STATE_WRITE_DAC1: begin
state_next = STATE_WRITE_DAC1;
count_next = count_reg + 1;
sclk_next = count_reg[0];
if (count_reg == 7'h02) begin
cs_next = 1'b0;
end
if (count_reg >= 7'h02 && count_reg[0] == 1'b0) begin
{din_next, data_next} = {data_reg, 1'b0};
end
if (count_reg == 7'h26) begin
cs_next = 1'b1;
count_next = 7'b0;
state_next = STATE_WRITE_DAC2;
end
end
STATE_WRITE_DAC2: begin
state_next = STATE_WRITE_DAC2;
count_next = count_reg + 1;
sclk_next = count_reg[0];
if (count_reg == 7'h02) begin
cs_next = 1'b0;
end
if (count_reg >= 7'h04 && count_reg[0] == 1'b0) begin
{din_next, data_next} = {data_reg, 1'b0};
end
if (count_reg == 7'h26) begin
cs_next = 1'b1;
count_next = 7'b0;
state_next = STATE_LOAD;
end
end
STATE_LOAD: begin
state_next = STATE_LOAD;
count_next = count_reg + 1;
if (count_reg[0] == 1'b1) begin
ldac_next = ~ldac_reg;
end
if (count_reg[2] == 1'b1) begin
state_next = STATE_WAIT;
count_next = 7'b0;
end
end
STATE_WAIT: begin
state_next = STATE_WAIT;
count_next = count_reg + 1;
if (count_reg == 7'h0e) begin
state_next = STATE_IDLE;
count_next = 7'b0;
end
end
endcase
end
always @(posedge clk) begin
if (~rstn) begin
state_reg <= STATE_IDLE;
data_reg <= 16'b0;
ready_reg <= 1'b0;
count_reg <= 7'b0;
cs_reg <= 1'b1;
din_reg <= 1'b0;
ldac_reg <= 1'b1;
sclk_reg <= 1'b0;
end else begin
state_reg <= state_next;
data_reg <= data_next;
count_reg <= count_next;
ready_reg <= ready_next;
cs_reg <= cs_next;
din_reg <= din_next;
ldac_reg <= ldac_next;
sclk_reg <= sclk_next;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_SIO_MACRO_BLACKBOX_V
`define SKY130_FD_IO__TOP_SIO_MACRO_BLACKBOX_V
/**
* top_sio_macro: sky130_fd_io__sio_macro consists of two SIO cells
* and a reference generator cell.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_sio_macro (
AMUXBUS_A ,
AMUXBUS_B ,
VINREF_DFT ,
VOUTREF_DFT ,
DFT_REFGEN ,
HLD_H_N_REFGEN ,
IBUF_SEL_REFGEN ,
ENABLE_VDDA_H ,
ENABLE_H ,
VOHREF ,
VREG_EN_REFGEN ,
VTRIP_SEL_REFGEN,
TIE_LO_ESD ,
IN_H ,
IN ,
PAD_A_NOESD_H ,
PAD ,
PAD_A_ESD_1_H ,
PAD_A_ESD_0_H ,
SLOW ,
VTRIP_SEL ,
HLD_H_N ,
VREG_EN ,
VOH_SEL ,
INP_DIS ,
HLD_OVR ,
OE_N ,
VREF_SEL ,
IBUF_SEL ,
DM0 ,
DM1 ,
OUT
);
inout AMUXBUS_A ;
inout AMUXBUS_B ;
inout VINREF_DFT ;
inout VOUTREF_DFT ;
input DFT_REFGEN ;
input HLD_H_N_REFGEN ;
input IBUF_SEL_REFGEN ;
input ENABLE_VDDA_H ;
input ENABLE_H ;
input VOHREF ;
input VREG_EN_REFGEN ;
input VTRIP_SEL_REFGEN;
output [1:0] TIE_LO_ESD ;
output [1:0] IN_H ;
output [1:0] IN ;
inout [1:0] PAD_A_NOESD_H ;
inout [1:0] PAD ;
inout [1:0] PAD_A_ESD_1_H ;
inout [1:0] PAD_A_ESD_0_H ;
input [1:0] SLOW ;
input [1:0] VTRIP_SEL ;
input [1:0] HLD_H_N ;
input [1:0] VREG_EN ;
input [2:0] VOH_SEL ;
input [1:0] INP_DIS ;
input [1:0] HLD_OVR ;
input [1:0] OE_N ;
input [1:0] VREF_SEL ;
input [1:0] IBUF_SEL ;
input [2:0] DM0 ;
input [2:0] DM1 ;
input [1:0] OUT ;
// Voltage supply signals
supply1 VCCD ;
supply1 VCCHIB ;
supply1 VDDA ;
supply1 VDDIO ;
supply1 VDDIO_Q;
supply0 VSSD ;
supply0 VSSIO ;
supply0 VSSIO_Q;
supply1 VSWITCH;
supply0 VSSA ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_SIO_MACRO_BLACKBOX_V
|
/*
Andrew Mattheisen
Zhiyang Ong
EE-577b 2007 fall
VITERBI DECODER
spd module
@modified by Zhiyang Ong on November 1, 2007
The output out signal must be of the data type reg
I had to reallocate this data-type reg.
Correction: It is relabelled to the wire data type since
it is not used again, or explicitly assigned a value in
this module
*/
/*
`include "spdu.v"
`include "demux2to4.v"
`include "selector.v"
*/
module spd (d0, d1, d2, d3, pm0, pm1, pm2, pm3, out, clk, reset);
// outputs
output out;
// inputs
input d0, d1, d2, d3;
input [3:0] pm0, pm1, pm2, pm3;
input clk, reset;
// @modified by Zhiyang Ong on November 1, 2007
// Registers...
// reg out;
/*
reg selectord0, selectord1;
reg spdu0out0, spdu0out1, spdu0out2, spdu0out3;
reg spdu1out0, spdu1out1, spdu1out2, spdu1out3;
reg spdu2out0, spdu2out1, spdu2out2, spdu2out3;
reg spdu3out0, spdu3out1, spdu3out2, spdu3out3;
reg spdu4out0, spdu4out1, spdu4out2, spdu4out3;
reg spdu5out0, spdu5out1, spdu5out2, spdu5out3;
reg spdu6out0, spdu6out1, spdu6out2, spdu6out3;
reg spdu7out0, spdu7out1, spdu7out2, spdu7out3;
reg spdu8out0, spdu8out1, spdu8out2, spdu8out3;
reg spdu9out0, spdu9out1, spdu9out2, spdu9out3;
reg spdu10out0, spdu10out1, spdu10out2, spdu10out3;
reg spdu11out0, spdu11out1, spdu11out2, spdu11out3;
reg spdu12out0, spdu12out1, spdu12out2, spdu12out3;
reg spdu13out0, spdu13out1, spdu13out2, spdu13out3;
reg spdu14out0, spdu14out1, spdu14out2, spdu14out3;
*/
// wires
// @Modified by Zhiyang Ong on November 1, 2007
wire out;
wire selectord0, selectord1;
wire spdu0out0, spdu0out1, spdu0out2, spdu0out3;
wire spdu1out0, spdu1out1, spdu1out2, spdu1out3;
wire spdu2out0, spdu2out1, spdu2out2, spdu2out3;
wire spdu3out0, spdu3out1, spdu3out2, spdu3out3;
wire spdu4out0, spdu4out1, spdu4out2, spdu4out3;
wire spdu5out0, spdu5out1, spdu5out2, spdu5out3;
wire spdu6out0, spdu6out1, spdu6out2, spdu6out3;
wire spdu7out0, spdu7out1, spdu7out2, spdu7out3;
wire spdu8out0, spdu8out1, spdu8out2, spdu8out3;
wire spdu9out0, spdu9out1, spdu9out2, spdu9out3;
wire spdu10out0, spdu10out1, spdu10out2, spdu10out3;
wire spdu11out0, spdu11out1, spdu11out2, spdu11out3;
wire spdu12out0, spdu12out1, spdu12out2, spdu12out3;
wire spdu13out0, spdu13out1, spdu13out2, spdu13out3;
wire spdu14out0, spdu14out1, spdu14out2, spdu14out3;
spdu spdu0(1'b0,
1'b0,
1'b1,
1'b1, d0, d1, d2, d3,
spdu0out0,
spdu0out1,
spdu0out2,
spdu0out3, clk, reset);
spdu spdu1(spdu0out0,
spdu0out1,
spdu0out2,
spdu0out3, d0, d1, d2, d3,
spdu1out0,
spdu1out1,
spdu1out2,
spdu1out3, clk, reset);
spdu spdu2(spdu1out0,
spdu1out1,
spdu1out2,
spdu1out3, d0, d1, d2, d3,
spdu2out0,
spdu2out1,
spdu2out2,
spdu2out3, clk, reset);
spdu spdu3(spdu2out0,
spdu2out1,
spdu2out2,
spdu2out3, d0, d1, d2, d3,
spdu3out0,
spdu3out1,
spdu3out2,
spdu3out3, clk, reset);
spdu spdu4(spdu3out0,
spdu3out1,
spdu3out2,
spdu3out3, d0, d1, d2, d3,
spdu4out0,
spdu4out1,
spdu4out2,
spdu4out3, clk, reset);
spdu spdu5(spdu4out0,
spdu4out1,
spdu4out2,
spdu4out3, d0, d1, d2, d3,
spdu5out0,
spdu5out1,
spdu5out2,
spdu5out3, clk, reset);
spdu spdu6(spdu5out0,
spdu5out1,
spdu5out2,
spdu5out3, d0, d1, d2, d3,
spdu6out0,
spdu6out1,
spdu6out2,
spdu6out3, clk, reset);
spdu spdu7(spdu6out0,
spdu6out1,
spdu6out2,
spdu6out3, d0, d1, d2, d3,
spdu7out0,
spdu7out1,
spdu7out2,
spdu7out3, clk, reset);
spdu spdu8(spdu7out0,
spdu7out1,
spdu7out2,
spdu7out3, d0, d1, d2, d3,
spdu8out0,
spdu8out1,
spdu8out2,
spdu8out3, clk, reset);
spdu spdu9(spdu8out0,
spdu8out1,
spdu8out2,
spdu8out3, d0, d1, d2, d3,
spdu9out0,
spdu9out1,
spdu9out2,
spdu9out3, clk, reset);
spdu spdu10(spdu9out0,
spdu9out1,
spdu9out2,
spdu9out3, d0, d1, d2, d3,
spdu10out0,
spdu10out1,
spdu10out2,
spdu10out3, clk, reset);
spdu spdu11(spdu10out0,
spdu10out1,
spdu10out2,
spdu10out3, d0, d1, d2, d3,
spdu11out0,
spdu11out1,
spdu11out2,
spdu11out3, clk, reset);
spdu spdu12(spdu11out0,
spdu11out1,
spdu11out2,
spdu11out3, d0, d1, d2, d3,
spdu12out0,
spdu12out1,
spdu12out2,
spdu12out3, clk, reset);
spdu spdu13(spdu12out0,
spdu12out1,
spdu12out2,
spdu12out3, d0, d1, d2, d3,
spdu13out0,
spdu13out1,
spdu13out2,
spdu13out3, clk, reset);
spdu spdu14(spdu13out0,
spdu13out1,
spdu13out2,
spdu13out3, d0, d1, d2, d3,
spdu14out0,
spdu14out1,
spdu14out2,
spdu14out3, clk, reset);
selector selector1 (pm0, pm1, pm2, pm3, selectord0, selectord1);
demux demux1 (spdu14out0, spdu14out1, spdu14out2, spdu14out3,
selectord0, selectord1, out);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module cf_h2v (
// hdmi interface
hdmi_clk,
hdmi_data,
// vdma interface
vdma_clk,
vdma_fs,
vdma_fs_ret,
vdma_valid,
vdma_be,
vdma_data,
vdma_last,
vdma_ready,
// processor interface
up_rstn,
up_clk,
up_sel,
up_rwn,
up_addr,
up_wdata,
up_rdata,
up_ack,
up_status,
// debug interface (chipscope)
vdma_dbg_data,
vdma_dbg_trigger,
hdmi_dbg_data,
hdmi_dbg_trigger);
// hdmi interface
input hdmi_clk;
input [15:0] hdmi_data;
// vdma interface
input vdma_clk;
output vdma_fs;
input vdma_fs_ret;
output vdma_valid;
output [ 7:0] vdma_be;
output [63:0] vdma_data;
output vdma_last;
input vdma_ready;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_rwn;
input [ 4:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
output [ 3:0] up_status;
// debug interface (chipscope)
output [39:0] vdma_dbg_data;
output [ 7:0] vdma_dbg_trigger;
output [61:0] hdmi_dbg_data;
output [ 7:0] hdmi_dbg_trigger;
reg up_crcb_init = 'd0;
reg up_align_right = 'd0;
reg up_tpg_enable = 'd0;
reg up_csc_bypass = 'd0;
reg up_edge_sel = 'd0;
reg up_enable = 'd0;
reg [15:0] up_vs_count = 'd0;
reg [15:0] up_hs_count = 'd0;
reg up_hdmi_hs_mismatch_hold = 'd0;
reg up_hdmi_vs_mismatch_hold = 'd0;
reg up_hdmi_oos_hold = 'd0;
reg up_hdmi_tpm_oos_hold = 'd0;
reg up_vdma_ovf_hold = 'd0;
reg up_vdma_unf_hold = 'd0;
reg up_vdma_tpm_oos_hold = 'd0;
reg [ 3:0] up_status = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_sel_d = 'd0;
reg up_sel_2d = 'd0;
reg up_ack = 'd0;
reg up_hdmi_hs_toggle_m1 = 'd0;
reg up_hdmi_hs_toggle_m2 = 'd0;
reg up_hdmi_hs_toggle_m3 = 'd0;
reg up_hdmi_hs_mismatch = 'd0;
reg [15:0] up_hdmi_hs = 'd0;
reg up_hdmi_vs_toggle_m1 = 'd0;
reg up_hdmi_vs_toggle_m2 = 'd0;
reg up_hdmi_vs_toggle_m3 = 'd0;
reg up_hdmi_vs_mismatch = 'd0;
reg [15:0] up_hdmi_vs = 'd0;
reg up_hdmi_tpm_oos_m1 = 'd0;
reg up_hdmi_tpm_oos = 'd0;
reg up_hdmi_oos_m1 = 'd0;
reg up_hdmi_oos = 'd0;
reg up_vdma_ovf_m1 = 'd0;
reg up_vdma_ovf = 'd0;
reg up_vdma_unf_m1 = 'd0;
reg up_vdma_unf = 'd0;
reg up_vdma_tpm_oos_m1 = 'd0;
reg up_vdma_tpm_oos = 'd0;
wire up_wr_s;
wire up_ack_s;
wire up_hdmi_hs_toggle_s;
wire up_hdmi_vs_toggle_s;
wire hdmi_hs_count_mismatch_s;
wire hdmi_hs_count_toggle_s;
wire [15:0] hdmi_hs_count_s;
wire hdmi_vs_count_mismatch_s;
wire hdmi_vs_count_toggle_s;
wire [15:0] hdmi_vs_count_s;
wire hdmi_tpm_oos_s;
wire hdmi_oos_s;
wire hdmi_fs_toggle_s;
wire [ 8:0] hdmi_fs_waddr_s;
wire hdmi_wr_s;
wire [ 8:0] hdmi_waddr_s;
wire [48:0] hdmi_wdata_s;
wire hdmi_waddr_rel_toggle_s;
wire [ 8:0] hdmi_waddr_rel_s;
wire [ 8:0] hdmi_waddr_g_s;
wire vdma_ovf_s;
wire vdma_unf_s;
wire vdma_tpm_oos_s;
// processor write interface (see regmap.txt for details)
assign up_wr_s = up_sel & ~up_rwn;
assign up_ack_s = up_sel_d & ~up_sel_2d;
// Whenever a register write happens up_toggle is toggled to notify the HDMI
// clock domain that it should update its registers. We need to be careful
// though to not toggle to fast, e.g. if the HDMI clock is running at slower
// rate than the AXI clock it is possible that two consecutive writes happen
// so fast that the toggled signal is not seen in the HDMI domain. Hence we
// synchronize the toggle signal from the HDMI domain back to the AXI domain.
// And only if both signals match, the original toggle signal and the one
// returned from the HDMI domain, we may toggle again.
reg [1:0] up_toggle_ret;
reg up_pending;
reg up_toggle;
wire hdmi_up_toggle_ret;
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_toggle <= 'b0;
up_toggle_ret <= 'b0;
end else begin
up_toggle_ret[0] <= hdmi_up_toggle_ret;
up_toggle_ret[1] <= up_toggle_ret[0];
if (up_wr_s == 1'b1) begin
up_pending <= 1'b1;
end else if (up_pending == 1'b1 && up_toggle_ret[1] == up_toggle) begin
up_toggle <= ~up_toggle;
up_pending <= 1'b0;
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_crcb_init <= 'd0;
up_align_right <= 'd0;
up_tpg_enable <= 'd0;
up_csc_bypass <= 'd0;
up_edge_sel <= 'd0;
up_enable <= 'd0;
up_vs_count <= 'd0;
up_hs_count <= 'd0;
up_hdmi_hs_mismatch_hold <= 'd0;
up_hdmi_vs_mismatch_hold <= 'd0;
up_hdmi_oos_hold <= 'd0;
up_hdmi_tpm_oos_hold <= 'd0;
up_vdma_ovf_hold <= 'd0;
up_vdma_unf_hold <= 'd0;
up_vdma_tpm_oos_hold <= 'd0;
up_status <= 'd0;
end else begin
if ((up_addr == 5'h1) && (up_wr_s == 1'b1)) begin
up_crcb_init <= up_wdata[5];
up_align_right <= up_wdata[4];
up_tpg_enable <= up_wdata[3];
up_csc_bypass <= up_wdata[2];
up_edge_sel <= up_wdata[1];
up_enable <= up_wdata[0];
end
if ((up_addr == 5'h2) && (up_wr_s == 1'b1)) begin
up_vs_count <= up_wdata[31:16];
up_hs_count <= up_wdata[15:0];
end
if (up_hdmi_hs_mismatch == 1'b1) begin
up_hdmi_hs_mismatch_hold <= 1'b1;
end else if ((up_addr == 5'h3) && (up_wr_s == 1'b1)) begin
up_hdmi_hs_mismatch_hold <= up_hdmi_hs_mismatch_hold & ~up_wdata[6];
end
if (up_hdmi_vs_mismatch == 1'b1) begin
up_hdmi_vs_mismatch_hold <= 1'b1;
end else if ((up_addr == 5'h3) && (up_wr_s == 1'b1)) begin
up_hdmi_vs_mismatch_hold <= up_hdmi_vs_mismatch_hold & ~up_wdata[5];
end
if (up_hdmi_oos == 1'b1) begin
up_hdmi_oos_hold <= 1'b1;
end else if ((up_addr == 5'h3) && (up_wr_s == 1'b1)) begin
up_hdmi_oos_hold <= up_hdmi_oos_hold & ~up_wdata[4];
end
if (up_hdmi_tpm_oos == 1'b1) begin
up_hdmi_tpm_oos_hold <= 1'b1;
end else if ((up_addr == 5'h3) && (up_wr_s == 1'b1)) begin
up_hdmi_tpm_oos_hold <= up_hdmi_tpm_oos_hold & ~up_wdata[3];
end
if (up_vdma_ovf == 1'b1) begin
up_vdma_ovf_hold <= 1'b1;
end else if ((up_addr == 5'h3) && (up_wr_s == 1'b1)) begin
up_vdma_ovf_hold <= up_vdma_ovf_hold & ~up_wdata[2];
end
if (up_vdma_unf == 1'b1) begin
up_vdma_unf_hold <= 1'b1;
end else if ((up_addr == 5'h3) && (up_wr_s == 1'b1)) begin
up_vdma_unf_hold <= up_vdma_unf_hold & ~up_wdata[1];
end
if (up_vdma_tpm_oos == 1'b1) begin
up_vdma_tpm_oos_hold <= 1'b1;
end else if ((up_addr == 5'h3) && (up_wr_s == 1'b1)) begin
up_vdma_tpm_oos_hold <= up_vdma_tpm_oos_hold & ~up_wdata[0];
end
up_status <= {up_enable, (up_hdmi_hs_mismatch_hold | up_hdmi_vs_mismatch_hold | up_hdmi_oos_hold),
(up_hdmi_tpm_oos_hold | up_vdma_tpm_oos_hold), (up_vdma_ovf_hold | up_vdma_unf_hold)};
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_sel_d <= 'd0;
up_sel_2d <= 'd0;
up_ack <= 'd0;
end else begin
case (up_addr)
5'h0: up_rdata <= 32'h00010061;
5'h1: up_rdata <= {26'd0, up_crcb_init, up_align_right, up_tpg_enable,
up_csc_bypass, up_edge_sel, up_enable};
5'h2: up_rdata <= {up_vs_count, up_hs_count};
5'h3: up_rdata <= {25'd0, up_hdmi_hs_mismatch_hold, up_hdmi_vs_mismatch_hold,
up_hdmi_oos_hold, up_hdmi_tpm_oos_hold, up_vdma_ovf_hold,
up_vdma_unf_hold, up_vdma_tpm_oos_hold};
5'h4: up_rdata <= {up_hdmi_vs, up_hdmi_hs};
default: up_rdata <= 0;
endcase
up_sel_d <= up_sel;
up_sel_2d <= up_sel_d;
up_ack <= up_ack_s;
end
end
// the hdmi data signals are transferred to the processor side using toggles
// others are simply double registered
assign up_hdmi_hs_toggle_s = up_hdmi_hs_toggle_m3 ^ up_hdmi_hs_toggle_m2;
assign up_hdmi_vs_toggle_s = up_hdmi_vs_toggle_m3 ^ up_hdmi_vs_toggle_m2;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_hdmi_hs_toggle_m1 <= 'd0;
up_hdmi_hs_toggle_m2 <= 'd0;
up_hdmi_hs_toggle_m3 <= 'd0;
up_hdmi_hs_mismatch <= 'd0;
up_hdmi_hs <= 'd0;
up_hdmi_vs_toggle_m1 <= 'd0;
up_hdmi_vs_toggle_m2 <= 'd0;
up_hdmi_vs_toggle_m3 <= 'd0;
up_hdmi_vs_mismatch <= 'd0;
up_hdmi_vs <= 'd0;
up_hdmi_tpm_oos_m1 <= 'd0;
up_hdmi_tpm_oos <= 'd0;
up_hdmi_oos_m1 <= 'd0;
up_hdmi_oos <= 'd0;
up_vdma_ovf_m1 <= 'd0;
up_vdma_ovf <= 'd0;
up_vdma_unf_m1 <= 'd0;
up_vdma_unf <= 'd0;
up_vdma_tpm_oos_m1 <= 'd0;
up_vdma_tpm_oos <= 'd0;
end else begin
up_hdmi_hs_toggle_m1 <= hdmi_hs_count_toggle_s;
up_hdmi_hs_toggle_m2 <= up_hdmi_hs_toggle_m1;
up_hdmi_hs_toggle_m3 <= up_hdmi_hs_toggle_m2;
if (up_hdmi_hs_toggle_s == 1'b1) begin
up_hdmi_hs_mismatch <= hdmi_hs_count_mismatch_s;
up_hdmi_hs <= hdmi_hs_count_s;
end
up_hdmi_vs_toggle_m1 <= hdmi_vs_count_toggle_s;
up_hdmi_vs_toggle_m2 <= up_hdmi_vs_toggle_m1;
up_hdmi_vs_toggle_m3 <= up_hdmi_vs_toggle_m2;
if (up_hdmi_vs_toggle_s == 1'b1) begin
up_hdmi_vs_mismatch <= hdmi_vs_count_mismatch_s;
up_hdmi_vs <= hdmi_vs_count_s;
end
up_hdmi_tpm_oos_m1 <= hdmi_tpm_oos_s;
up_hdmi_tpm_oos <= up_hdmi_tpm_oos_m1;
up_hdmi_oos_m1 <= hdmi_oos_s;
up_hdmi_oos <= up_hdmi_oos_m1;
up_vdma_ovf_m1 <= vdma_ovf_s;
up_vdma_ovf <= up_vdma_ovf_m1;
up_vdma_unf_m1 <= vdma_unf_s;
up_vdma_unf <= up_vdma_unf_m1;
up_vdma_tpm_oos_m1 <= vdma_tpm_oos_s;
up_vdma_tpm_oos <= up_vdma_tpm_oos_m1;
end
end
// hdmi interface
cf_h2v_hdmi i_hdmi (
.hdmi_clk (hdmi_clk),
.hdmi_data (hdmi_data),
.hdmi_hs_count_mismatch (hdmi_hs_count_mismatch_s),
.hdmi_hs_count_toggle (hdmi_hs_count_toggle_s),
.hdmi_hs_count (hdmi_hs_count_s),
.hdmi_vs_count_mismatch (hdmi_vs_count_mismatch_s),
.hdmi_vs_count_toggle (hdmi_vs_count_toggle_s),
.hdmi_vs_count (hdmi_vs_count_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.hdmi_oos (hdmi_oos_s),
.hdmi_fs_toggle (hdmi_fs_toggle_s),
.hdmi_fs_waddr (hdmi_fs_waddr_s),
.hdmi_wr (hdmi_wr_s),
.hdmi_waddr (hdmi_waddr_s),
.hdmi_wdata (hdmi_wdata_s),
.hdmi_waddr_rel_toggle (hdmi_waddr_rel_toggle_s),
.hdmi_waddr_rel (hdmi_waddr_rel_s),
.hdmi_waddr_g (hdmi_waddr_g_s),
.up_toggle (up_toggle),
.hdmi_up_toggle_ret (hdmi_up_toggle_ret),
.up_enable (up_enable),
.up_crcb_init (up_crcb_init),
.up_edge_sel (up_edge_sel),
.up_hs_count (up_hs_count),
.up_vs_count (up_vs_count),
.up_csc_bypass (up_csc_bypass),
.up_tpg_enable (up_tpg_enable),
.debug_data (hdmi_dbg_data),
.debug_trigger (hdmi_dbg_trigger));
// vdma interface
cf_h2v_vdma i_vdma (
.hdmi_clk (hdmi_clk),
.hdmi_fs_toggle (hdmi_fs_toggle_s),
.hdmi_fs_waddr (hdmi_fs_waddr_s),
.hdmi_wr (hdmi_wr_s),
.hdmi_waddr (hdmi_waddr_s),
.hdmi_wdata (hdmi_wdata_s),
.hdmi_waddr_rel_toggle (hdmi_waddr_rel_toggle_s),
.hdmi_waddr_rel (hdmi_waddr_rel_s),
.hdmi_waddr_g (hdmi_waddr_g_s),
.vdma_clk (vdma_clk),
.vdma_fs (vdma_fs),
.vdma_fs_ret (vdma_fs_ret),
.vdma_valid (vdma_valid),
.vdma_be (vdma_be),
.vdma_data (vdma_data),
.vdma_last (vdma_last),
.vdma_ready (vdma_ready),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s),
.vdma_tpm_oos (vdma_tpm_oos_s),
.up_align_right (up_align_right),
.debug_data (vdma_dbg_data),
.debug_trigger (vdma_dbg_trigger));
endmodule
// ***************************************************************************
// *************************************************************************** |
module wb_stream_writer
#(parameter WB_DW = 32,
parameter WB_AW = 32,
parameter FIFO_AW = 0,
parameter MAX_BURST_LEN = 2**FIFO_AW)
(input clk,
input rst,
//Wisbhone memory interface
output [WB_AW-1:0] wbm_adr_o,
output [WB_DW-1:0] wbm_dat_o,
output [WB_DW/8-1:0] wbm_sel_o,
output wbm_we_o ,
output wbm_cyc_o,
output wbm_stb_o,
output [2:0] wbm_cti_o,
output [1:0] wbm_bte_o,
input [WB_DW-1:0] wbm_dat_i,
input wbm_ack_i,
input wbm_err_i,
//Stream interface
output [WB_DW-1:0] stream_m_data_o,
output stream_m_valid_o,
input stream_m_ready_i,
output stream_m_irq_o,
//Configuration interface
input [4:0] wbs_adr_i,
input [WB_DW-1:0] wbs_dat_i,
input [WB_DW/8-1:0] wbs_sel_i,
input wbs_we_i ,
input wbs_cyc_i,
input wbs_stb_i,
input [2:0] wbs_cti_i,
input [1:0] wbs_bte_i,
output [WB_DW-1:0] wbs_dat_o,
output wbs_ack_o,
output wbs_err_o);
//FIFO interface
wire [WB_DW-1:0] fifo_din;
wire [FIFO_AW:0] fifo_cnt;
wire fifo_rd;
wire fifo_wr;
//Configuration parameters
wire enable;
wire [WB_DW-1:0] tx_cnt;
wire [WB_AW-1:0] start_adr;
wire [WB_AW-1:0] buf_size;
wire [WB_AW-1:0] burst_size;
wire busy;
wb_stream_writer_ctrl
#(.WB_AW (WB_AW),
.WB_DW (WB_DW),
.FIFO_AW (FIFO_AW),
.MAX_BURST_LEN (MAX_BURST_LEN))
ctrl
(.wb_clk_i (clk),
.wb_rst_i (rst),
//Stream data output
.wbm_adr_o (wbm_adr_o),
.wbm_dat_o (wbm_dat_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_cyc_o (wbm_cyc_o),
.wbm_stb_o (wbm_stb_o),
.wbm_cti_o (wbm_cti_o),
.wbm_bte_o (wbm_bte_o),
.wbm_dat_i (wbm_dat_i),
.wbm_ack_i (wbm_ack_i),
.wbm_err_i (wbm_err_i),
//FIFO interface
.fifo_d (fifo_din),
.fifo_wr (fifo_wr),
.fifo_cnt (fifo_cnt),
//Configuration interface
.busy (busy),
.enable (enable),
.tx_cnt (tx_cnt),
.start_adr (start_adr),
.buf_size (buf_size),
.burst_size (burst_size));
wb_stream_writer_cfg
#(.WB_AW (WB_AW),
.WB_DW (WB_DW))
cfg
(.wb_clk_i (clk),
.wb_rst_i (rst),
//Wishbone IF
.wb_adr_i (wbs_adr_i),
.wb_dat_i (wbs_dat_i),
.wb_sel_i (wbs_sel_i),
.wb_we_i (wbs_we_i),
.wb_cyc_i (wbs_cyc_i),
.wb_stb_i (wbs_stb_i),
.wb_cti_i (wbs_cti_i),
.wb_bte_i (wbs_bte_i),
.wb_dat_o (wbs_dat_o),
.wb_ack_o (wbs_ack_o),
.wb_err_o (wbs_err_o),
//Application IF
.irq (stream_m_irq_o),
.busy (busy),
.enable (enable),
.tx_cnt (tx_cnt),
.start_adr (start_adr),
.buf_size (buf_size),
.burst_size (burst_size));
wb_stream_writer_fifo
#(.DW (WB_DW),
.AW (FIFO_AW))
fifo0
(.clk (clk),
.rst (rst),
.stream_s_data_i (fifo_din),
.stream_s_valid_i (fifo_wr),
.stream_s_ready_o (),
.stream_m_data_o (stream_m_data_o),
.stream_m_valid_o (stream_m_valid_o),
.stream_m_ready_i (stream_m_ready_i),
.cnt (fifo_cnt));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_BLACKBOX_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_BLACKBOX_V
/**
* lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
* voltage, isolated well on input buffer,
* inverting sleep mode input, zero power
* sleep mode.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_BLACKBOX_V
|
module top (
fpga_clk_50,
fpga_reset_n,
fpga_led_output,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
emac_mdio,
emac_mdc,
emac_tx_ctl,
emac_tx_clk,
emac_txd,
emac_rx_ctl,
emac_rx_clk,
emac_rxd,
hps_usb1_D0,
hps_usb1_D1,
hps_usb1_D2,
hps_usb1_D3,
hps_usb1_D4,
hps_usb1_D5,
hps_usb1_D6,
hps_usb1_D7,
hps_usb1_CLK,
hps_usb1_STP,
hps_usb1_DIR,
hps_usb1_NXT,
sd_cmd,
sd_clk,
sd_d,
uart_rx,
uart_tx,
led,
i2c_sda,
i2c_scl,
///////// VGA /////////
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_N,
VGA_VS
);
input wire fpga_clk_50;
input wire fpga_reset_n;
output wire [3:0] fpga_led_output;
output wire [14:0] memory_mem_a;
output wire [2:0] memory_mem_ba;
output wire memory_mem_ck;
output wire memory_mem_ck_n;
output wire memory_mem_cke;
output wire memory_mem_cs_n;
output wire memory_mem_ras_n;
output wire memory_mem_cas_n;
output wire memory_mem_we_n;
output wire memory_mem_reset_n;
inout wire [31:0] memory_mem_dq;
inout wire [3:0] memory_mem_dqs;
inout wire [3:0] memory_mem_dqs_n;
output wire memory_mem_odt;
output wire [3:0] memory_mem_dm;
input wire memory_oct_rzqin;
inout wire emac_mdio;
output wire emac_mdc;
output wire emac_tx_ctl;
output wire emac_tx_clk;
output wire [3:0] emac_txd;
input wire emac_rx_ctl;
input wire emac_rx_clk;
input wire [3:0] emac_rxd;
inout wire hps_usb1_D0;
inout wire hps_usb1_D1;
inout wire hps_usb1_D2;
inout wire hps_usb1_D3;
inout wire hps_usb1_D4;
inout wire hps_usb1_D5;
inout wire hps_usb1_D6;
inout wire hps_usb1_D7;
input wire hps_usb1_CLK;
output wire hps_usb1_STP;
input wire hps_usb1_DIR;
input wire hps_usb1_NXT;
inout wire sd_cmd;
output wire sd_clk;
inout wire [3:0] sd_d;
input wire uart_rx;
output wire uart_tx;
inout wire led;
inout wire i2c_scl;
inout wire i2c_sda;
///////// VGA /////////
output wire [7:0] VGA_B;
output wire VGA_BLANK_N;
output wire VGA_CLK;
output wire [7:0] VGA_G;
output wire VGA_HS;
output wire [7:0] VGA_R;
output wire VGA_SYNC_N;
output wire VGA_VS;
wire [29:0] fpga_internal_led;
wire kernel_clk;
//=======================================================
// REG/WIRE declarations
//=======================================================
// internal wires and registers declaration
wire clk_65;
wire clk_130;
wire [7:0] vid_r,vid_g,vid_b;
wire vid_v_sync ;
wire vid_h_sync ;
wire vid_datavalid;
//=======================================================
// Structural coding
//=======================================================
assign VGA_BLANK_N = 1'b1;
assign VGA_SYNC_N = 1'b0;
assign VGA_CLK = clk_65;
assign {VGA_B,VGA_G,VGA_R} = {vid_b,vid_g,vid_r};
assign VGA_VS = vid_v_sync;
assign VGA_HS = vid_h_sync;
vga_pll vga_pll_inst(
.refclk(fpga_clk_50), // refclk.clk
.rst(1'b0), // reset.reset
.outclk_0(clk_65), // outclk0.clk
.outclk_1(clk_130), // outclk1.clk
.locked() // locked.export
);
system the_system (
.reset_50_reset_n (fpga_reset_n),
.clk_50_clk (fpga_clk_50),
.kernel_clk_clk (kernel_clk),
.memory_mem_a (memory_mem_a),
.memory_mem_ba (memory_mem_ba),
.memory_mem_ck (memory_mem_ck),
.memory_mem_ck_n (memory_mem_ck_n),
.memory_mem_cke (memory_mem_cke),
.memory_mem_cs_n (memory_mem_cs_n),
.memory_mem_ras_n (memory_mem_ras_n),
.memory_mem_cas_n (memory_mem_cas_n),
.memory_mem_we_n (memory_mem_we_n),
.memory_mem_reset_n (memory_mem_reset_n),
.memory_mem_dq (memory_mem_dq),
.memory_mem_dqs (memory_mem_dqs),
.memory_mem_dqs_n (memory_mem_dqs_n),
.memory_mem_odt (memory_mem_odt),
.memory_mem_dm (memory_mem_dm),
.memory_oct_rzqin (memory_oct_rzqin),
.peripheral_hps_io_emac1_inst_MDIO (emac_mdio),
.peripheral_hps_io_emac1_inst_MDC (emac_mdc),
.peripheral_hps_io_emac1_inst_TX_CLK (emac_tx_clk),
.peripheral_hps_io_emac1_inst_TX_CTL (emac_tx_ctl),
.peripheral_hps_io_emac1_inst_TXD0 (emac_txd[0]),
.peripheral_hps_io_emac1_inst_TXD1 (emac_txd[1]),
.peripheral_hps_io_emac1_inst_TXD2 (emac_txd[2]),
.peripheral_hps_io_emac1_inst_TXD3 (emac_txd[3]),
.peripheral_hps_io_emac1_inst_RX_CLK (emac_rx_clk),
.peripheral_hps_io_emac1_inst_RX_CTL (emac_rx_ctl),
.peripheral_hps_io_emac1_inst_RXD0 (emac_rxd[0]),
.peripheral_hps_io_emac1_inst_RXD1 (emac_rxd[1]),
.peripheral_hps_io_emac1_inst_RXD2 (emac_rxd[2]),
.peripheral_hps_io_emac1_inst_RXD3 (emac_rxd[3]),
.peripheral_hps_io_usb1_inst_D0 (hps_usb1_D0 ), // .hps_io_usb1_inst_D0
.peripheral_hps_io_usb1_inst_D1 (hps_usb1_D1 ), // .hps_io_usb1_inst_D1
.peripheral_hps_io_usb1_inst_D2 (hps_usb1_D2 ), // .hps_io_usb1_inst_D2
.peripheral_hps_io_usb1_inst_D3 (hps_usb1_D3 ), // .hps_io_usb1_inst_D3
.peripheral_hps_io_usb1_inst_D4 (hps_usb1_D4), // .hps_io_usb1_inst_D4
.peripheral_hps_io_usb1_inst_D5 (hps_usb1_D5 ), // .hps_io_usb1_inst_D5
.peripheral_hps_io_usb1_inst_D6 (hps_usb1_D6 ), // .hps_io_usb1_inst_D6
.peripheral_hps_io_usb1_inst_D7 (hps_usb1_D7 ), // .hps_io_usb1_inst_D7
.peripheral_hps_io_usb1_inst_CLK (hps_usb1_CLK ), // .hps_io_usb1_inst_CLK
.peripheral_hps_io_usb1_inst_STP (hps_usb1_STP ), // .hps_io_usb1_inst_STP
.peripheral_hps_io_usb1_inst_DIR (hps_usb1_DIR), // .hps_io_usb1_inst_DIR
.peripheral_hps_io_usb1_inst_NXT (hps_usb1_NXT ), // .hps_io_usb1_inst_NXT
.peripheral_hps_io_sdio_inst_CMD (sd_cmd),
.peripheral_hps_io_sdio_inst_CLK (sd_clk),
.peripheral_hps_io_sdio_inst_D0 (sd_d[0]),
.peripheral_hps_io_sdio_inst_D1 (sd_d[1]),
.peripheral_hps_io_sdio_inst_D2 (sd_d[2]),
.peripheral_hps_io_sdio_inst_D3 (sd_d[3]),
.peripheral_hps_io_uart0_inst_RX (uart_rx),
.peripheral_hps_io_uart0_inst_TX (uart_tx),
.peripheral_hps_io_gpio_inst_GPIO53 (led),
.peripheral_hps_io_i2c1_inst_SDA (i2c_sda),
.peripheral_hps_io_i2c1_inst_SCL (i2c_scl),
//itc
.acl_iface_clock_130_clk (clk_130),
.acl_iface_alt_vip_itc_0_clocked_video_vid_clk (clk_65), // alt_vip_itc_0_clocked_video.vid_clk
.acl_iface_alt_vip_itc_0_clocked_video_vid_data ({vid_r,vid_g,vid_b}), // .vid_data
.acl_iface_alt_vip_itc_0_clocked_video_underflow (), // .underflow
.acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid (vid_datavalid), // .vid_datavalid
.acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync (vid_v_sync), // .vid_v_sync
.acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync (vid_h_sync), // .vid_h_sync
.acl_iface_alt_vip_itc_0_clocked_video_vid_f (), // .vid_f
.acl_iface_alt_vip_itc_0_clocked_video_vid_h (), // .vid_h
.acl_iface_alt_vip_itc_0_clocked_video_vid_v (),
);
// module for visualizing the kernel clock with 4 LEDs
async_counter_30 AC30 (
.clk (kernel_clk),
.count (fpga_internal_led)
);
assign fpga_led_output[3:0] = ~fpga_internal_led[29:26];
endmodule
module async_counter_30(clk, count);
input clk;
output [29:0] count;
reg [14:0] count_a;
reg [14:0] count_b;
initial count_a = 15'b0;
initial count_b = 15'b0;
always @(negedge clk)
count_a <= count_a + 1'b1;
always @(negedge count_a[14])
count_b <= count_b + 1'b1;
assign count = {count_b, count_a};
endmodule
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
//
// RCN bus Serial Port DebuggeR (SPDR - pronounced "spider")
//
// Commands -
// @addr : Set bus address
// #size : Set bus size (b, h, or w)
// =data : Write data at address (and inc by size)
// ? : Read data from address (and inc by size)
// %data : Write GPO
// / : Read GPI
// ! : Read the current bus address/size
//
// All values are in hex and are padded with zero to proper size. Providing
// too many hex digits is ignored as bytes are captured and shifted A backspace
// aborts commands with arguments (@,#,=,%).
//
// The SPDR modules echoes valid entries and prints CrLf after each command.
// User terminals should select the remote echo option.
//
module rcn_spdr
(
input clk,
input clk_50,
input rst,
input [68:0] rcn_in,
output [68:0] rcn_out,
input [31:0] gpi,
output reg gpi_strobe,
output reg [31:0] gpo,
output reg gpo_strobe,
output uart_tx,
input uart_rx
);
parameter MASTER_ID = 0;
parameter SAMPLE_CLK_DIV = 6'd62; // Value for 115200 @ 50 MHz in
reg cs;
wire busy;
reg wr;
reg [3:0] mask;
reg [31:0] addr;
reg [31:0] wdata_final;
wire rdone;
wire wdone;
wire [31:0] rsp_data;
rcn_master #(.MASTER_ID(MASTER_ID)) rcn_master
(
.rst(rst),
.clk(clk),
.rcn_in(rcn_in),
.rcn_out(rcn_out),
.cs(cs),
.seq(2'b00),
.busy(busy),
.wr(wr),
.mask(mask),
.addr(addr[23:0]),
.wdata(wdata_final),
.rdone(rdone),
.wdone(wdone),
.rsp_seq(),
.rsp_mask(),
.rsp_addr(),
.rsp_data(rsp_data)
);
wire tx_busy;
wire tx_vld;
wire [7:0] tx_data;
wire rx_vld;
wire [7:0] rx_data;
rcn_uart_framer #(.SAMPLE_CLK_DIV(SAMPLE_CLK_DIV)) rcn_uart_framer
(
.clk_50(clk_50),
.rst(rst),
.tx_busy(tx_busy),
.tx_vld(tx_vld),
.tx_data(tx_data),
.rx_vld(rx_vld),
.rx_data(rx_data),
.rx_frame_error(),
.uart_tx(uart_tx),
.uart_rx(uart_rx)
);
reg [7:0] tx_byte;
reg tx_push;
wire tx_full;
wire tx_empty;
assign tx_vld = !tx_empty;
rcn_fifo_byte_async tx_fifo
(
.rst_in(rst),
.clk_in(clk),
.clk_out(clk_50),
.din(tx_byte),
.push(tx_push),
.full(tx_full),
.dout(tx_data),
.pop(!tx_busy),
.empty(tx_empty)
);
wire [7:0] rx_byte;
reg rx_pop;
wire rx_empty;
rcn_fifo_byte_async rx_fifo
(
.rst_in(rst),
.clk_in(clk_50),
.clk_out(clk),
.din(rx_data),
.push(rx_vld),
.full(),
.dout(rx_byte),
.pop(rx_pop),
.empty(rx_empty)
);
reg rx_is_num;
reg rx_is_backspace;
reg [3:0] rx_number;
reg [31:0] rx_number_shift;
always @ *
begin
rx_is_num = 1'b1;
rx_is_backspace = 1'b0;
rx_number = 4'd0;
case (rx_byte)
"0": rx_number = 4'h0;
"1": rx_number = 4'h1;
"2": rx_number = 4'h2;
"3": rx_number = 4'h3;
"4": rx_number = 4'h4;
"5": rx_number = 4'h5;
"6": rx_number = 4'h6;
"7": rx_number = 4'h7;
"8": rx_number = 4'h8;
"9": rx_number = 4'h9;
"A": rx_number = 4'hA;
"B": rx_number = 4'hB;
"C": rx_number = 4'hC;
"D": rx_number = 4'hD;
"E": rx_number = 4'hE;
"F": rx_number = 4'hF;
"a": rx_number = 4'hA;
"b": rx_number = 4'hB;
"c": rx_number = 4'hC;
"d": rx_number = 4'hD;
"e": rx_number = 4'hE;
"f": rx_number = 4'hF;
8'h08:
begin
rx_is_num = 1'b0;
rx_is_backspace = 1'b1;
end
default: rx_is_num = 1'b0;
endcase
end
always @ (posedge clk)
if (rx_pop && !rx_is_num)
rx_number_shift <= 32'd0;
else if (rx_pop)
rx_number_shift <= {rx_number_shift[27:0], rx_number};
reg update_addr;
reg inc_addr;
reg update_size;
reg [1:0] size_mode;
reg [2:0] size;
always @ (posedge clk or posedge rst)
if (rst)
addr <= 32'd0;
else if (update_addr)
addr <= rx_number_shift;
else if (inc_addr)
addr <= addr + {29'd0, size};
always @ (posedge clk or posedge rst)
if (rst)
size_mode <= 2'd0;
else if (update_size)
case (rx_byte)
"b": size_mode <= 2'd2;
"h": size_mode <= 2'd1;
"w": size_mode <= 2'd0;
default: size_mode <= 2'd0;
endcase
reg update_wdata;
reg [31:0] wdata;
always @ (posedge clk or posedge rst)
if (rst)
wdata <= 32'd0;
else if (update_wdata)
wdata <= rx_number_shift;
reg update_gpo;
always @ (posedge clk or posedge rst)
if (rst)
gpo <= 32'd0;
else if (update_gpo)
gpo <= rx_number_shift;
always @ (posedge clk)
gpo_strobe <= update_gpo;
reg [31:0] rdata_final;
reg capture_rdata;
reg capture_gpi;
reg capture_addr;
reg capture_shift;
reg [31:0] capture_data;
reg [7:0] capture_byte;
always @ (posedge clk or posedge rst)
if (rst)
capture_data <= 32'd0;
else if (capture_rdata)
capture_data <= rdata_final;
else if (capture_gpi)
capture_data <= gpi;
else if (capture_addr)
capture_data <= addr;
else if (capture_shift)
capture_data <= {capture_data[27:0], 4'd0};
always @ (posedge clk)
gpi_strobe <= capture_gpi;
always @ *
case (capture_data[31:28])
4'h0: capture_byte = "0";
4'h1: capture_byte = "1";
4'h2: capture_byte = "2";
4'h3: capture_byte = "3";
4'h4: capture_byte = "4";
4'h5: capture_byte = "5";
4'h6: capture_byte = "6";
4'h7: capture_byte = "7";
4'h8: capture_byte = "8";
4'h9: capture_byte = "9";
4'hA: capture_byte = "A";
4'hB: capture_byte = "B";
4'hC: capture_byte = "C";
4'hD: capture_byte = "D";
4'hE: capture_byte = "E";
default: capture_byte = "F";
endcase
reg [15:0] bus_timer;
reg bus_timer_rst;
wire bus_timeout = (bus_timer[15:4] == 12'hFFF);
always @ (posedge clk)
if (bus_timer_rst)
bus_timer <= 16'd0;
else if (!bus_timeout)
bus_timer <= bus_timer + 16'd1;
reg [4:0] state;
reg [4:0] next_state;
always @ (posedge clk or posedge rst)
if (rst)
state <= 5'd0;
else
state <= next_state;
always @ *
begin
next_state = state;
cs = 1'b0;
wr = 1'b0;
bus_timer_rst = 1'b0;
rx_pop = 1'b0;
tx_byte = 8'd0;
tx_push = 1'b0;
update_addr = 1'b0;
inc_addr = 1'b0;
update_size = 1'b0;
update_wdata = 1'b0;
update_gpo = 1'b0;
capture_rdata = 1'b0;
capture_gpi = 1'b0;
capture_addr = 1'b0;
capture_shift = 1'b0;
case (state)
5'd0:
if (!rx_empty)
begin
rx_pop = 1'b1;
tx_byte = rx_byte;
tx_push = 1'b1;
case (rx_byte)
"@": next_state = 5'd1;
"#": next_state = 5'd2;
"=": next_state = 5'd3;
"?": next_state = 5'd6;
"%": next_state = 5'd8;
"/": next_state = 5'd9;
"!": next_state = 5'd10;
default: tx_push = 1'b0;
endcase
end
//
// Update addr
//
5'd1:
if (!rx_empty)
begin
rx_pop = 1'b1;
tx_byte = rx_byte;
tx_push = 1'b1;
if (!rx_is_num)
begin
tx_push = 1'b0;
update_addr = !rx_is_backspace;
next_state = 5'd30;
end
end
//
// Update size
//
5'd2:
if (!rx_empty)
begin
rx_pop = 1'b1;
tx_byte = rx_byte;
tx_push = 1'b1;
update_size = !rx_is_backspace;
next_state = 5'd30;
end
//
// Write data
//
5'd3:
if (!rx_empty)
begin
rx_pop = 1'b1;
tx_byte = rx_byte;
tx_push = 1'b1;
if (!rx_is_num)
begin
tx_push = 1'b0;
update_wdata = !rx_is_backspace;
next_state = (rx_is_backspace) ? 5'd30 : state + 5'd1;
end
end
5'd4:
begin
cs = 1'b1;
wr = 1'b1;
bus_timer_rst = 1'b1;
if (!busy)
next_state = state + 5'd1;
end
5'd5:
if (wdone)
begin
inc_addr = 1'b1;
next_state = 5'd30;
end
else if (bus_timeout)
next_state = 5'd12;
//
// Read data
//
5'd6:
begin
cs = 1'b1;
wr = 1'b0;
bus_timer_rst = 1'b1;
if (!busy)
next_state = state + 5'd1;
end
5'd7:
if (rdone)
begin
inc_addr = 1'b1;
capture_rdata = 1'b1;
next_state = 5'd16;
end
else if (bus_timeout)
next_state = 5'd12;
//
// Write gpo
//
5'd8:
if (!rx_empty)
begin
rx_pop = 1'b1;
tx_byte = rx_byte;
tx_push = 1'b1;
if (!rx_is_num)
begin
tx_push = 1'b0;
update_gpo = !rx_is_backspace;
next_state = 5'd30;
end
end
//
// Read gpi
//
5'd9:
begin
capture_gpi = 1'b1;
next_state = 5'd22;
end
//
// Read addr/size
//
5'd10:
if (!tx_full)
begin
case (size_mode)
2'd0: tx_byte = "w";
2'd1: tx_byte = "h";
default: tx_byte = "b";
endcase
tx_push = 1'b1;
next_state = state + 5'd1;
end
5'd11:
if (!tx_full)
begin
tx_byte = "-";
tx_push = 1'b1;
capture_addr = 1'b1;
next_state = 5'd22;
end
//
// Send Error Indicator
//
5'd12:
if (!tx_full)
begin
tx_byte = ":";
tx_push = 1'b1;
next_state = state + 5'd1;
end
5'd13:
if (!tx_full)
begin
tx_byte = "E";
tx_push = 1'b1;
next_state = state + 5'd1;
end
5'd14:
if (!tx_full)
begin
tx_byte = "r";
tx_push = 1'b1;
next_state = state + 5'd1;
end
5'd15:
if (!tx_full)
begin
tx_byte = "r";
tx_push = 1'b1;
next_state = 5'd30;
end
//
// Send capture based on size
//
5'd16:
if (!tx_full)
begin
capture_shift = 1'b1;
tx_byte = capture_byte;
tx_push = size[2];
next_state = state + 5'd1;
end
5'd17:
if (!tx_full)
begin
capture_shift = 1'b1;
tx_byte = capture_byte;
tx_push = size[2];
next_state = state + 5'd1;
end
5'd18:
if (!tx_full)
begin
capture_shift = 1'b1;
tx_byte = capture_byte;
tx_push = size[2];
next_state = state + 5'd1;
end
5'd19:
if (!tx_full)
begin
capture_shift = 1'b1;
tx_byte = capture_byte;
tx_push = size[2];
next_state = state + 5'd1;
end
5'd20:
if (!tx_full)
begin
capture_shift = 1'b1;
tx_byte = capture_byte;
tx_push = |size[2:1];
next_state = state + 5'd1;
end
5'd21:
if (!tx_full)
begin
capture_shift = 1'b1;
tx_byte = capture_byte;
tx_push = |size[2:1];
next_state = 5'd28;
end
//
// Send all of capture data register
//
5'd22:
if (!tx_full)
begin
capture_shift = 1'b1;
tx_byte = capture_byte;
tx_push = 1'b1;
next_state = state + 5'd1;
end
5'd23:
if (!tx_full)
begin
capture_shift = 1'b1;
tx_byte = capture_byte;
tx_push = 1'b1;
next_state = state + 5'd1;
end
5'd24:
if (!tx_full)
begin
capture_shift = 1'b1;
tx_byte = capture_byte;
tx_push = 1'b1;
next_state = state + 5'd1;
end
5'd25:
if (!tx_full)
begin
capture_shift = 1'b1;
tx_byte = capture_byte;
tx_push = 1'b1;
next_state = state + 5'd1;
end
5'd26:
if (!tx_full)
begin
capture_shift = 1'b1;
tx_byte = capture_byte;
tx_push = 1'b1;
next_state = state + 5'd1;
end
5'd27:
if (!tx_full)
begin
capture_shift = 1'b1;
tx_byte = capture_byte;
tx_push = 1'b1;
next_state = state + 5'd1;
end
5'd28:
if (!tx_full)
begin
capture_shift = 1'b1;
tx_byte = capture_byte;
tx_push = 1'b1;
next_state = state + 5'd1;
end
5'd29:
if (!tx_full)
begin
capture_shift = 1'b1;
tx_byte = capture_byte;
tx_push = 1'b1;
next_state = state + 5'd1;
end
//
// Send Cr/Lf and start over
//
5'd30:
if (!tx_full)
begin
tx_byte = 8'h0D;
tx_push = 1'b1;
next_state = state + 5'd1;
end
5'd31:
if (!tx_full)
begin
tx_byte = 8'h0A;
tx_push = 1'b1;
next_state = 5'd0;
end
default: next_state = 5'd0;
endcase
end
always @ *
if (size_mode == 2'd2) // byte
begin
size = 3'd1;
wdata_final = {4{wdata[7:0]}};
case (addr[1:0])
2'b00:
begin
mask = 4'b0001;
rdata_final = {24'd0, rsp_data[7:0]};
end
2'b01:
begin
mask = 4'b0010;
rdata_final = {24'd0, rsp_data[15:8]};
end
2'b10:
begin
mask = 4'b0100;
rdata_final = {24'd0, rsp_data[23:16]};
end
default:
begin
mask = 4'b1000;
rdata_final = {24'd0, rsp_data[31:24]};
end
endcase
end
else if (size_mode == 2'd1) // half
begin
size = 3'd2;
wdata_final = {2{wdata[15:0]}};
if (!addr[1])
begin
mask = 4'b0011;
rdata_final = {16'd0, rsp_data[15:0]};
end
else
begin
mask = 4'b1100;
rdata_final = {16'd0, rsp_data[31:16]};
end
end
else
begin
size = 3'd4;
mask = 4'b1111;
wdata_final = wdata;
rdata_final = rsp_data;
end
endmodule
|
`timescale 1ns / 1ps
module LED7Seg(clk, seg, segsel, data);
// seg bits and led segment:
// 77
// 2 6
// 11
// 3 5
// 44 0
output [7:0] seg;
output [3:0] segsel;
input clk;
input [15:0] data;
reg [18:0] counter;
wire [3:0] v0, v1, v2, v3;
assign v0 = data[3:0];
assign v1 = data[7:4];
assign v2 = data[11:8];
assign v3 = data[15:12];
wire [1:0] dsel = counter[18:17];
assign segsel = ~(1 << dsel);
assign seg = decodev(dsel, v0, v1, v2, v3);
always @ (posedge clk) begin
counter = counter + 1;
end
function [7:0] decodev (
input [1:0] vsel,
input [4:0] v0,
input [4:0] v1,
input [4:0] v2,
input [4:0] v3);
case (vsel)
2'b00: decodev = decode(v0);
2'b01: decodev = decode(v1);
2'b10: decodev = decode(v2);
2'b11: decodev = decode(v3);
endcase
endfunction
function [7:0] decode (input [3:0] n);
case (n)
4'h0: decode = 8'b00000011;
4'h1: decode = 8'b10011111;
4'h2: decode = 8'b00100101;
4'h3: decode = 8'b00001101;
4'h4: decode = 8'b10011001;
4'h5: decode = 8'b01001001;
4'h6: decode = 8'b01000001;
4'h7: decode = 8'b00011111;
4'h8: decode = 8'b00000001;
4'h9: decode = 8'b00001001;
4'hA: decode = 8'b00010001;
4'hb: decode = 8'b11000001;
4'hC: decode = 8'b01100011;
4'hd: decode = 8'b10000101;
4'hE: decode = 8'b01100001;
4'hF: decode = 8'b01110001;
endcase
endfunction
endmodule
|
//==================================================================================================
// Filename : submidRecursiveKOA2.v
// Created On : 2016-10-28 08:46:44
// Last Modified : 2016-10-28 08:59:25
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
//==================================================================================================
// Filename : submidRecursiveKOA.v
// Created On : 2016-10-27 23:28:55
// Last Modified : 2016-10-28 08:42:21
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`include "global.v"
module submidRecursiveKOA2
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output reg [2*SW-1:0] Data_S_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
reg [SW-1:0] post_Data_A_i;
reg [SW-1:0] post_Data_B_i;
always @(posedge clk) begin : SEGMENTATION
post_Data_A_i = Data_A_i;
post_Data_B_i = Data_B_i;
end
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
reg [SW-1:0] Q_left;
reg [SW-1:0] Q_right;
reg [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
csubRecursiveKOA #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(post_Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(post_Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
csubRecursiveKOA #(.SW(SW/2)) right(
// .clk(clk),
.Data_A_i(post_Data_A_i[SW-SW/2-1:0]),
.Data_B_i(post_Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
csubRecursiveKOA #(.SW((SW/2)+1)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : EVEN
result_A_adder <= (post_Data_A_i[((SW/2)-1):0] + post_Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (post_Data_B_i[((SW/2)-1):0] + post_Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
Data_S_o <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
csubRecursiveKOA #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(post_Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(post_Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
csubRecursiveKOA #(.SW((SW/2)+1)) right(
// .clk(clk),
.Data_A_i(post_Data_A_i[SW-SW/2-1:0]),
.Data_B_i(post_Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
csubRecursiveKOA #(.SW(SW/2+2)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : ODD
result_A_adder <= (post_Data_A_i[SW-SW/2-1:0] + post_Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= post_Data_B_i[SW-SW/2-1:0] + post_Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
Data_S_o <= {leftside2,S_B,rightside2} + {Q_left,Q_right};
end
end
endcase
endgenerate
endmodule
|
/*
-- ============================================================================
-- FILE NAME : rom.v
-- DESCRIPTION : Read Only Memory
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** ÂÊwb_t@C **********/
`include "rom.h"
/********** W
[ **********/
module rom (
/********** NbN & Zbg **********/
input wire clk, // NbN
input wire reset, // ñ¯úZbg
/********** oXC^tF[X **********/
input wire cs_, // `bvZNg
input wire as_, // AhXXg[u
input wire [`RomAddrBus] addr, // AhX
output wire [`WordDataBus] rd_data, // ÇÝoµf[^
output reg rdy_ // fB
);
/********** Xilinx FPGA Block RAM : VO|[gROM **********/
x_s3e_sprom x_s3e_sprom (
.clka (clk), // NbN
.addra (addr), // AhX
.douta (rd_data) // ÇÝoµf[^
);
/********** fB̶¬ **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* ñ¯úZbg */
rdy_ <= #1 `DISABLE_;
end else begin
/* fB̶¬ */
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_)) begin
rdy_ <= #1 `ENABLE_;
end else begin
rdy_ <= #1 `DISABLE_;
end
end
end
endmodule
|
`include "m14k_const.vh"
module udi_top (
input [31:0] UDI_ir_e , // full 32 bit Spec2 Instruction
input UDI_irvalid_e , // Instruction reg. valid signal.
input [31:0] UDI_rs_e , // edp_abus_e data from register file
input [31:0] UDI_rt_e , // edp_bbus_e data from register file
input UDI_endianb_e , // Endian - 0=little, 1=big
input UDI_kd_mode_e , // Mode - 0=user, 1=kernel or debug
input UDI_kill_m , // Kill signal
input UDI_start_e , // mpc_run_ie signal to start the UDI.
input UDI_run_m , // mpc_run_m signal to qualify kill_m.
input UDI_greset , // greset signal to reset state machine.
input UDI_gclk , // Clock
input UDI_gscanenable , /* Outputs */
output [31:0] UDI_rd_m , // Result of the UDI in M stage
output [4:0] UDI_wrreg_e ,
output UDI_ri_e , // Illegal Spec2 Instn.
output UDI_stall_m , // Stall the pipeline. E stage signal
output UDI_present , // Indicate whether UDI is implemented
output UDI_honor_cee , // Indicate whether UDI has local state
input [`M14K_UDI_EXT_TOUDI_WIDTH-1:0] UDI_toudi , // External input to UDI module
output [`M14K_UDI_EXT_FROMUDI_WIDTH-1:0] UDI_fromudi // Output from UDI module to external system
);
//// BEGIN Wire declarations made by MVP
//wire [`M14K_UDI_EXT_FROMUDI_WIDTH-1:0] /*[0:0]*/ UDI_fromudi ;
//// END Wire declarations made by MVP
wire [31:0] udi_res ;
wire [1:0] udi_ctl_sum_mode_d ; //0- none 1- + 2- +>> 3- bypass
wire udi_ctl_res_sel_d ; //1- comparing
wire udi_ctl_thr_wr ; //1- wr_thr
wire [1:0] udi_ctl_sum_mode ; //0- none 1- + 2- +>> 3- bypass
wire udi_ctl_res_sel ; //1- comparing
localparam UDI_MAJ_OP = 6'd28 ; //RD = RS[31:16]^2 + RT[31:16]^2
localparam UDI_0 = 6'd16 ; //RD = RS[31:16]^2 + RT[31:16]^2
localparam UDI_1 = 6'd17 ; //RD = (RS[31:16]^2 + RT[31:16]^2) >> 1
localparam UDI_2 = 6'd18 ; //RD = RS[31:16]^2
localparam UDI_3 = 6'd19 ; //stored_threshold = RS
localparam UDI_4 = 6'd20 ; //RD = ( (RS[31:16]^2 + RT[31:16]^2) > stored_threshold ) ? 1 : 0
localparam UDI_5 = 6'd21 ; //RD = ( ((RS[31:16]^2 + RT[31:16]^2) >> 1) > stored_threshold ) ? 1 : 0
localparam UDI_6 = 6'd22 ; //RD = (RS[31:16]^2 > stored_threshold ) ? 1 : 0
localparam CTL_THR_WR_OFF = 1'b0 ;
localparam CTL_THR_WR_ON = 1'b1 ;
localparam CTL_SUM_MODE_NONE = 2'b00 ;
localparam CTL_SUM_MODE_SUM = 2'b01 ;
localparam CTL_SUM_MODE_SUMSHIFT = 2'b10 ;
localparam CTL_SUM_MODE_BYPASS = 2'b11 ;
localparam CTL_RES_CALC = 1'b0 ;
localparam CTL_RES_COMP = 1'b1 ;
assign UDI_fromudi[`M14K_UDI_EXT_FROMUDI_WIDTH-1:0] = {`M14K_UDI_EXT_FROMUDI_WIDTH{1'b0}} ;
assign UDI_ri_e = (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP && UDI_ir_e[5:4] == 2'b01 &&
( UDI_ir_e[5:0] != UDI_0 &&
UDI_ir_e[5:0] != UDI_1 &&
UDI_ir_e[5:0] != UDI_2 &&
UDI_ir_e[5:0] != UDI_3 &&
UDI_ir_e[5:0] != UDI_4 &&
UDI_ir_e[5:0] != UDI_5 &&
UDI_ir_e[5:0] != UDI_6
)
) ? 1'b1 : 1'b0 ; // Illegal Spec2 Instn.
assign UDI_stall_m = 1'b0 ;
assign UDI_present = 1'b1 ;
assign UDI_honor_cee = 1'b0 ;
assign UDI_rd_m = udi_res ;
assign UDI_wrreg_e = (UDI_ir_e[5:0] == UDI_3) ? 5'd0 : UDI_ir_e[15:11] ;
assign udi_ctl_thr_wr = (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP && UDI_ir_e[5:0] == UDI_3) ? CTL_THR_WR_ON : CTL_THR_WR_OFF ;
assign udi_ctl_sum_mode = (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP && (UDI_ir_e[5:0] == UDI_0 || UDI_ir_e[5:0] == UDI_4))
? CTL_SUM_MODE_SUM : (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP && (UDI_ir_e[5:0] == UDI_1 || UDI_ir_e[5:0] == UDI_5))
? CTL_SUM_MODE_SUMSHIFT : (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP && (UDI_ir_e[5:0] == UDI_2 || UDI_ir_e[5:0] == UDI_6))
? CTL_SUM_MODE_BYPASS : CTL_SUM_MODE_NONE ;
assign udi_ctl_res_sel = (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP &&
(UDI_ir_e[5:0] == UDI_0 || UDI_ir_e[5:0] == UDI_1 || UDI_ir_e[5:0] == UDI_2 || UDI_ir_e[5:0] == UDI_3))
? CTL_RES_CALC : CTL_RES_COMP ;
udi_inst_pow udi_inst_pow_u(
.gclk ( UDI_gclk ), //input
.gscanenable ( UDI_gscanenable ), //input
.in_rs ( UDI_rs_e ), //input [31:0]
.in_rt ( UDI_rt_e[31:16] ), //input [15:0]
.out_rd ( udi_res ), //output [31:0]
.udi_ctl_thr_wr ( udi_ctl_thr_wr ), //input
.udi_ctl_sum_mode ( udi_ctl_sum_mode_d ), //input [1:0]
.udi_ctl_res_sel ( udi_ctl_res_sel_d ) //input
);
mvp_cregister_wide #(2) _udi_ctl_sum_mode_1_0_(udi_ctl_sum_mode_d,UDI_gscanenable, (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP), UDI_gclk, udi_ctl_sum_mode);
mvp_cregister_wide #(1) _udi_ctl_res_sel_(udi_ctl_res_sel_d,UDI_gscanenable, (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP), UDI_gclk, udi_ctl_res_sel);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: offset_flag_to_one_hot.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The offset_flag_to_one_hot module takes a data offset,
// and offset_enable and computes the 1-hot encoding of the offset when enabled
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
module offset_flag_to_one_hot
#(
parameter C_WIDTH = 4
)
(
input [clog2s(C_WIDTH)-1:0] WR_OFFSET,
input WR_FLAG,
output [C_WIDTH-1:0] RD_ONE_HOT
);
`include "functions.vh"
assign RD_ONE_HOT = {{(C_WIDTH-1){1'b0}},WR_FLAG} << WR_OFFSET;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Fri Sep 22 18:26:44 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0]" */;
input clk;
input [63:0]probe0;
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// ============================================================================
// LCU
(* techmap_celltype = "$lcu" *)
module _80_xilinx_lcu (P, G, CI, CO);
parameter WIDTH = 2;
(* force_downto *)
input [WIDTH-1:0] P, G;
input CI;
(* force_downto *)
output [WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = WIDTH <= 2;
genvar i;
generate if (`LUT_SIZE == 4) begin
(* force_downto *)
wire [WIDTH-1:0] C = {CO, CI};
(* force_downto *)
wire [WIDTH-1:0] S = P & ~G;
generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
MUXCY muxcy (
.CI(C[i]),
.DI(G[i]),
.S(S[i]),
.O(CO[i])
);
end endgenerate
end else begin
localparam CARRY4_COUNT = (WIDTH + 3) / 4;
localparam MAX_WIDTH = CARRY4_COUNT * 4;
localparam PAD_WIDTH = MAX_WIDTH - WIDTH;
(* force_downto *)
wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, P & ~G};
(* force_downto *)
wire [MAX_WIDTH-1:0] GG = {{PAD_WIDTH{1'b0}}, G};
(* force_downto *)
wire [MAX_WIDTH-1:0] C;
assign CO = C;
generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
if (i == 0) begin
CARRY4 carry4
(
.CYINIT(CI),
.CI (1'd0),
.DI (GG[i*4 +: 4]),
.S (S [i*4 +: 4]),
.CO (C [i*4 +: 4]),
);
end else begin
CARRY4 carry4
(
.CYINIT(1'd0),
.CI (C [i*4 - 1]),
.DI (GG[i*4 +: 4]),
.S (S [i*4 +: 4]),
.CO (C [i*4 +: 4]),
);
end
end endgenerate
end endgenerate
endmodule
// ============================================================================
// ALU
(* techmap_celltype = "$alu" *)
module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
genvar i;
generate if (`LUT_SIZE == 4) begin
(* force_downto *)
wire [Y_WIDTH-1:0] C = {CO, CI};
(* force_downto *)
wire [Y_WIDTH-1:0] S = {AA ^ BB};
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
MUXCY muxcy (
.CI(C[i]),
.DI(AA[i]),
.S(S[i]),
.O(CO[i])
);
XORCY xorcy (
.CI(C[i]),
.LI(S[i]),
.O(Y[i])
);
end endgenerate
end else begin
localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;
localparam MAX_WIDTH = CARRY4_COUNT * 4;
localparam PAD_WIDTH = MAX_WIDTH - Y_WIDTH;
(* force_downto *)
wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB};
(* force_downto *)
wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA};
(* force_downto *)
wire [MAX_WIDTH-1:0] O;
(* force_downto *)
wire [MAX_WIDTH-1:0] C;
assign Y = O, CO = C;
genvar i;
generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
if (i == 0) begin
CARRY4 carry4
(
.CYINIT(CI),
.CI (1'd0),
.DI (DI[i*4 +: 4]),
.S (S [i*4 +: 4]),
.O (O [i*4 +: 4]),
.CO (C [i*4 +: 4])
);
end else begin
CARRY4 carry4
(
.CYINIT(1'd0),
.CI (C [i*4 - 1]),
.DI (DI[i*4 +: 4]),
.S (S [i*4 +: 4]),
.O (O [i*4 +: 4]),
.CO (C [i*4 +: 4])
);
end
end endgenerate
end endgenerate
assign X = S;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311OI_2_V
`define SKY130_FD_SC_MS__A311OI_2_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a311oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a311oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a311oi_2 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311OI_2_V
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 6;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("br_table3.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("br_table3_tb.vcd");
$dumpvars(0, cpu_tb);
if(USE_64B) begin
#90
`assert(result, 12);
`assert(result_type, `i64);
`assert(result_empty, 0);
`assert(trap, `ENDED);
end
else begin
#24
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
// Depth 2 FIFO Data width 0
module FIFO20(CLK,
RST,
ENQ,
FULL_N,
DEQ,
EMPTY_N,
CLR
);
parameter guarded = 1;
input RST;
input CLK;
input ENQ;
input CLR;
input DEQ;
output FULL_N;
output EMPTY_N;
reg empty_reg;
reg full_reg;
assign FULL_N = full_reg ;
assign EMPTY_N = empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
empty_reg = 1'b0 ;
full_reg = 1'b1 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
else if (ENQ && !DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
full_reg <= `BSV_ASSIGNMENT_DELAY ! empty_reg;
end // if (ENQ && !DEQ)
else if (!ENQ && DEQ)
begin
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
empty_reg <= `BSV_ASSIGNMENT_DELAY ! full_reg;
end // if (!ENQ && DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFO20: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! full_reg && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: FIFO20: %m -- Enqueuing to a full fifo" ) ;
end
end // if (RST == ! `BSV_RESET_VALUE)
end
// synopsys translate_on
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD2_BEHAVIORAL_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD2_BEHAVIORAL_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__clkdlyinv5sd2 (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD2_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/29/2016 09:39:31 PM
// Design Name:
// Module Name: new_block
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module new_block(
input wire [5:0] block_in,
input wire up_direction,
input wire direction,
input wire [9:0] relative_xpos,
input wire [8:0] relative_ypos,
output reg [5:0] block_out,
output reg write_enable,
output reg new_point
);
always @* begin
if(block_in == GY) begin
new_point = 1;
block_out = B;
write_enable = 1;
end
else if(((relative_xpos % 40) < 20) && (direction == 0)) begin
if(block_in == D) begin
if(up_direction) begin
new_point = 1;
block_out = DY;
write_enable = 1;
end
else begin
new_point = 0;
block_out = block_in;
write_enable = 0;
end
end
else if(block_in == J) begin
new_point = 0;
if(up_direction) begin
block_out = B;
write_enable = 1;
end
else begin
block_out = block_in;
write_enable = 0;
end
end
else begin
new_point = 0;
block_out = block_in;
write_enable = 0;
end
end
else if(((relative_xpos % 40) >= 20) && (direction == 1)) begin
if(block_in == D) begin
if(up_direction) begin
new_point = 1;
block_out = DY;
write_enable = 1;
end
else begin
new_point = 0;
block_out = block_in;
write_enable = 0;
end
end
else if(block_in == J) begin
new_point = 0;
if(up_direction) begin
block_out = B;
write_enable = 1;
end
else begin
block_out = block_in;
write_enable = 0;
end
end
else begin
new_point = 0;
block_out = block_in;
write_enable = 0;
end
end
else begin
new_point = 0;
block_out = block_in;
write_enable = 0;
end
end
localparam A = 1 ;
localparam B = 0 ;
localparam C = 2 ;
localparam D = 3 ;
localparam E = 4 ;
localparam F = 5 ;
localparam G = 6 ;
localparam H = 7 ;
localparam I = 8 ;
localparam J = 9 ;
localparam K = 10 ;
localparam L = 11 ;
localparam M = 12 ;
localparam N = 13 ;
localparam O = 14 ;
localparam P = 15 ;
localparam Q = 16 ;
localparam R = 17 ;
localparam S = 18 ;
localparam T = 19 ;
localparam U = 20 ;
localparam V = 21 ;
localparam W = 22 ;
localparam X = 23 ;
localparam Y = 24 ;
localparam Z = 25 ;
localparam AY = 26 ;
localparam IY = 27 ;
localparam GY = 28 ;
localparam KY = 29 ;
localparam PY = 30 ;
localparam TY = 31 ;
localparam UY = 32 ;
localparam WY = 33 ;
localparam DY = 34 ;
localparam BY = 35 ;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4_TB_V
`define SKY130_FD_SC_LS__NOR4_TB_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_ls__nor4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4_TB_V
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The top module of the example AXI slave
//
// ====================================================================
module sirv_expl_axi_slv #(
parameter AW = 32,
parameter DW = 32
)(
input axi_arvalid,
output axi_arready,
input [AW-1:0] axi_araddr,
input [3:0] axi_arcache,
input [2:0] axi_arprot,
input [1:0] axi_arlock,
input [1:0] axi_arburst,
input [3:0] axi_arlen,
input [2:0] axi_arsize,
input axi_awvalid,
output axi_awready,
input [AW-1:0] axi_awaddr,
input [3:0] axi_awcache,
input [2:0] axi_awprot,
input [1:0] axi_awlock,
input [1:0] axi_awburst,
input [3:0] axi_awlen,
input [2:0] axi_awsize,
output axi_rvalid,
input axi_rready,
output [DW-1:0] axi_rdata,
output [1:0] axi_rresp,
output axi_rlast,
input axi_wvalid,
output axi_wready,
input [DW-1:0] axi_wdata,
input [(DW/8)-1:0] axi_wstrb,
input axi_wlast,
output axi_bvalid,
input axi_bready,
output [1:0] axi_bresp,
input clk,
input rst_n
);
assign axi_rvalid = axi_arvalid;
assign axi_arready = axi_rready;
assign axi_rdata = {DW{1'b0}};
assign axi_rresp = 2'b0;
assign axi_rlast = 1'b1;
assign axi_bvalid = axi_wvalid;
assign axi_wready = axi_bready;
assign axi_bresp = 2'b0;
assign axi_awready = 1'b1;
endmodule
|
// Put your file header here
//
`ifndef TESTSIZE
`define TESTSIZE 78
`endif
module stimulus;
reg [9:0] test_vector [`TESTSIZE-1:0];
parameter period = 20;
parameter delay = 2;
// declare the signals here
reg clk, rst_n, push, pop;
reg [15:0] datain;
wire empty, almost_empty, full, almost_full, error;
wire [15:0] dataout;
integer i;
fifo fifo1 (
clk,
rst_n,
push,
pop,
datain,
empty,
almost_empty,
full,
almost_full,
error,
dataout
);
always #(period/2) clk = ~clk;
initial begin
`ifdef NETLIST
$sdf_annotate("fifo_my_64x16_syn.sdf", fifo1);
$fsdbDumpfile("fifo_my_64x16_syn.fsdb");
`else
$fsdbDumpfile("fifo_my_64x16.fsdb");
`endif
$fsdbDumpvars;
end
initial begin
$readmemb("pattern1.dat", test_vector);
clk = 1;
rst_n = 1;
idle;
#(period);
#(delay) rst_n = 0;
#(period*4) rst_n = 1;
// #(period/2*5+delay) rst_n = 1;
// #(period/2-delay);
#(period*2);
for (i = 0; i < `TESTSIZE; i = i + 1) begin
case ({test_vector[i][9],test_vector[i][8]})
2'b00: begin
#(period) pushing({test_vector[i][7:0]});
end
2'b01: begin
#(period) popping;
end
2'b10: begin
#(period) idle;
end
2'b11: begin
#(period) invalid;
end
endcase
end
#(period) idle;
#(period*4);
$finish;
end
// tasks
task idle;
begin
push = 0;
pop = 0;
datain = 16'b0;
end
endtask
task pushing;
input [15:0] data;
begin
push = 1;
pop = 0;
datain = data;
end
endtask
task popping;
begin
push = 0;
pop = 1;
end
endtask
task invalid;
begin
push = 1;
pop = 1;
end
endtask
endmodule
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// axi4_s_awready O 1 reg
// axi4_s_wready O 1 reg
// axi4_s_bvalid O 1 reg
// axi4_s_bid O 16 reg
// axi4_s_bresp O 2 reg
// axi4_s_arready O 1 reg
// axi4_s_rvalid O 1 reg
// axi4_s_rid O 16 reg
// axi4_s_rdata O 512 reg
// axi4_s_rresp O 2 reg
// axi4_s_rlast O 1 reg
// l1_to_l2_client_request_first O 69 reg
// RDY_l1_to_l2_client_request_first O 1 reg
// RDY_l1_to_l2_client_request_deq O 1 reg
// l1_to_l2_client_request_notEmpty O 1 reg
// RDY_l1_to_l2_client_request_notEmpty O 1 const
// RDY_l1_to_l2_client_response_enq O 1 reg
// l1_to_l2_client_response_notFull O 1 reg
// RDY_l1_to_l2_client_response_notFull O 1 const
// RDY_l2_to_l1_server_request_enq O 1 reg
// l2_to_l1_server_request_notFull O 1 reg
// RDY_l2_to_l1_server_request_notFull O 1 const
// l2_to_l1_server_response_first O 579 reg
// RDY_l2_to_l1_server_response_first O 1 reg
// RDY_l2_to_l1_server_response_deq O 1 reg
// l2_to_l1_server_response_notEmpty O 1 reg
// RDY_l2_to_l1_server_response_notEmpty O 1 const
// mmio_client_request_get O 131 reg
// RDY_mmio_client_request_get O 1 reg
// RDY_mmio_client_response_put O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// axi4_s_awvalid I 1
// axi4_s_awid I 16 reg
// axi4_s_awaddr I 64 reg
// axi4_s_awlen I 8 reg
// axi4_s_awsize I 3 reg
// axi4_s_awburst I 2 reg
// axi4_s_awlock I 1 reg
// axi4_s_awcache I 4 reg
// axi4_s_awprot I 3 reg
// axi4_s_awqos I 4 reg
// axi4_s_awregion I 4 reg
// axi4_s_wvalid I 1
// axi4_s_wdata I 512 reg
// axi4_s_wstrb I 64 reg
// axi4_s_wlast I 1 reg
// axi4_s_bready I 1
// axi4_s_arvalid I 1
// axi4_s_arid I 16 reg
// axi4_s_araddr I 64 reg
// axi4_s_arlen I 8 reg
// axi4_s_arsize I 3 reg
// axi4_s_arburst I 2 reg
// axi4_s_arlock I 1 reg
// axi4_s_arcache I 4 reg
// axi4_s_arprot I 3 reg
// axi4_s_arqos I 4 reg
// axi4_s_arregion I 4 reg
// axi4_s_rready I 1
// l1_to_l2_client_response_enq_x I 579 reg
// l2_to_l1_server_request_enq_x I 66 reg
// mmio_client_response_put I 65 reg
// EN_l1_to_l2_client_request_deq I 1
// EN_l1_to_l2_client_response_enq I 1
// EN_l2_to_l1_server_request_enq I 1
// EN_l2_to_l1_server_response_deq I 1
// EN_mmio_client_response_put I 1
// EN_mmio_client_request_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkDMA_Cache(CLK,
RST_N,
axi4_s_awvalid,
axi4_s_awid,
axi4_s_awaddr,
axi4_s_awlen,
axi4_s_awsize,
axi4_s_awburst,
axi4_s_awlock,
axi4_s_awcache,
axi4_s_awprot,
axi4_s_awqos,
axi4_s_awregion,
axi4_s_awready,
axi4_s_wvalid,
axi4_s_wdata,
axi4_s_wstrb,
axi4_s_wlast,
axi4_s_wready,
axi4_s_bvalid,
axi4_s_bid,
axi4_s_bresp,
axi4_s_bready,
axi4_s_arvalid,
axi4_s_arid,
axi4_s_araddr,
axi4_s_arlen,
axi4_s_arsize,
axi4_s_arburst,
axi4_s_arlock,
axi4_s_arcache,
axi4_s_arprot,
axi4_s_arqos,
axi4_s_arregion,
axi4_s_arready,
axi4_s_rvalid,
axi4_s_rid,
axi4_s_rdata,
axi4_s_rresp,
axi4_s_rlast,
axi4_s_rready,
l1_to_l2_client_request_first,
RDY_l1_to_l2_client_request_first,
EN_l1_to_l2_client_request_deq,
RDY_l1_to_l2_client_request_deq,
l1_to_l2_client_request_notEmpty,
RDY_l1_to_l2_client_request_notEmpty,
l1_to_l2_client_response_enq_x,
EN_l1_to_l2_client_response_enq,
RDY_l1_to_l2_client_response_enq,
l1_to_l2_client_response_notFull,
RDY_l1_to_l2_client_response_notFull,
l2_to_l1_server_request_enq_x,
EN_l2_to_l1_server_request_enq,
RDY_l2_to_l1_server_request_enq,
l2_to_l1_server_request_notFull,
RDY_l2_to_l1_server_request_notFull,
l2_to_l1_server_response_first,
RDY_l2_to_l1_server_response_first,
EN_l2_to_l1_server_response_deq,
RDY_l2_to_l1_server_response_deq,
l2_to_l1_server_response_notEmpty,
RDY_l2_to_l1_server_response_notEmpty,
EN_mmio_client_request_get,
mmio_client_request_get,
RDY_mmio_client_request_get,
mmio_client_response_put,
EN_mmio_client_response_put,
RDY_mmio_client_response_put);
input CLK;
input RST_N;
// action method axi4_s_m_awvalid
input axi4_s_awvalid;
input [15 : 0] axi4_s_awid;
input [63 : 0] axi4_s_awaddr;
input [7 : 0] axi4_s_awlen;
input [2 : 0] axi4_s_awsize;
input [1 : 0] axi4_s_awburst;
input axi4_s_awlock;
input [3 : 0] axi4_s_awcache;
input [2 : 0] axi4_s_awprot;
input [3 : 0] axi4_s_awqos;
input [3 : 0] axi4_s_awregion;
// value method axi4_s_m_awready
output axi4_s_awready;
// action method axi4_s_m_wvalid
input axi4_s_wvalid;
input [511 : 0] axi4_s_wdata;
input [63 : 0] axi4_s_wstrb;
input axi4_s_wlast;
// value method axi4_s_m_wready
output axi4_s_wready;
// value method axi4_s_m_bvalid
output axi4_s_bvalid;
// value method axi4_s_m_bid
output [15 : 0] axi4_s_bid;
// value method axi4_s_m_bresp
output [1 : 0] axi4_s_bresp;
// value method axi4_s_m_buser
// action method axi4_s_m_bready
input axi4_s_bready;
// action method axi4_s_m_arvalid
input axi4_s_arvalid;
input [15 : 0] axi4_s_arid;
input [63 : 0] axi4_s_araddr;
input [7 : 0] axi4_s_arlen;
input [2 : 0] axi4_s_arsize;
input [1 : 0] axi4_s_arburst;
input axi4_s_arlock;
input [3 : 0] axi4_s_arcache;
input [2 : 0] axi4_s_arprot;
input [3 : 0] axi4_s_arqos;
input [3 : 0] axi4_s_arregion;
// value method axi4_s_m_arready
output axi4_s_arready;
// value method axi4_s_m_rvalid
output axi4_s_rvalid;
// value method axi4_s_m_rid
output [15 : 0] axi4_s_rid;
// value method axi4_s_m_rdata
output [511 : 0] axi4_s_rdata;
// value method axi4_s_m_rresp
output [1 : 0] axi4_s_rresp;
// value method axi4_s_m_rlast
output axi4_s_rlast;
// value method axi4_s_m_ruser
// action method axi4_s_m_rready
input axi4_s_rready;
// value method l1_to_l2_client_request_first
output [68 : 0] l1_to_l2_client_request_first;
output RDY_l1_to_l2_client_request_first;
// action method l1_to_l2_client_request_deq
input EN_l1_to_l2_client_request_deq;
output RDY_l1_to_l2_client_request_deq;
// value method l1_to_l2_client_request_notEmpty
output l1_to_l2_client_request_notEmpty;
output RDY_l1_to_l2_client_request_notEmpty;
// action method l1_to_l2_client_response_enq
input [578 : 0] l1_to_l2_client_response_enq_x;
input EN_l1_to_l2_client_response_enq;
output RDY_l1_to_l2_client_response_enq;
// value method l1_to_l2_client_response_notFull
output l1_to_l2_client_response_notFull;
output RDY_l1_to_l2_client_response_notFull;
// action method l2_to_l1_server_request_enq
input [65 : 0] l2_to_l1_server_request_enq_x;
input EN_l2_to_l1_server_request_enq;
output RDY_l2_to_l1_server_request_enq;
// value method l2_to_l1_server_request_notFull
output l2_to_l1_server_request_notFull;
output RDY_l2_to_l1_server_request_notFull;
// value method l2_to_l1_server_response_first
output [578 : 0] l2_to_l1_server_response_first;
output RDY_l2_to_l1_server_response_first;
// action method l2_to_l1_server_response_deq
input EN_l2_to_l1_server_response_deq;
output RDY_l2_to_l1_server_response_deq;
// value method l2_to_l1_server_response_notEmpty
output l2_to_l1_server_response_notEmpty;
output RDY_l2_to_l1_server_response_notEmpty;
// actionvalue method mmio_client_request_get
input EN_mmio_client_request_get;
output [130 : 0] mmio_client_request_get;
output RDY_mmio_client_request_get;
// action method mmio_client_response_put
input [64 : 0] mmio_client_response_put;
input EN_mmio_client_response_put;
output RDY_mmio_client_response_put;
// signals for module outputs
wire [578 : 0] l2_to_l1_server_response_first;
wire [511 : 0] axi4_s_rdata;
wire [130 : 0] mmio_client_request_get;
wire [68 : 0] l1_to_l2_client_request_first;
wire [15 : 0] axi4_s_bid, axi4_s_rid;
wire [1 : 0] axi4_s_bresp, axi4_s_rresp;
wire RDY_l1_to_l2_client_request_deq,
RDY_l1_to_l2_client_request_first,
RDY_l1_to_l2_client_request_notEmpty,
RDY_l1_to_l2_client_response_enq,
RDY_l1_to_l2_client_response_notFull,
RDY_l2_to_l1_server_request_enq,
RDY_l2_to_l1_server_request_notFull,
RDY_l2_to_l1_server_response_deq,
RDY_l2_to_l1_server_response_first,
RDY_l2_to_l1_server_response_notEmpty,
RDY_mmio_client_request_get,
RDY_mmio_client_response_put,
axi4_s_arready,
axi4_s_awready,
axi4_s_bvalid,
axi4_s_rlast,
axi4_s_rvalid,
axi4_s_wready,
l1_to_l2_client_request_notEmpty,
l1_to_l2_client_response_notFull,
l2_to_l1_server_request_notFull,
l2_to_l1_server_response_notEmpty;
// register axi4_to_ld_rg_bytelane_hi
reg [7 : 0] axi4_to_ld_rg_bytelane_hi;
reg [7 : 0] axi4_to_ld_rg_bytelane_hi$D_IN;
wire axi4_to_ld_rg_bytelane_hi$EN;
// register axi4_to_ld_rg_bytelane_lo
reg [7 : 0] axi4_to_ld_rg_bytelane_lo;
reg [7 : 0] axi4_to_ld_rg_bytelane_lo$D_IN;
wire axi4_to_ld_rg_bytelane_lo$EN;
// register axi4_to_ld_rg_bytelane_slice_lo
reg [7 : 0] axi4_to_ld_rg_bytelane_slice_lo;
reg [7 : 0] axi4_to_ld_rg_bytelane_slice_lo$D_IN;
wire axi4_to_ld_rg_bytelane_slice_lo$EN;
// register axi4_to_ld_rg_cumulative_err
reg axi4_to_ld_rg_cumulative_err;
wire axi4_to_ld_rg_cumulative_err$D_IN, axi4_to_ld_rg_cumulative_err$EN;
// register axi4_to_ld_rg_remaining_slices
reg [3 : 0] axi4_to_ld_rg_remaining_slices;
reg [3 : 0] axi4_to_ld_rg_remaining_slices$D_IN;
wire axi4_to_ld_rg_remaining_slices$EN;
// register axi4_to_ld_rg_slice
reg [63 : 0] axi4_to_ld_rg_slice;
wire [63 : 0] axi4_to_ld_rg_slice$D_IN;
wire axi4_to_ld_rg_slice$EN;
// register axi4_to_ld_rg_state
reg [2 : 0] axi4_to_ld_rg_state;
reg [2 : 0] axi4_to_ld_rg_state$D_IN;
wire axi4_to_ld_rg_state$EN;
// register axi4_to_ld_rg_v_slice
reg [511 : 0] axi4_to_ld_rg_v_slice;
wire [511 : 0] axi4_to_ld_rg_v_slice$D_IN;
wire axi4_to_ld_rg_v_slice$EN;
// register axi4_to_st_rg_bytelane_hi
reg [7 : 0] axi4_to_st_rg_bytelane_hi;
reg [7 : 0] axi4_to_st_rg_bytelane_hi$D_IN;
wire axi4_to_st_rg_bytelane_hi$EN;
// register axi4_to_st_rg_bytelane_lo
reg [7 : 0] axi4_to_st_rg_bytelane_lo;
reg [7 : 0] axi4_to_st_rg_bytelane_lo$D_IN;
wire axi4_to_st_rg_bytelane_lo$EN;
// register axi4_to_st_rg_bytelane_slice_lo
reg [7 : 0] axi4_to_st_rg_bytelane_slice_lo;
reg [7 : 0] axi4_to_st_rg_bytelane_slice_lo$D_IN;
wire axi4_to_st_rg_bytelane_slice_lo$EN;
// register axi4_to_st_rg_cumulative_err
reg axi4_to_st_rg_cumulative_err;
wire axi4_to_st_rg_cumulative_err$D_IN, axi4_to_st_rg_cumulative_err$EN;
// register axi4_to_st_rg_discard_count
reg [7 : 0] axi4_to_st_rg_discard_count;
wire [7 : 0] axi4_to_st_rg_discard_count$D_IN;
wire axi4_to_st_rg_discard_count$EN;
// register axi4_to_st_rg_slice
reg [63 : 0] axi4_to_st_rg_slice;
reg [63 : 0] axi4_to_st_rg_slice$D_IN;
wire axi4_to_st_rg_slice$EN;
// register axi4_to_st_rg_state
reg [2 : 0] axi4_to_st_rg_state;
reg [2 : 0] axi4_to_st_rg_state$D_IN;
wire axi4_to_st_rg_state$EN;
// register axi4_to_st_rg_v_slice
reg [511 : 0] axi4_to_st_rg_v_slice;
reg [511 : 0] axi4_to_st_rg_v_slice$D_IN;
wire axi4_to_st_rg_v_slice$EN;
// register axi4_to_st_rg_v_strb
reg [63 : 0] axi4_to_st_rg_v_strb;
reg [63 : 0] axi4_to_st_rg_v_strb$D_IN;
wire axi4_to_st_rg_v_strb$EN;
// register rg_init_index
reg [5 : 0] rg_init_index;
wire [5 : 0] rg_init_index$D_IN;
wire rg_init_index$EN;
// register rg_state
reg [1 : 0] rg_state;
wire [1 : 0] rg_state$D_IN;
wire rg_state$EN;
// ports of submodule axi4_s_xactor_f_rd_addr
wire [108 : 0] axi4_s_xactor_f_rd_addr$D_IN, axi4_s_xactor_f_rd_addr$D_OUT;
wire axi4_s_xactor_f_rd_addr$CLR,
axi4_s_xactor_f_rd_addr$DEQ,
axi4_s_xactor_f_rd_addr$EMPTY_N,
axi4_s_xactor_f_rd_addr$ENQ,
axi4_s_xactor_f_rd_addr$FULL_N;
// ports of submodule axi4_s_xactor_f_rd_data
reg [530 : 0] axi4_s_xactor_f_rd_data$D_IN;
wire [530 : 0] axi4_s_xactor_f_rd_data$D_OUT;
wire axi4_s_xactor_f_rd_data$CLR,
axi4_s_xactor_f_rd_data$DEQ,
axi4_s_xactor_f_rd_data$EMPTY_N,
axi4_s_xactor_f_rd_data$ENQ,
axi4_s_xactor_f_rd_data$FULL_N;
// ports of submodule axi4_s_xactor_f_wr_addr
wire [108 : 0] axi4_s_xactor_f_wr_addr$D_IN, axi4_s_xactor_f_wr_addr$D_OUT;
wire axi4_s_xactor_f_wr_addr$CLR,
axi4_s_xactor_f_wr_addr$DEQ,
axi4_s_xactor_f_wr_addr$EMPTY_N,
axi4_s_xactor_f_wr_addr$ENQ,
axi4_s_xactor_f_wr_addr$FULL_N;
// ports of submodule axi4_s_xactor_f_wr_data
wire [576 : 0] axi4_s_xactor_f_wr_data$D_IN, axi4_s_xactor_f_wr_data$D_OUT;
wire axi4_s_xactor_f_wr_data$CLR,
axi4_s_xactor_f_wr_data$DEQ,
axi4_s_xactor_f_wr_data$EMPTY_N,
axi4_s_xactor_f_wr_data$ENQ,
axi4_s_xactor_f_wr_data$FULL_N;
// ports of submodule axi4_s_xactor_f_wr_resp
wire [17 : 0] axi4_s_xactor_f_wr_resp$D_IN, axi4_s_xactor_f_wr_resp$D_OUT;
wire axi4_s_xactor_f_wr_resp$CLR,
axi4_s_xactor_f_wr_resp$DEQ,
axi4_s_xactor_f_wr_resp$EMPTY_N,
axi4_s_xactor_f_wr_resp$ENQ,
axi4_s_xactor_f_wr_resp$FULL_N;
// ports of submodule axi4_to_ld_f_axi_rsp_info
wire [16 : 0] axi4_to_ld_f_axi_rsp_info$D_IN,
axi4_to_ld_f_axi_rsp_info$D_OUT;
wire axi4_to_ld_f_axi_rsp_info$CLR,
axi4_to_ld_f_axi_rsp_info$DEQ,
axi4_to_ld_f_axi_rsp_info$EMPTY_N,
axi4_to_ld_f_axi_rsp_info$ENQ,
axi4_to_ld_f_axi_rsp_info$FULL_N;
// ports of submodule axi4_to_ld_f_ld_rsp_info
reg [9 : 0] axi4_to_ld_f_ld_rsp_info$D_IN;
wire [9 : 0] axi4_to_ld_f_ld_rsp_info$D_OUT;
wire axi4_to_ld_f_ld_rsp_info$CLR,
axi4_to_ld_f_ld_rsp_info$DEQ,
axi4_to_ld_f_ld_rsp_info$EMPTY_N,
axi4_to_ld_f_ld_rsp_info$ENQ,
axi4_to_ld_f_ld_rsp_info$FULL_N;
// ports of submodule axi4_to_ld_f_reqs
reg [65 : 0] axi4_to_ld_f_reqs$D_IN;
wire [65 : 0] axi4_to_ld_f_reqs$D_OUT;
wire axi4_to_ld_f_reqs$CLR,
axi4_to_ld_f_reqs$DEQ,
axi4_to_ld_f_reqs$EMPTY_N,
axi4_to_ld_f_reqs$ENQ,
axi4_to_ld_f_reqs$FULL_N;
// ports of submodule axi4_to_ld_f_rsps
wire [64 : 0] axi4_to_ld_f_rsps$D_IN, axi4_to_ld_f_rsps$D_OUT;
wire axi4_to_ld_f_rsps$CLR,
axi4_to_ld_f_rsps$DEQ,
axi4_to_ld_f_rsps$EMPTY_N,
axi4_to_ld_f_rsps$ENQ,
axi4_to_ld_f_rsps$FULL_N;
// ports of submodule axi4_to_st_f_axi_rsp_info
wire [16 : 0] axi4_to_st_f_axi_rsp_info$D_IN,
axi4_to_st_f_axi_rsp_info$D_OUT;
wire axi4_to_st_f_axi_rsp_info$CLR,
axi4_to_st_f_axi_rsp_info$DEQ,
axi4_to_st_f_axi_rsp_info$EMPTY_N,
axi4_to_st_f_axi_rsp_info$ENQ,
axi4_to_st_f_axi_rsp_info$FULL_N;
// ports of submodule axi4_to_st_f_reqs
reg [129 : 0] axi4_to_st_f_reqs$D_IN;
wire [129 : 0] axi4_to_st_f_reqs$D_OUT;
wire axi4_to_st_f_reqs$CLR,
axi4_to_st_f_reqs$DEQ,
axi4_to_st_f_reqs$EMPTY_N,
axi4_to_st_f_reqs$ENQ,
axi4_to_st_f_reqs$FULL_N;
// ports of submodule axi4_to_st_f_rsps
wire axi4_to_st_f_rsps$CLR,
axi4_to_st_f_rsps$DEQ,
axi4_to_st_f_rsps$D_IN,
axi4_to_st_f_rsps$D_OUT,
axi4_to_st_f_rsps$EMPTY_N,
axi4_to_st_f_rsps$ENQ,
axi4_to_st_f_rsps$FULL_N;
// ports of submodule axi4_to_st_f_st_rsp_info
wire axi4_to_st_f_st_rsp_info$CLR,
axi4_to_st_f_st_rsp_info$DEQ,
axi4_to_st_f_st_rsp_info$D_IN,
axi4_to_st_f_st_rsp_info$D_OUT,
axi4_to_st_f_st_rsp_info$EMPTY_N,
axi4_to_st_f_st_rsp_info$ENQ,
axi4_to_st_f_st_rsp_info$FULL_N;
// ports of submodule f_L1_to_L2_Reqs
wire [68 : 0] f_L1_to_L2_Reqs$D_IN, f_L1_to_L2_Reqs$D_OUT;
wire f_L1_to_L2_Reqs$CLR,
f_L1_to_L2_Reqs$DEQ,
f_L1_to_L2_Reqs$EMPTY_N,
f_L1_to_L2_Reqs$ENQ,
f_L1_to_L2_Reqs$FULL_N;
// ports of submodule f_L1_to_L2_Rsps
wire [578 : 0] f_L1_to_L2_Rsps$D_IN, f_L1_to_L2_Rsps$D_OUT;
wire f_L1_to_L2_Rsps$CLR,
f_L1_to_L2_Rsps$DEQ,
f_L1_to_L2_Rsps$EMPTY_N,
f_L1_to_L2_Rsps$ENQ,
f_L1_to_L2_Rsps$FULL_N;
// ports of submodule f_L2_to_L1_Reqs
wire [65 : 0] f_L2_to_L1_Reqs$D_IN, f_L2_to_L1_Reqs$D_OUT;
wire f_L2_to_L1_Reqs$CLR,
f_L2_to_L1_Reqs$DEQ,
f_L2_to_L1_Reqs$EMPTY_N,
f_L2_to_L1_Reqs$ENQ,
f_L2_to_L1_Reqs$FULL_N;
// ports of submodule f_L2_to_L1_Rsps
wire [578 : 0] f_L2_to_L1_Rsps$D_IN, f_L2_to_L1_Rsps$D_OUT;
wire f_L2_to_L1_Rsps$CLR,
f_L2_to_L1_Rsps$DEQ,
f_L2_to_L1_Rsps$EMPTY_N,
f_L2_to_L1_Rsps$ENQ,
f_L2_to_L1_Rsps$FULL_N;
// ports of submodule f_mmio_rsp_is_load
wire f_mmio_rsp_is_load$CLR,
f_mmio_rsp_is_load$DEQ,
f_mmio_rsp_is_load$D_IN,
f_mmio_rsp_is_load$D_OUT,
f_mmio_rsp_is_load$EMPTY_N,
f_mmio_rsp_is_load$ENQ,
f_mmio_rsp_is_load$FULL_N;
// ports of submodule f_rd_addr
wire [108 : 0] f_rd_addr$D_IN, f_rd_addr$D_OUT;
wire f_rd_addr$CLR,
f_rd_addr$DEQ,
f_rd_addr$EMPTY_N,
f_rd_addr$ENQ,
f_rd_addr$FULL_N;
// ports of submodule f_rd_data
wire [530 : 0] f_rd_data$D_IN, f_rd_data$D_OUT;
wire f_rd_data$CLR,
f_rd_data$DEQ,
f_rd_data$EMPTY_N,
f_rd_data$ENQ,
f_rd_data$FULL_N;
// ports of submodule f_reqs
wire [685 : 0] f_reqs$D_IN, f_reqs$D_OUT;
wire f_reqs$CLR, f_reqs$DEQ, f_reqs$EMPTY_N, f_reqs$ENQ, f_reqs$FULL_N;
// ports of submodule f_single_reqs
wire [130 : 0] f_single_reqs$D_IN, f_single_reqs$D_OUT;
wire f_single_reqs$CLR,
f_single_reqs$DEQ,
f_single_reqs$EMPTY_N,
f_single_reqs$ENQ,
f_single_reqs$FULL_N;
// ports of submodule f_single_rsps
wire [64 : 0] f_single_rsps$D_IN, f_single_rsps$D_OUT;
wire f_single_rsps$CLR,
f_single_rsps$DEQ,
f_single_rsps$EMPTY_N,
f_single_rsps$ENQ,
f_single_rsps$FULL_N;
// ports of submodule f_wr_addr
wire [108 : 0] f_wr_addr$D_IN, f_wr_addr$D_OUT;
wire f_wr_addr$CLR,
f_wr_addr$DEQ,
f_wr_addr$EMPTY_N,
f_wr_addr$ENQ,
f_wr_addr$FULL_N;
// ports of submodule f_wr_data
wire [576 : 0] f_wr_data$D_IN, f_wr_data$D_OUT;
wire f_wr_data$CLR,
f_wr_data$DEQ,
f_wr_data$EMPTY_N,
f_wr_data$ENQ,
f_wr_data$FULL_N;
// ports of submodule f_wr_resp
wire [17 : 0] f_wr_resp$D_IN, f_wr_resp$D_OUT;
wire f_wr_resp$CLR,
f_wr_resp$DEQ,
f_wr_resp$EMPTY_N,
f_wr_resp$ENQ,
f_wr_resp$FULL_N;
// ports of submodule rf_data_sets
wire [511 : 0] rf_data_sets$D_IN, rf_data_sets$D_OUT_1;
wire [5 : 0] rf_data_sets$ADDR_1,
rf_data_sets$ADDR_2,
rf_data_sets$ADDR_3,
rf_data_sets$ADDR_4,
rf_data_sets$ADDR_5,
rf_data_sets$ADDR_IN;
wire rf_data_sets$WE;
// ports of submodule rf_tag_sets
reg [65 : 0] rf_tag_sets$D_IN;
reg [5 : 0] rf_tag_sets$ADDR_IN;
wire [65 : 0] rf_tag_sets$D_OUT_1, rf_tag_sets$D_OUT_2;
wire [5 : 0] rf_tag_sets$ADDR_1,
rf_tag_sets$ADDR_2,
rf_tag_sets$ADDR_3,
rf_tag_sets$ADDR_4,
rf_tag_sets$ADDR_5;
wire rf_tag_sets$WE;
// rule scheduling signals
wire CAN_FIRE_RL_axi4_to_ld_rl_finish_req,
CAN_FIRE_RL_axi4_to_ld_rl_handle_ld_rsp,
CAN_FIRE_RL_axi4_to_ld_rl_handle_ld_slice_ignore,
CAN_FIRE_RL_axi4_to_ld_rl_illegal_req,
CAN_FIRE_RL_axi4_to_ld_rl_next_slice,
CAN_FIRE_RL_axi4_to_ld_rl_partial,
CAN_FIRE_RL_axi4_to_ld_rl_send_axi_response,
CAN_FIRE_RL_axi4_to_ld_rl_shift_tail_slices,
CAN_FIRE_RL_axi4_to_ld_rl_start_xaction,
CAN_FIRE_RL_axi4_to_st_rl_finish_req,
CAN_FIRE_RL_axi4_to_st_rl_handle_st_rsps,
CAN_FIRE_RL_axi4_to_st_rl_illegal_req,
CAN_FIRE_RL_axi4_to_st_rl_next_slice,
CAN_FIRE_RL_axi4_to_st_rl_partial,
CAN_FIRE_RL_axi4_to_st_rl_send_axi_response,
CAN_FIRE_RL_axi4_to_st_rl_start_xaction,
CAN_FIRE_RL_rl_downgrade,
CAN_FIRE_RL_rl_evict,
CAN_FIRE_RL_rl_hit,
CAN_FIRE_RL_rl_init,
CAN_FIRE_RL_rl_merge_rd_req,
CAN_FIRE_RL_rl_merge_wr_req,
CAN_FIRE_RL_rl_mmio_AXI_rd_req,
CAN_FIRE_RL_rl_mmio_AXI_rd_rsp,
CAN_FIRE_RL_rl_mmio_LD_req,
CAN_FIRE_RL_rl_mmio_LD_rsp,
CAN_FIRE_RL_rl_mmio_ST_req,
CAN_FIRE_RL_rl_mmio_axi_wr_req,
CAN_FIRE_RL_rl_mmio_axi_wr_rsp,
CAN_FIRE_RL_rl_mmio_st_rsp,
CAN_FIRE_RL_rl_upgrade_req,
CAN_FIRE_RL_rl_upgrade_rsp,
CAN_FIRE_axi4_s_m_arvalid,
CAN_FIRE_axi4_s_m_awvalid,
CAN_FIRE_axi4_s_m_bready,
CAN_FIRE_axi4_s_m_rready,
CAN_FIRE_axi4_s_m_wvalid,
CAN_FIRE_l1_to_l2_client_request_deq,
CAN_FIRE_l1_to_l2_client_response_enq,
CAN_FIRE_l2_to_l1_server_request_enq,
CAN_FIRE_l2_to_l1_server_response_deq,
CAN_FIRE_mmio_client_request_get,
CAN_FIRE_mmio_client_response_put,
WILL_FIRE_RL_axi4_to_ld_rl_finish_req,
WILL_FIRE_RL_axi4_to_ld_rl_handle_ld_rsp,
WILL_FIRE_RL_axi4_to_ld_rl_handle_ld_slice_ignore,
WILL_FIRE_RL_axi4_to_ld_rl_illegal_req,
WILL_FIRE_RL_axi4_to_ld_rl_next_slice,
WILL_FIRE_RL_axi4_to_ld_rl_partial,
WILL_FIRE_RL_axi4_to_ld_rl_send_axi_response,
WILL_FIRE_RL_axi4_to_ld_rl_shift_tail_slices,
WILL_FIRE_RL_axi4_to_ld_rl_start_xaction,
WILL_FIRE_RL_axi4_to_st_rl_finish_req,
WILL_FIRE_RL_axi4_to_st_rl_handle_st_rsps,
WILL_FIRE_RL_axi4_to_st_rl_illegal_req,
WILL_FIRE_RL_axi4_to_st_rl_next_slice,
WILL_FIRE_RL_axi4_to_st_rl_partial,
WILL_FIRE_RL_axi4_to_st_rl_send_axi_response,
WILL_FIRE_RL_axi4_to_st_rl_start_xaction,
WILL_FIRE_RL_rl_downgrade,
WILL_FIRE_RL_rl_evict,
WILL_FIRE_RL_rl_hit,
WILL_FIRE_RL_rl_init,
WILL_FIRE_RL_rl_merge_rd_req,
WILL_FIRE_RL_rl_merge_wr_req,
WILL_FIRE_RL_rl_mmio_AXI_rd_req,
WILL_FIRE_RL_rl_mmio_AXI_rd_rsp,
WILL_FIRE_RL_rl_mmio_LD_req,
WILL_FIRE_RL_rl_mmio_LD_rsp,
WILL_FIRE_RL_rl_mmio_ST_req,
WILL_FIRE_RL_rl_mmio_axi_wr_req,
WILL_FIRE_RL_rl_mmio_axi_wr_rsp,
WILL_FIRE_RL_rl_mmio_st_rsp,
WILL_FIRE_RL_rl_upgrade_req,
WILL_FIRE_RL_rl_upgrade_rsp,
WILL_FIRE_axi4_s_m_arvalid,
WILL_FIRE_axi4_s_m_awvalid,
WILL_FIRE_axi4_s_m_bready,
WILL_FIRE_axi4_s_m_rready,
WILL_FIRE_axi4_s_m_wvalid,
WILL_FIRE_l1_to_l2_client_request_deq,
WILL_FIRE_l1_to_l2_client_response_enq,
WILL_FIRE_l2_to_l1_server_request_enq,
WILL_FIRE_l2_to_l1_server_response_deq,
WILL_FIRE_mmio_client_request_get,
WILL_FIRE_mmio_client_response_put;
// inputs to muxes for submodule ports
wire [685 : 0] MUX_f_reqs$enq_1__VAL_1, MUX_f_reqs$enq_1__VAL_2;
wire [578 : 0] MUX_f_L1_to_L2_Rsps$enq_1__VAL_1,
MUX_f_L1_to_L2_Rsps$enq_1__VAL_2;
wire [530 : 0] MUX_axi4_s_xactor_f_rd_data$enq_1__VAL_1,
MUX_axi4_s_xactor_f_rd_data$enq_1__VAL_2;
wire [511 : 0] MUX_axi4_to_ld_rg_v_slice$write_1__VAL_1,
MUX_axi4_to_ld_rg_v_slice$write_1__VAL_2,
MUX_axi4_to_st_rg_v_slice$write_1__VAL_1,
MUX_axi4_to_st_rg_v_slice$write_1__VAL_2,
MUX_rf_data_sets$upd_2__VAL_1,
MUX_rf_data_sets$upd_2__VAL_2;
wire [130 : 0] MUX_f_single_reqs$enq_1__VAL_1,
MUX_f_single_reqs$enq_1__VAL_2;
wire [129 : 0] MUX_axi4_to_st_f_reqs$enq_1__VAL_1,
MUX_axi4_to_st_f_reqs$enq_1__VAL_2,
MUX_axi4_to_st_f_reqs$enq_1__VAL_3;
wire [65 : 0] MUX_axi4_to_ld_f_reqs$enq_1__VAL_1,
MUX_axi4_to_ld_f_reqs$enq_1__VAL_2,
MUX_axi4_to_ld_f_reqs$enq_1__VAL_3,
MUX_rf_tag_sets$upd_2__VAL_1,
MUX_rf_tag_sets$upd_2__VAL_3,
MUX_rf_tag_sets$upd_2__VAL_4;
wire [63 : 0] MUX_axi4_to_st_rg_v_strb$write_1__VAL_1,
MUX_axi4_to_st_rg_v_strb$write_1__VAL_2;
wire [17 : 0] MUX_axi4_s_xactor_f_wr_resp$enq_1__VAL_1;
wire [16 : 0] MUX_axi4_to_ld_f_axi_rsp_info$enq_1__VAL_1,
MUX_axi4_to_ld_f_axi_rsp_info$enq_1__VAL_2,
MUX_axi4_to_st_f_axi_rsp_info$enq_1__VAL_1,
MUX_axi4_to_st_f_axi_rsp_info$enq_1__VAL_2;
wire [9 : 0] MUX_axi4_to_ld_f_ld_rsp_info$enq_1__VAL_1,
MUX_axi4_to_ld_f_ld_rsp_info$enq_1__VAL_3,
MUX_axi4_to_ld_f_ld_rsp_info$enq_1__VAL_4;
wire [7 : 0] MUX_axi4_to_ld_rg_bytelane_lo$write_1__VAL_1,
MUX_axi4_to_ld_rg_bytelane_lo$write_1__VAL_2,
MUX_axi4_to_ld_rg_bytelane_lo$write_1__VAL_3,
MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__VAL_1,
MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__VAL_2,
MUX_axi4_to_st_rg_bytelane_lo$write_1__VAL_1,
MUX_axi4_to_st_rg_bytelane_lo$write_1__VAL_2,
MUX_axi4_to_st_rg_bytelane_lo$write_1__VAL_3,
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__VAL_1,
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__VAL_2,
MUX_axi4_to_st_rg_discard_count$write_1__VAL_2;
wire [3 : 0] MUX_axi4_to_ld_rg_remaining_slices$write_1__VAL_1;
wire [2 : 0] MUX_axi4_to_ld_rg_state$write_1__VAL_1,
MUX_axi4_to_ld_rg_state$write_1__VAL_2,
MUX_axi4_to_ld_rg_state$write_1__VAL_3,
MUX_axi4_to_st_rg_state$write_1__VAL_2,
MUX_axi4_to_st_rg_state$write_1__VAL_3,
MUX_axi4_to_st_rg_state$write_1__VAL_4;
wire MUX_axi4_s_xactor_f_rd_data$enq_1__SEL_1,
MUX_axi4_s_xactor_f_rd_data$enq_1__SEL_2,
MUX_axi4_s_xactor_f_wr_resp$enq_1__PSEL_1,
MUX_axi4_s_xactor_f_wr_resp$enq_1__SEL_1,
MUX_axi4_to_ld_f_ld_rsp_info$enq_1__SEL_1,
MUX_axi4_to_ld_f_ld_rsp_info$enq_1__SEL_2,
MUX_axi4_to_ld_f_reqs$enq_1__SEL_1,
MUX_axi4_to_ld_f_reqs$enq_1__SEL_2,
MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__SEL_1,
MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__SEL_2,
MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__SEL_3,
MUX_axi4_to_ld_rg_remaining_slices$write_1__SEL_1,
MUX_axi4_to_ld_rg_remaining_slices$write_1__SEL_2,
MUX_axi4_to_st_f_axi_rsp_info$enq_1__SEL_1,
MUX_axi4_to_st_f_reqs$enq_1__SEL_1,
MUX_axi4_to_st_f_reqs$enq_1__SEL_2,
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_1,
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_2,
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_3,
MUX_axi4_to_st_rg_discard_count$write_1__SEL_1,
MUX_f_L1_to_L2_Rsps$enq_1__SEL_1,
MUX_f_single_reqs$enq_1__SEL_1,
MUX_f_single_reqs$enq_1__SEL_2,
MUX_rg_state$write_1__SEL_1,
MUX_rg_state$write_1__SEL_2,
MUX_rg_state$write_1__SEL_3;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h1963;
reg [31 : 0] v__h2441;
reg [31 : 0] v__h21995;
reg [31 : 0] v__h22278;
reg [31 : 0] v__h22510;
reg [31 : 0] v__h41979;
reg [31 : 0] v__h42147;
reg [31 : 0] v__h52258;
reg [31 : 0] v__h52431;
reg [31 : 0] v__h52625;
reg [31 : 0] v__h1957;
reg [31 : 0] v__h2435;
reg [31 : 0] v__h21989;
reg [31 : 0] v__h22272;
reg [31 : 0] v__h22504;
reg [31 : 0] v__h41973;
reg [31 : 0] v__h42141;
reg [31 : 0] v__h52252;
reg [31 : 0] v__h52425;
reg [31 : 0] v__h52619;
// synopsys translate_on
// remaining internal signals
wire [511 : 0] new_data___1__h23293, new_data___1__h4300, v__h22217;
wire [63 : 0] addr_axi_bus_lo__h41811,
addr_axi_bus_lo__h52058,
f_rd_addrD_OUT_BITS_92_TO_29_AND_mask3380__q3,
f_wr_addrD_OUT_BITS_92_TO_29_AND_mask6467__q4,
line_addr__h2730,
line_addr__h3158,
mask__h43380,
mask__h56467,
shifted_slice__h55312,
shifted_slice__h62392,
shifted_slice__h65843,
slice__h45713,
x__h44701,
x__h45249,
x__h55604,
x__h55986,
x__h62659,
x__h62662,
x__h66112,
x__h66115,
y_avValue_snd_snd__h55988,
y_avValue_snd_snd__h55990,
y_avValue_snd_snd__h56237,
y_avValue_snd_snd__h56239,
y_avValue_snd_snd__h56244,
y_avValue_snd_snd__h62664,
y_avValue_snd_snd__h62666,
y_avValue_snd_snd__h62908,
y_avValue_snd_snd__h62910,
y_avValue_snd_snd__h62915,
y_avValue_snd_snd__h66117,
y_avValue_snd_snd__h66119,
y_avValue_snd_snd__h66150,
y_avValue_snd_snd__h66152,
y_avValue_snd_snd__h66157;
wire [7 : 0] _1_SL_f_rd_addr_first__62_BITS_20_TO_18_66___d667,
_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28___d929,
addr_bytelane__h52059,
axi4_to_st_rg_bytelane_lo_MINUS_axi4_to_st_rg__ETC__q2,
bytelane_hi__h52936,
bytelane_hi__h60054,
bytelane_lo0053_MINUS_axi4_to_st_rg_bytelane_s_ETC__q1,
bytelane_lo__h42399,
bytelane_lo__h44346,
bytelane_lo__h52935,
bytelane_lo__h60053,
bytelane_slice_hi__h44327,
bytelane_slice_hi__h60018,
bytes_processed__h42786,
bytes_processed__h44683,
bytes_processed__h45231,
bytes_processed__h55567,
bytes_processed__h62638,
bytes_processed__h66091,
num_bytes__h42529,
num_bytes__h44435,
num_bytes__h44981,
num_bytes__h55297,
num_bytes__h62377,
num_bytes__h65828,
num_lsb_zero_bytes__h60039,
num_msb_zero_bytes__h52922,
num_msb_zero_bytes__h60040,
szwindow_bytelane_hi__h41816,
szwindow_bytelane_hi__h52063,
szwindow_bytelane_lo__h41815,
szwindow_bytelane_lo__h52062,
v__h42404,
v__h42504,
v__h44351,
v__h44413,
v__h44974,
v__h52941,
v__h55273,
v__h60059,
v__h62356,
v__h65821,
x__h42568,
x__h44474,
x__h44726,
x__h45020,
x__h45274,
x__h55337,
x__h56212,
x__h62417,
x__h62883,
x__h65868,
x__h66125,
y__h43356,
y__h54481,
y__h56443,
y__h61591,
y__h61599,
y_avValue_snd__h42763,
y_avValue_snd__h42779,
y_avValue_snd__h44660,
y_avValue_snd__h44676,
y_avValue_snd__h45208,
y_avValue_snd__h45224,
y_avValue_snd_fst__h55989,
y_avValue_snd_fst__h56238,
y_avValue_snd_fst__h62665,
y_avValue_snd_fst__h62909,
y_avValue_snd_fst__h66118,
y_avValue_snd_fst__h66151;
wire [3 : 0] x__h44141,
x__h53166,
x__h54490,
x__h57228,
x__h60276,
x__h61600;
wire [2 : 0] IF_axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_5_ETC___d796,
IF_axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7__ETC___d1172;
wire [1 : 0] rd_data_S_rresp__h49842,
x__h42811,
x__h44699,
x__h45247,
x__h55592,
x__h62654,
x__h66107,
y_avValue_fst__h42762,
y_avValue_fst__h42778,
y_avValue_fst__h44659,
y_avValue_fst__h44675,
y_avValue_fst__h45207,
y_avValue_fst__h45223,
y_avValue_fst__h55540,
y_avValue_fst__h55558,
y_avValue_fst__h62611,
y_avValue_fst__h62629,
y_avValue_fst__h66064,
y_avValue_fst__h66082;
wire IF_f_reqs_first__05_BIT_685_24_THEN_axi4_s_xac_ETC___d127,
NOT_f_L2_to_L1_Rsps_first__49_BITS_578_TO_515__ETC___d452,
NOT_f_rd_addr_first__62_BITS_28_TO_21_63_EQ_0__ETC___d679,
NOT_f_reqs_first__05_BIT_685_24_29_AND_NOT_rf__ETC___d135,
_0_CONCAT_IF_f_wr_data_first__21_BIT_1_36_THEN__ETC___d955,
_0_CONCAT_f_rd_addr_first__62_BITS_34_TO_29_72__ETC___d674,
_0_CONCAT_f_rd_addr_first__62_BITS_92_TO_29_90__ETC___d746,
_0_CONCAT_f_wr_addr_first__24_BITS_92_TO_29_89__ETC___d1063,
_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668,
_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930,
_7_MINUS_0_CONCAT_IF_f_wr_data_first__21_BIT_8__ETC___d1011,
_7_MINUS_0_CONCAT_IF_f_wr_data_first__21_BIT_8__ETC___d969,
_7_MINUS_0_CONCAT_f_rd_addr_first__62_BITS_34_T_ETC___d711,
axi4_s_xactor_f_rd_addr_first__0_BITS_92_TO_29_ETC___d12,
axi4_s_xactor_f_rd_addr_first__0_BITS_92_TO_29_ETC___d14,
axi4_s_xactor_f_rd_addr_first__0_BITS_92_TO_29_ETC___d16,
axi4_s_xactor_f_rd_addr_first__0_BITS_92_TO_29_ETC___d18,
axi4_s_xactor_f_wr_addr_first__0_BITS_92_TO_29_ETC___d42,
axi4_s_xactor_f_wr_addr_first__0_BITS_92_TO_29_ETC___d44,
axi4_s_xactor_f_wr_addr_first__0_BITS_92_TO_29_ETC___d46,
axi4_s_xactor_f_wr_addr_first__0_BITS_92_TO_29_ETC___d48,
axi4_to_ld_rg_bytelane_hi_02_MINUS_axi4_to_ld__ETC___d813,
axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_M_ETC___d777,
axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_U_ETC___d758,
axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_U_ETC___d793,
axi4_to_st_rg_bytelane_hi_176_MINUS_axi4_to_st_ETC___d1187,
axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1113,
axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1129,
axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1165,
axi4_to_st_rg_v_strb_075_BITS_7_TO_0_076_EQ_0__ETC___d1116,
f_wr_data_first__21_BITS_8_TO_1_34_EQ_0_35_OR__ETC___d957,
f_wr_data_first__21_BITS_8_TO_1_34_EQ_0_35_OR__ETC___d975,
f_wr_data_first__21_BIT_0_22_AND_f_wr_addr_fir_ETC___d1001,
f_wr_data_first__21_BIT_0_22_AND_f_wr_addr_fir_ETC___d1066,
rf_tag_sets_sub_f_L2_to_L1_Reqs_first__1_BITS__ETC___d77,
rf_tag_sets_sub_f_L2_to_L1_Reqs_first__1_BITS__ETC___d82,
rf_tag_sets_sub_f_reqs_first__05_BITS_616_TO_6_ETC___d114,
rg_state_EQ_1_01_AND_NOT_f_L2_to_L1_Reqs_notEm_ETC___d438;
// action method axi4_s_m_awvalid
assign CAN_FIRE_axi4_s_m_awvalid = 1'd1 ;
assign WILL_FIRE_axi4_s_m_awvalid = 1'd1 ;
// value method axi4_s_m_awready
assign axi4_s_awready = axi4_s_xactor_f_wr_addr$FULL_N ;
// action method axi4_s_m_wvalid
assign CAN_FIRE_axi4_s_m_wvalid = 1'd1 ;
assign WILL_FIRE_axi4_s_m_wvalid = 1'd1 ;
// value method axi4_s_m_wready
assign axi4_s_wready = axi4_s_xactor_f_wr_data$FULL_N ;
// value method axi4_s_m_bvalid
assign axi4_s_bvalid = axi4_s_xactor_f_wr_resp$EMPTY_N ;
// value method axi4_s_m_bid
assign axi4_s_bid = axi4_s_xactor_f_wr_resp$D_OUT[17:2] ;
// value method axi4_s_m_bresp
assign axi4_s_bresp = axi4_s_xactor_f_wr_resp$D_OUT[1:0] ;
// action method axi4_s_m_bready
assign CAN_FIRE_axi4_s_m_bready = 1'd1 ;
assign WILL_FIRE_axi4_s_m_bready = 1'd1 ;
// action method axi4_s_m_arvalid
assign CAN_FIRE_axi4_s_m_arvalid = 1'd1 ;
assign WILL_FIRE_axi4_s_m_arvalid = 1'd1 ;
// value method axi4_s_m_arready
assign axi4_s_arready = axi4_s_xactor_f_rd_addr$FULL_N ;
// value method axi4_s_m_rvalid
assign axi4_s_rvalid = axi4_s_xactor_f_rd_data$EMPTY_N ;
// value method axi4_s_m_rid
assign axi4_s_rid = axi4_s_xactor_f_rd_data$D_OUT[530:515] ;
// value method axi4_s_m_rdata
assign axi4_s_rdata = axi4_s_xactor_f_rd_data$D_OUT[514:3] ;
// value method axi4_s_m_rresp
assign axi4_s_rresp = axi4_s_xactor_f_rd_data$D_OUT[2:1] ;
// value method axi4_s_m_rlast
assign axi4_s_rlast = axi4_s_xactor_f_rd_data$D_OUT[0] ;
// action method axi4_s_m_rready
assign CAN_FIRE_axi4_s_m_rready = 1'd1 ;
assign WILL_FIRE_axi4_s_m_rready = 1'd1 ;
// value method l1_to_l2_client_request_first
assign l1_to_l2_client_request_first = f_L1_to_L2_Reqs$D_OUT ;
assign RDY_l1_to_l2_client_request_first = f_L1_to_L2_Reqs$EMPTY_N ;
// action method l1_to_l2_client_request_deq
assign RDY_l1_to_l2_client_request_deq = f_L1_to_L2_Reqs$EMPTY_N ;
assign CAN_FIRE_l1_to_l2_client_request_deq = f_L1_to_L2_Reqs$EMPTY_N ;
assign WILL_FIRE_l1_to_l2_client_request_deq =
EN_l1_to_l2_client_request_deq ;
// value method l1_to_l2_client_request_notEmpty
assign l1_to_l2_client_request_notEmpty = f_L1_to_L2_Reqs$EMPTY_N ;
assign RDY_l1_to_l2_client_request_notEmpty = 1'd1 ;
// action method l1_to_l2_client_response_enq
assign RDY_l1_to_l2_client_response_enq = f_L2_to_L1_Rsps$FULL_N ;
assign CAN_FIRE_l1_to_l2_client_response_enq = f_L2_to_L1_Rsps$FULL_N ;
assign WILL_FIRE_l1_to_l2_client_response_enq =
EN_l1_to_l2_client_response_enq ;
// value method l1_to_l2_client_response_notFull
assign l1_to_l2_client_response_notFull = f_L2_to_L1_Rsps$FULL_N ;
assign RDY_l1_to_l2_client_response_notFull = 1'd1 ;
// action method l2_to_l1_server_request_enq
assign RDY_l2_to_l1_server_request_enq = f_L2_to_L1_Reqs$FULL_N ;
assign CAN_FIRE_l2_to_l1_server_request_enq = f_L2_to_L1_Reqs$FULL_N ;
assign WILL_FIRE_l2_to_l1_server_request_enq =
EN_l2_to_l1_server_request_enq ;
// value method l2_to_l1_server_request_notFull
assign l2_to_l1_server_request_notFull = f_L2_to_L1_Reqs$FULL_N ;
assign RDY_l2_to_l1_server_request_notFull = 1'd1 ;
// value method l2_to_l1_server_response_first
assign l2_to_l1_server_response_first = f_L1_to_L2_Rsps$D_OUT ;
assign RDY_l2_to_l1_server_response_first = f_L1_to_L2_Rsps$EMPTY_N ;
// action method l2_to_l1_server_response_deq
assign RDY_l2_to_l1_server_response_deq = f_L1_to_L2_Rsps$EMPTY_N ;
assign CAN_FIRE_l2_to_l1_server_response_deq = f_L1_to_L2_Rsps$EMPTY_N ;
assign WILL_FIRE_l2_to_l1_server_response_deq =
EN_l2_to_l1_server_response_deq ;
// value method l2_to_l1_server_response_notEmpty
assign l2_to_l1_server_response_notEmpty = f_L1_to_L2_Rsps$EMPTY_N ;
assign RDY_l2_to_l1_server_response_notEmpty = 1'd1 ;
// actionvalue method mmio_client_request_get
assign mmio_client_request_get = f_single_reqs$D_OUT ;
assign RDY_mmio_client_request_get = f_single_reqs$EMPTY_N ;
assign CAN_FIRE_mmio_client_request_get = f_single_reqs$EMPTY_N ;
assign WILL_FIRE_mmio_client_request_get = EN_mmio_client_request_get ;
// action method mmio_client_response_put
assign RDY_mmio_client_response_put = f_single_rsps$FULL_N ;
assign CAN_FIRE_mmio_client_response_put = f_single_rsps$FULL_N ;
assign WILL_FIRE_mmio_client_response_put = EN_mmio_client_response_put ;
// submodule axi4_s_xactor_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) axi4_s_xactor_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(axi4_s_xactor_f_rd_addr$D_IN),
.ENQ(axi4_s_xactor_f_rd_addr$ENQ),
.DEQ(axi4_s_xactor_f_rd_addr$DEQ),
.CLR(axi4_s_xactor_f_rd_addr$CLR),
.D_OUT(axi4_s_xactor_f_rd_addr$D_OUT),
.FULL_N(axi4_s_xactor_f_rd_addr$FULL_N),
.EMPTY_N(axi4_s_xactor_f_rd_addr$EMPTY_N));
// submodule axi4_s_xactor_f_rd_data
FIFO2 #(.width(32'd531),
.guarded(1'd1)) axi4_s_xactor_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(axi4_s_xactor_f_rd_data$D_IN),
.ENQ(axi4_s_xactor_f_rd_data$ENQ),
.DEQ(axi4_s_xactor_f_rd_data$DEQ),
.CLR(axi4_s_xactor_f_rd_data$CLR),
.D_OUT(axi4_s_xactor_f_rd_data$D_OUT),
.FULL_N(axi4_s_xactor_f_rd_data$FULL_N),
.EMPTY_N(axi4_s_xactor_f_rd_data$EMPTY_N));
// submodule axi4_s_xactor_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) axi4_s_xactor_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(axi4_s_xactor_f_wr_addr$D_IN),
.ENQ(axi4_s_xactor_f_wr_addr$ENQ),
.DEQ(axi4_s_xactor_f_wr_addr$DEQ),
.CLR(axi4_s_xactor_f_wr_addr$CLR),
.D_OUT(axi4_s_xactor_f_wr_addr$D_OUT),
.FULL_N(axi4_s_xactor_f_wr_addr$FULL_N),
.EMPTY_N(axi4_s_xactor_f_wr_addr$EMPTY_N));
// submodule axi4_s_xactor_f_wr_data
FIFO2 #(.width(32'd577),
.guarded(1'd1)) axi4_s_xactor_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(axi4_s_xactor_f_wr_data$D_IN),
.ENQ(axi4_s_xactor_f_wr_data$ENQ),
.DEQ(axi4_s_xactor_f_wr_data$DEQ),
.CLR(axi4_s_xactor_f_wr_data$CLR),
.D_OUT(axi4_s_xactor_f_wr_data$D_OUT),
.FULL_N(axi4_s_xactor_f_wr_data$FULL_N),
.EMPTY_N(axi4_s_xactor_f_wr_data$EMPTY_N));
// submodule axi4_s_xactor_f_wr_resp
FIFO2 #(.width(32'd18), .guarded(1'd1)) axi4_s_xactor_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(axi4_s_xactor_f_wr_resp$D_IN),
.ENQ(axi4_s_xactor_f_wr_resp$ENQ),
.DEQ(axi4_s_xactor_f_wr_resp$DEQ),
.CLR(axi4_s_xactor_f_wr_resp$CLR),
.D_OUT(axi4_s_xactor_f_wr_resp$D_OUT),
.FULL_N(axi4_s_xactor_f_wr_resp$FULL_N),
.EMPTY_N(axi4_s_xactor_f_wr_resp$EMPTY_N));
// submodule axi4_to_ld_f_axi_rsp_info
FIFO2 #(.width(32'd17),
.guarded(1'd1)) axi4_to_ld_f_axi_rsp_info(.RST(RST_N),
.CLK(CLK),
.D_IN(axi4_to_ld_f_axi_rsp_info$D_IN),
.ENQ(axi4_to_ld_f_axi_rsp_info$ENQ),
.DEQ(axi4_to_ld_f_axi_rsp_info$DEQ),
.CLR(axi4_to_ld_f_axi_rsp_info$CLR),
.D_OUT(axi4_to_ld_f_axi_rsp_info$D_OUT),
.FULL_N(axi4_to_ld_f_axi_rsp_info$FULL_N),
.EMPTY_N(axi4_to_ld_f_axi_rsp_info$EMPTY_N));
// submodule axi4_to_ld_f_ld_rsp_info
SizedFIFO #(.p1width(32'd10),
.p2depth(32'd16),
.p3cntr_width(32'd4),
.guarded(1'd1)) axi4_to_ld_f_ld_rsp_info(.RST(RST_N),
.CLK(CLK),
.D_IN(axi4_to_ld_f_ld_rsp_info$D_IN),
.ENQ(axi4_to_ld_f_ld_rsp_info$ENQ),
.DEQ(axi4_to_ld_f_ld_rsp_info$DEQ),
.CLR(axi4_to_ld_f_ld_rsp_info$CLR),
.D_OUT(axi4_to_ld_f_ld_rsp_info$D_OUT),
.FULL_N(axi4_to_ld_f_ld_rsp_info$FULL_N),
.EMPTY_N(axi4_to_ld_f_ld_rsp_info$EMPTY_N));
// submodule axi4_to_ld_f_reqs
FIFO2 #(.width(32'd66), .guarded(1'd1)) axi4_to_ld_f_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(axi4_to_ld_f_reqs$D_IN),
.ENQ(axi4_to_ld_f_reqs$ENQ),
.DEQ(axi4_to_ld_f_reqs$DEQ),
.CLR(axi4_to_ld_f_reqs$CLR),
.D_OUT(axi4_to_ld_f_reqs$D_OUT),
.FULL_N(axi4_to_ld_f_reqs$FULL_N),
.EMPTY_N(axi4_to_ld_f_reqs$EMPTY_N));
// submodule axi4_to_ld_f_rsps
FIFO2 #(.width(32'd65), .guarded(1'd1)) axi4_to_ld_f_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(axi4_to_ld_f_rsps$D_IN),
.ENQ(axi4_to_ld_f_rsps$ENQ),
.DEQ(axi4_to_ld_f_rsps$DEQ),
.CLR(axi4_to_ld_f_rsps$CLR),
.D_OUT(axi4_to_ld_f_rsps$D_OUT),
.FULL_N(axi4_to_ld_f_rsps$FULL_N),
.EMPTY_N(axi4_to_ld_f_rsps$EMPTY_N));
// submodule axi4_to_st_f_axi_rsp_info
FIFO2 #(.width(32'd17),
.guarded(1'd1)) axi4_to_st_f_axi_rsp_info(.RST(RST_N),
.CLK(CLK),
.D_IN(axi4_to_st_f_axi_rsp_info$D_IN),
.ENQ(axi4_to_st_f_axi_rsp_info$ENQ),
.DEQ(axi4_to_st_f_axi_rsp_info$DEQ),
.CLR(axi4_to_st_f_axi_rsp_info$CLR),
.D_OUT(axi4_to_st_f_axi_rsp_info$D_OUT),
.FULL_N(axi4_to_st_f_axi_rsp_info$FULL_N),
.EMPTY_N(axi4_to_st_f_axi_rsp_info$EMPTY_N));
// submodule axi4_to_st_f_reqs
FIFO2 #(.width(32'd130), .guarded(1'd1)) axi4_to_st_f_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(axi4_to_st_f_reqs$D_IN),
.ENQ(axi4_to_st_f_reqs$ENQ),
.DEQ(axi4_to_st_f_reqs$DEQ),
.CLR(axi4_to_st_f_reqs$CLR),
.D_OUT(axi4_to_st_f_reqs$D_OUT),
.FULL_N(axi4_to_st_f_reqs$FULL_N),
.EMPTY_N(axi4_to_st_f_reqs$EMPTY_N));
// submodule axi4_to_st_f_rsps
FIFO2 #(.width(32'd1), .guarded(1'd1)) axi4_to_st_f_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(axi4_to_st_f_rsps$D_IN),
.ENQ(axi4_to_st_f_rsps$ENQ),
.DEQ(axi4_to_st_f_rsps$DEQ),
.CLR(axi4_to_st_f_rsps$CLR),
.D_OUT(axi4_to_st_f_rsps$D_OUT),
.FULL_N(axi4_to_st_f_rsps$FULL_N),
.EMPTY_N(axi4_to_st_f_rsps$EMPTY_N));
// submodule axi4_to_st_f_st_rsp_info
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd16),
.p3cntr_width(32'd4),
.guarded(1'd1)) axi4_to_st_f_st_rsp_info(.RST(RST_N),
.CLK(CLK),
.D_IN(axi4_to_st_f_st_rsp_info$D_IN),
.ENQ(axi4_to_st_f_st_rsp_info$ENQ),
.DEQ(axi4_to_st_f_st_rsp_info$DEQ),
.CLR(axi4_to_st_f_st_rsp_info$CLR),
.D_OUT(axi4_to_st_f_st_rsp_info$D_OUT),
.FULL_N(axi4_to_st_f_st_rsp_info$FULL_N),
.EMPTY_N(axi4_to_st_f_st_rsp_info$EMPTY_N));
// submodule f_L1_to_L2_Reqs
FIFO2 #(.width(32'd69), .guarded(1'd1)) f_L1_to_L2_Reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_L1_to_L2_Reqs$D_IN),
.ENQ(f_L1_to_L2_Reqs$ENQ),
.DEQ(f_L1_to_L2_Reqs$DEQ),
.CLR(f_L1_to_L2_Reqs$CLR),
.D_OUT(f_L1_to_L2_Reqs$D_OUT),
.FULL_N(f_L1_to_L2_Reqs$FULL_N),
.EMPTY_N(f_L1_to_L2_Reqs$EMPTY_N));
// submodule f_L1_to_L2_Rsps
FIFO2 #(.width(32'd579), .guarded(1'd1)) f_L1_to_L2_Rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_L1_to_L2_Rsps$D_IN),
.ENQ(f_L1_to_L2_Rsps$ENQ),
.DEQ(f_L1_to_L2_Rsps$DEQ),
.CLR(f_L1_to_L2_Rsps$CLR),
.D_OUT(f_L1_to_L2_Rsps$D_OUT),
.FULL_N(f_L1_to_L2_Rsps$FULL_N),
.EMPTY_N(f_L1_to_L2_Rsps$EMPTY_N));
// submodule f_L2_to_L1_Reqs
FIFO2 #(.width(32'd66), .guarded(1'd1)) f_L2_to_L1_Reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_L2_to_L1_Reqs$D_IN),
.ENQ(f_L2_to_L1_Reqs$ENQ),
.DEQ(f_L2_to_L1_Reqs$DEQ),
.CLR(f_L2_to_L1_Reqs$CLR),
.D_OUT(f_L2_to_L1_Reqs$D_OUT),
.FULL_N(f_L2_to_L1_Reqs$FULL_N),
.EMPTY_N(f_L2_to_L1_Reqs$EMPTY_N));
// submodule f_L2_to_L1_Rsps
FIFO2 #(.width(32'd579), .guarded(1'd1)) f_L2_to_L1_Rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_L2_to_L1_Rsps$D_IN),
.ENQ(f_L2_to_L1_Rsps$ENQ),
.DEQ(f_L2_to_L1_Rsps$DEQ),
.CLR(f_L2_to_L1_Rsps$CLR),
.D_OUT(f_L2_to_L1_Rsps$D_OUT),
.FULL_N(f_L2_to_L1_Rsps$FULL_N),
.EMPTY_N(f_L2_to_L1_Rsps$EMPTY_N));
// submodule f_mmio_rsp_is_load
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd16),
.p3cntr_width(32'd4),
.guarded(1'd1)) f_mmio_rsp_is_load(.RST(RST_N),
.CLK(CLK),
.D_IN(f_mmio_rsp_is_load$D_IN),
.ENQ(f_mmio_rsp_is_load$ENQ),
.DEQ(f_mmio_rsp_is_load$DEQ),
.CLR(f_mmio_rsp_is_load$CLR),
.D_OUT(f_mmio_rsp_is_load$D_OUT),
.FULL_N(f_mmio_rsp_is_load$FULL_N),
.EMPTY_N(f_mmio_rsp_is_load$EMPTY_N));
// submodule f_rd_addr
FIFO2 #(.width(32'd109), .guarded(1'd1)) f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(f_rd_addr$D_IN),
.ENQ(f_rd_addr$ENQ),
.DEQ(f_rd_addr$DEQ),
.CLR(f_rd_addr$CLR),
.D_OUT(f_rd_addr$D_OUT),
.FULL_N(f_rd_addr$FULL_N),
.EMPTY_N(f_rd_addr$EMPTY_N));
// submodule f_rd_data
FIFO2 #(.width(32'd531), .guarded(1'd1)) f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(f_rd_data$D_IN),
.ENQ(f_rd_data$ENQ),
.DEQ(f_rd_data$DEQ),
.CLR(f_rd_data$CLR),
.D_OUT(f_rd_data$D_OUT),
.FULL_N(f_rd_data$FULL_N),
.EMPTY_N(f_rd_data$EMPTY_N));
// submodule f_reqs
FIFO2 #(.width(32'd686), .guarded(1'd1)) f_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reqs$D_IN),
.ENQ(f_reqs$ENQ),
.DEQ(f_reqs$DEQ),
.CLR(f_reqs$CLR),
.D_OUT(f_reqs$D_OUT),
.FULL_N(f_reqs$FULL_N),
.EMPTY_N(f_reqs$EMPTY_N));
// submodule f_single_reqs
FIFO2 #(.width(32'd131), .guarded(1'd1)) f_single_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_single_reqs$D_IN),
.ENQ(f_single_reqs$ENQ),
.DEQ(f_single_reqs$DEQ),
.CLR(f_single_reqs$CLR),
.D_OUT(f_single_reqs$D_OUT),
.FULL_N(f_single_reqs$FULL_N),
.EMPTY_N(f_single_reqs$EMPTY_N));
// submodule f_single_rsps
FIFO2 #(.width(32'd65), .guarded(1'd1)) f_single_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_single_rsps$D_IN),
.ENQ(f_single_rsps$ENQ),
.DEQ(f_single_rsps$DEQ),
.CLR(f_single_rsps$CLR),
.D_OUT(f_single_rsps$D_OUT),
.FULL_N(f_single_rsps$FULL_N),
.EMPTY_N(f_single_rsps$EMPTY_N));
// submodule f_wr_addr
FIFO2 #(.width(32'd109), .guarded(1'd1)) f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(f_wr_addr$D_IN),
.ENQ(f_wr_addr$ENQ),
.DEQ(f_wr_addr$DEQ),
.CLR(f_wr_addr$CLR),
.D_OUT(f_wr_addr$D_OUT),
.FULL_N(f_wr_addr$FULL_N),
.EMPTY_N(f_wr_addr$EMPTY_N));
// submodule f_wr_data
FIFO2 #(.width(32'd577), .guarded(1'd1)) f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(f_wr_data$D_IN),
.ENQ(f_wr_data$ENQ),
.DEQ(f_wr_data$DEQ),
.CLR(f_wr_data$CLR),
.D_OUT(f_wr_data$D_OUT),
.FULL_N(f_wr_data$FULL_N),
.EMPTY_N(f_wr_data$EMPTY_N));
// submodule f_wr_resp
FIFO2 #(.width(32'd18), .guarded(1'd1)) f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(f_wr_resp$D_IN),
.ENQ(f_wr_resp$ENQ),
.DEQ(f_wr_resp$DEQ),
.CLR(f_wr_resp$CLR),
.D_OUT(f_wr_resp$D_OUT),
.FULL_N(f_wr_resp$FULL_N),
.EMPTY_N(f_wr_resp$EMPTY_N));
// submodule rf_data_sets
RegFile #(.addr_width(32'd6),
.data_width(32'd512),
.lo(6'h0),
.hi(6'd63)) rf_data_sets(.CLK(CLK),
.ADDR_1(rf_data_sets$ADDR_1),
.ADDR_2(rf_data_sets$ADDR_2),
.ADDR_3(rf_data_sets$ADDR_3),
.ADDR_4(rf_data_sets$ADDR_4),
.ADDR_5(rf_data_sets$ADDR_5),
.ADDR_IN(rf_data_sets$ADDR_IN),
.D_IN(rf_data_sets$D_IN),
.WE(rf_data_sets$WE),
.D_OUT_1(rf_data_sets$D_OUT_1),
.D_OUT_2(),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule rf_tag_sets
RegFile #(.addr_width(32'd6),
.data_width(32'd66),
.lo(6'h0),
.hi(6'd63)) rf_tag_sets(.CLK(CLK),
.ADDR_1(rf_tag_sets$ADDR_1),
.ADDR_2(rf_tag_sets$ADDR_2),
.ADDR_3(rf_tag_sets$ADDR_3),
.ADDR_4(rf_tag_sets$ADDR_4),
.ADDR_5(rf_tag_sets$ADDR_5),
.ADDR_IN(rf_tag_sets$ADDR_IN),
.D_IN(rf_tag_sets$D_IN),
.WE(rf_tag_sets$WE),
.D_OUT_1(rf_tag_sets$D_OUT_1),
.D_OUT_2(rf_tag_sets$D_OUT_2),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// rule RL_rl_init
assign CAN_FIRE_RL_rl_init = rg_state == 2'd0 ;
assign WILL_FIRE_RL_rl_init = CAN_FIRE_RL_rl_init ;
// rule RL_rl_merge_rd_req
assign CAN_FIRE_RL_rl_merge_rd_req =
axi4_s_xactor_f_rd_addr$EMPTY_N && f_reqs$FULL_N &&
(!axi4_s_xactor_f_rd_addr_first__0_BITS_92_TO_29_ETC___d12 &&
axi4_s_xactor_f_rd_addr_first__0_BITS_92_TO_29_ETC___d14 ||
!axi4_s_xactor_f_rd_addr_first__0_BITS_92_TO_29_ETC___d16 &&
axi4_s_xactor_f_rd_addr_first__0_BITS_92_TO_29_ETC___d18) ;
assign WILL_FIRE_RL_rl_merge_rd_req = CAN_FIRE_RL_rl_merge_rd_req ;
// rule RL_rl_merge_wr_req
assign CAN_FIRE_RL_rl_merge_wr_req =
f_reqs$FULL_N && axi4_s_xactor_f_wr_addr$EMPTY_N &&
axi4_s_xactor_f_wr_data$EMPTY_N &&
(!axi4_s_xactor_f_wr_addr_first__0_BITS_92_TO_29_ETC___d42 &&
axi4_s_xactor_f_wr_addr_first__0_BITS_92_TO_29_ETC___d44 ||
!axi4_s_xactor_f_wr_addr_first__0_BITS_92_TO_29_ETC___d46 &&
axi4_s_xactor_f_wr_addr_first__0_BITS_92_TO_29_ETC___d48) ;
assign WILL_FIRE_RL_rl_merge_wr_req =
CAN_FIRE_RL_rl_merge_wr_req && !WILL_FIRE_RL_rl_merge_rd_req ;
// rule RL_rl_downgrade
assign CAN_FIRE_RL_rl_downgrade =
f_L2_to_L1_Reqs$EMPTY_N &&
(rf_tag_sets$D_OUT_2[65:64] == 2'd0 ||
rf_tag_sets_sub_f_L2_to_L1_Reqs_first__1_BITS__ETC___d77 ||
!rf_tag_sets_sub_f_L2_to_L1_Reqs_first__1_BITS__ETC___d82 ||
f_L1_to_L2_Rsps$FULL_N) &&
rg_state != 2'd0 ;
assign WILL_FIRE_RL_rl_downgrade = CAN_FIRE_RL_rl_downgrade ;
// rule RL_rl_evict
assign CAN_FIRE_RL_rl_evict =
f_L1_to_L2_Rsps$FULL_N && f_reqs$EMPTY_N && rg_state == 2'd1 &&
!f_L2_to_L1_Reqs$EMPTY_N &&
rf_tag_sets$D_OUT_1[65:64] != 2'd0 &&
!rf_tag_sets_sub_f_reqs_first__05_BITS_616_TO_6_ETC___d114 ;
assign WILL_FIRE_RL_rl_evict = CAN_FIRE_RL_rl_evict ;
// rule RL_rl_hit
assign CAN_FIRE_RL_rl_hit =
f_reqs$EMPTY_N &&
IF_f_reqs_first__05_BIT_685_24_THEN_axi4_s_xac_ETC___d127 &&
rg_state == 2'd1 &&
!f_L2_to_L1_Reqs$EMPTY_N &&
NOT_f_reqs_first__05_BIT_685_24_29_AND_NOT_rf__ETC___d135 ;
assign WILL_FIRE_RL_rl_hit = CAN_FIRE_RL_rl_hit ;
// rule RL_rl_upgrade_req
assign CAN_FIRE_RL_rl_upgrade_req = MUX_rg_state$write_1__SEL_3 ;
assign WILL_FIRE_RL_rl_upgrade_req = MUX_rg_state$write_1__SEL_3 ;
// rule RL_rl_upgrade_rsp
assign CAN_FIRE_RL_rl_upgrade_rsp = MUX_rg_state$write_1__SEL_2 ;
assign WILL_FIRE_RL_rl_upgrade_rsp = MUX_rg_state$write_1__SEL_2 ;
// rule RL_rl_mmio_AXI_rd_req
assign CAN_FIRE_RL_rl_mmio_AXI_rd_req =
axi4_s_xactor_f_rd_addr$EMPTY_N && f_rd_addr$FULL_N &&
(axi4_s_xactor_f_rd_addr_first__0_BITS_92_TO_29_ETC___d12 ||
!axi4_s_xactor_f_rd_addr_first__0_BITS_92_TO_29_ETC___d14) &&
(axi4_s_xactor_f_rd_addr_first__0_BITS_92_TO_29_ETC___d16 ||
!axi4_s_xactor_f_rd_addr_first__0_BITS_92_TO_29_ETC___d18) ;
assign WILL_FIRE_RL_rl_mmio_AXI_rd_req = CAN_FIRE_RL_rl_mmio_AXI_rd_req ;
// rule RL_rl_mmio_LD_req
assign CAN_FIRE_RL_rl_mmio_LD_req = MUX_f_single_reqs$enq_1__SEL_1 ;
assign WILL_FIRE_RL_rl_mmio_LD_req = MUX_f_single_reqs$enq_1__SEL_1 ;
// rule RL_rl_mmio_LD_rsp
assign CAN_FIRE_RL_rl_mmio_LD_rsp =
f_mmio_rsp_is_load$EMPTY_N && f_single_rsps$EMPTY_N &&
axi4_to_ld_f_rsps$FULL_N &&
f_mmio_rsp_is_load$D_OUT ;
assign WILL_FIRE_RL_rl_mmio_LD_rsp = CAN_FIRE_RL_rl_mmio_LD_rsp ;
// rule RL_rl_mmio_AXI_rd_rsp
assign CAN_FIRE_RL_rl_mmio_AXI_rd_rsp =
axi4_s_xactor_f_rd_data$FULL_N && f_rd_data$EMPTY_N ;
assign WILL_FIRE_RL_rl_mmio_AXI_rd_rsp =
CAN_FIRE_RL_rl_mmio_AXI_rd_rsp && !WILL_FIRE_RL_rl_upgrade_rsp &&
!WILL_FIRE_RL_rl_hit ;
// rule RL_rl_mmio_axi_wr_req
assign CAN_FIRE_RL_rl_mmio_axi_wr_req =
axi4_s_xactor_f_wr_addr$EMPTY_N &&
axi4_s_xactor_f_wr_data$EMPTY_N &&
f_wr_addr$FULL_N &&
f_wr_data$FULL_N &&
(axi4_s_xactor_f_wr_addr_first__0_BITS_92_TO_29_ETC___d42 ||
!axi4_s_xactor_f_wr_addr_first__0_BITS_92_TO_29_ETC___d44) &&
(axi4_s_xactor_f_wr_addr_first__0_BITS_92_TO_29_ETC___d46 ||
!axi4_s_xactor_f_wr_addr_first__0_BITS_92_TO_29_ETC___d48) ;
assign WILL_FIRE_RL_rl_mmio_axi_wr_req = CAN_FIRE_RL_rl_mmio_axi_wr_req ;
// rule RL_rl_mmio_ST_req
assign CAN_FIRE_RL_rl_mmio_ST_req =
f_single_reqs$FULL_N && f_mmio_rsp_is_load$FULL_N &&
axi4_to_st_f_reqs$EMPTY_N ;
assign WILL_FIRE_RL_rl_mmio_ST_req = MUX_f_single_reqs$enq_1__SEL_2 ;
// rule RL_rl_mmio_st_rsp
assign CAN_FIRE_RL_rl_mmio_st_rsp =
f_mmio_rsp_is_load$EMPTY_N && axi4_to_st_f_rsps$FULL_N &&
!f_mmio_rsp_is_load$D_OUT ;
assign WILL_FIRE_RL_rl_mmio_st_rsp = CAN_FIRE_RL_rl_mmio_st_rsp ;
// rule RL_rl_mmio_axi_wr_rsp
assign CAN_FIRE_RL_rl_mmio_axi_wr_rsp =
axi4_s_xactor_f_wr_resp$FULL_N && f_wr_resp$EMPTY_N ;
assign WILL_FIRE_RL_rl_mmio_axi_wr_rsp =
CAN_FIRE_RL_rl_mmio_axi_wr_rsp && !WILL_FIRE_RL_rl_upgrade_rsp &&
!WILL_FIRE_RL_rl_hit ;
// rule RL_axi4_to_ld_rl_start_xaction
assign CAN_FIRE_RL_axi4_to_ld_rl_start_xaction =
f_rd_addr$EMPTY_N &&
NOT_f_rd_addr_first__62_BITS_28_TO_21_63_EQ_0__ETC___d679 &&
axi4_to_ld_rg_state == 3'd0 ;
assign WILL_FIRE_RL_axi4_to_ld_rl_start_xaction =
CAN_FIRE_RL_axi4_to_ld_rl_start_xaction ;
// rule RL_axi4_to_ld_rl_next_slice
assign CAN_FIRE_RL_axi4_to_ld_rl_next_slice =
f_rd_addr$EMPTY_N && axi4_to_ld_f_ld_rsp_info$FULL_N &&
(axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_U_ETC___d758 ||
axi4_to_ld_f_reqs$FULL_N) &&
axi4_to_ld_rg_state == 3'd2 ;
assign WILL_FIRE_RL_axi4_to_ld_rl_next_slice =
CAN_FIRE_RL_axi4_to_ld_rl_next_slice ;
// rule RL_axi4_to_ld_rl_partial
assign CAN_FIRE_RL_axi4_to_ld_rl_partial =
f_rd_addr$EMPTY_N && axi4_to_ld_f_ld_rsp_info$FULL_N &&
axi4_to_ld_f_reqs$FULL_N &&
axi4_to_ld_rg_state == 3'd1 ;
assign WILL_FIRE_RL_axi4_to_ld_rl_partial =
CAN_FIRE_RL_axi4_to_ld_rl_partial ;
// rule RL_axi4_to_ld_rl_finish_req
assign CAN_FIRE_RL_axi4_to_ld_rl_finish_req =
f_rd_addr$EMPTY_N && axi4_to_ld_f_ld_rsp_info$FULL_N &&
axi4_to_ld_f_axi_rsp_info$FULL_N &&
axi4_to_ld_rg_state == 3'd3 ;
assign WILL_FIRE_RL_axi4_to_ld_rl_finish_req =
CAN_FIRE_RL_axi4_to_ld_rl_finish_req ;
// rule RL_axi4_to_ld_rl_handle_ld_rsp
assign CAN_FIRE_RL_axi4_to_ld_rl_handle_ld_rsp =
axi4_to_ld_f_ld_rsp_info$EMPTY_N && axi4_to_ld_f_rsps$EMPTY_N &&
(axi4_to_ld_f_ld_rsp_info$D_OUT[9:8] == 2'd0 ||
axi4_to_ld_f_ld_rsp_info$D_OUT[9:8] == 2'd1) ;
assign WILL_FIRE_RL_axi4_to_ld_rl_handle_ld_rsp =
CAN_FIRE_RL_axi4_to_ld_rl_handle_ld_rsp ;
// rule RL_axi4_to_ld_rl_handle_ld_slice_ignore
assign CAN_FIRE_RL_axi4_to_ld_rl_handle_ld_slice_ignore =
axi4_to_ld_f_ld_rsp_info$EMPTY_N &&
axi4_to_ld_f_ld_rsp_info$D_OUT[9:8] == 2'd2 ;
assign WILL_FIRE_RL_axi4_to_ld_rl_handle_ld_slice_ignore =
CAN_FIRE_RL_axi4_to_ld_rl_handle_ld_slice_ignore ;
// rule RL_axi4_to_ld_rl_shift_tail_slices
assign CAN_FIRE_RL_axi4_to_ld_rl_shift_tail_slices =
axi4_to_ld_f_ld_rsp_info$EMPTY_N &&
axi4_to_ld_f_ld_rsp_info$D_OUT[9:8] == 2'd3 &&
axi4_to_ld_rg_remaining_slices != 4'd0 ;
assign WILL_FIRE_RL_axi4_to_ld_rl_shift_tail_slices =
CAN_FIRE_RL_axi4_to_ld_rl_shift_tail_slices ;
// rule RL_axi4_to_ld_rl_send_axi_response
assign CAN_FIRE_RL_axi4_to_ld_rl_send_axi_response =
axi4_to_ld_f_ld_rsp_info$EMPTY_N &&
axi4_to_ld_f_axi_rsp_info$EMPTY_N &&
f_rd_data$FULL_N &&
axi4_to_ld_f_ld_rsp_info$D_OUT[9:8] == 2'd3 &&
axi4_to_ld_rg_remaining_slices == 4'd0 ;
assign WILL_FIRE_RL_axi4_to_ld_rl_send_axi_response =
CAN_FIRE_RL_axi4_to_ld_rl_send_axi_response ;
// rule RL_axi4_to_ld_rl_illegal_req
assign CAN_FIRE_RL_axi4_to_ld_rl_illegal_req =
f_rd_addr$EMPTY_N && axi4_to_ld_f_ld_rsp_info$FULL_N &&
axi4_to_ld_f_axi_rsp_info$FULL_N &&
axi4_to_ld_rg_state == 3'd4 ;
assign WILL_FIRE_RL_axi4_to_ld_rl_illegal_req =
CAN_FIRE_RL_axi4_to_ld_rl_illegal_req ;
// rule RL_axi4_to_st_rl_start_xaction
assign CAN_FIRE_RL_axi4_to_st_rl_start_xaction =
f_wr_addr$EMPTY_N && f_wr_data$EMPTY_N &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930 ||
f_wr_data_first__21_BITS_8_TO_1_34_EQ_0_35_OR__ETC___d975) &&
axi4_to_st_rg_state == 3'd0 ;
assign WILL_FIRE_RL_axi4_to_st_rl_start_xaction =
CAN_FIRE_RL_axi4_to_st_rl_start_xaction ;
// rule RL_axi4_to_st_rl_next_slice
assign CAN_FIRE_RL_axi4_to_st_rl_next_slice =
(axi4_to_st_rg_v_strb[7:0] == 8'd0 || f_wr_addr$EMPTY_N) &&
axi4_to_st_rg_v_strb_075_BITS_7_TO_0_076_EQ_0__ETC___d1116 &&
(axi4_to_st_rg_v_strb[7:0] != 8'd0 &&
!axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1113 ||
v__h60059 != 8'd0 ||
f_wr_addr$EMPTY_N) &&
axi4_to_st_rg_state == 3'd2 ;
assign WILL_FIRE_RL_axi4_to_st_rl_next_slice =
CAN_FIRE_RL_axi4_to_st_rl_next_slice ;
// rule RL_axi4_to_st_rl_partial
assign CAN_FIRE_RL_axi4_to_st_rl_partial =
f_wr_addr$EMPTY_N && axi4_to_st_f_reqs$FULL_N &&
axi4_to_st_f_st_rsp_info$FULL_N &&
axi4_to_st_rg_state == 3'd1 ;
assign WILL_FIRE_RL_axi4_to_st_rl_partial =
CAN_FIRE_RL_axi4_to_st_rl_partial ;
// rule RL_axi4_to_st_rl_finish_req
assign CAN_FIRE_RL_axi4_to_st_rl_finish_req =
f_wr_addr$EMPTY_N && f_wr_data$EMPTY_N &&
axi4_to_st_f_st_rsp_info$FULL_N &&
axi4_to_st_f_axi_rsp_info$FULL_N &&
axi4_to_st_rg_state == 3'd3 ;
assign WILL_FIRE_RL_axi4_to_st_rl_finish_req =
CAN_FIRE_RL_axi4_to_st_rl_finish_req ;
// rule RL_axi4_to_st_rl_handle_st_rsps
assign CAN_FIRE_RL_axi4_to_st_rl_handle_st_rsps =
axi4_to_st_f_st_rsp_info$EMPTY_N && axi4_to_st_f_rsps$EMPTY_N &&
!axi4_to_st_f_st_rsp_info$D_OUT ;
assign WILL_FIRE_RL_axi4_to_st_rl_handle_st_rsps =
CAN_FIRE_RL_axi4_to_st_rl_handle_st_rsps ;
// rule RL_axi4_to_st_rl_send_axi_response
assign CAN_FIRE_RL_axi4_to_st_rl_send_axi_response =
axi4_to_st_f_st_rsp_info$EMPTY_N &&
axi4_to_st_f_axi_rsp_info$EMPTY_N &&
f_wr_resp$FULL_N &&
axi4_to_st_f_st_rsp_info$D_OUT ;
assign WILL_FIRE_RL_axi4_to_st_rl_send_axi_response =
CAN_FIRE_RL_axi4_to_st_rl_send_axi_response ;
// rule RL_axi4_to_st_rl_illegal_req
assign CAN_FIRE_RL_axi4_to_st_rl_illegal_req =
f_wr_data$EMPTY_N &&
(axi4_to_st_rg_discard_count != 8'd0 ||
f_wr_addr$EMPTY_N && axi4_to_st_f_st_rsp_info$FULL_N &&
axi4_to_st_f_axi_rsp_info$FULL_N) &&
axi4_to_st_rg_state == 3'd4 ;
assign WILL_FIRE_RL_axi4_to_st_rl_illegal_req =
CAN_FIRE_RL_axi4_to_st_rl_illegal_req ;
// inputs to muxes for submodule ports
assign MUX_axi4_s_xactor_f_rd_data$enq_1__SEL_1 =
WILL_FIRE_RL_rl_hit && !f_reqs$D_OUT[685] ;
assign MUX_axi4_s_xactor_f_rd_data$enq_1__SEL_2 =
WILL_FIRE_RL_rl_upgrade_rsp && !f_reqs$D_OUT[685] ;
assign MUX_axi4_s_xactor_f_wr_resp$enq_1__PSEL_1 =
WILL_FIRE_RL_rl_upgrade_rsp || WILL_FIRE_RL_rl_hit ;
assign MUX_axi4_s_xactor_f_wr_resp$enq_1__SEL_1 =
MUX_axi4_s_xactor_f_wr_resp$enq_1__PSEL_1 && f_reqs$D_OUT[685] ;
assign MUX_axi4_to_ld_f_ld_rsp_info$enq_1__SEL_1 =
WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
f_rd_addr$D_OUT[28:21] == 8'd0 &&
_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668 ;
assign MUX_axi4_to_ld_f_ld_rsp_info$enq_1__SEL_2 =
WILL_FIRE_RL_axi4_to_ld_rl_illegal_req ||
WILL_FIRE_RL_axi4_to_ld_rl_finish_req ;
assign MUX_axi4_to_ld_f_reqs$enq_1__SEL_1 =
WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
f_rd_addr$D_OUT[28:21] == 8'd0 &&
_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668 &&
_0_CONCAT_f_rd_addr_first__62_BITS_34_TO_29_72__ETC___d674 ;
assign MUX_axi4_to_ld_f_reqs$enq_1__SEL_2 =
WILL_FIRE_RL_axi4_to_ld_rl_next_slice &&
!axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_U_ETC___d758 ;
assign MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__SEL_1 =
WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
f_rd_addr$D_OUT[28:21] == 8'd0 &&
_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668 &&
(v__h42404 != 8'd0 ||
!_0_CONCAT_f_rd_addr_first__62_BITS_92_TO_29_90__ETC___d746) ;
assign MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__SEL_2 =
WILL_FIRE_RL_axi4_to_ld_rl_next_slice && v__h44351 == 8'd0 &&
axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_U_ETC___d793 ;
assign MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__SEL_3 =
WILL_FIRE_RL_axi4_to_ld_rl_partial && v__h44974 == 8'd0 &&
axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_U_ETC___d793 ;
assign MUX_axi4_to_ld_rg_remaining_slices$write_1__SEL_1 =
WILL_FIRE_RL_axi4_to_ld_rl_handle_ld_rsp &&
axi4_to_ld_f_ld_rsp_info$D_OUT[9:8] == 2'd0 ;
assign MUX_axi4_to_ld_rg_remaining_slices$write_1__SEL_2 =
WILL_FIRE_RL_axi4_to_ld_rl_shift_tail_slices ||
WILL_FIRE_RL_axi4_to_ld_rl_handle_ld_slice_ignore ;
assign MUX_axi4_to_st_f_axi_rsp_info$enq_1__SEL_1 =
WILL_FIRE_RL_axi4_to_st_rl_illegal_req &&
axi4_to_st_rg_discard_count == 8'd0 ;
assign MUX_axi4_to_st_f_reqs$enq_1__SEL_1 =
WILL_FIRE_RL_axi4_to_st_rl_next_slice &&
axi4_to_st_rg_v_strb[7:0] != 8'd0 &&
!axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1113 ;
assign MUX_axi4_to_st_f_reqs$enq_1__SEL_2 =
WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
f_wr_data_first__21_BIT_0_22_AND_f_wr_addr_fir_ETC___d1001 ;
assign MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_1 =
WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
f_wr_data_first__21_BIT_0_22_AND_f_wr_addr_fir_ETC___d1066 ;
assign MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_2 =
WILL_FIRE_RL_axi4_to_st_rl_next_slice && v__h60059 == 8'd0 &&
axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1165 ;
assign MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_3 =
WILL_FIRE_RL_axi4_to_st_rl_partial && v__h65821 == 8'd0 &&
axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1165 ;
assign MUX_axi4_to_st_rg_discard_count$write_1__SEL_1 =
WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930) ;
assign MUX_f_L1_to_L2_Rsps$enq_1__SEL_1 =
WILL_FIRE_RL_rl_downgrade &&
rf_tag_sets$D_OUT_2[65:64] != 2'd0 &&
!rf_tag_sets_sub_f_L2_to_L1_Reqs_first__1_BITS__ETC___d77 &&
rf_tag_sets_sub_f_L2_to_L1_Reqs_first__1_BITS__ETC___d82 ;
assign MUX_f_single_reqs$enq_1__SEL_1 =
axi4_to_ld_f_reqs$EMPTY_N && f_single_reqs$FULL_N &&
f_mmio_rsp_is_load$FULL_N ;
assign MUX_f_single_reqs$enq_1__SEL_2 =
CAN_FIRE_RL_rl_mmio_ST_req && !WILL_FIRE_RL_rl_mmio_LD_req ;
assign MUX_rg_state$write_1__SEL_1 =
WILL_FIRE_RL_rl_init && rg_init_index == 6'd63 ;
assign MUX_rg_state$write_1__SEL_2 =
f_reqs$EMPTY_N && f_L2_to_L1_Rsps$EMPTY_N &&
IF_f_reqs_first__05_BIT_685_24_THEN_axi4_s_xac_ETC___d127 &&
rg_state == 2'd3 &&
!f_L2_to_L1_Reqs$EMPTY_N ;
assign MUX_rg_state$write_1__SEL_3 =
f_reqs$EMPTY_N && f_L1_to_L2_Reqs$FULL_N &&
rg_state_EQ_1_01_AND_NOT_f_L2_to_L1_Reqs_notEm_ETC___d438 ;
assign MUX_axi4_s_xactor_f_rd_data$enq_1__VAL_1 =
{ f_reqs$D_OUT[684:669], rf_data_sets$D_OUT_1, 3'd1 } ;
assign MUX_axi4_s_xactor_f_rd_data$enq_1__VAL_2 =
{ f_reqs$D_OUT[684:669], v__h22217, 3'd1 } ;
assign MUX_axi4_s_xactor_f_wr_resp$enq_1__VAL_1 =
{ f_reqs$D_OUT[684:669], 2'd0 } ;
assign MUX_axi4_to_ld_f_axi_rsp_info$enq_1__VAL_1 =
{ 1'd0, f_rd_addr$D_OUT[108:93] } ;
assign MUX_axi4_to_ld_f_axi_rsp_info$enq_1__VAL_2 =
{ 1'd1, f_rd_addr$D_OUT[108:93] } ;
assign MUX_axi4_to_ld_f_ld_rsp_info$enq_1__VAL_1 =
_0_CONCAT_f_rd_addr_first__62_BITS_34_TO_29_72__ETC___d674 ?
{ 4'd0, f_rd_addr$D_OUT[34:29] } :
10'd682 ;
assign MUX_axi4_to_ld_f_ld_rsp_info$enq_1__VAL_3 =
axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_U_ETC___d758 ?
10'd682 :
{ 2'd0, x__h44726 } ;
assign MUX_axi4_to_ld_f_ld_rsp_info$enq_1__VAL_4 = { 2'd1, x__h45274 } ;
assign MUX_axi4_to_ld_f_reqs$enq_1__VAL_1 =
{ x__h42811, f_rd_addr$D_OUT[92:29] } ;
assign MUX_axi4_to_ld_f_reqs$enq_1__VAL_2 = { x__h44699, x__h44701 } ;
assign MUX_axi4_to_ld_f_reqs$enq_1__VAL_3 = { x__h45247, x__h45249 } ;
assign MUX_axi4_to_ld_rg_bytelane_lo$write_1__VAL_1 =
bytelane_lo__h42399 + bytes_processed__h42786 ;
assign MUX_axi4_to_ld_rg_bytelane_lo$write_1__VAL_2 =
bytelane_lo__h44346 + bytes_processed__h44683 ;
assign MUX_axi4_to_ld_rg_bytelane_lo$write_1__VAL_3 =
axi4_to_ld_rg_bytelane_lo + bytes_processed__h45231 ;
assign MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__VAL_1 =
(v__h42404 == 8'd0) ? 8'd8 : 8'd0 ;
assign MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__VAL_2 =
axi4_to_ld_rg_bytelane_slice_lo + 8'd8 ;
assign MUX_axi4_to_ld_rg_remaining_slices$write_1__VAL_1 =
axi4_to_ld_rg_remaining_slices - 4'd1 ;
assign MUX_axi4_to_ld_rg_state$write_1__VAL_1 =
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668) ?
3'd4 :
((v__h42404 == 8'd0) ?
(_0_CONCAT_f_rd_addr_first__62_BITS_92_TO_29_90__ETC___d746 ?
3'd3 :
3'd2) :
3'd1) ;
assign MUX_axi4_to_ld_rg_state$write_1__VAL_2 =
(v__h44351 == 8'd0) ?
IF_axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_5_ETC___d796 :
3'd1 ;
assign MUX_axi4_to_ld_rg_state$write_1__VAL_3 =
(v__h44974 == 8'd0) ?
IF_axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_5_ETC___d796 :
3'd1 ;
assign MUX_axi4_to_ld_rg_v_slice$write_1__VAL_1 =
{ 64'd0, axi4_to_ld_rg_v_slice[511:64] } ;
assign MUX_axi4_to_ld_rg_v_slice$write_1__VAL_2 =
(axi4_to_ld_f_ld_rsp_info$D_OUT[9:8] == 2'd0) ?
{ slice__h45713, axi4_to_ld_rg_v_slice[511:64] } :
{ axi4_to_ld_rg_v_slice[511:448] | slice__h45713,
axi4_to_ld_rg_v_slice[447:0] } ;
assign MUX_axi4_to_st_f_axi_rsp_info$enq_1__VAL_1 =
{ 1'd1, f_wr_addr$D_OUT[108:93] } ;
assign MUX_axi4_to_st_f_axi_rsp_info$enq_1__VAL_2 =
{ 1'd0, f_wr_addr$D_OUT[108:93] } ;
assign MUX_axi4_to_st_f_reqs$enq_1__VAL_1 =
{ x__h62654, x__h62659, x__h62662 } ;
assign MUX_axi4_to_st_f_reqs$enq_1__VAL_2 =
{ x__h55592, x__h55604, x__h55986 } ;
assign MUX_axi4_to_st_f_reqs$enq_1__VAL_3 =
{ x__h66107, x__h66112, x__h66115 } ;
assign MUX_axi4_to_st_rg_bytelane_lo$write_1__VAL_1 =
bytelane_lo__h60053 + bytes_processed__h62638 ;
assign MUX_axi4_to_st_rg_bytelane_lo$write_1__VAL_2 =
bytelane_lo__h52935 + bytes_processed__h55567 ;
assign MUX_axi4_to_st_rg_bytelane_lo$write_1__VAL_3 =
axi4_to_st_rg_bytelane_lo + bytes_processed__h66091 ;
assign MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__VAL_1 =
(v__h52941 == 8'd0) ? 8'd8 : 8'd0 ;
assign MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__VAL_2 =
axi4_to_st_rg_bytelane_slice_lo + 8'd8 ;
assign MUX_axi4_to_st_rg_discard_count$write_1__VAL_2 =
axi4_to_st_rg_discard_count - 8'd1 ;
assign MUX_axi4_to_st_rg_state$write_1__VAL_2 =
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930) ?
3'd4 :
((v__h52941 == 8'd0) ?
(_0_CONCAT_f_wr_addr_first__24_BITS_92_TO_29_89__ETC___d1063 ?
3'd3 :
3'd2) :
3'd1) ;
assign MUX_axi4_to_st_rg_state$write_1__VAL_3 =
(v__h60059 == 8'd0) ?
IF_axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7__ETC___d1172 :
3'd1 ;
assign MUX_axi4_to_st_rg_state$write_1__VAL_4 =
(v__h65821 == 8'd0) ?
IF_axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7__ETC___d1172 :
3'd1 ;
assign MUX_axi4_to_st_rg_v_slice$write_1__VAL_1 =
{ 64'd0, f_wr_data$D_OUT[576:129] } ;
assign MUX_axi4_to_st_rg_v_slice$write_1__VAL_2 =
{ 64'd0, axi4_to_st_rg_v_slice[511:64] } ;
assign MUX_axi4_to_st_rg_v_strb$write_1__VAL_1 =
{ 8'd0, f_wr_data$D_OUT[64:9] } ;
assign MUX_axi4_to_st_rg_v_strb$write_1__VAL_2 =
{ 8'd0, axi4_to_st_rg_v_strb[63:8] } ;
assign MUX_f_L1_to_L2_Rsps$enq_1__VAL_1 =
{ line_addr__h2730,
f_L2_to_L1_Reqs$D_OUT[1:0],
rf_tag_sets$D_OUT_2[65:64] == 2'd3,
rf_data_sets$D_OUT_1 } ;
assign MUX_f_L1_to_L2_Rsps$enq_1__VAL_2 =
{ rf_tag_sets$D_OUT_1[63:0],
2'd0,
rf_tag_sets$D_OUT_1[65:64] == 2'd3,
rf_data_sets$D_OUT_1 } ;
assign MUX_f_reqs$enq_1__VAL_1 =
{ 1'd0,
axi4_s_xactor_f_rd_addr$D_OUT,
576'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
assign MUX_f_reqs$enq_1__VAL_2 =
{ 1'd1,
axi4_s_xactor_f_wr_addr$D_OUT,
axi4_s_xactor_f_wr_data$D_OUT[64:1],
axi4_s_xactor_f_wr_data$D_OUT[576:65] } ;
assign MUX_f_single_reqs$enq_1__VAL_1 =
{ 1'd1,
axi4_to_ld_f_reqs$D_OUT[63:0],
axi4_to_ld_f_reqs$D_OUT } ;
assign MUX_f_single_reqs$enq_1__VAL_2 =
{ 1'd0,
axi4_to_st_f_reqs$D_OUT[127:64],
axi4_to_st_f_reqs$D_OUT[129:128],
axi4_to_st_f_reqs$D_OUT[63:0] } ;
assign MUX_rf_data_sets$upd_2__VAL_1 =
f_reqs$D_OUT[685] ? new_data___1__h4300 : rf_data_sets$D_OUT_1 ;
assign MUX_rf_data_sets$upd_2__VAL_2 =
f_reqs$D_OUT[685] ? new_data___1__h23293 : v__h22217 ;
assign MUX_rf_tag_sets$upd_2__VAL_1 =
{ f_L2_to_L1_Reqs$D_OUT[1:0],
f_L2_to_L1_Reqs$D_OUT[65:8],
6'd0 } ;
assign MUX_rf_tag_sets$upd_2__VAL_3 =
{ f_reqs$D_OUT[685] ? 2'd3 : rf_tag_sets$D_OUT_1[65:64],
line_addr__h3158 } ;
assign MUX_rf_tag_sets$upd_2__VAL_4 =
{ f_reqs$D_OUT[685] ? 2'd3 : f_L2_to_L1_Rsps$D_OUT[514:513],
line_addr__h3158 } ;
// register axi4_to_ld_rg_bytelane_hi
always@(MUX_axi4_to_ld_f_reqs$enq_1__SEL_1 or
MUX_axi4_to_ld_f_reqs$enq_1__SEL_2 or
bytelane_slice_hi__h44327 or
WILL_FIRE_RL_axi4_to_ld_rl_partial or axi4_to_ld_rg_bytelane_hi)
begin
case (1'b1) // synopsys parallel_case
MUX_axi4_to_ld_f_reqs$enq_1__SEL_1:
axi4_to_ld_rg_bytelane_hi$D_IN = 8'd7;
MUX_axi4_to_ld_f_reqs$enq_1__SEL_2:
axi4_to_ld_rg_bytelane_hi$D_IN = bytelane_slice_hi__h44327;
WILL_FIRE_RL_axi4_to_ld_rl_partial:
axi4_to_ld_rg_bytelane_hi$D_IN = axi4_to_ld_rg_bytelane_hi;
default: axi4_to_ld_rg_bytelane_hi$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
end
assign axi4_to_ld_rg_bytelane_hi$EN =
WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
f_rd_addr$D_OUT[28:21] == 8'd0 &&
_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668 &&
_0_CONCAT_f_rd_addr_first__62_BITS_34_TO_29_72__ETC___d674 ||
WILL_FIRE_RL_axi4_to_ld_rl_next_slice &&
!axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_U_ETC___d758 ||
WILL_FIRE_RL_axi4_to_ld_rl_partial ;
// register axi4_to_ld_rg_bytelane_lo
always@(MUX_axi4_to_ld_f_reqs$enq_1__SEL_1 or
MUX_axi4_to_ld_rg_bytelane_lo$write_1__VAL_1 or
MUX_axi4_to_ld_f_reqs$enq_1__SEL_2 or
MUX_axi4_to_ld_rg_bytelane_lo$write_1__VAL_2 or
WILL_FIRE_RL_axi4_to_ld_rl_partial or
MUX_axi4_to_ld_rg_bytelane_lo$write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_axi4_to_ld_f_reqs$enq_1__SEL_1:
axi4_to_ld_rg_bytelane_lo$D_IN =
MUX_axi4_to_ld_rg_bytelane_lo$write_1__VAL_1;
MUX_axi4_to_ld_f_reqs$enq_1__SEL_2:
axi4_to_ld_rg_bytelane_lo$D_IN =
MUX_axi4_to_ld_rg_bytelane_lo$write_1__VAL_2;
WILL_FIRE_RL_axi4_to_ld_rl_partial:
axi4_to_ld_rg_bytelane_lo$D_IN =
MUX_axi4_to_ld_rg_bytelane_lo$write_1__VAL_3;
default: axi4_to_ld_rg_bytelane_lo$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
end
assign axi4_to_ld_rg_bytelane_lo$EN =
WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
f_rd_addr$D_OUT[28:21] == 8'd0 &&
_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668 &&
_0_CONCAT_f_rd_addr_first__62_BITS_34_TO_29_72__ETC___d674 ||
WILL_FIRE_RL_axi4_to_ld_rl_next_slice &&
!axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_U_ETC___d758 ||
WILL_FIRE_RL_axi4_to_ld_rl_partial ;
// register axi4_to_ld_rg_bytelane_slice_lo
always@(MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__SEL_1 or
MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__VAL_1 or
MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__SEL_2 or
MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__VAL_2 or
MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__SEL_1:
axi4_to_ld_rg_bytelane_slice_lo$D_IN =
MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__VAL_1;
MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__SEL_2:
axi4_to_ld_rg_bytelane_slice_lo$D_IN =
MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__VAL_2;
MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__SEL_3:
axi4_to_ld_rg_bytelane_slice_lo$D_IN =
MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__VAL_2;
default: axi4_to_ld_rg_bytelane_slice_lo$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
end
assign axi4_to_ld_rg_bytelane_slice_lo$EN =
MUX_axi4_to_ld_rg_bytelane_slice_lo$write_1__SEL_1 ||
WILL_FIRE_RL_axi4_to_ld_rl_next_slice && v__h44351 == 8'd0 &&
axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_U_ETC___d793 ||
WILL_FIRE_RL_axi4_to_ld_rl_partial && v__h44974 == 8'd0 &&
axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_U_ETC___d793 ;
// register axi4_to_ld_rg_cumulative_err
assign axi4_to_ld_rg_cumulative_err$D_IN =
axi4_to_ld_rg_cumulative_err || axi4_to_ld_f_rsps$D_OUT[64] ;
assign axi4_to_ld_rg_cumulative_err$EN =
CAN_FIRE_RL_axi4_to_ld_rl_handle_ld_rsp ;
// register axi4_to_ld_rg_remaining_slices
always@(MUX_axi4_to_ld_rg_remaining_slices$write_1__SEL_1 or
MUX_axi4_to_ld_rg_remaining_slices$write_1__VAL_1 or
MUX_axi4_to_ld_rg_remaining_slices$write_1__SEL_2 or
WILL_FIRE_RL_axi4_to_ld_rl_send_axi_response)
begin
case (1'b1) // synopsys parallel_case
MUX_axi4_to_ld_rg_remaining_slices$write_1__SEL_1:
axi4_to_ld_rg_remaining_slices$D_IN =
MUX_axi4_to_ld_rg_remaining_slices$write_1__VAL_1;
MUX_axi4_to_ld_rg_remaining_slices$write_1__SEL_2:
axi4_to_ld_rg_remaining_slices$D_IN =
MUX_axi4_to_ld_rg_remaining_slices$write_1__VAL_1;
WILL_FIRE_RL_axi4_to_ld_rl_send_axi_response:
axi4_to_ld_rg_remaining_slices$D_IN = 4'd8;
default: axi4_to_ld_rg_remaining_slices$D_IN =
4'b1010 /* unspecified value */ ;
endcase
end
assign axi4_to_ld_rg_remaining_slices$EN =
WILL_FIRE_RL_axi4_to_ld_rl_handle_ld_rsp &&
axi4_to_ld_f_ld_rsp_info$D_OUT[9:8] == 2'd0 ||
WILL_FIRE_RL_axi4_to_ld_rl_shift_tail_slices ||
WILL_FIRE_RL_axi4_to_ld_rl_handle_ld_slice_ignore ||
WILL_FIRE_RL_axi4_to_ld_rl_send_axi_response ;
// register axi4_to_ld_rg_slice
assign axi4_to_ld_rg_slice$D_IN = 64'h0 ;
assign axi4_to_ld_rg_slice$EN = 1'b0 ;
// register axi4_to_ld_rg_state
always@(WILL_FIRE_RL_axi4_to_ld_rl_start_xaction or
MUX_axi4_to_ld_rg_state$write_1__VAL_1 or
WILL_FIRE_RL_axi4_to_ld_rl_next_slice or
MUX_axi4_to_ld_rg_state$write_1__VAL_2 or
WILL_FIRE_RL_axi4_to_ld_rl_partial or
MUX_axi4_to_ld_rg_state$write_1__VAL_3 or
MUX_axi4_to_ld_f_ld_rsp_info$enq_1__SEL_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_axi4_to_ld_rl_start_xaction:
axi4_to_ld_rg_state$D_IN = MUX_axi4_to_ld_rg_state$write_1__VAL_1;
WILL_FIRE_RL_axi4_to_ld_rl_next_slice:
axi4_to_ld_rg_state$D_IN = MUX_axi4_to_ld_rg_state$write_1__VAL_2;
WILL_FIRE_RL_axi4_to_ld_rl_partial:
axi4_to_ld_rg_state$D_IN = MUX_axi4_to_ld_rg_state$write_1__VAL_3;
MUX_axi4_to_ld_f_ld_rsp_info$enq_1__SEL_2:
axi4_to_ld_rg_state$D_IN = 3'd0;
default: axi4_to_ld_rg_state$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign axi4_to_ld_rg_state$EN =
WILL_FIRE_RL_axi4_to_ld_rl_start_xaction ||
WILL_FIRE_RL_axi4_to_ld_rl_next_slice ||
WILL_FIRE_RL_axi4_to_ld_rl_partial ||
WILL_FIRE_RL_axi4_to_ld_rl_illegal_req ||
WILL_FIRE_RL_axi4_to_ld_rl_finish_req ;
// register axi4_to_ld_rg_v_slice
assign axi4_to_ld_rg_v_slice$D_IN =
MUX_axi4_to_ld_rg_remaining_slices$write_1__SEL_2 ?
MUX_axi4_to_ld_rg_v_slice$write_1__VAL_1 :
MUX_axi4_to_ld_rg_v_slice$write_1__VAL_2 ;
assign axi4_to_ld_rg_v_slice$EN =
WILL_FIRE_RL_axi4_to_ld_rl_shift_tail_slices ||
WILL_FIRE_RL_axi4_to_ld_rl_handle_ld_slice_ignore ||
WILL_FIRE_RL_axi4_to_ld_rl_handle_ld_rsp ;
// register axi4_to_st_rg_bytelane_hi
always@(MUX_axi4_to_st_f_reqs$enq_1__SEL_1 or
bytelane_hi__h60054 or
MUX_axi4_to_st_f_reqs$enq_1__SEL_2 or
bytelane_hi__h52936 or
WILL_FIRE_RL_axi4_to_st_rl_partial or axi4_to_st_rg_bytelane_hi)
begin
case (1'b1) // synopsys parallel_case
MUX_axi4_to_st_f_reqs$enq_1__SEL_1:
axi4_to_st_rg_bytelane_hi$D_IN = bytelane_hi__h60054;
MUX_axi4_to_st_f_reqs$enq_1__SEL_2:
axi4_to_st_rg_bytelane_hi$D_IN = bytelane_hi__h52936;
WILL_FIRE_RL_axi4_to_st_rl_partial:
axi4_to_st_rg_bytelane_hi$D_IN = axi4_to_st_rg_bytelane_hi;
default: axi4_to_st_rg_bytelane_hi$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
end
assign axi4_to_st_rg_bytelane_hi$EN =
WILL_FIRE_RL_axi4_to_st_rl_next_slice &&
axi4_to_st_rg_v_strb[7:0] != 8'd0 &&
!axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1113 ||
WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
f_wr_data_first__21_BIT_0_22_AND_f_wr_addr_fir_ETC___d1001 ||
WILL_FIRE_RL_axi4_to_st_rl_partial ;
// register axi4_to_st_rg_bytelane_lo
always@(MUX_axi4_to_st_f_reqs$enq_1__SEL_1 or
MUX_axi4_to_st_rg_bytelane_lo$write_1__VAL_1 or
MUX_axi4_to_st_f_reqs$enq_1__SEL_2 or
MUX_axi4_to_st_rg_bytelane_lo$write_1__VAL_2 or
WILL_FIRE_RL_axi4_to_st_rl_partial or
MUX_axi4_to_st_rg_bytelane_lo$write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_axi4_to_st_f_reqs$enq_1__SEL_1:
axi4_to_st_rg_bytelane_lo$D_IN =
MUX_axi4_to_st_rg_bytelane_lo$write_1__VAL_1;
MUX_axi4_to_st_f_reqs$enq_1__SEL_2:
axi4_to_st_rg_bytelane_lo$D_IN =
MUX_axi4_to_st_rg_bytelane_lo$write_1__VAL_2;
WILL_FIRE_RL_axi4_to_st_rl_partial:
axi4_to_st_rg_bytelane_lo$D_IN =
MUX_axi4_to_st_rg_bytelane_lo$write_1__VAL_3;
default: axi4_to_st_rg_bytelane_lo$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
end
assign axi4_to_st_rg_bytelane_lo$EN =
WILL_FIRE_RL_axi4_to_st_rl_next_slice &&
axi4_to_st_rg_v_strb[7:0] != 8'd0 &&
!axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1113 ||
WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
f_wr_data_first__21_BIT_0_22_AND_f_wr_addr_fir_ETC___d1001 ||
WILL_FIRE_RL_axi4_to_st_rl_partial ;
// register axi4_to_st_rg_bytelane_slice_lo
always@(MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_1 or
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__VAL_1 or
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_2 or
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__VAL_2 or
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_1:
axi4_to_st_rg_bytelane_slice_lo$D_IN =
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__VAL_1;
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_2:
axi4_to_st_rg_bytelane_slice_lo$D_IN =
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__VAL_2;
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_3:
axi4_to_st_rg_bytelane_slice_lo$D_IN =
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__VAL_2;
default: axi4_to_st_rg_bytelane_slice_lo$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
end
assign axi4_to_st_rg_bytelane_slice_lo$EN =
WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
f_wr_data_first__21_BIT_0_22_AND_f_wr_addr_fir_ETC___d1066 ||
WILL_FIRE_RL_axi4_to_st_rl_next_slice && v__h60059 == 8'd0 &&
axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1165 ||
WILL_FIRE_RL_axi4_to_st_rl_partial && v__h65821 == 8'd0 &&
axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1165 ;
// register axi4_to_st_rg_cumulative_err
assign axi4_to_st_rg_cumulative_err$D_IN =
axi4_to_st_rg_cumulative_err || axi4_to_st_f_rsps$D_OUT ;
assign axi4_to_st_rg_cumulative_err$EN =
CAN_FIRE_RL_axi4_to_st_rl_handle_st_rsps ;
// register axi4_to_st_rg_discard_count
assign axi4_to_st_rg_discard_count$D_IN =
MUX_axi4_to_st_rg_discard_count$write_1__SEL_1 ?
f_wr_addr$D_OUT[28:21] :
MUX_axi4_to_st_rg_discard_count$write_1__VAL_2 ;
assign axi4_to_st_rg_discard_count$EN =
WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930) ||
WILL_FIRE_RL_axi4_to_st_rl_illegal_req &&
axi4_to_st_rg_discard_count != 8'd0 ;
// register axi4_to_st_rg_slice
always@(MUX_axi4_to_st_f_reqs$enq_1__SEL_1 or
axi4_to_st_rg_v_slice or
MUX_axi4_to_st_f_reqs$enq_1__SEL_2 or
f_wr_data$D_OUT or
WILL_FIRE_RL_axi4_to_st_rl_partial or axi4_to_st_rg_slice)
begin
case (1'b1) // synopsys parallel_case
MUX_axi4_to_st_f_reqs$enq_1__SEL_1:
axi4_to_st_rg_slice$D_IN = axi4_to_st_rg_v_slice[63:0];
MUX_axi4_to_st_f_reqs$enq_1__SEL_2:
axi4_to_st_rg_slice$D_IN = f_wr_data$D_OUT[128:65];
WILL_FIRE_RL_axi4_to_st_rl_partial:
axi4_to_st_rg_slice$D_IN = axi4_to_st_rg_slice;
default: axi4_to_st_rg_slice$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign axi4_to_st_rg_slice$EN =
WILL_FIRE_RL_axi4_to_st_rl_next_slice &&
axi4_to_st_rg_v_strb[7:0] != 8'd0 &&
!axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1113 ||
WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
f_wr_data_first__21_BIT_0_22_AND_f_wr_addr_fir_ETC___d1001 ||
WILL_FIRE_RL_axi4_to_st_rl_partial ;
// register axi4_to_st_rg_state
always@(WILL_FIRE_RL_axi4_to_st_rl_start_xaction or
MUX_axi4_to_st_rg_state$write_1__VAL_2 or
WILL_FIRE_RL_axi4_to_st_rl_next_slice or
MUX_axi4_to_st_rg_state$write_1__VAL_3 or
WILL_FIRE_RL_axi4_to_st_rl_partial or
MUX_axi4_to_st_rg_state$write_1__VAL_4 or
MUX_axi4_to_st_f_axi_rsp_info$enq_1__SEL_1 or
WILL_FIRE_RL_axi4_to_st_rl_finish_req)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_axi4_to_st_rl_start_xaction:
axi4_to_st_rg_state$D_IN = MUX_axi4_to_st_rg_state$write_1__VAL_2;
WILL_FIRE_RL_axi4_to_st_rl_next_slice:
axi4_to_st_rg_state$D_IN = MUX_axi4_to_st_rg_state$write_1__VAL_3;
WILL_FIRE_RL_axi4_to_st_rl_partial:
axi4_to_st_rg_state$D_IN = MUX_axi4_to_st_rg_state$write_1__VAL_4;
MUX_axi4_to_st_f_axi_rsp_info$enq_1__SEL_1 ||
WILL_FIRE_RL_axi4_to_st_rl_finish_req:
axi4_to_st_rg_state$D_IN = 3'd0;
default: axi4_to_st_rg_state$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign axi4_to_st_rg_state$EN =
WILL_FIRE_RL_axi4_to_st_rl_illegal_req &&
axi4_to_st_rg_discard_count == 8'd0 ||
WILL_FIRE_RL_axi4_to_st_rl_start_xaction ||
WILL_FIRE_RL_axi4_to_st_rl_next_slice ||
WILL_FIRE_RL_axi4_to_st_rl_partial ||
WILL_FIRE_RL_axi4_to_st_rl_finish_req ;
// register axi4_to_st_rg_v_slice
always@(MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_1 or
MUX_axi4_to_st_rg_v_slice$write_1__VAL_1 or
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_2 or
MUX_axi4_to_st_rg_v_slice$write_1__VAL_2 or
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_1:
axi4_to_st_rg_v_slice$D_IN =
MUX_axi4_to_st_rg_v_slice$write_1__VAL_1;
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_2:
axi4_to_st_rg_v_slice$D_IN =
MUX_axi4_to_st_rg_v_slice$write_1__VAL_2;
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_3:
axi4_to_st_rg_v_slice$D_IN =
MUX_axi4_to_st_rg_v_slice$write_1__VAL_2;
default: axi4_to_st_rg_v_slice$D_IN =
512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign axi4_to_st_rg_v_slice$EN =
WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
f_wr_data_first__21_BIT_0_22_AND_f_wr_addr_fir_ETC___d1066 ||
WILL_FIRE_RL_axi4_to_st_rl_next_slice && v__h60059 == 8'd0 &&
axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1165 ||
WILL_FIRE_RL_axi4_to_st_rl_partial && v__h65821 == 8'd0 &&
axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1165 ;
// register axi4_to_st_rg_v_strb
always@(MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_1 or
MUX_axi4_to_st_rg_v_strb$write_1__VAL_1 or
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_2 or
MUX_axi4_to_st_rg_v_strb$write_1__VAL_2 or
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_1:
axi4_to_st_rg_v_strb$D_IN = MUX_axi4_to_st_rg_v_strb$write_1__VAL_1;
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_2:
axi4_to_st_rg_v_strb$D_IN = MUX_axi4_to_st_rg_v_strb$write_1__VAL_2;
MUX_axi4_to_st_rg_bytelane_slice_lo$write_1__SEL_3:
axi4_to_st_rg_v_strb$D_IN = MUX_axi4_to_st_rg_v_strb$write_1__VAL_2;
default: axi4_to_st_rg_v_strb$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign axi4_to_st_rg_v_strb$EN =
WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
f_wr_data_first__21_BIT_0_22_AND_f_wr_addr_fir_ETC___d1066 ||
WILL_FIRE_RL_axi4_to_st_rl_next_slice && v__h60059 == 8'd0 &&
axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1165 ||
WILL_FIRE_RL_axi4_to_st_rl_partial && v__h65821 == 8'd0 &&
axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1165 ;
// register rg_init_index
assign rg_init_index$D_IN = rg_init_index + 6'd1 ;
assign rg_init_index$EN = WILL_FIRE_RL_rl_init && rg_init_index != 6'd63 ;
// register rg_state
assign rg_state$D_IN =
(MUX_rg_state$write_1__SEL_1 || WILL_FIRE_RL_rl_upgrade_rsp) ?
2'd1 :
2'd3 ;
assign rg_state$EN =
WILL_FIRE_RL_rl_init && rg_init_index == 6'd63 ||
WILL_FIRE_RL_rl_upgrade_rsp ||
WILL_FIRE_RL_rl_upgrade_req ;
// submodule axi4_s_xactor_f_rd_addr
assign axi4_s_xactor_f_rd_addr$D_IN =
{ axi4_s_arid,
axi4_s_araddr,
axi4_s_arlen,
axi4_s_arsize,
axi4_s_arburst,
axi4_s_arlock,
axi4_s_arcache,
axi4_s_arprot,
axi4_s_arqos,
axi4_s_arregion } ;
assign axi4_s_xactor_f_rd_addr$ENQ =
axi4_s_arvalid && axi4_s_xactor_f_rd_addr$FULL_N ;
assign axi4_s_xactor_f_rd_addr$DEQ =
WILL_FIRE_RL_rl_mmio_AXI_rd_req || WILL_FIRE_RL_rl_merge_rd_req ;
assign axi4_s_xactor_f_rd_addr$CLR = 1'b0 ;
// submodule axi4_s_xactor_f_rd_data
always@(MUX_axi4_s_xactor_f_rd_data$enq_1__SEL_1 or
MUX_axi4_s_xactor_f_rd_data$enq_1__VAL_1 or
MUX_axi4_s_xactor_f_rd_data$enq_1__SEL_2 or
MUX_axi4_s_xactor_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_rl_mmio_AXI_rd_rsp or f_rd_data$D_OUT)
begin
case (1'b1) // synopsys parallel_case
MUX_axi4_s_xactor_f_rd_data$enq_1__SEL_1:
axi4_s_xactor_f_rd_data$D_IN =
MUX_axi4_s_xactor_f_rd_data$enq_1__VAL_1;
MUX_axi4_s_xactor_f_rd_data$enq_1__SEL_2:
axi4_s_xactor_f_rd_data$D_IN =
MUX_axi4_s_xactor_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_rl_mmio_AXI_rd_rsp:
axi4_s_xactor_f_rd_data$D_IN = f_rd_data$D_OUT;
default: axi4_s_xactor_f_rd_data$D_IN =
531'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign axi4_s_xactor_f_rd_data$ENQ =
WILL_FIRE_RL_rl_hit && !f_reqs$D_OUT[685] ||
WILL_FIRE_RL_rl_upgrade_rsp && !f_reqs$D_OUT[685] ||
WILL_FIRE_RL_rl_mmio_AXI_rd_rsp ;
assign axi4_s_xactor_f_rd_data$DEQ =
axi4_s_rready && axi4_s_xactor_f_rd_data$EMPTY_N ;
assign axi4_s_xactor_f_rd_data$CLR = 1'b0 ;
// submodule axi4_s_xactor_f_wr_addr
assign axi4_s_xactor_f_wr_addr$D_IN =
{ axi4_s_awid,
axi4_s_awaddr,
axi4_s_awlen,
axi4_s_awsize,
axi4_s_awburst,
axi4_s_awlock,
axi4_s_awcache,
axi4_s_awprot,
axi4_s_awqos,
axi4_s_awregion } ;
assign axi4_s_xactor_f_wr_addr$ENQ =
axi4_s_awvalid && axi4_s_xactor_f_wr_addr$FULL_N ;
assign axi4_s_xactor_f_wr_addr$DEQ =
WILL_FIRE_RL_rl_mmio_axi_wr_req || WILL_FIRE_RL_rl_merge_wr_req ;
assign axi4_s_xactor_f_wr_addr$CLR = 1'b0 ;
// submodule axi4_s_xactor_f_wr_data
assign axi4_s_xactor_f_wr_data$D_IN =
{ axi4_s_wdata, axi4_s_wstrb, axi4_s_wlast } ;
assign axi4_s_xactor_f_wr_data$ENQ =
axi4_s_wvalid && axi4_s_xactor_f_wr_data$FULL_N ;
assign axi4_s_xactor_f_wr_data$DEQ =
WILL_FIRE_RL_rl_mmio_axi_wr_req || WILL_FIRE_RL_rl_merge_wr_req ;
assign axi4_s_xactor_f_wr_data$CLR = 1'b0 ;
// submodule axi4_s_xactor_f_wr_resp
assign axi4_s_xactor_f_wr_resp$D_IN =
MUX_axi4_s_xactor_f_wr_resp$enq_1__SEL_1 ?
MUX_axi4_s_xactor_f_wr_resp$enq_1__VAL_1 :
f_wr_resp$D_OUT ;
assign axi4_s_xactor_f_wr_resp$ENQ =
(WILL_FIRE_RL_rl_upgrade_rsp || WILL_FIRE_RL_rl_hit) &&
f_reqs$D_OUT[685] ||
WILL_FIRE_RL_rl_mmio_axi_wr_rsp ;
assign axi4_s_xactor_f_wr_resp$DEQ =
axi4_s_bready && axi4_s_xactor_f_wr_resp$EMPTY_N ;
assign axi4_s_xactor_f_wr_resp$CLR = 1'b0 ;
// submodule axi4_to_ld_f_axi_rsp_info
assign axi4_to_ld_f_axi_rsp_info$D_IN =
WILL_FIRE_RL_axi4_to_ld_rl_finish_req ?
MUX_axi4_to_ld_f_axi_rsp_info$enq_1__VAL_1 :
MUX_axi4_to_ld_f_axi_rsp_info$enq_1__VAL_2 ;
assign axi4_to_ld_f_axi_rsp_info$ENQ =
WILL_FIRE_RL_axi4_to_ld_rl_finish_req ||
WILL_FIRE_RL_axi4_to_ld_rl_illegal_req ;
assign axi4_to_ld_f_axi_rsp_info$DEQ =
CAN_FIRE_RL_axi4_to_ld_rl_send_axi_response ;
assign axi4_to_ld_f_axi_rsp_info$CLR = 1'b0 ;
// submodule axi4_to_ld_f_ld_rsp_info
always@(MUX_axi4_to_ld_f_ld_rsp_info$enq_1__SEL_1 or
MUX_axi4_to_ld_f_ld_rsp_info$enq_1__VAL_1 or
MUX_axi4_to_ld_f_ld_rsp_info$enq_1__SEL_2 or
WILL_FIRE_RL_axi4_to_ld_rl_next_slice or
MUX_axi4_to_ld_f_ld_rsp_info$enq_1__VAL_3 or
WILL_FIRE_RL_axi4_to_ld_rl_partial or
MUX_axi4_to_ld_f_ld_rsp_info$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_axi4_to_ld_f_ld_rsp_info$enq_1__SEL_1:
axi4_to_ld_f_ld_rsp_info$D_IN =
MUX_axi4_to_ld_f_ld_rsp_info$enq_1__VAL_1;
MUX_axi4_to_ld_f_ld_rsp_info$enq_1__SEL_2:
axi4_to_ld_f_ld_rsp_info$D_IN = 10'd938;
WILL_FIRE_RL_axi4_to_ld_rl_next_slice:
axi4_to_ld_f_ld_rsp_info$D_IN =
MUX_axi4_to_ld_f_ld_rsp_info$enq_1__VAL_3;
WILL_FIRE_RL_axi4_to_ld_rl_partial:
axi4_to_ld_f_ld_rsp_info$D_IN =
MUX_axi4_to_ld_f_ld_rsp_info$enq_1__VAL_4;
default: axi4_to_ld_f_ld_rsp_info$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign axi4_to_ld_f_ld_rsp_info$ENQ =
WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
f_rd_addr$D_OUT[28:21] == 8'd0 &&
_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668 ||
WILL_FIRE_RL_axi4_to_ld_rl_illegal_req ||
WILL_FIRE_RL_axi4_to_ld_rl_finish_req ||
WILL_FIRE_RL_axi4_to_ld_rl_next_slice ||
WILL_FIRE_RL_axi4_to_ld_rl_partial ;
assign axi4_to_ld_f_ld_rsp_info$DEQ =
WILL_FIRE_RL_axi4_to_ld_rl_send_axi_response ||
WILL_FIRE_RL_axi4_to_ld_rl_handle_ld_slice_ignore ||
WILL_FIRE_RL_axi4_to_ld_rl_handle_ld_rsp ;
assign axi4_to_ld_f_ld_rsp_info$CLR = 1'b0 ;
// submodule axi4_to_ld_f_reqs
always@(MUX_axi4_to_ld_f_reqs$enq_1__SEL_1 or
MUX_axi4_to_ld_f_reqs$enq_1__VAL_1 or
MUX_axi4_to_ld_f_reqs$enq_1__SEL_2 or
MUX_axi4_to_ld_f_reqs$enq_1__VAL_2 or
WILL_FIRE_RL_axi4_to_ld_rl_partial or
MUX_axi4_to_ld_f_reqs$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_axi4_to_ld_f_reqs$enq_1__SEL_1:
axi4_to_ld_f_reqs$D_IN = MUX_axi4_to_ld_f_reqs$enq_1__VAL_1;
MUX_axi4_to_ld_f_reqs$enq_1__SEL_2:
axi4_to_ld_f_reqs$D_IN = MUX_axi4_to_ld_f_reqs$enq_1__VAL_2;
WILL_FIRE_RL_axi4_to_ld_rl_partial:
axi4_to_ld_f_reqs$D_IN = MUX_axi4_to_ld_f_reqs$enq_1__VAL_3;
default: axi4_to_ld_f_reqs$D_IN =
66'h2AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign axi4_to_ld_f_reqs$ENQ =
WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
f_rd_addr$D_OUT[28:21] == 8'd0 &&
_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668 &&
_0_CONCAT_f_rd_addr_first__62_BITS_34_TO_29_72__ETC___d674 ||
WILL_FIRE_RL_axi4_to_ld_rl_next_slice &&
!axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_U_ETC___d758 ||
WILL_FIRE_RL_axi4_to_ld_rl_partial ;
assign axi4_to_ld_f_reqs$DEQ = MUX_f_single_reqs$enq_1__SEL_1 ;
assign axi4_to_ld_f_reqs$CLR = 1'b0 ;
// submodule axi4_to_ld_f_rsps
assign axi4_to_ld_f_rsps$D_IN =
{ !f_single_rsps$D_OUT[64], f_single_rsps$D_OUT[63:0] } ;
assign axi4_to_ld_f_rsps$ENQ = CAN_FIRE_RL_rl_mmio_LD_rsp ;
assign axi4_to_ld_f_rsps$DEQ = CAN_FIRE_RL_axi4_to_ld_rl_handle_ld_rsp ;
assign axi4_to_ld_f_rsps$CLR = 1'b0 ;
// submodule axi4_to_st_f_axi_rsp_info
assign axi4_to_st_f_axi_rsp_info$D_IN =
MUX_axi4_to_st_f_axi_rsp_info$enq_1__SEL_1 ?
MUX_axi4_to_st_f_axi_rsp_info$enq_1__VAL_1 :
MUX_axi4_to_st_f_axi_rsp_info$enq_1__VAL_2 ;
assign axi4_to_st_f_axi_rsp_info$ENQ =
WILL_FIRE_RL_axi4_to_st_rl_illegal_req &&
axi4_to_st_rg_discard_count == 8'd0 ||
WILL_FIRE_RL_axi4_to_st_rl_finish_req ;
assign axi4_to_st_f_axi_rsp_info$DEQ =
CAN_FIRE_RL_axi4_to_st_rl_send_axi_response ;
assign axi4_to_st_f_axi_rsp_info$CLR = 1'b0 ;
// submodule axi4_to_st_f_reqs
always@(MUX_axi4_to_st_f_reqs$enq_1__SEL_1 or
MUX_axi4_to_st_f_reqs$enq_1__VAL_1 or
MUX_axi4_to_st_f_reqs$enq_1__SEL_2 or
MUX_axi4_to_st_f_reqs$enq_1__VAL_2 or
WILL_FIRE_RL_axi4_to_st_rl_partial or
MUX_axi4_to_st_f_reqs$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_axi4_to_st_f_reqs$enq_1__SEL_1:
axi4_to_st_f_reqs$D_IN = MUX_axi4_to_st_f_reqs$enq_1__VAL_1;
MUX_axi4_to_st_f_reqs$enq_1__SEL_2:
axi4_to_st_f_reqs$D_IN = MUX_axi4_to_st_f_reqs$enq_1__VAL_2;
WILL_FIRE_RL_axi4_to_st_rl_partial:
axi4_to_st_f_reqs$D_IN = MUX_axi4_to_st_f_reqs$enq_1__VAL_3;
default: axi4_to_st_f_reqs$D_IN =
130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign axi4_to_st_f_reqs$ENQ =
WILL_FIRE_RL_axi4_to_st_rl_next_slice &&
axi4_to_st_rg_v_strb[7:0] != 8'd0 &&
!axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1113 ||
WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
f_wr_data_first__21_BIT_0_22_AND_f_wr_addr_fir_ETC___d1001 ||
WILL_FIRE_RL_axi4_to_st_rl_partial ;
assign axi4_to_st_f_reqs$DEQ = MUX_f_single_reqs$enq_1__SEL_2 ;
assign axi4_to_st_f_reqs$CLR = 1'b0 ;
// submodule axi4_to_st_f_rsps
assign axi4_to_st_f_rsps$D_IN = 1'd0 ;
assign axi4_to_st_f_rsps$ENQ = CAN_FIRE_RL_rl_mmio_st_rsp ;
assign axi4_to_st_f_rsps$DEQ = CAN_FIRE_RL_axi4_to_st_rl_handle_st_rsps ;
assign axi4_to_st_f_rsps$CLR = 1'b0 ;
// submodule axi4_to_st_f_st_rsp_info
assign axi4_to_st_f_st_rsp_info$D_IN =
!MUX_axi4_to_st_f_reqs$enq_1__SEL_1 &&
!MUX_axi4_to_st_f_reqs$enq_1__SEL_2 &&
!WILL_FIRE_RL_axi4_to_st_rl_partial ;
assign axi4_to_st_f_st_rsp_info$ENQ =
WILL_FIRE_RL_axi4_to_st_rl_next_slice &&
axi4_to_st_rg_v_strb[7:0] != 8'd0 &&
!axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1113 ||
WILL_FIRE_RL_axi4_to_st_rl_illegal_req &&
axi4_to_st_rg_discard_count == 8'd0 ||
WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
f_wr_data_first__21_BIT_0_22_AND_f_wr_addr_fir_ETC___d1001 ||
WILL_FIRE_RL_axi4_to_st_rl_partial ||
WILL_FIRE_RL_axi4_to_st_rl_finish_req ;
assign axi4_to_st_f_st_rsp_info$DEQ =
WILL_FIRE_RL_axi4_to_st_rl_send_axi_response ||
WILL_FIRE_RL_axi4_to_st_rl_handle_st_rsps ;
assign axi4_to_st_f_st_rsp_info$CLR = 1'b0 ;
// submodule f_L1_to_L2_Reqs
assign f_L1_to_L2_Reqs$D_IN =
{ line_addr__h3158,
rf_tag_sets$D_OUT_1[65:64],
f_reqs$D_OUT[685] ? 2'd2 : 2'd1,
f_reqs$D_OUT[685] } ;
assign f_L1_to_L2_Reqs$ENQ = MUX_rg_state$write_1__SEL_3 ;
assign f_L1_to_L2_Reqs$DEQ = EN_l1_to_l2_client_request_deq ;
assign f_L1_to_L2_Reqs$CLR = 1'b0 ;
// submodule f_L1_to_L2_Rsps
assign f_L1_to_L2_Rsps$D_IN =
MUX_f_L1_to_L2_Rsps$enq_1__SEL_1 ?
MUX_f_L1_to_L2_Rsps$enq_1__VAL_1 :
MUX_f_L1_to_L2_Rsps$enq_1__VAL_2 ;
assign f_L1_to_L2_Rsps$ENQ =
WILL_FIRE_RL_rl_downgrade &&
rf_tag_sets$D_OUT_2[65:64] != 2'd0 &&
!rf_tag_sets_sub_f_L2_to_L1_Reqs_first__1_BITS__ETC___d77 &&
rf_tag_sets_sub_f_L2_to_L1_Reqs_first__1_BITS__ETC___d82 ||
WILL_FIRE_RL_rl_evict ;
assign f_L1_to_L2_Rsps$DEQ = EN_l2_to_l1_server_response_deq ;
assign f_L1_to_L2_Rsps$CLR = 1'b0 ;
// submodule f_L2_to_L1_Reqs
assign f_L2_to_L1_Reqs$D_IN = l2_to_l1_server_request_enq_x ;
assign f_L2_to_L1_Reqs$ENQ = EN_l2_to_l1_server_request_enq ;
assign f_L2_to_L1_Reqs$DEQ = CAN_FIRE_RL_rl_downgrade ;
assign f_L2_to_L1_Reqs$CLR = 1'b0 ;
// submodule f_L2_to_L1_Rsps
assign f_L2_to_L1_Rsps$D_IN = l1_to_l2_client_response_enq_x ;
assign f_L2_to_L1_Rsps$ENQ = EN_l1_to_l2_client_response_enq ;
assign f_L2_to_L1_Rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign f_L2_to_L1_Rsps$CLR = 1'b0 ;
// submodule f_mmio_rsp_is_load
assign f_mmio_rsp_is_load$D_IN = !WILL_FIRE_RL_rl_mmio_ST_req ;
assign f_mmio_rsp_is_load$ENQ =
WILL_FIRE_RL_rl_mmio_ST_req || WILL_FIRE_RL_rl_mmio_LD_req ;
assign f_mmio_rsp_is_load$DEQ =
WILL_FIRE_RL_rl_mmio_st_rsp || WILL_FIRE_RL_rl_mmio_LD_rsp ;
assign f_mmio_rsp_is_load$CLR = 1'b0 ;
// submodule f_rd_addr
assign f_rd_addr$D_IN = axi4_s_xactor_f_rd_addr$D_OUT ;
assign f_rd_addr$ENQ = CAN_FIRE_RL_rl_mmio_AXI_rd_req ;
assign f_rd_addr$DEQ = MUX_axi4_to_ld_f_ld_rsp_info$enq_1__SEL_2 ;
assign f_rd_addr$CLR = 1'b0 ;
// submodule f_rd_data
assign f_rd_data$D_IN =
{ axi4_to_ld_f_axi_rsp_info$D_OUT[15:0],
axi4_to_ld_rg_v_slice,
rd_data_S_rresp__h49842,
1'd1 } ;
assign f_rd_data$ENQ = CAN_FIRE_RL_axi4_to_ld_rl_send_axi_response ;
assign f_rd_data$DEQ = WILL_FIRE_RL_rl_mmio_AXI_rd_rsp ;
assign f_rd_data$CLR = 1'b0 ;
// submodule f_reqs
assign f_reqs$D_IN =
WILL_FIRE_RL_rl_merge_rd_req ?
MUX_f_reqs$enq_1__VAL_1 :
MUX_f_reqs$enq_1__VAL_2 ;
assign f_reqs$ENQ =
WILL_FIRE_RL_rl_merge_rd_req || WILL_FIRE_RL_rl_merge_wr_req ;
assign f_reqs$DEQ = MUX_axi4_s_xactor_f_wr_resp$enq_1__PSEL_1 ;
assign f_reqs$CLR = 1'b0 ;
// submodule f_single_reqs
assign f_single_reqs$D_IN =
WILL_FIRE_RL_rl_mmio_LD_req ?
MUX_f_single_reqs$enq_1__VAL_1 :
MUX_f_single_reqs$enq_1__VAL_2 ;
assign f_single_reqs$ENQ =
WILL_FIRE_RL_rl_mmio_LD_req || WILL_FIRE_RL_rl_mmio_ST_req ;
assign f_single_reqs$DEQ = EN_mmio_client_request_get ;
assign f_single_reqs$CLR = 1'b0 ;
// submodule f_single_rsps
assign f_single_rsps$D_IN = mmio_client_response_put ;
assign f_single_rsps$ENQ = EN_mmio_client_response_put ;
assign f_single_rsps$DEQ =
f_mmio_rsp_is_load$EMPTY_N && f_single_rsps$EMPTY_N &&
axi4_to_ld_f_rsps$FULL_N &&
f_mmio_rsp_is_load$D_OUT ;
assign f_single_rsps$CLR = 1'b0 ;
// submodule f_wr_addr
assign f_wr_addr$D_IN = axi4_s_xactor_f_wr_addr$D_OUT ;
assign f_wr_addr$ENQ = CAN_FIRE_RL_rl_mmio_axi_wr_req ;
assign f_wr_addr$DEQ =
WILL_FIRE_RL_axi4_to_st_rl_illegal_req &&
axi4_to_st_rg_discard_count == 8'd0 ||
WILL_FIRE_RL_axi4_to_st_rl_finish_req ;
assign f_wr_addr$CLR = 1'b0 ;
// submodule f_wr_data
assign f_wr_data$D_IN = axi4_s_xactor_f_wr_data$D_OUT ;
assign f_wr_data$ENQ = CAN_FIRE_RL_rl_mmio_axi_wr_req ;
assign f_wr_data$DEQ =
WILL_FIRE_RL_axi4_to_st_rl_illegal_req ||
WILL_FIRE_RL_axi4_to_st_rl_finish_req ;
assign f_wr_data$CLR = 1'b0 ;
// submodule f_wr_resp
assign f_wr_resp$D_IN =
{ axi4_to_st_f_axi_rsp_info$D_OUT[15:0],
(axi4_to_st_f_axi_rsp_info$D_OUT[16] ||
axi4_to_st_rg_cumulative_err) ?
2'b10 :
2'b0 } ;
assign f_wr_resp$ENQ = CAN_FIRE_RL_axi4_to_st_rl_send_axi_response ;
assign f_wr_resp$DEQ = WILL_FIRE_RL_rl_mmio_axi_wr_rsp ;
assign f_wr_resp$CLR = 1'b0 ;
// submodule rf_data_sets
assign rf_data_sets$ADDR_1 =
WILL_FIRE_RL_rl_downgrade ?
f_L2_to_L1_Reqs$D_OUT[13:8] :
f_reqs$D_OUT[616:611] ;
assign rf_data_sets$ADDR_2 = 6'h0 ;
assign rf_data_sets$ADDR_3 = 6'h0 ;
assign rf_data_sets$ADDR_4 = 6'h0 ;
assign rf_data_sets$ADDR_5 = 6'h0 ;
assign rf_data_sets$ADDR_IN = f_reqs$D_OUT[616:611] ;
assign rf_data_sets$D_IN =
WILL_FIRE_RL_rl_hit ?
MUX_rf_data_sets$upd_2__VAL_1 :
MUX_rf_data_sets$upd_2__VAL_2 ;
assign rf_data_sets$WE =
WILL_FIRE_RL_rl_hit || WILL_FIRE_RL_rl_upgrade_rsp ;
// submodule rf_tag_sets
assign rf_tag_sets$ADDR_1 = f_reqs$D_OUT[616:611] ;
assign rf_tag_sets$ADDR_2 = f_L2_to_L1_Reqs$D_OUT[13:8] ;
assign rf_tag_sets$ADDR_3 = 6'h0 ;
assign rf_tag_sets$ADDR_4 = 6'h0 ;
assign rf_tag_sets$ADDR_5 = 6'h0 ;
always@(MUX_f_L1_to_L2_Rsps$enq_1__SEL_1 or
f_L2_to_L1_Reqs$D_OUT or
WILL_FIRE_RL_rl_evict or
WILL_FIRE_RL_rl_hit or
WILL_FIRE_RL_rl_upgrade_rsp or
f_reqs$D_OUT or WILL_FIRE_RL_rl_init or rg_init_index)
begin
case (1'b1) // synopsys parallel_case
MUX_f_L1_to_L2_Rsps$enq_1__SEL_1:
rf_tag_sets$ADDR_IN = f_L2_to_L1_Reqs$D_OUT[13:8];
WILL_FIRE_RL_rl_evict || WILL_FIRE_RL_rl_hit ||
WILL_FIRE_RL_rl_upgrade_rsp:
rf_tag_sets$ADDR_IN = f_reqs$D_OUT[616:611];
WILL_FIRE_RL_rl_init: rf_tag_sets$ADDR_IN = rg_init_index;
default: rf_tag_sets$ADDR_IN = 6'b101010 /* unspecified value */ ;
endcase
end
always@(MUX_f_L1_to_L2_Rsps$enq_1__SEL_1 or
MUX_rf_tag_sets$upd_2__VAL_1 or
WILL_FIRE_RL_rl_evict or
WILL_FIRE_RL_rl_hit or
MUX_rf_tag_sets$upd_2__VAL_3 or
WILL_FIRE_RL_rl_upgrade_rsp or
MUX_rf_tag_sets$upd_2__VAL_4 or WILL_FIRE_RL_rl_init)
begin
case (1'b1) // synopsys parallel_case
MUX_f_L1_to_L2_Rsps$enq_1__SEL_1:
rf_tag_sets$D_IN = MUX_rf_tag_sets$upd_2__VAL_1;
WILL_FIRE_RL_rl_evict: rf_tag_sets$D_IN = 66'h0AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_hit: rf_tag_sets$D_IN = MUX_rf_tag_sets$upd_2__VAL_3;
WILL_FIRE_RL_rl_upgrade_rsp:
rf_tag_sets$D_IN = MUX_rf_tag_sets$upd_2__VAL_4;
WILL_FIRE_RL_rl_init: rf_tag_sets$D_IN = 66'd0;
default: rf_tag_sets$D_IN =
66'h2AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rf_tag_sets$WE =
WILL_FIRE_RL_rl_downgrade &&
rf_tag_sets$D_OUT_2[65:64] != 2'd0 &&
!rf_tag_sets_sub_f_L2_to_L1_Reqs_first__1_BITS__ETC___d77 &&
rf_tag_sets_sub_f_L2_to_L1_Reqs_first__1_BITS__ETC___d82 ||
WILL_FIRE_RL_rl_evict ||
WILL_FIRE_RL_rl_hit ||
WILL_FIRE_RL_rl_upgrade_rsp ||
WILL_FIRE_RL_rl_init ;
// remaining internal signals
assign IF_axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_5_ETC___d796 =
axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_U_ETC___d793 ?
3'd2 :
3'd3 ;
assign IF_axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7__ETC___d1172 =
axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1165 ?
3'd2 :
3'd3 ;
assign IF_f_reqs_first__05_BIT_685_24_THEN_axi4_s_xac_ETC___d127 =
f_reqs$D_OUT[685] ?
axi4_s_xactor_f_wr_resp$FULL_N :
axi4_s_xactor_f_rd_data$FULL_N ;
assign NOT_f_L2_to_L1_Rsps_first__49_BITS_578_TO_515__ETC___d452 =
f_L2_to_L1_Rsps$D_OUT[578:515] != line_addr__h3158 ;
assign NOT_f_rd_addr_first__62_BITS_28_TO_21_63_EQ_0__ETC___d679 =
f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668 ||
axi4_to_ld_f_ld_rsp_info$FULL_N &&
(!_0_CONCAT_f_rd_addr_first__62_BITS_34_TO_29_72__ETC___d674 ||
axi4_to_ld_f_reqs$FULL_N) ;
assign NOT_f_reqs_first__05_BIT_685_24_29_AND_NOT_rf__ETC___d135 =
(!f_reqs$D_OUT[685] && rf_tag_sets$D_OUT_1[65:64] != 2'd0 ||
f_reqs$D_OUT[685] && rf_tag_sets$D_OUT_1[65:64] >= 2'd2) &&
rf_tag_sets_sub_f_reqs_first__05_BITS_616_TO_6_ETC___d114 ;
assign _0_CONCAT_IF_f_wr_data_first__21_BIT_1_36_THEN__ETC___d955 =
y__h54481 <= addr_bytelane__h52059 ;
assign _0_CONCAT_f_rd_addr_first__62_BITS_34_TO_29_72__ETC___d674 =
bytelane_lo__h42399 <= 8'd7 ;
assign _0_CONCAT_f_rd_addr_first__62_BITS_92_TO_29_90__ETC___d746 =
szwindow_bytelane_hi__h41816 <= 8'd7 ;
assign _0_CONCAT_f_wr_addr_first__24_BITS_92_TO_29_89__ETC___d1063 =
szwindow_bytelane_hi__h52063 <= 8'd7 ;
assign _1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668 =
_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66___d667 <= 8'd64 ;
assign _1_SL_f_rd_addr_first__62_BITS_20_TO_18_66___d667 =
8'd1 << f_rd_addr$D_OUT[20:18] ;
assign _1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930 =
_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28___d929 <= 8'd64 ;
assign _1_SL_f_wr_addr_first__24_BITS_20_TO_18_28___d929 =
8'd1 << f_wr_addr$D_OUT[20:18] ;
assign _7_MINUS_0_CONCAT_IF_f_wr_data_first__21_BIT_8__ETC___d1011 =
num_bytes__h55297 < 8'd8 ;
assign _7_MINUS_0_CONCAT_IF_f_wr_data_first__21_BIT_8__ETC___d969 =
bytelane_hi__h52936 < bytelane_lo__h52935 ;
assign _7_MINUS_0_CONCAT_f_rd_addr_first__62_BITS_34_T_ETC___d711 =
num_bytes__h42529 < 8'd8 ;
assign addr_axi_bus_lo__h41811 = { f_rd_addr$D_OUT[92:35], 6'd0 } ;
assign addr_axi_bus_lo__h52058 = { f_wr_addr$D_OUT[92:35], 6'd0 } ;
assign addr_bytelane__h52059 = { 2'd0, f_wr_addr$D_OUT[34:29] } ;
assign axi4_s_xactor_f_rd_addr_first__0_BITS_92_TO_29_ETC___d12 =
axi4_s_xactor_f_rd_addr$D_OUT[92:29] < 64'h0000000000001000 ;
assign axi4_s_xactor_f_rd_addr_first__0_BITS_92_TO_29_ETC___d14 =
axi4_s_xactor_f_rd_addr$D_OUT[92:29] < 64'd8192 ;
assign axi4_s_xactor_f_rd_addr_first__0_BITS_92_TO_29_ETC___d16 =
axi4_s_xactor_f_rd_addr$D_OUT[92:29] < 64'h0000000080000000 ;
assign axi4_s_xactor_f_rd_addr_first__0_BITS_92_TO_29_ETC___d18 =
axi4_s_xactor_f_rd_addr$D_OUT[92:29] < 64'h0000000090000000 ;
assign axi4_s_xactor_f_wr_addr_first__0_BITS_92_TO_29_ETC___d42 =
axi4_s_xactor_f_wr_addr$D_OUT[92:29] < 64'h0000000000001000 ;
assign axi4_s_xactor_f_wr_addr_first__0_BITS_92_TO_29_ETC___d44 =
axi4_s_xactor_f_wr_addr$D_OUT[92:29] < 64'd8192 ;
assign axi4_s_xactor_f_wr_addr_first__0_BITS_92_TO_29_ETC___d46 =
axi4_s_xactor_f_wr_addr$D_OUT[92:29] < 64'h0000000080000000 ;
assign axi4_s_xactor_f_wr_addr_first__0_BITS_92_TO_29_ETC___d48 =
axi4_s_xactor_f_wr_addr$D_OUT[92:29] < 64'h0000000090000000 ;
assign axi4_to_ld_rg_bytelane_hi_02_MINUS_axi4_to_ld__ETC___d813 =
num_bytes__h44981 < 8'd8 ;
assign axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_M_ETC___d777 =
num_bytes__h44435 < 8'd8 ;
assign axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_U_ETC___d758 =
bytelane_slice_hi__h44327 < bytelane_lo__h44346 ;
assign axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_U_ETC___d793 =
bytelane_slice_hi__h44327 < szwindow_bytelane_hi__h41816 ;
assign axi4_to_st_rg_bytelane_hi_176_MINUS_axi4_to_st_ETC___d1187 =
num_bytes__h65828 < 8'd8 ;
assign axi4_to_st_rg_bytelane_lo_MINUS_axi4_to_st_rg__ETC__q2 =
axi4_to_st_rg_bytelane_lo - axi4_to_st_rg_bytelane_slice_lo ;
assign axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1113 =
bytelane_hi__h60054 < bytelane_lo__h60053 ;
assign axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1129 =
num_bytes__h62377 < 8'd8 ;
assign axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1165 =
bytelane_slice_hi__h60018 < szwindow_bytelane_hi__h52063 ;
assign axi4_to_st_rg_v_strb_075_BITS_7_TO_0_076_EQ_0__ETC___d1116 =
axi4_to_st_rg_v_strb[7:0] == 8'd0 ||
axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1113 ||
f_wr_addr$EMPTY_N && axi4_to_st_f_reqs$FULL_N &&
axi4_to_st_f_st_rsp_info$FULL_N ;
assign bytelane_hi__h52936 = 8'd7 - num_msb_zero_bytes__h52922 ;
assign bytelane_hi__h60054 =
bytelane_slice_hi__h60018 - num_msb_zero_bytes__h60040 ;
assign bytelane_lo0053_MINUS_axi4_to_st_rg_bytelane_s_ETC__q1 =
bytelane_lo__h60053 - axi4_to_st_rg_bytelane_slice_lo ;
assign bytelane_lo__h42399 = { 2'd0, f_rd_addr$D_OUT[34:29] } ;
assign bytelane_lo__h44346 =
(axi4_to_ld_rg_bytelane_slice_lo <= bytelane_lo__h42399) ?
bytelane_lo__h42399 :
axi4_to_ld_rg_bytelane_slice_lo ;
assign bytelane_lo__h52935 =
_0_CONCAT_IF_f_wr_data_first__21_BIT_1_36_THEN__ETC___d955 ?
addr_bytelane__h52059 :
y__h54481 ;
assign bytelane_lo__h60053 =
(axi4_to_st_rg_bytelane_slice_lo <= y__h61599) ?
y__h61599 :
axi4_to_st_rg_bytelane_slice_lo ;
assign bytelane_slice_hi__h44327 = axi4_to_ld_rg_bytelane_slice_lo + 8'd7 ;
assign bytelane_slice_hi__h60018 = axi4_to_st_rg_bytelane_slice_lo + 8'd7 ;
assign bytes_processed__h42786 =
(x__h42568 == 8'd0 || f_rd_addr$D_OUT[29]) ?
8'd1 :
y_avValue_snd__h42779 ;
assign bytes_processed__h44683 =
(x__h44474 == 8'd0 || bytelane_lo__h44346[0]) ?
8'd1 :
y_avValue_snd__h44676 ;
assign bytes_processed__h45231 =
(x__h45020 == 8'd0 || axi4_to_ld_rg_bytelane_lo[0]) ?
8'd1 :
y_avValue_snd__h45224 ;
assign bytes_processed__h55567 =
(x__h55337 == 8'd0 || bytelane_lo__h52935[0]) ?
8'd1 :
y_avValue_snd_fst__h55989 ;
assign bytes_processed__h62638 =
(x__h62417 == 8'd0 || bytelane_lo__h60053[0]) ?
8'd1 :
y_avValue_snd_fst__h62665 ;
assign bytes_processed__h66091 =
(x__h65868 == 8'd0 || axi4_to_st_rg_bytelane_lo[0]) ?
8'd1 :
y_avValue_snd_fst__h66118 ;
assign f_rd_addrD_OUT_BITS_92_TO_29_AND_mask3380__q3 =
f_rd_addr$D_OUT[92:29] & mask__h43380 ;
assign f_wr_addrD_OUT_BITS_92_TO_29_AND_mask6467__q4 =
f_wr_addr$D_OUT[92:29] & mask__h56467 ;
assign f_wr_data_first__21_BITS_8_TO_1_34_EQ_0_35_OR__ETC___d957 =
f_wr_data$D_OUT[8:1] == 8'd0 ||
(_0_CONCAT_IF_f_wr_data_first__21_BIT_1_36_THEN__ETC___d955 ?
f_wr_addr$EMPTY_N :
f_wr_data$EMPTY_N) ;
assign f_wr_data_first__21_BITS_8_TO_1_34_EQ_0_35_OR__ETC___d975 =
f_wr_data_first__21_BITS_8_TO_1_34_EQ_0_35_OR__ETC___d957 &&
(f_wr_data$D_OUT[8:1] == 8'd0 ||
_7_MINUS_0_CONCAT_IF_f_wr_data_first__21_BIT_8__ETC___d969) ||
axi4_to_st_f_reqs$FULL_N && axi4_to_st_f_st_rsp_info$FULL_N ;
assign f_wr_data_first__21_BIT_0_22_AND_f_wr_addr_fir_ETC___d1001 =
f_wr_data$D_OUT[0] && f_wr_addr$D_OUT[28:21] == 8'd0 &&
_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930 &&
f_wr_data$D_OUT[8:1] != 8'd0 &&
!_7_MINUS_0_CONCAT_IF_f_wr_data_first__21_BIT_8__ETC___d969 ;
assign f_wr_data_first__21_BIT_0_22_AND_f_wr_addr_fir_ETC___d1066 =
f_wr_data$D_OUT[0] && f_wr_addr$D_OUT[28:21] == 8'd0 &&
_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930 &&
(v__h52941 != 8'd0 ||
!_0_CONCAT_f_wr_addr_first__24_BITS_92_TO_29_89__ETC___d1063) ;
assign line_addr__h2730 = { f_L2_to_L1_Reqs$D_OUT[65:8], 6'd0 } ;
assign line_addr__h3158 = { f_reqs$D_OUT[668:611], 6'd0 } ;
assign mask__h43380 = 64'hFFFFFFFFFFFFFFFF << x__h44141 ;
assign mask__h56467 = 64'hFFFFFFFFFFFFFFFF << x__h57228 ;
assign new_data___1__h23293 =
{ f_reqs$D_OUT[575] ? f_reqs$D_OUT[511:504] : v__h22217[511:504],
f_reqs$D_OUT[574] ? f_reqs$D_OUT[503:496] : v__h22217[503:496],
f_reqs$D_OUT[573] ? f_reqs$D_OUT[495:488] : v__h22217[495:488],
f_reqs$D_OUT[572] ? f_reqs$D_OUT[487:480] : v__h22217[487:480],
f_reqs$D_OUT[571] ? f_reqs$D_OUT[479:472] : v__h22217[479:472],
f_reqs$D_OUT[570] ? f_reqs$D_OUT[471:464] : v__h22217[471:464],
f_reqs$D_OUT[569] ? f_reqs$D_OUT[463:456] : v__h22217[463:456],
f_reqs$D_OUT[568] ? f_reqs$D_OUT[455:448] : v__h22217[455:448],
f_reqs$D_OUT[567] ? f_reqs$D_OUT[447:440] : v__h22217[447:440],
f_reqs$D_OUT[566] ? f_reqs$D_OUT[439:432] : v__h22217[439:432],
f_reqs$D_OUT[565] ? f_reqs$D_OUT[431:424] : v__h22217[431:424],
f_reqs$D_OUT[564] ? f_reqs$D_OUT[423:416] : v__h22217[423:416],
f_reqs$D_OUT[563] ? f_reqs$D_OUT[415:408] : v__h22217[415:408],
f_reqs$D_OUT[562] ? f_reqs$D_OUT[407:400] : v__h22217[407:400],
f_reqs$D_OUT[561] ? f_reqs$D_OUT[399:392] : v__h22217[399:392],
f_reqs$D_OUT[560] ? f_reqs$D_OUT[391:384] : v__h22217[391:384],
f_reqs$D_OUT[559] ? f_reqs$D_OUT[383:376] : v__h22217[383:376],
f_reqs$D_OUT[558] ? f_reqs$D_OUT[375:368] : v__h22217[375:368],
f_reqs$D_OUT[557] ? f_reqs$D_OUT[367:360] : v__h22217[367:360],
f_reqs$D_OUT[556] ? f_reqs$D_OUT[359:352] : v__h22217[359:352],
f_reqs$D_OUT[555] ? f_reqs$D_OUT[351:344] : v__h22217[351:344],
f_reqs$D_OUT[554] ? f_reqs$D_OUT[343:336] : v__h22217[343:336],
f_reqs$D_OUT[553] ? f_reqs$D_OUT[335:328] : v__h22217[335:328],
f_reqs$D_OUT[552] ? f_reqs$D_OUT[327:320] : v__h22217[327:320],
f_reqs$D_OUT[551] ? f_reqs$D_OUT[319:312] : v__h22217[319:312],
f_reqs$D_OUT[550] ? f_reqs$D_OUT[311:304] : v__h22217[311:304],
f_reqs$D_OUT[549] ? f_reqs$D_OUT[303:296] : v__h22217[303:296],
f_reqs$D_OUT[548] ? f_reqs$D_OUT[295:288] : v__h22217[295:288],
f_reqs$D_OUT[547] ? f_reqs$D_OUT[287:280] : v__h22217[287:280],
f_reqs$D_OUT[546] ? f_reqs$D_OUT[279:272] : v__h22217[279:272],
f_reqs$D_OUT[545] ? f_reqs$D_OUT[271:264] : v__h22217[271:264],
f_reqs$D_OUT[544] ? f_reqs$D_OUT[263:256] : v__h22217[263:256],
f_reqs$D_OUT[543] ? f_reqs$D_OUT[255:248] : v__h22217[255:248],
f_reqs$D_OUT[542] ? f_reqs$D_OUT[247:240] : v__h22217[247:240],
f_reqs$D_OUT[541] ? f_reqs$D_OUT[239:232] : v__h22217[239:232],
f_reqs$D_OUT[540] ? f_reqs$D_OUT[231:224] : v__h22217[231:224],
f_reqs$D_OUT[539] ? f_reqs$D_OUT[223:216] : v__h22217[223:216],
f_reqs$D_OUT[538] ? f_reqs$D_OUT[215:208] : v__h22217[215:208],
f_reqs$D_OUT[537] ? f_reqs$D_OUT[207:200] : v__h22217[207:200],
f_reqs$D_OUT[536] ? f_reqs$D_OUT[199:192] : v__h22217[199:192],
f_reqs$D_OUT[535] ? f_reqs$D_OUT[191:184] : v__h22217[191:184],
f_reqs$D_OUT[534] ? f_reqs$D_OUT[183:176] : v__h22217[183:176],
f_reqs$D_OUT[533] ? f_reqs$D_OUT[175:168] : v__h22217[175:168],
f_reqs$D_OUT[532] ? f_reqs$D_OUT[167:160] : v__h22217[167:160],
f_reqs$D_OUT[531] ? f_reqs$D_OUT[159:152] : v__h22217[159:152],
f_reqs$D_OUT[530] ? f_reqs$D_OUT[151:144] : v__h22217[151:144],
f_reqs$D_OUT[529] ? f_reqs$D_OUT[143:136] : v__h22217[143:136],
f_reqs$D_OUT[528] ? f_reqs$D_OUT[135:128] : v__h22217[135:128],
f_reqs$D_OUT[527] ? f_reqs$D_OUT[127:120] : v__h22217[127:120],
f_reqs$D_OUT[526] ? f_reqs$D_OUT[119:112] : v__h22217[119:112],
f_reqs$D_OUT[525] ? f_reqs$D_OUT[111:104] : v__h22217[111:104],
f_reqs$D_OUT[524] ? f_reqs$D_OUT[103:96] : v__h22217[103:96],
f_reqs$D_OUT[523] ? f_reqs$D_OUT[95:88] : v__h22217[95:88],
f_reqs$D_OUT[522] ? f_reqs$D_OUT[87:80] : v__h22217[87:80],
f_reqs$D_OUT[521] ? f_reqs$D_OUT[79:72] : v__h22217[79:72],
f_reqs$D_OUT[520] ? f_reqs$D_OUT[71:64] : v__h22217[71:64],
f_reqs$D_OUT[519] ? f_reqs$D_OUT[63:56] : v__h22217[63:56],
f_reqs$D_OUT[518] ? f_reqs$D_OUT[55:48] : v__h22217[55:48],
f_reqs$D_OUT[517] ? f_reqs$D_OUT[47:40] : v__h22217[47:40],
f_reqs$D_OUT[516] ? f_reqs$D_OUT[39:32] : v__h22217[39:32],
f_reqs$D_OUT[515] ? f_reqs$D_OUT[31:24] : v__h22217[31:24],
f_reqs$D_OUT[514] ? f_reqs$D_OUT[23:16] : v__h22217[23:16],
f_reqs$D_OUT[513] ? f_reqs$D_OUT[15:8] : v__h22217[15:8],
f_reqs$D_OUT[512] ? f_reqs$D_OUT[7:0] : v__h22217[7:0] } ;
assign new_data___1__h4300 =
{ f_reqs$D_OUT[575] ?
f_reqs$D_OUT[511:504] :
rf_data_sets$D_OUT_1[511:504],
f_reqs$D_OUT[574] ?
f_reqs$D_OUT[503:496] :
rf_data_sets$D_OUT_1[503:496],
f_reqs$D_OUT[573] ?
f_reqs$D_OUT[495:488] :
rf_data_sets$D_OUT_1[495:488],
f_reqs$D_OUT[572] ?
f_reqs$D_OUT[487:480] :
rf_data_sets$D_OUT_1[487:480],
f_reqs$D_OUT[571] ?
f_reqs$D_OUT[479:472] :
rf_data_sets$D_OUT_1[479:472],
f_reqs$D_OUT[570] ?
f_reqs$D_OUT[471:464] :
rf_data_sets$D_OUT_1[471:464],
f_reqs$D_OUT[569] ?
f_reqs$D_OUT[463:456] :
rf_data_sets$D_OUT_1[463:456],
f_reqs$D_OUT[568] ?
f_reqs$D_OUT[455:448] :
rf_data_sets$D_OUT_1[455:448],
f_reqs$D_OUT[567] ?
f_reqs$D_OUT[447:440] :
rf_data_sets$D_OUT_1[447:440],
f_reqs$D_OUT[566] ?
f_reqs$D_OUT[439:432] :
rf_data_sets$D_OUT_1[439:432],
f_reqs$D_OUT[565] ?
f_reqs$D_OUT[431:424] :
rf_data_sets$D_OUT_1[431:424],
f_reqs$D_OUT[564] ?
f_reqs$D_OUT[423:416] :
rf_data_sets$D_OUT_1[423:416],
f_reqs$D_OUT[563] ?
f_reqs$D_OUT[415:408] :
rf_data_sets$D_OUT_1[415:408],
f_reqs$D_OUT[562] ?
f_reqs$D_OUT[407:400] :
rf_data_sets$D_OUT_1[407:400],
f_reqs$D_OUT[561] ?
f_reqs$D_OUT[399:392] :
rf_data_sets$D_OUT_1[399:392],
f_reqs$D_OUT[560] ?
f_reqs$D_OUT[391:384] :
rf_data_sets$D_OUT_1[391:384],
f_reqs$D_OUT[559] ?
f_reqs$D_OUT[383:376] :
rf_data_sets$D_OUT_1[383:376],
f_reqs$D_OUT[558] ?
f_reqs$D_OUT[375:368] :
rf_data_sets$D_OUT_1[375:368],
f_reqs$D_OUT[557] ?
f_reqs$D_OUT[367:360] :
rf_data_sets$D_OUT_1[367:360],
f_reqs$D_OUT[556] ?
f_reqs$D_OUT[359:352] :
rf_data_sets$D_OUT_1[359:352],
f_reqs$D_OUT[555] ?
f_reqs$D_OUT[351:344] :
rf_data_sets$D_OUT_1[351:344],
f_reqs$D_OUT[554] ?
f_reqs$D_OUT[343:336] :
rf_data_sets$D_OUT_1[343:336],
f_reqs$D_OUT[553] ?
f_reqs$D_OUT[335:328] :
rf_data_sets$D_OUT_1[335:328],
f_reqs$D_OUT[552] ?
f_reqs$D_OUT[327:320] :
rf_data_sets$D_OUT_1[327:320],
f_reqs$D_OUT[551] ?
f_reqs$D_OUT[319:312] :
rf_data_sets$D_OUT_1[319:312],
f_reqs$D_OUT[550] ?
f_reqs$D_OUT[311:304] :
rf_data_sets$D_OUT_1[311:304],
f_reqs$D_OUT[549] ?
f_reqs$D_OUT[303:296] :
rf_data_sets$D_OUT_1[303:296],
f_reqs$D_OUT[548] ?
f_reqs$D_OUT[295:288] :
rf_data_sets$D_OUT_1[295:288],
f_reqs$D_OUT[547] ?
f_reqs$D_OUT[287:280] :
rf_data_sets$D_OUT_1[287:280],
f_reqs$D_OUT[546] ?
f_reqs$D_OUT[279:272] :
rf_data_sets$D_OUT_1[279:272],
f_reqs$D_OUT[545] ?
f_reqs$D_OUT[271:264] :
rf_data_sets$D_OUT_1[271:264],
f_reqs$D_OUT[544] ?
f_reqs$D_OUT[263:256] :
rf_data_sets$D_OUT_1[263:256],
f_reqs$D_OUT[543] ?
f_reqs$D_OUT[255:248] :
rf_data_sets$D_OUT_1[255:248],
f_reqs$D_OUT[542] ?
f_reqs$D_OUT[247:240] :
rf_data_sets$D_OUT_1[247:240],
f_reqs$D_OUT[541] ?
f_reqs$D_OUT[239:232] :
rf_data_sets$D_OUT_1[239:232],
f_reqs$D_OUT[540] ?
f_reqs$D_OUT[231:224] :
rf_data_sets$D_OUT_1[231:224],
f_reqs$D_OUT[539] ?
f_reqs$D_OUT[223:216] :
rf_data_sets$D_OUT_1[223:216],
f_reqs$D_OUT[538] ?
f_reqs$D_OUT[215:208] :
rf_data_sets$D_OUT_1[215:208],
f_reqs$D_OUT[537] ?
f_reqs$D_OUT[207:200] :
rf_data_sets$D_OUT_1[207:200],
f_reqs$D_OUT[536] ?
f_reqs$D_OUT[199:192] :
rf_data_sets$D_OUT_1[199:192],
f_reqs$D_OUT[535] ?
f_reqs$D_OUT[191:184] :
rf_data_sets$D_OUT_1[191:184],
f_reqs$D_OUT[534] ?
f_reqs$D_OUT[183:176] :
rf_data_sets$D_OUT_1[183:176],
f_reqs$D_OUT[533] ?
f_reqs$D_OUT[175:168] :
rf_data_sets$D_OUT_1[175:168],
f_reqs$D_OUT[532] ?
f_reqs$D_OUT[167:160] :
rf_data_sets$D_OUT_1[167:160],
f_reqs$D_OUT[531] ?
f_reqs$D_OUT[159:152] :
rf_data_sets$D_OUT_1[159:152],
f_reqs$D_OUT[530] ?
f_reqs$D_OUT[151:144] :
rf_data_sets$D_OUT_1[151:144],
f_reqs$D_OUT[529] ?
f_reqs$D_OUT[143:136] :
rf_data_sets$D_OUT_1[143:136],
f_reqs$D_OUT[528] ?
f_reqs$D_OUT[135:128] :
rf_data_sets$D_OUT_1[135:128],
f_reqs$D_OUT[527] ?
f_reqs$D_OUT[127:120] :
rf_data_sets$D_OUT_1[127:120],
f_reqs$D_OUT[526] ?
f_reqs$D_OUT[119:112] :
rf_data_sets$D_OUT_1[119:112],
f_reqs$D_OUT[525] ?
f_reqs$D_OUT[111:104] :
rf_data_sets$D_OUT_1[111:104],
f_reqs$D_OUT[524] ?
f_reqs$D_OUT[103:96] :
rf_data_sets$D_OUT_1[103:96],
f_reqs$D_OUT[523] ?
f_reqs$D_OUT[95:88] :
rf_data_sets$D_OUT_1[95:88],
f_reqs$D_OUT[522] ?
f_reqs$D_OUT[87:80] :
rf_data_sets$D_OUT_1[87:80],
f_reqs$D_OUT[521] ?
f_reqs$D_OUT[79:72] :
rf_data_sets$D_OUT_1[79:72],
f_reqs$D_OUT[520] ?
f_reqs$D_OUT[71:64] :
rf_data_sets$D_OUT_1[71:64],
f_reqs$D_OUT[519] ?
f_reqs$D_OUT[63:56] :
rf_data_sets$D_OUT_1[63:56],
f_reqs$D_OUT[518] ?
f_reqs$D_OUT[55:48] :
rf_data_sets$D_OUT_1[55:48],
f_reqs$D_OUT[517] ?
f_reqs$D_OUT[47:40] :
rf_data_sets$D_OUT_1[47:40],
f_reqs$D_OUT[516] ?
f_reqs$D_OUT[39:32] :
rf_data_sets$D_OUT_1[39:32],
f_reqs$D_OUT[515] ?
f_reqs$D_OUT[31:24] :
rf_data_sets$D_OUT_1[31:24],
f_reqs$D_OUT[514] ?
f_reqs$D_OUT[23:16] :
rf_data_sets$D_OUT_1[23:16],
f_reqs$D_OUT[513] ?
f_reqs$D_OUT[15:8] :
rf_data_sets$D_OUT_1[15:8],
f_reqs$D_OUT[512] ?
f_reqs$D_OUT[7:0] :
rf_data_sets$D_OUT_1[7:0] } ;
assign num_bytes__h42529 = x__h42568 + 8'd1 ;
assign num_bytes__h44435 = x__h44474 + 8'd1 ;
assign num_bytes__h44981 = x__h45020 + 8'd1 ;
assign num_bytes__h55297 = x__h55337 + 8'd1 ;
assign num_bytes__h62377 = x__h62417 + 8'd1 ;
assign num_bytes__h65828 = x__h65868 + 8'd1 ;
assign num_lsb_zero_bytes__h60039 = { 4'd0, x__h61600 } ;
assign num_msb_zero_bytes__h52922 = { 4'd0, x__h53166 } ;
assign num_msb_zero_bytes__h60040 = { 4'd0, x__h60276 } ;
assign rd_data_S_rresp__h49842 =
(axi4_to_ld_f_axi_rsp_info$D_OUT[16] ||
axi4_to_ld_rg_cumulative_err) ?
2'b10 :
2'b0 ;
assign rf_tag_sets_sub_f_L2_to_L1_Reqs_first__1_BITS__ETC___d77 =
rf_tag_sets$D_OUT_2[65:64] <= f_L2_to_L1_Reqs$D_OUT[1:0] ;
assign rf_tag_sets_sub_f_L2_to_L1_Reqs_first__1_BITS__ETC___d82 =
rf_tag_sets$D_OUT_2[63:0] == line_addr__h2730 ;
assign rf_tag_sets_sub_f_reqs_first__05_BITS_616_TO_6_ETC___d114 =
rf_tag_sets$D_OUT_1[63:0] == line_addr__h3158 ;
assign rg_state_EQ_1_01_AND_NOT_f_L2_to_L1_Reqs_notEm_ETC___d438 =
rg_state == 2'd1 && !f_L2_to_L1_Reqs$EMPTY_N &&
(rf_tag_sets$D_OUT_1[65:64] == 2'd0 ||
rf_tag_sets_sub_f_reqs_first__05_BITS_616_TO_6_ETC___d114 &&
f_reqs$D_OUT[685] &&
rf_tag_sets$D_OUT_1[65:64] == 2'd1) ;
assign shifted_slice__h55312 = f_wr_data$D_OUT[128:65] >> x__h56212 ;
assign shifted_slice__h62392 = axi4_to_st_rg_v_slice[63:0] >> x__h62883 ;
assign shifted_slice__h65843 = axi4_to_st_rg_slice >> x__h66125 ;
assign slice__h45713 =
axi4_to_ld_f_rsps$D_OUT[63:0] <<
{ axi4_to_ld_f_ld_rsp_info$D_OUT[4:0], 3'd0 } ;
assign szwindow_bytelane_hi__h41816 =
szwindow_bytelane_lo__h41815 + y__h43356 ;
assign szwindow_bytelane_hi__h52063 =
szwindow_bytelane_lo__h52062 + y__h56443 ;
assign szwindow_bytelane_lo__h41815 =
{ 2'd0, f_rd_addrD_OUT_BITS_92_TO_29_AND_mask3380__q3[5:0] } ;
assign szwindow_bytelane_lo__h52062 =
{ 2'd0, f_wr_addrD_OUT_BITS_92_TO_29_AND_mask6467__q4[5:0] } ;
assign v__h22217 =
f_L2_to_L1_Rsps$D_OUT[512] ?
f_L2_to_L1_Rsps$D_OUT[511:0] :
rf_data_sets$D_OUT_1 ;
assign v__h42404 =
_0_CONCAT_f_rd_addr_first__62_BITS_34_TO_29_72__ETC___d674 ?
v__h42504 :
8'd0 ;
assign v__h42504 = num_bytes__h42529 - bytes_processed__h42786 ;
assign v__h44351 =
axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_U_ETC___d758 ?
8'd0 :
v__h44413 ;
assign v__h44413 = num_bytes__h44435 - bytes_processed__h44683 ;
assign v__h44974 = num_bytes__h44981 - bytes_processed__h45231 ;
assign v__h52941 =
(f_wr_data$D_OUT[8:1] == 8'd0 ||
_7_MINUS_0_CONCAT_IF_f_wr_data_first__21_BIT_8__ETC___d969) ?
8'd0 :
v__h55273 ;
assign v__h55273 = num_bytes__h55297 - bytes_processed__h55567 ;
assign v__h60059 =
(axi4_to_st_rg_v_strb[7:0] == 8'd0 ||
axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1113) ?
8'd0 :
v__h62356 ;
assign v__h62356 = num_bytes__h62377 - bytes_processed__h62638 ;
assign v__h65821 = num_bytes__h65828 - bytes_processed__h66091 ;
assign x__h42568 = 8'd7 - bytelane_lo__h42399 ;
assign x__h42811 =
(x__h42568 == 8'd0 || f_rd_addr$D_OUT[29]) ?
2'b0 :
y_avValue_fst__h42778 ;
assign x__h44141 =
_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66___d667[0] ?
4'd0 :
(_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66___d667[1] ?
4'd1 :
(_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66___d667[2] ?
4'd2 :
(_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66___d667[3] ?
4'd3 :
(_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66___d667[4] ?
4'd4 :
(_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66___d667[5] ?
4'd5 :
(_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66___d667[6] ?
4'd6 :
(_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66___d667[7] ?
4'd7 :
4'd8))))))) ;
assign x__h44474 = bytelane_slice_hi__h44327 - bytelane_lo__h44346 ;
assign x__h44699 =
(x__h44474 == 8'd0 || bytelane_lo__h44346[0]) ?
2'b0 :
y_avValue_fst__h44675 ;
assign x__h44701 =
addr_axi_bus_lo__h41811 | { 56'd0, bytelane_lo__h44346 } ;
assign x__h44726 = bytelane_lo__h44346 - axi4_to_ld_rg_bytelane_slice_lo ;
assign x__h45020 = axi4_to_ld_rg_bytelane_hi - axi4_to_ld_rg_bytelane_lo ;
assign x__h45247 =
(x__h45020 == 8'd0 || axi4_to_ld_rg_bytelane_lo[0]) ?
2'b0 :
y_avValue_fst__h45223 ;
assign x__h45249 =
addr_axi_bus_lo__h41811 | { 56'd0, axi4_to_ld_rg_bytelane_lo } ;
assign x__h45274 =
axi4_to_ld_rg_bytelane_lo - axi4_to_ld_rg_bytelane_slice_lo ;
assign x__h53166 =
f_wr_data$D_OUT[8] ?
4'd0 :
(f_wr_data$D_OUT[7] ?
4'd1 :
(f_wr_data$D_OUT[6] ?
4'd2 :
(f_wr_data$D_OUT[5] ?
4'd3 :
(f_wr_data$D_OUT[4] ?
4'd4 :
(f_wr_data$D_OUT[3] ?
4'd5 :
(f_wr_data$D_OUT[2] ?
4'd6 :
(f_wr_data$D_OUT[1] ? 4'd7 : 4'd8))))))) ;
assign x__h54490 =
f_wr_data$D_OUT[1] ?
4'd0 :
(f_wr_data$D_OUT[2] ?
4'd1 :
(f_wr_data$D_OUT[3] ?
4'd2 :
(f_wr_data$D_OUT[4] ?
4'd3 :
(f_wr_data$D_OUT[5] ?
4'd4 :
(f_wr_data$D_OUT[6] ?
4'd5 :
(f_wr_data$D_OUT[7] ?
4'd6 :
(f_wr_data$D_OUT[8] ? 4'd7 : 4'd8))))))) ;
assign x__h55337 = bytelane_hi__h52936 - bytelane_lo__h52935 ;
assign x__h55592 =
(x__h55337 == 8'd0 || bytelane_lo__h52935[0]) ?
2'b0 :
y_avValue_fst__h55558 ;
assign x__h55604 =
addr_axi_bus_lo__h52058 | { 56'd0, bytelane_lo__h52935 } ;
assign x__h55986 =
(x__h55337 == 8'd0 || bytelane_lo__h52935[0]) ?
y_avValue_snd_snd__h55988 :
y_avValue_snd_snd__h55990 ;
assign x__h56212 = { bytelane_lo__h52935[4:0], 3'd0 } ;
assign x__h57228 =
_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28___d929[0] ?
4'd0 :
(_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28___d929[1] ?
4'd1 :
(_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28___d929[2] ?
4'd2 :
(_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28___d929[3] ?
4'd3 :
(_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28___d929[4] ?
4'd4 :
(_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28___d929[5] ?
4'd5 :
(_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28___d929[6] ?
4'd6 :
(_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28___d929[7] ?
4'd7 :
4'd8))))))) ;
assign x__h60276 =
axi4_to_st_rg_v_strb[7] ?
4'd0 :
(axi4_to_st_rg_v_strb[6] ?
4'd1 :
(axi4_to_st_rg_v_strb[5] ?
4'd2 :
(axi4_to_st_rg_v_strb[4] ?
4'd3 :
(axi4_to_st_rg_v_strb[3] ?
4'd4 :
(axi4_to_st_rg_v_strb[2] ?
4'd5 :
(axi4_to_st_rg_v_strb[1] ?
4'd6 :
(axi4_to_st_rg_v_strb[0] ?
4'd7 :
4'd8))))))) ;
assign x__h61600 =
axi4_to_st_rg_v_strb[0] ?
4'd0 :
(axi4_to_st_rg_v_strb[1] ?
4'd1 :
(axi4_to_st_rg_v_strb[2] ?
4'd2 :
(axi4_to_st_rg_v_strb[3] ?
4'd3 :
(axi4_to_st_rg_v_strb[4] ?
4'd4 :
(axi4_to_st_rg_v_strb[5] ?
4'd5 :
(axi4_to_st_rg_v_strb[6] ?
4'd6 :
(axi4_to_st_rg_v_strb[7] ?
4'd7 :
4'd8))))))) ;
assign x__h62417 = bytelane_hi__h60054 - bytelane_lo__h60053 ;
assign x__h62654 =
(x__h62417 == 8'd0 || bytelane_lo__h60053[0]) ?
2'b0 :
y_avValue_fst__h62629 ;
assign x__h62659 =
addr_axi_bus_lo__h52058 | { 56'd0, bytelane_lo__h60053 } ;
assign x__h62662 =
(x__h62417 == 8'd0 || bytelane_lo__h60053[0]) ?
y_avValue_snd_snd__h62664 :
y_avValue_snd_snd__h62666 ;
assign x__h62883 =
{ bytelane_lo0053_MINUS_axi4_to_st_rg_bytelane_s_ETC__q1[4:0],
3'd0 } ;
assign x__h65868 = axi4_to_st_rg_bytelane_hi - axi4_to_st_rg_bytelane_lo ;
assign x__h66107 =
(x__h65868 == 8'd0 || axi4_to_st_rg_bytelane_lo[0]) ?
2'b0 :
y_avValue_fst__h66082 ;
assign x__h66112 =
addr_axi_bus_lo__h52058 | { 56'd0, axi4_to_st_rg_bytelane_lo } ;
assign x__h66115 =
(x__h65868 == 8'd0 || axi4_to_st_rg_bytelane_lo[0]) ?
y_avValue_snd_snd__h66117 :
y_avValue_snd_snd__h66119 ;
assign x__h66125 =
{ axi4_to_st_rg_bytelane_lo_MINUS_axi4_to_st_rg__ETC__q2[4:0],
3'd0 } ;
assign y__h43356 =
_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66___d667 - 8'd1 ;
assign y__h54481 = { 4'd0, x__h54490 } ;
assign y__h56443 =
_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28___d929 - 8'd1 ;
assign y__h61591 =
axi4_to_st_rg_bytelane_slice_lo + num_lsb_zero_bytes__h60039 ;
assign y__h61599 =
(y__h61591 <= addr_bytelane__h52059) ?
addr_bytelane__h52059 :
y__h61591 ;
assign y_avValue_fst__h42762 =
_7_MINUS_0_CONCAT_f_rd_addr_first__62_BITS_34_T_ETC___d711 ?
2'b10 :
2'b11 ;
assign y_avValue_fst__h42778 =
(num_bytes__h42529 < 8'd4 || f_rd_addr$D_OUT[30:29] == 2'b10) ?
2'b01 :
y_avValue_fst__h42762 ;
assign y_avValue_fst__h44659 =
axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_M_ETC___d777 ?
2'b10 :
2'b11 ;
assign y_avValue_fst__h44675 =
(num_bytes__h44435 < 8'd4 || bytelane_lo__h44346[1:0] == 2'b10) ?
2'b01 :
y_avValue_fst__h44659 ;
assign y_avValue_fst__h45207 =
axi4_to_ld_rg_bytelane_hi_02_MINUS_axi4_to_ld__ETC___d813 ?
2'b10 :
2'b11 ;
assign y_avValue_fst__h45223 =
(num_bytes__h44981 < 8'd4 ||
axi4_to_ld_rg_bytelane_lo[1:0] == 2'b10) ?
2'b01 :
y_avValue_fst__h45207 ;
assign y_avValue_fst__h55540 =
_7_MINUS_0_CONCAT_IF_f_wr_data_first__21_BIT_8__ETC___d1011 ?
2'b10 :
2'b11 ;
assign y_avValue_fst__h55558 =
(num_bytes__h55297 < 8'd4 || bytelane_lo__h52935[1:0] == 2'b10) ?
2'b01 :
y_avValue_fst__h55540 ;
assign y_avValue_fst__h62611 =
axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1129 ?
2'b10 :
2'b11 ;
assign y_avValue_fst__h62629 =
(num_bytes__h62377 < 8'd4 || bytelane_lo__h60053[1:0] == 2'b10) ?
2'b01 :
y_avValue_fst__h62611 ;
assign y_avValue_fst__h66064 =
axi4_to_st_rg_bytelane_hi_176_MINUS_axi4_to_st_ETC___d1187 ?
2'b10 :
2'b11 ;
assign y_avValue_fst__h66082 =
(num_bytes__h65828 < 8'd4 ||
axi4_to_st_rg_bytelane_lo[1:0] == 2'b10) ?
2'b01 :
y_avValue_fst__h66064 ;
assign y_avValue_snd__h42763 =
_7_MINUS_0_CONCAT_f_rd_addr_first__62_BITS_34_T_ETC___d711 ?
8'd4 :
8'd8 ;
assign y_avValue_snd__h42779 =
(num_bytes__h42529 < 8'd4 || f_rd_addr$D_OUT[30:29] == 2'b10) ?
8'd2 :
y_avValue_snd__h42763 ;
assign y_avValue_snd__h44660 =
axi4_to_ld_rg_bytelane_slice_lo_54_PLUS_7_55_M_ETC___d777 ?
8'd4 :
8'd8 ;
assign y_avValue_snd__h44676 =
(num_bytes__h44435 < 8'd4 || bytelane_lo__h44346[1:0] == 2'b10) ?
8'd2 :
y_avValue_snd__h44660 ;
assign y_avValue_snd__h45208 =
axi4_to_ld_rg_bytelane_hi_02_MINUS_axi4_to_ld__ETC___d813 ?
8'd4 :
8'd8 ;
assign y_avValue_snd__h45224 =
(num_bytes__h44981 < 8'd4 ||
axi4_to_ld_rg_bytelane_lo[1:0] == 2'b10) ?
8'd2 :
y_avValue_snd__h45208 ;
assign y_avValue_snd_fst__h55989 =
(num_bytes__h55297 < 8'd4 || bytelane_lo__h52935[1:0] == 2'b10) ?
8'd2 :
y_avValue_snd_fst__h56238 ;
assign y_avValue_snd_fst__h56238 =
_7_MINUS_0_CONCAT_IF_f_wr_data_first__21_BIT_8__ETC___d1011 ?
8'd4 :
8'd8 ;
assign y_avValue_snd_fst__h62665 =
(num_bytes__h62377 < 8'd4 || bytelane_lo__h60053[1:0] == 2'b10) ?
8'd2 :
y_avValue_snd_fst__h62909 ;
assign y_avValue_snd_fst__h62909 =
axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1129 ?
8'd4 :
8'd8 ;
assign y_avValue_snd_fst__h66118 =
(num_bytes__h65828 < 8'd4 ||
axi4_to_st_rg_bytelane_lo[1:0] == 2'b10) ?
8'd2 :
y_avValue_snd_fst__h66151 ;
assign y_avValue_snd_fst__h66151 =
axi4_to_st_rg_bytelane_hi_176_MINUS_axi4_to_st_ETC___d1187 ?
8'd4 :
8'd8 ;
assign y_avValue_snd_snd__h55988 = { 56'd0, shifted_slice__h55312[7:0] } ;
assign y_avValue_snd_snd__h55990 =
(num_bytes__h55297 < 8'd4 || bytelane_lo__h52935[1:0] == 2'b10) ?
y_avValue_snd_snd__h56237 :
y_avValue_snd_snd__h56239 ;
assign y_avValue_snd_snd__h56237 = { 48'd0, shifted_slice__h55312[15:0] } ;
assign y_avValue_snd_snd__h56239 =
_7_MINUS_0_CONCAT_IF_f_wr_data_first__21_BIT_8__ETC___d1011 ?
y_avValue_snd_snd__h56244 :
shifted_slice__h55312 ;
assign y_avValue_snd_snd__h56244 = { 32'd0, shifted_slice__h55312[31:0] } ;
assign y_avValue_snd_snd__h62664 = { 56'd0, shifted_slice__h62392[7:0] } ;
assign y_avValue_snd_snd__h62666 =
(num_bytes__h62377 < 8'd4 || bytelane_lo__h60053[1:0] == 2'b10) ?
y_avValue_snd_snd__h62908 :
y_avValue_snd_snd__h62910 ;
assign y_avValue_snd_snd__h62908 = { 48'd0, shifted_slice__h62392[15:0] } ;
assign y_avValue_snd_snd__h62910 =
axi4_to_st_rg_bytelane_slice_lo_079_PLUS_7_080_ETC___d1129 ?
y_avValue_snd_snd__h62915 :
shifted_slice__h62392 ;
assign y_avValue_snd_snd__h62915 = { 32'd0, shifted_slice__h62392[31:0] } ;
assign y_avValue_snd_snd__h66117 = { 56'd0, shifted_slice__h65843[7:0] } ;
assign y_avValue_snd_snd__h66119 =
(num_bytes__h65828 < 8'd4 ||
axi4_to_st_rg_bytelane_lo[1:0] == 2'b10) ?
y_avValue_snd_snd__h66150 :
y_avValue_snd_snd__h66152 ;
assign y_avValue_snd_snd__h66150 = { 48'd0, shifted_slice__h65843[15:0] } ;
assign y_avValue_snd_snd__h66152 =
axi4_to_st_rg_bytelane_hi_176_MINUS_axi4_to_st_ETC___d1187 ?
y_avValue_snd_snd__h66157 :
shifted_slice__h65843 ;
assign y_avValue_snd_snd__h66157 = { 32'd0, shifted_slice__h65843[31:0] } ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
axi4_to_ld_rg_cumulative_err <= `BSV_ASSIGNMENT_DELAY 1'd0;
axi4_to_ld_rg_remaining_slices <= `BSV_ASSIGNMENT_DELAY 4'd8;
axi4_to_ld_rg_state <= `BSV_ASSIGNMENT_DELAY 3'd0;
axi4_to_st_rg_cumulative_err <= `BSV_ASSIGNMENT_DELAY 1'd0;
axi4_to_st_rg_state <= `BSV_ASSIGNMENT_DELAY 3'd0;
rg_init_index <= `BSV_ASSIGNMENT_DELAY 6'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (axi4_to_ld_rg_cumulative_err$EN)
axi4_to_ld_rg_cumulative_err <= `BSV_ASSIGNMENT_DELAY
axi4_to_ld_rg_cumulative_err$D_IN;
if (axi4_to_ld_rg_remaining_slices$EN)
axi4_to_ld_rg_remaining_slices <= `BSV_ASSIGNMENT_DELAY
axi4_to_ld_rg_remaining_slices$D_IN;
if (axi4_to_ld_rg_state$EN)
axi4_to_ld_rg_state <= `BSV_ASSIGNMENT_DELAY
axi4_to_ld_rg_state$D_IN;
if (axi4_to_st_rg_cumulative_err$EN)
axi4_to_st_rg_cumulative_err <= `BSV_ASSIGNMENT_DELAY
axi4_to_st_rg_cumulative_err$D_IN;
if (axi4_to_st_rg_state$EN)
axi4_to_st_rg_state <= `BSV_ASSIGNMENT_DELAY
axi4_to_st_rg_state$D_IN;
if (rg_init_index$EN)
rg_init_index <= `BSV_ASSIGNMENT_DELAY rg_init_index$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
if (axi4_to_ld_rg_bytelane_hi$EN)
axi4_to_ld_rg_bytelane_hi <= `BSV_ASSIGNMENT_DELAY
axi4_to_ld_rg_bytelane_hi$D_IN;
if (axi4_to_ld_rg_bytelane_lo$EN)
axi4_to_ld_rg_bytelane_lo <= `BSV_ASSIGNMENT_DELAY
axi4_to_ld_rg_bytelane_lo$D_IN;
if (axi4_to_ld_rg_bytelane_slice_lo$EN)
axi4_to_ld_rg_bytelane_slice_lo <= `BSV_ASSIGNMENT_DELAY
axi4_to_ld_rg_bytelane_slice_lo$D_IN;
if (axi4_to_ld_rg_slice$EN)
axi4_to_ld_rg_slice <= `BSV_ASSIGNMENT_DELAY axi4_to_ld_rg_slice$D_IN;
if (axi4_to_ld_rg_v_slice$EN)
axi4_to_ld_rg_v_slice <= `BSV_ASSIGNMENT_DELAY
axi4_to_ld_rg_v_slice$D_IN;
if (axi4_to_st_rg_bytelane_hi$EN)
axi4_to_st_rg_bytelane_hi <= `BSV_ASSIGNMENT_DELAY
axi4_to_st_rg_bytelane_hi$D_IN;
if (axi4_to_st_rg_bytelane_lo$EN)
axi4_to_st_rg_bytelane_lo <= `BSV_ASSIGNMENT_DELAY
axi4_to_st_rg_bytelane_lo$D_IN;
if (axi4_to_st_rg_bytelane_slice_lo$EN)
axi4_to_st_rg_bytelane_slice_lo <= `BSV_ASSIGNMENT_DELAY
axi4_to_st_rg_bytelane_slice_lo$D_IN;
if (axi4_to_st_rg_discard_count$EN)
axi4_to_st_rg_discard_count <= `BSV_ASSIGNMENT_DELAY
axi4_to_st_rg_discard_count$D_IN;
if (axi4_to_st_rg_slice$EN)
axi4_to_st_rg_slice <= `BSV_ASSIGNMENT_DELAY axi4_to_st_rg_slice$D_IN;
if (axi4_to_st_rg_v_slice$EN)
axi4_to_st_rg_v_slice <= `BSV_ASSIGNMENT_DELAY
axi4_to_st_rg_v_slice$D_IN;
if (axi4_to_st_rg_v_strb$EN)
axi4_to_st_rg_v_strb <= `BSV_ASSIGNMENT_DELAY axi4_to_st_rg_v_strb$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
axi4_to_ld_rg_bytelane_hi = 8'hAA;
axi4_to_ld_rg_bytelane_lo = 8'hAA;
axi4_to_ld_rg_bytelane_slice_lo = 8'hAA;
axi4_to_ld_rg_cumulative_err = 1'h0;
axi4_to_ld_rg_remaining_slices = 4'hA;
axi4_to_ld_rg_slice = 64'hAAAAAAAAAAAAAAAA;
axi4_to_ld_rg_state = 3'h2;
axi4_to_ld_rg_v_slice =
512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
axi4_to_st_rg_bytelane_hi = 8'hAA;
axi4_to_st_rg_bytelane_lo = 8'hAA;
axi4_to_st_rg_bytelane_slice_lo = 8'hAA;
axi4_to_st_rg_cumulative_err = 1'h0;
axi4_to_st_rg_discard_count = 8'hAA;
axi4_to_st_rg_slice = 64'hAAAAAAAAAAAAAAAA;
axi4_to_st_rg_state = 3'h2;
axi4_to_st_rg_v_slice =
512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
axi4_to_st_rg_v_strb = 64'hAAAAAAAAAAAAAAAA;
rg_init_index = 6'h2A;
rg_state = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
begin
v__h1963 = $stime;
#0;
end
v__h1957 = v__h1963 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$display("%0d: ERROR: %m.rl_merge_rd_req: burst requests not supported",
v__h1957);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
axi4_s_xactor_f_rd_addr$D_OUT[28:21] != 8'd0)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
begin
v__h2441 = $stime;
#0;
end
v__h2435 = v__h2441 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$display("%0d: ERROR: %m.rl_merge_wr_req: burst requests not supported",
v__h2435);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", axi4_s_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
axi4_s_xactor_f_wr_addr$D_OUT[28:21] != 8'd0)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp &&
NOT_f_L2_to_L1_Rsps_first__49_BITS_578_TO_515__ETC___d452)
begin
v__h21995 = $stime;
#0;
end
v__h21989 = v__h21995 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp &&
NOT_f_L2_to_L1_Rsps_first__49_BITS_578_TO_515__ETC___d452)
$display("%0d: %m.rl_upgrade_rsp: ERROR: rsp is not for addr %0h",
v__h21989,
line_addr__h3158);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp &&
NOT_f_L2_to_L1_Rsps_first__49_BITS_578_TO_515__ETC___d452)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp &&
NOT_f_L2_to_L1_Rsps_first__49_BITS_578_TO_515__ETC___d452)
$write("L2_to_L1_Rsp { ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp &&
NOT_f_L2_to_L1_Rsps_first__49_BITS_578_TO_515__ETC___d452)
$write("'h%h", f_L2_to_L1_Rsps$D_OUT[578:515]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp &&
NOT_f_L2_to_L1_Rsps_first__49_BITS_578_TO_515__ETC___d452)
$write(", ", "to_state: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp &&
NOT_f_L2_to_L1_Rsps_first__49_BITS_578_TO_515__ETC___d452 &&
f_L2_to_L1_Rsps$D_OUT[514:513] == 2'd0)
$write("INVALID");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp &&
NOT_f_L2_to_L1_Rsps_first__49_BITS_578_TO_515__ETC___d452 &&
f_L2_to_L1_Rsps$D_OUT[514:513] == 2'd1)
$write("SHARED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp &&
NOT_f_L2_to_L1_Rsps_first__49_BITS_578_TO_515__ETC___d452 &&
f_L2_to_L1_Rsps$D_OUT[514:513] == 2'd2)
$write("EXCLUSIVE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp &&
NOT_f_L2_to_L1_Rsps_first__49_BITS_578_TO_515__ETC___d452 &&
f_L2_to_L1_Rsps$D_OUT[514:513] != 2'd0 &&
f_L2_to_L1_Rsps$D_OUT[514:513] != 2'd1 &&
f_L2_to_L1_Rsps$D_OUT[514:513] != 2'd2)
$write("MODIFIED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp &&
NOT_f_L2_to_L1_Rsps_first__49_BITS_578_TO_515__ETC___d452)
$write(", ", "m_cline: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp &&
NOT_f_L2_to_L1_Rsps_first__49_BITS_578_TO_515__ETC___d452 &&
f_L2_to_L1_Rsps$D_OUT[512])
$write("tagged Valid ", "'h%h", f_L2_to_L1_Rsps$D_OUT[511:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp &&
NOT_f_L2_to_L1_Rsps_first__49_BITS_578_TO_515__ETC___d452 &&
!f_L2_to_L1_Rsps$D_OUT[512])
$write("tagged Invalid ", "");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp &&
NOT_f_L2_to_L1_Rsps_first__49_BITS_578_TO_515__ETC___d452)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp &&
NOT_f_L2_to_L1_Rsps_first__49_BITS_578_TO_515__ETC___d452)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp &&
NOT_f_L2_to_L1_Rsps_first__49_BITS_578_TO_515__ETC___d452)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] != 2'd0)
begin
v__h22278 = $stime;
#0;
end
v__h22272 = v__h22278 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] != 2'd0)
$display("%0d: %m.rl_upgrade_rsp: ERROR: rsp has refill data for non-INVALID frame",
v__h22272);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] != 2'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] != 2'd0)
$write("L2_to_L1_Rsp { ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] != 2'd0)
$write("'h%h", f_L2_to_L1_Rsps$D_OUT[578:515]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] != 2'd0)
$write(", ", "to_state: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] != 2'd0 &&
f_L2_to_L1_Rsps$D_OUT[514:513] == 2'd0)
$write("INVALID");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] != 2'd0 &&
f_L2_to_L1_Rsps$D_OUT[514:513] == 2'd1)
$write("SHARED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] != 2'd0 &&
f_L2_to_L1_Rsps$D_OUT[514:513] == 2'd2)
$write("EXCLUSIVE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] != 2'd0 &&
f_L2_to_L1_Rsps$D_OUT[514:513] != 2'd0 &&
f_L2_to_L1_Rsps$D_OUT[514:513] != 2'd1 &&
f_L2_to_L1_Rsps$D_OUT[514:513] != 2'd2)
$write("MODIFIED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] != 2'd0)
$write(", ", "m_cline: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] != 2'd0)
$write("tagged Valid ", "'h%h", f_L2_to_L1_Rsps$D_OUT[511:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] != 2'd0)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] != 2'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] != 2'd0)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && !f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] == 2'd0)
begin
v__h22510 = $stime;
#0;
end
v__h22504 = v__h22510 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && !f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] == 2'd0)
$display("%0d: %m.rl_upgrade_rsp: ERROR: rsp has no data for INVALID frame",
v__h22504);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && !f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] == 2'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && !f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] == 2'd0)
$write("L2_to_L1_Rsp { ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && !f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] == 2'd0)
$write("'h%h", f_L2_to_L1_Rsps$D_OUT[578:515]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && !f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] == 2'd0)
$write(", ", "to_state: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && !f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] == 2'd0 &&
f_L2_to_L1_Rsps$D_OUT[514:513] == 2'd0)
$write("INVALID");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && !f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] == 2'd0 &&
f_L2_to_L1_Rsps$D_OUT[514:513] == 2'd1)
$write("SHARED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && !f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] == 2'd0 &&
f_L2_to_L1_Rsps$D_OUT[514:513] == 2'd2)
$write("EXCLUSIVE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && !f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] == 2'd0 &&
f_L2_to_L1_Rsps$D_OUT[514:513] != 2'd0 &&
f_L2_to_L1_Rsps$D_OUT[514:513] != 2'd1 &&
f_L2_to_L1_Rsps$D_OUT[514:513] != 2'd2)
$write("MODIFIED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && !f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] == 2'd0)
$write(", ", "m_cline: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && !f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] == 2'd0)
$write("tagged Invalid ", "");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && !f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] == 2'd0)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && !f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] == 2'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_upgrade_rsp && !f_L2_to_L1_Rsps$D_OUT[512] &&
rf_tag_sets$D_OUT_1[65:64] == 2'd0)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668)
begin
v__h41979 = $stime;
#0;
end
v__h41973 = v__h41979 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668)
$display("%0d: %m.AXI4_to_LD:rl_start_xaction ================",
v__h41973);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668)
$display(" ERROR: illegal AXI4 request");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668)
$display(" awsize 0x%0h bytes > axi data bus width 0x%0h bytes",
_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66___d667,
$signed(32'd64));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
f_rd_addr$D_OUT[28:21] != 8'd0)
begin
v__h42147 = $stime;
#0;
end
v__h42141 = v__h42147 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
f_rd_addr$D_OUT[28:21] != 8'd0)
$display("%0d: %m.AXI4_to_LD:rl_start_xaction ================",
v__h42141);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
f_rd_addr$D_OUT[28:21] != 8'd0)
$display(" ERROR: illegal AXI4 request");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
f_rd_addr$D_OUT[28:21] != 8'd0)
$display(" arlen 0x%0h; only arlen 0 (1-beat bursts) supported",
f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write(" Discarding: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write("'h%h", f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write("'h%h", f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write("'h%h", f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write("'h%h", f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write("'h%h", f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write("'h%h", f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write("'h%h", f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write("'h%h", f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write("'h%h", f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write("'h%h", f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_ld_rl_start_xaction &&
(f_rd_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_rd_addr_first__62_BITS_20_TO_18_66_67_U_ETC___d668))
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930)
begin
v__h52258 = $stime;
#0;
end
v__h52252 = v__h52258 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930)
$display("%0d: %m.AXI4_to_ST:rl_start_xaction ================",
v__h52252);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930)
$display(" ERROR: illegal AXI4 request");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930)
$display(" awsize 0x%0h bytes > axi data bus width 0x%0h bytes",
_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28___d929,
$signed(32'd64));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
f_wr_addr$D_OUT[28:21] != 8'd0)
begin
v__h52431 = $stime;
#0;
end
v__h52425 = v__h52431 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
f_wr_addr$D_OUT[28:21] != 8'd0)
$display("%0d: %m.AXI4_to_ST:rl_start_xaction ================",
v__h52425);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
f_wr_addr$D_OUT[28:21] != 8'd0)
$display(" ERROR: illegal AXI4 request");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
f_wr_addr$D_OUT[28:21] != 8'd0)
$display(" awlen 0x%0h; only awlen 0 (1-beat bursts) supported",
f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction && !f_wr_data$D_OUT[0])
begin
v__h52625 = $stime;
#0;
end
v__h52619 = v__h52625 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction && !f_wr_data$D_OUT[0])
$display("%0d: %m.AXI4_to_ST:rl_start_xaction ================",
v__h52619);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction && !f_wr_data$D_OUT[0])
$display(" ERROR: illegal AXI4 request");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction && !f_wr_data$D_OUT[0])
$display(" wlast != 1; only 1-beat bursts supported");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write(" Discarding: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write("'h%h", f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write("'h%h", f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write("'h%h", f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write("'h%h", f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write("'h%h", f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write("'h%h", f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write("'h%h", f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write("'h%h", f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write("'h%h", f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write("'h%h", f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_axi4_to_st_rl_start_xaction &&
(!f_wr_data$D_OUT[0] || f_wr_addr$D_OUT[28:21] != 8'd0 ||
!_1_SL_f_wr_addr_first__24_BITS_20_TO_18_28_29_U_ETC___d930))
$write("\n");
end
// synopsys translate_on
endmodule // mkDMA_Cache
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__NOR4_FUNCTIONAL_PP_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nor4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B, C, D );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKINV_8_V
`define SKY130_FD_SC_MS__CLKINV_8_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkinv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkinv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKINV_8_V
|
// File generic.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
// no timescale needed
module test(
reset,
sysclk,
a,
b,
enf,
load,
qtd,
base
);
parameter [7:0] dog_width=8'b 10101100;
parameter [31:0] bus_width=32;
input reset, sysclk;
input [bus_width:0] a, b, enf, load, qtd, base;
wire reset;
wire sysclk;
wire [bus_width:0] a;
wire [bus_width:0] b;
wire [bus_width:0] enf;
wire [bus_width:0] load;
wire [bus_width:0] qtd;
wire [bus_width:0] base;
wire [1 + 1:0] foo;
reg [9:0] code; wire [9:0] code1;
wire [324:401] egg;
wire [bus_width * 3 - 1:bus_width * 4] baz;
wire [31:0] complex;
// Example of with statement
always @(*) begin
case(foo[2:0])
3'b 000,3'b 110 : code[9:2] <= {3'b 110,egg[325:329]};
3'b 101 : code[9:2] <= 8'b 11100010;
3'b 010 : code[9:2] <= {8{1'b1}};
3'b 011 : code[9:2] <= {8{1'b0}};
default : code[9:2] <= a + b + 1'b 1;
endcase
end
assign code1[1:0] = a[6:5] ^ ({a[4],b[6]});
assign foo = {(((1 + 1))-((0))+1){1'b0}};
assign egg = {78{1'b0}};
assign baz = {(((bus_width * 4))-((bus_width * 3 - 1))+1){1'b1}};
assign complex = {enf,(3'b 110 * load),qtd[3:0],base,5'b 11001};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_P_PP_PG_N_TB_V
`define SKY130_FD_SC_HDLL__UDP_DFF_P_PP_PG_N_TB_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__udp_dff_p_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 NOTIFIER = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 NOTIFIER = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 NOTIFIER = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 NOTIFIER = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N dut (.D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_P_PP_PG_N_TB_V
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1421777838 : 2899645186;
endmodule
|
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module CPC2_C5G(
//////////// CLOCK //////////
CLOCK_125_p,
CLOCK_50_B5B,
CLOCK_50_B6A,
CLOCK_50_B7A,
CLOCK_50_B8A,
//////////// LED //////////
LEDG,
LEDR,
//////////// KEY //////////
CPU_RESET_n,
KEY,
//////////// SW //////////
SW,
//////////// HDMI-TX //////////
HDMI_TX_CLK,
HDMI_TX_D,
HDMI_TX_DE,
HDMI_TX_HS,
HDMI_TX_INT,
HDMI_TX_VS,
//////////// Audio //////////
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
//////////// I2C for Audio/HDMI-TX/Si5338/HSMC //////////
I2C_SCL,
I2C_SDA,
//////////// SDCARD //////////
SD_CLK,
SD_CMD,
SD_DAT,
//////////// Uart to USB //////////
UART_RX,
UART_TX,
//////////// SRAM //////////
SRAM_A,
SRAM_CE_n,
SRAM_D,
SRAM_LB_n,
SRAM_OE_n,
SRAM_UB_n,
SRAM_WE_n,
//////////// GPIO, GPIO connect to GPIO Default //////////
GPIO
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_125_p;
input CLOCK_50_B5B;
input CLOCK_50_B6A;
input CLOCK_50_B7A;
input CLOCK_50_B8A;
//////////// LED //////////
output [7:0] LEDG;
output [9:0] LEDR;
//////////// KEY //////////
input CPU_RESET_n;
input [3:0] KEY;
//////////// SW //////////
input [9:0] SW;
//////////// HDMI-TX //////////
output HDMI_TX_CLK;
output [23:0] HDMI_TX_D;
output HDMI_TX_DE;
output HDMI_TX_HS;
input HDMI_TX_INT;
output HDMI_TX_VS;
//////////// Audio //////////
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_XCK;
//////////// I2C for Audio/HDMI-TX/Si5338/HSMC //////////
output I2C_SCL;
inout I2C_SDA;
//////////// SDCARD //////////
output SD_CLK;
inout SD_CMD;
inout [3:0] SD_DAT;
//////////// Uart to USB //////////
input UART_RX;
output UART_TX;
//////////// SRAM //////////
output [17:0] SRAM_A;
output SRAM_CE_n;
inout [15:0] SRAM_D;
output SRAM_LB_n;
output SRAM_OE_n;
output SRAM_UB_n;
output SRAM_WE_n;
//////////// GPIO, GPIO connect to GPIO Default //////////
inout [35:0] GPIO;
wire [2:0] dummy1;
CPC2 cpc2_inst (
.CLK_50(CLOCK_50_B5B),
.CLK2_50(CLOCK_50_B6A),
.CLK_12(CLOCK_50_B7A),
// Control Ports
.DATA7(), // Unused
.DATA6(), // Unused
.DATA5(KEY != 4'b1111), // Soft Reset - any key
.I2C_SCL(I2C_SCL), // INOUT - HDMI
.I2C_SDA(I2C_SDA), // INOUT - HDMI
// Disk/activity LED
.LED(LEDG[0]),
// Video port - output
.VSYNC(HDMI_TX_VS),
.HSYNC(HDMI_TX_HS),
.VDE(HDMI_TX_DE),
.VCLK(HDMI_TX_CLK),
.R(HDMI_TX_D[23:16]),
.G(HDMI_TX_D[15:8]),
.B(HDMI_TX_D[7:0]),
// Video Audio
.I2S(), // 4 bits
.ASCLK(),
.LRCLK(),
.MCLK(),
// Uart port
.uart_rx_i(UART_RX),
.uart_tx_o(UART_TX),
// USB port
.usb_mode(),
.usb_suspend(),
.usb_vm(),
.usb_vp(),
.usb_rcv(),
.usb_vpo(),
.usb_vmo(),
.usb_speed(),
.usb_oen(),
// SDRAM interface
.sdram_Dq(),
.sdram_Addr(),
.sdram_Ba(),
.sdramClk(),
.sdram_Cke(),
.sdram_Cs_n(),
.sdram_Ras_n(),
.sdram_Cas_n(),
.sdram_We_n(),
.sdram_Dqm()
);
endmodule
|
///////////////////////////////////////////////////////////
module counter_behavioural #(
parameter bits = 16
) (
input clock, reset, enable, load,
input [bits-1:0] init,
output reg [bits-1:0] q
);
always @(posedge clock, posedge reset)
if (reset)
q <= 0;
else if (enable)
if (load) q <= init;
else q <= q + 1;
endmodule
///////////////////////////////////////////////////////////
module register #(
parameter bits = 16
) (
input clock, reset, enable,
input [bits-1:0] d,
output reg [bits-1:0] q
);
always @(posedge clock, posedge reset)
if (reset)
q <= 0;
else if (enable)
q <= d;
endmodule
module mux2 #(
parameter bits = 16
) (
input sel,
input [bits-1:0] d0, d1,
output [bits-1:0] q
);
assign q = sel ? d1 : d0;
endmodule
module add #(
parameter bits = 16
) (
input [bits-1:0] a, b,
output [bits-1:0] q
);
assign q = a + b;
endmodule
module counter_structural #(
parameter bits = 16
) (
input clock, reset, enable, load,
input [bits-1:0] init,
output [bits-1:0] q
);
wire [bits-1:0] qp, qf;
add #(bits) theadd (q, 1, qp);
mux2 #(bits) themux (load, init, qp, qf);
register #(bits) thereg (clock, reset, enable, qf, q);
endmodule
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012, Ameer M. Abdelhadi; [email protected]. All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// phasemeter.v: Clock phase meter using high freq. sampling clock and a counter //
// //
// Ameer M.S. Abdelhadi ([email protected]; [email protected]), Sept. 2012 //
////////////////////////////////////////////////////////////////////////////////////
module phasemeter
( input clk_500, // sampling clock, 500Mhz
input clk_ref, // reference clock
input clk_phs, // phase-shifted clock, same frequency as reference clock
output reg phs_sgn, // measured pahse shift / sign
output [11:0] phs_bcd); // measured pahse shift / BCD {ones,tens,hundreds}
wire clk_ph1 = clk_ref && ~clk_phs;
localparam cntW = 8;
reg [cntW-1:0] cntR, cntF,cntR_,cntF_;
always @(posedge clk_500)
if (!clk_ph1) cntR <= {cntW{1'b0}};
else cntR <= cntR+{cntW{1'b1}};
always @(negedge clk_500)
if (!clk_ph1) cntF <= {cntW{1'b0}};
else cntF <= cntR+{cntW{1'b1}};
always @(negedge clk_ph1)
{cntR_,cntF_} <= {cntR,cntF};
always @(negedge clk_ref)
phs_sgn <= clk_phs;
wire [cntW:0] cnt_sum = cntR_ + cntF_;// + !phs_sign;
//wire [8:0] phs_bin = cnt_sum*8'd10/8'd8+(|cnt_sum[1:0]);
bin2bcd9 bin2bcd9_00 (cnt_sum,phs_bcd);
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
wire psl_valid_test_expr;
reg xzdetect_bit;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
assign psl_valid_test_expr = ~(test_expr ^ test_expr);
always@( reset_n or psl_valid_test_expr )
begin
if( reset_n == 1'b0 )
begin
xzdetect_bit = 1'b0;
end
else
begin
if( psl_valid_test_expr )
begin
//Do nothing
end
else
begin
xzdetect_bit = ~xzdetect_bit;
end
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin : assert_checks
assert_proposition_assert
assert_proposition_assert (
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzdetect_bit(xzdetect_bit),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_proposition.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_proposition_assert (reset_n, test_expr, xzdetect_bit, xzcheck_enable);
input reset_n, test_expr;
input xzdetect_bit, xzcheck_enable;
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_cycle_sequence (clock, reset, enable, event_sequence, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter num_cks = 2;
parameter necessary_condition = `OVL_NECESSARY_CONDITION_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [num_cks-1:0] event_sequence;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_CYCLE_SEQUENCE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SYNTHESIS
`else
// Sanity Checks
initial begin
if (num_cks < 2) begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal value for parameter num_cks which must be set to value greater than 1");
end
end
`endif
`ifdef OVL_VERILOG
`include "./vlog95/ovl_cycle_sequence_logic.v"
`endif
`ifdef OVL_SVA
`include "./sva05/ovl_cycle_sequence_logic.sv"
`endif
`ifdef OVL_PSL
`include "./psl05/assert_cycle_sequence_psl_logic.v"
`else
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endmodule // ovl_cycle_sequence
`endif
|
// -*- Mode: Verilog -*-
// Filename : wb_dsp_equations_top.v
// Description : Container for all Equations
// Author : Philip Tracton
// Created On : Wed Jan 13 16:34:33 2016
// Last Modified By: Philip Tracton
// Last Modified On: Wed Jan 13 16:34:33 2016
// Update Count : 0
// Status : Unknown, Use with caution!
module wb_dsp_equations_top (/*AUTOARG*/
// Outputs
eq_adr_o, eq_dat_o, eq_sel_o, eq_we_o, eq_cyc_o, eq_stb_o,
eq_cti_o, eq_bte_o, equation_done,
// Inputs
wb_clk, wb_rst, wb_dat_i, wb_ack_i, wb_err_i, wb_rty_i,
base_address, equation_enable
) ;
parameter dw = 32;
parameter aw = 32;
parameter DEBUG = 0;
input wb_clk;
input wb_rst;
output wire [aw-1:0] eq_adr_o;
output wire [dw-1:0] eq_dat_o;
output wire [3:0] eq_sel_o;
output wire eq_we_o;
output wire eq_cyc_o;
output wire eq_stb_o;
output wire [2:0] eq_cti_o;
output wire [1:0] eq_bte_o;
input [dw-1:0] wb_dat_i;
input wb_ack_i;
input wb_err_i;
input wb_rty_i;
input [aw-1:0] base_address;
input [7:0] equation_enable;
output equation_done;
/****************************************************************************
EQUATION: SUM
****************************************************************************/
wire [aw-1:0] sum_adr_o;
wire [dw-1:0] sum_dat_o;
wire [3:0] sum_sel_o;
wire sum_we_o;
wire sum_cyc_o;
wire sum_stb_o;
wire [2:0] sum_cti_o;
wire [1:0] sum_bte_o;
equation_sum #(.aw(aw), .dw(dw),.DEBUG(DEBUG))
sum(
// Outputs
.wb_adr_o(sum_adr_o),
.wb_dat_o(sum_dat_o),
.wb_sel_o(sum_sel_o),
.wb_we_o(sum_we_o),
.wb_cyc_o(sum_cyc_o),
.wb_stb_o(sum_stb_o),
.wb_cti_o(),
.wb_bte_o(),
.equation_done(sum_equation_done),
// Inputs
.wb_clk(wb_clk),
.wb_rst(wb_rst),
.wb_dat_i(wb_dat_i),
.wb_ack_i(wb_ack_i),
.wb_err_i(wb_err_i),
.wb_rty_i(wb_rty_i),
.base_address(base_address),
.equation_enable(equation_enable)
);
/****************************************************************************
Put all the equation output busses together. This is why they are required
to drive 0's on all signal when not active!
****************************************************************************/
assign eq_adr_o = sum_adr_o;
assign eq_dat_o = sum_dat_o;
assign eq_sel_o = sum_sel_o;
assign eq_we_o = sum_we_o;
assign eq_cyc_o = sum_cyc_o;
assign eq_stb_o = sum_stb_o;
assign eq_cti_o = sum_cti_o;
assign eq_bte_o = sum_bte_o;
assign eq_cti_o = 0;
assign eq_bte_o = 0;
assign equation_done = sum_equation_done;
endmodule // wb_dsp_equations_top
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__NOR4B_BEHAVIORAL_PP_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nor4b (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y , A, B, C, not0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4B_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2B_TB_V
`define SKY130_FD_SC_HS__NAND2B_TB_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand2b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 A_N = 1'b1;
#120 B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 A_N = 1'b0;
#200 B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 B = 1'b1;
#320 A_N = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 B = 1'bx;
#400 A_N = 1'bx;
end
sky130_fd_sc_hs__nand2b dut (.A_N(A_N), .B(B), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2B_TB_V
|
Require Import Verdi.Verdi.
Require Import Verdi.HandlerMonad.
Require Import Verdi.NameOverlay.
Require Import Verdi.LabeledNet.
Require Import Verdi.TotalMapSimulations.
Require Import Verdi.PartialMapSimulations.
Require Import Verdi.TotalMapExecutionSimulations.
Require Import Verdi.PartialMapExecutionSimulations.
Require Import NameAdjacency.
Require Import TreeAux.
Require Import FailureRecorderStaticLabeledCorrect.
Require Import TreeStaticLabeled.
Require Import InfSeqExt.infseq.
Require Import InfSeqExt.classical.
Require Import InfSeqExt.exteq.
Require Import InfSeqExt.map.
Require Import Sumbool.
Require Import Orders.
Require Import MSetFacts.
Require Import MSetProperties.
Require Import FMapInterface.
Require Import Sorting.Permutation.
Require Import mathcomp.ssreflect.ssreflect.
Require Import mathcomp.ssreflect.ssrbool.
Local Arguments update {_} {_} _ _ _ _ _ : simpl never.
Set Implicit Arguments.
Module TreeCorrect (Import NT : NameType)
(NOT : NameOrderedType NT) (NSet : MSetInterface.S with Module E := NOT)
(NOTC : NameOrderedTypeCompat NT) (NMap : FMapInterface.S with Module E := NOTC)
(Import RNT : RootNameType NT)
(Import ANT : AdjacentNameType NT) (Import A : Adjacency NT NOT NSet ANT)
(Import TA : TAux NT NOT NSet NOTC NMap).
Module NSetFacts := Facts NSet.
Module NSetProps := Properties NSet.
Module NSetOrdProps := OrdProperties NSet.
Require Import FMapFacts.
Module NMapFacts := Facts NMap.
Module FRC := FailureRecorderCorrect NT NOT NSet ANT A.
Module FR := FRC.FR.
Module TR := Tree NT NOT NSet NOTC NMap RNT ANT A TA.
Import TR.
Instance Tree_FailureRecorder_base_params_pt_map : BaseParamsPartialMap Tree_BaseParams FR.FailureRecorder_BaseParams :=
{
pt_map_data := fun d => FR.mkData d.(adjacent) ;
pt_map_input := fun _ => None ;
pt_map_output := fun _ => None
}.
Instance Tree_FailureRecorder_name_tot_map : MultiParamsNameTotalMap Tree_MultiParams FR.FailureRecorder_MultiParams :=
{
tot_map_name := id ;
tot_map_name_inv := id ;
}.
Instance Tree_FailureRecorder_name_tot_map_bijective : MultiParamsNameTotalMapBijective Tree_FailureRecorder_name_tot_map :=
{
tot_map_name_inv_inverse := fun _ => Logic.eq_refl ;
tot_map_name_inverse_inv := fun _ => Logic.eq_refl
}.
Instance Tree_FailureRecorder_multi_params_pt_map : MultiParamsMsgPartialMap Tree_MultiParams FR.FailureRecorder_MultiParams :=
{
pt_map_msg := fun m => match m with Fail => Some FR.Fail | _ => None end ;
}.
Instance Tree_FailureRecorder_multi_params_pt_map_congruency : MultiParamsPartialMapCongruency Tree_FailureRecorder_base_params_pt_map Tree_FailureRecorder_name_tot_map Tree_FailureRecorder_multi_params_pt_map :=
{
pt_init_handlers_eq := _ ;
pt_net_handlers_some := _ ;
pt_net_handlers_none := _ ;
pt_input_handlers_some := _ ;
pt_input_handlers_none := _
}.
Proof.
- by move => n; rewrite /= /InitData /=; break_if.
- move => me src mg st mg' H_eq.
rewrite /pt_mapped_net_handlers.
repeat break_let.
case H_n: net_handlers => [[out st'] ps].
rewrite /net_handlers /= /runGenHandler_ignore /= /unlabeled_net_handlers /lb_net_handlers /= /runGenHandler /id in Heqp H_n.
repeat break_let.
repeat tuple_inversion.
destruct st'.
by net_handler_cases; FR.net_handler_cases; simpl in *; congruence.
- move => me src mg st out st' ps H_eq H_eq'.
rewrite /= /runGenHandler_ignore /unlabeled_net_handlers /= /runGenHandler /= in H_eq'.
repeat break_let.
repeat tuple_inversion.
destruct st'.
by net_handler_cases; simpl in *; congruence.
- move => me inp st inp' H_eq.
rewrite /pt_mapped_input_handlers.
repeat break_let.
case H_i: input_handlers => [[out st'] ps].
rewrite /= /runGenHandler_ignore /= /unlabeled_input_handlers /lb_input_handlers /= /runGenHandler in Heqp H_i.
repeat break_let.
repeat tuple_inversion.
by io_handler_cases.
- move => me inp st out st' ps H_eq H_eq'.
rewrite /= /runGenHandler_ignore /= /unlabeled_input_handlers /lb_input_handlers /= /runGenHandler in H_eq'.
repeat break_let.
repeat tuple_inversion.
destruct st'.
io_handler_cases; simpl in *; try congruence.
rewrite /level_adjacent NSet.fold_spec /flip /=.
elim: NSet.elements => //=.
move => n l IH.
rewrite /flip /= /level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg).
by rewrite pt_map_name_msgs_app_distr /= IH.
rewrite /level_adjacent NSet.fold_spec /flip /=.
elim: NSet.elements => //=.
move => n l IH.
rewrite /flip /= /level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg).
by rewrite pt_map_name_msgs_app_distr /= IH.
Qed.
Instance Tree_FailureRecorder_fail_msg_params_pt_map_congruency : FailMsgParamsPartialMapCongruency Tree_FailMsgParams FR.FailureRecorder_FailMsgParams Tree_FailureRecorder_multi_params_pt_map :=
{
pt_fail_msg_fst_snd := Logic.eq_refl
}.
Instance Tree_FailureRecorder_name_overlay_params_tot_map_congruency : NameOverlayParamsTotalMapCongruency Tree_NameOverlayParams FR.FailureRecorder_NameOverlayParams Tree_FailureRecorder_name_tot_map :=
{
tot_adjacent_to_fst_snd := fun _ _ => conj (fun H => H) (fun H => H)
}.
Theorem Tree_Failed_pt_mapped_simulation_star_1 :
forall net failed tr,
@step_ordered_failure_star _ _ _ Tree_FailMsgParams step_ordered_failure_init (failed, net) tr ->
@step_ordered_failure_star _ _ _ FR.FailureRecorder_FailMsgParams step_ordered_failure_init (failed, pt_map_onet net) (pt_map_traces tr).
Proof.
move => onet failed tr H_st.
apply step_ordered_failure_pt_mapped_simulation_star_1 in H_st.
by rewrite map_id in H_st.
Qed.
Instance Tree_FailureRecorder_label_tot_map : LabeledMultiParamsLabelTotalMap Tree_LabeledMultiParams FR.FailureRecorder_LabeledMultiParams :=
{
tot_map_label := fun lb =>
match lb with
| Tau => FR.Tau
| RecvFail dst src => FR.RecvFail dst src
| RecvLevel _ _ => FR.Tau
| DeliverBroadcastTrue _ => FR.Tau
| DeliverBroadcastFalse _ => FR.Tau
| DeliverLevelRequest _ => FR.Tau
end
}.
Instance Tree_FailureRecorder_labeled_partial_map_congruency : LabeledMultiParamsPartialMapCongruency Tree_FailureRecorder_base_params_pt_map Tree_FailureRecorder_name_tot_map Tree_FailureRecorder_multi_params_pt_map Tree_FailureRecorder_label_tot_map :=
{
pt_lb_label_silent_fst_snd := Logic.eq_refl ;
pt_lb_net_handlers_some := _ ;
pt_lb_net_handlers_none := _ ;
pt_lb_input_handlers_some := _ ;
pt_lb_input_handlers_none := _
}.
Proof.
- move => me src m st m' out st' ps lb H_m H_eq.
rewrite /lb_net_handlers /= /runGenHandler /= /id /= in H_eq.
rewrite /tot_mapped_lb_net_handlers_label /= /runGenHandler /=.
case H_n: NetHandler => [[[lb' out'] st''] ps'].
by net_handler_cases; FR.net_handler_cases; simpl in *; congruence.
- move => me src m st H_eq.
rewrite /tot_mapped_lb_net_handlers_label /= /runGenHandler /=.
case H_n: NetHandler => [[[lb out] st'] ps].
by net_handler_cases.
- move => me inp st inp' out st' ps lb H_i H_eq.
rewrite /tot_mapped_lb_input_handlers_label /= /runGenHandler /=.
case H_inp: IOHandler => [[[lb' out'] st''] ps'].
by io_handler_cases.
- move => me inp st H_eq.
rewrite /tot_mapped_lb_input_handlers_label /= /runGenHandler /=.
case H_inp: IOHandler => [[[lb' out'] st''] ps'].
by io_handler_cases.
Qed.
Lemma Tree_node_not_adjacent_self :
forall net failed tr n,
step_ordered_failure_star step_ordered_failure_init (failed, net) tr ->
~ In n failed ->
~ NSet.In n (onwState net n).(adjacent).
Proof.
move => onet failed tr n H_st H_in_f.
have H_st' := Tree_Failed_pt_mapped_simulation_star_1 H_st.
exact: FRC.Failure_node_not_adjacent_self H_st' H_in_f.
Qed.
Lemma Tree_not_failed_no_fail :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
~ In Fail (onet.(onwPackets) n n').
Proof.
move => onet failed tr H_st n n' H_in_f.
have H_st' := Tree_Failed_pt_mapped_simulation_star_1 H_st.
have H_inv' := FRC.Failure_not_failed_no_fail H_st' n n' H_in_f.
move => H_in.
case: H_inv'.
rewrite /= /id /=.
move: H_in.
exact: in_msg_pt_map_msgs.
Qed.
Lemma Tree_in_adj_adjacent_to :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
NSet.In n' (onet.(onwState) n).(adjacent) ->
adjacent_to n' n.
Proof.
move => net failed tr H_st n n' H_in_f H_ins.
have H_st' := Tree_Failed_pt_mapped_simulation_star_1 H_st.
exact (FRC.Failure_in_adj_adjacent_to H_st' n H_in_f H_ins).
Qed.
Lemma Tree_pt_map_msg_injective :
forall m0 m1 m2 : msg,
pt_map_msg m0 = Some m2 -> pt_map_msg m1 = Some m2 -> m0 = m1.
Proof.
by case => [|lvo]; case => [|lvo'] H_eq.
Qed.
Lemma Tree_in_adj_or_incoming_fail :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
NSet.In n' (onet.(onwState) n).(adjacent) ->
~ In n' failed \/ (In n' failed /\ In Fail (onet.(onwPackets) n' n)).
Proof.
move => net failed tr H_st n n' H_in_f H_ins.
have H_st' := Tree_Failed_pt_mapped_simulation_star_1 H_st.
have H_inv' := FRC.Failure_in_adj_or_incoming_fail H_st' _ H_in_f H_ins.
case: H_inv' => H_inv'; first by left.
right.
move: H_inv' => [H_in_f' H_inv'].
split => //.
move: H_inv'.
apply: in_pt_map_msgs_in_msg; last exact: pt_fail_msg_fst_snd.
exact: Tree_pt_map_msg_injective.
Qed.
Lemma Tree_le_one_fail :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
count_occ Msg_eq_dec (onet.(onwPackets) n' n) Fail <= 1.
Proof.
move => onet failed tr H_st n n' H_in_f.
have H_st' := Tree_Failed_pt_mapped_simulation_star_1 H_st.
have H_inv' := FRC.Failure_le_one_fail H_st' _ n' H_in_f.
rewrite /= /id /= in H_inv'.
move: H_inv'.
set c1 := count_occ _ _ _.
set c2 := count_occ _ _ _.
suff H_suff: c1 = c2 by rewrite -H_suff.
rewrite /c1 /c2 {c1 c2}.
apply: count_occ_pt_map_msgs_eq => //.
exact: Tree_pt_map_msg_injective.
Qed.
Lemma Tree_adjacent_to_in_adj :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
~ In n' failed ->
adjacent_to n' n ->
NSet.In n' (onet.(onwState) n).(adjacent).
Proof.
move => onet failed tr H_st n n' H_in_f H_in_f' H_adj.
have H_st' := Tree_Failed_pt_mapped_simulation_star_1 H_st.
exact: (FRC.Failure_adjacent_to_in_adj H_st' H_in_f H_in_f' H_adj).
Qed.
Lemma Tree_in_queue_fail_then_adjacent :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
In Fail (onet.(onwPackets) n' n) ->
NSet.In n' (onet.(onwState) n).(adjacent).
Proof.
move => onet failed tr H_st n n' H_in_f H_ins.
have H_st' := Tree_Failed_pt_mapped_simulation_star_1 H_st.
have H_inv' := FRC.Failure_in_queue_fail_then_adjacent H_st' _ n' H_in_f.
apply: H_inv'.
rewrite /= /id /=.
move: H_ins.
exact: in_msg_pt_map_msgs.
Qed.
Lemma Tree_first_fail_in_adj :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
head (onet.(onwPackets) n' n) = Some Fail ->
NSet.In n' (onet.(onwState) n).(adjacent).
Proof.
move => onet failed tr H_st n n' H_in_f H_eq.
have H_st' := Tree_Failed_pt_mapped_simulation_star_1 H_st.
have H_inv' := FRC.Failure_first_fail_in_adj H_st' _ n' H_in_f.
apply: H_inv'.
rewrite /= /id /=.
move: H_eq.
exact: hd_error_pt_map_msgs.
Qed.
Lemma Tree_adjacent_failed_incoming_fail :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
NSet.In n' (onet.(onwState) n).(adjacent) ->
In n' failed ->
In Fail (onet.(onwPackets) n' n).
Proof.
move => onet failed tr H_st n n' H_in_f H_adj H_in_f'.
have H_or := Tree_in_adj_or_incoming_fail H_st _ H_in_f H_adj.
case: H_or => H_or //.
by move: H_or => [H_in H_in'].
Qed.
(* bfs_net_ok_root_levels_empty *)
Lemma Tree_root_levels_empty :
forall net failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, net) tr ->
forall n, ~ In n failed ->
root n ->
(net.(onwState) n).(levels) = NMap.empty lv.
Proof.
move => onet failed tr H.
have H_eq_f: failed = fst (failed, onet) by [].
have H_eq_o: onet = snd (failed, onet) by [].
rewrite H_eq_f {H_eq_f}.
rewrite {2}H_eq_o {H_eq_o}.
remember step_ordered_failure_init as y in *.
move: Heqy.
induction H using refl_trans_1n_trace_n1_ind => H_init {failed}.
rewrite H_init /=.
move => n H_in H_r.
rewrite /InitData /=.
by break_if.
concludes.
match goal with
| [ H : step_ordered_failure _ _ _ |- _ ] => invc H
end; simpl.
- find_apply_lem_hyp net_handlers_NetHandler; break_exists.
net_handler_cases => //= ; simpl in *;
update_destruct_max_simplify; repeat find_rewrite; auto.
- find_apply_lem_hyp input_handlers_IOHandler; break_exists.
io_handler_cases => //=; simpl in *;
update_destruct_max_simplify; repeat find_rewrite; auto.
- intros. simpl in *.
eauto.
Qed.
Definition head_message_enables_label m src dst l :=
forall net failed,
~ In dst failed ->
head (net.(onwPackets) src dst) = Some m ->
enabled lb_step_ordered_failure l (failed, net).
Lemma Fail_enables_RecvFail :
forall src dst, head_message_enables_label Fail src dst (RecvFail dst src).
Proof.
move => src dst.
rewrite /head_message_enables_label.
move => net failed H_f H_eq.
case H_eq_p: (onwPackets net src dst) => [|m ms]; first by find_rewrite.
find_rewrite.
simpl in *.
find_injection.
rewrite /enabled.
case H_hnd: (@lb_net_handlers _ Tree_LabeledMultiParams dst src Fail (onwState net dst)) => [[[lb' out] d'] l].
have H_lb := H_hnd.
rewrite /lb_net_handlers /= in H_hnd.
by net_handler_cases => //;
exists (failed, {| onwPackets := update2 Net.name_eq_dec (onwPackets net) src dst ms; onwState := update name_eq_dec (onwState net) dst d' |}), []; apply: LabeledStepOrderedFailure_deliver; eauto.
Qed.
Lemma Level_enables_RecvLevel :
forall src dst lvo, head_message_enables_label (Level lvo) src dst (RecvLevel dst src).
Proof.
move => src dst lvo.
rewrite /head_message_enables_label.
move => net failed H_f H_eq.
case H_eq_p: (onwPackets net src dst) => [|m ms]; first by find_rewrite.
find_rewrite.
simpl in *.
find_injection.
rewrite /enabled.
case H_hnd: (@lb_net_handlers _ Tree_LabeledMultiParams dst src (Level lvo) (onwState net dst)) => [[[lb' out] d'] l].
have H_lb := H_hnd.
rewrite /lb_net_handlers /= in H_hnd.
net_handler_cases => //; find_injection.
- by exists (failed, {| onwPackets := update2 Net.name_eq_dec (onwPackets net) src dst ms; onwState := update name_eq_dec (onwState net) dst (onwState net dst) |}), []; apply: LabeledStepOrderedFailure_deliver; eauto.
- by exists (failed, {| onwPackets := update2 Net.name_eq_dec (onwPackets net) src dst ms; onwState := update name_eq_dec (onwState net) dst d' |}), []; apply: LabeledStepOrderedFailure_deliver; eauto.
- by exists (failed, {| onwPackets := update2 Net.name_eq_dec (onwPackets net) src dst ms; onwState := update name_eq_dec (onwState net) dst d' |}), []; apply: LabeledStepOrderedFailure_deliver; eauto.
- by exists (failed, {| onwPackets := update2 Net.name_eq_dec (onwPackets net) src dst ms; onwState := update name_eq_dec (onwState net) dst d' |}), []; apply: LabeledStepOrderedFailure_deliver; eauto.
- by exists (failed, {| onwPackets := update2 Net.name_eq_dec (onwPackets net) src dst ms; onwState := update name_eq_dec (onwState net) dst d' |}), []; apply: LabeledStepOrderedFailure_deliver; eauto.
Qed.
Lemma Tree_lb_step_ordered_failure_RecvFail_enabled :
forall net net' net'' failed failed' failed'' tr tr' dst src l,
l <> RecvFail dst src ->
lb_step_ordered_failure (failed, net) l (failed', net') tr ->
lb_step_ordered_failure (failed, net) (RecvFail dst src) (failed'', net'') tr' ->
enabled lb_step_ordered_failure (RecvFail dst src) (failed', net').
Proof.
move => net net' net'' failed failed' failed'' tr tr' dst src l H_neq H_st H_st'.
destruct l => //.
- invcs H_st => //.
* by net_handler_cases.
* by io_handler_cases.
* invcs H_st' => //; last by io_handler_cases.
have H_hd: head (onwPackets net' src dst) = Some Fail by net_handler_cases => //; find_injection; find_rewrite.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
exact: Fail_enables_RecvFail.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: onwPackets net src dst = Fail :: ms by net_handler_cases => //; find_injection; find_rewrite.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; last by io_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some Fail.
rewrite /net' /=.
net_handler_cases => //=; rewrite /update2.
* break_if.
+ by break_and; subst; intuition.
+ by find_rewrite.
* break_if.
+ by break_and; subst; intuition.
+ by find_rewrite.
* break_if.
+ by break_and; subst; intuition.
+ by find_rewrite.
exact: Fail_enables_RecvFail.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: onwPackets net src dst = Fail :: ms by net_handler_cases => //; find_injection; find_rewrite.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; last by io_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some Fail.
rewrite /net' /=.
net_handler_cases => //=; rewrite /update2.
* break_if.
+ break_and; subst.
by find_rewrite.
+ by find_rewrite.
* break_if.
+ break_and; subst.
by find_rewrite.
+ by find_rewrite.
* break_if.
+ break_and; subst.
by find_rewrite.
+ by find_rewrite.
* break_if.
+ break_and; subst.
by find_rewrite.
+ by find_rewrite.
* break_if.
+ break_and; subst.
by find_rewrite.
+ by find_rewrite.
exact: Fail_enables_RecvFail.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: onwPackets net src dst = Fail :: ms by net_handler_cases => //; find_injection; find_rewrite.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; first by net_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some Fail.
rewrite /net' /=.
io_handler_cases => //=.
* find_injection.
case (name_eq_dec h src) => H_dec; last by rewrite collate_neq //; find_rewrite.
subst_max.
apply collate_head_head.
by find_rewrite.
* find_injection.
case (name_eq_dec h src) => H_dec; last by rewrite collate_neq //; find_rewrite.
subst_max.
apply collate_head_head.
by find_rewrite.
exact: Fail_enables_RecvFail.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: onwPackets net src dst = Fail :: ms by net_handler_cases => //; find_injection; find_rewrite.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; first by net_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some Fail.
rewrite /net' /=.
io_handler_cases => //=.
by find_rewrite.
exact: Fail_enables_RecvFail.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: onwPackets net src dst = Fail :: ms by net_handler_cases => //; find_injection; find_rewrite.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; first by net_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some Fail.
rewrite /net' /=.
by io_handler_cases => //=; find_rewrite.
exact: Fail_enables_RecvFail.
Qed.
Lemma Tree_lb_step_ordered_failure_RecvLevel_enabled :
forall net net' net'' failed failed' failed'' tr tr' dst src l,
l <> RecvLevel dst src ->
lb_step_ordered_failure (failed, net) l (failed', net') tr ->
lb_step_ordered_failure (failed, net) (RecvLevel dst src) (failed'', net'') tr' ->
enabled lb_step_ordered_failure (RecvLevel dst src) (failed', net').
Proof.
move => net net' net'' failed failed' failed'' tr tr' dst src l H_neq H_st H_st'.
destruct l => //.
- invcs H_st => //.
* by net_handler_cases.
* by io_handler_cases.
* invcs H_st' => //; last by io_handler_cases.
have H_hd: exists lvo, head (onwPackets net' src dst) = Some (Level lvo) by net_handler_cases => //; find_injection; find_rewrite; eexists.
break_exists.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
by apply: Level_enables_RecvLevel; eauto.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: exists lvo, onwPackets net src dst = Level lvo :: ms by net_handler_cases => //; find_injection; find_rewrite; eexists.
break_exists_name lvo.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; last by io_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some (Level lvo).
rewrite /net' /=.
net_handler_cases => //=; rewrite /update2.
* break_if.
+ break_and; subst.
by find_rewrite.
+ by find_rewrite.
* break_if.
+ break_and; subst.
by find_rewrite.
+ by find_rewrite.
* break_if.
+ break_and; subst.
by find_rewrite.
+ by find_rewrite.
by apply: Level_enables_RecvLevel; eauto.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: exists lvo, onwPackets net src dst = Level lvo :: ms by net_handler_cases => //; find_injection; find_rewrite; eexists.
break_exists_name lvo.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; last by io_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some (Level lvo).
rewrite /net' /=.
net_handler_cases => //=; rewrite /update2.
* break_if.
+ by break_and; subst; intuition.
+ by find_rewrite.
* break_if.
+ by break_and; subst; intuition.
+ by find_rewrite.
* break_if.
+ by break_and; subst; intuition.
+ by find_rewrite.
* break_if.
+ by break_and; subst; intuition.
+ by find_rewrite.
* break_if.
+ by break_and; subst; intuition.
+ by find_rewrite.
by apply: Level_enables_RecvLevel; eauto.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: exists lvo, onwPackets net src dst = Level lvo :: ms by net_handler_cases => //; find_injection; find_rewrite; eexists.
break_exists_name lvo.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; first by net_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some (Level lvo).
rewrite /net' /=.
io_handler_cases => //=.
* find_injection.
case (name_eq_dec h src) => H_dec; last by rewrite collate_neq //; find_rewrite.
subst_max.
apply collate_head_head.
by find_rewrite.
* find_injection.
case (name_eq_dec h src) => H_dec; last by rewrite collate_neq //; find_rewrite.
subst_max.
apply collate_head_head.
by find_rewrite.
by apply: Level_enables_RecvLevel; eauto.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: exists lvo, onwPackets net src dst = Level lvo :: ms by net_handler_cases => //; find_injection; find_rewrite; eexists.
break_exists_name lvo.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; first by net_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some (Level lvo).
rewrite /net' /=.
io_handler_cases => //=.
by find_rewrite.
by apply: Level_enables_RecvLevel; eauto.
- invcs H_st' => //; last by io_handler_cases.
have H_eq: exists lvo, onwPackets net src dst = Level lvo :: ms by net_handler_cases => //; find_injection; find_rewrite; eexists.
break_exists_name lvo.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //; first by net_handler_cases.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some (Level lvo).
rewrite /net' /=.
by io_handler_cases => //=; find_rewrite.
by apply: Level_enables_RecvLevel; eauto.
Qed.
Lemma Tree_RecvFail_enabled_weak_until_occurred :
forall s, lb_step_execution lb_step_ordered_failure s ->
forall src dst, l_enabled lb_step_ordered_failure (RecvFail dst src) (hd s) ->
weak_until (now (l_enabled lb_step_ordered_failure (RecvFail dst src)))
(now (occurred (RecvFail dst src)))
s.
Proof.
cofix c.
case => /=.
case; case => failed net l tr s H_exec src dst.
case (Label_eq_dec l (RecvFail dst src)) => H_eq H_en.
- find_rewrite.
exact: W0.
- apply: W_tl; first by [].
apply: c; first by find_apply_lem_hyp lb_step_execution_invar.
unfold l_enabled in *.
unfold enabled in H_en.
break_exists.
destruct s as [e s].
inversion H_exec; subst_max.
inversion H5; subst.
destruct e, evt_a.
destruct e', evt_a.
destruct x.
simpl in *.
by apply: Tree_lb_step_ordered_failure_RecvFail_enabled; eauto.
Qed.
Lemma Tree_RecvLevel_enabled_weak_until_occurred :
forall s, lb_step_execution lb_step_ordered_failure s ->
forall src dst, l_enabled lb_step_ordered_failure (RecvLevel dst src) (hd s) ->
weak_until (now (l_enabled lb_step_ordered_failure (RecvLevel dst src)))
(now (occurred (RecvLevel dst src)))
s.
Proof.
cofix c.
case => /=.
case; case => failed net l tr s H_exec src dst.
case (Label_eq_dec l (RecvLevel dst src)) => H_eq H_en.
- find_rewrite.
exact: W0.
- apply: W_tl; first by [].
apply: c; first by find_apply_lem_hyp lb_step_execution_invar.
unfold l_enabled in *.
unfold enabled in H_en.
break_exists.
destruct s as [e s].
inversion H_exec; subst_max.
inversion H5; subst.
destruct e, evt_a.
destruct e', evt_a.
destruct x.
simpl in *.
by apply: Tree_lb_step_ordered_failure_RecvLevel_enabled; eauto.
Qed.
Lemma Tree_RecvFail_eventually_occurred :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
forall src dst, l_enabled lb_step_ordered_failure (RecvFail dst src) (hd s) ->
eventually (now (occurred (RecvFail dst src))) s.
Proof.
move => s H_exec H_fair src dst H_en.
have H_wu := Tree_RecvFail_enabled_weak_until_occurred H_exec H_en.
apply weak_until_until_or_always in H_wu.
case: H_wu; first exact: until_eventually.
move => H_al.
apply always_continuously in H_al.
apply H_fair in H_al => //.
destruct s as [x s].
by apply always_now in H_al.
Qed.
Lemma Tree_RecvLevel_eventually_occurred :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
forall src dst, l_enabled lb_step_ordered_failure (RecvLevel dst src) (hd s) ->
eventually (now (occurred (RecvLevel dst src))) s.
Proof.
move => s H_exec H_fair src dst H_en.
have H_wu := Tree_RecvLevel_enabled_weak_until_occurred H_exec H_en.
apply weak_until_until_or_always in H_wu.
case: H_wu; first exact: until_eventually.
move => H_al.
apply always_continuously in H_al.
apply H_fair in H_al => //.
destruct s as [x s].
by apply always_now in H_al.
Qed.
Lemma Tree_lb_step_ordered_failure_not_in_failed :
forall net net' failed failed' lb tr h,
~ In h failed ->
lb_step_ordered_failure (failed, net) lb (failed', net') tr ->
~ In h failed'.
Proof.
move => net net' failed failed' lb tr h H_in_f H_step.
by invcs H_step.
Qed.
Lemma Tree_not_in_failed_always :
forall s, lb_step_execution lb_step_ordered_failure s ->
forall h, ~ In h (fst (hd s).(evt_a)) ->
always (now (fun e => ~ In h (fst e.(evt_a)))) s.
Proof.
cofix c.
move => s H_exec.
inversion H_exec => /=.
move => h H_in_f.
apply: Always; first by [].
rewrite /=.
apply: c; first by [].
rewrite /=.
destruct e, e', evt_a, evt_a0.
simpl in *.
by eapply Tree_lb_step_ordered_failure_not_in_failed; eauto.
Qed.
Lemma Tree_lb_step_ordered_failure_Fail_head_add_msg_end :
forall net net' failed failed' tr l,
lb_step_ordered_failure (failed, net) l (failed', net') tr ->
forall dst src ms, l <> RecvFail dst src ->
onwPackets net src dst = Fail :: ms ->
exists ms' : list Msg, onwPackets net' src dst = Fail :: ms ++ ms'.
Proof.
move => net net' failed failed' tr l H_st dst src ms H_neq H_eq.
invcs H_st => //=.
- net_handler_cases => //=.
* exists [].
rewrite /update2.
break_if; first by break_and; subst_max; intuition.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst_max; intuition.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst_max; intuition.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst; find_rewrite.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst; find_rewrite.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst; find_rewrite.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst; find_rewrite.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst; find_rewrite.
by rewrite -app_nil_end.
- io_handler_cases => //=.
* case (name_eq_dec h src) => H_dec.
+ subst_max.
case H_adj: (NSet.mem dst (net.(onwState) src).(adjacent)).
-- find_apply_lem_hyp NSetFacts.mem_2.
have H_in: In dst (NSet.elements (adjacent (onwState net src))).
apply NSet.elements_spec1 in H_adj.
rewrite /NSet.E.eq in H_adj.
apply InA_alt in H_adj.
break_exists.
break_and.
by subst_max.
have H_nd := NSet.elements_spec2w (adjacent (onwState net src)).
rewrite /NSet.E.eq in H_nd.
rewrite /level_adjacent NSet.fold_spec /flip /=.
elim: (NSet.elements (adjacent (onwState net src))) H_in H_nd => /= [|n ns IH] H_in H_nd; first by exists []; rewrite -app_nil_end.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
inversion H_nd; subst_max.
break_or_hyp.
rewrite /update2.
break_if; last by intuition.
exists [Level (Some 0)].
have H_not_in: ~ In dst ns.
move => H_in'.
contradict H7.
apply InA_alt.
by exists dst.
move {IH H8 H_nd H7}.
elim: ns H_not_in => /= [|n' ns IH] H_not_in; first by find_rewrite.
have H_in': ~ In dst ns by auto.
have H_neq': n' <> dst by auto.
concludes.
rewrite /flip /= {2}/level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
rewrite /update2.
break_if; first by break_and; subst_max.
by rewrite IH.
concludes.
concludes.
break_exists.
have H_neq': n <> dst.
move => H_eq'.
subst_max.
contradict H7.
apply InA_alt.
by exists dst.
rewrite /update2.
break_if; first by break_and.
rewrite H1.
by exists x.
-- have H_adj': ~ NSet.In dst (adjacent (onwState net src)).
move => H_ins.
find_apply_lem_hyp NSetFacts.mem_1.
by find_rewrite.
rewrite /level_adjacent NSet.fold_spec /=.
have H_in: ~ In dst (NSet.elements (adjacent (onwState net src))).
move => H_in.
contradict H_adj'.
apply NSet.elements_spec1.
rewrite /NSet.E.eq.
apply InA_alt.
exists dst.
by split.
elim: (NSet.elements (adjacent (onwState net src))) H_in => /= [|n ns IH] H_in; first by exists []; rewrite -app_nil_end.
have H_in': ~ In dst ns by auto.
have H_neq': n <> dst by auto.
concludes.
break_exists.
rewrite /flip /= {2}/level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
rewrite /update2.
break_if; first by break_and.
rewrite H.
by exists x.
+ rewrite collate_neq //.
by exists []; rewrite -app_nil_end.
* case (name_eq_dec h src) => H_dec.
+ subst_max.
case H_adj: (NSet.mem dst (net.(onwState) src).(adjacent)).
-- find_apply_lem_hyp NSetFacts.mem_2.
have H_in: In dst (NSet.elements (adjacent (onwState net src))).
apply NSet.elements_spec1 in H_adj.
rewrite /NSet.E.eq in H_adj.
apply InA_alt in H_adj.
break_exists.
break_and.
by subst_max.
have H_nd := NSet.elements_spec2w (adjacent (onwState net src)).
rewrite /NSet.E.eq in H_nd.
rewrite /level_adjacent NSet.fold_spec /flip /=.
elim: (NSet.elements (adjacent (onwState net src))) H_in H_nd => /= [|n ns IH] H_in H_nd; first by exists []; rewrite -app_nil_end.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
inversion H_nd; subst_max.
break_or_hyp.
rewrite /update2.
break_if; last by intuition.
exists [Level (level (adjacent (onwState net src)) (levels (onwState net src)))].
have H_not_in: ~ In dst ns.
move => H_in'.
contradict H7.
apply InA_alt.
by exists dst.
move {IH H8 H_nd H7}.
elim: ns H_not_in => /= [|n' ns IH] H_not_in; first by find_rewrite.
have H_in': ~ In dst ns by auto.
have H_neq': n' <> dst by auto.
concludes.
rewrite /flip /= {2}/level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
rewrite /update2.
break_if; first by break_and; subst_max.
by rewrite IH.
concludes.
concludes.
break_exists.
have H_neq': n <> dst.
move => H_eq'.
subst_max.
contradict H7.
apply InA_alt.
by exists dst.
rewrite /update2.
break_if; first by break_and.
rewrite H1.
by exists x.
-- have H_adj': ~ NSet.In dst (adjacent (onwState net src)).
move => H_ins.
find_apply_lem_hyp NSetFacts.mem_1.
by find_rewrite.
rewrite /level_adjacent NSet.fold_spec /=.
have H_in: ~ In dst (NSet.elements (adjacent (onwState net src))).
move => H_in.
contradict H_adj'.
apply NSet.elements_spec1.
rewrite /NSet.E.eq.
apply InA_alt.
exists dst.
by split.
elim: (NSet.elements (adjacent (onwState net src))) H_in => /= [|n ns IH] H_in; first by exists []; rewrite -app_nil_end.
have H_in': ~ In dst ns by auto.
have H_neq': n <> dst by auto.
concludes.
break_exists.
rewrite /flip /= {2}/level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
rewrite /update2.
break_if; first by break_and.
rewrite H0.
by exists x.
+ rewrite collate_neq //.
by exists []; rewrite -app_nil_end.
* by exists []; rewrite -app_nil_end.
- by exists []; rewrite -app_nil_end.
- by exists []; rewrite -app_nil_end.
- by exists []; rewrite -app_nil_end.
Qed.
Lemma Tree_lb_step_ordered_failure_Level_head_add_msg_end :
forall net net' failed failed' tr l,
lb_step_ordered_failure (failed, net) l (failed', net') tr ->
forall dst src lvo ms, l <> RecvLevel dst src ->
onwPackets net src dst = Level lvo :: ms ->
exists ms' : list Msg, onwPackets net' src dst = Level lvo :: ms ++ ms'.
Proof.
move => net net' failed failed' tr l H_st dst src lvo ms H_neq H_eq.
invcs H_st => //=.
- net_handler_cases => //=.
* exists [].
rewrite /update2.
break_if; first by break_and; subst; find_rewrite.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst; find_rewrite.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst; find_rewrite.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst_max; intuition.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst_max; intuition.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst_max; intuition.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst_max; intuition.
by rewrite -app_nil_end.
* exists [].
rewrite /update2.
break_if; first by break_and; subst_max; intuition.
by rewrite -app_nil_end.
- io_handler_cases => //=.
* case (name_eq_dec h src) => H_dec.
+ subst_max.
case H_adj: (NSet.mem dst (net.(onwState) src).(adjacent)).
-- find_apply_lem_hyp NSetFacts.mem_2.
have H_in: In dst (NSet.elements (adjacent (onwState net src))).
apply NSet.elements_spec1 in H_adj.
rewrite /NSet.E.eq in H_adj.
apply InA_alt in H_adj.
break_exists.
break_and.
by subst_max.
have H_nd := NSet.elements_spec2w (adjacent (onwState net src)).
rewrite /NSet.E.eq in H_nd.
rewrite /level_adjacent NSet.fold_spec /flip /=.
elim: (NSet.elements (adjacent (onwState net src))) H_in H_nd => /= [|n ns IH] H_in H_nd; first by exists []; rewrite -app_nil_end.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
inversion H_nd; subst_max.
break_or_hyp.
rewrite /update2.
break_if; last by intuition.
exists [Level (Some 0)].
have H_not_in: ~ In dst ns.
move => H_in'.
contradict H7.
apply InA_alt.
by exists dst.
move {IH H8 H_nd H7}.
elim: ns H_not_in => /= [|n' ns IH] H_not_in; first by find_rewrite.
have H_in': ~ In dst ns by auto.
have H_neq': n' <> dst by auto.
concludes.
rewrite /flip /= {2}/level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
rewrite /update2.
break_if; first by break_and; subst_max.
by rewrite IH.
concludes.
concludes.
break_exists.
have H_neq': n <> dst.
move => H_eq'.
subst_max.
contradict H7.
apply InA_alt.
by exists dst.
rewrite /update2.
break_if; first by break_and.
rewrite H1.
by exists x.
-- have H_adj': ~ NSet.In dst (adjacent (onwState net src)).
move => H_ins.
find_apply_lem_hyp NSetFacts.mem_1.
by find_rewrite.
rewrite /level_adjacent NSet.fold_spec /=.
have H_in: ~ In dst (NSet.elements (adjacent (onwState net src))).
move => H_in.
contradict H_adj'.
apply NSet.elements_spec1.
rewrite /NSet.E.eq.
apply InA_alt.
exists dst.
by split.
elim: (NSet.elements (adjacent (onwState net src))) H_in => /= [|n ns IH] H_in; first by exists []; rewrite -app_nil_end.
have H_in': ~ In dst ns by auto.
have H_neq': n <> dst by auto.
concludes.
break_exists.
rewrite /flip /= {2}/level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
rewrite /update2.
break_if; first by break_and.
rewrite H.
by exists x.
+ rewrite collate_neq //.
by exists []; rewrite -app_nil_end.
* case (name_eq_dec h src) => H_dec.
+ subst_max.
case H_adj: (NSet.mem dst (net.(onwState) src).(adjacent)).
-- find_apply_lem_hyp NSetFacts.mem_2.
have H_in: In dst (NSet.elements (adjacent (onwState net src))).
apply NSet.elements_spec1 in H_adj.
rewrite /NSet.E.eq in H_adj.
apply InA_alt in H_adj.
break_exists.
break_and.
by subst_max.
have H_nd := NSet.elements_spec2w (adjacent (onwState net src)).
rewrite /NSet.E.eq in H_nd.
rewrite /level_adjacent NSet.fold_spec /flip /=.
elim: (NSet.elements (adjacent (onwState net src))) H_in H_nd => /= [|n ns IH] H_in H_nd; first by exists []; rewrite -app_nil_end.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
inversion H_nd; subst_max.
break_or_hyp.
rewrite /update2.
break_if; last by intuition.
exists [Level (level (adjacent (onwState net src)) (levels (onwState net src)))].
have H_not_in: ~ In dst ns.
move => H_in'.
contradict H7.
apply InA_alt.
by exists dst.
move {IH H8 H_nd H7}.
elim: ns H_not_in => /= [|n' ns IH] H_not_in; first by find_rewrite.
have H_in': ~ In dst ns by auto.
have H_neq': n' <> dst by auto.
concludes.
rewrite /flip /= {2}/level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
rewrite /update2.
break_if; first by break_and; subst_max.
by rewrite IH.
concludes.
concludes.
break_exists.
have H_neq': n <> dst.
move => H_eq'.
subst_max.
contradict H7.
apply InA_alt.
by exists dst.
rewrite /update2.
break_if; first by break_and.
rewrite H1.
by exists x.
-- have H_adj': ~ NSet.In dst (adjacent (onwState net src)).
move => H_ins.
find_apply_lem_hyp NSetFacts.mem_1.
by find_rewrite.
rewrite /level_adjacent NSet.fold_spec /=.
have H_in: ~ In dst (NSet.elements (adjacent (onwState net src))).
move => H_in.
contradict H_adj'.
apply NSet.elements_spec1.
rewrite /NSet.E.eq.
apply InA_alt.
exists dst.
by split.
elim: (NSet.elements (adjacent (onwState net src))) H_in => /= [|n ns IH] H_in; first by exists []; rewrite -app_nil_end.
have H_in': ~ In dst ns by auto.
have H_neq': n <> dst by auto.
concludes.
break_exists.
rewrite /flip /= {2}/level_fold.
rewrite (@fold_left_level_fold_eq Tree_TreeMsg) /=.
rewrite collate_app /=.
rewrite /update2.
break_if; first by break_and.
rewrite H0.
by exists x.
+ rewrite collate_neq //.
by exists []; rewrite -app_nil_end.
* by exists []; rewrite -app_nil_end.
- by exists []; rewrite -app_nil_end.
- by exists []; rewrite -app_nil_end.
- by exists []; rewrite -app_nil_end.
Qed.
Lemma Tree_Fail_eventually_remove_head :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
forall src dst, ~ In dst (fst (evt_a (hd s))) ->
forall ms, onwPackets (snd (evt_a (hd s))) src dst = Fail :: ms ->
eventually (now (fun e => exists ms', onwPackets (snd (evt_a e)) src dst = ms ++ ms')) s.
Proof.
move => s H_exec H_fair src dst H_f ms H_eq.
have H_hd: head (onwPackets (snd (evt_a (hd s))) src dst) = Some Fail by find_rewrite.
have H_en := Fail_enables_RecvFail _ _ _ _ H_f H_hd.
have H_ev: eventually (now (occurred (RecvFail dst src))) s.
apply (@Tree_RecvFail_eventually_occurred _ H_exec H_fair src dst).
rewrite /l_enabled.
by destruct evt_a.
have H_ex: exists ms', onwPackets (snd (evt_a (hd s))) src dst = Fail :: ms ++ ms' by exists []; rewrite app_nil_r.
have H_al := Tree_not_in_failed_always H_exec _ H_f.
have H_wu := @Tree_RecvFail_enabled_weak_until_occurred _ H_exec src dst.
move: H_wu.
set le := l_enabled _ _ _.
have H_le: le by rewrite /le /l_enabled; destruct evt_a.
move => H_wu.
concludes.
move {H_eq H_f H_hd H_en H_le le}.
elim: H_ev H_exec H_fair H_ex H_al H_wu.
* case; case; case => /= failed net l tr.
case; case; case => /= failed' net' l' tr'.
case; case; case => /= failed'' net'' l'' tr'' s0 H_occ H_exec H_fair H_ex H_al H_wu.
apply: E_next.
apply: E0.
rewrite /=.
rewrite /occurred /= in H_occ.
subst_max.
inversion H_exec; subst_max.
break_exists_name ms'.
exists ms'.
simpl in *.
invcs H2; last by io_handler_cases.
net_handler_cases => //=.
+ find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
+ find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
+ find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
* case; case => failed net l tr.
case; case; case => failed' net' l' tr'.
case; case; case => failed'' net'' l'' tr'' s0 H_ev IH H_exec H_fair H_ex H_al H_wu.
simpl in *.
break_exists_name ms'.
case (Label_eq_dec l (RecvFail dst src)) => H_eq.
+ subst_max.
apply E_next.
apply E0.
inversion H_exec; subst_max.
simpl in *.
exists ms'.
invcs H2; last by io_handler_cases.
net_handler_cases => //=.
-- find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
-- find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
-- find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
+ apply E_next.
apply IH.
-- by find_apply_lem_hyp lb_step_execution_invar.
-- by find_apply_lem_hyp weak_local_fairness_invar.
-- inversion H_exec; subst_max.
simpl in *.
have H_add := Tree_lb_step_ordered_failure_Fail_head_add_msg_end H2 H_eq H_ex.
break_exists.
rewrite app_assoc_reverse in H.
by exists (ms' ++ x).
-- by find_apply_lem_hyp always_invar.
-- find_apply_lem_hyp weak_until_Cons.
simpl in *.
rewrite /occurred in H_wu.
break_or_hyp; simpl in *; last by intuition.
by rewrite H in H_eq.
Qed.
Lemma Tree_Level_eventually_remove_head :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
forall src dst, ~ In dst (fst (evt_a (hd s))) ->
forall lvo ms, onwPackets (snd (evt_a (hd s))) src dst = Level lvo :: ms ->
eventually (now (fun e => exists ms', onwPackets (snd (evt_a e)) src dst = ms ++ ms')) s.
Proof.
move => s H_exec H_fair src dst H_f lvo ms H_eq.
have H_hd: head (onwPackets (snd (evt_a (hd s))) src dst) = Some (Level lvo) by find_rewrite.
have H_en := Level_enables_RecvLevel _ _ _ _ H_f H_hd.
have H_ev: eventually (now (occurred (RecvLevel dst src))) s.
apply (@Tree_RecvLevel_eventually_occurred _ H_exec H_fair src dst).
rewrite /l_enabled.
by destruct evt_a.
have H_ex: exists ms', onwPackets (snd (evt_a (hd s))) src dst = Level lvo :: ms ++ ms' by exists []; rewrite app_nil_r.
have H_al := Tree_not_in_failed_always H_exec _ H_f.
have H_wu := @Tree_RecvLevel_enabled_weak_until_occurred _ H_exec src dst.
move: H_wu.
set le := l_enabled _ _ _.
have H_le: le by rewrite /le /l_enabled; destruct evt_a.
move => H_wu.
concludes.
move {H_eq H_f H_hd H_en H_le le}.
elim: H_ev H_exec H_fair H_ex H_al H_wu.
* case; case; case => /= failed net l tr.
case; case; case => /= failed' net' l' tr'.
case; case; case => /= failed'' net'' l'' tr'' s0 H_occ H_exec H_fair H_ex H_al H_wu.
apply: E_next.
apply: E0.
rewrite /=.
rewrite /occurred /= in H_occ.
subst_max.
inversion H_exec; subst_max.
break_exists_name ms'.
exists ms'.
simpl in *.
invcs H2; last by io_handler_cases.
net_handler_cases => //=.
+ find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
+ find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
+ find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
+ find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
+ find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
* case; case => failed net l tr.
case; case; case => failed' net' l' tr'.
case; case; case => failed'' net'' l'' tr'' s0 H_ev IH H_exec H_fair H_ex H_al H_wu.
simpl in *.
break_exists_name ms'.
case (Label_eq_dec l (RecvLevel dst src)) => H_eq.
+ subst_max.
apply E_next.
apply E0.
inversion H_exec; subst_max.
simpl in *.
exists ms'.
invcs H2; last by io_handler_cases.
net_handler_cases => //=.
-- find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
-- find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
-- find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
-- find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
-- find_injection; subst_max.
find_rewrite.
find_injection.
rewrite /update2.
by break_if; intuition.
+ apply E_next.
apply IH.
-- by find_apply_lem_hyp lb_step_execution_invar.
-- by find_apply_lem_hyp weak_local_fairness_invar.
-- inversion H_exec; subst_max.
simpl in *.
have H_add := Tree_lb_step_ordered_failure_Level_head_add_msg_end H2 H_eq H_ex.
break_exists.
rewrite app_assoc_reverse in H.
by exists (ms' ++ x).
-- by find_apply_lem_hyp always_invar.
-- find_apply_lem_hyp weak_until_Cons.
simpl in *.
rewrite /occurred in H_wu.
break_or_hyp; simpl in *; last by intuition.
by rewrite H in H_eq.
Qed.
Lemma Tree_msg_eventually_remove_head :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
forall src dst, ~ In dst (fst (evt_a (hd s))) ->
forall m ms, onwPackets (snd (evt_a (hd s))) src dst = m :: ms ->
eventually (now (fun e => exists ms', onwPackets (snd (evt_a e)) src dst = ms ++ ms')) s.
Proof.
move => s H_exec H_fai src dst H_in.
case.
- move => ms H_eq.
by apply: Tree_Fail_eventually_remove_head; eauto.
- move => ms H_eq.
by apply: Tree_Level_eventually_remove_head; eauto.
Qed.
Lemma Tree_msg_in_eventually_first :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
forall src dst, ~ In dst (fst (evt_a (hd s))) ->
forall m, In m (onwPackets (snd (evt_a (hd s))) src dst) ->
eventually (now (fun e => head (onwPackets (snd (evt_a e)) src dst) = Some m)) s.
Proof.
move => s H_exec H_fair src dst H_f m H_in.
find_apply_lem_hyp in_split.
break_exists_name l1.
break_exists_name l2.
elim: l1 s H_exec H_fair l2 H_in H_f => /=.
- case; case; case => failed net lb tr s H_exec H_fair l2.
rewrite /= => H_eq H_f.
apply: E0.
by rewrite /= H_eq.
- move => m' l /= IH.
case; case; case => /= failed net lb tr s.
set s' := Cons _ _.
move => H_exec H_fair l2 H_eq H_f.
have H_ev := Tree_msg_eventually_remove_head H_exec H_fair _ _ H_f H_eq.
have H_al := Tree_not_in_failed_always H_exec _ H_f.
simpl in *.
elim: H_ev H_exec H_fair H_al.
* case; case; case => /= failed' net' lb' tr' s0 H_eq' H_exec H_fair H_al.
break_exists.
rewrite app_assoc_reverse -app_comm_cons in H.
apply always_now in H_al.
by apply: IH => //=; eauto.
* case; case => /= failed' net' lb' tr' s0 H_ev IH' H_exec H_fair H_al.
apply: E_next.
apply IH'.
+ by find_apply_lem_hyp lb_step_execution_invar.
+ by find_apply_lem_hyp weak_local_fairness_invar.
+ by find_apply_lem_hyp always_invar.
Qed.
Lemma Tree_Fail_in_eventually_enabled :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
forall src dst, ~ In dst (fst (evt_a (hd s))) ->
In Fail (onwPackets (snd (evt_a (hd s))) src dst) ->
eventually (now (l_enabled lb_step_ordered_failure (RecvFail dst src))) s.
Proof.
move => s H_exec H_fair src dst H_f H_in.
have H_ev := Tree_msg_in_eventually_first H_exec H_fair _ _ H_f _ H_in.
have H_al := Tree_not_in_failed_always H_exec _ H_f.
move: H_al H_ev.
apply: eventually_monotonic.
- move => e s0 H_al.
by find_apply_lem_hyp always_invar.
- case; case; case => failed net l tr s' H_eq.
rewrite /l_enabled.
simpl in *.
apply: Fail_enables_RecvFail => //.
by find_apply_lem_hyp always_now.
Qed.
Lemma Tree_Level_in_eventually_enabled :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
forall src dst, ~ In dst (fst (evt_a (hd s))) ->
forall lvo, In (Level lvo) (onwPackets (snd (evt_a (hd s))) src dst) ->
eventually (now (l_enabled lb_step_ordered_failure (RecvLevel dst src))) s.
Proof.
move => s H_exec H_fair src dst H_f lvo H_in.
have H_ev := Tree_msg_in_eventually_first H_exec H_fair _ _ H_f _ H_in.
have H_al := Tree_not_in_failed_always H_exec _ H_f.
move: H_al H_ev.
apply: eventually_monotonic.
- move => e s0 H_al.
by find_apply_lem_hyp always_invar.
- case; case; case => failed net l tr s' H_eq.
rewrite /l_enabled.
simpl in *.
apply: Level_enables_RecvLevel => //.
by find_apply_lem_hyp always_now.
Qed.
Lemma Tree_FailureRecorder_lb_step_execution_pt_map : forall s,
lb_step_execution lb_step_ordered_failure s ->
lb_step_execution lb_step_ordered_failure (map pt_map_onet_event s).
Proof.
apply: lb_step_execution_lb_step_ordered_failure_pt_map_onet_infseq.
exact: FR.Label_eq_dec.
Qed.
Lemma Tree_FailureRecorder_pt_map_onet_hd_step_ordered_failure_star_always :
forall s, event_step_star step_ordered_failure step_ordered_failure_init (hd s) ->
lb_step_execution lb_step_ordered_failure s ->
always (now (event_step_star step_ordered_failure step_ordered_failure_init)) (map pt_map_onet_event s).
Proof.
apply: pt_map_onet_hd_step_ordered_failure_star_always.
exact: FR.Label_eq_dec.
Qed.
Lemma Tree_lb_step_ordered_failure_enabled_weak_fairness_pt_map_onet_eventually :
forall l, tot_map_label l <> FR.Tau ->
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
l_enabled lb_step_ordered_failure (tot_map_label l) (pt_map_onet_event (hd s)) ->
eventually (now (l_enabled lb_step_ordered_failure l)) s.
Proof.
case => //= dst src H_neq {H_neq}.
case => [[[failed net] l]] tr s H_exec H_fair H_en.
rewrite /l_enabled /enabled /= map_id in H_en.
break_exists.
destruct x as [failed' net'].
invcs H => //.
unfold id in *.
rewrite /runGenHandler /= in H7.
FR.net_handler_cases.
find_injection.
simpl in *.
move {H6}.
have H_in: In Fail (onwPackets net from to).
apply: in_pt_map_msgs_in_msg.
- by case => //; case.
- by eexists.
- by rewrite H4; left.
exact: Tree_Fail_in_eventually_enabled.
Qed.
Lemma Tree_pt_map_onet_tot_map_label_event_state_strong_local_fairness :
forall s, lb_step_execution lb_step_ordered_failure s ->
strong_local_fairness lb_step_ordered_failure label_silent s ->
strong_local_fairness lb_step_ordered_failure label_silent (map pt_map_onet_event s).
Proof.
apply: pt_map_onet_tot_map_label_event_strong_local_fairness.
- case; first by exists Tau.
move => dst src.
by exists (RecvFail dst src).
- move => l H_neq s H_exec H_fair.
find_apply_lem_hyp strong_local_fairness_weak.
exact: Tree_lb_step_ordered_failure_enabled_weak_fairness_pt_map_onet_eventually.
Qed.
Lemma Tree_has_fail_not_in_fail :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
forall src dst, ~ In dst (fst (evt_a (hd s))) ->
In Fail (onwPackets (snd (evt_a (hd s))) src dst) ->
eventually ((now (fun e => head (onwPackets (snd (evt_a e)) src dst) = Some Fail)) /\_
(always (now (fun e => ~ In Fail (List.tl (onwPackets (snd (evt_a e)) src dst)))))) s.
Proof.
Admitted.
Lemma Tree_pt_map_onet_always_enabled_continuously :
forall l : label,
tot_map_label l <> label_silent ->
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
always (now (l_enabled lb_step_ordered_failure (tot_map_label l))) (map pt_map_onet_event s) ->
continuously (now (l_enabled lb_step_ordered_failure l)) s.
Proof.
case => //= src dst H_neq.
case; case; case => /= failed net l tr s H_exec H_fair H_al.
find_rewrite_lem map_Cons.
find_apply_lem_hyp always_Cons.
break_and.
rewrite /= /l_enabled /enabled /= map_id /id in H.
break_exists_name a.
break_exists_name tr'.
destruct a as [failed' net'].
invcs H; last by FR.io_handler_cases.
unfold id in *.
FR.net_handler_cases => //.
simpl in *.
find_injection.
move: H5.
set ptm := pt_map_msgs _.
move => H_eq_pt.
have H_in_pt: In FR.Fail ptm by find_rewrite; left.
have H_in: In Fail (onwPackets net from to).
move: H_in_pt.
apply: in_pt_map_msgs_in_msg => //.
by case => //=; case.
unfold ptm in *.
move {ptm H_in_pt}.
have H_ev := Tree_has_fail_not_in_fail H_exec H_fair _ _ H6 H_in.
elim: H_ev H0 H_exec; clearall => //=.
- by admit.
- by admit.
(* have H_ev := Tree_msg_in_eventually_first H_exec H_fair _ _ H6 _ H_in.
have H_al := Tree_not_in_failed_always H_exec to H6.
simpl in *.
find_apply_lem_hyp always_invar.
move {H_fair H7 H_in H6}. *)
Admitted.
Lemma Tree_pt_map_onet_tot_map_label_event_state_weak_local_fairness :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
weak_local_fairness lb_step_ordered_failure label_silent (map pt_map_onet_event s).
Proof.
move => s H_star H_exec H_fair.
apply: pt_map_onet_tot_map_label_event_state_weak_local_fairness => //.
- case; first by exists Tau.
move => dst src.
by exists (RecvFail dst src).
- exact: Tree_pt_map_onet_always_enabled_continuously.
Qed.
Lemma Tree_lb_step_ordered_failure_continuously_no_fail :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
forall src dst,
~ In dst (fst (hd s).(evt_a)) ->
continuously (now (fun e => ~ In Fail ((snd e.(evt_a)).(onwPackets) src dst))) s.
Proof.
move => s H_exec H_fair src dst H_in_f.
have H_exec_map := Tree_FailureRecorder_lb_step_execution_pt_map H_exec.
have H_w := Tree_pt_map_onet_tot_map_label_event_state_weak_local_fairness H_exec H_fair.
have H_map := FRC.Failure_lb_step_ordered_failure_continuously_no_fail H_exec_map H_w src dst.
move: H_map.
set ind := ~ In _ _.
move => H_map.
have H_ind: ind.
move => H_ind.
case: H_in_f.
destruct s as [e s].
simpl in *.
by rewrite map_id in H_ind.
concludes.
move: H_map.
apply continuously_map_conv.
- exact: extensional_now.
- exact: extensional_now.
- case => /= e s0.
rewrite /id /=.
move => H_in H_in'.
case: H_in.
move: H_in'.
exact: in_msg_pt_map_msgs.
Qed.
Lemma Tree_lb_step_ordered_failure_continuously_adj_not_failed :
forall s, event_step_star step_ordered_failure step_ordered_failure_init (hd s) ->
lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
forall n n',
~ In n (fst (hd s).(evt_a)) ->
continuously (now (fun e =>
NSet.In n' ((snd e.(evt_a)).(onwState) n).(adjacent) ->
~ In n' (fst e.(evt_a)) /\ adjacent_to n' n)) s.
Proof.
move => s H_star H_exec H_fair src dst H_in_f.
have H_exec_map := Tree_FailureRecorder_lb_step_execution_pt_map H_exec.
have H_w := Tree_pt_map_onet_tot_map_label_event_state_weak_local_fairness H_exec H_fair.
have H_map := FRC.Failure_lb_step_ordered_failure_continuously_adj_not_failed _ H_exec_map H_w src dst.
move: H_map.
set ind := ~ In _ _.
set eex := event_step_star _ _ _.
move => H_map.
have H_ind: ind.
move => H_ind.
case: H_in_f.
destruct s as [e s].
simpl in *.
by rewrite map_id in H_ind.
have H_eex: eex.
rewrite /eex.
destruct s as [e s].
exact: pt_map_onet_hd_step_ordered_failure_star.
concludes.
concludes.
move: H_map.
apply continuously_map_conv.
- exact: extensional_now.
- exact: extensional_now.
- case => /= e s0.
rewrite /id map_id /=.
move => H_in H_in'.
by concludes.
Qed.
Inductive root_path_length (failed : list name) : name -> nat -> Prop :=
| root_path_length_self : forall n,
~ In n failed ->
root n ->
root_path_length failed n 0
| root_path_length_proxy : forall n n' k,
root_path_length failed n k ->
~ In n' failed ->
adjacent_to n n' ->
root_path_length failed n' (S k).
Definition min_root_path_length (failed : list name) (n : name) (k : nat) : Prop :=
root_path_length failed n k /\ (forall k', root_path_length failed n k' -> k <= k').
Lemma root_path_length_exists_root :
forall failed n k,
root_path_length failed n k ->
exists r, ~ In r failed /\ root r.
Proof.
move => failed n k.
elim => //.
move => r H_in H_eq.
by exists r.
Qed.
Lemma root_path_length_not_failed :
forall failed n k,
root_path_length failed n k ->
~ In n failed.
Proof. by move => failed n k; case. Qed.
Lemma min_root_path_length_not_adjacent_plus_2 :
forall failed n k n' k',
min_root_path_length failed n k ->
min_root_path_length failed n' k' ->
k' >= S (S k) ->
~ adjacent_to n n'.
Proof.
move => failed n k n' k' H_min H_min' H_ge H_adj.
unfold min_root_path_length in *.
repeat break_and.
have H_r: root_path_length failed n' (S k).
apply: root_path_length_proxy; eauto.
by apply: root_path_length_not_failed; eauto.
have H_r' := H0 _ H_r.
by omega.
Qed.
End TreeCorrect.
|
////////////////////////////////////////////////////////////////////-
// Design unit: vm (All In One)
// :
// File name : vm.v
// :
// Description: RTL Design of Vending Machine
// :
// Limitations: None
// :
// System : Verilog
// :
// Author : 1. Wan Ahmad Zainie bin Wan Mohamad (ME131135)
// : [email protected]
// : 2. Azfar 'Aizat bin Mohd Isa (ME131032)
// : [email protected]
//
// Revision : Version 0.1 2014-06-01
// : Version 1.0 2014-06-09 Ready for submission
// : Version 2.0 2014-06-10 Change to behavioral
////////////////////////////////////////////////////////////////////-
module vm(clk, rst, deposit, deposited, select, selected, price, cancel, maintenance,
refund, refundall, depositall, product, change, state);
input clk, rst;
input [9:0] deposit, price;
input [4:0] select;
input deposited, selected, cancel, maintenance;
output refund, refundall, depositall;
output [4:0] product;
output [9:0] change;
output [2:0] state;
wire ldRdeposit, ldRselect, ldRprice, ldA, ldRproduct, ldRchange;
wire ldRpurchase, ldMprice, ldMquantity, clrRdeposit, clrRselect;
wire clrRprice, clrA, clrRproduct, clrRchange, clrRpurchase, purchase;
du myDU(clk, rst, deposit, select, price, ldRdeposit, ldRselect, ldRprice,
ldA, ldRproduct, ldRchange, ldRpurchase, ldMprice, ldMquantity,
clrRdeposit, clrRselect, clrRprice, clrA, clrRproduct, clrRchange,
clrRpurchase, purchase, refund, product, change);
cu myCU(clk, rst, deposited, selected, cancel, maintenance, purchase,
ldRdeposit, ldRselect, ldRprice, ldA, ldRproduct, ldRchange,
ldRpurchase, ldMprice, ldMquantity, clrRdeposit, clrRselect,
clrRprice, clrA, clrRproduct, clrRchange, clrRpurchase,
refundall, depositall, state);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:31:21 05/25/2015
// Design Name: CAN_BUS_Model
// Module Name: C:/Users/dagosttv.ROSE-HULMAN/Documents/School/ECE/ECE398/CAN-Bus-Controller-/CANIPCORETEST.v
// Project Name: CAN_Controller
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: CAN_BUS_Model
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CANIPCORETEST;
// Inputs
reg can_clk;
reg can_phy_rx;
reg bus2ip_reset;
reg bus2ip_rnw;
reg bus2ip_cs;
reg sys_clk;
reg [0:5] bus2ip_addr;
reg [0:31] bus2ip_data;
// Outputs
wire ip2bus_intrevent;
wire ip2bus_error;
wire ip2bus_ack;
wire can_phy_tx;
wire [0:31] ip2bus_data;
// Instantiate the Unit Under Test (UUT)
CAN_BUS_Model uut (
.can_phy_rx(can_phy_rx),
.can_clk(can_clk),
.bus2ip_reset(bus2ip_reset),
.ip2bus_intrevent(ip2bus_intrevent),
.bus2ip_rnw(bus2ip_rnw),
.bus2ip_cs(bus2ip_cs),
.ip2bus_error(ip2bus_error),
.sys_clk(sys_clk),
.ip2bus_ack(ip2bus_ack),
.can_phy_tx(can_phy_tx),
.ip2bus_data(ip2bus_data),
.bus2ip_addr(bus2ip_addr),
.bus2ip_data(bus2ip_data)
);
initial begin
// Initialize Inputs
can_clk = 0;
bus2ip_reset = 1;
bus2ip_rnw = 1;
bus2ip_cs = 0;
sys_clk = 0;
bus2ip_addr = 6'd3;
bus2ip_data = 32'd42;
can_phy_rx = 1;
// Wait 100 ns for global reset to finish
#100;
bus2ip_reset = 0;
#10;
bus2ip_data = 32'd42;
bus2ip_addr = 6'd3;
#10;
bus2ip_cs = 1;
bus2ip_rnw = 0;
#50
bus2ip_cs = 0;
bus2ip_rnw = 1;
// Add stimulus here
end
always #5 sys_clk=~sys_clk;
always #25 can_clk=~can_clk;
endmodule
|
/****************************************************************************************
*
* File Name: mobile_ddr.v
* Version: 6.05
* Model: BUS Functional
*
* Dependencies: mobile_ddr_parameters.vh
*
* Description: Micron MOBILE DDR SDRAM
*
* Limitation: - Doesn't check for 8K-cycle refresh
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set Debug = 0 to disable $display messages
* - Model assume Clk and Clk# crossing at both edge
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2008 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes
* --- ------ ---------- ---------------------------------------
* 1.0 NMB 03/19/02 - Initial Release of Mobile DDR model
* based off of version 5.0 of DDR model
* 1.1 ritz 12/03/04 - New feature: 1/8th strength driver in Drive Strength (Ext Mode Reg).
* Bugfix - ba[0] ba[1] were swapped for determening ext_mode_enable
* thus ext_mode_reg wasnt being programmed.
* 1.2 ritz 12/07/04 - Logging transactions in transcript for automated testing
* 1.3 ritz 01/31/05 - updated to SMG DDR model version 5.2 (dqs edge checking errors fix)
* 1.4 ritz 02/15/05 - Fixed display.*WRITE to use hex for "data".
* 1.5 ritz 03/22/05 - Fixed read latency (#0.5 and 2*Read_latency-1) for MMG latency
* 2.0 bas 07/19/06 - Added PASR support and clk_n checking
* 3.0 bas 08/07/06 - Added tXP check, tCke check, Power-down/Deep power down enter/exit messages
FULL_MEM fix
* 3.11 bas 10/18/06 - Added clk spd chk, added RP support, added T48M part, added SRR functionality, changed tMRD checker to measure in tck pos edge, DPD optimization for FULL_MEM mode
* 3.12 bas 10/19/06 - Fixed PASR in FULL_MEM mode
* 3.20 bas 10/23/06 - changed tXP check to tPDX check for T25L, Initial release to web
* 3.30 bas 01/15/07 - Updated T48M Parameters (updated as of 12/06)
* 3.35 bas 02/28/07 - Model uses tAC correctly to calculate strobe/data launch
* 3.36 bas 03/05/07 - fixed error messages for different banks interrupting
reads/writes w/autoprecharge
* 3.37 bas 03/21/07 - Added T47M Part to 512Mb parameter file
* 3.40 bas 06/25/07 - Removed RP options from 1024Mb
- Updated 128Mb, 256Mb, and 512Mb parts to 05/07 datasheet
- Updated 1024Mb part to 02/07
- Added illegal Cas Latency check per speed grade
* 3.40 jwm 08/02/07 - Support for 512Mb T47M
* 3.80 clk 10/29/07 - Support for 1024Mb T48M
* 4.00 clk 12/30/07 - Fixed Read terminated by precharge testcase
* 4.70 clk 03/30/08 - Fixed typo in SRR code
* 4.80 clk 04/03/08 - Disable clk checking during initialization
* 4.90 clk 04/16/08 - Fixed tInit, added mpc support, updated t35m timing
* 5.00 clk 05/14/08 - Fixed back to back auto precharge commands
* 5.20 clk 05/21/08 - Fixed read interrupt by pre (BL8), fixed 1024Mb parameter file
* 5.30 clk 05/22/08 - Fixed DM signal which cause false tWTR errors
05/27/08 - Rewrote write and read pipelines, strobes
* 5.40 clk 05/28/08 - Fixed Addressing problem in Burst Order logic
* 5.50 clk 07/25/08 - Added T36N part type
* 5.60 clk 09/05/08 - Fixed tXP in 256Mb part type
* 5.70 clk 09/17/08 - Fixed burst term check for write w/ all DM active
* 5.80 clk 11/18/08 - Fixed internally latched dq & mask widths
* 5.90 clk 12/10/08 - Updated T36N parameters to latest datasheet
* 6.00 clk 03/05/09 - Fixed DQS problem w/ CL = 2, Fix Wr Pipeline during Rd interrupt
* 6.01 sph 01/20/10 - Added clock stop detection to fix tCH/tCL timing violation
* 6.02 sph 01/22/10 - Added check for nop/des is used when enter/exit stop clock mode
* 6.03 sph 06/07/10 - Include all the mobile_ddr_parameters.vh into a single package
* 6.04 sph 07/19/10 - Fixed Write with auto precharge tRP calculation
* 6.05 sph 03/04/11 - Move function ceil into mobile_ddr.v
****************************************************************************************/
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
`timescale 1ns / 1ps
module mobile_ddr (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm);
`ifdef den128Mb
`include "128Mb_mobile_ddr_parameters.vh"
`elsif den256Mb
`include "256Mb_mobile_ddr_parameters.vh"
`elsif den512Mb
`include "512Mb_mobile_ddr_parameters.vh"
`elsif den1024Mb
`include "1024Mb_mobile_ddr_parameters.vh"
`elsif den2048Mb
`include "2048Mb_mobile_ddr_parameters.vh"
`else
// NOTE: Intentionally cause a compile fail here to force the users
// to select the correct component density before continuing
ERROR: You must specify component density with +define+den____Mb.
`endif
`define MAX_PIPE 2*(CL_MAX + BL_MAX)
// Port Declarations
input Clk;
input Clk_n;
input Cke;
input Cs_n;
input Ras_n;
input Cas_n;
input We_n;
input [ADDR_BITS - 1 : 0] Addr;
input [1 : 0] Ba;
inout [DQ_BITS - 1 : 0] Dq;
inout [DQS_BITS - 1 : 0] Dqs;
input [DM_BITS - 1 : 0] Dm;
//time variables
realtime tXP_chk ;
reg enter_DPD ;
reg enter_PD ;
reg enter_APD ;
//integer clk checks
// Internal Wires (fixed width)
wire [31 : 0] Dq_in;
wire [3 : 0] Dqs_in;
wire [3 : 0] Dm_in;
assign Dq_in [DQ_BITS - 1 : 0] = Dq;
assign Dqs_in [DQS_BITS - 1 : 0] = Dqs;
assign Dm_in [DM_BITS - 1 : 0] = Dm;
// Data pair
reg [DQ_BITS-1 : 0] dq_rise;
reg [DM_BITS-1 : 0] dm_rise;
reg [DQ_BITS-1 : 0] dq_fall;
reg [DM_BITS-1 : 0] dm_fall;
reg [DM_BITS*2-1 : 0] dm_pair;
reg [DQ_BITS-1 : 0] Dq_buf;
// Power-down cycle counter
reg [03:00] PD_cntr ;
// prev cmd value
reg prev_Cs_n ;
reg prev_Ras_n ;
reg prev_Cas_n ;
reg prev_We_n ;
reg [01:00] prev_Ba ;
reg prev_cke ;
wire prev_nop = ~prev_Cs_n & prev_Ras_n & prev_Cas_n & prev_We_n ;
wire prev_des = prev_Cs_n ;
wire prev_bt = ~prev_Cs_n & prev_Ras_n & prev_Cas_n & ~prev_We_n ;
wire prev_rd = ~prev_Cs_n & prev_Ras_n & ~prev_Cas_n & prev_We_n ;
reg Clk_Chk_enable = 1'b0 ;
//differential clk
reg diff_ck;
always @(posedge Clk) diff_ck <= Clk;
always @(posedge Clk_n) diff_ck <= ~Clk_n;
//measure clock period
realtime clk_period ;
realtime pos_clk_edge ;
integer clk_pos_edge_cnt ;
always @(posedge diff_ck) begin
clk_period = $realtime - pos_clk_edge ;
pos_clk_edge = $realtime ;
if ((Cke == 1'b1) && (clk_pos_edge_cnt < 2)) begin
clk_pos_edge_cnt = clk_pos_edge_cnt + 1 ;
end else if (Cke == 1'b0) begin
clk_pos_edge_cnt = 2'b00 ;
end
end
//measure duty cycle
realtime neg_clk_edge ;
always @(negedge diff_ck) begin
neg_clk_edge = $realtime ;
end
realtime pos_clk_time ;
realtime neg_clk_time ;
reg clock_stop = 0;
// Mode Register
reg [ADDR_BITS - 1 : 0] Mode_reg;
reg [ADDR_BITS - 1 : 0] Ext_Mode_reg;
reg [2*DQ_BITS - 1 : 0] Srr_reg;
// SRR Registers
reg SRR_read;
// Internal System Clock
reg CkeZ, Sys_clk;
// Internal Dqs initialize
// reg Dqs_int;
// Dqs buffer
reg Dqs_out;
// reg [DQS_BITS - 1 : 0] Dqs_gen;
reg Dqs_out_en;
// Dq buffer
reg [DQ_BITS - 1 : 0] Dq_out_temp;
reg [DQ_BITS - 1 : 0] Dq_out;
reg Dq_out_en;
// Read pipeline variables
reg [`MAX_PIPE : 0] Read_pipeline ;
reg [1 : 0] Read_bank [0 : 6];
reg [COL_BITS - 1 : 0] Read_cols [0 : 6];
// Write pipeline variables
reg [`MAX_PIPE :-2] Write_pipeline;
reg [BA_BITS-1 : 0] Write_bank_pipeline [`MAX_PIPE :-2];
reg [COL_BITS - 1 : 0] Write_col_pipeline [`MAX_PIPE :-2];
// Auto precharge variables
reg [3:0] Read_precharge_access ;
reg [3:0] Read_precharge_pre ;
reg [3:0] Write_precharge_access ;
reg [3:0] Write_precharge_pre ;
integer Count_precharge [0:3];
reg SelfRefresh;
reg [3:0] Read_precharge_count [3:0] ;
reg [3:0] Write_precharge_count [3:0];
reg wr_ap_display_msg ;
reg rd_ap_display_msg ;
// Manual precharge variables
// reg [0 : 6] A10_precharge ;
// reg [1 : 0] Bank_precharge [0 : 6];
// reg [0 : 6] Cmnd_precharge ;
// Burst terminate variables
// reg Cmnd_bst [0 : 6];
// tMRD counter
integer MRD_cntr ;
integer SRR_cntr ;
integer SRC_cntr ;
integer tWTR_cntr ;
// Memory Banks
`ifdef FULL_MEM
reg [DQ_BITS - 1 : 0] mem_array [0 : (1<<full_mem_bits)-1];
`else
reg [DQ_BITS - 1 : 0] mem_array [0 : (1<<part_mem_bits)-1];
reg [full_mem_bits - 1 : 0] addr_array [0 : (1<<part_mem_bits)-1];
reg [part_mem_bits : 0] mem_used;
reg [part_mem_bits : 0] memory_index;
initial mem_used = 0;
`endif
// Dqs edge checking
integer i;
reg [3:0] expect_pos_dqs;
reg [3:0] expect_neg_dqs;
// Burst counter
reg [COL_BITS - 1 : 0] Burst_counter;
// Burst counter delay
reg [COL_BITS - 1 : 0] Burst_counter_dly;
always @(Mode_reg or Burst_counter) begin
if (Mode_reg[6:4] == 3'b010) begin
// Burst_counter_dly <= #tAC2_max Burst_counter;
end else if (Mode_reg[6:4] == 3'b011) begin
// Burst_counter_dly <= #tAC3_max Burst_counter;
end
end
// Precharge variables
reg Pc_b0, Pc_b1, Pc_b2, Pc_b3;
// Activate variables
reg Act_b0, Act_b1, Act_b2, Act_b3;
// Data IO variables
// reg Data_in_enable;
wire Data_in_enable = Write_pipeline[-2];
// reg Data_out_enable;
wire Data_out_enable = Read_pipeline[0];
wire tWTR_en = ((|Write_pipeline[`MAX_PIPE : 0]) & ~(&Dm));
// Data Out Enable delay
// reg Data_out_enable_dly;
// always @(Mode_reg or Data_out_enable) begin
// if (Mode_reg[6:4] == 3'b010) begin
// Data_out_enable_dly <= #tAC2_max Data_out_enable;
// end else if (Mode_reg[6:4] == 3'b011) begin
// Data_out_enable_dly <= #tAC3_max Data_out_enable;
// end
// end
// Internal address mux variables
reg [1 : 0] Prev_bank;
reg [1 : 0] Bank_addr;
reg [COL_BITS - 1 : 0] Cols_addr, Cols_brst, Cols_temp;
reg [ADDR_BITS - 1 : 0] Rows_addr;
reg [ADDR_BITS - 1 : 0] B0_row_addr;
reg [ADDR_BITS - 1 : 0] B1_row_addr;
reg [ADDR_BITS - 1 : 0] B2_row_addr;
reg [ADDR_BITS - 1 : 0] B3_row_addr;
integer aref_count;
reg ext_mode_load_done;
reg mode_load_done;
reg power_up_done;
// Write DQS for tDSS , tDSH, tDQSH, tDQSL checks
wire wdqs_valid = Write_pipeline[`MAX_PIPE:0];
// Commands Decode
wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;
wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n & Cke;
wire Sref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n & ~Cke;
wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n;
wire Ext_mode_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & Ba[1] & ~Ba[0];
wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[1] & ~Ba[0];
wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n;
wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n;
wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n;
wire DPD_enable = ~Cs_n & Ras_n & Cas_n & ~We_n & ~Cke;
wire PD_enable = ((~Cs_n & Ras_n & Cas_n & We_n) | Cs_n) & ~Cke;
wire nop_enable = ~Cs_n & Ras_n & Cas_n & We_n ;
wire des_enable = Cs_n ;
wire srr_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[1] & Ba[0] & ((part_size==128)|(part_size==512)|(part_size==1024)) ;
reg Cke_Chk = 0 ;
parameter tInit = 200000 ;
reg Cke_Print = 1'b0 ;
real Init_Cmd_Chk ;
// Burst Length Decode
// reg [4:0] burst_length = 1 << (Mode_reg[2:0]);
reg [4:0] burst_length ;
reg read_precharge_truncation;
// CAS Latency Decode
wire [2:0] cas_latency = Mode_reg[6:4] ;
wire [2:0] cas_latency_x2 = ((2*Mode_reg[6:4])-1);
real tAC_max ;
always @ (Mode_reg)
begin
if (Mode_reg[6:4] == 3'b011)
tAC_max = tAC3_max ;
else if (Mode_reg[6:4] == 3'b010)
tAC_max = tAC2_max ;
end
// DQS Buffer
reg [DQS_BITS - 1 : 0] dqs_delayed ;
// always@* begin
// dqs_delayed <= Dqs_out ;
// end
assign Dqs = (Dqs_out_en) ? {DQS_BITS{Dqs_out}} : 'bz;
assign Dq = (Dq_out_en ) ? Dq_out : 'bz;
// Debug message
wire Debug = 1'b0;
// Timing Check
realtime MRD_chk;
realtime RFC_chk;
realtime RRD_chk;
realtime RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
realtime RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3;
realtime RC_chk0, RC_chk1, RC_chk2, RC_chk3;
realtime RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
realtime RP_chk0, RP_chk1, RP_chk2, RP_chk3;
realtime WR_chk0, WR_chk1, WR_chk2, WR_chk3;
realtime SRR_chk;
integer tWR_cycle;
//
reg [2:0] current_init_state ;
parameter [2:0] begin_init = 3'b000 ;
parameter [2:0] cke_init = 3'b001 ;
parameter [2:0] prech_init = 3'b010 ;
parameter [2:0] begin_mode_init = 3'b011 ;
parameter [2:0] mode_init = 3'b100 ;
parameter [2:0] ext_mode_init = 3'b101 ;
parameter [2:0] mode_done_init = 3'b110 ;
initial begin
CkeZ = 1'b0;
Sys_clk = 1'b0;
{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b1111;
// Dqs_int = 1'b0;
Dqs_out_en = {DQS_BITS{1'b0}};
Dqs_out = {DQS_BITS{1'bz}};
// Dqs_gen = {DQS_BITS{1'bz}};
Dq_out = {DQ_BITS{1'bz}};
Dq_out_en = {DQ_BITS{1'b0}};
// dq_delayed = {DQ_BITS{1'bz}};
// Data_in_enable = 1'b0;
// Data_out_enable = 1'b0;
aref_count = 0;
SelfRefresh = 1'b0;
power_up_done = 0;
ext_mode_load_done = 0;
mode_load_done = 0;
// MRD_chk = 0;
RFC_chk = 0;
RRD_chk = 0;
RAS_chk0 = 0;
RAS_chk1 = 0;
RAS_chk2 = 0;
RAS_chk3 = 0;
RAP_chk0 = 0;
RAP_chk1 = 0;
RAP_chk2 = 0;
RAP_chk3 = 0;
RC_chk0 = 0;
RC_chk1 = 0;
RC_chk2 = 0;
RC_chk3 = 0;
RCD_chk0 = 0;
RCD_chk1 = 0;
RCD_chk2 = 0;
RCD_chk3 = 0;
RP_chk0 = 0;
RP_chk1 = 0;
RP_chk2 = 0;
RP_chk3 = 0;
WR_chk0 = 0;
WR_chk1 = 0;
WR_chk2 = 0;
WR_chk3 = 0;
SRR_chk = 0;
$timeformat (-9, 3, " ns", 12);
pos_clk_time = 0;
neg_clk_time = 0;
enter_DPD = 0;
enter_PD = 0;
enter_APD = 0;
current_init_state = begin_init ;
SRR_read = 1'b0;
MRD_cntr = 8;
SRR_cntr = 8;
SRC_cntr = 8;
tWTR_cntr = 8;
Read_precharge_access[0] = 1'b0 ;
Read_precharge_access[1] = 1'b0 ;
Read_precharge_access[2] = 1'b0 ;
Read_precharge_access[3] = 1'b0 ;
Read_precharge_pre[0] = 1'b0 ;
Read_precharge_pre[1] = 1'b0 ;
Read_precharge_pre[2] = 1'b0 ;
Read_precharge_pre[3] = 1'b0 ;
Write_precharge_access[0] = 1'b0 ;
Write_precharge_access[1] = 1'b0 ;
Write_precharge_access[2] = 1'b0 ;
Write_precharge_access[3] = 1'b0 ;
Write_precharge_pre[0] = 1'b0 ;
Write_precharge_pre[1] = 1'b0 ;
Write_precharge_pre[2] = 1'b0 ;
Write_precharge_pre[3] = 1'b0 ;
wr_ap_display_msg = 1'b0 ;
rd_ap_display_msg = 1'b0 ;
Read_precharge_count[0] = 4'hf;
Read_precharge_count[1] = 4'hf;
Read_precharge_count[2] = 4'hf;
Read_precharge_count[3] = 4'hf;
Write_precharge_count[0] = 4'hf;
Write_precharge_count[1] = 4'hf;
Write_precharge_count[2] = 4'hf;
Write_precharge_count[3] = 4'hf;
end
function integer ceil;
input number;
real number;
if (number > $rtoi(number))
ceil = $rtoi(number) + 1;
else
ceil = number;
endfunction
// make sure 200 us has passed since cke for first command
always @ (Clk_Chk_enable or nop_enable or des_enable)
begin
if (~Clk_Chk_enable) begin
if (~nop_enable & ~des_enable) begin
Clk_Chk_enable = 1'b1 ;
if (~Cke_Chk) begin
if (($realtime - Init_Cmd_Chk < tInit - 0.001) & ~Cke_Print) begin
$display("Warning: You must wait 200 us from CKE assertion before you perform a command. Current wait time: %3.0f ns", $realtime - (Init_Cmd_Chk));
Cke_Print = 1'b1 ;
end
end
end
end
end
// Check for tCH, tCK, and clock stop mode
always @(diff_ck) begin
if (diff_ck) begin
neg_clk_time = $realtime - neg_clk_edge ;
end
if (~diff_ck) begin
pos_clk_time = $realtime - pos_clk_edge ;
end
if (Cke & Clk_Chk_enable) begin
// clock stop mode when either pulse width is 2x bigger than the other (reasonable assumption???)
clock_stop = ((pos_clk_time / neg_clk_time > 2) | (neg_clk_time / pos_clk_time > 2));
// Check if NOP/DES when enter/exit clock stop mode
if ((clock_stop && diff_ck) && (~(prev_nop || prev_des) || ~(nop_enable || des_enable))) begin
$display ("%m: at time %t ERROR: Nop or Deselect is required when enter or exit Stop Clock Mode", $time);
end
if ((pos_clk_time / clk_period < tCH_MIN) && ~clock_stop) begin
$display ("%m: at time %t ERROR: tCH minimum violation on CLK by %t", $time, tCH_MIN*clk_period - pos_clk_time);
end
if ((pos_clk_time / clk_period > tCH_MAX) && ~clock_stop) begin
$display ("%m: at time %t ERROR: tCH maximum violation on CLK by %t", $time, pos_clk_time - tCH_MAX*clk_period);
end
if ((neg_clk_time / clk_period < tCL_MIN) && ~clock_stop) begin
$display ("%m: at time %t ERROR: tCL minimum violation on CLK by %t", $time, tCL_MIN*clk_period - pos_clk_time);
end
if ((neg_clk_time / clk_period > tCL_MAX) && ~clock_stop) begin
$display ("%m: at time %t ERROR: tCL maximum violation on CLK by %t", $time, pos_clk_time - tCL_MAX*clk_period);
end
end
end
//clock Frequency Check
always @(posedge diff_ck) begin
if (clk_pos_edge_cnt > 1) begin
if (Mode_reg[6:4] == 3'b011) begin
if (clk_period < (tCK3_min-0.001)) begin
$display ("%m : at time %t ERROR : Illegal clk period for CAS Latency 3", $realtime);
$display ("%m : at time %t CLK PERIOD = %t", $realtime, clk_period);
end
end
if (Mode_reg[6:4] == 3'b010) begin
if (clk_period < (tCK2_min-0.001)) begin
$display ("%m : at time %t ERROR : Illegal clk period for CAS Latency 2", $realtime);
$display ("%m : at time %t CLK PERIOD = %t", $realtime, clk_period);
end
end
end
end
//SRR reg settings
always @(posedge power_up_done) begin
Srr_reg = 'b0 ;
Srr_reg[3:0] = 4'b1111 ; //Manufacturer(Micron)
Srr_reg[7:4] = 4'b0000 ; //Revision ID(Default to 0 in model)
Srr_reg[10:8] = 3'b100 ; //Refresh Rate(based on temp sensor - will default to 1x in model)
Srr_reg[11] = (DQ_BITS == 32)? 1'b1 : 1'b0 ; //Part width(x32 or x16)
Srr_reg[12] = 1'b0 ; //Device Type (LP DDR)
Srr_reg[15:13] = (part_size == 1024)? 3'b011 :
(part_size == 512 )? 3'b010 :
(part_size == 256 )? 3'b001 :
3'b000 ; //Density(1024Mb, 512Mb, 256Mb, 128Mb)
end
// System Clock
always begin
@ (posedge diff_ck) begin
Sys_clk = CkeZ;
CkeZ = Cke;
end
@ (negedge diff_ck) begin
Sys_clk = 1'b0;
end
end
task store_prev_cmd;
begin
prev_Cs_n <= Cs_n ;
prev_Ras_n <= Ras_n ;
prev_Cas_n <= Cas_n ;
prev_We_n <= We_n ;
prev_Ba[1] <= Ba[1] ;
prev_Ba[0] <= Ba[0] ;
prev_cke <= Cke ;
end
endtask
task MRD_counter;
begin
if (Cke) begin
if (MRD_cntr < tMRD) begin
MRD_cntr = MRD_cntr + 1'b1;
end
end
end
endtask
task SRR_counter;
begin
if (Cke) begin
if (SRR_cntr < tSRR) begin
SRR_cntr = SRR_cntr + 1'b1;
end
end
end
endtask
task SRC_counter;
begin
if (Cke) begin
if (SRC_cntr < ((Mode_reg[6:4])+1)) begin
SRC_cntr = SRC_cntr + 1'b1;
end
end
end
endtask
task tWTR_counter;
begin
if (Cke) begin
if (tWTR_en) begin
tWTR_cntr = 0 ;
end else begin
tWTR_cntr = tWTR_cntr + 1'b1;
end
end
end
endtask
task command_counter;
begin
if (Cke) begin
for (i=0; i<4;i=i+1) begin
if (Read_precharge_count[i] < 4'hf) begin
Read_precharge_count[i] = Read_precharge_count[i] + 1'b1;
end
end
for (i=0; i<4;i=i+1) begin
if (Write_precharge_count[i] < 4'hf) begin
Write_precharge_count[i] = Write_precharge_count[i] + 1'b1;
end
end
end
end
endtask
task PD_counter;
begin
if (~Cke) begin
if (PD_cntr < tCKE) begin
PD_cntr = PD_cntr + (enter_DPD | enter_PD | DPD_enable | PD_enable);
end
end else begin
PD_cntr = 4'h0 ;
end
end
endtask
task tXP_check;
begin
if (Cke == 1'b1 && prev_cke == 1'b0) begin
tXP_chk = $realtime ;
end
if (Cke) begin
if (~nop_enable && ~des_enable) begin
if ($realtime-tXP_chk < tXP - 0.001) begin
`ifdef T25L
$display ("%m: At time %t ERROR: tPDX violation", $realtime);
`else
$display ("%m: At time %t ERROR: tXP violation", $realtime);
`endif
end
end
end
end
endtask
// DPD pos edge clk cntr
always begin
@ (posedge diff_ck) begin
tXP_check ;
Power_down_chk ;
PD_counter ;
store_prev_cmd ;
end
end
// Check to make sure that we have a Deselect or NOP command on the bus when CKE is brought high
always @(Cke) begin
if (Cke === 1'b1) begin
Init_Cmd_Chk = $realtime ;
if (SelfRefresh === 1'b1) begin
SelfRefresh = 1'b0;
end
if (!((Cs_n) || (~Cs_n & Ras_n & Cas_n & We_n))) begin
$display ("%m: At time %t MEMORY ERROR: You must have a Deselect or NOP command applied", $realtime);
$display ("%m: when the Clock Enable is brought High.");
end
end
end
//BL Mode Reg settings
always@(Mode_reg[2:0] or mode_load_done) begin
if (mode_load_done) begin
case (Mode_reg[2:0])
3'b001 : burst_length = 5'b00010;
3'b010 : burst_length = 5'b00100;
3'b011 : burst_length = 5'b01000;
3'b100 : burst_length = 5'b10000;
default : burst_length = 5'bxxxxx;
endcase
end
end
// Init sequence
always @(current_init_state or Cke or Prech_enable or ext_mode_load_done or mode_load_done or aref_count) begin
if (current_init_state == begin_init) begin
if (Cke) begin
current_init_state = cke_init ;
power_up_done = 1'b0 ;
end
end
if (current_init_state == cke_init) begin
if (Prech_enable) begin
current_init_state = prech_init ;
aref_count = 0 ;
end
end
if (current_init_state == prech_init) begin
if (~Prech_enable) begin
current_init_state = begin_mode_init ;
end
end
if (current_init_state == begin_mode_init) begin
if (ext_mode_load_done) begin
current_init_state = ext_mode_init ;
end
if (mode_load_done) begin
current_init_state = mode_init ;
end
end
if (current_init_state == mode_init) begin
if (ext_mode_load_done) begin
current_init_state = mode_done_init ;
end
end
if (current_init_state == ext_mode_init) begin
if (mode_load_done) begin
current_init_state = mode_done_init ;
end
end
if (current_init_state == mode_done_init && aref_count >= 2) begin
power_up_done = 1'b1;
end
end
// this task will erase the contents of 0 or more banks
task erase_mem;
input [BA_BITS+1:0] bank_MSB_row; //bank bits + 2 row MSB
input DPD_mode ; //erase all memory locations
integer i;
begin
if (DPD_mode) begin
`ifdef FULL_MEM
for (i=0; i<{(BA_BITS+ROW_BITS+COL_BITS){1'b1}}; i=i+1) begin
mem_array[i] = 'bx;
end
`else
memory_index = 0;
i = 0;
// remove the selected banks
for (memory_index=0; memory_index<mem_used; memory_index=memory_index+1) begin
addr_array[i] = 'bx;
mem_array[i] = 'bx;
i = i + 1;
end
`endif
end else begin
`ifdef FULL_MEM
for (i={bank_MSB_row, {(ROW_BITS+COL_BITS-2){1'b1}}}; i<={1'b0, {(BA_BITS+ROW_BITS+COL_BITS){1'b1}}}; i=i+1) begin
mem_array[i] = 'bx;
end
`else
memory_index = 0;
i = 0;
// remove the selected banks
for (memory_index=0; memory_index<mem_used; memory_index=memory_index+1) begin
if (addr_array[memory_index]>({bank_MSB_row, {(ROW_BITS+COL_BITS-2){1'b1}}})) begin
addr_array[i] = 'bx;
mem_array[i] = 'bx;
i = i + 1;
end else begin
i = i + 1;
end
end
`endif
end
end
endtask
// Write Memory
task write_mem;
input [full_mem_bits - 1 : 0] addr;
input [DQ_BITS - 1 : 0] data;
reg [part_mem_bits : 0] i;
begin
`ifdef FULL_MEM
mem_array[addr] = data;
`else
begin : loop
for (i = 0; i < mem_used; i = i + 1) begin
if (addr_array[i] === addr) begin
disable loop;
end
end
end
if (i === mem_used) begin
if (i === (1<<part_mem_bits)) begin
$display ("%m: At time %t ERROR: Memory overflow.\n Write to Address %d with Data %d will be lost.\n You must increase the part_mem_bits parameter or `define FULL_MEM.", $realtime, addr, data);
end else begin
mem_used = mem_used + 1;
addr_array[i] = addr;
end
end
mem_array[i] = data;
`endif
end
endtask
// Read Memory
task read_mem;
input [full_mem_bits - 1 : 0] addr;
output [DQ_BITS - 1 : 0] data;
reg [part_mem_bits : 0] i;
begin
`ifdef FULL_MEM
data = mem_array[addr];
`else
begin : loop
for (i = 0; i < mem_used; i = i + 1) begin
if (addr_array[i] === addr) begin
disable loop;
end
end
end
if (i <= mem_used) begin
data = mem_array[i];
end else begin
data = 'bx;
end
`endif
end
endtask
// Burst Decode
task Burst_Decode;
begin
// Advance Burst Counter
// if (Burst_counter < burst_length) begin
if (Write_pipeline[-2]) begin
Burst_counter = Burst_counter + 1;
end
// Burst Type
if (Mode_reg[3] === 1'b0) begin // Sequential Burst
Cols_temp = Cols_addr + 1;
end else if (Mode_reg[3] === 1'b1) begin // Interleaved Burst
Cols_temp[2] = Burst_counter[2] ^ Cols_brst[2];
Cols_temp[1] = Burst_counter[1] ^ Cols_brst[1];
Cols_temp[0] = Burst_counter[0] ^ Cols_brst[0];
end
// Burst Length
if (burst_length === 2) begin
Cols_addr [0] = Cols_temp [0];
end else if (burst_length === 4) begin
Cols_addr [1 : 0] = Cols_temp [1 : 0];
end else if (burst_length === 8) begin
Cols_addr [2 : 0] = Cols_temp [2 : 0];
end else if (burst_length === 16) begin
Cols_addr [3 : 0] = Cols_temp [3 : 0];
end else begin
Cols_addr = Cols_temp;
end
// Data Counter
// if (Burst_counter >= burst_length) begin
// Data_in_enable = 1'b0;
// Data_out_enable = 1'b0;
// read_precharge_truncation = 1'b0;
// SRR_read = 1'b0;
// end
end
endtask
// SRC check
task Timing_chk_SRC;
begin
if (Active_enable || Aref_enable || Sref_enable || Burst_term ||
Ext_mode_enable || Mode_reg_enable || Prech_enable || Read_enable ||
Write_enable || DPD_enable || PD_enable || srr_enable) begin
if (part_size == 1024) begin
if (SRC_cntr < ((Mode_reg[6:4])+tSRC)) begin
$display ("%m: At time %t ERROR: tSRC Violation", $realtime);
end
end
end
end
endtask
task ShiftPipelines;
begin
// read command pipeline
Read_pipeline = Read_pipeline >> 1;
Write_pipeline = Write_pipeline >> 1;
for (i = -2; i < `MAX_PIPE-1; i = i + 1)
begin
Write_col_pipeline [i] = Write_col_pipeline[i+1];
Write_bank_pipeline [i] = Write_bank_pipeline[i+1];
end
end
endtask
// Dq and Dqs Drivers
task Dq_Dqs_Drivers;
begin
// Initialize Read command
if (Read_pipeline [0] === 1'b1) begin
// Data_out_enable = 1'b1;
Bank_addr = Write_bank_pipeline[0];
Cols_addr = Write_col_pipeline [0];
Cols_brst = Cols_addr [2 : 0];
// if (SRR_read == 1'b1) begin
// Burst_counter = burst_length - 2;
// end else begin
// Burst_counter = 0;
// end
// Row Address Mux
case (Bank_addr)
2'd0 : Rows_addr = B0_row_addr;
2'd1 : Rows_addr = B1_row_addr;
2'd2 : Rows_addr = B2_row_addr;
2'd3 : Rows_addr = B3_row_addr;
default : $display ("%m: At time %t ERROR: Invalid Bank Address", $realtime);
endcase
end
// Read latch
if (Read_pipeline[0] === 1'b1) begin
// output data
if (SRR_read == 1'b1) begin
if (Cols_addr == 0) begin
Dq_out_temp = Srr_reg[DQ_BITS-1:0];
end else begin
Dq_out_temp = Srr_reg[2*DQ_BITS-1:DQ_BITS];
SRR_read = 1'b0 ;
end
end else begin
read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_out_temp);
end
if (Debug) begin
$display ("At time %t %m:READ: Bank = %d, Row = %d, Col = %d, Data = %h", $realtime, Bank_addr, Rows_addr, Cols_addr, Dq_out_temp);
end
end
Dq_out <= #(tAC_max) Dq_out_temp ;
Dqs_out <= #(tAC_max) ((|Read_pipeline[0]) & Sys_clk) ;
if (cas_latency == 3)
Dqs_out_en <= #(tAC_max) (|Read_pipeline[2:0]);
else
Dqs_out_en <= #(tAC_max) (|Read_pipeline[1:0]);
if (Sys_clk) begin
Dq_out_en <= #(tAC_max) (Read_pipeline[0]);
end
end
endtask
// Write FIFO and DM Mask Logic
task Write_FIFO_DM_Mask_Logic;
begin
// Initialize Write command
if (Write_pipeline [-2] === 1'b1) begin
// Data_in_enable = 1'b1;
Bank_addr = Write_bank_pipeline [-2];
Cols_addr = Write_col_pipeline [-2];
Cols_brst = Cols_addr [2 : 0];
// Burst_counter = 0;
// Row address mux
case (Bank_addr)
2'd0 : Rows_addr = B0_row_addr;
2'd1 : Rows_addr = B1_row_addr;
2'd2 : Rows_addr = B2_row_addr;
2'd3 : Rows_addr = B3_row_addr;
default : $display ("%m: At time %t ERROR: Invalid Row Address", $realtime);
endcase
end
// Write data
// if (Data_in_enable === 1'b1) begin
if (Write_pipeline[-2] === 1'b1) begin
// Data Buffer
read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
// write negedge Dqs on posedge Sys_clk
if (Sys_clk) begin
if (!dm_fall[0]) begin
Dq_buf [ 7 : 0] = dq_fall [ 7 : 0];
end
if (!dm_fall[1]) begin
Dq_buf [15 : 8] = dq_fall [15 : 8];
end
`ifdef x32
if (!dm_fall[2]) begin
Dq_buf [23 : 16] = dq_fall [23 : 16];
end
if (!dm_fall[3]) begin
Dq_buf [31 : 24] = dq_fall [31 : 24];
end
`endif
if (~&dm_fall) begin
if (Debug) begin
$display ("At time %t %m:WRITE: Bank = %d, Row = %d, Col = %d, Data = %h", $realtime, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
end
end
// write posedge Dqs on negedge Sys_clk
end else begin
if (!dm_rise[0]) begin
Dq_buf [ 7 : 0] = dq_rise [ 7 : 0];
end
if (!dm_rise[1]) begin
Dq_buf [15 : 8] = dq_rise [15 : 8];
end
`ifdef x32
if (!dm_rise[2]) begin
Dq_buf [23 : 16] = dq_rise [23 : 16];
end
if (!dm_rise[3]) begin
Dq_buf [31 : 24] = dq_rise [31 : 24];
end
`endif
if (~&dm_rise) begin
if (Debug) begin
$display ("At time %t %m:WRITE: Bank = %d, Row = %d, Col = %d, Data = %h", $realtime, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
end
end
end
// Write Data
write_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
// tWR start and tWTR check
if (Sys_clk && &dm_pair === 1'b0) begin
case (Bank_addr)
2'd0 : WR_chk0 = $realtime;
2'd1 : WR_chk1 = $realtime;
2'd2 : WR_chk2 = $realtime;
2'd3 : WR_chk3 = $realtime;
default : $display ("%m: At time %t ERROR: Invalid Bank Address (tWR)", $realtime);
endcase
// // tWTR check
// if (Read_enable === 1'b1) begin
// $display ("%m: At time %t ERROR: tWTR violation during Read", $realtime);
// end
end
end
end
endtask
// Auto Precharge Calculation
task Auto_Precharge_Calculation;
begin
// Precharge counter
if (Read_precharge_access [0] === 1'b1 || Write_precharge_access [0] === 1'b1) begin
Count_precharge [0] = Count_precharge [0] + 1;
end
if (Read_precharge_access [1] === 1'b1 || Write_precharge_access [1] === 1'b1) begin
Count_precharge [1] = Count_precharge [1] + 1;
end
if (Read_precharge_access [2] === 1'b1 || Write_precharge_access [2] === 1'b1) begin
Count_precharge [2] = Count_precharge [2] + 1;
end
if (Read_precharge_access [3] === 1'b1 || Write_precharge_access [3] === 1'b1) begin
Count_precharge [3] = Count_precharge [3] + 1;
end
// Read with AutoPrecharge Calculation
// The device start internal precharge when:
// 1. BL/2 cycles after command
// 2. Meet tRAS requirement
if (Read_precharge_access[0] & (Count_precharge[0] >= burst_length/2)) begin
Read_precharge_access[0] = 1'b0 ;
Read_precharge_pre[0] = 1'b1 ;
end
if ((Read_precharge_pre[0] === 1'b1) && ($realtime - RAS_chk0 >= tRAS - 0.001)) begin
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $realtime;
Read_precharge_pre[0] = 1'b0;
end
if (Read_precharge_access[1] & (Count_precharge[1] >= burst_length/2)) begin
Read_precharge_access[1] = 1'b0 ;
Read_precharge_pre[1] = 1'b1 ;
end
if ((Read_precharge_pre[1] === 1'b1) && ($realtime - RAS_chk1 >= tRAS - 0.001)) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $realtime;
Read_precharge_pre[1] = 1'b0;
end
if (Read_precharge_access[2] & (Count_precharge[2] >= burst_length/2)) begin
Read_precharge_access[2] = 1'b0 ;
Read_precharge_pre[2] = 1'b1 ;
end
if ((Read_precharge_pre[2] === 1'b1) && ($realtime - RAS_chk2 >= tRAS - 0.001)) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $realtime;
Read_precharge_pre[2] = 1'b0;
end
if (Read_precharge_access[3] & (Count_precharge[3] >= burst_length/2)) begin
Read_precharge_access[3] = 1'b0 ;
Read_precharge_pre[3] = 1'b1 ;
end
if ((Read_precharge_pre[3] === 1'b1) && ($realtime - RAS_chk3 >= tRAS - 0.001)) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $realtime;
Read_precharge_pre[3] = 1'b0;
end
// Write with AutoPrecharge Calculation
// The device start internal precharge when:
// 1. Meet tWR requirement
// 2. Meet tRAS requirement
//
// tWR is time base and should be round up to the next integer
// For example, tWR = 15 ns, tCK = 5.4 ns, then
// tWR cycle = tWR / tCK = 15 / 5.4 = 3 (2.7 round up)
tWR_cycle = ceil(tWR / clk_period); // Using ceil for round up to next integer
if (Write_precharge_access[0] & (Count_precharge[0] >= (burst_length / 2 + 1) + tWR_cycle)) begin
Write_precharge_access[0] = 1'b0 ;
Write_precharge_pre[0] = 1'b1 ;
end
if (Write_precharge_pre[0] & ($realtime - RAS_chk0 >= tRAS - 0.001)) begin
Write_precharge_pre[0] = 1'b0;
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $realtime;
end
if (Write_precharge_access[1] & (Count_precharge[1] >= (burst_length / 2 + 1) + tWR_cycle)) begin
Write_precharge_access[1] = 1'b0 ;
Write_precharge_pre[1] = 1'b1 ;
end
if (Write_precharge_pre[1] & ($realtime - RAS_chk1 >= tRAS - 0.001)) begin
Write_precharge_pre[1] = 1'b0;
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $realtime;
end
if (Write_precharge_access[2] & (Count_precharge[2] >= (burst_length / 2 + 1) + tWR_cycle)) begin
Write_precharge_access[2] = 1'b0 ;
Write_precharge_pre[2] = 1'b1 ;
end
if (Write_precharge_pre[2] & ($realtime - RAS_chk2 >= tRAS - 0.001)) begin
Write_precharge_pre[2] = 1'b0;
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $realtime;
end
if (Write_precharge_access[3] & (Count_precharge[3] >= (burst_length / 2 + 1) + tWR_cycle)) begin
Write_precharge_access[3] = 1'b0 ;
Write_precharge_pre[3] = 1'b1 ;
end
if (Write_precharge_pre[3] & ($realtime - RAS_chk3 >= tRAS - 0.001)) begin
Write_precharge_pre[3] = 1'b0;
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $realtime;
end
end
endtask
task Power_down_chk;
begin
if (DPD_enable == 1'b1 && enter_DPD == 1'b0) begin
if (prev_cke & Pc_b0 & Pc_b1 & Pc_b2 & Pc_b3) begin
erase_mem(4'b0000, 1'b1);
current_init_state = begin_init ;
ext_mode_load_done = 1'b0 ;
mode_load_done = 1'b0 ;
enter_DPD = 1'b1;
$display ("%m: at time %t Entering Deep Power-Down Mode", $realtime);
end
end
if (enter_DPD == 1'b1) begin
if (Cke == 1'b1 && prev_cke == 1'b0) begin
if (PD_cntr < tCKE) begin
$display ("%m: At time %t ERROR: tCKE violation during exiting of Deep Power-Down Mode", $realtime);
end
$display ("%m: at time %t Exiting Deep Power-Down Mode - A 200 us delay is required with either DESELECT or NOP commands present before the initialization sequence may begin", $realtime);
enter_DPD = 1'b0;
end
end
if (PD_enable == 1'b1 && enter_PD == 1'b0) begin
if (prev_cke) begin
if (Pc_b0 & Pc_b1 & Pc_b2 & Pc_b3) begin
$display ("%m: at time %t Entering Power-Down Mode", $realtime);
enter_PD = 1'b1;
end else if (~Pc_b0 | ~Pc_b1 | ~Pc_b2 | ~Pc_b3) begin
$display ("%m: at time %t Entering Active Power-Down Mode", $realtime);
enter_APD = 1'b1;
end
end
end
if (enter_PD == 1'b1 || enter_APD == 1'b1) begin
if (Cke == 1'b1 && prev_cke == 1'b0) begin
if (PD_cntr < tCKE) begin
if (enter_PD == 1'b1) begin
$display ("%m: At time %t ERROR: tCKE violation during exiting of Power-Down Mode", $realtime);
end else if (enter_APD == 1'b1) begin
$display ("%m: At time %t ERROR: tCKE violation during exiting of Active Power-Down Mode", $realtime);
end
end
if (enter_PD == 1'b1) begin
$display ("%m: at time %t Exiting Power-Down Mode", $realtime);
enter_PD = 1'b0 ;
end else if (enter_APD == 1'b1) begin
$display ("%m: at time %t Exiting Active Power-Down Mode", $realtime);
enter_APD = 1'b0 ;
end
end
end
end
endtask
reg [31:0] xx ;
function [COL_BITS-1:0] Burst_Order;
input [COL_BITS-1:0] Col;
input [31:0] i;
begin
if (Mode_reg[3] == 1'b1) //interleaved
Burst_Order = (Col & -1*burst_length) + (Col%burst_length ^ i);
else // sequential
begin
xx = -1*burst_length;
Burst_Order = (Col & xx) + (Col%burst_length + i) % (burst_length);
end
end
endfunction
// Control Logic
task Control_Logic;
begin
// Self Refresh
if (Sref_enable === 1'b1) begin
// Partial Array Self Refresh
if (part_size == 128) begin
case (Ext_Mode_reg[2:0])
3'b000 : ;//keep Bank 0-7
3'b001 : begin $display("%m: at time %t INFO: Banks 2-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0111, 1'b0); end
3'b010 : begin $display("%m: at time %t INFO: Banks 1-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0011, 1'b0); end
3'b011 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end
3'b100 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end
3'b101 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end
3'b110 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end
endcase
end else begin
case (Ext_Mode_reg[2:0])
3'b000 : ;//keep Bank 0-7
3'b001 : begin $display("%m: at time %t INFO: Banks 2-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0111, 1'b0); end
3'b010 : begin $display("%m: at time %t INFO: Banks 1-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0011, 1'b0); end
3'b011 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end
3'b100 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end
3'b101 : begin $display("%m: at time %t INFO: Banks 1-3 and 1/2 of bank 0 will be lost due to Partial Array Self Refresh", $realtime); erase_mem(4'b0001, 1'b0); end
3'b110 : begin $display("%m: at time %t INFO: Banks 1-3 and 3/4 of bank 0 will be lost due to Partial Array Self Refresh", $realtime); erase_mem(4'b0000, 1'b0); end
endcase
end
SelfRefresh = 1'b1;
end
if (Aref_enable === 1'b1) begin
if (Debug) begin
$display ("Debug: At time %t %m:AUTOREFRESH: Auto Refresh", $realtime);
end
// aref_count is to make sure we have met part of the initialization sequence
if (~power_up_done) begin
aref_count = aref_count + 1;
end
// Auto Refresh to Auto Refresh
if ($realtime - RFC_chk < tRFC - 0.001) begin
$display ("%m: At time %t ERROR: tRFC violation during Auto Refresh", $realtime);
end
// Precharge to Auto Refresh
if (($realtime - RP_chk0 < tRP - 0.001) || ($realtime - RP_chk1 < tRP - 0.001) ||
($realtime - RP_chk2 < tRP - 0.001) || ($realtime - RP_chk3 < tRP - 0.001)) begin
$display ("%m: At time %t ERROR: tRP violation during Auto Refresh", $realtime);
end
// Precharge to Auto Refresh
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("%m: At time %t ERROR: All banks must be Precharged before Auto Refresh", $realtime);
end
// Record Current tRFC time
RFC_chk = $realtime;
end
// SRR Register
if (srr_enable == 1'b1) begin
if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1 &&
Data_out_enable === 1'b0 && Data_in_enable === 1'b0) begin
SRR_read = 1'b1;
SRR_chk = $realtime;
SRR_cntr = 0;
end
end
// Extended Mode Register
if (Ext_mode_enable == 1'b1) begin
if (Debug) begin
$display ("Debug: At time %t %m:EMR : Extended Mode Register", $realtime);
end
// Register Mode
Ext_Mode_reg = Addr;
if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1) begin
// ensure that power sequence is met properly
if (~power_up_done) begin
ext_mode_load_done = 1'b1;
end
$display ("At time %t %m:ELMR : Extended Load Mode Register", $realtime);
if (part_size == 128) begin
// Self Refresh Coverage
case (Addr[2 : 0])
3'b000 : $display ("%m : Self Refresh Cov = 4 banks");
3'b001 : $display ("%m : Self Refresh Cov = 2 banks");
3'b010 : $display ("%m : Self Refresh Cov = 1 bank");
3'b101 : $display ("%m : PASR = Reserved");
3'b110 : $display ("%m : PASR = Reserved");
default : $display ("%m : PASR = Reserved");
endcase
end else begin
// Self Refresh Coverage
case (Addr[2 : 0])
3'b000 : $display ("%m : Self Refresh Cov = 4 banks");
3'b001 : $display ("%m : Self Refresh Cov = 2 banks");
3'b010 : $display ("%m : Self Refresh Cov = 1 bank");
3'b101 : $display ("%m : Self Refresh Cov = 1/2 bank");
3'b110 : $display ("%m : Self Refresh Cov = 1/4 bank");
default : $display ("%m : PASR = Reserved");
endcase
end
// Maximum Case Temp
// case (Addr[4 : 3])
// 2'b11 : $display ("%m : Maximum Case Temp = 85C");
// 2'b00 : $display ("%m : Maximum Case Temp = 70C");
// 2'b01 : $display ("%m : Maximum Case Temp = 45C");
// 2'b10 : $display ("%m : Maximum Case Temp = 15C");
// endcase
// Drive Strength
case (Addr[7 : 5])
3'b000 : $display ("%m : Drive Strength = Full Strength");
3'b001 : $display ("%m : Drive Strength = Half Strength");
3'b010 : $display ("%m : Drive Strength = Quarter Strength");
3'b011 : $display ("%m : Drive Strength = Three Quarter Strength");
3'b100 : $display ("%m : Drive Strength = Three Quarter Strength");
endcase
end else begin
$display ("%m: At time %t ERROR: all banks must be Precharged before Extended Mode Register", $realtime);
end
// Precharge to EMR
if (($realtime - RP_chk0 < tRP - 0.001) || ($realtime - RP_chk1 < tRP - 0.001) ||
($realtime - RP_chk2 < tRP - 0.001) || ($realtime - RP_chk3 < tRP - 0.001)) begin
$display ("%m: At time %t ERROR: tRP violation during Extended Mode Register", $realtime);
end
// LMR/EMR to LMR/EMR
// if ($realtime - MRD_chk < tMRD) begin
// $display ("%m: At time %t ERROR: tMRD violation during Extended Mode Register", $realtime);
// end
if (MRD_cntr < tMRD) begin
$display ("%m: At time %t ERROR: tMRD violation during Extended Mode Register", $realtime);
end
// Record current tMRD time
// MRD_chk = $realtime;
MRD_cntr = 0;
end
// Load Mode Register
if (Mode_reg_enable === 1'b1) begin
if (Debug) begin
$display ("Debug: At time %t %m:LMR : Load Mode Register", $realtime);
end
// Register Mode
Mode_reg = Addr;
if (Mode_reg[6:4] == 3'b010) begin
if (tCK2_min == 0) begin
$display ("%m : at time %t ERROR : Illegal CAS Latency of 2 set for current speed grade", $realtime);
end
end
// Precharge to LMR
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("%m: At time %t ERROR: all banks must be Precharged before Load Mode Register", $realtime);
end
// Precharge to LMR
if (($realtime - RP_chk0 < tRP - 0.001) || ($realtime - RP_chk1 < tRP - 0.001) ||
($realtime - RP_chk2 < tRP - 0.001) || ($realtime - RP_chk3 < tRP - 0.001)) begin
$display ("%m: At time %t ERROR: tRP violation during Load Mode Register", $realtime);
end
// LMR/EMR to LMR/EMR
// if ($realtime - MRD_chk < tMRD) begin
// $display ("%m: At time %t ERROR: tMRD violation during Load Mode Register", $realtime);
// end
if (MRD_cntr < tMRD) begin
$display ("%m: At time %t ERROR: tMRD violation during Load Mode Register", $realtime);
end
if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1) begin
// ensure that power sequence is met properly
if (~power_up_done) begin
mode_load_done = 1'b1;
end
// Burst Length
case (Addr [2 : 0])
3'b001 : $display ("At time %t %m:LMR : Burst Length = 2", $realtime);
3'b010 : $display ("At time %t %m:LMR : Burst Length = 4", $realtime);
3'b011 : $display ("At time %t %m:LMR : Burst Length = 8", $realtime);
3'b100 : $display ("At time %t %m:LMR : Burst Length = 16",$realtime);
default :
begin
$display ("%m: At time %t ERROR: Undefined burst length selection", $realtime);
$stop;
end
endcase
// CAS Latency
case (Addr [6 : 4])
3'b010 : $display ("At time %t %m:LMR : CAS Latency = 2", $realtime);
3'b011 : $display ("At time %t %m:LMR : CAS Latency = 3", $realtime);
default : begin
$display ("%m: At time %t ERROR: CAS Latency not supported", $realtime);
$stop;
end
endcase
end
// Record current tMRD time
// MRD_chk = $realtime;
MRD_cntr = 0;
end
// Activate Block
if (Active_enable === 1'b1) begin
if (!(power_up_done)) begin
$display ("%m: At time %t ERROR: Power Up and Initialization Sequence not completed before executing Activate command", $realtime);
end
// Display Debug Message
if (Debug) begin
$display ("Debug: At time %t %m:ACTIVATE: Bank = %d, Row = %d", $realtime, Ba, Addr);
end
// Activating an open bank can cause corruption.
if ((Ba === 2'b00 && Pc_b0 === 1'b0) || (Ba === 2'b01 && Pc_b1 === 1'b0) ||
(Ba === 2'b10 && Pc_b2 === 1'b0) || (Ba === 2'b11 && Pc_b3 === 1'b0)) begin
$display ("%m: At time %t ERROR: Bank = %d is already activated - data can be corrupted", $realtime, Ba);
end
// Activate Bank 0
if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
// Activate to Activate (same bank)
if ($realtime - RC_chk0 < tRC - 0.001) begin
$display ("%m: At time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
end
// Precharge to Activate
if ($realtime - RP_chk0 < tRP - 0.001) begin
$display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
end
// Record variables for checking violation
Act_b0 = 1'b1;
Pc_b0 = 1'b0;
B0_row_addr = Addr;
RC_chk0 = $realtime;
RCD_chk0 = $realtime;
RAS_chk0 = $realtime;
RAP_chk0 = $realtime;
end
// Activate Bank 1
if (Ba === 2'b01 && Pc_b1 === 1'b1) begin
// Activate to Activate (same bank)
if ($realtime - RC_chk1 < tRC - 0.001) begin
$display ("%m: At time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
end
// Precharge to Activate
if ($realtime - RP_chk1 < tRP - 0.001) begin
$display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
end
// Record variables for checking violation
Act_b1 = 1'b1;
Pc_b1 = 1'b0;
B1_row_addr = Addr;
RC_chk1 = $realtime;
RCD_chk1 = $realtime;
RAS_chk1 = $realtime;
RAP_chk1 = $realtime;
end
// Activate Bank 2
if (Ba === 2'b10 && Pc_b2 === 1'b1) begin
// Activate to Activate (same bank)
if ($realtime - RC_chk2 < tRC - 0.001) begin
$display ("%m: At time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
end
// Precharge to Activate
if ($realtime - RP_chk2 < tRP - 0.001) begin
$display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
end
// Record variables for checking violation
Act_b2 = 1'b1;
Pc_b2 = 1'b0;
B2_row_addr = Addr;
RC_chk2 = $realtime;
RCD_chk2 = $realtime;
RAS_chk2 = $realtime;
RAP_chk2 = $realtime;
end
// Activate Bank 3
if (Ba === 2'b11 && Pc_b3 === 1'b1) begin
// Activate to Activate (same bank)
if ($realtime - RC_chk3 < tRC - 0.001) begin
$display ("%m: t time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
end
// Precharge to Activate
if ($realtime - RP_chk3 < tRP - 0.001) begin
$display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
end
// Record variables for checking violation
Act_b3 = 1'b1;
Pc_b3 = 1'b0;
B3_row_addr = Addr;
RC_chk3 = $realtime;
RCD_chk3 = $realtime;
RAS_chk3 = $realtime;
RAP_chk3 = $realtime;
end
// Activate to Activate (different bank)
if ((Prev_bank != Ba) && ($realtime - RRD_chk < tRRD - 0.001)) begin
$display ("%m: At time %t ERROR: tRRD violation during Activate bank = %d", $realtime, Ba);
end
// AutoRefresh to Activate
if ($realtime - RFC_chk < tRFC - 0.001) begin
$display ("%m: At time %t ERROR: tRFC violation during Activate bank %d", $realtime, Ba);
end
// Record variable for checking violation
RRD_chk = $realtime;
Prev_bank = Ba;
end
// Precharge Block - consider NOP if bank already precharged or in process of precharging
if (Prech_enable === 1'b1) begin
// Display Debug Message
if (Debug) begin
$display ("Debug: At time %t %m:PRE: Addr[10] = %b, Bank = %b", $realtime, Addr[10], Ba);
end
// EMR or LMR to Precharge
// if ($realtime - MRD_chk < tMRD) begin
// $display ("%m: At time %t ERROR: tMRD violation during Precharge", $realtime);
// end
if (MRD_cntr < tMRD) begin
$display ("%m: At time %t ERROR: tMRD violation during Precharge", $realtime);
end
// Precharge bank 0
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
Act_b0 = 1'b0;
Pc_b0 = 1'b1;
RP_chk0 = $realtime;
// Activate to Precharge Bank
if ($realtime - RAS_chk0 < tRAS - 0.001) begin
$display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime);
end
// tWR violation check for Write
if ($realtime - WR_chk0 < tWR - 0.001) begin
$display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime);
end
end
// Precharge bank 1
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
Act_b1 = 1'b0;
Pc_b1 = 1'b1;
RP_chk1 = $realtime;
// Activate to Precharge Bank 1
if ($realtime - RAS_chk1 < tRAS - 0.001) begin
$display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime);
end
// tWR violation check for Write
if ($realtime - WR_chk1 < tWR - 0.001) begin
$display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime);
end
end
// Precharge bank 2
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
Act_b2 = 1'b0;
Pc_b2 = 1'b1;
RP_chk2 = $realtime;
// Activate to Precharge Bank 2
if ($realtime - RAS_chk2 < tRAS - 0.001) begin
$display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime);
end
// tWR violation check for Write
if ($realtime - WR_chk2 < tWR - 0.001) begin
$display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime);
end
end
// Precharge bank 3
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
Act_b3 = 1'b0;
Pc_b3 = 1'b1;
RP_chk3 = $realtime;
// Activate to Precharge Bank 3
if ($realtime - RAS_chk3 < tRAS - 0.001) begin
$display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime);
end
// tWR violation check for Write
if ($realtime - WR_chk3 < tWR - 0.001) begin
$display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime);
end
end
// Pipeline for READ
if ((Addr[10] === 1'b1) | (Ba == Write_bank_pipeline[4]))
for (i = 4; i < `MAX_PIPE; i = i + 1)
Read_pipeline[i] = 1'b0 ;
end
// Burst terminate
if (Burst_term === 1'b1) begin
// Display Debug Message
if (Debug) begin
$display ("Debug: %m: At time %t BURST_TERMINATE): Burst Terminate",$realtime);
end
// Burst Terminate Command Pipeline for Read
for (i = cas_latency_x2-1; i < `MAX_PIPE; i = i + 1)
Read_pipeline[i] = 1'b0 ;
// Illegal to burst terminate a Write
if ((Data_in_enable === 1'b1) & ~((&dm_rise) & (&dm_fall))) begin
$display ("%m: At time %t ERROR: It's illegal to burst terminate a Write", $realtime);
end
// Illegal to burst terminate a Read with Auto Precharge
if (|Read_precharge_access) begin
$display ("%m: At time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $realtime);
end
end
// Read Command
if (Read_enable === 1'b1) begin
if (!(power_up_done)) begin
$display ("%m: At time %t ERROR: Power Up and Initialization Sequence not completed before executing Read Command", $realtime);
end
// Display Debug Message
if (Debug) begin
$display ("Debug: At time %t %m:READ: Bank = %d, Col = %d", $realtime, Ba, {Addr [11], Addr [9 : 0]});
end
if (part_size == 1024) begin
if (SRR_read == 1'b1) begin
if (SRR_cntr < tSRR) begin
$display ("%m: At time %t ERROR: tSRR Violation", $realtime);
end
SRC_cntr = 0 ;
end
end else begin
if (SRR_read == 1'b1) begin
if ($realtime - SRR_chk < tSRR-0.01) begin
$display ("%m: At time %t ERROR: tSRR Violation", $realtime);
end
SRC_cntr = 0;
end
end
// CAS Latency pipeline
if (SRR_read) begin
if ({Ba, Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]} > 0) begin
$display ("%m: At time %t ERROR: Address must be all 0 during SRR Read", $realtime);
end
for (i=0; i<2; i=i+1)
begin
Read_pipeline[cas_latency_x2 - 2 + i + 1] = 1'b1;
Write_col_pipeline [cas_latency_x2 - 2 + i + 1] = i;
Write_bank_pipeline [cas_latency_x2 - 2 + i + 1] = 0;
end
end else begin
for (i=0; i<burst_length; i=i+1)
begin
Read_pipeline[cas_latency_x2 - 2 + i + 1] = 1'b1;
Write_bank_pipeline [cas_latency_x2 - 2 + i + 1] = Ba;
Write_col_pipeline [cas_latency_x2 - 2 + i + 1] = Burst_Order({Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}, i);
end
end
// Clear out Write Pipeline
Write_pipeline = 64'b0;
// Interrupt a Read with Auto Precharge
if (Read_precharge_access [Ba] === 1'b1) begin
$display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge (same bank)", $realtime);
end else if ((Read_precharge_access [0] === 1'b1) |
(Read_precharge_access [1] === 1'b1) |
(Read_precharge_access [2] === 1'b1) |
(Read_precharge_access [3] === 1'b1) ) begin
$display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge (different banks)", $realtime);
end
// Interrupt a Write with Auto Precharge
if (Write_precharge_access [Ba] === 1'b1) begin
// $display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge (same banks)", $realtime);
end else if ((Write_precharge_count [0] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) |
(Write_precharge_count [1] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) |
(Write_precharge_count [2] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) |
(Write_precharge_count [3] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) |
(Write_precharge_count [0] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) |
(Write_precharge_count [1] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) |
(Write_precharge_count [2] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) |
(Write_precharge_count [3] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) ) begin
$display ("%m: At time %t ERROR: It's illegal to interrupt a data transfer on a Write with Auto Precharge (different banks)", $realtime);
end
// Activate to Read
if (((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
(Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) &&
(SRR_read == 1'b0)) begin
$display("%m: At time %t ERROR: Bank is not Activated for Read", $realtime);
end
// Activate to Read without Auto Precharge
if ((Addr [10] === 1'b0 && Ba === 2'b00 && $realtime - RCD_chk0 < tRCD - 0.001) ||
(Addr [10] === 1'b0 && Ba === 2'b01 && $realtime - RCD_chk1 < tRCD - 0.001) ||
(Addr [10] === 1'b0 && Ba === 2'b10 && $realtime - RCD_chk2 < tRCD - 0.001) ||
(Addr [10] === 1'b0 && Ba === 2'b11 && $realtime - RCD_chk3 < tRCD - 0.001)) begin
$display("%m: At time %t ERROR: tRCD violation during Read", $realtime);
end
// Auto Precharge
if (Addr[10] === 1'b1) begin
Read_precharge_access [Ba]= 1'b1;
Count_precharge [Ba]= 0;
Read_precharge_count[Ba] = 4'h0;
end
// tWTR
if (tWTR_cntr < tWTR - 0.001) begin
$display("%m: At time %t ERROR: tWTR violation during Read", $realtime);
end
end
// Write Command
if (Write_enable === 1'b1) begin
if (!(power_up_done)) begin
$display ("%m: At time %t ERROR: Power Up and Initialization Sequence not completed before executing Write Command", $realtime);
end
// display debug message
if (Debug) begin
$display ("Debug: At time %t %m:WRITE: Bank = %d, Col = %d", $realtime, Ba, {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]});
end
// Pipeline for Write
// Write_pipeline [3] = 1'b1;
for (i=0; i<burst_length; i=i+1)
begin
Write_pipeline[1 + i] = 1'b1;
// Write_col_pipeline [1 + i] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]} + i;
Write_col_pipeline [1 + i] = Burst_Order({Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}, i);
Write_bank_pipeline [1 + i] = Ba;
end
// Interrupt a Write with Auto Precharge (same bank only)
if (Write_precharge_access [Ba] === 1'b1) begin
$display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge", $realtime);
end
// Activate to Write
if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
(Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
$display("%m: At time %t ERROR: Bank is not Activated for Write", $realtime);
end
// Activate to Write
if ((Ba === 2'b00 && $realtime - RCD_chk0 < tRCD - 0.001) ||
(Ba === 2'b01 && $realtime - RCD_chk1 < tRCD - 0.001) ||
(Ba === 2'b10 && $realtime - RCD_chk2 < tRCD - 0.001) ||
(Ba === 2'b11 && $realtime - RCD_chk3 < tRCD - 0.001)) begin
$display("%m: At time %t ERROR: tRCD violation during Write to Bank %d", $realtime, Ba);
end
if (Read_pipeline[0]) begin
$display("%m: At time %t ERROR: Read to Write violation", $realtime);
end
// Interrupt a Write with Auto Precharge
if (Write_precharge_access [Ba] === 1'b1) begin
$display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge (same bank)", $realtime);
end else if (((Write_precharge_access [0] === 1'b1) & (Count_precharge[0] < (burst_length/2))) |
((Write_precharge_access [1] === 1'b1) & (Count_precharge[1] < (burst_length/2))) |
((Write_precharge_access [2] === 1'b1) & (Count_precharge[2] < (burst_length/2))) |
((Write_precharge_access [3] === 1'b1) & (Count_precharge[3] < (burst_length/2))) ) begin
$display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge (different bank)", $realtime);
end
// Interrupt a Read with Auto Precharge
if (((Read_precharge_count [Ba] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
((Read_precharge_count [Ba] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) ) begin
// $display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge (same bank)", $realtime);
end else if (((Read_precharge_count [0] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
((Read_precharge_count [1] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
((Read_precharge_count [2] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
((Read_precharge_count [3] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
((Read_precharge_count [0] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) |
((Read_precharge_count [1] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) |
((Read_precharge_count [2] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) |
((Read_precharge_count [3] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) ) begin
$display ("%m: At time %t ERROR: It's illegal to interrupt a data transfer on a Read with Auto Precharge (different bank)", $realtime);
end
// Auto Precharge
if (Addr[10] === 1'b1) begin
Write_precharge_access [Ba]= 1'b1;
Count_precharge [Ba]= 0;
Write_precharge_count[Ba] = 4'h0;
end
end
end
endtask
// Main Logic
always @ (posedge Sys_clk) begin
ShiftPipelines;
// Manual_Precharge_Pipeline;
// Burst_Terminate_Pipeline;
Dq_Dqs_Drivers;
Write_FIFO_DM_Mask_Logic;
Burst_Decode;
Auto_Precharge_Calculation;
Timing_chk_SRC;
Control_Logic;
MRD_counter;
SRR_counter;
SRC_counter;
tWTR_counter;
command_counter;
end
always @ (negedge Sys_clk) begin
ShiftPipelines;
// Manual_Precharge_Pipeline;
// Burst_Terminate_Pipeline;
Dq_Dqs_Drivers;
Write_FIFO_DM_Mask_Logic;
Burst_Decode;
end
// Dqs Receiver
always @ (posedge Dqs_in[0]) begin
// Latch data at posedge Dqs
dq_rise[7 : 0] = Dq_in[7 : 0];
dm_rise[0] = Dm_in[0];
expect_pos_dqs[0] = 0;
end
always @ (posedge Dqs_in[1]) begin
// Latch data at posedge Dqs
dq_rise[15 : 8] = Dq_in[15 : 8];
dm_rise[1] = Dm_in[1];
expect_pos_dqs[1] = 0;
end
`ifdef x32
always @ (posedge Dqs_in[2]) begin
// Latch data at posedge Dqs
dq_rise[23 : 16] = Dq_in[23 : 16];
dm_rise[2] = Dm_in[2];
expect_pos_dqs[2] = 0;
end
always @ (posedge Dqs_in[3]) begin
// Latch data at posedge Dqs
dq_rise[31 : 24] = Dq_in[31 : 24];
dm_rise[3] = Dm_in[3];
expect_pos_dqs[3] = 0;
end
`endif
always @ (negedge Dqs_in[0]) begin
// Latch data at negedge Dqs
dq_fall[7 : 0] = Dq_in[7 : 0];
dm_fall[0] = Dm_in[0];
dm_pair[1:0] = {dm_rise[0], dm_fall[0]};
expect_neg_dqs[0] = 0;
end
always @ (negedge Dqs_in[1]) begin
// Latch data at negedge Dqs
dq_fall[15: 8] = Dq_in[15 : 8];
dm_fall[1] = Dm_in[1];
dm_pair[3:2] = {dm_rise[1], dm_fall[1]};
expect_neg_dqs[1] = 0;
end
`ifdef x32
always @ (negedge Dqs_in[2]) begin
// Latch data at negedge Dqs
dq_fall[23: 16] = Dq_in[23 : 16];
dm_fall[2] = Dm_in[2];
dm_pair[5:4] = {dm_rise[2], dm_fall[2]};
expect_neg_dqs[2] = 0;
end
always @ (negedge Dqs_in[3]) begin
// Latch data at negedge Dqs
dq_fall[31: 24] = Dq_in[31 : 24];
dm_fall[3] = Dm_in[3];
dm_pair[7:6] = {dm_rise[3], dm_fall[3]};
expect_neg_dqs[3] = 0;
end
`endif
// Dqs edge checking
always @ (posedge Sys_clk) begin
// if (Write_pipeline[2] || Write_pipeline[1] || Data_in_enable) begin
if (Write_pipeline[-1]) begin
for (i=0; i<DQS_BITS; i=i+1) begin
if (expect_neg_dqs[i]) begin
$display ("%m: At time %t ERROR: Negative DQS[%1d] transition required.", $realtime, i);
end
expect_neg_dqs[i] = 1'b1;
end
end else begin
expect_neg_dqs = 0;
expect_pos_dqs = 0;
end
end
always @ (negedge Sys_clk) begin
// if (Write_pipeline[2] || Write_pipeline[1] || Data_in_enable) begin
if (Write_pipeline[-1]) begin
for (i=0; i<DQS_BITS; i=i+1) begin
if (expect_pos_dqs[i]) begin
$display ("%m: At time %t ERROR: Positive DQS[%1d] transition required.", $realtime, i);
end
expect_pos_dqs[i] = 1'b1;
end
end else begin
expect_neg_dqs = 0;
expect_pos_dqs = 0;
end
end
specify
// SYMBOL UNITS DESCRIPTION
// ------ ----- -----------
`ifdef sg5 // specparams for -6 (CL = 3)
specparam tCLK_MIN = 5.0 ; // tCLK ns minimum clk cycle time
specparam tDSS = 1.0 ; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.0 ; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.0 ; // tIH ns Input Hold Time (fast)
specparam tIS = 1.0 ; // tIS ns Input Setup Time (fast)
specparam tDQSH = 1.75; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 1.75; // tDQSL ns DQS input Low Pulse Width
`elsif sg54 // specparams for -6 (CL = 3)
specparam tCLK_MIN = 5.4; // tCLK ns minimum clk cycle time
specparam tDSS = 1.08; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.08; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.0; // tIH ns Input Hold Time (fast)
specparam tIS = 1.0; // tIS ns Input Setup Time (fast)
specparam tDQSH = 2.16; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 2.16; // tDQSL ns DQS input Low Pulse Width
`elsif sg6 // specparams for -6 (CL = 3)
specparam tCLK_MIN = 6.0; // tCLK ns minimum clk cycle time
specparam tDSS = 1.2; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.2; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.1; // tIH ns Input Hold Time (fast)
specparam tIS = 1.1; // tIS ns Input Setup Time (fast)
specparam tDQSH = 2.1; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 2.1; // tDQSL ns DQS input Low Pulse Width
`elsif sg75 // specparams for -75 (CL = 3)
specparam tCLK_MIN = 7.5; // tCLK ns minimum clk cycle time
specparam tDSS = 1.5; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.5; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.3; // tIH ns Input Hold Time (fast)
specparam tIS = 1.3; // tIS ns Input Setup Time (fast)
specparam tDQSH = 3.0; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 3.0; // tDQSL ns DQS input Low Pulse Width
`elsif sg5v18 // specparams for -6 (CL = 3)
specparam tCLK_MIN = 5.0 ; // tCLK ns minimum clk cycle time
specparam tDSS = 1.0 ; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.0 ; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 0.9 ; // tIH ns Input Hold Time (fast)
specparam tIS = 0.9 ; // tIS ns Input Setup Time (fast)
specparam tDQSH = 2.0 ; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 2.0 ; // tDQSL ns DQS input Low Pulse Width
`elsif sg6v18 // specparams for -6 (CL = 3)
specparam tCLK_MIN = 6.0; // tCLK ns minimum clk cycle time
specparam tDSS = 1.2; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.2; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.1; // tIH ns Input Hold Time (fast)
specparam tIS = 1.1; // tIS ns Input Setup Time (fast)
specparam tDQSH = 2.4; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 2.4; // tDQSL ns DQS input Low Pulse Width
`elsif sg75v18 // specparams for -75 (CL = 3)
specparam tCLK_MIN = 7.5; // tCLK ns minimum clk cycle time
specparam tDSS = 1.5; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.5; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.3; // tIH ns Input Hold Time (fast)
specparam tIS = 1.3; // tIS ns Input Setup Time (fast)
specparam tDQSH = 3.0; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 3.0; // tDQSL ns DQS input Low Pulse Width
`elsif sg6v12 // specparams for -6 (CL = 3)
specparam tCLK_MIN = 6.0; // tCLK ns minimum clk cycle time
specparam tDSS = 1.2; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.2; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.1; // tIH ns Input Hold Time (fast)
specparam tIS = 1.1; // tIS ns Input Setup Time (fast)
specparam tDQSH = 2.1; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 2.1; // tDQSL ns DQS input Low Pulse Width
`elsif sg75v12 // specparams for -75 (CL = 3)
specparam tCLK_MIN = 7.5; // tCLK ns minimum clk cycle time
specparam tDSS = 1.5; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.5; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.3; // tIH ns Input Hold Time (fast)
specparam tIS = 1.3; // tIS ns Input Setup Time (fast)
specparam tDQSH = 3.0; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 3.0; // tDQSL ns DQS input Low Pulse Width
`elsif sg10v12 // specparams for -10 (CL = 3)
specparam tCLK_MIN = 9.6; // tCLK ns minimum clk cycle time
specparam tDSS = 1.92; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.92; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.7; // tIH ns Input Hold Time (fast)
specparam tIS = 1.7; // tIS ns Input Setup Time (fast)
specparam tDQSH = 3.84; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 3.84; // tDQSL ns DQS input Low Pulse Width
`else `define sg10 // specparams for -10 (CL = 3)
specparam tCLK_MIN = 9.6; // tCLK ns minimum clk cycle time
specparam tDSS = 1.92; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.92; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.5; // tIH ns Input Hold Time (fast)
specparam tIS = 1.5; // tIS ns Input Setup Time (fast)
specparam tDQSH = 3.84; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 3.84; // tDQSL ns DQS input Low Pulse Width
`endif
$period (posedge Clk, tCLK_MIN);
$width (posedge Dqs_in[0] &&& wdqs_valid, tDQSH);
$width (posedge Dqs_in[1] &&& wdqs_valid, tDQSH);
$width (negedge Dqs_in[0] &&& wdqs_valid, tDQSL);
$width (negedge Dqs_in[1] &&& wdqs_valid, tDQSL);
$setuphold(posedge Clk, Cke, tIS, tIH);
$setuphold(posedge Clk, Cs_n, tIS, tIH);
$setuphold(posedge Clk, Cas_n, tIS, tIH);
$setuphold(posedge Clk, Ras_n, tIS, tIH);
$setuphold(posedge Clk, We_n, tIS, tIH);
$setuphold(posedge Clk, Addr, tIS, tIH);
$setuphold(posedge Clk, Ba, tIS, tIH);
$setuphold(posedge Clk, negedge Dqs &&& wdqs_valid, tDSS , tDSH);
endspecify
endmodule
|
//wb_seeed_tft.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Self Defining Bus (SDB)
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x00000008
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: (19 UNICODE characters)
SDB_NAME:wb_seeed_tft
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x10
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:3
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/01/07
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:8
*/
`define DEFAULT_MEMORY_TIMEOUT 300
`include "project_defines.v"
`include "seeed_tft_defines.v"
//Configure command register size to be 8 bit: 0 or 16bit: 1
`define CONTROL_ENABLE 0
`define CONTROL_ENABLE_INTERRUPT 1
`define CONTROL_BACKLIGHT_ENABLE 2
`define CONTROL_RESET_DISPLAY 3
`define CONTROL_COMMAND_MODE 4
`define CONTROL_COMMAND_WRITE 5
`define CONTROL_COMMAND_READ 6
`define CONTROL_COMMAND_RS 7
`define CONTROL_CHIP_SELECT 8
`define CONTROL_ENABLE_TEARING 9
`define CONTROL_SOFT_TEAR 10
`define CONTROL_TEAR_POLARITY 11
//status bit definition
`define STATUS_MEMORY_0_EMPTY 0
`define STATUS_MEMORY_1_EMPTY 1
module wb_seeed_tft #(
parameter BUFFER_SIZE = 12
)(
input clk,
input rst,
output [31:0] debug,
//wishbone slave signals
input i_wbs_we,
input i_wbs_stb,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_adr,
input [31:0] i_wbs_dat,
output reg [31:0] o_wbs_dat,
output reg o_wbs_ack,
output reg o_wbs_int,
//master control signal for memory arbitration
output mem_o_we,
output mem_o_stb,
output mem_o_cyc,
output [3:0] mem_o_sel,
output [31:0] mem_o_adr,
output [31:0] mem_o_dat,
input [31:0] mem_i_dat,
input mem_i_ack,
input mem_i_int,
output o_backlight_enable,
output o_register_data_sel,
output o_write_n,
output o_read_n,
inout [7:0] io_data,
output o_cs_n,
output o_reset_n,
input i_tearing_effect,
output o_display_on
);
//Local Parameters
localparam REG_CONTROL = 32'h00000000;
localparam REG_STATUS = 32'h00000001;
localparam REG_COMMAND_DATA = 32'h00000002;
localparam REG_PIXEL_COUNT = 32'h00000003;
localparam REG_MEM_0_BASE = 32'h00000004;
localparam REG_MEM_0_SIZE = 32'h00000005;
localparam REG_MEM_1_BASE = 32'h00000006;
localparam REG_MEM_1_SIZE = 32'h00000007;
//What command needs to be send to start sending data
localparam REG_DATA_ADDRESS = 32'h00000008;
//What the address of tearing data to find
localparam REG_TEAR_ADDRESS = 32'h00000009;
//if this value is 'anded with the tearing result then we have vsync
localparam REG_TEAR_COUNT = 32'h0000000A;
localparam REG_TEAR_VALUE = 32'h0000000B;
//Reg/Wire
wire timeout_elapsed;
reg timeout_enable;
reg [31:0] timeout_count;
reg [31:0] timeout_value;
reg enable_mem_read;
reg memory_data_strobe;
reg enable_strobe;
wire [31:0] status;
reg [31:0] clock_divider = 1;
reg [31:0] control;
reg [7:0] r_tearing_reg;
reg [31:0] r_tearing_value;
reg [31:0] r_tearing_count;
wire w_tearing_polarity;
reg [7:0] r_mem_write_cmd;
reg [23:0] request_count;
reg memory_ready;
reg active_bank;
//Mem 2 PPFIFO
reg [31:0] r_memory_0_base;
reg [31:0] r_memory_0_size;
wire [31:0] w_memory_0_count;
reg r_memory_0_new_data;
wire w_memory_0_empty;
wire [31:0] w_default_mem_0_base;
reg [31:0] r_memory_1_base;
reg [31:0] r_memory_1_size;
wire [31:0] w_memory_1_count;
reg r_memory_1_new_data;
wire w_memory_1_empty;
wire [31:0] w_default_mem_1_base;
wire w_read_finished;
//Configuration
wire w_soft_tearing;
//control
wire w_enable;
wire w_enable_interrupt;
wire w_reset_display;
wire w_command_mode;
wire w_backlight_enable;
wire w_cmd_write_stb;
wire w_cmd_read_stb;
wire w_cmd_rs;
wire w_chip_select;
wire w_enable_tearing;
wire w_cmd_finished;
reg [7:0] r_cmd_data_out;
wire [7:0] w_cmd_data_in;
reg [31:0] r_num_pixels;
//status
wire [23:0] wfifo_size;
wire [1:0] wfifo_ready;
wire [1:0] wfifo_activate;
wire wfifo_strobe;
wire [31:0] wfifo_data;
reg [3:0] state;
seeed_tft #(
.BUFFER_SIZE (BUFFER_SIZE )
) lcd (
.rst (rst ),
.clk (clk ),
.debug (debug ),
.i_soft_tearing (w_soft_tearing ),
.i_tearing_reg (r_tearing_reg ),
.i_tearing_value (r_tearing_value ),
.i_tearing_count (r_tearing_count ),
.i_mem_write_cmd (r_mem_write_cmd ),
.i_tearing_polarity (w_tearing_polarity ),
.i_enable (w_enable ),
.i_enable_tearing (w_enable_tearing ),
.i_reset_display (w_reset_display ),
.i_data_command_mode (~w_command_mode ),
.i_cmd_rs (w_cmd_rs ),
.i_cmd_write_stb (w_cmd_write_stb ),
.i_cmd_read_stb (w_cmd_read_stb ),
.i_cmd_data (r_cmd_data_out ),
.o_cmd_data (w_cmd_data_in ),
.o_cmd_finished (w_cmd_finished ),
.i_backlight_enable (w_backlight_enable ),
.i_chip_select (w_chip_select ),
.i_num_pixels (r_num_pixels ),
.o_fifo_rdy (wfifo_ready ),
.i_fifo_act (wfifo_activate ),
.i_fifo_stb (wfifo_strobe ),
.o_fifo_size (wfifo_size ),
.i_fifo_data (wfifo_data ),
.o_backlight_enable (o_backlight_enable ),
.o_register_data_sel (o_register_data_sel ),
.o_write_n (o_write_n ),
.o_read_n (o_read_n ),
.io_data (io_data ),
.o_cs_n (o_cs_n ),
.o_reset_n (o_reset_n ),
.i_tearing_effect (i_tearing_effect ),
.o_display_on (o_display_on )
);
wb_mem_2_ppfifo m2p(
.clk (clk ),
.rst (rst ),
//.debug (debug ),
//Control
.i_enable (w_enable ),
.i_memory_0_base (r_memory_0_base ),
.i_memory_0_size (r_memory_0_size ),
.o_memory_0_count (w_memory_0_count ),
.i_memory_0_new_data (r_memory_0_new_data ),
.o_memory_0_empty (w_memory_0_empty ),
.o_default_mem_0_base (w_default_mem_0_base ),
.i_memory_1_base (r_memory_1_base ),
.i_memory_1_size (r_memory_1_size ),
.o_memory_1_count (w_memory_1_count ),
.i_memory_1_new_data (r_memory_1_new_data ),
.o_memory_1_empty (w_memory_1_empty ),
.o_default_mem_1_base (w_default_mem_1_base ),
.o_read_finished (w_read_finished ),
//master control signal for memory arbitration
.o_mem_we (mem_o_we ),
.o_mem_stb (mem_o_stb ),
.o_mem_cyc (mem_o_cyc ),
.o_mem_sel (mem_o_sel ),
.o_mem_adr (mem_o_adr ),
.o_mem_dat (mem_o_dat ),
.i_mem_dat (mem_i_dat ),
.i_mem_ack (mem_i_ack ),
.i_mem_int (mem_i_int ),
//Ping Pong FIFO Interface
.i_ppfifo_rdy (wfifo_ready ),
.o_ppfifo_act (wfifo_activate ),
.i_ppfifo_size (wfifo_size ),
.o_ppfifo_stb (wfifo_strobe ),
.o_ppfifo_data (wfifo_data )
);
//Asynchronous Logic
//control
assign w_enable = control[`CONTROL_ENABLE];
assign w_enable_interrupt = control[`CONTROL_ENABLE_INTERRUPT];
assign w_backlight_enable = control[`CONTROL_BACKLIGHT_ENABLE];
assign w_reset_display = control[`CONTROL_RESET_DISPLAY];
assign w_command_mode = control[`CONTROL_COMMAND_MODE];
assign w_cmd_write_stb = control[`CONTROL_COMMAND_WRITE];
assign w_cmd_read_stb = control[`CONTROL_COMMAND_READ];
assign w_cmd_rs = control[`CONTROL_COMMAND_RS];
assign w_chip_select = control[`CONTROL_CHIP_SELECT];
assign w_enable_tearing = control[`CONTROL_ENABLE_TEARING];
assign w_soft_tearing = control[`CONTROL_SOFT_TEAR];
assign w_tearing_polarity = control[`CONTROL_TEAR_POLARITY];
assign status[`STATUS_MEMORY_0_EMPTY] = w_memory_0_empty;
assign status[`STATUS_MEMORY_1_EMPTY] = w_memory_1_empty;
assign status[31:2] = 0;
//assign debug[1:0] = wfifo_ready;
//assign debug[3:2] = wfifo_activate;
//assign debug[4] = wfifo_strobe;
//assign debug[5] = wfifo_data[31];
//assign debug[31:16] = wfifo_data[23:8];
//blocks
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
timeout_enable <= 0;
timeout_value <= `DEFAULT_MEMORY_TIMEOUT;
control <= 0;
r_tearing_reg <= 0;
r_tearing_value <= 0;
r_tearing_count <= 0;
r_mem_write_cmd <= `CMD_START_MEM_WRITE;
r_cmd_data_out <= 0;
//Default base, user can change this from the API
r_memory_0_base <= w_default_mem_0_base;
r_memory_1_base <= w_default_mem_1_base;
//Nothing in the memory initially
r_memory_0_size <= 0;
r_memory_1_size <= 0;
r_memory_0_new_data <= 0;
r_memory_1_new_data <= 0;
end
else begin
r_memory_0_new_data <= 0;
r_memory_1_new_data <= 0;
//Reset bits that need resetting
if (w_cmd_write_stb) begin
control[`CONTROL_COMMAND_WRITE] <= 0;
end
if (w_cmd_read_stb) begin
control[`CONTROL_COMMAND_READ] <= 0;
end
//when the master acks our ack, then put our ack down
if (o_wbs_ack & ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb & i_wbs_cyc) begin
//master is requesting somethign
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
REG_CONTROL: begin
control <= i_wbs_dat;
if (i_wbs_dat[`CONTROL_ENABLE] && !w_enable) begin
$display ("-----------------------------------------------------------");
$display ("8080_LCD: Core Enable");
$display ("-----------------------------------------------------------");
end
end
REG_COMMAND_DATA: begin
r_cmd_data_out <= i_wbs_dat[7:0];
end
REG_PIXEL_COUNT: begin
r_num_pixels <= i_wbs_dat;
end
REG_MEM_0_BASE: begin
r_memory_0_base <= i_wbs_dat;
end
REG_MEM_0_SIZE: begin
r_memory_0_size <= i_wbs_dat;
if (i_wbs_dat > 0) begin
r_memory_0_new_data <= 1;
end
end
REG_DATA_ADDRESS: begin
r_mem_write_cmd <= i_wbs_dat;
end
REG_TEAR_ADDRESS: begin
r_tearing_reg <= i_wbs_dat;
end
REG_TEAR_VALUE: begin
r_tearing_value <= i_wbs_dat;
end
REG_TEAR_COUNT: begin
r_tearing_count <= i_wbs_dat;
end
REG_MEM_1_BASE: begin
r_memory_1_base <= i_wbs_dat;
end
REG_MEM_1_SIZE: begin
r_memory_1_size <= i_wbs_dat;
if (i_wbs_dat > 0) begin
r_memory_1_new_data <= 1;
end
end
default: begin
end
endcase
end
else begin
//read request
case (i_wbs_adr)
REG_CONTROL: begin
o_wbs_dat <= control;
end
REG_STATUS: begin
o_wbs_dat <= status;
end
REG_COMMAND_DATA: begin
//This will probably be read so fast that I won't have to check
//the ready flag
o_wbs_dat <= {24'h000000, w_cmd_data_in};
end
REG_PIXEL_COUNT: begin
o_wbs_dat <= r_num_pixels;
end
REG_DATA_ADDRESS: begin
o_wbs_dat <= r_mem_write_cmd;
end
REG_TEAR_ADDRESS: begin
o_wbs_dat <= r_tearing_reg;
end
REG_TEAR_VALUE: begin
o_wbs_dat <= r_tearing_value;
end
REG_TEAR_COUNT: begin
o_wbs_dat <= r_tearing_count;
end
REG_MEM_0_BASE: begin
o_wbs_dat <= r_memory_0_base;
end
REG_MEM_0_SIZE: begin
o_wbs_dat <= w_memory_0_count;
end
REG_MEM_1_BASE: begin
o_wbs_dat <= r_memory_1_base;
end
REG_MEM_1_SIZE: begin
o_wbs_dat <= w_memory_1_count;
end
//add as many ADDR_X you need here
default: begin
o_wbs_dat <= 32'h00;
end
endcase
end
o_wbs_ack <= 1;
end
end
end
//initerrupt controller
always @ (posedge clk) begin
if (rst) begin
o_wbs_int <= 0;
end
else if (w_enable) begin
if (!w_memory_0_empty && !w_memory_1_empty) begin
o_wbs_int <= 0;
end
if (i_wbs_stb) begin
//de-assert the interrupt on wbs transactions so I can launch another
//interrupt when the wbs is de-asserted
o_wbs_int <= 0;
end
else if (w_memory_0_empty || w_memory_1_empty) begin
o_wbs_int <= 1;
end
end
else begin
//if we're not enable de-assert interrupt
o_wbs_int <= 0;
end
end
always @ (posedge clk) begin
if (wfifo_strobe) begin
$display ("\tI2S MEM CONTROLLER: Wrote: %h: Request: %h", wfifo_data, wfifo_size);
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 14:20:02 10/03/2016
// Module Name: INSTR_MEM
// Project Name: MIPS
// Description: MIPS Instruction Memory implementation in verilog.
//
// Dependencies: None
//
////////////////////////////////////////////////////////////////////////////////
module INSTR_MEM(input clk, input [31:0] addr, output reg [31:0] data);
// Declare the memory block.
reg [31:0] MEM [128:0];
// Initialize memory.
initial begin
/* SET 1 - Using NOPs to mitigate data hazards.
MEM[0] <= 32'b100011_00000_00001_0000_0000_0000_0001; // LW r1 , 1(r0)
MEM[1] <= 32'b100011_00000_00010_0000_0000_0000_0010; // LW r2 , 2(r0)
MEM[2] <= 32'b100011_00000_00011_0000_0000_0000_0011; // LW r3 , 3(r0)
MEM[3] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[4] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[5] <= 32'b000000_00001_00010_00001_00000_100000; // ADD r1, r1, r2
MEM[6] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[7] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[8] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[9] <= 32'b000000_00001_00011_00001_00000_100000; // ADD r1, r1, r3
MEM[10] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[11] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[12] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[13] <= 32'b000000_00001_00001_00001_00000_100000; // ADD r1, r1, r1
MEM[14] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[15] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[16] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[17] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[18] <= 32'b000000_00001_00000_00001_00000_100000; // ADD r1, r1, r0
MEM[19] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[20] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[21] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[22] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[23] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
*/
/* SET 2 - Using ordering of instructions to mitigate data hazards.
MEM[0] <= 32'b100011_00000_00001_0000_0000_0000_0001; // LW r1, 1(r0)
MEM[1] <= 32'b100011_00000_00010_0000_0000_0000_0010; // LW r2, 2(r0)
MEM[2] <= 32'b100011_00000_00011_0000_0000_0000_0011; // LW r3, 3(r0)
MEM[3] <= 32'b100011_00000_00100_0000_0000_0000_0100; // LW r4, 4(r0)
MEM[4] <= 32'b100011_00000_00101_0000_0000_0000_0101; // LW r5, 5(r0)
MEM[5] <= 32'b101011_00000_00001_0000_0000_0000_0110; // SW r1, 6(r0)
MEM[6] <= 32'b101011_00000_00010_0000_0000_0000_0111; // SW r2, 7(r0)
MEM[7] <= 32'b101011_00000_00011_0000_0000_0000_1000; // SW r3, 8(r0)
MEM[8] <= 32'b101011_00000_00100_0000_0000_0000_1001; // SW r4, 9(r0)
MEM[9] <= 32'b101011_00000_00101_0000_0000_0000_1010; // SW r5, 10(r0)
*/
/* SET 3 - Using forwarding to mitigate data hazards. */
MEM[0] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[1] <= 32'b001000_00001_00001_0000000000000001; // ADD r1, r1, 1
MEM[2] <= 32'b001000_00010_00010_0000000000000010; // ADD r2, r2, 2
end
// Assign the contents at the requested memory address to data.
always @ *
begin
data <= MEM[addr];
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axis_data_fifo:1.1
// IP Revision: 8
(* X_CORE_INFO = "axis_data_fifo_v1_1_8_axis_data_fifo,Vivado 2015.4.2" *)
(* CHECK_LICENSE_TYPE = "design_SWandHW_standalone_axis_data_fifo_2_0,axis_data_fifo_v1_1_8_axis_data_fifo,{}" *)
(* CORE_GENERATION_INFO = "design_SWandHW_standalone_axis_data_fifo_2_0,axis_data_fifo_v1_1_8_axis_data_fifo,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_data_fifo,x_ipVersion=1.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_SIGNAL_SET=0b00000000000000000000000000011011,C_FIFO_DEPTH=32,C_FIFO_MODE=1,C_IS_ACLK_ASYNC=0,C_SYNCHRONIZER_STAGE=2,C_ACLKEN_CONV_MODE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_SWandHW_standalone_axis_data_fifo_2_0 (
s_axis_aresetn,
s_axis_aclk,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tkeep,
s_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tlast,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count
);
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_RSTIF RST" *)
input wire s_axis_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_CLKIF CLK" *)
input wire s_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input wire s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output wire s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input wire [31 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *)
input wire [3 : 0] s_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input wire s_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [31 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TKEEP" *)
output wire [3 : 0] m_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output wire m_axis_tlast;
output wire [31 : 0] axis_data_count;
output wire [31 : 0] axis_wr_data_count;
output wire [31 : 0] axis_rd_data_count;
axis_data_fifo_v1_1_8_axis_data_fifo #(
.C_FAMILY("zynq"),
.C_AXIS_TDATA_WIDTH(32),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(1),
.C_AXIS_SIGNAL_SET('B00000000000000000000000000011011),
.C_FIFO_DEPTH(32),
.C_FIFO_MODE(1),
.C_IS_ACLK_ASYNC(0),
.C_SYNCHRONIZER_STAGE(2),
.C_ACLKEN_CONV_MODE(0)
) inst (
.s_axis_aresetn(s_axis_aresetn),
.m_axis_aresetn(1'H0),
.s_axis_aclk(s_axis_aclk),
.s_axis_aclken(1'H1),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(4'HF),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(1'H0),
.s_axis_tdest(1'H0),
.s_axis_tuser(1'H0),
.m_axis_aclk(1'H0),
.m_axis_aclken(1'H1),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axis_data_count(axis_data_count),
.axis_wr_data_count(axis_wr_data_count),
.axis_rd_data_count(axis_rd_data_count)
);
endmodule
|
/*
Copyright (c) 2014-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "XILINX"
)
(
/*
* Clock: 156.25MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
output wire [7:0] led_red,
output wire [7:0] led_green,
output wire [1:0] led_bmc,
output wire [1:0] led_exp,
/*
* Ethernet: QSFP28
*/
input wire qsfp_0_tx_clk_0,
input wire qsfp_0_tx_rst_0,
output wire [63:0] qsfp_0_txd_0,
output wire [7:0] qsfp_0_txc_0,
input wire qsfp_0_rx_clk_0,
input wire qsfp_0_rx_rst_0,
input wire [63:0] qsfp_0_rxd_0,
input wire [7:0] qsfp_0_rxc_0,
input wire qsfp_0_tx_clk_1,
input wire qsfp_0_tx_rst_1,
output wire [63:0] qsfp_0_txd_1,
output wire [7:0] qsfp_0_txc_1,
input wire qsfp_0_rx_clk_1,
input wire qsfp_0_rx_rst_1,
input wire [63:0] qsfp_0_rxd_1,
input wire [7:0] qsfp_0_rxc_1,
input wire qsfp_0_tx_clk_2,
input wire qsfp_0_tx_rst_2,
output wire [63:0] qsfp_0_txd_2,
output wire [7:0] qsfp_0_txc_2,
input wire qsfp_0_rx_clk_2,
input wire qsfp_0_rx_rst_2,
input wire [63:0] qsfp_0_rxd_2,
input wire [7:0] qsfp_0_rxc_2,
input wire qsfp_0_tx_clk_3,
input wire qsfp_0_tx_rst_3,
output wire [63:0] qsfp_0_txd_3,
output wire [7:0] qsfp_0_txc_3,
input wire qsfp_0_rx_clk_3,
input wire qsfp_0_rx_rst_3,
input wire [63:0] qsfp_0_rxd_3,
input wire [7:0] qsfp_0_rxc_3,
input wire qsfp_1_tx_clk_0,
input wire qsfp_1_tx_rst_0,
output wire [63:0] qsfp_1_txd_0,
output wire [7:0] qsfp_1_txc_0,
input wire qsfp_1_rx_clk_0,
input wire qsfp_1_rx_rst_0,
input wire [63:0] qsfp_1_rxd_0,
input wire [7:0] qsfp_1_rxc_0,
input wire qsfp_1_tx_clk_1,
input wire qsfp_1_tx_rst_1,
output wire [63:0] qsfp_1_txd_1,
output wire [7:0] qsfp_1_txc_1,
input wire qsfp_1_rx_clk_1,
input wire qsfp_1_rx_rst_1,
input wire [63:0] qsfp_1_rxd_1,
input wire [7:0] qsfp_1_rxc_1,
input wire qsfp_1_tx_clk_2,
input wire qsfp_1_tx_rst_2,
output wire [63:0] qsfp_1_txd_2,
output wire [7:0] qsfp_1_txc_2,
input wire qsfp_1_rx_clk_2,
input wire qsfp_1_rx_rst_2,
input wire [63:0] qsfp_1_rxd_2,
input wire [7:0] qsfp_1_rxc_2,
input wire qsfp_1_tx_clk_3,
input wire qsfp_1_tx_rst_3,
output wire [63:0] qsfp_1_txd_3,
output wire [7:0] qsfp_1_txc_3,
input wire qsfp_1_rx_clk_3,
input wire qsfp_1_rx_rst_3,
input wire [63:0] qsfp_1_rxd_3,
input wire [7:0] qsfp_1_rxc_3
);
// AXI between MAC and Ethernet modules
wire [63:0] rx_axis_tdata;
wire [7:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [63:0] tx_axis_tdata;
wire [7:0] tx_axis_tkeep;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [63:0] rx_eth_payload_axis_tdata;
wire [7:0] rx_eth_payload_axis_tkeep;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [63:0] tx_eth_payload_axis_tdata;
wire [7:0] tx_eth_payload_axis_tkeep;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [63:0] rx_ip_payload_axis_tdata;
wire [7:0] rx_ip_payload_axis_tkeep;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [63:0] tx_ip_payload_axis_tdata;
wire [7:0] tx_ip_payload_axis_tkeep;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [63:0] rx_udp_payload_axis_tdata;
wire [7:0] rx_udp_payload_axis_tkeep;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [63:0] tx_udp_payload_axis_tdata;
wire [7:0] tx_udp_payload_axis_tkeep;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [63:0] rx_fifo_udp_payload_axis_tdata;
wire [7:0] rx_fifo_udp_payload_axis_tkeep;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [63:0] tx_fifo_udp_payload_axis_tdata;
wire [7:0] tx_fifo_udp_payload_axis_tkeep;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tkeep = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
valid_last <= tx_udp_payload_axis_tvalid;
if (tx_udp_payload_axis_tvalid && !valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
end
end
end
assign led_red = led_reg;
assign led_green = led_reg;
assign led_bmc = 2'b00;
assign led_exp = 2'b11;
assign qsfp_0_txd_1 = 64'h0707070707070707;
assign qsfp_0_txc_1 = 8'hff;
assign qsfp_0_txd_2 = 64'h0707070707070707;
assign qsfp_0_txc_2 = 8'hff;
assign qsfp_0_txd_3 = 64'h0707070707070707;
assign qsfp_0_txc_3 = 8'hff;
assign qsfp_1_txd_0 = 64'h0707070707070707;
assign qsfp_1_txc_0 = 8'hff;
assign qsfp_1_txd_1 = 64'h0707070707070707;
assign qsfp_1_txc_1 = 8'hff;
assign qsfp_1_txd_2 = 64'h0707070707070707;
assign qsfp_1_txc_2 = 8'hff;
assign qsfp_1_txd_3 = 64'h0707070707070707;
assign qsfp_1_txc_3 = 8'hff;
eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(qsfp_0_rx_clk_0),
.rx_rst(qsfp_0_rx_rst_0),
.tx_clk(qsfp_0_tx_clk_0),
.tx_rst(qsfp_0_tx_rst_0),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.xgmii_rxd(qsfp_0_rxd_0),
.xgmii_rxc(qsfp_0_rxc_0),
.xgmii_txd(qsfp_0_txd_0),
.xgmii_txc(qsfp_0_txc_0),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
);
eth_axis_rx #(
.DATA_WIDTH(64)
)
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx #(
.DATA_WIDTH(64)
)
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tkeep(tx_axis_tkeep),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete_64
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(1'b0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
`resetall
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_BEHAVIORAL_PP_V
/**
* lsbufhv2lv: Level-shift buffer, low voltage-to-low voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, VPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, LVPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_BEHAVIORAL_PP_V |
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 218 06/27/2010 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0,
c1,
c2,
c3,
c4,
locked);
input inclk0;
output c0;
output c1;
output c2;
output c3;
output c4;
output locked;
wire [4:0] sub_wire0;
wire sub_wire3;
wire [0:0] sub_wire9 = 1'h0;
wire [4:4] sub_wire6 = sub_wire0[4:4];
wire [2:2] sub_wire5 = sub_wire0[2:2];
wire [0:0] sub_wire4 = sub_wire0[0:0];
wire [3:3] sub_wire2 = sub_wire0[3:3];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c3 = sub_wire2;
wire locked = sub_wire3;
wire c0 = sub_wire4;
wire c2 = sub_wire5;
wire c4 = sub_wire6;
wire sub_wire7 = inclk0;
wire [1:0] sub_wire8 = {sub_wire9, sub_wire7};
altpll altpll_component (
.inclk (sub_wire8),
.clk (sub_wire0),
.locked (sub_wire3),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "-2917",
altpll_component.clk1_divide_by = 2,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 4,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 1,
altpll_component.clk2_phase_shift = "0",
altpll_component.clk3_divide_by = 5,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 4,
altpll_component.clk3_phase_shift = "0",
altpll_component.clk4_divide_by = 5,
altpll_component.clk4_duty_cycle = 50,
altpll_component.clk4_multiply_by = 2,
altpll_component.clk4_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_USED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "4"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "5"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "5"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.500000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "40.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "20.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "10000000.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "40.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "20.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.91666700"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2917"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altera_dcm.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_dcm (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 5,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 5,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "50000",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=altera_dcm",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "5"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "5"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "10.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altera_dcm.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "50000"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dcm.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dcm.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dcm.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dcm.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dcm.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dcm_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dcm_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//****************************************************************************/
//
// Copyright (C) yyyy Ronan Barzic - [email protected]
// Date : Fri Apr 22 13:25:26 2016
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,MA 02110-1301,USA.
//
//
// Filename : two_phase_slave.v
//
// Description :
// A simple module that handles request and provides an acknowledge
// after some time
//
//
//
//
//****************************************************************************/
`timescale 1ns/1ps
module two_phase_slave (/*AUTOARG*/
// Outputs
ack,
// Inputs
req
);
input req;
output ack;
parameter spread=200;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
reg ack;
event evt_dbg_1;
event evt_dbg_2;
always @(posedge req) begin
if(ack == 1'b1) begin
$display("-E- Protocol violation (posedge req while ack == 1)");
$finish(1);
end
else begin
#($unsigned($random) % 200);
ack <= 1'b1;
end
end
always @(negedge req) begin
if(ack == 1'b0) begin
$display("-E- Protocol violation (negedge req while ack == 0)");
$finish(1);
end
else begin
#($unsigned($random) % 200);
ack <= 1'b0;
end
end
endmodule // two_phase_slave
/*
Local Variables:
verilog-library-directories:(
"."
)
End:
*/
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLRTP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SRDLRTP_FUNCTIONAL_V
/**
* srdlrtp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pkg_s/sky130_fd_sc_lp__udp_dlatch_pr_pp_pkg_s.v"
`celldefine
module sky130_fd_sc_lp__srdlrtp (
Q ,
RESET_B,
D ,
GATE ,
SLEEP_B
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input SLEEP_B;
// Local signals
wire buf_Q;
wire RESET;
wire kapwr;
wire vgnd ;
wire vpwr ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_dlatch$PR_pp$PKG$s `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, SLEEP_B, kapwr, vgnd, vpwr);
bufif1 bufif10 (Q , buf_Q, vpwr );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLRTP_FUNCTIONAL_V |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: six_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module six_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/six_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/six_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL six_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL six_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL six_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL six_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL six_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL six_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//======================================================================
//
// tb_chacha.v
// -----------
// Testbench for the Chacha top level wrapper.
//
//
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module tb_chacha();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 1;
localparam CLK_HALF_PERIOD = 1;
localparam CLK_PERIOD = 2 * CLK_HALF_PERIOD;
localparam TC1 = 1;
localparam TC2 = 2;
localparam TC3 = 3;
localparam TC4 = 4;
localparam TC5 = 5;
localparam TC6 = 6;
localparam TC7 = 7;
localparam TC8 = 8;
localparam TC9 = 9;
localparam TC10 = 10;
localparam ONE = 1;
localparam TWO = 2;
localparam THREE = 3;
localparam FOUR = 4;
localparam FIVE = 5;
localparam SIX = 6;
localparam SEVEN = 7;
localparam EIGHT = 8;
localparam KEY_128_BITS = 0;
localparam KEY_256_BITS = 1;
localparam EIGHT_ROUNDS = 8;
localparam TWELWE_ROUNDS = 12;
localparam TWENTY_ROUNDS = 20;
localparam DISABLE = 0;
localparam ENABLE = 1;
// API for the dut.
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_KEYLEN = 8'h0a;
localparam KEYLEN_BIT = 0;
localparam ADDR_ROUNDS = 8'h0b;
localparam ROUNDS_HIGH_BIT = 4;
localparam ROUNDS_LOW_BIT = 0;
localparam ADDR_KEY0 = 8'h10;
localparam ADDR_KEY1 = 8'h11;
localparam ADDR_KEY2 = 8'h12;
localparam ADDR_KEY3 = 8'h13;
localparam ADDR_KEY4 = 8'h14;
localparam ADDR_KEY5 = 8'h15;
localparam ADDR_KEY6 = 8'h16;
localparam ADDR_KEY7 = 8'h17;
localparam ADDR_IV0 = 8'h20;
localparam ADDR_IV1 = 8'h21;
localparam ADDR_DATA_IN0 = 8'h40;
localparam ADDR_DATA_IN15 = 8'h4f;
localparam ADDR_DATA_OUT0 = 8'h80;
localparam ADDR_DATA_OUT1 = 8'h81;
localparam ADDR_DATA_OUT2 = 8'h82;
localparam ADDR_DATA_OUT3 = 8'h83;
localparam ADDR_DATA_OUT4 = 8'h84;
localparam ADDR_DATA_OUT5 = 8'h85;
localparam ADDR_DATA_OUT6 = 8'h86;
localparam ADDR_DATA_OUT7 = 8'h87;
localparam ADDR_DATA_OUT8 = 8'h88;
localparam ADDR_DATA_OUT9 = 8'h89;
localparam ADDR_DATA_OUT10 = 8'h8a;
localparam ADDR_DATA_OUT11 = 8'h8b;
localparam ADDR_DATA_OUT12 = 8'h8c;
localparam ADDR_DATA_OUT13 = 8'h8d;
localparam ADDR_DATA_OUT14 = 8'h8e;
localparam ADDR_DATA_OUT15 = 8'h8f;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg tb_clk;
reg tb_reset_n;
reg tb_cs;
reg tb_write_read;
reg [7 : 0] tb_address;
reg [31 : 0] tb_data_in;
wire [31 : 0] tb_data_out;
wire tb_error;
reg [63 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg error_found;
reg [31 : 0] read_data;
reg [511 : 0] extracted_data;
reg display_cycle_ctr;
reg display_read_write;
reg display_core_state;
//----------------------------------------------------------------
// Chacha device under test.
//----------------------------------------------------------------
chacha dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.cs(tb_cs),
.we(tb_write_read),
.addr(tb_address),
.write_data(tb_data_in),
.read_data(tb_data_out)
);
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//--------------------------------------------------------------------
// dut_monitor
//
// Monitor displaying information every cycle.
// Includes the cycle counter.
//--------------------------------------------------------------------
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
if (display_cycle_ctr)
begin
$display("cycle = %016x:", cycle_ctr);
end
if (display_core_state)
begin
$display("core ctrl: 0x%02x, core_qr_ctr: 0x%02x, core_dr_ctr: 0x%02x, init: 0x%01x, next: 0x%01x, core_ready: 0x%02x",
dut.core.chacha_ctrl_reg, dut.core.qr_ctr_reg,
dut.core.dr_ctr_reg, dut.core.init,
dut.core.next, dut.core.ready_reg);
$display("state0_reg = 0x%08x, state1_reg = 0x%08x, state2_reg = 0x%08x, state3_reg = 0x%08x",
dut.core.state_reg[00], dut.core.state_reg[01], dut.core.state_reg[02], dut.core.state_reg[03]);
$display("state4_reg = 0x%08x, state5_reg = 0x%08x, state6_reg = 0x%08x, state7_reg = 0x%08x",
dut.core.state_reg[04], dut.core.state_reg[05], dut.core.state_reg[06], dut.core.state_reg[07]);
$display("state8_reg = 0x%08x, state9_reg = 0x%08x, state10_reg = 0x%08x, state11_reg = 0x%08x",
dut.core.state_reg[08], dut.core.state_reg[09], dut.core.state_reg[10], dut.core.state_reg[11]);
$display("state12_reg = 0x%08x, state13_reg = 0x%08x, state14_reg = 0x%08x, state15_reg = 0x%08x",
dut.core.state_reg[12], dut.core.state_reg[13], dut.core.state_reg[14], dut.core.state_reg[15]);
$display("");
end
if (display_read_write)
begin
if (dut.cs)
begin
if (dut.we)
begin
$display("*** Write acess: addr 0x%02x = 0x%08x", dut.addr, dut.write_data);
end
else
begin
$display("*** Read acess: addr 0x%02x = 0x%08x", dut.addr, dut.read_data);
end
end
end
end // dut_monitor
//----------------------------------------------------------------
// reset_dut
//----------------------------------------------------------------
task reset_dut;
begin
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Set the input to the DUT to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 0;
tb_cs = 0;
tb_write_read = 0;
tb_address = 8'h0;
tb_data_in = 32'h0;
display_cycle_ctr = 0;
display_read_write = 0;
display_core_state = 0;
end
endtask // init_sim
//----------------------------------------------------------------
// read_reg
//
// Task that reads and display the value of
// a register in the dut.
//----------------------------------------------------------------
task read_reg(input [7 : 0] addr);
begin
tb_cs = 1;
tb_write_read = 0;
tb_address = addr;
#(CLK_PERIOD);
tb_cs = 0;
tb_write_read = 0;
tb_address = 8'h0;
tb_data_in = 32'h0;
end
endtask // read_reg
//----------------------------------------------------------------
// write_reg
//
// Task that writes to a register in the dut.
//----------------------------------------------------------------
task write_reg(input [7 : 0] addr, input [31 : 0] data);
begin
tb_cs = 1;
tb_write_read = 1;
tb_address = addr;
tb_data_in = data;
#(CLK_PERIOD);
tb_cs = 0;
tb_write_read = 0;
tb_address = 8'h0;
tb_data_in = 32'h0;
end
endtask // write_reg
//----------------------------------------------------------------
// dump_top_state
//
// Dump the internal state of the top to std out.
//----------------------------------------------------------------
task dump_top_state;
begin
$display("");
$display("Top internal state");
$display("------------------");
$display("init_reg = %01x", dut.init_reg);
$display("next_reg = %01x", dut.next_reg);
$display("keylen_reg = %01x", dut.keylen_reg);
$display("rounds_reg = %01x", dut.rounds_reg);
$display("");
$display("key0_reg = %08x, key1_reg = %08x, key2_reg = %08x, key3_reg = %08x",
dut.key_reg[0], dut.key_reg[1], dut.key_reg[2], dut.key_reg[3]);
$display("key4_reg = %08x, key5_reg = %08x, key6_reg = %08x, key7_reg = %08x",
dut.key_reg[4], dut.key_reg[5], dut.key_reg[6], dut.key_reg[7]);
$display("");
$display("iv0_reg = %08x, iv1_reg = %08x", dut.iv_reg[0], dut.iv_reg[1]);
$display("");
$display("data_in0_reg = %08x, data_in1_reg = %08x, data_in2_reg = %08x, data_in3_reg = %08x",
dut.data_in_reg[00], dut.data_in_reg[01], dut.data_in_reg[02], dut.data_in_reg[03]);
$display("data_in4_reg = %08x, data_in5_reg = %08x, data_in6_reg = %08x, data_in7_reg = %08x",
dut.data_in_reg[04], dut.data_in_reg[05], dut.data_in_reg[06], dut.data_in_reg[07]);
$display("data_in8_reg = %08x, data_in9_reg = %08x, data_in10_reg = %08x, data_in11_reg = %08x",
dut.data_in_reg[08], dut.data_in_reg[09], dut.data_in_reg[10], dut.data_in_reg[11]);
$display("data_in12_reg = %08x, data_in13_reg = %08x, data_in14_reg = %08x, data_in15_reg = %08x",
dut.data_in_reg[12], dut.data_in_reg[13], dut.data_in_reg[14], dut.data_in_reg[15]);
$display("");
$display("ready = 0x%01x, data_out_valid = %01x", dut.core_ready, dut.core_data_out_valid);
$display("data_out00 = %08x, data_out01 = %08x, data_out02 = %08x, data_out03 = %08x",
dut.core_data_out[511 : 480], dut.core_data_out[479 : 448],
dut.core_data_out[447 : 416], dut.core_data_out[415 : 384]);
$display("data_out04 = %08x, data_out05 = %08x, data_out06 = %08x, data_out07 = %08x",
dut.core_data_out[383 : 352], dut.core_data_out[351 : 320],
dut.core_data_out[319 : 288], dut.core_data_out[287 : 256]);
$display("data_out08 = %08x, data_out09 = %08x, data_out10 = %08x, data_out11 = %08x",
dut.core_data_out[255 : 224], dut.core_data_out[223 : 192],
dut.core_data_out[191 : 160], dut.core_data_out[159 : 128]);
$display("data_out12 = %08x, data_out13 = %08x, data_out14 = %08x, data_out15 = %08x",
dut.core_data_out[127 : 96], dut.core_data_out[95 : 64],
dut.core_data_out[63 : 32], dut.core_data_out[31 : 0]);
$display("");
end
endtask // dump_top_state
//----------------------------------------------------------------
// dump_core_state
//
// Dump the internal state of the core to std out.
//----------------------------------------------------------------
task dump_core_state;
begin
$display("");
$display("Core internal state");
$display("-------------------");
$display("Round state:");
$display("state0_reg = 0x%08x, state1_reg = 0x%08x, state2_reg = 0x%08x, state3_reg = 0x%08x",
dut.core.state_reg[00], dut.core.state_reg[01], dut.core.state_reg[02], dut.core.state_reg[03]);
$display("state4_reg = 0x%08x, state5_reg = 0x%08x, state6_reg = 0x%08x, state7_reg = 0x%08x",
dut.core.state_reg[04], dut.core.state_reg[05], dut.core.state_reg[06], dut.core.state_reg[07]);
$display("state8_reg = 0x%08x, state9_reg = 0x%08x, state10_reg = 0x%08x, state11_reg = 0x%08x",
dut.core.state_reg[08], dut.core.state_reg[09], dut.core.state_reg[10], dut.core.state_reg[11]);
$display("state12_reg = 0x%08x, state13_reg = 0x%08x, state14_reg = 0x%08x, state15_reg = 0x%08x",
dut.core.state_reg[12], dut.core.state_reg[13], dut.core.state_reg[14], dut.core.state_reg[15]);
$display("");
$display("rounds = %01x", dut.core.rounds);
$display("qr_ctr_reg = %01x, dr_ctr_reg = %01x", dut.core.qr_ctr_reg, dut.core.dr_ctr_reg);
$display("block0_ctr_reg = %08x, block1_ctr_reg = %08x", dut.core.block0_ctr_reg, dut.core.block1_ctr_reg);
$display("");
$display("chacha_ctrl_reg = %02x", dut.core.chacha_ctrl_reg);
$display("");
$display("data_in = %064x", dut.core.data_in);
$display("data_out_valid_reg = %01x", dut.core.data_out_valid_reg);
$display("");
$display("qr0_a_prim = %08x, qr0_b_prim = %08x", dut.core.qr0_a_prim, dut.core.qr0_b_prim);
$display("qr0_c_prim = %08x, qr0_d_prim = %08x", dut.core.qr0_c_prim, dut.core.qr0_d_prim);
$display("");
end
endtask // dump_core_state
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d test cases did not complete successfully.", error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// read_write_test()
//
// Simple test case that tries to read and write to the
// registers in the dut.
//
// Note: Currently not self testing. No expected values.
//----------------------------------------------------------------
task read_write_test;
begin
tc_ctr = tc_ctr + 1;
write_reg(ADDR_KEY0, 32'h55555555);
read_reg(ADDR_KEY0);
write_reg(ADDR_KEY1, 32'haaaaaaaa);
read_reg(ADDR_KEY1);
read_reg(ADDR_CTRL);
read_reg(ADDR_STATUS);
read_reg(ADDR_KEYLEN);
read_reg(ADDR_ROUNDS);
read_reg(ADDR_KEY0);
read_reg(ADDR_KEY1);
read_reg(ADDR_KEY2);
read_reg(ADDR_KEY3);
read_reg(ADDR_KEY4);
read_reg(ADDR_KEY5);
read_reg(ADDR_KEY6);
read_reg(ADDR_KEY7);
end
endtask // read_write_test
//----------------------------------------------------------------
// write_localparams()
//
// Write key, iv and other parameters to the dut.
//----------------------------------------------------------------
task write_parameters(input [256 : 0] key,
input key_length,
input [64 : 0] iv,
input [4 : 0] rounds);
begin
write_reg(ADDR_KEY0, key[255 : 224]);
write_reg(ADDR_KEY1, key[223 : 192]);
write_reg(ADDR_KEY2, key[191 : 160]);
write_reg(ADDR_KEY3, key[159 : 128]);
write_reg(ADDR_KEY4, key[127 : 96]);
write_reg(ADDR_KEY5, key[95 : 64]);
write_reg(ADDR_KEY6, key[63 : 32]);
write_reg(ADDR_KEY7, key[31 : 0]);
write_reg(ADDR_IV0, iv[63 : 32]);
write_reg(ADDR_IV1, iv[31 : 0]);
write_reg(ADDR_KEYLEN, {{31'h0}, key_length});
write_reg(ADDR_ROUNDS, {{27'h0}, rounds});
end
endtask // write_parameters
//----------------------------------------------------------------
// start_init_block()
//
// Toggle the init signal in the dut to make it start processing
// the first block available in the data in registers.
//
// Note: It is the callers responsibility to call the function
// when the dut is ready to react on the init signal.
//----------------------------------------------------------------
task start_init_block;
begin
write_reg(ADDR_CTRL, 32'h00000001);
#(2 * CLK_PERIOD);
write_reg(ADDR_CTRL, 32'h00000000);
end
endtask // start_init_block
//----------------------------------------------------------------
// start_next_block()
//
// Toggle the next signal in the dut to make it start processing
// the next block available in the data in registers.
//
// Note: It is the callers responsibility to call the function
// when the dut is ready to react on the next signal.
//----------------------------------------------------------------
task start_next_block;
begin
write_reg(ADDR_CTRL, 32'h00000002);
#(2 * CLK_PERIOD);
write_reg(ADDR_CTRL, 32'h00000000);
if (DEBUG)
begin
$display("Debug of next state.");
dump_core_state();
#(2 * CLK_PERIOD);
dump_core_state();
end
end
endtask // start_next_block
//----------------------------------------------------------------
// wait_ready()
//
// Wait for the ready flag in the dut to be set.
//
// Note: It is the callers responsibility to call the function
// when the dut is actively processing and will in fact at some
// point set the flag.
//----------------------------------------------------------------
task wait_ready;
begin
while (!tb_data_out[STATUS_READY_BIT])
begin
read_reg(ADDR_STATUS);
end
end
endtask // wait_ready
//----------------------------------------------------------------
// extract_data()
//
// Extracts all 16 data out words and combine them into the
// global extracted_data.
//----------------------------------------------------------------
task extract_data;
begin
read_reg(ADDR_DATA_OUT0);
extracted_data[511 : 480] = tb_data_out;
read_reg(ADDR_DATA_OUT1);
extracted_data[479 : 448] = tb_data_out;
read_reg(ADDR_DATA_OUT2);
extracted_data[447 : 416] = tb_data_out;
read_reg(ADDR_DATA_OUT3);
extracted_data[415 : 384] = tb_data_out;
read_reg(ADDR_DATA_OUT4);
extracted_data[383 : 352] = tb_data_out;
read_reg(ADDR_DATA_OUT5);
extracted_data[351 : 320] = tb_data_out;
read_reg(ADDR_DATA_OUT6);
extracted_data[319 : 288] = tb_data_out;
read_reg(ADDR_DATA_OUT7);
extracted_data[287 : 256] = tb_data_out;
read_reg(ADDR_DATA_OUT8);
extracted_data[255 : 224] = tb_data_out;
read_reg(ADDR_DATA_OUT9);
extracted_data[223 : 192] = tb_data_out;
read_reg(ADDR_DATA_OUT10);
extracted_data[191 : 160] = tb_data_out;
read_reg(ADDR_DATA_OUT11);
extracted_data[159 : 128] = tb_data_out;
read_reg(ADDR_DATA_OUT12);
extracted_data[127 : 96] = tb_data_out;
read_reg(ADDR_DATA_OUT13);
extracted_data[95 : 64] = tb_data_out;
read_reg(ADDR_DATA_OUT14);
extracted_data[63 : 32] = tb_data_out;
read_reg(ADDR_DATA_OUT15);
extracted_data[31 : 0] = tb_data_out;
end
endtask // extract_data
//----------------------------------------------------------------
// check_name_version()
//
// Read the name and version from the DUT.
//----------------------------------------------------------------
task check_name_version;
reg [31 : 0] name0;
reg [31 : 0] name1;
reg [31 : 0] version;
begin
$display("*** Trying to read name and version from core.");
read_reg(ADDR_NAME0);
name0 = tb_data_out;
read_reg(ADDR_NAME1);
name1 = tb_data_out;
read_reg(ADDR_VERSION);
version = tb_data_out;
$display("DUT name: %c%c%c%c%c%c%c%c",
name0[31 : 24], name0[23 : 16], name0[15 : 8], name0[7 : 0],
name1[31 : 24], name1[23 : 16], name1[15 : 8], name1[7 : 0]);
$display("DUT version: %c%c%c%c",
version[31 : 24], version[23 : 16], version[15 : 8], version[7 : 0]);
$display("");
end
endtask // check_name_version
//----------------------------------------------------------------
// run_two_blocks_test_vector()
//
// Runs a test case with two blocks based on the given
// test vector. Only the final block is compared.
//----------------------------------------------------------------
task run_two_blocks_test_vector(input [7 : 0] major,
input [7 : 0] minor,
input [256 : 0] key,
input key_length,
input [64 : 0] iv,
input [4 : 0] rounds,
input [511 : 0] expected);
begin
tc_ctr = tc_ctr + 1;
$display("***TC%2d-%2d started", major, minor);
$display("***-----------------");
write_parameters(key, key_length, iv, rounds);
start_init_block();
wait_ready();
extract_data();
if (DEBUG)
begin
$display("State after first block:");
dump_core_state();
$display("First block:");
$display("0x%064x", extracted_data);
end
start_next_block();
if (DEBUG)
begin
$display("State after init of second block:");
dump_core_state();
end
wait_ready();
extract_data();
if (DEBUG)
begin
$display("State after init of second block:");
dump_core_state();
$display("Second block:");
$display("0x%064x", extracted_data);
end
if (extracted_data != expected)
begin
error_ctr = error_ctr + 1;
$display("***TC%2d-%2d - ERROR", major, minor);
$display("***-----------------");
$display("Expected:");
$display("0x%064x", expected);
$display("Got:");
$display("0x%064x", extracted_data);
end
else
begin
$display("***TC%2d-%2d - SUCCESS", major, minor);
$display("***-------------------");
end
$display("");
end
endtask // run_two_blocks_test_vector
//----------------------------------------------------------------
// run_test_vector()
//
// Runs a test case based on the given test vector.
//----------------------------------------------------------------
task run_test_vector(input [7 : 0] major,
input [7 : 0] minor,
input [256 : 0] key,
input key_length,
input [64 : 0] iv,
input [4 : 0] rounds,
input [511 : 0] expected);
begin
tc_ctr = tc_ctr + 1;
$display("***TC%2d-%2d started", major, minor);
$display("***-----------------");
write_parameters(key, key_length, iv, rounds);
start_init_block();
$display("*** Started.");
wait_ready();
$display("*** Ready seen.");
dump_top_state();
extract_data();
if (extracted_data != expected)
begin
error_ctr = error_ctr + 1;
$display("***TC%2d-%2d - ERROR", major, minor);
$display("***-----------------");
$display("Expected:");
$display("0x%064x", expected);
$display("Got:");
$display("0x%064x", extracted_data);
end
else
begin
$display("***TC%2d-%2d - SUCCESS", major, minor);
$display("***-------------------");
end
$display("");
end
endtask // run_test_vector
//----------------------------------------------------------------
// chacha_test
// The main test functionality.
//----------------------------------------------------------------
initial
begin : chacha_test
$display(" -- Testbench for chacha started --");
init_sim();
reset_dut();
$display("State at init after reset:");
dump_top_state();
// Check name and version.
check_name_version();
$display("TC1-1: All zero inputs. 128 bit key, 8 rounds.");
run_test_vector(TC1, ONE,
256'h0,
KEY_128_BITS,
64'h0,
EIGHT_ROUNDS,
512'he28a5fa4a67f8c5defed3e6fb7303486aa8427d31419a729572d777953491120b64ab8e72b8deb85cd6aea7cb6089a101824beeb08814a428aab1fa2c816081b);
$display("TC7-2: Increasing, decreasing sequences in key and IV. 256 bit key, 8 rounds.");
run_test_vector(TC7, TWO,
256'h00112233445566778899aabbccddeeffffeeddccbbaa99887766554433221100,
KEY_256_BITS,
64'h0f1e2d3c4b596877,
EIGHT_ROUNDS,
512'h60fdedbd1a280cb741d0593b6ea0309010acf18e1471f68968f4c9e311dca149b8e027b47c81e0353db013891aa5f68ea3b13dd2f3b8dd0873bf3746e7d6c567);
$display("TC7-3: Increasing, decreasing sequences in key and IV. 256 bit key, 8 rounds.");
$display("TC7-3: Testing correct second block.");
run_two_blocks_test_vector(TC7, THREE,
256'h00112233445566778899aabbccddeeffffeeddccbbaa99887766554433221100,
KEY_256_BITS,
64'h0f1e2d3c4b596877,
EIGHT_ROUNDS,
512'hfe882395601ce8aded444867fe62ed8741420002e5d28bb573113a418c1f4008e954c188f38ec4f26bb8555e2b7c92bf4380e2ea9e553187fdd42821794416de);
display_test_result();
$display("*** chacha simulation done.");
$finish;
end // chacha_test
endmodule // tb_chacha
//======================================================================
// EOF tb_chacha.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S4S_BLACKBOX_V
`define SKY130_FD_SC_HS__DLYMETAL6S4S_BLACKBOX_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlymetal6s4s (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S4S_BLACKBOX_V
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant I2C Master byte-controller ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_byte_ctrl.v,v 1.7 2004/02/18 11:40:46 rherveille Exp $
//
// $Date: 2004/02/18 11:40:46 $
// $Revision: 1.7 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: i2c_master_byte_ctrl.v,v $
// Revision 1.7 2004/02/18 11:40:46 rherveille
// Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
//
// Revision 1.6 2003/08/09 07:01:33 rherveille
// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
// Fixed a potential bug in the byte controller's host-acknowledge generation.
//
// Revision 1.5 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.4 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.3 2001/11/05 11:59:25 rherveille
// Fixed wb_ack_o generation bug.
// Fixed bug in the byte_controller statemachine.
// Added headers.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "i2c_master_defines.v"
module i2c_master_byte_ctrl (
clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, spi_mode, din,
cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen, spi_miso );
// parameters
parameter dedicated_spi = 0;
//
// inputs & outputs
//
input clk; // master clock
input rst; // synchronous active high reset
input nReset; // asynchronous active low reset
input ena; // core enable signal
input [15:0] clk_cnt; // 4x SCL
// control inputs
input start;
input stop;
input read;
input write;
input ack_in;
input spi_mode;
input [7:0] din;
// status outputs
output cmd_ack;
reg cmd_ack;
output ack_out;
reg ack_out;
output i2c_busy;
output i2c_al;
output [7:0] dout;
// I2C signals
input scl_i;
output scl_o;
output scl_oen;
input sda_i;
output sda_o;
output sda_oen;
// SPI MISO
input spi_miso;
//
// Variable declarations
//
// statemachine
parameter [6:0] ST_IDLE = 7'b000_0000;
parameter [6:0] ST_START = 7'b000_0001;
parameter [6:0] ST_READ = 7'b000_0010;
parameter [6:0] ST_WRITE = 7'b000_0100;
parameter [6:0] ST_ACK = 7'b000_1000;
parameter [6:0] ST_STOP = 7'b001_0000;
parameter [6:0] ST_SPI_READ = 7'b010_0000;
parameter [6:0] ST_SPI_WRITE = 7'b100_0000;
// signals for bit_controller
reg [5:0] core_cmd;
reg core_txd;
wire core_ack, core_rxd;
// signals for shift register
reg [7:0] sr; //8bit shift register
reg shift, ld;
// signals for state machine
wire go;
reg [2:0] dcnt;
wire cnt_done;
//
// Module body
//
// hookup bit_controller
i2c_master_bit_ctrl #(.dedicated_spi(dedicated_spi)) bit_controller (
.clk ( clk ),
.rst ( rst ),
.nReset ( nReset ),
.ena ( ena ),
.clk_cnt ( clk_cnt ),
.cmd ( core_cmd ),
.cmd_ack ( core_ack ),
.busy ( i2c_busy ),
.al ( i2c_al ),
.din ( core_txd ),
.dout ( core_rxd ),
.scl_i ( scl_i ),
.scl_o ( scl_o ),
.scl_oen ( scl_oen ),
.sda_i ( sda_i ),
.sda_o ( sda_o ),
.sda_oen ( sda_oen ),
.spi_miso (spi_miso)
);
// generate go-signal
assign go = (read | write | stop) & ~cmd_ack;
// assign dout output to shift-register
assign dout = sr;
// generate shift register
always @(posedge clk or negedge nReset)
if (!nReset)
sr <= #1 8'h0;
else if (rst)
sr <= #1 8'h0;
else if (ld)
sr <= #1 din;
else if (shift)
sr <= #1 {sr[6:0], core_rxd};
// generate counter
always @(posedge clk or negedge nReset)
if (!nReset)
dcnt <= #1 3'h0;
else if (rst)
dcnt <= #1 3'h0;
else if (ld)
dcnt <= #1 3'h7;
else if (shift)
dcnt <= #1 dcnt - 3'h1;
assign cnt_done = ~(|dcnt);
//
// state machine
//
reg [6:0] c_state; // synopsis enum_state
always @(posedge clk or negedge nReset)
if (!nReset)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else if (rst | i2c_al)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else
begin
// initially reset all signals
core_txd <= #1 sr[7];
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
case (c_state) // synopsys full_case parallel_case
ST_IDLE:
if (go)
begin
if (start)
begin
c_state <= #1 ST_START;
core_cmd <= #1 `I2C_CMD_START;
end
else if (read)
begin
c_state <= #1 spi_mode ? ST_SPI_READ : ST_READ;
core_cmd <= #1 spi_mode ? `SPI_CMD_READ : `I2C_CMD_READ;
end
else if (write)
begin
c_state <= #1 spi_mode ? ST_SPI_WRITE : ST_WRITE;
core_cmd <= #1 spi_mode ? `SPI_CMD_WRITE : `I2C_CMD_WRITE;
end
else // stop
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
ld <= #1 1'b1;
end
ST_START:
if (core_ack)
begin
if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
ld <= #1 1'b1;
end
ST_WRITE:
if (core_ack)
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE; // stay in same state
core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
shift <= #1 1'b1;
end
ST_READ:
if (core_ack)
begin
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else
begin
c_state <= #1 ST_READ; // stay in same state
core_cmd <= #1 `I2C_CMD_READ; // read next bit
end
shift <= #1 1'b1;
core_txd <= #1 ack_in;
end
ST_ACK:
if (core_ack)
begin
if (stop)
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
else
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
// assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out <= #1 core_rxd;
core_txd <= #1 1'b1;
end
else
core_txd <= #1 ack_in;
ST_STOP:
if (core_ack)
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
ST_SPI_WRITE:
if (core_ack)
if (cnt_done)
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
cmd_ack <= #1 1'b1;
end
else
begin
c_state <= #1 ST_SPI_WRITE; // stay in same state
core_cmd <= #1 `SPI_CMD_WRITE; // write next bit
shift <= #1 1'b1;
end
ST_SPI_READ:
if (core_ack)
begin
if (cnt_done)
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
cmd_ack <= #1 1'b1;
end
else
begin
c_state <= #1 ST_SPI_READ; // stay in same state
core_cmd <= #1 `SPI_CMD_READ; // read next bit
end
shift <= #1 1'b1;
core_txd <= #1 ack_in;
end
endcase
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.4
// \ \ Application : MIG
// / / Filename : col_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// The column machine manages the dq bus. Since there is a single DQ
// bus, and the column part of the DRAM is tightly coupled to this DQ
// bus, conceptually, the DQ bus and all of the column hardware in
// a multi rank DRAM array are managed as a single unit.
//
//
// The column machine does not "enforce" the column timing directly.
// It generates information and sends it to the bank machines. If the
// bank machines incorrectly make a request, the column machine will
// simply overwrite the existing request with the new request even
// if this would result in a timing or protocol violation.
//
// The column machine
// hosts the block that controls read and write data transfer
// to and from the dq bus.
//
// And if configured, there is provision for tracking the address
// of a command as it moves through the column pipeline. This
// address will be logged for detected ECC errors.
`timescale 1 ps / 1 ps
module col_mach #
(
parameter TCQ = 100,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CS_WIDTH = 4,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DELAY_WR_DATA_CNTRL = 0,
parameter DQS_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter nCK_PER_CLK = 2,
parameter nPHY_WRLAT = 0,
parameter nRD_EN2CNFG_WR = 6,
parameter nWR_EN2CNFG_RD = 4,
parameter nWR_EN2CNFG_WR = 4,
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16
)
(/*AUTOARG*/
// Outputs
dq_busy_data, wr_data_offset, dfi_wrdata_en, wr_data_en,
wr_data_addr, dfi_rddata_en, inhbt_wr_config, inhbt_rd_config,
rd_rmw, ecc_err_addr, ecc_status_valid, wr_ecc_buf, rd_data_end,
rd_data_addr, rd_data_offset, rd_data_en,
// Inputs
clk, rst, sent_col, col_size, io_config, col_wr_data_buf_addr,
dfi_rddata_valid, col_periodic_rd, col_data_buf_addr, col_rmw,
col_ra, col_ba, col_row, col_a
);
input clk;
input rst;
input sent_col;
output reg dq_busy_data = 1'b0;
// The following generates a column command disable based mostly on the type
// of DRAM and the fabric to DRAM CK ratio.
generate
if ((nCK_PER_CLK == 1) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
begin : three_bumps
reg [1:0] granted_col_d_r;
wire [1:0] granted_col_d_ns = {sent_col, granted_col_d_r[1]};
always @(posedge clk) granted_col_d_r <= #TCQ granted_col_d_ns;
always @(/*AS*/granted_col_d_r or sent_col)
dq_busy_data = sent_col || |granted_col_d_r;
end
if (((nCK_PER_CLK == 2) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
|| ((nCK_PER_CLK == 1) && ((BURST_MODE == "4") || (DRAM_TYPE == "DDR2"))))
begin : one_bump
always @(/*AS*/sent_col) dq_busy_data = sent_col;
end
endgenerate
// This generates a data offset based on fabric clock to DRAM CK ratio and
// the size bit. Note that this is different that the dq_busy_data signal
// generated above.
reg [1:0] offset_r = 2'b0;
reg [1:0] offset_ns = 2'b0;
input col_size;
wire data_end;
generate
if (DATA_BUF_OFFSET_WIDTH == 2) begin : data_valid_1_1
always @(/*AS*/col_size or offset_r or rst or sent_col) begin
if (rst) offset_ns = 2'b0;
else begin
offset_ns = offset_r;
if (sent_col) offset_ns = 2'b1;
else if (|offset_r && (offset_r != {col_size, 1'b1}))
offset_ns = offset_r + 2'b1;
else offset_ns = 2'b0;
end
end
always @(posedge clk) offset_r <= #TCQ offset_ns;
assign data_end = col_size ? (offset_r == 2'b11) : offset_r[0];
end
else begin : data_valid_2_1
always @(/*AS*/col_size or rst or sent_col)
offset_ns[0] = rst ? 1'b0 : sent_col && col_size;
always @(posedge clk) offset_r[0] <= #TCQ offset_ns[0];
assign data_end = col_size ? offset_r[0] : 1'b1;
end
endgenerate
reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r1 = {DATA_BUF_OFFSET_WIDTH{1'b0}};
generate
if ((nPHY_WRLAT == 1) || (DELAY_WR_DATA_CNTRL == 1)) begin : offset_pipe
always @(posedge clk) offset_r1 <=
#TCQ offset_r[DATA_BUF_OFFSET_WIDTH-1:0];
end
endgenerate
output wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
assign wr_data_offset = (DELAY_WR_DATA_CNTRL == 1)
? offset_r1[DATA_BUF_OFFSET_WIDTH-1:0]
: (EARLY_WR_DATA_ADDR == "OFF")
? offset_r[DATA_BUF_OFFSET_WIDTH-1:0]
: offset_ns[DATA_BUF_OFFSET_WIDTH-1:0];
input [RANK_WIDTH:0] io_config;
reg sent_col_r1;
always @(posedge clk) sent_col_r1 <= #TCQ sent_col;
wire wrdata_en = (nPHY_WRLAT == 0)
? ((sent_col || |offset_r) && io_config[RANK_WIDTH])
: ((sent_col_r1 || |offset_r1) && io_config[RANK_WIDTH]);
output wire [DQS_WIDTH-1:0] dfi_wrdata_en;
assign dfi_wrdata_en = {DQS_WIDTH{wrdata_en}};
output wire wr_data_en;
assign wr_data_en = (DELAY_WR_DATA_CNTRL == 1)
? ((sent_col_r1 || |offset_r1) && io_config[RANK_WIDTH])
: ((sent_col || |offset_r) && io_config[RANK_WIDTH]);
input [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr;
output wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
generate
if (DELAY_WR_DATA_CNTRL == 1) begin : delay_wr_data_cntrl_eq_1
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r;
always @(posedge clk) col_wr_data_buf_addr_r <=
#TCQ col_wr_data_buf_addr;
assign wr_data_addr = col_wr_data_buf_addr_r;
end
else begin : delay_wr_data_cntrl_ne_1
assign wr_data_addr = col_wr_data_buf_addr;
end
endgenerate
// CAS-RD to dfi_rddata_en
wire read_data_valid = (sent_col || |offset_r) && ~io_config[RANK_WIDTH];
output wire [DQS_WIDTH-1:0] dfi_rddata_en;
assign dfi_rddata_en = {DQS_WIDTH{read_data_valid}};
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam ONE = 1;
localparam nRD_EN2CNFG_WR_LOCAL = nRD_EN2CNFG_WR - 2;
localparam nWR_EN2CNFG_WR_LOCAL = nWR_EN2CNFG_WR - 2;
localparam WR_WAIT_CNT_WIDTH = clogb2(nRD_EN2CNFG_WR_LOCAL + 1);
reg [WR_WAIT_CNT_WIDTH-1:0] cnfg_wr_wait_r;
reg [WR_WAIT_CNT_WIDTH-1:0] cnfg_wr_wait_ns;
always @(/*AS*/cnfg_wr_wait_r or read_data_valid or rst or wrdata_en) begin
if (rst) cnfg_wr_wait_ns = {WR_WAIT_CNT_WIDTH{1'b0}};
else begin
cnfg_wr_wait_ns = cnfg_wr_wait_r;
if (wrdata_en)
cnfg_wr_wait_ns = nWR_EN2CNFG_WR_LOCAL[WR_WAIT_CNT_WIDTH-1:0];
else
if (read_data_valid)
cnfg_wr_wait_ns = nRD_EN2CNFG_WR_LOCAL[WR_WAIT_CNT_WIDTH-1:0];
else
if (|cnfg_wr_wait_r)
cnfg_wr_wait_ns = cnfg_wr_wait_r - ONE[WR_WAIT_CNT_WIDTH-1:0];
end // else: !if(rst)
end
always @(posedge clk) cnfg_wr_wait_r <= #TCQ cnfg_wr_wait_ns;
localparam nWR_EN2CNFG_RD_LOCAL = nWR_EN2CNFG_RD - 2;
localparam RD_WAIT_CNT_WIDTH = clogb2(nWR_EN2CNFG_RD_LOCAL + 1);
reg [RD_WAIT_CNT_WIDTH-1:0] cnfg_rd_wait_r;
reg [RD_WAIT_CNT_WIDTH-1:0] cnfg_rd_wait_ns;
always @(/*AS*/cnfg_rd_wait_r or rst or wrdata_en) begin
if (rst) cnfg_rd_wait_ns = {RD_WAIT_CNT_WIDTH{1'b0}};
else begin
cnfg_rd_wait_ns = cnfg_rd_wait_r;
if (wrdata_en)
cnfg_rd_wait_ns = nWR_EN2CNFG_RD_LOCAL[RD_WAIT_CNT_WIDTH-1:0];
else
if (|cnfg_rd_wait_r)
cnfg_rd_wait_ns = cnfg_rd_wait_r - ONE[RD_WAIT_CNT_WIDTH-1:0];
end
end
always @(posedge clk) cnfg_rd_wait_r <= #TCQ cnfg_rd_wait_ns;
// Finally, generate the inhbit signals. Do it in a way to help timing.
wire inhbt_wr_config_ns = (cnfg_wr_wait_ns != {WR_WAIT_CNT_WIDTH{1'b0}});
reg inhbt_wr_config_r;
always @(posedge clk) inhbt_wr_config_r <= #TCQ inhbt_wr_config_ns;
output wire inhbt_wr_config;
assign inhbt_wr_config = sent_col || wrdata_en || inhbt_wr_config_r;
wire inhbt_rd_config_ns = (cnfg_rd_wait_ns != {RD_WAIT_CNT_WIDTH{1'b0}});
reg inhbt_rd_config_r;
always @(posedge clk) inhbt_rd_config_r <= #TCQ inhbt_rd_config_ns;
output wire inhbt_rd_config;
assign inhbt_rd_config = sent_col || wrdata_en || inhbt_rd_config_r;
// Implement FIFO that records reads as they are sent to the DRAM.
// When dfi_rddata_valid is returned some unknown time later, the
// FIFO output is used to control how the data is interpreted.
input dfi_rddata_valid;
output wire rd_rmw;
output reg [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
output reg ecc_status_valid;
output reg wr_ecc_buf;
output reg rd_data_end;
output reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
output reg [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
output reg rd_data_en;
input col_periodic_rd;
input [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr;
input col_rmw;
input [RANK_WIDTH-1:0] col_ra;
input [BANK_WIDTH-1:0] col_ba;
input [ROW_WIDTH-1:0] col_row;
input [ROW_WIDTH-1:0] col_a;
wire [11:0] col_a_full = {col_a[13], col_a[11], col_a[9:0]};
wire [COL_WIDTH-1:0] col_a_extracted = col_a_full[COL_WIDTH-1:0];
localparam MC_ERR_LINE_WIDTH = MC_ERR_ADDR_WIDTH-DATA_BUF_OFFSET_WIDTH;
localparam FIFO_WIDTH = 1 /*data_end*/ +
1 /*periodic_rd*/ +
DATA_BUF_ADDR_WIDTH +
DATA_BUF_OFFSET_WIDTH +
((ECC == "OFF") ? 0 : 1+MC_ERR_LINE_WIDTH);
localparam FULL_RAM_CNT = (FIFO_WIDTH/6);
localparam REMAINDER = FIFO_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
generate
begin : read_fifo
wire [MC_ERR_LINE_WIDTH:0] ecc_line;
if (CS_WIDTH == 1)
assign ecc_line = {col_rmw, col_ba, col_row, col_a_extracted};
else
assign ecc_line = {col_rmw,
col_ra,
col_ba,
col_row,
col_a_extracted};
wire [FIFO_WIDTH-1:0] real_fifo_data;
if (ECC == "OFF")
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0]};
else
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0],
ecc_line};
wire [RAM_WIDTH-1:0] fifo_in_data;
if (REMAINDER == 0)
assign fifo_in_data = real_fifo_data;
else
assign fifo_in_data = {{6-REMAINDER{1'b0}}, real_fifo_data};
wire [RAM_WIDTH-1:0] fifo_out_data_ns;
reg [4:0] head_r;
wire [4:0] head_ns = rst ? 5'b0 : read_data_valid
? (head_r + 5'b1)
: head_r;
always @(posedge clk) head_r <= #TCQ head_ns;
reg [4:0] tail_r;
wire [4:0] tail_ns = rst ? 5'b0 : dfi_rddata_valid
? (tail_r + 5'b1)
: tail_r;
always @(posedge clk) tail_r <= #TCQ tail_ns;
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : fifo_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(fifo_out_data_ns[((i*6)+4)+:2]),
.DOB(fifo_out_data_ns[((i*6)+2)+:2]),
.DOC(fifo_out_data_ns[((i*6)+0)+:2]),
.DOD(),
.DIA(fifo_in_data[((i*6)+4)+:2]),
.DIB(fifo_in_data[((i*6)+2)+:2]),
.DIC(fifo_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(tail_ns),
.ADDRB(tail_ns),
.ADDRC(tail_ns),
.ADDRD(head_r),
.WE(1'b1),
.WCLK(clk)
);
end // block: fifo_ram
reg [RAM_WIDTH-1:0] fifo_out_data_r;
always @(posedge clk) fifo_out_data_r <= #TCQ fifo_out_data_ns;
// When ECC is ON, most of the FIFO output is delayed
// by one state.
if (ECC == "OFF") begin
reg periodic_rd;
always @(/*AS*/dfi_rddata_valid or fifo_out_data_r) begin
{rd_data_end,
periodic_rd,
rd_data_addr,
rd_data_offset} = fifo_out_data_r[FIFO_WIDTH-1:0];
ecc_err_addr = {MC_ERR_ADDR_WIDTH{1'b0}};
rd_data_en = dfi_rddata_valid && ~periodic_rd;
ecc_status_valid = 1'b0;
wr_ecc_buf = 1'b0;
end
assign rd_rmw = 1'b0;
end
else begin
wire rd_data_end_ns;
wire periodic_rd;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr_ns;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset_ns;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr_ns;
assign {rd_data_end_ns,
periodic_rd,
rd_data_addr_ns,
rd_data_offset_ns,
rd_rmw,
ecc_err_addr_ns[DATA_BUF_OFFSET_WIDTH+:MC_ERR_LINE_WIDTH]} =
{fifo_out_data_r[FIFO_WIDTH-1:0]};
assign ecc_err_addr_ns[0+:DATA_BUF_OFFSET_WIDTH] = rd_data_offset_ns;
always @(posedge clk) rd_data_end <= #TCQ rd_data_end_ns;
always @(posedge clk) rd_data_addr <= #TCQ rd_data_addr_ns;
always @(posedge clk) rd_data_offset <= #TCQ rd_data_offset_ns;
always @(posedge clk) ecc_err_addr <= #TCQ ecc_err_addr_ns;
wire rd_data_en_ns = dfi_rddata_valid && ~(periodic_rd || rd_rmw);
always @(posedge clk) rd_data_en <= rd_data_en_ns;
wire ecc_status_valid_ns = dfi_rddata_valid && ~periodic_rd;
always @(posedge clk) ecc_status_valid <= #TCQ ecc_status_valid_ns;
wire wr_ecc_buf_ns = dfi_rddata_valid && ~periodic_rd && rd_rmw;
always @(posedge clk) wr_ecc_buf <= #TCQ wr_ecc_buf_ns;
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_1_V
`define SKY130_FD_SC_HVL__DFRBP_1_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog wrapper for dfrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_1_V
|
// Computer_System.v
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module Computer_System (
output wire hps_io_hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0
inout wire hps_io_hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1
inout wire hps_io_hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2
inout wire hps_io_hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3
output wire hps_io_hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0
output wire hps_io_hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK
inout wire hps_io_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_io_hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_io_hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_io_hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_io_hps_io_gpio_inst_GPIO41, // .hps_io_gpio_inst_GPIO41
inout wire hps_io_hps_io_gpio_inst_GPIO48, // .hps_io_gpio_inst_GPIO48
inout wire hps_io_hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_hps_io_gpio_inst_GPIO61, // .hps_io_gpio_inst_GPIO61
output wire [9:0] leds_export, // leds.export
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
input wire [3:0] pushbuttons_export, // pushbuttons.export
output wire [12:0] sdram_addr, // sdram.addr
output wire [1:0] sdram_ba, // .ba
output wire sdram_cas_n, // .cas_n
output wire sdram_cke, // .cke
output wire sdram_cs_n, // .cs_n
inout wire [15:0] sdram_dq, // .dq
output wire [1:0] sdram_dqm, // .dqm
output wire sdram_ras_n, // .ras_n
output wire sdram_we_n, // .we_n
output wire sdram_clk_clk, // sdram_clk.clk
input wire [9:0] slider_switches_export, // slider_switches.export
input wire system_pll_ref_clk_clk, // system_pll_ref_clk.clk
input wire system_pll_ref_reset_reset, // system_pll_ref_reset.reset
output wire vga_CLK, // vga.CLK
output wire vga_HS, // .HS
output wire vga_VS, // .VS
output wire vga_BLANK, // .BLANK
output wire vga_SYNC, // .SYNC
output wire [7:0] vga_R, // .R
output wire [7:0] vga_G, // .G
output wire [7:0] vga_B, // .B
input wire vga_pll_ref_clk_clk, // vga_pll_ref_clk.clk
input wire vga_pll_ref_reset_reset, // vga_pll_ref_reset.reset
input wire video_in_TD_CLK27, // video_in.TD_CLK27
input wire [7:0] video_in_TD_DATA, // .TD_DATA
input wire video_in_TD_HS, // .TD_HS
input wire video_in_TD_VS, // .TD_VS
input wire video_in_clk27_reset, // .clk27_reset
output wire video_in_TD_RESET, // .TD_RESET
output wire video_in_overflow_flag // .overflow_flag
);
wire system_pll_sys_clk_clk; // System_PLL:sys_clk_clk -> [ARM_A9_HPS:f2h_axi_clk, ARM_A9_HPS:h2f_axi_clk, ARM_A9_HPS:h2f_lw_axi_clk, LEDs:clk, Onchip_SRAM:clk, Pixel_DMA_Addr_Translation:clk, Pushbuttons:clk, SDRAM:clk, Slider_Switches:clk, SysID:clock, VGA_Subsystem:sys_clk_clk, Video_In_DMA_Addr_Translation:clk, Video_In_Subsystem:sys_clk_clk, mm_interconnect_0:System_PLL_sys_clk_clk, mm_interconnect_1:System_PLL_sys_clk_clk, mm_interconnect_2:System_PLL_sys_clk_clk, mm_interconnect_3:System_PLL_sys_clk_clk, rst_controller:clk, rst_controller_003:clk]
wire [1:0] arm_a9_hps_h2f_axi_master_awburst; // ARM_A9_HPS:h2f_AWBURST -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_awburst
wire [3:0] arm_a9_hps_h2f_axi_master_arlen; // ARM_A9_HPS:h2f_ARLEN -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_arlen
wire [15:0] arm_a9_hps_h2f_axi_master_wstrb; // ARM_A9_HPS:h2f_WSTRB -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_wstrb
wire arm_a9_hps_h2f_axi_master_wready; // mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_wready -> ARM_A9_HPS:h2f_WREADY
wire [11:0] arm_a9_hps_h2f_axi_master_rid; // mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_rid -> ARM_A9_HPS:h2f_RID
wire arm_a9_hps_h2f_axi_master_rready; // ARM_A9_HPS:h2f_RREADY -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_rready
wire [3:0] arm_a9_hps_h2f_axi_master_awlen; // ARM_A9_HPS:h2f_AWLEN -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_awlen
wire [11:0] arm_a9_hps_h2f_axi_master_wid; // ARM_A9_HPS:h2f_WID -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_wid
wire [3:0] arm_a9_hps_h2f_axi_master_arcache; // ARM_A9_HPS:h2f_ARCACHE -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_arcache
wire arm_a9_hps_h2f_axi_master_wvalid; // ARM_A9_HPS:h2f_WVALID -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_wvalid
wire [29:0] arm_a9_hps_h2f_axi_master_araddr; // ARM_A9_HPS:h2f_ARADDR -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_araddr
wire [2:0] arm_a9_hps_h2f_axi_master_arprot; // ARM_A9_HPS:h2f_ARPROT -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_arprot
wire [2:0] arm_a9_hps_h2f_axi_master_awprot; // ARM_A9_HPS:h2f_AWPROT -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_awprot
wire [127:0] arm_a9_hps_h2f_axi_master_wdata; // ARM_A9_HPS:h2f_WDATA -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_wdata
wire arm_a9_hps_h2f_axi_master_arvalid; // ARM_A9_HPS:h2f_ARVALID -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_arvalid
wire [3:0] arm_a9_hps_h2f_axi_master_awcache; // ARM_A9_HPS:h2f_AWCACHE -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_awcache
wire [11:0] arm_a9_hps_h2f_axi_master_arid; // ARM_A9_HPS:h2f_ARID -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_arid
wire [1:0] arm_a9_hps_h2f_axi_master_arlock; // ARM_A9_HPS:h2f_ARLOCK -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_arlock
wire [1:0] arm_a9_hps_h2f_axi_master_awlock; // ARM_A9_HPS:h2f_AWLOCK -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_awlock
wire [29:0] arm_a9_hps_h2f_axi_master_awaddr; // ARM_A9_HPS:h2f_AWADDR -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_awaddr
wire [1:0] arm_a9_hps_h2f_axi_master_bresp; // mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_bresp -> ARM_A9_HPS:h2f_BRESP
wire arm_a9_hps_h2f_axi_master_arready; // mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_arready -> ARM_A9_HPS:h2f_ARREADY
wire [127:0] arm_a9_hps_h2f_axi_master_rdata; // mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_rdata -> ARM_A9_HPS:h2f_RDATA
wire arm_a9_hps_h2f_axi_master_awready; // mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_awready -> ARM_A9_HPS:h2f_AWREADY
wire [1:0] arm_a9_hps_h2f_axi_master_arburst; // ARM_A9_HPS:h2f_ARBURST -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_arburst
wire [2:0] arm_a9_hps_h2f_axi_master_arsize; // ARM_A9_HPS:h2f_ARSIZE -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_arsize
wire arm_a9_hps_h2f_axi_master_bready; // ARM_A9_HPS:h2f_BREADY -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_bready
wire arm_a9_hps_h2f_axi_master_rlast; // mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_rlast -> ARM_A9_HPS:h2f_RLAST
wire arm_a9_hps_h2f_axi_master_wlast; // ARM_A9_HPS:h2f_WLAST -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_wlast
wire [1:0] arm_a9_hps_h2f_axi_master_rresp; // mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_rresp -> ARM_A9_HPS:h2f_RRESP
wire [11:0] arm_a9_hps_h2f_axi_master_awid; // ARM_A9_HPS:h2f_AWID -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_awid
wire [11:0] arm_a9_hps_h2f_axi_master_bid; // mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_bid -> ARM_A9_HPS:h2f_BID
wire arm_a9_hps_h2f_axi_master_bvalid; // mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_bvalid -> ARM_A9_HPS:h2f_BVALID
wire [2:0] arm_a9_hps_h2f_axi_master_awsize; // ARM_A9_HPS:h2f_AWSIZE -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_awsize
wire arm_a9_hps_h2f_axi_master_awvalid; // ARM_A9_HPS:h2f_AWVALID -> mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_awvalid
wire arm_a9_hps_h2f_axi_master_rvalid; // mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_rvalid -> ARM_A9_HPS:h2f_RVALID
wire video_in_subsystem_top_io_buff_out_waitrequest; // mm_interconnect_0:Video_In_Subsystem_top_io_buff_out_waitrequest -> Video_In_Subsystem:top_io_buff_out_waitrequest
wire [31:0] video_in_subsystem_top_io_buff_out_address; // Video_In_Subsystem:top_io_buff_out_address -> mm_interconnect_0:Video_In_Subsystem_top_io_buff_out_address
wire video_in_subsystem_top_io_buff_out_write; // Video_In_Subsystem:top_io_buff_out_write -> mm_interconnect_0:Video_In_Subsystem_top_io_buff_out_write
wire [15:0] video_in_subsystem_top_io_buff_out_writedata; // Video_In_Subsystem:top_io_buff_out_writedata -> mm_interconnect_0:Video_In_Subsystem_top_io_buff_out_writedata
wire video_in_subsystem_video_in_dma_master_waitrequest; // mm_interconnect_0:Video_In_Subsystem_video_in_dma_master_waitrequest -> Video_In_Subsystem:video_in_dma_master_waitrequest
wire [31:0] video_in_subsystem_video_in_dma_master_address; // Video_In_Subsystem:video_in_dma_master_address -> mm_interconnect_0:Video_In_Subsystem_video_in_dma_master_address
wire video_in_subsystem_video_in_dma_master_write; // Video_In_Subsystem:video_in_dma_master_write -> mm_interconnect_0:Video_In_Subsystem_video_in_dma_master_write
wire [15:0] video_in_subsystem_video_in_dma_master_writedata; // Video_In_Subsystem:video_in_dma_master_writedata -> mm_interconnect_0:Video_In_Subsystem_video_in_dma_master_writedata
wire vga_subsystem_pixel_dma_master_waitrequest; // mm_interconnect_0:VGA_Subsystem_pixel_dma_master_waitrequest -> VGA_Subsystem:pixel_dma_master_waitrequest
wire [15:0] vga_subsystem_pixel_dma_master_readdata; // mm_interconnect_0:VGA_Subsystem_pixel_dma_master_readdata -> VGA_Subsystem:pixel_dma_master_readdata
wire [31:0] vga_subsystem_pixel_dma_master_address; // VGA_Subsystem:pixel_dma_master_address -> mm_interconnect_0:VGA_Subsystem_pixel_dma_master_address
wire vga_subsystem_pixel_dma_master_read; // VGA_Subsystem:pixel_dma_master_read -> mm_interconnect_0:VGA_Subsystem_pixel_dma_master_read
wire vga_subsystem_pixel_dma_master_readdatavalid; // mm_interconnect_0:VGA_Subsystem_pixel_dma_master_readdatavalid -> VGA_Subsystem:pixel_dma_master_readdatavalid
wire vga_subsystem_pixel_dma_master_lock; // VGA_Subsystem:pixel_dma_master_lock -> mm_interconnect_0:VGA_Subsystem_pixel_dma_master_lock
wire mm_interconnect_0_vga_subsystem_char_buffer_slave_chipselect; // mm_interconnect_0:VGA_Subsystem_char_buffer_slave_chipselect -> VGA_Subsystem:char_buffer_slave_chipselect
wire [31:0] mm_interconnect_0_vga_subsystem_char_buffer_slave_readdata; // VGA_Subsystem:char_buffer_slave_readdata -> mm_interconnect_0:VGA_Subsystem_char_buffer_slave_readdata
wire [10:0] mm_interconnect_0_vga_subsystem_char_buffer_slave_address; // mm_interconnect_0:VGA_Subsystem_char_buffer_slave_address -> VGA_Subsystem:char_buffer_slave_address
wire [3:0] mm_interconnect_0_vga_subsystem_char_buffer_slave_byteenable; // mm_interconnect_0:VGA_Subsystem_char_buffer_slave_byteenable -> VGA_Subsystem:char_buffer_slave_byteenable
wire mm_interconnect_0_vga_subsystem_char_buffer_slave_write; // mm_interconnect_0:VGA_Subsystem_char_buffer_slave_write -> VGA_Subsystem:char_buffer_slave_write
wire [31:0] mm_interconnect_0_vga_subsystem_char_buffer_slave_writedata; // mm_interconnect_0:VGA_Subsystem_char_buffer_slave_writedata -> VGA_Subsystem:char_buffer_slave_writedata
wire mm_interconnect_0_vga_subsystem_char_buffer_slave_clken; // mm_interconnect_0:VGA_Subsystem_char_buffer_slave_clken -> VGA_Subsystem:char_buffer_slave_clken
wire mm_interconnect_0_sdram_s1_chipselect; // mm_interconnect_0:SDRAM_s1_chipselect -> SDRAM:az_cs
wire [15:0] mm_interconnect_0_sdram_s1_readdata; // SDRAM:za_data -> mm_interconnect_0:SDRAM_s1_readdata
wire mm_interconnect_0_sdram_s1_waitrequest; // SDRAM:za_waitrequest -> mm_interconnect_0:SDRAM_s1_waitrequest
wire [24:0] mm_interconnect_0_sdram_s1_address; // mm_interconnect_0:SDRAM_s1_address -> SDRAM:az_addr
wire mm_interconnect_0_sdram_s1_read; // mm_interconnect_0:SDRAM_s1_read -> SDRAM:az_rd_n
wire [1:0] mm_interconnect_0_sdram_s1_byteenable; // mm_interconnect_0:SDRAM_s1_byteenable -> SDRAM:az_be_n
wire mm_interconnect_0_sdram_s1_readdatavalid; // SDRAM:za_valid -> mm_interconnect_0:SDRAM_s1_readdatavalid
wire mm_interconnect_0_sdram_s1_write; // mm_interconnect_0:SDRAM_s1_write -> SDRAM:az_wr_n
wire [15:0] mm_interconnect_0_sdram_s1_writedata; // mm_interconnect_0:SDRAM_s1_writedata -> SDRAM:az_data
wire mm_interconnect_0_onchip_sram_s1_chipselect; // mm_interconnect_0:Onchip_SRAM_s1_chipselect -> Onchip_SRAM:chipselect
wire [31:0] mm_interconnect_0_onchip_sram_s1_readdata; // Onchip_SRAM:readdata -> mm_interconnect_0:Onchip_SRAM_s1_readdata
wire [15:0] mm_interconnect_0_onchip_sram_s1_address; // mm_interconnect_0:Onchip_SRAM_s1_address -> Onchip_SRAM:address
wire [3:0] mm_interconnect_0_onchip_sram_s1_byteenable; // mm_interconnect_0:Onchip_SRAM_s1_byteenable -> Onchip_SRAM:byteenable
wire mm_interconnect_0_onchip_sram_s1_write; // mm_interconnect_0:Onchip_SRAM_s1_write -> Onchip_SRAM:write
wire [31:0] mm_interconnect_0_onchip_sram_s1_writedata; // mm_interconnect_0:Onchip_SRAM_s1_writedata -> Onchip_SRAM:writedata
wire mm_interconnect_0_onchip_sram_s1_clken; // mm_interconnect_0:Onchip_SRAM_s1_clken -> Onchip_SRAM:clken
wire mm_interconnect_0_onchip_sram_s2_chipselect; // mm_interconnect_0:Onchip_SRAM_s2_chipselect -> Onchip_SRAM:chipselect2
wire [31:0] mm_interconnect_0_onchip_sram_s2_readdata; // Onchip_SRAM:readdata2 -> mm_interconnect_0:Onchip_SRAM_s2_readdata
wire [15:0] mm_interconnect_0_onchip_sram_s2_address; // mm_interconnect_0:Onchip_SRAM_s2_address -> Onchip_SRAM:address2
wire [3:0] mm_interconnect_0_onchip_sram_s2_byteenable; // mm_interconnect_0:Onchip_SRAM_s2_byteenable -> Onchip_SRAM:byteenable2
wire mm_interconnect_0_onchip_sram_s2_write; // mm_interconnect_0:Onchip_SRAM_s2_write -> Onchip_SRAM:write2
wire [31:0] mm_interconnect_0_onchip_sram_s2_writedata; // mm_interconnect_0:Onchip_SRAM_s2_writedata -> Onchip_SRAM:writedata2
wire mm_interconnect_0_onchip_sram_s2_clken; // mm_interconnect_0:Onchip_SRAM_s2_clken -> Onchip_SRAM:clken2
wire [1:0] arm_a9_hps_h2f_lw_axi_master_awburst; // ARM_A9_HPS:h2f_lw_AWBURST -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_awburst
wire [3:0] arm_a9_hps_h2f_lw_axi_master_arlen; // ARM_A9_HPS:h2f_lw_ARLEN -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_arlen
wire [3:0] arm_a9_hps_h2f_lw_axi_master_wstrb; // ARM_A9_HPS:h2f_lw_WSTRB -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_wstrb
wire arm_a9_hps_h2f_lw_axi_master_wready; // mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_wready -> ARM_A9_HPS:h2f_lw_WREADY
wire [11:0] arm_a9_hps_h2f_lw_axi_master_rid; // mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_rid -> ARM_A9_HPS:h2f_lw_RID
wire arm_a9_hps_h2f_lw_axi_master_rready; // ARM_A9_HPS:h2f_lw_RREADY -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_rready
wire [3:0] arm_a9_hps_h2f_lw_axi_master_awlen; // ARM_A9_HPS:h2f_lw_AWLEN -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_awlen
wire [11:0] arm_a9_hps_h2f_lw_axi_master_wid; // ARM_A9_HPS:h2f_lw_WID -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_wid
wire [3:0] arm_a9_hps_h2f_lw_axi_master_arcache; // ARM_A9_HPS:h2f_lw_ARCACHE -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_arcache
wire arm_a9_hps_h2f_lw_axi_master_wvalid; // ARM_A9_HPS:h2f_lw_WVALID -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_wvalid
wire [20:0] arm_a9_hps_h2f_lw_axi_master_araddr; // ARM_A9_HPS:h2f_lw_ARADDR -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_araddr
wire [2:0] arm_a9_hps_h2f_lw_axi_master_arprot; // ARM_A9_HPS:h2f_lw_ARPROT -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_arprot
wire [2:0] arm_a9_hps_h2f_lw_axi_master_awprot; // ARM_A9_HPS:h2f_lw_AWPROT -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_awprot
wire [31:0] arm_a9_hps_h2f_lw_axi_master_wdata; // ARM_A9_HPS:h2f_lw_WDATA -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_wdata
wire arm_a9_hps_h2f_lw_axi_master_arvalid; // ARM_A9_HPS:h2f_lw_ARVALID -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_arvalid
wire [3:0] arm_a9_hps_h2f_lw_axi_master_awcache; // ARM_A9_HPS:h2f_lw_AWCACHE -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_awcache
wire [11:0] arm_a9_hps_h2f_lw_axi_master_arid; // ARM_A9_HPS:h2f_lw_ARID -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_arid
wire [1:0] arm_a9_hps_h2f_lw_axi_master_arlock; // ARM_A9_HPS:h2f_lw_ARLOCK -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_arlock
wire [1:0] arm_a9_hps_h2f_lw_axi_master_awlock; // ARM_A9_HPS:h2f_lw_AWLOCK -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_awlock
wire [20:0] arm_a9_hps_h2f_lw_axi_master_awaddr; // ARM_A9_HPS:h2f_lw_AWADDR -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_awaddr
wire [1:0] arm_a9_hps_h2f_lw_axi_master_bresp; // mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_bresp -> ARM_A9_HPS:h2f_lw_BRESP
wire arm_a9_hps_h2f_lw_axi_master_arready; // mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_arready -> ARM_A9_HPS:h2f_lw_ARREADY
wire [31:0] arm_a9_hps_h2f_lw_axi_master_rdata; // mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_rdata -> ARM_A9_HPS:h2f_lw_RDATA
wire arm_a9_hps_h2f_lw_axi_master_awready; // mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_awready -> ARM_A9_HPS:h2f_lw_AWREADY
wire [1:0] arm_a9_hps_h2f_lw_axi_master_arburst; // ARM_A9_HPS:h2f_lw_ARBURST -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_arburst
wire [2:0] arm_a9_hps_h2f_lw_axi_master_arsize; // ARM_A9_HPS:h2f_lw_ARSIZE -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_arsize
wire arm_a9_hps_h2f_lw_axi_master_bready; // ARM_A9_HPS:h2f_lw_BREADY -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_bready
wire arm_a9_hps_h2f_lw_axi_master_rlast; // mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_rlast -> ARM_A9_HPS:h2f_lw_RLAST
wire arm_a9_hps_h2f_lw_axi_master_wlast; // ARM_A9_HPS:h2f_lw_WLAST -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_wlast
wire [1:0] arm_a9_hps_h2f_lw_axi_master_rresp; // mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_rresp -> ARM_A9_HPS:h2f_lw_RRESP
wire [11:0] arm_a9_hps_h2f_lw_axi_master_awid; // ARM_A9_HPS:h2f_lw_AWID -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_awid
wire [11:0] arm_a9_hps_h2f_lw_axi_master_bid; // mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_bid -> ARM_A9_HPS:h2f_lw_BID
wire arm_a9_hps_h2f_lw_axi_master_bvalid; // mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_bvalid -> ARM_A9_HPS:h2f_lw_BVALID
wire [2:0] arm_a9_hps_h2f_lw_axi_master_awsize; // ARM_A9_HPS:h2f_lw_AWSIZE -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_awsize
wire arm_a9_hps_h2f_lw_axi_master_awvalid; // ARM_A9_HPS:h2f_lw_AWVALID -> mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_awvalid
wire arm_a9_hps_h2f_lw_axi_master_rvalid; // mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_rvalid -> ARM_A9_HPS:h2f_lw_RVALID
wire [31:0] video_in_subsystem_top_io_switches_stream_readdata; // mm_interconnect_1:Video_In_Subsystem_top_io_switches_stream_readdata -> Video_In_Subsystem:top_io_switches_stream_readdata
wire [31:0] video_in_subsystem_top_io_switches_stream_address; // Video_In_Subsystem:top_io_switches_stream_address -> mm_interconnect_1:Video_In_Subsystem_top_io_switches_stream_address
wire video_in_subsystem_top_io_switches_stream_read; // Video_In_Subsystem:top_io_switches_stream_read -> mm_interconnect_1:Video_In_Subsystem_top_io_switches_stream_read
wire video_in_subsystem_top_io_ledr_stream_chipselect; // Video_In_Subsystem:top_io_ledr_stream_chipselect -> mm_interconnect_1:Video_In_Subsystem_top_io_ledr_stream_chipselect
wire [3:0] video_in_subsystem_top_io_ledr_stream_address; // Video_In_Subsystem:top_io_ledr_stream_address -> mm_interconnect_1:Video_In_Subsystem_top_io_ledr_stream_address
wire [31:0] video_in_subsystem_top_io_ledr_stream_writedata; // Video_In_Subsystem:top_io_ledr_stream_writedata -> mm_interconnect_1:Video_In_Subsystem_top_io_ledr_stream_writedata
wire video_in_subsystem_top_io_ledr_stream_write; // Video_In_Subsystem:top_io_ledr_stream_write_n -> mm_interconnect_1:Video_In_Subsystem_top_io_ledr_stream_write
wire [31:0] mm_interconnect_1_vga_subsystem_char_buffer_control_slave_readdata; // VGA_Subsystem:char_buffer_control_slave_readdata -> mm_interconnect_1:VGA_Subsystem_char_buffer_control_slave_readdata
wire [1:0] mm_interconnect_1_vga_subsystem_char_buffer_control_slave_address; // mm_interconnect_1:VGA_Subsystem_char_buffer_control_slave_address -> VGA_Subsystem:char_buffer_control_slave_address
wire mm_interconnect_1_vga_subsystem_char_buffer_control_slave_read; // mm_interconnect_1:VGA_Subsystem_char_buffer_control_slave_read -> VGA_Subsystem:char_buffer_control_slave_read
wire [3:0] mm_interconnect_1_vga_subsystem_char_buffer_control_slave_byteenable; // mm_interconnect_1:VGA_Subsystem_char_buffer_control_slave_byteenable -> VGA_Subsystem:char_buffer_control_slave_byteenable
wire mm_interconnect_1_vga_subsystem_char_buffer_control_slave_write; // mm_interconnect_1:VGA_Subsystem_char_buffer_control_slave_write -> VGA_Subsystem:char_buffer_control_slave_write
wire [31:0] mm_interconnect_1_vga_subsystem_char_buffer_control_slave_writedata; // mm_interconnect_1:VGA_Subsystem_char_buffer_control_slave_writedata -> VGA_Subsystem:char_buffer_control_slave_writedata
wire [31:0] mm_interconnect_1_sysid_control_slave_readdata; // SysID:readdata -> mm_interconnect_1:SysID_control_slave_readdata
wire [0:0] mm_interconnect_1_sysid_control_slave_address; // mm_interconnect_1:SysID_control_slave_address -> SysID:address
wire mm_interconnect_1_video_in_subsystem_edge_detection_control_slave_chipselect; // mm_interconnect_1:Video_In_Subsystem_edge_detection_control_slave_chipselect -> Video_In_Subsystem:edge_detection_control_slave_chipselect
wire [31:0] mm_interconnect_1_video_in_subsystem_edge_detection_control_slave_readdata; // Video_In_Subsystem:edge_detection_control_slave_readdata -> mm_interconnect_1:Video_In_Subsystem_edge_detection_control_slave_readdata
wire [1:0] mm_interconnect_1_video_in_subsystem_edge_detection_control_slave_address; // mm_interconnect_1:Video_In_Subsystem_edge_detection_control_slave_address -> Video_In_Subsystem:edge_detection_control_slave_address
wire mm_interconnect_1_video_in_subsystem_edge_detection_control_slave_write; // mm_interconnect_1:Video_In_Subsystem_edge_detection_control_slave_write -> Video_In_Subsystem:edge_detection_control_slave_write_n
wire [31:0] mm_interconnect_1_video_in_subsystem_edge_detection_control_slave_writedata; // mm_interconnect_1:Video_In_Subsystem_edge_detection_control_slave_writedata -> Video_In_Subsystem:edge_detection_control_slave_writedata
wire mm_interconnect_1_leds_s1_chipselect; // mm_interconnect_1:LEDs_s1_chipselect -> LEDs:chipselect
wire [31:0] mm_interconnect_1_leds_s1_readdata; // LEDs:readdata -> mm_interconnect_1:LEDs_s1_readdata
wire [1:0] mm_interconnect_1_leds_s1_address; // mm_interconnect_1:LEDs_s1_address -> LEDs:address
wire mm_interconnect_1_leds_s1_write; // mm_interconnect_1:LEDs_s1_write -> LEDs:write_n
wire [31:0] mm_interconnect_1_leds_s1_writedata; // mm_interconnect_1:LEDs_s1_writedata -> LEDs:writedata
wire [31:0] mm_interconnect_1_slider_switches_s1_readdata; // Slider_Switches:readdata -> mm_interconnect_1:Slider_Switches_s1_readdata
wire [1:0] mm_interconnect_1_slider_switches_s1_address; // mm_interconnect_1:Slider_Switches_s1_address -> Slider_Switches:address
wire mm_interconnect_1_pushbuttons_s1_chipselect; // mm_interconnect_1:Pushbuttons_s1_chipselect -> Pushbuttons:chipselect
wire [31:0] mm_interconnect_1_pushbuttons_s1_readdata; // Pushbuttons:readdata -> mm_interconnect_1:Pushbuttons_s1_readdata
wire [1:0] mm_interconnect_1_pushbuttons_s1_address; // mm_interconnect_1:Pushbuttons_s1_address -> Pushbuttons:address
wire mm_interconnect_1_pushbuttons_s1_write; // mm_interconnect_1:Pushbuttons_s1_write -> Pushbuttons:write_n
wire [31:0] mm_interconnect_1_pushbuttons_s1_writedata; // mm_interconnect_1:Pushbuttons_s1_writedata -> Pushbuttons:writedata
wire [31:0] mm_interconnect_1_pixel_dma_addr_translation_slave_readdata; // Pixel_DMA_Addr_Translation:slave_readdata -> mm_interconnect_1:Pixel_DMA_Addr_Translation_slave_readdata
wire mm_interconnect_1_pixel_dma_addr_translation_slave_waitrequest; // Pixel_DMA_Addr_Translation:slave_waitrequest -> mm_interconnect_1:Pixel_DMA_Addr_Translation_slave_waitrequest
wire [1:0] mm_interconnect_1_pixel_dma_addr_translation_slave_address; // mm_interconnect_1:Pixel_DMA_Addr_Translation_slave_address -> Pixel_DMA_Addr_Translation:slave_address
wire mm_interconnect_1_pixel_dma_addr_translation_slave_read; // mm_interconnect_1:Pixel_DMA_Addr_Translation_slave_read -> Pixel_DMA_Addr_Translation:slave_read
wire [3:0] mm_interconnect_1_pixel_dma_addr_translation_slave_byteenable; // mm_interconnect_1:Pixel_DMA_Addr_Translation_slave_byteenable -> Pixel_DMA_Addr_Translation:slave_byteenable
wire mm_interconnect_1_pixel_dma_addr_translation_slave_write; // mm_interconnect_1:Pixel_DMA_Addr_Translation_slave_write -> Pixel_DMA_Addr_Translation:slave_write
wire [31:0] mm_interconnect_1_pixel_dma_addr_translation_slave_writedata; // mm_interconnect_1:Pixel_DMA_Addr_Translation_slave_writedata -> Pixel_DMA_Addr_Translation:slave_writedata
wire [31:0] mm_interconnect_1_video_in_dma_addr_translation_slave_readdata; // Video_In_DMA_Addr_Translation:slave_readdata -> mm_interconnect_1:Video_In_DMA_Addr_Translation_slave_readdata
wire mm_interconnect_1_video_in_dma_addr_translation_slave_waitrequest; // Video_In_DMA_Addr_Translation:slave_waitrequest -> mm_interconnect_1:Video_In_DMA_Addr_Translation_slave_waitrequest
wire [1:0] mm_interconnect_1_video_in_dma_addr_translation_slave_address; // mm_interconnect_1:Video_In_DMA_Addr_Translation_slave_address -> Video_In_DMA_Addr_Translation:slave_address
wire mm_interconnect_1_video_in_dma_addr_translation_slave_read; // mm_interconnect_1:Video_In_DMA_Addr_Translation_slave_read -> Video_In_DMA_Addr_Translation:slave_read
wire [3:0] mm_interconnect_1_video_in_dma_addr_translation_slave_byteenable; // mm_interconnect_1:Video_In_DMA_Addr_Translation_slave_byteenable -> Video_In_DMA_Addr_Translation:slave_byteenable
wire mm_interconnect_1_video_in_dma_addr_translation_slave_write; // mm_interconnect_1:Video_In_DMA_Addr_Translation_slave_write -> Video_In_DMA_Addr_Translation:slave_write
wire [31:0] mm_interconnect_1_video_in_dma_addr_translation_slave_writedata; // mm_interconnect_1:Video_In_DMA_Addr_Translation_slave_writedata -> Video_In_DMA_Addr_Translation:slave_writedata
wire mm_interconnect_1_video_in_subsystem_top_avalon_slave_chipselect; // mm_interconnect_1:Video_In_Subsystem_top_avalon_slave_chipselect -> Video_In_Subsystem:top_avalon_slave_chipselect
wire [31:0] mm_interconnect_1_video_in_subsystem_top_avalon_slave_readdata; // Video_In_Subsystem:top_avalon_slave_readdata -> mm_interconnect_1:Video_In_Subsystem_top_avalon_slave_readdata
wire [15:0] mm_interconnect_1_video_in_subsystem_top_avalon_slave_address; // mm_interconnect_1:Video_In_Subsystem_top_avalon_slave_address -> Video_In_Subsystem:top_avalon_slave_address
wire mm_interconnect_1_video_in_subsystem_top_avalon_slave_write; // mm_interconnect_1:Video_In_Subsystem_top_avalon_slave_write -> Video_In_Subsystem:top_avalon_slave_write_n
wire [31:0] mm_interconnect_1_video_in_subsystem_top_avalon_slave_writedata; // mm_interconnect_1:Video_In_Subsystem_top_avalon_slave_writedata -> Video_In_Subsystem:top_avalon_slave_writedata
wire [31:0] pixel_dma_addr_translation_master_readdata; // mm_interconnect_2:Pixel_DMA_Addr_Translation_master_readdata -> Pixel_DMA_Addr_Translation:master_readdata
wire pixel_dma_addr_translation_master_waitrequest; // mm_interconnect_2:Pixel_DMA_Addr_Translation_master_waitrequest -> Pixel_DMA_Addr_Translation:master_waitrequest
wire [1:0] pixel_dma_addr_translation_master_address; // Pixel_DMA_Addr_Translation:master_address -> mm_interconnect_2:Pixel_DMA_Addr_Translation_master_address
wire [3:0] pixel_dma_addr_translation_master_byteenable; // Pixel_DMA_Addr_Translation:master_byteenable -> mm_interconnect_2:Pixel_DMA_Addr_Translation_master_byteenable
wire pixel_dma_addr_translation_master_read; // Pixel_DMA_Addr_Translation:master_read -> mm_interconnect_2:Pixel_DMA_Addr_Translation_master_read
wire pixel_dma_addr_translation_master_write; // Pixel_DMA_Addr_Translation:master_write -> mm_interconnect_2:Pixel_DMA_Addr_Translation_master_write
wire [31:0] pixel_dma_addr_translation_master_writedata; // Pixel_DMA_Addr_Translation:master_writedata -> mm_interconnect_2:Pixel_DMA_Addr_Translation_master_writedata
wire [31:0] mm_interconnect_2_vga_subsystem_pixel_dma_control_slave_readdata; // VGA_Subsystem:pixel_dma_control_slave_readdata -> mm_interconnect_2:VGA_Subsystem_pixel_dma_control_slave_readdata
wire [1:0] mm_interconnect_2_vga_subsystem_pixel_dma_control_slave_address; // mm_interconnect_2:VGA_Subsystem_pixel_dma_control_slave_address -> VGA_Subsystem:pixel_dma_control_slave_address
wire mm_interconnect_2_vga_subsystem_pixel_dma_control_slave_read; // mm_interconnect_2:VGA_Subsystem_pixel_dma_control_slave_read -> VGA_Subsystem:pixel_dma_control_slave_read
wire [3:0] mm_interconnect_2_vga_subsystem_pixel_dma_control_slave_byteenable; // mm_interconnect_2:VGA_Subsystem_pixel_dma_control_slave_byteenable -> VGA_Subsystem:pixel_dma_control_slave_byteenable
wire mm_interconnect_2_vga_subsystem_pixel_dma_control_slave_write; // mm_interconnect_2:VGA_Subsystem_pixel_dma_control_slave_write -> VGA_Subsystem:pixel_dma_control_slave_write
wire [31:0] mm_interconnect_2_vga_subsystem_pixel_dma_control_slave_writedata; // mm_interconnect_2:VGA_Subsystem_pixel_dma_control_slave_writedata -> VGA_Subsystem:pixel_dma_control_slave_writedata
wire [31:0] video_in_dma_addr_translation_master_readdata; // mm_interconnect_3:Video_In_DMA_Addr_Translation_master_readdata -> Video_In_DMA_Addr_Translation:master_readdata
wire video_in_dma_addr_translation_master_waitrequest; // mm_interconnect_3:Video_In_DMA_Addr_Translation_master_waitrequest -> Video_In_DMA_Addr_Translation:master_waitrequest
wire [1:0] video_in_dma_addr_translation_master_address; // Video_In_DMA_Addr_Translation:master_address -> mm_interconnect_3:Video_In_DMA_Addr_Translation_master_address
wire [3:0] video_in_dma_addr_translation_master_byteenable; // Video_In_DMA_Addr_Translation:master_byteenable -> mm_interconnect_3:Video_In_DMA_Addr_Translation_master_byteenable
wire video_in_dma_addr_translation_master_read; // Video_In_DMA_Addr_Translation:master_read -> mm_interconnect_3:Video_In_DMA_Addr_Translation_master_read
wire video_in_dma_addr_translation_master_write; // Video_In_DMA_Addr_Translation:master_write -> mm_interconnect_3:Video_In_DMA_Addr_Translation_master_write
wire [31:0] video_in_dma_addr_translation_master_writedata; // Video_In_DMA_Addr_Translation:master_writedata -> mm_interconnect_3:Video_In_DMA_Addr_Translation_master_writedata
wire [31:0] mm_interconnect_3_video_in_subsystem_video_in_dma_control_slave_readdata; // Video_In_Subsystem:video_in_dma_control_slave_readdata -> mm_interconnect_3:Video_In_Subsystem_video_in_dma_control_slave_readdata
wire [1:0] mm_interconnect_3_video_in_subsystem_video_in_dma_control_slave_address; // mm_interconnect_3:Video_In_Subsystem_video_in_dma_control_slave_address -> Video_In_Subsystem:video_in_dma_control_slave_address
wire mm_interconnect_3_video_in_subsystem_video_in_dma_control_slave_read; // mm_interconnect_3:Video_In_Subsystem_video_in_dma_control_slave_read -> Video_In_Subsystem:video_in_dma_control_slave_read
wire [3:0] mm_interconnect_3_video_in_subsystem_video_in_dma_control_slave_byteenable; // mm_interconnect_3:Video_In_Subsystem_video_in_dma_control_slave_byteenable -> Video_In_Subsystem:video_in_dma_control_slave_byteenable
wire mm_interconnect_3_video_in_subsystem_video_in_dma_control_slave_write; // mm_interconnect_3:Video_In_Subsystem_video_in_dma_control_slave_write -> Video_In_Subsystem:video_in_dma_control_slave_write
wire [31:0] mm_interconnect_3_video_in_subsystem_video_in_dma_control_slave_writedata; // mm_interconnect_3:Video_In_Subsystem_video_in_dma_control_slave_writedata -> Video_In_Subsystem:video_in_dma_control_slave_writedata
wire irq_mapper_receiver0_irq; // Pushbuttons:irq -> irq_mapper:receiver0_irq
wire [31:0] arm_a9_hps_f2h_irq0_irq; // irq_mapper:sender_irq -> ARM_A9_HPS:f2h_irq_p0
wire [31:0] arm_a9_hps_f2h_irq1_irq; // irq_mapper_001:sender_irq -> ARM_A9_HPS:f2h_irq_p1
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [LEDs:reset_n, Onchip_SRAM:reset, Pixel_DMA_Addr_Translation:reset, Pushbuttons:reset_n, SDRAM:reset_n, Slider_Switches:reset_n, SysID:reset_n, Video_In_DMA_Addr_Translation:reset, mm_interconnect_0:SDRAM_reset_reset_bridge_in_reset_reset, mm_interconnect_0:Video_In_Subsystem_sys_reset_reset_bridge_in_reset_reset, mm_interconnect_1:SysID_reset_reset_bridge_in_reset_reset, mm_interconnect_1:Video_In_Subsystem_sys_reset_reset_bridge_in_reset_reset, mm_interconnect_2:Pixel_DMA_Addr_Translation_reset_reset_bridge_in_reset_reset, mm_interconnect_2:VGA_Subsystem_sys_reset_reset_bridge_in_reset_reset, mm_interconnect_3:Video_In_DMA_Addr_Translation_reset_reset_bridge_in_reset_reset, mm_interconnect_3:Video_In_Subsystem_sys_reset_reset_bridge_in_reset_reset, rst_translator:in_reset]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [Onchip_SRAM:reset_req, rst_translator:reset_req_in]
wire arm_a9_hps_h2f_reset_reset; // ARM_A9_HPS:h2f_rst_n -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0, rst_controller_003:reset_in0]
wire system_pll_reset_source_reset; // System_PLL:reset_source_reset -> [rst_controller:reset_in1, rst_controller_001:reset_in1, rst_controller_002:reset_in1]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> VGA_Subsystem:sys_reset_reset_n
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> Video_In_Subsystem:sys_reset_reset_n
wire rst_controller_003_reset_out_reset; // rst_controller_003:reset_out -> [mm_interconnect_0:ARM_A9_HPS_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_1:ARM_A9_HPS_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset]
Computer_System_ARM_A9_HPS #(
.F2S_Width (2),
.S2F_Width (3)
) arm_a9_hps (
.mem_a (memory_mem_a), // memory.mem_a
.mem_ba (memory_mem_ba), // .mem_ba
.mem_ck (memory_mem_ck), // .mem_ck
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.mem_cke (memory_mem_cke), // .mem_cke
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.mem_we_n (memory_mem_we_n), // .mem_we_n
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.mem_dq (memory_mem_dq), // .mem_dq
.mem_dqs (memory_mem_dqs), // .mem_dqs
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.mem_odt (memory_mem_odt), // .mem_odt
.mem_dm (memory_mem_dm), // .mem_dm
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_io_hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_io_hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_io_hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_io_hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_io_hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_io_hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_io_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_io_hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_io_hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_io_hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_io_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_io_hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_io_hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO41 (hps_io_hps_io_gpio_inst_GPIO41), // .hps_io_gpio_inst_GPIO41
.hps_io_gpio_inst_GPIO48 (hps_io_hps_io_gpio_inst_GPIO48), // .hps_io_gpio_inst_GPIO48
.hps_io_gpio_inst_GPIO53 (hps_io_hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_io_hps_io_gpio_inst_GPIO61), // .hps_io_gpio_inst_GPIO61
.h2f_rst_n (arm_a9_hps_h2f_reset_reset), // h2f_reset.reset_n
.h2f_axi_clk (system_pll_sys_clk_clk), // h2f_axi_clock.clk
.h2f_AWID (arm_a9_hps_h2f_axi_master_awid), // h2f_axi_master.awid
.h2f_AWADDR (arm_a9_hps_h2f_axi_master_awaddr), // .awaddr
.h2f_AWLEN (arm_a9_hps_h2f_axi_master_awlen), // .awlen
.h2f_AWSIZE (arm_a9_hps_h2f_axi_master_awsize), // .awsize
.h2f_AWBURST (arm_a9_hps_h2f_axi_master_awburst), // .awburst
.h2f_AWLOCK (arm_a9_hps_h2f_axi_master_awlock), // .awlock
.h2f_AWCACHE (arm_a9_hps_h2f_axi_master_awcache), // .awcache
.h2f_AWPROT (arm_a9_hps_h2f_axi_master_awprot), // .awprot
.h2f_AWVALID (arm_a9_hps_h2f_axi_master_awvalid), // .awvalid
.h2f_AWREADY (arm_a9_hps_h2f_axi_master_awready), // .awready
.h2f_WID (arm_a9_hps_h2f_axi_master_wid), // .wid
.h2f_WDATA (arm_a9_hps_h2f_axi_master_wdata), // .wdata
.h2f_WSTRB (arm_a9_hps_h2f_axi_master_wstrb), // .wstrb
.h2f_WLAST (arm_a9_hps_h2f_axi_master_wlast), // .wlast
.h2f_WVALID (arm_a9_hps_h2f_axi_master_wvalid), // .wvalid
.h2f_WREADY (arm_a9_hps_h2f_axi_master_wready), // .wready
.h2f_BID (arm_a9_hps_h2f_axi_master_bid), // .bid
.h2f_BRESP (arm_a9_hps_h2f_axi_master_bresp), // .bresp
.h2f_BVALID (arm_a9_hps_h2f_axi_master_bvalid), // .bvalid
.h2f_BREADY (arm_a9_hps_h2f_axi_master_bready), // .bready
.h2f_ARID (arm_a9_hps_h2f_axi_master_arid), // .arid
.h2f_ARADDR (arm_a9_hps_h2f_axi_master_araddr), // .araddr
.h2f_ARLEN (arm_a9_hps_h2f_axi_master_arlen), // .arlen
.h2f_ARSIZE (arm_a9_hps_h2f_axi_master_arsize), // .arsize
.h2f_ARBURST (arm_a9_hps_h2f_axi_master_arburst), // .arburst
.h2f_ARLOCK (arm_a9_hps_h2f_axi_master_arlock), // .arlock
.h2f_ARCACHE (arm_a9_hps_h2f_axi_master_arcache), // .arcache
.h2f_ARPROT (arm_a9_hps_h2f_axi_master_arprot), // .arprot
.h2f_ARVALID (arm_a9_hps_h2f_axi_master_arvalid), // .arvalid
.h2f_ARREADY (arm_a9_hps_h2f_axi_master_arready), // .arready
.h2f_RID (arm_a9_hps_h2f_axi_master_rid), // .rid
.h2f_RDATA (arm_a9_hps_h2f_axi_master_rdata), // .rdata
.h2f_RRESP (arm_a9_hps_h2f_axi_master_rresp), // .rresp
.h2f_RLAST (arm_a9_hps_h2f_axi_master_rlast), // .rlast
.h2f_RVALID (arm_a9_hps_h2f_axi_master_rvalid), // .rvalid
.h2f_RREADY (arm_a9_hps_h2f_axi_master_rready), // .rready
.f2h_axi_clk (system_pll_sys_clk_clk), // f2h_axi_clock.clk
.f2h_AWID (), // f2h_axi_slave.awid
.f2h_AWADDR (), // .awaddr
.f2h_AWLEN (), // .awlen
.f2h_AWSIZE (), // .awsize
.f2h_AWBURST (), // .awburst
.f2h_AWLOCK (), // .awlock
.f2h_AWCACHE (), // .awcache
.f2h_AWPROT (), // .awprot
.f2h_AWVALID (), // .awvalid
.f2h_AWREADY (), // .awready
.f2h_AWUSER (), // .awuser
.f2h_WID (), // .wid
.f2h_WDATA (), // .wdata
.f2h_WSTRB (), // .wstrb
.f2h_WLAST (), // .wlast
.f2h_WVALID (), // .wvalid
.f2h_WREADY (), // .wready
.f2h_BID (), // .bid
.f2h_BRESP (), // .bresp
.f2h_BVALID (), // .bvalid
.f2h_BREADY (), // .bready
.f2h_ARID (), // .arid
.f2h_ARADDR (), // .araddr
.f2h_ARLEN (), // .arlen
.f2h_ARSIZE (), // .arsize
.f2h_ARBURST (), // .arburst
.f2h_ARLOCK (), // .arlock
.f2h_ARCACHE (), // .arcache
.f2h_ARPROT (), // .arprot
.f2h_ARVALID (), // .arvalid
.f2h_ARREADY (), // .arready
.f2h_ARUSER (), // .aruser
.f2h_RID (), // .rid
.f2h_RDATA (), // .rdata
.f2h_RRESP (), // .rresp
.f2h_RLAST (), // .rlast
.f2h_RVALID (), // .rvalid
.f2h_RREADY (), // .rready
.h2f_lw_axi_clk (system_pll_sys_clk_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (arm_a9_hps_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (arm_a9_hps_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (arm_a9_hps_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (arm_a9_hps_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (arm_a9_hps_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (arm_a9_hps_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (arm_a9_hps_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (arm_a9_hps_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (arm_a9_hps_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (arm_a9_hps_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (arm_a9_hps_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (arm_a9_hps_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (arm_a9_hps_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (arm_a9_hps_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (arm_a9_hps_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (arm_a9_hps_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (arm_a9_hps_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (arm_a9_hps_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (arm_a9_hps_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (arm_a9_hps_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (arm_a9_hps_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (arm_a9_hps_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (arm_a9_hps_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (arm_a9_hps_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (arm_a9_hps_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (arm_a9_hps_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (arm_a9_hps_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (arm_a9_hps_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (arm_a9_hps_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (arm_a9_hps_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (arm_a9_hps_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (arm_a9_hps_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (arm_a9_hps_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (arm_a9_hps_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (arm_a9_hps_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (arm_a9_hps_h2f_lw_axi_master_rready), // .rready
.f2h_irq_p0 (arm_a9_hps_f2h_irq0_irq), // f2h_irq0.irq
.f2h_irq_p1 (arm_a9_hps_f2h_irq1_irq) // f2h_irq1.irq
);
Computer_System_LEDs leds (
.clk (system_pll_sys_clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_1_leds_s1_address), // s1.address
.write_n (~mm_interconnect_1_leds_s1_write), // .write_n
.writedata (mm_interconnect_1_leds_s1_writedata), // .writedata
.chipselect (mm_interconnect_1_leds_s1_chipselect), // .chipselect
.readdata (mm_interconnect_1_leds_s1_readdata), // .readdata
.out_port (leds_export) // external_connection.export
);
Computer_System_Onchip_SRAM onchip_sram (
.address (mm_interconnect_0_onchip_sram_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_sram_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_sram_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_sram_s1_write), // .write
.readdata (mm_interconnect_0_onchip_sram_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_sram_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_sram_s1_byteenable), // .byteenable
.address2 (mm_interconnect_0_onchip_sram_s2_address), // s2.address
.chipselect2 (mm_interconnect_0_onchip_sram_s2_chipselect), // .chipselect
.clken2 (mm_interconnect_0_onchip_sram_s2_clken), // .clken
.write2 (mm_interconnect_0_onchip_sram_s2_write), // .write
.readdata2 (mm_interconnect_0_onchip_sram_s2_readdata), // .readdata
.writedata2 (mm_interconnect_0_onchip_sram_s2_writedata), // .writedata
.byteenable2 (mm_interconnect_0_onchip_sram_s2_byteenable), // .byteenable
.clk (system_pll_sys_clk_clk), // clk1.clk
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.freeze (1'b0) // (terminated)
);
altera_up_avalon_video_dma_ctrl_addr_trans #(
.ADDRESS_TRANSLATION_MASK (32'b11000000000000000000000000000000)
) pixel_dma_addr_translation (
.clk (system_pll_sys_clk_clk), // clock.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.slave_address (mm_interconnect_1_pixel_dma_addr_translation_slave_address), // slave.address
.slave_byteenable (mm_interconnect_1_pixel_dma_addr_translation_slave_byteenable), // .byteenable
.slave_read (mm_interconnect_1_pixel_dma_addr_translation_slave_read), // .read
.slave_write (mm_interconnect_1_pixel_dma_addr_translation_slave_write), // .write
.slave_writedata (mm_interconnect_1_pixel_dma_addr_translation_slave_writedata), // .writedata
.slave_readdata (mm_interconnect_1_pixel_dma_addr_translation_slave_readdata), // .readdata
.slave_waitrequest (mm_interconnect_1_pixel_dma_addr_translation_slave_waitrequest), // .waitrequest
.master_readdata (pixel_dma_addr_translation_master_readdata), // master.readdata
.master_waitrequest (pixel_dma_addr_translation_master_waitrequest), // .waitrequest
.master_address (pixel_dma_addr_translation_master_address), // .address
.master_byteenable (pixel_dma_addr_translation_master_byteenable), // .byteenable
.master_read (pixel_dma_addr_translation_master_read), // .read
.master_write (pixel_dma_addr_translation_master_write), // .write
.master_writedata (pixel_dma_addr_translation_master_writedata) // .writedata
);
Computer_System_Pushbuttons pushbuttons (
.clk (system_pll_sys_clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_1_pushbuttons_s1_address), // s1.address
.write_n (~mm_interconnect_1_pushbuttons_s1_write), // .write_n
.writedata (mm_interconnect_1_pushbuttons_s1_writedata), // .writedata
.chipselect (mm_interconnect_1_pushbuttons_s1_chipselect), // .chipselect
.readdata (mm_interconnect_1_pushbuttons_s1_readdata), // .readdata
.in_port (pushbuttons_export), // external_connection.export
.irq (irq_mapper_receiver0_irq) // irq.irq
);
Computer_System_SDRAM sdram (
.clk (system_pll_sys_clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.az_addr (mm_interconnect_0_sdram_s1_address), // s1.address
.az_be_n (~mm_interconnect_0_sdram_s1_byteenable), // .byteenable_n
.az_cs (mm_interconnect_0_sdram_s1_chipselect), // .chipselect
.az_data (mm_interconnect_0_sdram_s1_writedata), // .writedata
.az_rd_n (~mm_interconnect_0_sdram_s1_read), // .read_n
.az_wr_n (~mm_interconnect_0_sdram_s1_write), // .write_n
.za_data (mm_interconnect_0_sdram_s1_readdata), // .readdata
.za_valid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.za_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.zs_addr (sdram_addr), // wire.export
.zs_ba (sdram_ba), // .export
.zs_cas_n (sdram_cas_n), // .export
.zs_cke (sdram_cke), // .export
.zs_cs_n (sdram_cs_n), // .export
.zs_dq (sdram_dq), // .export
.zs_dqm (sdram_dqm), // .export
.zs_ras_n (sdram_ras_n), // .export
.zs_we_n (sdram_we_n) // .export
);
Computer_System_Slider_Switches slider_switches (
.clk (system_pll_sys_clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_1_slider_switches_s1_address), // s1.address
.readdata (mm_interconnect_1_slider_switches_s1_readdata), // .readdata
.in_port (slider_switches_export) // external_connection.export
);
Computer_System_SysID sysid (
.clock (system_pll_sys_clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.readdata (mm_interconnect_1_sysid_control_slave_readdata), // control_slave.readdata
.address (mm_interconnect_1_sysid_control_slave_address) // .address
);
Computer_System_System_PLL system_pll (
.ref_clk_clk (system_pll_ref_clk_clk), // ref_clk.clk
.ref_reset_reset (system_pll_ref_reset_reset), // ref_reset.reset
.sys_clk_clk (system_pll_sys_clk_clk), // sys_clk.clk
.sdram_clk_clk (sdram_clk_clk), // sdram_clk.clk
.reset_source_reset (system_pll_reset_source_reset) // reset_source.reset
);
Computer_System_VGA_Subsystem vga_subsystem (
.char_buffer_control_slave_address (mm_interconnect_1_vga_subsystem_char_buffer_control_slave_address), // char_buffer_control_slave.address
.char_buffer_control_slave_byteenable (mm_interconnect_1_vga_subsystem_char_buffer_control_slave_byteenable), // .byteenable
.char_buffer_control_slave_read (mm_interconnect_1_vga_subsystem_char_buffer_control_slave_read), // .read
.char_buffer_control_slave_write (mm_interconnect_1_vga_subsystem_char_buffer_control_slave_write), // .write
.char_buffer_control_slave_writedata (mm_interconnect_1_vga_subsystem_char_buffer_control_slave_writedata), // .writedata
.char_buffer_control_slave_readdata (mm_interconnect_1_vga_subsystem_char_buffer_control_slave_readdata), // .readdata
.char_buffer_slave_address (mm_interconnect_0_vga_subsystem_char_buffer_slave_address), // char_buffer_slave.address
.char_buffer_slave_clken (mm_interconnect_0_vga_subsystem_char_buffer_slave_clken), // .clken
.char_buffer_slave_chipselect (mm_interconnect_0_vga_subsystem_char_buffer_slave_chipselect), // .chipselect
.char_buffer_slave_write (mm_interconnect_0_vga_subsystem_char_buffer_slave_write), // .write
.char_buffer_slave_readdata (mm_interconnect_0_vga_subsystem_char_buffer_slave_readdata), // .readdata
.char_buffer_slave_writedata (mm_interconnect_0_vga_subsystem_char_buffer_slave_writedata), // .writedata
.char_buffer_slave_byteenable (mm_interconnect_0_vga_subsystem_char_buffer_slave_byteenable), // .byteenable
.pixel_dma_control_slave_address (mm_interconnect_2_vga_subsystem_pixel_dma_control_slave_address), // pixel_dma_control_slave.address
.pixel_dma_control_slave_byteenable (mm_interconnect_2_vga_subsystem_pixel_dma_control_slave_byteenable), // .byteenable
.pixel_dma_control_slave_read (mm_interconnect_2_vga_subsystem_pixel_dma_control_slave_read), // .read
.pixel_dma_control_slave_write (mm_interconnect_2_vga_subsystem_pixel_dma_control_slave_write), // .write
.pixel_dma_control_slave_writedata (mm_interconnect_2_vga_subsystem_pixel_dma_control_slave_writedata), // .writedata
.pixel_dma_control_slave_readdata (mm_interconnect_2_vga_subsystem_pixel_dma_control_slave_readdata), // .readdata
.pixel_dma_master_readdatavalid (vga_subsystem_pixel_dma_master_readdatavalid), // pixel_dma_master.readdatavalid
.pixel_dma_master_waitrequest (vga_subsystem_pixel_dma_master_waitrequest), // .waitrequest
.pixel_dma_master_address (vga_subsystem_pixel_dma_master_address), // .address
.pixel_dma_master_lock (vga_subsystem_pixel_dma_master_lock), // .lock
.pixel_dma_master_read (vga_subsystem_pixel_dma_master_read), // .read
.pixel_dma_master_readdata (vga_subsystem_pixel_dma_master_readdata), // .readdata
.sys_clk_clk (system_pll_sys_clk_clk), // sys_clk.clk
.sys_reset_reset_n (~rst_controller_001_reset_out_reset), // sys_reset.reset_n
.vga_CLK (vga_CLK), // vga.CLK
.vga_HS (vga_HS), // .HS
.vga_VS (vga_VS), // .VS
.vga_BLANK (vga_BLANK), // .BLANK
.vga_SYNC (vga_SYNC), // .SYNC
.vga_R (vga_R), // .R
.vga_G (vga_G), // .G
.vga_B (vga_B), // .B
.vga_pll_ref_clk_clk (vga_pll_ref_clk_clk), // vga_pll_ref_clk.clk
.vga_pll_ref_reset_reset (vga_pll_ref_reset_reset) // vga_pll_ref_reset.reset
);
altera_up_avalon_video_dma_ctrl_addr_trans #(
.ADDRESS_TRANSLATION_MASK (32'b11000000000000000000000000000000)
) video_in_dma_addr_translation (
.clk (system_pll_sys_clk_clk), // clock.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.slave_address (mm_interconnect_1_video_in_dma_addr_translation_slave_address), // slave.address
.slave_byteenable (mm_interconnect_1_video_in_dma_addr_translation_slave_byteenable), // .byteenable
.slave_read (mm_interconnect_1_video_in_dma_addr_translation_slave_read), // .read
.slave_write (mm_interconnect_1_video_in_dma_addr_translation_slave_write), // .write
.slave_writedata (mm_interconnect_1_video_in_dma_addr_translation_slave_writedata), // .writedata
.slave_readdata (mm_interconnect_1_video_in_dma_addr_translation_slave_readdata), // .readdata
.slave_waitrequest (mm_interconnect_1_video_in_dma_addr_translation_slave_waitrequest), // .waitrequest
.master_readdata (video_in_dma_addr_translation_master_readdata), // master.readdata
.master_waitrequest (video_in_dma_addr_translation_master_waitrequest), // .waitrequest
.master_address (video_in_dma_addr_translation_master_address), // .address
.master_byteenable (video_in_dma_addr_translation_master_byteenable), // .byteenable
.master_read (video_in_dma_addr_translation_master_read), // .read
.master_write (video_in_dma_addr_translation_master_write), // .write
.master_writedata (video_in_dma_addr_translation_master_writedata) // .writedata
);
Computer_System_Video_In_Subsystem video_in_subsystem (
.edge_detection_control_slave_address (mm_interconnect_1_video_in_subsystem_edge_detection_control_slave_address), // edge_detection_control_slave.address
.edge_detection_control_slave_write_n (~mm_interconnect_1_video_in_subsystem_edge_detection_control_slave_write), // .write_n
.edge_detection_control_slave_writedata (mm_interconnect_1_video_in_subsystem_edge_detection_control_slave_writedata), // .writedata
.edge_detection_control_slave_chipselect (mm_interconnect_1_video_in_subsystem_edge_detection_control_slave_chipselect), // .chipselect
.edge_detection_control_slave_readdata (mm_interconnect_1_video_in_subsystem_edge_detection_control_slave_readdata), // .readdata
.sys_clk_clk (system_pll_sys_clk_clk), // sys_clk.clk
.sys_reset_reset_n (~rst_controller_002_reset_out_reset), // sys_reset.reset_n
.top_avalon_slave_address (mm_interconnect_1_video_in_subsystem_top_avalon_slave_address), // top_avalon_slave.address
.top_avalon_slave_readdata (mm_interconnect_1_video_in_subsystem_top_avalon_slave_readdata), // .readdata
.top_avalon_slave_writedata (mm_interconnect_1_video_in_subsystem_top_avalon_slave_writedata), // .writedata
.top_avalon_slave_write_n (~mm_interconnect_1_video_in_subsystem_top_avalon_slave_write), // .write_n
.top_avalon_slave_chipselect (mm_interconnect_1_video_in_subsystem_top_avalon_slave_chipselect), // .chipselect
.top_io_buff_out_waitrequest (video_in_subsystem_top_io_buff_out_waitrequest), // top_io_buff_out.waitrequest
.top_io_buff_out_address (video_in_subsystem_top_io_buff_out_address), // .address
.top_io_buff_out_write (video_in_subsystem_top_io_buff_out_write), // .write
.top_io_buff_out_writedata (video_in_subsystem_top_io_buff_out_writedata), // .writedata
.top_io_ledr_stream_writedata (video_in_subsystem_top_io_ledr_stream_writedata), // top_io_ledr_stream.writedata
.top_io_ledr_stream_address (video_in_subsystem_top_io_ledr_stream_address), // .address
.top_io_ledr_stream_write_n (video_in_subsystem_top_io_ledr_stream_write), // .write_n
.top_io_ledr_stream_chipselect (video_in_subsystem_top_io_ledr_stream_chipselect), // .chipselect
.top_io_switches_stream_address (video_in_subsystem_top_io_switches_stream_address), // top_io_switches_stream.address
.top_io_switches_stream_readdata (video_in_subsystem_top_io_switches_stream_readdata), // .readdata
.top_io_switches_stream_read (video_in_subsystem_top_io_switches_stream_read), // .read
.video_in_TD_CLK27 (video_in_TD_CLK27), // video_in.TD_CLK27
.video_in_TD_DATA (video_in_TD_DATA), // .TD_DATA
.video_in_TD_HS (video_in_TD_HS), // .TD_HS
.video_in_TD_VS (video_in_TD_VS), // .TD_VS
.video_in_clk27_reset (video_in_clk27_reset), // .clk27_reset
.video_in_TD_RESET (video_in_TD_RESET), // .TD_RESET
.video_in_overflow_flag (video_in_overflow_flag), // .overflow_flag
.video_in_dma_control_slave_address (mm_interconnect_3_video_in_subsystem_video_in_dma_control_slave_address), // video_in_dma_control_slave.address
.video_in_dma_control_slave_byteenable (mm_interconnect_3_video_in_subsystem_video_in_dma_control_slave_byteenable), // .byteenable
.video_in_dma_control_slave_read (mm_interconnect_3_video_in_subsystem_video_in_dma_control_slave_read), // .read
.video_in_dma_control_slave_write (mm_interconnect_3_video_in_subsystem_video_in_dma_control_slave_write), // .write
.video_in_dma_control_slave_writedata (mm_interconnect_3_video_in_subsystem_video_in_dma_control_slave_writedata), // .writedata
.video_in_dma_control_slave_readdata (mm_interconnect_3_video_in_subsystem_video_in_dma_control_slave_readdata), // .readdata
.video_in_dma_master_address (video_in_subsystem_video_in_dma_master_address), // video_in_dma_master.address
.video_in_dma_master_waitrequest (video_in_subsystem_video_in_dma_master_waitrequest), // .waitrequest
.video_in_dma_master_write (video_in_subsystem_video_in_dma_master_write), // .write
.video_in_dma_master_writedata (video_in_subsystem_video_in_dma_master_writedata) // .writedata
);
Computer_System_mm_interconnect_0 mm_interconnect_0 (
.ARM_A9_HPS_h2f_axi_master_awid (arm_a9_hps_h2f_axi_master_awid), // ARM_A9_HPS_h2f_axi_master.awid
.ARM_A9_HPS_h2f_axi_master_awaddr (arm_a9_hps_h2f_axi_master_awaddr), // .awaddr
.ARM_A9_HPS_h2f_axi_master_awlen (arm_a9_hps_h2f_axi_master_awlen), // .awlen
.ARM_A9_HPS_h2f_axi_master_awsize (arm_a9_hps_h2f_axi_master_awsize), // .awsize
.ARM_A9_HPS_h2f_axi_master_awburst (arm_a9_hps_h2f_axi_master_awburst), // .awburst
.ARM_A9_HPS_h2f_axi_master_awlock (arm_a9_hps_h2f_axi_master_awlock), // .awlock
.ARM_A9_HPS_h2f_axi_master_awcache (arm_a9_hps_h2f_axi_master_awcache), // .awcache
.ARM_A9_HPS_h2f_axi_master_awprot (arm_a9_hps_h2f_axi_master_awprot), // .awprot
.ARM_A9_HPS_h2f_axi_master_awvalid (arm_a9_hps_h2f_axi_master_awvalid), // .awvalid
.ARM_A9_HPS_h2f_axi_master_awready (arm_a9_hps_h2f_axi_master_awready), // .awready
.ARM_A9_HPS_h2f_axi_master_wid (arm_a9_hps_h2f_axi_master_wid), // .wid
.ARM_A9_HPS_h2f_axi_master_wdata (arm_a9_hps_h2f_axi_master_wdata), // .wdata
.ARM_A9_HPS_h2f_axi_master_wstrb (arm_a9_hps_h2f_axi_master_wstrb), // .wstrb
.ARM_A9_HPS_h2f_axi_master_wlast (arm_a9_hps_h2f_axi_master_wlast), // .wlast
.ARM_A9_HPS_h2f_axi_master_wvalid (arm_a9_hps_h2f_axi_master_wvalid), // .wvalid
.ARM_A9_HPS_h2f_axi_master_wready (arm_a9_hps_h2f_axi_master_wready), // .wready
.ARM_A9_HPS_h2f_axi_master_bid (arm_a9_hps_h2f_axi_master_bid), // .bid
.ARM_A9_HPS_h2f_axi_master_bresp (arm_a9_hps_h2f_axi_master_bresp), // .bresp
.ARM_A9_HPS_h2f_axi_master_bvalid (arm_a9_hps_h2f_axi_master_bvalid), // .bvalid
.ARM_A9_HPS_h2f_axi_master_bready (arm_a9_hps_h2f_axi_master_bready), // .bready
.ARM_A9_HPS_h2f_axi_master_arid (arm_a9_hps_h2f_axi_master_arid), // .arid
.ARM_A9_HPS_h2f_axi_master_araddr (arm_a9_hps_h2f_axi_master_araddr), // .araddr
.ARM_A9_HPS_h2f_axi_master_arlen (arm_a9_hps_h2f_axi_master_arlen), // .arlen
.ARM_A9_HPS_h2f_axi_master_arsize (arm_a9_hps_h2f_axi_master_arsize), // .arsize
.ARM_A9_HPS_h2f_axi_master_arburst (arm_a9_hps_h2f_axi_master_arburst), // .arburst
.ARM_A9_HPS_h2f_axi_master_arlock (arm_a9_hps_h2f_axi_master_arlock), // .arlock
.ARM_A9_HPS_h2f_axi_master_arcache (arm_a9_hps_h2f_axi_master_arcache), // .arcache
.ARM_A9_HPS_h2f_axi_master_arprot (arm_a9_hps_h2f_axi_master_arprot), // .arprot
.ARM_A9_HPS_h2f_axi_master_arvalid (arm_a9_hps_h2f_axi_master_arvalid), // .arvalid
.ARM_A9_HPS_h2f_axi_master_arready (arm_a9_hps_h2f_axi_master_arready), // .arready
.ARM_A9_HPS_h2f_axi_master_rid (arm_a9_hps_h2f_axi_master_rid), // .rid
.ARM_A9_HPS_h2f_axi_master_rdata (arm_a9_hps_h2f_axi_master_rdata), // .rdata
.ARM_A9_HPS_h2f_axi_master_rresp (arm_a9_hps_h2f_axi_master_rresp), // .rresp
.ARM_A9_HPS_h2f_axi_master_rlast (arm_a9_hps_h2f_axi_master_rlast), // .rlast
.ARM_A9_HPS_h2f_axi_master_rvalid (arm_a9_hps_h2f_axi_master_rvalid), // .rvalid
.ARM_A9_HPS_h2f_axi_master_rready (arm_a9_hps_h2f_axi_master_rready), // .rready
.System_PLL_sys_clk_clk (system_pll_sys_clk_clk), // System_PLL_sys_clk.clk
.ARM_A9_HPS_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_003_reset_out_reset), // ARM_A9_HPS_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.SDRAM_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // SDRAM_reset_reset_bridge_in_reset.reset
.Video_In_Subsystem_sys_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // Video_In_Subsystem_sys_reset_reset_bridge_in_reset.reset
.VGA_Subsystem_pixel_dma_master_address (vga_subsystem_pixel_dma_master_address), // VGA_Subsystem_pixel_dma_master.address
.VGA_Subsystem_pixel_dma_master_waitrequest (vga_subsystem_pixel_dma_master_waitrequest), // .waitrequest
.VGA_Subsystem_pixel_dma_master_read (vga_subsystem_pixel_dma_master_read), // .read
.VGA_Subsystem_pixel_dma_master_readdata (vga_subsystem_pixel_dma_master_readdata), // .readdata
.VGA_Subsystem_pixel_dma_master_readdatavalid (vga_subsystem_pixel_dma_master_readdatavalid), // .readdatavalid
.VGA_Subsystem_pixel_dma_master_lock (vga_subsystem_pixel_dma_master_lock), // .lock
.Video_In_Subsystem_top_io_buff_out_address (video_in_subsystem_top_io_buff_out_address), // Video_In_Subsystem_top_io_buff_out.address
.Video_In_Subsystem_top_io_buff_out_waitrequest (video_in_subsystem_top_io_buff_out_waitrequest), // .waitrequest
.Video_In_Subsystem_top_io_buff_out_write (video_in_subsystem_top_io_buff_out_write), // .write
.Video_In_Subsystem_top_io_buff_out_writedata (video_in_subsystem_top_io_buff_out_writedata), // .writedata
.Video_In_Subsystem_video_in_dma_master_address (video_in_subsystem_video_in_dma_master_address), // Video_In_Subsystem_video_in_dma_master.address
.Video_In_Subsystem_video_in_dma_master_waitrequest (video_in_subsystem_video_in_dma_master_waitrequest), // .waitrequest
.Video_In_Subsystem_video_in_dma_master_write (video_in_subsystem_video_in_dma_master_write), // .write
.Video_In_Subsystem_video_in_dma_master_writedata (video_in_subsystem_video_in_dma_master_writedata), // .writedata
.Onchip_SRAM_s1_address (mm_interconnect_0_onchip_sram_s1_address), // Onchip_SRAM_s1.address
.Onchip_SRAM_s1_write (mm_interconnect_0_onchip_sram_s1_write), // .write
.Onchip_SRAM_s1_readdata (mm_interconnect_0_onchip_sram_s1_readdata), // .readdata
.Onchip_SRAM_s1_writedata (mm_interconnect_0_onchip_sram_s1_writedata), // .writedata
.Onchip_SRAM_s1_byteenable (mm_interconnect_0_onchip_sram_s1_byteenable), // .byteenable
.Onchip_SRAM_s1_chipselect (mm_interconnect_0_onchip_sram_s1_chipselect), // .chipselect
.Onchip_SRAM_s1_clken (mm_interconnect_0_onchip_sram_s1_clken), // .clken
.Onchip_SRAM_s2_address (mm_interconnect_0_onchip_sram_s2_address), // Onchip_SRAM_s2.address
.Onchip_SRAM_s2_write (mm_interconnect_0_onchip_sram_s2_write), // .write
.Onchip_SRAM_s2_readdata (mm_interconnect_0_onchip_sram_s2_readdata), // .readdata
.Onchip_SRAM_s2_writedata (mm_interconnect_0_onchip_sram_s2_writedata), // .writedata
.Onchip_SRAM_s2_byteenable (mm_interconnect_0_onchip_sram_s2_byteenable), // .byteenable
.Onchip_SRAM_s2_chipselect (mm_interconnect_0_onchip_sram_s2_chipselect), // .chipselect
.Onchip_SRAM_s2_clken (mm_interconnect_0_onchip_sram_s2_clken), // .clken
.SDRAM_s1_address (mm_interconnect_0_sdram_s1_address), // SDRAM_s1.address
.SDRAM_s1_write (mm_interconnect_0_sdram_s1_write), // .write
.SDRAM_s1_read (mm_interconnect_0_sdram_s1_read), // .read
.SDRAM_s1_readdata (mm_interconnect_0_sdram_s1_readdata), // .readdata
.SDRAM_s1_writedata (mm_interconnect_0_sdram_s1_writedata), // .writedata
.SDRAM_s1_byteenable (mm_interconnect_0_sdram_s1_byteenable), // .byteenable
.SDRAM_s1_readdatavalid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.SDRAM_s1_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.SDRAM_s1_chipselect (mm_interconnect_0_sdram_s1_chipselect), // .chipselect
.VGA_Subsystem_char_buffer_slave_address (mm_interconnect_0_vga_subsystem_char_buffer_slave_address), // VGA_Subsystem_char_buffer_slave.address
.VGA_Subsystem_char_buffer_slave_write (mm_interconnect_0_vga_subsystem_char_buffer_slave_write), // .write
.VGA_Subsystem_char_buffer_slave_readdata (mm_interconnect_0_vga_subsystem_char_buffer_slave_readdata), // .readdata
.VGA_Subsystem_char_buffer_slave_writedata (mm_interconnect_0_vga_subsystem_char_buffer_slave_writedata), // .writedata
.VGA_Subsystem_char_buffer_slave_byteenable (mm_interconnect_0_vga_subsystem_char_buffer_slave_byteenable), // .byteenable
.VGA_Subsystem_char_buffer_slave_chipselect (mm_interconnect_0_vga_subsystem_char_buffer_slave_chipselect), // .chipselect
.VGA_Subsystem_char_buffer_slave_clken (mm_interconnect_0_vga_subsystem_char_buffer_slave_clken) // .clken
);
Computer_System_mm_interconnect_1 mm_interconnect_1 (
.ARM_A9_HPS_h2f_lw_axi_master_awid (arm_a9_hps_h2f_lw_axi_master_awid), // ARM_A9_HPS_h2f_lw_axi_master.awid
.ARM_A9_HPS_h2f_lw_axi_master_awaddr (arm_a9_hps_h2f_lw_axi_master_awaddr), // .awaddr
.ARM_A9_HPS_h2f_lw_axi_master_awlen (arm_a9_hps_h2f_lw_axi_master_awlen), // .awlen
.ARM_A9_HPS_h2f_lw_axi_master_awsize (arm_a9_hps_h2f_lw_axi_master_awsize), // .awsize
.ARM_A9_HPS_h2f_lw_axi_master_awburst (arm_a9_hps_h2f_lw_axi_master_awburst), // .awburst
.ARM_A9_HPS_h2f_lw_axi_master_awlock (arm_a9_hps_h2f_lw_axi_master_awlock), // .awlock
.ARM_A9_HPS_h2f_lw_axi_master_awcache (arm_a9_hps_h2f_lw_axi_master_awcache), // .awcache
.ARM_A9_HPS_h2f_lw_axi_master_awprot (arm_a9_hps_h2f_lw_axi_master_awprot), // .awprot
.ARM_A9_HPS_h2f_lw_axi_master_awvalid (arm_a9_hps_h2f_lw_axi_master_awvalid), // .awvalid
.ARM_A9_HPS_h2f_lw_axi_master_awready (arm_a9_hps_h2f_lw_axi_master_awready), // .awready
.ARM_A9_HPS_h2f_lw_axi_master_wid (arm_a9_hps_h2f_lw_axi_master_wid), // .wid
.ARM_A9_HPS_h2f_lw_axi_master_wdata (arm_a9_hps_h2f_lw_axi_master_wdata), // .wdata
.ARM_A9_HPS_h2f_lw_axi_master_wstrb (arm_a9_hps_h2f_lw_axi_master_wstrb), // .wstrb
.ARM_A9_HPS_h2f_lw_axi_master_wlast (arm_a9_hps_h2f_lw_axi_master_wlast), // .wlast
.ARM_A9_HPS_h2f_lw_axi_master_wvalid (arm_a9_hps_h2f_lw_axi_master_wvalid), // .wvalid
.ARM_A9_HPS_h2f_lw_axi_master_wready (arm_a9_hps_h2f_lw_axi_master_wready), // .wready
.ARM_A9_HPS_h2f_lw_axi_master_bid (arm_a9_hps_h2f_lw_axi_master_bid), // .bid
.ARM_A9_HPS_h2f_lw_axi_master_bresp (arm_a9_hps_h2f_lw_axi_master_bresp), // .bresp
.ARM_A9_HPS_h2f_lw_axi_master_bvalid (arm_a9_hps_h2f_lw_axi_master_bvalid), // .bvalid
.ARM_A9_HPS_h2f_lw_axi_master_bready (arm_a9_hps_h2f_lw_axi_master_bready), // .bready
.ARM_A9_HPS_h2f_lw_axi_master_arid (arm_a9_hps_h2f_lw_axi_master_arid), // .arid
.ARM_A9_HPS_h2f_lw_axi_master_araddr (arm_a9_hps_h2f_lw_axi_master_araddr), // .araddr
.ARM_A9_HPS_h2f_lw_axi_master_arlen (arm_a9_hps_h2f_lw_axi_master_arlen), // .arlen
.ARM_A9_HPS_h2f_lw_axi_master_arsize (arm_a9_hps_h2f_lw_axi_master_arsize), // .arsize
.ARM_A9_HPS_h2f_lw_axi_master_arburst (arm_a9_hps_h2f_lw_axi_master_arburst), // .arburst
.ARM_A9_HPS_h2f_lw_axi_master_arlock (arm_a9_hps_h2f_lw_axi_master_arlock), // .arlock
.ARM_A9_HPS_h2f_lw_axi_master_arcache (arm_a9_hps_h2f_lw_axi_master_arcache), // .arcache
.ARM_A9_HPS_h2f_lw_axi_master_arprot (arm_a9_hps_h2f_lw_axi_master_arprot), // .arprot
.ARM_A9_HPS_h2f_lw_axi_master_arvalid (arm_a9_hps_h2f_lw_axi_master_arvalid), // .arvalid
.ARM_A9_HPS_h2f_lw_axi_master_arready (arm_a9_hps_h2f_lw_axi_master_arready), // .arready
.ARM_A9_HPS_h2f_lw_axi_master_rid (arm_a9_hps_h2f_lw_axi_master_rid), // .rid
.ARM_A9_HPS_h2f_lw_axi_master_rdata (arm_a9_hps_h2f_lw_axi_master_rdata), // .rdata
.ARM_A9_HPS_h2f_lw_axi_master_rresp (arm_a9_hps_h2f_lw_axi_master_rresp), // .rresp
.ARM_A9_HPS_h2f_lw_axi_master_rlast (arm_a9_hps_h2f_lw_axi_master_rlast), // .rlast
.ARM_A9_HPS_h2f_lw_axi_master_rvalid (arm_a9_hps_h2f_lw_axi_master_rvalid), // .rvalid
.ARM_A9_HPS_h2f_lw_axi_master_rready (arm_a9_hps_h2f_lw_axi_master_rready), // .rready
.System_PLL_sys_clk_clk (system_pll_sys_clk_clk), // System_PLL_sys_clk.clk
.ARM_A9_HPS_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_003_reset_out_reset), // ARM_A9_HPS_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.SysID_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // SysID_reset_reset_bridge_in_reset.reset
.Video_In_Subsystem_sys_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // Video_In_Subsystem_sys_reset_reset_bridge_in_reset.reset
.Video_In_Subsystem_top_io_ledr_stream_address (video_in_subsystem_top_io_ledr_stream_address), // Video_In_Subsystem_top_io_ledr_stream.address
.Video_In_Subsystem_top_io_ledr_stream_chipselect (video_in_subsystem_top_io_ledr_stream_chipselect), // .chipselect
.Video_In_Subsystem_top_io_ledr_stream_write (~video_in_subsystem_top_io_ledr_stream_write), // .write
.Video_In_Subsystem_top_io_ledr_stream_writedata (video_in_subsystem_top_io_ledr_stream_writedata), // .writedata
.Video_In_Subsystem_top_io_switches_stream_address (video_in_subsystem_top_io_switches_stream_address), // Video_In_Subsystem_top_io_switches_stream.address
.Video_In_Subsystem_top_io_switches_stream_read (video_in_subsystem_top_io_switches_stream_read), // .read
.Video_In_Subsystem_top_io_switches_stream_readdata (video_in_subsystem_top_io_switches_stream_readdata), // .readdata
.LEDs_s1_address (mm_interconnect_1_leds_s1_address), // LEDs_s1.address
.LEDs_s1_write (mm_interconnect_1_leds_s1_write), // .write
.LEDs_s1_readdata (mm_interconnect_1_leds_s1_readdata), // .readdata
.LEDs_s1_writedata (mm_interconnect_1_leds_s1_writedata), // .writedata
.LEDs_s1_chipselect (mm_interconnect_1_leds_s1_chipselect), // .chipselect
.Pixel_DMA_Addr_Translation_slave_address (mm_interconnect_1_pixel_dma_addr_translation_slave_address), // Pixel_DMA_Addr_Translation_slave.address
.Pixel_DMA_Addr_Translation_slave_write (mm_interconnect_1_pixel_dma_addr_translation_slave_write), // .write
.Pixel_DMA_Addr_Translation_slave_read (mm_interconnect_1_pixel_dma_addr_translation_slave_read), // .read
.Pixel_DMA_Addr_Translation_slave_readdata (mm_interconnect_1_pixel_dma_addr_translation_slave_readdata), // .readdata
.Pixel_DMA_Addr_Translation_slave_writedata (mm_interconnect_1_pixel_dma_addr_translation_slave_writedata), // .writedata
.Pixel_DMA_Addr_Translation_slave_byteenable (mm_interconnect_1_pixel_dma_addr_translation_slave_byteenable), // .byteenable
.Pixel_DMA_Addr_Translation_slave_waitrequest (mm_interconnect_1_pixel_dma_addr_translation_slave_waitrequest), // .waitrequest
.Pushbuttons_s1_address (mm_interconnect_1_pushbuttons_s1_address), // Pushbuttons_s1.address
.Pushbuttons_s1_write (mm_interconnect_1_pushbuttons_s1_write), // .write
.Pushbuttons_s1_readdata (mm_interconnect_1_pushbuttons_s1_readdata), // .readdata
.Pushbuttons_s1_writedata (mm_interconnect_1_pushbuttons_s1_writedata), // .writedata
.Pushbuttons_s1_chipselect (mm_interconnect_1_pushbuttons_s1_chipselect), // .chipselect
.Slider_Switches_s1_address (mm_interconnect_1_slider_switches_s1_address), // Slider_Switches_s1.address
.Slider_Switches_s1_readdata (mm_interconnect_1_slider_switches_s1_readdata), // .readdata
.SysID_control_slave_address (mm_interconnect_1_sysid_control_slave_address), // SysID_control_slave.address
.SysID_control_slave_readdata (mm_interconnect_1_sysid_control_slave_readdata), // .readdata
.VGA_Subsystem_char_buffer_control_slave_address (mm_interconnect_1_vga_subsystem_char_buffer_control_slave_address), // VGA_Subsystem_char_buffer_control_slave.address
.VGA_Subsystem_char_buffer_control_slave_write (mm_interconnect_1_vga_subsystem_char_buffer_control_slave_write), // .write
.VGA_Subsystem_char_buffer_control_slave_read (mm_interconnect_1_vga_subsystem_char_buffer_control_slave_read), // .read
.VGA_Subsystem_char_buffer_control_slave_readdata (mm_interconnect_1_vga_subsystem_char_buffer_control_slave_readdata), // .readdata
.VGA_Subsystem_char_buffer_control_slave_writedata (mm_interconnect_1_vga_subsystem_char_buffer_control_slave_writedata), // .writedata
.VGA_Subsystem_char_buffer_control_slave_byteenable (mm_interconnect_1_vga_subsystem_char_buffer_control_slave_byteenable), // .byteenable
.Video_In_DMA_Addr_Translation_slave_address (mm_interconnect_1_video_in_dma_addr_translation_slave_address), // Video_In_DMA_Addr_Translation_slave.address
.Video_In_DMA_Addr_Translation_slave_write (mm_interconnect_1_video_in_dma_addr_translation_slave_write), // .write
.Video_In_DMA_Addr_Translation_slave_read (mm_interconnect_1_video_in_dma_addr_translation_slave_read), // .read
.Video_In_DMA_Addr_Translation_slave_readdata (mm_interconnect_1_video_in_dma_addr_translation_slave_readdata), // .readdata
.Video_In_DMA_Addr_Translation_slave_writedata (mm_interconnect_1_video_in_dma_addr_translation_slave_writedata), // .writedata
.Video_In_DMA_Addr_Translation_slave_byteenable (mm_interconnect_1_video_in_dma_addr_translation_slave_byteenable), // .byteenable
.Video_In_DMA_Addr_Translation_slave_waitrequest (mm_interconnect_1_video_in_dma_addr_translation_slave_waitrequest), // .waitrequest
.Video_In_Subsystem_edge_detection_control_slave_address (mm_interconnect_1_video_in_subsystem_edge_detection_control_slave_address), // Video_In_Subsystem_edge_detection_control_slave.address
.Video_In_Subsystem_edge_detection_control_slave_write (mm_interconnect_1_video_in_subsystem_edge_detection_control_slave_write), // .write
.Video_In_Subsystem_edge_detection_control_slave_readdata (mm_interconnect_1_video_in_subsystem_edge_detection_control_slave_readdata), // .readdata
.Video_In_Subsystem_edge_detection_control_slave_writedata (mm_interconnect_1_video_in_subsystem_edge_detection_control_slave_writedata), // .writedata
.Video_In_Subsystem_edge_detection_control_slave_chipselect (mm_interconnect_1_video_in_subsystem_edge_detection_control_slave_chipselect), // .chipselect
.Video_In_Subsystem_top_avalon_slave_address (mm_interconnect_1_video_in_subsystem_top_avalon_slave_address), // Video_In_Subsystem_top_avalon_slave.address
.Video_In_Subsystem_top_avalon_slave_write (mm_interconnect_1_video_in_subsystem_top_avalon_slave_write), // .write
.Video_In_Subsystem_top_avalon_slave_readdata (mm_interconnect_1_video_in_subsystem_top_avalon_slave_readdata), // .readdata
.Video_In_Subsystem_top_avalon_slave_writedata (mm_interconnect_1_video_in_subsystem_top_avalon_slave_writedata), // .writedata
.Video_In_Subsystem_top_avalon_slave_chipselect (mm_interconnect_1_video_in_subsystem_top_avalon_slave_chipselect) // .chipselect
);
Computer_System_mm_interconnect_2 mm_interconnect_2 (
.System_PLL_sys_clk_clk (system_pll_sys_clk_clk), // System_PLL_sys_clk.clk
.Pixel_DMA_Addr_Translation_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // Pixel_DMA_Addr_Translation_reset_reset_bridge_in_reset.reset
.VGA_Subsystem_sys_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // VGA_Subsystem_sys_reset_reset_bridge_in_reset.reset
.Pixel_DMA_Addr_Translation_master_address (pixel_dma_addr_translation_master_address), // Pixel_DMA_Addr_Translation_master.address
.Pixel_DMA_Addr_Translation_master_waitrequest (pixel_dma_addr_translation_master_waitrequest), // .waitrequest
.Pixel_DMA_Addr_Translation_master_byteenable (pixel_dma_addr_translation_master_byteenable), // .byteenable
.Pixel_DMA_Addr_Translation_master_read (pixel_dma_addr_translation_master_read), // .read
.Pixel_DMA_Addr_Translation_master_readdata (pixel_dma_addr_translation_master_readdata), // .readdata
.Pixel_DMA_Addr_Translation_master_write (pixel_dma_addr_translation_master_write), // .write
.Pixel_DMA_Addr_Translation_master_writedata (pixel_dma_addr_translation_master_writedata), // .writedata
.VGA_Subsystem_pixel_dma_control_slave_address (mm_interconnect_2_vga_subsystem_pixel_dma_control_slave_address), // VGA_Subsystem_pixel_dma_control_slave.address
.VGA_Subsystem_pixel_dma_control_slave_write (mm_interconnect_2_vga_subsystem_pixel_dma_control_slave_write), // .write
.VGA_Subsystem_pixel_dma_control_slave_read (mm_interconnect_2_vga_subsystem_pixel_dma_control_slave_read), // .read
.VGA_Subsystem_pixel_dma_control_slave_readdata (mm_interconnect_2_vga_subsystem_pixel_dma_control_slave_readdata), // .readdata
.VGA_Subsystem_pixel_dma_control_slave_writedata (mm_interconnect_2_vga_subsystem_pixel_dma_control_slave_writedata), // .writedata
.VGA_Subsystem_pixel_dma_control_slave_byteenable (mm_interconnect_2_vga_subsystem_pixel_dma_control_slave_byteenable) // .byteenable
);
Computer_System_mm_interconnect_3 mm_interconnect_3 (
.System_PLL_sys_clk_clk (system_pll_sys_clk_clk), // System_PLL_sys_clk.clk
.Video_In_DMA_Addr_Translation_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // Video_In_DMA_Addr_Translation_reset_reset_bridge_in_reset.reset
.Video_In_Subsystem_sys_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // Video_In_Subsystem_sys_reset_reset_bridge_in_reset.reset
.Video_In_DMA_Addr_Translation_master_address (video_in_dma_addr_translation_master_address), // Video_In_DMA_Addr_Translation_master.address
.Video_In_DMA_Addr_Translation_master_waitrequest (video_in_dma_addr_translation_master_waitrequest), // .waitrequest
.Video_In_DMA_Addr_Translation_master_byteenable (video_in_dma_addr_translation_master_byteenable), // .byteenable
.Video_In_DMA_Addr_Translation_master_read (video_in_dma_addr_translation_master_read), // .read
.Video_In_DMA_Addr_Translation_master_readdata (video_in_dma_addr_translation_master_readdata), // .readdata
.Video_In_DMA_Addr_Translation_master_write (video_in_dma_addr_translation_master_write), // .write
.Video_In_DMA_Addr_Translation_master_writedata (video_in_dma_addr_translation_master_writedata), // .writedata
.Video_In_Subsystem_video_in_dma_control_slave_address (mm_interconnect_3_video_in_subsystem_video_in_dma_control_slave_address), // Video_In_Subsystem_video_in_dma_control_slave.address
.Video_In_Subsystem_video_in_dma_control_slave_write (mm_interconnect_3_video_in_subsystem_video_in_dma_control_slave_write), // .write
.Video_In_Subsystem_video_in_dma_control_slave_read (mm_interconnect_3_video_in_subsystem_video_in_dma_control_slave_read), // .read
.Video_In_Subsystem_video_in_dma_control_slave_readdata (mm_interconnect_3_video_in_subsystem_video_in_dma_control_slave_readdata), // .readdata
.Video_In_Subsystem_video_in_dma_control_slave_writedata (mm_interconnect_3_video_in_subsystem_video_in_dma_control_slave_writedata), // .writedata
.Video_In_Subsystem_video_in_dma_control_slave_byteenable (mm_interconnect_3_video_in_subsystem_video_in_dma_control_slave_byteenable) // .byteenable
);
Computer_System_irq_mapper irq_mapper (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (arm_a9_hps_f2h_irq0_irq) // sender.irq
);
Computer_System_irq_mapper_001 irq_mapper_001 (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.sender_irq (arm_a9_hps_f2h_irq1_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~arm_a9_hps_h2f_reset_reset), // reset_in0.reset
.reset_in1 (system_pll_reset_source_reset), // reset_in1.reset
.clk (system_pll_sys_clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("none"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~arm_a9_hps_h2f_reset_reset), // reset_in0.reset
.reset_in1 (system_pll_reset_source_reset), // reset_in1.reset
.clk (), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("none"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~arm_a9_hps_h2f_reset_reset), // reset_in0.reset
.reset_in1 (system_pll_reset_source_reset), // reset_in1.reset
.clk (), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_003 (
.reset_in0 (~arm_a9_hps_h2f_reset_reset), // reset_in0.reset
.clk (system_pll_sys_clk_clk), // clk.clk
.reset_out (rst_controller_003_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
//-----------------------------------------------------------------------------
// Title : CIC decimator with dynamically-adjustable decimator
// Project :
//-----------------------------------------------------------------------------
// File : cic_decim.v
// Author : danielot <[email protected]>
// Company :
// Created : 2016-05-03
// Last update: 2016-05-03
// Platform :
// Standard : VHDL'93/02
//-----------------------------------------------------------------------------
// Description: CIC decimator with dinamically adjustable decimation rate
//-----------------------------------------------------------------------------
// Copyright (c) 2016
//-----------------------------------------------------------------------------
// Revisions :
// Date Version Author Description
// 2016-05-03 1.0 danielot Created
//-----------------------------------------------------------------------------
//
// Design based on code available on GNU Radio
// The CIC has a valid signal (act) pipeline that signals when the data is
// filling integrator and comb pipelines. When the decimation strobe
// comes (act_out_i), the data in the last integrator register is sampled
// to the comb stage. However, to allow the decimation strobe to happen in
// a different clock period from the valid input signal, the valid signal
// in the last register is marked as invalid during the decimation. The
// sampling only happens when this register is valid, avoiding data corruption
// from occasional spurious decimation strobes.
module cic_decim
#(
parameter DATAIN_WIDTH = 16,
parameter DATAOUT_WIDTH = DATAIN_WIDTH,
parameter M = 2,
parameter N = 5,
parameter MAXRATE = 64,
parameter BITGROWTH = 35, //N*log2(M*MAXRATE)
// Select 0 to use the default round to minus infinity (floor)
// or 1 to use convergent rounding
parameter ROUND_CONVERGENT = 0
)
(
input clk_i,
input rst_i,
input en_i,
input [DATAIN_WIDTH-1:0] data_i,
output [DATAOUT_WIDTH-1:0] data_o,
input act_i,
input act_out_i,
output val_o
);
localparam DATAOUT_FULL_WIDTH = DATAIN_WIDTH + BITGROWTH;
localparam DATAOUT_EXTRA_BITS = DATAOUT_FULL_WIDTH - DATAOUT_WIDTH;
wire [DATAOUT_FULL_WIDTH-1:0] datain_extended;
reg [DATAOUT_FULL_WIDTH-1:0] integrator [0:N-1];
reg [DATAOUT_FULL_WIDTH-1:0] diffdelay [0:N-1][0:M-1];
reg [DATAOUT_FULL_WIDTH-1:0] pipe [0:N-1];
wire[DATAOUT_FULL_WIDTH-1:0] data_int;
wire[DATAOUT_WIDTH-1:0] data_out;
reg [DATAOUT_WIDTH-1:0] data_out_reg;
reg [DATAOUT_FULL_WIDTH-1:0] sampler = {{1'b0}};
reg val_int = {{1'b0}};
wire val_out;
reg val_out_reg = {{1'b0}};
reg act_int [0:N-1];
reg act_samp;
reg act_comb [0:N-1];
integer i,j;
assign datain_extended = {{(BITGROWTH){data_i[DATAIN_WIDTH-1]}},data_i};
// Integrator sections
always @(posedge clk_i)
if (rst_i)
for (i=0; i<N; i=i+1) begin
integrator[i] <= {{1'b0}};
act_int[i] <= {{1'b0}};
end
else if (en_i) begin
if (act_i) begin
integrator[0] <= integrator[0] + datain_extended;
act_int[0] <= 1'b1;
for (i=1; i<N; i=i+1) begin
integrator[i] <= integrator[i] + integrator[i-1];
act_int[i] <= act_int[i-1];
end
end
else begin
// Clear the act_int flag only when the COMB section acknowledges it
if (act_out_i) begin
act_int[N-1] <= 1'b0;
end
end
end
// Comb sections
always @(posedge clk_i) begin
if (rst_i) begin
sampler <= {{1'b0}};
for (i=0; i<N; i=i+1) begin
pipe[i] <= {{1'b0}};
act_comb[i] <= {{1'b0}};
for (j=0; j<M; j=j+1)
diffdelay[i][j] <= {{1'b0}};
end
act_samp <= 1'b0;
val_int <= 1'b0;
end
else begin
if (en_i) begin
if (act_out_i && act_int[N-1]) begin
sampler <= integrator[N-1];
act_samp <= 1'b1;
diffdelay[0][0] <= sampler;
for (j=1; j<M; j=j+1)
diffdelay[0][j] <= diffdelay[0][j-1];
pipe[0] <= sampler - diffdelay[0][M-1];
act_comb[0] <= act_samp;
for (i=1; i<N; i=i+1) begin
diffdelay[i][0] <= pipe[i-1];
for (j=1; j<M; j=j+1)
diffdelay[i][j] <= diffdelay[i][j-1];
pipe[i] <= pipe[i-1] - diffdelay[i][M-1];
act_comb[i] <= act_comb[i-1];
end
if(N==1)
val_int <= act_samp;
else
val_int <= act_comb[N-2]; //same as act_comb[N-1]
end // if (act_out_i)
else begin
val_int <= 1'b0;
end // else: !if(act_out_i)
end // if (en_i)
end // else: !if(rst_i)
end // always @ (posedge clk_i)
assign data_int = pipe[N-1];
generate
if (DATAOUT_EXTRA_BITS==0) begin
assign data_out = data_int[DATAOUT_FULL_WIDTH-1:0];
end
// Round bits as selected data output width <= computed data output
// width
else if (DATAOUT_EXTRA_BITS > 0) begin
if (ROUND_CONVERGENT) begin
// Round convergent using the algorithm described in
// https://groups.google.com/forum/#!topic/comp.lang.verilog/sRt57P-FJEE
assign data_out = data_int[DATAOUT_FULL_WIDTH-1:DATAOUT_EXTRA_BITS] +
((data_int[DATAOUT_EXTRA_BITS-1:0] == {1'b1, {(DATAOUT_EXTRA_BITS-1){1'b0}}}) ?
data_int[DATAOUT_EXTRA_BITS] : data_int[DATAOUT_EXTRA_BITS-1]);
end
else begin
assign data_out = data_int[DATAOUT_FULL_WIDTH-1:DATAOUT_EXTRA_BITS];
end
end
// Sign-extend bits as selected data output width > computed data output
// width
else begin // DATAOUT_EXTRA_BITS < 0 means we need to sign-extend
assign data_out = {{(DATAOUT_WIDTH-DATAOUT_FULL_WIDTH){data_int[DATAOUT_FULL_WIDTH-1]}}, data_int};
end
endgenerate
assign val_out = val_int;
// Output stage
always @(posedge clk_i) begin
if (rst_i) begin
data_out_reg <= {{1'b0}};
val_out_reg <= {{1'b0}};
end
else begin
if (en_i) begin
data_out_reg <= data_out;
val_out_reg <= val_out;
end
end
end
assign data_o = data_out_reg;
assign val_o = val_out_reg;
endmodule
|
`timescale 1ns/10ps
module DE0_NANO_SOC_QSYS_pll_sys(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(3),
.output_clock_frequency0("100.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("40.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("200.000000 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_2, outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTDDIO_OUT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_out
// ============================================================
// File Name: rgmii_out4.v
// Megafunction Name(s):
// altddio_out
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 176 04/19/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_rgmii_out4 (
aclr,
datain_h,
datain_l,
outclock,
dataout);
input aclr;
input [3:0] datain_h;
input [3:0] datain_l;
input outclock;
output [3:0] dataout;
wire [3:0] sub_wire0;
wire [3:0] dataout = sub_wire0[3:0];
altddio_out altddio_out_component (
.outclock (outclock),
.datain_h (datain_h),
.aclr (aclr),
.datain_l (datain_l),
.dataout (sub_wire0),
.aset (1'b0),
.oe (1'b1),
.outclocken (1'b1));
defparam
altddio_out_component.extend_oe_disable = "UNUSED",
altddio_out_component.intended_device_family = "Stratix II",
altddio_out_component.lpm_type = "altddio_out",
altddio_out_component.oe_reg = "UNUSED",
altddio_out_component.width = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: OE NUMERIC "0"
// Retrieval info: PRIVATE: OE_REG NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
// Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL datain_h[3..0]
// Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL datain_l[3..0]
// Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL dataout[3..0]
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
// Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0
// Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0
// Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4_bb.v TRUE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__SDFRTP_BEHAVIORAL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ms__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTP_BEHAVIORAL_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:03:36 09/24/2013
// Design Name: Comparador
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab3/laboratorio3/test_comparador.v
// Project Name: laboratorio3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Comparador
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_comparador;
// Inputs
reg clock;
reg reset;
reg [3:0] write_value;
reg [3:0] read_value;
reg read_value_reg_en;
// Outputs
wire led_success;
wire led_fail;
// Instantiate the Unit Under Test (UUT)
Comparador uut (
.clock(clock),
.reset(reset),
.write_value(write_value),
.read_value(read_value),
.read_value_reg_en(read_value_reg_en),
.led_success(led_success),
.led_fail(led_fail)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
write_value = 0;
read_value = 0;
read_value_reg_en = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 00:48:00 01/25/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #3 Project
// Module Name: CDC_Input_Synchronizer
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: Clock Domain Crossing Synchronizer
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module CDC_Input_Synchronizer
#(
parameter SYNC_REG_LEN = 2
)
(
// Input Signal
input ASYNC_IN,
// Output Signal
output SYNC_OUT,
// System Signals
input CLK
);
//
// Set a SDC False Path for the async input register so Quartus
// properly reconizes the synchronizer chain and calculates MTBF.
//
(* altera_attribute = {"-name SDC_STATEMENT \"set_false_path -to [get_registers {*|CDC_Input_Synchronizer:*|async_reg}]\""} *)
//
// Asynchronous Input Signal Register
//
reg async_reg;
always @(posedge CLK)
begin
async_reg <= ASYNC_IN;
end
//
// Synchronous Registers
//
genvar i;
generate
begin
if (SYNC_REG_LEN < 1)
begin
assign SYNC_OUT = async_reg;
end
else
begin
reg [SYNC_REG_LEN-1:0] sync_reg;
assign SYNC_OUT = sync_reg[SYNC_REG_LEN-1];
for (i=0; i < SYNC_REG_LEN; i=i+1)
begin : sync_reg_gen
if (i == 0)
begin
always @(posedge CLK)
begin
sync_reg[i] <= async_reg;
end
end
else
begin
always @(posedge CLK)
begin
sync_reg[i] <= sync_reg[i-1];
end
end
end
end
end
endgenerate
endmodule
|
// Raster_Laser_Projector_Video_In_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 203
`timescale 1 ps / 1 ps
module Raster_Laser_Projector_Video_In_avalon_st_adapter #(
parameter inBitsPerSymbol = 8,
parameter inUsePackets = 1,
parameter inDataWidth = 8,
parameter inChannelWidth = 1,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 8,
parameter outChannelWidth = 0,
parameter outErrorWidth = 0,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [7:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
input wire in_0_startofpacket, // .startofpacket
input wire in_0_endofpacket, // .endofpacket
input wire in_0_channel, // .channel
output wire [7:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire out_0_startofpacket, // .startofpacket
output wire out_0_endofpacket // .endofpacket
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 8)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 8)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 8)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
Raster_Laser_Projector_Video_In_avalon_st_adapter_channel_adapter_0 channel_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.in_startofpacket (in_0_startofpacket), // .startofpacket
.in_endofpacket (in_0_endofpacket), // .endofpacket
.in_channel (in_0_channel), // .channel
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_startofpacket (out_0_startofpacket), // .startofpacket
.out_endofpacket (out_0_endofpacket) // .endofpacket
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DFRTP_FUNCTIONAL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr/sky130_fd_sc_ms__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_ms__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ms__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTP_FUNCTIONAL_V |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_pipe_sync.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_sync.v
// Description : PIPE Sync Module for 7 Series Transceiver
// Version : 20.1
//------------------------------------------------------------------------------
// PCIE_TXSYNC_MODE : 0 = Manual TX sync (default).
// : 1 = Auto TX sync.
// PCIE_RXSYNC_MODE : 0 = Manual RX sync (default).
// : 1 = Auto RX sync.
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Sync Module --------------------------------------------------
module PCIEBus_pipe_sync #
(
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe TX buffer enable for Gen3 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter PCIE_LANE = 1, // PCIe lane
parameter PCIE_LINK_SPEED = 3, // PCIe link speed
parameter BYPASS_TXDELAY_ALIGN = 0, // Bypass TX delay align
parameter BYPASS_RXDELAY_ALIGN = 0 // Bypass RX delay align
)
(
//---------- Input -------------------------------------
input SYNC_CLK,
input SYNC_RST_N,
input SYNC_SLAVE,
input SYNC_GEN3,
input SYNC_RATE_IDLE,
input SYNC_MMCM_LOCK,
input SYNC_RXELECIDLE,
input SYNC_RXCDRLOCK,
input SYNC_ACTIVE_LANE,
input SYNC_TXSYNC_START,
input SYNC_TXPHINITDONE,
input SYNC_TXDLYSRESETDONE,
input SYNC_TXPHALIGNDONE,
input SYNC_TXSYNCDONE,
input SYNC_RXSYNC_START,
input SYNC_RXDLYSRESETDONE,
input SYNC_RXPHALIGNDONE_M,
input SYNC_RXPHALIGNDONE_S,
input SYNC_RXSYNC_DONEM_IN,
input SYNC_RXSYNCDONE,
//---------- Output ------------------------------------
output SYNC_TXPHDLYRESET,
output SYNC_TXPHALIGN,
output SYNC_TXPHALIGNEN,
output SYNC_TXPHINIT,
output SYNC_TXDLYBYPASS,
output SYNC_TXDLYSRESET,
output SYNC_TXDLYEN,
output SYNC_TXSYNC_DONE,
output [ 5:0] SYNC_FSM_TX,
output SYNC_RXPHALIGN,
output SYNC_RXPHALIGNEN,
output SYNC_RXDLYBYPASS,
output SYNC_RXDLYSRESET,
output SYNC_RXDLYEN,
output SYNC_RXDDIEN,
output SYNC_RXSYNC_DONEM_OUT,
output SYNC_RXSYNC_DONE,
output [ 6:0] SYNC_FSM_RX
);
//---------- Input Register ----------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg2;
//---------- Output Register ---------------------------
reg txdlyen = 1'd0;
reg txsync_done = 1'd0;
reg [ 5:0] fsm_tx = 6'd0;
reg rxdlyen = 1'd0;
reg rxsync_done = 1'd0;
reg [ 6:0] fsm_rx = 7'd0;
//---------- FSM ---------------------------------------
localparam FSM_TXSYNC_IDLE = 6'b000001;
localparam FSM_MMCM_LOCK = 6'b000010;
localparam FSM_TXSYNC_START = 6'b000100;
localparam FSM_TXPHINITDONE = 6'b001000; // Manual TX sync only
localparam FSM_TXSYNC_DONE1 = 6'b010000;
localparam FSM_TXSYNC_DONE2 = 6'b100000;
localparam FSM_RXSYNC_IDLE = 7'b0000001;
localparam FSM_RXCDRLOCK = 7'b0000010;
localparam FSM_RXSYNC_START = 7'b0000100;
localparam FSM_RXSYNC_DONE1 = 7'b0001000;
localparam FSM_RXSYNC_DONE2 = 7'b0010000;
localparam FSM_RXSYNC_DONES = 7'b0100000;
localparam FSM_RXSYNC_DONEM = 7'b1000000;
//---------- Input FF ----------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
if (!SYNC_RST_N)
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= 1'd0;
rate_idle_reg1 <= 1'd0;
mmcm_lock_reg1 <= 1'd0;
rxelecidle_reg1 <= 1'd0;
rxcdrlock_reg1 <= 1'd0;
txsync_start_reg1 <= 1'd0;
txphinitdone_reg1 <= 1'd0;
txdlysresetdone_reg1 <= 1'd0;
txphaligndone_reg1 <= 1'd0;
txsyncdone_reg1 <= 1'd0;
rxsync_start_reg1 <= 1'd0;
rxdlysresetdone_reg1 <= 1'd0;
rxphaligndone_m_reg1 <= 1'd0;
rxphaligndone_s_reg1 <= 1'd0;
rxsync_donem_reg1 <= 1'd0;
rxsyncdone_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= 1'd0;
rate_idle_reg2 <= 1'd0;
mmcm_lock_reg2 <= 1'd0;
rxelecidle_reg2 <= 1'd0;
rxcdrlock_reg2 <= 1'd0;
txsync_start_reg2 <= 1'd0;
txphinitdone_reg2 <= 1'd0;
txdlysresetdone_reg2 <= 1'd0;
txphaligndone_reg2 <= 1'd0;
txsyncdone_reg2 <= 1'd0;
rxsync_start_reg2 <= 1'd0;
rxdlysresetdone_reg2 <= 1'd0;
rxphaligndone_m_reg2 <= 1'd0;
rxphaligndone_s_reg2 <= 1'd0;
rxsync_donem_reg2 <= 1'd0;
rxsyncdone_reg2 <= 1'd0;
//---------- 3rd Stage FF --------------------------
txsync_start_reg3 <= 1'd0;
txphinitdone_reg3 <= 1'd0;
txdlysresetdone_reg3 <= 1'd0;
txphaligndone_reg3 <= 1'd0;
txsyncdone_reg3 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= SYNC_GEN3;
rate_idle_reg1 <= SYNC_RATE_IDLE;
mmcm_lock_reg1 <= SYNC_MMCM_LOCK;
rxelecidle_reg1 <= SYNC_RXELECIDLE;
rxcdrlock_reg1 <= SYNC_RXCDRLOCK;
txsync_start_reg1 <= SYNC_TXSYNC_START;
txphinitdone_reg1 <= SYNC_TXPHINITDONE;
txdlysresetdone_reg1 <= SYNC_TXDLYSRESETDONE;
txphaligndone_reg1 <= SYNC_TXPHALIGNDONE;
txsyncdone_reg1 <= SYNC_TXSYNCDONE;
rxsync_start_reg1 <= SYNC_RXSYNC_START;
rxdlysresetdone_reg1 <= SYNC_RXDLYSRESETDONE;
rxphaligndone_m_reg1 <= SYNC_RXPHALIGNDONE_M;
rxphaligndone_s_reg1 <= SYNC_RXPHALIGNDONE_S;
rxsync_donem_reg1 <= SYNC_RXSYNC_DONEM_IN;
rxsyncdone_reg1 <= SYNC_RXSYNCDONE;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= gen3_reg1;
rate_idle_reg2 <= rate_idle_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
rxelecidle_reg2 <= rxelecidle_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
txsync_start_reg2 <= txsync_start_reg1;
txphinitdone_reg2 <= txphinitdone_reg1;
txdlysresetdone_reg2 <= txdlysresetdone_reg1;
txphaligndone_reg2 <= txphaligndone_reg1;
txsyncdone_reg2 <= txsyncdone_reg1;
rxsync_start_reg2 <= rxsync_start_reg1;
rxdlysresetdone_reg2 <= rxdlysresetdone_reg1;
rxphaligndone_m_reg2 <= rxphaligndone_m_reg1;
rxphaligndone_s_reg2 <= rxphaligndone_s_reg1;
rxsync_donem_reg2 <= rxsync_donem_reg1;
rxsyncdone_reg2 <= rxsyncdone_reg1;
//---------- 3rd Stage FF --------------------------
txsync_start_reg3 <= txsync_start_reg2;
txphinitdone_reg3 <= txphinitdone_reg2;
txdlysresetdone_reg3 <= txdlysresetdone_reg2;
txphaligndone_reg3 <= txphaligndone_reg2;
txsyncdone_reg3 <= txsyncdone_reg2;
end
end
//---------- Generate TX Sync FSM ----------------------------------------------
generate if ((PCIE_LINK_SPEED == 3) || (PCIE_TXBUF_EN == "FALSE"))
begin : txsync_fsm
//---------- PIPE TX Sync FSM ----------------------------------------------
always @ (posedge SYNC_CLK)
begin
if (!SYNC_RST_N)
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
else
begin
case (fsm_tx)
//---------- Idle State ------------------------
FSM_TXSYNC_IDLE :
begin
//---------- Exiting Reset or Rate Change --
if (txsync_start_reg2)
begin
fsm_tx <= FSM_MMCM_LOCK;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
else
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= txdlyen;
txsync_done <= txsync_done;
end
end
//---------- Check MMCM Lock -------------------
FSM_MMCM_LOCK :
begin
fsm_tx <= (mmcm_lock_reg2 ? FSM_TXSYNC_START : FSM_MMCM_LOCK);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- TX Delay Soft Reset ---------------
FSM_TXSYNC_START :
begin
fsm_tx <= (((!txdlysresetdone_reg3 && txdlysresetdone_reg2) || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE)) ? FSM_TXPHINITDONE : FSM_TXSYNC_START);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- Wait for TX Phase Init Done (Manual Mode Only)
FSM_TXPHINITDONE :
begin
fsm_tx <= (((!txphinitdone_reg3 && txphinitdone_reg2) || (PCIE_TXSYNC_MODE == 1) || (!SYNC_ACTIVE_LANE)) ? FSM_TXSYNC_DONE1 : FSM_TXPHINITDONE);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- Wait for TX Phase Alignment Done --
FSM_TXSYNC_DONE1 :
begin
if (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && !SYNC_SLAVE)
fsm_tx <= ((!txsyncdone_reg3 && txsyncdone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
else
fsm_tx <= ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- Wait for Master TX Delay Alignment Done
FSM_TXSYNC_DONE2 :
begin
if ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) || SYNC_SLAVE || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1)) || (BYPASS_TXDELAY_ALIGN == 1))
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= !SYNC_SLAVE;
txsync_done <= 1'd1;
end
else
begin
fsm_tx <= FSM_TXSYNC_DONE2;
txdlyen <= !SYNC_SLAVE;
txsync_done <= 1'd0;
end
end
//---------- Default State ---------------------
default :
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
endcase
end
end
end
//---------- TX Sync FSM Default------------------------------------------------
else
begin : txsync_fsm_disable
//---------- Default -------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
end
endgenerate
//---------- Generate RX Sync FSM ----------------------------------------------
generate if ((PCIE_LINK_SPEED == 3) && (PCIE_RXBUF_EN == "FALSE"))
begin : rxsync_fsm
//---------- PIPE RX Sync FSM ----------------------------------------------
always @ (posedge SYNC_CLK)
begin
if (!SYNC_RST_N)
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
else
begin
case (fsm_rx)
//---------- Idle State ------------------------
FSM_RXSYNC_IDLE :
begin
//---------- Exiting Rate Change -----------
if (rxsync_start_reg2)
begin
fsm_rx <= FSM_RXCDRLOCK;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Exiting Electrical Idle without Rate Change
else if (gen3_reg2 && rate_idle_reg2 && ((rxelecidle_reg2 == 1'd1) && (rxelecidle_reg1 == 1'd0)))
begin
fsm_rx <= FSM_RXCDRLOCK;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Idle --------------------------
else
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= rxelecidle_reg2 ? 1'd0 : rxdlyen;
rxsync_done <= rxelecidle_reg2 ? 1'd0 : rxsync_done;
end
end
//---------- Wait for RX Electrical Idle Exit and RX CDR Lock
FSM_RXCDRLOCK :
begin
fsm_rx <= ((!rxelecidle_reg2 && rxcdrlock_reg2) ? FSM_RXSYNC_START : FSM_RXCDRLOCK);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Start RX Sync with RX Delay Soft Reset
FSM_RXSYNC_START :
begin
fsm_rx <= ((!rxdlysresetdone_reg2 && rxdlysresetdone_reg1) ? FSM_RXSYNC_DONE1 : FSM_RXSYNC_START);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Wait for RX Phase Alignment Done --
FSM_RXSYNC_DONE1 :
begin
if (SYNC_SLAVE)
begin
fsm_rx <= ((!rxphaligndone_s_reg2 && rxphaligndone_s_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
else
begin
fsm_rx <= ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
end
//---------- Wait for Master RX Delay Alignment Done
FSM_RXSYNC_DONE2 :
begin
if (SYNC_SLAVE)
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd1;
end
else if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1))
begin
fsm_rx <= ((PCIE_LANE == 1) ? FSM_RXSYNC_IDLE : FSM_RXSYNC_DONES);
rxdlyen <= (PCIE_LANE == 1);
rxsync_done <= (PCIE_LANE == 1);
end
else
begin
fsm_rx <= FSM_RXSYNC_DONE2;
rxdlyen <= 1'd1;
rxsync_done <= 1'd0;
end
end
//---------- Wait for Slave RX Phase Alignment Done
FSM_RXSYNC_DONES :
begin
if (!rxphaligndone_s_reg2 && rxphaligndone_s_reg1)
begin
fsm_rx <= FSM_RXSYNC_DONEM;
rxdlyen <= 1'd1;
rxsync_done <= 1'd0;
end
else
begin
fsm_rx <= FSM_RXSYNC_DONES;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
end
//---------- Wait for Master RX Delay Alignment Done
FSM_RXSYNC_DONEM :
begin
if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1))
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd1;
rxsync_done <= 1'd1;
end
else
begin
fsm_rx <= FSM_RXSYNC_DONEM;
rxdlyen <= 1'd1;
rxsync_done <= 1'd0;
end
end
//---------- Default State ---------------------
default :
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
endcase
end
end
end
//---------- RX Sync FSM Default -----------------------------------------------
else
begin : rxsync_fsm_disable
//---------- Default -------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
end
endgenerate
//---------- PIPE Sync Output --------------------------------------------------
assign SYNC_TXPHALIGNEN = ((PCIE_TXSYNC_MODE == 1) || (!gen3_reg2 && (PCIE_TXBUF_EN == "TRUE"))) ? 1'd0 : 1'd1;
assign SYNC_TXDLYBYPASS = 1'd0;
//assign SYNC_TXDLYSRESET = !(((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;
assign SYNC_TXDLYSRESET = (fsm_tx == FSM_TXSYNC_START);
assign SYNC_TXPHDLYRESET = (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;
assign SYNC_TXPHINIT = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXPHINITDONE);
assign SYNC_TXPHALIGN = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXSYNC_DONE1);
assign SYNC_TXDLYEN = PCIE_TXSYNC_MODE ? 1'd0 : txdlyen;
assign SYNC_TXSYNC_DONE = txsync_done;
assign SYNC_FSM_TX = fsm_tx;
assign SYNC_RXPHALIGNEN = ((PCIE_RXSYNC_MODE == 1) || (!gen3_reg2) || (PCIE_RXBUF_EN == "TRUE")) ? 1'd0 : 1'd1;
assign SYNC_RXDLYBYPASS = !gen3_reg2 || (PCIE_RXBUF_EN == "TRUE");
assign SYNC_RXDLYSRESET = (fsm_rx == FSM_RXSYNC_START);
assign SYNC_RXPHALIGN = PCIE_RXSYNC_MODE ? 1'd0 : (!SYNC_SLAVE ? (fsm_rx == FSM_RXSYNC_DONE1) : (rxsync_donem_reg2 && (fsm_rx == FSM_RXSYNC_DONE1)));
assign SYNC_RXDLYEN = PCIE_RXSYNC_MODE ? 1'd0 : rxdlyen;
assign SYNC_RXDDIEN = gen3_reg2 && (PCIE_RXBUF_EN == "FALSE");
assign SYNC_RXSYNC_DONE = rxsync_done;
assign SYNC_RXSYNC_DONEM_OUT = (fsm_rx == FSM_RXSYNC_DONES);
assign SYNC_FSM_RX = fsm_rx;
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon May 26 11:11:49 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim
// /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/clk_193MHz/clk_193MHz_funcsim.v
// Design : clk_193MHz
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* core_generation_info = "clk_193MHz,clk_wiz_v5_1,{component_name=clk_193MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_193MHz
(clk_100MHz,
clk_193MHz,
locked);
input clk_100MHz;
output clk_193MHz;
output locked;
(* IBUF_LOW_PWR *) wire clk_100MHz;
wire clk_193MHz;
wire locked;
clk_193MHzclk_193MHz_clk_wiz U0
(.clk_100MHz(clk_100MHz),
.clk_193MHz(clk_193MHz),
.locked(locked));
endmodule
(* ORIG_REF_NAME = "clk_193MHz_clk_wiz" *)
module clk_193MHzclk_193MHz_clk_wiz
(clk_100MHz,
clk_193MHz,
locked);
input clk_100MHz;
output clk_193MHz;
output locked;
(* IBUF_LOW_PWR *) wire clk_100MHz;
wire clk_100MHz_clk_193MHz;
wire clk_193MHz;
wire clk_193MHz_clk_193MHz;
wire clkfbout_buf_clk_193MHz;
wire clkfbout_clk_193MHz;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* box_type = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_193MHz),
.O(clkfbout_buf_clk_193MHz));
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
(* box_type = "PRIMITIVE" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_100MHz),
.O(clk_100MHz_clk_193MHz));
(* box_type = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_193MHz_clk_193MHz),
.O(clk_193MHz));
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(45.875000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(4.750000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.000000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_193MHz),
.CLKFBOUT(clkfbout_clk_193MHz),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_100MHz_clk_193MHz),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_193MHz_clk_193MHz),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module fileio;
integer in,out,mon;
reg clk;
reg enable;
wire valid;
reg [31:0] din;
reg [31:0] exp;
wire [31:0] dout;
integer statusI,statusO;
dut dut (clk,enable,din,dout,valid);
initial begin
clk = 0;
enable = 0;
din = 0;
exp = 0;
in = $fopen("input.txt","r");
out = $fopen("output.txt","r");
mon = $fopen("monitor.txt","w");
end
always # 1 clk = ~clk;
// DUT input driver code
initial begin
repeat (10) @ (posedge clk);
while ( ! $feof(in)) begin
@ (negedge clk);
enable = 1;
statusI = $fscanf(in,"%h %h\n",din[31:16],din[15:0]);
@ (negedge clk);
enable = 0;
end
repeat (10) @ (posedge clk);
$fclose(in);
$fclose(out);
$fclose(mon);
#100 $finish;
end
// DUT output monitor and compare logic
always @ (posedge clk)
if (valid) begin
$fwrite(mon,"%h %h\n",dout[31:16],dout[15:0]);
statusO = $fscanf(out,"%h %h\n",exp[31:16],exp[15:0]);
if (dout ! == exp) begin
$display("%0dns Error : input and output does not match",$time);
$display(" Got %h",dout);
$display(" Exp %h",exp);
end else begin
$display("%0dns Match : input and output match",$time);
$display(" Got %h",dout);
$display(" Exp %h",exp);
end
end
endmodule
// DUT model
module dut(
input wire clk,enable,
input wire [31:0] din,
output reg [31:0] dout,
output reg valid
);
always @ (posedge clk)
begin
dout <= din + 1;
valid <= enable;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_dtl_pad_r3.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_dtl_pad_r3(j_ad ,req1_oe ,cbu0 ,j_rst_l ,cbu1 ,j_req1_i ,
j_par_data ,serial_in ,spare_out ,j_par_en ,serial_out ,ps_select ,
bypass_enable ,bso ,down_25_buf ,cbd0 ,j_err_i ,jad32 ,jpar_o ,
j_rst_l_o ,so ,j_req5 ,cbd1 ,req5_l ,j_req0 ,j_err ,j_req4 ,jpar ,
spare_in ,por_l_buf ,j_req0_i ,j_req0_en ,vddo ,rst_io_l_buf ,
bsr_si ,ref ,shift_dr_buf ,hiz_l_buf ,rst_val_dn_buf ,update_dr_buf
,req4_l ,jad32_en ,jad32_data ,spare_en ,se_buf ,up_open_buf ,si ,
clk ,mode_ctl_buf ,rst_val_up_buf ,reset_l_buf ,clock_dr_buf ,spare
,sel_bypass_buf );
output [1:0] spare_out ;
input [8:1] cbu0 ;
input [8:1] cbu1 ;
input [1:0] down_25_buf ;
input [8:1] cbd0 ;
input [8:1] cbd1 ;
input [0:0] spare_in ;
input [1:0] por_l_buf ;
input [1:0] rst_io_l_buf ;
input [1:0] shift_dr_buf ;
input [1:0] hiz_l_buf ;
input [1:0] rst_val_dn_buf ;
input [1:0] update_dr_buf ;
input [0:0] spare_en ;
input [1:0] se_buf ;
input [1:0] up_open_buf ;
input [1:0] mode_ctl_buf ;
input [1:0] rst_val_up_buf ;
input [1:0] reset_l_buf ;
input [1:0] clock_dr_buf ;
input [1:0] sel_bypass_buf ;
inout [1:0] spare ;
output serial_out ;
output bso ;
output jad32 ;
output jpar_o ;
output j_rst_l_o ;
output so ;
output req5_l ;
output req4_l ;
input req1_oe ;
input j_req1_i ;
input j_par_data ;
input serial_in ;
input j_par_en ;
input ps_select ;
input bypass_enable ;
input j_err_i ;
input j_req0_i ;
input j_req0_en ;
input vddo ;
input bsr_si ;
input ref ;
input jad32_en ;
input jad32_data ;
input si ;
input clk ;
inout j_ad ;
inout j_rst_l ;
inout j_req5 ;
inout j_req0 ;
inout j_err ;
inout j_req4 ;
inout jpar ;
supply1 vdd ;
supply0 vss ;
wire [9:2] bscan ;
wire [9:2] scan ;
wire [1:0] net109 ;
wire [1:0] net0186 ;
wire [1:0] net0118 ;
wire ck0 ;
wire ck2 ;
wire ck3 ;
wire net245 ;
wire j_req0_o ;
wire req1_in ;
wire net177 ;
wire j_err_o ;
assign req1_in = j_req1_i ;
terminator I166_0_ (
.TERM (net0186[1] ) );
bw_io_dtl_pad I143_1_ (
.cbu ({cbu0 } ),
.cbd ({cbd0 } ),
.bypass_enable (vss ),
.so (scan[5] ),
.por_l (por_l_buf[0] ),
.clock_dr (clock_dr_buf[0] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[0] ),
.clk (ck0 ),
.reset_l (reset_l_buf[0] ),
.hiz_l (hiz_l_buf[0] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[0] ),
.rst_io_l (rst_io_l_buf[0] ),
.rst_val_up (rst_val_up_buf[0] ),
.bso (bscan[5] ),
.serial_out (net109[0] ),
.bsr_si (bscan[9] ),
.rst_val_dn (rst_val_dn_buf[0] ),
.mode_ctl (mode_ctl_buf[0] ),
.si (scan[9] ),
.oe (vdd ),
.data (j_err_i ),
.se (se_buf[0] ),
.up_open (vss ),
.down_25 (vss ),
.to_core (j_err_o ),
.ref (ref ),
.pad (j_err ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[0] ) );
bw_io_dtl_pad I2 (
.cbu ({cbu0 } ),
.cbd ({cbd0 } ),
.bypass_enable (bypass_enable ),
.so (scan[3] ),
.por_l (por_l_buf[0] ),
.clock_dr (clock_dr_buf[0] ),
.bypass_in (vss ),
.serial_in (serial_in ),
.update_dr (update_dr_buf[0] ),
.clk (ck0 ),
.reset_l (reset_l_buf[0] ),
.hiz_l (hiz_l_buf[0] ),
.ps_select (ps_select ),
.out_type (vss ),
.shift_dr (shift_dr_buf[0] ),
.rst_io_l (rst_io_l_buf[0] ),
.rst_val_up (rst_val_up_buf[0] ),
.bso (bscan[3] ),
.serial_out (serial_out ),
.bsr_si (bscan[4] ),
.rst_val_dn (rst_val_dn_buf[0] ),
.mode_ctl (mode_ctl_buf[0] ),
.si (scan[4] ),
.oe (jad32_en ),
.data (jad32_data ),
.se (se_buf[0] ),
.up_open (up_open_buf[0] ),
.down_25 (down_25_buf[0] ),
.to_core (jad32 ),
.ref (ref ),
.pad (j_ad ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[0] ) );
terminator I167_1_ (
.TERM (net0118[0] ) );
terminator I141 (
.TERM (j_req0_o ) );
bw_io_dtl_pad I143_0_ (
.cbu ({cbu0 } ),
.cbd ({cbd0 } ),
.bypass_enable (vss ),
.so (scan[4] ),
.por_l (por_l_buf[0] ),
.clock_dr (clock_dr_buf[0] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[0] ),
.clk (ck0 ),
.reset_l (reset_l_buf[0] ),
.hiz_l (hiz_l_buf[0] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[0] ),
.rst_io_l (rst_io_l_buf[0] ),
.rst_val_up (rst_val_up_buf[0] ),
.bso (bscan[4] ),
.serial_out (net109[1] ),
.bsr_si (bscan[5] ),
.rst_val_dn (rst_val_dn_buf[0] ),
.mode_ctl (mode_ctl_buf[0] ),
.si (scan[5] ),
.oe (j_req0_en ),
.data (j_req0_i ),
.se (se_buf[0] ),
.up_open (vss ),
.down_25 (vss ),
.to_core (j_req0_o ),
.ref (ref ),
.pad (j_req0 ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[0] ) );
terminator I142 (
.TERM (j_err_o ) );
bw_io_dtl_pad I120_1_ (
.cbu ({cbu1 } ),
.cbd ({cbd1 } ),
.bypass_enable (vss ),
.so (scan[2] ),
.por_l (por_l_buf[1] ),
.clock_dr (clock_dr_buf[1] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[1] ),
.clk (ck3 ),
.reset_l (reset_l_buf[1] ),
.hiz_l (hiz_l_buf[1] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[1] ),
.rst_io_l (rst_io_l_buf[1] ),
.rst_val_up (rst_val_up_buf[1] ),
.bso (bscan[2] ),
.serial_out (net0118[0] ),
.bsr_si (bscan[6] ),
.rst_val_dn (rst_val_dn_buf[1] ),
.mode_ctl (mode_ctl_buf[1] ),
.si (scan[6] ),
.oe (vss ),
.data (vdd ),
.se (se_buf[1] ),
.up_open (vss ),
.down_25 (vss ),
.to_core (req5_l ),
.ref (ref ),
.pad (j_req5 ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[1] ) );
terminator I167_0_ (
.TERM (net0118[1] ) );
bw_io_dtl_pad I120_0_ (
.cbu ({cbu1 } ),
.cbd ({cbd1 } ),
.bypass_enable (vss ),
.so (so ),
.por_l (por_l_buf[1] ),
.clock_dr (clock_dr_buf[1] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[1] ),
.clk (ck3 ),
.reset_l (reset_l_buf[1] ),
.hiz_l (hiz_l_buf[1] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[1] ),
.rst_io_l (rst_io_l_buf[1] ),
.rst_val_up (rst_val_up_buf[1] ),
.bso (bso ),
.serial_out (net0118[1] ),
.bsr_si (bscan[2] ),
.rst_val_dn (rst_val_dn_buf[1] ),
.mode_ctl (mode_ctl_buf[1] ),
.si (scan[2] ),
.oe (vss ),
.data (vdd ),
.se (se_buf[1] ),
.up_open (vss ),
.down_25 (vss ),
.to_core (req4_l ),
.ref (ref ),
.pad (j_req4 ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[1] ) );
terminator I164 (
.TERM (net177 ) );
terminator I165 (
.TERM (net245 ) );
bw_io_dtl_pad I41_2_ (
.cbu ({cbu1 } ),
.cbd ({cbd1 } ),
.bypass_enable (vss ),
.so (scan[6] ),
.por_l (por_l_buf[1] ),
.clock_dr (clock_dr_buf[1] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[1] ),
.clk (ck2 ),
.reset_l (reset_l_buf[1] ),
.hiz_l (hiz_l_buf[1] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[1] ),
.rst_io_l (rst_io_l_buf[1] ),
.rst_val_up (rst_val_up_buf[1] ),
.bso (bscan[6] ),
.serial_out (net0186[1] ),
.bsr_si (bscan[7] ),
.rst_val_dn (rst_val_dn_buf[1] ),
.mode_ctl (mode_ctl_buf[1] ),
.si (scan[7] ),
.oe (vss ),
.data (vdd ),
.se (se_buf[1] ),
.up_open (up_open_buf[1] ),
.down_25 (down_25_buf[1] ),
.to_core (j_rst_l_o ),
.ref (ref ),
.pad (j_rst_l ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[1] ) );
bw_io_dtl_pad I41_3_ (
.cbu ({cbu1 } ),
.cbd ({cbd1 } ),
.bypass_enable (vss ),
.so (scan[7] ),
.por_l (por_l_buf[1] ),
.clock_dr (clock_dr_buf[1] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[1] ),
.clk (ck2 ),
.reset_l (reset_l_buf[1] ),
.hiz_l (hiz_l_buf[1] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[1] ),
.rst_io_l (rst_io_l_buf[1] ),
.rst_val_up (rst_val_up_buf[1] ),
.bso (bscan[7] ),
.serial_out (net0186[0] ),
.bsr_si (bscan[8] ),
.rst_val_dn (rst_val_dn_buf[1] ),
.mode_ctl (mode_ctl_buf[1] ),
.si (scan[8] ),
.oe (j_par_en ),
.data (j_par_data ),
.se (se_buf[1] ),
.up_open (up_open_buf[1] ),
.down_25 (down_25_buf[1] ),
.to_core (jpar_o ),
.ref (ref ),
.pad (jpar ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[1] ) );
terminator I163_5_ (
.TERM (net109[0] ) );
terminator I163_4_ (
.TERM (net109[1] ) );
bw_u1_ckbuf_30x I190 (
.clk (ck2 ),
.rclk (clk ) );
bw_u1_ckbuf_28x I191 (
.clk (ck3 ),
.rclk (clk ) );
bw_io_dtl_pad I43 (
.cbu ({cbu0 } ),
.cbd ({cbd0 } ),
.bypass_enable (vss ),
.so (scan[9] ),
.por_l (por_l_buf[0] ),
.clock_dr (clock_dr_buf[0] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[0] ),
.clk (ck0 ),
.reset_l (reset_l_buf[0] ),
.hiz_l (hiz_l_buf[0] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[0] ),
.rst_io_l (rst_io_l_buf[0] ),
.rst_val_up (rst_val_up_buf[0] ),
.bso (bscan[9] ),
.serial_out (net177 ),
.bsr_si (bsr_si ),
.rst_val_dn (rst_val_dn_buf[0] ),
.mode_ctl (mode_ctl_buf[0] ),
.si (si ),
.oe (req1_oe ),
.data (req1_in ),
.se (se_buf[0] ),
.up_open (vss ),
.down_25 (vss ),
.to_core (spare_out[1] ),
.ref (ref ),
.pad (spare[1] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[0] ) );
bw_io_dtl_pad I119 (
.cbu ({cbu1 } ),
.cbd ({cbd1 } ),
.bypass_enable (vss ),
.so (scan[8] ),
.por_l (por_l_buf[1] ),
.clock_dr (clock_dr_buf[1] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[1] ),
.clk (ck2 ),
.reset_l (reset_l_buf[1] ),
.hiz_l (hiz_l_buf[1] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[1] ),
.rst_io_l (rst_io_l_buf[1] ),
.rst_val_up (rst_val_up_buf[1] ),
.bso (bscan[8] ),
.serial_out (net245 ),
.bsr_si (bscan[3] ),
.rst_val_dn (rst_val_dn_buf[1] ),
.mode_ctl (mode_ctl_buf[1] ),
.si (scan[3] ),
.oe (spare_en[0] ),
.data (spare_in[0] ),
.se (se_buf[1] ),
.up_open (up_open_buf[1] ),
.down_25 (down_25_buf[1] ),
.to_core (spare_out[0] ),
.ref (ref ),
.pad (spare[0] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[1] ) );
terminator I166_1_ (
.TERM (net0186[0] ) );
bw_u1_ckbuf_33x I47 (
.clk (ck0 ),
.rclk (clk ) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111A_BLACKBOX_V
`define SKY130_FD_SC_LS__O2111A_BLACKBOX_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2111a (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111A_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISOLATCH_BEHAVIORAL_V
`define SKY130_FD_SC_LP__INPUTISOLATCH_BEHAVIORAL_V
/**
* inputisolatch: Latching input isolator with inverted enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__inputisolatch (
Q ,
D ,
SLEEP_B
);
// Module ports
output Q ;
input D ;
input SLEEP_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SLEEP_B_delayed;
wire D_delayed ;
reg notifier ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, SLEEP_B_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISOLATCH_BEHAVIORAL_V |
//////////////////////////////////////////////////////////////////////////////
//name : server
//input : input_eth_rx:16
//input : input_socket:16
//output : output_socket:16
//output : output_eth_tx:16
//source_file : ../source/server.c
///======
///
///Created by C2CHIP
//////////////////////////////////////////////////////////////////////////////
// Register Allocation
// ===================
// Register Name Size
// 0 put_eth return address 2
// 1 variable i 2
// 2 put_socket return address 2
// 3 variable i 2
// 4 get_eth return address 2
// 5 variable get_eth return value 2
// 6 rdy_eth return address 2
// 7 variable rdy_eth return value 2
// 8 get_socket return address 2
// 9 variable get_socket return value 2
// 10 array 2
// 11 variable checksum 4
// 12 reset_checksum return address 2
// 13 add_checksum return address 2
// 14 variable data 2
// 15 check_checksum return address 2
// 16 variable check_checksum return value 2
// 17 calc_ack return address 2
// 18 variable calc_ack return value 2
// 19 array 2
// 20 array 2
// 21 variable length 2
// 22 variable new_ack_0 2
// 23 variable new_ack_1 2
// 24 variable return_value 2
// 25 put_ethernet_packet return address 2
// 26 array 2
// 27 variable number_of_bytes 2
// 28 variable destination_mac_address_hi 2
// 29 variable destination_mac_address_med 2
// 30 variable destination_mac_address_lo 2
// 31 variable protocol 2
// 32 variable byte 2
// 33 variable index 2
// 34 get_ethernet_packet return address 2
// 35 variable get_ethernet_packet return value 2
// 36 array 2
// 37 variable number_of_bytes 2
// 38 variable index 2
// 39 variable byte 2
// 40 array 2
// 41 array 2
// 42 array 2
// 43 array 2
// 44 array 2
// 45 variable arp_pounsigneder 2
// 46 get_arp_cache return address 2
// 47 variable get_arp_cache return value 2
// 48 variable ip_hi 2
// 49 variable ip_lo 2
// 50 variable number_of_bytes 2
// 51 variable byte 2
// 52 array 2
// 53 variable i 2
// 54 put_ip_packet return address 2
// 55 array 2
// 56 variable total_length 2
// 57 variable protocol 2
// 58 variable ip_hi 2
// 59 variable ip_lo 2
// 60 variable number_of_bytes 2
// 61 variable i 2
// 62 variable arp_cache 2
// 63 get_ip_packet return address 2
// 64 variable get_ip_packet return value 2
// 65 array 2
// 66 variable total_length 2
// 67 variable header_length 2
// 68 variable payload_start 2
// 69 variable payload_length 2
// 70 variable i 2
// 71 variable from 2
// 72 variable to 2
// 73 variable payload_end 2
// 74 variable number_of_bytes 2
// 75 variable remote_ip_hi 2
// 76 variable remote_ip_lo 2
// 77 variable tx_source 2
// 78 variable tx_dest 2
// 79 array 2
// 80 array 2
// 81 array 2
// 82 variable tx_window 2
// 83 variable tx_fin_flag 2
// 84 variable tx_syn_flag 2
// 85 variable tx_rst_flag 2
// 86 variable tx_psh_flag 2
// 87 variable tx_ack_flag 2
// 88 variable tx_urg_flag 2
// 89 variable rx_source 2
// 90 variable rx_dest 2
// 91 array 2
// 92 array 2
// 93 variable rx_fin_flag 2
// 94 variable rx_syn_flag 2
// 95 variable rx_rst_flag 2
// 96 variable rx_ack_flag 2
// 97 put_tcp_packet return address 2
// 98 array 2
// 99 variable tx_length 2
// 100 variable payload_start 2
// 101 variable packet_length 2
// 102 variable index 2
// 103 variable i 2
// 104 variable rx_length 2
// 105 variable rx_start 2
// 106 get_tcp_packet return address 2
// 107 variable get_tcp_packet return value 2
// 108 array 2
// 109 variable number_of_bytes 2
// 110 variable header_length 2
// 111 variable payload_start 2
// 112 variable total_length 2
// 113 variable payload_length 2
// 114 variable tcp_header_length 2
// 115 application_put_data return address 2
// 116 array 2
// 117 variable start 2
// 118 variable length 2
// 119 variable i 2
// 120 variable index 2
// 121 application_get_data return address 2
// 122 variable application_get_data return value 2
// 123 array 2
// 124 variable start 2
// 125 variable i 2
// 126 variable index 2
// 127 variable length 2
// 128 server return address 2
// 129 array 2
// 130 array 2
// 131 variable tx_start 2
// 132 variable tx_length 2
// 133 variable timeout 2
// 134 variable resend_wait 2
// 135 variable bytes 2
// 136 variable index 2
// 137 variable last_state 2
// 138 variable new_rx_data 2
// 139 variable state 2
// 140 temporary_register 2
// 141 temporary_register 2
// 142 temporary_register 2
// 143 temporary_register 4
// 144 temporary_register 4
// 145 temporary_register 4
// 146 temporary_register 2
// 147 temporary_register 2
// 148 temporary_register 1024
// 149 temporary_register 2
// 150 temporary_register 2
// 151 temporary_register 2048
module server(input_eth_rx,input_socket,input_eth_rx_stb,input_socket_stb,output_socket_ack,output_eth_tx_ack,clk,rst,output_socket,output_eth_tx,output_socket_stb,output_eth_tx_stb,input_eth_rx_ack,input_socket_ack);
integer file_count;
real fp_value;
input [15:0] input_eth_rx;
input [15:0] input_socket;
input input_eth_rx_stb;
input input_socket_stb;
input output_socket_ack;
input output_eth_tx_ack;
input clk;
input rst;
output [15:0] output_socket;
output [15:0] output_eth_tx;
output output_socket_stb;
output output_eth_tx_stb;
output input_eth_rx_ack;
output input_socket_ack;
reg [15:0] timer;
reg timer_enable;
reg stage_0_enable;
reg stage_1_enable;
reg stage_2_enable;
reg [11:0] program_counter;
reg [11:0] program_counter_0;
reg [53:0] instruction_0;
reg [5:0] opcode_0;
reg [7:0] dest_0;
reg [7:0] src_0;
reg [7:0] srcb_0;
reg [31:0] literal_0;
reg [11:0] program_counter_1;
reg [5:0] opcode_1;
reg [7:0] dest_1;
reg [31:0] register_1;
reg [31:0] registerb_1;
reg [31:0] literal_1;
reg [7:0] dest_2;
reg [31:0] result_2;
reg write_enable_2;
reg [15:0] address_2;
reg [15:0] data_out_2;
reg [15:0] data_in_2;
reg memory_enable_2;
reg [15:0] address_4;
reg [31:0] data_out_4;
reg [31:0] data_in_4;
reg memory_enable_4;
reg [15:0] s_output_socket_stb;
reg [15:0] s_output_eth_tx_stb;
reg [15:0] s_output_socket;
reg [15:0] s_output_eth_tx;
reg [15:0] s_input_eth_rx_ack;
reg [15:0] s_input_socket_ack;
reg [15:0] memory_2 [2685:0];
reg [53:0] instructions [3551:0];
reg [31:0] registers [151:0];
//////////////////////////////////////////////////////////////////////////////
// INSTRUCTION INITIALIZATION
//
// Initialise the contents of the instruction memory
//
// Intruction Set
// ==============
// 0 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'literal'}
// 1 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_and_link'}
// 2 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'stop'}
// 3 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'move'}
// 4 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'nop'}
// 5 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'eth_tx', 'op': 'write'}
// 6 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'jmp_to_reg'}
// 7 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'socket', 'op': 'write'}
// 8 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'eth_rx', 'op': 'read'}
// 9 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'eth_rx', 'op': 'ready'}
// 10 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'socket', 'op': 'read'}
// 11 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '+'}
// 12 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '&'}
// 13 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_if_false'}
// 14 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '+'}
// 15 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'goto'}
// 16 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': '~'}
// 17 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read_request'}
// 18 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read_wait'}
// 19 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read'}
// 20 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '<'}
// 21 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '!='}
// 22 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_if_true'}
// 23 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_write'}
// 24 {'right': False, 'float': False, 'unsigned': True, 'literal': False, 'file': '/home/amer/Nexys3/TCP3/source/server.h', 'line': 107, 'op': 'report'}
// 25 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '=='}
// 26 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '!='}
// 27 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': '+'}
// 28 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<'}
// 29 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '=='}
// 30 {'float': False, 'literal': True, 'right': False, 'unsigned': True, 'op': '|'}
// 31 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<='}
// 32 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '>>'}
// 33 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<<'}
// 34 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '-'}
// 35 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '-'}
// 36 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '<='}
// 37 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '|'}
// 38 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'socket', 'op': 'ready'}
// 39 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '=='}
// 40 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'file': '/home/amer/Nexys3/TCP3/source/server.h', 'line': 542, 'op': 'report'}
// 41 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'wait_clocks'}
// Intructions
// ===========
initial
begin
instructions[0] = {6'd0, 8'd10, 8'd0, 32'd0};//{'dest': 10, 'literal': 0, 'op': 'literal'}
instructions[1] = {6'd0, 8'd11, 8'd0, 32'd0};//{'dest': 11, 'literal': 0, 'size': 4, 'signed': 4, 'op': 'literal'}
instructions[2] = {6'd0, 8'd40, 8'd0, 32'd520};//{'dest': 40, 'literal': 520, 'op': 'literal'}
instructions[3] = {6'd0, 8'd41, 8'd0, 32'd536};//{'dest': 41, 'literal': 536, 'op': 'literal'}
instructions[4] = {6'd0, 8'd42, 8'd0, 32'd552};//{'dest': 42, 'literal': 552, 'op': 'literal'}
instructions[5] = {6'd0, 8'd43, 8'd0, 32'd568};//{'dest': 43, 'literal': 568, 'op': 'literal'}
instructions[6] = {6'd0, 8'd44, 8'd0, 32'd584};//{'dest': 44, 'literal': 584, 'op': 'literal'}
instructions[7] = {6'd0, 8'd45, 8'd0, 32'd0};//{'dest': 45, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[8] = {6'd0, 8'd75, 8'd0, 32'd0};//{'dest': 75, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[9] = {6'd0, 8'd76, 8'd0, 32'd0};//{'dest': 76, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[10] = {6'd0, 8'd77, 8'd0, 32'd0};//{'dest': 77, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[11] = {6'd0, 8'd78, 8'd0, 32'd0};//{'dest': 78, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[12] = {6'd0, 8'd79, 8'd0, 32'd620};//{'dest': 79, 'literal': 620, 'op': 'literal'}
instructions[13] = {6'd0, 8'd80, 8'd0, 32'd622};//{'dest': 80, 'literal': 622, 'op': 'literal'}
instructions[14] = {6'd0, 8'd81, 8'd0, 32'd624};//{'dest': 81, 'literal': 624, 'op': 'literal'}
instructions[15] = {6'd0, 8'd82, 8'd0, 32'd1460};//{'dest': 82, 'literal': 1460, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[16] = {6'd0, 8'd83, 8'd0, 32'd0};//{'dest': 83, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[17] = {6'd0, 8'd84, 8'd0, 32'd0};//{'dest': 84, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[18] = {6'd0, 8'd85, 8'd0, 32'd0};//{'dest': 85, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[19] = {6'd0, 8'd86, 8'd0, 32'd0};//{'dest': 86, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[20] = {6'd0, 8'd87, 8'd0, 32'd0};//{'dest': 87, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[21] = {6'd0, 8'd88, 8'd0, 32'd0};//{'dest': 88, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[22] = {6'd0, 8'd89, 8'd0, 32'd0};//{'dest': 89, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[23] = {6'd0, 8'd90, 8'd0, 32'd0};//{'dest': 90, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[24] = {6'd0, 8'd91, 8'd0, 32'd626};//{'dest': 91, 'literal': 626, 'op': 'literal'}
instructions[25] = {6'd0, 8'd92, 8'd0, 32'd628};//{'dest': 92, 'literal': 628, 'op': 'literal'}
instructions[26] = {6'd0, 8'd93, 8'd0, 32'd0};//{'dest': 93, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[27] = {6'd0, 8'd94, 8'd0, 32'd0};//{'dest': 94, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[28] = {6'd0, 8'd95, 8'd0, 32'd0};//{'dest': 95, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[29] = {6'd0, 8'd96, 8'd0, 32'd0};//{'dest': 96, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[30] = {6'd0, 8'd104, 8'd0, 32'd0};//{'dest': 104, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[31] = {6'd0, 8'd105, 8'd0, 32'd0};//{'dest': 105, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[32] = {6'd1, 8'd128, 8'd0, 32'd2627};//{'dest': 128, 'label': 2627, 'op': 'jmp_and_link'}
instructions[33] = {6'd2, 8'd0, 8'd0, 32'd0};//{'op': 'stop'}
instructions[34] = {6'd3, 8'd140, 8'd1, 32'd0};//{'dest': 140, 'src': 1, 'op': 'move'}
instructions[35] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[36] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[37] = {6'd5, 8'd0, 8'd140, 32'd0};//{'src': 140, 'output': 'eth_tx', 'op': 'write'}
instructions[38] = {6'd6, 8'd0, 8'd0, 32'd0};//{'src': 0, 'op': 'jmp_to_reg'}
instructions[39] = {6'd3, 8'd140, 8'd3, 32'd0};//{'dest': 140, 'src': 3, 'op': 'move'}
instructions[40] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[41] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[42] = {6'd7, 8'd0, 8'd140, 32'd0};//{'src': 140, 'output': 'socket', 'op': 'write'}
instructions[43] = {6'd6, 8'd0, 8'd2, 32'd0};//{'src': 2, 'op': 'jmp_to_reg'}
instructions[44] = {6'd8, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'eth_rx', 'op': 'read'}
instructions[45] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[46] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[47] = {6'd3, 8'd5, 8'd140, 32'd0};//{'dest': 5, 'src': 140, 'op': 'move'}
instructions[48] = {6'd6, 8'd0, 8'd4, 32'd0};//{'src': 4, 'op': 'jmp_to_reg'}
instructions[49] = {6'd9, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'eth_rx', 'op': 'ready'}
instructions[50] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[51] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[52] = {6'd3, 8'd7, 8'd140, 32'd0};//{'dest': 7, 'src': 140, 'op': 'move'}
instructions[53] = {6'd6, 8'd0, 8'd6, 32'd0};//{'src': 6, 'op': 'jmp_to_reg'}
instructions[54] = {6'd10, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'socket', 'op': 'read'}
instructions[55] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[56] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[57] = {6'd3, 8'd9, 8'd140, 32'd0};//{'dest': 9, 'src': 140, 'op': 'move'}
instructions[58] = {6'd6, 8'd0, 8'd8, 32'd0};//{'src': 8, 'op': 'jmp_to_reg'}
instructions[59] = {6'd0, 8'd143, 8'd0, 32'd0};//{'dest': 143, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[60] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[61] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[62] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[63] = {6'd6, 8'd0, 8'd12, 32'd0};//{'src': 12, 'op': 'jmp_to_reg'}
instructions[64] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[65] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[66] = {6'd3, 8'd145, 8'd14, 32'd0};//{'dest': 145, 'src': 14, 'op': 'move'}
instructions[67] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[68] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[69] = {6'd11, 8'd143, 8'd144, 32'd145};//{'srcb': 145, 'src': 144, 'dest': 143, 'signed': False, 'op': '+', 'type': 'int', 'size': 4}
instructions[70] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[71] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[72] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[73] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[74] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[75] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[76] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[77] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[78] = {6'd12, 8'd143, 8'd144, 32'd65536};//{'src': 144, 'right': 65536, 'dest': 143, 'signed': False, 'op': '&', 'type': 'int', 'size': 4}
instructions[79] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[80] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[81] = {6'd13, 8'd0, 8'd143, 32'd99};//{'src': 143, 'label': 99, 'op': 'jmp_if_false'}
instructions[82] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[83] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[84] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[85] = {6'd12, 8'd143, 8'd144, 32'd65535};//{'src': 144, 'right': 65535, 'dest': 143, 'signed': False, 'op': '&', 'type': 'int', 'size': 4}
instructions[86] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[87] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[88] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[89] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[90] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[91] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[92] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[93] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[94] = {6'd14, 8'd143, 8'd144, 32'd1};//{'src': 144, 'right': 1, 'dest': 143, 'signed': False, 'op': '+', 'type': 'int', 'size': 4}
instructions[95] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[96] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[97] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[98] = {6'd15, 8'd0, 8'd0, 32'd99};//{'label': 99, 'op': 'goto'}
instructions[99] = {6'd6, 8'd0, 8'd13, 32'd0};//{'src': 13, 'op': 'jmp_to_reg'}
instructions[100] = {6'd3, 8'd143, 8'd11, 32'd0};//{'dest': 143, 'src': 11, 'op': 'move'}
instructions[101] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[102] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[103] = {6'd16, 8'd140, 8'd143, 32'd0};//{'dest': 140, 'src': 143, 'op': '~'}
instructions[104] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[105] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[106] = {6'd3, 8'd16, 8'd140, 32'd0};//{'dest': 16, 'src': 140, 'op': 'move'}
instructions[107] = {6'd6, 8'd0, 8'd15, 32'd0};//{'src': 15, 'op': 'jmp_to_reg'}
instructions[108] = {6'd0, 8'd22, 8'd0, 32'd0};//{'dest': 22, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[109] = {6'd0, 8'd23, 8'd0, 32'd0};//{'dest': 23, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[110] = {6'd0, 8'd24, 8'd0, 32'd0};//{'dest': 24, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[111] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[112] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[113] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[114] = {6'd11, 8'd146, 8'd142, 32'd20};//{'dest': 146, 'src': 142, 'srcb': 20, 'signed': False, 'op': '+'}
instructions[115] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[116] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[117] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028726488, 'op': 'memory_read_request'}
instructions[118] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[119] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028726488, 'op': 'memory_read_wait'}
instructions[120] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028726488, 'element_size': 2, 'op': 'memory_read'}
instructions[121] = {6'd3, 8'd142, 8'd21, 32'd0};//{'dest': 142, 'src': 21, 'op': 'move'}
instructions[122] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[123] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[124] = {6'd11, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[125] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[126] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[127] = {6'd3, 8'd22, 8'd140, 32'd0};//{'dest': 22, 'src': 140, 'op': 'move'}
instructions[128] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[130] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[131] = {6'd11, 8'd142, 8'd141, 32'd20};//{'dest': 142, 'src': 141, 'srcb': 20, 'signed': False, 'op': '+'}
instructions[132] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[133] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[134] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 140515028726992, 'op': 'memory_read_request'}
instructions[135] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[136] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 140515028726992, 'op': 'memory_read_wait'}
instructions[137] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 140515028726992, 'element_size': 2, 'op': 'memory_read'}
instructions[138] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[139] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[140] = {6'd3, 8'd23, 8'd140, 32'd0};//{'dest': 23, 'src': 140, 'op': 'move'}
instructions[141] = {6'd3, 8'd141, 8'd22, 32'd0};//{'dest': 141, 'src': 22, 'op': 'move'}
instructions[142] = {6'd3, 8'd142, 8'd21, 32'd0};//{'dest': 142, 'src': 21, 'op': 'move'}
instructions[143] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[144] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[145] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[146] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[147] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[148] = {6'd13, 8'd0, 8'd140, 32'd157};//{'src': 140, 'label': 157, 'op': 'jmp_if_false'}
instructions[149] = {6'd3, 8'd141, 8'd23, 32'd0};//{'dest': 141, 'src': 23, 'op': 'move'}
instructions[150] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[151] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[152] = {6'd14, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[154] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[155] = {6'd3, 8'd23, 8'd140, 32'd0};//{'dest': 23, 'src': 140, 'op': 'move'}
instructions[156] = {6'd15, 8'd0, 8'd0, 32'd157};//{'label': 157, 'op': 'goto'}
instructions[157] = {6'd3, 8'd141, 8'd22, 32'd0};//{'dest': 141, 'src': 22, 'op': 'move'}
instructions[158] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[159] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[160] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[161] = {6'd11, 8'd147, 8'd146, 32'd19};//{'dest': 147, 'src': 146, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[162] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[163] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[164] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028748768, 'op': 'memory_read_request'}
instructions[165] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[166] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028748768, 'op': 'memory_read_wait'}
instructions[167] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140515028748768, 'element_size': 2, 'op': 'memory_read'}
instructions[168] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[170] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[171] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[172] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[173] = {6'd22, 8'd0, 8'd140, 32'd188};//{'src': 140, 'label': 188, 'op': 'jmp_if_true'}
instructions[174] = {6'd3, 8'd141, 8'd23, 32'd0};//{'dest': 141, 'src': 23, 'op': 'move'}
instructions[175] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[176] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[177] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[178] = {6'd11, 8'd147, 8'd146, 32'd19};//{'dest': 147, 'src': 146, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[179] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[180] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[181] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028749056, 'op': 'memory_read_request'}
instructions[182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[183] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028749056, 'op': 'memory_read_wait'}
instructions[184] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140515028749056, 'element_size': 2, 'op': 'memory_read'}
instructions[185] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[186] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[187] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[188] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[189] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[190] = {6'd13, 8'd0, 8'd140, 32'd212};//{'src': 140, 'label': 212, 'op': 'jmp_if_false'}
instructions[191] = {6'd3, 8'd140, 8'd22, 32'd0};//{'dest': 140, 'src': 22, 'op': 'move'}
instructions[192] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[195] = {6'd11, 8'd142, 8'd141, 32'd19};//{'dest': 142, 'src': 141, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[198] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[199] = {6'd3, 8'd140, 8'd23, 32'd0};//{'dest': 140, 'src': 23, 'op': 'move'}
instructions[200] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[201] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[202] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[203] = {6'd11, 8'd142, 8'd141, 32'd19};//{'dest': 142, 'src': 141, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[204] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[205] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[206] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[207] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[208] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[210] = {6'd3, 8'd24, 8'd140, 32'd0};//{'dest': 24, 'src': 140, 'op': 'move'}
instructions[211] = {6'd15, 8'd0, 8'd0, 32'd212};//{'label': 212, 'op': 'goto'}
instructions[212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[213] = {6'd3, 8'd140, 8'd24, 32'd0};//{'dest': 140, 'src': 24, 'op': 'move'}
instructions[214] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[215] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[216] = {6'd3, 8'd18, 8'd140, 32'd0};//{'dest': 18, 'src': 140, 'op': 'move'}
instructions[217] = {6'd6, 8'd0, 8'd17, 32'd0};//{'src': 17, 'op': 'jmp_to_reg'}
instructions[218] = {6'd0, 8'd32, 8'd0, 32'd0};//{'dest': 32, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[219] = {6'd0, 8'd33, 8'd0, 32'd0};//{'dest': 33, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[220] = {6'd3, 8'd140, 8'd27, 32'd0};//{'dest': 140, 'src': 27, 'op': 'move'}
instructions[221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[222] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[223] = {6'd24, 8'd0, 8'd140, 32'd0};//{'src': 140, 'signed': False, 'file': '/home/amer/Nexys3/TCP3/source/server.h', 'line': 107, 'type': 'int', 'op': 'report'}
instructions[224] = {6'd3, 8'd140, 8'd28, 32'd0};//{'dest': 140, 'src': 28, 'op': 'move'}
instructions[225] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[226] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[227] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[228] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[230] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[231] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[232] = {6'd3, 8'd140, 8'd29, 32'd0};//{'dest': 140, 'src': 29, 'op': 'move'}
instructions[233] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[234] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[235] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[236] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[237] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[238] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[239] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[240] = {6'd3, 8'd140, 8'd30, 32'd0};//{'dest': 140, 'src': 30, 'op': 'move'}
instructions[241] = {6'd0, 8'd141, 8'd0, 32'd2};//{'dest': 141, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[242] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[243] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[244] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[245] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[246] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[247] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[248] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[249] = {6'd0, 8'd141, 8'd0, 32'd3};//{'dest': 141, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[250] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[251] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[252] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[253] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[255] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[256] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[257] = {6'd0, 8'd141, 8'd0, 32'd4};//{'dest': 141, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[258] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[260] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[261] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[263] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[264] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[265] = {6'd0, 8'd141, 8'd0, 32'd5};//{'dest': 141, 'literal': 5, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[266] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[268] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[269] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[270] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[271] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[272] = {6'd3, 8'd140, 8'd31, 32'd0};//{'dest': 140, 'src': 31, 'op': 'move'}
instructions[273] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[274] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[275] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[276] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[277] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[278] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[279] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[280] = {6'd3, 8'd141, 8'd27, 32'd0};//{'dest': 141, 'src': 27, 'op': 'move'}
instructions[281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[282] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[283] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[284] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[285] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[286] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[287] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[288] = {6'd3, 8'd33, 8'd140, 32'd0};//{'dest': 33, 'src': 140, 'op': 'move'}
instructions[289] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[291] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[292] = {6'd3, 8'd32, 8'd140, 32'd0};//{'dest': 32, 'src': 140, 'op': 'move'}
instructions[293] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[295] = {6'd3, 8'd141, 8'd32, 32'd0};//{'dest': 141, 'src': 32, 'op': 'move'}
instructions[296] = {6'd3, 8'd142, 8'd27, 32'd0};//{'dest': 142, 'src': 27, 'op': 'move'}
instructions[297] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[298] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[299] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[301] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[302] = {6'd13, 8'd0, 8'd140, 32'd327};//{'src': 140, 'label': 327, 'op': 'jmp_if_false'}
instructions[303] = {6'd3, 8'd142, 8'd33, 32'd0};//{'dest': 142, 'src': 33, 'op': 'move'}
instructions[304] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[305] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[306] = {6'd11, 8'd146, 8'd142, 32'd26};//{'dest': 146, 'src': 142, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[307] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[308] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[309] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028269248, 'op': 'memory_read_request'}
instructions[310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[311] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028269248, 'op': 'memory_read_wait'}
instructions[312] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028269248, 'element_size': 2, 'op': 'memory_read'}
instructions[313] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[314] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[315] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[316] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[317] = {6'd3, 8'd140, 8'd33, 32'd0};//{'dest': 140, 'src': 33, 'op': 'move'}
instructions[318] = {6'd14, 8'd33, 8'd33, 32'd1};//{'src': 33, 'right': 1, 'dest': 33, 'signed': False, 'op': '+', 'size': 2}
instructions[319] = {6'd3, 8'd141, 8'd32, 32'd0};//{'dest': 141, 'src': 32, 'op': 'move'}
instructions[320] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[321] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[322] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[323] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[324] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[325] = {6'd3, 8'd32, 8'd140, 32'd0};//{'dest': 32, 'src': 140, 'op': 'move'}
instructions[326] = {6'd15, 8'd0, 8'd0, 32'd293};//{'label': 293, 'op': 'goto'}
instructions[327] = {6'd6, 8'd0, 8'd25, 32'd0};//{'src': 25, 'op': 'jmp_to_reg'}
instructions[328] = {6'd0, 8'd37, 8'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[329] = {6'd0, 8'd38, 8'd0, 32'd0};//{'dest': 38, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[330] = {6'd0, 8'd39, 8'd0, 32'd0};//{'dest': 39, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[331] = {6'd1, 8'd6, 8'd0, 32'd49};//{'dest': 6, 'label': 49, 'op': 'jmp_and_link'}
instructions[332] = {6'd3, 8'd141, 8'd7, 32'd0};//{'dest': 141, 'src': 7, 'op': 'move'}
instructions[333] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[334] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[335] = {6'd25, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[336] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[337] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[338] = {6'd13, 8'd0, 8'd140, 32'd345};//{'src': 140, 'label': 345, 'op': 'jmp_if_false'}
instructions[339] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[340] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[341] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[342] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[343] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[344] = {6'd15, 8'd0, 8'd0, 32'd345};//{'label': 345, 'op': 'goto'}
instructions[345] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[346] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[347] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[348] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[349] = {6'd3, 8'd37, 8'd140, 32'd0};//{'dest': 37, 'src': 140, 'op': 'move'}
instructions[350] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[351] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[352] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[353] = {6'd3, 8'd38, 8'd140, 32'd0};//{'dest': 38, 'src': 140, 'op': 'move'}
instructions[354] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[355] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[356] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[357] = {6'd3, 8'd39, 8'd140, 32'd0};//{'dest': 39, 'src': 140, 'op': 'move'}
instructions[358] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[359] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[360] = {6'd3, 8'd141, 8'd39, 32'd0};//{'dest': 141, 'src': 39, 'op': 'move'}
instructions[361] = {6'd3, 8'd142, 8'd37, 32'd0};//{'dest': 142, 'src': 37, 'op': 'move'}
instructions[362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[363] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[364] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[365] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[366] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[367] = {6'd13, 8'd0, 8'd140, 32'd387};//{'src': 140, 'label': 387, 'op': 'jmp_if_false'}
instructions[368] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[369] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[370] = {6'd3, 8'd141, 8'd38, 32'd0};//{'dest': 141, 'src': 38, 'op': 'move'}
instructions[371] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[372] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[373] = {6'd11, 8'd142, 8'd141, 32'd36};//{'dest': 142, 'src': 141, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[374] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[376] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[377] = {6'd3, 8'd140, 8'd38, 32'd0};//{'dest': 140, 'src': 38, 'op': 'move'}
instructions[378] = {6'd14, 8'd38, 8'd38, 32'd1};//{'src': 38, 'right': 1, 'dest': 38, 'signed': False, 'op': '+', 'size': 2}
instructions[379] = {6'd3, 8'd141, 8'd39, 32'd0};//{'dest': 141, 'src': 39, 'op': 'move'}
instructions[380] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[381] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[382] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[383] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[384] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[385] = {6'd3, 8'd39, 8'd140, 32'd0};//{'dest': 39, 'src': 140, 'op': 'move'}
instructions[386] = {6'd15, 8'd0, 8'd0, 32'd358};//{'label': 358, 'op': 'goto'}
instructions[387] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[388] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[389] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[390] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[391] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[392] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[393] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028270256, 'op': 'memory_read_request'}
instructions[394] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[395] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028270256, 'op': 'memory_read_wait'}
instructions[396] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028270256, 'element_size': 2, 'op': 'memory_read'}
instructions[397] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[398] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[399] = {6'd26, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[400] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[401] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[402] = {6'd13, 8'd0, 8'd140, 32'd416};//{'src': 140, 'label': 416, 'op': 'jmp_if_false'}
instructions[403] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[404] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[405] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[406] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[407] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[408] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[409] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028270544, 'op': 'memory_read_request'}
instructions[410] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[411] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028270544, 'op': 'memory_read_wait'}
instructions[412] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028270544, 'element_size': 2, 'op': 'memory_read'}
instructions[413] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[414] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[415] = {6'd26, 8'd140, 8'd141, 32'd65535};//{'src': 141, 'right': 65535, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[418] = {6'd13, 8'd0, 8'd140, 32'd425};//{'src': 140, 'label': 425, 'op': 'jmp_if_false'}
instructions[419] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[420] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[421] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[422] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[423] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[424] = {6'd15, 8'd0, 8'd0, 32'd425};//{'label': 425, 'op': 'goto'}
instructions[425] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[426] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[427] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[428] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[429] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[431] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028291664, 'op': 'memory_read_request'}
instructions[432] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[433] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028291664, 'op': 'memory_read_wait'}
instructions[434] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028291664, 'element_size': 2, 'op': 'memory_read'}
instructions[435] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[436] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[437] = {6'd26, 8'd140, 8'd141, 32'd515};//{'src': 141, 'right': 515, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[438] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[439] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[440] = {6'd13, 8'd0, 8'd140, 32'd454};//{'src': 140, 'label': 454, 'op': 'jmp_if_false'}
instructions[441] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[442] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[443] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[444] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[445] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[446] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[447] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028291952, 'op': 'memory_read_request'}
instructions[448] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[449] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028291952, 'op': 'memory_read_wait'}
instructions[450] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028291952, 'element_size': 2, 'op': 'memory_read'}
instructions[451] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[452] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[453] = {6'd26, 8'd140, 8'd141, 32'd65535};//{'src': 141, 'right': 65535, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[454] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[456] = {6'd13, 8'd0, 8'd140, 32'd463};//{'src': 140, 'label': 463, 'op': 'jmp_if_false'}
instructions[457] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[458] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[459] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[460] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[461] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[462] = {6'd15, 8'd0, 8'd0, 32'd463};//{'label': 463, 'op': 'goto'}
instructions[463] = {6'd0, 8'd142, 8'd0, 32'd2};//{'dest': 142, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[464] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[465] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[466] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[467] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[468] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[469] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028292528, 'op': 'memory_read_request'}
instructions[470] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[471] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028292528, 'op': 'memory_read_wait'}
instructions[472] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028292528, 'element_size': 2, 'op': 'memory_read'}
instructions[473] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[474] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[475] = {6'd26, 8'd140, 8'd141, 32'd1029};//{'src': 141, 'right': 1029, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[477] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[478] = {6'd13, 8'd0, 8'd140, 32'd492};//{'src': 140, 'label': 492, 'op': 'jmp_if_false'}
instructions[479] = {6'd0, 8'd142, 8'd0, 32'd2};//{'dest': 142, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[480] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[481] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[482] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[483] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[484] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[485] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028292816, 'op': 'memory_read_request'}
instructions[486] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[487] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028292816, 'op': 'memory_read_wait'}
instructions[488] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028292816, 'element_size': 2, 'op': 'memory_read'}
instructions[489] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[490] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[491] = {6'd26, 8'd140, 8'd141, 32'd65535};//{'src': 141, 'right': 65535, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[492] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[493] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[494] = {6'd13, 8'd0, 8'd140, 32'd501};//{'src': 140, 'label': 501, 'op': 'jmp_if_false'}
instructions[495] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[496] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[497] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[498] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[499] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[500] = {6'd15, 8'd0, 8'd0, 32'd501};//{'label': 501, 'op': 'goto'}
instructions[501] = {6'd0, 8'd142, 8'd0, 32'd6};//{'dest': 142, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[502] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[503] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[504] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[505] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[506] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[507] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028293392, 'op': 'memory_read_request'}
instructions[508] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[509] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028293392, 'op': 'memory_read_wait'}
instructions[510] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028293392, 'element_size': 2, 'op': 'memory_read'}
instructions[511] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[512] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[513] = {6'd25, 8'd140, 8'd141, 32'd2054};//{'src': 141, 'right': 2054, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[514] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[515] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[516] = {6'd13, 8'd0, 8'd140, 32'd749};//{'src': 140, 'label': 749, 'op': 'jmp_if_false'}
instructions[517] = {6'd0, 8'd142, 8'd0, 32'd10};//{'dest': 142, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[518] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[519] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[520] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[521] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[522] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[523] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028293896, 'op': 'memory_read_request'}
instructions[524] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[525] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028293896, 'op': 'memory_read_wait'}
instructions[526] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028293896, 'element_size': 2, 'op': 'memory_read'}
instructions[527] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[528] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[529] = {6'd25, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[531] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[532] = {6'd13, 8'd0, 8'd140, 32'd743};//{'src': 140, 'label': 743, 'op': 'jmp_if_false'}
instructions[533] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[534] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[535] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[536] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[537] = {6'd27, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[538] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[539] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[540] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[541] = {6'd0, 8'd140, 8'd0, 32'd2048};//{'dest': 140, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[542] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[543] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[544] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[545] = {6'd27, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[546] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[547] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[548] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[549] = {6'd0, 8'd140, 8'd0, 32'd1540};//{'dest': 140, 'literal': 1540, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[550] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[551] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[552] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[553] = {6'd27, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[554] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[555] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[556] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[557] = {6'd0, 8'd140, 8'd0, 32'd2};//{'dest': 140, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[558] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[559] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[560] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[561] = {6'd27, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[562] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[563] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[564] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[565] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[566] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[567] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[568] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[569] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[570] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[571] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[572] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[573] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[574] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[575] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[576] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[577] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[578] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[579] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[580] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[581] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[582] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[583] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[584] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[585] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[586] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[587] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[588] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[589] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[590] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[591] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[592] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[593] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[594] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[595] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[596] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[597] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[598] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[599] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[600] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[601] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[602] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[603] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[604] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[605] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[606] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[607] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[608] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[609] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[610] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[611] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028314160, 'op': 'memory_read_request'}
instructions[612] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[613] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028314160, 'op': 'memory_read_wait'}
instructions[614] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028314160, 'element_size': 2, 'op': 'memory_read'}
instructions[615] = {6'd0, 8'd141, 8'd0, 32'd16};//{'dest': 141, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[616] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[617] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[618] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[619] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[620] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[621] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[622] = {6'd0, 8'd146, 8'd0, 32'd12};//{'dest': 146, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[623] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[624] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[625] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[626] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[627] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[628] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028314592, 'op': 'memory_read_request'}
instructions[629] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[630] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028314592, 'op': 'memory_read_wait'}
instructions[631] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028314592, 'element_size': 2, 'op': 'memory_read'}
instructions[632] = {6'd0, 8'd141, 8'd0, 32'd17};//{'dest': 141, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[633] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[634] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[635] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[636] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[637] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[638] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[639] = {6'd0, 8'd146, 8'd0, 32'd13};//{'dest': 146, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[640] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[641] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[642] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[643] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[644] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[645] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028315024, 'op': 'memory_read_request'}
instructions[646] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[647] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028315024, 'op': 'memory_read_wait'}
instructions[648] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028315024, 'element_size': 2, 'op': 'memory_read'}
instructions[649] = {6'd0, 8'd141, 8'd0, 32'd18};//{'dest': 141, 'literal': 18, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[650] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[651] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[652] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[653] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[654] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[655] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[656] = {6'd0, 8'd146, 8'd0, 32'd14};//{'dest': 146, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[657] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[658] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[659] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[660] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[661] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[662] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028315456, 'op': 'memory_read_request'}
instructions[663] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[664] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028315456, 'op': 'memory_read_wait'}
instructions[665] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028315456, 'element_size': 2, 'op': 'memory_read'}
instructions[666] = {6'd0, 8'd141, 8'd0, 32'd19};//{'dest': 141, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[667] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[668] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[669] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[670] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[671] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[672] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[673] = {6'd0, 8'd146, 8'd0, 32'd15};//{'dest': 146, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[674] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[675] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[676] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[677] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[678] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[679] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028315888, 'op': 'memory_read_request'}
instructions[680] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[681] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028315888, 'op': 'memory_read_wait'}
instructions[682] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028315888, 'element_size': 2, 'op': 'memory_read'}
instructions[683] = {6'd0, 8'd141, 8'd0, 32'd20};//{'dest': 141, 'literal': 20, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[684] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[685] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[686] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[687] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[688] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[689] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[690] = {6'd3, 8'd148, 8'd10, 32'd0};//{'dest': 148, 'src': 10, 'op': 'move'}
instructions[691] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[692] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[693] = {6'd3, 8'd26, 8'd148, 32'd0};//{'dest': 26, 'src': 148, 'op': 'move'}
instructions[694] = {6'd0, 8'd141, 8'd0, 32'd64};//{'dest': 141, 'literal': 64, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[695] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[696] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[697] = {6'd3, 8'd27, 8'd141, 32'd0};//{'dest': 27, 'src': 141, 'op': 'move'}
instructions[698] = {6'd0, 8'd142, 8'd0, 32'd11};//{'dest': 142, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[699] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[700] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[701] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[702] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[703] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[704] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028337224, 'op': 'memory_read_request'}
instructions[705] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[706] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028337224, 'op': 'memory_read_wait'}
instructions[707] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028337224, 'element_size': 2, 'op': 'memory_read'}
instructions[708] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[709] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[710] = {6'd3, 8'd28, 8'd141, 32'd0};//{'dest': 28, 'src': 141, 'op': 'move'}
instructions[711] = {6'd0, 8'd142, 8'd0, 32'd12};//{'dest': 142, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[712] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[713] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[714] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[715] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[716] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[717] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028337368, 'op': 'memory_read_request'}
instructions[718] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[719] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028337368, 'op': 'memory_read_wait'}
instructions[720] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028337368, 'element_size': 2, 'op': 'memory_read'}
instructions[721] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[722] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[723] = {6'd3, 8'd29, 8'd141, 32'd0};//{'dest': 29, 'src': 141, 'op': 'move'}
instructions[724] = {6'd0, 8'd142, 8'd0, 32'd13};//{'dest': 142, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[725] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[726] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[727] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[728] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[729] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[730] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028337512, 'op': 'memory_read_request'}
instructions[731] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[732] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028337512, 'op': 'memory_read_wait'}
instructions[733] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028337512, 'element_size': 2, 'op': 'memory_read'}
instructions[734] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[735] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[736] = {6'd3, 8'd30, 8'd141, 32'd0};//{'dest': 30, 'src': 141, 'op': 'move'}
instructions[737] = {6'd0, 8'd141, 8'd0, 32'd2054};//{'dest': 141, 'literal': 2054, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[738] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[739] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[740] = {6'd3, 8'd31, 8'd141, 32'd0};//{'dest': 31, 'src': 141, 'op': 'move'}
instructions[741] = {6'd1, 8'd25, 8'd0, 32'd218};//{'dest': 25, 'label': 218, 'op': 'jmp_and_link'}
instructions[742] = {6'd15, 8'd0, 8'd0, 32'd743};//{'label': 743, 'op': 'goto'}
instructions[743] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[744] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[745] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[746] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[747] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[748] = {6'd15, 8'd0, 8'd0, 32'd749};//{'label': 749, 'op': 'goto'}
instructions[749] = {6'd3, 8'd140, 8'd37, 32'd0};//{'dest': 140, 'src': 37, 'op': 'move'}
instructions[750] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[751] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[752] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[753] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[754] = {6'd0, 8'd50, 8'd0, 32'd0};//{'dest': 50, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[755] = {6'd0, 8'd51, 8'd0, 32'd0};//{'dest': 51, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[756] = {6'd0, 8'd52, 8'd0, 32'd600};//{'dest': 52, 'literal': 600, 'op': 'literal'}
instructions[757] = {6'd0, 8'd53, 8'd0, 32'd0};//{'dest': 53, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[758] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[759] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[760] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[761] = {6'd3, 8'd53, 8'd140, 32'd0};//{'dest': 53, 'src': 140, 'op': 'move'}
instructions[762] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[763] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[764] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[765] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[766] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[767] = {6'd28, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[768] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[769] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[770] = {6'd13, 8'd0, 8'd140, 32'd814};//{'src': 140, 'label': 814, 'op': 'jmp_if_false'}
instructions[771] = {6'd3, 8'd142, 8'd53, 32'd0};//{'dest': 142, 'src': 53, 'op': 'move'}
instructions[772] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[773] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[774] = {6'd11, 8'd146, 8'd142, 32'd40};//{'dest': 146, 'src': 142, 'srcb': 40, 'signed': False, 'op': '+'}
instructions[775] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[776] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[777] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028337872, 'op': 'memory_read_request'}
instructions[778] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[779] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028337872, 'op': 'memory_read_wait'}
instructions[780] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028337872, 'element_size': 2, 'op': 'memory_read'}
instructions[781] = {6'd3, 8'd142, 8'd48, 32'd0};//{'dest': 142, 'src': 48, 'op': 'move'}
instructions[782] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[783] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[784] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[785] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[786] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[787] = {6'd13, 8'd0, 8'd140, 32'd802};//{'src': 140, 'label': 802, 'op': 'jmp_if_false'}
instructions[788] = {6'd3, 8'd142, 8'd53, 32'd0};//{'dest': 142, 'src': 53, 'op': 'move'}
instructions[789] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[790] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[791] = {6'd11, 8'd146, 8'd142, 32'd41};//{'dest': 146, 'src': 142, 'srcb': 41, 'signed': False, 'op': '+'}
instructions[792] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[793] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[794] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028338160, 'op': 'memory_read_request'}
instructions[795] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[796] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028338160, 'op': 'memory_read_wait'}
instructions[797] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028338160, 'element_size': 2, 'op': 'memory_read'}
instructions[798] = {6'd3, 8'd142, 8'd49, 32'd0};//{'dest': 142, 'src': 49, 'op': 'move'}
instructions[799] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[800] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[801] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[802] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[803] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[804] = {6'd13, 8'd0, 8'd140, 32'd811};//{'src': 140, 'label': 811, 'op': 'jmp_if_false'}
instructions[805] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[806] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[807] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[808] = {6'd3, 8'd47, 8'd140, 32'd0};//{'dest': 47, 'src': 140, 'op': 'move'}
instructions[809] = {6'd6, 8'd0, 8'd46, 32'd0};//{'src': 46, 'op': 'jmp_to_reg'}
instructions[810] = {6'd15, 8'd0, 8'd0, 32'd811};//{'label': 811, 'op': 'goto'}
instructions[811] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[812] = {6'd14, 8'd53, 8'd53, 32'd1};//{'src': 53, 'right': 1, 'dest': 53, 'signed': False, 'op': '+', 'size': 2}
instructions[813] = {6'd15, 8'd0, 8'd0, 32'd762};//{'label': 762, 'op': 'goto'}
instructions[814] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[815] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[816] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[817] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[818] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[819] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[820] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[821] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[822] = {6'd0, 8'd140, 8'd0, 32'd2048};//{'dest': 140, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[823] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[824] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[825] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[826] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[827] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[828] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[829] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[830] = {6'd0, 8'd140, 8'd0, 32'd1540};//{'dest': 140, 'literal': 1540, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[831] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[832] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[833] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[834] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[835] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[836] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[837] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[838] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[839] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[840] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[841] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[842] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[843] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[844] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[845] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[846] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[847] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[848] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[849] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[850] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[851] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[852] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[853] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[854] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[855] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[856] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[857] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[858] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[859] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[860] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[861] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[862] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[863] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[864] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[865] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[866] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[867] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[868] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[869] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[870] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[871] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[872] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[873] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[874] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[875] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[876] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[877] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[878] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[879] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[880] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[881] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[882] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[883] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[884] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[885] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[886] = {6'd3, 8'd140, 8'd48, 32'd0};//{'dest': 140, 'src': 48, 'op': 'move'}
instructions[887] = {6'd0, 8'd141, 8'd0, 32'd19};//{'dest': 141, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[888] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[889] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[890] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[891] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[892] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[893] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[894] = {6'd3, 8'd140, 8'd49, 32'd0};//{'dest': 140, 'src': 49, 'op': 'move'}
instructions[895] = {6'd0, 8'd141, 8'd0, 32'd20};//{'dest': 141, 'literal': 20, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[896] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[897] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[898] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[899] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[900] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[901] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[902] = {6'd3, 8'd148, 8'd10, 32'd0};//{'dest': 148, 'src': 10, 'op': 'move'}
instructions[903] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[904] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[905] = {6'd3, 8'd26, 8'd148, 32'd0};//{'dest': 26, 'src': 148, 'op': 'move'}
instructions[906] = {6'd0, 8'd141, 8'd0, 32'd64};//{'dest': 141, 'literal': 64, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[907] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[908] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[909] = {6'd3, 8'd27, 8'd141, 32'd0};//{'dest': 27, 'src': 141, 'op': 'move'}
instructions[910] = {6'd0, 8'd141, 8'd0, 32'd65535};//{'dest': 141, 'literal': 65535, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[911] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[912] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[913] = {6'd3, 8'd28, 8'd141, 32'd0};//{'dest': 28, 'src': 141, 'op': 'move'}
instructions[914] = {6'd0, 8'd141, 8'd0, 32'd65535};//{'dest': 141, 'literal': 65535, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[915] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[916] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[917] = {6'd3, 8'd29, 8'd141, 32'd0};//{'dest': 29, 'src': 141, 'op': 'move'}
instructions[918] = {6'd0, 8'd141, 8'd0, 32'd65535};//{'dest': 141, 'literal': 65535, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[919] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[920] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[921] = {6'd3, 8'd30, 8'd141, 32'd0};//{'dest': 30, 'src': 141, 'op': 'move'}
instructions[922] = {6'd0, 8'd141, 8'd0, 32'd2054};//{'dest': 141, 'literal': 2054, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[923] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[924] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[925] = {6'd3, 8'd31, 8'd141, 32'd0};//{'dest': 31, 'src': 141, 'op': 'move'}
instructions[926] = {6'd1, 8'd25, 8'd0, 32'd218};//{'dest': 25, 'label': 218, 'op': 'jmp_and_link'}
instructions[927] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[928] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[929] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[930] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[931] = {6'd3, 8'd50, 8'd140, 32'd0};//{'dest': 50, 'src': 140, 'op': 'move'}
instructions[932] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[933] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[934] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[935] = {6'd3, 8'd53, 8'd140, 32'd0};//{'dest': 53, 'src': 140, 'op': 'move'}
instructions[936] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[937] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[938] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[939] = {6'd3, 8'd51, 8'd140, 32'd0};//{'dest': 51, 'src': 140, 'op': 'move'}
instructions[940] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[941] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[942] = {6'd3, 8'd141, 8'd51, 32'd0};//{'dest': 141, 'src': 51, 'op': 'move'}
instructions[943] = {6'd3, 8'd142, 8'd50, 32'd0};//{'dest': 142, 'src': 50, 'op': 'move'}
instructions[944] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[945] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[946] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[947] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[948] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[949] = {6'd13, 8'd0, 8'd140, 32'd979};//{'src': 140, 'label': 979, 'op': 'jmp_if_false'}
instructions[950] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[951] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[952] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[953] = {6'd28, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[954] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[955] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[956] = {6'd13, 8'd0, 8'd140, 32'd967};//{'src': 140, 'label': 967, 'op': 'jmp_if_false'}
instructions[957] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[958] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[959] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[960] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[961] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[962] = {6'd11, 8'd142, 8'd141, 32'd52};//{'dest': 142, 'src': 141, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[963] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[964] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[965] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[966] = {6'd15, 8'd0, 8'd0, 32'd969};//{'label': 969, 'op': 'goto'}
instructions[967] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[968] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[969] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[970] = {6'd14, 8'd53, 8'd53, 32'd1};//{'src': 53, 'right': 1, 'dest': 53, 'signed': False, 'op': '+', 'size': 2}
instructions[971] = {6'd3, 8'd141, 8'd51, 32'd0};//{'dest': 141, 'src': 51, 'op': 'move'}
instructions[972] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[973] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[974] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[975] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[976] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[977] = {6'd3, 8'd51, 8'd140, 32'd0};//{'dest': 51, 'src': 140, 'op': 'move'}
instructions[978] = {6'd15, 8'd0, 8'd0, 32'd940};//{'label': 940, 'op': 'goto'}
instructions[979] = {6'd0, 8'd142, 8'd0, 32'd6};//{'dest': 142, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[980] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[981] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[982] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[983] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[984] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[985] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028392416, 'op': 'memory_read_request'}
instructions[986] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[987] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028392416, 'op': 'memory_read_wait'}
instructions[988] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028392416, 'element_size': 2, 'op': 'memory_read'}
instructions[989] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[990] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[991] = {6'd25, 8'd140, 8'd141, 32'd2054};//{'src': 141, 'right': 2054, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[992] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[993] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[994] = {6'd13, 8'd0, 8'd140, 32'd1008};//{'src': 140, 'label': 1008, 'op': 'jmp_if_false'}
instructions[995] = {6'd0, 8'd142, 8'd0, 32'd10};//{'dest': 142, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[996] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[997] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[998] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[999] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1000] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1001] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028392704, 'op': 'memory_read_request'}
instructions[1002] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1003] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028392704, 'op': 'memory_read_wait'}
instructions[1004] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028392704, 'element_size': 2, 'op': 'memory_read'}
instructions[1005] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1006] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1007] = {6'd25, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1008] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1009] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1010] = {6'd13, 8'd0, 8'd140, 32'd1139};//{'src': 140, 'label': 1139, 'op': 'jmp_if_false'}
instructions[1011] = {6'd0, 8'd142, 8'd0, 32'd14};//{'dest': 142, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1012] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1013] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1014] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1015] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1016] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1017] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028393280, 'op': 'memory_read_request'}
instructions[1018] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1019] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028393280, 'op': 'memory_read_wait'}
instructions[1020] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028393280, 'element_size': 2, 'op': 'memory_read'}
instructions[1021] = {6'd3, 8'd142, 8'd48, 32'd0};//{'dest': 142, 'src': 48, 'op': 'move'}
instructions[1022] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1023] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1024] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1025] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1026] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1027] = {6'd13, 8'd0, 8'd140, 32'd1042};//{'src': 140, 'label': 1042, 'op': 'jmp_if_false'}
instructions[1028] = {6'd0, 8'd142, 8'd0, 32'd15};//{'dest': 142, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1029] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1030] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1031] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1032] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1033] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1034] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028393568, 'op': 'memory_read_request'}
instructions[1035] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1036] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028393568, 'op': 'memory_read_wait'}
instructions[1037] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028393568, 'element_size': 2, 'op': 'memory_read'}
instructions[1038] = {6'd3, 8'd142, 8'd49, 32'd0};//{'dest': 142, 'src': 49, 'op': 'move'}
instructions[1039] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1040] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1041] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1042] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1043] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1044] = {6'd13, 8'd0, 8'd140, 32'd1138};//{'src': 140, 'label': 1138, 'op': 'jmp_if_false'}
instructions[1045] = {6'd3, 8'd140, 8'd48, 32'd0};//{'dest': 140, 'src': 48, 'op': 'move'}
instructions[1046] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1047] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1048] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1049] = {6'd11, 8'd142, 8'd141, 32'd40};//{'dest': 142, 'src': 141, 'srcb': 40, 'signed': False, 'op': '+'}
instructions[1050] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1051] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1052] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1053] = {6'd3, 8'd140, 8'd49, 32'd0};//{'dest': 140, 'src': 49, 'op': 'move'}
instructions[1054] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1055] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1056] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1057] = {6'd11, 8'd142, 8'd141, 32'd41};//{'dest': 142, 'src': 141, 'srcb': 41, 'signed': False, 'op': '+'}
instructions[1058] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1059] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1060] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1061] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1062] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1063] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1064] = {6'd11, 8'd147, 8'd146, 32'd52};//{'dest': 147, 'src': 146, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1065] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1066] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1067] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028407288, 'op': 'memory_read_request'}
instructions[1068] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1069] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028407288, 'op': 'memory_read_wait'}
instructions[1070] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028407288, 'element_size': 2, 'op': 'memory_read'}
instructions[1071] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1072] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1073] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1074] = {6'd11, 8'd142, 8'd141, 32'd42};//{'dest': 142, 'src': 141, 'srcb': 42, 'signed': False, 'op': '+'}
instructions[1075] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1076] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1077] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1078] = {6'd0, 8'd146, 8'd0, 32'd12};//{'dest': 146, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1079] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1080] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1081] = {6'd11, 8'd147, 8'd146, 32'd52};//{'dest': 147, 'src': 146, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1082] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1083] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1084] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028407720, 'op': 'memory_read_request'}
instructions[1085] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1086] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028407720, 'op': 'memory_read_wait'}
instructions[1087] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028407720, 'element_size': 2, 'op': 'memory_read'}
instructions[1088] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1089] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1090] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1091] = {6'd11, 8'd142, 8'd141, 32'd43};//{'dest': 142, 'src': 141, 'srcb': 43, 'signed': False, 'op': '+'}
instructions[1092] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1093] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1094] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1095] = {6'd0, 8'd146, 8'd0, 32'd13};//{'dest': 146, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1096] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1097] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1098] = {6'd11, 8'd147, 8'd146, 32'd52};//{'dest': 147, 'src': 146, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1099] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1100] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1101] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028408152, 'op': 'memory_read_request'}
instructions[1102] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1103] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028408152, 'op': 'memory_read_wait'}
instructions[1104] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028408152, 'element_size': 2, 'op': 'memory_read'}
instructions[1105] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1106] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1107] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1108] = {6'd11, 8'd142, 8'd141, 32'd44};//{'dest': 142, 'src': 141, 'srcb': 44, 'signed': False, 'op': '+'}
instructions[1109] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1110] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1111] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1112] = {6'd3, 8'd140, 8'd45, 32'd0};//{'dest': 140, 'src': 45, 'op': 'move'}
instructions[1113] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1114] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1115] = {6'd3, 8'd53, 8'd140, 32'd0};//{'dest': 53, 'src': 140, 'op': 'move'}
instructions[1116] = {6'd3, 8'd140, 8'd45, 32'd0};//{'dest': 140, 'src': 45, 'op': 'move'}
instructions[1117] = {6'd14, 8'd45, 8'd45, 32'd1};//{'src': 45, 'right': 1, 'dest': 45, 'signed': False, 'op': '+', 'size': 2}
instructions[1118] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1119] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1120] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1121] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1122] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1123] = {6'd25, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1124] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1125] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1126] = {6'd13, 8'd0, 8'd140, 32'd1132};//{'src': 140, 'label': 1132, 'op': 'jmp_if_false'}
instructions[1127] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1128] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1130] = {6'd3, 8'd45, 8'd140, 32'd0};//{'dest': 45, 'src': 140, 'op': 'move'}
instructions[1131] = {6'd15, 8'd0, 8'd0, 32'd1132};//{'label': 1132, 'op': 'goto'}
instructions[1132] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[1133] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1134] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1135] = {6'd3, 8'd47, 8'd140, 32'd0};//{'dest': 47, 'src': 140, 'op': 'move'}
instructions[1136] = {6'd6, 8'd0, 8'd46, 32'd0};//{'src': 46, 'op': 'jmp_to_reg'}
instructions[1137] = {6'd15, 8'd0, 8'd0, 32'd1138};//{'label': 1138, 'op': 'goto'}
instructions[1138] = {6'd15, 8'd0, 8'd0, 32'd1139};//{'label': 1139, 'op': 'goto'}
instructions[1139] = {6'd15, 8'd0, 8'd0, 32'd927};//{'label': 927, 'op': 'goto'}
instructions[1140] = {6'd0, 8'd60, 8'd0, 32'd0};//{'dest': 60, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1141] = {6'd0, 8'd61, 8'd0, 32'd0};//{'dest': 61, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1142] = {6'd0, 8'd62, 8'd0, 32'd0};//{'dest': 62, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1143] = {6'd3, 8'd141, 8'd58, 32'd0};//{'dest': 141, 'src': 58, 'op': 'move'}
instructions[1144] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1145] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1146] = {6'd3, 8'd48, 8'd141, 32'd0};//{'dest': 48, 'src': 141, 'op': 'move'}
instructions[1147] = {6'd3, 8'd141, 8'd59, 32'd0};//{'dest': 141, 'src': 59, 'op': 'move'}
instructions[1148] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1149] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1150] = {6'd3, 8'd49, 8'd141, 32'd0};//{'dest': 49, 'src': 141, 'op': 'move'}
instructions[1151] = {6'd1, 8'd46, 8'd0, 32'd754};//{'dest': 46, 'label': 754, 'op': 'jmp_and_link'}
instructions[1152] = {6'd3, 8'd140, 8'd47, 32'd0};//{'dest': 140, 'src': 47, 'op': 'move'}
instructions[1153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1154] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1155] = {6'd3, 8'd62, 8'd140, 32'd0};//{'dest': 62, 'src': 140, 'op': 'move'}
instructions[1156] = {6'd0, 8'd140, 8'd0, 32'd17664};//{'dest': 140, 'literal': 17664, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1157] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1158] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1159] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1160] = {6'd27, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1161] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1162] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1163] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1164] = {6'd3, 8'd140, 8'd56, 32'd0};//{'dest': 140, 'src': 56, 'op': 'move'}
instructions[1165] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1166] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1167] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1168] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1170] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1171] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1172] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1173] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1174] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1175] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1176] = {6'd27, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1177] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1178] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1179] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1180] = {6'd0, 8'd140, 8'd0, 32'd16384};//{'dest': 140, 'literal': 16384, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1181] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1183] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1184] = {6'd27, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1185] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1186] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1187] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1188] = {6'd3, 8'd146, 8'd57, 32'd0};//{'dest': 146, 'src': 57, 'op': 'move'}
instructions[1189] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1190] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1191] = {6'd30, 8'd140, 8'd146, 32'd65280};//{'src': 146, 'dest': 140, 'signed': False, 'op': '|', 'size': 2, 'type': 'int', 'left': 65280}
instructions[1192] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1195] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1198] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1199] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1200] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1201] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1202] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1203] = {6'd27, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1204] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1205] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1206] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1207] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1208] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1210] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1211] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1213] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1214] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1215] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1216] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1217] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1218] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1219] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1220] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1222] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1223] = {6'd3, 8'd140, 8'd58, 32'd0};//{'dest': 140, 'src': 58, 'op': 'move'}
instructions[1224] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1225] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1226] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1227] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1228] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1230] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1231] = {6'd3, 8'd140, 8'd59, 32'd0};//{'dest': 140, 'src': 59, 'op': 'move'}
instructions[1232] = {6'd0, 8'd141, 8'd0, 32'd16};//{'dest': 141, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1233] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1234] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1235] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1236] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1237] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1238] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1239] = {6'd3, 8'd141, 8'd56, 32'd0};//{'dest': 141, 'src': 56, 'op': 'move'}
instructions[1240] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1241] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1242] = {6'd14, 8'd140, 8'd141, 32'd14};//{'src': 141, 'right': 14, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1243] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1244] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1245] = {6'd3, 8'd60, 8'd140, 32'd0};//{'dest': 60, 'src': 140, 'op': 'move'}
instructions[1246] = {6'd1, 8'd12, 8'd0, 32'd59};//{'dest': 12, 'label': 59, 'op': 'jmp_and_link'}
instructions[1247] = {6'd0, 8'd140, 8'd0, 32'd7};//{'dest': 140, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1248] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1249] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1250] = {6'd3, 8'd61, 8'd140, 32'd0};//{'dest': 61, 'src': 140, 'op': 'move'}
instructions[1251] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1252] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1253] = {6'd3, 8'd141, 8'd61, 32'd0};//{'dest': 141, 'src': 61, 'op': 'move'}
instructions[1254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1255] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1256] = {6'd31, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '<=', 'type': 'int', 'size': 2}
instructions[1257] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1258] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1259] = {6'd13, 8'd0, 8'd140, 32'd1277};//{'src': 140, 'label': 1277, 'op': 'jmp_if_false'}
instructions[1260] = {6'd3, 8'd142, 8'd61, 32'd0};//{'dest': 142, 'src': 61, 'op': 'move'}
instructions[1261] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1263] = {6'd11, 8'd146, 8'd142, 32'd55};//{'dest': 146, 'src': 142, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1264] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1265] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1266] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028462408, 'op': 'memory_read_request'}
instructions[1267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1268] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028462408, 'op': 'memory_read_wait'}
instructions[1269] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028462408, 'element_size': 2, 'op': 'memory_read'}
instructions[1270] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1271] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1272] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1273] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1274] = {6'd3, 8'd140, 8'd61, 32'd0};//{'dest': 140, 'src': 61, 'op': 'move'}
instructions[1275] = {6'd14, 8'd61, 8'd61, 32'd1};//{'src': 61, 'right': 1, 'dest': 61, 'signed': False, 'op': '+', 'size': 2}
instructions[1276] = {6'd15, 8'd0, 8'd0, 32'd1251};//{'label': 1251, 'op': 'goto'}
instructions[1277] = {6'd1, 8'd15, 8'd0, 32'd100};//{'dest': 15, 'label': 100, 'op': 'jmp_and_link'}
instructions[1278] = {6'd3, 8'd140, 8'd16, 32'd0};//{'dest': 140, 'src': 16, 'op': 'move'}
instructions[1279] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1280] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1282] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1283] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1284] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1285] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1286] = {6'd3, 8'd141, 8'd60, 32'd0};//{'dest': 141, 'src': 60, 'op': 'move'}
instructions[1287] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1288] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1289] = {6'd28, 8'd140, 8'd141, 32'd64};//{'src': 141, 'right': 64, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[1290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1291] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1292] = {6'd13, 8'd0, 8'd140, 32'd1298};//{'src': 140, 'label': 1298, 'op': 'jmp_if_false'}
instructions[1293] = {6'd0, 8'd140, 8'd0, 32'd64};//{'dest': 140, 'literal': 64, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1295] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1296] = {6'd3, 8'd60, 8'd140, 32'd0};//{'dest': 60, 'src': 140, 'op': 'move'}
instructions[1297] = {6'd15, 8'd0, 8'd0, 32'd1298};//{'label': 1298, 'op': 'goto'}
instructions[1298] = {6'd3, 8'd143, 8'd55, 32'd0};//{'dest': 143, 'src': 55, 'op': 'move'}
instructions[1299] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1301] = {6'd3, 8'd26, 8'd143, 32'd0};//{'dest': 26, 'src': 143, 'op': 'move'}
instructions[1302] = {6'd3, 8'd141, 8'd60, 32'd0};//{'dest': 141, 'src': 60, 'op': 'move'}
instructions[1303] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1304] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1305] = {6'd3, 8'd27, 8'd141, 32'd0};//{'dest': 27, 'src': 141, 'op': 'move'}
instructions[1306] = {6'd3, 8'd142, 8'd62, 32'd0};//{'dest': 142, 'src': 62, 'op': 'move'}
instructions[1307] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1308] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1309] = {6'd11, 8'd146, 8'd142, 32'd42};//{'dest': 146, 'src': 142, 'srcb': 42, 'signed': False, 'op': '+'}
instructions[1310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1311] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1312] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028468224, 'op': 'memory_read_request'}
instructions[1313] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1314] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028468224, 'op': 'memory_read_wait'}
instructions[1315] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028468224, 'element_size': 2, 'op': 'memory_read'}
instructions[1316] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1317] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1318] = {6'd3, 8'd28, 8'd141, 32'd0};//{'dest': 28, 'src': 141, 'op': 'move'}
instructions[1319] = {6'd3, 8'd142, 8'd62, 32'd0};//{'dest': 142, 'src': 62, 'op': 'move'}
instructions[1320] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1321] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1322] = {6'd11, 8'd146, 8'd142, 32'd43};//{'dest': 146, 'src': 142, 'srcb': 43, 'signed': False, 'op': '+'}
instructions[1323] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1324] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1325] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028468368, 'op': 'memory_read_request'}
instructions[1326] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1327] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028468368, 'op': 'memory_read_wait'}
instructions[1328] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028468368, 'element_size': 2, 'op': 'memory_read'}
instructions[1329] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1330] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1331] = {6'd3, 8'd29, 8'd141, 32'd0};//{'dest': 29, 'src': 141, 'op': 'move'}
instructions[1332] = {6'd3, 8'd142, 8'd62, 32'd0};//{'dest': 142, 'src': 62, 'op': 'move'}
instructions[1333] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1334] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1335] = {6'd11, 8'd146, 8'd142, 32'd44};//{'dest': 146, 'src': 142, 'srcb': 44, 'signed': False, 'op': '+'}
instructions[1336] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1337] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1338] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028468512, 'op': 'memory_read_request'}
instructions[1339] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1340] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028468512, 'op': 'memory_read_wait'}
instructions[1341] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028468512, 'element_size': 2, 'op': 'memory_read'}
instructions[1342] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1343] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1344] = {6'd3, 8'd30, 8'd141, 32'd0};//{'dest': 30, 'src': 141, 'op': 'move'}
instructions[1345] = {6'd0, 8'd141, 8'd0, 32'd2048};//{'dest': 141, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1346] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1347] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1348] = {6'd3, 8'd31, 8'd141, 32'd0};//{'dest': 31, 'src': 141, 'op': 'move'}
instructions[1349] = {6'd1, 8'd25, 8'd0, 32'd218};//{'dest': 25, 'label': 218, 'op': 'jmp_and_link'}
instructions[1350] = {6'd6, 8'd0, 8'd54, 32'd0};//{'src': 54, 'op': 'jmp_to_reg'}
instructions[1351] = {6'd0, 8'd66, 8'd0, 32'd0};//{'dest': 66, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1352] = {6'd0, 8'd67, 8'd0, 32'd0};//{'dest': 67, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1353] = {6'd0, 8'd68, 8'd0, 32'd0};//{'dest': 68, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1354] = {6'd0, 8'd69, 8'd0, 32'd0};//{'dest': 69, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1355] = {6'd0, 8'd70, 8'd0, 32'd0};//{'dest': 70, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1356] = {6'd0, 8'd71, 8'd0, 32'd0};//{'dest': 71, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1357] = {6'd0, 8'd72, 8'd0, 32'd0};//{'dest': 72, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1358] = {6'd0, 8'd73, 8'd0, 32'd0};//{'dest': 73, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1359] = {6'd0, 8'd74, 8'd0, 32'd0};//{'dest': 74, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1360] = {6'd3, 8'd143, 8'd65, 32'd0};//{'dest': 143, 'src': 65, 'op': 'move'}
instructions[1361] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1363] = {6'd3, 8'd36, 8'd143, 32'd0};//{'dest': 36, 'src': 143, 'op': 'move'}
instructions[1364] = {6'd1, 8'd34, 8'd0, 32'd328};//{'dest': 34, 'label': 328, 'op': 'jmp_and_link'}
instructions[1365] = {6'd3, 8'd140, 8'd35, 32'd0};//{'dest': 140, 'src': 35, 'op': 'move'}
instructions[1366] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1367] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1368] = {6'd3, 8'd74, 8'd140, 32'd0};//{'dest': 74, 'src': 140, 'op': 'move'}
instructions[1369] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1370] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1371] = {6'd3, 8'd141, 8'd74, 32'd0};//{'dest': 141, 'src': 74, 'op': 'move'}
instructions[1372] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1373] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1374] = {6'd25, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1376] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1377] = {6'd13, 8'd0, 8'd140, 32'd1384};//{'src': 140, 'label': 1384, 'op': 'jmp_if_false'}
instructions[1378] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1379] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1380] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1381] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1382] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1383] = {6'd15, 8'd0, 8'd0, 32'd1384};//{'label': 1384, 'op': 'goto'}
instructions[1384] = {6'd0, 8'd142, 8'd0, 32'd6};//{'dest': 142, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1385] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1386] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1387] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1388] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1389] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1390] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028469232, 'op': 'memory_read_request'}
instructions[1391] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1392] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028469232, 'op': 'memory_read_wait'}
instructions[1393] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028469232, 'element_size': 2, 'op': 'memory_read'}
instructions[1394] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1395] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1396] = {6'd26, 8'd140, 8'd141, 32'd2048};//{'src': 141, 'right': 2048, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1397] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1398] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1399] = {6'd13, 8'd0, 8'd140, 32'd1406};//{'src': 140, 'label': 1406, 'op': 'jmp_if_false'}
instructions[1400] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1401] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1402] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1403] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1404] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1405] = {6'd15, 8'd0, 8'd0, 32'd1406};//{'label': 1406, 'op': 'goto'}
instructions[1406] = {6'd0, 8'd142, 8'd0, 32'd15};//{'dest': 142, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1407] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1408] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1409] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1410] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1411] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1412] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028469736, 'op': 'memory_read_request'}
instructions[1413] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1414] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028469736, 'op': 'memory_read_wait'}
instructions[1415] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028469736, 'element_size': 2, 'op': 'memory_read'}
instructions[1416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1418] = {6'd26, 8'd140, 8'd141, 32'd49320};//{'src': 141, 'right': 49320, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1419] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1420] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1421] = {6'd13, 8'd0, 8'd140, 32'd1428};//{'src': 140, 'label': 1428, 'op': 'jmp_if_false'}
instructions[1422] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1423] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1424] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1425] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1426] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1427] = {6'd15, 8'd0, 8'd0, 32'd1428};//{'label': 1428, 'op': 'goto'}
instructions[1428] = {6'd0, 8'd142, 8'd0, 32'd16};//{'dest': 142, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1429] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1431] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1432] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1433] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1434] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028470240, 'op': 'memory_read_request'}
instructions[1435] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1436] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028470240, 'op': 'memory_read_wait'}
instructions[1437] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028470240, 'element_size': 2, 'op': 'memory_read'}
instructions[1438] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1439] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1440] = {6'd26, 8'd140, 8'd141, 32'd119};//{'src': 141, 'right': 119, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1441] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1442] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1443] = {6'd13, 8'd0, 8'd140, 32'd1450};//{'src': 140, 'label': 1450, 'op': 'jmp_if_false'}
instructions[1444] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1445] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1446] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1447] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1448] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1449] = {6'd15, 8'd0, 8'd0, 32'd1450};//{'label': 1450, 'op': 'goto'}
instructions[1450] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1451] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1452] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1453] = {6'd11, 8'd147, 8'd146, 32'd65};//{'dest': 147, 'src': 146, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1454] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1456] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515029212264, 'op': 'memory_read_request'}
instructions[1457] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1458] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515029212264, 'op': 'memory_read_wait'}
instructions[1459] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140515029212264, 'element_size': 2, 'op': 'memory_read'}
instructions[1460] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1461] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1462] = {6'd12, 8'd141, 8'd142, 32'd255};//{'src': 142, 'right': 255, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1463] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1464] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1465] = {6'd25, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1466] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1467] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1468] = {6'd13, 8'd0, 8'd140, 32'd1675};//{'src': 140, 'label': 1675, 'op': 'jmp_if_false'}
instructions[1469] = {6'd0, 8'd147, 8'd0, 32'd7};//{'dest': 147, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1470] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1471] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1472] = {6'd11, 8'd149, 8'd147, 32'd65};//{'dest': 149, 'src': 147, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1473] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1474] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1475] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 140515028500352, 'op': 'memory_read_request'}
instructions[1476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1477] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 140515028500352, 'op': 'memory_read_wait'}
instructions[1478] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 140515028500352, 'element_size': 2, 'op': 'memory_read'}
instructions[1479] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1480] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1481] = {6'd32, 8'd142, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 142, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[1482] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1483] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1484] = {6'd12, 8'd141, 8'd142, 32'd15};//{'src': 142, 'right': 15, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1485] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1486] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1487] = {6'd33, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '<<', 'type': 'int', 'size': 2}
instructions[1488] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1489] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1490] = {6'd3, 8'd67, 8'd140, 32'd0};//{'dest': 67, 'src': 140, 'op': 'move'}
instructions[1491] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1492] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1493] = {6'd3, 8'd141, 8'd67, 32'd0};//{'dest': 141, 'src': 67, 'op': 'move'}
instructions[1494] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1495] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1496] = {6'd14, 8'd140, 8'd141, 32'd7};//{'src': 141, 'right': 7, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1497] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1498] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1499] = {6'd3, 8'd68, 8'd140, 32'd0};//{'dest': 68, 'src': 140, 'op': 'move'}
instructions[1500] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1501] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1502] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1503] = {6'd11, 8'd142, 8'd141, 32'd65};//{'dest': 142, 'src': 141, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1504] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1505] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1506] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 140515028470456, 'op': 'memory_read_request'}
instructions[1507] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1508] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 140515028470456, 'op': 'memory_read_wait'}
instructions[1509] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 140515028470456, 'element_size': 2, 'op': 'memory_read'}
instructions[1510] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1511] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1512] = {6'd3, 8'd66, 8'd140, 32'd0};//{'dest': 66, 'src': 140, 'op': 'move'}
instructions[1513] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1514] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1515] = {6'd3, 8'd146, 8'd66, 32'd0};//{'dest': 146, 'src': 66, 'op': 'move'}
instructions[1516] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1517] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1518] = {6'd14, 8'd142, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1519] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1520] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1521] = {6'd32, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[1522] = {6'd3, 8'd142, 8'd67, 32'd0};//{'dest': 142, 'src': 67, 'op': 'move'}
instructions[1523] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1524] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1525] = {6'd34, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[1526] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1527] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1528] = {6'd3, 8'd69, 8'd140, 32'd0};//{'dest': 69, 'src': 140, 'op': 'move'}
instructions[1529] = {6'd3, 8'd142, 8'd68, 32'd0};//{'dest': 142, 'src': 68, 'op': 'move'}
instructions[1530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1531] = {6'd3, 8'd146, 8'd69, 32'd0};//{'dest': 146, 'src': 69, 'op': 'move'}
instructions[1532] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1533] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1534] = {6'd11, 8'd141, 8'd142, 32'd146};//{'srcb': 146, 'src': 142, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1535] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1536] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1537] = {6'd35, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[1538] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1539] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1540] = {6'd3, 8'd73, 8'd140, 32'd0};//{'dest': 73, 'src': 140, 'op': 'move'}
instructions[1541] = {6'd3, 8'd142, 8'd68, 32'd0};//{'dest': 142, 'src': 68, 'op': 'move'}
instructions[1542] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1543] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1544] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1545] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1546] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1547] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028463488, 'op': 'memory_read_request'}
instructions[1548] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1549] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028463488, 'op': 'memory_read_wait'}
instructions[1550] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028463488, 'element_size': 2, 'op': 'memory_read'}
instructions[1551] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1552] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1553] = {6'd25, 8'd140, 8'd141, 32'd2048};//{'src': 141, 'right': 2048, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1554] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1555] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1556] = {6'd13, 8'd0, 8'd140, 32'd1669};//{'src': 140, 'label': 1669, 'op': 'jmp_if_false'}
instructions[1557] = {6'd0, 8'd140, 8'd0, 32'd19};//{'dest': 140, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1558] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1559] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1560] = {6'd3, 8'd72, 8'd140, 32'd0};//{'dest': 72, 'src': 140, 'op': 'move'}
instructions[1561] = {6'd1, 8'd12, 8'd0, 32'd59};//{'dest': 12, 'label': 59, 'op': 'jmp_and_link'}
instructions[1562] = {6'd3, 8'd141, 8'd68, 32'd0};//{'dest': 141, 'src': 68, 'op': 'move'}
instructions[1563] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1564] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1565] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1566] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1567] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1568] = {6'd3, 8'd71, 8'd140, 32'd0};//{'dest': 71, 'src': 140, 'op': 'move'}
instructions[1569] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1570] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1571] = {6'd3, 8'd141, 8'd71, 32'd0};//{'dest': 141, 'src': 71, 'op': 'move'}
instructions[1572] = {6'd3, 8'd142, 8'd73, 32'd0};//{'dest': 142, 'src': 73, 'op': 'move'}
instructions[1573] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1574] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1575] = {6'd36, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<=', 'type': 'int', 'size': 2}
instructions[1576] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1577] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1578] = {6'd13, 8'd0, 8'd140, 32'd1612};//{'src': 140, 'label': 1612, 'op': 'jmp_if_false'}
instructions[1579] = {6'd3, 8'd141, 8'd71, 32'd0};//{'dest': 141, 'src': 71, 'op': 'move'}
instructions[1580] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1581] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1582] = {6'd11, 8'd142, 8'd141, 32'd65};//{'dest': 142, 'src': 141, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1583] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1584] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1585] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 140515028499200, 'op': 'memory_read_request'}
instructions[1586] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1587] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 140515028499200, 'op': 'memory_read_wait'}
instructions[1588] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 140515028499200, 'element_size': 2, 'op': 'memory_read'}
instructions[1589] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1590] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1591] = {6'd3, 8'd70, 8'd140, 32'd0};//{'dest': 70, 'src': 140, 'op': 'move'}
instructions[1592] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1593] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1594] = {6'd3, 8'd141, 8'd70, 32'd0};//{'dest': 141, 'src': 70, 'op': 'move'}
instructions[1595] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1596] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1597] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1598] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1599] = {6'd3, 8'd140, 8'd70, 32'd0};//{'dest': 140, 'src': 70, 'op': 'move'}
instructions[1600] = {6'd3, 8'd141, 8'd72, 32'd0};//{'dest': 141, 'src': 72, 'op': 'move'}
instructions[1601] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1602] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1603] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[1604] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1605] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1606] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1607] = {6'd3, 8'd140, 8'd72, 32'd0};//{'dest': 140, 'src': 72, 'op': 'move'}
instructions[1608] = {6'd14, 8'd72, 8'd72, 32'd1};//{'src': 72, 'right': 1, 'dest': 72, 'signed': False, 'op': '+', 'size': 2}
instructions[1609] = {6'd3, 8'd140, 8'd71, 32'd0};//{'dest': 140, 'src': 71, 'op': 'move'}
instructions[1610] = {6'd14, 8'd71, 8'd71, 32'd1};//{'src': 71, 'right': 1, 'dest': 71, 'signed': False, 'op': '+', 'size': 2}
instructions[1611] = {6'd15, 8'd0, 8'd0, 32'd1569};//{'label': 1569, 'op': 'goto'}
instructions[1612] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1613] = {6'd0, 8'd141, 8'd0, 32'd17};//{'dest': 141, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1614] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1615] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1616] = {6'd27, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[1617] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1618] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1619] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1620] = {6'd1, 8'd15, 8'd0, 32'd100};//{'dest': 15, 'label': 100, 'op': 'jmp_and_link'}
instructions[1621] = {6'd3, 8'd140, 8'd16, 32'd0};//{'dest': 140, 'src': 16, 'op': 'move'}
instructions[1622] = {6'd0, 8'd141, 8'd0, 32'd18};//{'dest': 141, 'literal': 18, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1623] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1624] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1625] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[1626] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1627] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1628] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1629] = {6'd3, 8'd148, 8'd10, 32'd0};//{'dest': 148, 'src': 10, 'op': 'move'}
instructions[1630] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1631] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1632] = {6'd3, 8'd55, 8'd148, 32'd0};//{'dest': 55, 'src': 148, 'op': 'move'}
instructions[1633] = {6'd3, 8'd141, 8'd66, 32'd0};//{'dest': 141, 'src': 66, 'op': 'move'}
instructions[1634] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1635] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1636] = {6'd3, 8'd56, 8'd141, 32'd0};//{'dest': 56, 'src': 141, 'op': 'move'}
instructions[1637] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1638] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1639] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1640] = {6'd3, 8'd57, 8'd141, 32'd0};//{'dest': 57, 'src': 141, 'op': 'move'}
instructions[1641] = {6'd0, 8'd142, 8'd0, 32'd13};//{'dest': 142, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1642] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1643] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1644] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1645] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1646] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1647] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515027983392, 'op': 'memory_read_request'}
instructions[1648] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1649] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515027983392, 'op': 'memory_read_wait'}
instructions[1650] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515027983392, 'element_size': 2, 'op': 'memory_read'}
instructions[1651] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1652] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1653] = {6'd3, 8'd58, 8'd141, 32'd0};//{'dest': 58, 'src': 141, 'op': 'move'}
instructions[1654] = {6'd0, 8'd142, 8'd0, 32'd14};//{'dest': 142, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1655] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1656] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1657] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1658] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1659] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1660] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515027983536, 'op': 'memory_read_request'}
instructions[1661] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1662] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515027983536, 'op': 'memory_read_wait'}
instructions[1663] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515027983536, 'element_size': 2, 'op': 'memory_read'}
instructions[1664] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1665] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1666] = {6'd3, 8'd59, 8'd141, 32'd0};//{'dest': 59, 'src': 141, 'op': 'move'}
instructions[1667] = {6'd1, 8'd54, 8'd0, 32'd1140};//{'dest': 54, 'label': 1140, 'op': 'jmp_and_link'}
instructions[1668] = {6'd15, 8'd0, 8'd0, 32'd1669};//{'label': 1669, 'op': 'goto'}
instructions[1669] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1670] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1671] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1672] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1673] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1674] = {6'd15, 8'd0, 8'd0, 32'd1675};//{'label': 1675, 'op': 'goto'}
instructions[1675] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1676] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1677] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1678] = {6'd11, 8'd147, 8'd146, 32'd65};//{'dest': 147, 'src': 146, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1679] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1680] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1681] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515027983968, 'op': 'memory_read_request'}
instructions[1682] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1683] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515027983968, 'op': 'memory_read_wait'}
instructions[1684] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140515027983968, 'element_size': 2, 'op': 'memory_read'}
instructions[1685] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1686] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1687] = {6'd12, 8'd141, 8'd142, 32'd255};//{'src': 142, 'right': 255, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1688] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1689] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1690] = {6'd26, 8'd140, 8'd141, 32'd6};//{'src': 141, 'right': 6, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1691] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1692] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1693] = {6'd13, 8'd0, 8'd140, 32'd1700};//{'src': 140, 'label': 1700, 'op': 'jmp_if_false'}
instructions[1694] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1695] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1696] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1697] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1698] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1699] = {6'd15, 8'd0, 8'd0, 32'd1700};//{'label': 1700, 'op': 'goto'}
instructions[1700] = {6'd3, 8'd140, 8'd74, 32'd0};//{'dest': 140, 'src': 74, 'op': 'move'}
instructions[1701] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1702] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1703] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1704] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1705] = {6'd0, 8'd100, 8'd0, 32'd17};//{'dest': 100, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1706] = {6'd0, 8'd101, 8'd0, 32'd0};//{'dest': 101, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1707] = {6'd0, 8'd102, 8'd0, 32'd0};//{'dest': 102, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1708] = {6'd0, 8'd103, 8'd0, 32'd0};//{'dest': 103, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1709] = {6'd3, 8'd140, 8'd77, 32'd0};//{'dest': 140, 'src': 77, 'op': 'move'}
instructions[1710] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1711] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1712] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1713] = {6'd14, 8'd141, 8'd146, 32'd0};//{'src': 146, 'right': 0, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1714] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1715] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1716] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1717] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1718] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1719] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1720] = {6'd3, 8'd140, 8'd78, 32'd0};//{'dest': 140, 'src': 78, 'op': 'move'}
instructions[1721] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1722] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1723] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1724] = {6'd14, 8'd141, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1725] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1726] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1727] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1728] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1729] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1730] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1731] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1732] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1733] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1734] = {6'd11, 8'd147, 8'd146, 32'd79};//{'dest': 147, 'src': 146, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[1735] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1736] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1737] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028018960, 'op': 'memory_read_request'}
instructions[1738] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1739] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028018960, 'op': 'memory_read_wait'}
instructions[1740] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028018960, 'element_size': 2, 'op': 'memory_read'}
instructions[1741] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1742] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1743] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1744] = {6'd14, 8'd141, 8'd146, 32'd2};//{'src': 146, 'right': 2, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1745] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1746] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1747] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1748] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1749] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1750] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1751] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1752] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1753] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1754] = {6'd11, 8'd147, 8'd146, 32'd79};//{'dest': 147, 'src': 146, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[1755] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1756] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1757] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028019536, 'op': 'memory_read_request'}
instructions[1758] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1759] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028019536, 'op': 'memory_read_wait'}
instructions[1760] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028019536, 'element_size': 2, 'op': 'memory_read'}
instructions[1761] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1762] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1763] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1764] = {6'd14, 8'd141, 8'd146, 32'd3};//{'src': 146, 'right': 3, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1765] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1766] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1767] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1768] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1769] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1770] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1771] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1772] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1773] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1774] = {6'd11, 8'd147, 8'd146, 32'd81};//{'dest': 147, 'src': 146, 'srcb': 81, 'signed': False, 'op': '+'}
instructions[1775] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1776] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1777] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028020112, 'op': 'memory_read_request'}
instructions[1778] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1779] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028020112, 'op': 'memory_read_wait'}
instructions[1780] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028020112, 'element_size': 2, 'op': 'memory_read'}
instructions[1781] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1782] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1783] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1784] = {6'd14, 8'd141, 8'd146, 32'd4};//{'src': 146, 'right': 4, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1785] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1786] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1787] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1788] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1789] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1790] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1791] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1792] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1793] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1794] = {6'd11, 8'd147, 8'd146, 32'd81};//{'dest': 147, 'src': 146, 'srcb': 81, 'signed': False, 'op': '+'}
instructions[1795] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1796] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1797] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028020688, 'op': 'memory_read_request'}
instructions[1798] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1799] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028020688, 'op': 'memory_read_wait'}
instructions[1800] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028020688, 'element_size': 2, 'op': 'memory_read'}
instructions[1801] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1802] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1803] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1804] = {6'd14, 8'd141, 8'd146, 32'd5};//{'src': 146, 'right': 5, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1805] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1806] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1807] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1808] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1809] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1810] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1811] = {6'd0, 8'd140, 8'd0, 32'd20480};//{'dest': 140, 'literal': 20480, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1812] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1813] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1814] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1815] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1816] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1817] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1818] = {6'd27, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': True, 'op': '+'}
instructions[1819] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1820] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1821] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1822] = {6'd3, 8'd140, 8'd82, 32'd0};//{'dest': 140, 'src': 82, 'op': 'move'}
instructions[1823] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1824] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1825] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1826] = {6'd14, 8'd141, 8'd146, 32'd7};//{'src': 146, 'right': 7, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1827] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1828] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1829] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1830] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1831] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1832] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1833] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1834] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1835] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1836] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1837] = {6'd14, 8'd141, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1838] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1839] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1840] = {6'd27, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': True, 'op': '+'}
instructions[1841] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1842] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1843] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1844] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1845] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1846] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1847] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1848] = {6'd14, 8'd141, 8'd146, 32'd9};//{'src': 146, 'right': 9, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1849] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1850] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1851] = {6'd27, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': True, 'op': '+'}
instructions[1852] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1853] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1854] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1855] = {6'd3, 8'd140, 8'd83, 32'd0};//{'dest': 140, 'src': 83, 'op': 'move'}
instructions[1856] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1857] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1858] = {6'd13, 8'd0, 8'd140, 32'd1886};//{'src': 140, 'label': 1886, 'op': 'jmp_if_false'}
instructions[1859] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1860] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1861] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1862] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1863] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1864] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1865] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1866] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1867] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1868] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 140515029252432, 'op': 'memory_read_request'}
instructions[1869] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1870] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 140515029252432, 'op': 'memory_read_wait'}
instructions[1871] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 140515029252432, 'element_size': 2, 'op': 'memory_read'}
instructions[1872] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1873] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1874] = {6'd37, 8'd140, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1875] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1876] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1877] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1878] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1879] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1880] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1881] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1882] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1883] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1884] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1885] = {6'd15, 8'd0, 8'd0, 32'd1886};//{'label': 1886, 'op': 'goto'}
instructions[1886] = {6'd3, 8'd140, 8'd84, 32'd0};//{'dest': 140, 'src': 84, 'op': 'move'}
instructions[1887] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1888] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1889] = {6'd13, 8'd0, 8'd140, 32'd1917};//{'src': 140, 'label': 1917, 'op': 'jmp_if_false'}
instructions[1890] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1891] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1892] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1893] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1894] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1895] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1896] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1897] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1898] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1899] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 140515029253152, 'op': 'memory_read_request'}
instructions[1900] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1901] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 140515029253152, 'op': 'memory_read_wait'}
instructions[1902] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 140515029253152, 'element_size': 2, 'op': 'memory_read'}
instructions[1903] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1904] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1905] = {6'd37, 8'd140, 8'd146, 32'd2};//{'src': 146, 'right': 2, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1906] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1907] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1908] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1909] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1910] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1911] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1912] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1913] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1914] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1915] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1916] = {6'd15, 8'd0, 8'd0, 32'd1917};//{'label': 1917, 'op': 'goto'}
instructions[1917] = {6'd3, 8'd140, 8'd85, 32'd0};//{'dest': 140, 'src': 85, 'op': 'move'}
instructions[1918] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1919] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1920] = {6'd13, 8'd0, 8'd140, 32'd1948};//{'src': 140, 'label': 1948, 'op': 'jmp_if_false'}
instructions[1921] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1922] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1923] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1924] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1925] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1926] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1927] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1928] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1929] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1930] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 140515029253872, 'op': 'memory_read_request'}
instructions[1931] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1932] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 140515029253872, 'op': 'memory_read_wait'}
instructions[1933] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 140515029253872, 'element_size': 2, 'op': 'memory_read'}
instructions[1934] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1935] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1936] = {6'd37, 8'd140, 8'd146, 32'd4};//{'src': 146, 'right': 4, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1937] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1938] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1939] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1940] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1941] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1942] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1943] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1944] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1945] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1946] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1947] = {6'd15, 8'd0, 8'd0, 32'd1948};//{'label': 1948, 'op': 'goto'}
instructions[1948] = {6'd3, 8'd140, 8'd86, 32'd0};//{'dest': 140, 'src': 86, 'op': 'move'}
instructions[1949] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1950] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1951] = {6'd13, 8'd0, 8'd140, 32'd1979};//{'src': 140, 'label': 1979, 'op': 'jmp_if_false'}
instructions[1952] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1953] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1954] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1955] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1956] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1957] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1958] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1959] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1960] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1961] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 140515028046336, 'op': 'memory_read_request'}
instructions[1962] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1963] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 140515028046336, 'op': 'memory_read_wait'}
instructions[1964] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 140515028046336, 'element_size': 2, 'op': 'memory_read'}
instructions[1965] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1966] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1967] = {6'd37, 8'd140, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1968] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1969] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1970] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1971] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1972] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1973] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1974] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1975] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1976] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1977] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1978] = {6'd15, 8'd0, 8'd0, 32'd1979};//{'label': 1979, 'op': 'goto'}
instructions[1979] = {6'd3, 8'd140, 8'd87, 32'd0};//{'dest': 140, 'src': 87, 'op': 'move'}
instructions[1980] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1981] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1982] = {6'd13, 8'd0, 8'd140, 32'd2010};//{'src': 140, 'label': 2010, 'op': 'jmp_if_false'}
instructions[1983] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1984] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1985] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1986] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1987] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1988] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1989] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1990] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1991] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1992] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 140515028047056, 'op': 'memory_read_request'}
instructions[1993] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1994] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 140515028047056, 'op': 'memory_read_wait'}
instructions[1995] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 140515028047056, 'element_size': 2, 'op': 'memory_read'}
instructions[1996] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1997] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1998] = {6'd37, 8'd140, 8'd146, 32'd16};//{'src': 146, 'right': 16, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1999] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[2000] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2001] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2002] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2003] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2004] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2005] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2006] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2007] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2008] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2009] = {6'd15, 8'd0, 8'd0, 32'd2010};//{'label': 2010, 'op': 'goto'}
instructions[2010] = {6'd3, 8'd140, 8'd88, 32'd0};//{'dest': 140, 'src': 88, 'op': 'move'}
instructions[2011] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2012] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2013] = {6'd13, 8'd0, 8'd140, 32'd2041};//{'src': 140, 'label': 2041, 'op': 'jmp_if_false'}
instructions[2014] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[2015] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2016] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2017] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2018] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2019] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2020] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2021] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2022] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2023] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 140515028047776, 'op': 'memory_read_request'}
instructions[2024] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2025] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 140515028047776, 'op': 'memory_read_wait'}
instructions[2026] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 140515028047776, 'element_size': 2, 'op': 'memory_read'}
instructions[2027] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2028] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2029] = {6'd37, 8'd140, 8'd146, 32'd32};//{'src': 146, 'right': 32, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[2030] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[2031] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2032] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2033] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2034] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2035] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2036] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2037] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2038] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2039] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2040] = {6'd15, 8'd0, 8'd0, 32'd2041};//{'label': 2041, 'op': 'goto'}
instructions[2041] = {6'd1, 8'd12, 8'd0, 32'd59};//{'dest': 12, 'label': 59, 'op': 'jmp_and_link'}
instructions[2042] = {6'd0, 8'd141, 8'd0, 32'd49320};//{'dest': 141, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2043] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2044] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2045] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2046] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2047] = {6'd0, 8'd141, 8'd0, 32'd119};//{'dest': 141, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2048] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2049] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2050] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2051] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2052] = {6'd3, 8'd141, 8'd75, 32'd0};//{'dest': 141, 'src': 75, 'op': 'move'}
instructions[2053] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2054] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2055] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2056] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2057] = {6'd3, 8'd141, 8'd76, 32'd0};//{'dest': 141, 'src': 76, 'op': 'move'}
instructions[2058] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2059] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2060] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2061] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2062] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2063] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2064] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2065] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2066] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2067] = {6'd3, 8'd142, 8'd99, 32'd0};//{'dest': 142, 'src': 99, 'op': 'move'}
instructions[2068] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2069] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2070] = {6'd14, 8'd141, 8'd142, 32'd20};//{'src': 142, 'right': 20, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2071] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2072] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2073] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2074] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2075] = {6'd3, 8'd146, 8'd99, 32'd0};//{'dest': 146, 'src': 99, 'op': 'move'}
instructions[2076] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2077] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2078] = {6'd14, 8'd142, 8'd146, 32'd20};//{'src': 146, 'right': 20, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2079] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2080] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2081] = {6'd14, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2082] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2083] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2084] = {6'd32, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2085] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2086] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2087] = {6'd3, 8'd101, 8'd140, 32'd0};//{'dest': 101, 'src': 140, 'op': 'move'}
instructions[2088] = {6'd3, 8'd140, 8'd100, 32'd0};//{'dest': 140, 'src': 100, 'op': 'move'}
instructions[2089] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2090] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2091] = {6'd3, 8'd102, 8'd140, 32'd0};//{'dest': 102, 'src': 140, 'op': 'move'}
instructions[2092] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2093] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2094] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2095] = {6'd3, 8'd103, 8'd140, 32'd0};//{'dest': 103, 'src': 140, 'op': 'move'}
instructions[2096] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2097] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2098] = {6'd3, 8'd141, 8'd103, 32'd0};//{'dest': 141, 'src': 103, 'op': 'move'}
instructions[2099] = {6'd3, 8'd142, 8'd101, 32'd0};//{'dest': 142, 'src': 101, 'op': 'move'}
instructions[2100] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2101] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2102] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2103] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2104] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2105] = {6'd13, 8'd0, 8'd140, 32'd2125};//{'src': 140, 'label': 2125, 'op': 'jmp_if_false'}
instructions[2106] = {6'd3, 8'd142, 8'd102, 32'd0};//{'dest': 142, 'src': 102, 'op': 'move'}
instructions[2107] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2108] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2109] = {6'd11, 8'd146, 8'd142, 32'd98};//{'dest': 146, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2110] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2111] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2112] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028068472, 'op': 'memory_read_request'}
instructions[2113] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2114] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028068472, 'op': 'memory_read_wait'}
instructions[2115] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028068472, 'element_size': 2, 'op': 'memory_read'}
instructions[2116] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2117] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2118] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2119] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2120] = {6'd3, 8'd140, 8'd102, 32'd0};//{'dest': 140, 'src': 102, 'op': 'move'}
instructions[2121] = {6'd14, 8'd102, 8'd102, 32'd1};//{'src': 102, 'right': 1, 'dest': 102, 'signed': False, 'op': '+', 'size': 2}
instructions[2122] = {6'd3, 8'd140, 8'd103, 32'd0};//{'dest': 140, 'src': 103, 'op': 'move'}
instructions[2123] = {6'd14, 8'd103, 8'd103, 32'd1};//{'src': 103, 'right': 1, 'dest': 103, 'signed': False, 'op': '+', 'size': 2}
instructions[2124] = {6'd15, 8'd0, 8'd0, 32'd2096};//{'label': 2096, 'op': 'goto'}
instructions[2125] = {6'd1, 8'd15, 8'd0, 32'd100};//{'dest': 15, 'label': 100, 'op': 'jmp_and_link'}
instructions[2126] = {6'd3, 8'd140, 8'd16, 32'd0};//{'dest': 140, 'src': 16, 'op': 'move'}
instructions[2127] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[2128] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2130] = {6'd14, 8'd141, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2131] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2132] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2133] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2134] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2135] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2136] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2137] = {6'd3, 8'd143, 8'd98, 32'd0};//{'dest': 143, 'src': 98, 'op': 'move'}
instructions[2138] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2139] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2140] = {6'd3, 8'd55, 8'd143, 32'd0};//{'dest': 55, 'src': 143, 'op': 'move'}
instructions[2141] = {6'd3, 8'd142, 8'd99, 32'd0};//{'dest': 142, 'src': 99, 'op': 'move'}
instructions[2142] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2143] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2144] = {6'd14, 8'd141, 8'd142, 32'd40};//{'src': 142, 'right': 40, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2145] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2146] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2147] = {6'd3, 8'd56, 8'd141, 32'd0};//{'dest': 56, 'src': 141, 'op': 'move'}
instructions[2148] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2149] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2150] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2151] = {6'd3, 8'd57, 8'd141, 32'd0};//{'dest': 57, 'src': 141, 'op': 'move'}
instructions[2152] = {6'd3, 8'd141, 8'd75, 32'd0};//{'dest': 141, 'src': 75, 'op': 'move'}
instructions[2153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2154] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2155] = {6'd3, 8'd58, 8'd141, 32'd0};//{'dest': 58, 'src': 141, 'op': 'move'}
instructions[2156] = {6'd3, 8'd141, 8'd76, 32'd0};//{'dest': 141, 'src': 76, 'op': 'move'}
instructions[2157] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2158] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2159] = {6'd3, 8'd59, 8'd141, 32'd0};//{'dest': 59, 'src': 141, 'op': 'move'}
instructions[2160] = {6'd1, 8'd54, 8'd0, 32'd1140};//{'dest': 54, 'label': 1140, 'op': 'jmp_and_link'}
instructions[2161] = {6'd6, 8'd0, 8'd97, 32'd0};//{'src': 97, 'op': 'jmp_to_reg'}
instructions[2162] = {6'd0, 8'd109, 8'd0, 32'd0};//{'dest': 109, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2163] = {6'd0, 8'd110, 8'd0, 32'd0};//{'dest': 110, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2164] = {6'd0, 8'd111, 8'd0, 32'd0};//{'dest': 111, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2165] = {6'd0, 8'd112, 8'd0, 32'd0};//{'dest': 112, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2166] = {6'd0, 8'd113, 8'd0, 32'd0};//{'dest': 113, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2167] = {6'd0, 8'd114, 8'd0, 32'd0};//{'dest': 114, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2168] = {6'd3, 8'd143, 8'd108, 32'd0};//{'dest': 143, 'src': 108, 'op': 'move'}
instructions[2169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2170] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2171] = {6'd3, 8'd65, 8'd143, 32'd0};//{'dest': 65, 'src': 143, 'op': 'move'}
instructions[2172] = {6'd1, 8'd63, 8'd0, 32'd1351};//{'dest': 63, 'label': 1351, 'op': 'jmp_and_link'}
instructions[2173] = {6'd3, 8'd140, 8'd64, 32'd0};//{'dest': 140, 'src': 64, 'op': 'move'}
instructions[2174] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2175] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2176] = {6'd3, 8'd109, 8'd140, 32'd0};//{'dest': 109, 'src': 140, 'op': 'move'}
instructions[2177] = {6'd0, 8'd147, 8'd0, 32'd7};//{'dest': 147, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2178] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2179] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2180] = {6'd11, 8'd149, 8'd147, 32'd108};//{'dest': 149, 'src': 147, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2181] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2183] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 140515028090392, 'op': 'memory_read_request'}
instructions[2184] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2185] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 140515028090392, 'op': 'memory_read_wait'}
instructions[2186] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 140515028090392, 'element_size': 2, 'op': 'memory_read'}
instructions[2187] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2188] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2189] = {6'd32, 8'd142, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 142, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2190] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2191] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2192] = {6'd12, 8'd141, 8'd142, 32'd15};//{'src': 142, 'right': 15, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2195] = {6'd33, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '<<', 'type': 'int', 'size': 2}
instructions[2196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2198] = {6'd3, 8'd110, 8'd140, 32'd0};//{'dest': 110, 'src': 140, 'op': 'move'}
instructions[2199] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2200] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2201] = {6'd3, 8'd141, 8'd110, 32'd0};//{'dest': 141, 'src': 110, 'op': 'move'}
instructions[2202] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2203] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2204] = {6'd14, 8'd140, 8'd141, 32'd7};//{'src': 141, 'right': 7, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2205] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2206] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2207] = {6'd3, 8'd111, 8'd140, 32'd0};//{'dest': 111, 'src': 140, 'op': 'move'}
instructions[2208] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2210] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2211] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2213] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2214] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 140515028497040, 'op': 'memory_read_request'}
instructions[2215] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2216] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 140515028497040, 'op': 'memory_read_wait'}
instructions[2217] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 140515028497040, 'element_size': 2, 'op': 'memory_read'}
instructions[2218] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2219] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2220] = {6'd3, 8'd112, 8'd140, 32'd0};//{'dest': 112, 'src': 140, 'op': 'move'}
instructions[2221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2222] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2223] = {6'd3, 8'd141, 8'd112, 32'd0};//{'dest': 141, 'src': 112, 'op': 'move'}
instructions[2224] = {6'd3, 8'd146, 8'd110, 32'd0};//{'dest': 146, 'src': 110, 'op': 'move'}
instructions[2225] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2226] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2227] = {6'd33, 8'd142, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 142, 'signed': False, 'op': '<<', 'type': 'int', 'size': 2}
instructions[2228] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2230] = {6'd34, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[2231] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2232] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2233] = {6'd3, 8'd113, 8'd140, 32'd0};//{'dest': 113, 'src': 140, 'op': 'move'}
instructions[2234] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2235] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2236] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2237] = {6'd14, 8'd146, 8'd149, 32'd6};//{'src': 149, 'right': 6, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2238] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2239] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2240] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2241] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2242] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2243] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028101168, 'op': 'memory_read_request'}
instructions[2244] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2245] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028101168, 'op': 'memory_read_wait'}
instructions[2246] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140515028101168, 'element_size': 2, 'op': 'memory_read'}
instructions[2247] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2248] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2249] = {6'd12, 8'd141, 8'd142, 32'd61440};//{'src': 142, 'right': 61440, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2250] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2251] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2252] = {6'd32, 8'd140, 8'd141, 32'd10};//{'src': 141, 'right': 10, 'dest': 140, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2253] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2255] = {6'd3, 8'd114, 8'd140, 32'd0};//{'dest': 114, 'src': 140, 'op': 'move'}
instructions[2256] = {6'd3, 8'd141, 8'd113, 32'd0};//{'dest': 141, 'src': 113, 'op': 'move'}
instructions[2257] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2258] = {6'd3, 8'd142, 8'd114, 32'd0};//{'dest': 142, 'src': 114, 'op': 'move'}
instructions[2259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2260] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2261] = {6'd34, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[2262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2263] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2264] = {6'd3, 8'd104, 8'd140, 32'd0};//{'dest': 104, 'src': 140, 'op': 'move'}
instructions[2265] = {6'd3, 8'd141, 8'd111, 32'd0};//{'dest': 141, 'src': 111, 'op': 'move'}
instructions[2266] = {6'd3, 8'd146, 8'd114, 32'd0};//{'dest': 146, 'src': 114, 'op': 'move'}
instructions[2267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2268] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2269] = {6'd32, 8'd142, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 142, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2270] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2271] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2272] = {6'd11, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2273] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2274] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2275] = {6'd3, 8'd105, 8'd140, 32'd0};//{'dest': 105, 'src': 140, 'op': 'move'}
instructions[2276] = {6'd3, 8'd146, 8'd111, 32'd0};//{'dest': 146, 'src': 111, 'op': 'move'}
instructions[2277] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2278] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2279] = {6'd14, 8'd141, 8'd146, 32'd0};//{'src': 146, 'right': 0, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2280] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2282] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2283] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2284] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2285] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 140515028070344, 'op': 'memory_read_request'}
instructions[2286] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2287] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 140515028070344, 'op': 'memory_read_wait'}
instructions[2288] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 140515028070344, 'element_size': 2, 'op': 'memory_read'}
instructions[2289] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2291] = {6'd3, 8'd89, 8'd140, 32'd0};//{'dest': 89, 'src': 140, 'op': 'move'}
instructions[2292] = {6'd3, 8'd146, 8'd111, 32'd0};//{'dest': 146, 'src': 111, 'op': 'move'}
instructions[2293] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2295] = {6'd14, 8'd141, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2296] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2297] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2298] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2299] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2301] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 140515028087008, 'op': 'memory_read_request'}
instructions[2302] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2303] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 140515028087008, 'op': 'memory_read_wait'}
instructions[2304] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 140515028087008, 'element_size': 2, 'op': 'memory_read'}
instructions[2305] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2306] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2307] = {6'd3, 8'd90, 8'd140, 32'd0};//{'dest': 90, 'src': 140, 'op': 'move'}
instructions[2308] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2309] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2311] = {6'd14, 8'd146, 8'd149, 32'd2};//{'src': 149, 'right': 2, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2312] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2313] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2314] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2315] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2316] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2317] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028099800, 'op': 'memory_read_request'}
instructions[2318] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2319] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028099800, 'op': 'memory_read_wait'}
instructions[2320] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028099800, 'element_size': 2, 'op': 'memory_read'}
instructions[2321] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2322] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2323] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2324] = {6'd11, 8'd142, 8'd141, 32'd91};//{'dest': 142, 'src': 141, 'srcb': 91, 'signed': False, 'op': '+'}
instructions[2325] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2326] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2327] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2328] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2329] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2330] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2331] = {6'd14, 8'd146, 8'd149, 32'd3};//{'src': 149, 'right': 3, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2332] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2333] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2334] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2335] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2336] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2337] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028099944, 'op': 'memory_read_request'}
instructions[2338] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2339] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028099944, 'op': 'memory_read_wait'}
instructions[2340] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028099944, 'element_size': 2, 'op': 'memory_read'}
instructions[2341] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2342] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2343] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2344] = {6'd11, 8'd142, 8'd141, 32'd91};//{'dest': 142, 'src': 141, 'srcb': 91, 'signed': False, 'op': '+'}
instructions[2345] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2346] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2347] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2348] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2349] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2350] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2351] = {6'd14, 8'd146, 8'd149, 32'd4};//{'src': 149, 'right': 4, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2352] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2353] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2354] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2355] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2356] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2357] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028100664, 'op': 'memory_read_request'}
instructions[2358] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2359] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028100664, 'op': 'memory_read_wait'}
instructions[2360] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028100664, 'element_size': 2, 'op': 'memory_read'}
instructions[2361] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2363] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2364] = {6'd11, 8'd142, 8'd141, 32'd92};//{'dest': 142, 'src': 141, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[2365] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2366] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2367] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2368] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2369] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2370] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2371] = {6'd14, 8'd146, 8'd149, 32'd5};//{'src': 149, 'right': 5, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2372] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2373] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2374] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2376] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2377] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028101456, 'op': 'memory_read_request'}
instructions[2378] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2379] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028101456, 'op': 'memory_read_wait'}
instructions[2380] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028101456, 'element_size': 2, 'op': 'memory_read'}
instructions[2381] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2382] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2383] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2384] = {6'd11, 8'd142, 8'd141, 32'd92};//{'dest': 142, 'src': 141, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[2385] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2386] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2387] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2388] = {6'd3, 8'd146, 8'd111, 32'd0};//{'dest': 146, 'src': 111, 'op': 'move'}
instructions[2389] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2390] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2391] = {6'd14, 8'd141, 8'd146, 32'd7};//{'src': 146, 'right': 7, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2392] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2393] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2394] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2395] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2396] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2397] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 140515028101960, 'op': 'memory_read_request'}
instructions[2398] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2399] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 140515028101960, 'op': 'memory_read_wait'}
instructions[2400] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 140515028101960, 'element_size': 2, 'op': 'memory_read'}
instructions[2401] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2402] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2403] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2404] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2405] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2406] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2407] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2408] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2409] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2410] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028102464, 'op': 'memory_read_request'}
instructions[2411] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2412] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028102464, 'op': 'memory_read_wait'}
instructions[2413] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028102464, 'element_size': 2, 'op': 'memory_read'}
instructions[2414] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2415] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2416] = {6'd12, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2418] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2419] = {6'd3, 8'd93, 8'd140, 32'd0};//{'dest': 93, 'src': 140, 'op': 'move'}
instructions[2420] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2421] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2422] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2423] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2424] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2425] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2426] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2427] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2428] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2429] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028103112, 'op': 'memory_read_request'}
instructions[2430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2431] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028103112, 'op': 'memory_read_wait'}
instructions[2432] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028103112, 'element_size': 2, 'op': 'memory_read'}
instructions[2433] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2434] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2435] = {6'd12, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2436] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2437] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2438] = {6'd3, 8'd94, 8'd140, 32'd0};//{'dest': 94, 'src': 140, 'op': 'move'}
instructions[2439] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2440] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2441] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2442] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2443] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2444] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2445] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2446] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2447] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2448] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028116112, 'op': 'memory_read_request'}
instructions[2449] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2450] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028116112, 'op': 'memory_read_wait'}
instructions[2451] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028116112, 'element_size': 2, 'op': 'memory_read'}
instructions[2452] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2453] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2454] = {6'd12, 8'd140, 8'd141, 32'd4};//{'src': 141, 'right': 4, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2456] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2457] = {6'd3, 8'd95, 8'd140, 32'd0};//{'dest': 95, 'src': 140, 'op': 'move'}
instructions[2458] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2459] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2460] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2461] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2462] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2463] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2464] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2465] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2466] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2467] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028116760, 'op': 'memory_read_request'}
instructions[2468] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2469] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028116760, 'op': 'memory_read_wait'}
instructions[2470] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028116760, 'element_size': 2, 'op': 'memory_read'}
instructions[2471] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2472] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2473] = {6'd12, 8'd140, 8'd141, 32'd8};//{'src': 141, 'right': 8, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2474] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2475] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2477] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2478] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2479] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2480] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2481] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2482] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2483] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028117408, 'op': 'memory_read_request'}
instructions[2484] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2485] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028117408, 'op': 'memory_read_wait'}
instructions[2486] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028117408, 'element_size': 2, 'op': 'memory_read'}
instructions[2487] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2488] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2489] = {6'd12, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2490] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2491] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2492] = {6'd3, 8'd96, 8'd140, 32'd0};//{'dest': 96, 'src': 140, 'op': 'move'}
instructions[2493] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2494] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2495] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2496] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2497] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2498] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2499] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2500] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2501] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2502] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028118056, 'op': 'memory_read_request'}
instructions[2503] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2504] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028118056, 'op': 'memory_read_wait'}
instructions[2505] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028118056, 'element_size': 2, 'op': 'memory_read'}
instructions[2506] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2507] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2508] = {6'd12, 8'd140, 8'd141, 32'd32};//{'src': 141, 'right': 32, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2509] = {6'd3, 8'd140, 8'd109, 32'd0};//{'dest': 140, 'src': 109, 'op': 'move'}
instructions[2510] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2511] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2512] = {6'd3, 8'd107, 8'd140, 32'd0};//{'dest': 107, 'src': 140, 'op': 'move'}
instructions[2513] = {6'd6, 8'd0, 8'd106, 32'd0};//{'src': 106, 'op': 'jmp_to_reg'}
instructions[2514] = {6'd0, 8'd119, 8'd0, 32'd0};//{'dest': 119, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2515] = {6'd0, 8'd120, 8'd0, 32'd0};//{'dest': 120, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2516] = {6'd3, 8'd140, 8'd117, 32'd0};//{'dest': 140, 'src': 117, 'op': 'move'}
instructions[2517] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2518] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2519] = {6'd3, 8'd120, 8'd140, 32'd0};//{'dest': 120, 'src': 140, 'op': 'move'}
instructions[2520] = {6'd3, 8'd141, 8'd118, 32'd0};//{'dest': 141, 'src': 118, 'op': 'move'}
instructions[2521] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2522] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2523] = {6'd3, 8'd3, 8'd141, 32'd0};//{'dest': 3, 'src': 141, 'op': 'move'}
instructions[2524] = {6'd1, 8'd2, 8'd0, 32'd39};//{'dest': 2, 'label': 39, 'op': 'jmp_and_link'}
instructions[2525] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2526] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2527] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2528] = {6'd3, 8'd119, 8'd140, 32'd0};//{'dest': 119, 'src': 140, 'op': 'move'}
instructions[2529] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2531] = {6'd3, 8'd141, 8'd119, 32'd0};//{'dest': 141, 'src': 119, 'op': 'move'}
instructions[2532] = {6'd3, 8'd142, 8'd118, 32'd0};//{'dest': 142, 'src': 118, 'op': 'move'}
instructions[2533] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2534] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2535] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2536] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2537] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2538] = {6'd13, 8'd0, 8'd140, 32'd2563};//{'src': 140, 'label': 2563, 'op': 'jmp_if_false'}
instructions[2539] = {6'd3, 8'd142, 8'd120, 32'd0};//{'dest': 142, 'src': 120, 'op': 'move'}
instructions[2540] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2541] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2542] = {6'd11, 8'd146, 8'd142, 32'd116};//{'dest': 146, 'src': 142, 'srcb': 116, 'signed': False, 'op': '+'}
instructions[2543] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2544] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2545] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028142200, 'op': 'memory_read_request'}
instructions[2546] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2547] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028142200, 'op': 'memory_read_wait'}
instructions[2548] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028142200, 'element_size': 2, 'op': 'memory_read'}
instructions[2549] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2550] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2551] = {6'd3, 8'd3, 8'd141, 32'd0};//{'dest': 3, 'src': 141, 'op': 'move'}
instructions[2552] = {6'd1, 8'd2, 8'd0, 32'd39};//{'dest': 2, 'label': 39, 'op': 'jmp_and_link'}
instructions[2553] = {6'd3, 8'd140, 8'd120, 32'd0};//{'dest': 140, 'src': 120, 'op': 'move'}
instructions[2554] = {6'd14, 8'd120, 8'd120, 32'd1};//{'src': 120, 'right': 1, 'dest': 120, 'signed': False, 'op': '+', 'size': 2}
instructions[2555] = {6'd3, 8'd141, 8'd119, 32'd0};//{'dest': 141, 'src': 119, 'op': 'move'}
instructions[2556] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2557] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2558] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2559] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2560] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2561] = {6'd3, 8'd119, 8'd140, 32'd0};//{'dest': 119, 'src': 140, 'op': 'move'}
instructions[2562] = {6'd15, 8'd0, 8'd0, 32'd2529};//{'label': 2529, 'op': 'goto'}
instructions[2563] = {6'd6, 8'd0, 8'd115, 32'd0};//{'src': 115, 'op': 'jmp_to_reg'}
instructions[2564] = {6'd0, 8'd125, 8'd0, 32'd0};//{'dest': 125, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2565] = {6'd0, 8'd126, 8'd0, 32'd0};//{'dest': 126, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2566] = {6'd0, 8'd127, 8'd0, 32'd0};//{'dest': 127, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2567] = {6'd38, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'input': 'socket', 'op': 'ready'}
instructions[2568] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2569] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2570] = {6'd39, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': True, 'op': '==', 'type': 'int', 'size': 2}
instructions[2571] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2572] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2573] = {6'd13, 8'd0, 8'd140, 32'd2580};//{'src': 140, 'label': 2580, 'op': 'jmp_if_false'}
instructions[2574] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2575] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2576] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2577] = {6'd3, 8'd122, 8'd140, 32'd0};//{'dest': 122, 'src': 140, 'op': 'move'}
instructions[2578] = {6'd6, 8'd0, 8'd121, 32'd0};//{'src': 121, 'op': 'jmp_to_reg'}
instructions[2579] = {6'd15, 8'd0, 8'd0, 32'd2580};//{'label': 2580, 'op': 'goto'}
instructions[2580] = {6'd3, 8'd140, 8'd124, 32'd0};//{'dest': 140, 'src': 124, 'op': 'move'}
instructions[2581] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2582] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2583] = {6'd3, 8'd126, 8'd140, 32'd0};//{'dest': 126, 'src': 140, 'op': 'move'}
instructions[2584] = {6'd1, 8'd8, 8'd0, 32'd54};//{'dest': 8, 'label': 54, 'op': 'jmp_and_link'}
instructions[2585] = {6'd3, 8'd140, 8'd9, 32'd0};//{'dest': 140, 'src': 9, 'op': 'move'}
instructions[2586] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2587] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2588] = {6'd3, 8'd127, 8'd140, 32'd0};//{'dest': 127, 'src': 140, 'op': 'move'}
instructions[2589] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2590] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2591] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2592] = {6'd3, 8'd125, 8'd140, 32'd0};//{'dest': 125, 'src': 140, 'op': 'move'}
instructions[2593] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2594] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2595] = {6'd3, 8'd141, 8'd125, 32'd0};//{'dest': 141, 'src': 125, 'op': 'move'}
instructions[2596] = {6'd3, 8'd142, 8'd127, 32'd0};//{'dest': 142, 'src': 127, 'op': 'move'}
instructions[2597] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2598] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2599] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2600] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2601] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2602] = {6'd13, 8'd0, 8'd140, 32'd2622};//{'src': 140, 'label': 2622, 'op': 'jmp_if_false'}
instructions[2603] = {6'd1, 8'd8, 8'd0, 32'd54};//{'dest': 8, 'label': 54, 'op': 'jmp_and_link'}
instructions[2604] = {6'd3, 8'd140, 8'd9, 32'd0};//{'dest': 140, 'src': 9, 'op': 'move'}
instructions[2605] = {6'd3, 8'd141, 8'd126, 32'd0};//{'dest': 141, 'src': 126, 'op': 'move'}
instructions[2606] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2607] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2608] = {6'd11, 8'd142, 8'd141, 32'd123};//{'dest': 142, 'src': 141, 'srcb': 123, 'signed': False, 'op': '+'}
instructions[2609] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2610] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2611] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2612] = {6'd3, 8'd140, 8'd126, 32'd0};//{'dest': 140, 'src': 126, 'op': 'move'}
instructions[2613] = {6'd14, 8'd126, 8'd126, 32'd1};//{'src': 126, 'right': 1, 'dest': 126, 'signed': False, 'op': '+', 'size': 2}
instructions[2614] = {6'd3, 8'd141, 8'd125, 32'd0};//{'dest': 141, 'src': 125, 'op': 'move'}
instructions[2615] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2616] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2617] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2618] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2619] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2620] = {6'd3, 8'd125, 8'd140, 32'd0};//{'dest': 125, 'src': 140, 'op': 'move'}
instructions[2621] = {6'd15, 8'd0, 8'd0, 32'd2593};//{'label': 2593, 'op': 'goto'}
instructions[2622] = {6'd3, 8'd140, 8'd127, 32'd0};//{'dest': 140, 'src': 127, 'op': 'move'}
instructions[2623] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2624] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2625] = {6'd3, 8'd122, 8'd140, 32'd0};//{'dest': 122, 'src': 140, 'op': 'move'}
instructions[2626] = {6'd6, 8'd0, 8'd121, 32'd0};//{'src': 121, 'op': 'jmp_to_reg'}
instructions[2627] = {6'd0, 8'd129, 8'd0, 32'd638};//{'dest': 129, 'literal': 638, 'op': 'literal'}
instructions[2628] = {6'd0, 8'd130, 8'd0, 32'd1662};//{'dest': 130, 'literal': 1662, 'op': 'literal'}
instructions[2629] = {6'd0, 8'd131, 8'd0, 32'd27};//{'dest': 131, 'literal': 27, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2630] = {6'd0, 8'd132, 8'd0, 32'd0};//{'dest': 132, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2631] = {6'd0, 8'd133, 8'd0, 32'd0};//{'dest': 133, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2632] = {6'd0, 8'd134, 8'd0, 32'd0};//{'dest': 134, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2633] = {6'd0, 8'd135, 8'd0, 32'd0};//{'dest': 135, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2634] = {6'd0, 8'd136, 8'd0, 32'd0};//{'dest': 136, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2635] = {6'd0, 8'd137, 8'd0, 32'd0};//{'dest': 137, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2636] = {6'd0, 8'd138, 8'd0, 32'd0};//{'dest': 138, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2637] = {6'd0, 8'd139, 8'd0, 32'd0};//{'dest': 139, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2638] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2639] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2640] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2641] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2642] = {6'd27, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': True, 'op': '+'}
instructions[2643] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2644] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2645] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2646] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2647] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2648] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2649] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2650] = {6'd27, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': True, 'op': '+'}
instructions[2651] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2652] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2653] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2654] = {6'd3, 8'd140, 8'd133, 32'd0};//{'dest': 140, 'src': 133, 'op': 'move'}
instructions[2655] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2656] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2657] = {6'd13, 8'd0, 8'd140, 32'd2661};//{'src': 140, 'label': 2661, 'op': 'jmp_if_false'}
instructions[2658] = {6'd3, 8'd140, 8'd133, 32'd0};//{'dest': 140, 'src': 133, 'op': 'move'}
instructions[2659] = {6'd35, 8'd133, 8'd133, 32'd1};//{'src': 133, 'right': 1, 'dest': 133, 'signed': False, 'op': '-', 'size': 2}
instructions[2660] = {6'd15, 8'd0, 8'd0, 32'd2928};//{'label': 2928, 'op': 'goto'}
instructions[2661] = {6'd0, 8'd140, 8'd0, 32'd120};//{'dest': 140, 'literal': 120, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2662] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2663] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2664] = {6'd3, 8'd133, 8'd140, 32'd0};//{'dest': 133, 'src': 140, 'op': 'move'}
instructions[2665] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2666] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2667] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2668] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[2669] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2670] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2671] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2672] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[2673] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2674] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2675] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2676] = {6'd3, 8'd83, 8'd140, 32'd0};//{'dest': 83, 'src': 140, 'op': 'move'}
instructions[2677] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2678] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2679] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2680] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[2681] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2682] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2683] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2684] = {6'd3, 8'd85, 8'd140, 32'd0};//{'dest': 85, 'src': 140, 'op': 'move'}
instructions[2685] = {6'd0, 8'd140, 8'd0, 32'd46};//{'dest': 140, 'literal': 46, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2686] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2687] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2688] = {6'd40, 8'd0, 8'd140, 32'd0};//{'src': 140, 'signed': True, 'file': '/home/amer/Nexys3/TCP3/source/server.h', 'line': 542, 'type': 'int', 'op': 'report'}
instructions[2689] = {6'd0, 8'd141, 8'd0, 32'd46};//{'dest': 141, 'literal': 46, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2690] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2691] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2692] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[2693] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[2694] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2695] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2696] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2697] = {6'd3, 8'd136, 8'd140, 32'd0};//{'dest': 136, 'src': 140, 'op': 'move'}
instructions[2698] = {6'd0, 8'd140, 8'd0, 32'd24};//{'dest': 140, 'literal': 24, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2699] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2700] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2701] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2702] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2703] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2704] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2705] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2706] = {6'd0, 8'd140, 8'd0, 32'd62290};//{'dest': 140, 'literal': 62290, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2707] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2708] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2709] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2710] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2711] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2712] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2713] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2714] = {6'd0, 8'd140, 8'd0, 32'd64494};//{'dest': 140, 'literal': 64494, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2715] = {6'd0, 8'd141, 8'd0, 32'd2};//{'dest': 141, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2716] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2717] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2718] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2719] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2720] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2721] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2722] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2723] = {6'd0, 8'd141, 8'd0, 32'd3};//{'dest': 141, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2724] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2725] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2726] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2727] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2728] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2729] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2730] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2731] = {6'd0, 8'd141, 8'd0, 32'd4};//{'dest': 141, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2732] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2733] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2734] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2735] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2736] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2737] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2738] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2739] = {6'd0, 8'd141, 8'd0, 32'd5};//{'dest': 141, 'literal': 5, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2740] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2741] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2742] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2743] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2744] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2745] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2746] = {6'd0, 8'd140, 8'd0, 32'd2054};//{'dest': 140, 'literal': 2054, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2747] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2748] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2749] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2750] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2751] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2752] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2753] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2754] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2755] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2756] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2757] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2758] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2759] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2760] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2761] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2762] = {6'd0, 8'd140, 8'd0, 32'd2048};//{'dest': 140, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2763] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2764] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2765] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2766] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2767] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2768] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2769] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2770] = {6'd0, 8'd140, 8'd0, 32'd1540};//{'dest': 140, 'literal': 1540, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2771] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2772] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2773] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2774] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2775] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2776] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2777] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2778] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2779] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2780] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2781] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2782] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2783] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2784] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2785] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2786] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2787] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2788] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2789] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2790] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2791] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2792] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2793] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2794] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2795] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2796] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2797] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2798] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2799] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2800] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2801] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2802] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2803] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2804] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2805] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2806] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2807] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2808] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2809] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2810] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2811] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2812] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2813] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2814] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2815] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2816] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2817] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2818] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2819] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2820] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2821] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2822] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2823] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2824] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2825] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2826] = {6'd0, 8'd140, 8'd0, 32'd24};//{'dest': 140, 'literal': 24, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2827] = {6'd0, 8'd141, 8'd0, 32'd16};//{'dest': 141, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2828] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2829] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2830] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2831] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2832] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2833] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2834] = {6'd0, 8'd140, 8'd0, 32'd62290};//{'dest': 140, 'literal': 62290, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2835] = {6'd0, 8'd141, 8'd0, 32'd17};//{'dest': 141, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2836] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2837] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2838] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2839] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2840] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2841] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2842] = {6'd0, 8'd140, 8'd0, 32'd64494};//{'dest': 140, 'literal': 64494, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2843] = {6'd0, 8'd141, 8'd0, 32'd18};//{'dest': 141, 'literal': 18, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2844] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2845] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2846] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2847] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2848] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2849] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2850] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2851] = {6'd0, 8'd141, 8'd0, 32'd19};//{'dest': 141, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2852] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2853] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2854] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2855] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2856] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2857] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2858] = {6'd0, 8'd140, 8'd0, 32'd105};//{'dest': 140, 'literal': 105, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2859] = {6'd0, 8'd141, 8'd0, 32'd20};//{'dest': 141, 'literal': 20, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2860] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2861] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2862] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2863] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2864] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2865] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2866] = {6'd0, 8'd140, 8'd0, 32'd58291};//{'dest': 140, 'literal': 58291, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2867] = {6'd0, 8'd141, 8'd0, 32'd21};//{'dest': 141, 'literal': 21, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2868] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2869] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2870] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2871] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2872] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2873] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2874] = {6'd0, 8'd140, 8'd0, 32'd12976};//{'dest': 140, 'literal': 12976, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2875] = {6'd0, 8'd141, 8'd0, 32'd22};//{'dest': 141, 'literal': 22, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2876] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2877] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2878] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2879] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2880] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2881] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2882] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2883] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2884] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2885] = {6'd3, 8'd135, 8'd140, 32'd0};//{'dest': 135, 'src': 140, 'op': 'move'}
instructions[2886] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2887] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2888] = {6'd3, 8'd141, 8'd135, 32'd0};//{'dest': 141, 'src': 135, 'op': 'move'}
instructions[2889] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2890] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2891] = {6'd28, 8'd140, 8'd141, 32'd46};//{'src': 141, 'right': 46, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2892] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2893] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2894] = {6'd13, 8'd0, 8'd140, 32'd2919};//{'src': 140, 'label': 2919, 'op': 'jmp_if_false'}
instructions[2895] = {6'd3, 8'd142, 8'd136, 32'd0};//{'dest': 142, 'src': 136, 'op': 'move'}
instructions[2896] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2897] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2898] = {6'd11, 8'd146, 8'd142, 32'd130};//{'dest': 146, 'src': 142, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2899] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2900] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2901] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028221536, 'op': 'memory_read_request'}
instructions[2902] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2903] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515028221536, 'op': 'memory_read_wait'}
instructions[2904] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515028221536, 'element_size': 2, 'op': 'memory_read'}
instructions[2905] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2906] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2907] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[2908] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[2909] = {6'd3, 8'd140, 8'd136, 32'd0};//{'dest': 140, 'src': 136, 'op': 'move'}
instructions[2910] = {6'd14, 8'd136, 8'd136, 32'd1};//{'src': 136, 'right': 1, 'dest': 136, 'signed': False, 'op': '+', 'size': 2}
instructions[2911] = {6'd3, 8'd141, 8'd135, 32'd0};//{'dest': 141, 'src': 135, 'op': 'move'}
instructions[2912] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2913] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2914] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2915] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2916] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2917] = {6'd3, 8'd135, 8'd140, 32'd0};//{'dest': 135, 'src': 140, 'op': 'move'}
instructions[2918] = {6'd15, 8'd0, 8'd0, 32'd2886};//{'label': 2886, 'op': 'goto'}
instructions[2919] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[2920] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2921] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2922] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[2923] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2924] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2925] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2926] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[2927] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[2928] = {6'd3, 8'd140, 8'd139, 32'd0};//{'dest': 140, 'src': 139, 'op': 'move'}
instructions[2929] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2930] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2931] = {6'd39, 8'd141, 8'd140, 32'd0};//{'src': 140, 'right': 0, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2932] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2933] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2934] = {6'd22, 8'd0, 8'd141, 32'd2951};//{'src': 141, 'label': 2951, 'op': 'jmp_if_true'}
instructions[2935] = {6'd39, 8'd141, 8'd140, 32'd1};//{'src': 140, 'right': 1, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2936] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2937] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2938] = {6'd22, 8'd0, 8'd141, 32'd2968};//{'src': 141, 'label': 2968, 'op': 'jmp_if_true'}
instructions[2939] = {6'd39, 8'd141, 8'd140, 32'd2};//{'src': 140, 'right': 2, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2940] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2941] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2942] = {6'd22, 8'd0, 8'd141, 32'd3034};//{'src': 141, 'label': 3034, 'op': 'jmp_if_true'}
instructions[2943] = {6'd39, 8'd141, 8'd140, 32'd3};//{'src': 140, 'right': 3, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2944] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2945] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2946] = {6'd22, 8'd0, 8'd141, 32'd3113};//{'src': 141, 'label': 3113, 'op': 'jmp_if_true'}
instructions[2947] = {6'd39, 8'd141, 8'd140, 32'd4};//{'src': 140, 'right': 4, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2948] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2949] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2950] = {6'd22, 8'd0, 8'd141, 32'd3123};//{'src': 141, 'label': 3123, 'op': 'jmp_if_true'}
instructions[2951] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2952] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2953] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2954] = {6'd3, 8'd85, 8'd140, 32'd0};//{'dest': 85, 'src': 140, 'op': 'move'}
instructions[2955] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2956] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2957] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2958] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[2959] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2960] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2961] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2962] = {6'd3, 8'd83, 8'd140, 32'd0};//{'dest': 83, 'src': 140, 'op': 'move'}
instructions[2963] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2964] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2965] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2966] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[2967] = {6'd15, 8'd0, 8'd0, 32'd3155};//{'label': 3155, 'op': 'goto'}
instructions[2968] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2969] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2970] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2971] = {6'd11, 8'd142, 8'd141, 32'd129};//{'dest': 142, 'src': 141, 'srcb': 129, 'signed': False, 'op': '+'}
instructions[2972] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2973] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2974] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 140515028171664, 'op': 'memory_read_request'}
instructions[2975] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2976] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 140515028171664, 'op': 'memory_read_wait'}
instructions[2977] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 140515028171664, 'element_size': 2, 'op': 'memory_read'}
instructions[2978] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2979] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2980] = {6'd3, 8'd75, 8'd140, 32'd0};//{'dest': 75, 'src': 140, 'op': 'move'}
instructions[2981] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2982] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2983] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2984] = {6'd11, 8'd142, 8'd141, 32'd129};//{'dest': 142, 'src': 141, 'srcb': 129, 'signed': False, 'op': '+'}
instructions[2985] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2986] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2987] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 140515028221104, 'op': 'memory_read_request'}
instructions[2988] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2989] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 140515028221104, 'op': 'memory_read_wait'}
instructions[2990] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 140515028221104, 'element_size': 2, 'op': 'memory_read'}
instructions[2991] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2992] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2993] = {6'd3, 8'd76, 8'd140, 32'd0};//{'dest': 76, 'src': 140, 'op': 'move'}
instructions[2994] = {6'd3, 8'd140, 8'd89, 32'd0};//{'dest': 140, 'src': 89, 'op': 'move'}
instructions[2995] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2996] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2997] = {6'd3, 8'd78, 8'd140, 32'd0};//{'dest': 78, 'src': 140, 'op': 'move'}
instructions[2998] = {6'd0, 8'd140, 8'd0, 32'd80};//{'dest': 140, 'literal': 80, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2999] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3000] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3001] = {6'd3, 8'd77, 8'd140, 32'd0};//{'dest': 77, 'src': 140, 'op': 'move'}
instructions[3002] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[3003] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3004] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3005] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3006] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[3007] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3008] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3009] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3010] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3011] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3012] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3013] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3014] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3015] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3016] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3017] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3018] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3019] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[3020] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3021] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3022] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3023] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[3024] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3025] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3026] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3027] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3028] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3029] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3030] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3031] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3032] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3033] = {6'd15, 8'd0, 8'd0, 32'd3155};//{'label': 3155, 'op': 'goto'}
instructions[3034] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3035] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3036] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3037] = {6'd3, 8'd123, 8'd151, 32'd0};//{'dest': 123, 'src': 151, 'op': 'move'}
instructions[3038] = {6'd3, 8'd141, 8'd131, 32'd0};//{'dest': 141, 'src': 131, 'op': 'move'}
instructions[3039] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3040] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3041] = {6'd3, 8'd124, 8'd141, 32'd0};//{'dest': 124, 'src': 141, 'op': 'move'}
instructions[3042] = {6'd1, 8'd121, 8'd0, 32'd2564};//{'dest': 121, 'label': 2564, 'op': 'jmp_and_link'}
instructions[3043] = {6'd3, 8'd140, 8'd122, 32'd0};//{'dest': 140, 'src': 122, 'op': 'move'}
instructions[3044] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3045] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3046] = {6'd3, 8'd132, 8'd140, 32'd0};//{'dest': 132, 'src': 140, 'op': 'move'}
instructions[3047] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3048] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3049] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3050] = {6'd11, 8'd147, 8'd146, 32'd80};//{'dest': 147, 'src': 146, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3051] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3052] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3053] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028231952, 'op': 'memory_read_request'}
instructions[3054] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3055] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028231952, 'op': 'memory_read_wait'}
instructions[3056] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028231952, 'element_size': 2, 'op': 'memory_read'}
instructions[3057] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3058] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3059] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3060] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[3061] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3062] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3063] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3064] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3065] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3066] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3067] = {6'd11, 8'd147, 8'd146, 32'd80};//{'dest': 147, 'src': 146, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3068] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3069] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3070] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028232384, 'op': 'memory_read_request'}
instructions[3071] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3072] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028232384, 'op': 'memory_read_wait'}
instructions[3073] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028232384, 'element_size': 2, 'op': 'memory_read'}
instructions[3074] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3075] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3076] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3077] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[3078] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3079] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3080] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3081] = {6'd3, 8'd143, 8'd80, 32'd0};//{'dest': 143, 'src': 80, 'op': 'move'}
instructions[3082] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3083] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3084] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3085] = {6'd3, 8'd143, 8'd79, 32'd0};//{'dest': 143, 'src': 79, 'op': 'move'}
instructions[3086] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3087] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3088] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3089] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[3090] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3091] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3092] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3093] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3094] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3095] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3096] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3097] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3098] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[3099] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3100] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3101] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3102] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[3103] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3104] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3105] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3106] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3107] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[3108] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3109] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3110] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3111] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3112] = {6'd15, 8'd0, 8'd0, 32'd3155};//{'label': 3155, 'op': 'goto'}
instructions[3113] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3114] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3115] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3116] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3117] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[3118] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3119] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3120] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3121] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3122] = {6'd15, 8'd0, 8'd0, 32'd3155};//{'label': 3155, 'op': 'goto'}
instructions[3123] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3124] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3125] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3126] = {6'd3, 8'd83, 8'd140, 32'd0};//{'dest': 83, 'src': 140, 'op': 'move'}
instructions[3127] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3128] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3130] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[3131] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[3132] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3133] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3134] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3135] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[3136] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3137] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3138] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3139] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3140] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3141] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3142] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3143] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3144] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3145] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3146] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3147] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3148] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3149] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3150] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3151] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3152] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3153] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3154] = {6'd15, 8'd0, 8'd0, 32'd3155};//{'label': 3155, 'op': 'goto'}
instructions[3155] = {6'd0, 8'd140, 8'd0, 32'd10000};//{'dest': 140, 'literal': 10000, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3156] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3157] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3158] = {6'd3, 8'd134, 8'd140, 32'd0};//{'dest': 134, 'src': 140, 'op': 'move'}
instructions[3159] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3160] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3161] = {6'd3, 8'd140, 8'd134, 32'd0};//{'dest': 140, 'src': 134, 'op': 'move'}
instructions[3162] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3163] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3164] = {6'd13, 8'd0, 8'd140, 32'd3550};//{'src': 140, 'label': 3550, 'op': 'jmp_if_false'}
instructions[3165] = {6'd3, 8'd151, 8'd129, 32'd0};//{'dest': 151, 'src': 129, 'op': 'move'}
instructions[3166] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3167] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3168] = {6'd3, 8'd108, 8'd151, 32'd0};//{'dest': 108, 'src': 151, 'op': 'move'}
instructions[3169] = {6'd1, 8'd106, 8'd0, 32'd2162};//{'dest': 106, 'label': 2162, 'op': 'jmp_and_link'}
instructions[3170] = {6'd3, 8'd140, 8'd107, 32'd0};//{'dest': 140, 'src': 107, 'op': 'move'}
instructions[3171] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3172] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3173] = {6'd3, 8'd135, 8'd140, 32'd0};//{'dest': 135, 'src': 140, 'op': 'move'}
instructions[3174] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3175] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3176] = {6'd3, 8'd140, 8'd135, 32'd0};//{'dest': 140, 'src': 135, 'op': 'move'}
instructions[3177] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3178] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3179] = {6'd13, 8'd0, 8'd140, 32'd3184};//{'src': 140, 'label': 3184, 'op': 'jmp_if_false'}
instructions[3180] = {6'd3, 8'd141, 8'd90, 32'd0};//{'dest': 141, 'src': 90, 'op': 'move'}
instructions[3181] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3183] = {6'd25, 8'd140, 8'd141, 32'd80};//{'src': 141, 'right': 80, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3184] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3185] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3186] = {6'd13, 8'd0, 8'd140, 32'd3543};//{'src': 140, 'label': 3543, 'op': 'jmp_if_false'}
instructions[3187] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3188] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3189] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3190] = {6'd26, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[3191] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3192] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3193] = {6'd13, 8'd0, 8'd140, 32'd3199};//{'src': 140, 'label': 3199, 'op': 'jmp_if_false'}
instructions[3194] = {6'd3, 8'd141, 8'd89, 32'd0};//{'dest': 141, 'src': 89, 'op': 'move'}
instructions[3195] = {6'd3, 8'd142, 8'd78, 32'd0};//{'dest': 142, 'src': 78, 'op': 'move'}
instructions[3196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3198] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[3199] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3200] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3201] = {6'd13, 8'd0, 8'd140, 32'd3204};//{'src': 140, 'label': 3204, 'op': 'jmp_if_false'}
instructions[3202] = {6'd15, 8'd0, 8'd0, 32'd3547};//{'label': 3547, 'op': 'goto'}
instructions[3203] = {6'd15, 8'd0, 8'd0, 32'd3204};//{'label': 3204, 'op': 'goto'}
instructions[3204] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3205] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3206] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3207] = {6'd3, 8'd138, 8'd140, 32'd0};//{'dest': 138, 'src': 140, 'op': 'move'}
instructions[3208] = {6'd3, 8'd140, 8'd139, 32'd0};//{'dest': 140, 'src': 139, 'op': 'move'}
instructions[3209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3210] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3211] = {6'd3, 8'd137, 8'd140, 32'd0};//{'dest': 137, 'src': 140, 'op': 'move'}
instructions[3212] = {6'd3, 8'd140, 8'd139, 32'd0};//{'dest': 140, 'src': 139, 'op': 'move'}
instructions[3213] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3214] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3215] = {6'd39, 8'd141, 8'd140, 32'd0};//{'src': 140, 'right': 0, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3216] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3217] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3218] = {6'd22, 8'd0, 8'd141, 32'd3235};//{'src': 141, 'label': 3235, 'op': 'jmp_if_true'}
instructions[3219] = {6'd39, 8'd141, 8'd140, 32'd1};//{'src': 140, 'right': 1, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3220] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3222] = {6'd22, 8'd0, 8'd141, 32'd3258};//{'src': 141, 'label': 3258, 'op': 'jmp_if_true'}
instructions[3223] = {6'd39, 8'd141, 8'd140, 32'd2};//{'src': 140, 'right': 2, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3224] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3225] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3226] = {6'd22, 8'd0, 8'd141, 32'd3336};//{'src': 141, 'label': 3336, 'op': 'jmp_if_true'}
instructions[3227] = {6'd39, 8'd141, 8'd140, 32'd3};//{'src': 140, 'right': 3, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3228] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3230] = {6'd22, 8'd0, 8'd141, 32'd3372};//{'src': 141, 'label': 3372, 'op': 'jmp_if_true'}
instructions[3231] = {6'd39, 8'd141, 8'd140, 32'd4};//{'src': 140, 'right': 4, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3232] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3233] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3234] = {6'd22, 8'd0, 8'd141, 32'd3460};//{'src': 141, 'label': 3460, 'op': 'jmp_if_true'}
instructions[3235] = {6'd3, 8'd140, 8'd94, 32'd0};//{'dest': 140, 'src': 94, 'op': 'move'}
instructions[3236] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3237] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3238] = {6'd13, 8'd0, 8'd140, 32'd3244};//{'src': 140, 'label': 3244, 'op': 'jmp_if_false'}
instructions[3239] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3240] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3241] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3242] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3243] = {6'd15, 8'd0, 8'd0, 32'd3257};//{'label': 3257, 'op': 'goto'}
instructions[3244] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3245] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3246] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3247] = {6'd3, 8'd85, 8'd140, 32'd0};//{'dest': 85, 'src': 140, 'op': 'move'}
instructions[3248] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3249] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3250] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3251] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3252] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3253] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3255] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3256] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3257] = {6'd15, 8'd0, 8'd0, 32'd3470};//{'label': 3470, 'op': 'goto'}
instructions[3258] = {6'd3, 8'd140, 8'd96, 32'd0};//{'dest': 140, 'src': 96, 'op': 'move'}
instructions[3259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3260] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3261] = {6'd13, 8'd0, 8'd140, 32'd3335};//{'src': 140, 'label': 3335, 'op': 'jmp_if_false'}
instructions[3262] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3263] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3264] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3265] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3266] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3268] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515027733680, 'op': 'memory_read_request'}
instructions[3269] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3270] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515027733680, 'op': 'memory_read_wait'}
instructions[3271] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515027733680, 'element_size': 2, 'op': 'memory_read'}
instructions[3272] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3273] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3274] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3275] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[3276] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3277] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3278] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3279] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3280] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3282] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3283] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3284] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3285] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515027734112, 'op': 'memory_read_request'}
instructions[3286] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3287] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515027734112, 'op': 'memory_read_wait'}
instructions[3288] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515027734112, 'element_size': 2, 'op': 'memory_read'}
instructions[3289] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3291] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3292] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[3293] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3295] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3296] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3297] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3298] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3299] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3301] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3302] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028852816, 'op': 'memory_read_request'}
instructions[3303] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3304] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028852816, 'op': 'memory_read_wait'}
instructions[3305] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028852816, 'element_size': 2, 'op': 'memory_read'}
instructions[3306] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3307] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3308] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3309] = {6'd11, 8'd142, 8'd141, 32'd80};//{'dest': 142, 'src': 141, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3311] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3312] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3313] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3314] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3315] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3316] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3317] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3318] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3319] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028853248, 'op': 'memory_read_request'}
instructions[3320] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3321] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515028853248, 'op': 'memory_read_wait'}
instructions[3322] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 140515028853248, 'element_size': 2, 'op': 'memory_read'}
instructions[3323] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3324] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3325] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3326] = {6'd11, 8'd142, 8'd141, 32'd80};//{'dest': 142, 'src': 141, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3327] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3328] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3329] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3330] = {6'd0, 8'd140, 8'd0, 32'd2};//{'dest': 140, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3331] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3332] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3333] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3334] = {6'd15, 8'd0, 8'd0, 32'd3335};//{'label': 3335, 'op': 'goto'}
instructions[3335] = {6'd15, 8'd0, 8'd0, 32'd3470};//{'label': 3470, 'op': 'goto'}
instructions[3336] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[3337] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3338] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3339] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3340] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[3341] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3342] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3343] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3344] = {6'd3, 8'd141, 8'd104, 32'd0};//{'dest': 141, 'src': 104, 'op': 'move'}
instructions[3345] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3346] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3347] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3348] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3349] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3350] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3351] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3352] = {6'd3, 8'd138, 8'd140, 32'd0};//{'dest': 138, 'src': 140, 'op': 'move'}
instructions[3353] = {6'd3, 8'd140, 8'd93, 32'd0};//{'dest': 140, 'src': 93, 'op': 'move'}
instructions[3354] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3355] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3356] = {6'd13, 8'd0, 8'd140, 32'd3362};//{'src': 140, 'label': 3362, 'op': 'jmp_if_false'}
instructions[3357] = {6'd0, 8'd140, 8'd0, 32'd4};//{'dest': 140, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3358] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3359] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3360] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3361] = {6'd15, 8'd0, 8'd0, 32'd3371};//{'label': 3371, 'op': 'goto'}
instructions[3362] = {6'd3, 8'd140, 8'd132, 32'd0};//{'dest': 140, 'src': 132, 'op': 'move'}
instructions[3363] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3364] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3365] = {6'd13, 8'd0, 8'd140, 32'd3371};//{'src': 140, 'label': 3371, 'op': 'jmp_if_false'}
instructions[3366] = {6'd0, 8'd140, 8'd0, 32'd3};//{'dest': 140, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3367] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3368] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3369] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3370] = {6'd15, 8'd0, 8'd0, 32'd3371};//{'label': 3371, 'op': 'goto'}
instructions[3371] = {6'd15, 8'd0, 8'd0, 32'd3470};//{'label': 3470, 'op': 'goto'}
instructions[3372] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[3373] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3374] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3375] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3376] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[3377] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3378] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3379] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3380] = {6'd3, 8'd141, 8'd104, 32'd0};//{'dest': 141, 'src': 104, 'op': 'move'}
instructions[3381] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3382] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3383] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3384] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3385] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3386] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3387] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3388] = {6'd3, 8'd138, 8'd140, 32'd0};//{'dest': 138, 'src': 140, 'op': 'move'}
instructions[3389] = {6'd3, 8'd140, 8'd93, 32'd0};//{'dest': 140, 'src': 93, 'op': 'move'}
instructions[3390] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3391] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3392] = {6'd13, 8'd0, 8'd140, 32'd3398};//{'src': 140, 'label': 3398, 'op': 'jmp_if_false'}
instructions[3393] = {6'd0, 8'd140, 8'd0, 32'd4};//{'dest': 140, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3394] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3395] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3396] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3397] = {6'd15, 8'd0, 8'd0, 32'd3459};//{'label': 3459, 'op': 'goto'}
instructions[3398] = {6'd3, 8'd140, 8'd96, 32'd0};//{'dest': 140, 'src': 96, 'op': 'move'}
instructions[3399] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3400] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3401] = {6'd13, 8'd0, 8'd140, 32'd3425};//{'src': 140, 'label': 3425, 'op': 'jmp_if_false'}
instructions[3402] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3403] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3404] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3405] = {6'd11, 8'd146, 8'd142, 32'd80};//{'dest': 146, 'src': 142, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3406] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3407] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3408] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515027763712, 'op': 'memory_read_request'}
instructions[3409] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3410] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515027763712, 'op': 'memory_read_wait'}
instructions[3411] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515027763712, 'element_size': 2, 'op': 'memory_read'}
instructions[3412] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3413] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3414] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3415] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3418] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515027763856, 'op': 'memory_read_request'}
instructions[3419] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3420] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515027763856, 'op': 'memory_read_wait'}
instructions[3421] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140515027763856, 'element_size': 2, 'op': 'memory_read'}
instructions[3422] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3423] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3424] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3425] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3426] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3427] = {6'd13, 8'd0, 8'd140, 32'd3451};//{'src': 140, 'label': 3451, 'op': 'jmp_if_false'}
instructions[3428] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3429] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3431] = {6'd11, 8'd146, 8'd142, 32'd80};//{'dest': 146, 'src': 142, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3432] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3433] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3434] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515027764144, 'op': 'memory_read_request'}
instructions[3435] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3436] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 140515027764144, 'op': 'memory_read_wait'}
instructions[3437] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 140515027764144, 'element_size': 2, 'op': 'memory_read'}
instructions[3438] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3439] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3440] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3441] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3442] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3443] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3444] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515027764288, 'op': 'memory_read_request'}
instructions[3445] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3446] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140515027764288, 'op': 'memory_read_wait'}
instructions[3447] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140515027764288, 'element_size': 2, 'op': 'memory_read'}
instructions[3448] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3449] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3450] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3451] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3452] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3453] = {6'd13, 8'd0, 8'd140, 32'd3459};//{'src': 140, 'label': 3459, 'op': 'jmp_if_false'}
instructions[3454] = {6'd0, 8'd140, 8'd0, 32'd2};//{'dest': 140, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3456] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3457] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3458] = {6'd15, 8'd0, 8'd0, 32'd3459};//{'label': 3459, 'op': 'goto'}
instructions[3459] = {6'd15, 8'd0, 8'd0, 32'd3470};//{'label': 3470, 'op': 'goto'}
instructions[3460] = {6'd3, 8'd140, 8'd96, 32'd0};//{'dest': 140, 'src': 96, 'op': 'move'}
instructions[3461] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3462] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3463] = {6'd13, 8'd0, 8'd140, 32'd3469};//{'src': 140, 'label': 3469, 'op': 'jmp_if_false'}
instructions[3464] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3465] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3466] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3467] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3468] = {6'd15, 8'd0, 8'd0, 32'd3469};//{'label': 3469, 'op': 'goto'}
instructions[3469] = {6'd15, 8'd0, 8'd0, 32'd3470};//{'label': 3470, 'op': 'goto'}
instructions[3470] = {6'd3, 8'd140, 8'd95, 32'd0};//{'dest': 140, 'src': 95, 'op': 'move'}
instructions[3471] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3472] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3473] = {6'd13, 8'd0, 8'd140, 32'd3479};//{'src': 140, 'label': 3479, 'op': 'jmp_if_false'}
instructions[3474] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3475] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3477] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3478] = {6'd15, 8'd0, 8'd0, 32'd3479};//{'label': 3479, 'op': 'goto'}
instructions[3479] = {6'd3, 8'd140, 8'd138, 32'd0};//{'dest': 140, 'src': 138, 'op': 'move'}
instructions[3480] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3481] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3482] = {6'd13, 8'd0, 8'd140, 32'd3515};//{'src': 140, 'label': 3515, 'op': 'jmp_if_false'}
instructions[3483] = {6'd3, 8'd151, 8'd129, 32'd0};//{'dest': 151, 'src': 129, 'op': 'move'}
instructions[3484] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3485] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3486] = {6'd3, 8'd116, 8'd151, 32'd0};//{'dest': 116, 'src': 151, 'op': 'move'}
instructions[3487] = {6'd3, 8'd141, 8'd105, 32'd0};//{'dest': 141, 'src': 105, 'op': 'move'}
instructions[3488] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3489] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3490] = {6'd3, 8'd117, 8'd141, 32'd0};//{'dest': 117, 'src': 141, 'op': 'move'}
instructions[3491] = {6'd3, 8'd141, 8'd104, 32'd0};//{'dest': 141, 'src': 104, 'op': 'move'}
instructions[3492] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3493] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3494] = {6'd3, 8'd118, 8'd141, 32'd0};//{'dest': 118, 'src': 141, 'op': 'move'}
instructions[3495] = {6'd1, 8'd115, 8'd0, 32'd2514};//{'dest': 115, 'label': 2514, 'op': 'jmp_and_link'}
instructions[3496] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3497] = {6'd3, 8'd142, 8'd137, 32'd0};//{'dest': 142, 'src': 137, 'op': 'move'}
instructions[3498] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3499] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3500] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3501] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3502] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3503] = {6'd13, 8'd0, 8'd140, 32'd3514};//{'src': 140, 'label': 3514, 'op': 'jmp_if_false'}
instructions[3504] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3505] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3506] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3507] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3508] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[3509] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3510] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3511] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3512] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3513] = {6'd15, 8'd0, 8'd0, 32'd3514};//{'label': 3514, 'op': 'goto'}
instructions[3514] = {6'd15, 8'd0, 8'd0, 32'd3515};//{'label': 3515, 'op': 'goto'}
instructions[3515] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3516] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3517] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3518] = {6'd25, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3519] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3520] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3521] = {6'd13, 8'd0, 8'd140, 32'd3523};//{'src': 140, 'label': 3523, 'op': 'jmp_if_false'}
instructions[3522] = {6'd38, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'socket', 'op': 'ready'}
instructions[3523] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3524] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3525] = {6'd13, 8'd0, 8'd140, 32'd3528};//{'src': 140, 'label': 3528, 'op': 'jmp_if_false'}
instructions[3526] = {6'd15, 8'd0, 8'd0, 32'd3550};//{'label': 3550, 'op': 'goto'}
instructions[3527] = {6'd15, 8'd0, 8'd0, 32'd3528};//{'label': 3528, 'op': 'goto'}
instructions[3528] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3529] = {6'd3, 8'd142, 8'd137, 32'd0};//{'dest': 142, 'src': 137, 'op': 'move'}
instructions[3530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3531] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3532] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[3533] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3534] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3535] = {6'd13, 8'd0, 8'd140, 32'd3542};//{'src': 140, 'label': 3542, 'op': 'jmp_if_false'}
instructions[3536] = {6'd0, 8'd140, 8'd0, 32'd120};//{'dest': 140, 'literal': 120, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3537] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3538] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3539] = {6'd3, 8'd133, 8'd140, 32'd0};//{'dest': 133, 'src': 140, 'op': 'move'}
instructions[3540] = {6'd15, 8'd0, 8'd0, 32'd3550};//{'label': 3550, 'op': 'goto'}
instructions[3541] = {6'd15, 8'd0, 8'd0, 32'd3542};//{'label': 3542, 'op': 'goto'}
instructions[3542] = {6'd15, 8'd0, 8'd0, 32'd3547};//{'label': 3547, 'op': 'goto'}
instructions[3543] = {6'd0, 8'd140, 8'd0, 32'd10000};//{'dest': 140, 'literal': 10000, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3544] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3545] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3546] = {6'd41, 8'd0, 8'd140, 32'd0};//{'src': 140, 'op': 'wait_clocks'}
instructions[3547] = {6'd3, 8'd140, 8'd134, 32'd0};//{'dest': 140, 'src': 134, 'op': 'move'}
instructions[3548] = {6'd35, 8'd134, 8'd134, 32'd1};//{'src': 134, 'right': 1, 'dest': 134, 'signed': False, 'op': '-', 'size': 2}
instructions[3549] = {6'd15, 8'd0, 8'd0, 32'd3159};//{'label': 3159, 'op': 'goto'}
instructions[3550] = {6'd15, 8'd0, 8'd0, 32'd2654};//{'label': 2654, 'op': 'goto'}
instructions[3551] = {6'd6, 8'd0, 8'd128, 32'd0};//{'src': 128, 'op': 'jmp_to_reg'}
end
//////////////////////////////////////////////////////////////////////////////
// CPU IMPLEMENTAION OF C PROCESS
//
// This section of the file contains a CPU implementing the C process.
always @(posedge clk)
begin
//implement memory for 2 byte x n arrays
if (memory_enable_2 == 1'b1) begin
memory_2[address_2] <= data_in_2;
end
data_out_2 <= memory_2[address_2];
memory_enable_2 <= 1'b0;
write_enable_2 <= 0;
//stage 0 instruction fetch
if (stage_0_enable) begin
stage_1_enable <= 1;
instruction_0 <= instructions[program_counter];
opcode_0 = instruction_0[53:48];
dest_0 = instruction_0[47:40];
src_0 = instruction_0[39:32];
srcb_0 = instruction_0[7:0];
literal_0 = instruction_0[31:0];
if(write_enable_2) begin
registers[dest_2] <= result_2;
end
program_counter_0 <= program_counter;
program_counter <= program_counter + 1;
end
//stage 1 opcode fetch
if (stage_1_enable) begin
stage_2_enable <= 1;
register_1 <= registers[src_0];
registerb_1 <= registers[srcb_0];
dest_1 <= dest_0;
literal_1 <= literal_0;
opcode_1 <= opcode_0;
program_counter_1 <= program_counter_0;
end
//stage 2 opcode fetch
if (stage_2_enable) begin
dest_2 <= dest_1;
case(opcode_1)
16'd0:
begin
result_2 <= literal_1;
write_enable_2 <= 1;
end
16'd1:
begin
program_counter <= literal_1;
result_2 <= program_counter_1 + 1;
write_enable_2 <= 1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd2:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd3:
begin
result_2 <= register_1;
write_enable_2 <= 1;
end
16'd5:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_eth_tx_stb <= 1'b1;
s_output_eth_tx <= register_1;
end
16'd6:
begin
program_counter <= register_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd7:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_socket_stb <= 1'b1;
s_output_socket <= register_1;
end
16'd8:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_eth_rx_ack <= 1'b1;
end
16'd9:
begin
result_2 <= 0;
result_2[0] <= input_eth_rx_stb;
write_enable_2 <= 1;
end
16'd10:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_socket_ack <= 1'b1;
end
16'd11:
begin
result_2 <= $unsigned(register_1) + $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd12:
begin
result_2 <= $unsigned(register_1) & $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd13:
begin
if (register_1 == 0) begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
end
16'd14:
begin
result_2 <= $unsigned(register_1) + $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd15:
begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd16:
begin
result_2 <= ~register_1;
write_enable_2 <= 1;
end
16'd17:
begin
address_2 <= register_1;
end
16'd19:
begin
result_2 <= data_out_2;
write_enable_2 <= 1;
end
16'd20:
begin
result_2 <= $unsigned(register_1) < $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd21:
begin
result_2 <= $unsigned(register_1) != $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd22:
begin
if (register_1 != 0) begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
end
16'd23:
begin
address_2 <= register_1;
data_in_2 <= registerb_1;
memory_enable_2 <= 1'b1;
end
16'd24:
begin
$display ("%d (report at line: 107 in file: /home/amer/Nexys3/TCP3/source/server.h)", $unsigned(register_1));
end
16'd25:
begin
result_2 <= $unsigned(register_1) == $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd26:
begin
result_2 <= $unsigned(register_1) != $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd27:
begin
result_2 <= $signed(register_1) + $signed(registerb_1);
write_enable_2 <= 1;
end
16'd28:
begin
result_2 <= $unsigned(register_1) < $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd29:
begin
result_2 <= $unsigned(register_1) == $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd30:
begin
result_2 <= $unsigned(literal_1) | $unsigned(register_1);
write_enable_2 <= 1;
end
16'd31:
begin
result_2 <= $unsigned(register_1) <= $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd32:
begin
result_2 <= $unsigned(register_1) >> $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd33:
begin
result_2 <= $unsigned(register_1) << $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd34:
begin
result_2 <= $unsigned(register_1) - $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd35:
begin
result_2 <= $unsigned(register_1) - $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd36:
begin
result_2 <= $unsigned(register_1) <= $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd37:
begin
result_2 <= $unsigned(register_1) | $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd38:
begin
result_2 <= 0;
result_2[0] <= input_socket_stb;
write_enable_2 <= 1;
end
16'd39:
begin
result_2 <= $signed(register_1) == $signed(literal_1);
write_enable_2 <= 1;
end
16'd40:
begin
$display ("%d (report at line: 542 in file: /home/amer/Nexys3/TCP3/source/server.h)", $signed(register_1));
end
16'd41:
begin
timer <= register_1;
timer_enable <= 1;
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
endcase
end
if (s_output_eth_tx_stb == 1'b1 && output_eth_tx_ack == 1'b1) begin
s_output_eth_tx_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_output_socket_stb == 1'b1 && output_socket_ack == 1'b1) begin
s_output_socket_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_eth_rx_ack == 1'b1 && input_eth_rx_stb == 1'b1) begin
result_2 <= input_eth_rx;
write_enable_2 <= 1;
s_input_eth_rx_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_socket_ack == 1'b1 && input_socket_stb == 1'b1) begin
result_2 <= input_socket;
write_enable_2 <= 1;
s_input_socket_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (timer == 0) begin
if (timer_enable) begin
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
timer_enable <= 0;
end
end else begin
timer <= timer - 1;
end
if (rst == 1'b1) begin
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
timer <= 0;
timer_enable <= 0;
program_counter <= 0;
s_input_eth_rx_ack <= 0;
s_input_socket_ack <= 0;
s_output_socket_stb <= 0;
s_output_eth_tx_stb <= 0;
end
end
assign input_eth_rx_ack = s_input_eth_rx_ack;
assign input_socket_ack = s_input_socket_ack;
assign output_socket_stb = s_output_socket_stb;
assign output_socket = s_output_socket;
assign output_eth_tx_stb = s_output_eth_tx_stb;
assign output_eth_tx = s_output_eth_tx;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTP_1_V
`define SKY130_FD_SC_HD__DLXTP_1_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog wrapper for dlxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlxtp_1 (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlxtp_1 (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111AI_BLACKBOX_V
`define SKY130_FD_SC_LS__O2111AI_BLACKBOX_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2111ai (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111AI_BLACKBOX_V
|
module uc(input wire clock,reset,z, input wire [1:0] id_out, input wire [5:0] opcode,
output reg s_inc, s_inm, we3, rwe1, rwe2, rwe3, rwe4, sec, sece, s_es, s_rel, swe, s_ret, output wire [2:0] op);
assign op = opcode[2:0];
always @(*)
begin
rwe1 <= 1'b0; //Desactivar puertos de E/S
rwe2 <= 1'b0; //Desactivar puertos de E/S
rwe3 <= 1'b0; //Desactivar puertos de E/S
rwe4 <= 1'b0; //Desactivar puertos de E/S
swe <= 1'b0; //desactivar registro especial(subrutina)
s_ret <= 1'b0; //no tomar valor de retorno
sece <= 1'b0; //Desactivar Salida de E/S
if (reset == 1'b1)
begin
we3 <= 1'b0; //No escribir en el banco de registros
s_inm <= 1'b0; //Da igual el valor, no se trabaja con registros
s_inc <= 1'b1; //Para que el PC coja la siguiente instrucción
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //Despreciar salto relativo
swe <= 1'b0; //desactivar registro especial(subrutina)
s_ret <= 1'b0; //no tomar valor de retorno
end
else
begin
casex (opcode)
// Instrucciones ariméticas (4ºbit a 0)
6'bxx0xxx:
begin
//op <= opcode[2:0]; //Código de operación de ALU
we3 <= 1'b1; //Permitir escritura en registros
s_inm <= 1'b0; //Escoger resultado de la ALU
s_inc <= 1'b1; //Escoger siguiente instrucción
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //Despreciar salto relativo
end
// Instrucción: Carga Inmediata
6'bxx1010:
begin
we3 <= 1'b1; //Permitir escritura en registros
s_inm <= 1'b1; //La ALU no nos interesa
s_inc <= 1'b1; //Escoger siguiente instrucción
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //Despreciar salto relativo
end
// Instrucción: Salto Incondicional
6'bxx1001:
begin
we3 <= 1'b0; //No trabaja con registros
s_inm <= 1'b0; //Da igual el valor porque no se trabaja con registros
s_inc <= 1'b0; //Escoger el salto indicado
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //Despreciar salto relativo
end
// Instrucción: LES cargar desde E/S
6'bxx1011:
begin
we3 <= 1'b1; //Permitir escritura en registros
s_inm <= 1'b0; //Da igual el valor porque no se trabaja con registro
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b1; //Activar entrada desde E/S
s_inc <= 1'b1; //Siguiente instrucción
s_rel <= 1'b0; //Despreciar salto relativo
end
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Instrucción: PRINT muestra por pantalla un registro
// 6'bxx1100:
// begin
// // we3 <= 1'b0; // No trabaja con registros
// // s_inm <= 1'b0; // Da igual el valor porque no se trabaja con registro
// // sec <= 1'b1; // Se envia a la E/S desde un registro
// // s_es <= 1'b0; //Desactivar entrada desde E/S
// // s_inc <= 1'b1; //Siguiente instrucción
// // s_rel <= 1'b0; //Despreciar salto relativo
// // rwe1 <= 1'b1;
// // rwe2 <= 1'b1;
// // rwe3 <= 1'b1;
// // rwe4 <= 1'b1;
// end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Instrucción: Envia a la E/S desde el registro
6'bxx1101:
begin
we3 <= 1'b0; //No trabaja con registros
s_inm <= 1'b0; //Da igual el valor porque no se trabaja con registros
sec <= 1'b1; //A 1 = Registro
sece <= 1'b1; //Activar Salida de E/S
s_es <= 1'b0; //Desctivar entrada desde E/S
s_inc <= 1'b1; //Siguiente instrucción
s_rel <= 1'b0; //Despreciar salto relativo
if (id_out == 2'b00)
rwe1 <= 1'b1;
else if(id_out == 2'b01)
rwe2 <= 1'b1;
else if(id_out == 2'b10)
rwe3 <= 1'b1;
else
rwe4 <= 1'b1;
end
// Instrucción: Envia a la E/S desde la memoria
6'bxx1110:
begin
we3 <= 1'b0; //No trabaja con registros
s_inm <= 1'b0; //Da igual el valor porque no se trabaja con registros
sec <= 1'b0; //A 0 = Memoria
sece <= 1'b1; //Activar Salida de E/S
s_es <= 1'b0; //Desctivar entrada desde E/S
s_inc <= 1'b1; //Siguiente instrucción
s_rel <= 1'b0; //Despreciar salto relativo
if (id_out == 2'b00)
rwe1 <= 1'b1;
else if(id_out == 2'b01)
rwe2 <= 1'b1;
else if(id_out == 2'b10)
rwe3 <= 1'b1;
else
rwe4 <= 1'b1;
end
// Instrucción: Salto Condicional (si z=0)
6'b011111:
begin
we3 <= 1'b0; //No trabaja con registros
s_inm <= 1'b0; //Da igual el valor porque no se trabaja con registros
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //Despreciar salto relativo
if (z == 1'b0)
s_inc <= 1'b0; //Saltar
else
s_inc <= 1'b1; //Siguiente instrucćión
end
// Instrucción: Salto Condicional (si z=1)
6'b001111:
begin
we3 <= 1'b0; //No trabaja con registros
s_inm <= 1'b0; //Da igual el valor porque no se trabaja con registros
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //Despreciar salto relativo
if (z == 1'b0)
s_inc <= 1'b1; //Siguiente instrucción
else
s_inc <= 1'b0; //Saltar
end
//Instrucción: Salto relativo
6'b011000:
begin
we3 <= 1'b0; //Denegar escritura en registros
s_inm <= 1'b0; //La ALU no nos interesa
s_inc <= 1'b1; //Escoger el salto relativo
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b1; //Escoger salto relativo
end
//Instrucción: Salto a subrutina
6'b101000:
begin
we3 <= 1'b0; //Denegar escritura en registros
s_inm <= 1'b0; //La ALU no nos interesa
s_inc <= 1'b0; //Escoger siguiente instrucción
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //Escoger siguiente instrucción
swe <= 1'b1; //activar registro especial(subrutina)
end
//Instrucción: Retorno subrutina
6'b111000:
begin
we3 <= 1'b0; //denegar escritura en registros
s_inm <= 1'b0; //La ALU no nos interesa
s_inc <= 1'b0; //da igual
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //Da igual
s_ret <= 1'b1; //Tomar el valor de retorno
end
//Instrucción: NOP
6'b111111:
begin
we3 <= 1'b0; //Denegar escritura en registros
s_inm <= 1'b0; //La ALU no nos interesa
s_inc <= 1'b1; //Escoger siguiente instrucción
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //No activar salto relativo
s_ret <= 1'b0; //No tomar el valor de retorno
end
default:
begin
we3 <= 1'b0; //Denegar escritura en registros
s_inm <= 1'b0; //La ALU no nos interesa
s_inc <= 1'b1; //Escoger siguiente instrucción
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //No activar salto relativo
s_ret <= 1'b0; //No tomar el valor de retorno
end
endcase
end
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__SEDFXTP_FUNCTIONAL_PP_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_pg/sky130_fd_sc_hs__u_df_p_pg.v"
`celldefine
module sky130_fd_sc_hs__sedfxtp (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_hs__u_mux_2_1 u_mux_21 (de_d , buf_Q, D, DE );
sky130_fd_sc_hs__u_df_p_pg `UNIT_DELAY u_df_p_pg0 (buf_Q , mux_out, CLK, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXTP_FUNCTIONAL_PP_V |
/* ****************************************************************************
-- (C) Copyright 2018 Kevin M. Hubbard - All rights reserved.
-- Source file: deep_sump_hyperram.v
-- Date: July 2018
-- Author: khubbard
-- Description: Deep Sump extension to sump2.v logic analyzer. This uses a FIFO
-- and a slow deep memory ( either internal or external ) for
-- extending event capture window in a parallel storage path.
-- Language: Verilog-2001
-- Simulation: Mentor-Modelsim
-- Synthesis: Xilint-XST,Xilinx-Vivado,Lattice-Synplify
-- License: This project is licensed with the CERN Open Hardware Licence
-- v1.2. You may redistribute and modify this project under the
-- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).
-- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED
-- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL
-- v.1.2 for applicable Conditions.
--
-- Revision History:
-- Ver# When Who What
-- ---- -------- -------- --------------------------------------------------
-- 0.1 04.29.18 khubbard Creation
-- ***************************************************************************/
`default_nettype none // Strictly enforce all nets to be declared
// Note: The RAM depth len+bits is for 64bits.
// Take total number of bits and divide by 64 to get depth_len
module deep_sump_hyperram #
(
parameter depth_len = 65536,
parameter depth_bits = 16
)
(
input wire reset,
input wire a_clk,
input wire b_clk,
input wire a_we,
input wire [depth_bits-1:0] a_addr,
input wire [63:0] a_di,
output reg a_overrun,
input wire b_rd_req,
input wire [depth_bits-1:0] b_addr,
output reg [63:0] b_do,
input wire [7:0] dram_dq_in,
output wire [7:0] dram_dq_out,
output wire dram_dq_oe_l,
input wire dram_rwds_in,
output wire dram_rwds_out,
output wire dram_rwds_oe_l,
output wire dram_ck,
output wire dram_rst_l,
output wire dram_cs_l,
output wire [7:0] sump_dbg
);
reg [107:0] fifo_din;
reg fifo_wr_en;
reg fifo_rd_en;
wire [107:0] fifo_dout;
reg [107:0] fifo_dout_q;
wire fifo_full;
wire fifo_almost_full;
wire fifo_overflow;
wire fifo_empty;
wire fifo_almost_empty;
wire fifo_valid;
reg fifo_valid_p1;
reg fifo_valid_p2;
reg hr_rd_req;
reg hr_wr_req;
reg hr_mem_or_reg;
reg [3:0] hr_wr_byte_en;
reg [31:0] hr_addr;
reg [5:0] hr_rd_num_dwords;
reg [31:0] hr_wr_d;
wire [31:0] hr_rd_d;
reg [63:0] hr_rd_d_sr;
wire hr_rd_rdy;
wire hr_busy;
wire hr_burst_wr_rdy;
reg [7:0] hr_latency_1x;
reg [7:0] hr_latency_2x;
reg [7:0] hr_wr_sr;
reg cfg_done_jk;
reg dword_two_jk;
reg [15:0] fifo_rd_en_sr;
wire lat_2x;
//-----------------------------------------------------------------------------
// Deep Sump pushes write address+data to a FIFO.
//-----------------------------------------------------------------------------
always @( posedge a_clk )
begin
fifo_din <= 108'd0;
fifo_din[depth_bits-1+64:64] <= a_addr[depth_bits-1:0];
fifo_din[63:0] <= a_di[63:0];
fifo_wr_en <= a_we;
a_overrun <= fifo_full | fifo_almost_full;// mark capture as invalid
if ( fifo_almost_full == 1 || fifo_full == 1 ) begin
fifo_wr_en <= 0;
end
end // always
//-----------------------------------------------------------------------------
// Instead of waiting 150uS from Power On to configure the HyperRAM, wait
// until the 1st time FIFO goes not-empty from Reset and then issue the cfg.
// Default 6 Clock 166 MHz Latency, latency1x=0x12, latency2x=0x16
// CfgReg0 write(0x00000800, 0x8f1f0000);
// Configd 3 Clock 83 MHz Latency, latency1x=0x04, latency2x=0x0a
// CfgReg0 write(0x00000800, 0x8fe40000);
//
// The FIFO with Deep Sump writes gets popped whenever HyperRAM is available.
// Deep Sump read requests are multi cycle. They come in on the b_clk domain
//-----------------------------------------------------------------------------
always @( posedge b_clk )
begin
hr_wr_sr <= { hr_wr_sr[6:0], hr_wr_req };
hr_latency_1x <= 8'h04;
hr_latency_2x <= 8'h0a;
hr_rd_num_dwords <= 6'd2;
hr_wr_byte_en <= 4'hF;
hr_rd_req <= 0;
hr_wr_req <= 0;
hr_mem_or_reg <= 0;
fifo_rd_en <= 0;
fifo_rd_en_sr <= { fifo_rd_en_sr[14:0], fifo_rd_en };
fifo_valid_p1 <= fifo_valid;
fifo_valid_p2 <= fifo_valid_p1;
b_do <= hr_rd_d_sr[63:0];
if ( hr_busy == 0 && hr_wr_sr == 8'd0 ) begin
if ( cfg_done_jk == 1 && b_rd_req == 1 ) begin
hr_addr <= 32'd0;
hr_addr[depth_bits-1+1:0] <= {b_addr[depth_bits-1:0],1'b0};// Note 64->32
hr_rd_req <= 1;
end
end
if ( hr_rd_rdy == 1 ) begin
hr_rd_d_sr <= { hr_rd_d_sr[31:0], hr_rd_d[31:0] };
end
// Configure HyperRAM optimal latency on 1st FIFO push after powerup
if ( cfg_done_jk == 0 && fifo_empty == 0 ) begin
cfg_done_jk <= 1;
hr_addr <= 32'h00000800;
hr_wr_d <= 32'h8fe40000;
hr_mem_or_reg <= 1;// Config Reg Write instead of DRAM Write
hr_wr_req <= 1;
end
// When FIFO has data, pop 32bits of Address and 64bits of Data and then
// Push those 2 DWORDs of Data to HyperRAM as a burst.
if ( hr_busy == 0 && hr_wr_sr == 8'd0 &&
fifo_rd_en_sr == 16'd0 && fifo_rd_en == 0 ) begin
if ( cfg_done_jk == 1 && fifo_empty == 0 ) begin
fifo_rd_en <= 1;// Pop Addr+Data off of FIFO for a HyperRAM Write
end
end
if ( fifo_valid == 1 && fifo_valid_p1 == 0 ) begin
fifo_dout_q <= fifo_dout[107:0];
end
// 1st DWORD is sent to DRAM as soon as FIFO pops it
if ( fifo_valid_p1 == 1 && fifo_valid_p2 == 0 ) begin
hr_addr <= { fifo_dout_q[94:64], 1'b0 };// Burst Address. Note 64->32
hr_wr_d <= fifo_dout_q[63:32];// Burst Data DWORD-1
dword_two_jk <= 1;// Queue up for the 2nd DWORD
hr_wr_req <= 1;
end
// 2nd DWORD is the burst. It just waits for hr_burst_wr_rdy
if ( dword_two_jk == 1 && hr_burst_wr_rdy == 1 ) begin
hr_addr <= { fifo_dout_q[94:64],1'b0};// Don't Care, just saves gates
hr_wr_d <= fifo_dout_q[31:0]; // Burst Data DWORD-2
dword_two_jk <= 0;
hr_wr_req <= 1;
end
if ( reset == 1 ) begin
cfg_done_jk <= 0;
dword_two_jk <= 0;
end
end // always
//-----------------------------------------------------------------------------
// Rate converting FIFO for HyperRAM DRAM access.
//
// Push Side
// wr_clk _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_
// wr_en _____/ \___
// din -----< >---
// almost_full
// overflow
//
// Pop Side
// rd_clk _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_
// rd_en _____________________/ \__________
// valid _____________________________/ \__
// dout -----------------------------< >--
// empty
// almost_empty
//-----------------------------------------------------------------------------
fifo_xilinx_512x108 u_fifo_xilinx_512x108
(
.rst ( reset ),
.wr_clk ( a_clk ),
.rd_clk ( b_clk ),
.din ( fifo_din[107:0] ),
.wr_en ( fifo_wr_en ),
.rd_en ( fifo_rd_en ),
.dout ( fifo_dout[107:0] ),
.full ( fifo_full ),
.almost_full ( fifo_almost_full ),
.overflow ( fifo_overflow ),
.empty ( fifo_empty ),
.almost_empty ( fifo_almost_empty ),
.valid ( fifo_valid )
);
assign sump_dbg[0] = fifo_wr_en;
assign sump_dbg[1] = fifo_rd_en;
//assign sump_dbg[2] = fifo_full;
//assign sump_dbg[2] = fifo_almost_full;
assign sump_dbg[2] = dram_rwds_in;
assign sump_dbg[3] = lat_2x;
assign sump_dbg[4] = hr_wr_req;
assign sump_dbg[5] = hr_rd_req;
assign sump_dbg[6] = hr_busy;
assign sump_dbg[7] = ~dram_cs_l;
//-----------------------------------------------------------------------------
// Bridge to a HyperRAM
//-----------------------------------------------------------------------------
hyper_xface u_hyper_xface
(
.reset ( reset ),
.clk ( b_clk ),
.rd_req ( hr_rd_req ),
.wr_req ( hr_wr_req ),
.mem_or_reg ( hr_mem_or_reg ),
.wr_byte_en ( hr_wr_byte_en ),
.addr ( hr_addr[31:0] ),
.rd_num_dwords ( hr_rd_num_dwords[5:0] ),
.wr_d ( hr_wr_d[31:0] ),
.rd_d ( hr_rd_d[31:0] ),
.rd_rdy ( hr_rd_rdy ),
.busy ( hr_busy ),
.lat_2x ( lat_2x ),
.burst_wr_rdy ( hr_burst_wr_rdy ),
.latency_1x ( hr_latency_1x[7:0] ),
.latency_2x ( hr_latency_2x[7:0] ),
.dram_dq_in ( dram_dq_in[7:0] ),
.dram_dq_out ( dram_dq_out[7:0] ),
.dram_dq_oe_l ( dram_dq_oe_l ),
.dram_rwds_in ( dram_rwds_in ),
.dram_rwds_out ( dram_rwds_out ),
.dram_rwds_oe_l ( dram_rwds_oe_l ),
.dram_ck ( dram_ck ),
.dram_rst_l ( dram_rst_l ),
.dram_cs_l ( dram_cs_l ),
.sump_dbg ( )
);// module hyper_xface
endmodule // deep_sump_hyperram
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/30 16:03:32
// Design Name:
// Module Name: uart_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module UART_top(clk,rst_n,tx_int,rx_int,RS232_rx,data_in,RS232_tx,data_out);
input clk,rst_n,RS232_rx;
input [7:0] data_in;
input tx_int; //½ÓÊÕÊý¾ÝÖжÏÐźÅ,½ÓÊÕ¹ý³ÌÖÐһֱΪ¸ß
output rx_int;
output RS232_tx;
output [7:0] data_out;
wire bps_start_rx,bps_start_tx;
wire clk_bps_rx,clk_bps_tx;
wire clk_rx,clk_tx;
wire [7:0] rx_data; //½ÓÊÕÊý¾Ý´æ´¢Æ÷,ÓÃÀ´´æ´¢½ÓÊÕµ½µÄÊý¾Ý,Ö±µ½ÏÂÒ»¸öÊý¾Ý½ÓÊÕ
//parameter BAUD_RATE = 9600;
clk_bluetooth ins_clk_bt(
// Clock out ports
.clk_txd(clk_tx),
.clk_rxd(clk_rx),
// Status and control signals
.resetn(rst_n),
// Clock in ports
.clk_in1(clk)
);
//////////////////////////////////×ÓÄ£¿é¶Ë¿ÚÉêÃ÷///////////////////////////////////
speed_select speed_rx( //Êý¾Ý½ÓÊÕ²¨ÌØÂÊÑ¡ÔñÄ£¿é
.clk(clk_rx),
.rst_n(rst_n),
.bps_start(bps_start_rx),
.clk_bps(clk_bps_rx)
);
UART_rx ins_UART_rx( //Êý¾Ý½ÓÊÕÄ£¿é
.clk(clk_rx),
.rst_n(rst_n),
.bps_start(bps_start_rx),
.clk_bps(clk_bps_rx),
.RS232_rx(RS232_rx),
.rx_data(rx_data),
.rx_int(rx_int),
.data_out(data_out)
);
speed_select speed_tx( //Êý¾Ý·¢ËͲ¨ÌØÂÊ¿ØÖÆÄ£¿é
.clk(clk_tx),
.rst_n(rst_n),
.bps_start(bps_start_tx),
.clk_bps(clk_bps_tx)
);
UART_tx ins_UART_tx(
.clk(clk),
.rst_n(rst_n),
.bps_start(bps_start_tx),
.clk_bps(clk_bps_tx),
.RS232_tx(RS232_tx),
.tx_data(data_in),
.tx_int(tx_int)
);
//wire flag_fifo_empty,flag_fifo_full;
//// Instantiate the Character FIFO - Core generator module
//fifo_bt_txd char_fifo_io (
// .din (fifo_din), // Bus [7:0]
// .rd_clk (clk_tx),
// .rd_en (fifo_rd_en),
// .rst (rst_n), // ASYNCHRONOUS reset - to both sides
// .wr_clk (clk),
// .wr_en (fifo_wr_en),
// .dout (fifo_dout), // Bus [7 : 0]
// .empty (flag_fifo_empty),
// .full (flag_fifo_full)
//);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Varun Kondagunturi
//
// Create Date: 17:08:26 06/12/2014
// Design Name:
// Module Name: Abacus_Top_Module
// Project Name:
// Target Devices:
// Tool versions:
//
//
// Description:
//This is the Top-Level Source file for the Abacus Project.
//Slide switches provide two 8-bit binary inputs A and B.
//Slide Switches [15 down to 8] is input A.
//Slide Switches [7 down to 0] is input B.
//Inputs from the Push Buttons ( btnU, btnD, btnR, btnL) will allow the user to select different arithmetic operations that will be computed on the inputs A and B.
//btnU: Subtraction/Difference. Result will Scroll
//When A>B, difference is positive.
//When A<B, difference is negative. If the button is not held down but just pressed once, the result will scroll. To find out if the result is negative, press and hold onto the push button btnU. This will show the negative sign.
//btnD: Multiplication/Product. Result will Scroll
//btnR: Quotient(Division Operation). Press and Hold the button to display result
//btnL: Remainder ( Division Operation). Press and Hold the button to display result
//Output is displayed on the 7 segment LED display.
//
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top(
//CLK Input
input clk,
//Push Button Inputs
input btnC,
input btnU,
input btnD,
input btnR,
input btnL,
// Slide Switch Inputs
// Input A = sw[15:8]
//Input B = sw[7:0]
input [15:0] sw,
// LED Outputs
output [15:0] led,
// Seven Segment Display Outputs
output [6:0] seg,
output [3:0] an,
output dp
);
//Seven Segment Display Signal
reg [15:0] x;//input to seg7 to define segment pattern
//adder signals
wire [7:0] sum;
wire [7:0] diff;
wire cout;
// 16 bit BCD Converter Signals
reg [15:0] B; // Inputs to B will be Adder/Subtractor and Multiplication Results
wire[19:0] bcdout;// bcdout is sent to Scroll_Display Module
// 16 bit BCD Converter Signals for Divider Sub-Module
reg [15:0] B1; // input will be 8 bit quotient signal
wire[19:0] bcdout1;// sent to Scroll_Display Module
reg [15:0] B2; // input will be 8 bit remainder signal
wire[19:0] bcdout2;// sent to Scroll_Display Module
// 7segment display scroll signals
wire [19:0] scroll_datain;
wire [15:0] scroll_dataout;
// Segment Scrolling for Divider result
wire [19:0] scroll_datain_QU;
wire [15:0] scroll_dataout_QU;
wire [19:0] scroll_datain_REM;
wire [15:0] scroll_dataout_REM;
// Divider or Mod signals
wire [7:0] QU;// Quotient
wire [7:0] REM; // Remainder
// Product or Multiplication Signals
wire [15:0] Product;
wire [7:0] PP0;// partial product outputs from multi modules.
wire [7:0] PP1;
wire [7:0] PP2;
wire [7:0] PP3;
wire [21:0] p_temp;
// Difference Signals
wire [7:0] zero_diff;
wire [7:0] twoC_diff;
// Clear Signal for Adder/Sub/Product
wire clr_seg;
assign clr_seg = btnU | btnD | btnC;// | btnR | btnL ;
// Clear Signal for Divider
wire clr_seg_DIV;//
assign clr_seg_DIV = btnR | btnL;
assign zero_diff[7:0] = diff[7:0]; //{1'b0, diff[7:0]};
assign twoC_diff[7:0] = ((~(zero_diff[7:0])) +8'b00000001);
assign p_temp[3:0] = PP0[3:0];
assign Product[3:0] = p_temp[3:0];
assign p_temp[9:4] = PP0[7:4]+PP1[3:0]+PP2[3:0]; //sum2_2[3:0]; 6 bits
assign Product[7:4] = p_temp[7:4];
assign p_temp[15:10] = PP1[7:4] + PP2[7:4] + PP3[3:0]+ {2'b00, p_temp[9:8]} ; //sumC_C[3:0]; // 6 bits
assign Product[11:8] = p_temp[13:10];
assign p_temp[21:16] = PP3[7:4] + {2'b00,p_temp[15:14]}; //P3[7:4]+ {3'b000, tempC_C[4]};
assign Product[15:12] = p_temp[19:16];
assign led[15:0] = sw[15:0];
always @(*) begin
if ( (btnU == 1) && (sw[15:8] <= sw[7:0]))
begin
B = twoC_diff[7:0];
x[15:12] = 'hA;
x[11:8] = scroll_dataout[11:8]; //hundreds;
x[7:4] = scroll_dataout[7:4];// tens;
x[3:0] = scroll_dataout[3:0];//ones;
end
else if ( (btnU == 1) && (sw[15:8] >= sw[7:0] ))
begin
B = diff[7:0];
x[15:12] = scroll_dataout[15:12];//'hC;
x[11:8] = scroll_dataout[11:8]; //hundreds;
x[7:4] = scroll_dataout[7:4];// tens;
x[3:0] = scroll_dataout[3:0];//ones;
end
else if (btnD == 1) begin
B = Product[15:0];
x[15:12] = scroll_dataout[15:12];//'hC
x[11:8] = scroll_dataout[11:8]; //hundreds;
x[7:4] = scroll_dataout[7:4];// tens;
x[3:0] = scroll_dataout[3:0];//ones;
end
else if (btnR == 1) begin
B1 = QU[7:0]; // bcdout1
x[15:12] = scroll_dataout_QU[15:12];//'hC;
x[11:8] = scroll_dataout_QU[11:8]; //hundreds;
x[7:4] = scroll_dataout_QU[7:4];// tens;
x[3:0] = scroll_dataout_QU[3:0];//ones;
end
else if (btnL == 1) begin
B2 = REM[7:0]; // bcdout2
x[15:12] = scroll_dataout_REM[15:12];//'hC;
x[11:8] = scroll_dataout_REM[11:8]; //hundreds;
x[7:4] = scroll_dataout_REM[7:4];// tens;
x[3:0] = scroll_dataout_REM[3:0];//ones;
end
else
begin
B = {cout, sum[7:0]};
x[15:12] = scroll_dataout[15:12];//'hC;
x[11:8] = scroll_dataout[11:8]; //hundreds;
x[7:4] = scroll_dataout[7:4];// tens;
x[3:0] = scroll_dataout[3:0];//ones;
end
end
// Binary to BCD conversion module1 for Adder/Sub/Multi Result
bin_to_decimal u1 (
.B(B),
.bcdout(bcdout)
);
// Binary to BCD conversion module2 for Quotient Result
BIN_DEC1 u2 (
.B1(B1), // QU in binary
.bcdout1(bcdout1)// QU in BCD
);
// Binary to BCD conversion module3 for Remainder Result
BIN_DEC2 u3 (
.B2(B2), // REM in binary
.bcdout2(bcdout2)// REM in BCD
);
// Scrolls Display
seg_scroll u4(
.clk(clk),
.clr(clr_seg),
.scroll_datain(bcdout),
.scroll_dataout(scroll_dataout)
);
//Using Seg_Scroll for Static Display of Quotient Result
Seg_Scroll_QU u5(
.clk(clk),
.clr(clr_seg_DIV),
.scroll_datain_QU(bcdout1),
.scroll_dataout_QU(scroll_dataout_QU)
);
//Using Seg_Scroll for Static Display of Remainder Result
Seg_Scroll_REM u6(
.clk(clk),
.clr(clr_seg_DIV),
.scroll_datain_REM(bcdout2),
.scroll_dataout_REM(scroll_dataout_REM)
);
// 7segment display module
seg7decimal u7 (
.x(x),
.clk(clk),
.clr(btnC),
.a_to_g(seg),
.an(an),
.dp(dp)
);
// Arithmetic Operations
// Adder/Subtractor Module
adder u8 (
.clk(clk),
.a(sw[15:8]),
.b(sw[7:0]),
.sum(sum),
.diff(diff),
.cout(cout),
.cin(btnU)
);
// Product/Multiplication
// Partial Product 0 Module
multi_4_4_pp0 u9 (
.clk(clk),
//.clr(btn[1]),
.A0_3(sw[11:8]),
.B0_3(sw[3:0]),
.pp0(PP0)
);
// Partial Product 1 Module
multi_4_4_pp1 u10 (
.clk(clk),
//.clr(btn[1]),
.A4_7(sw[15:12]),
.B0_3(sw[3:0]),
.pp1(PP1)
);
// Partial Product 2 Module
multi_4_4_pp2 u11 (
.clk(clk),
//.clr(btn[1]),
.A0_3(sw[11:8]),
.B4_7(sw[7:4]),
.pp2(PP2)
);
// Partial Product 3 Module
multi_4_4_pp3 u12 (
.clk(clk),
//.clr(btn[1]),
.A4_7(sw[15:12]),
.B4_7(sw[7:4]),
.pp3(PP3)
);
// Divider Module
divider u13(
.clk(clk),
.div(sw[15:8]),
.dvr(sw[7:0]),
.quotient(QU),
.remainder(REM)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_impctl_dtl_uprcn.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_impctl_dtl_uprcn(si_l ,so_l ,pad ,sclk ,vddo ,cbu ,above ,
clk ,se ,global_reset_n );
input [8:1] cbu ;
output so_l ;
output pad ;
output above ;
input si_l ;
input sclk ;
input vddo ;
input clk ;
input se ;
input global_reset_n ;
supply1 vdd ;
supply0 vss ;
wire net093 ;
wire net0103 ;
wire sclk1 ;
wire sclk2 ;
wire srcv ;
wire net0153 ;
wire bsr_dn_l ;
wire si ;
wire scan1 ;
wire net0130 ;
wire net0135 ;
wire net0139 ;
wire net051 ;
wire net056 ;
wire net059 ;
wire net062 ;
wire bsr_dn25_l ;
wire net067 ;
wire bsr_up ;
wire net073 ;
wire net0125 ;
wire net0126 ;
wire net0127 ;
wire net0129 ;
wire abvref ;
bw_io_dtl_drv_zctl I227 (
.cbu ({cbu } ),
.cbd ({vss ,vss ,vss ,vss ,vss ,vss ,vss ,vss } ),
.pad (pad ),
.sel_data_n (vss ),
.pad_up (net0135 ),
.pad_dn_l (net0125 ),
.pad_dn25_l (net0126 ),
.por (net0139 ),
.bsr_up (bsr_up ),
.bsr_dn_l (bsr_dn_l ),
.bsr_dn25_l (bsr_dn25_l ),
.vddo (vddo ) );
bw_io_dtlhstl_rcv I1 (
.out (abvref ),
.so (srcv ),
.pad (net0103 ),
.ref (net067 ),
.clk (clk ),
.pad_clk_en_l (net0127 ),
.cmsi_clk_en_l (net0153 ),
.cmsi_l (net0129 ),
.se_buf (net0130 ),
.vddo (vddo ) );
bw_u1_soff_4x I257 (
.q (sclk1 ),
.so (net093 ),
.ck (clk ),
.d (sclk ),
.se (se ),
.sd (srcv ) );
bw_u1_soffr_4x I260 (
.q (sclk2 ),
.so (scan1 ),
.ck (clk ),
.d (sclk1 ),
.se (se ),
.sd (net093 ),
.r_l (global_reset_n ) );
bw_u1_soffr_4x I263 (
.q (above ),
.so (net073 ),
.ck (clk ),
.d (net062 ),
.se (se ),
.sd (scan1 ),
.r_l (global_reset_n ) );
bw_u1_inv_4x I268 (
.z (net051 ),
.a (sclk2 ) );
bw_u1_nand2_4x I269 (
.z (net062 ),
.a (net056 ),
.b (net059 ) );
bw_u1_nand2_4x I270 (
.z (net059 ),
.a (net051 ),
.b (above ) );
bw_u1_nand2_4x I271 (
.z (net056 ),
.a (abvref ),
.b (sclk2 ) );
bw_u1_inv_4x I304 (
.z (si ),
.a (si_l ) );
bw_u1_inv_4x I305 (
.z (so_l ),
.a (net073 ) );
bw_io_dtl_edgelogic I306 (
.pad_clk_en_l (net0127 ),
.cmsi_clk_en_l (net0153 ),
.bsr_dn25_l (bsr_dn25_l ),
.pad_dn_l (net0125 ),
.pad_dn25_l (net0126 ),
.bsr_up (bsr_up ),
.bsr_mode (vss ),
.bsr_data_to_core (vss ),
.por_l (vdd ),
.bsr_dn_l (bsr_dn_l ),
.se_buf (net0130 ),
.cmsi_l (net0129 ),
.por (net0139 ),
.reset_l (vdd ),
.sel_bypass (vss ),
.up_open (vss ),
.oe (vdd ),
.down_25 (vss ),
.clk (clk ),
.data (vdd ),
.se (se ),
.si (si ),
.pad_up (net0135 ) );
bw_io_ic_filter I310 (
.torcvr (net0103 ),
.topad (pad ),
.vddo (vddo ) );
bw_io_dtl_vref I313 (
.vref_impctl (net067 ),
.vddo (vddo ) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFBBN_SYMBOL_V
`define SKY130_FD_SC_HD__SDFBBN_SYMBOL_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfbbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFBBN_SYMBOL_V
|
/****************************************************************************************
*
* File Name: IS42s86400.V
* Version: 1.1
* Date: Oct 8th, 2003
* Model: BUS Functional
* Simulator: Model Technology
* Modify Timing parametre and check to fit other speed
* Model: IC42s86400 -7
****************************************************************************************/
`timescale 1ns / 1ps
module IS42s86400 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n);
parameter addr_bits = 13;
parameter data_bits = 8;
parameter col_bits = 10;
parameter mem_sizes = 8388608;
inout [data_bits - 1 : 0] Dq;
input [addr_bits - 1 : 0] Addr;
input [1 : 0] Ba;
input Clk;
input Cke;
input Cs_n;
input Ras_n;
input Cas_n;
input We_n;
wire [1 : 0] Dqm;
assign Dqm[0]= 1'b0;
assign Dqm[1]= 1'b0;
reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline
reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline
reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline
reg [1 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline
reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
reg [addr_bits - 1 : 0] Mode_reg;
reg [data_bits - 1 : 0] Dq_reg, Dq_dqm;
reg [col_bits - 1 : 0] Col_temp, Burst_counter;
reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate
reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge
reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command
reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks)
reg Auto_precharge [0 : 3]; // RW Auto Precharge (Bank)
reg Read_precharge [0 : 3]; // R Auto Precharge
reg Write_precharge [0 : 3]; // W Auto Precharge
reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge
reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge
reg [1 : 0] RW_interrupt_bank; // RW Interrupt Bank
integer RW_interrupt_counter [0 : 3]; // RW Interrupt Counter
integer Count_precharge [0 : 3]; // RW Auto Precharge Counter
reg Data_in_enable;
reg Data_out_enable;
reg [1 : 0] Bank, Prev_bank;
reg [addr_bits - 1 : 0] Row;
reg [col_bits - 1 : 0] Col, Col_brst;
// Internal system clock
reg CkeZ, Sys_clk;
// Commands Decode
wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;
wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n;
wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n;
wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n;
wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n;
wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n;
wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n;
// Burst Length Decode
wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0];
wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
wire Burst_length_f = Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
// CAS Latency Decode
wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4];
wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];
// Write Burst Mode
wire Write_burst_mode = Mode_reg[9];
wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ
assign Dq = Dq_reg; // DQ buffer
// Commands Operation
`define ACT 0
`define NOP 1
`define READ 2
`define WRITE 3
`define PRECH 4
`define A_REF 5
`define BST 6
`define LMR 7
//***********************************************************************
// Timing Parameters for -7
parameter tAC = 5.5; // CAS=3
parameter tHZ = 5.5;
parameter tOH = 2.5; //CAS=3
parameter tMRD = 2.0; // 2 Clk Cycles, 10 ns
parameter tRAS = 49.0;
parameter tRC = 70.0;
parameter tRCD = 21.0;
parameter tRP = 21.0;
parameter tRRD = 14.0;
parameter tDPL = 14.0; //
//************************************************************************
// Timing Check variable
time MRD_chk;
time DPL_chkm [0 : 3];
time RC_chk, RRD_chk;
time RC_chk0, RC_chk1, RC_chk2, RC_chk3;
time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
initial begin
Dq_reg = {data_bits{1'bz}};
Data_in_enable = 0; Data_out_enable = 0;
Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1;
Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0;
DPL_chkm[0] = 0; DPL_chkm[1] = 0; DPL_chkm[2] = 0; DPL_chkm[3] = 0;
RW_interrupt_read[0] = 0; RW_interrupt_read[1] = 0;
RW_interrupt_read[2] = 0; RW_interrupt_read[3] = 0;
RW_interrupt_write[0] = 0; RW_interrupt_write[1] = 0;
RW_interrupt_write[2] = 0; RW_interrupt_write[3] = 0;
MRD_chk = 0; RC_chk = 0; RRD_chk = 0;
RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0;
RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0;
RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0;
RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0;
$timeformat (-9, 1, " ns", 12);
end
// System clock generator
always begin
@ (posedge Clk) begin
Sys_clk = CkeZ;
CkeZ = Cke;
end
@ (negedge Clk) begin
Sys_clk = 1'b0;
end
end
always @ (posedge Sys_clk) begin
// Internal Commamd Pipelined
Command[0] = Command[1];
Command[1] = Command[2];
Command[2] = Command[3];
Command[3] = `NOP;
Col_addr[0] = Col_addr[1];
Col_addr[1] = Col_addr[2];
Col_addr[2] = Col_addr[3];
Col_addr[3] = {col_bits{1'b0}};
Bank_addr[0] = Bank_addr[1];
Bank_addr[1] = Bank_addr[2];
Bank_addr[2] = Bank_addr[3];
Bank_addr[3] = 2'b0;
Bank_precharge[0] = Bank_precharge[1];
Bank_precharge[1] = Bank_precharge[2];
Bank_precharge[2] = Bank_precharge[3];
Bank_precharge[3] = 2'b0;
A10_precharge[0] = A10_precharge[1];
A10_precharge[1] = A10_precharge[2];
A10_precharge[2] = A10_precharge[3];
A10_precharge[3] = 1'b0;
// Dqm pipeline for Read
Dqm_reg0 = Dqm_reg1;
Dqm_reg1 = Dqm;
// Read or Write with Auto Precharge Counter
if (Auto_precharge[0] === 1'b1) begin
Count_precharge[0] = Count_precharge[0] + 1;
end
if (Auto_precharge[1] === 1'b1) begin
Count_precharge[1] = Count_precharge[1] + 1;
end
if (Auto_precharge[2] === 1'b1) begin
Count_precharge[2] = Count_precharge[2] + 1;
end
if (Auto_precharge[3] === 1'b1) begin
Count_precharge[3] = Count_precharge[3] + 1;
end
// Read or Write Interrupt Counter
if (RW_interrupt_write[0] === 1'b1) begin
RW_interrupt_counter[0] = RW_interrupt_counter[0] + 1;
end
if (RW_interrupt_write[1] === 1'b1) begin
RW_interrupt_counter[1] = RW_interrupt_counter[1] + 1;
end
if (RW_interrupt_write[2] === 1'b1) begin
RW_interrupt_counter[2] = RW_interrupt_counter[2] + 1;
end
if (RW_interrupt_write[3] === 1'b1) begin
RW_interrupt_counter[3] = RW_interrupt_counter[3] + 1;
end
// tMRD Counter
MRD_chk = MRD_chk + 1;
// Auto Refresh
if (Aref_enable === 1'b1) begin
// Auto Refresh to Auto Refresh
if ($time - RC_chk < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Auto Refresh", $time);
end
// Precharge to Auto Refresh
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $time);
end
// Precharge to Refresh
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);
end
// Load Mode Register to Auto Refresh
if (MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violation during Auto Refresh", $time);
end
// Record Current tRC time
RC_chk = $time;
end
// Load Mode Register
if (Mode_reg_enable === 1'b1) begin
// Register Mode
Mode_reg = Addr;
// Precharge to Load Mode Register
if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0) begin
$display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $time);
end
// Precharge to Load Mode Register
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $time);
end
// Auto Refresh to Load Mode Register
if ($time - RC_chk < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Load Mode Register", $time);
end
// Load Mode Register to Load Mode Register
if (MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $time);
end
// Reset MRD Counter
MRD_chk = 0;
end
// Active Block (Latch Bank Address and Row Address)
if (Active_enable === 1'b1) begin
// Activate Bank 0
if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
// ACTIVE to ACTIVE command period
if ($time - RC_chk0 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 0", $time);
end
// Precharge to Activate Bank 0
if ($time - RP_chk0 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 0", $time);
end
// Record variables
Act_b0 = 1'b1;
Pc_b0 = 1'b0;
B0_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk0 = $time;
RC_chk0 = $time;
RCD_chk0 = $time;
end
if (Ba == 2'b01 && Pc_b1 == 1'b1) begin
// ACTIVE to ACTIVE command period
if ($time - RC_chk1 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 1", $time);
end
// Precharge to Activate Bank 1
if ($time - RP_chk1 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 1", $time);
end
// Record variables
Act_b1 = 1'b1;
Pc_b1 = 1'b0;
B1_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk1 = $time;
RC_chk1 = $time;
RCD_chk1 = $time;
end
if (Ba == 2'b10 && Pc_b2 == 1'b1) begin
// ACTIVE to ACTIVE command period
if ($time - RC_chk2 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 2", $time);
end
// Precharge to Activate Bank 2
if ($time - RP_chk2 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 2", $time);
end
// Record variables
Act_b2 = 1'b1;
Pc_b2 = 1'b0;
B2_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk2 = $time;
RC_chk2 = $time;
RCD_chk2 = $time;
end
if (Ba == 2'b11 && Pc_b3 == 1'b1) begin
// ACTIVE to ACTIVE command period
if ($time - RC_chk3 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 3", $time);
end
// Precharge to Activate Bank 3
if ($time - RP_chk3 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 3", $time);
end
// Record variables
Act_b3 = 1'b1;
Pc_b3 = 1'b0;
B3_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk3 = $time;
RC_chk3 = $time;
RCD_chk3 = $time;
end
// Active Bank A to Active Bank B
if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin
$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba);
end
// Auto Refresh to Activate
if ($time - RC_chk < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank = %d", $time, Ba);
end
// Load Mode Register to Active
if (MRD_chk < tMRD ) begin
$display ("%m : at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba);
end
// Record variables for checking violation
RRD_chk = $time;
Prev_bank = Ba;
end
// Precharge Block
if (Prech_enable == 1'b1) begin
// Load Mode Register to Precharge
if ($time - MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violaiton during Precharge", $time);
end
// Precharge Bank 0
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
Act_b0 = 1'b0;
Pc_b0 = 1'b1;
RP_chk0 = $time;
// Activate to Precharge
if ($time - RAS_chk0 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tDPL violation check for write
if ($time - DPL_chkm[0] < tDPL) begin
$display ("%m : at time %t ERROR: tDPL violation during Precharge", $time);
end
end
// Precharge Bank 1
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
Act_b1 = 1'b0;
Pc_b1 = 1'b1;
RP_chk1 = $time;
// Activate to Precharge
if ($time - RAS_chk1 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tDPL violation check for write
if ($time - DPL_chkm[1] < tDPL) begin
$display ("%m : at time %t ERROR: tDPL violation during Precharge", $time);
end
end
// Precharge Bank 2
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
Act_b2 = 1'b0;
Pc_b2 = 1'b1;
RP_chk2 = $time;
// Activate to Precharge
if ($time - RAS_chk2 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tDPL violation check for write
if ($time - DPL_chkm[2] < tDPL) begin
$display ("%m : at time %t ERROR: tDPL violation during Precharge", $time);
end
end
// Precharge Bank 3
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
Act_b3 = 1'b0;
Pc_b3 = 1'b1;
RP_chk3 = $time;
// Activate to Precharge
if ($time - RAS_chk3 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tDPL violation check for write
if ($time - DPL_chkm[3] < tDPL) begin
$display ("%m : at time %t ERROR: tDPL violation during Precharge", $time);
end
end
// Terminate a Write Immediately (if same bank or all banks)
if (Data_in_enable === 1'b1 && (Bank === Ba || Addr[10] === 1'b1)) begin
Data_in_enable = 1'b0;
end
// Precharge Command Pipeline for Read
if (Cas_latency_3 === 1'b1) begin
Command[2] = `PRECH;
Bank_precharge[2] = Ba;
A10_precharge[2] = Addr[10];
end else if (Cas_latency_2 === 1'b1) begin
Command[1] = `PRECH;
Bank_precharge[1] = Ba;
A10_precharge[1] = Addr[10];
end
end
// Burst terminate
if (Burst_term === 1'b1) begin
// Terminate a Write Immediately
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
// Terminate a Read Depend on CAS Latency
if (Cas_latency_3 === 1'b1) begin
Command[2] = `BST;
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `BST;
end
end
// Read, Write, Column Latch
if (Read_enable === 1'b1) begin
// Check to see if bank is open (ACT)
if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
(Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
$display("%m : at time %t ERROR: Bank is not Activated for Read", $time);
end
// Activate to Read or Write
if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) ||
(Ba == 2'b01) && ($time - RCD_chk1 < tRCD) ||
(Ba == 2'b10) && ($time - RCD_chk2 < tRCD) ||
(Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin
$display("%m : at time %t ERROR: tRCD violation during Read", $time);
end
// CAS Latency pipeline
if (Cas_latency_3 == 1'b1) begin
Command[2] = `READ;
Col_addr[2] = Addr;
Bank_addr[2] = Ba;
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `READ;
Col_addr[1] = Addr;
Bank_addr[1] = Ba;
end
// Read interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
// Interrupting a Write with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_write[RW_interrupt_bank] = 1'b1;
RW_interrupt_counter[RW_interrupt_bank] = 0;
end
end
// Write with Auto Precharge
if (Addr[10] == 1'b1) begin
Auto_precharge[Ba] = 1'b1;
Count_precharge[Ba] = 0;
RW_interrupt_bank = Ba;
Read_precharge[Ba] = 1'b1;
end
end
// Write Command
if (Write_enable == 1'b1) begin
// Activate to Write
if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
(Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
$display("%m : at time %t ERROR: Bank is not Activated for Write", $time);
end
// Activate to Read or Write
if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) ||
(Ba == 2'b01) && ($time - RCD_chk1 < tRCD) ||
(Ba == 2'b10) && ($time - RCD_chk2 < tRCD) ||
(Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin
$display("%m : at time %t ERROR: tRCD violation during Read", $time);
end
// Latch Write command, Bank, and Column
Command[0] = `WRITE;
Col_addr[0] = Addr;
Bank_addr[0] = Ba;
// Write interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
// Interrupting a Write with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_write[RW_interrupt_bank] = 1'b1;
end
end
// Write interrupt Read (terminate Read immediately)
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
// Interrupting a Read with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Read_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_read[RW_interrupt_bank] = 1'b1;
end
end
// Write with Auto Precharge
if (Addr[10] == 1'b1) begin
Auto_precharge[Ba] = 1'b1;
Count_precharge[Ba] = 0;
RW_interrupt_bank = Ba;
Write_precharge[Ba] = 1'b1;
end
end
/*
Write with Auto Precharge Calculation
The device start internal precharge when:
1. Meet minimum tRAS requirement
and 2. tDPL cycle(s) after last valid data
or 3. Interrupt by a Read or Write (with or without Auto
Precharge)
Note: Model is starting the internal precharge 1 cycle after
they meet all the
requirement but tRP will be compensate for the time after
the 1 cycle.
*/
if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1))
begin
if ((($time - RAS_chk0 >= tRAS) &&
// Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) ||
(RW_interrupt_write[0] == 1'b1 && RW_interrupt_counter[0] >= 1)) begin // Case 3
Auto_precharge[0] = 1'b0;
Write_precharge[0] = 1'b0;
RW_interrupt_write[0] = 1'b0;
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time + tDPL;
end
end
if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1))
begin
if ((($time - RAS_chk1 >= tRAS) &&
// Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) ||
(RW_interrupt_write[1] == 1'b1 && RW_interrupt_counter[1] >= 1)) begin // Case 3
Auto_precharge[1] = 1'b0;
Write_precharge[1] = 1'b0;
RW_interrupt_write[1] = 1'b0;
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time + tDPL;
end
end
if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1))
begin
if ((($time - RAS_chk2 >= tRAS) &&
// Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) ||
(RW_interrupt_write[2] == 1'b1 && RW_interrupt_counter[2] >= 1)) begin // Case 3
Auto_precharge[2] = 1'b0;
Write_precharge[2] = 1'b0;
RW_interrupt_write[2] = 1'b0;
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time + tDPL;
end
// end
end
if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1))
begin
if ((($time - RAS_chk3 >= tRAS) &&
// Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) ||
(RW_interrupt_write[3] == 1'b1 && RW_interrupt_counter[3] >= 1)) begin // Case 3
Auto_precharge[3] = 1'b0;
Write_precharge[3] = 1'b0;
RW_interrupt_write[3] = 1'b0;
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time + tDPL;
end
end
// Read with Auto Precharge Calculation
// The device start internal precharge:
// 1. Meet minimum tRAS requirement
// and 2. CAS Latency - 1 cycles before last burst
// or 3. Interrupt by a Read or Write (with or without AutoPrecharge)
if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1))
begin
if ((($time - RAS_chk0 >= tRAS) &&
// Case 1
((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) ||
// Case 2
(Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
(RW_interrupt_read[0] == 1'b1)) begin
// Case 3
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
Auto_precharge[0] = 1'b0;
Read_precharge[0] = 1'b0;
RW_interrupt_read[0] = 1'b0;
end
end
if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1))
begin
if ((($time - RAS_chk1 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
(RW_interrupt_read[1] == 1'b1)) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
Auto_precharge[1] = 1'b0;
Read_precharge[1] = 1'b0;
RW_interrupt_read[1] = 1'b0;
end
end
if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1))
begin
if ((($time - RAS_chk2 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
(RW_interrupt_read[2] == 1'b1)) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
Auto_precharge[2] = 1'b0;
Read_precharge[2] = 1'b0;
RW_interrupt_read[2] = 1'b0;
end
end
if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1))
begin
if ((($time - RAS_chk3 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
(RW_interrupt_read[3] == 1'b1)) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
Auto_precharge[3] = 1'b0;
Read_precharge[3] = 1'b0;
RW_interrupt_read[3] = 1'b0;
end
end
// Internal Precharge or Bst
if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks
if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
end else if (Command[0] == `BST) begin // BST terminate a read to current bank
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
if (Data_out_enable == 1'b0) begin
Dq_reg <= #tOH {data_bits{1'bz}};
end
// Detect Read or Write command
if (Command[0] == `READ) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
case (Bank_addr[0])
2'b00 : Row = B0_row_addr;
2'b01 : Row = B1_row_addr;
2'b10 : Row = B2_row_addr;
2'b11 : Row = B3_row_addr;
endcase
Burst_counter = 0;
Data_in_enable = 1'b0;
Data_out_enable = 1'b1;
end else if (Command[0] == `WRITE) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
case (Bank_addr[0])
2'b00 : Row = B0_row_addr;
2'b01 : Row = B1_row_addr;
2'b10 : Row = B2_row_addr;
2'b11 : Row = B3_row_addr;
endcase
Burst_counter = 0;
Data_in_enable = 1'b1;
Data_out_enable = 1'b0;
end
// DQ buffer (Driver/Receiver)
if (Data_in_enable == 1'b1) begin
// Writing Data to Memory
// Array buffer
case (Bank)
2'b00 : Dq_dqm = Bank0 [{Row, Col}];
2'b01 : Dq_dqm = Bank1 [{Row, Col}];
2'b10 : Dq_dqm = Bank2 [{Row, Col}];
2'b11 : Dq_dqm = Bank3 [{Row, Col}];
endcase
// Dqm operation
if (Dqm[0] == 1'b0) begin
Dq_dqm [ 7 : 0] = Dq [ 7 : 0];
end
if (Dqm[1] == 1'b0) begin
Dq_dqm [15 : 8] = Dq [15 : 8];
end
// Write to memory
case (Bank)
2'b00 : Bank0 [{Row, Col}] = Dq_dqm;
2'b01 : Bank1 [{Row, Col}] = Dq_dqm;
2'b10 : Bank2 [{Row, Col}] = Dq_dqm;
2'b11 : Bank3 [{Row, Col}] = Dq_dqm;
endcase
if (Dqm !== 2'b11) begin
// Record tDPL for manual precharge
DPL_chkm [Bank] = $time;
end
// Advance burst counter subroutine
#tHZ Burst_decode;
end else if (Data_out_enable == 1'b1) begin
// Reading Data from Memory
// Array buffer
case (Bank)
2'b00 : Dq_dqm = Bank0[{Row, Col}];
2'b01 : Dq_dqm = Bank1[{Row, Col}];
2'b10 : Dq_dqm = Bank2[{Row, Col}];
2'b11 : Dq_dqm = Bank3[{Row, Col}];
endcase
// Dqm operation
if (Dqm_reg0 [0] == 1'b1) begin
Dq_dqm [ 7 : 0] = 8'bz;
end
if (Dqm_reg0 [1] == 1'b1) begin
Dq_dqm [15 : 8] = 8'bz;
end
if (Dqm_reg0 !== 2'b11) begin
Dq_reg = #tAC Dq_dqm;
end else begin
Dq_reg = #tHZ {data_bits{1'bz}};
end
// Advance burst counter subroutine
Burst_decode;
end
end
// Burst counter decode
task Burst_decode;
begin
// Advance Burst Counter
Burst_counter = Burst_counter + 1;
// Burst Type
if (Mode_reg[3] == 1'b0) begin
// Sequential Burst
Col_temp = Col + 1;
end else if (Mode_reg[3] == 1'b1) begin
// Interleaved Burst
Col_temp[2] = Burst_counter[2] ^ Col_brst[2];
Col_temp[1] = Burst_counter[1] ^ Col_brst[1];
Col_temp[0] = Burst_counter[0] ^ Col_brst[0];
end
// Burst Length
if (Burst_length_2) begin
// Burst Length = 2
Col [0] = Col_temp [0];
end else if (Burst_length_4) begin
// Burst Length = 4
Col [1 : 0] = Col_temp [1 : 0];
end else if (Burst_length_8) begin
// Burst Length = 8
Col [2 : 0] = Col_temp [2 : 0];
end else begin
// Burst Length = FULL
Col = Col_temp;
end
// Burst Read Single Write
if (Write_burst_mode == 1'b1) begin
Data_in_enable = 1'b0;
end
// Data Counter
if (Burst_length_1 == 1'b1) begin
if (Burst_counter >= 1) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_2 == 1'b1) begin
if (Burst_counter >= 2) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_4 == 1'b1) begin
if (Burst_counter >= 4) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_8 == 1'b1) begin
if (Burst_counter >= 8) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end
end
endtask
// *************************************************************************************
// Timing Parameters for -7
specify
specparam
tAH = 1.0, // Addr, Ba Hold Time
tAS = 1.75, // Addr, Ba Setup Time
tCH = 3.0, // Clock High-Level Width
tCL = 3.0, // Clock Low-Level Width
tCK = 7.0, // Clock Cycle Time,cas=3
tDH = 1.0, // Data-in Hold Time
tDS = 1.75, // Data-in Setup Time
tCKH = 1.0, // CKE Hold Time
tCKS = 1.75, // CKE Setup Time
tCMH = 1.0, // CS#, RAS#, CAS#, WE#, DQM# Hold Time
tCMS = 1.75; // CS#, RAS#, CAS#, WE#, DQM# Setup Time
// ************************************************************************
$width (posedge Clk, tCH);
$width (negedge Clk, tCL);
$period (negedge Clk, tCK);
$period (posedge Clk, tCK);
$setuphold(posedge Clk, Cke, tCKS, tCKH);
$setuphold(posedge Clk, Cs_n, tCMS, tCMH);
$setuphold(posedge Clk, Cas_n, tCMS, tCMH);
$setuphold(posedge Clk, Ras_n, tCMS, tCMH);
$setuphold(posedge Clk, We_n, tCMS, tCMH);
$setuphold(posedge Clk, Addr, tAS, tAH);
$setuphold(posedge Clk, Ba, tAS, tAH);
$setuphold(posedge Clk, Dqm, tCMS, tCMH);
$setuphold(posedge Dq_chk, Dq, tDS, tDH);
endspecify
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10036 10230
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ddr3_odt_gen
# (parameter
CFG_DWIDTH_RATIO = 2,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_PORT_WIDTH_TCL = 4,
CFG_PORT_WIDTH_CAS_WR_LAT = 4
)
(
ctl_clk,
ctl_reset_n,
cfg_tcl,
cfg_cas_wr_lat,
cfg_output_regd,
bg_do_write,
bg_do_read,
bg_do_burst_chop,
int_odt_l,
int_odt_h,
int_odt_i_1,
int_odt_i_2
);
localparam integer CFG_TCL_PIPE_LENGTH = 2**CFG_PORT_WIDTH_TCL;
//=================================================================================================//
// DDR3 ODT timing parameters //
//=================================================================================================//
localparam integer CFG_ODTH8 = 6; //Indicates No. of cycles ODT signal should stay high
localparam integer CFG_ODTH4 = 4; //Indicates No. of cycles ODT signal should stay high
localparam integer CFG_ODTPIPE_THRESHOLD = CFG_DWIDTH_RATIO / 2;
// AL also applies to ODT signal so ODT logic is AL agnostic
// also regdimm because ODT is registered too
// ODTLon = CWL + AL - 2
// ODTLoff = CWL + AL - 2
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_TCL-1:0] cfg_tcl;
input [CFG_PORT_WIDTH_CAS_WR_LAT-1:0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
input bg_do_write;
input bg_do_read;
input bg_do_burst_chop;
output int_odt_l;
output int_odt_h;
output int_odt_i_1;
output int_odt_i_2;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire bg_do_write;
reg int_do_read;
reg int_do_write_burst_chop;
reg int_do_read_burst_chop;
reg int_do_read_burst_chop_c;
reg do_read_r;
wire [3:0] diff_unreg; // difference between CL and CWL
reg [3:0] diff;
wire [3:0] diff_modulo_unreg;
reg [3:0] diff_modulo;
wire [3:0] sel_do_read_pipe_unreg;
reg [3:0] sel_do_read_pipe;
reg diff_modulo_not_zero;
reg diff_modulo_one;
reg diff_modulo_two;
reg diff_modulo_three;
reg int_odt_l_int;
reg int_odt_l_int_r1;
reg int_odt_l_int_r2;
reg premux_odt_h;
reg premux_odt_h_r;
reg int_odt_h_int;
reg int_odt_h_int_r1;
reg int_odt_h_int_r2;
reg int_odt_i_1_int;
reg int_odt_i_2_int;
reg int_odt_i_1_int_r1;
reg int_odt_i_2_int_r1;
reg int_odt_i_1_int_r2;
reg int_odt_i_2_int_r2;
wire int_odt_l;
wire int_odt_h;
wire int_odt_i_1;
wire int_odt_i_2;
reg [3:0] doing_write_count;
reg [3:0] doing_read_count;
wire doing_read_count_not_zero;
reg doing_read_count_not_zero_r;
wire [3:0] doing_write_count_limit;
wire [3:0] doing_read_count_limit;
reg [CFG_TCL_PIPE_LENGTH -1:0] do_read_pipe;
reg [CFG_TCL_PIPE_LENGTH -1:0] do_burst_chop_pipe;
//=================================================================================================//
// Define ODT pulse width during READ operation //
//=================================================================================================//
//ODTLon/ODTLoff are calculated based on CWL, Below logic is to compensate for that timing during read, Needs to delay ODT signal by cfg_tcl - cfg_cas_wr_lat
assign diff_unreg = cfg_tcl - cfg_cas_wr_lat;
assign diff_modulo_unreg = (diff % CFG_ODTPIPE_THRESHOLD);
assign sel_do_read_pipe_unreg = (diff / CFG_ODTPIPE_THRESHOLD) + diff_modulo_not_zero;
//assign diff_modulo_not_zero = (|diff_modulo);
//assign sel_do_read_pipe = diff - CFG_ODTPIPE_THRESHOLD;
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
diff <= 0;
diff_modulo <= 0;
sel_do_read_pipe <= 0;
end
else
begin
diff <= diff_unreg;
diff_modulo <= diff_modulo_unreg;
sel_do_read_pipe <= (sel_do_read_pipe_unreg > 0) ? (sel_do_read_pipe_unreg - 1'b1) : 0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
diff_modulo_not_zero <= 1'b0;
diff_modulo_one <= 1'b0;
diff_modulo_two <= 1'b0;
diff_modulo_three <= 1'b0;
end
else
begin
diff_modulo_not_zero <= |diff_modulo;
diff_modulo_one <= (diff_modulo == 1) ? 1'b1 : 1'b0;
diff_modulo_two <= (diff_modulo == 2) ? 1'b1 : 1'b0;
diff_modulo_three <= (diff_modulo == 3) ? 1'b1 : 1'b0;
end
end
always @ (*)
begin
int_do_read = (diff < CFG_ODTPIPE_THRESHOLD) ? bg_do_read : do_read_pipe [sel_do_read_pipe] ;
int_do_read_burst_chop_c = (diff < CFG_ODTPIPE_THRESHOLD) ? bg_do_burst_chop : do_burst_chop_pipe [sel_do_read_pipe] ;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_do_read_burst_chop <= 1'b0;
end
else
begin
if (int_do_read)
begin
int_do_read_burst_chop <= int_do_read_burst_chop_c;
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_read_pipe <= 0;
end
else
begin
do_read_pipe[CFG_TCL_PIPE_LENGTH-1:0] <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0], bg_do_read};
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_burst_chop_pipe <= 0;
end
else
begin
do_burst_chop_pipe[CFG_TCL_PIPE_LENGTH-1:0] <= {do_burst_chop_pipe[CFG_TCL_PIPE_LENGTH-2:0], bg_do_burst_chop};
end
end
assign doing_read_count_limit = int_do_read_burst_chop ? ((CFG_ODTH4 / (CFG_DWIDTH_RATIO / 2)) - 1) : ((CFG_ODTH8 / (CFG_DWIDTH_RATIO / 2)) - 1);
assign doing_read_count_not_zero = (|doing_read_count);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_read_count <= 0;
end
else
begin
if (int_do_read)
begin
doing_read_count <= 1;
end
else if (doing_read_count >= doing_read_count_limit)
begin
doing_read_count <= 0;
end
else if (doing_read_count > 0)
begin
doing_read_count <= doing_read_count + 1'b1;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
doing_read_count_not_zero_r <= 1'b0;
end
else
begin
doing_read_count_not_zero_r <= doing_read_count_not_zero;
end
end
//=================================================================================================//
// Define ODT pulse width during WRITE operation //
//=================================================================================================//
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_do_write_burst_chop <= 1'b0;
end
else
begin
if (bg_do_write)
begin
int_do_write_burst_chop <= bg_do_burst_chop;
end
end
end
assign doing_write_count_limit = int_do_write_burst_chop ? ((CFG_ODTH4 / (CFG_DWIDTH_RATIO / 2)) - 1) : ((CFG_ODTH8 / (CFG_DWIDTH_RATIO / 2)) - 1);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_write_count <= 0;
end
else
begin
if (bg_do_write)
begin
doing_write_count <= 1;
end
else if (doing_write_count >= doing_write_count_limit)
begin
doing_write_count <= 0;
end
else if (doing_write_count > 0)
begin
doing_write_count <= doing_write_count + 1'b1;
end
end
end
//=================================================================================================//
// ODT signal generation block //
//=================================================================================================//
always @ (*)
begin
if (bg_do_write || int_do_read)
begin
premux_odt_h = 1'b1;
end
else if (doing_write_count > 0 || doing_read_count > 0)
begin
premux_odt_h = 1'b1;
end
else
begin
premux_odt_h = 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
premux_odt_h_r <= 1'b0;
end
else
begin
if (int_do_read)
begin
premux_odt_h_r <= 1'b1;
end
else if ((doing_read_count > 1 && ((diff_modulo_one && CFG_ODTPIPE_THRESHOLD == 4) || diff_modulo_two)) || (doing_read_count > 0 && ((diff_modulo_one && CFG_ODTPIPE_THRESHOLD == 2) || diff_modulo_three)))
begin
premux_odt_h_r <= 1'b1;
end
else
begin
premux_odt_h_r <= 1'b0;
end
end
end
always @ (*)
begin
if (diff_modulo_not_zero & (int_do_read|doing_read_count_not_zero_r))
begin
int_odt_h_int = premux_odt_h_r;
end
else // write, read with normal odt
begin
int_odt_h_int = premux_odt_h;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_l_int <= 1'b0;
end
else
begin
if (bg_do_write || (int_do_read && !diff_modulo_two && !diff_modulo_three))
begin
int_odt_l_int <= 1'b1;
end
else if (doing_write_count > 0 || doing_read_count > 0)
begin
int_odt_l_int <= 1'b1;
end
else
begin
int_odt_l_int <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_i_1_int <= 1'b0;
end
else
begin
if (bg_do_write || int_do_read)
begin
int_odt_i_1_int <= 1'b1;
end
else if (doing_write_count > 1 || (doing_read_count > 1 && !diff_modulo_not_zero) || (doing_read_count > 0 && diff_modulo_not_zero))
begin
int_odt_i_1_int <= 1'b1;
end
else
begin
int_odt_i_1_int <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_i_2_int <= 1'b0;
end
else
begin
if (bg_do_write || int_do_read)
begin
int_odt_i_2_int <= 1'b1;
end
else if (doing_write_count > 1 || (doing_read_count > 1 && (!diff_modulo_not_zero || diff_modulo_one)) || (doing_read_count > 0 && (diff_modulo_two || diff_modulo_three)))
begin
int_odt_i_2_int <= 1'b1;
end
else
begin
int_odt_i_2_int <= 1'b0;
end
end
end
//Generate registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_h_int_r1 <= 1'b0;
int_odt_l_int_r1 <= 1'b0;
int_odt_i_1_int_r1 <= 1'b0;
int_odt_i_2_int_r1 <= 1'b0;
int_odt_h_int_r2 <= 1'b0;
int_odt_l_int_r2 <= 1'b0;
int_odt_i_1_int_r2 <= 1'b0;
int_odt_i_2_int_r2 <= 1'b0;
end
else
begin
int_odt_h_int_r1 <= int_odt_h_int;
int_odt_l_int_r1 <= int_odt_l_int;
int_odt_i_1_int_r1 <= int_odt_i_1_int;
int_odt_i_2_int_r1 <= int_odt_i_2_int;
int_odt_h_int_r2 <= int_odt_h_int_r1;
int_odt_l_int_r2 <= int_odt_l_int_r1;
int_odt_i_1_int_r2 <= int_odt_i_1_int_r1;
int_odt_i_2_int_r2 <= int_odt_i_2_int_r1;
end
end
generate
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
assign int_odt_h = (cfg_output_regd == 2) ? int_odt_h_int_r2 : ((cfg_output_regd == 1) ? int_odt_h_int_r1 : int_odt_h_int);
assign int_odt_l = (cfg_output_regd == 2) ? int_odt_h_int_r2 : ((cfg_output_regd == 1) ? int_odt_h_int_r1 : int_odt_h_int);
assign int_odt_i_1 = 1'b0;
assign int_odt_i_2 = 1'b0;
end
else if (CFG_DWIDTH_RATIO == 4) // half rate
begin
assign int_odt_h = (cfg_output_regd == 2) ? int_odt_h_int_r2 : ((cfg_output_regd == 1) ? int_odt_h_int_r1 : int_odt_h_int);
assign int_odt_l = (cfg_output_regd == 2) ? int_odt_l_int_r2 : ((cfg_output_regd == 1) ? int_odt_l_int_r1 : int_odt_l_int);
assign int_odt_i_1 = 1'b0;
assign int_odt_i_2 = 1'b0;
end
else if (CFG_DWIDTH_RATIO == 8) // quarter rate
begin
assign int_odt_h = (cfg_output_regd == 2) ? int_odt_h_int_r2 : ((cfg_output_regd == 1) ? int_odt_h_int_r1 : int_odt_h_int );
assign int_odt_l = (cfg_output_regd == 2) ? int_odt_l_int_r2 : ((cfg_output_regd == 1) ? int_odt_l_int_r1 : int_odt_l_int );
assign int_odt_i_1 = (cfg_output_regd == 2) ? int_odt_i_1_int_r2 : ((cfg_output_regd == 1) ? int_odt_i_1_int_r1 : int_odt_i_1_int);
assign int_odt_i_2 = (cfg_output_regd == 2) ? int_odt_i_2_int_r2 : ((cfg_output_regd == 1) ? int_odt_i_2_int_r1 : int_odt_i_2_int);
end
endgenerate
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
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//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module init_config_rom (
clka,
addra,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [9 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [31 : 0] douta;
blk_mem_gen_v8_3_4 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(3),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("init_config_rom.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_READ_WIDTH_A(32),
.C_WRITE_DEPTH_A(1024),
.C_READ_DEPTH_A(1024),
.C_ADDRA_WIDTH(10),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(32),
.C_READ_WIDTH_B(32),
.C_WRITE_DEPTH_B(1024),
.C_READ_DEPTH_B(1024),
.C_ADDRB_WIDTH(10),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.622 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(1'B0),
.addra(addra),
.dina(32'B0),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(10'B0),
.dinb(32'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(32'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
/*
Filename: translation_layer.v
Version: 1.0
Verilog Standard: Verilog-2001
Description: The translation layer provides a uniform interface for all classic
PCIe interfaces, such as all Altera devices, and all Xilinx devices (pre VC709).
Notes: Any modifications to this file should meet the conditions set
forth in the "Trellis Style Guide"
Author: Dustin Richmond (@darichmond)
Co-Authors:
*/
`include "trellis.vh" // Defines the user-facing signal widths.
`include "xilinx.vh"
module translation_xilinx
#(
parameter C_PCI_DATA_WIDTH = 256
)
(
input CLK,
input RST_IN,
// Interface: Xilinx RX
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RX_TDATA,
input [(C_PCI_DATA_WIDTH/8)-1:0] M_AXIS_RX_TKEEP,
input M_AXIS_RX_TLAST,
input M_AXIS_RX_TVALID,
output M_AXIS_RX_TREADY,
input [`SIG_XIL_RX_TUSER_W-1:0] M_AXIS_RX_TUSER,
output RX_NP_OK,
output RX_NP_REQ,
// Interface: Xilinx TX
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_TX_TDATA,
output [(C_PCI_DATA_WIDTH/8)-1:0] S_AXIS_TX_TKEEP,
output S_AXIS_TX_TLAST,
output S_AXIS_TX_TVALID,
input S_AXIS_TX_TREADY,
output [`SIG_XIL_TX_TUSER_W-1:0] S_AXIS_TX_TUSER,
output TX_CFG_GNT,
// Interface: Xilinx Configuration
input [`SIG_BUSID_W-1:0] CFG_BUS_NUMBER,
input [`SIG_DEVID_W-1:0] CFG_DEVICE_NUMBER,
input [`SIG_FNID_W-1:0] CFG_FUNCTION_NUMBER,
input [`SIG_CFGREG_W-1:0] CFG_COMMAND,
input [`SIG_CFGREG_W-1:0] CFG_DCOMMAND,
input [`SIG_CFGREG_W-1:0] CFG_LSTATUS,
input [`SIG_CFGREG_W-1:0] CFG_LCOMMAND,
// Interface: Xilinx Flow Control
input [`SIG_FC_CPLD_W-1:0] FC_CPLD,
input [`SIG_FC_CPLH_W-1:0] FC_CPLH,
output [`SIG_FC_SEL_W-1:0] FC_SEL,
// Interface: Xilinx Interrupt
input CFG_INTERRUPT_MSIEN,
input CFG_INTERRUPT_RDY,
output CFG_INTERRUPT,
// Interface: RX Classic
output [C_PCI_DATA_WIDTH-1:0] RX_TLP,
output RX_TLP_VALID,
output RX_TLP_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RX_TLP_START_OFFSET,
output RX_TLP_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RX_TLP_END_OFFSET,
output [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
input RX_TLP_READY,
// Interface: TX Classic
output TX_TLP_READY,
input [C_PCI_DATA_WIDTH-1:0] TX_TLP,
input TX_TLP_VALID,
input TX_TLP_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_START_OFFSET,
input TX_TLP_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_END_OFFSET,
// Interface: Configuration
output [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
output CONFIG_BUS_MASTER_ENABLE,
output [`SIG_LINKWIDTH_W-1:0] CONFIG_LINK_WIDTH,
output [`SIG_LINKRATE_W-1:0] CONFIG_LINK_RATE,
output [`SIG_MAXREAD_W-1:0] CONFIG_MAX_READ_REQUEST_SIZE,
output [`SIG_MAXPAYLOAD_W-1:0] CONFIG_MAX_PAYLOAD_SIZE,
output CONFIG_INTERRUPT_MSIENABLE,
output CONFIG_CPL_BOUNDARY_SEL,
// Interface: Flow Control
output [`SIG_FC_CPLD_W-1:0] CONFIG_MAX_CPL_DATA,
output [`SIG_FC_CPLH_W-1:0] CONFIG_MAX_CPL_HDR,
// Interface: Interrupt
output INTR_MSI_RDY, // High when interrupt is able to be sent
input INTR_MSI_REQUEST // High to request interrupt
);
`include "functions.vh"
/*
Notes on the Configuration Interface:
Link Width (cfg_lstatus[9:4]): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16
Link Rate (cfg_lstatus[3:0]): 0001=2.5GT/s, 0010=5.0GT/s, 0011=8.0GT/s
Max Read Request Size (cfg_dcommand[14:12]): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
Max Payload Size (cfg_dcommand[7:5]): 000=128B, 001=256B, 010=512B, 011=1024B
Bus Master Enable (cfg_command[2]): 1=Enabled, 0=Disabled
Read Completion Boundary (cfg_lcommand[3]): 0=64 bytes, 1=128 bytes
MSI Enable (cfg_msicsr[0]): 1=Enabled, 0=Disabled
Notes on the Flow Control Interface:
FC_CPLD (Xilinx) Receive credit limit for data
FC_CPLH (Xilinx) Receive credit limit for headers
FC_SEL (Xilinx Only) Selects the correct output on the FC_* signals
Notes on the TX Interface:
TX_CFG_GNT (Xilinx): 1=Always allow core to transmit internally generated TLPs
Notes on the RX Interface:
RX_NP_OK (Xilinx): 1=Always allow non posted transactions
*/
/*AUTOWIRE*/
reg rRxTlpValid;
reg rRxTlpEndFlag;
// Rx Interface (From PCIe Core)
assign RX_TLP = M_AXIS_RX_TDATA;
assign RX_TLP_VALID = M_AXIS_RX_TVALID;
// Rx Interface (To PCIe Core)
assign M_AXIS_RX_TREADY = RX_TLP_READY;
// TX Interface (From PCIe Core)
assign TX_TLP_READY = S_AXIS_TX_TREADY;
// TX Interface (TO PCIe Core)
assign S_AXIS_TX_TDATA = TX_TLP;
assign S_AXIS_TX_TVALID = TX_TLP_VALID;
assign S_AXIS_TX_TLAST = TX_TLP_END_FLAG;
// Configuration Interface
assign CONFIG_COMPLETER_ID = {CFG_BUS_NUMBER,CFG_DEVICE_NUMBER,CFG_FUNCTION_NUMBER};
assign CONFIG_BUS_MASTER_ENABLE = CFG_COMMAND[`CFG_COMMAND_BUSMSTR_R];
assign CONFIG_LINK_WIDTH = CFG_LSTATUS[`CFG_LSTATUS_LWIDTH_R];
assign CONFIG_LINK_RATE = CFG_LSTATUS[`CFG_LSTATUS_LRATE_R];
assign CONFIG_MAX_READ_REQUEST_SIZE = CFG_DCOMMAND[`CFG_DCOMMAND_MAXREQ_R];
assign CONFIG_MAX_PAYLOAD_SIZE = CFG_DCOMMAND[`CFG_DCOMMAND_MAXPAY_R];
assign CONFIG_INTERRUPT_MSIENABLE = CFG_INTERRUPT_MSIEN;
assign CONFIG_CPL_BOUNDARY_SEL = CFG_LCOMMAND[`CFG_LCOMMAND_RCB_R];
assign CONFIG_MAX_CPL_DATA = FC_CPLD;
assign CONFIG_MAX_CPL_HDR = FC_CPLH;
assign FC_SEL = `SIG_FC_SEL_RX_MAXALLOC_V;
assign RX_NP_OK = 1'b1;
assign RX_NP_REQ = 1'b1;
assign TX_CFG_GNT = 1'b1;
// Interrupt interface
assign CFG_INTERRUPT = INTR_MSI_REQUEST;
assign INTR_MSI_RDY = CFG_INTERRUPT_RDY;
generate
if (C_PCI_DATA_WIDTH == 9'd32) begin : gen_xilinx_32
assign RX_TLP_START_FLAG = ~rRxTlpValid | rRxTlpEndFlag;
assign RX_TLP_START_OFFSET = {clog2s(C_PCI_DATA_WIDTH/32){1'b0}};
assign RX_TLP_END_OFFSET = 0;
assign RX_TLP_END_FLAG = M_AXIS_RX_TLAST;
assign S_AXIS_TX_TKEEP = 4'hF;
end else if (C_PCI_DATA_WIDTH == 9'd64) begin : gen_xilinx_64
assign RX_TLP_START_FLAG = ~rRxTlpValid | rRxTlpEndFlag;
assign RX_TLP_START_OFFSET = {clog2s(C_PCI_DATA_WIDTH/32){1'b0}};
assign RX_TLP_END_OFFSET = M_AXIS_RX_TKEEP[4];
assign RX_TLP_END_FLAG = M_AXIS_RX_TLAST;
assign S_AXIS_TX_TKEEP = {{4{TX_TLP_END_OFFSET | ~TX_TLP_END_FLAG}},4'hF};
end else if (C_PCI_DATA_WIDTH == 9'd128) begin : gen_xilinx_128
assign RX_TLP_END_OFFSET = M_AXIS_RX_TUSER[20:19];
assign RX_TLP_END_FLAG = M_AXIS_RX_TUSER[21];
assign RX_TLP_START_FLAG = M_AXIS_RX_TUSER[14];
assign RX_TLP_START_OFFSET = M_AXIS_RX_TUSER[13:12];
assign S_AXIS_TX_TKEEP = {{4{~TX_TLP_END_FLAG | (TX_TLP_END_OFFSET == 2'b11)}},
{4{~TX_TLP_END_FLAG | (TX_TLP_END_OFFSET >= 2'b10)}},
{4{~TX_TLP_END_FLAG | (TX_TLP_END_OFFSET >= 2'b01)}},
{4{1'b1}}};// TODO: More efficient if we use masks...
end else if (C_PCI_DATA_WIDTH == 9'd256) begin : x256
// Not possible...
end
endgenerate
always @(posedge CLK) begin
rRxTlpValid <= RX_TLP_VALID;
rRxTlpEndFlag <= RX_TLP_END_FLAG;
end
endmodule // translation_layer
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EBUFN_4_V
`define SKY130_FD_SC_LS__EBUFN_4_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__ebufn_4 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__ebufn_4 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__EBUFN_4_V
|
// file: clock_divider.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1_____7.143______0.000______50.0______244.806____114.212
// CLK_OUT2____25.000______0.000______50.0______191.696____114.212
// CLK_OUT3___100.000______0.000______50.0______144.719____114.212
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clock_divider,clk_wiz_v5_1,{component_name=clock_divider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=3,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clock_divider
(
// Clock in ports
input CLOCK_PLL,
// Clock out ports
output CLOCK_7_143,
output CLOCK_25,
output CLOCK_100,
// Status and control signals
input reset,
output locked
);
clock_divider_clk_wiz inst
(
// Clock in ports
.CLOCK_PLL(CLOCK_PLL),
// Clock out ports
.CLOCK_7_143(CLOCK_7_143),
.CLOCK_25(CLOCK_25),
.CLOCK_100(CLOCK_100),
// Status and control signals
.reset(reset),
.locked(locked)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: data_prbs_gen.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:41:58 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module is used LFSR to generate random data for memory
// data write or memory data read comparison.The first data is
// seeded by the input prbs_seed_i which is connected to memory address.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module data_prbs_gen #
(
parameter TCQ = 100,
parameter EYE_TEST = "FALSE",
parameter PRBS_WIDTH = 32, // "SEQUENTIAL_BUrst_i"
parameter SEED_WIDTH = 32
)
(
input clk_i,
input clk_en,
input rst_i,
input [31:0] prbs_fseed_i,
input prbs_seed_init, // when high the prbs_x_seed will be loaded
input [PRBS_WIDTH - 1:0] prbs_seed_i,
output [PRBS_WIDTH - 1:0] prbs_o // generated address
);
reg [PRBS_WIDTH - 1 :0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
integer i;
always @ (posedge clk_i)
begin
if (prbs_seed_init && EYE_TEST == "FALSE" || rst_i ) //reset it to a known good state to prevent it locks up
// if (rst_i ) //reset it to a known good state to prevent it locks up
begin
lfsr_q <= #TCQ {prbs_seed_i + prbs_fseed_i[31:0] + 32'h55555555};
end
else if (clk_en) begin
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
always @ (lfsr_q[PRBS_WIDTH:1]) begin
prbs = lfsr_q[PRBS_WIDTH:1];
end
assign prbs_o = prbs;
endmodule
|
`include "core.h"
`default_nettype none
module pipeline_control_spr_exchange(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//System Register
input wire [31:0] iSYSREG_SPR,
input wire [31:0] iSYSREG_TISR,
input wire [31:0] iSYSREG_TIDR,
//Request
input wire iRD_START,
input wire iRD_KERNEL, //0:User Mode(Kernel -> User) | 1 : Kernel Mode(User -> Kernel)
//FInish
output wire oFINISH,
output wire [31:0] oFINISH_SPR,
//Load Store
output wire oLDST_USE,
output wire oLDST_REQ,
input wire iLDST_BUSY,
output wire [1:0] oLDST_ORDER, //00=Byte Order 01=2Byte Order 10= Word Order 11= None
output wire oLDST_RW, //0=Read 1=Write
output wire [13:0] oLDST_ASID,
output wire [1:0] oLDST_MMUMOD,
output wire [31:0] oLDST_PDT,
output wire [31:0] oLDST_ADDR,
output wire [31:0] oLDST_DATA,
input wire iLDST_REQ,
input wire [31:0] iLDST_DATA
);
/***************************************************************************
State
***************************************************************************/
localparam L_PARAM_IDLE = 3'h0;
localparam L_PARAM_LOAD_REQ = 3'h1;
localparam L_PARAM_LOAD_ACK = 3'h2;
localparam L_PARAM_STORE_REQ = 3'h3;
localparam L_PARAM_STORE_ACK = 3'h4;
reg [2:0] state;
reg [2:0] b_state;
always@*begin
case(b_state)
L_PARAM_IDLE:
begin
if(iRD_START)begin
state = L_PARAM_LOAD_REQ;
end
else begin
state = L_PARAM_IDLE;
end
end
L_PARAM_LOAD_REQ:
begin
if(!iLDST_BUSY)begin
state = L_PARAM_LOAD_ACK;
end
else begin
state = L_PARAM_LOAD_REQ;
end
end
L_PARAM_LOAD_ACK:
begin
//Get Check
if(iLDST_REQ)begin
state = L_PARAM_STORE_REQ;
end
else begin
state = L_PARAM_LOAD_ACK;
end
end
L_PARAM_STORE_REQ:
begin
if(!iLDST_BUSY)begin
state = L_PARAM_STORE_ACK;
end
else begin
state = L_PARAM_STORE_REQ;
end
end
L_PARAM_STORE_ACK:
begin
//Get Check
if(iLDST_REQ)begin
state = L_PARAM_IDLE;
end
else begin
state = L_PARAM_STORE_ACK;
end
end
default:
begin
state = L_PARAM_IDLE;
end
endcase
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= L_PARAM_IDLE;
end
else if(iRESET_SYNC)begin
b_state <= L_PARAM_IDLE;
end
else begin
b_state <= state;
end
end
reg b_finish;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_finish <= 1'b0;
end
else if(iRESET_SYNC)begin
b_finish <= 1'b0;
end
else begin
b_finish <= (state == L_PARAM_STORE_ACK) && iLDST_REQ;
end
end
/***************************************************************************
Load Data Buffer
***************************************************************************/
reg [31:0] b_load_data;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_load_data <= 32'h0;
end
else if(iRESET_SYNC)begin
b_load_data <= 32'h0;
end
else begin
if((state == L_PARAM_LOAD_ACK) && iLDST_REQ)begin
b_load_data <= iLDST_DATA;
end
end
end
/***************************************************************************
Load Store Pipe
***************************************************************************/
reg b_ldst_use;
reg b_ldst_req;
reg [31:0] b_ldst_data;
wire [31:0] uspr_addr = iSYSREG_TISR + {iSYSREG_TIDR[13:0], 8'h0} + `TST_USPR;
wire [31:0] kspr_addr = iSYSREG_TISR + {iSYSREG_TIDR[13:0], 8'h0} + `TST_KSPR;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_ldst_use <= 1'b0;
b_ldst_req <= 1'b0;
b_ldst_data <= 32'h0;
end
else if(iRESET_SYNC)begin
b_ldst_use <= 1'b0;
b_ldst_req <= 1'b0;
b_ldst_data <= 32'h0;
end
else begin
b_ldst_use <= state != L_PARAM_IDLE;
b_ldst_req <= state == L_PARAM_STORE_REQ || state == L_PARAM_LOAD_REQ;
b_ldst_data <= iSYSREG_SPR;
end
end
reg [31:0] b_ldst_addr;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_ldst_addr <= 32'h0;
end
else if(iRESET_SYNC)begin
b_ldst_addr <= 32'h0;
end
else begin
if(iRD_KERNEL)begin
if(state == L_PARAM_STORE_REQ)begin
b_ldst_addr <= uspr_addr;
end
else begin
b_ldst_addr <= kspr_addr;
end
end
else begin
if(state == L_PARAM_STORE_REQ)begin
b_ldst_addr <= kspr_addr;
end
else begin
b_ldst_addr <= uspr_addr;
end
end
end
end
/***************************************************************************
Assign
***************************************************************************/
assign oFINISH = b_finish;
assign oFINISH_SPR = b_load_data;
assign oLDST_USE = b_ldst_use;
assign oLDST_REQ = b_ldst_req;
assign oLDST_ORDER = 2'h2; //00=Byte Order 01=2Byte Order 10= Word Order 11= None
assign oLDST_RW = 1'b0; //0=Read 1=Write
assign oLDST_ASID = 14'h0;
assign oLDST_MMUMOD = 2'h0;
assign oLDST_PDT = 32'h0;
assign oLDST_ADDR = b_ldst_addr;
assign oLDST_DATA = b_ldst_data;
endmodule
`default_nettype wire |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSTP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__DFSTP_PP_BLACKBOX_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSTP_PP_BLACKBOX_V
|
module Arreglo_Torus (
input RST, // Reset maestro
input CLK, // Reloj maestro
input[3:0] A00,A01, // Coef Matriz A
input[3:0] A10,A11,
input[3:0] B00,B01, // Coef Matriz B
input[3:0] B10,B11,
input ENpH, // Habilitaciones Rp Alto
input ENpL, // Habilitaciones Rp Bajo
input ENa, // Habilitaciones Ra
input ENr, // Habilitaciones Rb
input SEL, // Selectores Mux
output[7:0] MTX00,MTX01,// Salida
output[7:0] MTX10,MTX11
);
wire[3:0] Aq00,Aq01,Aq10,Aq11;
wire[3:0] RaQ00,RaQ01,RaQ10,RaQ11;
wire[3:0] Ya00,Ya01,Ya10,Ya11;
wire[3:0] Bq00,Bq01,Bq10,Bq11;
wire[3:0] RbQ00,RbQ01,RbQ10,RbQ11;
wire[3:0] Yb00,Yb01,Yb10,Yb11;
Registro_4b Ra00(RST,CLK,ENpH,A01,Aq01);
Registro_4b RaM00(RST,CLK,ENpL,Aq00,RaQ01);
Mux4_2_1 MuxA00(Aq01,RaQ01,SEL,Ya00);
Registro_4b Rb00(RST,CLK,ENpH,B10,Bq10);
Registro_4b RbM00(RST,CLK,ENpL,Bq00,RbQ10);
Mux4_2_1 MuxB00(Bq10,RbQ10,SEL,Yb00);
MAC MAC00(RST,CLK,ENa,ENr,Ya00,Yb00,MTX00);
Registro_4b Ra01(RST,CLK,ENpH,A10,Aq10);
Registro_4b RaM01(RST,CLK,ENpL,Aq11,RaQ10);
Mux4_2_1 MuxA01(Aq10,RaQ10,SEL,Ya01);
Registro_4b Rb01(RST,CLK,ENpH,B00,Bq00);
Registro_4b RbM01(RST,CLK,ENpL,Bq10,RbQ00);
Mux4_2_1 MuxB01(Bq00,RbQ00,SEL,Yb01);
MAC MAC01(RST,CLK,ENa,ENr,Ya01,Yb01,MTX10);
Registro_4b Ra10(RST,CLK,ENpH,A00,Aq00);
Registro_4b RaM10(RST,CLK,ENpL,Aq01,RaQ00);
Mux4_2_1 MuxA10(Aq00,RaQ00,SEL,Ya10);
Registro_4b Rb10(RST,CLK,ENpH,B01,Bq01);
Registro_4b RbM10(RST,CLK,ENpL,Bq11,RbQ01);
Mux4_2_1 MuxB10(Bq01,RbQ01,SEL,Yb10);
MAC MAC10(RST,CLK,ENa,ENr,Ya10,Yb10,MTX01);
Registro_4b Ra11(RST,CLK,ENpH,A11,Aq11);
Registro_4b RaM11(RST,CLK,ENpL,Aq10,RaQ11);
Mux4_2_1 MuxA11(Aq11,RaQ11,SEL,Ya11);
Registro_4b Rb11(RST,CLK,ENpH,B11,Bq11);
Registro_4b RbM11(RST,CLK,ENpL,Bq01,RbQ11);
Mux4_2_1 MuxB11(Bq11,RbQ11,SEL,Yb11);
MAC MAC11(RST,CLK,ENa,ENr,Ya11,Yb11,MTX11);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX4_BLACKBOX_V
`define SKY130_FD_SC_MS__MUX4_BLACKBOX_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX4_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad9265_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dcfilter_data_out,
adc_valid,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter CHID = 0;
parameter DP_DISABLE = 0;
// adc interface
input adc_clk;
input adc_rst;
input [15:0] adc_data;
input adc_or;
// channel interface
output [15:0] adc_dcfilter_data_out;
output adc_valid;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire [15:0] adc_dfmt_data_s;
wire adc_dcfilt_enb_s;
wire adc_dfmt_se_s;
wire adc_dfmt_type_s;
wire adc_dfmt_enable_s;
wire [15:0] adc_dcfilt_offset_s;
wire [15:0] adc_dcfilt_coeff_s;
wire [ 3:0] adc_pnseq_sel_s;
wire adc_pn_err_s;
wire adc_pn_oos_s;
// iq correction inputs
axi_ad9265_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
generate
if (DP_DISABLE == 1) begin
assign adc_dfmt_data_s = adc_data;
end else begin
ad_datafmt #(.DATA_WIDTH(16)) i_ad_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data),
.valid_out (),
.data_out (adc_dfmt_data_s),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign adc_dcfilter_data_out = adc_dfmt_data_s;
end else begin
ad_dcfilter i_ad_dcfilter (
.clk (adc_clk),
.valid (1'b1),
.data (adc_dfmt_data_s),
.valid_out (adc_valid),
.data_out (adc_dcfilter_data_out),
.dcfilt_enb (adc_dcfilt_enb_s),
.dcfilt_coeff (adc_dcfilt_coeff_s),
.dcfilt_offset (adc_dcfilt_offset_s));
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (adc_dcfilt_enb_s),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dcfilt_offset (adc_dcfilt_offset_s),
.adc_dcfilt_coeff (adc_dcfilt_coeff_s),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo64_clock_crossing.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo64_clock_crossing (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdusedw,
wrfull);
input [63:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [63:0] q;
output [12:0] rdusedw;
output wrfull;
wire [63:0] sub_wire0;
wire [12:0] sub_wire1;
wire sub_wire2;
wire [63:0] q = sub_wire0[63:0];
wire [12:0] rdusedw = sub_wire1[12:0];
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdusedw (sub_wire1),
.wrfull (sub_wire2),
.aclr (),
.eccstatus (),
.rdempty (),
.rdfull (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.add_usedw_msb_bit = "ON",
dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 4096,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 64,
dcfifo_component.lpm_widthu = 13,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "64"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "1"
// Retrieval info: PRIVATE: output_width NUMERIC "64"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_USEDW_MSB_BIT STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 13 0 OUTPUT NODEFVAL "rdusedw[12..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: CONNECT: rdusedw 0 0 13 0 @rdusedw 0 0 13 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo64_clock_crossing.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo64_clock_crossing.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo64_clock_crossing.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo64_clock_crossing.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo64_clock_crossing_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo64_clock_crossing_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
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