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// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: Alok:user:sample_generator:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_sample_generator_0_1 (
FrameSize,
En,
AXI_En,
m_axis_tdata,
m_axis_tstrb,
m_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_aclk,
m_axis_aresetn,
s_axis_tdata,
s_axis_tstrb,
s_axis_tlast,
s_axis_tvalid,
s_axis_tready,
s_axis_aclk,
s_axis_aresetn
);
input wire [7 : 0] FrameSize;
input wire En;
input wire AXI_En;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [31 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TSTRB" *)
output wire [3 : 0] m_axis_tstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output wire m_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXIS_CLK CLK" *)
input wire m_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 M_AXIS_RST RST" *)
input wire m_axis_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input wire [31 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TSTRB" *)
input wire [3 : 0] s_axis_tstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input wire s_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input wire s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output wire s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXIS_CLK CLK" *)
input wire s_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_AXIS_RST RST" *)
input wire s_axis_aresetn;
sample_generator_v1_0 #(
.C_M_AXIS_TDATA_WIDTH(32), // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
.C_M_AXIS_START_COUNT(32), // Start count is the numeber of clock cycles the master will wait before initiating/issuing any transaction.
.C_S_AXIS_TDATA_WIDTH(32) // AXI4Stream sink: Data Width
) inst (
.FrameSize(FrameSize),
.En(En),
.AXI_En(AXI_En),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(m_axis_tstrb),
.m_axis_tlast(m_axis_tlast),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(s_axis_tstrb),
.s_axis_tlast(s_axis_tlast),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_aclk(s_axis_aclk),
.s_axis_aresetn(s_axis_aresetn)
);
endmodule
|
module test(
input rst,
input clk,
input a0,
input wr_n,
input [ 7:0] din,
output signed [15:0] xleft,
output signed [15:0] xright,
output sample,
output [ 7:0] dout
);
wire wr_n, cen_fm, cen_fm2;
wire a0;
wire [7:0] din, dout;
jtframe_cen3p57 u_cen(
.clk ( clk ), // 48 MHz
.cen_3p57 ( cen_fm ),
.cen_1p78 ( cen_fm2 )
);
wire ct1, ct2, irq_n;
jt51 uut(
.rst ( rst ), // reset
.clk ( clk ), // main clock
.cen ( cen_fm ), // clock enable
.cen_p1 ( cen_fm2 ), // clock enable at half the speed
.cs_n ( 1'b0 ), // chip select
.wr_n ( wr_n ), // write
.a0 ( a0 ),
.din ( din ), // data in
.dout ( dout ), // data out
// peripheral control
.ct1 ( ct1 ),
.ct2 ( ct2 ),
.irq_n ( irq_n ), // I do not synchronize this signal
// Low resolution output (same as real chip)
.sample ( sample ), // marks new output sample
.left ( ),
.right ( ),
// Full resolution output
.xleft ( xleft ),
.xright ( xright ),
// unsigned outputs for sigma delta converters, full resolution
.dacleft ( ),
.dacright ( )
);
endmodule
module jtframe_cen3p57(
input clk, // 48 MHz
output reg cen_3p57,
output reg cen_1p78
);
wire [10:0] step=11'd105;
wire [10:0] lim =11'd1408;
wire [10:0] absmax = lim+step;
reg [10:0] cencnt=11'd0;
reg [10:0] next;
reg [10:0] next2;
always @(*) begin
next = cencnt+11'd105;
next2 = next-lim;
end
reg alt=1'b0;
always @(posedge clk) begin
cen_3p57 <= 1'b0;
cen_1p78 <= 1'b0;
if( cencnt >= absmax ) begin
// something went wrong: restart
cencnt <= 11'd0;
alt <= 1'b0;
end else
if( next >= lim ) begin
cencnt <= next2;
cen_3p57 <= 1'b1;
alt <= ~alt;
if( alt ) cen_1p78 <= 1'b1;
end else begin
cencnt <= next;
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / DSP_PREADD
// /___/ /\ Filename : DSP_PREADD.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/15/12 - Migrate from E1.
// 12/10/12 - Add dynamic registers
// 01/11/13 - DIN, D_DATA data width change (26/24) sync4 yml
// 10/22/14 - 808642 - Added #1 to $finish
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DSP_PREADD
`ifdef XIL_TIMING
#(
parameter LOC = "UNPLACED"
)
`endif
(
output [26:0] AD,
input ADDSUB,
input [26:0] D_DATA,
input INMODE2,
input [26:0] PREADD_AB
);
// define constants
localparam MODULE_NAME = "DSP_PREADD";
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
`endif
`ifndef XIL_TIMING
initial begin
$display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME);
#1 $finish;
end
`endif
// begin behavioral model
wire [26:0] D_DATA_mux;
//*********************************************************
//*** Preaddsub AD
//*********************************************************
assign D_DATA_mux = INMODE2 ? D_DATA : 27'b0;
assign AD = ADDSUB ? (D_DATA_mux - PREADD_AB) : (D_DATA_mux + PREADD_AB);
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
specify
(ADDSUB *> AD) = (0:0:0, 0:0:0);
(D_DATA *> AD) = (0:0:0, 0:0:0);
(INMODE2 *> AD) = (0:0:0, 0:0:0);
(PREADD_AB *> AD) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
endmodule
`endcelldefine
|
//======================================================================
//
// rosc.v
// ------
// Digital ring oscillator used as entropy source. Based on the
// idea of using carry chain in adders as inverter by Bernd Paysan.
//
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module rosc #(parameter WIDTH = 2)
(
input wire clk,
input wire reset_n,
input wire we,
input wire [(WIDTH - 1) : 0] opa,
input wire [(WIDTH - 1) : 0] opb,
output wire dout
);
//----------------------------------------------------------------
// Registers.
//----------------------------------------------------------------
reg dout_reg;
reg dout_new;
//----------------------------------------------------------------
// Concurrent assignment.
//----------------------------------------------------------------
assign dout = dout_reg;
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
dout_reg <= 1'b0;
end
else
begin
if (we)
begin
dout_reg <= dout_new;
end
end
end
//----------------------------------------------------------------
// adder_osc
//
// Adder logic that generates the oscillator.
//
// NOTE: This logic contains a combinational loop and does
// not play well with an event driven simulator.
//----------------------------------------------------------------
always @*
begin: adder_osc
reg [WIDTH : 0] sum;
reg cin;
cin = ~sum[WIDTH];
sum = opa + opb + cin;
dout_new = sum[WIDTH];
end
endmodule // rosc
//======================================================================
// EOF rosc.v
//======================================================================
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: flop_rptrs_xc3.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module flop_rptrs_xc3(/*AUTOARG*/
// Outputs
sparc_out, so, jbussync2_out, jbussync1_out, grst_out,
gdbginit_out, ddrsync2_out, ddrsync1_out, cken_out,
// Inputs
spare_in, se, sd, jbussync2_in, jbussync1_in, grst_in,
gdbginit_in, gclk, ddrsync2_in, ddrsync1_in, cken_in, agrst_l,
adbginit_l
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [25:0] cken_out; // From cken_ff_25_ of bw_u1_soffasr_2x.v, ...
output ddrsync1_out; // From ddrsync1_ff of bw_u1_soffasr_2x.v
output ddrsync2_out; // From ddrsync2_ff of bw_u1_soffasr_2x.v
output gdbginit_out; // From gdbginit_ff of bw_u1_soffasr_2x.v
output grst_out; // From gclk_ff of bw_u1_soffasr_2x.v
output jbussync1_out; // From jbussync1_ff of bw_u1_soffasr_2x.v
output jbussync2_out; // From jbussync2_ff of bw_u1_soffasr_2x.v
output so; // From scanout_latch of bw_u1_scanlg_2x.v
output [5:0] sparc_out; // From spare_ff_5_ of bw_u1_soffasr_2x.v, ...
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l; // To gdbginit_ff of bw_u1_soffasr_2x.v
input agrst_l; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
input [25:0] cken_in; // To cken_ff_25_ of bw_u1_soffasr_2x.v, ...
input ddrsync1_in; // To ddrsync1_ff of bw_u1_soffasr_2x.v
input ddrsync2_in; // To ddrsync2_ff of bw_u1_soffasr_2x.v
input gclk; // To I73 of bw_u1_ckbuf_33x.v
input gdbginit_in; // To gdbginit_ff of bw_u1_soffasr_2x.v
input grst_in; // To gclk_ff of bw_u1_soffasr_2x.v
input jbussync1_in; // To jbussync1_ff of bw_u1_soffasr_2x.v
input jbussync2_in; // To jbussync2_ff of bw_u1_soffasr_2x.v
input sd; // To spare_ff_5_ of bw_u1_soffasr_2x.v
input se; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
input [5:0] spare_in; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire clk; // From I73 of bw_u1_ckbuf_33x.v
wire scan_data_0; // From spare_ff_5_ of bw_u1_soffasr_2x.v
wire scan_data_1; // From spare_ff_4_ of bw_u1_soffasr_2x.v
wire scan_data_10; // From gdbginit_ff of bw_u1_soffasr_2x.v
wire scan_data_11; // From gclk_ff of bw_u1_soffasr_2x.v
wire scan_data_2; // From spare_ff_3_ of bw_u1_soffasr_2x.v
wire scan_data_3; // From spare_ff_2_ of bw_u1_soffasr_2x.v
wire scan_data_4; // From spare_ff_1_ of bw_u1_soffasr_2x.v
wire scan_data_5; // From spare_ff_0_ of bw_u1_soffasr_2x.v
wire scan_data_6; // From jbussync2_ff of bw_u1_soffasr_2x.v
wire scan_data_7; // From jbussync1_ff of bw_u1_soffasr_2x.v
wire scan_data_8; // From ddrsync2_ff of bw_u1_soffasr_2x.v
wire scan_data_9; // From ddrsync1_ff of bw_u1_soffasr_2x.v
// End of automatics
/* bw_u1_ckbuf_33x AUTO_TEMPLATE (
.clk (clk ),
.rclk (gclk ) ); */
bw_u1_ckbuf_33x I73
(/*AUTOINST*/
// Outputs
.clk (clk ), // Templated
// Inputs
.rclk (gclk )); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.q (sparc_out[@]),
.d (spare_in[@]),
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.sd (scan_data_@"(- 4 @)" ),
.so (scan_data_@"(- 5 @)" ),
); */
bw_u1_soffasr_2x spare_ff_5_
(
// Inputs
.sd (sd ),
/*AUTOINST*/
// Outputs
.q (sparc_out[5]), // Templated
.so (scan_data_0 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[5]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se));
bw_u1_soffasr_2x spare_ff_4_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[4]), // Templated
.so (scan_data_1 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[4]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_0 )); // Templated
bw_u1_soffasr_2x spare_ff_3_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[3]), // Templated
.so (scan_data_2 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[3]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_1 )); // Templated
bw_u1_soffasr_2x spare_ff_2_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[2]), // Templated
.so (scan_data_3 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[2]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_2 )); // Templated
bw_u1_soffasr_2x spare_ff_1_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[1]), // Templated
.so (scan_data_4 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[1]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_3 )); // Templated
bw_u1_soffasr_2x spare_ff_0_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[0]), // Templated
.so (scan_data_5 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[0]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_4 )); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.q (cken_out[@] ),
.d (cken_in[@] ),
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.se (1'b0),
.sd (1'b0),
.so (),
); */
bw_u1_soffasr_2x cken_ff_25_
( /*AUTOINST*/
// Outputs
.q (cken_out[25] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[25] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_24_
( /*AUTOINST*/
// Outputs
.q (cken_out[24] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[24] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_23_
( /*AUTOINST*/
// Outputs
.q (cken_out[23] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[23] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_22_
( /*AUTOINST*/
// Outputs
.q (cken_out[22] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[22] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_21_
( /*AUTOINST*/
// Outputs
.q (cken_out[21] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[21] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_20_
( /*AUTOINST*/
// Outputs
.q (cken_out[20] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[20] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_19_
( /*AUTOINST*/
// Outputs
.q (cken_out[19] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[19] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_18_
( /*AUTOINST*/
// Outputs
.q (cken_out[18] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[18] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_17_
( /*AUTOINST*/
// Outputs
.q (cken_out[17] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[17] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_16_
( /*AUTOINST*/
// Outputs
.q (cken_out[16] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[16] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_15_
( /*AUTOINST*/
// Outputs
.q (cken_out[15] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[15] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_14_
( /*AUTOINST*/
// Outputs
.q (cken_out[14] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[14] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_13_
( /*AUTOINST*/
// Outputs
.q (cken_out[13] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[13] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_12_
( /*AUTOINST*/
// Outputs
.q (cken_out[12] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[12] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_11_
( /*AUTOINST*/
// Outputs
.q (cken_out[11] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[11] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_10_
( /*AUTOINST*/
// Outputs
.q (cken_out[10] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[10] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_9_
( /*AUTOINST*/
// Outputs
.q (cken_out[9] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[9] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_8_
( /*AUTOINST*/
// Outputs
.q (cken_out[8] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[8] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_7_
( /*AUTOINST*/
// Outputs
.q (cken_out[7] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[7] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_6_
( /*AUTOINST*/
// Outputs
.q (cken_out[6] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[6] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_5_
( /*AUTOINST*/
// Outputs
.q (cken_out[5] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[5] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_4_
( /*AUTOINST*/
// Outputs
.q (cken_out[4] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[4] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_3_
( /*AUTOINST*/
// Outputs
.q (cken_out[3] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[3] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_2_
( /*AUTOINST*/
// Outputs
.q (cken_out[2] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[2] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_1_
( /*AUTOINST*/
// Outputs
.q (cken_out[1] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[1] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_0_
( /*AUTOINST*/
// Outputs
.q (cken_out[0] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[0] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.se (se ),
); */
bw_u1_soffasr_2x ddrsync1_ff
(
// Outputs
.q (ddrsync1_out ),
.so (scan_data_9 ),
// Inputs
.d (ddrsync1_in ),
.sd (scan_data_8 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x ddrsync2_ff
(
// Outputs
.q (ddrsync2_out ),
.so (scan_data_8 ),
// Inputs
.d (ddrsync2_in ),
.sd (scan_data_7 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x jbussync1_ff
(
// Outputs
.q (jbussync1_out ),
.so (scan_data_7 ),
// Inputs
.d (jbussync1_in ),
.sd (scan_data_6 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x jbussync2_ff
(
// Outputs
.q (jbussync2_out ),
.so (scan_data_6 ),
// Inputs
.d (jbussync2_in ),
.sd (scan_data_5 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x gdbginit_ff
(
// Outputs
.q (gdbginit_out ),
.so (scan_data_10 ),
// Inputs
.d (gdbginit_in ),
.sd (scan_data_9 ),
.r_l (adbginit_l),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x gclk_ff
(
// Outputs
.q (grst_out ),
.so (scan_data_11 ),
// Inputs
.d (grst_in ),
.sd (scan_data_10 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
/* bw_u1_scanlg_2x AUTO_TEMPLATE (
.sd (scan_data_11 ),
.ck (clk ),
); */
bw_u1_scanlg_2x scanout_latch
( /*AUTOINST*/
// Outputs
.so (so),
// Inputs
.sd (scan_data_11 ), // Templated
.ck (clk ), // Templated
.se (1'b1));
endmodule
// Local Variables:
// verilog-library-files:("../../../common/rtl/u1.behV" )
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_1_V
`define SKY130_FD_SC_LS__FILL_1_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_1_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rxc_engine_classic.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The RXC Engine (Ultrascale) takes a single stream of
// AXI packets and provides the completion packets on the RXC Interface.
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
`include "ultrascale.vh"
module rxc_engine_ultrascale
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH=10,
// Number of data pipeline registers for metadata and data stages
parameter C_RX_META_STAGES = 0,
parameter C_RX_DATA_STAGES = 1)
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RXC_RST,
// Interface: RC
input M_AXIS_RC_TVALID,
input M_AXIS_RC_TLAST,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RC_TDATA,
input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_RC_TKEEP,
input [`SIG_RC_TUSER_W-1:0] M_AXIS_RC_TUSER,
output M_AXIS_RC_TREADY,
// Interface: RXC Engine
output [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
output RXC_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
output RXC_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
output RXC_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
output [`SIG_LBE_W-1:0] RXC_META_LDWBE,
output [`SIG_FBE_W-1:0] RXC_META_FDWBE,
output [`SIG_TAG_W-1:0] RXC_META_TAG,
output [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
output [`SIG_TYPE_W-1:0] RXC_META_TYPE,
output [`SIG_LEN_W-1:0] RXC_META_LENGTH,
output [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
output [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
output RXC_META_EP
);
`include "functions.vh"
// Width of the Byte Enable Shift register
localparam C_RX_BE_W = (`SIG_FBE_W + `SIG_LBE_W);
localparam C_RX_INPUT_STAGES = 0;
localparam C_RX_OUTPUT_STAGES = 2; // Should always be at least one
localparam C_RX_COMPUTATION_STAGES = 1;
localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
// CYCLE = LOW ORDER BIT (INDEX) / C_PCI_DATA_WIDTH
localparam C_RX_METADW0_CYCLE = (`UPKT_RXC_METADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW1_CYCLE = (`UPKT_RXC_METADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW2_CYCLE = (`UPKT_RXC_METADW2_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_PAYLOAD_CYCLE = (`UPKT_RXC_PAYLOAD_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_BE_CYCLE = C_RX_INPUT_STAGES; // Available on the first cycle (as per the spec)
localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXC_METADW0_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXC_METADW1_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW2_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXC_METADW2_I%C_PCI_DATA_WIDTH);
localparam C_RX_BE_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES;
// Mask width of the calculated SOF/EOF fields
localparam C_OFFSET_WIDTH = clog2(C_PCI_DATA_WIDTH/32);
wire wMAxisRcSop;
wire wMAxisRcTlast;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrSop;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrEop;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrDataValid;
wire [(C_RX_PIPELINE_DEPTH+1)*C_RX_BE_W-1:0] wRxSrBe;
wire [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] wRxSrData;
wire wRxcDataValid;
wire wRxcDataReady; // Pinned High
wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataWordEnable;
wire wRxcDataEndFlag;
wire [clog2(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataEndOffset;
wire wRxcDataStartFlag;
wire [clog2(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataStartOffset;
wire [`SIG_BYTECNT_W-1:0] wRxcMetaBytesRemaining;
wire [`SIG_CPLID_W-1:0] wRxcMetaCompleterId;
wire [`UPKT_RXC_MAXHDR_W-1:0] wRxcHdr;
wire [`SIG_TYPE_W-1:0] wRxcType;
wire [`SIG_BARDECODE_W-1:0] wRxcBarDecoded;
wire [`UPKT_RXC_MAXHDR_W-1:0] wHdr;
wire [`SIG_TYPE_W-1:0] wType;
wire wHasPayload;
wire _wEndFlag;
wire wEndFlag;
wire wEndFlagLastCycle;
wire [clog2(C_PCI_DATA_WIDTH/32)-1:0] wEndOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wEndMask;
wire _wStartFlag;
wire wStartFlag;
wire [1:0] wStartFlags;
wire [clog2(C_PCI_DATA_WIDTH/32)-1:0] wStartOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wStartMask;
wire [C_OFFSET_WIDTH-1:0] wOffsetMask;
reg rValid,_rValid;
reg rRST;
assign DONE_RXC_RST = ~rRST;
assign wMAxisRcSop = M_AXIS_RC_TUSER[`UPKT_RC_TUSER_SOP_I];
assign wMAxisRcTlast = M_AXIS_RC_TLAST;
// We assert the end flag on the last cycle of a packet, however on single
// cycle packets we need to check that there wasn't an end flag last cycle
// (because wStartFlag will take priority when setting rValid) so we can
// deassert rValid if necessary.
assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES];
assign wEndFlagLastCycle = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES + 1];
/* verilator lint_off WIDTH */
assign wStartOffset = 3;
assign wEndOffset = wHdr[`UPKT_RXC_LENGTH_I +: C_OFFSET_WIDTH] + ((`UPKT_RXC_MAXHDR_W-32)/32);
/* verilator lint_on WIDTH */
// Output assignments. See the header file derived from the user
// guide for indices.
assign RXC_META_LENGTH = wRxcHdr[`UPKT_RXC_LENGTH_I+:`SIG_LEN_W];
//assign RXC_META_ATTR = wRxcHdr[`UPKT_RXC_ATTR_R];
//assign RXC_META_TC = wRxcHdr[`UPKT_RXC_TC_R];
assign RXC_META_TAG = wRxcHdr[`UPKT_RXC_TAG_R];
assign RXC_META_FDWBE = 0;// TODO: Remove (use addr)
assign RXC_META_LDWBE = 0;// TODO: Remove (use addr)
assign RXC_META_ADDR = wRxcHdr[(`UPKT_RXC_ADDRLOW_I) +: `SIG_LOWADDR_W];
assign RXC_DATA_START_FLAG = wRxcDataStartFlag;
assign RXC_DATA_START_OFFSET = {C_PCI_DATA_WIDTH > 64, 1'b1};
assign RXC_DATA_END_FLAG = wRxcDataEndFlag;
assign RXC_DATA_END_OFFSET = wRxcDataEndOffset;
assign RXC_DATA_VALID = wRxcDataValid;
assign RXC_DATA = wRxSrData[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
assign RXC_META_TYPE = wRxcType;
assign RXC_META_BYTES_REMAINING = wRxcHdr[`UPKT_RXC_BYTECNT_I +: `SIG_BYTECNT_W];
assign RXC_META_COMPLETER_ID = wRxcHdr[`UPKT_RXC_CPLID_R];
assign RXC_META_EP = wRxcHdr[`UPKT_RXC_EP_R];
assign M_AXIS_RC_TREADY = 1'b1;
assign _wEndFlag = wRxSrEop[C_RX_INPUT_STAGES];
assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES+1];
assign _wStartFlag = wStartFlags != 0;
assign wType = (wHasPayload)? `TRLS_CPL_WD: `TRLS_CPL_ND;
generate
if(C_PCI_DATA_WIDTH == 64) begin
assign wStartFlags[0] = 0;
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1];
//assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wRxSrEop[C_RX_INPUT_STAGES]; // No Payload
end else if (C_PCI_DATA_WIDTH == 128) begin
assign wStartFlags[1] = 0;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
end else begin // 256
assign wStartFlags[1] = 0;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
end // else: !if(C_PCI_DATA_WIDTH == 128)
endgenerate
always @(*) begin
_rValid = rValid;
if(_wStartFlag) begin
_rValid = 1'b1;
end else if (wEndFlag) begin
_rValid = 1'b0;
end
end
always @(posedge CLK) begin
if(rRST) begin
rValid <= 1'b0;
end else begin
rValid <= _rValid;
end
end
always @(posedge CLK) begin
rRST <= RST_BUS | RST_LOGIC;
end
register
#(// Parameters
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
start_flag_register
(// Outputs
.RD_DATA (wStartFlag),
// Inputs
.WR_DATA (_wStartFlag),
.WR_EN (1),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
meta_DW2_register
(// Outputs
.RD_DATA (wHdr[95:64]),
// Inputs
.WR_DATA (wRxSrData[C_RX_METADW2_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW2_CYCLE]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32 + 1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
meta_DW1_register
(// Outputs
.RD_DATA ({wHdr[63:32],wHasPayload}),
// Inputs
.WR_DATA ({wRxSrData[C_RX_METADW1_INDEX +: 32],
wRxSrData[C_RX_METADW1_INDEX +: `UPKT_LEN_W] != 0}),
.WR_EN (wRxSrSop[C_RX_METADW1_CYCLE]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_DW0_register
(// Outputs
.RD_DATA (wHdr[31:0]),
// Inputs
.WR_DATA (wRxSrData[C_RX_METADW0_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW0_CYCLE]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// Shift register for input data with output taps for each delayed
// cycle.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (C_PCI_DATA_WIDTH),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
data_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrData),
// Inputs
.WR_DATA (M_AXIS_RC_TDATA),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// Start Flag Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
sop_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrSop),
// Inputs
.WR_DATA (wMAxisRcSop & M_AXIS_RC_TVALID),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// End Flag Shift Register.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
eop_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrEop),
// Inputs
.WR_DATA (wMAxisRcTlast),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// Data Valid Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
valid_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrDataValid),
// Inputs
.WR_DATA (M_AXIS_RC_TVALID),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
o2m_ef
(// Outputs
.MASK (wEndMask),
// Inputs
.OFFSET_ENABLE (wEndFlag),
.OFFSET (wEndOffset)
/*AUTOINST*/);
generate
if(C_RX_OUTPUT_STAGES == 0) begin
assign RXC_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | ~wHasPayload}};
end else begin
register
#(// Parameters
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
dw_enable
(// Outputs
.RD_DATA (wRxcDataWordEnable),
// Inputs
.RST_IN (~rValid | ~wHasPayload),
.WR_DATA (wEndMask & wStartMask),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES-1),
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
dw_pipeline
(// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA (RXC_DATA_WORD_ENABLE),
.RD_DATA_VALID (),
// Inputs
.WR_DATA (wRxcDataWordEnable),
.WR_DATA_VALID (1),
.RD_DATA_READY (1'b1),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
end
endgenerate
// Shift register for input data with output taps for each delayed
// cycle.
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES),
.C_WIDTH (`UPKT_RXC_MAXHDR_W +
2*(1 + clog2(C_PCI_DATA_WIDTH/32))+`SIG_TYPE_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_pipeline
(
// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA ({wRxcHdr, wRxcDataStartFlag,
wRxcDataStartOffset,wRxcDataEndFlag,
wRxcDataEndOffset,wRxcType}),
.RD_DATA_VALID (wRxcDataValid),
// Inputs
.WR_DATA ({wHdr,wStartFlag,
wStartOffset[C_OFFSET_WIDTH-1:0],
wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0],wType}),
.WR_DATA_VALID (rValid),
.RD_DATA_READY (1'b1),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/")
// End:
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
// No shared code for this OVL
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is FALSE");
end
end
end
assign fire_2state_1 = (test_expr == 1'b0);
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
end
wire valid_test_expr = ((test_expr ^ test_expr) == 1'b0);
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
// No coverage for this OVL
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module user_logic (
pid,
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_data_or_p,
adc_data_or_n,
spi_cs0n,
spi_cs1n,
spi_clk,
spi_sd_o,
spi_sd_i,
dma_clk,
dma_valid,
dma_data,
dma_be,
dma_last,
dma_ready,
delay_clk,
up_status,
up_adc_capture_int,
up_adc_capture_ext,
dma_dbg_data,
dma_dbg_trigger,
adc_clk,
adc_dbg_data,
adc_dbg_trigger,
adc_mon_valid,
adc_mon_data,
Bus2IP_Clk,
Bus2IP_Resetn,
Bus2IP_Data,
Bus2IP_BE,
Bus2IP_RdCE,
Bus2IP_WrCE,
IP2Bus_Data,
IP2Bus_RdAck,
IP2Bus_WrAck,
IP2Bus_Error);
parameter C_NUM_REG = 32;
parameter C_SLV_DWIDTH = 32;
parameter C_CF_BUFTYPE = 0;
parameter C_IODELAY_GROUP = "adc_if_delay_group";
input [ 7:0] pid;
input adc_clk_in_p;
input adc_clk_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
input adc_data_or_p;
input adc_data_or_n;
output spi_cs0n;
output spi_cs1n;
output spi_clk;
output spi_sd_o;
input spi_sd_i;
input dma_clk;
output dma_valid;
output [63:0] dma_data;
output [ 7:0] dma_be;
output dma_last;
input dma_ready;
input delay_clk;
output [ 7:0] up_status;
output up_adc_capture_int;
input up_adc_capture_ext;
output [63:0] dma_dbg_data;
output [ 7:0] dma_dbg_trigger;
output adc_clk;
output [63:0] adc_dbg_data;
output [ 7:0] adc_dbg_trigger;
output adc_mon_valid;
output [31:0] adc_mon_data;
input Bus2IP_Clk;
input Bus2IP_Resetn;
input [31:0] Bus2IP_Data;
input [ 3:0] Bus2IP_BE;
input [31:0] Bus2IP_RdCE;
input [31:0] Bus2IP_WrCE;
output [31:0] IP2Bus_Data;
output IP2Bus_RdAck;
output IP2Bus_WrAck;
output IP2Bus_Error;
reg up_sel = 'd0;
reg up_rwn = 'd0;
reg [ 4:0] up_addr = 'd0;
reg [31:0] up_wdata = 'd0;
reg IP2Bus_RdAck = 'd0;
reg IP2Bus_WrAck = 'd0;
reg [31:0] IP2Bus_Data = 'd0;
reg IP2Bus_Error = 'd0;
wire [31:0] up_rwce_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
assign up_rwce_s = (Bus2IP_RdCE == 0) ? Bus2IP_WrCE : Bus2IP_RdCE;
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
up_sel <= 'd0;
up_rwn <= 'd0;
up_addr <= 'd0;
up_wdata <= 'd0;
end else begin
up_sel <= (up_rwce_s == 0) ? 1'b0 : 1'b1;
up_rwn <= (Bus2IP_RdCE == 0) ? 1'b0 : 1'b1;
case (up_rwce_s)
32'h80000000: up_addr <= 5'h00;
32'h40000000: up_addr <= 5'h01;
32'h20000000: up_addr <= 5'h02;
32'h10000000: up_addr <= 5'h03;
32'h08000000: up_addr <= 5'h04;
32'h04000000: up_addr <= 5'h05;
32'h02000000: up_addr <= 5'h06;
32'h01000000: up_addr <= 5'h07;
32'h00800000: up_addr <= 5'h08;
32'h00400000: up_addr <= 5'h09;
32'h00200000: up_addr <= 5'h0a;
32'h00100000: up_addr <= 5'h0b;
32'h00080000: up_addr <= 5'h0c;
32'h00040000: up_addr <= 5'h0d;
32'h00020000: up_addr <= 5'h0e;
32'h00010000: up_addr <= 5'h0f;
32'h00008000: up_addr <= 5'h10;
32'h00004000: up_addr <= 5'h11;
32'h00002000: up_addr <= 5'h12;
32'h00001000: up_addr <= 5'h13;
32'h00000800: up_addr <= 5'h14;
32'h00000400: up_addr <= 5'h15;
32'h00000200: up_addr <= 5'h16;
32'h00000100: up_addr <= 5'h17;
32'h00000080: up_addr <= 5'h18;
32'h00000040: up_addr <= 5'h19;
32'h00000020: up_addr <= 5'h1a;
32'h00000010: up_addr <= 5'h1b;
32'h00000008: up_addr <= 5'h1c;
32'h00000004: up_addr <= 5'h1d;
32'h00000002: up_addr <= 5'h1e;
32'h00000001: up_addr <= 5'h1f;
default: up_addr <= 5'h1f;
endcase
up_wdata <= Bus2IP_Data;
end
end
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
IP2Bus_RdAck <= 'd0;
IP2Bus_WrAck <= 'd0;
IP2Bus_Data <= 'd0;
IP2Bus_Error <= 'd0;
end else begin
IP2Bus_RdAck <= (Bus2IP_RdCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_WrAck <= (Bus2IP_WrCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_Data <= up_rdata_s;
IP2Bus_Error <= 'd0;
end
end
assign spi_cs0n = 1'b1;
assign spi_cs1n = 1'b1;
assign spi_clk = 1'b0;
assign spi_sd_o = 1'b0;
cf_adc_2c #(.C_CF_BUFTYPE(C_CF_BUFTYPE), .C_IODELAY_GROUP(C_IODELAY_GROUP)) i_adc_2c (
.pid (pid),
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_or_p (adc_data_or_p),
.adc_data_or_n (adc_data_or_n),
.dma_clk (dma_clk),
.dma_valid (dma_valid),
.dma_data (dma_data),
.dma_be (dma_be),
.dma_last (dma_last),
.dma_ready (dma_ready),
.up_rstn (Bus2IP_Resetn),
.up_clk (Bus2IP_Clk),
.up_sel (up_sel),
.up_rwn (up_rwn),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s),
.up_status (up_status),
.up_adc_capture_int (up_adc_capture_int),
.up_adc_capture_ext (up_adc_capture_ext),
.delay_clk (delay_clk),
.dma_dbg_data (dma_dbg_data),
.dma_dbg_trigger (dma_dbg_trigger),
.adc_clk (adc_clk),
.adc_dbg_data (adc_dbg_data),
.adc_dbg_trigger (adc_dbg_trigger),
.adc_mon_valid (adc_mon_valid),
.adc_mon_data (adc_mon_data));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 2-11-2018
Based on information posted by Nemesis on:
http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc&start=167
Based on jt51_phasegen.v, from JT51
*/
module jt12_pg_sum (
input [ 3:0] mul,
input [19:0] phase_in,
input pg_rst,
input signed [5:0] detune_signed,
input [16:0] phinc_pure,
output reg [19:0] phase_out,
output reg [ 9:0] phase_op
);
reg [16:0] phinc_premul;
reg [19:0] phinc_mul;
always @(*) begin
phinc_premul = phinc_pure + {{11{detune_signed[5]}},detune_signed};
phinc_mul = ( mul==4'd0 ) ? {4'b0,phinc_premul[16:1]} : ({3'd0,phinc_premul} * mul);
phase_out = pg_rst ? 20'd0 : (phase_in + { phinc_mul});
phase_op = phase_out[19:10];
end
endmodule // jt12_pg_sum |
// Displays a Mandelbrot set on VGA output
module MandelbrotFPGA(CLOCK_27, CLOCK_50, KEY, SW, VGA_CLK,
VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC,
VGA_R, VGA_G, VGA_B, LEDG, LEDR);
input CLOCK_27; // 27 MHz
input CLOCK_50; // 50 MHz
input [3:0] KEY; // Pushbutton[3:0]
input [17:0] SW; // Toggle Switch[17:0]
output [8:0] LEDG; // LED Green[8:0]
output [17:0] LEDR; // LED Red[17:0]
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK;// VGA BLANK
output VGA_SYNC; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
wire VGA_CTRL_CLK;
wire AUD_CTRL_CLK;
wire [9:0] mVGA_R;
wire [9:0] mVGA_G;
wire [9:0] mVGA_B;
wire [9:0] mVGA_X;
wire [9:0] mVGA_Y;
wire DLY_RST;
Reset_Delay r0 (.iCLK(CLOCK_50), .oRESET(DLY_RST));
VGA_Audio_PLL p1 (.areset(~DLY_RST),.inclk0(CLOCK_27),.c0(VGA_CTRL_CLK),.c2(VGA_CLK));
VGA_Controller u1 ( // Host Side
.iCursor_RGB_EN(4'h7),
.oCoord_X(mVGA_X),
.oCoord_Y(mVGA_Y),
.iRed(mVGA_R),
.iGreen(mVGA_G),
.iBlue(mVGA_B),
// VGA Side
.oVGA_R(VGA_R),
.oVGA_G(VGA_G),
.oVGA_B(VGA_B),
.oVGA_H_SYNC(VGA_HS),
.oVGA_V_SYNC(VGA_VS),
.oVGA_SYNC(VGA_SYNC),
.oVGA_BLANK(VGA_BLANK),
// Control Signal
.iCLK(VGA_CTRL_CLK),
.iRST_N(DLY_RST) );
pattern u2 (mVGA_R, mVGA_G, mVGA_B, mVGA_X, mVGA_Y, VGA_CLK, DLY_RST, SW, KEY);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S18_2_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S18_2_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog wrapper for clkdlybuf4s18 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkdlybuf4s18.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s18_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkdlybuf4s18 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s18_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkdlybuf4s18 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S18_2_V
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the ALU
// Import the modules that will be tested for in this testbench
`include "jpdt.v"
`include "control.h"
// IMPORTANT: To run this, try: ncverilog -f alu.f +gui
module tb_alu();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the ALU
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// result output signal
wire [0:127] res;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// reg_A
reg [0:127] r_A;
// reg_B
reg [0:127] r_B;
// Control signal bits - ww; ctrl_ww
reg [0:1] c_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform; alu_op
*/
reg [0:4] a_op;
// Bus/Signal to contain the expected output/result
reg [0:127] e_r;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Instantiate an instance of alu() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
alu a_l_u (
// instance_name(signal name),
// Signal name can be the same as the instance name
// alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result)
r_A,r_B,c_ww,a_op,res);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// aluwmuleu AND w8
/*
r_A=31'h0402050f;
r_B=31'h0301020c;
e_r=31'h000c0006;
c_ww=`w8;
a_op=`aluwmuleu;
*/
r_A=128'h0402030405060708f00a0b0cff0eff00;
r_B=128'h03010202030303031004f505ff09fe10;
e_r=128'h000c0006000f00150f000a87fe01fd02;
c_ww=`w8;
a_op=`aluwmuleu;
#10
// aluwmuleu AND w16
r_A=128'h000100020000ffff000f10bff103ffff;
r_B=128'h000200040006ffff000c100000120014;
e_r=128'h0000000200000000000000b40010f236;
c_ww=`w16;
a_op=`aluwmuleu;
// ======================================
#10
// aluwmulou AND w8
r_A=128'h0102030405060708090aff0c0dff0fff;
r_B=128'h01010202030303031004040508000fff;
e_r=128'h00020008001200180028003c0000fe01;
c_ww=`w8;
a_op=`aluwmulou;
#10
// aluwmulou AND w16
r_A=128'h0001000200000008000f10bff103ffff;
r_B=128'h0002000400060008000c001000120014;
e_r=128'h000000080000004000010bf00013ffec;
c_ww=`w16;
a_op=`aluwmulou;
// ======================================
#10
// aluwmulos AND w8
/*
r_A=128'h010330405060708090aff0c0dff0ff02;
r_B=128'h01fa0202030303031004040508000f08;
*/
r_A=128'h0180010501f9015301040100013c0100;
r_B=128'h017f010901fa010001fd01f101b80100;
e_r=128'hc080002d002a0000fff40000ef200000;
c_ww=`w8;
a_op=`aluwmulos;
#10
// aluwmulos AND w16
r_A=128'h1111000211118000111120541111fff9;
r_B=128'hffff0004ffff7fffffff0000fffffffd;
e_r=128'h00000008c00080000000000000000015;
c_ww=`w16;
a_op=`aluwmulos;
// ======================================
#10
// aluwmules AND w8
/*
r_A=128'h0180010501f9015301040100013c0100;
r_B=128'h017f010901fa010001fd01f101b80100;
*/
r_A=128'h80010501f9015301040100013c010001;
r_B=128'h7f010901fa010001fd01f101b8010001;
e_r=128'hc080002d002a0000fff40000ef200000;
c_ww=`w8;
a_op=`aluwmules;
#10
// aluwmules AND w16
/*
r_A=128'h1111000211118000111120541111fff9;
r_B=128'hffff0004ffff7fffffff0000fffffffd;
*/
r_A=128'h000211118000111120541111fff91111;
r_B=128'h0004ffff7fffffff0000fffffffdffff;
e_r=128'h00000008c00080000000000000000015;
c_ww=`w16;
a_op=`aluwmules;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__A21O_BEHAVIORAL_PP_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21O_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DLATCH_PR_BLACKBOX_V
`define SKY130_FD_SC_MS__UDP_DLATCH_PR_BLACKBOX_V
/**
* udp_dlatch$PR: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dlatch$PR (
Q ,
D ,
GATE ,
RESET
);
output Q ;
input D ;
input GATE ;
input RESET;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DLATCH_PR_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTP_4_V
`define SKY130_FD_SC_LP__DLRTP_4_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTP_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BA_1_V
`define SKY130_FD_SC_HS__O21BA_1_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21ba_1 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
sky130_fd_sc_hs__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21ba_1 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BA_1_V
|
// Code your design here
module main();
reg [31:0] x, y, newx;
reg real alpha [0:15];
reg real powers [0:16];
reg real currangle, x_out, y_out;
integer i;
reg real AG_CONST, AG;
initial begin
AG_CONST = 1.20;///0.6072529350;
AG = 2458;
x = AG;
y = 0;
alpha[0] = 0;
alpha[1] = 31.47292;
alpha[2] = 14.63407;
alpha[3] = 7.19962;
alpha[4] = 3.58565;
alpha[5] = 1.79107;
alpha[6] = 0.89531;
alpha[7] = 0.44763;
alpha[8] = 0.22381;
alpha[9] = 0.11190;
alpha[10] = 0.05595;
alpha[11] = 0.02797;
alpha[12] = 0.01398;
alpha[13] = 0.00699;
alpha[14] = 0.00349;
alpha[15] = 0.00174;
powers[0] = 0.00048828125; //2^-11
powers[1] = 0.0009765625; //2^-10
powers[2] = 0.001953125; //2^-9
powers[3] = 0.00390625; //2^-8
powers[4] = 0.0078125; //2^-7
powers[5] = 0.015625; //2^-6
powers[6] = 0.03125; //2^-5
powers[7] = 0.0625; //2^-4
powers[8] = 0.125; //2^-3
powers[9] = 0.25; //2^-2
powers[10] = 0.5; //2^-1
powers[11] = 1.0;
powers[12] = 2.0;
powers[13] = 4.0;
powers[14] = 8.0;
powers[15] = 16.0;
powers[16] = 32.0;
currangle = 90.0;
for (i = 1; i < 15; i = i + 1) begin
if (currangle > 0) begin
while(currangle >= alpha[i]) begin
newx = x + (y>>i);
y = y+ (x >> i);
x = newx;
currangle = currangle - alpha[i];
end
end else begin
while(currangle <= alpha[i]) begin
newx = x - (y>>i);
y = y- (x >> i);
x = newx;
currangle = currangle + alpha[i];
end
end
end
$display("x %f\n", x/2048.0);
$display("y %f\n", y/2048.0);
x_out = 0;
y_out = 0;
for (i = 0; i < 17; i = i + 1) begin
x_out = (x[i]) ? x_out + powers[i] : x_out;
y_out = (y[i]) ? y_out + powers[i] : y_out;
end
$display("x %f\n", x_out);
$display("y %f\n", y_out);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_P_PP_PG_N_TB_V
`define SKY130_FD_SC_LS__UDP_DFF_P_PP_PG_N_TB_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 NOTIFIER = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 NOTIFIER = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 NOTIFIER = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 NOTIFIER = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dut (.D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_P_PP_PG_N_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SRSDFXTP_BEHAVIORAL_V
/**
* srsdfxtp: Scan flop with sleep mode, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`include "../../models/udp_dff_p_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_p_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__srsdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SLEEP_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SLEEP_B;
// Module supplies
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire pwrgood_pp0_out_Q;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$P_pp$PKG$sN dff0 (buf_Q , mux_out, CLK_delayed, SLEEP_B, notifier, KAPWR, VGND, VPWR);
assign awake = ( SLEEP_B === 1'b0 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Q, buf_Q, VPWR, VGND );
buf buf0 (Q , pwrgood_pp0_out_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFXTP_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:55:30 03/10/2014
// Design Name:
// Module Name: Frequency
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Nonoverlapping_template(
input wire clk,
input wire rst,
input wire rand,
output reg pass
);
parameter n = 8, M = 256, m = 4, B = 4'b1100, mu = 253, r = 4, U = 46288;
reg [7:0] count_bits0, count_bits1;
reg [5:0] count_match;
reg [2:0] count_blocks;
reg [21:0] chi_sqr;
reg [m-1:0] cap;
always @(posedge clk)
if (rst) begin
count_bits0 <= 8'HFF;
count_bits1 <= 0;
count_blocks <= 8'HFF;
count_match <= 0;
cap <= 0;
chi_sqr <= 0;
pass <= 0;
end
else begin
count_bits0 <= count_bits0 + 1;
if (count_bits0 == (M-1)) begin
count_bits0 <= 0;
count_blocks <= count_blocks + 1;
if (count_blocks == (n-1)) begin
count_blocks <= 0;
end
end
count_bits1 <= count_bits0;
cap <= {cap[m-2:0],rand};
if (~(|(cap^B))) count_match <= count_match + 1;
if (count_bits1 == (M-1)) begin
cap <= 0;
count_match <= 0;
chi_sqr <= chi_sqr + ((count_match << r) - mu)*((count_match << r) - mu);
end
if (count_blocks == 0)
if (count_bits1 == 0)
begin
chi_sqr <= 0;
if (chi_sqr <= U) pass <= 1;
else pass <= 0;
end
end
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: openMSP430_fpga.v
//
// *Module Description:
// openMSP430 FPGA Top-level for the Diligent
// Spartan-3 starter kit.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`include "openMSP430_defines.v"
module openMSP430_fpga (
// Clock Sources
CLK_50MHz,
CLK_SOCKET,
// Slide Switches
SW7,
SW6,
SW5,
SW4,
SW3,
SW2,
SW1,
SW0,
// Push Button Switches
BTN3,
BTN2,
BTN1,
BTN0,
// LEDs
LED7,
LED6,
LED5,
LED4,
LED3,
LED2,
LED1,
LED0,
// Four-Sigit, Seven-Segment LED Display
SEG_A,
SEG_B,
SEG_C,
SEG_D,
SEG_E,
SEG_F,
SEG_G,
SEG_DP,
SEG_AN0,
SEG_AN1,
SEG_AN2,
SEG_AN3,
// RS-232 Port
UART_RXD,
UART_TXD,
UART_RXD_A,
UART_TXD_A,
// PS/2 Mouse/Keyboard Port
PS2_D,
PS2_C,
// Fast, Asynchronous SRAM
SRAM_A17, // Address Bus Connections
SRAM_A16,
SRAM_A15,
SRAM_A14,
SRAM_A13,
SRAM_A12,
SRAM_A11,
SRAM_A10,
SRAM_A9,
SRAM_A8,
SRAM_A7,
SRAM_A6,
SRAM_A5,
SRAM_A4,
SRAM_A3,
SRAM_A2,
SRAM_A1,
SRAM_A0,
SRAM_OE, // Write enable and output enable control signals
SRAM_WE,
SRAM0_IO15, // SRAM Data signals, chip enables, and byte enables
SRAM0_IO14,
SRAM0_IO13,
SRAM0_IO12,
SRAM0_IO11,
SRAM0_IO10,
SRAM0_IO9,
SRAM0_IO8,
SRAM0_IO7,
SRAM0_IO6,
SRAM0_IO5,
SRAM0_IO4,
SRAM0_IO3,
SRAM0_IO2,
SRAM0_IO1,
SRAM0_IO0,
SRAM0_CE1,
SRAM0_UB1,
SRAM0_LB1,
SRAM1_IO15,
SRAM1_IO14,
SRAM1_IO13,
SRAM1_IO12,
SRAM1_IO11,
SRAM1_IO10,
SRAM1_IO9,
SRAM1_IO8,
SRAM1_IO7,
SRAM1_IO6,
SRAM1_IO5,
SRAM1_IO4,
SRAM1_IO3,
SRAM1_IO2,
SRAM1_IO1,
SRAM1_IO0,
SRAM1_CE2,
SRAM1_UB2,
SRAM1_LB2,
// VGA Port
VGA_R,
VGA_G,
VGA_B,
VGA_HS,
VGA_VS
);
// Clock Sources
input CLK_50MHz;
input CLK_SOCKET;
// Slide Switches
input SW7;
input SW6;
input SW5;
input SW4;
input SW3;
input SW2;
input SW1;
input SW0;
// Push Button Switches
input BTN3;
input BTN2;
input BTN1;
input BTN0;
// LEDs
output LED7;
output LED6;
output LED5;
output LED4;
output LED3;
output LED2;
output LED1;
output LED0;
// Four-Sigit, Seven-Segment LED Display
output SEG_A;
output SEG_B;
output SEG_C;
output SEG_D;
output SEG_E;
output SEG_F;
output SEG_G;
output SEG_DP;
output SEG_AN0;
output SEG_AN1;
output SEG_AN2;
output SEG_AN3;
// RS-232 Port
input UART_RXD;
output UART_TXD;
input UART_RXD_A;
output UART_TXD_A;
// PS/2 Mouse/Keyboard Port
inout PS2_D;
output PS2_C;
// Fast, Asynchronous SRAM
output SRAM_A17; // Address Bus Connections
output SRAM_A16;
output SRAM_A15;
output SRAM_A14;
output SRAM_A13;
output SRAM_A12;
output SRAM_A11;
output SRAM_A10;
output SRAM_A9;
output SRAM_A8;
output SRAM_A7;
output SRAM_A6;
output SRAM_A5;
output SRAM_A4;
output SRAM_A3;
output SRAM_A2;
output SRAM_A1;
output SRAM_A0;
output SRAM_OE; // Write enable and output enable control signals
output SRAM_WE;
inout SRAM0_IO15; // SRAM Data signals, chip enables, and byte enables
inout SRAM0_IO14;
inout SRAM0_IO13;
inout SRAM0_IO12;
inout SRAM0_IO11;
inout SRAM0_IO10;
inout SRAM0_IO9;
inout SRAM0_IO8;
inout SRAM0_IO7;
inout SRAM0_IO6;
inout SRAM0_IO5;
inout SRAM0_IO4;
inout SRAM0_IO3;
inout SRAM0_IO2;
inout SRAM0_IO1;
inout SRAM0_IO0;
output SRAM0_CE1;
output SRAM0_UB1;
output SRAM0_LB1;
inout SRAM1_IO15;
inout SRAM1_IO14;
inout SRAM1_IO13;
inout SRAM1_IO12;
inout SRAM1_IO11;
inout SRAM1_IO10;
inout SRAM1_IO9;
inout SRAM1_IO8;
inout SRAM1_IO7;
inout SRAM1_IO6;
inout SRAM1_IO5;
inout SRAM1_IO4;
inout SRAM1_IO3;
inout SRAM1_IO2;
inout SRAM1_IO1;
inout SRAM1_IO0;
output SRAM1_CE2;
output SRAM1_UB2;
output SRAM1_LB2;
// VGA Port
output VGA_R;
output VGA_G;
output VGA_B;
output VGA_HS;
output VGA_VS;
//=============================================================================
// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
//=============================================================================
// openMSP430 output buses
wire [13:0] per_addr;
wire [15:0] per_din;
wire [1:0] per_we;
wire [`DMEM_MSB:0] dmem_addr;
wire [15:0] dmem_din;
wire [1:0] dmem_wen;
wire [`PMEM_MSB:0] pmem_addr;
wire [15:0] pmem_din;
wire [1:0] pmem_wen;
wire [13:0] irq_acc;
// openMSP430 input buses
wire [13:0] irq_bus;
wire [15:0] per_dout;
wire [15:0] dmem_dout;
wire [15:0] pmem_dout;
// GPIO
wire [7:0] p1_din;
wire [7:0] p1_dout;
wire [7:0] p1_dout_en;
wire [7:0] p1_sel;
wire [7:0] p2_din;
wire [7:0] p2_dout;
wire [7:0] p2_dout_en;
wire [7:0] p2_sel;
wire [7:0] p3_din;
wire [7:0] p3_dout;
wire [7:0] p3_dout_en;
wire [7:0] p3_sel;
wire [15:0] per_dout_dio;
// Timer A
wire [15:0] per_dout_tA;
// 7 segment driver
wire [15:0] per_dout_7seg;
// Simple UART
wire irq_uart_rx;
wire irq_uart_tx;
wire [15:0] per_dout_uart;
wire hw_uart_txd;
wire hw_uart_rxd;
// Others
wire reset_pin;
//=============================================================================
// 2) CLOCK GENERATION
//=============================================================================
// Input buffers
//------------------------
IBUFG ibuf_clk_main (.O(clk_50M_in), .I(CLK_50MHz));
IBUFG ibuf_clk_socket (.O(clk_socket_in), .I(CLK_SOCKET));
// Digital Clock Manager
//------------------------
// Generate 20MHz clock from 50MHz on-board oscillator
//`define DCM_FX_MODE
`ifdef DCM_FX_MODE
DCM dcm_adv_clk_main (
// OUTPUTs
.CLK0 (),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKDV (),
.CLKFX (dcm_clk),
.CLKFX180 (),
.PSDONE (),
.STATUS (),
.LOCKED (dcm_locked),
// INPUTs
.CLKIN (clk_50M_in),
.CLKFB (1'b0),
.PSINCDEC (1'b0),
.PSEN (1'b0),
.DSSEN (1'b0),
.RST (reset_pin),
.PSCLK (1'b0)
);
// synopsys translate_off
defparam dcm_adv_clk_main.CLK_FEEDBACK = "NONE";
defparam dcm_adv_clk_main.CLKDV_DIVIDE = 2.5;
defparam dcm_adv_clk_main.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam dcm_adv_clk_main.CLKIN_PERIOD = 20.0;
defparam dcm_adv_clk_main.CLKOUT_PHASE_SHIFT = "NONE";
defparam dcm_adv_clk_main.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam dcm_adv_clk_main.DFS_FREQUENCY_MODE = "LOW";
defparam dcm_adv_clk_main.DLL_FREQUENCY_MODE = "LOW";
defparam dcm_adv_clk_main.DUTY_CYCLE_CORRECTION = "TRUE";
defparam dcm_adv_clk_main.FACTORY_JF = 16'hC080;
defparam dcm_adv_clk_main.PHASE_SHIFT = 0;
defparam dcm_adv_clk_main.STARTUP_WAIT = "FALSE";
defparam dcm_adv_clk_main.CLKFX_DIVIDE = 5;
defparam dcm_adv_clk_main.CLKFX_MULTIPLY = 2;
// synopsys translate_on
`else
DCM dcm_adv_clk_main (
// OUTPUTs
.CLKDV (dcm_clk),
.CLKFX (),
.CLKFX180 (),
.CLK0 (CLK0_BUF),
.CLK2X (),
.CLK2X180 (),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.LOCKED (dcm_locked),
.PSDONE (),
.STATUS (),
// INPUTs
.CLKFB (CLKFB_IN),
.CLKIN (clk_50M_in),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.DSSEN (1'b0),
.PSCLK (1'b0),
.RST (reset_pin)
);
BUFG CLK0_BUFG_INST (
.I(CLK0_BUF),
.O(CLKFB_IN)
);
// synopsys translate_off
defparam dcm_adv_clk_main.CLK_FEEDBACK = "1X";
defparam dcm_adv_clk_main.CLKDV_DIVIDE = 2.5;
defparam dcm_adv_clk_main.CLKFX_DIVIDE = 1;
defparam dcm_adv_clk_main.CLKFX_MULTIPLY = 4;
defparam dcm_adv_clk_main.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam dcm_adv_clk_main.CLKIN_PERIOD = 20.000;
defparam dcm_adv_clk_main.CLKOUT_PHASE_SHIFT = "NONE";
defparam dcm_adv_clk_main.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam dcm_adv_clk_main.DFS_FREQUENCY_MODE = "LOW";
defparam dcm_adv_clk_main.DLL_FREQUENCY_MODE = "LOW";
defparam dcm_adv_clk_main.DUTY_CYCLE_CORRECTION = "TRUE";
defparam dcm_adv_clk_main.FACTORY_JF = 16'h8080;
defparam dcm_adv_clk_main.PHASE_SHIFT = 0;
defparam dcm_adv_clk_main.STARTUP_WAIT = "FALSE";
// synopsys translate_on
`endif
//wire dcm_locked = 1'b1;
//wire reset_n;
//reg dcm_clk;
//always @(posedge clk_50M_in)
// if (~reset_n) dcm_clk <= 1'b0;
// else dcm_clk <= ~dcm_clk;
// Clock buffers
//------------------------
BUFG buf_sys_clock (.O(clk_sys), .I(dcm_clk));
//=============================================================================
// 3) RESET GENERATION & FPGA STARTUP
//=============================================================================
// Reset input buffer
IBUF ibuf_reset_n (.O(reset_pin), .I(BTN3));
wire reset_pin_n = ~reset_pin;
// Release the reset only, if the DCM is locked
assign reset_n = reset_pin_n & dcm_locked;
//Include the startup device
wire gsr_tb;
wire gts_tb;
STARTUP_SPARTAN3 xstartup (.CLK(clk_sys), .GSR(gsr_tb), .GTS(gts_tb));
//=============================================================================
// 4) OPENMSP430
//=============================================================================
openMSP430 openMSP430_0 (
// OUTPUTs
.aclk (), // ASIC ONLY: ACLK
.aclk_en (aclk_en), // FPGA ONLY: ACLK enable
.dbg_freeze (dbg_freeze), // Freeze peripherals
.dbg_i2c_sda_out (), // Debug interface: I2C SDA OUT
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
.dco_enable (), // ASIC ONLY: Fast oscillator enable
.dco_wkup (), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
.dmem_addr (dmem_addr), // Data Memory address
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
.dmem_din (dmem_din), // Data Memory data input
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
.lfxt_enable (), // ASIC ONLY: Low frequency oscillator enable
.lfxt_wkup (), // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
.mclk (mclk), // Main system clock
.dma_dout (), // Direct Memory Access data output
.dma_ready (), // Direct Memory Access is complete
.dma_resp (), // Direct Memory Access response (0:Okay / 1:Error)
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_we (per_we), // Peripheral write enable (high active)
.per_en (per_en), // Peripheral enable (high active)
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
.pmem_din (pmem_din), // Program Memory data input (optional)
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
.puc_rst (puc_rst), // Main system reset
.smclk (), // ASIC ONLY: SMCLK
.smclk_en (smclk_en), // FPGA ONLY: SMCLK enable
// INPUTs
.cpu_en (1'b1), // Enable CPU code execution (asynchronous and non-glitchy)
.dbg_en (1'b1), // Debug interface enable (asynchronous and non-glitchy)
.dbg_i2c_addr (7'h00), // Debug interface: I2C Address
.dbg_i2c_broadcast (7'h00), // Debug interface: I2C Broadcast Address (for multicore systems)
.dbg_i2c_scl (1'b1), // Debug interface: I2C SCL
.dbg_i2c_sda_in (1'b1), // Debug interface: I2C SDA IN
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
.dco_clk (clk_sys), // Fast oscillator (fast clock)
.dmem_dout (dmem_dout), // Data Memory data output
.irq (irq_bus), // Maskable interrupts
.lfxt_clk (1'b0), // Low frequency oscillator (typ 32kHz)
.dma_addr (15'h0000), // Direct Memory Access address
.dma_din (16'h0000), // Direct Memory Access data input
.dma_en (1'b0), // Direct Memory Access enable (high active)
.dma_priority (1'b0), // Direct Memory Access priority (0:low / 1:high)
.dma_we (2'b00), // Direct Memory Access write byte enable (high active)
.dma_wkup (1'b0), // ASIC ONLY: DMA Sub-System Wake-up (asynchronous and non-glitchy)
.nmi (nmi), // Non-maskable interrupt (asynchronous)
.per_dout (per_dout), // Peripheral data output
.pmem_dout (pmem_dout), // Program Memory data output
.reset_n (reset_n), // Reset Pin (low active, asynchronous and non-glitchy)
.scan_enable (1'b0), // ASIC ONLY: Scan enable (active during scan shifting)
.scan_mode (1'b0), // ASIC ONLY: Scan mode
.wkup (1'b0) // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
);
//=============================================================================
// 5) OPENMSP430 PERIPHERALS
//=============================================================================
//
// Digital I/O
//-------------------------------
omsp_gpio #(.P1_EN(1),
.P2_EN(1),
.P3_EN(1),
.P4_EN(0),
.P5_EN(0),
.P6_EN(0)) gpio_0 (
// OUTPUTs
.irq_port1 (irq_port1), // Port 1 interrupt
.irq_port2 (irq_port2), // Port 2 interrupt
.p1_dout (p1_dout), // Port 1 data output
.p1_dout_en (p1_dout_en), // Port 1 data output enable
.p1_sel (p1_sel), // Port 1 function select
.p2_dout (p2_dout), // Port 2 data output
.p2_dout_en (p2_dout_en), // Port 2 data output enable
.p2_sel (p2_sel), // Port 2 function select
.p3_dout (p3_dout), // Port 3 data output
.p3_dout_en (p3_dout_en), // Port 3 data output enable
.p3_sel (p3_sel), // Port 3 function select
.p4_dout (), // Port 4 data output
.p4_dout_en (), // Port 4 data output enable
.p4_sel (), // Port 4 function select
.p5_dout (), // Port 5 data output
.p5_dout_en (), // Port 5 data output enable
.p5_sel (), // Port 5 function select
.p6_dout (), // Port 6 data output
.p6_dout_en (), // Port 6 data output enable
.p6_sel (), // Port 6 function select
.per_dout (per_dout_dio), // Peripheral data output
// INPUTs
.mclk (mclk), // Main system clock
.p1_din (p1_din), // Port 1 data input
.p2_din (p2_din), // Port 2 data input
.p3_din (p3_din), // Port 3 data input
.p4_din (8'h00), // Port 4 data input
.p5_din (8'h00), // Port 5 data input
.p6_din (8'h00), // Port 6 data input
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst) // Main system reset
);
//
// Timer A
//----------------------------------------------
omsp_timerA timerA_0 (
// OUTPUTs
.irq_ta0 (irq_ta0), // Timer A interrupt: TACCR0
.irq_ta1 (irq_ta1), // Timer A interrupt: TAIV, TACCR1, TACCR2
.per_dout (per_dout_tA), // Peripheral data output
.ta_out0 (ta_out0), // Timer A output 0
.ta_out0_en (ta_out0_en), // Timer A output 0 enable
.ta_out1 (ta_out1), // Timer A output 1
.ta_out1_en (ta_out1_en), // Timer A output 1 enable
.ta_out2 (ta_out2), // Timer A output 2
.ta_out2_en (ta_out2_en), // Timer A output 2 enable
// INPUTs
.aclk_en (aclk_en), // ACLK enable (from CPU)
.dbg_freeze (dbg_freeze), // Freeze Timer A counter
.inclk (inclk), // INCLK external timer clock (SLOW)
.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst), // Main system reset
.smclk_en (smclk_en), // SMCLK enable (from CPU)
.ta_cci0a (ta_cci0a), // Timer A capture 0 input A
.ta_cci0b (ta_cci0b), // Timer A capture 0 input B
.ta_cci1a (ta_cci1a), // Timer A capture 1 input A
.ta_cci1b (1'b0), // Timer A capture 1 input B
.ta_cci2a (ta_cci2a), // Timer A capture 2 input A
.ta_cci2b (1'b0), // Timer A capture 2 input B
.taclk (taclk) // TACLK external timer clock (SLOW)
);
//
// Four-Digit, Seven-Segment LED Display driver
//----------------------------------------------
driver_7segment driver_7segment_0 (
// OUTPUTs
.per_dout (per_dout_7seg), // Peripheral data output
.seg_a (seg_a_), // Segment A control
.seg_b (seg_b_), // Segment B control
.seg_c (seg_c_), // Segment C control
.seg_d (seg_d_), // Segment D control
.seg_e (seg_e_), // Segment E control
.seg_f (seg_f_), // Segment F control
.seg_g (seg_g_), // Segment G control
.seg_dp (seg_dp_), // Segment DP control
.seg_an0 (seg_an0_), // Anode 0 control
.seg_an1 (seg_an1_), // Anode 1 control
.seg_an2 (seg_an2_), // Anode 2 control
.seg_an3 (seg_an3_), // Anode 3 control
// INPUTs
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst) // Main system reset
);
//
// Simple full duplex UART (8N1 protocol)
//----------------------------------------
omsp_uart #(.BASE_ADDR(15'h0080)) uart_0 (
// OUTPUTs
.irq_uart_rx (irq_uart_rx), // UART receive interrupt
.irq_uart_tx (irq_uart_tx), // UART transmit interrupt
.per_dout (per_dout_uart), // Peripheral data output
.uart_txd (hw_uart_txd), // UART Data Transmit (TXD)
// INPUTs
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst), // Main system reset
.smclk_en (smclk_en), // SMCLK enable (from CPU)
.uart_rxd (hw_uart_rxd) // UART Data Receive (RXD)
);
//
// Combine peripheral data buses
//-------------------------------
assign per_dout = per_dout_dio |
per_dout_tA |
per_dout_7seg |
per_dout_uart;
//
// Assign interrupts
//-------------------------------
assign nmi = 1'b0;
assign irq_bus = {1'b0, // Vector 13 (0xFFFA)
1'b0, // Vector 12 (0xFFF8)
1'b0, // Vector 11 (0xFFF6)
1'b0, // Vector 10 (0xFFF4) - Watchdog -
irq_ta0, // Vector 9 (0xFFF2)
irq_ta1, // Vector 8 (0xFFF0)
irq_uart_rx, // Vector 7 (0xFFEE)
irq_uart_tx, // Vector 6 (0xFFEC)
1'b0, // Vector 5 (0xFFEA)
1'b0, // Vector 4 (0xFFE8)
irq_port2, // Vector 3 (0xFFE6)
irq_port1, // Vector 2 (0xFFE4)
1'b0, // Vector 1 (0xFFE2)
1'b0}; // Vector 0 (0xFFE0)
//
// GPIO Function selection
//--------------------------
// P1.0/TACLK I/O pin / Timer_A, clock signal TACLK input
// P1.1/TA0 I/O pin / Timer_A, capture: CCI0A input, compare: Out0 output
// P1.2/TA1 I/O pin / Timer_A, capture: CCI1A input, compare: Out1 output
// P1.3/TA2 I/O pin / Timer_A, capture: CCI2A input, compare: Out2 output
// P1.4/SMCLK I/O pin / SMCLK signal output
// P1.5/TA0 I/O pin / Timer_A, compare: Out0 output
// P1.6/TA1 I/O pin / Timer_A, compare: Out1 output
// P1.7/TA2 I/O pin / Timer_A, compare: Out2 output
wire [7:0] p1_io_mux_b_unconnected;
wire [7:0] p1_io_dout;
wire [7:0] p1_io_dout_en;
wire [7:0] p1_io_din;
io_mux #8 io_mux_p1 (
.a_din (p1_din),
.a_dout (p1_dout),
.a_dout_en (p1_dout_en),
.b_din ({p1_io_mux_b_unconnected[7],
p1_io_mux_b_unconnected[6],
p1_io_mux_b_unconnected[5],
p1_io_mux_b_unconnected[4],
ta_cci2a,
ta_cci1a,
ta_cci0a,
taclk
}),
.b_dout ({ta_out2,
ta_out1,
ta_out0,
(smclk_en & mclk),
ta_out2,
ta_out1,
ta_out0,
1'b0
}),
.b_dout_en ({ta_out2_en,
ta_out1_en,
ta_out0_en,
1'b1,
ta_out2_en,
ta_out1_en,
ta_out0_en,
1'b0
}),
.io_din (p1_io_din),
.io_dout (p1_io_dout),
.io_dout_en (p1_io_dout_en),
.sel (p1_sel)
);
// P2.0/ACLK I/O pin / ACLK output
// P2.1/INCLK I/O pin / Timer_A, clock signal at INCLK
// P2.2/TA0 I/O pin / Timer_A, capture: CCI0B input
// P2.3/TA1 I/O pin / Timer_A, compare: Out1 output
// P2.4/TA2 I/O pin / Timer_A, compare: Out2 output
wire [7:0] p2_io_mux_b_unconnected;
wire [7:0] p2_io_dout;
wire [7:0] p2_io_dout_en;
wire [7:0] p2_io_din;
io_mux #8 io_mux_p2 (
.a_din (p2_din),
.a_dout (p2_dout),
.a_dout_en (p2_dout_en),
.b_din ({p2_io_mux_b_unconnected[7],
p2_io_mux_b_unconnected[6],
p2_io_mux_b_unconnected[5],
p2_io_mux_b_unconnected[4],
p2_io_mux_b_unconnected[3],
ta_cci0b,
inclk,
p2_io_mux_b_unconnected[0]
}),
.b_dout ({1'b0,
1'b0,
1'b0,
ta_out2,
ta_out1,
1'b0,
1'b0,
(aclk_en & mclk)
}),
.b_dout_en ({1'b0,
1'b0,
1'b0,
ta_out2_en,
ta_out1_en,
1'b0,
1'b0,
1'b1
}),
.io_din (p2_io_din),
.io_dout (p2_io_dout),
.io_dout_en (p2_io_dout_en),
.sel (p2_sel)
);
//=============================================================================
// 6) PROGRAM AND DATA MEMORIES
//=============================================================================
// Data Memory
ram_8x512_hi ram_8x512_hi_0 (
.addr (dmem_addr),
.clk (clk_sys),
.din (dmem_din[15:8]),
.dout (dmem_dout[15:8]),
.en (dmem_cen),
.we (dmem_wen[1])
);
ram_8x512_lo ram_8x512_lo_0 (
.addr (dmem_addr),
.clk (clk_sys),
.din (dmem_din[7:0]),
.dout (dmem_dout[7:0]),
.en (dmem_cen),
.we (dmem_wen[0])
);
// Program Memory
rom_8x2k_hi rom_8x2k_hi_0 (
.addr (pmem_addr),
.clk (clk_sys),
.din (pmem_din[15:8]),
.dout (pmem_dout[15:8]),
.en (pmem_cen),
.we (pmem_wen[1])
);
rom_8x2k_lo rom_8x2k_lo_0 (
.addr (pmem_addr),
.clk (clk_sys),
.din (pmem_din[7:0]),
.dout (pmem_dout[7:0]),
.en (pmem_cen),
.we (pmem_wen[0])
);
//=============================================================================
// 7) I/O CELLS
//=============================================================================
// Slide Switches (Port 1 inputs)
//--------------------------------
IBUF SW7_PIN (.O(p3_din[7]), .I(SW7));
IBUF SW6_PIN (.O(p3_din[6]), .I(SW6));
IBUF SW5_PIN (.O(p3_din[5]), .I(SW5));
IBUF SW4_PIN (.O(p3_din[4]), .I(SW4));
IBUF SW3_PIN (.O(p3_din[3]), .I(SW3));
IBUF SW2_PIN (.O(p3_din[2]), .I(SW2));
IBUF SW1_PIN (.O(p3_din[1]), .I(SW1));
IBUF SW0_PIN (.O(p3_din[0]), .I(SW0));
// LEDs (Port 1 outputs)
//-----------------------
OBUF LED7_PIN (.I(p3_dout[7] & p3_dout_en[7]), .O(LED7));
OBUF LED6_PIN (.I(p3_dout[6] & p3_dout_en[6]), .O(LED6));
OBUF LED5_PIN (.I(p3_dout[5] & p3_dout_en[5]), .O(LED5));
OBUF LED4_PIN (.I(p3_dout[4] & p3_dout_en[4]), .O(LED4));
OBUF LED3_PIN (.I(p3_dout[3] & p3_dout_en[3]), .O(LED3));
OBUF LED2_PIN (.I(p3_dout[2] & p3_dout_en[2]), .O(LED2));
OBUF LED1_PIN (.I(p3_dout[1] & p3_dout_en[1]), .O(LED1));
OBUF LED0_PIN (.I(p3_dout[0] & p3_dout_en[0]), .O(LED0));
// Push Button Switches
//----------------------
IBUF BTN2_PIN (.O(), .I(BTN2));
IBUF BTN1_PIN (.O(), .I(BTN1));
IBUF BTN0_PIN (.O(), .I(BTN0));
// Four-Sigit, Seven-Segment LED Display
//---------------------------------------
OBUF SEG_A_PIN (.I(seg_a_), .O(SEG_A));
OBUF SEG_B_PIN (.I(seg_b_), .O(SEG_B));
OBUF SEG_C_PIN (.I(seg_c_), .O(SEG_C));
OBUF SEG_D_PIN (.I(seg_d_), .O(SEG_D));
OBUF SEG_E_PIN (.I(seg_e_), .O(SEG_E));
OBUF SEG_F_PIN (.I(seg_f_), .O(SEG_F));
OBUF SEG_G_PIN (.I(seg_g_), .O(SEG_G));
OBUF SEG_DP_PIN (.I(seg_dp_), .O(SEG_DP));
OBUF SEG_AN0_PIN (.I(seg_an0_), .O(SEG_AN0));
OBUF SEG_AN1_PIN (.I(seg_an1_), .O(SEG_AN1));
OBUF SEG_AN2_PIN (.I(seg_an2_), .O(SEG_AN2));
OBUF SEG_AN3_PIN (.I(seg_an3_), .O(SEG_AN3));
// RS-232 Port
//----------------------
// P1.1 (TX) and P2.2 (RX)
assign p1_io_din = 8'h00;
assign p2_io_din[7:3] = 5'h00;
assign p2_io_din[1:0] = 2'h0;
// Mux the RS-232 port between:
// - GPIO port P1.1 (TX) / P2.2 (RX)
// - the debug interface.
// - the simple hardware UART
//
// The mux is controlled with the SW0/SW1 switches:
// 00 = debug interface
// 01 = GPIO
// 10 = simple hardware uart
// 11 = debug interface
wire sdi_select = ({p3_din[1], p3_din[0]}==2'b00) |
({p3_din[1], p3_din[0]}==2'b11);
wire gpio_select = ({p3_din[1], p3_din[0]}==2'b01);
wire uart_select = ({p3_din[1], p3_din[0]}==2'b10);
wire uart_txd_out = gpio_select ? p1_io_dout[1] :
uart_select ? hw_uart_txd : dbg_uart_txd;
wire uart_rxd_in;
assign p2_io_din[2] = gpio_select ? uart_rxd_in : 1'b1;
assign hw_uart_rxd = uart_select ? uart_rxd_in : 1'b1;
assign dbg_uart_rxd = sdi_select ? uart_rxd_in : 1'b1;
IBUF UART_RXD_PIN (.O(uart_rxd_in), .I(UART_RXD));
OBUF UART_TXD_PIN (.I(uart_txd_out), .O(UART_TXD));
IBUF UART_RXD_A_PIN (.O(), .I(UART_RXD_A));
OBUF UART_TXD_A_PIN (.I(1'b0), .O(UART_TXD_A));
// PS/2 Mouse/Keyboard Port
//--------------------------
IOBUF PS2_D_PIN (.O(), .I(1'b0), .T(1'b1), .IO(PS2_D));
OBUF PS2_C_PIN (.I(1'b0), .O(PS2_C));
// Fast, Asynchronous SRAM
//--------------------------
OBUF SRAM_A17_PIN (.I(1'b0), .O(SRAM_A17));
OBUF SRAM_A16_PIN (.I(1'b0), .O(SRAM_A16));
OBUF SRAM_A15_PIN (.I(1'b0), .O(SRAM_A15));
OBUF SRAM_A14_PIN (.I(1'b0), .O(SRAM_A14));
OBUF SRAM_A13_PIN (.I(1'b0), .O(SRAM_A13));
OBUF SRAM_A12_PIN (.I(1'b0), .O(SRAM_A12));
OBUF SRAM_A11_PIN (.I(1'b0), .O(SRAM_A11));
OBUF SRAM_A10_PIN (.I(1'b0), .O(SRAM_A10));
OBUF SRAM_A9_PIN (.I(1'b0), .O(SRAM_A9));
OBUF SRAM_A8_PIN (.I(1'b0), .O(SRAM_A8));
OBUF SRAM_A7_PIN (.I(1'b0), .O(SRAM_A7));
OBUF SRAM_A6_PIN (.I(1'b0), .O(SRAM_A6));
OBUF SRAM_A5_PIN (.I(1'b0), .O(SRAM_A5));
OBUF SRAM_A4_PIN (.I(1'b0), .O(SRAM_A4));
OBUF SRAM_A3_PIN (.I(1'b0), .O(SRAM_A3));
OBUF SRAM_A2_PIN (.I(1'b0), .O(SRAM_A2));
OBUF SRAM_A1_PIN (.I(1'b0), .O(SRAM_A1));
OBUF SRAM_A0_PIN (.I(1'b0), .O(SRAM_A0));
OBUF SRAM_OE_PIN (.I(1'b1), .O(SRAM_OE));
OBUF SRAM_WE_PIN (.I(1'b1), .O(SRAM_WE));
IOBUF SRAM0_IO15_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO15));
IOBUF SRAM0_IO14_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO14));
IOBUF SRAM0_IO13_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO13));
IOBUF SRAM0_IO12_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO12));
IOBUF SRAM0_IO11_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO11));
IOBUF SRAM0_IO10_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO10));
IOBUF SRAM0_IO9_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO9));
IOBUF SRAM0_IO8_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO8));
IOBUF SRAM0_IO7_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO7));
IOBUF SRAM0_IO6_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO6));
IOBUF SRAM0_IO5_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO5));
IOBUF SRAM0_IO4_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO4));
IOBUF SRAM0_IO3_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO3));
IOBUF SRAM0_IO2_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO2));
IOBUF SRAM0_IO1_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO1));
IOBUF SRAM0_IO0_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO0));
OBUF SRAM0_CE1_PIN (.I(1'b1), .O(SRAM0_CE1));
OBUF SRAM0_UB1_PIN (.I(1'b1), .O(SRAM0_UB1));
OBUF SRAM0_LB1_PIN (.I(1'b1), .O(SRAM0_LB1));
IOBUF SRAM1_IO15_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO15));
IOBUF SRAM1_IO14_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO14));
IOBUF SRAM1_IO13_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO13));
IOBUF SRAM1_IO12_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO12));
IOBUF SRAM1_IO11_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO11));
IOBUF SRAM1_IO10_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO10));
IOBUF SRAM1_IO9_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO9));
IOBUF SRAM1_IO8_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO8));
IOBUF SRAM1_IO7_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO7));
IOBUF SRAM1_IO6_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO6));
IOBUF SRAM1_IO5_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO5));
IOBUF SRAM1_IO4_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO4));
IOBUF SRAM1_IO3_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO3));
IOBUF SRAM1_IO2_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO2));
IOBUF SRAM1_IO1_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO1));
IOBUF SRAM1_IO0_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO0));
OBUF SRAM1_CE2_PIN (.I(1'b1), .O(SRAM1_CE2));
OBUF SRAM1_UB2_PIN (.I(1'b1), .O(SRAM1_UB2));
OBUF SRAM1_LB2_PIN (.I(1'b1), .O(SRAM1_LB2));
// VGA Port
//---------------------------------------
OBUF VGA_R_PIN (.I(1'b0), .O(VGA_R));
OBUF VGA_G_PIN (.I(1'b0), .O(VGA_G));
OBUF VGA_B_PIN (.I(1'b0), .O(VGA_B));
OBUF VGA_HS_PIN (.I(1'b0), .O(VGA_HS));
OBUF VGA_VS_PIN (.I(1'b0), .O(VGA_VS));
endmodule // openMSP430_fpga
|
`include "constants.v"
module fp16_smult (
input wire [31: 0] a,
input wire [31: 0] b,
output reg [31: 0] prod
);
function [31: 0] fp16_mult;
input [31: 0] a;
input [31: 0] b;
reg [31: 0] prod;
reg [31: 0] product_hi;
reg [31: 0] product_lo;
reg [31: 0] A;
reg [31: 0] B;
reg [31: 0] C;
reg [31: 0] D;
reg [31: 0] AC;
reg [31: 0] BD;
reg [31: 0] AD_CB;
reg [31: 0] ad_cb_temp;
begin
A = (a >> 16);
B = a & 'hFFFF;
C = (b >> 16);
D = b & 'hFFFF;
AC = A * C;
BD = B * D;
AD_CB = A * D + C * B;
ad_cb_temp = AD_CB << 16;
product_hi = AC + (AD_CB);
product_lo = BD + ad_cb_temp;
if (product_lo < BD) begin
product_lo = product_lo + 1;
end
prod = (product_hi << 16) | (product_lo >> 16);//{product_hi[15: 0], product_lo[15: 0]};
if (product_hi >> 31 != product_lo >> 15) begin
prod = `FP16_OVERFLOW;
end
fp16_mult = prod;
end
endfunction
always @(*) begin
prod = fp16_mult(a, b);
if (prod == `FP16_OVERFLOW) begin
prod = ((a >= 0) == (b >= 0)) ? `FP16_MAXIMUM : `FP16_MINIMUM;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211OI_1_V
`define SKY130_FD_SC_MS__A211OI_1_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a211oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a211oi_1 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211OI_1_V
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: main_memory_sxm_d.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module main_memory_sxm_d (
address,
clock,
data,
wren,
q);
input [7:0] address;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "Scalar_x_Matrix_Disp.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "Scalar_x_Matrix_Disp.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "Scalar_x_Matrix_Disp.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL main_memory_sxm_d.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL main_memory_sxm_d.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL main_memory_sxm_d.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL main_memory_sxm_d.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL main_memory_sxm_d_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL main_memory_sxm_d_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: ff_64x256_fwft.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ff_64x256_fwft (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [63:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [63:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [63:0] sub_wire3;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [63:0] q = sub_wire3[63:0];
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_empty (),
.almost_full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Cyclone V",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M10K",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 64,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "64"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "64"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M10K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_64x256_fwft.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_64x256_fwft.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_64x256_fwft.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_64x256_fwft.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_64x256_fwft_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_64x256_fwft_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:23:14 11/09/2016
// Design Name:
// Module Name: Sprite
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Sprite_Controller # ( parameter SizeX= 32, parameter SizeY=32) (
input wire [9:0] iColumnCount,
input wire[9:0] iRowCount,
input wire imask,
input wire iEnable,
input wire [9:0] iPosX,
input wire [9:0] iPosY,
input wire [2:0] iColorSprite,
input wire [2:0] iColorBack ,
output reg [2:0] oRGB
);
always @ (*)
begin
if(iColumnCount <= SizeX + iPosX && iRowCount <= SizeY + iPosY
&& iColumnCount >= iPosX && iRowCount >= iPosY && iEnable == 1 && imask == 1 )
begin
oRGB <= iColorSprite;
end
else
begin
oRGB <= iColorBack;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBN_SYMBOL_V
`define SKY130_FD_SC_MS__SDFBBN_SYMBOL_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfbbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBN_SYMBOL_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 18:54:16 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_processing_system7_0_0_sim_netlist.v
// Design : ip_design_processing_system7_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "ip_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_CLK1,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_I" *) input I2C0_SDA_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_O" *) output I2C0_SDA_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_T" *) output I2C0_SDA_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_I" *) input I2C0_SCL_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_O" *) output I2C0_SCL_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_T" *) output I2C0_SCL_T;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 10000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK1" *) output FCLK_CLK1;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_RESET0_N;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "TRUE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *)
(* C_GP1_EN_MODIFIABLE_TXN = "1" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg484" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "ip_design_processing_system7_0_0.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(FCLK_CLK1),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(I2C0_SCL_I),
.I2C0_SCL_O(I2C0_SCL_O),
.I2C0_SCL_T(I2C0_SCL_T),
.I2C0_SDA_I(I2C0_SDA_I),
.I2C0_SDA_O(I2C0_SDA_O),
.I2C0_SDA_T(I2C0_SDA_T),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(1'b0),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "TRUE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg484" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "ip_design_processing_system7_0_0.hwdef" *) (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire \<const1> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [1:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]\^M_AXI_GP0_ARCACHE ;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]\^M_AXI_GP0_AWCACHE ;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]\^M_AXI_GP1_ARCACHE ;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]\^M_AXI_GP1_AWCACHE ;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
VCC VCC
(.P(\<const1> ));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered[0]),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_1.FCLK_CLK_1_BUFG
(.I(FCLK_CLK_unbuffered[1]),
.O(FCLK_CLK1));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* This is a test bench file of the Queue module.
*
* Author: Kimi
* Date: 29/01/11
**/
`timescale 1ns /1ps
module queue_test_bench();
// define prams
localparam DAT_WD = 16;
localparam DEPTH = 20;
localparam ADD_WD = clogb2(DEPTH);
//localparam HI = clogb2(DEPTH);
localparam WRITE_OP = 1'b0;
localparam READ_OP = 1'b1;
// dut related signals
reg [DAT_WD-1:0] EV_in;
wire [DAT_WD-1:0] EV_out;
wire [ADD_WD:0] dut_len;
reg op, cs, rst, clk;
wire full, empty, busy, dv;
reg [DAT_WD-1:0] data_in;
reg [DAT_WD-1:0] dut_data_out;
reg [DAT_WD-1:0] gm_data_out;
// heap related variables
reg [DAT_WD-1:0] ram [0:DEPTH-1];
reg [ADD_WD-1:0] gm_len;
integer s;
integer round;
localparam mean = 3;
localparam std_dev = 2;
reg [8*10:1] op_str;
integer stat_rd;
integer stat_wr;
//////////////////////////////////////////////////
// clock generation
always begin
clk = 0;
#5;
clk = 1;
#10;
clk = 0;
#5;
end
//////////////////////////////////////////////////
// operation decoding into human-readable state
always @* begin
if(cs)
if(op==READ_OP) begin
op_str = "R";
stat_rd = stat_rd + 1;
end
else begin
op_str = "W";
stat_wr = stat_wr + 1;
end
else
op_str = "NOP";
end
initial begin
// init all signals
rst = 1;
clk = 0;
cs = 0;
op = 0;
data_in = 0;
dut_data_out = 0;
gm_data_out = 0;
s = 15;
gm_len = 0;
round = 0;
stat_rd = 0;
stat_wr = 0;
#50;
rst = 0;
$display("\n\n********************Start***************************\n");
for (round = 0; round < 150 ; round = round + 1 ) begin
// cast an operation
//usage: $dist_normal ( seed , mean , standard_deviation )
if ( IsEmpty(dut_len) ) begin
op = WRITE_OP;
end
else if ( IsFull(dut_len) ) begin
op = READ_OP;
end
else begin
op = ( $dist_normal ( s , mean , std_dev ) < 5 ) ? WRITE_OP : READ_OP ;
end
case (op)
WRITE_OP: begin
data_in = {$random}%15;//{DAT_WD{1'b1}}; // allow data [0,...,max_allowed_by_DAT_WD]
$display("Write @%04d [%04h]", $time, data_in );
fork
begin
Insert_dut(data_in);
end
begin
@(posedge clk) // write to GM at posedge clk (for sync of 2 models)
Insert_gm(data_in);
end
join
end
READ_OP: begin
$display("Read @%04d", $time);
fork
begin
Extract_dut(dut_data_out);
end
begin
@(posedge clk) // (for sync of 2 models)
Extract_gm(gm_data_out);
end
join
$display(" read data, dut [%04h] , gm [%04h] @%04d", dut_data_out, gm_data_out, $time);
end
endcase // case (op)
wait (!busy);
end
#50;
$display("\n\n********************End***************************\n");
$display("Statistics\n\tread count: [%04d]\n\twrite count:[%04d]", stat_rd ,stat_wr);
end
//////////////////////////////////////////
// test processes
always @( negedge busy ) begin
#1;
Compare_rams;
end
always @( posedge dv ) begin
#1;
Compare_top;
end
task Compare_rams;
integer j;
begin
for( j=0; j < gm_len ; j=j+1) begin
if (ram[j] != dut.ram.ram[j])
$display("\tError @%04d: Rams are not equal at index [%04d] dut[%04h] , gm[%04h]", $time, j, dut.ram.ram[j], ram[j]);
end
end
endtask
task Compare_top;
begin
if ( ram[0] != EV_out )
$display("\tError @%04d: Topmost elements are not equal dut [%04h] gm [%04h]", $time, ram[0], dut.ram.ram[0]);
end
endtask
///////////////////////////////////////////
// DUT module instantiation
Queue #(.data_wd(DAT_WD),
.q_add_wd(ADD_WD),
.q_max_len(DEPTH),
.hi(DAT_WD-1),
.lo(0)
)
dut(
.EV_in(EV_in),
.op(op),
.cs(cs),
.rst(rst),
.clk(clk),
.EV_out(EV_out),
.dv(dv),
.full(full),
.empty(empty),
.busy(busy),
.length(dut_len)
);
////////////////////////////////////////////////
// dut related tasks
task Insert_dut(
input reg [DAT_WD-1:0] key);
begin
op = 0;
cs = 0;
EV_in = key;
wait(!busy);
cs=1;
op = WRITE_OP;
@(posedge clk);
@(negedge clk);
EV_in = 0;
cs = 0;
op = 0;
end
endtask
task Extract_dut(
output reg [DAT_WD-1:0] key);
begin
op = 0;
cs = 0;
wait((dv && !busy));
cs=1;
op = READ_OP;
@(posedge clk);
key = EV_out;
@(negedge clk);
cs = 0;
op = 0;
end
endtask
////////////////////////////////////////////////
// inner tasks
task Print;
integer i;
reg [DAT_WD-1:0] top;
begin
for (i=0; i<DEPTH; i=i+1) begin
Extract_gm(top);
#10;
$display("%d",top);
end
end
endtask
// extrac top most element from Heap
task Extract_gm ;
output [DAT_WD-1:0] top;
reg [DAT_WD-1:0] smallest;
reg [ADD_WD-1:0] smallest_idx;
reg [ADD_WD-1:0] i;
begin
i = 0;
if( !IsEmpty(gm_len) ) begin
top = ram[0];
gm_len = gm_len - 1'b1;
Swap(0, gm_len);
min3(0, LeftChild(i), RigthChild(i), smallest, smallest_idx);
while ( smallest_idx != i) begin
Swap(smallest_idx, i);
i = smallest_idx;
min3(i, LeftChild(i), RigthChild(i), smallest, smallest_idx);
#5;
end
end
end
endtask
// return min of three elements: left_child_idx, right_child_idx and i
// and corresponding ram entry
task min3( input [ADD_WD-1:0] i, left_child_idx, right_child_idx,
output [DAT_WD-1:0] smallest,
output [ADD_WD-1:0] smallest_idx
);
begin
smallest = ram[i];
smallest_idx = i;
if( left_child_idx < gm_len ) begin
smallest = (ram[i] < ram[left_child_idx]) ? ram[i] : ram[left_child_idx];
smallest_idx = (ram[i] < ram[left_child_idx]) ? i : left_child_idx;
end
if ( right_child_idx < gm_len ) begin
smallest = (ram[smallest_idx] < ram[right_child_idx]) ? ram[smallest_idx]: ram[right_child_idx];
smallest_idx = (ram[smallest_idx] < ram[right_child_idx]) ? smallest_idx : right_child_idx;
end
end
endtask
// insert key into the heap
task Insert_gm;
input [DAT_WD-1:0] key;
reg [ADD_WD-1:0] i;
begin
if ( !IsFull(gm_len) ) begin
ram[gm_len] = key;
i = gm_len;
gm_len = gm_len + 1'b1;
while( i>0 && ram[i] < ram[Parent(i)] ) begin
Swap( i, Parent(i) );
i = Parent(i);
#5;
end
end
end
endtask
// return true iff heap is full
function automatic IsEmpty(input reg [ADD_WD-1:0] length);
IsEmpty = length == {ADD_WD{1'b0}};
endfunction
// return true iff heap is full
function automatic IsFull(input reg [ADD_WD-1:0] length);
IsFull = length == DEPTH;
endfunction
// swaps the i'th and j'th indexes in the ram
task Swap;
input [ADD_WD-1:0] i, j;
reg [DAT_WD-1:0] temp;
begin
temp = ram[i];
ram[i] = ram[j];
ram[j] = temp;
end
endtask
// returns parent index of idx
function [ADD_WD-1:0] Parent(input reg [ADD_WD-1:0] idx);
Parent = (idx-1)/2;
endfunction
// returns left child index of idx
function [ADD_WD-1:0] LeftChild(input reg [ADD_WD-1:0] i);
LeftChild = (2*i)+1;
endfunction
// returns right child index of idx
function [ADD_WD-1:0] RigthChild(input reg [ADD_WD-1:0] i);
RigthChild = 2*(i+1);
endfunction
//define the clogb2 function
function integer clogb2;
input [31:0] value;
begin
value = value - 1;
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
value = value >> 1;
end
endfunction
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:07:43 05/06/2013
// Design Name:
// Module Name: Converter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Converter(
input ScanCodeType,
input Clock,
input Reset,
input [7:0] Actual,
input [7:0] Anterior,
output reg [6:0] Ascii,
output reg NewAscii
);
wire [9:0]Entrada;
reg LoadMayus;
reg CompShift;
reg CompMayus;
reg CompSoltar;
reg CompAscii;
reg Mayus;
reg Shift;
assign Entrada = {Shift, Mayus^Shift,Actual};
always @(*)begin
if (Actual==8'h12)CompShift=1; else CompShift=0;
end
always @(*)begin
if (Actual==8'h58)CompMayus=1; else CompMayus=0;
end
always @(*)begin
if (Anterior==8'hF0)CompSoltar=1; else CompSoltar=0;
end
always@(*)begin
LoadMayus=(CompMayus && CompSoltar);
end
always @(*)begin
if (Ascii==7'h00)CompAscii=0; else CompAscii=1;
end
always @(*) begin
NewAscii = (CompSoltar && CompAscii);
end
always @(posedge Clock)begin
if(Reset)Mayus=0; else begin
if(LoadMayus && ScanCodeType)Mayus=~Mayus;
end
end
always @(posedge Clock)begin
if(Reset)Shift=0; else begin
if(CompShift&&ScanCodeType)Shift=~CompSoltar;
end
end
always @(*)begin
case (Entrada)
//Alfabeto
10'h015:Ascii= 7'h71;
10'h115:Ascii= 7'h51;
10'h215:Ascii= 7'h71;
10'h315:Ascii= 7'h51;
10'h01D:Ascii= 7'h77;
10'h11D:Ascii= 7'h57;
10'h21D:Ascii= 7'h77;
10'h31D:Ascii= 7'h57;
10'h024:Ascii= 7'h65;
10'h124:Ascii= 7'h45;
10'h224:Ascii= 7'h65;
10'h324:Ascii= 7'h45;
10'h02D:Ascii= 7'h72;
10'h12D:Ascii= 7'h52;
10'h22D:Ascii= 7'h72;
10'h32D:Ascii= 7'h52;
10'h02C:Ascii= 7'h74;
10'h12C:Ascii= 7'h54;
10'h22C:Ascii= 7'h74;
10'h32C:Ascii= 7'h54;
10'h035:Ascii= 7'h79;
10'h135:Ascii= 7'h59;
10'h235:Ascii= 7'h79;
10'h335:Ascii= 7'h59;
10'h03C:Ascii= 7'h75;
10'h13C:Ascii= 7'h55;
10'h23C:Ascii= 7'h75;
10'h33C:Ascii= 7'h55;
10'h043:Ascii= 7'h69;
10'h143:Ascii= 7'h49;
10'h243:Ascii= 7'h69;
10'h343:Ascii= 7'h49;
10'h044:Ascii= 7'h6F;
10'h144:Ascii= 7'h4F;
10'h244:Ascii= 7'h6F;
10'h344:Ascii= 7'h4F;
10'h04D:Ascii= 7'h70;
10'h14D:Ascii= 7'h50;
10'h24D:Ascii= 7'h70;
10'h34D:Ascii= 7'h50;
10'h01C:Ascii= 7'h61;
10'h11C:Ascii= 7'h41;
10'h21C:Ascii= 7'h61;
10'h31C:Ascii= 7'h41;
10'h01B:Ascii= 7'h73;
10'h11B:Ascii= 7'h53;
10'h21B:Ascii= 7'h73;
10'h31B:Ascii= 7'h53;
10'h023:Ascii= 7'h64;
10'h123:Ascii= 7'h44;
10'h223:Ascii= 7'h64;
10'h323:Ascii= 7'h44;
10'h02B:Ascii= 7'h66;
10'h12B:Ascii= 7'h46;
10'h22B:Ascii= 7'h66;
10'h32B:Ascii= 7'h46;
10'h034:Ascii= 7'h67;
10'h134:Ascii= 7'h47;
10'h234:Ascii= 7'h67;
10'h334:Ascii= 7'h47;
10'h033:Ascii= 7'h68;
10'h133:Ascii= 7'h48;
10'h233:Ascii= 7'h68;
10'h333:Ascii= 7'h48;
10'h03B:Ascii= 7'h6A;
10'h13B:Ascii= 7'h4A;
10'h23B:Ascii= 7'h6A;
10'h33B:Ascii= 7'h4A;
10'h042:Ascii= 7'h6B;
10'h142:Ascii= 7'h4B;
10'h242:Ascii= 7'h6B;
10'h342:Ascii= 7'h4B;
10'h04B:Ascii= 7'h6C;
10'h14B:Ascii= 7'h4C;
10'h24B:Ascii= 7'h6C;
10'h34B:Ascii= 7'h4C;
10'h01A:Ascii= 7'h7A;
10'h11A:Ascii= 7'h5A;
10'h21A:Ascii= 7'h7A;
10'h31A:Ascii= 7'h5A;
10'h022:Ascii= 7'h78;
10'h122:Ascii= 7'h58;
10'h222:Ascii= 7'h78;
10'h322:Ascii= 7'h58;
10'h021:Ascii= 7'h63;
10'h121:Ascii= 7'h43;
10'h221:Ascii= 7'h63;
10'h321:Ascii= 7'h43;
10'h02A:Ascii= 7'h76;
10'h12A:Ascii= 7'h56;
10'h22A:Ascii= 7'h76;
10'h32A:Ascii= 7'h56;
10'h032:Ascii= 7'h62;
10'h132:Ascii= 7'h42;
10'h232:Ascii= 7'h62;
10'h332:Ascii= 7'h42;
10'h031:Ascii= 7'h6E;
10'h131:Ascii= 7'h4E;
10'h231:Ascii= 7'h6E;
10'h331:Ascii= 7'h4E;
10'h03A:Ascii= 7'h6D;
10'h13A:Ascii= 7'h4D;
10'h23A:Ascii= 7'h6D;
10'h33A:Ascii= 7'h4D;
//Simbolos
10'h00E:Ascii= 7'h60;
10'h10E:Ascii= 7'h60;
10'h20E:Ascii= 7'h7E;
10'h30E:Ascii= 7'h7E;
10'h016:Ascii= 7'h31;
10'h116:Ascii= 7'h31;
10'h216:Ascii= 7'h21;
10'h316:Ascii= 7'h21;
10'h01E:Ascii= 7'h32;
10'h11E:Ascii= 7'h32;
10'h21E:Ascii= 7'h40;
10'h31E:Ascii= 7'h40;
10'h026:Ascii= 7'h33;
10'h126:Ascii= 7'h33;
10'h226:Ascii= 7'h23;
10'h326:Ascii= 7'h23;
10'h025:Ascii= 7'h34;
10'h125:Ascii= 7'h34;
10'h225:Ascii= 7'h24;
10'h325:Ascii= 7'h24;
10'h02E:Ascii= 7'h35;
10'h12E:Ascii= 7'h35;
10'h22E:Ascii= 7'h25;
10'h32E:Ascii= 7'h25;
10'h036:Ascii= 7'h36;
10'h136:Ascii= 7'h36;
10'h236:Ascii= 7'h5E;
10'h336:Ascii= 7'h5E;
10'h03D:Ascii= 7'h37;
10'h13D:Ascii= 7'h37;
10'h23D:Ascii= 7'h26;
10'h33D:Ascii= 7'h26;
10'h03E:Ascii= 7'h38;
10'h13E:Ascii= 7'h38;
10'h23E:Ascii= 7'h2A;
10'h33E:Ascii= 7'h2A;
10'h046:Ascii= 7'h39;
10'h146:Ascii= 7'h39;
10'h246:Ascii= 7'h28;
10'h346:Ascii= 7'h28;
10'h045:Ascii= 7'h30;
10'h145:Ascii= 7'h30;
10'h245:Ascii= 7'h29;
10'h345:Ascii= 7'h29;
10'h04E:Ascii= 7'h2D;
10'h14E:Ascii= 7'h2D;
10'h24E:Ascii= 7'h5F;
10'h34E:Ascii= 7'h5F;
10'h055:Ascii= 7'h2B;
10'h155:Ascii= 7'h2B;
10'h255:Ascii= 7'h2B;
10'h355:Ascii= 7'h2B;
10'h05D:Ascii= 7'h5C;
10'h15D:Ascii= 7'h5C;
10'h25D:Ascii= 7'h7C;
10'h35D:Ascii= 7'h7C;
10'h054:Ascii= 7'h5B;
10'h154:Ascii= 7'h5B;
10'h254:Ascii= 7'h7B;
10'h354:Ascii= 7'h7B;
10'h05B:Ascii= 7'h5D;
10'h15B:Ascii= 7'h5D;
10'h25B:Ascii= 7'h7D;
10'h35B:Ascii= 7'h7D;
10'h04C:Ascii= 7'h3B;
10'h14C:Ascii= 7'h3B;
10'h24C:Ascii= 7'h3A;
10'h34C:Ascii= 7'h3A;
10'h052:Ascii= 7'h27;
10'h152:Ascii= 7'h27;
10'h252:Ascii= 7'h22;
10'h352:Ascii= 7'h22;
10'h041:Ascii= 7'h2C;
10'h141:Ascii= 7'h2C;
10'h241:Ascii= 7'h3C;
10'h341:Ascii= 7'h3C;
10'h049:Ascii= 7'h2E;
10'h149:Ascii= 7'h2E;
10'h249:Ascii= 7'h3E;
10'h349:Ascii= 7'h3E;
10'h04A:Ascii= 7'h2F;
10'h14A:Ascii= 7'h2F;
10'h24A:Ascii= 7'h3F;
10'h34A:Ascii= 7'h3F;
//Independientes
10'h066:Ascii= 7'h08;
10'h166:Ascii= 7'h08;
10'h266:Ascii= 7'h08;
10'h366:Ascii= 7'h08;
10'h029:Ascii= 7'h20;
10'h129:Ascii= 7'h20;
10'h229:Ascii= 7'h20;
10'h329:Ascii= 7'h20;
10'h05A:Ascii= 7'h04;
10'h15A:Ascii= 7'h04;
10'h25A:Ascii= 7'h04;
10'h35A:Ascii= 7'h04;
10'h076:Ascii= 7'h1B;
10'h176:Ascii= 7'h1B;
10'h276:Ascii= 7'h1B;
10'h376:Ascii= 7'h1B;
default: Ascii=7'b0;
endcase
end
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Extraction to Ocaml : use of basic Ocaml types *)
Scheme Equality for nat.
Extract Inductive bool => bool [ true false ].
Extract Inductive option => option [ Some None ].
Extract Inductive unit => unit [ "()" ].
Extract Inductive list => list [ "[]" "( :: )" ].
Extract Inductive prod => "( * )" [ "" ].
(** NB: The "" above is a hack, but produce nicer code than "(,)" *)
(** Mapping sumbool to bool and sumor to option is not always nicer,
but it helps when realizing stuff like [lt_eq_lt_dec] *)
Extract Inductive sumbool => bool [ true false ].
Extract Inductive sumor => option [ Some None ].
(** Restore lazyness of andb, orb.
NB: without these Extract Constant, andb/orb would be inlined
by extraction in order to have lazyness, producing inelegant
(if ... then ... else false) and (if ... then true else ...).
*)
Extract Inlined Constant andb => "(&&)".
Extract Inlined Constant orb => "(||)".
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2_PP_SYMBOL_V
`define SKY130_FD_SC_HS__NAND2_PP_SYMBOL_V
/**
* nand2: 2-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2_PP_SYMBOL_V
|
//--------------------------------------------------------------------------------
//-- Filename: REQ_MANAGER.v
//--
//-- Description: Request Manager Module
//--
//-- Multiple low layer module are linked in this module.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module REQ_MANAGER(
clk,
rst_n,
en,
// REQ_QUEUE_WRAPPER
rdata_i,
rdata_wr_en_i,
req_queue_full_o,
//CPM
CMGFTL_cmd_fifo_full_i,
CMGFTL_cmd_fifo_almost_full_i,
CMGFTL_cmd_fifo_wr_en_o,
CMGFTL_cmd_fifo_data_o,
FTLCMG_cmd_fifo_empty_i,
FTLCMG_cmd_fifo_almost_empty_i,
FTLCMG_cmd_fifo_rd_en_o,
FTLCMG_cmd_fifo_data_i,
bar1_wr_en2_o,
bar1_addr2_o,
bar1_wr_be2_o,
bar1_wr_d2_o,
bar1_wr_ack2_n_i,
bar1_wr_en3_o,
bar1_addr3_o,
bar1_wr_be3_o,
bar1_wr_d3_o,
bar1_wr_ack3_n_i,
bar1_arbiter_busy_i,
bar1_wr_busy_i,
mrd_start_i,
mrd_done_i,
mwr_start_i,
mwr_done_i,
req_compl_i,
recv_fifo_av_i,
//BAR0_WRAPPER
a_i,
wr_en_i,
wr_be_i,
wr_busy_o,
rd_d_o,
rd_be_i,
wr_d_i,
bar1_wr_en1_o,
bar1_addr1_o,
bar1_wr_be1_o,
bar1_wr_d1_o,
bar1_wr_ack1_n_i,
compl_done_i,
dma_rd_req_flag_o,
cpld_malformed_i,
//INT_MANAGER
msi_on,
cfg_interrupt_assert_n_o,
cfg_interrupt_rdy_n_i,
cfg_interrupt_n_o,
cfg_interrupt_legacyclr,
//DMA READ QUEUE
dma_rd_q_rd_en_i,
dma_rd_q_rd_data_o,
dma_rd_q_empty_o,
dma_rd_xfer_done_i,
dma_rd_done_entry_i,
dma_rd_xfer_done_ack_o,
/*************ouyang***************/
//response queue interface
response_queue_empty_o,
response_queue_data_o,
response_queue_rd_en_i ,//read enable signal for response queue
//msix interface
msg_lower_addr_o,
msg_upper_addr_o,
msg_data_o,
// the base addr for response queue
response_queue_addr_o,
//count enable for response queue offset
response_queue_addr_offset_cnt_en_i,
interrupt_block_o,
response_queue_cur_offset_reg_o,
response_queue_addr_offset_o
/**********************************/
);
/*************ouyang***************/
//response queue interface
output response_queue_empty_o;
output [31:0] response_queue_data_o;
input response_queue_rd_en_i ;//read enable signal for response queue
//msix interface
output [31:0] msg_lower_addr_o;
output [31:0] msg_upper_addr_o;
output [31:0] msg_data_o;
// the base addr for response queue
output [31:0] response_queue_addr_o;
//count enable for response queue offset
input response_queue_addr_offset_cnt_en_i;
output interrupt_block_o;
output [31:0] response_queue_cur_offset_reg_o;
output [10:0] response_queue_addr_offset_o;
/*********************************/
input clk;
input rst_n;
output en;
// Request Queue Wrapper
//
input [127:0] rdata_i;
input rdata_wr_en_i;
output req_queue_full_o;
// CPM
//
input CMGFTL_cmd_fifo_full_i;
input CMGFTL_cmd_fifo_almost_full_i;
output CMGFTL_cmd_fifo_wr_en_o;
output [127:0] CMGFTL_cmd_fifo_data_o;
input FTLCMG_cmd_fifo_empty_i;
input FTLCMG_cmd_fifo_almost_empty_i;
output FTLCMG_cmd_fifo_rd_en_o;
input [127:0] FTLCMG_cmd_fifo_data_i;
output bar1_wr_en2_o;
output [6:0] bar1_addr2_o;
output [3:0] bar1_wr_be2_o;
output [31:0] bar1_wr_d2_o;
input bar1_wr_ack2_n_i;
output bar1_wr_en3_o;
output [6:0] bar1_addr3_o;
output [3:0] bar1_wr_be3_o;
output [31:0] bar1_wr_d3_o;
input bar1_wr_ack3_n_i;
input bar1_arbiter_busy_i;
input bar1_wr_busy_i;
input mrd_start_i , mwr_start_i;
input mrd_done_i , mwr_done_i;
input req_compl_i;
input recv_fifo_av_i;
// BAR0 Wrapper
//
input [6:0] a_i;
input [3:0] rd_be_i;
output [31:0] rd_d_o;
input wr_en_i;
input [7:0] wr_be_i;
input [31:0] wr_d_i;
output wr_busy_o;
output bar1_wr_en1_o;
output [6:0] bar1_addr1_o;
output [3:0] bar1_wr_be1_o;
output [31:0] bar1_wr_d1_o;
input bar1_wr_ack1_n_i;
input compl_done_i;
output dma_rd_req_flag_o;
input cpld_malformed_i;
// Interrupt Manager
//
input msi_on;
output cfg_interrupt_assert_n_o;
input cfg_interrupt_rdy_n_i;
output cfg_interrupt_n_o;
input cfg_interrupt_legacyclr;
input dma_rd_q_rd_en_i;
output [63:0] dma_rd_q_rd_data_o;
output dma_rd_q_empty_o;
input dma_rd_xfer_done_i;
input [63:0] dma_rd_done_entry_i;
output dma_rd_xfer_done_ack_o;
reg dma_rd_q_wr_en;
wire dma_rd_q_wr_en0 , dma_rd_q_wr_en1;
reg [63:0] dma_rd_q_wr_data;
wire [63:0] dma_rd_q_wr_data0 , dma_rd_q_wr_data1;
wire dma_rd_q_rd_en;
wire [63:0] dma_rd_q_rd_data;
wire dma_rd_q_empty;
wire dma_rd_q_full;
// local Wires
//
wire [9:0] req_queue_av;
wire rd_req_empty;
wire rd_req_rd_en;
wire [127:0] rd_req_data;
wire wr_req_empty;
wire wr_req_rd_en;
wire [127:0] wr_req_data;
wire [31:0] req_cnt;
wire req_unsupported;
wire [15:0] req_queue_depth;
wire resp_empty;
wire [31:0] resp;
wire resp_rd_en;
wire fatal_err = 1'b0;
wire lba_ofr_err = 1'b0;
wire prp_offset_err = 1'b0;
wire id_ob_err = 1'b0;
wire rd_req_done;
wire wr_req_done;
wire [31:0] int_cnt;
wire int_en;
wire int_rd_msk;
wire int_wr_msk;
assign dma_rd_q_rd_en = dma_rd_q_rd_en_i;
assign dma_rd_q_rd_data_o = dma_rd_q_rd_data;
assign dma_rd_q_empty_o = dma_rd_q_empty;
REQ_QUEUE_WRAPPER REQ_QUEUE_WRAP(
.clk(clk),
.rst_n(rst_n),
.en(en),
//receive request queue
.rdata_i(rdata_i),
.rdata_wr_en_i(rdata_wr_en_i),
.req_queue_av_o(req_queue_av),
.req_queue_full_o(req_queue_full_o),
//rd request queue
.rd_req_empty_o(rd_req_empty),
.rd_req_rd_en_i(rd_req_rd_en),
.rd_req_data_o(rd_req_data),
//wr request queue
.wr_req_empty_o(wr_req_empty),
.wr_req_rd_en_i(wr_req_rd_en),
.wr_req_data_o(wr_req_data),
.req_cnt_o(req_cnt),
.req_unsupported_o(req_unsupported)
);
CPM CMD_PROCESS_UNIT(
.clk(clk),
.rst_n(rst_n),
.en(en),
//REQ QUEUE WRAPPER
.rd_req_data_i(rd_req_data),
.rd_req_rd_en_o(rd_req_rd_en),
.rd_req_empty_i(rd_req_empty),
.wr_req_data_i(wr_req_data),
.wr_req_rd_en_o(wr_req_rd_en),
.wr_req_empty_i(wr_req_empty),
//receive cmd fifo
.CMGFTL_cmd_fifo_full_i(CMGFTL_cmd_fifo_full_i),
.CMGFTL_cmd_fifo_almost_full_i(CMGFTL_cmd_fifo_almost_full_i),
.CMGFTL_cmd_fifo_wr_en_o(CMGFTL_cmd_fifo_wr_en_o),
.CMGFTL_cmd_fifo_data_o(CMGFTL_cmd_fifo_data_o),
//send cmd fifo
.FTLCMG_cmd_fifo_empty_i(FTLCMG_cmd_fifo_empty_i),
.FTLCMG_cmd_fifo_almost_empty_i(FTLCMG_cmd_fifo_almost_empty_i),
.FTLCMG_cmd_fifo_rd_en_o(FTLCMG_cmd_fifo_rd_en_o),
.FTLCMG_cmd_fifo_data_i(FTLCMG_cmd_fifo_data_i),
//BAR1 Write Arbiter write port 2
.bar1_wr_en2_o(bar1_wr_en2_o),
.bar1_addr2_o(bar1_addr2_o),
.bar1_wr_be2_o(bar1_wr_be2_o),
.bar1_wr_d2_o(bar1_wr_d2_o),
.bar1_wr_ack2_n_i(bar1_wr_ack2_n_i),
//BAR1 Write Arbiter write port 3
.bar1_wr_en3_o(bar1_wr_en3_o),
.bar1_addr3_o(bar1_addr3_o),
.bar1_wr_be3_o(bar1_wr_be3_o),
.bar1_wr_d3_o(bar1_wr_d3_o),
.bar1_wr_ack3_n_i(bar1_wr_ack3_n_i),
.bar1_arbiter_busy_i(bar1_arbiter_busy_i),
.bar1_wr_busy_i(bar1_wr_busy_i),
//BAR1
.mrd_start_i(mrd_start_i),
.mrd_done_i(mrd_done_i),
.mwr_start_i(mwr_start_i),
.mwr_done_i(mwr_done_i),
.recv_fifo_av_i(recv_fifo_av_i),
//BAR0 register
.req_queue_depth_i(req_queue_depth),
.resp_o(resp),
.resp_empty_o(resp_empty),
.resp_rd_en_i(resp_rd_en),
.fatal_err_o(),
.lba_ofr_err_o(),
.prp_offset_err_o(),
.id_ob_err_o(),
//Interrupt Generator
.rd_req_done_o(rd_req_done),
.wr_req_done_o(wr_req_done),
.dma_rd_q_wr_en_o(dma_rd_q_wr_en0),
.dma_rd_q_wr_data_o(dma_rd_q_wr_data0),
.dma_rd_q_full_i(dma_rd_q_full),
.dma_rd_xfer_done_i(dma_rd_xfer_done_i),
.dma_rd_done_entry_i(dma_rd_done_entry_i),
.dma_rd_xfer_done_ack_o(dma_rd_xfer_done_ack_o),
/*************ouyang***************/
//response queue interface
.response_queue_empty_o(response_queue_empty_o),
.response_queue_data_o(response_queue_data_o),
.response_queue_rd_en_i(response_queue_rd_en_i) //read enable signal for response queue
/**********************************/
);
BAR0_WRAPPER BAR0_WRAP(
.clk(clk),
.rst_n(rst_n),
.en(en),
//read and write port
.a_i(a_i),
.wr_en_i(wr_en_i),
.wr_be_i(wr_be_i),
.wr_busy_o(wr_busy_o),
.rd_d_o(rd_d_o),
.rd_be_i(rd_be_i),
.wr_d_i(wr_d_i),
//BAR1 Write Arbiter write port 1
.bar1_wr_en1_o(bar1_wr_en1_o),
.bar1_addr1_o(bar1_addr1_o),
.bar1_wr_be1_o(bar1_wr_be1_o),
.bar1_wr_d1_o(bar1_wr_d1_o),
.bar1_wr_ack1_n_i(bar1_wr_ack1_n_i),
.bar1_arbiter_busy_i(bar1_arbiter_busy_i),
.bar1_wr_busy_i(bar1_wr_busy_i),
//response message read port
.resp_i(resp),
.resp_empty_i(resp_empty),
.resp_rd_en_o(resp_rd_en),
.req_compl_i(req_compl_i),
.mrd_start_i(mrd_start_i),
.mrd_done_i(mrd_done_i),
.compl_done_i(compl_done_i),
.dma_rd_req_flag_o(dma_rd_req_flag_o),
.req_queue_av_i(req_queue_av),
.req_queue_depth_o(req_queue_depth),
.int_cnt_i(int_cnt),
.req_cnt_i(req_cnt),
//error report
.cpld_malformed_i(cpld_malformed_i),
.fatal_err_i(fatal_err),
.req_unsupported_i(req_unsupported),
.lba_ofr_err_i(lba_ofr_err),
.prp_offset_err_i(prp_offset_err),
.id_ob_err_i(id_ob_err),
.cont_rdy_o(),
//INT ctrl
.int_en_o(int_en),
.int_rd_msk_o(int_rd_msk),
.int_wr_msk_o(int_wr_msk),
.dma_rd_q_wr_en_o(dma_rd_q_wr_en1),
.dma_rd_q_wr_data_o(dma_rd_q_wr_data1),
.dma_rd_q_full_i(dma_rd_q_full),
/*************ouyang***************/
//msix interface
.msg_lower_addr_o(msg_lower_addr_o),
.msg_upper_addr_o(msg_upper_addr_o),
.msg_data_o(msg_data_o),
// the base addr for response queue
.response_queue_addr_o(response_queue_addr_o),
//count enable for response queue offset
.response_queue_addr_offset_cnt_en_i(response_queue_addr_offset_cnt_en_i),
.interrupt_block_o(interrupt_block_o),
.response_queue_cur_offset_reg_o(response_queue_cur_offset_reg_o),
.response_queue_addr_offset_o(response_queue_addr_offset_o),
.response_queue_num_i(response_queue_data_o[15:10])
/**********************************/
);
INT_MANAGER INT_CTRL(
.clk(clk),
.rst_n(rst_n),
.en(en),
.int_en(int_en),
.rd_int_msk_i(int_rd_msk),
.wr_int_msk_i(int_wr_msk),
.rd_req_done_i(rd_req_done),
.wr_req_done_i(wr_req_done),
.int_cnt_o(int_cnt),
.msi_on(msi_on),
.cfg_interrupt_assert_n_o(cfg_interrupt_assert_n_o),
.cfg_interrupt_rdy_n_i(cfg_interrupt_rdy_n_i),
.cfg_interrupt_n_o(cfg_interrupt_n_o),
.cfg_interrupt_legacyclr(cfg_interrupt_legacyclr)
);
wire srst = !rst_n || !en;
always @ ( * ) begin
if( !rst_n || !en ) begin
dma_rd_q_wr_en = 1'b0;
dma_rd_q_wr_data = 64'b0;
end
else begin
if( dma_rd_q_wr_en0 && !dma_rd_q_wr_en1 ) begin
dma_rd_q_wr_en = 1'b1;
dma_rd_q_wr_data = dma_rd_q_wr_data0;
end else if( dma_rd_q_wr_en1 && !dma_rd_q_wr_en0 ) begin
dma_rd_q_wr_en = 1'b1;
dma_rd_q_wr_data = dma_rd_q_wr_data1;
end else begin
dma_rd_q_wr_en = 1'b0;
dma_rd_q_wr_data = 64'b0;
end
end
end
DMA_READ_QUEUE DMA_READ_QUEUE (
.clk(clk), // input clk
.srst(srst), // input srst
.din(dma_rd_q_wr_data), // input [31 : 0] din
.wr_en(dma_rd_q_wr_en), // input wr_en
.rd_en(dma_rd_q_rd_en), // input rd_en
.dout(dma_rd_q_rd_data), // output [31 : 0] dout
.full(dma_rd_q_full), // output full
.empty(dma_rd_q_empty) // output empty
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXTP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DLXTP_PP_SYMBOL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXTP_PP_SYMBOL_V
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_traffic_gen:2.0
// IP Revision: 5
(* X_CORE_INFO = "axi_traffic_gen_v2_0_top,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "axi_traffic_gen_0,axi_traffic_gen_v2_0_top,{}" *)
(* CORE_GENERATION_INFO = "axi_traffic_gen_0,axi_traffic_gen_v2_0_top,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_traffic_gen,x_ipVersion=2.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=virtex7,C_BASEADDR=0x00000000,C_HIGHADDR=0x0000FFFF,C_ZERO_INVALID=1,C_NO_EXCL=0,C_S_AXI_DATA_WIDTH=32,C_S_AXI_AWUSER_WIDTH=8,C_S_AXI_ARUSER_WIDTH=8,C_S_AXI_ID_WIDTH=1,C_M_AXI_THREAD_ID_WIDTH=1,C_M_AXI_DATA_WIDTH=32,C_M_AXI_AWUSER_WIDTH=8,C_M_AXI_ARUSER_WIDTH=8,C_AXIS1_HAS_TKEEP=1,C_AXIS1_HAS_TSTRB=1,C_AXIS2_HAS_TKEEP=0,C_AXIS2_HAS_TSTRB=0,C_AXIS_TDATA_WIDTH=32,C_AXIS_TUSER_WIDTH=8,C_AXIS_TID_WIDTH=8,C_AXIS_TDEST_WIDTH=8,C_ATG_BASIC_AXI4=0,C_ATG_REPEAT_TYPE=0,C_ATG_HLTP_MODE=0,C_ATG_STATIC=0,C_ATG_SYSTEM_INIT=1,C_ATG_SYSTEM_TEST=0,C_ATG_STREAMING=0,C_ATG_STREAMING_MST_ONLY=1,C_ATG_STREAMING_MST_LPBK=0,C_ATG_STREAMING_SLV_LPBK=0,C_ATG_STREAMING_MAX_LEN_BITS=16,C_AXIS_SPARSE_EN=1,C_ATG_SLAVE_ONLY=0,C_ATG_STATIC_WR_ADDRESS=0x12A00000,C_ATG_STATIC_RD_ADDRESS=0x13A00000,C_ATG_STATIC_WR_HIGH_ADDRESS=0x12A00FFF,C_ATG_STATIC_RD_HIGH_ADDRESS=0x13A00FFF,C_ATG_STATIC_INCR=0,C_ATG_STATIC_EN_READ=1,C_ATG_STATIC_EN_WRITE=1,C_ATG_STATIC_FREE_RUN=1,C_ATG_STATIC_RD_PIPELINE=3,C_ATG_STATIC_WR_PIPELINE=3,C_ATG_STATIC_TRANGAP=256,C_ATG_STATIC_LENGTH=16,C_ATG_SYSTEM_INIT_DATA_MIF=axi_traffic_gen_0_data.mif,C_ATG_SYSTEM_INIT_ADDR_MIF=axi_traffic_gen_0_addr.mif,C_ATG_SYSTEM_INIT_CTRL_MIF=axi_traffic_gen_0_ctrl.mif,C_ATG_SYSTEM_INIT_MASK_MIF=axi_traffic_gen_0_mask.mif,C_ATG_MIF_DATA_DEPTH=16,C_ATG_MIF_ADDR_BITS=4,C_ATG_SYSTEM_CMD_MAX_RETRY=256,C_ATG_SYSTEM_TEST_MAX_CLKS=265000,C_ATG_SYSTEM_MAX_CHANNELS=00000000000000000000000000000001,C_ATG_SYSTEM_CH1_LOW=0x00000000,C_ATG_SYSTEM_CH1_HIGH=0xFFFFFFFF,C_ATG_SYSTEM_CH2_LOW=0x00000100,C_ATG_SYSTEM_CH2_HIGH=0x000001FF,C_ATG_SYSTEM_CH3_LOW=0x00000200,C_ATG_SYSTEM_CH3_HIGH=0x000002FF,C_ATG_SYSTEM_CH4_LOW=0x00000300,C_ATG_SYSTEM_CH4_HIGH=0x000003FF,C_ATG_SYSTEM_CH5_LOW=0x00000400,C_ATG_SYSTEM_CH5_HIGH=0x000004FF,C_RAMINIT_CMDRAM0_F=axi_traffic_gen_0_default_cmdram.mif,C_RAMINIT_CMDRAM1_F=NONE,C_RAMINIT_CMDRAM2_F=NONE,C_RAMINIT_CMDRAM3_F=NONE,C_RAMINIT_SRAM0_F=axi_traffic_gen_0_default_mstram.mif,C_RAMINIT_PARAMRAM0_F=axi_traffic_gen_0_default_prmram.mif}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module axi_traffic_gen_0 (
s_axi_aclk,
s_axi_aresetn,
m_axi_lite_ch1_awaddr,
m_axi_lite_ch1_awprot,
m_axi_lite_ch1_awvalid,
m_axi_lite_ch1_awready,
m_axi_lite_ch1_wdata,
m_axi_lite_ch1_wstrb,
m_axi_lite_ch1_wvalid,
m_axi_lite_ch1_wready,
m_axi_lite_ch1_bresp,
m_axi_lite_ch1_bvalid,
m_axi_lite_ch1_bready,
done,
status
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_LITE_CH1 AWADDR" *)
output wire [31 : 0] m_axi_lite_ch1_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_LITE_CH1 AWPROT" *)
output wire [2 : 0] m_axi_lite_ch1_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_LITE_CH1 AWVALID" *)
output wire m_axi_lite_ch1_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_LITE_CH1 AWREADY" *)
input wire m_axi_lite_ch1_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_LITE_CH1 WDATA" *)
output wire [31 : 0] m_axi_lite_ch1_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_LITE_CH1 WSTRB" *)
output wire [3 : 0] m_axi_lite_ch1_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_LITE_CH1 WVALID" *)
output wire m_axi_lite_ch1_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_LITE_CH1 WREADY" *)
input wire m_axi_lite_ch1_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_LITE_CH1 BRESP" *)
input wire [1 : 0] m_axi_lite_ch1_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_LITE_CH1 BVALID" *)
input wire m_axi_lite_ch1_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_LITE_CH1 BREADY" *)
output wire m_axi_lite_ch1_bready;
output wire done;
output wire [31 : 0] status;
axi_traffic_gen_v2_0_top #(
.C_FAMILY("virtex7"),
.C_BASEADDR('H00000000),
.C_HIGHADDR('H0000FFFF),
.C_ZERO_INVALID(1),
.C_NO_EXCL(0),
.C_S_AXI_DATA_WIDTH(32),
.C_S_AXI_AWUSER_WIDTH(8),
.C_S_AXI_ARUSER_WIDTH(8),
.C_S_AXI_ID_WIDTH(1),
.C_M_AXI_THREAD_ID_WIDTH(1),
.C_M_AXI_DATA_WIDTH(32),
.C_M_AXI_AWUSER_WIDTH(8),
.C_M_AXI_ARUSER_WIDTH(8),
.C_AXIS1_HAS_TKEEP(1),
.C_AXIS1_HAS_TSTRB(1),
.C_AXIS2_HAS_TKEEP(0),
.C_AXIS2_HAS_TSTRB(0),
.C_AXIS_TDATA_WIDTH(32),
.C_AXIS_TUSER_WIDTH(8),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(8),
.C_ATG_BASIC_AXI4(0),
.C_ATG_REPEAT_TYPE(0),
.C_ATG_HLTP_MODE(0),
.C_ATG_STATIC(0),
.C_ATG_SYSTEM_INIT(1),
.C_ATG_SYSTEM_TEST(0),
.C_ATG_STREAMING(0),
.C_ATG_STREAMING_MST_ONLY(1),
.C_ATG_STREAMING_MST_LPBK(0),
.C_ATG_STREAMING_SLV_LPBK(0),
.C_ATG_STREAMING_MAX_LEN_BITS(16),
.C_AXIS_SPARSE_EN(1),
.C_ATG_SLAVE_ONLY(0),
.C_ATG_STATIC_WR_ADDRESS('H12A00000),
.C_ATG_STATIC_RD_ADDRESS('H13A00000),
.C_ATG_STATIC_WR_HIGH_ADDRESS('H12A00FFF),
.C_ATG_STATIC_RD_HIGH_ADDRESS('H13A00FFF),
.C_ATG_STATIC_INCR(0),
.C_ATG_STATIC_EN_READ(1),
.C_ATG_STATIC_EN_WRITE(1),
.C_ATG_STATIC_FREE_RUN(1),
.C_ATG_STATIC_RD_PIPELINE(3),
.C_ATG_STATIC_WR_PIPELINE(3),
.C_ATG_STATIC_TRANGAP(256),
.C_ATG_STATIC_LENGTH(16),
.C_ATG_SYSTEM_INIT_DATA_MIF("axi_traffic_gen_0_data.mif"),
.C_ATG_SYSTEM_INIT_ADDR_MIF("axi_traffic_gen_0_addr.mif"),
.C_ATG_SYSTEM_INIT_CTRL_MIF("axi_traffic_gen_0_ctrl.mif"),
.C_ATG_SYSTEM_INIT_MASK_MIF("axi_traffic_gen_0_mask.mif"),
.C_ATG_MIF_DATA_DEPTH(16),
.C_ATG_MIF_ADDR_BITS(4),
.C_ATG_SYSTEM_CMD_MAX_RETRY(256),
.C_ATG_SYSTEM_TEST_MAX_CLKS(265000),
.C_ATG_SYSTEM_MAX_CHANNELS('B00000000000000000000000000000001),
.C_ATG_SYSTEM_CH1_LOW('H00000000),
.C_ATG_SYSTEM_CH1_HIGH('HFFFFFFFF),
.C_ATG_SYSTEM_CH2_LOW('H00000100),
.C_ATG_SYSTEM_CH2_HIGH('H000001FF),
.C_ATG_SYSTEM_CH3_LOW('H00000200),
.C_ATG_SYSTEM_CH3_HIGH('H000002FF),
.C_ATG_SYSTEM_CH4_LOW('H00000300),
.C_ATG_SYSTEM_CH4_HIGH('H000003FF),
.C_ATG_SYSTEM_CH5_LOW('H00000400),
.C_ATG_SYSTEM_CH5_HIGH('H000004FF),
.C_RAMINIT_CMDRAM0_F("axi_traffic_gen_0_default_cmdram.mif"),
.C_RAMINIT_CMDRAM1_F("NONE"),
.C_RAMINIT_CMDRAM2_F("NONE"),
.C_RAMINIT_CMDRAM3_F("NONE"),
.C_RAMINIT_SRAM0_F("axi_traffic_gen_0_default_mstram.mif"),
.C_RAMINIT_PARAMRAM0_F("axi_traffic_gen_0_default_prmram.mif")
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.core_ext_start(1'B0),
.core_ext_stop(1'B0),
.s_axi_awid(1'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(1'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awuser(8'B0),
.s_axi_awvalid(1'B0),
.s_axi_awready(),
.s_axi_wlast(1'B0),
.s_axi_wdata(32'B0),
.s_axi_wstrb(4'B0),
.s_axi_wvalid(1'B0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'B0),
.s_axi_arid(1'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(1'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_aruser(8'B0),
.s_axi_arvalid(1'B0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rlast(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rvalid(),
.s_axi_rready(1'B0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'B0),
.m_axi_wlast(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wvalid(),
.m_axi_wready(1'B0),
.m_axi_bid(1'B0),
.m_axi_bresp(2'B0),
.m_axi_bvalid(1'B0),
.m_axi_bready(),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'B0),
.m_axi_rid(1'B0),
.m_axi_rlast(1'B0),
.m_axi_rdata(32'B0),
.m_axi_rresp(2'B0),
.m_axi_rvalid(1'B0),
.m_axi_rready(),
.m_axis_1_tready(1'B1),
.m_axis_1_tvalid(),
.m_axis_1_tlast(),
.m_axis_1_tdata(),
.m_axis_1_tstrb(),
.m_axis_1_tkeep(),
.m_axis_1_tuser(),
.m_axis_1_tid(),
.m_axis_1_tdest(),
.s_axis_1_tready(),
.s_axis_1_tvalid(1'B0),
.s_axis_1_tlast(1'B0),
.s_axis_1_tdata(32'B0),
.s_axis_1_tstrb(4'HF),
.s_axis_1_tkeep(4'HF),
.s_axis_1_tuser(8'B0),
.s_axis_1_tid(8'B0),
.s_axis_1_tdest(8'B0),
.axis_err_count(),
.s_axis_2_tready(),
.s_axis_2_tvalid(1'B0),
.s_axis_2_tlast(1'B0),
.s_axis_2_tdata(32'B0),
.s_axis_2_tstrb(4'HF),
.s_axis_2_tkeep(4'HF),
.s_axis_2_tuser(8'B0),
.s_axis_2_tid(8'B0),
.s_axis_2_tdest(8'B0),
.m_axis_2_tready(1'B1),
.m_axis_2_tvalid(),
.m_axis_2_tlast(),
.m_axis_2_tdata(),
.m_axis_2_tstrb(),
.m_axis_2_tkeep(),
.m_axis_2_tuser(),
.m_axis_2_tid(),
.m_axis_2_tdest(),
.irq_out(),
.err_out(),
.m_axi_lite_ch1_awaddr(m_axi_lite_ch1_awaddr),
.m_axi_lite_ch1_awprot(m_axi_lite_ch1_awprot),
.m_axi_lite_ch1_awvalid(m_axi_lite_ch1_awvalid),
.m_axi_lite_ch1_awready(m_axi_lite_ch1_awready),
.m_axi_lite_ch1_wdata(m_axi_lite_ch1_wdata),
.m_axi_lite_ch1_wstrb(m_axi_lite_ch1_wstrb),
.m_axi_lite_ch1_wvalid(m_axi_lite_ch1_wvalid),
.m_axi_lite_ch1_wready(m_axi_lite_ch1_wready),
.m_axi_lite_ch1_bresp(m_axi_lite_ch1_bresp),
.m_axi_lite_ch1_bvalid(m_axi_lite_ch1_bvalid),
.m_axi_lite_ch1_bready(m_axi_lite_ch1_bready),
.m_axi_lite_ch1_araddr(),
.m_axi_lite_ch1_arvalid(),
.m_axi_lite_ch1_arready(1'B0),
.m_axi_lite_ch1_rdata(32'B0),
.m_axi_lite_ch1_rvalid(1'B0),
.m_axi_lite_ch1_rresp(2'B0),
.m_axi_lite_ch1_rready(),
.m_axi_lite_ch2_awaddr(),
.m_axi_lite_ch2_awprot(),
.m_axi_lite_ch2_awvalid(),
.m_axi_lite_ch2_awready(1'B0),
.m_axi_lite_ch2_wdata(),
.m_axi_lite_ch2_wstrb(),
.m_axi_lite_ch2_wvalid(),
.m_axi_lite_ch2_wready(1'B0),
.m_axi_lite_ch2_bresp(2'B0),
.m_axi_lite_ch2_bvalid(1'B0),
.m_axi_lite_ch2_bready(),
.m_axi_lite_ch2_araddr(),
.m_axi_lite_ch2_arvalid(),
.m_axi_lite_ch2_arready(1'B0),
.m_axi_lite_ch2_rdata(32'B0),
.m_axi_lite_ch2_rvalid(1'B0),
.m_axi_lite_ch2_rresp(2'B0),
.m_axi_lite_ch2_rready(),
.m_axi_lite_ch3_awaddr(),
.m_axi_lite_ch3_awprot(),
.m_axi_lite_ch3_awvalid(),
.m_axi_lite_ch3_awready(1'B0),
.m_axi_lite_ch3_wdata(),
.m_axi_lite_ch3_wstrb(),
.m_axi_lite_ch3_wvalid(),
.m_axi_lite_ch3_wready(1'B0),
.m_axi_lite_ch3_bresp(2'B0),
.m_axi_lite_ch3_bvalid(1'B0),
.m_axi_lite_ch3_bready(),
.m_axi_lite_ch3_araddr(),
.m_axi_lite_ch3_arvalid(),
.m_axi_lite_ch3_arready(1'B0),
.m_axi_lite_ch3_rdata(32'B0),
.m_axi_lite_ch3_rvalid(1'B0),
.m_axi_lite_ch3_rresp(2'B0),
.m_axi_lite_ch3_rready(),
.m_axi_lite_ch4_awaddr(),
.m_axi_lite_ch4_awprot(),
.m_axi_lite_ch4_awvalid(),
.m_axi_lite_ch4_awready(1'B0),
.m_axi_lite_ch4_wdata(),
.m_axi_lite_ch4_wstrb(),
.m_axi_lite_ch4_wvalid(),
.m_axi_lite_ch4_wready(1'B0),
.m_axi_lite_ch4_bresp(2'B0),
.m_axi_lite_ch4_bvalid(1'B0),
.m_axi_lite_ch4_bready(),
.m_axi_lite_ch4_araddr(),
.m_axi_lite_ch4_arvalid(),
.m_axi_lite_ch4_arready(1'B0),
.m_axi_lite_ch4_rdata(32'B0),
.m_axi_lite_ch4_rvalid(1'B0),
.m_axi_lite_ch4_rresp(2'B0),
.m_axi_lite_ch4_rready(),
.m_axi_lite_ch5_awaddr(),
.m_axi_lite_ch5_awprot(),
.m_axi_lite_ch5_awvalid(),
.m_axi_lite_ch5_awready(1'B0),
.m_axi_lite_ch5_wdata(),
.m_axi_lite_ch5_wstrb(),
.m_axi_lite_ch5_wvalid(),
.m_axi_lite_ch5_wready(1'B0),
.m_axi_lite_ch5_bresp(2'B0),
.m_axi_lite_ch5_bvalid(1'B0),
.m_axi_lite_ch5_bready(),
.m_axi_lite_ch5_araddr(),
.m_axi_lite_ch5_arvalid(),
.m_axi_lite_ch5_arready(1'B0),
.m_axi_lite_ch5_rdata(32'B0),
.m_axi_lite_ch5_rvalid(1'B0),
.m_axi_lite_ch5_rresp(2'B0),
.m_axi_lite_ch5_rready(),
.done(done),
.status(status)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_2_V
`define SKY130_FD_SC_LP__SDFRTP_2_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfrtp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfrtp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1P_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__INPUTISO1P_PP_BLACKBOX_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inputiso1p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1P_PP_BLACKBOX_V
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
// Date : Tue Nov 10 13:18:32 2015
// Host : centennial.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.1 (Maipo)
// Command : write_verilog -force -mode funcsim
// /afs/ece.cmu.edu/usr/rmrobert/Private/18545/Atari7800/new_atari/project_1/project_1.srcs/sources_1/ip/BIOS_ROM/BIOS_ROM_funcsim.v
// Design : BIOS_ROM
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "BIOS_ROM,blk_mem_gen_v8_2,{}" *) (* core_generation_info = "BIOS_ROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=BIOS_ROM.mif,C_INIT_FILE=BIOS_ROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=4096,C_READ_DEPTH_B=4096,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.535699 mW}" *) (* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2015.2" *)
(* NotValidForBitStream *)
module BIOS_ROM
(clka,
ena,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [11:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [7:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [7:0]douta;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [7:0]NLW_U0_doutb_UNCONNECTED;
wire [11:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [7:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "12" *)
(* C_ADDRB_WIDTH = "12" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.535699 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "BIOS_ROM.mem" *)
(* C_INIT_FILE_NAME = "BIOS_ROM.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "4096" *)
(* C_READ_DEPTH_B = "4096" *)
(* C_READ_WIDTH_A = "8" *)
(* C_READ_WIDTH_B = "8" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "4096" *)
(* C_WRITE_DEPTH_B = "4096" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "8" *)
(* C_WRITE_WIDTH_B = "8" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
BIOS_ROM_blk_mem_gen_v8_2 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[7:0]),
.eccpipece(1'b0),
.ena(ena),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[11:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rstb(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[11:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[7:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module BIOS_ROM_blk_mem_gen_generic_cstr
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
BIOS_ROM_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module BIOS_ROM_blk_mem_gen_prim_width
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
BIOS_ROM_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module BIOS_ROM_blk_mem_gen_prim_wrapper_init
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71 ;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00F46C48),
.INIT_01(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_02(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_10(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_11(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_12(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_13(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_14(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_15(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_16(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_17(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_18(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_19(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_20(256'hFFFD2DFFFCADF410CA88EAD0FD80D9FE00BD7FA2FFA0018516A926C24C26C24C),
.INIT_21(256'hF9ADC5D0F029F049FFF8ADCED0FFC9FE09FFF8ADD4F0FFFD0DFFFCADDCF0FFC9),
.INIT_22(256'hA9253620A7B0FFFDCD01E9AE9040C924068DEE85F029FFF9ADBCD003C90B29FF),
.INIT_23(256'hD0F8C088180099FF00B97FA048FAD0CA18009D8A00A2018516A9241B20F08500),
.INIT_24(256'h241B20EED0FFC92406AD2406EE4823FF2068241B20240A8D24A924098D2EA9F5),
.INIT_25(256'h06AD2406CE4823FF2068241B202406CE240A8D24A924098D36A9241220241220),
.INIT_26(256'h8D07291A00ADF110CA1A009D18885D18505D1800BD77A23C8560A9EEB0EEC524),
.INIT_27(256'hA226C24C26B94CF510CA06D01A00DD2000BD77A220009D1A009D04A200A91A00),
.INIT_28(256'h0C10F0C60860FAD0E818003E00A260F0D0E818009D2DD5B9A8FF007D18007D00),
.INIT_29(256'h918E5572B6626792D0E10983F7EECAAB65C76028018516A9FC30F0A5018502A9),
.INIT_2A(256'hEDB890FA94A38734FC17A98473FBD1383108C8AF45063DE6B7592078BE81C5DC),
.INIT_2B(256'hEC352656F6E3E741807FE4BC1011B9A7519D605A6D0DB38253F3D9430A5B3BCE),
.INIT_2C(256'h3E022B7718805805B18C42B01C4A971513A43FA2BFCFEF4652AC9EF47F0CDFD6),
.INIT_2D(256'h93DE0307F94B2EE80E762D2AF819579B9FD88B79144FF1EB8A0B6ECB6A1A49A8),
.INIT_2E(256'hC02F0FAD9689AA391FFE85361E2295A0235EE01DCCA1D2DA7A7DF0B2E5D47E16),
.INIT_2F(256'h54BD9986BB752C7B33D770A6CD7CC1DD2574AE8F401B5F21F5A5C3EA245D2747),
.INIT_30(256'h440164DB3A88C2E94D04E26B69D59C98C61237294EC4615CBA8D4C4832636C9A),
.INIT_31(256'h9DFF80BDE586E48677A2EE0965F7ABC783CAD3C96866B43C7150FD2830F2B56F),
.INIT_32(256'h10CA19019DFED5BDE48677A2F2C6257B20FB8420018502A9F410CA20009D1901),
.INIT_33(256'hE5A426392060F710CA20009D1800BD77A225728DE0A5F2C625E120E385E1A5F7),
.INIT_34(256'h7C8C26748C266E8CC818008DFAD0CA18009D26718D00A9AA48E2651898E184C8),
.INIT_35(256'h09F025D93D2000B9E1A41B30E1C62681CE267CCE2674CE266ECE00A226818C26),
.INIT_36(256'h4020100804020160E08501A9E1856825A44CE83008E0E8266A2026728D2662BD),
.INIT_37(256'h8E268C8E26A98ECA26AC8E268F8E18008E00A2E185E085E4E538E3A526392080),
.INIT_38(256'h2662BD1730E1C6269FEE269AEE2692EE268CEE26A9EE07A2269F8E269A8E2692),
.INIT_39(256'h00A0E286E8E4A660E185E3A526084CEC10CA268820039026A62026AD8D26908D),
.INIT_3A(256'h3007C0F610CA19009D2A1900BD18E2A626598D2662B9C826558D2662B919008C),
.INIT_3B(256'h00691700B90C90F410881800991900791800B918E2A4211F1E1D1C1B1A1960E2),
.INIT_3C(256'h009900E91700B90CB0F410881800991900F91800B938E2A46026794C88170099),
.INIT_3D(256'h6CF89A018616A226A84CC8FBF0E2C46001F01900D91800B900A06026974C8817),
.INIT_3E(256'hF9D02AE0E803950185AA00A904804CF710CA04809DF7D4BD7FA2018502A9FFFC),
.INIT_3F(256'h85EA0F851C851B85118504CB2004CB2001108D9AFD10CA04A22330EA04A90285),
.INIT_40(256'h608DF1188D068502A90C3002241ED0F1128D098502A9093003240430EA00A902),
.INIT_41(256'hFFFFFFFFFFFFFFEAFFFC6C0885FDA9D9300224EA04CB201B8508A92C850ED0F4),
.INIT_42(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_43(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_44(256'hA0F91DBD05A2208500A93C857FA9F48512A9F585FBA9018502A9D87801851DA9),
.INIT_45(256'h0BD080C520808D43A9E510CAEDD0881FD02100D921009927D02000D920009900),
.INIT_46(256'h4C02A0F8804C01A00AD01800CD18008DF8804C04A0F9384C03D00180CD21808D),
.INIT_47(256'hF91DBD05A2F385F92BB9F185F923B9F48407A0F285F08500A9F8804C03A0F880),
.INIT_48(256'h55FF00FB174CD710F4A4F4C6E910CAF1D088CFD0F2D1F291D0D0F0D1F09100A0),
.INIT_49(256'h0330F510F7F0AAA9F8804C00A01F1E1D1C1B1A191823222726252423220F69AA),
.INIT_4A(256'h00C9F9334C03F0F9334C0310DF30E1D000A9E5D0AAC5AA85F9334C03D0F9334C),
.INIT_4B(256'hB3D001AAEC01AA8EBBF056E055A2F9334C0390C6B001C9F9334C03B0CF90D1D0),
.INIT_4C(256'hAAC9984ED00155EC488A55D0AAC968E89ACAA5D00155CC01558CADF0ABC0AAA4),
.INIT_4D(256'h00D92DD055C5000099FF4936D0AAC93AD0AAC500B540D055C0A80100BDAA49D0),
.INIT_4E(256'h85EEA90ED02121CDF09115D0CCC54681F085CCA9F18520A923D020ABDD28D001),
.INIT_4F(256'h5569EDD0AAC9F1F0F310F5B0EA55691855A9F9334CF9EB4C00F06CF185F9A9F0),
.INIT_50(256'hE8AAFFA9CFD0D130D390AAE918D8D0ABC9DCF0DE10E0B055E9E4D0E630E890EA),
.INIT_51(256'hC619D0F0C41DD0F0E6F08523D0C826F08829D0C8A82DD0FFE0311033F0CA36D0),
.INIT_52(256'hB00AFA900AF9334C03F0AAC96A6A6A07D052C92A2A2A18AAA911D0F0C515F0F0),
.INIT_53(256'hC91B295529DDD05FC91B0955A9E5D00AC94AEAB04AED904A0549F2D050C90AF7),
.INIT_54(256'hB8D0FAC968BDD08DC968C2D052E0BAFA584CFA9120CDD04EC91B495509D5D011),
.INIT_55(256'h2485248502100650F3242285EFA50FA23C8543A9488AFA584C6048E6A948F8A9),
.INIT_56(256'h0609F029EFA527850E09F0293C8640A2EC10CA22850FE902B010C910E9382485),
.INIT_57(256'h0290106918EFA511906069F3A51910F1C6268503090F690290406918F0292585),
.INIT_58(256'hE0E80195AA00A99AFFFB144C4068AA68F08502A9F38500A9F185F2A5EF850F69),
.INIT_59(256'hF700BD25009DF600BD24009DF500BD23009DF400BD208600A2018502A9F9D02C),
.INIT_5A(256'hBD19849DFCC6BD1F849DFC4BBD2A3000E022009DFBBEBD27009DF800BD26009D),
.INIT_5B(256'hABD0CA1E849DFE96BD1D849DFE57BD1C849DFE18BD1B849DFDB4BD1A849DFD3D),
.INIT_5C(256'h27852EA9268556A9258566A9EF8549A9F285F18503A932F00429FFF9AD23064C),
.INIT_5D(256'h191F84603C8543A92C851FA9308584A9FC102824FC302824F585FAA9F485AAA9),
.INIT_5E(256'h46191B91000048191C8D00004A191C8900004A191C850000BB1F1940840000BB),
.INIT_5F(256'h2CAF0000501C2CAF001C2CAF00003E1917A600003E19179D0000421919960000),
.INIT_60(256'h000028192DE8000028192DD5000028192DC2000028192DAF0000501D2CAF001D),
.INIT_61(256'h2DC20000281B2DAF0000281A2DE80000281A2DD50000281A2DC20000281A2DAF),
.INIT_62(256'h051322050D228500220300220F00220F00220F06220F0000281B2DD50000281B),
.INIT_63(256'h3722025122003722024B220037220100220F3122052B22052522051F22051922),
.INIT_64(256'h22003722026F22003722026922003722026322003722025D2200372202572200),
.INIT_65(256'h0F00220F00220F00220F4122018722003722028122003722027B220037220275),
.INIT_66(256'hFF1FF87F807F80FF07FC817FE00F7EF8871FC08F7FFC808F7F7C0000220F0022),
.INIT_67(256'hFFFF3F0000C000F0FFFFFF3F000C00003E0000807F0000001FFEFF03807F00F0),
.INIT_68(256'h0F0000FF0300C0FF0000FC03FCFFFF3F0000F003F0FFFFFF3F003F0000FC0300),
.INIT_69(256'h8F7F7C00FCC33F00F03F0000FF3F0000FF0300F0FF0300FCC3FF03F03F0000FC),
.INIT_6A(256'hF01FFEFF07807F00F8FF1FE07F807F80FF01FC837FF00F7EF8871F808F7F7C80),
.INIT_6B(256'h0300FFC03F00FCC3FF00F03F00C03FFF0000FF0300FCF30F00FE0300807F0000),
.INIT_6C(256'hFC03C0FFF03F00FC03F00F00FF03C03F00FF00FC03FC3FF03F00F00FFC0300FF),
.INIT_6D(256'h7EF8871F808F7F7C808F7F7C00FC03F03FF03F00FFFFFF3F00FF03F0FFFFFF03),
.INIT_6E(256'hFF0FFE0F00807F0000FC1FFEFF0F807F00FCFF1FC0FF807FC0FF00F8837FF007),
.INIT_6F(256'hF03FF03F0000FF03FF03FF0300F03FFC03FC0FF03FC0FFFFFFFF00FF03FCFFFF),
.INIT_70(256'h808F7F7C808F7F7C00FCC3FF00F03FFC0F0000FC0FFFC3FF0000C0FFFC03FF03),
.INIT_71(256'h00807F0000FF1FFEFF1F807F00FEFF1F80FF807FC07F00F8837FF0077CF8870F),
.INIT_72(256'h0F808F7F7C808F7F7C005555555555555555555555555555555555555555FE3F),
.INIT_73(256'hFF00807F00C0FF1FE0FF1F807F00FEFF0100FF817FE03F00F0837FF003FCF8C7),
.INIT_74(256'hC70F808F7F7C808F7F7C00AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAFE),
.INIT_75(256'hFEFF01807F00E0FF1F00FE3F807F00FF1F0000FE817FE01F00F0877FF803FCF8),
.INIT_76(256'h4B8158601B0812B4C6C9CA095555555555555555555555555555555555555555),
.INIT_77(256'h6A9306CD8A2DAFECC53B000A8DFAE2E22FBC7C3B847932DC7BA025D9BFD80186),
.INIT_78(256'hFEC855510C4723EF20B5066DF7E873D37168A20CCE8CEF3653B26AC4774614A5),
.INIT_79(256'hA1BD870A801D8F71B388CC222D3B583CF86305D8C4E276B03867A7203FC458F4),
.INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEA3942806846ECD3E270E92359),
.INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7F(256'h00F933FB17F000F72D34383931294328434347FFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],douta}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module BIOS_ROM_blk_mem_gen_top
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
BIOS_ROM_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "12" *) (* C_ADDRB_WIDTH = "12" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.535699 mW" *) (* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *) (* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) (* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) (* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *) (* C_INIT_FILE = "BIOS_ROM.mem" *) (* C_INIT_FILE_NAME = "BIOS_ROM.mif" *)
(* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *) (* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) (* C_READ_DEPTH_A = "4096" *)
(* C_READ_DEPTH_B = "4096" *) (* C_READ_WIDTH_A = "8" *) (* C_READ_WIDTH_B = "8" *)
(* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "4096" *)
(* C_WRITE_DEPTH_B = "4096" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "8" *) (* C_WRITE_WIDTH_B = "8" *) (* C_XDEVICEFAMILY = "zynq" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_2" *) (* downgradeipidentifiedwarnings = "yes" *)
module BIOS_ROM_blk_mem_gen_v8_2
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [11:0]addra;
input [7:0]dina;
output [7:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [11:0]addrb;
input [7:0]dinb;
output [7:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [11:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [7:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [7:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [11:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [11:0]addra;
wire [11:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]dinb;
wire [7:0]douta;
wire eccpipece;
wire ena;
wire enb;
wire injectdbiterr;
wire injectsbiterr;
wire regcea;
wire regceb;
wire rsta;
wire rstb;
wire s_aclk;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_injectdbiterr;
wire s_axi_injectsbiterr;
wire s_axi_rready;
wire [7:0]s_axi_wdata;
wire s_axi_wlast;
wire [0:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sleep;
wire [0:0]wea;
wire [0:0]web;
assign dbiterr = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
BIOS_ROM_blk_mem_gen_v8_2_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *)
module BIOS_ROM_blk_mem_gen_v8_2_synth
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
BIOS_ROM_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__O22AI_FUNCTIONAL_PP_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22AI_FUNCTIONAL_PP_V |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Dual Data Rate Input D Flip-Flop
// /___/ /\ Filename : IDDR2.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:51 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 08/20/08 - CR 478850 added pulldown on R/S and pullup on CE.
// 04/08/09 - CR 517973 Reworked to matched Holistic tests
// 01/12/10 - CR 538181 Fixed R/S to take INIT values
// 05/04/10 - CR 558177 revert the above CR. Holistic tests are failing
// End Revision
`timescale 1 ps / 1 ps
module IDDR2 (Q0, Q1, C0, C1, CE, D, R, S);
output Q0;
output Q1;
input C0;
input C1;
input CE;
input D;
tri0 GSR = glbl.GSR;
input R;
input S;
parameter DDR_ALIGNMENT = "NONE";
parameter INIT_Q0 = 1'b0;
parameter INIT_Q1 = 1'b0;
parameter SRTYPE = "SYNC";
pullup P1 (CE);
pulldown P2 (R);
pulldown P3 (S);
reg q0_out, q1_out;
reg q0_out_int, q1_out_int;
reg q0_c0_out_int, q1_c0_out_int;
wire PC0, PC1;
buf buf_q0 (Q0, q0_out);
buf buf_q1 (Q1, q1_out);
initial begin
if ((INIT_Q0 != 1'b0) && (INIT_Q0 != 1'b1)) begin
$display("Attribute Syntax Error : The attribute INIT_Q0 on IDDR2 instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q0);
$finish;
end
if ((INIT_Q1 != 1'b0) && (INIT_Q1 != 1'b1)) begin
$display("Attribute Syntax Error : The attribute INIT_Q0 on IDDR2 instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q1);
$finish;
end
if ((DDR_ALIGNMENT != "C1") && (DDR_ALIGNMENT != "C0") && (DDR_ALIGNMENT != "NONE")) begin
$display("Attribute Syntax Error : The attribute DDR_ALIGNMENT on IDDR2 instance %m is set to %s. Legal values for this attribute are C0, C1 or NONE.", DDR_ALIGNMENT);
$finish;
end
if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
$display("Attribute Syntax Error : The attribute SRTYPE on IDDR2 instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
$finish;
end
end // initial begin
assign PC0 = ((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))? C0 : C1;
assign PC1 = ((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))? C1 : C0;
always @(GSR or R or S) begin
if (GSR == 1) begin
assign q0_out_int = INIT_Q0;
assign q1_out_int = INIT_Q1;
assign q0_c0_out_int = INIT_Q0;
assign q1_c0_out_int = INIT_Q1;
end
else begin
deassign q0_out_int;
deassign q1_out_int;
deassign q0_c0_out_int;
deassign q1_c0_out_int;
if (SRTYPE == "ASYNC") begin
if (R == 1) begin
assign q0_out_int = 0;
assign q1_out_int = 0;
assign q0_c0_out_int = 0;
assign q1_c0_out_int = 0;
end
else if (R == 0 && S == 1) begin
assign q0_out_int = 1;
assign q1_out_int = 1;
end
end // if (SRTYPE == "ASYNC")
end // if (GSR == 1'b0)
end // always @ (GSR or R or S)
always @(posedge PC0) begin
if (R == 1 && SRTYPE == "SYNC") begin
q0_out_int <= 0;
q0_c0_out_int <= 0;
q1_c0_out_int <= 0;
end
else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
q0_out_int <= 1;
end
else if (CE == 1 && R == 0 && S == 0) begin
q0_out_int <= D;
q0_c0_out_int <= q0_out_int;
q1_c0_out_int <= q1_out_int;
end
end // always @ (posedge PC0)
always @(posedge PC1) begin
if (R == 1 && SRTYPE == "SYNC") begin
q1_out_int <= 0;
end
else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
q1_out_int <= 1;
end
else if (CE == 1 && R == 0 && S == 0) begin
q1_out_int <= D;
end
end // always @ (posedge PC1)
always @(q0_out_int or q1_out_int or q1_c0_out_int or q0_c0_out_int) begin
case (DDR_ALIGNMENT)
"NONE" : begin
q0_out <= q0_out_int;
q1_out <= q1_out_int;
end
"C0" : begin
q0_out <= q0_out_int;
q1_out <= q1_c0_out_int;
end
"C1" : begin
q0_out <= q0_out_int;
q1_out <= q1_c0_out_int;
end
endcase // case(DDR_ALIGNMENT)
end // always @ (q0_out_int or q1_out_int or q1_c0_out_int or q0_c0_out_int)
specify
if (C0) (C0 => Q0) = (100, 100);
if (C0) (C0 => Q1) = (100, 100);
if (C1) (C1 => Q1) = (100, 100);
if (C1) (C1 => Q0) = (100, 100);
specparam PATHPULSE$ = 0;
endspecify
endmodule // IDDR2
|
/*
########################################################################
ELINK CONFIGURATION REGISTER FILE
########################################################################
*/
module ecfg (/*AUTOARG*/
// Outputs
soft_reset, mi_dout, ecfg_tx_enable, ecfg_tx_mmu_enable,
ecfg_tx_gpio_enable, ecfg_tx_ctrlmode, ecfg_timeout_enable,
ecfg_rx_enable, ecfg_rx_mmu_enable, ecfg_rx_gpio_enable,
ecfg_clk_settings, ecfg_coreid, ecfg_dataout,
// Inputs
hard_reset, mi_clk, mi_en, mi_we, mi_addr, mi_din, ecfg_rx_datain,
ecfg_tx_datain, embox_not_empty, embox_full, ecfg_tx_debug,
ecfg_rx_debug
);
/******************************/
/*Compile Time Parameters */
/******************************/
parameter RFAW = 5; // 32 registers for now
parameter DEFAULT_COREID = 12'h808; // reset value for ecfg_coreid
parameter DEFAULT_VERSION = 16'h0000; // reset value for version
parameter DEFAULT_CLKDIV = 4'd7;
/******************************/
/*HARDWARE RESET (EXTERNAL) */
/******************************/
input hard_reset; // ecfg registers reset only by "hard reset"
output soft_reset; // soft reset output driven by register
/*****************************/
/*SIMPLE MEMORY INTERFACE */
/*****************************/
input mi_clk;
input mi_en;
input mi_we; // single we, must write 32 bit words
input [19:0] mi_addr; // complete physical address (no shifting!)
input [31:0] mi_din;
output [31:0] mi_dout;
/*****************************/
/*ELINK CONTROL SIGNALS */
/*****************************/
//reset
//tx
output ecfg_tx_enable; // enable signal for TX
output ecfg_tx_mmu_enable; // enables MMU on transmit path
output ecfg_tx_gpio_enable; // forces TX output pins to constants
output [3:0] ecfg_tx_ctrlmode; // value for emesh ctrlmode tag
output ecfg_timeout_enable; // enables axi slave timeout circuit
//rx
output ecfg_rx_enable; // enable signal for rx
output ecfg_rx_mmu_enable; // enables MMU on rx path
output ecfg_rx_gpio_enable; // forces rx wait pins to constants
//clocks
output [15:0] ecfg_clk_settings; // clock settings
//coreid
output [11:0] ecfg_coreid; // core-id of fpga elink
//gpio
input [8:0] ecfg_rx_datain; // frame and data
input [1:0] ecfg_tx_datain; // wait signals
output [10:0] ecfg_dataout; // data for elink outputs
//debug
input embox_not_empty; // not-empty interrupt
input embox_full; // full debug signal
input [15:0] ecfg_tx_debug; // etx debug signals
input [15:0] ecfg_rx_debug; // etx debug signals
/*------------------------CODE BODY---------------------------------------*/
//registers
reg ecfg_reset_reg;
reg [8:0] ecfg_tx_reg;
reg [4:0] ecfg_rx_reg;
reg [15:0] ecfg_clk_reg;
reg [11:0] ecfg_coreid_reg;
reg [15:0] ecfg_version_reg;
reg [10:0] ecfg_datain_reg;
reg [10:0] ecfg_dataout_reg;
reg [7:0] ecfg_debug_reg;
reg [31:0] mi_dout;
//wires
wire ecfg_read;
wire ecfg_write;
wire ecfg_match;
wire ecfg_regmux;
wire [31:0] ecfg_reg_mux;
wire ecfg_tx_write;
wire ecfg_rx_write;
wire ecfg_clk_write;
wire ecfg_coreid_write;
wire ecfg_version_write;
wire ecfg_dataout_write;
wire ecfg_reset_write;
wire [31:0] ecfg_debug_vector;
/*****************************/
/*ADDRESS DECODE LOGIC */
/*****************************/
//read/write decode
assign ecfg_write = mi_en & mi_we;
assign ecfg_read = mi_en & ~mi_we;
//Config write enables
assign ecfg_reset_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELRESET);
assign ecfg_clk_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELCLK);
assign ecfg_tx_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELTX);
assign ecfg_rx_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELRX);
assign ecfg_coreid_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELCOREID);
assign ecfg_dataout_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELDATAOUT);
assign ecfg_version_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELVERSION);
//###########################
//# RESET
//###########################
always @ (posedge mi_clk)
if(hard_reset)
ecfg_reset_reg <= 1'b0;
else if (ecfg_reset_write)
ecfg_reset_reg <= mi_din[0];
assign soft_reset = ecfg_reset_reg;
//###########################
//# TX
//###########################
always @ (posedge mi_clk)
if(hard_reset)
ecfg_tx_reg[8:0] <= 9'b0;
else if (ecfg_tx_write)
ecfg_tx_reg[8:0] <= mi_din[8:0];
assign ecfg_tx_enable = ecfg_tx_reg[0];
assign ecfg_tx_mmu_enable = ecfg_tx_reg[1];
assign ecfg_tx_gpio_enable = (ecfg_tx_reg[3:2]==2'b01);
assign ecfg_tx_ctrlmode[3:0] = ecfg_tx_reg[7:4];
assign ecfg_timeout_enable = ecfg_tx_reg[8];
//###########################
//# RX
//###########################
always @ (posedge mi_clk)
if(hard_reset)
ecfg_rx_reg[4:0] <= 5'b0;
else if (ecfg_rx_write)
ecfg_rx_reg[4:0] <= mi_din[4:0];
assign ecfg_rx_enable = ecfg_rx_reg[0];
assign ecfg_rx_mmu_enable = ecfg_rx_reg[1];
assign ecfg_rx_gpio_enable = ecfg_rx_reg[3:2]==2'b01;
//###########################
//# CCLK/LCLK (PLL)
//###########################
always @ (posedge mi_clk)
if(hard_reset)
ecfg_clk_reg[15:0] <= 'd0;
else if (ecfg_clk_write)
ecfg_clk_reg[15:0] <= mi_din[15:0];
assign ecfg_clk_settings[15:0] = ecfg_clk_reg[15:0];
//assign ecfg_cclk_en = ~(ecfg_clk_reg[3:0]==4'b0000);
//assign ecfg_cclk_div[3:0] = ecfg_clk_reg[3:0];
//assign ecfg_cclk_pllcfg[3:0] = ecfg_clk_reg[7:4];
//assign ecfg_cclk_bypass = ecfg_clk_reg[8];
//###########################
//# COREID
//###########################
always @ (posedge mi_clk)
if(hard_reset)
ecfg_coreid_reg[11:0] <= DEFAULT_COREID;
else if (ecfg_coreid_write)
ecfg_coreid_reg[11:0] <= mi_din[11:0];
assign ecfg_coreid[11:0] = ecfg_coreid_reg[11:0];
//###########################
//# VERSION
//###########################
always @ (posedge mi_clk)
if(hard_reset)
ecfg_version_reg[15:0] <= DEFAULT_VERSION;
else if (ecfg_version_write)
ecfg_version_reg[15:0] <= mi_din[15:0];
//###########################
//# DATAIN
//###########################
always @ (posedge mi_clk)
ecfg_datain_reg[10:0] <= {ecfg_rx_datain[1:0], ecfg_rx_datain[8:0]};
//###########################
//# DATAOUT
//###########################
always @ (posedge mi_clk)
if(hard_reset)
ecfg_dataout_reg[10:0] <= 11'd0;
else if (ecfg_dataout_write)
ecfg_dataout_reg[10:0] <= mi_din[10:0];
assign ecfg_dataout[10:0] = ecfg_dataout_reg[10:0];
//###########################1
//# DEBUG
//###########################
assign ecfg_debug_vector[31:0]= {embox_not_empty,
ecfg_rx_debug[14:3],
ecfg_tx_debug[14:3],
ecfg_rx_debug[2:0],
ecfg_tx_debug[2:0],
embox_full
};
always @ (posedge mi_clk)
if(hard_reset)
ecfg_debug_reg[7:0] <= 8'd0;
else
ecfg_debug_reg[7:0] <=ecfg_debug_reg[7:0] | ecfg_debug_vector[7:0];
//###############################
//# DATA READBACK MUX
//###############################
//Pipelineing readback
always @ (posedge mi_clk)
if(ecfg_read)
case(mi_addr[RFAW+1:2])
`ELRESET: mi_dout[31:0] <= {31'b0, ecfg_reset_reg};
`ELTX: mi_dout[31:0] <= {23'b0, ecfg_tx_reg[8:0]};
`ELRX: mi_dout[31:0] <= {27'b0, ecfg_rx_reg[4:0]};
`ELCLK: mi_dout[31:0] <= {24'b0, ecfg_clk_reg[7:0]};
`ELCOREID: mi_dout[31:0] <= {20'b0, ecfg_coreid_reg[11:0]};
`ELVERSION: mi_dout[31:0] <= {16'b0, ecfg_version_reg[15:0]};
`ELDATAIN: mi_dout[31:0] <= {21'b0, ecfg_datain_reg[10:0]};
`ELDATAOUT: mi_dout[31:0] <= {21'b0, ecfg_dataout_reg[10:0]};
`ELDEBUG: mi_dout[31:0] <= {ecfg_debug_vector[31:8],ecfg_debug_reg[7:0]};
default: mi_dout[31:0] <= 32'd0;
endcase
endmodule // ecfg
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BAI_SYMBOL_V
`define SKY130_FD_SC_LP__O21BAI_SYMBOL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o21bai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BAI_SYMBOL_V
|
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module fifo_tx
#(
parameter integer DWIDTH = 9,
parameter integer AWIDTH = 6
)
(
input clock, reset, wr_en, rd_en,
input [DWIDTH-1:0] data_in/* synthesis syn_noprune */,
output reg f_full,write_tx,f_empty,
output [DWIDTH-1:0] data_out/* synthesis syn_noprune */,
output reg [AWIDTH-1:0] counter/* synthesis syn_noprune */
);
reg [AWIDTH-1:0] wr_ptr/* synthesis syn_noprune */;
reg [AWIDTH-1:0] rd_ptr/* synthesis syn_noprune */;
reg [1:0] state_data_write;
reg [1:0] next_state_data_write;
reg [1:0] state_data_read;
reg [1:0] next_state_data_read;
//reg [AWIDTH-1:0] counter_writer/* synthesis syn_noprune */;
//reg [AWIDTH-1:0] counter_reader/* synthesis syn_noprune */;
/****************************************/
always@(*)
begin
next_state_data_write = state_data_write;
case(state_data_write)
2'd0:
begin
if(wr_en && !f_full)
begin
next_state_data_write = 2'd1;
end
else
begin
next_state_data_write = 2'd0;
end
end
2'd1:
begin
if(wr_en)
begin
next_state_data_write = 2'd1;
end
else
begin
next_state_data_write = 2'd2;
end
end
2'd2:
begin
next_state_data_write = 2'd0;
end
default:
begin
next_state_data_write = 2'd0;
end
endcase
end
/****************************************/
always@(*)
begin
next_state_data_read = state_data_read;
case(state_data_read)
2'd0:
begin
if(counter > 6'd0)
begin
next_state_data_read = 2'd1;
end
else
begin
next_state_data_read = 2'd0;
end
end
2'd1:
begin
if(rd_en && !f_empty)
begin
next_state_data_read = 2'd2;
end
else
begin
next_state_data_read = 2'd1;
end
end
2'd2:
begin
if(rd_en)
begin
next_state_data_read = 2'd2;
end
else
begin
next_state_data_read = 2'd3;
end
end
2'd3:
begin
next_state_data_read = 2'd0;
end
default:
begin
next_state_data_read = 2'd0;
end
endcase
end
//Write pointer
always@(posedge clock or negedge reset)
begin
if (!reset)
begin
wr_ptr <= {(AWIDTH){1'b0}};
state_data_write <= 2'd0;
end
else
begin
state_data_write <= next_state_data_write;
case(state_data_write)
2'd0:
begin
wr_ptr <= wr_ptr;
end
2'd1:
begin
wr_ptr <= wr_ptr;
end
2'd2:
begin
wr_ptr <= wr_ptr + 6'd1;
end
default:
begin
wr_ptr <= wr_ptr;
end
endcase
end
end
//FULL - EMPTY COUNTER
always@(posedge clock or negedge reset)
begin
if (!reset)
begin
f_full <= 1'b0;
f_empty <= 1'b0;
counter <= {(AWIDTH){1'b0}};
end
else
begin
if(state_data_write == 2'd2)
begin
counter <= counter + 6'd1;
end
else
begin
if(counter > 6'd0 && state_data_read == 2'd3)
counter <= counter - 6'd1;
else
counter <= counter;
end
if(counter == 6'd63)
begin
f_full <= 1'b1;
end
else
begin
f_full <= 1'b0;
end
if(counter == 6'd0)
begin
f_empty <= 1'b1;
end
else
begin
f_empty <= 1'b0;
end
end
end
//Read pointer
always@(posedge clock or negedge reset)
begin
if (!reset)
begin
rd_ptr <= {(AWIDTH){1'b0}};
write_tx <= 1'b0;
state_data_read <= 2'd0;
end
else
begin
state_data_read <= next_state_data_read;
case(state_data_read)
2'd0:
begin
write_tx<= 1'b0;
end
2'd1:
begin
if(rd_en && !f_empty)
begin
rd_ptr <= rd_ptr + 6'd1;
end
else
begin
rd_ptr <= rd_ptr;
end
write_tx<= 1'b1;
end
2'd2:
begin
write_tx<= 1'b0;
end
2'd3:
begin
write_tx<= 1'b0;
end
default:
begin
rd_ptr <= rd_ptr;
end
endcase
end
end
mem_data mem_dta_fifo_tx(
.clock(clock),
.reset(reset),
.data_in(data_in),
.wr_ptr(wr_ptr),
.rd_ptr(rd_ptr),
.data_out(data_out)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__INV_FUNCTIONAL_PP_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_FUNCTIONAL_PP_V |
`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/06/2013 06:51:42 PM
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module main (
// Clk Input
input clk_in,
// Data Pins
output reset,
output sclk, // Half the speed of data_clk, a 20,000th the speed of clk
output sdata,
output scmd,
// Power Pins
output vbat,
output vdd,
// LED String Data Pins
output status_led,
output light_clk,
output light_data
);
// GPIO OUT MAP
// 0 - VDD
// 1 - VBAT
// 2 - RESET
// 3 - SCLK
// 4 - SDATA
// 5 - SCMD
wire [31 : 0] gpio;
zynq_1_wrapper cpu(.gpio(gpio));
assign vdd = gpio[0];
assign vbat = gpio[1];
assign reset = gpio[2];
assign sclk = gpio[3];
assign sdata = gpio[4];
assign scmd = gpio[5];
assign status_led = gpio[6];
assign light_clk = gpio[7];
assign light_data = gpio[8];
wire clk;
IBUFG clk_buf(.I(clk_in), .O(clk)); // Clock Buffer Conversion
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Nov 2 10:18:17 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
output [63:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, ADD_OVRFLW_NRM,
left_right_SHT2, bit_shift_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2,
ZERO_FLAG_SHT2, ADD_OVRFLW_NRM2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
OP_FLAG_SFG, ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_,
n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111,
n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121,
n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131,
n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141,
n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151,
n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161,
n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171,
n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181,
n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191,
n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201,
n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601,
n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611,
n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621,
n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631,
n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641,
n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651,
n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661,
n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671,
n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681,
n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691,
n1692, n1693, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702,
n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712,
n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722,
n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732,
n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742,
n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822,
n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832,
n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842,
n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852,
n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882,
n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892,
DP_OP_15J18_122_2221_n35, n1899, n1900, n1901, n1902, n1903, n1904,
n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914,
n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924,
n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934,
n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944,
n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954,
n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964,
n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974,
n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984,
n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994,
n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004,
n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014,
n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024,
n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034,
n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044,
n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054,
n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064,
n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074,
n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084,
n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094,
n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104,
n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114,
n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124,
n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134,
n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144,
n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154,
n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164,
n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174,
n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184,
n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194,
n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204,
n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214,
n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224,
n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234,
n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244,
n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254,
n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264,
n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274,
n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284,
n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294,
n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304,
n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314,
n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324,
n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334,
n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344,
n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354,
n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364,
n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374,
n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384,
n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394,
n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404,
n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414,
n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424,
n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434,
n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444,
n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454,
n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464,
n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474,
n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484,
n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494,
n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504,
n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514,
n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524,
n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534,
n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544,
n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554,
n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564,
n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574,
n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584,
n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594,
n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604,
n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614,
n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624,
n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634,
n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644,
n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654,
n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664,
n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674,
n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684,
n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694,
n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704,
n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714,
n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724,
n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734,
n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744,
n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754,
n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764,
n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774,
n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784,
n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794,
n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804,
n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814,
n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824,
n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834,
n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844,
n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854,
n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864,
n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874,
n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884,
n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894,
n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904,
n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914,
n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924,
n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934,
n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944,
n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954,
n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964,
n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974,
n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984,
n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994,
n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004,
n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014,
n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024,
n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034,
n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044,
n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054,
n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064,
n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074,
n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084,
n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094,
n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104,
n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114,
n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124,
n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134,
n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144,
n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154,
n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164,
n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174,
n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184,
n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194,
n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204,
n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214,
n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224,
n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234,
n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244,
n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254,
n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264,
n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274,
n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284,
n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294,
n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304,
n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314,
n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324,
n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334,
n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344,
n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354,
n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364,
n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374,
n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384,
n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394,
n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404,
n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414,
n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424,
n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434,
n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444,
n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454,
n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464,
n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474,
n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484,
n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494,
n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504,
n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514,
n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524,
n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534,
n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544,
n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554,
n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564,
n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574,
n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584,
n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594,
n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604,
n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614,
n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624,
n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634,
n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644,
n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654,
n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664,
n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674,
n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684,
n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694,
n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3704, n3705,
n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714, n3715,
n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724, n3725,
n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734, n3735,
n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744, n3745,
n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754, n3755,
n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764, n3765,
n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774, n3775,
n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784, n3785,
n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794, n3795,
n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804, n3805,
n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814, n3815,
n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824, n3825,
n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834, n3835,
n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844, n3845,
n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854, n3855,
n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864, n3865,
n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874, n3875,
n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884, n3885,
n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894, n3895,
n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904, n3905,
n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914, n3915,
n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924, n3925,
n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934, n3935,
n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944, n3945,
n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954, n3955,
n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965,
n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975,
n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985,
n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994, n3995,
n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005,
n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015,
n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024, n4025,
n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034, n4035,
n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044, n4045,
n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054, n4055,
n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065,
n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075,
n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085,
n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095,
n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104, n4105,
n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114, n4115,
n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124, n4125,
n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134, n4135,
n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145,
n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155,
n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165,
n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175,
n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185,
n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195,
n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205,
n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215,
n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225,
n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235,
n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245,
n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255,
n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265,
n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275,
n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285,
n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294, n4295,
n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304, n4305,
n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314, n4315,
n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324, n4325,
n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334, n4335,
n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345,
n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355,
n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365,
n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374, n4375,
n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384, n4385,
n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394, n4395,
n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404, n4405,
n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414, n4415,
n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424, n4425,
n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434, n4435,
n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444, n4445,
n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455,
n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464, n4465,
n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474, n4475,
n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484, n4485,
n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494, n4495,
n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504, n4505,
n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514, n4515,
n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524, n4525,
n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534, n4535,
n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545,
n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555,
n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565,
n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575,
n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585,
n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594, n4595,
n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605,
n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615,
n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625,
n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635,
n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645,
n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655,
n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665,
n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675,
n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685,
n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695,
n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705,
n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715,
n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725,
n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735,
n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745,
n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754;
wire [3:0] Shift_reg_FLAGS_7;
wire [63:0] intDX_EWSW;
wire [63:0] intDY_EWSW;
wire [62:0] DMP_EXP_EWSW;
wire [57:0] DmP_EXP_EWSW;
wire [62:0] DMP_SHT1_EWSW;
wire [51:0] DmP_mant_SHT1_SW;
wire [5:0] Shift_amount_SHT1_EWR;
wire [54:0] Raw_mant_NRM_SWR;
wire [53:0] Data_array_SWR;
wire [62:0] DMP_SHT2_EWSW;
wire [5:2] shift_value_SHT2_EWR;
wire [10:0] DMP_exp_NRM2_EW;
wire [10:0] DMP_exp_NRM_EW;
wire [5:0] LZD_output_NRM2_EW;
wire [62:0] DMP_SFG;
wire [54:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n1890), .CK(clk), .RN(n4676), .Q(
Shift_reg_FLAGS_7_6), .QN(n4484) );
DFFRXLTS inst_ShiftRegister_Q_reg_2_ ( .D(n1886), .CK(clk), .RN(n4754), .Q(
Shift_reg_FLAGS_7[2]), .QN(n1901) );
DFFRXLTS inst_ShiftRegister_Q_reg_0_ ( .D(n1884), .CK(clk), .RN(n4754), .Q(
Shift_reg_FLAGS_7[0]) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1819), .CK(clk), .RN(n4683), .Q(
intAS) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1753), .CK(clk), .RN(n4744),
.Q(left_right_SHT2), .QN(n1903) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_43_ ( .D(n1741), .CK(clk), .RN(n4734), .Q(
Data_array_SWR[42]), .QN(n1945) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_42_ ( .D(n1740), .CK(clk), .RN(n4734), .Q(
Data_array_SWR[41]), .QN(n1947) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_39_ ( .D(n1737), .CK(clk), .RN(n4734), .Q(
Data_array_SWR[38]), .QN(n1943) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_34_ ( .D(n1732), .CK(clk), .RN(n4734), .QN(
n1909) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(n1687), .CK(clk), .RN(n4744),
.Q(Shift_amount_SHT1_EWR[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n1675), .CK(clk), .RN(n4689), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n1674), .CK(clk), .RN(n4689), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n1673), .CK(clk), .RN(n4689), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n1672), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n1671), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n1670), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n1669), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n1668), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n1667), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n1666), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n1665), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n1664), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n1663), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n1662), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n1661), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n1660), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n1659), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n1658), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n1657), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n1656), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n1655), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n1654), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n1653), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(n1652), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(n1651), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(n1650), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(n1649), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n1648), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n1647), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n1646), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n1645), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_31_ ( .D(n1644), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_32_ ( .D(n1643), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_33_ ( .D(n1642), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_34_ ( .D(n1641), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_35_ ( .D(n1640), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_36_ ( .D(n1639), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[36]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_37_ ( .D(n1638), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_38_ ( .D(n1637), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_39_ ( .D(n1636), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_40_ ( .D(n1635), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[40]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_41_ ( .D(n1634), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[41]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_42_ ( .D(n1633), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_43_ ( .D(n1632), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_44_ ( .D(n1631), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_45_ ( .D(n1630), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_46_ ( .D(n1629), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[46]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_47_ ( .D(n1628), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_48_ ( .D(n1627), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[48]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_49_ ( .D(n1626), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_50_ ( .D(n1625), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_51_ ( .D(n1624), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[51]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_52_ ( .D(n1623), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[52]), .QN(n4606) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_58_ ( .D(n1617), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[58]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_59_ ( .D(n1616), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[59]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_60_ ( .D(n1615), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[60]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_61_ ( .D(n1614), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[61]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_62_ ( .D(n1613), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[62]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1612), .CK(clk), .RN(n4696), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n1611), .CK(clk), .RN(n4696), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1610), .CK(clk), .RN(n4696), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1609), .CK(clk), .RN(n4696), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1606), .CK(clk), .RN(n4696), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1603), .CK(clk), .RN(n4696), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1600), .CK(clk), .RN(n4696), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1597), .CK(clk), .RN(n4696), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1594), .CK(clk), .RN(n4696), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1591), .CK(clk), .RN(n4696), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1588), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1585), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1582), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1579), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1576), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1573), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1570), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1567), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1564), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1561), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1558), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1555), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1552), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1549), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1546), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1543), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1540), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1537), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1534), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1531), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1528), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1525), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1522), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1519), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_31_ ( .D(n1516), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[31]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_32_ ( .D(n1513), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[32]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_33_ ( .D(n1510), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[33]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_34_ ( .D(n1507), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[34]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_35_ ( .D(n1504), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[35]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_36_ ( .D(n1501), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_37_ ( .D(n1498), .CK(clk), .RN(n4700), .Q(
DMP_SHT1_EWSW[37]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_37_ ( .D(n1497), .CK(clk), .RN(n4700), .Q(
DMP_SHT2_EWSW[37]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_38_ ( .D(n1495), .CK(clk), .RN(n4700), .Q(
DMP_SHT1_EWSW[38]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_38_ ( .D(n1494), .CK(clk), .RN(n4700), .Q(
DMP_SHT2_EWSW[38]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_39_ ( .D(n1492), .CK(clk), .RN(n4700), .Q(
DMP_SHT1_EWSW[39]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_39_ ( .D(n1491), .CK(clk), .RN(n4700), .Q(
DMP_SHT2_EWSW[39]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_40_ ( .D(n1489), .CK(clk), .RN(n4700), .Q(
DMP_SHT1_EWSW[40]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_40_ ( .D(n1488), .CK(clk), .RN(n4700), .Q(
DMP_SHT2_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_41_ ( .D(n1486), .CK(clk), .RN(n4700), .Q(
DMP_SHT1_EWSW[41]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_41_ ( .D(n1485), .CK(clk), .RN(n4700), .Q(
DMP_SHT2_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_42_ ( .D(n1483), .CK(clk), .RN(n4701), .Q(
DMP_SHT1_EWSW[42]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_42_ ( .D(n1482), .CK(clk), .RN(n4701), .Q(
DMP_SHT2_EWSW[42]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_43_ ( .D(n1480), .CK(clk), .RN(n4701), .Q(
DMP_SHT1_EWSW[43]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_43_ ( .D(n1479), .CK(clk), .RN(n4701), .Q(
DMP_SHT2_EWSW[43]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_44_ ( .D(n1477), .CK(clk), .RN(n4701), .Q(
DMP_SHT1_EWSW[44]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_44_ ( .D(n1476), .CK(clk), .RN(n4701), .Q(
DMP_SHT2_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_45_ ( .D(n1474), .CK(clk), .RN(n4701), .Q(
DMP_SHT1_EWSW[45]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_45_ ( .D(n1473), .CK(clk), .RN(n4701), .Q(
DMP_SHT2_EWSW[45]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_46_ ( .D(n1471), .CK(clk), .RN(n4701), .Q(
DMP_SHT1_EWSW[46]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_46_ ( .D(n1470), .CK(clk), .RN(n4701), .Q(
DMP_SHT2_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_47_ ( .D(n1468), .CK(clk), .RN(n4702), .Q(
DMP_SHT1_EWSW[47]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_47_ ( .D(n1467), .CK(clk), .RN(n4702), .Q(
DMP_SHT2_EWSW[47]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_48_ ( .D(n1465), .CK(clk), .RN(n4702), .Q(
DMP_SHT1_EWSW[48]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_48_ ( .D(n1464), .CK(clk), .RN(n4702), .Q(
DMP_SHT2_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_49_ ( .D(n1462), .CK(clk), .RN(n4702), .Q(
DMP_SHT1_EWSW[49]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_49_ ( .D(n1461), .CK(clk), .RN(n4702), .Q(
DMP_SHT2_EWSW[49]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_50_ ( .D(n1459), .CK(clk), .RN(n4702), .Q(
DMP_SHT1_EWSW[50]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_50_ ( .D(n1458), .CK(clk), .RN(n4702), .Q(
DMP_SHT2_EWSW[50]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_51_ ( .D(n1456), .CK(clk), .RN(n4702), .Q(
DMP_SHT1_EWSW[51]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_51_ ( .D(n1455), .CK(clk), .RN(n4702), .Q(
DMP_SHT2_EWSW[51]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_52_ ( .D(n1453), .CK(clk), .RN(n4703), .Q(
DMP_SHT1_EWSW[52]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_52_ ( .D(n1452), .CK(clk), .RN(n4703), .Q(
DMP_SHT2_EWSW[52]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_52_ ( .D(n1451), .CK(clk), .RN(n4703), .Q(
DMP_SFG[52]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1449), .CK(clk), .RN(n4725), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1939) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_53_ ( .D(n1448), .CK(clk), .RN(n4703), .Q(
DMP_SHT1_EWSW[53]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_53_ ( .D(n1447), .CK(clk), .RN(n4703), .Q(
DMP_SHT2_EWSW[53]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_53_ ( .D(n1446), .CK(clk), .RN(n4703), .Q(
DMP_SFG[53]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1445), .CK(clk), .RN(n4703), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_54_ ( .D(n1443), .CK(clk), .RN(n4703), .Q(
DMP_SHT1_EWSW[54]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_54_ ( .D(n1442), .CK(clk), .RN(n4703), .Q(
DMP_SHT2_EWSW[54]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_54_ ( .D(n1441), .CK(clk), .RN(n4703), .Q(
DMP_SFG[54]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1440), .CK(clk), .RN(n4704), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_55_ ( .D(n1438), .CK(clk), .RN(n4704), .Q(
DMP_SHT1_EWSW[55]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_55_ ( .D(n1437), .CK(clk), .RN(n4704), .Q(
DMP_SHT2_EWSW[55]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_55_ ( .D(n1436), .CK(clk), .RN(n4704), .Q(
DMP_SFG[55]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1435), .CK(clk), .RN(n4704), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_56_ ( .D(n1433), .CK(clk), .RN(n4704), .Q(
DMP_SHT1_EWSW[56]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_56_ ( .D(n1432), .CK(clk), .RN(n4704), .Q(
DMP_SHT2_EWSW[56]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_56_ ( .D(n1431), .CK(clk), .RN(n4704), .Q(
DMP_SFG[56]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1430), .CK(clk), .RN(n4704), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_57_ ( .D(n1428), .CK(clk), .RN(n4704), .Q(
DMP_SHT1_EWSW[57]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_57_ ( .D(n1427), .CK(clk), .RN(n4705), .Q(
DMP_SHT2_EWSW[57]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_57_ ( .D(n1426), .CK(clk), .RN(n4705), .Q(
DMP_SFG[57]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1425), .CK(clk), .RN(n4705), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_58_ ( .D(n1423), .CK(clk), .RN(n4705), .Q(
DMP_SHT1_EWSW[58]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_58_ ( .D(n1422), .CK(clk), .RN(n4705), .Q(
DMP_SHT2_EWSW[58]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_58_ ( .D(n1421), .CK(clk), .RN(n4705), .Q(
DMP_SFG[58]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1420), .CK(clk), .RN(n4705), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_59_ ( .D(n1418), .CK(clk), .RN(n4705), .Q(
DMP_SHT1_EWSW[59]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_59_ ( .D(n1417), .CK(clk), .RN(n4705), .Q(
DMP_SHT2_EWSW[59]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_59_ ( .D(n1416), .CK(clk), .RN(n4705), .Q(
DMP_SFG[59]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1415), .CK(clk), .RN(n4706), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_60_ ( .D(n1413), .CK(clk), .RN(n4706), .Q(
DMP_SHT1_EWSW[60]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_60_ ( .D(n1412), .CK(clk), .RN(n4706), .Q(
DMP_SHT2_EWSW[60]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_60_ ( .D(n1411), .CK(clk), .RN(n4706), .Q(
DMP_SFG[60]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(n1410), .CK(clk), .RN(n4706), .Q(
DMP_exp_NRM_EW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_61_ ( .D(n1408), .CK(clk), .RN(n4706), .Q(
DMP_SHT1_EWSW[61]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_61_ ( .D(n1407), .CK(clk), .RN(n4706), .Q(
DMP_SHT2_EWSW[61]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_61_ ( .D(n1406), .CK(clk), .RN(n4706), .Q(
DMP_SFG[61]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(n1405), .CK(clk), .RN(n4706), .Q(
DMP_exp_NRM_EW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_62_ ( .D(n1403), .CK(clk), .RN(n4706), .Q(
DMP_SHT1_EWSW[62]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_62_ ( .D(n1402), .CK(clk), .RN(n4707), .Q(
DMP_SHT2_EWSW[62]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_62_ ( .D(n1401), .CK(clk), .RN(n4707), .Q(
DMP_SFG[62]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(n1400), .CK(clk), .RN(n4707), .Q(
DMP_exp_NRM_EW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n1398), .CK(clk), .RN(n4707), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1397), .CK(clk), .RN(n4707), .Q(
DmP_mant_SHT1_SW[0]), .QN(n4665) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n1396), .CK(clk), .RN(n4707), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1395), .CK(clk), .RN(n4707), .Q(
DmP_mant_SHT1_SW[1]), .QN(n4664) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n1394), .CK(clk), .RN(n4707), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1393), .CK(clk), .RN(n4707), .Q(
DmP_mant_SHT1_SW[2]), .QN(n4663) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n1392), .CK(clk), .RN(n4707), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1391), .CK(clk), .RN(n4708), .Q(
DmP_mant_SHT1_SW[3]), .QN(n4662) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n1390), .CK(clk), .RN(n4708), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1389), .CK(clk), .RN(n4708), .Q(
DmP_mant_SHT1_SW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n1388), .CK(clk), .RN(n4708), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1387), .CK(clk), .RN(n4708), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n1386), .CK(clk), .RN(n4708), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1385), .CK(clk), .RN(n4708), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n1384), .CK(clk), .RN(n4708), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1383), .CK(clk), .RN(n4708), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n1382), .CK(clk), .RN(n4708), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1381), .CK(clk), .RN(n4709), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n1380), .CK(clk), .RN(n4709), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1379), .CK(clk), .RN(n4709), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n1378), .CK(clk), .RN(n4709), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1377), .CK(clk), .RN(n4709),
.Q(DmP_mant_SHT1_SW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n1376), .CK(clk), .RN(n4709), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1375), .CK(clk), .RN(n4709),
.Q(DmP_mant_SHT1_SW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n1374), .CK(clk), .RN(n4709), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1373), .CK(clk), .RN(n4709),
.Q(DmP_mant_SHT1_SW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n1372), .CK(clk), .RN(n4709), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1371), .CK(clk), .RN(n4710),
.Q(DmP_mant_SHT1_SW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n1370), .CK(clk), .RN(n4710), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(n4710),
.Q(DmP_mant_SHT1_SW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n1368), .CK(clk), .RN(n4710), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1367), .CK(clk), .RN(n4710),
.Q(DmP_mant_SHT1_SW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n1366), .CK(clk), .RN(n4710), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1365), .CK(clk), .RN(n4710),
.Q(DmP_mant_SHT1_SW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n1364), .CK(clk), .RN(n4710), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1363), .CK(clk), .RN(n4710),
.Q(DmP_mant_SHT1_SW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n1362), .CK(clk), .RN(n4710), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1361), .CK(clk), .RN(n4711),
.Q(DmP_mant_SHT1_SW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n1360), .CK(clk), .RN(n4711), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1359), .CK(clk), .RN(n4711),
.Q(DmP_mant_SHT1_SW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n1358), .CK(clk), .RN(n4711), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1357), .CK(clk), .RN(n4711),
.Q(DmP_mant_SHT1_SW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n1356), .CK(clk), .RN(n4711), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1355), .CK(clk), .RN(n4711),
.Q(DmP_mant_SHT1_SW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(n1346), .CK(clk), .RN(n4712), .Q(
DmP_EXP_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(n1345), .CK(clk), .RN(n4712),
.Q(DmP_mant_SHT1_SW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(n1344), .CK(clk), .RN(n4712), .Q(
DmP_EXP_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(n1343), .CK(clk), .RN(n4712),
.Q(DmP_mant_SHT1_SW[27]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_28_ ( .D(n1342), .CK(clk), .RN(n4712), .Q(
DmP_EXP_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(n1341), .CK(clk), .RN(n4712),
.Q(DmP_mant_SHT1_SW[28]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_29_ ( .D(n1340), .CK(clk), .RN(n4712), .Q(
DmP_EXP_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(n1339), .CK(clk), .RN(n4712),
.Q(DmP_mant_SHT1_SW[29]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_30_ ( .D(n1338), .CK(clk), .RN(n4712), .Q(
DmP_EXP_EWSW[30]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(n1337), .CK(clk), .RN(n4713),
.Q(DmP_mant_SHT1_SW[30]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_31_ ( .D(n1336), .CK(clk), .RN(n4713), .Q(
DmP_EXP_EWSW[31]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(n1335), .CK(clk), .RN(n4713),
.Q(DmP_mant_SHT1_SW[31]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_32_ ( .D(n1334), .CK(clk), .RN(n4713), .Q(
DmP_EXP_EWSW[32]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(n1333), .CK(clk), .RN(n4713),
.Q(DmP_mant_SHT1_SW[32]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_33_ ( .D(n1332), .CK(clk), .RN(n4713), .Q(
DmP_EXP_EWSW[33]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(n1331), .CK(clk), .RN(n4713),
.Q(DmP_mant_SHT1_SW[33]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_34_ ( .D(n1330), .CK(clk), .RN(n4713), .Q(
DmP_EXP_EWSW[34]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(n1329), .CK(clk), .RN(n4713),
.Q(DmP_mant_SHT1_SW[34]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_35_ ( .D(n1328), .CK(clk), .RN(n4713), .Q(
DmP_EXP_EWSW[35]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(n1327), .CK(clk), .RN(n4714),
.Q(DmP_mant_SHT1_SW[35]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_36_ ( .D(n1326), .CK(clk), .RN(n4714), .Q(
DmP_EXP_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(n1325), .CK(clk), .RN(n4714),
.Q(DmP_mant_SHT1_SW[36]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_37_ ( .D(n1324), .CK(clk), .RN(n4714), .Q(
DmP_EXP_EWSW[37]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(n1323), .CK(clk), .RN(n4714),
.Q(DmP_mant_SHT1_SW[37]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_38_ ( .D(n1322), .CK(clk), .RN(n4714), .Q(
DmP_EXP_EWSW[38]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(n1321), .CK(clk), .RN(n4714),
.Q(DmP_mant_SHT1_SW[38]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_39_ ( .D(n1320), .CK(clk), .RN(n4714), .Q(
DmP_EXP_EWSW[39]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(n1319), .CK(clk), .RN(n4714),
.Q(DmP_mant_SHT1_SW[39]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_40_ ( .D(n1318), .CK(clk), .RN(n4714), .Q(
DmP_EXP_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(n1317), .CK(clk), .RN(n4715),
.Q(DmP_mant_SHT1_SW[40]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_41_ ( .D(n1316), .CK(clk), .RN(n4715), .Q(
DmP_EXP_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(n1315), .CK(clk), .RN(n4715),
.Q(DmP_mant_SHT1_SW[41]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_42_ ( .D(n1314), .CK(clk), .RN(n4715), .Q(
DmP_EXP_EWSW[42]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(n1313), .CK(clk), .RN(n4715),
.Q(DmP_mant_SHT1_SW[42]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_43_ ( .D(n1312), .CK(clk), .RN(n4715), .Q(
DmP_EXP_EWSW[43]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(n1311), .CK(clk), .RN(n4715),
.Q(DmP_mant_SHT1_SW[43]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_44_ ( .D(n1310), .CK(clk), .RN(n4715), .Q(
DmP_EXP_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(n1309), .CK(clk), .RN(n4715),
.Q(DmP_mant_SHT1_SW[44]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_45_ ( .D(n1308), .CK(clk), .RN(n4715), .Q(
DmP_EXP_EWSW[45]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(n1307), .CK(clk), .RN(n4716),
.Q(DmP_mant_SHT1_SW[45]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_46_ ( .D(n1306), .CK(clk), .RN(n4716), .Q(
DmP_EXP_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(n1305), .CK(clk), .RN(n4716),
.Q(DmP_mant_SHT1_SW[46]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_47_ ( .D(n1304), .CK(clk), .RN(n4716), .Q(
DmP_EXP_EWSW[47]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(n1303), .CK(clk), .RN(n4716),
.Q(DmP_mant_SHT1_SW[47]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_48_ ( .D(n1302), .CK(clk), .RN(n4716), .Q(
DmP_EXP_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(n1301), .CK(clk), .RN(n4716),
.Q(DmP_mant_SHT1_SW[48]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_49_ ( .D(n1300), .CK(clk), .RN(n4716), .Q(
DmP_EXP_EWSW[49]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(n1299), .CK(clk), .RN(n4716),
.Q(DmP_mant_SHT1_SW[49]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_53_ ( .D(n1293), .CK(clk), .RN(n4717), .Q(
DmP_EXP_EWSW[53]), .QN(n4486) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n1286), .CK(clk), .RN(n4717), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n1285), .CK(clk), .RN(n4717), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n1284), .CK(clk), .RN(n4717), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n1283), .CK(clk), .RN(n4718), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1282), .CK(clk), .RN(n4718),
.Q(ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1280), .CK(clk), .RN(n4718), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1279), .CK(clk), .RN(n4718), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1275), .CK(clk), .RN(n4718), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1274), .CK(clk), .RN(n4718), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1273), .CK(clk), .RN(n4718), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1272), .CK(clk), .RN(n4718), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1271), .CK(clk), .RN(n4718),
.Q(SIGN_FLAG_SHT1SHT2) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1254), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[15]), .QN(n4521) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1253), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[16]), .QN(n4615) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1252), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[17]), .QN(n4588) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1251), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[18]), .QN(n4591) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1249), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[20]), .QN(n1994) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1247), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[22]), .QN(n4577) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1246), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[23]), .QN(n4667) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1244), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[25]), .QN(n4585) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(n1241), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[28]), .QN(n4611) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(n1240), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[29]), .QN(n4593) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(n1239), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[30]), .QN(n4666) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(n1233), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[36]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(n1232), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[37]), .QN(n4669) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(n1231), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[38]), .QN(n4616) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(n1230), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[39]), .QN(n4592) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(n1229), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[40]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(n1227), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[42]), .QN(n4672) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(n1226), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[43]), .QN(n4589) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(n1225), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[44]), .QN(n4590) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(n1224), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[45]), .QN(n4673) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(n1222), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[47]), .QN(n1993) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(n1213), .CK(clk), .RN(n2706),
.Q(LZD_output_NRM2_EW[3]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(n1211), .CK(clk), .RN(n4725),
.Q(LZD_output_NRM2_EW[4]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(n1209), .CK(clk), .RN(n4725),
.Q(LZD_output_NRM2_EW[5]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1156), .CK(clk), .RN(n4736), .Q(
DmP_mant_SFG_SWR[0]), .QN(n4668) );
DFFRX1TS inst_ShiftRegister_Q_reg_4_ ( .D(n1888), .CK(clk), .RN(n4753), .Q(
n1910), .QN(n4674) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1261), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[8]), .QN(n4660) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(n1102), .CK(clk), .RN(n4726), .Q(
DmP_mant_SFG_SWR[54]), .QN(n4659) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(n1104), .CK(clk), .RN(n4734), .Q(
DmP_mant_SFG_SWR[52]), .QN(n4657) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1154), .CK(clk), .RN(n4727), .Q(
DmP_mant_SFG_SWR[2]), .QN(n4656) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1141), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[15]), .QN(n4654) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(n1127), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[29]), .QN(n4646) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(n1125), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[31]), .QN(n4645) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_43_ ( .D(n1113), .CK(clk), .RN(n4731), .Q(
DmP_mant_SFG_SWR[43]), .QN(n4643) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(n1112), .CK(clk), .RN(n4731), .Q(
DmP_mant_SFG_SWR[44]), .QN(n4642) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(n1105), .CK(clk), .RN(n4733), .Q(
DmP_mant_SFG_SWR[51]), .QN(n4639) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1144), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[12]), .QN(n4638) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1142), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[14]), .QN(n4637) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1146), .CK(clk), .RN(n4727), .Q(
DmP_mant_SFG_SWR[10]), .QN(n4635) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(n1130), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[26]), .QN(n4633) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(n1128), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[28]), .QN(n4632) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1256), .CK(clk), .RN(n4739), .Q(
Raw_mant_NRM_SWR[13]), .QN(n4628) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1260), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[9]), .QN(n4626) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1259), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[10]), .QN(n4625) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(n1103), .CK(clk), .RN(n4736), .Q(
DmP_mant_SFG_SWR[53]), .QN(n4624) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(n1106), .CK(clk), .RN(n4733), .Q(
DmP_mant_SFG_SWR[50]), .QN(n4623) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1267), .CK(clk), .RN(n4737), .Q(
Raw_mant_NRM_SWR[2]), .QN(n4620) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1264), .CK(clk), .RN(n4739), .Q(
Raw_mant_NRM_SWR[5]), .QN(n4619) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1265), .CK(clk), .RN(n4739), .Q(
Raw_mant_NRM_SWR[4]), .QN(n4617) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(n1108), .CK(clk), .RN(n4732), .Q(
DmP_mant_SFG_SWR[48]), .QN(n4614) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(n1107), .CK(clk), .RN(n4732), .Q(
DmP_mant_SFG_SWR[49]), .QN(n4613) );
DFFRX1TS SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n1754), .CK(clk), .RN(n4689),
.Q(bit_shift_SHT2), .QN(n4612) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1812), .CK(clk), .RN(n4683),
.Q(intDY_EWSW[6]), .QN(n4579) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1802), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[16]), .QN(n4578) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1266), .CK(clk), .RN(n4739), .Q(
Raw_mant_NRM_SWR[3]), .QN(n4576) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1262), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[7]), .QN(n4575) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(n1115), .CK(clk), .RN(n4731), .Q(
DmP_mant_SFG_SWR[41]), .QN(n4573) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_42_ ( .D(n1114), .CK(clk), .RN(n4731), .Q(
DmP_mant_SFG_SWR[42]), .QN(n4572) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n1697), .CK(clk), .RN(n4738),
.Q(shift_value_SHT2_EWR[2]), .QN(n4570) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1263), .CK(clk), .RN(n4739), .Q(
Raw_mant_NRM_SWR[6]), .QN(n4569) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n1891), .CK(clk), .RN(
n4676), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n4567) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1790), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[28]), .QN(n4563) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1792), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[26]), .QN(n4562) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1794), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[24]), .QN(n4561) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1796), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[22]), .QN(n4560) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1798), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[20]), .QN(n4559) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1800), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[18]), .QN(n4558) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(n1117), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[39]), .QN(n4546) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1152), .CK(clk), .RN(n4727), .Q(
DmP_mant_SFG_SWR[4]), .QN(n4545) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1150), .CK(clk), .RN(n4727), .Q(
DmP_mant_SFG_SWR[6]), .QN(n4544) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(n1116), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[40]), .QN(n4535) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n1695), .CK(clk), .RN(n4726),
.Q(shift_value_SHT2_EWR[4]), .QN(n4534) );
DFFRX1TS inst_ShiftRegister_Q_reg_5_ ( .D(n1889), .CK(clk), .RN(n4676), .Q(
n1953), .QN(n4629) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(n1693), .CK(clk), .RN(n4736),
.Q(shift_value_SHT2_EWR[5]), .QN(n4520) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(n1775), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[43]), .QN(n4515) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(n1777), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[41]), .QN(n4514) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(n1783), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[35]), .QN(n4513) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(n1785), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[33]), .QN(n4512) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n4676), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n4511) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1813), .CK(clk), .RN(n4683),
.Q(intDY_EWSW[5]), .QN(n4509) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1811), .CK(clk), .RN(n4683),
.Q(intDY_EWSW[7]), .QN(n4508) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1808), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[10]), .QN(n4507) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n1696), .CK(clk), .RN(n4738),
.Q(shift_value_SHT2_EWR[3]), .QN(n4506) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1255), .CK(clk), .RN(n4739), .Q(
Raw_mant_NRM_SWR[14]), .QN(n4505) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(n1761), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[57]), .QN(n4503) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1787), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[31]), .QN(n4502) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1789), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[29]), .QN(n4501) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1795), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[23]), .QN(n4500) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1797), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[21]), .QN(n4499) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1805), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[13]), .QN(n4497) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1791), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[27]), .QN(n4495) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1793), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[25]), .QN(n4494) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1799), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[19]), .QN(n4493) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1801), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[17]), .QN(n4492) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1809), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[9]), .QN(n4491) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1155), .CK(clk), .RN(n4736), .Q(
DmP_mant_SFG_SWR[1]), .QN(n4489) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(n1827), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[56]), .QN(n4487) );
DFFRX2TS inst_ShiftRegister_Q_reg_1_ ( .D(n1885), .CK(clk), .RN(n4753), .Q(
Shift_reg_FLAGS_7[1]), .QN(n4627) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(n1764), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[54]), .QN(n4482) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(n1763), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[55]), .QN(n4481) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(n1942), .CK(clk), .RN(n4683), .Q(ready) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1281), .CK(clk), .RN(n4718), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1287), .CK(clk), .RN(n4719), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_54_ ( .D(n1684), .CK(clk), .RN(n4720), .Q(
final_result_ieee[54]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_55_ ( .D(n1683), .CK(clk), .RN(n4720), .Q(
final_result_ieee[55]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_58_ ( .D(n1680), .CK(clk), .RN(n4719), .Q(
final_result_ieee[58]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_59_ ( .D(n1679), .CK(clk), .RN(n4719), .Q(
final_result_ieee[59]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1208), .CK(clk), .RN(n4723), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1199), .CK(clk), .RN(n4723), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1198), .CK(clk), .RN(n4722), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1197), .CK(clk), .RN(n4723), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1196), .CK(clk), .RN(n4722), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1195), .CK(clk), .RN(n4723), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_32_ ( .D(n1194), .CK(clk), .RN(n4722), .Q(
final_result_ieee[32]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1191), .CK(clk), .RN(n4723), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_34_ ( .D(n1190), .CK(clk), .RN(n4722), .Q(
final_result_ieee[34]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1189), .CK(clk), .RN(n4724), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_35_ ( .D(n1188), .CK(clk), .RN(n4722), .Q(
final_result_ieee[35]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1187), .CK(clk), .RN(n4724), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_36_ ( .D(n1186), .CK(clk), .RN(n4721), .Q(
final_result_ieee[36]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_37_ ( .D(n1184), .CK(clk), .RN(n4721), .Q(
final_result_ieee[37]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_38_ ( .D(n1182), .CK(clk), .RN(n4721), .Q(
final_result_ieee[38]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_39_ ( .D(n1180), .CK(clk), .RN(n4721), .Q(
final_result_ieee[39]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_40_ ( .D(n1178), .CK(clk), .RN(n4721), .Q(
final_result_ieee[40]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1167), .CK(clk), .RN(n2705), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_46_ ( .D(n1166), .CK(clk), .RN(n4720), .Q(
final_result_ieee[46]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1165), .CK(clk), .RN(n2711), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_47_ ( .D(n1164), .CK(clk), .RN(n4720), .Q(
final_result_ieee[47]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1163), .CK(clk), .RN(n2708), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_48_ ( .D(n1162), .CK(clk), .RN(n4720), .Q(
final_result_ieee[48]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_52_ ( .D(n1686), .CK(clk), .RN(n4720), .Q(
final_result_ieee[52]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_53_ ( .D(n1685), .CK(clk), .RN(n4720), .Q(
final_result_ieee[53]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_56_ ( .D(n1682), .CK(clk), .RN(n4719), .Q(
final_result_ieee[56]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_57_ ( .D(n1681), .CK(clk), .RN(n4719), .Q(
final_result_ieee[57]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_60_ ( .D(n1678), .CK(clk), .RN(n4719), .Q(
final_result_ieee[60]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_61_ ( .D(n1677), .CK(clk), .RN(n4719), .Q(
final_result_ieee[61]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_62_ ( .D(n1676), .CK(clk), .RN(n4719), .Q(
final_result_ieee[62]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_63_ ( .D(n1270), .CK(clk), .RN(n4719), .Q(
final_result_ieee[63]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1185), .CK(clk), .RN(n4724), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1183), .CK(clk), .RN(n4724), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1181), .CK(clk), .RN(n4724), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1179), .CK(clk), .RN(n4724), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1288), .CK(clk), .RN(n4719), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1207), .CK(clk), .RN(n4723), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1206), .CK(clk), .RN(n4722), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1205), .CK(clk), .RN(n4723), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1204), .CK(clk), .RN(n4722), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1203), .CK(clk), .RN(n4723), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1202), .CK(clk), .RN(n4722), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1201), .CK(clk), .RN(n4723), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1200), .CK(clk), .RN(n4722), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1193), .CK(clk), .RN(n4723), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_33_ ( .D(n1192), .CK(clk), .RN(n4722), .Q(
final_result_ieee[33]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1177), .CK(clk), .RN(n4724), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_41_ ( .D(n1176), .CK(clk), .RN(n4721), .Q(
final_result_ieee[41]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1175), .CK(clk), .RN(n4724), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_42_ ( .D(n1174), .CK(clk), .RN(n4721), .Q(
final_result_ieee[42]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1173), .CK(clk), .RN(n4724), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_43_ ( .D(n1172), .CK(clk), .RN(n4721), .Q(
final_result_ieee[43]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1171), .CK(clk), .RN(n4724), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_44_ ( .D(n1170), .CK(clk), .RN(n4721), .Q(
final_result_ieee[44]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1169), .CK(clk), .RN(n2707), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_45_ ( .D(n1168), .CK(clk), .RN(n4721), .Q(
final_result_ieee[45]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1161), .CK(clk), .RN(n2709), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_49_ ( .D(n1160), .CK(clk), .RN(n4720), .Q(
final_result_ieee[49]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1159), .CK(clk), .RN(n2706), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_50_ ( .D(n1158), .CK(clk), .RN(n4720), .Q(
final_result_ieee[50]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_51_ ( .D(n1157), .CK(clk), .RN(n4720), .Q(
final_result_ieee[51]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1720), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[22]), .QN(n4622) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1713), .CK(clk), .RN(n4733), .Q(
Data_array_SWR[15]), .QN(n4621) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_47_ ( .D(n1745), .CK(clk), .RN(n4734), .Q(
Data_array_SWR[46]), .QN(n4608) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(n1109), .CK(clk), .RN(n4732), .Q(
DmP_mant_SFG_SWR[47]), .QN(n4640) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_49_ ( .D(n1747), .CK(clk), .RN(n4736), .Q(
Data_array_SWR[48]), .QN(n4610) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_50_ ( .D(n1748), .CK(clk), .RN(n4734), .Q(
Data_array_SWR[49]), .QN(n4609) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(n1110), .CK(clk), .RN(n4731), .Q(
DmP_mant_SFG_SWR[46]), .QN(n4658) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_45_ ( .D(n1111), .CK(clk), .RN(n4731), .Q(
DmP_mant_SFG_SWR[45]), .QN(n4641) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_48_ ( .D(n1746), .CK(clk), .RN(n4731), .Q(
Data_array_SWR[47]), .QN(n4607) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(n1778), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[40]), .QN(n4599) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(n1786), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[32]), .QN(n4565) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(n1776), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[42]), .QN(n4600) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(n1768), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[50]), .QN(n4581) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(n1780), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[38]), .QN(n4596) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(n1823), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[60]), .QN(n4583) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(n1825), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[58]), .QN(n4582) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(n1771), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[47]), .QN(n4528) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(n1821), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[62]), .QN(n4504) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(n1767), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[51]), .QN(n4603) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1804), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[14]), .QN(n4557) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(n1824), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[59]), .QN(n4524) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(n1774), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[44]), .QN(n4601) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(n1773), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[45]), .QN(n4527) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(n1822), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[61]), .QN(n4568) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(n1772), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[46]), .QN(n4602) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1803), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[15]), .QN(n4498) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(n1830), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[53]), .QN(n4531) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1817), .CK(clk), .RN(n4683),
.Q(intDY_EWSW[1]), .QN(n4595) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1139), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[17]), .QN(n4551) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1135), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[21]), .QN(n4550) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_33_ ( .D(n1123), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[33]), .QN(n4548) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_37_ ( .D(n1119), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[37]), .QN(n4547) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1140), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[16]), .QN(n4543) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1138), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[18]), .QN(n4542) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1136), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[20]), .QN(n4541) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1134), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[22]), .QN(n4540) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(n1124), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[32]), .QN(n4539) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_34_ ( .D(n1122), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[34]), .QN(n4538) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_36_ ( .D(n1120), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[36]), .QN(n4537) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(n1118), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[38]), .QN(n4536) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(n1779), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[39]), .QN(n4526) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(n1828), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[55]), .QN(n4532) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n1583), .CK(clk), .RN(n4746), .Q(
DMP_SFG[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1870), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[13]), .QN(n1954) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(n1842), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[41]), .QN(n1955) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_24_ ( .D(n1535), .CK(clk), .RN(n4749), .Q(
DMP_SFG[24]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(n1845), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[38]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_23_ ( .D(n1538), .CK(clk), .RN(n4749), .Q(
DMP_SFG[23]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_25_ ( .D(n1532), .CK(clk), .RN(n4749), .Q(
DMP_SFG[25]) );
DFFRX4TS SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1276), .CK(clk), .RN(n4725),
.Q(ADD_OVRFLW_NRM2), .QN(DP_OP_15J18_122_2221_n35) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n1586), .CK(clk), .RN(n4746), .Q(
DMP_SFG[7]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1269), .CK(clk), .RN(n4736), .Q(
Raw_mant_NRM_SWR[0]), .QN(n4587) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(n1228), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[41]), .QN(n4519) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1143), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[13]), .QN(n4655) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(n1782), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[36]), .QN(n4598) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(n1834), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[49]), .QN(n4584) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(n1766), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[52]), .QN(n4518) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(n1829), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[54]), .QN(n4529) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1878), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[5]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1876), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[7]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(n1836), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[47]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(n1846), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[37]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(n1831), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[52]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1859), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[24]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(n1835), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[48]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1867), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[16]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(n1843), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[40]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1873), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(n1851), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[32]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1881), .CK(clk), .RN(n4676),
.Q(intDX_EWSW[2]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n1892), .CK(clk), .RN(
n4676), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(n1841), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[42]), .QN(n1971) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(n1849), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[34]), .QN(n1965) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(n1758), .CK(clk), .RN(n4689),
.Q(intDY_EWSW[60]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1883), .CK(clk), .RN(n4676),
.Q(intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(n1760), .CK(clk), .RN(n4689),
.Q(intDY_EWSW[58]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1853), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[30]), .QN(n1979) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1854), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[29]), .QN(n1991) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1856), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[27]), .QN(n1984) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1864), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[19]), .QN(n1980) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1861), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[22]), .QN(n1970) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(n1756), .CK(clk), .RN(n4689),
.Q(intDY_EWSW[62]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_2_ ( .D(n1601), .CK(clk), .RN(n4745), .Q(
DMP_SFG[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_52_ ( .D(n1750), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[51]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_53_ ( .D(n1751), .CK(clk), .RN(n4736), .Q(
Data_array_SWR[52]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_54_ ( .D(n1752), .CK(clk), .RN(n4737), .Q(
Data_array_SWR[53]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n1559), .CK(clk), .RN(n4748), .Q(
DMP_SFG[16]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_42_ ( .D(n1481), .CK(clk), .RN(n4752), .Q(
DMP_SFG[42]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_41_ ( .D(n1484), .CK(clk), .RN(n4752), .Q(
DMP_SFG[41]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_39_ ( .D(n1490), .CK(clk), .RN(n4752), .Q(
DMP_SFG[39]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_37_ ( .D(n1496), .CK(clk), .RN(n4752), .Q(
DMP_SFG[37]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_35_ ( .D(n1502), .CK(clk), .RN(n4751), .Q(
DMP_SFG[35]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_33_ ( .D(n1508), .CK(clk), .RN(n4751), .Q(
DMP_SFG[33]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_31_ ( .D(n1514), .CK(clk), .RN(n4751), .Q(
DMP_SFG[31]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_30_ ( .D(n1517), .CK(clk), .RN(n4750), .Q(
DMP_SFG[30]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_29_ ( .D(n1520), .CK(clk), .RN(n4750), .Q(
DMP_SFG[29]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_28_ ( .D(n1523), .CK(clk), .RN(n4750), .Q(
DMP_SFG[28]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_27_ ( .D(n1526), .CK(clk), .RN(n4750), .Q(
DMP_SFG[27]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_26_ ( .D(n1529), .CK(clk), .RN(n4750), .Q(
DMP_SFG[26]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n1541), .CK(clk), .RN(n4749), .Q(
DMP_SFG[22]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n1544), .CK(clk), .RN(n4749), .Q(
DMP_SFG[21]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n1547), .CK(clk), .RN(n4748), .Q(
DMP_SFG[20]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n1550), .CK(clk), .RN(n4748), .Q(
DMP_SFG[19]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n1553), .CK(clk), .RN(n4748), .Q(
DMP_SFG[18]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n1556), .CK(clk), .RN(n4748), .Q(
DMP_SFG[17]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n1565), .CK(clk), .RN(n4747), .Q(
DMP_SFG[14]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n1568), .CK(clk), .RN(n4747), .Q(
DMP_SFG[13]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n1574), .CK(clk), .RN(n4747), .Q(
DMP_SFG[11]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n1580), .CK(clk), .RN(n4746), .Q(
DMP_SFG[9]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n1589), .CK(clk), .RN(n4746), .Q(
DMP_SFG[6]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n1592), .CK(clk), .RN(n4745), .Q(
DMP_SFG[5]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1258), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1721), .CK(clk), .RN(n4733), .Q(
Data_array_SWR[23]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1722), .CK(clk), .RN(n4732), .Q(
Data_array_SWR[24]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1723), .CK(clk), .RN(n4738), .Q(
Data_array_SWR[25]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_38_ ( .D(n1736), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[37]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_28_ ( .D(n1726), .CK(clk), .RN(n4732), .Q(
Data_array_SWR[28]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_29_ ( .D(n1727), .CK(clk), .RN(n4739), .Q(
Data_array_SWR[29]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_27_ ( .D(n1725), .CK(clk), .RN(n4733), .Q(
Data_array_SWR[27]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1712), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[14]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_40_ ( .D(n1738), .CK(clk), .RN(n4731), .Q(
Data_array_SWR[39]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_41_ ( .D(n1739), .CK(clk), .RN(n4737), .Q(
Data_array_SWR[40]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1716), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[18]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n1607), .CK(clk), .RN(n4744), .Q(
DMP_SFG[0]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_40_ ( .D(n1487), .CK(clk), .RN(n4752), .Q(
DMP_SFG[40]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_38_ ( .D(n1493), .CK(clk), .RN(n4752), .Q(
DMP_SFG[38]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_36_ ( .D(n1499), .CK(clk), .RN(n4752), .Q(
DMP_SFG[36]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_34_ ( .D(n1505), .CK(clk), .RN(n4751), .Q(
DMP_SFG[34]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_32_ ( .D(n1511), .CK(clk), .RN(n4751), .Q(
DMP_SFG[32]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n1571), .CK(clk), .RN(n4747), .Q(
DMP_SFG[12]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n1577), .CK(clk), .RN(n4746), .Q(
DMP_SFG[10]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n1595), .CK(clk), .RN(n4745), .Q(
DMP_SFG[4]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(n1850), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[33]), .QN(n1963) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_50_ ( .D(n1457), .CK(clk), .RN(n4754), .Q(
DMP_SFG[50]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_48_ ( .D(n1463), .CK(clk), .RN(n4754), .Q(
DMP_SFG[48]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_46_ ( .D(n1469), .CK(clk), .RN(n4753), .Q(
DMP_SFG[46]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_44_ ( .D(n1475), .CK(clk), .RN(n4753), .Q(
DMP_SFG[44]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_49_ ( .D(n1460), .CK(clk), .RN(n4754), .Q(
DMP_SFG[49]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_47_ ( .D(n1466), .CK(clk), .RN(n4754), .Q(
DMP_SFG[47]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_45_ ( .D(n1472), .CK(clk), .RN(n4753), .Q(
DMP_SFG[45]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_43_ ( .D(n1478), .CK(clk), .RN(n4752), .Q(
DMP_SFG[43]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1872), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[11]), .QN(n1989) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_51_ ( .D(n1454), .CK(clk), .RN(n4754), .Q(
DMP_SFG[51]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(n1844), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[39]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1707), .CK(clk), .RN(n4737), .Q(
Data_array_SWR[9]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1706), .CK(clk), .RN(n4731), .Q(
Data_array_SWR[8]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(n1762), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[56]), .QN(n1988) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1709), .CK(clk), .RN(n4733), .Q(
Data_array_SWR[11]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(n1820), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[63]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1250), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1869), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[14]), .QN(n1969) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1278), .CK(clk), .RN(n4744), .Q(
OP_FLAG_SFG) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1703), .CK(clk), .RN(n4737), .Q(
Data_array_SWR[5]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1705), .CK(clk), .RN(n4733), .Q(
Data_array_SWR[7]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_52_ ( .D(n1294), .CK(clk), .RN(n4717), .Q(
DmP_EXP_EWSW[52]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_57_ ( .D(n1618), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[57]) );
DFFRX1TS inst_ShiftRegister_Q_reg_3_ ( .D(n1887), .CK(clk), .RN(n4676), .Q(
Shift_reg_FLAGS_7[3]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n1562), .CK(clk), .RN(n4747), .Q(
DMP_SFG[15]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n1604), .CK(clk), .RN(n4745), .Q(
DMP_SFG[1]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1689), .CK(clk), .RN(n4738),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(n1347), .CK(clk), .RN(n4738),
.Q(DmP_mant_SHT1_SW[25]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1533), .CK(clk), .RN(n4750), .Q(
DMP_SHT2_EWSW[25]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1536), .CK(clk), .RN(n4749), .Q(
DMP_SHT2_EWSW[24]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1539), .CK(clk), .RN(n4749), .Q(
DMP_SHT2_EWSW[23]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1584), .CK(clk), .RN(n4746), .Q(
DMP_SHT2_EWSW[8]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1587), .CK(clk), .RN(n4746), .Q(
DMP_SHT2_EWSW[7]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1599), .CK(clk), .RN(n4745), .Q(
DMP_SHT2_EWSW[3]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1688), .CK(clk), .RN(n4744),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1690), .CK(clk), .RN(n4739),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_63_ ( .D(n1755), .CK(clk), .RN(n4689),
.Q(intDY_EWSW[63]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(n1295), .CK(clk), .RN(n4736),
.Q(DmP_mant_SHT1_SW[51]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(n1297), .CK(clk), .RN(n4736),
.Q(DmP_mant_SHT1_SW[50]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1353), .CK(clk), .RN(n4738),
.Q(DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1691), .CK(clk), .RN(n4739),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1212), .CK(clk), .RN(n2710),
.Q(LZD_output_NRM2_EW[1]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1692), .CK(clk), .RN(n4739),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1879), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[4]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1877), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[6]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1874), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(n1832), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[51]), .QN(n1958) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1871), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[12]), .QN(n1961) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1855), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[28]), .QN(n1986) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1862), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[21]), .QN(n1966) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(n1837), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[46]), .QN(n1975) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1863), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[20]), .QN(n1962) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(n1759), .CK(clk), .RN(n4689),
.Q(intDY_EWSW[59]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_30_ ( .D(n1728), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[30]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_26_ ( .D(n1724), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[26]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1719), .CK(clk), .RN(n4738), .Q(
Data_array_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1718), .CK(clk), .RN(n4732), .Q(
Data_array_SWR[20]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1715), .CK(clk), .RN(n4738), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1714), .CK(clk), .RN(n4732), .Q(
Data_array_SWR[16]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_45_ ( .D(n1743), .CK(clk), .RN(n4737), .Q(
Data_array_SWR[44]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_44_ ( .D(n1742), .CK(clk), .RN(n4731), .Q(
Data_array_SWR[43]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1717), .CK(clk), .RN(n4733), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1711), .CK(clk), .RN(n4737), .Q(
Data_array_SWR[13]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1710), .CK(clk), .RN(n4732), .Q(
Data_array_SWR[12]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_33_ ( .D(n1731), .CK(clk), .RN(n4737), .Q(
Data_array_SWR[33]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_32_ ( .D(n1730), .CK(clk), .RN(n4732), .Q(
Data_array_SWR[32]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_31_ ( .D(n1729), .CK(clk), .RN(n4733), .Q(
Data_array_SWR[31]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1814), .CK(clk), .RN(n4683),
.Q(intDY_EWSW[4]), .QN(n4554) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1866), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[17]), .QN(n1983) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1860), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[23]), .QN(n1973) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1858), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[25]), .QN(n1952) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1852), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[31]), .QN(n1981) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(n1847), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[36]), .QN(n1968) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1875), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[8]), .QN(n1950) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1865), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[18]), .QN(n1990) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1857), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[26]), .QN(n1957) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(n1833), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[50]), .QN(n1956) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(n1848), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[35]), .QN(n1967) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(n1840), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[43]), .QN(n1972) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(n1838), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[45]), .QN(n1974) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(n1826), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[57]), .QN(n1985) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(n1765), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[53]), .QN(n1987) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1708), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[10]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1818), .CK(clk), .RN(n4683),
.Q(intDY_EWSW[0]), .QN(n4490) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1816), .CK(clk), .RN(n4683),
.Q(intDY_EWSW[2]), .QN(n4553) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(n1757), .CK(clk), .RN(n4689),
.Q(intDY_EWSW[61]), .QN(n1992) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1882), .CK(clk), .RN(n4676),
.Q(intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(n1781), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[37]), .QN(n4525) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1704), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[6]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_54_ ( .D(n1292), .CK(clk), .RN(n4717), .Q(
DmP_EXP_EWSW[54]), .QN(n1978) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_56_ ( .D(n1290), .CK(clk), .RN(n4717), .Q(
DmP_EXP_EWSW[56]), .QN(n1964) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_55_ ( .D(n1620), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[55]), .QN(n1960) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1145), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[11]), .QN(n4650) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_54_ ( .D(n1621), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[54]), .QN(n4485) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_56_ ( .D(n1619), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[56]), .QN(n4530) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_53_ ( .D(n1622), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[53]), .QN(n1959) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n1598), .CK(clk), .RN(n4745), .Q(
DMP_SFG[3]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_37_ ( .D(n1735), .CK(clk), .RN(n4737), .Q(
Data_array_SWR[36]), .QN(n4605) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_36_ ( .D(n1734), .CK(clk), .RN(n4732), .Q(
Data_array_SWR[35]), .QN(n4604) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_35_ ( .D(n1733), .CK(clk), .RN(n4734), .Q(
Data_array_SWR[34]), .QN(n4618) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1880), .CK(clk), .RN(n4676),
.Q(intDX_EWSW[3]), .QN(n1949) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1868), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[15]), .QN(n1951) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(n1770), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[48]), .QN(n4566) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1608), .CK(clk), .RN(n4745), .Q(
DMP_SHT2_EWSW[0]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1605), .CK(clk), .RN(n4745), .Q(
DMP_SHT2_EWSW[1]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1602), .CK(clk), .RN(n4745), .Q(
DMP_SHT2_EWSW[2]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1596), .CK(clk), .RN(n4745), .Q(
DMP_SHT2_EWSW[4]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1593), .CK(clk), .RN(n4746), .Q(
DMP_SHT2_EWSW[5]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1581), .CK(clk), .RN(n4746), .Q(
DMP_SHT2_EWSW[9]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1578), .CK(clk), .RN(n4747), .Q(
DMP_SHT2_EWSW[10]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1575), .CK(clk), .RN(n4747), .Q(
DMP_SHT2_EWSW[11]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1572), .CK(clk), .RN(n4747), .Q(
DMP_SHT2_EWSW[12]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1569), .CK(clk), .RN(n4747), .Q(
DMP_SHT2_EWSW[13]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1566), .CK(clk), .RN(n4747), .Q(
DMP_SHT2_EWSW[14]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1563), .CK(clk), .RN(n4748), .Q(
DMP_SHT2_EWSW[15]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1560), .CK(clk), .RN(n4748), .Q(
DMP_SHT2_EWSW[16]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1557), .CK(clk), .RN(n4748), .Q(
DMP_SHT2_EWSW[17]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1554), .CK(clk), .RN(n4748), .Q(
DMP_SHT2_EWSW[18]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1551), .CK(clk), .RN(n4748), .Q(
DMP_SHT2_EWSW[19]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1548), .CK(clk), .RN(n4749), .Q(
DMP_SHT2_EWSW[20]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1545), .CK(clk), .RN(n4749), .Q(
DMP_SHT2_EWSW[21]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1542), .CK(clk), .RN(n4749), .Q(
DMP_SHT2_EWSW[22]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1527), .CK(clk), .RN(n4750), .Q(
DMP_SHT2_EWSW[27]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1524), .CK(clk), .RN(n4750), .Q(
DMP_SHT2_EWSW[28]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1521), .CK(clk), .RN(n4750), .Q(
DMP_SHT2_EWSW[29]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1518), .CK(clk), .RN(n4751), .Q(
DMP_SHT2_EWSW[30]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_31_ ( .D(n1515), .CK(clk), .RN(n4751), .Q(
DMP_SHT2_EWSW[31]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_32_ ( .D(n1512), .CK(clk), .RN(n4751), .Q(
DMP_SHT2_EWSW[32]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_33_ ( .D(n1509), .CK(clk), .RN(n4751), .Q(
DMP_SHT2_EWSW[33]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_34_ ( .D(n1506), .CK(clk), .RN(n4751), .Q(
DMP_SHT2_EWSW[34]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_35_ ( .D(n1503), .CK(clk), .RN(n4752), .Q(
DMP_SHT2_EWSW[35]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_36_ ( .D(n1500), .CK(clk), .RN(n4752), .Q(
DMP_SHT2_EWSW[36]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(n1349), .CK(clk), .RN(n4738),
.Q(DmP_mant_SHT1_SW[24]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_57_ ( .D(n1289), .CK(clk), .RN(n4717), .Q(
DmP_EXP_EWSW[57]) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1450), .CK(clk), .RN(n4725), .Q(
DMP_exp_NRM_EW[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_55_ ( .D(n1291), .CK(clk), .RN(n4717), .Q(
DmP_EXP_EWSW[55]), .QN(n4488) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n1352), .CK(clk), .RN(n4711), .Q(
DmP_EXP_EWSW[23]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n1350), .CK(clk), .RN(n4711), .Q(
DmP_EXP_EWSW[24]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n1348), .CK(clk), .RN(n4712), .Q(
DmP_EXP_EWSW[25]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_50_ ( .D(n1298), .CK(clk), .RN(n4716), .Q(
DmP_EXP_EWSW[50]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_51_ ( .D(n1296), .CK(clk), .RN(n4717), .Q(
DmP_EXP_EWSW[51]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1701), .CK(clk), .RN(n4733), .Q(
Data_array_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1700), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1699), .CK(clk), .RN(n4737), .Q(
Data_array_SWR[1]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(n1243), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[26]), .QN(n4630) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(n1242), .CK(clk), .RN(n4727), .Q(
Raw_mant_NRM_SWR[27]), .QN(n4580) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(n1238), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[31]), .QN(n4510) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(n1237), .CK(clk), .RN(n4744), .Q(
Raw_mant_NRM_SWR[32]), .QN(n4671) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(n1236), .CK(clk), .RN(n4744), .Q(
Raw_mant_NRM_SWR[33]), .QN(n4594) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(n1235), .CK(clk), .RN(n4744), .Q(
Raw_mant_NRM_SWR[34]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(n1234), .CK(clk), .RN(n4744), .Q(
Raw_mant_NRM_SWR[35]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(n1223), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[46]), .QN(n4552) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_49_ ( .D(n1220), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[49]), .QN(n4483) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_50_ ( .D(n1219), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[50]), .QN(n4533) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_51_ ( .D(n1218), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[51]), .QN(n4522) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_52_ ( .D(n1217), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[52]), .QN(n4523) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_53_ ( .D(n1216), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[53]), .QN(n4670) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_54_ ( .D(n1215), .CK(clk), .RN(n4744), .Q(
Raw_mant_NRM_SWR[54]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1248), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[21]), .QN(n4661) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1137), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[19]), .QN(n4649) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1133), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[23]), .QN(n4648) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1131), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[25]), .QN(n4647) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_35_ ( .D(n1121), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[35]), .QN(n4644) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1132), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[24]), .QN(n4634) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(n1126), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[30]), .QN(n4631) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(n1784), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[34]), .QN(n4597) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1245), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[24]), .QN(n4586) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1268), .CK(clk), .RN(n4736), .Q(
Raw_mant_NRM_SWR[1]), .QN(n4571) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1788), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[30]), .QN(n4564) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1806), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[12]), .QN(n4556) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1810), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[8]), .QN(n4555) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_27_ ( .D(n1129), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[27]), .QN(n4549) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(n1769), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[49]), .QN(n4517) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1807), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[11]), .QN(n4516) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(n1839), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[44]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(n1214), .CK(clk), .RN(n2709),
.Q(LZD_output_NRM2_EW[2]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1257), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[12]), .QN(n4574) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(n1351), .CK(clk), .RN(n4738),
.Q(DmP_mant_SHT1_SW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1590), .CK(clk), .RN(n4746), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1530), .CK(clk), .RN(n4750), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n1354), .CK(clk), .RN(n4711), .Q(
DmP_EXP_EWSW[22]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1815), .CK(clk), .RN(n4683),
.Q(intDY_EWSW[3]), .QN(n4496) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(n1221), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[48]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1210), .CK(clk), .RN(n2704),
.Q(LZD_output_NRM2_EW[0]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1147), .CK(clk), .RN(n4727), .Q(
DmP_mant_SFG_SWR[9]), .QN(n4651) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1153), .CK(clk), .RN(n4727), .Q(
DmP_mant_SFG_SWR[3]), .QN(n4653) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1148), .CK(clk), .RN(n4727), .Q(
DmP_mant_SFG_SWR[8]), .QN(n4636) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1151), .CK(clk), .RN(n4727), .Q(
DmP_mant_SFG_SWR[5]), .QN(n1976) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1149), .CK(clk), .RN(n4727), .Q(
DmP_mant_SFG_SWR[7]), .QN(n4652) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1444), .CK(clk), .RN(n4725), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1439), .CK(clk), .RN(n4725), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1434), .CK(clk), .RN(n4725), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1429), .CK(clk), .RN(n4725), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1424), .CK(clk), .RN(n4725), .Q(
DMP_exp_NRM2_EW[5]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1419), .CK(clk), .RN(n4726), .Q(
DMP_exp_NRM2_EW[6]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1414), .CK(clk), .RN(n4726), .Q(
DMP_exp_NRM2_EW[7]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1409), .CK(clk), .RN(n4726), .Q(
DMP_exp_NRM2_EW[8]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1404), .CK(clk), .RN(n4726), .Q(
DMP_exp_NRM2_EW[9]) );
DFFRX2TS NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1277), .CK(clk), .RN(n4726), .Q(
ADD_OVRFLW_NRM) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1399), .CK(clk), .RN(n4726),
.Q(DMP_exp_NRM2_EW[10]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_51_ ( .D(n1749), .CK(clk), .RN(n4734), .Q(
Data_array_SWR[50]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_46_ ( .D(n1744), .CK(clk), .RN(n4734), .Q(
Data_array_SWR[45]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1702), .CK(clk), .RN(n4726), .Q(
Data_array_SWR[4]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1698), .CK(clk), .RN(n4726), .Q(
Data_array_SWR[0]) );
OAI211X1TS U1897 ( .A0(n3394), .A1(n3584), .B0(n3393), .C0(n3392), .Y(n1710)
);
OAI211X1TS U1898 ( .A0(n3399), .A1(n3584), .B0(n3370), .C0(n3369), .Y(n1742)
);
OAI211X1TS U1899 ( .A0(n3428), .A1(n3584), .B0(n3427), .C0(n3426), .Y(n1714)
);
AOI222X1TS U1900 ( .A0(n4370), .A1(n2785), .B0(Shift_amount_SHT1_EWR[5]),
.B1(n2806), .C0(shift_value_SHT2_EWR[5]), .C1(n2784), .Y(n2786) );
BUFX3TS U1901 ( .A(n3039), .Y(n3051) );
BUFX6TS U1902 ( .A(n3039), .Y(n3047) );
BUFX6TS U1903 ( .A(n2950), .Y(n3049) );
AOI222X4TS U1904 ( .A0(n2958), .A1(Data_array_SWR[32]), .B0(n2938), .B1(
Data_array_SWR[28]), .C0(n3653), .C1(Data_array_SWR[24]), .Y(n2974) );
AOI222X4TS U1905 ( .A0(n2939), .A1(Data_array_SWR[31]), .B0(n2938), .B1(
Data_array_SWR[27]), .C0(n3653), .C1(Data_array_SWR[23]), .Y(n2953) );
CLKBUFX2TS U1906 ( .A(n2314), .Y(n2914) );
BUFX4TS U1907 ( .A(n2892), .Y(n2931) );
BUFX3TS U1908 ( .A(n4477), .Y(n4286) );
AND2X2TS U1909 ( .A(n3697), .B(Shift_reg_FLAGS_7[3]), .Y(n4477) );
BUFX3TS U1910 ( .A(n2955), .Y(n3697) );
CLKBUFX2TS U1911 ( .A(n2310), .Y(n2928) );
INVX2TS U1912 ( .A(n1925), .Y(n1926) );
INVX2TS U1913 ( .A(n4675), .Y(n2955) );
BUFX3TS U1914 ( .A(Shift_reg_FLAGS_7[0]), .Y(n4675) );
OAI2BB2XLTS U1915 ( .B0(n2164), .B1(n2160), .A0N(n2159), .A1N(n2158), .Y(
n2161) );
INVX2TS U1916 ( .A(n3695), .Y(n4479) );
NOR2X1TS U1917 ( .A(n2606), .B(n2365), .Y(n2366) );
OAI2BB2XLTS U1918 ( .B0(intDX_EWSW[30]), .B1(n2231), .A0N(intDY_EWSW[31]),
.A1N(n1981), .Y(n2232) );
OAI2BB2XLTS U1919 ( .B0(intDX_EWSW[28]), .B1(n2225), .A0N(intDY_EWSW[29]),
.A1N(n1991), .Y(n2234) );
CLKBUFX2TS U1920 ( .A(Shift_reg_FLAGS_7[1]), .Y(n4468) );
NOR2X1TS U1921 ( .A(n2536), .B(n2535), .Y(n2778) );
NAND2X2TS U1922 ( .A(n2472), .B(n4505), .Y(n2774) );
NAND2XLTS U1923 ( .A(n2439), .B(n2055), .Y(n2057) );
NOR2X1TS U1924 ( .A(n3876), .B(n2073), .Y(n2075) );
NAND2X1TS U1925 ( .A(n2813), .B(n2135), .Y(n2137) );
NOR2X1TS U1926 ( .A(n3900), .B(n2061), .Y(n2063) );
NOR2X1TS U1927 ( .A(n3997), .B(n2029), .Y(n2031) );
NOR2X1TS U1928 ( .A(n4107), .B(n2013), .Y(n2015) );
NOR2X1TS U1929 ( .A(n3802), .B(n3815), .Y(n2813) );
NOR2X1TS U1930 ( .A(n4080), .B(n2019), .Y(n2021) );
AOI21X1TS U1931 ( .A0(n4210), .A1(n2102), .B0(n2101), .Y(n4130) );
NOR2X1TS U1932 ( .A(n4112), .B(n4192), .Y(n2108) );
XOR2X1TS U1933 ( .A(DP_OP_15J18_122_2221_n35), .B(n2333), .Y(n2338) );
NOR2X2TS U1934 ( .A(Raw_mant_NRM_SWR[54]), .B(Raw_mant_NRM_SWR[53]), .Y(
n2510) );
NOR3XLTS U1935 ( .A(Raw_mant_NRM_SWR[46]), .B(Raw_mant_NRM_SWR[45]), .C(
n4590), .Y(n2509) );
INVX2TS U1936 ( .A(n2496), .Y(n2497) );
NOR2X1TS U1937 ( .A(n3954), .B(n3915), .Y(n2123) );
NOR2X1TS U1938 ( .A(n3953), .B(n2043), .Y(n2045) );
OAI21X1TS U1939 ( .A0(n2717), .A1(n4168), .B0(n2718), .Y(n4116) );
NOR2XLTS U1940 ( .A(n2411), .B(n2112), .Y(n2114) );
OAI211XLTS U1941 ( .A0(n1963), .A1(intDY_EWSW[33]), .B0(n2301), .C0(n2300),
.Y(n2302) );
NOR2X4TS U1942 ( .A(n4506), .B(n4570), .Y(n2405) );
AOI21X1TS U1943 ( .A0(n2576), .A1(n2139), .B0(n2138), .Y(n3847) );
OAI21X2TS U1944 ( .A0(n3862), .A1(n3856), .B0(n3857), .Y(n3871) );
NOR2XLTS U1945 ( .A(n3439), .B(n2692), .Y(n2693) );
OR2X1TS U1946 ( .A(ADD_OVRFLW_NRM2), .B(LZD_output_NRM2_EW[0]), .Y(n2335) );
AOI21X2TS U1947 ( .A0(n3764), .A1(n2091), .B0(n2090), .Y(n3773) );
NOR2XLTS U1948 ( .A(n3374), .B(n4619), .Y(n3150) );
NOR2X1TS U1949 ( .A(n2801), .B(n2518), .Y(n2519) );
CLKINVX6TS U1950 ( .A(n3616), .Y(n3590) );
AFHCINX2TS U1951 ( .CIN(n2344), .B(n2345), .A(DMP_exp_NRM2_EW[3]), .S(n2356),
.CO(n2342) );
OAI21XLTS U1952 ( .A0(n3677), .A1(n4325), .B0(n3686), .Y(n3678) );
INVX2TS U1953 ( .A(n4466), .Y(n2310) );
CLKINVX3TS U1954 ( .A(ADD_OVRFLW_NRM2), .Y(n1918) );
INVX4TS U1955 ( .A(n2397), .Y(n3693) );
INVX2TS U1956 ( .A(n4396), .Y(n4395) );
BUFX3TS U1957 ( .A(n2314), .Y(n2930) );
CLKINVX3TS U1958 ( .A(n1995), .Y(n3459) );
OAI211XLTS U1959 ( .A0(n3222), .A1(n3459), .B0(n3221), .C0(n3220), .Y(n1733)
);
OAI211XLTS U1960 ( .A0(n3560), .A1(n3607), .B0(n3287), .C0(n3286), .Y(n1704)
);
OAI211XLTS U1961 ( .A0(n3321), .A1(n3607), .B0(n3320), .C0(n3319), .Y(n1708)
);
OAI211XLTS U1962 ( .A0(n3343), .A1(n3459), .B0(n3342), .C0(n3341), .Y(n1749)
);
OAI211XLTS U1963 ( .A0(n3422), .A1(n3584), .B0(n3421), .C0(n3420), .Y(n1718)
);
OAI211XLTS U1964 ( .A0(n3559), .A1(n3459), .B0(n3297), .C0(n3296), .Y(n1702)
);
OAI211XLTS U1965 ( .A0(n3570), .A1(n3594), .B0(n3569), .C0(n3568), .Y(n1707)
);
OAI211XLTS U1966 ( .A0(n3388), .A1(n3607), .B0(n3387), .C0(n3386), .Y(n1716)
);
OAI211XLTS U1967 ( .A0(n3391), .A1(n3418), .B0(n3390), .C0(n3389), .Y(n1726)
);
OAI211XLTS U1968 ( .A0(n3199), .A1(n3584), .B0(n3198), .C0(n3197), .Y(n1746)
);
OAI21XLTS U1969 ( .A0(n3625), .A1(n3047), .B0(n3018), .Y(n1200) );
OAI211XLTS U1970 ( .A0(n2810), .A1(n2809), .B0(n2808), .C0(n2807), .Y(n1695)
);
OAI21XLTS U1971 ( .A0(n4527), .A1(n3092), .B0(n2925), .Y(n1308) );
OAI21XLTS U1972 ( .A0(n4596), .A1(n3089), .B0(n3088), .Y(n1322) );
OAI21XLTS U1973 ( .A0(n4502), .A1(n3089), .B0(n2915), .Y(n1336) );
OAI21XLTS U1974 ( .A0(n4499), .A1(n3068), .B0(n3061), .Y(n1356) );
OAI21XLTS U1975 ( .A0(n4557), .A1(n3068), .B0(n2895), .Y(n1370) );
OAI21XLTS U1976 ( .A0(n4508), .A1(n3128), .B0(n3127), .Y(n1384) );
OAI21XLTS U1977 ( .A0(n4490), .A1(n3546), .B0(n2913), .Y(n1398) );
OAI21XLTS U1978 ( .A0(n4603), .A1(n3146), .B0(n3145), .Y(n1624) );
OAI21XLTS U1979 ( .A0(n4596), .A1(n3121), .B0(n3120), .Y(n1637) );
OAI21XLTS U1980 ( .A0(n4516), .A1(n3104), .B0(n2927), .Y(n1664) );
OAI211XLTS U1981 ( .A0(n3356), .A1(n3459), .B0(n3355), .C0(n3354), .Y(n1732)
);
OAI211XLTS U1982 ( .A0(n3304), .A1(n3584), .B0(n3303), .C0(n3302), .Y(n1706)
);
OAI211X1TS U1983 ( .A0(n3444), .A1(n3584), .B0(n3443), .C0(n3442), .Y(n1738)
);
OAI211X1TS U1984 ( .A0(n3452), .A1(n3459), .B0(n3451), .C0(n3450), .Y(n1741)
);
OAI211X1TS U1985 ( .A0(n3460), .A1(n3459), .B0(n3458), .C0(n3457), .Y(n1740)
);
OAI211X1TS U1986 ( .A0(n3585), .A1(n3584), .B0(n3583), .C0(n3582), .Y(n1715)
);
OAI21X1TS U1987 ( .A0(n3343), .A1(n3158), .B0(n2904), .Y(n1751) );
OAI211X1TS U1988 ( .A0(n3595), .A1(n3594), .B0(n3593), .C0(n3592), .Y(n1719)
);
OAI211X1TS U1989 ( .A0(n3403), .A1(n3607), .B0(n3402), .C0(n3401), .Y(n1743)
);
OAI211X1TS U1990 ( .A0(n3564), .A1(n3594), .B0(n3563), .C0(n3562), .Y(n1703)
);
OAI211X1TS U1991 ( .A0(n3332), .A1(n3594), .B0(n3331), .C0(n3330), .Y(n1731)
);
OAI211X1TS U1992 ( .A0(n3266), .A1(n3594), .B0(n3265), .C0(n3264), .Y(n1735)
);
OAI21X1TS U1993 ( .A0(n1935), .A1(n3039), .B0(n2975), .Y(n1203) );
OAI21X1TS U1994 ( .A0(n3621), .A1(n3047), .B0(n3046), .Y(n1202) );
OAI21X1TS U1995 ( .A0(n3626), .A1(n3039), .B0(n2954), .Y(n1201) );
OAI21X1TS U1996 ( .A0(n3629), .A1(n3047), .B0(n3032), .Y(n1192) );
OAI21X1TS U1997 ( .A0(n3051), .A1(n3628), .B0(n3020), .Y(n1177) );
OAI21X1TS U1998 ( .A0(n1936), .A1(n3039), .B0(n3036), .Y(n1161) );
OAI21X1TS U1999 ( .A0(n3627), .A1(n3047), .B0(n2994), .Y(n1176) );
OAI21X1TS U2000 ( .A0(n3619), .A1(n3047), .B0(n2966), .Y(n1206) );
OAI21X1TS U2001 ( .A0(n3632), .A1(n3051), .B0(n2877), .Y(n1160) );
OAI21X1TS U2002 ( .A0(n3633), .A1(n3051), .B0(n2890), .Y(n1168) );
OAI21X1TS U2003 ( .A0(n3051), .A1(n3639), .B0(n3013), .Y(n1175) );
OAI21X1TS U2004 ( .A0(n3620), .A1(n3047), .B0(n3034), .Y(n1207) );
OAI21X1TS U2005 ( .A0(n3051), .A1(n3644), .B0(n2957), .Y(n1173) );
OAI21X1TS U2006 ( .A0(n3647), .A1(n3051), .B0(n3050), .Y(n1159) );
OAI21X1TS U2007 ( .A0(n3642), .A1(n3047), .B0(n2946), .Y(n1172) );
OAI21X1TS U2008 ( .A0(n3638), .A1(n3047), .B0(n3042), .Y(n1174) );
OAI21X1TS U2009 ( .A0(n3635), .A1(n3051), .B0(n2884), .Y(n1170) );
OAI21X1TS U2010 ( .A0(n3622), .A1(n3047), .B0(n3002), .Y(n1204) );
OAI21X1TS U2011 ( .A0(n3646), .A1(n3051), .B0(n2864), .Y(n1158) );
OAI21X1TS U2012 ( .A0(n2732), .A1(n3047), .B0(n2370), .Y(n1157) );
OAI21X1TS U2013 ( .A0(n3051), .A1(n3636), .B0(n2968), .Y(n1171) );
OAI21X1TS U2014 ( .A0(n3630), .A1(n3039), .B0(n3038), .Y(n1193) );
OAI21X1TS U2015 ( .A0(n3623), .A1(n3039), .B0(n3015), .Y(n1205) );
OAI211X1TS U2016 ( .A0(n3616), .A1(n3233), .B0(n3157), .C0(n2570), .Y(n2571)
);
NAND2X6TS U2017 ( .A(n3164), .B(n2695), .Y(n3558) );
BUFX12TS U2018 ( .A(n2950), .Y(n3045) );
OAI21X1TS U2019 ( .A0(n3158), .A1(n3339), .B0(n2832), .Y(n1752) );
INVX3TS U2020 ( .A(n1995), .Y(n3418) );
INVX3TS U2021 ( .A(n1995), .Y(n3607) );
AO22XLTS U2022 ( .A0(n4385), .A1(n4288), .B0(final_result_ieee[34]), .B1(
n4383), .Y(n1190) );
INVX12TS U2023 ( .A(n3174), .Y(n2695) );
AO22XLTS U2024 ( .A0(n4381), .A1(n4328), .B0(final_result_ieee[15]), .B1(
n4377), .Y(n1189) );
OAI2BB1X2TS U2025 ( .A0N(n2148), .A1N(n3979), .B0(n2147), .Y(n1215) );
AO22XLTS U2026 ( .A0(n4385), .A1(n4287), .B0(final_result_ieee[35]), .B1(
n4383), .Y(n1188) );
NOR2X6TS U2027 ( .A(n3693), .B(n1929), .Y(n2950) );
AO22XLTS U2028 ( .A0(n4385), .A1(n4327), .B0(final_result_ieee[16]), .B1(
n4383), .Y(n1191) );
BUFX6TS U2029 ( .A(n2397), .Y(n4390) );
INVX4TS U2030 ( .A(n3680), .Y(n2397) );
NAND2X2TS U2031 ( .A(n2563), .B(n4369), .Y(n4373) );
OAI21X1TS U2032 ( .A0(n2803), .A1(n4374), .B0(n2802), .Y(n1211) );
XNOR2X1TS U2033 ( .A(n3133), .B(n3132), .Y(n3138) );
OAI21X1TS U2034 ( .A0(n2752), .A1(n2520), .B0(n2751), .Y(n1697) );
OAI21X1TS U2035 ( .A0(n2752), .A1(n3382), .B0(n2750), .Y(n1214) );
OAI21X1TS U2036 ( .A0(n4568), .A1(n3546), .B0(n2902), .Y(n1614) );
OAI21X1TS U2037 ( .A0(n4504), .A1(n3546), .B0(n2905), .Y(n1613) );
OAI21X1TS U2038 ( .A0(n4581), .A1(n3146), .B0(n3139), .Y(n1625) );
OAI21X1TS U2039 ( .A0(n4602), .A1(n3146), .B0(n3141), .Y(n1629) );
OAI21X1TS U2040 ( .A0(n4524), .A1(n3546), .B0(n2906), .Y(n1616) );
OAI21X1TS U2041 ( .A0(n4600), .A1(n3121), .B0(n3109), .Y(n1633) );
OAI21X1TS U2042 ( .A0(n4601), .A1(n3146), .B0(n3123), .Y(n1631) );
OAI21X1TS U2043 ( .A0(n4514), .A1(n3121), .B0(n3112), .Y(n1634) );
OAI21X1TS U2044 ( .A0(n4582), .A1(n4465), .B0(n3149), .Y(n1617) );
OAI21X1TS U2045 ( .A0(n4528), .A1(n3146), .B0(n3143), .Y(n1628) );
OAI21X1TS U2046 ( .A0(n4599), .A1(n3121), .B0(n3114), .Y(n1635) );
OAI21X1TS U2047 ( .A0(n4566), .A1(n3146), .B0(n3142), .Y(n1627) );
OAI21X1TS U2048 ( .A0(n4527), .A1(n3146), .B0(n3055), .Y(n1630) );
OAI21X1TS U2049 ( .A0(n4603), .A1(n4465), .B0(n2318), .Y(n1296) );
OAI21X1TS U2050 ( .A0(n4515), .A1(n3146), .B0(n3053), .Y(n1632) );
OAI21X1TS U2051 ( .A0(n4517), .A1(n3146), .B0(n2903), .Y(n1626) );
OAI21X1TS U2052 ( .A0(n4583), .A1(n3546), .B0(n2910), .Y(n1615) );
OAI21X1TS U2053 ( .A0(n4526), .A1(n3121), .B0(n2901), .Y(n1636) );
OAI21X1TS U2054 ( .A0(n4602), .A1(n3092), .B0(n2316), .Y(n1306) );
OAI21X1TS U2055 ( .A0(n4491), .A1(n3128), .B0(n3060), .Y(n1380) );
OAI21X1TS U2056 ( .A0(n4579), .A1(n3128), .B0(n3065), .Y(n1386) );
OAI21X1TS U2057 ( .A0(n4496), .A1(n3104), .B0(n2849), .Y(n1672) );
OAI21X1TS U2058 ( .A0(n4509), .A1(n3128), .B0(n3124), .Y(n1388) );
OAI21X1TS U2059 ( .A0(n4509), .A1(n3104), .B0(n2313), .Y(n1670) );
OAI21X1TS U2060 ( .A0(n4507), .A1(n3128), .B0(n3064), .Y(n1378) );
OAI21X1TS U2061 ( .A0(n4516), .A1(n3128), .B0(n2909), .Y(n1376) );
OAI21X1TS U2062 ( .A0(n4554), .A1(n3128), .B0(n3075), .Y(n1390) );
OAI21X1TS U2063 ( .A0(n4555), .A1(n3128), .B0(n2908), .Y(n1382) );
OAI21X1TS U2064 ( .A0(n4556), .A1(n3068), .B0(n3056), .Y(n1374) );
OAI21X1TS U2065 ( .A0(n4512), .A1(n3121), .B0(n3052), .Y(n1642) );
OAI21X1TS U2066 ( .A0(n4496), .A1(n3128), .B0(n2894), .Y(n1392) );
OAI21X1TS U2067 ( .A0(n4497), .A1(n3068), .B0(n3062), .Y(n1372) );
OAI21X1TS U2068 ( .A0(n4597), .A1(n3121), .B0(n3101), .Y(n1641) );
OAI21X1TS U2069 ( .A0(n4553), .A1(n3128), .B0(n3069), .Y(n1394) );
OAI21X1TS U2070 ( .A0(n4579), .A1(n3104), .B0(n2851), .Y(n1669) );
OAI21X1TS U2071 ( .A0(n4595), .A1(n3546), .B0(n2897), .Y(n1396) );
OAI21X1TS U2072 ( .A0(n4600), .A1(n3092), .B0(n3081), .Y(n1314) );
OAI21X1TS U2073 ( .A0(n4498), .A1(n3068), .B0(n2893), .Y(n1368) );
OAI21X1TS U2074 ( .A0(n4525), .A1(n3089), .B0(n3085), .Y(n1324) );
OAI21X1TS U2075 ( .A0(n4578), .A1(n3068), .B0(n3067), .Y(n1366) );
OAI21X1TS U2076 ( .A0(n4490), .A1(n3146), .B0(n3140), .Y(n1675) );
OAI21X1TS U2077 ( .A0(n4599), .A1(n3089), .B0(n3083), .Y(n1318) );
OAI21X1TS U2078 ( .A0(n4492), .A1(n3068), .B0(n2912), .Y(n1364) );
OAI21X1TS U2079 ( .A0(n4501), .A1(n3080), .B0(n2315), .Y(n1340) );
OAI21X1TS U2080 ( .A0(n4495), .A1(n3080), .B0(n3079), .Y(n1344) );
OAI21X1TS U2081 ( .A0(n4526), .A1(n3089), .B0(n2899), .Y(n1320) );
OAI21X1TS U2082 ( .A0(n4598), .A1(n3121), .B0(n2937), .Y(n1639) );
OAI21X1TS U2083 ( .A0(n4559), .A1(n3068), .B0(n3059), .Y(n1358) );
OAI21X1TS U2084 ( .A0(n4513), .A1(n3121), .B0(n3054), .Y(n1640) );
OAI21X1TS U2085 ( .A0(n4503), .A1(n4467), .B0(n2850), .Y(n1618) );
OAI21X1TS U2086 ( .A0(n4563), .A1(n3080), .B0(n3071), .Y(n1342) );
OAI21X1TS U2087 ( .A0(n4554), .A1(n3104), .B0(n2853), .Y(n1671) );
OAI21X1TS U2088 ( .A0(n4493), .A1(n3068), .B0(n3063), .Y(n1360) );
OAI21X1TS U2089 ( .A0(n4508), .A1(n3104), .B0(n2312), .Y(n1668) );
OAI21X1TS U2090 ( .A0(n4558), .A1(n3068), .B0(n2911), .Y(n1362) );
OAI21X1TS U2091 ( .A0(n4515), .A1(n3092), .B0(n2921), .Y(n1312) );
OAI21X1TS U2092 ( .A0(n4562), .A1(n3080), .B0(n2917), .Y(n1346) );
OAI21X1TS U2093 ( .A0(n4601), .A1(n3092), .B0(n3091), .Y(n1310) );
OAI21X1TS U2094 ( .A0(n4525), .A1(n3121), .B0(n3118), .Y(n1638) );
OAI21X1TS U2095 ( .A0(n4564), .A1(n3080), .B0(n3070), .Y(n1338) );
OAI21X1TS U2096 ( .A0(n4560), .A1(n3117), .B0(n3097), .Y(n1653) );
OAI21X1TS U2097 ( .A0(n4491), .A1(n3104), .B0(n3099), .Y(n1666) );
OAI21X1TS U2098 ( .A0(n4555), .A1(n3104), .B0(n2926), .Y(n1667) );
OAI21X1TS U2099 ( .A0(n4497), .A1(n3104), .B0(n3103), .Y(n1662) );
OAI21X1TS U2100 ( .A0(n4556), .A1(n3104), .B0(n3093), .Y(n1663) );
OAI21X1TS U2101 ( .A0(n4499), .A1(n3117), .B0(n3105), .Y(n1654) );
INVX4TS U2102 ( .A(n3144), .Y(n4465) );
OAI21X1TS U2103 ( .A0(n4578), .A1(n3117), .B0(n3116), .Y(n1659) );
OAI21X1TS U2104 ( .A0(n4498), .A1(n3117), .B0(n2898), .Y(n1660) );
OAI21X1TS U2105 ( .A0(n4493), .A1(n3117), .B0(n3108), .Y(n1656) );
OAI21X1TS U2106 ( .A0(n4492), .A1(n3117), .B0(n2935), .Y(n1658) );
OAI21X1TS U2107 ( .A0(n4558), .A1(n3117), .B0(n2934), .Y(n1657) );
OAI21X1TS U2108 ( .A0(n4559), .A1(n3117), .B0(n3096), .Y(n1655) );
OAI21X1TS U2109 ( .A0(n4557), .A1(n3117), .B0(n2900), .Y(n1661) );
OAI21X1TS U2110 ( .A0(n4500), .A1(n3117), .B0(n2929), .Y(n1652) );
INVX3TS U2111 ( .A(n2930), .Y(n3126) );
INVX3TS U2112 ( .A(n2930), .Y(n3148) );
BUFX6TS U2113 ( .A(n2931), .Y(n3057) );
INVX3TS U2114 ( .A(n2896), .Y(n3128) );
INVX3TS U2115 ( .A(n2930), .Y(n3066) );
INVX3TS U2116 ( .A(n2914), .Y(n3087) );
INVX3TS U2117 ( .A(n2914), .Y(n3078) );
INVX3TS U2118 ( .A(n2914), .Y(n3090) );
INVX3TS U2119 ( .A(n2896), .Y(n3068) );
INVX2TS U2120 ( .A(n2931), .Y(n3080) );
NAND3X1TS U2121 ( .A(n2558), .B(Raw_mant_NRM_SWR[11]), .C(n4574), .Y(n2559)
);
NOR2X1TS U2122 ( .A(n2446), .B(n2359), .Y(n2364) );
NAND2BX1TS U2123 ( .AN(n2349), .B(n2446), .Y(n2350) );
OAI21X1TS U2124 ( .A0(n2732), .A1(n3670), .B0(n2729), .Y(n1103) );
OAI21X1TS U2125 ( .A0(n2732), .A1(n3668), .B0(n2731), .Y(n1155) );
NAND3BX1TS U2126 ( .AN(n2346), .B(n2445), .C(n2356), .Y(n2349) );
NAND3X1TS U2127 ( .A(n2538), .B(Raw_mant_NRM_SWR[37]), .C(n4616), .Y(n2539)
);
OAI21X2TS U2128 ( .A0(n3618), .A1(n4630), .B0(n3173), .Y(n1904) );
OR2X6TS U2129 ( .A(n2131), .B(n2130), .Y(n2574) );
OAI21X1TS U2130 ( .A0(n3682), .A1(n4325), .B0(n3686), .Y(n3683) );
NAND3X1TS U2131 ( .A(n2514), .B(n2523), .C(n2513), .Y(n2515) );
INVX2TS U2132 ( .A(n4452), .Y(n3698) );
AND3X1TS U2133 ( .A(n2690), .B(n4468), .C(n2689), .Y(n3339) );
INVX2TS U2134 ( .A(n4452), .Y(n3702) );
AOI211X2TS U2135 ( .A0(n3649), .A1(n3030), .B0(n3029), .C0(n1917), .Y(n3630)
);
NAND3X1TS U2136 ( .A(n4301), .B(n1908), .C(n4300), .Y(n4380) );
INVX2TS U2137 ( .A(n4452), .Y(n3699) );
INVX2TS U2138 ( .A(n4452), .Y(n4449) );
AO22XLTS U2139 ( .A0(n4429), .A1(add_subt), .B0(n4427), .B1(intAS), .Y(n1819) );
INVX1TS U2140 ( .A(n3681), .Y(n3682) );
INVX3TS U2141 ( .A(n4286), .Y(n4342) );
NAND3X1TS U2142 ( .A(n2357), .B(n2447), .C(n2448), .Y(n2346) );
INVX1TS U2143 ( .A(n3672), .Y(n3673) );
INVX1TS U2144 ( .A(n3676), .Y(n3677) );
NOR2X2TS U2145 ( .A(n2115), .B(n2371), .Y(n2131) );
AND2X2TS U2146 ( .A(n4286), .B(n1927), .Y(n3624) );
INVX1TS U2147 ( .A(n3685), .Y(n3687) );
NOR2X1TS U2148 ( .A(n3028), .B(n3659), .Y(n3029) );
AND2X2TS U2149 ( .A(n4286), .B(n1928), .Y(n3631) );
INVX3TS U2150 ( .A(n4286), .Y(n4349) );
AOI21X1TS U2151 ( .A0(n2438), .A1(n2055), .B0(n2054), .Y(n2056) );
INVX3TS U2152 ( .A(n2520), .Y(n3380) );
OAI211X2TS U2153 ( .A0(n2866), .A1(n4608), .B0(n2645), .C0(n2609), .Y(n2949)
);
INVX3TS U2154 ( .A(n2520), .Y(n3361) );
OAI21X1TS U2155 ( .A0(n2178), .A1(n2177), .B0(n2176), .Y(n2180) );
NOR2X1TS U2156 ( .A(n3365), .B(n4620), .Y(n2566) );
AOI211X1TS U2157 ( .A0(n2235), .A1(n2234), .B0(n2233), .C0(n2232), .Y(n2299)
);
INVX3TS U2158 ( .A(n2520), .Y(n3430) );
OAI211X2TS U2159 ( .A0(n2658), .A1(n4610), .B0(n2401), .C0(n2986), .Y(n3000)
);
BUFX3TS U2160 ( .A(n4418), .Y(n4414) );
INVX3TS U2161 ( .A(n1899), .Y(n3439) );
OAI21X2TS U2162 ( .A0(n3779), .A1(n2071), .B0(n2070), .Y(n2824) );
INVX3TS U2163 ( .A(n1899), .Y(n3611) );
NOR2X1TS U2164 ( .A(n2207), .B(n2206), .Y(n2221) );
OAI211X1TS U2165 ( .A0(intDX_EWSW[61]), .A1(n1992), .B0(n2157), .C0(n2156),
.Y(n2158) );
CLKINVX2TS U2166 ( .A(n3787), .Y(n3788) );
NOR2X1TS U2167 ( .A(n2477), .B(n2484), .Y(n2479) );
OR2X2TS U2168 ( .A(n3696), .B(ADD_OVRFLW_NRM), .Y(n2520) );
AND2X4TS U2169 ( .A(beg_OP), .B(n4400), .Y(n4418) );
AOI211X1TS U2170 ( .A0(intDX_EWSW[16]), .A1(n2273), .B0(n2280), .C0(n2286),
.Y(n2275) );
INVX3TS U2171 ( .A(n4472), .Y(n4441) );
INVX2TS U2172 ( .A(n4472), .Y(n3701) );
AOI211X1TS U2173 ( .A0(intDX_EWSW[52]), .A1(n4518), .B0(n2162), .C0(n2206),
.Y(n2208) );
INVX3TS U2174 ( .A(n2658), .Y(n2981) );
OAI211X2TS U2175 ( .A0(intDY_EWSW[20]), .A1(n1962), .B0(n2291), .C0(n2274),
.Y(n2285) );
NAND3X1TS U2176 ( .A(n2155), .B(n2154), .C(intDY_EWSW[60]), .Y(n2156) );
OAI211X2TS U2177 ( .A0(intDY_EWSW[28]), .A1(n1986), .B0(n2235), .C0(n2226),
.Y(n2294) );
NOR2X1TS U2178 ( .A(n2521), .B(Raw_mant_NRM_SWR[9]), .Y(n2527) );
INVX3TS U2179 ( .A(n2866), .Y(n2982) );
OAI211X2TS U2180 ( .A0(intDY_EWSW[12]), .A1(n1961), .B0(n2272), .C0(n2252),
.Y(n2266) );
CLKXOR2X2TS U2181 ( .A(DP_OP_15J18_122_2221_n35), .B(n2335), .Y(n2339) );
INVX2TS U2182 ( .A(n3828), .Y(n3831) );
INVX2TS U2183 ( .A(n3900), .Y(n3903) );
INVX3TS U2184 ( .A(n4468), .Y(n3696) );
NAND2BX1TS U2185 ( .AN(intDX_EWSW[62]), .B(intDY_EWSW[62]), .Y(n2157) );
INVX1TS U2186 ( .A(Shift_reg_FLAGS_7[2]), .Y(n3695) );
NOR2X1TS U2187 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[21]), .Y(
n2465) );
NOR2X1TS U2188 ( .A(Raw_mant_NRM_SWR[19]), .B(Raw_mant_NRM_SWR[22]), .Y(
n2463) );
NOR2X1TS U2189 ( .A(Raw_mant_NRM_SWR[24]), .B(Raw_mant_NRM_SWR[20]), .Y(
n2464) );
NAND2BX1TS U2190 ( .AN(intDY_EWSW[51]), .B(intDX_EWSW[51]), .Y(n2211) );
NAND2BX1TS U2191 ( .AN(intDY_EWSW[29]), .B(intDX_EWSW[29]), .Y(n2226) );
NAND2BX1TS U2192 ( .AN(intDY_EWSW[32]), .B(intDX_EWSW[32]), .Y(n2301) );
NAND2BX1TS U2193 ( .AN(intDY_EWSW[59]), .B(intDX_EWSW[59]), .Y(n2150) );
INVX3TS U2194 ( .A(Shift_reg_FLAGS_7[1]), .Y(n3382) );
NAND2BX1TS U2195 ( .AN(intDY_EWSW[62]), .B(intDX_EWSW[62]), .Y(n2159) );
NOR2X1TS U2196 ( .A(Raw_mant_NRM_SWR[8]), .B(n4575), .Y(n2521) );
NAND2BX1TS U2197 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n2228) );
OR2X2TS U2198 ( .A(n4520), .B(n4612), .Y(n1908) );
INVX3TS U2199 ( .A(n4484), .Y(n4466) );
NAND2BX1TS U2200 ( .AN(intDY_EWSW[40]), .B(intDX_EWSW[40]), .Y(n2182) );
NAND2BX1TS U2201 ( .AN(intDY_EWSW[21]), .B(intDX_EWSW[21]), .Y(n2274) );
NAND2BX1TS U2202 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2169) );
NAND2BX1TS U2203 ( .AN(intDY_EWSW[41]), .B(intDX_EWSW[41]), .Y(n2183) );
OAI21X1TS U2204 ( .A0(intDY_EWSW[31]), .A1(n1981), .B0(intDY_EWSW[30]), .Y(
n2231) );
OR2X4TS U2205 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[5]),
.Y(n2323) );
NAND2BX1TS U2206 ( .AN(intDY_EWSW[19]), .B(intDX_EWSW[19]), .Y(n2282) );
OAI2BB1X2TS U2207 ( .A0N(n3979), .A1N(n3138), .B0(n3137), .Y(n1216) );
NOR2X2TS U2208 ( .A(n3980), .B(n2039), .Y(n2439) );
NOR3X4TS U2209 ( .A(Raw_mant_NRM_SWR[50]), .B(Raw_mant_NRM_SWR[49]), .C(
Raw_mant_NRM_SWR[48]), .Y(n2740) );
NAND2X4TS U2210 ( .A(n2744), .B(n2489), .Y(n2536) );
OAI21X2TS U2211 ( .A0(n4130), .A1(n2106), .B0(n2105), .Y(n2409) );
OAI21X2TS U2212 ( .A0(n3746), .A1(n3740), .B0(n3741), .Y(n3735) );
NOR2X2TS U2213 ( .A(n3780), .B(n2071), .Y(n2823) );
AFHCONX2TS U2214 ( .A(DMP_exp_NRM2_EW[4]), .B(n2343), .CI(n2342), .CON(n2347), .S(n2445) );
OAI21X1TS U2215 ( .A0(n3051), .A1(n3634), .B0(n3004), .Y(n1169) );
AOI21X4TS U2216 ( .A0(n3744), .A1(n2095), .B0(n2094), .Y(n3734) );
OAI21X2TS U2217 ( .A0(n3773), .A1(n2093), .B0(n2092), .Y(n3744) );
OAI21X2TS U2218 ( .A0(n3981), .A1(n2039), .B0(n2038), .Y(n2438) );
NAND2X4TS U2219 ( .A(n2510), .B(n2512), .Y(n2739) );
AND2X4TS U2220 ( .A(n2694), .B(n2693), .Y(n3164) );
OAI211X1TS U2221 ( .A0(n3412), .A1(n3459), .B0(n3411), .C0(n3410), .Y(n1737)
);
AOI21X4TS U2222 ( .A0(n3894), .A1(n2087), .B0(n2086), .Y(n3754) );
OAI21X2TS U2223 ( .A0(n4123), .A1(n2009), .B0(n2008), .Y(n2712) );
OAI21X2TS U2224 ( .A0(n3734), .A1(n2097), .B0(n2096), .Y(n3133) );
OAI21X1TS U2225 ( .A0(n3714), .A1(n2053), .B0(n2052), .Y(n2054) );
OAI21X2TS U2226 ( .A0(n3754), .A1(n2089), .B0(n2088), .Y(n3764) );
OAI21X4TS U2227 ( .A0(n3896), .A1(n3890), .B0(n3891), .Y(n3755) );
OAI21X4TS U2228 ( .A0(n3766), .A1(n3760), .B0(n3761), .Y(n3774) );
NAND2X2TS U2229 ( .A(n2593), .B(n2063), .Y(n3780) );
AOI21X4TS U2230 ( .A0(n3860), .A1(n2083), .B0(n2082), .Y(n3869) );
OAI21X2TS U2231 ( .A0(n3846), .A1(n2081), .B0(n2080), .Y(n3860) );
XOR2X4TS U2232 ( .A(n2100), .B(n4659), .Y(n2148) );
OAI211X1TS U2233 ( .A0(intDY_EWSW[36]), .A1(n1968), .B0(n2197), .C0(n2191),
.Y(n2304) );
OA22X1TS U2234 ( .A0(n1971), .A1(intDY_EWSW[42]), .B0(n1972), .B1(
intDY_EWSW[43]), .Y(n2184) );
CLKAND2X2TS U2235 ( .A(n4639), .B(DMP_SFG[49]), .Y(n2094) );
CLKAND2X2TS U2236 ( .A(n4640), .B(DMP_SFG[45]), .Y(n2086) );
NOR2X1TS U2237 ( .A(n1985), .B(intDY_EWSW[57]), .Y(n2165) );
OAI21XLTS U2238 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n2542), .B0(n4569), .Y(n2548) );
NOR2XLTS U2239 ( .A(Raw_mant_NRM_SWR[4]), .B(n4576), .Y(n2542) );
INVX2TS U2240 ( .A(n4358), .Y(n3934) );
INVX2TS U2241 ( .A(n2371), .Y(n4027) );
CLKAND2X2TS U2242 ( .A(n4624), .B(DMP_SFG[51]), .Y(n2098) );
CLKAND2X2TS U2243 ( .A(n4613), .B(DMP_SFG[47]), .Y(n2090) );
CLKAND2X2TS U2244 ( .A(n4641), .B(DMP_SFG[43]), .Y(n2082) );
BUFX3TS U2245 ( .A(n2930), .Y(n4467) );
NAND2BXLTS U2246 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n2261) );
NOR2X1TS U2247 ( .A(n1989), .B(intDY_EWSW[11]), .Y(n2259) );
NAND2BXLTS U2248 ( .AN(intDY_EWSW[13]), .B(intDX_EWSW[13]), .Y(n2252) );
NAND3XLTS U2249 ( .A(n1950), .B(n2261), .C(intDY_EWSW[8]), .Y(n2263) );
NAND2BXLTS U2250 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n2262) );
NOR2BX1TS U2251 ( .AN(n2189), .B(n2188), .Y(n2194) );
OAI2BB2XLTS U2252 ( .B0(intDX_EWSW[32]), .B1(n2187), .A0N(intDY_EWSW[33]),
.A1N(n1963), .Y(n2189) );
OAI21XLTS U2253 ( .A0(intDY_EWSW[33]), .A1(n1963), .B0(intDY_EWSW[32]), .Y(
n2187) );
OAI2BB2XLTS U2254 ( .B0(intDX_EWSW[34]), .B1(n2190), .A0N(intDY_EWSW[35]),
.A1N(n1967), .Y(n2193) );
OAI21XLTS U2255 ( .A0(intDY_EWSW[35]), .A1(n1967), .B0(intDY_EWSW[34]), .Y(
n2190) );
NOR2X1TS U2256 ( .A(n3790), .B(n3782), .Y(n2133) );
NOR2X1TS U2257 ( .A(n4038), .B(n2434), .Y(n2119) );
NAND2X1TS U2258 ( .A(n2433), .B(n2119), .Y(n2121) );
NOR2X1TS U2259 ( .A(n4067), .B(n4061), .Y(n2117) );
OAI21XLTS U2260 ( .A0(n2418), .A1(n4084), .B0(n2419), .Y(n2109) );
OAI21XLTS U2261 ( .A0(n2019), .A1(n4081), .B0(n2018), .Y(n2020) );
OA22X1TS U2262 ( .A0(n1979), .A1(intDY_EWSW[30]), .B0(n1981), .B1(
intDY_EWSW[31]), .Y(n2235) );
AOI2BB2XLTS U2263 ( .B0(intDY_EWSW[53]), .B1(n2205), .A0N(intDX_EWSW[52]),
.A1N(n2204), .Y(n2207) );
OAI21XLTS U2264 ( .A0(intDY_EWSW[53]), .A1(n2205), .B0(intDY_EWSW[52]), .Y(
n2204) );
OAI21XLTS U2265 ( .A0(intDY_EWSW[55]), .A1(n2216), .B0(intDY_EWSW[54]), .Y(
n2217) );
OAI2BB2XLTS U2266 ( .B0(intDX_EWSW[42]), .B1(n2173), .A0N(intDY_EWSW[43]),
.A1N(n1972), .Y(n2174) );
OAI21XLTS U2267 ( .A0(intDY_EWSW[43]), .A1(n1972), .B0(intDY_EWSW[42]), .Y(
n2173) );
OAI21X1TS U2268 ( .A0(intDY_EWSW[50]), .A1(n1956), .B0(n2211), .Y(n2215) );
NOR2XLTS U2269 ( .A(n2165), .B(intDX_EWSW[56]), .Y(n2149) );
OR2X1TS U2270 ( .A(Raw_mant_NRM_SWR[48]), .B(Raw_mant_NRM_SWR[47]), .Y(n2508) );
NOR2XLTS U2271 ( .A(Raw_mant_NRM_SWR[50]), .B(Raw_mant_NRM_SWR[49]), .Y(
n2507) );
NAND2X1TS U2272 ( .A(n3810), .B(n2069), .Y(n2071) );
NAND2X1TS U2273 ( .A(n4145), .B(n2104), .Y(n2106) );
NOR2X1TS U2274 ( .A(n4156), .B(n4151), .Y(n2104) );
OAI21XLTS U2275 ( .A0(n2013), .A1(n4108), .B0(n2012), .Y(n2014) );
NAND2X1TS U2276 ( .A(n2713), .B(n2015), .Y(n4075) );
NOR2X1TS U2277 ( .A(n2817), .B(n2819), .Y(n2135) );
NAND2X1TS U2278 ( .A(n3718), .B(n2051), .Y(n2053) );
NAND2X1TS U2279 ( .A(n3921), .B(n2123), .Y(n2374) );
OAI21XLTS U2280 ( .A0(n3915), .A1(n3955), .B0(n3916), .Y(n2122) );
OAI21XLTS U2281 ( .A0(n2043), .A1(n3952), .B0(n2042), .Y(n2044) );
NAND2X1TS U2282 ( .A(n3950), .B(n2045), .Y(n3713) );
NOR2X1TS U2283 ( .A(n4357), .B(n4351), .Y(n3921) );
OAI21X1TS U2284 ( .A0(n4351), .A1(n4356), .B0(n4352), .Y(n3920) );
OAI21XLTS U2285 ( .A0(n2035), .A1(n4036), .B0(n2034), .Y(n2036) );
OAI21XLTS U2286 ( .A0(n4192), .A1(n4197), .B0(n4193), .Y(n2107) );
NAND2X1TS U2287 ( .A(n4115), .B(n2108), .Y(n2411) );
CLKAND2X2TS U2288 ( .A(n2674), .B(n2673), .Y(n4326) );
NAND4XLTS U2289 ( .A(n2404), .B(n2403), .C(n2402), .D(n3024), .Y(n3675) );
INVX2TS U2290 ( .A(n4210), .Y(n4240) );
OR2X1TS U2291 ( .A(shift_value_SHT2_EWR[4]), .B(n4520), .Y(n2393) );
CLKAND2X2TS U2292 ( .A(n2322), .B(n2321), .Y(n4314) );
NAND4XLTS U2293 ( .A(n2621), .B(n2620), .C(n2619), .D(n3024), .Y(n3684) );
NAND4XLTS U2294 ( .A(n2661), .B(n2660), .C(n2659), .D(n3024), .Y(n3679) );
NAND4XLTS U2295 ( .A(n2612), .B(n2611), .C(n2610), .D(n3024), .Y(n3690) );
CLKAND2X2TS U2296 ( .A(n3656), .B(n3655), .Y(n4341) );
CLKAND2X2TS U2297 ( .A(n2669), .B(n2668), .Y(n4332) );
OAI21XLTS U2298 ( .A0(n2774), .A1(n4625), .B0(n2773), .Y(n2775) );
OAI21XLTS U2299 ( .A0(n2793), .A1(n4666), .B0(n2759), .Y(n2760) );
NAND3XLTS U2300 ( .A(n2758), .B(n1993), .C(n2757), .Y(n2759) );
NOR2XLTS U2301 ( .A(Raw_mant_NRM_SWR[40]), .B(Raw_mant_NRM_SWR[42]), .Y(
n2738) );
OAI21XLTS U2302 ( .A0(Raw_mant_NRM_SWR[6]), .A1(Raw_mant_NRM_SWR[4]), .B0(
n2733), .Y(n2736) );
AOI21X1TS U2303 ( .A0(n3735), .A1(n3732), .B0(n2145), .Y(n3135) );
OAI21X1TS U2304 ( .A0(n3806), .A1(n2816), .B0(n2815), .Y(n3838) );
OAI21X1TS U2305 ( .A0(n3849), .A1(n2812), .B0(n2811), .Y(n3822) );
INVX2TS U2306 ( .A(n3802), .Y(n3821) );
INVX2TS U2307 ( .A(n2422), .Y(n4011) );
INVX2TS U2308 ( .A(n4099), .Y(n4184) );
INVX2TS U2309 ( .A(n2161), .Y(n2309) );
INVX2TS U2310 ( .A(n3158), .Y(n3551) );
AND3X1TS U2311 ( .A(n3326), .B(n3325), .C(n3324), .Y(n3344) );
OR2X1TS U2312 ( .A(n3365), .B(n4594), .Y(n3329) );
INVX2TS U2313 ( .A(n4024), .Y(n4025) );
OR2X1TS U2314 ( .A(n3618), .B(n4593), .Y(n3167) );
OR2X1TS U2315 ( .A(n3618), .B(n4611), .Y(n3163) );
AND3X1TS U2316 ( .A(n3262), .B(n3261), .C(n3260), .Y(n3473) );
CLKINVX6TS U2317 ( .A(n3558), .Y(n3588) );
AO21XLTS U2318 ( .A0(n3027), .A1(n4298), .B0(n3648), .Y(n1902) );
AO21XLTS U2319 ( .A0(n2971), .A1(n3022), .B0(n2970), .Y(n1900) );
AO21XLTS U2320 ( .A0(n2969), .A1(n3649), .B0(n1916), .Y(n2970) );
NOR2X4TS U2321 ( .A(n2368), .B(n2367), .Y(n4392) );
INVX2TS U2322 ( .A(n2350), .Y(n2351) );
INVX2TS U2323 ( .A(n4107), .Y(n4110) );
INVX2TS U2324 ( .A(n4222), .Y(n4132) );
INVX2TS U2325 ( .A(n4123), .Y(n4221) );
OAI21XLTS U2326 ( .A0(n4157), .A1(n4156), .B0(n4155), .Y(n4159) );
AO21XLTS U2327 ( .A0(n2963), .A1(n4298), .B0(n1917), .Y(n2964) );
AO21XLTS U2328 ( .A0(n2998), .A1(n4298), .B0(n1917), .Y(n2999) );
AO21XLTS U2329 ( .A0(n2947), .A1(n3649), .B0(n1917), .Y(n2948) );
NAND3BXLTS U2330 ( .AN(n2801), .B(n2800), .C(n2799), .Y(n2805) );
OAI21X1TS U2331 ( .A0(n3135), .A1(n3129), .B0(n3130), .Y(n4366) );
NOR2XLTS U2332 ( .A(n4657), .B(DMP_SFG[50]), .Y(n2097) );
NOR2XLTS U2333 ( .A(n4623), .B(DMP_SFG[48]), .Y(n2093) );
NOR2XLTS U2334 ( .A(n4614), .B(DMP_SFG[46]), .Y(n2089) );
OAI21X1TS U2335 ( .A0(n3869), .A1(n2085), .B0(n2084), .Y(n3894) );
NOR2XLTS U2336 ( .A(n4658), .B(DMP_SFG[44]), .Y(n2085) );
NOR2XLTS U2337 ( .A(n4642), .B(DMP_SFG[42]), .Y(n2081) );
OAI21XLTS U2338 ( .A0(n3849), .A1(n3848), .B0(n3847), .Y(n3851) );
INVX2TS U2339 ( .A(n2579), .Y(n3882) );
INVX2TS U2340 ( .A(n2575), .Y(n2578) );
OAI21XLTS U2341 ( .A0(n3781), .A1(n2586), .B0(n2585), .Y(n2589) );
INVX2TS U2342 ( .A(n3810), .Y(n3813) );
INVX2TS U2343 ( .A(n3797), .Y(n3800) );
INVX2TS U2344 ( .A(n3905), .Y(n3791) );
INVX2TS U2345 ( .A(n2594), .Y(n2595) );
INVX2TS U2346 ( .A(n2384), .Y(n3781) );
OAI21XLTS U2347 ( .A0(n3971), .A1(n3970), .B0(n3969), .Y(n3973) );
OAI21XLTS U2348 ( .A0(n4358), .A1(n4357), .B0(n4356), .Y(n4360) );
INVX2TS U2349 ( .A(n2416), .Y(n4085) );
INVX2TS U2350 ( .A(n3057), .Y(n3092) );
INVX2TS U2351 ( .A(n3057), .Y(n3089) );
NAND4XLTS U2352 ( .A(n3497), .B(n3496), .C(n3495), .D(n3494), .Y(n3544) );
NAND4XLTS U2353 ( .A(n3505), .B(n3504), .C(n3503), .D(n3502), .Y(n3543) );
NAND4XLTS U2354 ( .A(n3489), .B(n3488), .C(n3487), .D(n3486), .Y(n3545) );
BUFX3TS U2355 ( .A(n2931), .Y(n3122) );
BUFX3TS U2356 ( .A(n2931), .Y(n3113) );
BUFX3TS U2357 ( .A(n2914), .Y(n3146) );
AND3X1TS U2358 ( .A(n3216), .B(n3215), .C(n3214), .Y(n3356) );
OR2X1TS U2359 ( .A(n3365), .B(n4669), .Y(n3210) );
OR2X1TS U2360 ( .A(n3429), .B(n4519), .Y(n3406) );
OR2X1TS U2361 ( .A(n3429), .B(n4672), .Y(n3409) );
OR2X1TS U2362 ( .A(n3365), .B(n4590), .Y(n3368) );
OR2X1TS U2363 ( .A(n3429), .B(n4589), .Y(n3434) );
AO22XLTS U2364 ( .A0(n4409), .A1(Data_X[45]), .B0(n4408), .B1(intDX_EWSW[45]), .Y(n1838) );
AO22XLTS U2365 ( .A0(n4409), .A1(Data_X[43]), .B0(n4408), .B1(intDX_EWSW[43]), .Y(n1840) );
AO22XLTS U2366 ( .A0(n4406), .A1(Data_X[35]), .B0(n4405), .B1(intDX_EWSW[35]), .Y(n1848) );
AO22XLTS U2367 ( .A0(n4409), .A1(Data_X[50]), .B0(n4408), .B1(intDX_EWSW[50]), .Y(n1833) );
AO22XLTS U2368 ( .A0(n4406), .A1(Data_X[36]), .B0(n4405), .B1(intDX_EWSW[36]), .Y(n1847) );
AO22XLTS U2369 ( .A0(n4409), .A1(Data_X[31]), .B0(n4405), .B1(intDX_EWSW[31]), .Y(n1852) );
AO22XLTS U2370 ( .A0(n4429), .A1(Data_Y[59]), .B0(n4427), .B1(intDY_EWSW[59]), .Y(n1759) );
AO22XLTS U2371 ( .A0(n4409), .A1(Data_X[46]), .B0(n4408), .B1(intDX_EWSW[46]), .Y(n1837) );
AO22XLTS U2372 ( .A0(n4409), .A1(Data_X[51]), .B0(n4427), .B1(intDX_EWSW[51]), .Y(n1832) );
AO22XLTS U2373 ( .A0(n4429), .A1(Data_X[63]), .B0(n4427), .B1(intDX_EWSW[63]), .Y(n1820) );
AO22XLTS U2374 ( .A0(n4406), .A1(Data_X[39]), .B0(n4405), .B1(intDX_EWSW[39]), .Y(n1844) );
AO22XLTS U2375 ( .A0(n4406), .A1(Data_X[33]), .B0(n4405), .B1(intDX_EWSW[33]), .Y(n1850) );
AO22XLTS U2376 ( .A0(n4404), .A1(Data_X[30]), .B0(n4405), .B1(intDX_EWSW[30]), .Y(n1853) );
AO22XLTS U2377 ( .A0(n4429), .A1(Data_Y[58]), .B0(n4427), .B1(intDY_EWSW[58]), .Y(n1760) );
AO22XLTS U2378 ( .A0(n4429), .A1(Data_Y[60]), .B0(n4427), .B1(intDY_EWSW[60]), .Y(n1758) );
AO22XLTS U2379 ( .A0(n4406), .A1(Data_X[34]), .B0(n4405), .B1(intDX_EWSW[34]), .Y(n1849) );
AO22XLTS U2380 ( .A0(n4409), .A1(Data_X[42]), .B0(n4408), .B1(intDX_EWSW[42]), .Y(n1841) );
AO22XLTS U2381 ( .A0(n4406), .A1(Data_X[32]), .B0(n4405), .B1(intDX_EWSW[32]), .Y(n1851) );
AO22XLTS U2382 ( .A0(n4406), .A1(Data_X[40]), .B0(n4408), .B1(intDX_EWSW[40]), .Y(n1843) );
AO22XLTS U2383 ( .A0(n4409), .A1(Data_X[44]), .B0(n4408), .B1(intDX_EWSW[44]), .Y(n1839) );
AO22XLTS U2384 ( .A0(n4409), .A1(Data_X[47]), .B0(n4408), .B1(intDX_EWSW[47]), .Y(n1836) );
AO22XLTS U2385 ( .A0(n4406), .A1(Data_X[38]), .B0(n4405), .B1(intDX_EWSW[38]), .Y(n1845) );
AO22XLTS U2386 ( .A0(n4407), .A1(Data_X[41]), .B0(n4408), .B1(intDX_EWSW[41]), .Y(n1842) );
AO22XLTS U2387 ( .A0(n4428), .A1(intDY_EWSW[1]), .B0(n4410), .B1(Data_Y[1]),
.Y(n1817) );
AO22XLTS U2388 ( .A0(n4413), .A1(intDY_EWSW[15]), .B0(n4416), .B1(Data_Y[15]), .Y(n1803) );
AO22XLTS U2389 ( .A0(n4423), .A1(intDY_EWSW[46]), .B0(n4425), .B1(Data_Y[46]), .Y(n1772) );
AO22XLTS U2390 ( .A0(n4413), .A1(intDX_EWSW[61]), .B0(n4422), .B1(Data_X[61]), .Y(n1822) );
AO22XLTS U2391 ( .A0(n4423), .A1(intDY_EWSW[45]), .B0(n4425), .B1(Data_Y[45]), .Y(n1773) );
AO22XLTS U2392 ( .A0(n4426), .A1(intDY_EWSW[44]), .B0(n4422), .B1(Data_Y[44]), .Y(n1774) );
AO22XLTS U2393 ( .A0(n4411), .A1(intDX_EWSW[59]), .B0(n4425), .B1(Data_X[59]), .Y(n1824) );
AO22XLTS U2394 ( .A0(n4413), .A1(intDY_EWSW[14]), .B0(n4416), .B1(Data_Y[14]), .Y(n1804) );
AO22XLTS U2395 ( .A0(n4426), .A1(intDY_EWSW[51]), .B0(n4424), .B1(Data_Y[51]), .Y(n1767) );
AO22XLTS U2396 ( .A0(n4423), .A1(intDY_EWSW[47]), .B0(n4422), .B1(Data_Y[47]), .Y(n1771) );
AO22XLTS U2397 ( .A0(n4411), .A1(intDX_EWSW[58]), .B0(n4422), .B1(Data_X[58]), .Y(n1825) );
AO22XLTS U2398 ( .A0(n4426), .A1(intDY_EWSW[50]), .B0(n4425), .B1(Data_Y[50]), .Y(n1768) );
AO22XLTS U2399 ( .A0(n4423), .A1(intDY_EWSW[42]), .B0(n4425), .B1(Data_Y[42]), .Y(n1776) );
AO22XLTS U2400 ( .A0(n4413), .A1(intDY_EWSW[17]), .B0(n4410), .B1(Data_Y[17]), .Y(n1801) );
AO22XLTS U2401 ( .A0(n4417), .A1(intDY_EWSW[25]), .B0(n4416), .B1(Data_Y[25]), .Y(n1793) );
AO22XLTS U2402 ( .A0(n4413), .A1(intDY_EWSW[13]), .B0(n4414), .B1(Data_Y[13]), .Y(n1805) );
AO22XLTS U2403 ( .A0(n4417), .A1(intDY_EWSW[23]), .B0(n4416), .B1(Data_Y[23]), .Y(n1795) );
AO22XLTS U2404 ( .A0(n4417), .A1(intDY_EWSW[29]), .B0(n4416), .B1(Data_Y[29]), .Y(n1789) );
AO22XLTS U2405 ( .A0(n4411), .A1(intDY_EWSW[11]), .B0(n4414), .B1(Data_Y[11]), .Y(n1807) );
AO22XLTS U2406 ( .A0(n4423), .A1(intDY_EWSW[49]), .B0(n4425), .B1(Data_Y[49]), .Y(n1769) );
AO22XLTS U2407 ( .A0(n4413), .A1(intDY_EWSW[12]), .B0(n4414), .B1(Data_Y[12]), .Y(n1806) );
AO22XLTS U2408 ( .A0(n4417), .A1(intDY_EWSW[18]), .B0(n4418), .B1(Data_Y[18]), .Y(n1800) );
AO22XLTS U2409 ( .A0(n4417), .A1(intDY_EWSW[20]), .B0(n4418), .B1(Data_Y[20]), .Y(n1798) );
AO22XLTS U2410 ( .A0(n4417), .A1(intDY_EWSW[22]), .B0(n4416), .B1(Data_Y[22]), .Y(n1796) );
AO22XLTS U2411 ( .A0(n4417), .A1(intDY_EWSW[24]), .B0(n4416), .B1(Data_Y[24]), .Y(n1794) );
AO22XLTS U2412 ( .A0(n4419), .A1(intDY_EWSW[26]), .B0(n4416), .B1(Data_Y[26]), .Y(n1792) );
AO22XLTS U2413 ( .A0(n4419), .A1(intDY_EWSW[28]), .B0(n4416), .B1(Data_Y[28]), .Y(n1790) );
AO22XLTS U2414 ( .A0(n4413), .A1(intDY_EWSW[16]), .B0(n4418), .B1(Data_Y[16]), .Y(n1802) );
XOR2XLTS U2415 ( .A(n4268), .B(n4267), .Y(n4270) );
CLKAND2X2TS U2416 ( .A(n4266), .B(n4265), .Y(n4268) );
AOI2BB2XLTS U2417 ( .B0(intDY_EWSW[3]), .B1(n1949), .A0N(intDX_EWSW[2]),
.A1N(n2242), .Y(n2243) );
NAND2BXLTS U2418 ( .AN(intDY_EWSW[2]), .B(intDX_EWSW[2]), .Y(n2241) );
NOR2X1TS U2419 ( .A(n3721), .B(n2380), .Y(n2125) );
NOR2BX1TS U2420 ( .AN(n2255), .B(n2254), .Y(n2256) );
OAI211XLTS U2421 ( .A0(intDY_EWSW[8]), .A1(n1950), .B0(n2261), .C0(n2264),
.Y(n2254) );
INVX2TS U2422 ( .A(n2266), .Y(n2255) );
OAI2BB2XLTS U2423 ( .B0(n2267), .B1(n2266), .A0N(n2265), .A1N(n2264), .Y(
n2270) );
OAI21XLTS U2424 ( .A0(intDY_EWSW[13]), .A1(n1954), .B0(intDY_EWSW[12]), .Y(
n2258) );
OAI21XLTS U2425 ( .A0(intDY_EWSW[15]), .A1(n1951), .B0(intDY_EWSW[14]), .Y(
n2268) );
OAI21XLTS U2426 ( .A0(intDY_EWSW[41]), .A1(n1955), .B0(intDY_EWSW[40]), .Y(
n2172) );
NOR2X1TS U2427 ( .A(n1974), .B(intDY_EWSW[45]), .Y(n2170) );
OAI21XLTS U2428 ( .A0(n4151), .A1(n4155), .B0(n4152), .Y(n2103) );
NOR2X1TS U2429 ( .A(n2374), .B(n2127), .Y(n2129) );
NAND2X1TS U2430 ( .A(n2379), .B(n2125), .Y(n2127) );
NOR2X1TS U2431 ( .A(n4037), .B(n2035), .Y(n2037) );
NAND2X1TS U2432 ( .A(n4035), .B(n2037), .Y(n2039) );
OAI221XLTS U2433 ( .A0(n4501), .A1(intDX_EWSW[29]), .B0(n4559), .B1(
intDX_EWSW[20]), .C0(n3507), .Y(n3512) );
OA22X1TS U2434 ( .A0(n1970), .A1(intDY_EWSW[22]), .B0(n1973), .B1(
intDY_EWSW[23]), .Y(n2291) );
OAI21XLTS U2435 ( .A0(intDY_EWSW[21]), .A1(n1966), .B0(intDY_EWSW[20]), .Y(
n2279) );
OAI2BB2XLTS U2436 ( .B0(intDX_EWSW[22]), .B1(n2287), .A0N(intDY_EWSW[23]),
.A1N(n1973), .Y(n2288) );
OAI21XLTS U2437 ( .A0(intDY_EWSW[23]), .A1(n1973), .B0(intDY_EWSW[22]), .Y(
n2287) );
OAI21XLTS U2438 ( .A0(intDY_EWSW[29]), .A1(n1991), .B0(intDY_EWSW[28]), .Y(
n2225) );
NOR2X1TS U2439 ( .A(n1952), .B(intDY_EWSW[25]), .Y(n2292) );
OAI2BB1X1TS U2440 ( .A0N(n2278), .A1N(n2277), .B0(n2276), .Y(n2298) );
NOR2BX1TS U2441 ( .AN(n2275), .B(n2285), .Y(n2276) );
AOI211XLTS U2442 ( .A0(n2272), .A1(n2271), .B0(n2270), .C0(n2269), .Y(n2277)
);
NAND2BX1TS U2443 ( .AN(n2257), .B(n2256), .Y(n2278) );
OA22X1TS U2444 ( .A0(n1965), .A1(intDY_EWSW[34]), .B0(n1967), .B1(
intDY_EWSW[35]), .Y(n2300) );
OAI21XLTS U2445 ( .A0(n2194), .A1(n2193), .B0(n2192), .Y(n2195) );
NAND3XLTS U2446 ( .A(n1968), .B(n2191), .C(intDY_EWSW[36]), .Y(n2186) );
NOR2X1TS U2447 ( .A(n3828), .B(n2067), .Y(n2069) );
OAI21XLTS U2448 ( .A0(n2005), .A1(n4138), .B0(n2004), .Y(n2006) );
OR2X1TS U2449 ( .A(n2474), .B(Raw_mant_NRM_SWR[9]), .Y(n2471) );
OAI21XLTS U2450 ( .A0(Raw_mant_NRM_SWR[36]), .A1(Raw_mant_NRM_SWR[35]), .B0(
n4519), .Y(n2493) );
NAND3XLTS U2451 ( .A(n2551), .B(Raw_mant_NRM_SWR[32]), .C(n4594), .Y(n2499)
);
NOR2XLTS U2452 ( .A(n2794), .B(n2522), .Y(n2525) );
OAI21XLTS U2453 ( .A0(Raw_mant_NRM_SWR[40]), .A1(n4592), .B0(n4519), .Y(
n2545) );
OAI21XLTS U2454 ( .A0(n2553), .A1(n4593), .B0(n2552), .Y(n2554) );
NAND4XLTS U2455 ( .A(n2754), .B(n2475), .C(n2474), .D(n2473), .Y(n2476) );
NOR2XLTS U2456 ( .A(Raw_mant_NRM_SWR[13]), .B(Raw_mant_NRM_SWR[10]), .Y(
n2473) );
NOR2XLTS U2457 ( .A(Raw_mant_NRM_SWR[14]), .B(Raw_mant_NRM_SWR[9]), .Y(n2475) );
OR2X1TS U2458 ( .A(n2529), .B(Raw_mant_NRM_SWR[35]), .Y(n2787) );
NOR2X1TS U2459 ( .A(n2579), .B(n2581), .Y(n2139) );
OAI21XLTS U2460 ( .A0(n2049), .A1(n3719), .B0(n2048), .Y(n2050) );
NOR2X1TS U2461 ( .A(n2428), .B(n2121), .Y(n2373) );
OAI21X1TS U2462 ( .A0(n2429), .A1(n2121), .B0(n2120), .Y(n2372) );
OAI21XLTS U2463 ( .A0(n2434), .A1(n4039), .B0(n2435), .Y(n2118) );
NAND2X1TS U2464 ( .A(n4002), .B(n2117), .Y(n2428) );
AOI21X1TS U2465 ( .A0(n4001), .A1(n2117), .B0(n2116), .Y(n2429) );
OAI21XLTS U2466 ( .A0(n4061), .A1(n4066), .B0(n4062), .Y(n2116) );
OAI21XLTS U2467 ( .A0(n2029), .A1(n3996), .B0(n2028), .Y(n2030) );
NAND2X1TS U2468 ( .A(n3995), .B(n2031), .Y(n3980) );
AOI21X2TS U2469 ( .A0(n2409), .A1(n2114), .B0(n2113), .Y(n2371) );
NAND2X1TS U2470 ( .A(n2412), .B(n2110), .Y(n2112) );
AOI21X2TS U2471 ( .A0(n2712), .A1(n2025), .B0(n2024), .Y(n2422) );
NOR2X1TS U2472 ( .A(n4075), .B(n2023), .Y(n2025) );
NAND2X1TS U2473 ( .A(n4076), .B(n2021), .Y(n2023) );
AOI211X1TS U2474 ( .A0(intDY_EWSW[46]), .A1(n2181), .B0(n2180), .C0(n2179),
.Y(n2224) );
NAND3X1TS U2475 ( .A(n2208), .B(n2218), .C(n2167), .Y(n2305) );
NAND4X1TS U2476 ( .A(n2185), .B(n2184), .C(n2183), .D(n2182), .Y(n2303) );
NAND3XLTS U2477 ( .A(n2546), .B(n4519), .C(n2505), .Y(n2514) );
MX2X1TS U2478 ( .A(DmP_mant_SHT1_SW[25]), .B(Raw_mant_NRM_SWR[27]), .S0(
n4369), .Y(n3175) );
CLKAND2X2TS U2479 ( .A(n2961), .B(n2960), .Y(n3012) );
NAND4BXLTS U2480 ( .AN(n2445), .B(n2358), .C(n4387), .D(n4386), .Y(n2359) );
NOR2XLTS U2481 ( .A(n2448), .B(n2447), .Y(n2358) );
NOR2BX1TS U2482 ( .AN(LZD_output_NRM2_EW[2]), .B(ADD_OVRFLW_NRM2), .Y(n2333)
);
INVX2TS U2483 ( .A(n4131), .Y(n4223) );
NOR2XLTS U2484 ( .A(n4233), .B(n1999), .Y(n2001) );
OAI21XLTS U2485 ( .A0(n1999), .A1(n4232), .B0(n1998), .Y(n2000) );
INVX2TS U2486 ( .A(n4112), .Y(n4199) );
INVX2TS U2487 ( .A(n4116), .Y(n4117) );
AOI2BB2XLTS U2488 ( .B0(n2788), .B1(Raw_mant_NRM_SWR[34]), .A0N(n2787),
.A1N(n4594), .Y(n2789) );
OR2X1TS U2489 ( .A(Raw_mant_NRM_SWR[24]), .B(Raw_mant_NRM_SWR[23]), .Y(n2487) );
NAND2X1TS U2490 ( .A(n2575), .B(n2139), .Y(n3848) );
OAI21X2TS U2491 ( .A0(n2811), .A1(n2137), .B0(n2136), .Y(n2576) );
OAI21XLTS U2492 ( .A0(n2819), .A1(n3833), .B0(n2820), .Y(n2134) );
NOR2X1TS U2493 ( .A(n2812), .B(n2137), .Y(n2575) );
AOI21X1TS U2494 ( .A0(n2824), .A1(n2075), .B0(n2074), .Y(n2585) );
OAI21XLTS U2495 ( .A0(n2073), .A1(n3877), .B0(n2072), .Y(n2074) );
NAND2X1TS U2496 ( .A(n2823), .B(n2075), .Y(n2586) );
INVX2TS U2497 ( .A(n2817), .Y(n3834) );
NOR2X1TS U2498 ( .A(n3797), .B(n2065), .Y(n3810) );
INVX2TS U2499 ( .A(n3790), .Y(n3906) );
NOR2X1TS U2500 ( .A(n3970), .B(n3964), .Y(n2379) );
AOI21X1TS U2501 ( .A0(n3934), .A1(n2377), .B0(n2376), .Y(n3971) );
INVX2TS U2502 ( .A(n3713), .Y(n3716) );
AOI21X1TS U2503 ( .A0(n4027), .A1(n2373), .B0(n2372), .Y(n4358) );
AOI21X1TS U2504 ( .A0(n4011), .A1(n2439), .B0(n2438), .Y(n3929) );
INVX2TS U2505 ( .A(n4012), .Y(n4026) );
NOR2X1TS U2506 ( .A(n4099), .B(n4094), .Y(n2412) );
AOI221X1TS U2507 ( .A0(n4603), .A1(intDX_EWSW[51]), .B0(intDX_EWSW[52]),
.B1(n4518), .C0(n3477), .Y(n3487) );
AOI221X1TS U2508 ( .A0(n4602), .A1(intDX_EWSW[46]), .B0(intDX_EWSW[47]),
.B1(n4528), .C0(n3492), .Y(n3495) );
NAND4XLTS U2509 ( .A(n3541), .B(n3540), .C(n3539), .D(n3538), .Y(n3542) );
OR2X1TS U2510 ( .A(n3429), .B(n4671), .Y(n3335) );
AND3X1TS U2511 ( .A(n3204), .B(n3203), .C(n3202), .Y(n3403) );
AND3X1TS U2512 ( .A(n3196), .B(n3195), .C(n3194), .Y(n3400) );
AND3X1TS U2513 ( .A(n3278), .B(n3277), .C(n3276), .Y(n3560) );
OR2X1TS U2514 ( .A(n3374), .B(n4575), .Y(n3284) );
INVX2TS U2515 ( .A(n4019), .Y(n4021) );
OR2X1TS U2516 ( .A(n3365), .B(n4628), .Y(n3307) );
OR2X1TS U2517 ( .A(n3374), .B(n4574), .Y(n3314) );
OR2X1TS U2518 ( .A(n3374), .B(n4626), .Y(n3281) );
OR2X1TS U2519 ( .A(n3618), .B(n1994), .Y(n3373) );
INVX2TS U2520 ( .A(n2717), .Y(n2719) );
INVX2TS U2521 ( .A(n2819), .Y(n2821) );
OR2X1TS U2522 ( .A(n3429), .B(n4523), .Y(n2700) );
OR2X1TS U2523 ( .A(n3429), .B(n4522), .Y(n3190) );
OR2X1TS U2524 ( .A(n3429), .B(n4483), .Y(n3193) );
OR2X1TS U2525 ( .A(n3365), .B(n4615), .Y(n3245) );
OR2X1TS U2526 ( .A(n3618), .B(n4591), .Y(n3242) );
OR2X1TS U2527 ( .A(n3618), .B(n4588), .Y(n3239) );
OR2X1TS U2528 ( .A(n3374), .B(n4667), .Y(n3269) );
OR2X1TS U2529 ( .A(n3618), .B(n4585), .Y(n3182) );
OR2X1TS U2530 ( .A(n3374), .B(n4577), .Y(n3272) );
OR2X1TS U2531 ( .A(n3374), .B(n4586), .Y(n3179) );
OR2X4TS U2532 ( .A(n4393), .B(n4392), .Y(n3680) );
OAI21XLTS U2533 ( .A0(n3673), .A1(n4325), .B0(n3686), .Y(n3674) );
OAI21XLTS U2534 ( .A0(n4329), .A1(n4310), .B0(n1931), .Y(n2395) );
OAI21XLTS U2535 ( .A0(n4329), .A1(n4320), .B0(n1931), .Y(n2846) );
OAI211XLTS U2536 ( .A0(n4320), .A1(n4333), .B0(n1931), .C0(n4319), .Y(n4321)
);
OAI211XLTS U2537 ( .A0(n4310), .A1(n4333), .B0(n1931), .C0(n4309), .Y(n4311)
);
BUFX3TS U2538 ( .A(n2397), .Y(n4385) );
OAI211XLTS U2539 ( .A0(n4330), .A1(n4333), .B0(n1931), .C0(n4303), .Y(n4304)
);
BUFX3TS U2540 ( .A(n2397), .Y(n4381) );
NAND3XLTS U2541 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n4511), .C(
n4567), .Y(n4394) );
INVX2TS U2542 ( .A(n4126), .Y(n4128) );
INVX2TS U2543 ( .A(n4038), .Y(n4040) );
OAI21XLTS U2544 ( .A0(n4052), .A1(n4037), .B0(n4036), .Y(n4042) );
INVX2TS U2545 ( .A(n4234), .Y(n4236) );
OAI21XLTS U2546 ( .A0(n4248), .A1(n4233), .B0(n4232), .Y(n4238) );
INVX2TS U2547 ( .A(n4206), .Y(n4208) );
OAI21XLTS U2548 ( .A0(n4240), .A1(n4234), .B0(n4235), .Y(n4212) );
OAI211XLTS U2549 ( .A0(n4314), .A1(n2393), .B0(n2325), .C0(n2324), .Y(n2329)
);
OAI21XLTS U2550 ( .A0(n4166), .A1(n4165), .B0(n4164), .Y(n4171) );
INVX2TS U2551 ( .A(n4192), .Y(n4194) );
OAI21XLTS U2552 ( .A0(n3687), .A1(n4325), .B0(n3686), .Y(n3688) );
OAI21XLTS U2553 ( .A0(n4140), .A1(n4139), .B0(n4138), .Y(n4143) );
INVX2TS U2554 ( .A(n4061), .Y(n4063) );
OAI21XLTS U2555 ( .A0(n4068), .A1(n4067), .B0(n4066), .Y(n4070) );
OAI21XLTS U2556 ( .A0(n4341), .A1(n3659), .B0(n3658), .Y(n3663) );
AND3X1TS U2557 ( .A(n2780), .B(n2779), .C(n2799), .Y(n2782) );
AOI31XLTS U2558 ( .A0(n2755), .A1(n2754), .A2(Raw_mant_NRM_SWR[10]), .B0(
n2753), .Y(n2766) );
INVX2TS U2559 ( .A(n2581), .Y(n2583) );
INVX2TS U2560 ( .A(n3881), .Y(n2580) );
INVX2TS U2561 ( .A(n3815), .Y(n3817) );
INVX2TS U2562 ( .A(n3819), .Y(n3820) );
INVX2TS U2563 ( .A(n2597), .Y(n2599) );
OAI21XLTS U2564 ( .A0(n3849), .A1(n2680), .B0(n2681), .Y(n2602) );
INVX2TS U2565 ( .A(n2680), .Y(n2682) );
OAI21XLTS U2566 ( .A0(n3781), .A1(n2679), .B0(n2678), .Y(n2684) );
OAI21XLTS U2567 ( .A0(n3727), .A1(n3721), .B0(n3722), .Y(n2383) );
INVX2TS U2568 ( .A(n2380), .Y(n2382) );
AOI21X1TS U2569 ( .A0(n3945), .A1(n2379), .B0(n2378), .Y(n3727) );
INVX2TS U2570 ( .A(n3721), .Y(n3723) );
OAI21XLTS U2571 ( .A0(n3968), .A1(n3720), .B0(n3719), .Y(n3725) );
INVX2TS U2572 ( .A(n3964), .Y(n3966) );
INVX2TS U2573 ( .A(n3970), .Y(n3941) );
OAI21XLTS U2574 ( .A0(n3960), .A1(n3954), .B0(n3955), .Y(n3923) );
INVX2TS U2575 ( .A(n3954), .Y(n3956) );
OAI21XLTS U2576 ( .A0(n4355), .A1(n3953), .B0(n3952), .Y(n3958) );
OAI21XLTS U2577 ( .A0(n3929), .A1(n3928), .B0(n3927), .Y(n3932) );
INVX2TS U2578 ( .A(n2434), .Y(n2436) );
INVX2TS U2579 ( .A(n4048), .Y(n4050) );
INVX2TS U2580 ( .A(n4054), .Y(n3986) );
OAI21XLTS U2581 ( .A0(n4033), .A1(n3985), .B0(n3984), .Y(n3988) );
INVX2TS U2582 ( .A(n4067), .Y(n3998) );
OAI21XLTS U2583 ( .A0(n4023), .A1(n3997), .B0(n3996), .Y(n4000) );
INVX2TS U2584 ( .A(n4084), .Y(n2417) );
INVX2TS U2585 ( .A(n4094), .Y(n4096) );
INVX2TS U2586 ( .A(n4183), .Y(n4100) );
INVX2TS U2587 ( .A(n4472), .Y(busy) );
AOI2BB2XLTS U2588 ( .B0(Data_array_SWR[1]), .B1(n3439), .A0N(n3158), .A1N(
n3157), .Y(n3159) );
AOI2BB2XLTS U2589 ( .B0(Data_array_SWR[2]), .B1(n3439), .A0N(n3158), .A1N(
n3156), .Y(n3154) );
MX2X1TS U2590 ( .A(DMP_exp_NRM_EW[0]), .B(DMP_SFG[52]), .S0(n4479), .Y(n1450) );
MX2X1TS U2591 ( .A(DmP_mant_SHT1_SW[24]), .B(DmP_EXP_EWSW[24]), .S0(n4474),
.Y(n1349) );
MX2X1TS U2592 ( .A(DMP_SHT2_EWSW[36]), .B(DMP_SHT1_EWSW[36]), .S0(n3704),
.Y(n1500) );
MX2X1TS U2593 ( .A(DMP_SHT2_EWSW[35]), .B(DMP_SHT1_EWSW[35]), .S0(n3701),
.Y(n1503) );
MX2X1TS U2594 ( .A(DMP_SHT2_EWSW[34]), .B(DMP_SHT1_EWSW[34]), .S0(n4441),
.Y(n1506) );
MX2X1TS U2595 ( .A(DMP_SHT2_EWSW[33]), .B(DMP_SHT1_EWSW[33]), .S0(n3701),
.Y(n1509) );
MX2X1TS U2596 ( .A(DMP_SHT2_EWSW[32]), .B(DMP_SHT1_EWSW[32]), .S0(n4441),
.Y(n1512) );
MX2X1TS U2597 ( .A(DMP_SHT2_EWSW[31]), .B(DMP_SHT1_EWSW[31]), .S0(n3701),
.Y(n1515) );
MX2X1TS U2598 ( .A(DMP_SHT2_EWSW[30]), .B(DMP_SHT1_EWSW[30]), .S0(n4441),
.Y(n1518) );
MX2X1TS U2599 ( .A(DMP_SHT2_EWSW[29]), .B(DMP_SHT1_EWSW[29]), .S0(n4441),
.Y(n1521) );
MX2X1TS U2600 ( .A(DMP_SHT2_EWSW[28]), .B(DMP_SHT1_EWSW[28]), .S0(n3701),
.Y(n1524) );
MX2X1TS U2601 ( .A(DMP_SHT2_EWSW[27]), .B(DMP_SHT1_EWSW[27]), .S0(n4441),
.Y(n1527) );
MX2X1TS U2602 ( .A(DMP_SHT2_EWSW[26]), .B(DMP_SHT1_EWSW[26]), .S0(n3701),
.Y(n1530) );
MX2X1TS U2603 ( .A(DMP_SHT2_EWSW[22]), .B(DMP_SHT1_EWSW[22]), .S0(n4441),
.Y(n1542) );
MX2X1TS U2604 ( .A(DMP_SHT2_EWSW[21]), .B(DMP_SHT1_EWSW[21]), .S0(n3701),
.Y(n1545) );
MX2X1TS U2605 ( .A(DMP_SHT2_EWSW[20]), .B(DMP_SHT1_EWSW[20]), .S0(n4441),
.Y(n1548) );
MX2X1TS U2606 ( .A(DMP_SHT2_EWSW[19]), .B(DMP_SHT1_EWSW[19]), .S0(n3701),
.Y(n1551) );
MX2X1TS U2607 ( .A(DMP_SHT2_EWSW[18]), .B(DMP_SHT1_EWSW[18]), .S0(n4441),
.Y(n1554) );
MX2X1TS U2608 ( .A(DMP_SHT2_EWSW[17]), .B(DMP_SHT1_EWSW[17]), .S0(n1911),
.Y(n1557) );
MX2X1TS U2609 ( .A(DMP_SHT2_EWSW[16]), .B(DMP_SHT1_EWSW[16]), .S0(n1911),
.Y(n1560) );
MX2X1TS U2610 ( .A(DMP_SHT2_EWSW[15]), .B(DMP_SHT1_EWSW[15]), .S0(n1911),
.Y(n1563) );
MX2X1TS U2611 ( .A(DMP_SHT2_EWSW[14]), .B(DMP_SHT1_EWSW[14]), .S0(n1912),
.Y(n1566) );
MX2X1TS U2612 ( .A(DMP_SHT2_EWSW[13]), .B(DMP_SHT1_EWSW[13]), .S0(n1912),
.Y(n1569) );
MX2X1TS U2613 ( .A(DMP_SHT2_EWSW[12]), .B(DMP_SHT1_EWSW[12]), .S0(n1912),
.Y(n1572) );
MX2X1TS U2614 ( .A(DMP_SHT2_EWSW[11]), .B(DMP_SHT1_EWSW[11]), .S0(n1912),
.Y(n1575) );
MX2X1TS U2615 ( .A(DMP_SHT2_EWSW[10]), .B(DMP_SHT1_EWSW[10]), .S0(n4441),
.Y(n1578) );
MX2X1TS U2616 ( .A(DMP_SHT2_EWSW[9]), .B(DMP_SHT1_EWSW[9]), .S0(n3701), .Y(
n1581) );
MX2X1TS U2617 ( .A(DMP_SHT2_EWSW[6]), .B(DMP_SHT1_EWSW[6]), .S0(n3704), .Y(
n1590) );
MX2X1TS U2618 ( .A(DMP_SHT2_EWSW[5]), .B(DMP_SHT1_EWSW[5]), .S0(n3704), .Y(
n1593) );
MX2X1TS U2619 ( .A(DMP_SHT2_EWSW[4]), .B(DMP_SHT1_EWSW[4]), .S0(n3704), .Y(
n1596) );
MX2X1TS U2620 ( .A(DMP_SHT2_EWSW[2]), .B(DMP_SHT1_EWSW[2]), .S0(n3704), .Y(
n1602) );
MX2X1TS U2621 ( .A(DMP_SHT2_EWSW[1]), .B(DMP_SHT1_EWSW[1]), .S0(n3704), .Y(
n1605) );
MX2X1TS U2622 ( .A(DMP_SHT2_EWSW[0]), .B(DMP_SHT1_EWSW[0]), .S0(n3704), .Y(
n1608) );
AO22XLTS U2623 ( .A0(n4426), .A1(intDY_EWSW[48]), .B0(n4425), .B1(Data_Y[48]), .Y(n1770) );
AO22XLTS U2624 ( .A0(n4407), .A1(Data_X[15]), .B0(n4402), .B1(intDX_EWSW[15]), .Y(n1868) );
AO22XLTS U2625 ( .A0(n4406), .A1(Data_X[3]), .B0(n4401), .B1(intDX_EWSW[3]),
.Y(n1880) );
MX2X1TS U2626 ( .A(DMP_SHT2_EWSW[3]), .B(DMP_SFG[3]), .S0(n1915), .Y(n1598)
);
OAI222X1TS U2627 ( .A0(n3666), .A1(n3628), .B0(n3668), .B1(n3627), .C0(n4650), .C1(n3637), .Y(n1145) );
OAI222X1TS U2628 ( .A0(n3670), .A1(n3636), .B0(n3668), .B1(n3635), .C0(n4636), .C1(n3637), .Y(n1148) );
OAI222X1TS U2629 ( .A0(n3643), .A1(n3634), .B0(n3645), .B1(n3633), .C0(n4652), .C1(n3637), .Y(n1149) );
OAI222X1TS U2630 ( .A0(n3643), .A1(n1936), .B0(n3645), .B1(n3632), .C0(n4653), .C1(n4286), .Y(n1153) );
AO22XLTS U2631 ( .A0(n4419), .A1(intDY_EWSW[37]), .B0(n4420), .B1(Data_Y[37]), .Y(n1781) );
AO22XLTS U2632 ( .A0(n4421), .A1(Data_X[1]), .B0(n4401), .B1(intDX_EWSW[1]),
.Y(n1882) );
AO22XLTS U2633 ( .A0(n4429), .A1(Data_Y[61]), .B0(n4428), .B1(intDY_EWSW[61]), .Y(n1757) );
AO22XLTS U2634 ( .A0(n4411), .A1(intDY_EWSW[2]), .B0(n4412), .B1(Data_Y[2]),
.Y(n1816) );
AO22XLTS U2635 ( .A0(n4428), .A1(intDY_EWSW[3]), .B0(n4414), .B1(Data_Y[3]),
.Y(n1815) );
AO22XLTS U2636 ( .A0(n4411), .A1(intDY_EWSW[0]), .B0(n4416), .B1(Data_Y[0]),
.Y(n1818) );
AO22XLTS U2637 ( .A0(n4426), .A1(intDY_EWSW[53]), .B0(n4424), .B1(Data_Y[53]), .Y(n1765) );
AO22XLTS U2638 ( .A0(n4429), .A1(Data_X[57]), .B0(n4427), .B1(intDX_EWSW[57]), .Y(n1826) );
AO22XLTS U2639 ( .A0(n4404), .A1(Data_X[26]), .B0(n4403), .B1(intDX_EWSW[26]), .Y(n1857) );
AO22XLTS U2640 ( .A0(n4407), .A1(Data_X[18]), .B0(n4402), .B1(intDX_EWSW[18]), .Y(n1865) );
AO22XLTS U2641 ( .A0(n4421), .A1(Data_X[8]), .B0(n4401), .B1(intDX_EWSW[8]),
.Y(n1875) );
AO22XLTS U2642 ( .A0(n4404), .A1(Data_X[25]), .B0(n4403), .B1(intDX_EWSW[25]), .Y(n1858) );
AO22XLTS U2643 ( .A0(n4407), .A1(Data_X[23]), .B0(n4403), .B1(intDX_EWSW[23]), .Y(n1860) );
AO22XLTS U2644 ( .A0(n4407), .A1(Data_X[17]), .B0(n4402), .B1(intDX_EWSW[17]), .Y(n1866) );
AO22XLTS U2645 ( .A0(n4428), .A1(intDY_EWSW[4]), .B0(n4412), .B1(Data_Y[4]),
.Y(n1814) );
OAI211X1TS U2646 ( .A0(n3600), .A1(n3599), .B0(n3598), .C0(n3597), .Y(n1724)
);
AO22XLTS U2647 ( .A0(n4407), .A1(Data_X[20]), .B0(n4403), .B1(intDX_EWSW[20]), .Y(n1863) );
AO22XLTS U2648 ( .A0(n4407), .A1(Data_X[21]), .B0(n4403), .B1(intDX_EWSW[21]), .Y(n1862) );
AO22XLTS U2649 ( .A0(n4404), .A1(Data_X[28]), .B0(n4403), .B1(intDX_EWSW[28]), .Y(n1855) );
AO22XLTS U2650 ( .A0(n4404), .A1(Data_X[12]), .B0(n4402), .B1(intDX_EWSW[12]), .Y(n1871) );
AO22XLTS U2651 ( .A0(n4421), .A1(Data_X[9]), .B0(n4401), .B1(intDX_EWSW[9]),
.Y(n1874) );
AO22XLTS U2652 ( .A0(n4415), .A1(Data_X[6]), .B0(n4401), .B1(intDX_EWSW[6]),
.Y(n1877) );
AO22XLTS U2653 ( .A0(n4410), .A1(Data_X[4]), .B0(n4401), .B1(intDX_EWSW[4]),
.Y(n1879) );
MX2X1TS U2654 ( .A(n4372), .B(LZD_output_NRM2_EW[1]), .S0(n4374), .Y(n1212)
);
MX2X1TS U2655 ( .A(n4256), .B(Shift_amount_SHT1_EWR[1]), .S0(n4435), .Y(
n1691) );
MX2X1TS U2656 ( .A(DmP_mant_SHT1_SW[22]), .B(DmP_EXP_EWSW[22]), .S0(n4474),
.Y(n1353) );
MX2X1TS U2657 ( .A(DmP_mant_SHT1_SW[23]), .B(DmP_EXP_EWSW[23]), .S0(n4474),
.Y(n1351) );
MX2X1TS U2658 ( .A(DmP_mant_SHT1_SW[50]), .B(DmP_EXP_EWSW[50]), .S0(n4474),
.Y(n1297) );
MX2X1TS U2659 ( .A(DmP_mant_SHT1_SW[51]), .B(DmP_EXP_EWSW[51]), .S0(n4474),
.Y(n1295) );
AO22XLTS U2660 ( .A0(n4429), .A1(Data_Y[63]), .B0(n4428), .B1(intDY_EWSW[63]), .Y(n1755) );
AO21XLTS U2661 ( .A0(n1995), .A1(n2572), .B0(n2571), .Y(n1698) );
MX2X1TS U2662 ( .A(n4260), .B(Shift_amount_SHT1_EWR[2]), .S0(n4435), .Y(
n1690) );
MX2X1TS U2663 ( .A(Shift_amount_SHT1_EWR[4]), .B(n3707), .S0(n1953), .Y(
n1688) );
MX2X1TS U2664 ( .A(DMP_SHT2_EWSW[3]), .B(DMP_SHT1_EWSW[3]), .S0(n3704), .Y(
n1599) );
MX2X1TS U2665 ( .A(DMP_SHT2_EWSW[7]), .B(DMP_SHT1_EWSW[7]), .S0(n3704), .Y(
n1587) );
MX2X1TS U2666 ( .A(DMP_SHT2_EWSW[8]), .B(DMP_SHT1_EWSW[8]), .S0(n1912), .Y(
n1584) );
MX2X1TS U2667 ( .A(DMP_SHT2_EWSW[23]), .B(DMP_SHT1_EWSW[23]), .S0(n1911),
.Y(n1539) );
MX2X1TS U2668 ( .A(DMP_SHT2_EWSW[24]), .B(DMP_SHT1_EWSW[24]), .S0(n1911),
.Y(n1536) );
MX2X1TS U2669 ( .A(DMP_SHT2_EWSW[25]), .B(DMP_SHT1_EWSW[25]), .S0(n1911),
.Y(n1533) );
MX2X1TS U2670 ( .A(DmP_mant_SHT1_SW[25]), .B(DmP_EXP_EWSW[25]), .S0(n4474),
.Y(n1347) );
MX2X1TS U2671 ( .A(Shift_amount_SHT1_EWR[3]), .B(n4264), .S0(n1953), .Y(
n1689) );
MX2X1TS U2672 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n4369),
.Y(n1444) );
MX2X1TS U2673 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n4480),
.Y(n1434) );
MX2X1TS U2674 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n4480),
.Y(n1424) );
MX2X1TS U2675 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n4369),
.Y(n1414) );
MX2X1TS U2676 ( .A(DMP_exp_NRM2_EW[9]), .B(DMP_exp_NRM_EW[9]), .S0(n4480),
.Y(n1404) );
MX2X1TS U2677 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n4480),
.Y(n1439) );
MX2X1TS U2678 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n4480),
.Y(n1419) );
MX2X1TS U2679 ( .A(DMP_exp_NRM2_EW[8]), .B(DMP_exp_NRM_EW[8]), .S0(n4468),
.Y(n1409) );
MX2X1TS U2680 ( .A(DMP_SHT2_EWSW[1]), .B(DMP_SFG[1]), .S0(n1915), .Y(n1604)
);
MX2X1TS U2681 ( .A(DMP_SHT2_EWSW[15]), .B(DMP_SFG[15]), .S0(n4449), .Y(n1562) );
MX2X1TS U2682 ( .A(DMP_exp_NRM2_EW[10]), .B(DMP_exp_NRM_EW[10]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1399) );
AO22XLTS U2683 ( .A0(n4399), .A1(n1911), .B0(n4398), .B1(
Shift_reg_FLAGS_7[3]), .Y(n1887) );
AO22XLTS U2684 ( .A0(n4368), .A1(n4367), .B0(ADD_OVRFLW_NRM), .B1(n4478),
.Y(n1277) );
OR2X1TS U2685 ( .A(n4366), .B(DmP_mant_SFG_SWR[54]), .Y(n4368) );
MX2X1TS U2686 ( .A(n4348), .B(DmP_mant_SFG_SWR[5]), .S0(n4349), .Y(n1151) );
OAI222X1TS U2687 ( .A0(n3666), .A1(n3644), .B0(n3640), .B1(n3642), .C0(n4651), .C1(n3637), .Y(n1147) );
MX2X1TS U2688 ( .A(OP_FLAG_SHT2), .B(OP_FLAG_SFG), .S0(n1915), .Y(n1278) );
AO22XLTS U2689 ( .A0(n4407), .A1(Data_X[14]), .B0(n4402), .B1(intDX_EWSW[14]), .Y(n1869) );
XOR2XLTS U2690 ( .A(n4023), .B(n4022), .Y(n4032) );
AO22XLTS U2691 ( .A0(n4426), .A1(intDY_EWSW[56]), .B0(n4424), .B1(Data_Y[56]), .Y(n1762) );
MX2X1TS U2692 ( .A(DMP_SHT2_EWSW[51]), .B(DMP_SFG[51]), .S0(n4449), .Y(n1454) );
AO22XLTS U2693 ( .A0(n4421), .A1(Data_X[11]), .B0(n4402), .B1(intDX_EWSW[11]), .Y(n1872) );
MX2X1TS U2694 ( .A(DMP_SHT2_EWSW[43]), .B(DMP_SFG[43]), .S0(n3699), .Y(n1478) );
MX2X1TS U2695 ( .A(DMP_SHT2_EWSW[45]), .B(DMP_SFG[45]), .S0(n3699), .Y(n1472) );
MX2X1TS U2696 ( .A(DMP_SHT2_EWSW[47]), .B(DMP_SFG[47]), .S0(n4476), .Y(n1466) );
MX2X1TS U2697 ( .A(DMP_SHT2_EWSW[49]), .B(DMP_SFG[49]), .S0(n3698), .Y(n1460) );
MX2X1TS U2698 ( .A(DMP_SHT2_EWSW[44]), .B(DMP_SFG[44]), .S0(n4476), .Y(n1475) );
MX2X1TS U2699 ( .A(DMP_SHT2_EWSW[46]), .B(DMP_SFG[46]), .S0(n4449), .Y(n1469) );
MX2X1TS U2700 ( .A(DMP_SHT2_EWSW[48]), .B(DMP_SFG[48]), .S0(n3702), .Y(n1463) );
MX2X1TS U2701 ( .A(DMP_SHT2_EWSW[50]), .B(DMP_SFG[50]), .S0(n3702), .Y(n1457) );
MX2X1TS U2702 ( .A(DMP_SHT2_EWSW[4]), .B(DMP_SFG[4]), .S0(n1915), .Y(n1595)
);
MX2X1TS U2703 ( .A(DMP_SHT2_EWSW[10]), .B(DMP_SFG[10]), .S0(n3699), .Y(n1577) );
MX2X1TS U2704 ( .A(DMP_SHT2_EWSW[12]), .B(DMP_SFG[12]), .S0(n3698), .Y(n1571) );
MX2X1TS U2705 ( .A(DMP_SHT2_EWSW[32]), .B(DMP_SFG[32]), .S0(n3702), .Y(n1511) );
MX2X1TS U2706 ( .A(DMP_SHT2_EWSW[34]), .B(DMP_SFG[34]), .S0(n3698), .Y(n1505) );
MX2X1TS U2707 ( .A(DMP_SHT2_EWSW[36]), .B(DMP_SFG[36]), .S0(n4476), .Y(n1499) );
MX2X1TS U2708 ( .A(DMP_SHT2_EWSW[38]), .B(DMP_SFG[38]), .S0(n3698), .Y(n1493) );
MX2X1TS U2709 ( .A(DMP_SHT2_EWSW[40]), .B(DMP_SFG[40]), .S0(n4476), .Y(n1487) );
MX2X1TS U2710 ( .A(DMP_SHT2_EWSW[0]), .B(DMP_SFG[0]), .S0(n1915), .Y(n1607)
);
OAI211X1TS U2711 ( .A0(n3556), .A1(n3599), .B0(n3172), .C0(n3171), .Y(n1725)
);
MX2X1TS U2712 ( .A(DMP_SHT2_EWSW[5]), .B(DMP_SFG[5]), .S0(n1914), .Y(n1592)
);
MX2X1TS U2713 ( .A(DMP_SHT2_EWSW[6]), .B(DMP_SFG[6]), .S0(n1914), .Y(n1589)
);
MX2X1TS U2714 ( .A(DMP_SHT2_EWSW[9]), .B(DMP_SFG[9]), .S0(n1914), .Y(n1580)
);
MX2X1TS U2715 ( .A(DMP_SHT2_EWSW[11]), .B(DMP_SFG[11]), .S0(n4476), .Y(n1574) );
MX2X1TS U2716 ( .A(DMP_SHT2_EWSW[13]), .B(DMP_SFG[13]), .S0(n3698), .Y(n1568) );
MX2X1TS U2717 ( .A(DMP_SHT2_EWSW[14]), .B(DMP_SFG[14]), .S0(n4449), .Y(n1565) );
MX2X1TS U2718 ( .A(DMP_SHT2_EWSW[17]), .B(DMP_SFG[17]), .S0(n4476), .Y(n1556) );
MX2X1TS U2719 ( .A(DMP_SHT2_EWSW[18]), .B(DMP_SFG[18]), .S0(n3699), .Y(n1553) );
MX2X1TS U2720 ( .A(DMP_SHT2_EWSW[19]), .B(DMP_SFG[19]), .S0(n3699), .Y(n1550) );
MX2X1TS U2721 ( .A(DMP_SHT2_EWSW[20]), .B(DMP_SFG[20]), .S0(n4449), .Y(n1547) );
MX2X1TS U2722 ( .A(DMP_SHT2_EWSW[21]), .B(DMP_SFG[21]), .S0(n3698), .Y(n1544) );
MX2X1TS U2723 ( .A(DMP_SHT2_EWSW[22]), .B(DMP_SFG[22]), .S0(n3702), .Y(n1541) );
MX2X1TS U2724 ( .A(DMP_SHT2_EWSW[26]), .B(DMP_SFG[26]), .S0(n3702), .Y(n1529) );
MX2X1TS U2725 ( .A(DMP_SHT2_EWSW[27]), .B(DMP_SFG[27]), .S0(n3699), .Y(n1526) );
MX2X1TS U2726 ( .A(DMP_SHT2_EWSW[28]), .B(DMP_SFG[28]), .S0(n1914), .Y(n1523) );
MX2X1TS U2727 ( .A(DMP_SHT2_EWSW[29]), .B(DMP_SFG[29]), .S0(n3702), .Y(n1520) );
MX2X1TS U2728 ( .A(DMP_SHT2_EWSW[30]), .B(DMP_SFG[30]), .S0(n3698), .Y(n1517) );
MX2X1TS U2729 ( .A(DMP_SHT2_EWSW[31]), .B(DMP_SFG[31]), .S0(n3699), .Y(n1514) );
MX2X1TS U2730 ( .A(DMP_SHT2_EWSW[33]), .B(DMP_SFG[33]), .S0(n4449), .Y(n1508) );
MX2X1TS U2731 ( .A(DMP_SHT2_EWSW[35]), .B(DMP_SFG[35]), .S0(n4449), .Y(n1502) );
MX2X1TS U2732 ( .A(DMP_SHT2_EWSW[37]), .B(DMP_SFG[37]), .S0(n4476), .Y(n1496) );
MX2X1TS U2733 ( .A(DMP_SHT2_EWSW[39]), .B(DMP_SFG[39]), .S0(n3699), .Y(n1490) );
MX2X1TS U2734 ( .A(DMP_SHT2_EWSW[41]), .B(DMP_SFG[41]), .S0(n3702), .Y(n1484) );
MX2X1TS U2735 ( .A(DMP_SHT2_EWSW[42]), .B(DMP_SFG[42]), .S0(n4476), .Y(n1481) );
MX2X1TS U2736 ( .A(DMP_SHT2_EWSW[16]), .B(DMP_SFG[16]), .S0(n3702), .Y(n1559) );
MX2X1TS U2737 ( .A(DMP_SHT2_EWSW[2]), .B(DMP_SFG[2]), .S0(n1915), .Y(n1601)
);
AO22XLTS U2738 ( .A0(n4429), .A1(Data_Y[62]), .B0(n4427), .B1(intDY_EWSW[62]), .Y(n1756) );
AO22XLTS U2739 ( .A0(n4418), .A1(Data_X[22]), .B0(n4403), .B1(intDX_EWSW[22]), .Y(n1861) );
AO22XLTS U2740 ( .A0(n4407), .A1(Data_X[19]), .B0(n4402), .B1(intDX_EWSW[19]), .Y(n1864) );
AO22XLTS U2741 ( .A0(n4404), .A1(Data_X[27]), .B0(n4403), .B1(intDX_EWSW[27]), .Y(n1856) );
AO22XLTS U2742 ( .A0(n4404), .A1(Data_X[29]), .B0(n4403), .B1(intDX_EWSW[29]), .Y(n1854) );
AO22XLTS U2743 ( .A0(n4404), .A1(Data_X[0]), .B0(n4427), .B1(intDX_EWSW[0]),
.Y(n1883) );
AO22XLTS U2744 ( .A0(n4421), .A1(Data_X[2]), .B0(n4401), .B1(intDX_EWSW[2]),
.Y(n1881) );
AO22XLTS U2745 ( .A0(n4421), .A1(Data_X[10]), .B0(n4402), .B1(intDX_EWSW[10]), .Y(n1873) );
AO22XLTS U2746 ( .A0(n4407), .A1(Data_X[16]), .B0(n4402), .B1(intDX_EWSW[16]), .Y(n1867) );
AO22XLTS U2747 ( .A0(n4409), .A1(Data_X[48]), .B0(n4408), .B1(intDX_EWSW[48]), .Y(n1835) );
AO22XLTS U2748 ( .A0(n4404), .A1(Data_X[24]), .B0(n4403), .B1(intDX_EWSW[24]), .Y(n1859) );
AO22XLTS U2749 ( .A0(n4429), .A1(Data_X[52]), .B0(n4427), .B1(intDX_EWSW[52]), .Y(n1831) );
AO22XLTS U2750 ( .A0(n4406), .A1(Data_X[37]), .B0(n4405), .B1(intDX_EWSW[37]), .Y(n1846) );
AO22XLTS U2751 ( .A0(n4421), .A1(Data_X[7]), .B0(n4401), .B1(intDX_EWSW[7]),
.Y(n1876) );
AO22XLTS U2752 ( .A0(n4415), .A1(Data_X[5]), .B0(n4401), .B1(intDX_EWSW[5]),
.Y(n1878) );
AO22XLTS U2753 ( .A0(n4411), .A1(intDX_EWSW[54]), .B0(n4414), .B1(Data_X[54]), .Y(n1829) );
AO22XLTS U2754 ( .A0(n4426), .A1(intDY_EWSW[52]), .B0(n4424), .B1(Data_Y[52]), .Y(n1766) );
AO22XLTS U2755 ( .A0(n4417), .A1(intDX_EWSW[49]), .B0(n4414), .B1(Data_X[49]), .Y(n1834) );
AO22XLTS U2756 ( .A0(n4419), .A1(intDY_EWSW[36]), .B0(n4420), .B1(Data_Y[36]), .Y(n1782) );
XOR2XLTS U2757 ( .A(n2822), .B(n2827), .Y(n2831) );
MX2X1TS U2758 ( .A(DMP_SHT2_EWSW[7]), .B(DMP_SFG[7]), .S0(n1914), .Y(n1586)
);
MX2X1TS U2759 ( .A(DMP_SHT2_EWSW[25]), .B(DMP_SFG[25]), .S0(n3698), .Y(n1532) );
MX2X1TS U2760 ( .A(DMP_SHT2_EWSW[23]), .B(DMP_SFG[23]), .S0(n3699), .Y(n1538) );
MX2X1TS U2761 ( .A(DMP_SHT2_EWSW[24]), .B(DMP_SFG[24]), .S0(n4449), .Y(n1535) );
AO22XLTS U2762 ( .A0(n4404), .A1(Data_X[13]), .B0(n4402), .B1(intDX_EWSW[13]), .Y(n1870) );
MX2X1TS U2763 ( .A(DMP_SHT2_EWSW[8]), .B(DMP_SFG[8]), .S0(n1914), .Y(n1583)
);
AO22XLTS U2764 ( .A0(n4413), .A1(intDX_EWSW[55]), .B0(n4414), .B1(Data_X[55]), .Y(n1828) );
AO22XLTS U2765 ( .A0(n4419), .A1(intDY_EWSW[39]), .B0(n4424), .B1(Data_Y[39]), .Y(n1779) );
MX2X1TS U2766 ( .A(n4384), .B(DmP_mant_SFG_SWR[38]), .S0(n3705), .Y(n1118)
);
MX2X1TS U2767 ( .A(n4288), .B(DmP_mant_SFG_SWR[36]), .S0(n4342), .Y(n1120)
);
MX2X1TS U2768 ( .A(n4289), .B(DmP_mant_SFG_SWR[34]), .S0(n3705), .Y(n1122)
);
MX2X1TS U2769 ( .A(n4295), .B(DmP_mant_SFG_SWR[32]), .S0(n4342), .Y(n1124)
);
MX2X1TS U2770 ( .A(n4379), .B(DmP_mant_SFG_SWR[22]), .S0(n4342), .Y(n1134)
);
MX2X1TS U2771 ( .A(n4376), .B(DmP_mant_SFG_SWR[20]), .S0(n4342), .Y(n1136)
);
MX2X1TS U2772 ( .A(n4327), .B(DmP_mant_SFG_SWR[18]), .S0(n4342), .Y(n1138)
);
MX2X1TS U2773 ( .A(n4375), .B(DmP_mant_SFG_SWR[16]), .S0(n4342), .Y(n1140)
);
MX2X1TS U2774 ( .A(n4287), .B(DmP_mant_SFG_SWR[37]), .S0(n4342), .Y(n1119)
);
MX2X1TS U2775 ( .A(n4382), .B(DmP_mant_SFG_SWR[33]), .S0(n4342), .Y(n1123)
);
MX2X1TS U2776 ( .A(n4378), .B(DmP_mant_SFG_SWR[21]), .S0(n4342), .Y(n1135)
);
MX2X1TS U2777 ( .A(n4328), .B(DmP_mant_SFG_SWR[17]), .S0(n4349), .Y(n1139)
);
AO22XLTS U2778 ( .A0(n4413), .A1(intDX_EWSW[53]), .B0(n4425), .B1(Data_X[53]), .Y(n1830) );
AO22XLTS U2779 ( .A0(n4411), .A1(intDX_EWSW[62]), .B0(n4422), .B1(Data_X[62]), .Y(n1821) );
AO22XLTS U2780 ( .A0(n4411), .A1(intDX_EWSW[60]), .B0(n4421), .B1(Data_X[60]), .Y(n1823) );
AO22XLTS U2781 ( .A0(n4423), .A1(intDY_EWSW[38]), .B0(n4420), .B1(Data_Y[38]), .Y(n1780) );
AO22XLTS U2782 ( .A0(n4423), .A1(intDY_EWSW[32]), .B0(n4420), .B1(Data_Y[32]), .Y(n1786) );
AO22XLTS U2783 ( .A0(n4423), .A1(intDY_EWSW[40]), .B0(n4420), .B1(Data_Y[40]), .Y(n1778) );
OAI222X1TS U2784 ( .A0(n3640), .A1(n3644), .B0(n3666), .B1(n3642), .C0(n4641), .C1(n3641), .Y(n1111) );
MX2X1TS U2785 ( .A(n4392), .B(underflow_flag), .S0(n4391), .Y(n1288) );
NOR2XLTS U2786 ( .A(n4392), .B(SIGN_FLAG_SHT1SHT2), .Y(n3671) );
AO22XLTS U2787 ( .A0(n4390), .A1(n4276), .B0(final_result_ieee[48]), .B1(
n4469), .Y(n1162) );
AO22XLTS U2788 ( .A0(n4390), .A1(n4350), .B0(final_result_ieee[2]), .B1(
n4469), .Y(n1163) );
AO22XLTS U2789 ( .A0(n4390), .A1(n4277), .B0(final_result_ieee[47]), .B1(
n4469), .Y(n1164) );
AO22XLTS U2790 ( .A0(n4381), .A1(n4348), .B0(final_result_ieee[3]), .B1(
n4469), .Y(n1165) );
AO22XLTS U2791 ( .A0(n4390), .A1(n4278), .B0(final_result_ieee[46]), .B1(
n4469), .Y(n1166) );
AO22XLTS U2792 ( .A0(n4381), .A1(n4347), .B0(final_result_ieee[4]), .B1(
n4469), .Y(n1167) );
AO22XLTS U2793 ( .A0(n4390), .A1(n4279), .B0(final_result_ieee[40]), .B1(
n4383), .Y(n1178) );
AO22XLTS U2794 ( .A0(n4385), .A1(n4280), .B0(final_result_ieee[39]), .B1(
n4469), .Y(n1180) );
AO22XLTS U2795 ( .A0(n4385), .A1(n4281), .B0(final_result_ieee[38]), .B1(
n4383), .Y(n1182) );
AO22XLTS U2796 ( .A0(n4385), .A1(n4282), .B0(final_result_ieee[37]), .B1(
n4383), .Y(n1184) );
AO22XLTS U2797 ( .A0(n4385), .A1(n4384), .B0(final_result_ieee[36]), .B1(
n4383), .Y(n1186) );
AO22XLTS U2798 ( .A0(n4381), .A1(n4375), .B0(final_result_ieee[14]), .B1(
n4377), .Y(n1187) );
AO22XLTS U2799 ( .A0(n4385), .A1(n4289), .B0(final_result_ieee[32]), .B1(
n4377), .Y(n1194) );
AO22XLTS U2800 ( .A0(n4381), .A1(n4376), .B0(final_result_ieee[18]), .B1(
n4377), .Y(n1195) );
AO22XLTS U2801 ( .A0(n4385), .A1(n4382), .B0(final_result_ieee[31]), .B1(
n4383), .Y(n1196) );
AO22XLTS U2802 ( .A0(n4381), .A1(n4378), .B0(final_result_ieee[19]), .B1(
n4377), .Y(n1197) );
AO22XLTS U2803 ( .A0(n4385), .A1(n4295), .B0(final_result_ieee[30]), .B1(
n4377), .Y(n1198) );
AO22XLTS U2804 ( .A0(n4381), .A1(n4379), .B0(final_result_ieee[20]), .B1(
n4383), .Y(n1199) );
AO22XLTS U2805 ( .A0(n4381), .A1(n4380), .B0(final_result_ieee[25]), .B1(
n4383), .Y(n1208) );
AOI2BB2XLTS U2806 ( .B0(n4390), .B1(n4389), .A0N(n1942), .A1N(
final_result_ieee[59]), .Y(n1679) );
AOI2BB2XLTS U2807 ( .B0(n4390), .B1(n4388), .A0N(n1942), .A1N(
final_result_ieee[58]), .Y(n1680) );
AOI2BB2XLTS U2808 ( .B0(n4390), .B1(n4387), .A0N(n1942), .A1N(
final_result_ieee[55]), .Y(n1683) );
AOI2BB2XLTS U2809 ( .B0(n4390), .B1(n4386), .A0N(n4675), .A1N(
final_result_ieee[54]), .Y(n1684) );
AO22XLTS U2810 ( .A0(n1942), .A1(ZERO_FLAG_SHT1SHT2), .B0(n4469), .B1(
zero_flag), .Y(n1281) );
AO22XLTS U2811 ( .A0(n4426), .A1(intDY_EWSW[55]), .B0(n4424), .B1(Data_Y[55]), .Y(n1763) );
AO22XLTS U2812 ( .A0(n4426), .A1(intDY_EWSW[54]), .B0(n4425), .B1(Data_Y[54]), .Y(n1764) );
AO22XLTS U2813 ( .A0(n4411), .A1(intDX_EWSW[56]), .B0(n4412), .B1(Data_X[56]), .Y(n1827) );
AO22XLTS U2814 ( .A0(n4428), .A1(intDY_EWSW[9]), .B0(n4410), .B1(Data_Y[9]),
.Y(n1809) );
AO22XLTS U2815 ( .A0(n4413), .A1(intDY_EWSW[19]), .B0(n4424), .B1(Data_Y[19]), .Y(n1799) );
AO22XLTS U2816 ( .A0(n4417), .A1(intDY_EWSW[27]), .B0(n4410), .B1(Data_Y[27]), .Y(n1791) );
AO22XLTS U2817 ( .A0(n4417), .A1(intDY_EWSW[21]), .B0(n4420), .B1(Data_Y[21]), .Y(n1797) );
AO22XLTS U2818 ( .A0(n4419), .A1(intDY_EWSW[31]), .B0(n4420), .B1(Data_Y[31]), .Y(n1787) );
AO22XLTS U2819 ( .A0(n4426), .A1(intDY_EWSW[57]), .B0(n4425), .B1(Data_Y[57]), .Y(n1761) );
XOR2XLTS U2820 ( .A(n4186), .B(n4185), .Y(n4191) );
AO22XLTS U2821 ( .A0(n4411), .A1(intDY_EWSW[10]), .B0(n4410), .B1(Data_Y[10]), .Y(n1808) );
AO22XLTS U2822 ( .A0(n4428), .A1(intDY_EWSW[7]), .B0(n4421), .B1(Data_Y[7]),
.Y(n1811) );
AO22XLTS U2823 ( .A0(n4428), .A1(intDY_EWSW[5]), .B0(n4415), .B1(Data_Y[5]),
.Y(n1813) );
AO22XLTS U2824 ( .A0(n4419), .A1(intDY_EWSW[33]), .B0(n4420), .B1(Data_Y[33]), .Y(n1785) );
AO22XLTS U2825 ( .A0(n4419), .A1(intDY_EWSW[35]), .B0(n4420), .B1(Data_Y[35]), .Y(n1783) );
AO22XLTS U2826 ( .A0(n4423), .A1(intDY_EWSW[41]), .B0(n4424), .B1(Data_Y[41]), .Y(n1777) );
AO22XLTS U2827 ( .A0(n4423), .A1(intDY_EWSW[43]), .B0(n4424), .B1(Data_Y[43]), .Y(n1775) );
MX2X1TS U2828 ( .A(n4281), .B(DmP_mant_SFG_SWR[40]), .S0(n3705), .Y(n1116)
);
MX2X1TS U2829 ( .A(n4347), .B(DmP_mant_SFG_SWR[6]), .S0(n4349), .Y(n1150) );
MX2X1TS U2830 ( .A(n4350), .B(DmP_mant_SFG_SWR[4]), .S0(n4349), .Y(n1152) );
MX2X1TS U2831 ( .A(n4282), .B(DmP_mant_SFG_SWR[39]), .S0(n3705), .Y(n1117)
);
MX2X1TS U2832 ( .A(n4380), .B(DmP_mant_SFG_SWR[27]), .S0(n4342), .Y(n1129)
);
AO22XLTS U2833 ( .A0(n4428), .A1(intDY_EWSW[8]), .B0(n4412), .B1(Data_Y[8]),
.Y(n1810) );
AO22XLTS U2834 ( .A0(n4419), .A1(intDY_EWSW[30]), .B0(n4424), .B1(Data_Y[30]), .Y(n1788) );
AOI2BB2XLTS U2835 ( .B0(beg_OP), .B1(n4511), .A0N(n4511), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n2573) );
XOR2XLTS U2836 ( .A(n4225), .B(n4224), .Y(n4230) );
MX2X1TS U2837 ( .A(n4279), .B(DmP_mant_SFG_SWR[42]), .S0(n3705), .Y(n1114)
);
MX2X1TS U2838 ( .A(n4280), .B(DmP_mant_SFG_SWR[41]), .S0(n3705), .Y(n1115)
);
XOR2XLTS U2839 ( .A(n4114), .B(n4113), .Y(n4122) );
XOR2XLTS U2840 ( .A(n4140), .B(n4129), .Y(n4137) );
XOR2XLTS U2841 ( .A(n4248), .B(n4247), .Y(n4252) );
AO22XLTS U2842 ( .A0(n4428), .A1(intDY_EWSW[6]), .B0(n4410), .B1(Data_Y[6]),
.Y(n1812) );
AO22XLTS U2843 ( .A0(n4419), .A1(intDY_EWSW[34]), .B0(n4420), .B1(Data_Y[34]), .Y(n1784) );
OAI21XLTS U2844 ( .A0(n1899), .A1(n4612), .B0(n3618), .Y(n1754) );
MX2X1TS U2845 ( .A(n4277), .B(DmP_mant_SFG_SWR[49]), .S0(n1914), .Y(n1107)
);
MX2X1TS U2846 ( .A(n4278), .B(DmP_mant_SFG_SWR[48]), .S0(n3705), .Y(n1108)
);
MX2X1TS U2847 ( .A(n4276), .B(DmP_mant_SFG_SWR[50]), .S0(n1915), .Y(n1106)
);
XOR2XLTS U2848 ( .A(n4166), .B(n4154), .Y(n4163) );
XOR2XLTS U2849 ( .A(n4196), .B(n4195), .Y(n4205) );
OAI222X1TS U2850 ( .A0(n3643), .A1(n3639), .B0(n3640), .B1(n3638), .C0(n4635), .C1(n3637), .Y(n1146) );
OAI222X1TS U2851 ( .A0(n3645), .A1(n3639), .B0(n3670), .B1(n3638), .C0(n4642), .C1(n3641), .Y(n1112) );
OAI222X1TS U2852 ( .A0(n3640), .A1(n3628), .B0(n3643), .B1(n3627), .C0(n4643), .C1(n3641), .Y(n1113) );
OAI222X1TS U2853 ( .A0(n3670), .A1(n3647), .B0(n3645), .B1(n3646), .C0(n4656), .C1(n4286), .Y(n1154) );
OAI222X1TS U2854 ( .A0(n3668), .A1(n3647), .B0(n3643), .B1(n3646), .C0(n4657), .C1(n1913), .Y(n1104) );
MX2X1TS U2855 ( .A(n4370), .B(LZD_output_NRM2_EW[5]), .S0(n3382), .Y(n1209)
);
MX2X1TS U2856 ( .A(n4371), .B(LZD_output_NRM2_EW[3]), .S0(n4374), .Y(n1213)
);
AOI22X1TS U2857 ( .A0(n2146), .A1(n4367), .B0(Raw_mant_NRM_SWR[54]), .B1(
n3747), .Y(n2147) );
XOR2XLTS U2858 ( .A(n3734), .B(n3733), .Y(n3739) );
XOR2XLTS U2859 ( .A(n3773), .B(n3772), .Y(n3778) );
XOR2XLTS U2860 ( .A(n3754), .B(n3753), .Y(n3759) );
XOR2XLTS U2861 ( .A(n3869), .B(n3868), .Y(n3875) );
XOR2XLTS U2862 ( .A(n3846), .B(n3845), .Y(n3854) );
XOR2XLTS U2863 ( .A(n2584), .B(n2587), .Y(n2592) );
XOR2XLTS U2864 ( .A(n3884), .B(n3883), .Y(n3889) );
XOR2XLTS U2865 ( .A(n3836), .B(n3835), .Y(n3841) );
XOR2XLTS U2866 ( .A(n3804), .B(n3803), .Y(n3809) );
XOR2XLTS U2867 ( .A(n3814), .B(n3785), .Y(n3796) );
XOR2XLTS U2868 ( .A(n3908), .B(n3907), .Y(n3914) );
XOR2XLTS U2869 ( .A(n3968), .B(n3967), .Y(n3977) );
XOR2XLTS U2870 ( .A(n4355), .B(n4354), .Y(n4364) );
XOR2XLTS U2871 ( .A(n4052), .B(n4051), .Y(n4060) );
XOR2XLTS U2872 ( .A(n4014), .B(n4013), .Y(n4018) );
XOR2XLTS U2873 ( .A(n2421), .B(n2423), .Y(n2427) );
XOR2XLTS U2874 ( .A(n4087), .B(n4086), .Y(n4093) );
AO22XLTS U2875 ( .A0(n4480), .A1(SIGN_FLAG_NRM), .B0(n4627), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n1271) );
AO22XLTS U2876 ( .A0(n1926), .A1(SIGN_FLAG_SFG), .B0(n4478), .B1(
SIGN_FLAG_NRM), .Y(n1272) );
AO22XLTS U2877 ( .A0(n4477), .A1(SIGN_FLAG_SHT2), .B0(n3700), .B1(
SIGN_FLAG_SFG), .Y(n1273) );
AO22XLTS U2878 ( .A0(busy), .A1(SIGN_FLAG_SHT1), .B0(n4475), .B1(
SIGN_FLAG_SHT2), .Y(n1274) );
AO22XLTS U2879 ( .A0(n4474), .A1(SIGN_FLAG_EXP), .B0(n4473), .B1(
SIGN_FLAG_SHT1), .Y(n1275) );
AO22XLTS U2880 ( .A0(busy), .A1(OP_FLAG_SHT1), .B0(n4472), .B1(OP_FLAG_SHT2),
.Y(n1279) );
AO22XLTS U2881 ( .A0(n4471), .A1(OP_FLAG_EXP), .B0(n4470), .B1(OP_FLAG_SHT1),
.Y(n1280) );
AO22XLTS U2882 ( .A0(n4468), .A1(ZERO_FLAG_NRM), .B0(n4627), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n1282) );
AO22XLTS U2883 ( .A0(n1926), .A1(ZERO_FLAG_SFG), .B0(n4478), .B1(
ZERO_FLAG_NRM), .Y(n1283) );
AO22XLTS U2884 ( .A0(n4477), .A1(ZERO_FLAG_SHT2), .B0(n3700), .B1(
ZERO_FLAG_SFG), .Y(n1284) );
AO22XLTS U2885 ( .A0(busy), .A1(ZERO_FLAG_SHT1), .B0(n4475), .B1(
ZERO_FLAG_SHT2), .Y(n1285) );
AO22XLTS U2886 ( .A0(n4471), .A1(ZERO_FLAG_EXP), .B0(n4470), .B1(
ZERO_FLAG_SHT1), .Y(n1286) );
AO22XLTS U2887 ( .A0(n4471), .A1(DmP_EXP_EWSW[49]), .B0(n4470), .B1(
DmP_mant_SHT1_SW[49]), .Y(n1299) );
OAI21XLTS U2888 ( .A0(n4517), .A1(n3092), .B0(n2891), .Y(n1300) );
AO22XLTS U2889 ( .A0(n4471), .A1(DmP_EXP_EWSW[48]), .B0(n4470), .B1(
DmP_mant_SHT1_SW[48]), .Y(n1301) );
AO22XLTS U2890 ( .A0(n4471), .A1(DmP_EXP_EWSW[47]), .B0(n4470), .B1(
DmP_mant_SHT1_SW[47]), .Y(n1303) );
OAI21XLTS U2891 ( .A0(n4528), .A1(n3092), .B0(n2317), .Y(n1304) );
AO22XLTS U2892 ( .A0(n4471), .A1(DmP_EXP_EWSW[46]), .B0(n4470), .B1(
DmP_mant_SHT1_SW[46]), .Y(n1305) );
AO22XLTS U2893 ( .A0(n4471), .A1(DmP_EXP_EWSW[45]), .B0(n4470), .B1(
DmP_mant_SHT1_SW[45]), .Y(n1307) );
AO22XLTS U2894 ( .A0(n4471), .A1(DmP_EXP_EWSW[44]), .B0(n4470), .B1(
DmP_mant_SHT1_SW[44]), .Y(n1309) );
AO22XLTS U2895 ( .A0(n4471), .A1(DmP_EXP_EWSW[43]), .B0(n4470), .B1(
DmP_mant_SHT1_SW[43]), .Y(n1311) );
AO22XLTS U2896 ( .A0(n4471), .A1(DmP_EXP_EWSW[42]), .B0(n4470), .B1(
DmP_mant_SHT1_SW[42]), .Y(n1313) );
AO22XLTS U2897 ( .A0(n4463), .A1(DmP_EXP_EWSW[41]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[41]), .Y(n1315) );
OAI21XLTS U2898 ( .A0(n4514), .A1(n3092), .B0(n3082), .Y(n1316) );
AO22XLTS U2899 ( .A0(n4463), .A1(DmP_EXP_EWSW[40]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[40]), .Y(n1317) );
AO22XLTS U2900 ( .A0(n4463), .A1(DmP_EXP_EWSW[39]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[39]), .Y(n1319) );
AO22XLTS U2901 ( .A0(n4463), .A1(DmP_EXP_EWSW[38]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[38]), .Y(n1321) );
AO22XLTS U2902 ( .A0(n4463), .A1(DmP_EXP_EWSW[37]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[37]), .Y(n1323) );
AO22XLTS U2903 ( .A0(n4463), .A1(DmP_EXP_EWSW[36]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[36]), .Y(n1325) );
OAI21XLTS U2904 ( .A0(n4598), .A1(n3089), .B0(n2920), .Y(n1326) );
AO22XLTS U2905 ( .A0(n4463), .A1(DmP_EXP_EWSW[35]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[35]), .Y(n1327) );
OAI21XLTS U2906 ( .A0(n4513), .A1(n3089), .B0(n2923), .Y(n1328) );
AO22XLTS U2907 ( .A0(n4463), .A1(DmP_EXP_EWSW[34]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[34]), .Y(n1329) );
OAI21XLTS U2908 ( .A0(n4597), .A1(n3089), .B0(n3076), .Y(n1330) );
AO22XLTS U2909 ( .A0(n4463), .A1(DmP_EXP_EWSW[33]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[33]), .Y(n1331) );
OAI21XLTS U2910 ( .A0(n4512), .A1(n3089), .B0(n2922), .Y(n1332) );
AO22XLTS U2911 ( .A0(n4463), .A1(DmP_EXP_EWSW[32]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[32]), .Y(n1333) );
OAI21XLTS U2912 ( .A0(n4565), .A1(n3089), .B0(n3074), .Y(n1334) );
AO22XLTS U2913 ( .A0(n4461), .A1(DmP_EXP_EWSW[31]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[31]), .Y(n1335) );
AO22XLTS U2914 ( .A0(n4461), .A1(DmP_EXP_EWSW[30]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[30]), .Y(n1337) );
AO22XLTS U2915 ( .A0(n4461), .A1(DmP_EXP_EWSW[29]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[29]), .Y(n1339) );
AO22XLTS U2916 ( .A0(n4461), .A1(DmP_EXP_EWSW[28]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[28]), .Y(n1341) );
AO22XLTS U2917 ( .A0(n4461), .A1(DmP_EXP_EWSW[27]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[27]), .Y(n1343) );
AO22XLTS U2918 ( .A0(n4461), .A1(DmP_EXP_EWSW[26]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[26]), .Y(n1345) );
AO22XLTS U2919 ( .A0(n4461), .A1(DmP_EXP_EWSW[21]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[21]), .Y(n1355) );
AO22XLTS U2920 ( .A0(n4461), .A1(DmP_EXP_EWSW[20]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[20]), .Y(n1357) );
AO22XLTS U2921 ( .A0(n4461), .A1(DmP_EXP_EWSW[19]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1359) );
AO22XLTS U2922 ( .A0(n4461), .A1(DmP_EXP_EWSW[18]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[18]), .Y(n1361) );
AO22XLTS U2923 ( .A0(n4457), .A1(DmP_EXP_EWSW[17]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[17]), .Y(n1363) );
AO22XLTS U2924 ( .A0(n4457), .A1(DmP_EXP_EWSW[16]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[16]), .Y(n1365) );
AO22XLTS U2925 ( .A0(n4457), .A1(DmP_EXP_EWSW[15]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[15]), .Y(n1367) );
AO22XLTS U2926 ( .A0(n4457), .A1(DmP_EXP_EWSW[14]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[14]), .Y(n1369) );
AO22XLTS U2927 ( .A0(n4457), .A1(DmP_EXP_EWSW[13]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1371) );
AO22XLTS U2928 ( .A0(n4457), .A1(DmP_EXP_EWSW[12]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[12]), .Y(n1373) );
AO22XLTS U2929 ( .A0(n4457), .A1(DmP_EXP_EWSW[11]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[11]), .Y(n1375) );
AO22XLTS U2930 ( .A0(n4457), .A1(DmP_EXP_EWSW[10]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[10]), .Y(n1377) );
AO22XLTS U2931 ( .A0(n4457), .A1(DmP_EXP_EWSW[9]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[9]), .Y(n1379) );
AO22XLTS U2932 ( .A0(n4457), .A1(DmP_EXP_EWSW[8]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[8]), .Y(n1381) );
AO22XLTS U2933 ( .A0(n4455), .A1(DmP_EXP_EWSW[7]), .B0(n4454), .B1(
DmP_mant_SHT1_SW[7]), .Y(n1383) );
AO22XLTS U2934 ( .A0(n4455), .A1(DmP_EXP_EWSW[6]), .B0(n4454), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1385) );
AO22XLTS U2935 ( .A0(n4455), .A1(DmP_EXP_EWSW[5]), .B0(n4454), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1387) );
AO22XLTS U2936 ( .A0(n4455), .A1(DmP_EXP_EWSW[4]), .B0(n4454), .B1(
DmP_mant_SHT1_SW[4]), .Y(n1389) );
AO22XLTS U2937 ( .A0(n4455), .A1(DmP_EXP_EWSW[3]), .B0(n4454), .B1(
DmP_mant_SHT1_SW[3]), .Y(n1391) );
AO22XLTS U2938 ( .A0(n4455), .A1(DmP_EXP_EWSW[2]), .B0(n4454), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1393) );
AO22XLTS U2939 ( .A0(n4455), .A1(DmP_EXP_EWSW[1]), .B0(n4454), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1395) );
AO22XLTS U2940 ( .A0(n4455), .A1(DmP_EXP_EWSW[0]), .B0(n4454), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1397) );
AO22XLTS U2941 ( .A0(n1926), .A1(DMP_SFG[62]), .B0(n4478), .B1(
DMP_exp_NRM_EW[10]), .Y(n1400) );
AO22XLTS U2942 ( .A0(n4477), .A1(DMP_SHT2_EWSW[62]), .B0(n3700), .B1(
DMP_SFG[62]), .Y(n1401) );
AO22XLTS U2943 ( .A0(n4453), .A1(DMP_SHT1_EWSW[62]), .B0(n4475), .B1(
DMP_SHT2_EWSW[62]), .Y(n1402) );
AO22XLTS U2944 ( .A0(n4455), .A1(DMP_EXP_EWSW[62]), .B0(n4454), .B1(
DMP_SHT1_EWSW[62]), .Y(n1403) );
AO22XLTS U2945 ( .A0(n4479), .A1(DMP_SFG[61]), .B0(n3695), .B1(
DMP_exp_NRM_EW[9]), .Y(n1405) );
AO22XLTS U2946 ( .A0(n1913), .A1(DMP_SHT2_EWSW[61]), .B0(n3700), .B1(
DMP_SFG[61]), .Y(n1406) );
AO22XLTS U2947 ( .A0(busy), .A1(DMP_SHT1_EWSW[61]), .B0(n4475), .B1(
DMP_SHT2_EWSW[61]), .Y(n1407) );
AO22XLTS U2948 ( .A0(n4455), .A1(DMP_EXP_EWSW[61]), .B0(n4454), .B1(
DMP_SHT1_EWSW[61]), .Y(n1408) );
AO22XLTS U2949 ( .A0(n4479), .A1(DMP_SFG[60]), .B0(n3695), .B1(
DMP_exp_NRM_EW[8]), .Y(n1410) );
AO22XLTS U2950 ( .A0(n4477), .A1(DMP_SHT2_EWSW[60]), .B0(n4449), .B1(
DMP_SFG[60]), .Y(n1411) );
AO22XLTS U2951 ( .A0(n1912), .A1(DMP_SHT1_EWSW[60]), .B0(n4475), .B1(
DMP_SHT2_EWSW[60]), .Y(n1412) );
AO22XLTS U2952 ( .A0(n4451), .A1(DMP_EXP_EWSW[60]), .B0(n4450), .B1(
DMP_SHT1_EWSW[60]), .Y(n1413) );
AO22XLTS U2953 ( .A0(n4479), .A1(DMP_SFG[59]), .B0(n1925), .B1(
DMP_exp_NRM_EW[7]), .Y(n1415) );
AO22XLTS U2954 ( .A0(n1913), .A1(DMP_SHT2_EWSW[59]), .B0(n3700), .B1(
DMP_SFG[59]), .Y(n1416) );
AO22XLTS U2955 ( .A0(n1911), .A1(DMP_SHT1_EWSW[59]), .B0(n4674), .B1(
DMP_SHT2_EWSW[59]), .Y(n1417) );
AO22XLTS U2956 ( .A0(n4451), .A1(DMP_EXP_EWSW[59]), .B0(n4450), .B1(
DMP_SHT1_EWSW[59]), .Y(n1418) );
AO22XLTS U2957 ( .A0(n4479), .A1(DMP_SFG[58]), .B0(n1925), .B1(
DMP_exp_NRM_EW[6]), .Y(n1420) );
AO22XLTS U2958 ( .A0(n1913), .A1(DMP_SHT2_EWSW[58]), .B0(n3700), .B1(
DMP_SFG[58]), .Y(n1421) );
AO22XLTS U2959 ( .A0(n4453), .A1(DMP_SHT1_EWSW[58]), .B0(n4472), .B1(
DMP_SHT2_EWSW[58]), .Y(n1422) );
AO22XLTS U2960 ( .A0(n4451), .A1(DMP_EXP_EWSW[58]), .B0(n4450), .B1(
DMP_SHT1_EWSW[58]), .Y(n1423) );
AO22XLTS U2961 ( .A0(n4479), .A1(DMP_SFG[57]), .B0(n4448), .B1(
DMP_exp_NRM_EW[5]), .Y(n1425) );
AO22XLTS U2962 ( .A0(n4452), .A1(DMP_SHT2_EWSW[57]), .B0(n3702), .B1(
DMP_SFG[57]), .Y(n1426) );
AO22XLTS U2963 ( .A0(n4453), .A1(DMP_SHT1_EWSW[57]), .B0(n4472), .B1(
DMP_SHT2_EWSW[57]), .Y(n1427) );
AO22XLTS U2964 ( .A0(n4451), .A1(DMP_EXP_EWSW[57]), .B0(n4450), .B1(
DMP_SHT1_EWSW[57]), .Y(n1428) );
AO22XLTS U2965 ( .A0(n1926), .A1(DMP_SFG[56]), .B0(n4448), .B1(
DMP_exp_NRM_EW[4]), .Y(n1430) );
AO22XLTS U2966 ( .A0(n1913), .A1(DMP_SHT2_EWSW[56]), .B0(n3700), .B1(
DMP_SFG[56]), .Y(n1431) );
AO22XLTS U2967 ( .A0(n4453), .A1(DMP_SHT1_EWSW[56]), .B0(n4472), .B1(
DMP_SHT2_EWSW[56]), .Y(n1432) );
AO22XLTS U2968 ( .A0(n4451), .A1(DMP_EXP_EWSW[56]), .B0(n4450), .B1(
DMP_SHT1_EWSW[56]), .Y(n1433) );
AO22XLTS U2969 ( .A0(n4479), .A1(DMP_SFG[55]), .B0(n4448), .B1(
DMP_exp_NRM_EW[3]), .Y(n1435) );
AO22XLTS U2970 ( .A0(n1913), .A1(DMP_SHT2_EWSW[55]), .B0(n3700), .B1(
DMP_SFG[55]), .Y(n1436) );
AO22XLTS U2971 ( .A0(n4453), .A1(DMP_SHT1_EWSW[55]), .B0(n4472), .B1(
DMP_SHT2_EWSW[55]), .Y(n1437) );
AO22XLTS U2972 ( .A0(n4451), .A1(DMP_EXP_EWSW[55]), .B0(n4450), .B1(
DMP_SHT1_EWSW[55]), .Y(n1438) );
AO22XLTS U2973 ( .A0(n1926), .A1(DMP_SFG[54]), .B0(n1901), .B1(
DMP_exp_NRM_EW[2]), .Y(n1440) );
AO22XLTS U2974 ( .A0(n4477), .A1(DMP_SHT2_EWSW[54]), .B0(n3698), .B1(
DMP_SFG[54]), .Y(n1441) );
AO22XLTS U2975 ( .A0(n4453), .A1(DMP_SHT1_EWSW[54]), .B0(n4472), .B1(
DMP_SHT2_EWSW[54]), .Y(n1442) );
AO22XLTS U2976 ( .A0(n4451), .A1(DMP_EXP_EWSW[54]), .B0(n4450), .B1(
DMP_SHT1_EWSW[54]), .Y(n1443) );
AO22XLTS U2977 ( .A0(n4479), .A1(DMP_SFG[53]), .B0(n1901), .B1(
DMP_exp_NRM_EW[1]), .Y(n1445) );
AO22XLTS U2978 ( .A0(n4452), .A1(DMP_SHT2_EWSW[53]), .B0(n3700), .B1(
DMP_SFG[53]), .Y(n1446) );
AO22XLTS U2979 ( .A0(n4453), .A1(DMP_SHT1_EWSW[53]), .B0(n4447), .B1(
DMP_SHT2_EWSW[53]), .Y(n1447) );
AO22XLTS U2980 ( .A0(n4451), .A1(DMP_EXP_EWSW[53]), .B0(n4450), .B1(
DMP_SHT1_EWSW[53]), .Y(n1448) );
MX2X1TS U2981 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n4369),
.Y(n1449) );
AO22XLTS U2982 ( .A0(n4452), .A1(DMP_SHT2_EWSW[52]), .B0(n3700), .B1(
DMP_SFG[52]), .Y(n1451) );
AO22XLTS U2983 ( .A0(n4453), .A1(DMP_SHT1_EWSW[52]), .B0(n4447), .B1(
DMP_SHT2_EWSW[52]), .Y(n1452) );
AO22XLTS U2984 ( .A0(n4451), .A1(DMP_EXP_EWSW[52]), .B0(n4450), .B1(
DMP_SHT1_EWSW[52]), .Y(n1453) );
AO22XLTS U2985 ( .A0(n4453), .A1(DMP_SHT1_EWSW[51]), .B0(n4447), .B1(
DMP_SHT2_EWSW[51]), .Y(n1455) );
AO22XLTS U2986 ( .A0(n4451), .A1(DMP_EXP_EWSW[51]), .B0(n4446), .B1(
DMP_SHT1_EWSW[51]), .Y(n1456) );
AO22XLTS U2987 ( .A0(n1912), .A1(DMP_SHT1_EWSW[50]), .B0(n4447), .B1(
DMP_SHT2_EWSW[50]), .Y(n1458) );
AO22XLTS U2988 ( .A0(n4445), .A1(DMP_EXP_EWSW[50]), .B0(n4446), .B1(
DMP_SHT1_EWSW[50]), .Y(n1459) );
AO22XLTS U2989 ( .A0(n4453), .A1(DMP_SHT1_EWSW[49]), .B0(n4472), .B1(
DMP_SHT2_EWSW[49]), .Y(n1461) );
AO22XLTS U2990 ( .A0(n4445), .A1(DMP_EXP_EWSW[49]), .B0(n4446), .B1(
DMP_SHT1_EWSW[49]), .Y(n1462) );
AO22XLTS U2991 ( .A0(busy), .A1(DMP_SHT1_EWSW[48]), .B0(n4444), .B1(
DMP_SHT2_EWSW[48]), .Y(n1464) );
AO22XLTS U2992 ( .A0(n4445), .A1(DMP_EXP_EWSW[48]), .B0(n4446), .B1(
DMP_SHT1_EWSW[48]), .Y(n1465) );
AO22XLTS U2993 ( .A0(busy), .A1(DMP_SHT1_EWSW[47]), .B0(n4444), .B1(
DMP_SHT2_EWSW[47]), .Y(n1467) );
AO22XLTS U2994 ( .A0(n4445), .A1(DMP_EXP_EWSW[47]), .B0(n4446), .B1(
DMP_SHT1_EWSW[47]), .Y(n1468) );
AO22XLTS U2995 ( .A0(busy), .A1(DMP_SHT1_EWSW[46]), .B0(n4444), .B1(
DMP_SHT2_EWSW[46]), .Y(n1470) );
AO22XLTS U2996 ( .A0(n4445), .A1(DMP_EXP_EWSW[46]), .B0(n4446), .B1(
DMP_SHT1_EWSW[46]), .Y(n1471) );
AO22XLTS U2997 ( .A0(n1912), .A1(DMP_SHT1_EWSW[45]), .B0(n4444), .B1(
DMP_SHT2_EWSW[45]), .Y(n1473) );
AO22XLTS U2998 ( .A0(n4445), .A1(DMP_EXP_EWSW[45]), .B0(n4446), .B1(
DMP_SHT1_EWSW[45]), .Y(n1474) );
AO22XLTS U2999 ( .A0(busy), .A1(DMP_SHT1_EWSW[44]), .B0(n4444), .B1(
DMP_SHT2_EWSW[44]), .Y(n1476) );
AO22XLTS U3000 ( .A0(n4445), .A1(DMP_EXP_EWSW[44]), .B0(n4446), .B1(
DMP_SHT1_EWSW[44]), .Y(n1477) );
AO22XLTS U3001 ( .A0(busy), .A1(DMP_SHT1_EWSW[43]), .B0(n4444), .B1(
DMP_SHT2_EWSW[43]), .Y(n1479) );
AO22XLTS U3002 ( .A0(n4445), .A1(DMP_EXP_EWSW[43]), .B0(n4446), .B1(
DMP_SHT1_EWSW[43]), .Y(n1480) );
AO22XLTS U3003 ( .A0(n1910), .A1(DMP_SHT1_EWSW[42]), .B0(n4444), .B1(
DMP_SHT2_EWSW[42]), .Y(n1482) );
AO22XLTS U3004 ( .A0(n4445), .A1(DMP_EXP_EWSW[42]), .B0(n4446), .B1(
DMP_SHT1_EWSW[42]), .Y(n1483) );
AO22XLTS U3005 ( .A0(n1910), .A1(DMP_SHT1_EWSW[41]), .B0(n4444), .B1(
DMP_SHT2_EWSW[41]), .Y(n1485) );
AO22XLTS U3006 ( .A0(n4445), .A1(DMP_EXP_EWSW[41]), .B0(n4443), .B1(
DMP_SHT1_EWSW[41]), .Y(n1486) );
AO22XLTS U3007 ( .A0(n1910), .A1(DMP_SHT1_EWSW[40]), .B0(n4444), .B1(
DMP_SHT2_EWSW[40]), .Y(n1488) );
AO22XLTS U3008 ( .A0(n4442), .A1(DMP_EXP_EWSW[40]), .B0(n4443), .B1(
DMP_SHT1_EWSW[40]), .Y(n1489) );
AO22XLTS U3009 ( .A0(n1910), .A1(DMP_SHT1_EWSW[39]), .B0(n4444), .B1(
DMP_SHT2_EWSW[39]), .Y(n1491) );
AO22XLTS U3010 ( .A0(n4442), .A1(DMP_EXP_EWSW[39]), .B0(n4443), .B1(
DMP_SHT1_EWSW[39]), .Y(n1492) );
AO22XLTS U3011 ( .A0(n4441), .A1(DMP_SHT1_EWSW[38]), .B0(n4447), .B1(
DMP_SHT2_EWSW[38]), .Y(n1494) );
AO22XLTS U3012 ( .A0(n4442), .A1(DMP_EXP_EWSW[38]), .B0(n4443), .B1(
DMP_SHT1_EWSW[38]), .Y(n1495) );
AO22XLTS U3013 ( .A0(n3701), .A1(DMP_SHT1_EWSW[37]), .B0(n4447), .B1(
DMP_SHT2_EWSW[37]), .Y(n1497) );
AO22XLTS U3014 ( .A0(n4442), .A1(DMP_EXP_EWSW[37]), .B0(n4443), .B1(
DMP_SHT1_EWSW[37]), .Y(n1498) );
AO22XLTS U3015 ( .A0(n4442), .A1(DMP_EXP_EWSW[36]), .B0(n4443), .B1(
DMP_SHT1_EWSW[36]), .Y(n1501) );
AO22XLTS U3016 ( .A0(n4442), .A1(DMP_EXP_EWSW[35]), .B0(n4443), .B1(
DMP_SHT1_EWSW[35]), .Y(n1504) );
AO22XLTS U3017 ( .A0(n4442), .A1(DMP_EXP_EWSW[34]), .B0(n4443), .B1(
DMP_SHT1_EWSW[34]), .Y(n1507) );
AO22XLTS U3018 ( .A0(n4442), .A1(DMP_EXP_EWSW[33]), .B0(n4443), .B1(
DMP_SHT1_EWSW[33]), .Y(n1510) );
AO22XLTS U3019 ( .A0(n4442), .A1(DMP_EXP_EWSW[32]), .B0(n4443), .B1(
DMP_SHT1_EWSW[32]), .Y(n1513) );
AO22XLTS U3020 ( .A0(n4442), .A1(DMP_EXP_EWSW[31]), .B0(n4450), .B1(
DMP_SHT1_EWSW[31]), .Y(n1516) );
AO22XLTS U3021 ( .A0(n4440), .A1(DMP_EXP_EWSW[30]), .B0(n4439), .B1(
DMP_SHT1_EWSW[30]), .Y(n1519) );
AO22XLTS U3022 ( .A0(n4440), .A1(DMP_EXP_EWSW[29]), .B0(n4439), .B1(
DMP_SHT1_EWSW[29]), .Y(n1522) );
AO22XLTS U3023 ( .A0(n4440), .A1(DMP_EXP_EWSW[28]), .B0(n4439), .B1(
DMP_SHT1_EWSW[28]), .Y(n1525) );
AO22XLTS U3024 ( .A0(n4440), .A1(DMP_EXP_EWSW[27]), .B0(n4439), .B1(
DMP_SHT1_EWSW[27]), .Y(n1528) );
AO22XLTS U3025 ( .A0(n4440), .A1(DMP_EXP_EWSW[26]), .B0(n4439), .B1(
DMP_SHT1_EWSW[26]), .Y(n1531) );
AO22XLTS U3026 ( .A0(n4440), .A1(DMP_EXP_EWSW[25]), .B0(n4439), .B1(
DMP_SHT1_EWSW[25]), .Y(n1534) );
AO22XLTS U3027 ( .A0(n4440), .A1(DMP_EXP_EWSW[24]), .B0(n4439), .B1(
DMP_SHT1_EWSW[24]), .Y(n1537) );
AO22XLTS U3028 ( .A0(n4440), .A1(DMP_EXP_EWSW[23]), .B0(n4439), .B1(
DMP_SHT1_EWSW[23]), .Y(n1540) );
AO22XLTS U3029 ( .A0(n4440), .A1(DMP_EXP_EWSW[22]), .B0(n4439), .B1(
DMP_SHT1_EWSW[22]), .Y(n1543) );
AO22XLTS U3030 ( .A0(n4440), .A1(DMP_EXP_EWSW[21]), .B0(n4439), .B1(
DMP_SHT1_EWSW[21]), .Y(n1546) );
AO22XLTS U3031 ( .A0(n4438), .A1(DMP_EXP_EWSW[20]), .B0(n4437), .B1(
DMP_SHT1_EWSW[20]), .Y(n1549) );
AO22XLTS U3032 ( .A0(n4438), .A1(DMP_EXP_EWSW[19]), .B0(n4437), .B1(
DMP_SHT1_EWSW[19]), .Y(n1552) );
AO22XLTS U3033 ( .A0(n4438), .A1(DMP_EXP_EWSW[18]), .B0(n4437), .B1(
DMP_SHT1_EWSW[18]), .Y(n1555) );
AO22XLTS U3034 ( .A0(n4438), .A1(DMP_EXP_EWSW[17]), .B0(n4437), .B1(
DMP_SHT1_EWSW[17]), .Y(n1558) );
AO22XLTS U3035 ( .A0(n4438), .A1(DMP_EXP_EWSW[16]), .B0(n4437), .B1(
DMP_SHT1_EWSW[16]), .Y(n1561) );
AO22XLTS U3036 ( .A0(n4438), .A1(DMP_EXP_EWSW[15]), .B0(n4437), .B1(
DMP_SHT1_EWSW[15]), .Y(n1564) );
AO22XLTS U3037 ( .A0(n4438), .A1(DMP_EXP_EWSW[14]), .B0(n4437), .B1(
DMP_SHT1_EWSW[14]), .Y(n1567) );
AO22XLTS U3038 ( .A0(n4438), .A1(DMP_EXP_EWSW[13]), .B0(n4437), .B1(
DMP_SHT1_EWSW[13]), .Y(n1570) );
AO22XLTS U3039 ( .A0(n4438), .A1(DMP_EXP_EWSW[12]), .B0(n4437), .B1(
DMP_SHT1_EWSW[12]), .Y(n1573) );
AO22XLTS U3040 ( .A0(n4438), .A1(DMP_EXP_EWSW[11]), .B0(n4437), .B1(
DMP_SHT1_EWSW[11]), .Y(n1576) );
AO22XLTS U3041 ( .A0(n4436), .A1(DMP_EXP_EWSW[10]), .B0(n4435), .B1(
DMP_SHT1_EWSW[10]), .Y(n1579) );
AO22XLTS U3042 ( .A0(n4436), .A1(DMP_EXP_EWSW[9]), .B0(n4435), .B1(
DMP_SHT1_EWSW[9]), .Y(n1582) );
AO22XLTS U3043 ( .A0(n4436), .A1(DMP_EXP_EWSW[8]), .B0(n4435), .B1(
DMP_SHT1_EWSW[8]), .Y(n1585) );
AO22XLTS U3044 ( .A0(n4436), .A1(DMP_EXP_EWSW[7]), .B0(n4435), .B1(
DMP_SHT1_EWSW[7]), .Y(n1588) );
AO22XLTS U3045 ( .A0(n4436), .A1(DMP_EXP_EWSW[6]), .B0(n4435), .B1(
DMP_SHT1_EWSW[6]), .Y(n1591) );
AO22XLTS U3046 ( .A0(n4436), .A1(DMP_EXP_EWSW[5]), .B0(n4435), .B1(
DMP_SHT1_EWSW[5]), .Y(n1594) );
AO22XLTS U3047 ( .A0(n4436), .A1(DMP_EXP_EWSW[4]), .B0(n4435), .B1(
DMP_SHT1_EWSW[4]), .Y(n1597) );
AO22XLTS U3048 ( .A0(n4436), .A1(DMP_EXP_EWSW[3]), .B0(n4458), .B1(
DMP_SHT1_EWSW[3]), .Y(n1600) );
AO22XLTS U3049 ( .A0(n4436), .A1(DMP_EXP_EWSW[2]), .B0(n4459), .B1(
DMP_SHT1_EWSW[2]), .Y(n1603) );
AO22XLTS U3050 ( .A0(n4436), .A1(DMP_EXP_EWSW[1]), .B0(n4459), .B1(
DMP_SHT1_EWSW[1]), .Y(n1606) );
AO22XLTS U3051 ( .A0(n4474), .A1(DMP_EXP_EWSW[0]), .B0(n4464), .B1(
DMP_SHT1_EWSW[0]), .Y(n1609) );
OAI21XLTS U3052 ( .A0(n3550), .A1(n4432), .B0(n3546), .Y(n3548) );
AO22XLTS U3053 ( .A0(n4434), .A1(n4433), .B0(ZERO_FLAG_EXP), .B1(n4432), .Y(
n1611) );
AO21XLTS U3054 ( .A0(OP_FLAG_EXP), .A1(n4432), .B0(n4433), .Y(n1612) );
OAI21XLTS U3055 ( .A0(n4565), .A1(n2314), .B0(n3100), .Y(n1643) );
OAI21XLTS U3056 ( .A0(n4502), .A1(n2314), .B0(n2932), .Y(n1644) );
OAI21XLTS U3057 ( .A0(n4564), .A1(n2914), .B0(n3094), .Y(n1645) );
OAI21XLTS U3058 ( .A0(n4501), .A1(n2930), .B0(n3102), .Y(n1646) );
OAI21XLTS U3059 ( .A0(n4563), .A1(n2314), .B0(n3095), .Y(n1647) );
OAI21XLTS U3060 ( .A0(n4495), .A1(n2314), .B0(n3107), .Y(n1648) );
OAI21XLTS U3061 ( .A0(n4562), .A1(n2314), .B0(n2933), .Y(n1649) );
OAI21XLTS U3062 ( .A0(n4494), .A1(n2314), .B0(n2936), .Y(n1650) );
OAI21XLTS U3063 ( .A0(n4561), .A1(n2314), .B0(n3098), .Y(n1651) );
OAI21XLTS U3064 ( .A0(n4507), .A1(n2314), .B0(n3111), .Y(n1665) );
OAI21XLTS U3065 ( .A0(n4595), .A1(n2930), .B0(n2848), .Y(n1674) );
MX2X1TS U3066 ( .A(Shift_amount_SHT1_EWR[5]), .B(n3712), .S0(n1953), .Y(
n1687) );
OAI21XLTS U3067 ( .A0(n1899), .A1(n3689), .B0(n3201), .Y(n1753) );
MX2X1TS U3068 ( .A(Shift_reg_FLAGS_7[2]), .B(Shift_reg_FLAGS_7[3]), .S0(
n4399), .Y(n1886) );
AO22XLTS U3069 ( .A0(n4398), .A1(Shift_reg_FLAGS_7_6), .B0(n4399), .B1(n4400), .Y(n1890) );
OR2X4TS U3070 ( .A(n3704), .B(n4468), .Y(n1899) );
INVX2TS U3071 ( .A(n4286), .Y(n3705) );
INVX2TS U3072 ( .A(n1928), .Y(n3689) );
INVX2TS U3073 ( .A(n3008), .Y(n3657) );
OR2X4TS U3074 ( .A(n2311), .B(n4432), .Y(n2314) );
NAND2X1TS U3075 ( .A(n4298), .B(n3652), .Y(n1905) );
NAND2X1TS U3076 ( .A(n4298), .B(n2982), .Y(n1906) );
BUFX3TS U3077 ( .A(n2931), .Y(n3144) );
AND2X4TS U3078 ( .A(n2311), .B(Shift_reg_FLAGS_7_6), .Y(n2892) );
BUFX3TS U3079 ( .A(n2892), .Y(n2896) );
OA21XLTS U3080 ( .A0(n1928), .A1(shift_value_SHT2_EWR[4]), .B0(n1916), .Y(
n1907) );
CLKBUFX3TS U3081 ( .A(n2708), .Y(n2704) );
MXI2X2TS U3082 ( .A(n3596), .B(n3175), .S0(n3174), .Y(n3556) );
MXI2X2TS U3083 ( .A(n3175), .B(n1904), .S0(n3174), .Y(n3600) );
CLKINVX3TS U3084 ( .A(n4480), .Y(n3323) );
CLKINVX3TS U3085 ( .A(n4480), .Y(n3376) );
INVX2TS U3086 ( .A(n4475), .Y(n1911) );
INVX2TS U3087 ( .A(n4475), .Y(n1912) );
INVX2TS U3088 ( .A(n3705), .Y(n1913) );
INVX2TS U3089 ( .A(n1913), .Y(n1914) );
INVX2TS U3090 ( .A(n1913), .Y(n1915) );
INVX2TS U3091 ( .A(n1908), .Y(n1916) );
INVX2TS U3092 ( .A(n1908), .Y(n1917) );
INVX2TS U3093 ( .A(n2988), .Y(n1919) );
INVX2TS U3094 ( .A(n2988), .Y(n1920) );
INVX2TS U3095 ( .A(n1905), .Y(n1921) );
INVX2TS U3096 ( .A(n1905), .Y(n1922) );
INVX2TS U3097 ( .A(n1906), .Y(n1923) );
INVX2TS U3098 ( .A(n1906), .Y(n1924) );
INVX2TS U3099 ( .A(n4479), .Y(n1925) );
INVX2TS U3100 ( .A(left_right_SHT2), .Y(n1927) );
INVX2TS U3101 ( .A(n1927), .Y(n1928) );
INVX2TS U3102 ( .A(n1927), .Y(n1929) );
OAI21X1TS U3103 ( .A0(n4206), .A1(n4235), .B0(n4207), .Y(n2101) );
OAI211X1TS U3104 ( .A0(n3294), .A1(n3418), .B0(n3236), .C0(n3235), .Y(n1701)
);
OAI21XLTS U3105 ( .A0(n4581), .A1(n3092), .B0(n2918), .Y(n1298) );
OAI21XLTS U3106 ( .A0(n4494), .A1(n3080), .B0(n2919), .Y(n1348) );
OAI21XLTS U3107 ( .A0(n4561), .A1(n3080), .B0(n3073), .Y(n1350) );
OAI21XLTS U3108 ( .A0(n4500), .A1(n3080), .B0(n2916), .Y(n1352) );
OAI21XLTS U3109 ( .A0(n4560), .A1(n3080), .B0(n3072), .Y(n1354) );
OAI21XLTS U3110 ( .A0(n4503), .A1(n3080), .B0(n2924), .Y(n1289) );
CLKBUFX3TS U3111 ( .A(n2726), .Y(n2709) );
OAI211XLTS U3112 ( .A0(n2747), .A1(n4505), .B0(n2746), .C0(n2745), .Y(n2749)
);
OR2X1TS U3113 ( .A(n3365), .B(n4505), .Y(n3311) );
CLKINVX3TS U3114 ( .A(n4480), .Y(n3431) );
OAI221X1TS U3115 ( .A0(n4508), .A1(intDX_EWSW[7]), .B0(n4579), .B1(
intDX_EWSW[6]), .C0(n3530), .Y(n3537) );
OAI221XLTS U3116 ( .A0(n4509), .A1(intDX_EWSW[5]), .B0(n4563), .B1(
intDX_EWSW[28]), .C0(n3531), .Y(n3536) );
NAND3X2TS U3117 ( .A(n3167), .B(n3166), .C(n3165), .Y(n3608) );
NAND3X2TS U3118 ( .A(n3347), .B(n3346), .C(n3345), .Y(n3610) );
NAND3X2TS U3119 ( .A(n3182), .B(n3181), .C(n3180), .Y(n3552) );
NAND3X2TS U3120 ( .A(n2810), .B(n2700), .C(n2699), .Y(n3338) );
NAND3X2TS U3121 ( .A(n3242), .B(n3241), .C(n3240), .Y(n3578) );
NAND3X2TS U3122 ( .A(n3373), .B(n3372), .C(n3371), .Y(n3579) );
NAND3X2TS U3123 ( .A(n3179), .B(n3178), .C(n3177), .Y(n3589) );
NAND3X2TS U3124 ( .A(n3190), .B(n3189), .C(n3188), .Y(n3340) );
NAND3X2TS U3125 ( .A(n3225), .B(n3224), .C(n3223), .Y(n3464) );
NAND3X2TS U3126 ( .A(n3248), .B(n3247), .C(n3246), .Y(n3571) );
NAND3X2TS U3127 ( .A(n3269), .B(n3268), .C(n3267), .Y(n3586) );
NAND3X2TS U3128 ( .A(n3281), .B(n3280), .C(n3279), .Y(n3567) );
NAND3X2TS U3129 ( .A(n3284), .B(n3283), .C(n3282), .Y(n3557) );
NAND3X2TS U3130 ( .A(n3311), .B(n3310), .C(n3309), .Y(n3572) );
NAND3X2TS U3131 ( .A(n3314), .B(n3313), .C(n3312), .Y(n3566) );
NAND3X2TS U3132 ( .A(n3406), .B(n3405), .C(n3404), .Y(n3466) );
NAND3X2TS U3133 ( .A(n3409), .B(n3408), .C(n3407), .Y(n3456) );
NAND3X2TS U3134 ( .A(n3434), .B(n3433), .C(n3432), .Y(n3454) );
INVX2TS U3135 ( .A(n3339), .Y(n1930) );
CLKINVX3TS U3136 ( .A(n2658), .Y(n3651) );
CLKINVX3TS U3137 ( .A(n2658), .Y(n2869) );
NAND2X2TS U3138 ( .A(shift_value_SHT2_EWR[3]), .B(bit_shift_SHT2), .Y(n2645)
);
OAI21XLTS U3139 ( .A0(n4331), .A1(n4330), .B0(n4291), .Y(n4284) );
OAI21XLTS U3140 ( .A0(n4331), .A1(n4310), .B0(n4291), .Y(n2841) );
OAI21XLTS U3141 ( .A0(n4331), .A1(n4320), .B0(n4291), .Y(n2837) );
OAI211XLTS U3142 ( .A0(n4320), .A1(n4292), .B0(n4291), .C0(n2675), .Y(n2676)
);
OAI211XLTS U3143 ( .A0(n4330), .A1(n4292), .B0(n4291), .C0(n2670), .Y(n2671)
);
OAI21X4TS U3144 ( .A0(shift_value_SHT2_EWR[4]), .A1(n1903), .B0(n1917), .Y(
n4291) );
INVX2TS U3145 ( .A(n1907), .Y(n1931) );
CLKINVX3TS U3146 ( .A(Shift_reg_FLAGS_7[1]), .Y(n4374) );
OAI221XLTS U3147 ( .A0(n4499), .A1(intDX_EWSW[21]), .B0(n4566), .B1(
intDX_EWSW[48]), .C0(n3515), .Y(n3520) );
AOI211X1TS U3148 ( .A0(intDX_EWSW[48]), .A1(n4566), .B0(n2209), .C0(n2215),
.Y(n2167) );
OAI21XLTS U3149 ( .A0(n4566), .A1(n3092), .B0(n3084), .Y(n1302) );
OAI221X1TS U3150 ( .A0(n4498), .A1(intDX_EWSW[15]), .B0(n4557), .B1(
intDX_EWSW[14]), .C0(n3522), .Y(n3529) );
OAI221X1TS U3151 ( .A0(n4496), .A1(intDX_EWSW[3]), .B0(n4553), .B1(
intDX_EWSW[2]), .C0(n3532), .Y(n3535) );
OAI211XLTS U3152 ( .A0(n2941), .A1(n4604), .B0(n2878), .C0(n3024), .Y(n2879)
);
OAI211XLTS U3153 ( .A0(n4618), .A1(n2941), .B0(n2885), .C0(n3024), .Y(n2886)
);
OAI211XLTS U3154 ( .A0(n2941), .A1(n4605), .B0(n2940), .C0(n3024), .Y(n2942)
);
OAI211XLTS U3155 ( .A0(n4621), .A1(n2988), .B0(n2987), .C0(n3024), .Y(n2989)
);
OAI211XLTS U3156 ( .A0(n3008), .A1(n4622), .B0(n3007), .C0(n3024), .Y(n3009)
);
NAND2X4TS U3157 ( .A(n1916), .B(shift_value_SHT2_EWR[4]), .Y(n3024) );
INVX2TS U3158 ( .A(n3657), .Y(n1932) );
INVX2TS U3159 ( .A(n1932), .Y(n1933) );
INVX2TS U3160 ( .A(n1932), .Y(n1934) );
CLKBUFX3TS U3161 ( .A(n2704), .Y(n2710) );
CLKBUFX3TS U3162 ( .A(n2703), .Y(n2707) );
OAI222X1TS U3163 ( .A0(n4465), .A1(n4531), .B0(n1959), .B1(n4466), .C0(n1987), .C1(n4467), .Y(n1622) );
AOI211X4TS U3164 ( .A0(n4296), .A1(n2843), .B0(n2329), .C0(n2328), .Y(n2732)
);
OAI21XLTS U3165 ( .A0(DmP_EXP_EWSW[55]), .A1(n1960), .B0(n4261), .Y(n4262)
);
CLKINVX3TS U3166 ( .A(n2866), .Y(n2870) );
CLKINVX3TS U3167 ( .A(n2866), .Y(n2959) );
OR2X4TS U3168 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n2866) );
OAI21X2TS U3169 ( .A0(n3000), .A1(n3648), .B0(n3005), .Y(n3644) );
AOI21X2TS U3170 ( .A0(n2949), .A1(n3022), .B0(n2948), .Y(n3626) );
INVX2TS U3171 ( .A(n1900), .Y(n1935) );
AOI21X2TS U3172 ( .A0(n2862), .A1(n3649), .B0(n3648), .Y(n3647) );
INVX2TS U3173 ( .A(n1902), .Y(n1936) );
OAI21X2TS U3174 ( .A0(n3006), .A1(n3648), .B0(n3005), .Y(n3639) );
OAI21X2TS U3175 ( .A0(n4297), .A1(n3648), .B0(n3005), .Y(n3628) );
OAI21X2TS U3176 ( .A0(n2971), .A1(n3648), .B0(n3005), .Y(n3636) );
OAI211X4TS U3177 ( .A0(n2658), .A1(n4609), .B0(n2618), .C0(n2986), .Y(n2971)
);
AOI221X1TS U3178 ( .A0(n4598), .A1(intDX_EWSW[36]), .B0(intDX_EWSW[37]),
.B1(n4525), .C0(n3501), .Y(n3502) );
AOI221X1TS U3179 ( .A0(n4595), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[33]), .B1(
n4512), .C0(n3499), .Y(n3504) );
OAI221X1TS U3180 ( .A0(n4504), .A1(intDY_EWSW[62]), .B0(n4568), .B1(
intDY_EWSW[61]), .C0(n3480), .Y(n3483) );
OAI21XLTS U3181 ( .A0(n4553), .A1(n2930), .B0(n2852), .Y(n1673) );
OAI221XLTS U3182 ( .A0(n4490), .A1(intDX_EWSW[0]), .B0(n4555), .B1(
intDX_EWSW[8]), .C0(n3533), .Y(n3534) );
OAI222X4TS U3183 ( .A0(n4467), .A1(n4531), .B0(n4486), .B1(n4466), .C0(n1987), .C1(n4465), .Y(n1293) );
OAI221X1TS U3184 ( .A0(n4582), .A1(intDY_EWSW[58]), .B0(n4503), .B1(
intDX_EWSW[57]), .C0(n3478), .Y(n3485) );
AOI221X1TS U3185 ( .A0(n4601), .A1(intDX_EWSW[44]), .B0(intDX_EWSW[45]),
.B1(n4527), .C0(n3493), .Y(n3494) );
AOI221X1TS U3186 ( .A0(n4600), .A1(intDX_EWSW[42]), .B0(intDX_EWSW[43]),
.B1(n4515), .C0(n3490), .Y(n3497) );
AOI221X1TS U3187 ( .A0(n4597), .A1(intDX_EWSW[34]), .B0(intDX_EWSW[35]),
.B1(n4513), .C0(n3498), .Y(n3505) );
OAI221XLTS U3188 ( .A0(n4516), .A1(intDX_EWSW[11]), .B0(n4581), .B1(
intDX_EWSW[50]), .C0(n3474), .Y(n3475) );
OAI221X1TS U3189 ( .A0(n4495), .A1(intDX_EWSW[27]), .B0(n4562), .B1(
intDX_EWSW[26]), .C0(n3508), .Y(n3511) );
OAI221X1TS U3190 ( .A0(n4493), .A1(intDX_EWSW[19]), .B0(n4558), .B1(
intDX_EWSW[18]), .C0(n3516), .Y(n3519) );
OAI221X1TS U3191 ( .A0(n4502), .A1(intDX_EWSW[31]), .B0(n4564), .B1(
intDX_EWSW[30]), .C0(n3506), .Y(n3513) );
OAI221XLTS U3192 ( .A0(n4494), .A1(intDX_EWSW[25]), .B0(n4565), .B1(
intDX_EWSW[32]), .C0(n3509), .Y(n3510) );
OAI221X1TS U3193 ( .A0(n4500), .A1(intDX_EWSW[23]), .B0(n4560), .B1(
intDX_EWSW[22]), .C0(n3514), .Y(n3521) );
OAI221XLTS U3194 ( .A0(n4492), .A1(intDX_EWSW[17]), .B0(n4561), .B1(
intDX_EWSW[24]), .C0(n3517), .Y(n3518) );
AOI222X1TS U3195 ( .A0(intDX_EWSW[4]), .A1(n4554), .B0(intDX_EWSW[5]), .B1(
n2245), .C0(n2244), .C1(n2243), .Y(n2249) );
OAI221XLTS U3196 ( .A0(n4497), .A1(intDX_EWSW[13]), .B0(n4554), .B1(
intDX_EWSW[4]), .C0(n3523), .Y(n3528) );
AOI222X4TS U3197 ( .A0(n2939), .A1(Data_array_SWR[33]), .B0(n2938), .B1(
Data_array_SWR[29]), .C0(n3653), .C1(Data_array_SWR[25]), .Y(n2997) );
INVX2TS U3198 ( .A(n1909), .Y(n1937) );
AOI32X1TS U3199 ( .A0(n2151), .A1(n2150), .A2(intDY_EWSW[58]), .B0(
intDY_EWSW[59]), .B1(n4524), .Y(n2152) );
OAI221XLTS U3200 ( .A0(n4583), .A1(intDY_EWSW[60]), .B0(n4524), .B1(
intDY_EWSW[59]), .C0(n3481), .Y(n3482) );
OAI2BB2XLTS U3201 ( .B0(intDX_EWSW[12]), .B1(n2258), .A0N(intDY_EWSW[13]),
.A1N(n1954), .Y(n2271) );
OAI221X1TS U3202 ( .A0(n4507), .A1(intDX_EWSW[10]), .B0(n4556), .B1(
intDX_EWSW[12]), .C0(n3524), .Y(n3527) );
OAI221XLTS U3203 ( .A0(n4491), .A1(intDX_EWSW[9]), .B0(n4578), .B1(
intDX_EWSW[16]), .C0(n3525), .Y(n3526) );
INVX2TS U3204 ( .A(n4340), .Y(n1938) );
INVX2TS U3205 ( .A(n4340), .Y(n4323) );
OAI21XLTS U3206 ( .A0(n2728), .A1(n4458), .B0(n2727), .Y(n1692) );
NOR2BX1TS U3207 ( .AN(LZD_output_NRM2_EW[1]), .B(ADD_OVRFLW_NRM2), .Y(n2334)
);
NOR4X2TS U3208 ( .A(n3545), .B(n3544), .C(n3543), .D(n3542), .Y(n4434) );
CLKINVX3TS U3209 ( .A(n1899), .Y(n3468) );
CLKINVX3TS U3210 ( .A(n1899), .Y(n3604) );
CLKINVX3TS U3211 ( .A(n1899), .Y(n3425) );
CLKINVX3TS U3212 ( .A(n1899), .Y(n3448) );
INVX2TS U3213 ( .A(n1939), .Y(n1940) );
NOR2X2TS U3214 ( .A(n2567), .B(n2566), .Y(n3156) );
INVX2TS U3215 ( .A(n4167), .Y(n4169) );
OAI21XLTS U3216 ( .A0(n4173), .A1(n4167), .B0(n4168), .Y(n2722) );
NOR2X2TS U3217 ( .A(DMP_SFG[8]), .B(DmP_mant_SFG_SWR[10]), .Y(n4167) );
NOR2X2TS U3218 ( .A(n3153), .B(n3152), .Y(n3232) );
NAND3X2TS U3219 ( .A(n3193), .B(n3192), .C(n3191), .Y(n3396) );
NAND3X2TS U3220 ( .A(n3364), .B(n3363), .C(n3362), .Y(n3455) );
NAND3X2TS U3221 ( .A(n3368), .B(n3367), .C(n3366), .Y(n3453) );
NAND3X2TS U3222 ( .A(n3210), .B(n3209), .C(n3208), .Y(n3352) );
NAND3X2TS U3223 ( .A(n3329), .B(n3328), .C(n3327), .Y(n3602) );
NAND3X2TS U3224 ( .A(n3272), .B(n3271), .C(n3270), .Y(n3587) );
NAND3X2TS U3225 ( .A(n3379), .B(n3378), .C(n3377), .Y(n3591) );
NAND3X2TS U3226 ( .A(n3239), .B(n3238), .C(n3237), .Y(n3581) );
NAND3X2TS U3227 ( .A(n3245), .B(n3244), .C(n3243), .Y(n3573) );
NAND3X2TS U3228 ( .A(n3307), .B(n3306), .C(n3305), .Y(n3574) );
NAND3X2TS U3229 ( .A(n3290), .B(n3289), .C(n3288), .Y(n3565) );
NAND3X2TS U3230 ( .A(n3187), .B(n3186), .C(n3185), .Y(n3256) );
NOR2X2TS U3231 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .Y(n2772)
);
OAI21X2TS U3232 ( .A0(n4310), .A1(n2323), .B0(n2882), .Y(n2730) );
NOR2X2TS U3233 ( .A(n3151), .B(n3150), .Y(n3294) );
CLKINVX3TS U3234 ( .A(n2393), .Y(n3664) );
NOR2X2TS U3235 ( .A(DMP_SFG[15]), .B(DmP_mant_SFG_SWR[17]), .Y(n2418) );
CLKBUFX3TS U3236 ( .A(n2705), .Y(n2706) );
OAI211XLTS U3237 ( .A0(n2856), .A1(n4320), .B0(n2643), .C0(n2642), .Y(n2644)
);
OAI211XLTS U3238 ( .A0(n2856), .A1(n4310), .B0(n2635), .C0(n2634), .Y(n2636)
);
OAI211XLTS U3239 ( .A0(n2856), .A1(n4330), .B0(n2628), .C0(n2627), .Y(n2629)
);
NOR2XLTS U3240 ( .A(n2839), .B(n2856), .Y(n2328) );
NAND2X2TS U3241 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[5]),
.Y(n2856) );
INVX2TS U3242 ( .A(n4325), .Y(n1941) );
NAND2X4TS U3243 ( .A(n4298), .B(n1928), .Y(n4325) );
AOI222X1TS U3244 ( .A0(n3148), .A1(intDX_EWSW[52]), .B0(DmP_EXP_EWSW[52]),
.B1(n4432), .C0(intDY_EWSW[52]), .C1(n3057), .Y(n2854) );
NOR2X2TS U3245 ( .A(DMP_SFG[3]), .B(DmP_mant_SFG_SWR[5]), .Y(n4206) );
INVX2TS U3246 ( .A(n4469), .Y(n1942) );
NAND2X2TS U3247 ( .A(n2352), .B(n4675), .Y(n4393) );
BUFX3TS U3248 ( .A(n2955), .Y(n4469) );
AOI21X2TS U3249 ( .A0(n3000), .A1(n4296), .B0(n2999), .Y(n3623) );
AOI21X2TS U3250 ( .A0(n3006), .A1(n4296), .B0(n2964), .Y(n3620) );
OAI211X4TS U3251 ( .A0(n2658), .A1(n4607), .B0(n2657), .C0(n2986), .Y(n3006)
);
OAI21X2TS U3252 ( .A0(n2949), .A1(n3648), .B0(n3005), .Y(n3634) );
NAND2X1TS U3253 ( .A(n2490), .B(Raw_mant_NRM_SWR[19]), .Y(n2549) );
BUFX3TS U3254 ( .A(n4674), .Y(n4444) );
OAI21XLTS U3255 ( .A0(n4431), .A1(intDX_EWSW[63]), .B0(n4466), .Y(n4430) );
OR2X1TS U3256 ( .A(n4641), .B(DMP_SFG[43]), .Y(n2083) );
OR2X1TS U3257 ( .A(n4640), .B(DMP_SFG[45]), .Y(n2087) );
OR2X1TS U3258 ( .A(n4613), .B(DMP_SFG[47]), .Y(n2091) );
OR2X1TS U3259 ( .A(n4639), .B(DMP_SFG[49]), .Y(n2095) );
OR2X1TS U3260 ( .A(DMP_SFG[44]), .B(DmP_mant_SFG_SWR[46]), .Y(n3867) );
OR2X1TS U3261 ( .A(DMP_SFG[46]), .B(DmP_mant_SFG_SWR[48]), .Y(n3752) );
OR2X1TS U3262 ( .A(DMP_SFG[48]), .B(DmP_mant_SFG_SWR[50]), .Y(n3771) );
OR2X1TS U3263 ( .A(DMP_SFG[50]), .B(DmP_mant_SFG_SWR[52]), .Y(n3732) );
NOR2X2TS U3264 ( .A(DMP_SFG[32]), .B(DmP_mant_SFG_SWR[34]), .Y(n2680) );
NAND2X1TS U3265 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n4265) );
INVX2TS U3266 ( .A(n1943), .Y(n1944) );
INVX2TS U3267 ( .A(n1945), .Y(n1946) );
INVX2TS U3268 ( .A(n1947), .Y(n1948) );
NOR2X1TS U3269 ( .A(DMP_SFG[14]), .B(DmP_mant_SFG_SWR[16]), .Y(n2416) );
NOR2X1TS U3270 ( .A(n4542), .B(DMP_SFG[16]), .Y(n2027) );
OAI21X4TS U3271 ( .A0(n2866), .A1(Data_array_SWR[53]), .B0(n2865), .Y(n4330)
);
OAI21X4TS U3272 ( .A0(n2866), .A1(Data_array_SWR[52]), .B0(n2865), .Y(n4310)
);
OAI21X4TS U3273 ( .A0(n2866), .A1(Data_array_SWR[51]), .B0(n2865), .Y(n4320)
);
NOR2X1TS U3274 ( .A(n4545), .B(DMP_SFG[2]), .Y(n1999) );
NAND2X1TS U3275 ( .A(DMP_SFG[2]), .B(DmP_mant_SFG_SWR[4]), .Y(n4235) );
OAI21XLTS U3276 ( .A0(intDX_EWSW[1]), .A1(n2239), .B0(intDX_EWSW[0]), .Y(
n2238) );
NOR2XLTS U3277 ( .A(n2259), .B(intDX_EWSW[10]), .Y(n2260) );
NOR2XLTS U3278 ( .A(n2280), .B(intDX_EWSW[16]), .Y(n2281) );
NOR2XLTS U3279 ( .A(n2209), .B(intDX_EWSW[48]), .Y(n2210) );
NOR2XLTS U3280 ( .A(n2292), .B(intDX_EWSW[24]), .Y(n2227) );
AOI211X2TS U3281 ( .A0(intDX_EWSW[44]), .A1(n2171), .B0(n2170), .C0(n2177),
.Y(n2185) );
NOR2XLTS U3282 ( .A(n2170), .B(intDX_EWSW[44]), .Y(n2168) );
NAND2X1TS U3283 ( .A(n4525), .B(intDX_EWSW[37]), .Y(n2191) );
OAI21XLTS U3284 ( .A0(intDX_EWSW[37]), .A1(n4525), .B0(n2186), .Y(n2196) );
OR2X1TS U3285 ( .A(Raw_mant_NRM_SWR[16]), .B(Raw_mant_NRM_SWR[15]), .Y(n1977) );
OR4X2TS U3286 ( .A(n2305), .B(n2304), .C(n2303), .D(n2302), .Y(n1982) );
AND2X4TS U3287 ( .A(n3176), .B(n3174), .Y(n1995) );
OAI21XLTS U3288 ( .A0(intDY_EWSW[3]), .A1(n1949), .B0(intDY_EWSW[2]), .Y(
n2242) );
OAI21XLTS U3289 ( .A0(Raw_mant_NRM_SWR[50]), .A1(n4483), .B0(n4522), .Y(
n2530) );
OAI21XLTS U3290 ( .A0(n2380), .A1(n3722), .B0(n2381), .Y(n2124) );
INVX2TS U3291 ( .A(n2758), .Y(n2533) );
OAI21XLTS U3292 ( .A0(n2509), .A1(n2508), .B0(n2507), .Y(n2511) );
NOR2X1TS U3293 ( .A(n3720), .B(n2049), .Y(n2051) );
OAI2BB2XLTS U3294 ( .B0(intDX_EWSW[20]), .B1(n2279), .A0N(intDY_EWSW[21]),
.A1N(n1966), .Y(n2290) );
OAI21XLTS U3295 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n4521), .B0(n4588), .Y(
n2537) );
NAND2X1TS U3296 ( .A(n2373), .B(n2129), .Y(n2115) );
OR2X1TS U3297 ( .A(Raw_mant_NRM_SWR[20]), .B(Raw_mant_NRM_SWR[19]), .Y(n2535) );
NOR2XLTS U3298 ( .A(Raw_mant_NRM_SWR[34]), .B(Raw_mant_NRM_SWR[32]), .Y(
n2741) );
NAND2X1TS U3299 ( .A(n3786), .B(n2133), .Y(n2812) );
OAI21X1TS U3300 ( .A0(n2410), .A1(n2112), .B0(n2111), .Y(n2113) );
INVX2TS U3301 ( .A(n4115), .Y(n4118) );
NOR2XLTS U3302 ( .A(n4656), .B(DMP_SFG[0]), .Y(n1997) );
INVX2TS U3303 ( .A(n4156), .Y(n4141) );
OR2X1TS U3304 ( .A(n2555), .B(n2554), .Y(n2556) );
INVX2TS U3305 ( .A(n3782), .Y(n3784) );
INVX2TS U3306 ( .A(n3915), .Y(n3917) );
OR2X1TS U3307 ( .A(n3429), .B(n4533), .Y(n3187) );
OAI21XLTS U3308 ( .A0(n4330), .A1(n4329), .B0(n1931), .Y(n4336) );
OAI211XLTS U3309 ( .A0(n4310), .A1(n4292), .B0(n4291), .C0(n4290), .Y(n4293)
);
INVX2TS U3310 ( .A(n4178), .Y(n4181) );
INVX2TS U3311 ( .A(n2409), .Y(n4173) );
INVX2TS U3312 ( .A(n3876), .Y(n3879) );
INVX2TS U3313 ( .A(n3798), .Y(n3799) );
INVX2TS U3314 ( .A(n2574), .Y(n3849) );
OAI21X1TS U3315 ( .A0(n2041), .A1(n3927), .B0(n2040), .Y(n3949) );
OAI21XLTS U3316 ( .A0(n4055), .A1(n4054), .B0(n4053), .Y(n4057) );
INVX2TS U3317 ( .A(n4080), .Y(n4083) );
OR2X1TS U3318 ( .A(n3374), .B(n4625), .Y(n3290) );
OR2X1TS U3319 ( .A(n3374), .B(n4521), .Y(n3248) );
OR2X1TS U3320 ( .A(n3374), .B(n4661), .Y(n3379) );
OR2X1TS U3321 ( .A(n3618), .B(n4510), .Y(n3347) );
OR2X1TS U3322 ( .A(n3365), .B(n4592), .Y(n3225) );
OR2X1TS U3323 ( .A(n3429), .B(n4673), .Y(n3364) );
OR2X1TS U3324 ( .A(n3429), .B(n4670), .Y(n2698) );
AOI211XLTS U3325 ( .A0(n4338), .A1(n4308), .B0(n2395), .C0(n2394), .Y(n2396)
);
AOI21X2TS U3326 ( .A0(n3133), .A1(n2099), .B0(n2098), .Y(n2100) );
OAI21XLTS U3327 ( .A0(n3940), .A1(n3939), .B0(n3938), .Y(n3943) );
OAI21XLTS U3328 ( .A0(n4044), .A1(n4038), .B0(n4039), .Y(n2437) );
OAI21XLTS U3329 ( .A0(DmP_EXP_EWSW[53]), .A1(n1959), .B0(n4253), .Y(n4254)
);
INVX2TS U3330 ( .A(DmP_mant_SFG_SWR[0]), .Y(n4272) );
CLKBUFX2TS U3331 ( .A(n4414), .Y(n4422) );
AND3X1TS U3332 ( .A(n3213), .B(n3212), .C(n3211), .Y(n3263) );
AFHCINX2TS U3333 ( .CIN(n2347), .B(n2348), .A(DMP_exp_NRM2_EW[5]), .S(n2446),
.CO(n2362) );
BUFX3TS U3334 ( .A(n2930), .Y(n3121) );
BUFX3TS U3335 ( .A(n2930), .Y(n3117) );
BUFX3TS U3336 ( .A(n2930), .Y(n3104) );
AND3X1TS U3337 ( .A(n3231), .B(n3230), .C(n3229), .Y(n3559) );
AND3X1TS U3338 ( .A(n3300), .B(n3299), .C(n3298), .Y(n3570) );
AND3X1TS U3339 ( .A(n3385), .B(n3384), .C(n3383), .Y(n3585) );
INVX2TS U3340 ( .A(n3176), .Y(n3555) );
AND3X1TS U3341 ( .A(n3170), .B(n3169), .C(n3168), .Y(n3391) );
AND3X1TS U3342 ( .A(n3219), .B(n3218), .C(n3217), .Y(n3332) );
AND3X1TS U3343 ( .A(n3360), .B(n3359), .C(n3358), .Y(n3399) );
BUFX3TS U3344 ( .A(n4418), .Y(n4415) );
OAI2BB1X1TS U3345 ( .A0N(n4174), .A1N(n2831), .B0(n2830), .Y(n1228) );
OAI2BB1X1TS U3346 ( .A0N(n4174), .A1N(n2389), .B0(n2388), .Y(n1236) );
NAND2X1TS U3347 ( .A(n4489), .B(n4272), .Y(n4267) );
NAND2X1TS U3348 ( .A(n4656), .B(DMP_SFG[0]), .Y(n1996) );
OAI21X1TS U3349 ( .A0(n4267), .A1(n1997), .B0(n1996), .Y(n4231) );
NOR2X1TS U3350 ( .A(n4653), .B(DMP_SFG[1]), .Y(n4233) );
NAND2X1TS U3351 ( .A(n4653), .B(DMP_SFG[1]), .Y(n4232) );
NAND2X1TS U3352 ( .A(n4545), .B(DMP_SFG[2]), .Y(n1998) );
AOI21X1TS U3353 ( .A0(n4231), .A1(n2001), .B0(n2000), .Y(n4123) );
NOR2X1TS U3354 ( .A(n1976), .B(DMP_SFG[3]), .Y(n4217) );
NOR2X1TS U3355 ( .A(n4544), .B(DMP_SFG[4]), .Y(n2003) );
NOR2X1TS U3356 ( .A(n4217), .B(n2003), .Y(n4125) );
NOR2X1TS U3357 ( .A(n4652), .B(DMP_SFG[5]), .Y(n4139) );
NOR2X1TS U3358 ( .A(n4636), .B(DMP_SFG[6]), .Y(n2005) );
NOR2X1TS U3359 ( .A(n4139), .B(n2005), .Y(n2007) );
NAND2X1TS U3360 ( .A(n4125), .B(n2007), .Y(n2009) );
NAND2X1TS U3361 ( .A(n1976), .B(DMP_SFG[3]), .Y(n4218) );
NAND2X1TS U3362 ( .A(n4544), .B(DMP_SFG[4]), .Y(n2002) );
OAI21X1TS U3363 ( .A0(n2003), .A1(n4218), .B0(n2002), .Y(n4124) );
NAND2X1TS U3364 ( .A(n4652), .B(DMP_SFG[5]), .Y(n4138) );
NAND2X1TS U3365 ( .A(n4636), .B(DMP_SFG[6]), .Y(n2004) );
AOI21X1TS U3366 ( .A0(n4124), .A1(n2007), .B0(n2006), .Y(n2008) );
NOR2X1TS U3367 ( .A(n4651), .B(DMP_SFG[7]), .Y(n4165) );
NOR2X1TS U3368 ( .A(n4635), .B(DMP_SFG[8]), .Y(n2011) );
NOR2X1TS U3369 ( .A(n4165), .B(n2011), .Y(n2713) );
NOR2X1TS U3370 ( .A(n4650), .B(DMP_SFG[9]), .Y(n4107) );
NOR2X1TS U3371 ( .A(n4638), .B(DMP_SFG[10]), .Y(n2013) );
NOR2X1TS U3372 ( .A(n4655), .B(DMP_SFG[11]), .Y(n4178) );
NOR2X1TS U3373 ( .A(n4637), .B(DMP_SFG[12]), .Y(n2017) );
NOR2X1TS U3374 ( .A(n4178), .B(n2017), .Y(n4076) );
NOR2X1TS U3375 ( .A(n4654), .B(DMP_SFG[13]), .Y(n4080) );
NOR2X1TS U3376 ( .A(n4543), .B(DMP_SFG[14]), .Y(n2019) );
NAND2X1TS U3377 ( .A(n4651), .B(DMP_SFG[7]), .Y(n4164) );
NAND2X1TS U3378 ( .A(n4635), .B(DMP_SFG[8]), .Y(n2010) );
OAI21X1TS U3379 ( .A0(n2011), .A1(n4164), .B0(n2010), .Y(n2714) );
NAND2X1TS U3380 ( .A(n4650), .B(DMP_SFG[9]), .Y(n4108) );
NAND2X1TS U3381 ( .A(n4638), .B(DMP_SFG[10]), .Y(n2012) );
AOI21X1TS U3382 ( .A0(n2714), .A1(n2015), .B0(n2014), .Y(n4074) );
NAND2X1TS U3383 ( .A(n4655), .B(DMP_SFG[11]), .Y(n4179) );
NAND2X1TS U3384 ( .A(n4637), .B(DMP_SFG[12]), .Y(n2016) );
OAI21X1TS U3385 ( .A0(n2017), .A1(n4179), .B0(n2016), .Y(n4077) );
NAND2X1TS U3386 ( .A(n4654), .B(DMP_SFG[13]), .Y(n4081) );
NAND2X1TS U3387 ( .A(n4543), .B(DMP_SFG[14]), .Y(n2018) );
AOI21X1TS U3388 ( .A0(n4077), .A1(n2021), .B0(n2020), .Y(n2022) );
OAI21X1TS U3389 ( .A0(n4074), .A1(n2023), .B0(n2022), .Y(n2024) );
NOR2X1TS U3390 ( .A(n4551), .B(DMP_SFG[15]), .Y(n4007) );
NOR2X1TS U3391 ( .A(n4007), .B(n2027), .Y(n3995) );
NOR2X1TS U3392 ( .A(n4649), .B(DMP_SFG[17]), .Y(n3997) );
NOR2X1TS U3393 ( .A(n4541), .B(DMP_SFG[18]), .Y(n2029) );
NOR2X1TS U3394 ( .A(n4550), .B(DMP_SFG[19]), .Y(n3985) );
NOR2X1TS U3395 ( .A(n4540), .B(DMP_SFG[20]), .Y(n2033) );
NOR2X1TS U3396 ( .A(n3985), .B(n2033), .Y(n4035) );
NOR2X1TS U3397 ( .A(n4648), .B(DMP_SFG[21]), .Y(n4037) );
NOR2X1TS U3398 ( .A(n4634), .B(DMP_SFG[22]), .Y(n2035) );
NOR2X1TS U3399 ( .A(n4647), .B(DMP_SFG[23]), .Y(n3928) );
NOR2X1TS U3400 ( .A(n4633), .B(DMP_SFG[24]), .Y(n2041) );
NOR2X1TS U3401 ( .A(n3928), .B(n2041), .Y(n3950) );
NOR2X1TS U3402 ( .A(n4549), .B(DMP_SFG[25]), .Y(n3953) );
NOR2X1TS U3403 ( .A(n4632), .B(DMP_SFG[26]), .Y(n2043) );
NOR2X1TS U3404 ( .A(n4646), .B(DMP_SFG[27]), .Y(n3939) );
NOR2X1TS U3405 ( .A(n4631), .B(DMP_SFG[28]), .Y(n2047) );
NOR2X1TS U3406 ( .A(n3939), .B(n2047), .Y(n3718) );
NOR2X1TS U3407 ( .A(n4645), .B(DMP_SFG[29]), .Y(n3720) );
NOR2X1TS U3408 ( .A(n4539), .B(DMP_SFG[30]), .Y(n2049) );
NOR2X2TS U3409 ( .A(n3713), .B(n2053), .Y(n2055) );
NAND2X1TS U3410 ( .A(n4551), .B(DMP_SFG[15]), .Y(n4008) );
NAND2X1TS U3411 ( .A(n4542), .B(DMP_SFG[16]), .Y(n2026) );
OAI21X1TS U3412 ( .A0(n2027), .A1(n4008), .B0(n2026), .Y(n3994) );
NAND2X1TS U3413 ( .A(n4649), .B(DMP_SFG[17]), .Y(n3996) );
NAND2X1TS U3414 ( .A(n4541), .B(DMP_SFG[18]), .Y(n2028) );
AOI21X1TS U3415 ( .A0(n3994), .A1(n2031), .B0(n2030), .Y(n3981) );
NAND2X1TS U3416 ( .A(n4550), .B(DMP_SFG[19]), .Y(n3984) );
NAND2X1TS U3417 ( .A(n4540), .B(DMP_SFG[20]), .Y(n2032) );
OAI21X1TS U3418 ( .A0(n2033), .A1(n3984), .B0(n2032), .Y(n4034) );
NAND2X1TS U3419 ( .A(n4648), .B(DMP_SFG[21]), .Y(n4036) );
NAND2X1TS U3420 ( .A(n4634), .B(DMP_SFG[22]), .Y(n2034) );
AOI21X1TS U3421 ( .A0(n4034), .A1(n2037), .B0(n2036), .Y(n2038) );
NAND2X1TS U3422 ( .A(n4647), .B(DMP_SFG[23]), .Y(n3927) );
NAND2X1TS U3423 ( .A(n4633), .B(DMP_SFG[24]), .Y(n2040) );
NAND2X1TS U3424 ( .A(n4549), .B(DMP_SFG[25]), .Y(n3952) );
NAND2X1TS U3425 ( .A(n4632), .B(DMP_SFG[26]), .Y(n2042) );
AOI21X1TS U3426 ( .A0(n3949), .A1(n2045), .B0(n2044), .Y(n3714) );
NAND2X1TS U3427 ( .A(n4646), .B(DMP_SFG[27]), .Y(n3938) );
NAND2X1TS U3428 ( .A(n4631), .B(DMP_SFG[28]), .Y(n2046) );
OAI21X1TS U3429 ( .A0(n2047), .A1(n3938), .B0(n2046), .Y(n3717) );
NAND2X1TS U3430 ( .A(n4645), .B(DMP_SFG[29]), .Y(n3719) );
NAND2X1TS U3431 ( .A(n4539), .B(DMP_SFG[30]), .Y(n2048) );
AOI21X1TS U3432 ( .A0(n3717), .A1(n2051), .B0(n2050), .Y(n2052) );
OAI21X4TS U3433 ( .A0(n2422), .A1(n2057), .B0(n2056), .Y(n2384) );
NOR2X1TS U3434 ( .A(n4548), .B(DMP_SFG[31]), .Y(n2679) );
NOR2X1TS U3435 ( .A(n4538), .B(DMP_SFG[32]), .Y(n2059) );
NOR2X1TS U3436 ( .A(n2679), .B(n2059), .Y(n2593) );
NOR2X1TS U3437 ( .A(n4644), .B(DMP_SFG[33]), .Y(n3900) );
NOR2X1TS U3438 ( .A(n4537), .B(DMP_SFG[34]), .Y(n2061) );
NOR2X1TS U3439 ( .A(n4547), .B(DMP_SFG[35]), .Y(n3797) );
NOR2X1TS U3440 ( .A(n4536), .B(DMP_SFG[36]), .Y(n2065) );
NOR2X1TS U3441 ( .A(n4546), .B(DMP_SFG[37]), .Y(n3828) );
NOR2X1TS U3442 ( .A(n4535), .B(DMP_SFG[38]), .Y(n2067) );
NOR2X1TS U3443 ( .A(n4573), .B(DMP_SFG[39]), .Y(n3876) );
NOR2X1TS U3444 ( .A(n4572), .B(DMP_SFG[40]), .Y(n2073) );
NOR2X1TS U3445 ( .A(n4643), .B(DMP_SFG[41]), .Y(n2077) );
NOR2X2TS U3446 ( .A(n2586), .B(n2077), .Y(n2079) );
NAND2X1TS U3447 ( .A(n4548), .B(DMP_SFG[31]), .Y(n2678) );
NAND2X1TS U3448 ( .A(n4538), .B(DMP_SFG[32]), .Y(n2058) );
OAI21X1TS U3449 ( .A0(n2059), .A1(n2678), .B0(n2058), .Y(n2594) );
NAND2X1TS U3450 ( .A(n4644), .B(DMP_SFG[33]), .Y(n3901) );
NAND2X1TS U3451 ( .A(n4537), .B(DMP_SFG[34]), .Y(n2060) );
OAI21X1TS U3452 ( .A0(n2061), .A1(n3901), .B0(n2060), .Y(n2062) );
AOI21X2TS U3453 ( .A0(n2594), .A1(n2063), .B0(n2062), .Y(n3779) );
NAND2X1TS U3454 ( .A(n4547), .B(DMP_SFG[35]), .Y(n3798) );
NAND2X1TS U3455 ( .A(n4536), .B(DMP_SFG[36]), .Y(n2064) );
OAI21X1TS U3456 ( .A0(n2065), .A1(n3798), .B0(n2064), .Y(n3811) );
NAND2X1TS U3457 ( .A(n4546), .B(DMP_SFG[37]), .Y(n3829) );
NAND2X1TS U3458 ( .A(n4535), .B(DMP_SFG[38]), .Y(n2066) );
OAI21X1TS U3459 ( .A0(n2067), .A1(n3829), .B0(n2066), .Y(n2068) );
AOI21X1TS U3460 ( .A0(n3811), .A1(n2069), .B0(n2068), .Y(n2070) );
NAND2X1TS U3461 ( .A(n4573), .B(DMP_SFG[39]), .Y(n3877) );
NAND2X1TS U3462 ( .A(n4572), .B(DMP_SFG[40]), .Y(n2072) );
NAND2X1TS U3463 ( .A(n4643), .B(DMP_SFG[41]), .Y(n2076) );
OAI21X2TS U3464 ( .A0(n2585), .A1(n2077), .B0(n2076), .Y(n2078) );
AOI21X4TS U3465 ( .A0(n2384), .A1(n2079), .B0(n2078), .Y(n3846) );
NAND2X1TS U3466 ( .A(n4642), .B(DMP_SFG[42]), .Y(n2080) );
NAND2X1TS U3467 ( .A(n4658), .B(DMP_SFG[44]), .Y(n2084) );
NAND2X1TS U3468 ( .A(n4614), .B(DMP_SFG[46]), .Y(n2088) );
NAND2X1TS U3469 ( .A(n4623), .B(DMP_SFG[48]), .Y(n2092) );
NAND2X1TS U3470 ( .A(n4657), .B(DMP_SFG[50]), .Y(n2096) );
OR2X1TS U3471 ( .A(n4624), .B(DMP_SFG[51]), .Y(n2099) );
AND2X2TS U3472 ( .A(n1926), .B(OP_FLAG_SFG), .Y(n3979) );
NOR2X1TS U3473 ( .A(DMP_SFG[16]), .B(DmP_mant_SFG_SWR[18]), .Y(n4012) );
NOR2X2TS U3474 ( .A(DMP_SFG[17]), .B(DmP_mant_SFG_SWR[19]), .Y(n4019) );
NOR2X1TS U3475 ( .A(n4012), .B(n4019), .Y(n4002) );
NOR2X2TS U3476 ( .A(DMP_SFG[18]), .B(DmP_mant_SFG_SWR[20]), .Y(n4067) );
NOR2X2TS U3477 ( .A(DMP_SFG[19]), .B(DmP_mant_SFG_SWR[21]), .Y(n4061) );
NOR2X2TS U3478 ( .A(DMP_SFG[20]), .B(DmP_mant_SFG_SWR[22]), .Y(n4054) );
NOR2X2TS U3479 ( .A(DMP_SFG[21]), .B(DmP_mant_SFG_SWR[23]), .Y(n4048) );
NOR2X1TS U3480 ( .A(n4054), .B(n4048), .Y(n2433) );
NOR2X2TS U3481 ( .A(DMP_SFG[22]), .B(DmP_mant_SFG_SWR[24]), .Y(n4038) );
NOR2X2TS U3482 ( .A(DMP_SFG[23]), .B(DmP_mant_SFG_SWR[25]), .Y(n2434) );
NOR2X2TS U3483 ( .A(DMP_SFG[24]), .B(DmP_mant_SFG_SWR[26]), .Y(n4357) );
NOR2X2TS U3484 ( .A(DMP_SFG[25]), .B(DmP_mant_SFG_SWR[27]), .Y(n4351) );
NOR2X2TS U3485 ( .A(DMP_SFG[26]), .B(DmP_mant_SFG_SWR[28]), .Y(n3954) );
NOR2X2TS U3486 ( .A(DMP_SFG[27]), .B(DmP_mant_SFG_SWR[29]), .Y(n3915) );
NOR2X2TS U3487 ( .A(DMP_SFG[28]), .B(DmP_mant_SFG_SWR[30]), .Y(n3970) );
NOR2X2TS U3488 ( .A(DMP_SFG[29]), .B(DmP_mant_SFG_SWR[31]), .Y(n3964) );
NOR2X2TS U3489 ( .A(DMP_SFG[30]), .B(DmP_mant_SFG_SWR[32]), .Y(n3721) );
NOR2X2TS U3490 ( .A(DMP_SFG[31]), .B(DmP_mant_SFG_SWR[33]), .Y(n2380) );
NOR2X1TS U3491 ( .A(DMP_SFG[1]), .B(DmP_mant_SFG_SWR[3]), .Y(n4244) );
NAND2X1TS U3492 ( .A(DMP_SFG[1]), .B(DmP_mant_SFG_SWR[3]), .Y(n4245) );
OAI21X1TS U3493 ( .A0(n4244), .A1(n4265), .B0(n4245), .Y(n4210) );
NOR2X2TS U3494 ( .A(DMP_SFG[2]), .B(DmP_mant_SFG_SWR[4]), .Y(n4234) );
NOR2X1TS U3495 ( .A(n4234), .B(n4206), .Y(n2102) );
NAND2X1TS U3496 ( .A(DMP_SFG[3]), .B(DmP_mant_SFG_SWR[5]), .Y(n4207) );
NOR2X1TS U3497 ( .A(DMP_SFG[4]), .B(DmP_mant_SFG_SWR[6]), .Y(n4131) );
NOR2X2TS U3498 ( .A(DMP_SFG[5]), .B(DmP_mant_SFG_SWR[7]), .Y(n4126) );
NOR2X1TS U3499 ( .A(n4131), .B(n4126), .Y(n4145) );
NOR2X2TS U3500 ( .A(DMP_SFG[6]), .B(DmP_mant_SFG_SWR[8]), .Y(n4156) );
NOR2X2TS U3501 ( .A(DMP_SFG[7]), .B(DmP_mant_SFG_SWR[9]), .Y(n4151) );
NAND2X1TS U3502 ( .A(DMP_SFG[4]), .B(DmP_mant_SFG_SWR[6]), .Y(n4222) );
NAND2X1TS U3503 ( .A(DMP_SFG[5]), .B(DmP_mant_SFG_SWR[7]), .Y(n4127) );
OAI21X1TS U3504 ( .A0(n4126), .A1(n4222), .B0(n4127), .Y(n4144) );
NAND2X1TS U3505 ( .A(DMP_SFG[6]), .B(DmP_mant_SFG_SWR[8]), .Y(n4155) );
NAND2X1TS U3506 ( .A(DMP_SFG[7]), .B(DmP_mant_SFG_SWR[9]), .Y(n4152) );
AOI21X1TS U3507 ( .A0(n4144), .A1(n2104), .B0(n2103), .Y(n2105) );
NOR2X2TS U3508 ( .A(DMP_SFG[9]), .B(DmP_mant_SFG_SWR[11]), .Y(n2717) );
NOR2X1TS U3509 ( .A(n4167), .B(n2717), .Y(n4115) );
NOR2X1TS U3510 ( .A(DMP_SFG[10]), .B(DmP_mant_SFG_SWR[12]), .Y(n4112) );
NOR2X2TS U3511 ( .A(DMP_SFG[11]), .B(DmP_mant_SFG_SWR[13]), .Y(n4192) );
NOR2X1TS U3512 ( .A(DMP_SFG[12]), .B(DmP_mant_SFG_SWR[14]), .Y(n4099) );
NOR2X2TS U3513 ( .A(DMP_SFG[13]), .B(DmP_mant_SFG_SWR[15]), .Y(n4094) );
NOR2X2TS U3514 ( .A(n2416), .B(n2418), .Y(n2110) );
NAND2X1TS U3515 ( .A(DMP_SFG[8]), .B(DmP_mant_SFG_SWR[10]), .Y(n4168) );
NAND2X1TS U3516 ( .A(DMP_SFG[9]), .B(DmP_mant_SFG_SWR[11]), .Y(n2718) );
NAND2X1TS U3517 ( .A(DMP_SFG[10]), .B(DmP_mant_SFG_SWR[12]), .Y(n4197) );
NAND2X1TS U3518 ( .A(DMP_SFG[11]), .B(DmP_mant_SFG_SWR[13]), .Y(n4193) );
AOI21X1TS U3519 ( .A0(n4116), .A1(n2108), .B0(n2107), .Y(n2410) );
NAND2X1TS U3520 ( .A(DMP_SFG[12]), .B(DmP_mant_SFG_SWR[14]), .Y(n4183) );
NAND2X1TS U3521 ( .A(DMP_SFG[13]), .B(DmP_mant_SFG_SWR[15]), .Y(n4095) );
OAI21X1TS U3522 ( .A0(n4094), .A1(n4183), .B0(n4095), .Y(n2413) );
NAND2X1TS U3523 ( .A(DMP_SFG[14]), .B(DmP_mant_SFG_SWR[16]), .Y(n4084) );
NAND2X1TS U3524 ( .A(DMP_SFG[15]), .B(DmP_mant_SFG_SWR[17]), .Y(n2419) );
AOI21X1TS U3525 ( .A0(n2413), .A1(n2110), .B0(n2109), .Y(n2111) );
NAND2X1TS U3526 ( .A(DMP_SFG[16]), .B(DmP_mant_SFG_SWR[18]), .Y(n4024) );
NAND2X1TS U3527 ( .A(DMP_SFG[17]), .B(DmP_mant_SFG_SWR[19]), .Y(n4020) );
OAI21X1TS U3528 ( .A0(n4019), .A1(n4024), .B0(n4020), .Y(n4001) );
NAND2X1TS U3529 ( .A(DMP_SFG[18]), .B(DmP_mant_SFG_SWR[20]), .Y(n4066) );
NAND2X1TS U3530 ( .A(DMP_SFG[19]), .B(DmP_mant_SFG_SWR[21]), .Y(n4062) );
NAND2X1TS U3531 ( .A(DMP_SFG[20]), .B(DmP_mant_SFG_SWR[22]), .Y(n4053) );
NAND2X1TS U3532 ( .A(DMP_SFG[21]), .B(DmP_mant_SFG_SWR[23]), .Y(n4049) );
OAI21X1TS U3533 ( .A0(n4048), .A1(n4053), .B0(n4049), .Y(n2432) );
NAND2X1TS U3534 ( .A(DMP_SFG[22]), .B(DmP_mant_SFG_SWR[24]), .Y(n4039) );
NAND2X1TS U3535 ( .A(DMP_SFG[23]), .B(DmP_mant_SFG_SWR[25]), .Y(n2435) );
AOI21X1TS U3536 ( .A0(n2432), .A1(n2119), .B0(n2118), .Y(n2120) );
NAND2X1TS U3537 ( .A(DMP_SFG[24]), .B(DmP_mant_SFG_SWR[26]), .Y(n4356) );
NAND2X1TS U3538 ( .A(DMP_SFG[25]), .B(DmP_mant_SFG_SWR[27]), .Y(n4352) );
NAND2X1TS U3539 ( .A(DMP_SFG[26]), .B(DmP_mant_SFG_SWR[28]), .Y(n3955) );
NAND2X1TS U3540 ( .A(DMP_SFG[27]), .B(DmP_mant_SFG_SWR[29]), .Y(n3916) );
AOI21X1TS U3541 ( .A0(n3920), .A1(n2123), .B0(n2122), .Y(n2375) );
NAND2X1TS U3542 ( .A(DMP_SFG[28]), .B(DmP_mant_SFG_SWR[30]), .Y(n3969) );
NAND2X1TS U3543 ( .A(DMP_SFG[29]), .B(DmP_mant_SFG_SWR[31]), .Y(n3965) );
OAI21X1TS U3544 ( .A0(n3964), .A1(n3969), .B0(n3965), .Y(n2378) );
NAND2X1TS U3545 ( .A(DMP_SFG[30]), .B(DmP_mant_SFG_SWR[32]), .Y(n3722) );
NAND2X1TS U3546 ( .A(DMP_SFG[31]), .B(DmP_mant_SFG_SWR[33]), .Y(n2381) );
AOI21X1TS U3547 ( .A0(n2378), .A1(n2125), .B0(n2124), .Y(n2126) );
OAI21X1TS U3548 ( .A0(n2375), .A1(n2127), .B0(n2126), .Y(n2128) );
AO21X4TS U3549 ( .A0(n2372), .A1(n2129), .B0(n2128), .Y(n2130) );
NOR2X2TS U3550 ( .A(DMP_SFG[33]), .B(DmP_mant_SFG_SWR[35]), .Y(n2597) );
NOR2X1TS U3551 ( .A(n2680), .B(n2597), .Y(n3786) );
NOR2X1TS U3552 ( .A(DMP_SFG[34]), .B(DmP_mant_SFG_SWR[36]), .Y(n3790) );
NOR2X2TS U3553 ( .A(DMP_SFG[35]), .B(DmP_mant_SFG_SWR[37]), .Y(n3782) );
NOR2X1TS U3554 ( .A(DMP_SFG[36]), .B(DmP_mant_SFG_SWR[38]), .Y(n3802) );
NOR2X2TS U3555 ( .A(DMP_SFG[37]), .B(DmP_mant_SFG_SWR[39]), .Y(n3815) );
NOR2X1TS U3556 ( .A(DMP_SFG[38]), .B(DmP_mant_SFG_SWR[40]), .Y(n2817) );
NOR2X2TS U3557 ( .A(DMP_SFG[39]), .B(DmP_mant_SFG_SWR[41]), .Y(n2819) );
NOR2X1TS U3558 ( .A(DMP_SFG[40]), .B(DmP_mant_SFG_SWR[42]), .Y(n2579) );
NOR2X2TS U3559 ( .A(DMP_SFG[41]), .B(DmP_mant_SFG_SWR[43]), .Y(n2581) );
NOR2X2TS U3560 ( .A(DMP_SFG[42]), .B(DmP_mant_SFG_SWR[44]), .Y(n3842) );
NOR2X2TS U3561 ( .A(n3848), .B(n3842), .Y(n2141) );
NAND2X1TS U3562 ( .A(DMP_SFG[32]), .B(DmP_mant_SFG_SWR[34]), .Y(n2681) );
NAND2X1TS U3563 ( .A(DMP_SFG[33]), .B(DmP_mant_SFG_SWR[35]), .Y(n2598) );
OAI21X1TS U3564 ( .A0(n2597), .A1(n2681), .B0(n2598), .Y(n3787) );
NAND2X1TS U3565 ( .A(DMP_SFG[34]), .B(DmP_mant_SFG_SWR[36]), .Y(n3905) );
NAND2X1TS U3566 ( .A(DMP_SFG[35]), .B(DmP_mant_SFG_SWR[37]), .Y(n3783) );
OAI21X1TS U3567 ( .A0(n3782), .A1(n3905), .B0(n3783), .Y(n2132) );
AOI21X2TS U3568 ( .A0(n3787), .A1(n2133), .B0(n2132), .Y(n2811) );
NAND2X1TS U3569 ( .A(DMP_SFG[36]), .B(DmP_mant_SFG_SWR[38]), .Y(n3819) );
NAND2X1TS U3570 ( .A(DMP_SFG[37]), .B(DmP_mant_SFG_SWR[39]), .Y(n3816) );
OAI21X1TS U3571 ( .A0(n3815), .A1(n3819), .B0(n3816), .Y(n2814) );
NAND2X1TS U3572 ( .A(DMP_SFG[38]), .B(DmP_mant_SFG_SWR[40]), .Y(n3833) );
NAND2X1TS U3573 ( .A(DMP_SFG[39]), .B(DmP_mant_SFG_SWR[41]), .Y(n2820) );
AOI21X1TS U3574 ( .A0(n2814), .A1(n2135), .B0(n2134), .Y(n2136) );
NAND2X1TS U3575 ( .A(DMP_SFG[40]), .B(DmP_mant_SFG_SWR[42]), .Y(n3881) );
NAND2X1TS U3576 ( .A(DMP_SFG[41]), .B(DmP_mant_SFG_SWR[43]), .Y(n2582) );
OAI21X1TS U3577 ( .A0(n2581), .A1(n3881), .B0(n2582), .Y(n2138) );
NAND2X1TS U3578 ( .A(DMP_SFG[42]), .B(DmP_mant_SFG_SWR[44]), .Y(n3843) );
OAI21X2TS U3579 ( .A0(n3847), .A1(n3842), .B0(n3843), .Y(n2140) );
AOI21X4TS U3580 ( .A0(n2574), .A1(n2141), .B0(n2140), .Y(n3862) );
NOR2X1TS U3581 ( .A(DMP_SFG[43]), .B(DmP_mant_SFG_SWR[45]), .Y(n3856) );
NAND2X1TS U3582 ( .A(DMP_SFG[43]), .B(DmP_mant_SFG_SWR[45]), .Y(n3857) );
NAND2X1TS U3583 ( .A(DMP_SFG[44]), .B(DmP_mant_SFG_SWR[46]), .Y(n3866) );
INVX2TS U3584 ( .A(n3866), .Y(n2142) );
AOI21X4TS U3585 ( .A0(n3871), .A1(n3867), .B0(n2142), .Y(n3896) );
NOR2X1TS U3586 ( .A(DMP_SFG[45]), .B(DmP_mant_SFG_SWR[47]), .Y(n3890) );
NAND2X1TS U3587 ( .A(DMP_SFG[45]), .B(DmP_mant_SFG_SWR[47]), .Y(n3891) );
NAND2X1TS U3588 ( .A(DMP_SFG[46]), .B(DmP_mant_SFG_SWR[48]), .Y(n3751) );
INVX2TS U3589 ( .A(n3751), .Y(n2143) );
AOI21X4TS U3590 ( .A0(n3755), .A1(n3752), .B0(n2143), .Y(n3766) );
NOR2X1TS U3591 ( .A(DMP_SFG[47]), .B(DmP_mant_SFG_SWR[49]), .Y(n3760) );
NAND2X1TS U3592 ( .A(DMP_SFG[47]), .B(DmP_mant_SFG_SWR[49]), .Y(n3761) );
NAND2X1TS U3593 ( .A(DMP_SFG[48]), .B(DmP_mant_SFG_SWR[50]), .Y(n3770) );
INVX2TS U3594 ( .A(n3770), .Y(n2144) );
AOI21X4TS U3595 ( .A0(n3774), .A1(n3771), .B0(n2144), .Y(n3746) );
NOR2X1TS U3596 ( .A(DMP_SFG[49]), .B(DmP_mant_SFG_SWR[51]), .Y(n3740) );
NAND2X1TS U3597 ( .A(DMP_SFG[49]), .B(DmP_mant_SFG_SWR[51]), .Y(n3741) );
NAND2X1TS U3598 ( .A(DMP_SFG[50]), .B(DmP_mant_SFG_SWR[52]), .Y(n3731) );
INVX2TS U3599 ( .A(n3731), .Y(n2145) );
NOR2X1TS U3600 ( .A(DMP_SFG[51]), .B(DmP_mant_SFG_SWR[53]), .Y(n3129) );
NAND2X1TS U3601 ( .A(DMP_SFG[51]), .B(DmP_mant_SFG_SWR[53]), .Y(n3130) );
XNOR2X1TS U3602 ( .A(n4366), .B(DmP_mant_SFG_SWR[54]), .Y(n2146) );
INVX2TS U3603 ( .A(n1926), .Y(n4448) );
BUFX3TS U3604 ( .A(n4448), .Y(n3747) );
NOR2X4TS U3605 ( .A(n3747), .B(OP_FLAG_SFG), .Y(n4174) );
BUFX3TS U3606 ( .A(n4174), .Y(n4367) );
INVX2TS U3607 ( .A(intDX_EWSW[60]), .Y(n2155) );
NAND2X1TS U3608 ( .A(n1992), .B(intDX_EWSW[61]), .Y(n2154) );
OAI211X1TS U3609 ( .A0(intDY_EWSW[60]), .A1(n2155), .B0(n2159), .C0(n2154),
.Y(n2164) );
AOI22X1TS U3610 ( .A0(intDY_EWSW[57]), .A1(n1985), .B0(intDY_EWSW[56]), .B1(
n2149), .Y(n2153) );
INVX2TS U3611 ( .A(intDX_EWSW[58]), .Y(n2151) );
OAI21X1TS U3612 ( .A0(intDY_EWSW[58]), .A1(n2151), .B0(n2150), .Y(n2163) );
OA21XLTS U3613 ( .A0(n2153), .A1(n2163), .B0(n2152), .Y(n2160) );
INVX2TS U3614 ( .A(intDX_EWSW[53]), .Y(n2205) );
NOR2X1TS U3615 ( .A(n2205), .B(intDY_EWSW[53]), .Y(n2162) );
INVX2TS U3616 ( .A(intDX_EWSW[55]), .Y(n2216) );
OAI22X1TS U3617 ( .A0(n2216), .A1(intDY_EWSW[55]), .B0(intDY_EWSW[54]), .B1(
n4529), .Y(n2206) );
NOR2BX1TS U3618 ( .AN(intDX_EWSW[56]), .B(intDY_EWSW[56]), .Y(n2166) );
NOR4X2TS U3619 ( .A(n2166), .B(n2165), .C(n2164), .D(n2163), .Y(n2218) );
NOR2X1TS U3620 ( .A(n4584), .B(intDY_EWSW[49]), .Y(n2209) );
NOR2BX1TS U3621 ( .AN(n2169), .B(intDX_EWSW[46]), .Y(n2181) );
AOI22X1TS U3622 ( .A0(intDY_EWSW[45]), .A1(n1974), .B0(intDY_EWSW[44]), .B1(
n2168), .Y(n2178) );
OAI21X1TS U3623 ( .A0(intDY_EWSW[46]), .A1(n1975), .B0(n2169), .Y(n2177) );
INVX2TS U3624 ( .A(intDY_EWSW[44]), .Y(n2171) );
OAI2BB2XLTS U3625 ( .B0(intDX_EWSW[40]), .B1(n2172), .A0N(intDY_EWSW[41]),
.A1N(n1955), .Y(n2175) );
AOI32X1TS U3626 ( .A0(n2185), .A1(n2175), .A2(n2184), .B0(n2174), .B1(n2185),
.Y(n2176) );
NOR2BX1TS U3627 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2179) );
INVX2TS U3628 ( .A(intDY_EWSW[38]), .Y(n2199) );
NOR2BX1TS U3629 ( .AN(intDX_EWSW[39]), .B(intDY_EWSW[39]), .Y(n2198) );
AOI21X1TS U3630 ( .A0(intDX_EWSW[38]), .A1(n2199), .B0(n2198), .Y(n2197) );
INVX2TS U3631 ( .A(n2300), .Y(n2188) );
INVX2TS U3632 ( .A(n2304), .Y(n2192) );
OAI2BB1X1TS U3633 ( .A0N(n2197), .A1N(n2196), .B0(n2195), .Y(n2203) );
NOR2BX1TS U3634 ( .AN(intDY_EWSW[39]), .B(intDX_EWSW[39]), .Y(n2202) );
NOR3X1TS U3635 ( .A(n2199), .B(n2198), .C(intDX_EWSW[38]), .Y(n2201) );
INVX2TS U3636 ( .A(n2305), .Y(n2200) );
OAI31X1TS U3637 ( .A0(n2203), .A1(n2202), .A2(n2201), .B0(n2200), .Y(n2223)
);
INVX2TS U3638 ( .A(n2208), .Y(n2214) );
AOI22X1TS U3639 ( .A0(intDY_EWSW[49]), .A1(n4584), .B0(intDY_EWSW[48]), .B1(
n2210), .Y(n2213) );
AOI32X1TS U3640 ( .A0(n1956), .A1(n2211), .A2(intDY_EWSW[50]), .B0(
intDY_EWSW[51]), .B1(n1958), .Y(n2212) );
OAI32X1TS U3641 ( .A0(n2215), .A1(n2214), .A2(n2213), .B0(n2212), .B1(n2214),
.Y(n2220) );
OAI2BB2XLTS U3642 ( .B0(intDX_EWSW[54]), .B1(n2217), .A0N(intDY_EWSW[55]),
.A1N(n2216), .Y(n2219) );
OAI31X1TS U3643 ( .A0(n2221), .A1(n2220), .A2(n2219), .B0(n2218), .Y(n2222)
);
OAI221X1TS U3644 ( .A0(n2305), .A1(n2224), .B0(n2303), .B1(n2223), .C0(n2222), .Y(n2308) );
OAI21X1TS U3645 ( .A0(intDY_EWSW[26]), .A1(n1957), .B0(n2228), .Y(n2295) );
AOI22X1TS U3646 ( .A0(n2227), .A1(intDY_EWSW[24]), .B0(intDY_EWSW[25]), .B1(
n1952), .Y(n2230) );
AOI32X1TS U3647 ( .A0(n1957), .A1(n2228), .A2(intDY_EWSW[26]), .B0(
intDY_EWSW[27]), .B1(n1984), .Y(n2229) );
OAI32X1TS U3648 ( .A0(n2295), .A1(n2294), .A2(n2230), .B0(n2229), .B1(n2294),
.Y(n2233) );
INVX2TS U3649 ( .A(intDY_EWSW[5]), .Y(n2245) );
OAI2BB1X1TS U3650 ( .A0N(n2245), .A1N(intDX_EWSW[5]), .B0(intDY_EWSW[4]),
.Y(n2236) );
OAI22X1TS U3651 ( .A0(intDX_EWSW[4]), .A1(n2236), .B0(n2245), .B1(
intDX_EWSW[5]), .Y(n2251) );
INVX2TS U3652 ( .A(intDY_EWSW[7]), .Y(n2247) );
OAI2BB1X1TS U3653 ( .A0N(n2247), .A1N(intDX_EWSW[7]), .B0(intDY_EWSW[6]),
.Y(n2237) );
OAI22X1TS U3654 ( .A0(intDX_EWSW[6]), .A1(n2237), .B0(n2247), .B1(
intDX_EWSW[7]), .Y(n2250) );
INVX2TS U3655 ( .A(intDY_EWSW[1]), .Y(n2239) );
AOI2BB2X1TS U3656 ( .B0(intDX_EWSW[1]), .B1(n2239), .A0N(intDY_EWSW[0]),
.A1N(n2238), .Y(n2240) );
OAI211X1TS U3657 ( .A0(n1949), .A1(intDY_EWSW[3]), .B0(n2241), .C0(n2240),
.Y(n2244) );
INVX2TS U3658 ( .A(intDY_EWSW[6]), .Y(n2246) );
AOI22X1TS U3659 ( .A0(intDX_EWSW[7]), .A1(n2247), .B0(intDX_EWSW[6]), .B1(
n2246), .Y(n2248) );
OAI32X1TS U3660 ( .A0(n2251), .A1(n2250), .A2(n2249), .B0(n2248), .B1(n2250),
.Y(n2257) );
OA22X1TS U3661 ( .A0(n1969), .A1(intDY_EWSW[14]), .B0(n1951), .B1(
intDY_EWSW[15]), .Y(n2272) );
INVX2TS U3662 ( .A(intDY_EWSW[10]), .Y(n2253) );
AOI21X1TS U3663 ( .A0(intDX_EWSW[10]), .A1(n2253), .B0(n2259), .Y(n2264) );
AOI22X1TS U3664 ( .A0(intDY_EWSW[11]), .A1(n1989), .B0(intDY_EWSW[10]), .B1(
n2260), .Y(n2267) );
AOI21X1TS U3665 ( .A0(n2263), .A1(n2262), .B0(n2266), .Y(n2265) );
OAI2BB2XLTS U3666 ( .B0(intDX_EWSW[14]), .B1(n2268), .A0N(intDY_EWSW[15]),
.A1N(n1951), .Y(n2269) );
INVX2TS U3667 ( .A(intDY_EWSW[16]), .Y(n2273) );
NOR2X1TS U3668 ( .A(n1983), .B(intDY_EWSW[17]), .Y(n2280) );
OAI21X1TS U3669 ( .A0(intDY_EWSW[18]), .A1(n1990), .B0(n2282), .Y(n2286) );
AOI22X1TS U3670 ( .A0(n2281), .A1(intDY_EWSW[16]), .B0(intDY_EWSW[17]), .B1(
n1983), .Y(n2284) );
AOI32X1TS U3671 ( .A0(n1990), .A1(n2282), .A2(intDY_EWSW[18]), .B0(
intDY_EWSW[19]), .B1(n1980), .Y(n2283) );
OAI32X1TS U3672 ( .A0(n2286), .A1(n2285), .A2(n2284), .B0(n2283), .B1(n2285),
.Y(n2289) );
AOI211X1TS U3673 ( .A0(n2291), .A1(n2290), .B0(n2289), .C0(n2288), .Y(n2297)
);
NOR2BX1TS U3674 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n2293) );
OR4X2TS U3675 ( .A(n2295), .B(n2294), .C(n2293), .D(n2292), .Y(n2296) );
AOI32X1TS U3676 ( .A0(n2299), .A1(n2298), .A2(n2297), .B0(n2296), .B1(n2299),
.Y(n2306) );
NOR2BX4TS U3677 ( .AN(n2306), .B(n1982), .Y(n2307) );
NOR3BX4TS U3678 ( .AN(n2309), .B(n2308), .C(n2307), .Y(n2311) );
BUFX3TS U3679 ( .A(n2928), .Y(n4432) );
BUFX3TS U3680 ( .A(n2928), .Y(n3110) );
AOI22X1TS U3681 ( .A0(intDX_EWSW[7]), .A1(n3144), .B0(DMP_EXP_EWSW[7]), .B1(
n3110), .Y(n2312) );
AOI22X1TS U3682 ( .A0(intDX_EWSW[5]), .A1(n3144), .B0(DMP_EXP_EWSW[5]), .B1(
n3110), .Y(n2313) );
CLKBUFX2TS U3683 ( .A(n2928), .Y(n2907) );
BUFX3TS U3684 ( .A(n2907), .Y(n3077) );
AOI22X1TS U3685 ( .A0(intDX_EWSW[29]), .A1(n3078), .B0(DmP_EXP_EWSW[29]),
.B1(n3077), .Y(n2315) );
BUFX3TS U3686 ( .A(n2907), .Y(n4397) );
AOI22X1TS U3687 ( .A0(intDX_EWSW[46]), .A1(n3090), .B0(DmP_EXP_EWSW[46]),
.B1(n4397), .Y(n2316) );
AOI22X1TS U3688 ( .A0(intDX_EWSW[47]), .A1(n3090), .B0(DmP_EXP_EWSW[47]),
.B1(n4397), .Y(n2317) );
AOI22X1TS U3689 ( .A0(intDX_EWSW[51]), .A1(n3090), .B0(DmP_EXP_EWSW[51]),
.B1(n4397), .Y(n2318) );
NOR2X1TS U3690 ( .A(n4534), .B(shift_value_SHT2_EWR[5]), .Y(n2392) );
INVX2TS U3691 ( .A(n2392), .Y(n2398) );
INVX2TS U3692 ( .A(n2398), .Y(n4296) );
NOR2X2TS U3693 ( .A(n4506), .B(shift_value_SHT2_EWR[2]), .Y(n2939) );
BUFX3TS U3694 ( .A(n2939), .Y(n3652) );
NOR2X2TS U3695 ( .A(n4570), .B(shift_value_SHT2_EWR[3]), .Y(n2938) );
INVX2TS U3696 ( .A(n2938), .Y(n2658) );
AOI22X1TS U3697 ( .A0(n3652), .A1(Data_array_SWR[25]), .B0(n2869), .B1(
Data_array_SWR[21]), .Y(n2320) );
AOI22X1TS U3698 ( .A0(n2405), .A1(Data_array_SWR[29]), .B0(n2870), .B1(
Data_array_SWR[17]), .Y(n2319) );
NAND2X1TS U3699 ( .A(n2320), .B(n2319), .Y(n2843) );
BUFX3TS U3700 ( .A(n2939), .Y(n2958) );
AOI22X1TS U3701 ( .A0(n2405), .A1(Data_array_SWR[44]), .B0(n2958), .B1(
Data_array_SWR[40]), .Y(n2322) );
AOI22X1TS U3702 ( .A0(n3651), .A1(Data_array_SWR[36]), .B0(n2870), .B1(
Data_array_SWR[33]), .Y(n2321) );
INVX2TS U3703 ( .A(n2393), .Y(n3023) );
INVX2TS U3704 ( .A(n2323), .Y(n4298) );
AOI22X1TS U3705 ( .A0(n1922), .A1(Data_array_SWR[9]), .B0(n1924), .B1(
Data_array_SWR[1]), .Y(n2325) );
BUFX3TS U3706 ( .A(n2405), .Y(n2976) );
NAND2X1TS U3707 ( .A(n4298), .B(n2976), .Y(n3008) );
INVX2TS U3708 ( .A(n2323), .Y(n3649) );
NAND2X1TS U3709 ( .A(n3649), .B(n2981), .Y(n2988) );
AOI22X1TS U3710 ( .A0(n3657), .A1(Data_array_SWR[13]), .B0(n1920), .B1(
Data_array_SWR[5]), .Y(n2324) );
NAND2X1TS U3711 ( .A(n2981), .B(Data_array_SWR[52]), .Y(n2327) );
NAND2X1TS U3712 ( .A(n2982), .B(Data_array_SWR[48]), .Y(n2326) );
NAND3X2TS U3713 ( .A(n2327), .B(n2326), .C(n2645), .Y(n4307) );
INVX2TS U3714 ( .A(n4307), .Y(n2839) );
NOR2BX1TS U3715 ( .AN(LZD_output_NRM2_EW[5]), .B(ADD_OVRFLW_NRM2), .Y(n2330)
);
XOR2X1TS U3716 ( .A(n1918), .B(n2330), .Y(n2348) );
NOR2BX1TS U3717 ( .AN(LZD_output_NRM2_EW[4]), .B(ADD_OVRFLW_NRM2), .Y(n2331)
);
XOR2X1TS U3718 ( .A(n1918), .B(n2331), .Y(n2343) );
NOR2BX1TS U3719 ( .AN(LZD_output_NRM2_EW[3]), .B(ADD_OVRFLW_NRM2), .Y(n2332)
);
XOR2X1TS U3720 ( .A(DP_OP_15J18_122_2221_n35), .B(n2332), .Y(n2345) );
CLKXOR2X2TS U3721 ( .A(DP_OP_15J18_122_2221_n35), .B(n2334), .Y(n2341) );
XNOR2X4TS U3722 ( .A(n2336), .B(ADD_OVRFLW_NRM2), .Y(n2368) );
AFHCONX2TS U3723 ( .A(DMP_exp_NRM2_EW[2]), .B(n2338), .CI(n2337), .CON(n2344), .S(n2357) );
AFHCONX2TS U3724 ( .A(n1940), .B(DP_OP_15J18_122_2221_n35), .CI(n2339),
.CON(n2340), .S(n2447) );
AFHCINX2TS U3725 ( .CIN(n2340), .B(n2341), .A(DMP_exp_NRM2_EW[1]), .S(n2448),
.CO(n2337) );
NAND2X4TS U3726 ( .A(n2368), .B(n2351), .Y(n2352) );
ADDFHX2TS U3727 ( .A(n1918), .B(DMP_exp_NRM2_EW[10]), .CI(n2353), .CO(n2336),
.S(n3691) );
AFHCINX2TS U3728 ( .CIN(n2354), .B(n1918), .A(DMP_exp_NRM2_EW[9]), .S(n2606),
.CO(n2353) );
AFHCONX2TS U3729 ( .A(DMP_exp_NRM2_EW[8]), .B(n1918), .CI(n2355), .CON(n2354), .S(n2449) );
INVX2TS U3730 ( .A(n2356), .Y(n4387) );
INVX2TS U3731 ( .A(n2357), .Y(n4386) );
AFHCINX2TS U3732 ( .CIN(n2360), .B(n1918), .A(DMP_exp_NRM2_EW[7]), .S(n2361),
.CO(n2355) );
INVX2TS U3733 ( .A(n2361), .Y(n4389) );
AFHCONX2TS U3734 ( .A(DMP_exp_NRM2_EW[6]), .B(n1918), .CI(n2362), .CON(n2360), .S(n2363) );
INVX2TS U3735 ( .A(n2363), .Y(n4388) );
NAND4BX1TS U3736 ( .AN(n2449), .B(n2364), .C(n4389), .D(n4388), .Y(n2365) );
NAND2BX2TS U3737 ( .AN(n3691), .B(n2366), .Y(n2367) );
NAND2X4TS U3738 ( .A(n4390), .B(n1928), .Y(n3039) );
INVX2TS U3739 ( .A(n2866), .Y(n3653) );
OR2X2TS U3740 ( .A(n3653), .B(bit_shift_SHT2), .Y(n2865) );
NOR2X1TS U3741 ( .A(n3649), .B(n4612), .Y(n2369) );
BUFX3TS U3742 ( .A(n2369), .Y(n3648) );
INVX2TS U3743 ( .A(n3648), .Y(n2882) );
AOI22X1TS U3744 ( .A0(n2950), .A1(n2730), .B0(final_result_ieee[51]), .B1(
n3697), .Y(n2370) );
INVX2TS U3745 ( .A(n2374), .Y(n2377) );
INVX2TS U3746 ( .A(n2375), .Y(n2376) );
INVX2TS U3747 ( .A(n3971), .Y(n3945) );
NAND2X1TS U3748 ( .A(n2382), .B(n2381), .Y(n2385) );
XNOR2X1TS U3749 ( .A(n2383), .B(n2385), .Y(n2389) );
INVX2TS U3750 ( .A(n2385), .Y(n2386) );
XOR2X1TS U3751 ( .A(n3781), .B(n2386), .Y(n2387) );
BUFX3TS U3752 ( .A(n3979), .Y(n4275) );
AOI22X1TS U3753 ( .A0(n2387), .A1(n4275), .B0(Raw_mant_NRM_SWR[33]), .B1(
n3747), .Y(n2388) );
NAND2X2TS U3754 ( .A(n3649), .B(n3689), .Y(n4340) );
INVX2TS U3755 ( .A(n4325), .Y(n4338) );
AOI22X1TS U3756 ( .A0(n2982), .A1(Data_array_SWR[36]), .B0(n2958), .B1(
Data_array_SWR[44]), .Y(n2391) );
AOI22X1TS U3757 ( .A0(n2981), .A1(Data_array_SWR[40]), .B0(n2405), .B1(
Data_array_SWR[48]), .Y(n2390) );
NAND2X2TS U3758 ( .A(n2391), .B(n2390), .Y(n4308) );
INVX2TS U3759 ( .A(n2392), .Y(n3659) );
NOR2X4TS U3760 ( .A(n3689), .B(n2398), .Y(n4316) );
INVX2TS U3761 ( .A(n4316), .Y(n4329) );
NAND2X2TS U3762 ( .A(n3664), .B(n1927), .Y(n4333) );
NOR2X4TS U3763 ( .A(n1929), .B(n3659), .Y(n4318) );
INVX2TS U3764 ( .A(n4318), .Y(n4331) );
OAI22X1TS U3765 ( .A0(n2839), .A1(n4333), .B0(n4314), .B1(n4331), .Y(n2394)
);
OAI2BB1X1TS U3766 ( .A0N(n1938), .A1N(n2843), .B0(n2396), .Y(n4328) );
BUFX3TS U3767 ( .A(n2955), .Y(n4377) );
AOI22X1TS U3768 ( .A0(n1933), .A1(Data_array_SWR[25]), .B0(n1924), .B1(
Data_array_SWR[13]), .Y(n2404) );
AOI22X1TS U3769 ( .A0(n1922), .A1(Data_array_SWR[21]), .B0(n1919), .B1(
Data_array_SWR[17]), .Y(n2403) );
INVX2TS U3770 ( .A(n3659), .Y(n3022) );
AOI22X1TS U3771 ( .A0(n2976), .A1(Data_array_SWR[40]), .B0(n2981), .B1(
Data_array_SWR[33]), .Y(n2400) );
BUFX3TS U3772 ( .A(n2939), .Y(n2833) );
AOI22X1TS U3773 ( .A0(n2833), .A1(Data_array_SWR[36]), .B0(n2959), .B1(
Data_array_SWR[29]), .Y(n2399) );
NAND2X1TS U3774 ( .A(n2400), .B(n2399), .Y(n2998) );
AOI22X1TS U3775 ( .A0(n2833), .A1(Data_array_SWR[52]), .B0(n2870), .B1(
Data_array_SWR[44]), .Y(n2401) );
NAND2X1TS U3776 ( .A(n2976), .B(bit_shift_SHT2), .Y(n2986) );
AOI22X1TS U3777 ( .A0(n4296), .A1(n2998), .B0(n3023), .B1(n3000), .Y(n2402)
);
BUFX3TS U3778 ( .A(n2405), .Y(n3654) );
AOI22X1TS U3779 ( .A0(n3654), .A1(Data_array_SWR[52]), .B0(n2869), .B1(
Data_array_SWR[44]), .Y(n2407) );
AOI22X1TS U3780 ( .A0(n2833), .A1(Data_array_SWR[48]), .B0(n2870), .B1(
Data_array_SWR[40]), .Y(n2406) );
NAND2X1TS U3781 ( .A(n2407), .B(n2406), .Y(n3672) );
AOI22X1TS U3782 ( .A0(n1929), .A1(n3675), .B0(n4323), .B1(n3672), .Y(n2408)
);
NAND2X2TS U3783 ( .A(n3648), .B(n1927), .Y(n2665) );
NAND2X1TS U3784 ( .A(n2408), .B(n2665), .Y(n4280) );
OAI21X1TS U3785 ( .A0(n4173), .A1(n2411), .B0(n2410), .Y(n4101) );
INVX2TS U3786 ( .A(n4101), .Y(n4188) );
INVX2TS U3787 ( .A(n2412), .Y(n2415) );
INVX2TS U3788 ( .A(n2413), .Y(n2414) );
OAI21X1TS U3789 ( .A0(n4188), .A1(n2415), .B0(n2414), .Y(n4089) );
AOI21X1TS U3790 ( .A0(n4089), .A1(n4085), .B0(n2417), .Y(n2421) );
INVX2TS U3791 ( .A(n2418), .Y(n2420) );
NAND2X1TS U3792 ( .A(n2420), .B(n2419), .Y(n2423) );
INVX2TS U3793 ( .A(n2423), .Y(n2424) );
XNOR2X1TS U3794 ( .A(n4011), .B(n2424), .Y(n2425) );
BUFX3TS U3795 ( .A(n4448), .Y(n4090) );
AOI22X1TS U3796 ( .A0(n2425), .A1(n4275), .B0(Raw_mant_NRM_SWR[17]), .B1(
n4090), .Y(n2426) );
OAI2BB1X1TS U3797 ( .A0N(n4174), .A1N(n2427), .B0(n2426), .Y(n1252) );
INVX2TS U3798 ( .A(n2428), .Y(n2431) );
INVX2TS U3799 ( .A(n2429), .Y(n2430) );
AOI21X1TS U3800 ( .A0(n4027), .A1(n2431), .B0(n2430), .Y(n4055) );
INVX2TS U3801 ( .A(n4055), .Y(n3990) );
AOI21X1TS U3802 ( .A0(n3990), .A1(n2433), .B0(n2432), .Y(n4044) );
NAND2X1TS U3803 ( .A(n2436), .B(n2435), .Y(n2440) );
XNOR2X1TS U3804 ( .A(n2437), .B(n2440), .Y(n2444) );
INVX2TS U3805 ( .A(n3929), .Y(n3951) );
INVX2TS U3806 ( .A(n2440), .Y(n2441) );
XNOR2X1TS U3807 ( .A(n3951), .B(n2441), .Y(n2442) );
AOI22X1TS U3808 ( .A0(n2442), .A1(n4275), .B0(Raw_mant_NRM_SWR[25]), .B1(
n4090), .Y(n2443) );
OAI2BB1X1TS U3809 ( .A0N(n4174), .A1N(n2444), .B0(n2443), .Y(n1244) );
OA22X1TS U3810 ( .A0(n3693), .A1(n2445), .B0(n4675), .B1(
final_result_ieee[56]), .Y(n1682) );
OA22X1TS U3811 ( .A0(n3693), .A1(n2446), .B0(n4675), .B1(
final_result_ieee[57]), .Y(n1681) );
OA22X1TS U3812 ( .A0(n3693), .A1(n2447), .B0(n4675), .B1(
final_result_ieee[52]), .Y(n1686) );
OA22X1TS U3813 ( .A0(n3693), .A1(n2448), .B0(n4675), .B1(
final_result_ieee[53]), .Y(n1685) );
OA22X1TS U3814 ( .A0(n3693), .A1(n2449), .B0(n4675), .B1(
final_result_ieee[60]), .Y(n1678) );
INVX2TS U3815 ( .A(n2740), .Y(n2450) );
NOR2X2TS U3816 ( .A(Raw_mant_NRM_SWR[52]), .B(Raw_mant_NRM_SWR[51]), .Y(
n2512) );
NOR2X6TS U3817 ( .A(n2450), .B(n2739), .Y(n2758) );
NOR2X2TS U3818 ( .A(Raw_mant_NRM_SWR[40]), .B(Raw_mant_NRM_SWR[39]), .Y(
n2504) );
NOR3X1TS U3819 ( .A(Raw_mant_NRM_SWR[42]), .B(Raw_mant_NRM_SWR[36]), .C(
Raw_mant_NRM_SWR[43]), .Y(n2451) );
NAND2X1TS U3820 ( .A(n2504), .B(n2451), .Y(n2455) );
NOR2X1TS U3821 ( .A(Raw_mant_NRM_SWR[45]), .B(Raw_mant_NRM_SWR[44]), .Y(
n2452) );
NAND2X2TS U3822 ( .A(n4552), .B(n2452), .Y(n2757) );
NOR2X1TS U3823 ( .A(Raw_mant_NRM_SWR[41]), .B(Raw_mant_NRM_SWR[47]), .Y(
n2453) );
NOR2X2TS U3824 ( .A(Raw_mant_NRM_SWR[38]), .B(Raw_mant_NRM_SWR[37]), .Y(
n2791) );
NAND2X2TS U3825 ( .A(n2453), .B(n2791), .Y(n2454) );
NOR3X2TS U3826 ( .A(n2455), .B(n2757), .C(n2454), .Y(n2456) );
NAND2X4TS U3827 ( .A(n2758), .B(n2456), .Y(n2529) );
NOR2X1TS U3828 ( .A(Raw_mant_NRM_SWR[35]), .B(Raw_mant_NRM_SWR[34]), .Y(
n2458) );
NOR2X1TS U3829 ( .A(Raw_mant_NRM_SWR[32]), .B(Raw_mant_NRM_SWR[33]), .Y(
n2457) );
NAND2X1TS U3830 ( .A(n2458), .B(n2457), .Y(n2459) );
NOR2X6TS U3831 ( .A(n2529), .B(n2459), .Y(n2496) );
NOR2X1TS U3832 ( .A(Raw_mant_NRM_SWR[29]), .B(Raw_mant_NRM_SWR[28]), .Y(
n2495) );
NOR2X1TS U3833 ( .A(Raw_mant_NRM_SWR[31]), .B(Raw_mant_NRM_SWR[26]), .Y(
n2460) );
NAND2X1TS U3834 ( .A(n2495), .B(n2460), .Y(n2461) );
NOR3X1TS U3835 ( .A(n2461), .B(Raw_mant_NRM_SWR[30]), .C(
Raw_mant_NRM_SWR[27]), .Y(n2462) );
NAND2X4TS U3836 ( .A(n2496), .B(n2462), .Y(n2794) );
NOR2X6TS U3837 ( .A(n2794), .B(Raw_mant_NRM_SWR[25]), .Y(n2762) );
NAND2X1TS U3838 ( .A(n2464), .B(n2463), .Y(n2467) );
NOR2X1TS U3839 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[18]), .Y(
n2770) );
NAND2X1TS U3840 ( .A(n2770), .B(n2465), .Y(n2466) );
NOR2X1TS U3841 ( .A(n2467), .B(n2466), .Y(n2468) );
NAND2X4TS U3842 ( .A(n2762), .B(n2468), .Y(n2517) );
NOR2X4TS U3843 ( .A(n2517), .B(n1977), .Y(n2472) );
NOR2X4TS U3844 ( .A(n2774), .B(Raw_mant_NRM_SWR[13]), .Y(n2755) );
NOR2X2TS U3845 ( .A(Raw_mant_NRM_SWR[12]), .B(Raw_mant_NRM_SWR[11]), .Y(
n2754) );
INVX2TS U3846 ( .A(n2754), .Y(n2469) );
NOR2X1TS U3847 ( .A(n2469), .B(Raw_mant_NRM_SWR[10]), .Y(n2470) );
NAND2X2TS U3848 ( .A(n2755), .B(n2470), .Y(n2783) );
NOR2X1TS U3849 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[7]), .Y(n2474)
);
NOR2X1TS U3850 ( .A(n2783), .B(n2471), .Y(n2483) );
INVX2TS U3851 ( .A(n2755), .Y(n2481) );
INVX2TS U3852 ( .A(n2472), .Y(n2747) );
NOR2X4TS U3853 ( .A(n2747), .B(n2476), .Y(n2733) );
INVX2TS U3854 ( .A(n2772), .Y(n2477) );
NOR2X1TS U3855 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .Y(n2484)
);
INVX2TS U3856 ( .A(n2517), .Y(n2478) );
AOI22X1TS U3857 ( .A0(n2733), .A1(n2479), .B0(n2478), .B1(
Raw_mant_NRM_SWR[15]), .Y(n2480) );
OAI21X1TS U3858 ( .A0(n2481), .A1(n2754), .B0(n2480), .Y(n2482) );
NOR2X2TS U3859 ( .A(n2483), .B(n2482), .Y(n2781) );
INVX4TS U3860 ( .A(n2733), .Y(n2771) );
NAND2X1TS U3861 ( .A(n2772), .B(n2484), .Y(n2485) );
NOR2X4TS U3862 ( .A(n2771), .B(n2485), .Y(n2804) );
NOR3X1TS U3863 ( .A(Raw_mant_NRM_SWR[2]), .B(n4587), .C(Raw_mant_NRM_SWR[1]),
.Y(n2486) );
NAND2X2TS U3864 ( .A(n2804), .B(n2486), .Y(n2779) );
INVX2TS U3865 ( .A(n2762), .Y(n2488) );
NOR2X4TS U3866 ( .A(n2488), .B(n2487), .Y(n2744) );
NOR2X1TS U3867 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[22]), .Y(
n2489) );
INVX2TS U3868 ( .A(n2536), .Y(n2490) );
NAND2X1TS U3869 ( .A(n2762), .B(Raw_mant_NRM_SWR[24]), .Y(n2491) );
AND2X2TS U3870 ( .A(n2549), .B(n2491), .Y(n2765) );
NOR3X1TS U3871 ( .A(n2757), .B(Raw_mant_NRM_SWR[47]), .C(
Raw_mant_NRM_SWR[43]), .Y(n2492) );
NAND2X1TS U3872 ( .A(n2758), .B(n2492), .Y(n2737) );
NOR2X2TS U3873 ( .A(n2737), .B(Raw_mant_NRM_SWR[42]), .Y(n2546) );
NAND2X1TS U3874 ( .A(n2546), .B(n2504), .Y(n2790) );
INVX2TS U3875 ( .A(n2791), .Y(n2494) );
NOR3X1TS U3876 ( .A(n2790), .B(n2494), .C(n2493), .Y(n2500) );
NAND2X2TS U3877 ( .A(n2496), .B(n4510), .Y(n2793) );
NOR2X2TS U3878 ( .A(n2793), .B(Raw_mant_NRM_SWR[30]), .Y(n2503) );
NAND2X1TS U3879 ( .A(n2503), .B(n2495), .Y(n2756) );
OA22X2TS U3880 ( .A0(n2756), .A1(n4580), .B0(n4510), .B1(n2497), .Y(n2550)
);
NOR2X1TS U3881 ( .A(n2787), .B(Raw_mant_NRM_SWR[34]), .Y(n2551) );
NAND2X1TS U3882 ( .A(n2762), .B(Raw_mant_NRM_SWR[23]), .Y(n2498) );
NAND4BX1TS U3883 ( .AN(n2500), .B(n2550), .C(n2499), .D(n2498), .Y(n2501) );
NOR2X1TS U3884 ( .A(n2536), .B(n1994), .Y(n2734) );
NOR2X1TS U3885 ( .A(n2501), .B(n2734), .Y(n2502) );
NAND3X2TS U3886 ( .A(n2779), .B(n2765), .C(n2502), .Y(n2801) );
INVX2TS U3887 ( .A(n2503), .Y(n2553) );
NOR2X1TS U3888 ( .A(n2553), .B(n4611), .Y(n2743) );
INVX2TS U3889 ( .A(n2504), .Y(n2505) );
NOR3X1TS U3890 ( .A(n2757), .B(Raw_mant_NRM_SWR[47]), .C(n4589), .Y(n2506)
);
NAND2X1TS U3891 ( .A(n2758), .B(n2506), .Y(n2523) );
OAI2BB1X1TS U3892 ( .A0N(n2512), .A1N(n2511), .B0(n2510), .Y(n2513) );
AOI21X1TS U3893 ( .A0(n2743), .A1(n4593), .B0(n2515), .Y(n2516) );
OAI21X1TS U3894 ( .A0(n2517), .A1(n4615), .B0(n2516), .Y(n2518) );
NAND2X2TS U3895 ( .A(n2781), .B(n2519), .Y(n4372) );
NAND2X4TS U3896 ( .A(n4372), .B(n3380), .Y(n2694) );
NAND2X1TS U3897 ( .A(n3382), .B(Shift_amount_SHT1_EWR[1]), .Y(n2691) );
BUFX3TS U3898 ( .A(n4674), .Y(n4475) );
INVX4TS U3899 ( .A(n4475), .Y(n3704) );
AOI21X4TS U3900 ( .A0(n2694), .A1(n2691), .B0(n3611), .Y(n3176) );
NOR2X1TS U3901 ( .A(n2794), .B(n4585), .Y(n2797) );
NAND2X1TS U3902 ( .A(n4586), .B(Raw_mant_NRM_SWR[23]), .Y(n2522) );
INVX2TS U3903 ( .A(n2523), .Y(n2524) );
NOR3X1TS U3904 ( .A(n2797), .B(n2525), .C(n2524), .Y(n2526) );
OA21X2TS U3905 ( .A0(n2783), .A1(n2527), .B0(n2526), .Y(n2767) );
NOR2X1TS U3906 ( .A(Raw_mant_NRM_SWR[2]), .B(n4571), .Y(n2528) );
NAND2X2TS U3907 ( .A(n2804), .B(n2528), .Y(n2799) );
CLKINVX1TS U3908 ( .A(n2529), .Y(n2788) );
NAND2X1TS U3909 ( .A(n4552), .B(Raw_mant_NRM_SWR[45]), .Y(n2532) );
AOI21X1TS U3910 ( .A0(n2530), .A1(n4523), .B0(Raw_mant_NRM_SWR[53]), .Y(
n2531) );
OAI22X1TS U3911 ( .A0(n2533), .A1(n2532), .B0(Raw_mant_NRM_SWR[54]), .B1(
n2531), .Y(n2534) );
AOI21X1TS U3912 ( .A0(n2788), .A1(Raw_mant_NRM_SWR[35]), .B0(n2534), .Y(
n2541) );
NAND3X1TS U3913 ( .A(n2778), .B(n4591), .C(n2537), .Y(n2540) );
INVX2TS U3914 ( .A(n2790), .Y(n2538) );
NAND4X1TS U3915 ( .A(n2799), .B(n2541), .C(n2540), .D(n2539), .Y(n2561) );
INVX2TS U3916 ( .A(n2744), .Y(n2544) );
NAND2X1TS U3917 ( .A(n4577), .B(Raw_mant_NRM_SWR[21]), .Y(n2543) );
NOR2X1TS U3918 ( .A(n2544), .B(n2543), .Y(n2796) );
AOI21X1TS U3919 ( .A0(n2546), .A1(n2545), .B0(n2796), .Y(n2547) );
OA21X2TS U3920 ( .A0(n2771), .A1(n2548), .B0(n2547), .Y(n2764) );
INVX2TS U3921 ( .A(n2549), .Y(n2557) );
INVX2TS U3922 ( .A(n2550), .Y(n2555) );
AOI22X1TS U3923 ( .A0(n2551), .A1(Raw_mant_NRM_SWR[33]), .B0(
Raw_mant_NRM_SWR[47]), .B1(n2758), .Y(n2552) );
AOI21X1TS U3924 ( .A0(n2557), .A1(n1994), .B0(n2556), .Y(n2560) );
INVX2TS U3925 ( .A(n2774), .Y(n2558) );
NAND2X1TS U3926 ( .A(n2558), .B(Raw_mant_NRM_SWR[13]), .Y(n2773) );
NAND4X2TS U3927 ( .A(n2764), .B(n2560), .C(n2773), .D(n2559), .Y(n2748) );
NOR2X2TS U3928 ( .A(n2561), .B(n2748), .Y(n2562) );
NAND2X2TS U3929 ( .A(n2767), .B(n2562), .Y(n2563) );
BUFX3TS U3930 ( .A(Shift_reg_FLAGS_7[1]), .Y(n4369) );
NAND2X1TS U3931 ( .A(n4468), .B(ADD_OVRFLW_NRM), .Y(n2565) );
INVX2TS U3932 ( .A(n2565), .Y(n3322) );
CLKBUFX2TS U3933 ( .A(n3322), .Y(n3381) );
AOI21X1TS U3934 ( .A0(Shift_amount_SHT1_EWR[0]), .A1(n4374), .B0(n3381), .Y(
n2564) );
AND2X8TS U3935 ( .A(n4373), .B(n2564), .Y(n3174) );
OAI22X1TS U3936 ( .A0(n2520), .A1(n4523), .B0(n4369), .B1(n4665), .Y(n2567)
);
INVX2TS U3937 ( .A(n2565), .Y(n3357) );
INVX2TS U3938 ( .A(n3357), .Y(n3365) );
INVX2TS U3939 ( .A(n3156), .Y(n2572) );
NAND2X4TS U3940 ( .A(n3176), .B(n2695), .Y(n3616) );
OAI22X1TS U3941 ( .A0(n2520), .A1(n4522), .B0(n4369), .B1(n4664), .Y(n2569)
);
NOR2X1TS U3942 ( .A(n3365), .B(n4576), .Y(n2568) );
NOR2X2TS U3943 ( .A(n2569), .B(n2568), .Y(n3233) );
CLKBUFX2TS U3944 ( .A(n2520), .Y(n3201) );
INVX2TS U3945 ( .A(n3201), .Y(n2785) );
AOI22X1TS U3946 ( .A0(n2785), .A1(Raw_mant_NRM_SWR[53]), .B0(n3322), .B1(
Raw_mant_NRM_SWR[1]), .Y(n3157) );
AOI22X1TS U3947 ( .A0(Raw_mant_NRM_SWR[54]), .A1(n3308), .B0(n3439), .B1(
Data_array_SWR[0]), .Y(n2570) );
NOR2X2TS U3948 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n4567), .Y(n4396) );
OAI21XLTS U3949 ( .A0(n4396), .A1(n2573), .B0(n4394), .Y(n1891) );
INVX2TS U3950 ( .A(n2576), .Y(n2577) );
OAI21X1TS U3951 ( .A0(n3849), .A1(n2578), .B0(n2577), .Y(n3886) );
AOI21X1TS U3952 ( .A0(n3886), .A1(n3882), .B0(n2580), .Y(n2584) );
NAND2X1TS U3953 ( .A(n2583), .B(n2582), .Y(n2587) );
INVX2TS U3954 ( .A(n2587), .Y(n2588) );
XNOR2X1TS U3955 ( .A(n2589), .B(n2588), .Y(n2590) );
BUFX3TS U3956 ( .A(n4448), .Y(n3974) );
AOI22X1TS U3957 ( .A0(n2590), .A1(n4275), .B0(Raw_mant_NRM_SWR[43]), .B1(
n3974), .Y(n2591) );
OAI2BB1X1TS U3958 ( .A0N(n4174), .A1N(n2592), .B0(n2591), .Y(n1226) );
INVX2TS U3959 ( .A(n2593), .Y(n2596) );
OAI21X1TS U3960 ( .A0(n3781), .A1(n2596), .B0(n2595), .Y(n3904) );
NAND2X1TS U3961 ( .A(n2599), .B(n2598), .Y(n2601) );
INVX2TS U3962 ( .A(n2601), .Y(n2600) );
XNOR2X1TS U3963 ( .A(n3904), .B(n2600), .Y(n2605) );
XNOR2X1TS U3964 ( .A(n2602), .B(n2601), .Y(n2603) );
AOI22X1TS U3965 ( .A0(n2603), .A1(n4367), .B0(Raw_mant_NRM_SWR[35]), .B1(
n3747), .Y(n2604) );
OAI2BB1X1TS U3966 ( .A0N(n3979), .A1N(n2605), .B0(n2604), .Y(n1234) );
OA22X1TS U3967 ( .A0(n3693), .A1(n2606), .B0(n4675), .B1(
final_result_ieee[61]), .Y(n1677) );
AOI22X1TS U3968 ( .A0(n1933), .A1(Data_array_SWR[27]), .B0(n1924), .B1(
Data_array_SWR[15]), .Y(n2612) );
AOI22X1TS U3969 ( .A0(n1922), .A1(Data_array_SWR[23]), .B0(n1919), .B1(
Data_array_SWR[19]), .Y(n2611) );
AOI22X1TS U3970 ( .A0(n3654), .A1(Data_array_SWR[42]), .B0(n2981), .B1(
Data_array_SWR[34]), .Y(n2608) );
AOI22X1TS U3971 ( .A0(n2833), .A1(Data_array_SWR[38]), .B0(n2959), .B1(
Data_array_SWR[31]), .Y(n2607) );
NAND2X1TS U3972 ( .A(n2608), .B(n2607), .Y(n2947) );
NAND2X1TS U3973 ( .A(n3651), .B(Data_array_SWR[50]), .Y(n2609) );
AOI22X1TS U3974 ( .A0(n3022), .A1(n2947), .B0(n3023), .B1(n2949), .Y(n2610)
);
AOI22X1TS U3975 ( .A0(n3654), .A1(Data_array_SWR[50]), .B0(n3651), .B1(n1946), .Y(n2614) );
AOI22X1TS U3976 ( .A0(n3652), .A1(Data_array_SWR[46]), .B0(n2870), .B1(n1944), .Y(n2613) );
NAND2X1TS U3977 ( .A(n2614), .B(n2613), .Y(n3685) );
AOI22X1TS U3978 ( .A0(n1928), .A1(n3690), .B0(n4323), .B1(n3685), .Y(n2615)
);
NAND2X1TS U3979 ( .A(n2615), .B(n2665), .Y(n4282) );
BUFX3TS U3980 ( .A(n2955), .Y(n4383) );
AOI22X1TS U3981 ( .A0(n1934), .A1(Data_array_SWR[26]), .B0(n1924), .B1(
Data_array_SWR[14]), .Y(n2621) );
AOI22X1TS U3982 ( .A0(Data_array_SWR[22]), .A1(n1922), .B0(n1919), .B1(
Data_array_SWR[18]), .Y(n2620) );
AOI22X1TS U3983 ( .A0(n3654), .A1(Data_array_SWR[41]), .B0(n2981), .B1(n1937), .Y(n2617) );
AOI22X1TS U3984 ( .A0(n2833), .A1(Data_array_SWR[37]), .B0(n2959), .B1(
Data_array_SWR[30]), .Y(n2616) );
NAND2X1TS U3985 ( .A(n2617), .B(n2616), .Y(n2969) );
AOI22X1TS U3986 ( .A0(Data_array_SWR[53]), .A1(n2958), .B0(n2870), .B1(
Data_array_SWR[45]), .Y(n2618) );
AOI22X1TS U3987 ( .A0(n4296), .A1(n2969), .B0(n3664), .B1(n2971), .Y(n2619)
);
AOI22X1TS U3988 ( .A0(n3654), .A1(Data_array_SWR[51]), .B0(n2869), .B1(
Data_array_SWR[43]), .Y(n2623) );
AOI22X1TS U3989 ( .A0(n2833), .A1(Data_array_SWR[47]), .B0(n2870), .B1(
Data_array_SWR[39]), .Y(n2622) );
NAND2X1TS U3990 ( .A(n2623), .B(n2622), .Y(n3681) );
AOI22X1TS U3991 ( .A0(n1929), .A1(n3684), .B0(n4323), .B1(n3681), .Y(n2624)
);
NAND2X1TS U3992 ( .A(n2624), .B(n2665), .Y(n4281) );
AOI22X1TS U3993 ( .A0(n2982), .A1(Data_array_SWR[37]), .B0(n2958), .B1(
Data_array_SWR[45]), .Y(n2626) );
AOI22X1TS U3994 ( .A0(n2869), .A1(n1948), .B0(Data_array_SWR[49]), .B1(n2405), .Y(n2625) );
NAND2X2TS U3995 ( .A(n2626), .B(n2625), .Y(n4337) );
AOI22X1TS U3996 ( .A0(n1923), .A1(Data_array_SWR[6]), .B0(n1921), .B1(
Data_array_SWR[14]), .Y(n2628) );
AOI22X1TS U3997 ( .A0(Data_array_SWR[18]), .A1(n1933), .B0(
Data_array_SWR[10]), .B1(n1919), .Y(n2627) );
AOI21X1TS U3998 ( .A0(n3664), .A1(n4337), .B0(n2629), .Y(n2654) );
AOI22X1TS U3999 ( .A0(n2982), .A1(Data_array_SWR[47]), .B0(n2981), .B1(
Data_array_SWR[51]), .Y(n2630) );
NAND2X2TS U4000 ( .A(n2630), .B(n2645), .Y(n4302) );
AOI22X1TS U4001 ( .A0(n2833), .A1(Data_array_SWR[30]), .B0(n2959), .B1(
Data_array_SWR[22]), .Y(n2632) );
AOI22X1TS U4002 ( .A0(n2976), .A1(n1937), .B0(n3651), .B1(Data_array_SWR[26]), .Y(n2631) );
NAND2X1TS U4003 ( .A(n2632), .B(n2631), .Y(n4305) );
AOI22X1TS U4004 ( .A0(n4338), .A1(n4302), .B0(n4318), .B1(n4305), .Y(n2633)
);
NAND2X2TS U4005 ( .A(n3648), .B(n1929), .Y(n3686) );
OAI211X1TS U4006 ( .A0(n1928), .A1(n2654), .B0(n2633), .C0(n3686), .Y(n4347)
);
AOI22X1TS U4007 ( .A0(n1923), .A1(Data_array_SWR[5]), .B0(n1921), .B1(
Data_array_SWR[13]), .Y(n2635) );
AOI22X1TS U4008 ( .A0(n1933), .A1(Data_array_SWR[17]), .B0(n1919), .B1(
Data_array_SWR[9]), .Y(n2634) );
AOI21X1TS U4009 ( .A0(n3664), .A1(n4308), .B0(n2636), .Y(n2667) );
AOI22X1TS U4010 ( .A0(n3652), .A1(Data_array_SWR[29]), .B0(n2982), .B1(
Data_array_SWR[21]), .Y(n2638) );
AOI22X1TS U4011 ( .A0(n2976), .A1(Data_array_SWR[33]), .B0(n2869), .B1(
Data_array_SWR[25]), .Y(n2637) );
NAND2X1TS U4012 ( .A(n2638), .B(n2637), .Y(n4312) );
AOI22X1TS U4013 ( .A0(n4338), .A1(n4307), .B0(n4318), .B1(n4312), .Y(n2639)
);
OAI211X1TS U4014 ( .A0(n1928), .A1(n2667), .B0(n2639), .C0(n3686), .Y(n4348)
);
AOI22X1TS U4015 ( .A0(n2982), .A1(Data_array_SWR[35]), .B0(n2958), .B1(
Data_array_SWR[43]), .Y(n2641) );
AOI22X1TS U4016 ( .A0(n2981), .A1(Data_array_SWR[39]), .B0(n2405), .B1(
Data_array_SWR[47]), .Y(n2640) );
NAND2X2TS U4017 ( .A(n2641), .B(n2640), .Y(n4317) );
AOI22X1TS U4018 ( .A0(n1923), .A1(Data_array_SWR[4]), .B0(n1921), .B1(
Data_array_SWR[12]), .Y(n2643) );
AOI22X1TS U4019 ( .A0(n1933), .A1(Data_array_SWR[16]), .B0(n1919), .B1(
Data_array_SWR[8]), .Y(n2642) );
AOI21X1TS U4020 ( .A0(n3023), .A1(n4317), .B0(n2644), .Y(n2652) );
NAND2X1TS U4021 ( .A(n2981), .B(Data_array_SWR[53]), .Y(n2647) );
NAND2X1TS U4022 ( .A(n2982), .B(Data_array_SWR[49]), .Y(n2646) );
NAND3X2TS U4023 ( .A(n2647), .B(n2646), .C(n2645), .Y(n4315) );
AOI22X1TS U4024 ( .A0(n3652), .A1(Data_array_SWR[28]), .B0(n2959), .B1(
Data_array_SWR[20]), .Y(n2649) );
AOI22X1TS U4025 ( .A0(n2976), .A1(Data_array_SWR[32]), .B0(n3651), .B1(
Data_array_SWR[24]), .Y(n2648) );
NAND2X1TS U4026 ( .A(n2649), .B(n2648), .Y(n4322) );
AOI22X1TS U4027 ( .A0(n4338), .A1(n4315), .B0(n4318), .B1(n4322), .Y(n2650)
);
OAI211X1TS U4028 ( .A0(n1929), .A1(n2652), .B0(n2650), .C0(n3686), .Y(n4350)
);
AOI22X1TS U4029 ( .A0(n4323), .A1(n4315), .B0(n4316), .B1(n4322), .Y(n2651)
);
OAI211X1TS U4030 ( .A0(n2652), .A1(n1927), .B0(n2651), .C0(n2665), .Y(n4276)
);
AOI22X1TS U4031 ( .A0(n4323), .A1(n4302), .B0(n4316), .B1(n4305), .Y(n2653)
);
OAI211X1TS U4032 ( .A0(n2654), .A1(n3689), .B0(n2653), .C0(n2665), .Y(n4278)
);
AOI22X1TS U4033 ( .A0(n1934), .A1(Data_array_SWR[24]), .B0(n1924), .B1(
Data_array_SWR[12]), .Y(n2661) );
AOI22X1TS U4034 ( .A0(n1922), .A1(Data_array_SWR[20]), .B0(n1919), .B1(
Data_array_SWR[16]), .Y(n2660) );
AOI22X1TS U4035 ( .A0(n3654), .A1(Data_array_SWR[39]), .B0(n2981), .B1(
Data_array_SWR[32]), .Y(n2656) );
AOI22X1TS U4036 ( .A0(n2833), .A1(Data_array_SWR[35]), .B0(n2959), .B1(
Data_array_SWR[28]), .Y(n2655) );
NAND2X1TS U4037 ( .A(n2656), .B(n2655), .Y(n2963) );
AOI22X1TS U4038 ( .A0(n2833), .A1(Data_array_SWR[51]), .B0(n2959), .B1(
Data_array_SWR[43]), .Y(n2657) );
AOI22X1TS U4039 ( .A0(n3022), .A1(n2963), .B0(n3664), .B1(n3006), .Y(n2659)
);
AOI22X1TS U4040 ( .A0(Data_array_SWR[53]), .A1(n2405), .B0(n2869), .B1(
Data_array_SWR[45]), .Y(n2663) );
AOI22X1TS U4041 ( .A0(Data_array_SWR[49]), .A1(n2958), .B0(n2959), .B1(n1948), .Y(n2662) );
NAND2X1TS U4042 ( .A(n2663), .B(n2662), .Y(n3676) );
AOI22X1TS U4043 ( .A0(n1929), .A1(n3679), .B0(n4323), .B1(n3676), .Y(n2664)
);
NAND2X1TS U4044 ( .A(n2664), .B(n2665), .Y(n4279) );
AOI22X1TS U4045 ( .A0(n4323), .A1(n4307), .B0(n4316), .B1(n4312), .Y(n2666)
);
OAI211X1TS U4046 ( .A0(n2667), .A1(n3689), .B0(n2666), .C0(n2665), .Y(n4277)
);
AOI22X1TS U4047 ( .A0(n2976), .A1(Data_array_SWR[43]), .B0(n2958), .B1(
Data_array_SWR[39]), .Y(n2669) );
AOI22X1TS U4048 ( .A0(n2869), .A1(Data_array_SWR[35]), .B0(n3653), .B1(
Data_array_SWR[32]), .Y(n2668) );
NAND2X2TS U4049 ( .A(n1929), .B(n3664), .Y(n4292) );
AOI22X1TS U4050 ( .A0(n4318), .A1(n4302), .B0(n4316), .B1(n4337), .Y(n2670)
);
AOI21X1TS U4051 ( .A0(n4338), .A1(n4305), .B0(n2671), .Y(n2672) );
OAI21X1TS U4052 ( .A0(n4332), .A1(n4340), .B0(n2672), .Y(n4295) );
AOI22X1TS U4053 ( .A0(n2405), .A1(Data_array_SWR[45]), .B0(n2958), .B1(n1948), .Y(n2674) );
AOI22X1TS U4054 ( .A0(n2869), .A1(Data_array_SWR[37]), .B0(n2959), .B1(n1937), .Y(n2673) );
AOI22X1TS U4055 ( .A0(n4318), .A1(n4315), .B0(n4316), .B1(n4317), .Y(n2675)
);
AOI21X1TS U4056 ( .A0(n4338), .A1(n4322), .B0(n2676), .Y(n2677) );
OAI21X1TS U4057 ( .A0(n4326), .A1(n4340), .B0(n2677), .Y(n4289) );
NAND2X1TS U4058 ( .A(n2682), .B(n2681), .Y(n2685) );
INVX2TS U4059 ( .A(n2685), .Y(n2683) );
XNOR2X1TS U4060 ( .A(n2684), .B(n2683), .Y(n2688) );
XOR2X1TS U4061 ( .A(n3849), .B(n2685), .Y(n2686) );
AOI22X1TS U4062 ( .A0(n2686), .A1(n4367), .B0(Raw_mant_NRM_SWR[34]), .B1(
n3747), .Y(n2687) );
OAI2BB1X1TS U4063 ( .A0N(n3979), .A1N(n2688), .B0(n2687), .Y(n1235) );
NAND2X1TS U4064 ( .A(n2520), .B(Raw_mant_NRM_SWR[54]), .Y(n2690) );
NAND2X1TS U4065 ( .A(n3361), .B(Raw_mant_NRM_SWR[0]), .Y(n2689) );
INVX2TS U4066 ( .A(n2691), .Y(n2692) );
BUFX3TS U4067 ( .A(n3588), .Y(n3465) );
INVX2TS U4068 ( .A(n3357), .Y(n3429) );
NAND2X1TS U4069 ( .A(n3430), .B(Raw_mant_NRM_SWR[1]), .Y(n2697) );
BUFX3TS U4070 ( .A(Shift_reg_FLAGS_7[1]), .Y(n4480) );
NAND2X1TS U4071 ( .A(n3323), .B(DmP_mant_SHT1_SW[51]), .Y(n2696) );
NAND3X1TS U4072 ( .A(n2698), .B(n2697), .C(n2696), .Y(n3252) );
AOI22X1TS U4073 ( .A0(n1995), .A1(n1930), .B0(n3465), .B1(n3252), .Y(n2702)
);
NAND2X4TS U4074 ( .A(n3164), .B(n3174), .Y(n3158) );
BUFX3TS U4075 ( .A(n3551), .Y(n3435) );
NAND2X1TS U4076 ( .A(n3380), .B(Raw_mant_NRM_SWR[2]), .Y(n2810) );
NAND2X1TS U4077 ( .A(n3696), .B(DmP_mant_SHT1_SW[50]), .Y(n2699) );
AOI22X1TS U4078 ( .A0(n3435), .A1(n3338), .B0(Data_array_SWR[51]), .B1(n3604), .Y(n2701) );
NAND2X1TS U4079 ( .A(n2702), .B(n2701), .Y(n1750) );
INVX2TS U4080 ( .A(rst), .Y(n2726) );
CLKBUFX3TS U4081 ( .A(n2726), .Y(n4754) );
CLKBUFX3TS U4082 ( .A(n4754), .Y(n2703) );
CLKBUFX3TS U4083 ( .A(n2703), .Y(n2708) );
BUFX3TS U4084 ( .A(n2708), .Y(n4706) );
BUFX3TS U4085 ( .A(n2704), .Y(n4705) );
BUFX3TS U4086 ( .A(n2708), .Y(n4704) );
BUFX3TS U4087 ( .A(n2708), .Y(n4703) );
BUFX3TS U4088 ( .A(n2708), .Y(n4702) );
CLKBUFX3TS U4089 ( .A(n2726), .Y(n2711) );
CLKBUFX3TS U4090 ( .A(n2711), .Y(n2705) );
BUFX3TS U4091 ( .A(n2706), .Y(n4700) );
CLKBUFX2TS U4092 ( .A(n4754), .Y(n4753) );
BUFX3TS U4093 ( .A(n4753), .Y(n4752) );
BUFX3TS U4094 ( .A(n2703), .Y(n4751) );
BUFX3TS U4095 ( .A(n2711), .Y(n4699) );
BUFX3TS U4096 ( .A(n2705), .Y(n4717) );
BUFX3TS U4097 ( .A(n2710), .Y(n4716) );
BUFX3TS U4098 ( .A(n2705), .Y(n4715) );
BUFX3TS U4099 ( .A(n2708), .Y(n4714) );
BUFX3TS U4100 ( .A(n2705), .Y(n4712) );
BUFX3TS U4101 ( .A(n2709), .Y(n4711) );
BUFX3TS U4102 ( .A(n2707), .Y(n4710) );
BUFX3TS U4103 ( .A(n2708), .Y(n4709) );
BUFX3TS U4104 ( .A(n2706), .Y(n4708) );
BUFX3TS U4105 ( .A(n2706), .Y(n4707) );
BUFX3TS U4106 ( .A(n2704), .Y(n4680) );
BUFX3TS U4107 ( .A(n2705), .Y(n4679) );
BUFX3TS U4108 ( .A(n2704), .Y(n4678) );
BUFX3TS U4109 ( .A(n2704), .Y(n4677) );
BUFX3TS U4110 ( .A(n2703), .Y(n4749) );
BUFX3TS U4111 ( .A(n2703), .Y(n4748) );
BUFX3TS U4112 ( .A(n2703), .Y(n4747) );
BUFX3TS U4113 ( .A(n2706), .Y(n4697) );
BUFX3TS U4114 ( .A(n2703), .Y(n4746) );
BUFX3TS U4115 ( .A(n2703), .Y(n4750) );
BUFX3TS U4116 ( .A(n2710), .Y(n4696) );
BUFX3TS U4117 ( .A(n2706), .Y(n4695) );
BUFX3TS U4118 ( .A(n2706), .Y(n4694) );
BUFX3TS U4119 ( .A(n2706), .Y(n4693) );
BUFX3TS U4120 ( .A(n2703), .Y(n4692) );
BUFX3TS U4121 ( .A(n2707), .Y(n4691) );
BUFX3TS U4122 ( .A(n2707), .Y(n4690) );
BUFX3TS U4123 ( .A(n2705), .Y(n4718) );
BUFX3TS U4124 ( .A(n2707), .Y(n4685) );
BUFX3TS U4125 ( .A(n2704), .Y(n4676) );
BUFX3TS U4126 ( .A(n2709), .Y(n4738) );
BUFX3TS U4127 ( .A(n2709), .Y(n4689) );
BUFX3TS U4128 ( .A(n2705), .Y(n4737) );
BUFX3TS U4129 ( .A(n2704), .Y(n4739) );
BUFX3TS U4130 ( .A(n2711), .Y(n4729) );
BUFX3TS U4131 ( .A(n2703), .Y(n4681) );
BUFX3TS U4132 ( .A(n2707), .Y(n4684) );
BUFX3TS U4133 ( .A(n2711), .Y(n4682) );
BUFX3TS U4134 ( .A(n2707), .Y(n4688) );
BUFX3TS U4135 ( .A(n2704), .Y(n4683) );
BUFX3TS U4136 ( .A(n2707), .Y(n4686) );
BUFX3TS U4137 ( .A(n2708), .Y(n4687) );
BUFX3TS U4138 ( .A(n2711), .Y(n4731) );
BUFX3TS U4139 ( .A(n2711), .Y(n4732) );
BUFX3TS U4140 ( .A(n2711), .Y(n4733) );
BUFX3TS U4141 ( .A(n2711), .Y(n4735) );
BUFX3TS U4142 ( .A(n2705), .Y(n4723) );
BUFX3TS U4143 ( .A(n2705), .Y(n4719) );
BUFX3TS U4144 ( .A(n2706), .Y(n4720) );
BUFX3TS U4145 ( .A(n2710), .Y(n4721) );
BUFX3TS U4146 ( .A(n2707), .Y(n4722) );
BUFX3TS U4147 ( .A(n2710), .Y(n4724) );
BUFX3TS U4148 ( .A(n2709), .Y(n4745) );
BUFX3TS U4149 ( .A(n2709), .Y(n4741) );
BUFX3TS U4150 ( .A(n2710), .Y(n4725) );
BUFX3TS U4151 ( .A(n2709), .Y(n4744) );
BUFX3TS U4152 ( .A(n2710), .Y(n4734) );
BUFX3TS U4153 ( .A(n2710), .Y(n4727) );
BUFX3TS U4154 ( .A(n2709), .Y(n4743) );
BUFX3TS U4155 ( .A(n2710), .Y(n4726) );
BUFX3TS U4156 ( .A(n2711), .Y(n4742) );
BUFX3TS U4157 ( .A(n3979), .Y(n4271) );
INVX2TS U4158 ( .A(n2712), .Y(n4166) );
INVX2TS U4159 ( .A(n2713), .Y(n2716) );
INVX2TS U4160 ( .A(n2714), .Y(n2715) );
OAI21X1TS U4161 ( .A0(n4166), .A1(n2716), .B0(n2715), .Y(n4111) );
NAND2X1TS U4162 ( .A(n2719), .B(n2718), .Y(n2721) );
INVX2TS U4163 ( .A(n2721), .Y(n2720) );
XNOR2X1TS U4164 ( .A(n4111), .B(n2720), .Y(n2725) );
XNOR2X1TS U4165 ( .A(n2722), .B(n2721), .Y(n2723) );
BUFX3TS U4166 ( .A(n4174), .Y(n4160) );
BUFX3TS U4167 ( .A(n4448), .Y(n4213) );
AOI22X1TS U4168 ( .A0(n2723), .A1(n4160), .B0(Raw_mant_NRM_SWR[11]), .B1(
n4213), .Y(n2724) );
OAI2BB1X1TS U4169 ( .A0N(n4271), .A1N(n2725), .B0(n2724), .Y(n1258) );
BUFX3TS U4170 ( .A(n2726), .Y(n4701) );
BUFX3TS U4171 ( .A(n2726), .Y(n4713) );
BUFX3TS U4172 ( .A(n2726), .Y(n4698) );
BUFX3TS U4173 ( .A(n2726), .Y(n4730) );
BUFX3TS U4174 ( .A(n2726), .Y(n4736) );
BUFX3TS U4175 ( .A(n2709), .Y(n4728) );
BUFX3TS U4176 ( .A(n2726), .Y(n4740) );
NAND2X1TS U4177 ( .A(DmP_EXP_EWSW[52]), .B(n4606), .Y(n4255) );
OA21XLTS U4178 ( .A0(DmP_EXP_EWSW[52]), .A1(n4606), .B0(n4255), .Y(n2728) );
BUFX3TS U4179 ( .A(n4629), .Y(n4458) );
NAND2X1TS U4180 ( .A(n4458), .B(Shift_amount_SHT1_EWR[0]), .Y(n2727) );
INVX2TS U4181 ( .A(n3357), .Y(n3618) );
INVX2TS U4182 ( .A(n3631), .Y(n3643) );
AOI22X1TS U4183 ( .A0(n2730), .A1(n3624), .B0(DmP_mant_SFG_SWR[53]), .B1(
n4349), .Y(n2729) );
INVX2TS U4184 ( .A(n3624), .Y(n3645) );
AOI22X1TS U4185 ( .A0(n2730), .A1(n3631), .B0(DmP_mant_SFG_SWR[1]), .B1(
n4349), .Y(n2731) );
INVX2TS U4186 ( .A(n2734), .Y(n2735) );
OAI211X1TS U4187 ( .A0(n2738), .A1(n2737), .B0(n2736), .C0(n2735), .Y(n2753)
);
INVX2TS U4188 ( .A(n2753), .Y(n2746) );
OAI22X1TS U4189 ( .A0(n2787), .A1(n2741), .B0(n2740), .B1(n2739), .Y(n2742)
);
AOI211X1TS U4190 ( .A0(n2744), .A1(Raw_mant_NRM_SWR[22]), .B0(n2743), .C0(
n2742), .Y(n2745) );
AOI211X1TS U4191 ( .A0(n2755), .A1(Raw_mant_NRM_SWR[12]), .B0(n2749), .C0(
n2748), .Y(n2752) );
NAND2X1TS U4192 ( .A(n3696), .B(LZD_output_NRM2_EW[2]), .Y(n2750) );
NOR2X2TS U4193 ( .A(n3439), .B(n4369), .Y(n2806) );
AOI22X1TS U4194 ( .A0(n2806), .A1(Shift_amount_SHT1_EWR[2]), .B0(
shift_value_SHT2_EWR[2]), .B1(n3611), .Y(n2751) );
NOR3X1TS U4195 ( .A(n2756), .B(Raw_mant_NRM_SWR[27]), .C(n4630), .Y(n2761)
);
AOI211X1TS U4196 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n2762), .B0(n2761), .C0(
n2760), .Y(n2763) );
AND4X1TS U4197 ( .A(n2766), .B(n2765), .C(n2764), .D(n2763), .Y(n2768) );
OAI211X1TS U4198 ( .A0(n2783), .A1(n4660), .B0(n2768), .C0(n2767), .Y(n4371)
);
INVX2TS U4199 ( .A(n1899), .Y(n2784) );
AOI222X1TS U4200 ( .A0(n4371), .A1(n3375), .B0(n2806), .B1(
Shift_amount_SHT1_EWR[3]), .C0(shift_value_SHT2_EWR[3]), .C1(n2784),
.Y(n2769) );
INVX2TS U4201 ( .A(n2769), .Y(n1696) );
NAND3XLTS U4202 ( .A(n4505), .B(n4615), .C(n2770), .Y(n2777) );
AOI21X1TS U4203 ( .A0(n2772), .A1(n4620), .B0(n2771), .Y(n2776) );
AOI211X1TS U4204 ( .A0(n2778), .A1(n2777), .B0(n2776), .C0(n2775), .Y(n2780)
);
OAI211X1TS U4205 ( .A0(n2783), .A1(n4626), .B0(n2782), .C0(n2781), .Y(n4370)
);
INVX2TS U4206 ( .A(n2786), .Y(n1693) );
OAI31X1TS U4207 ( .A0(Raw_mant_NRM_SWR[41]), .A1(n2791), .A2(n2790), .B0(
n2789), .Y(n2798) );
NOR4X1TS U4208 ( .A(Raw_mant_NRM_SWR[30]), .B(Raw_mant_NRM_SWR[29]), .C(
Raw_mant_NRM_SWR[28]), .D(Raw_mant_NRM_SWR[26]), .Y(n2792) );
OAI22X1TS U4209 ( .A0(n2794), .A1(n4577), .B0(n2793), .B1(n2792), .Y(n2795)
);
NOR4X1TS U4210 ( .A(n2798), .B(n2797), .C(n2796), .D(n2795), .Y(n2800) );
AOI21X1TS U4211 ( .A0(n2804), .A1(Raw_mant_NRM_SWR[2]), .B0(n2805), .Y(n2803) );
NAND2X1TS U4212 ( .A(n3696), .B(LZD_output_NRM2_EW[4]), .Y(n2802) );
INVX2TS U4213 ( .A(n2804), .Y(n2809) );
NAND2X1TS U4214 ( .A(n2805), .B(n3361), .Y(n2808) );
AOI22X1TS U4215 ( .A0(n2806), .A1(Shift_amount_SHT1_EWR[4]), .B0(
shift_value_SHT2_EWR[4]), .B1(n3439), .Y(n2807) );
INVX2TS U4216 ( .A(n3822), .Y(n3806) );
INVX2TS U4217 ( .A(n2813), .Y(n2816) );
INVX2TS U4218 ( .A(n2814), .Y(n2815) );
INVX2TS U4219 ( .A(n3833), .Y(n2818) );
AOI21X1TS U4220 ( .A0(n3838), .A1(n3834), .B0(n2818), .Y(n2822) );
NAND2X1TS U4221 ( .A(n2821), .B(n2820), .Y(n2827) );
INVX2TS U4222 ( .A(n2823), .Y(n2826) );
INVX2TS U4223 ( .A(n2824), .Y(n2825) );
OAI21X1TS U4224 ( .A0(n3781), .A1(n2826), .B0(n2825), .Y(n3880) );
INVX2TS U4225 ( .A(n2827), .Y(n2828) );
XNOR2X1TS U4226 ( .A(n3880), .B(n2828), .Y(n2829) );
AOI22X1TS U4227 ( .A0(n2829), .A1(n4275), .B0(Raw_mant_NRM_SWR[41]), .B1(
n3974), .Y(n2830) );
AOI21X1TS U4228 ( .A0(n3611), .A1(Data_array_SWR[53]), .B0(n3381), .Y(n2832)
);
AOI22X1TS U4229 ( .A0(Data_array_SWR[26]), .A1(n2833), .B0(n3651), .B1(
Data_array_SWR[22]), .Y(n2835) );
AOI22X1TS U4230 ( .A0(n3654), .A1(Data_array_SWR[30]), .B0(n2870), .B1(
Data_array_SWR[18]), .Y(n2834) );
NAND2X1TS U4231 ( .A(n2835), .B(n2834), .Y(n2857) );
INVX2TS U4232 ( .A(n4315), .Y(n2844) );
OAI22X1TS U4233 ( .A0(n2844), .A1(n4292), .B0(n4326), .B1(n4329), .Y(n2836)
);
AOI211X1TS U4234 ( .A0(n1938), .A1(n4317), .B0(n2837), .C0(n2836), .Y(n2838)
);
OAI2BB1X1TS U4235 ( .A0N(n1941), .A1N(n2857), .B0(n2838), .Y(n4288) );
OAI22X1TS U4236 ( .A0(n2839), .A1(n4292), .B0(n4314), .B1(n4329), .Y(n2840)
);
AOI211X1TS U4237 ( .A0(n1938), .A1(n4308), .B0(n2841), .C0(n2840), .Y(n2842)
);
OAI2BB1X1TS U4238 ( .A0N(n1941), .A1N(n2843), .B0(n2842), .Y(n4287) );
OAI22X1TS U4239 ( .A0(n2844), .A1(n4333), .B0(n4326), .B1(n4331), .Y(n2845)
);
AOI211X1TS U4240 ( .A0(n1941), .A1(n4317), .B0(n2846), .C0(n2845), .Y(n2847)
);
OAI2BB1X1TS U4241 ( .A0N(n1938), .A1N(n2857), .B0(n2847), .Y(n4327) );
AOI22X1TS U4242 ( .A0(intDX_EWSW[1]), .A1(n3057), .B0(DMP_EXP_EWSW[1]), .B1(
n4432), .Y(n2848) );
AOI22X1TS U4243 ( .A0(intDX_EWSW[3]), .A1(n3057), .B0(DMP_EXP_EWSW[3]), .B1(
n3110), .Y(n2849) );
AOI22X1TS U4244 ( .A0(DMP_EXP_EWSW[57]), .A1(n4397), .B0(intDX_EWSW[57]),
.B1(n3057), .Y(n2850) );
AOI22X1TS U4245 ( .A0(intDX_EWSW[6]), .A1(n3057), .B0(DMP_EXP_EWSW[6]), .B1(
n3110), .Y(n2851) );
AOI22X1TS U4246 ( .A0(intDX_EWSW[2]), .A1(n3057), .B0(DMP_EXP_EWSW[2]), .B1(
n4432), .Y(n2852) );
AOI22X1TS U4247 ( .A0(intDX_EWSW[4]), .A1(n3057), .B0(DMP_EXP_EWSW[4]), .B1(
n3110), .Y(n2853) );
INVX2TS U4248 ( .A(n2854), .Y(n1294) );
INVX2TS U4249 ( .A(n4326), .Y(n2855) );
NAND2X1TS U4250 ( .A(n2855), .B(n3023), .Y(n2861) );
INVX2TS U4251 ( .A(n2856), .Y(n3660) );
AOI22X1TS U4252 ( .A0(n2857), .A1(n4296), .B0(n3660), .B1(n4315), .Y(n2860)
);
AOI22X1TS U4253 ( .A0(n1922), .A1(Data_array_SWR[10]), .B0(n1924), .B1(
Data_array_SWR[2]), .Y(n2859) );
AOI22X1TS U4254 ( .A0(Data_array_SWR[14]), .A1(n1934), .B0(n1920), .B1(
Data_array_SWR[6]), .Y(n2858) );
NAND4X1TS U4255 ( .A(n2861), .B(n2860), .C(n2859), .D(n2858), .Y(n3048) );
INVX2TS U4256 ( .A(n3048), .Y(n3646) );
INVX2TS U4257 ( .A(n4320), .Y(n2862) );
INVX2TS U4258 ( .A(n3647), .Y(n2863) );
AOI22X1TS U4259 ( .A0(n2950), .A1(n2863), .B0(final_result_ieee[50]), .B1(
n3697), .Y(n2864) );
OA21X1TS U4260 ( .A0(Data_array_SWR[50]), .A1(n2866), .B0(n2865), .Y(n3027)
);
AOI22X1TS U4261 ( .A0(n3654), .A1(Data_array_SWR[31]), .B0(n3651), .B1(
Data_array_SWR[23]), .Y(n2868) );
AOI22X1TS U4262 ( .A0(n3652), .A1(Data_array_SWR[27]), .B0(n2870), .B1(
Data_array_SWR[19]), .Y(n2867) );
NAND2X1TS U4263 ( .A(n2868), .B(n2867), .Y(n3021) );
AOI22X1TS U4264 ( .A0(n3027), .A1(n3660), .B0(n4296), .B1(n3021), .Y(n2876)
);
AOI22X1TS U4265 ( .A0(n1920), .A1(Data_array_SWR[7]), .B0(n1924), .B1(
Data_array_SWR[3]), .Y(n2875) );
AOI22X1TS U4266 ( .A0(n1934), .A1(Data_array_SWR[15]), .B0(n1922), .B1(
Data_array_SWR[11]), .Y(n2874) );
AOI22X1TS U4267 ( .A0(n3654), .A1(Data_array_SWR[46]), .B0(n3651), .B1(n1944), .Y(n2872) );
AOI22X1TS U4268 ( .A0(n3652), .A1(n1946), .B0(n2870), .B1(Data_array_SWR[34]), .Y(n2871) );
NAND2X1TS U4269 ( .A(n2872), .B(n2871), .Y(n3030) );
NAND2X1TS U4270 ( .A(n3030), .B(n3023), .Y(n2873) );
NAND4X1TS U4271 ( .A(n2876), .B(n2875), .C(n2874), .D(n2873), .Y(n3035) );
INVX2TS U4272 ( .A(n3035), .Y(n3632) );
AOI22X1TS U4273 ( .A0(n2950), .A1(n1902), .B0(final_result_ieee[49]), .B1(
n3697), .Y(n2877) );
NAND2X1TS U4274 ( .A(n3022), .B(n2976), .Y(n2941) );
AOI22X1TS U4275 ( .A0(n1921), .A1(Data_array_SWR[16]), .B0(n1923), .B1(
Data_array_SWR[8]), .Y(n2878) );
AOI21X1TS U4276 ( .A0(n3664), .A1(n3681), .B0(n2879), .Y(n2881) );
AOI22X1TS U4277 ( .A0(n1934), .A1(Data_array_SWR[20]), .B0(n1920), .B1(
Data_array_SWR[12]), .Y(n2880) );
OAI211X1TS U4278 ( .A0(n2974), .A1(n3659), .B0(n2881), .C0(n2880), .Y(n2967)
);
INVX2TS U4279 ( .A(n2967), .Y(n3635) );
NAND2X2TS U4280 ( .A(n2882), .B(n2323), .Y(n3005) );
INVX2TS U4281 ( .A(n3636), .Y(n2883) );
AOI22X1TS U4282 ( .A0(n2950), .A1(n2883), .B0(final_result_ieee[44]), .B1(
n3697), .Y(n2884) );
AOI22X1TS U4283 ( .A0(n1921), .A1(Data_array_SWR[15]), .B0(n1923), .B1(
Data_array_SWR[7]), .Y(n2885) );
AOI21X1TS U4284 ( .A0(n3664), .A1(n3685), .B0(n2886), .Y(n2888) );
AOI22X1TS U4285 ( .A0(n3657), .A1(Data_array_SWR[19]), .B0(n1920), .B1(
Data_array_SWR[11]), .Y(n2887) );
OAI211X1TS U4286 ( .A0(n2953), .A1(n2398), .B0(n2888), .C0(n2887), .Y(n3003)
);
INVX2TS U4287 ( .A(n3003), .Y(n3633) );
INVX2TS U4288 ( .A(n3634), .Y(n2889) );
AOI22X1TS U4289 ( .A0(n2950), .A1(n2889), .B0(final_result_ieee[45]), .B1(
n3697), .Y(n2890) );
AOI22X1TS U4290 ( .A0(intDX_EWSW[49]), .A1(n3090), .B0(DmP_EXP_EWSW[49]),
.B1(n4397), .Y(n2891) );
AOI22X1TS U4291 ( .A0(intDX_EWSW[15]), .A1(n3066), .B0(DmP_EXP_EWSW[15]),
.B1(n2310), .Y(n2893) );
BUFX3TS U4292 ( .A(n2907), .Y(n3547) );
AOI22X1TS U4293 ( .A0(intDX_EWSW[3]), .A1(n3126), .B0(DmP_EXP_EWSW[3]), .B1(
n3547), .Y(n2894) );
AOI22X1TS U4294 ( .A0(intDX_EWSW[14]), .A1(n3066), .B0(DmP_EXP_EWSW[14]),
.B1(n2310), .Y(n2895) );
INVX4TS U4295 ( .A(n2896), .Y(n3546) );
AOI22X1TS U4296 ( .A0(intDX_EWSW[1]), .A1(n3126), .B0(DmP_EXP_EWSW[1]), .B1(
n3547), .Y(n2897) );
BUFX3TS U4297 ( .A(n2928), .Y(n3115) );
AOI22X1TS U4298 ( .A0(intDX_EWSW[15]), .A1(n2892), .B0(DMP_EXP_EWSW[15]),
.B1(n3115), .Y(n2898) );
BUFX3TS U4299 ( .A(n2907), .Y(n3086) );
AOI22X1TS U4300 ( .A0(intDX_EWSW[39]), .A1(n3078), .B0(DmP_EXP_EWSW[39]),
.B1(n3086), .Y(n2899) );
AOI22X1TS U4301 ( .A0(intDX_EWSW[14]), .A1(n2892), .B0(DMP_EXP_EWSW[14]),
.B1(n3115), .Y(n2900) );
BUFX3TS U4302 ( .A(n4432), .Y(n3119) );
AOI22X1TS U4303 ( .A0(intDX_EWSW[39]), .A1(n3122), .B0(DMP_EXP_EWSW[39]),
.B1(n3119), .Y(n2901) );
AOI22X1TS U4304 ( .A0(intDY_EWSW[61]), .A1(n3148), .B0(DMP_EXP_EWSW[61]),
.B1(n3547), .Y(n2902) );
BUFX3TS U4305 ( .A(n2928), .Y(n3147) );
AOI22X1TS U4306 ( .A0(intDX_EWSW[49]), .A1(n3144), .B0(DMP_EXP_EWSW[49]),
.B1(n3147), .Y(n2903) );
INVX2TS U4307 ( .A(n3252), .Y(n3343) );
BUFX3TS U4308 ( .A(n3588), .Y(n3613) );
AOI22X1TS U4309 ( .A0(n3613), .A1(n1930), .B0(Data_array_SWR[52]), .B1(n3604), .Y(n2904) );
AOI22X1TS U4310 ( .A0(intDY_EWSW[62]), .A1(n3148), .B0(DMP_EXP_EWSW[62]),
.B1(n3547), .Y(n2905) );
AOI22X1TS U4311 ( .A0(intDY_EWSW[59]), .A1(n3148), .B0(DMP_EXP_EWSW[59]),
.B1(n3547), .Y(n2906) );
BUFX3TS U4312 ( .A(n2907), .Y(n3125) );
AOI22X1TS U4313 ( .A0(intDX_EWSW[8]), .A1(n3126), .B0(DmP_EXP_EWSW[8]), .B1(
n3125), .Y(n2908) );
AOI22X1TS U4314 ( .A0(intDX_EWSW[11]), .A1(n3126), .B0(DmP_EXP_EWSW[11]),
.B1(n3125), .Y(n2909) );
AOI22X1TS U4315 ( .A0(intDY_EWSW[60]), .A1(n3148), .B0(DMP_EXP_EWSW[60]),
.B1(n3547), .Y(n2910) );
AOI22X1TS U4316 ( .A0(intDX_EWSW[18]), .A1(n3066), .B0(DmP_EXP_EWSW[18]),
.B1(n2310), .Y(n2911) );
AOI22X1TS U4317 ( .A0(intDX_EWSW[17]), .A1(n3066), .B0(DmP_EXP_EWSW[17]),
.B1(n2310), .Y(n2912) );
AOI22X1TS U4318 ( .A0(intDX_EWSW[0]), .A1(n3148), .B0(DmP_EXP_EWSW[0]), .B1(
n3547), .Y(n2913) );
AOI22X1TS U4319 ( .A0(intDX_EWSW[31]), .A1(n3087), .B0(DmP_EXP_EWSW[31]),
.B1(n3077), .Y(n2915) );
AOI22X1TS U4320 ( .A0(intDX_EWSW[23]), .A1(n3078), .B0(DmP_EXP_EWSW[23]),
.B1(n2310), .Y(n2916) );
AOI22X1TS U4321 ( .A0(intDX_EWSW[26]), .A1(n3078), .B0(DmP_EXP_EWSW[26]),
.B1(n3077), .Y(n2917) );
AOI22X1TS U4322 ( .A0(intDX_EWSW[50]), .A1(n3090), .B0(DmP_EXP_EWSW[50]),
.B1(n4397), .Y(n2918) );
AOI22X1TS U4323 ( .A0(intDX_EWSW[25]), .A1(n3078), .B0(DmP_EXP_EWSW[25]),
.B1(n3547), .Y(n2919) );
AOI22X1TS U4324 ( .A0(intDX_EWSW[36]), .A1(n3087), .B0(DmP_EXP_EWSW[36]),
.B1(n3086), .Y(n2920) );
AOI22X1TS U4325 ( .A0(intDX_EWSW[43]), .A1(n3090), .B0(DmP_EXP_EWSW[43]),
.B1(n3086), .Y(n2921) );
AOI22X1TS U4326 ( .A0(intDX_EWSW[33]), .A1(n3087), .B0(DmP_EXP_EWSW[33]),
.B1(n3077), .Y(n2922) );
AOI22X1TS U4327 ( .A0(intDX_EWSW[35]), .A1(n3087), .B0(DmP_EXP_EWSW[35]),
.B1(n3077), .Y(n2923) );
AOI22X1TS U4328 ( .A0(DmP_EXP_EWSW[57]), .A1(n4397), .B0(intDX_EWSW[57]),
.B1(n3148), .Y(n2924) );
AOI22X1TS U4329 ( .A0(intDX_EWSW[45]), .A1(n3090), .B0(DmP_EXP_EWSW[45]),
.B1(n3086), .Y(n2925) );
AOI22X1TS U4330 ( .A0(intDX_EWSW[8]), .A1(n2892), .B0(DMP_EXP_EWSW[8]), .B1(
n3110), .Y(n2926) );
AOI22X1TS U4331 ( .A0(intDX_EWSW[11]), .A1(n2892), .B0(DMP_EXP_EWSW[11]),
.B1(n3110), .Y(n2927) );
BUFX3TS U4332 ( .A(n2928), .Y(n3106) );
AOI22X1TS U4333 ( .A0(intDX_EWSW[23]), .A1(n2896), .B0(DMP_EXP_EWSW[23]),
.B1(n3106), .Y(n2929) );
AOI22X1TS U4334 ( .A0(intDX_EWSW[31]), .A1(n3113), .B0(DMP_EXP_EWSW[31]),
.B1(n3106), .Y(n2932) );
AOI22X1TS U4335 ( .A0(intDX_EWSW[26]), .A1(n3113), .B0(DMP_EXP_EWSW[26]),
.B1(n3106), .Y(n2933) );
AOI22X1TS U4336 ( .A0(intDX_EWSW[18]), .A1(n2896), .B0(DMP_EXP_EWSW[18]),
.B1(n3115), .Y(n2934) );
AOI22X1TS U4337 ( .A0(intDX_EWSW[17]), .A1(n2896), .B0(DMP_EXP_EWSW[17]),
.B1(n3115), .Y(n2935) );
AOI22X1TS U4338 ( .A0(intDX_EWSW[25]), .A1(n2896), .B0(DMP_EXP_EWSW[25]),
.B1(n3147), .Y(n2936) );
AOI22X1TS U4339 ( .A0(intDX_EWSW[36]), .A1(n3122), .B0(DMP_EXP_EWSW[36]),
.B1(n3119), .Y(n2937) );
AOI22X1TS U4340 ( .A0(n1921), .A1(Data_array_SWR[17]), .B0(n1923), .B1(
Data_array_SWR[9]), .Y(n2940) );
AOI21X1TS U4341 ( .A0(n3023), .A1(n3672), .B0(n2942), .Y(n2944) );
AOI22X1TS U4342 ( .A0(n3657), .A1(Data_array_SWR[21]), .B0(n1920), .B1(
Data_array_SWR[13]), .Y(n2943) );
OAI211X1TS U4343 ( .A0(n2997), .A1(n2398), .B0(n2944), .C0(n2943), .Y(n2956)
);
INVX2TS U4344 ( .A(n2956), .Y(n3642) );
INVX2TS U4345 ( .A(n3644), .Y(n2945) );
AOI22X1TS U4346 ( .A0(n3045), .A1(n2945), .B0(final_result_ieee[43]), .B1(
n3697), .Y(n2946) );
AOI21X1TS U4347 ( .A0(n1934), .A1(Data_array_SWR[34]), .B0(n1917), .Y(n2952)
);
NAND2X1TS U4348 ( .A(n3685), .B(n3022), .Y(n2951) );
OAI211X1TS U4349 ( .A0(n2953), .A1(n2323), .B0(n2952), .C0(n2951), .Y(n3016)
);
BUFX3TS U4350 ( .A(n2955), .Y(n3044) );
AOI22X1TS U4351 ( .A0(n3049), .A1(n3016), .B0(final_result_ieee[21]), .B1(
n3044), .Y(n2954) );
BUFX3TS U4352 ( .A(n2955), .Y(n4391) );
AOI22X1TS U4353 ( .A0(n3049), .A1(n2956), .B0(final_result_ieee[7]), .B1(
n4391), .Y(n2957) );
AOI22X1TS U4354 ( .A0(n2976), .A1(Data_array_SWR[37]), .B0(n2958), .B1(n1937), .Y(n2961) );
AOI22X1TS U4355 ( .A0(n3651), .A1(Data_array_SWR[30]), .B0(n2959), .B1(
Data_array_SWR[26]), .Y(n2960) );
NAND2X1TS U4356 ( .A(n3676), .B(n4296), .Y(n2962) );
OAI211X1TS U4357 ( .A0(n3012), .A1(n2323), .B0(n1908), .C0(n2962), .Y(n3033)
);
INVX2TS U4358 ( .A(n3033), .Y(n3619) );
INVX2TS U4359 ( .A(n3620), .Y(n2965) );
AOI22X1TS U4360 ( .A0(n3045), .A1(n2965), .B0(final_result_ieee[26]), .B1(
n3044), .Y(n2966) );
AOI22X1TS U4361 ( .A0(n3049), .A1(n2967), .B0(final_result_ieee[6]), .B1(
n4391), .Y(n2968) );
AOI21X1TS U4362 ( .A0(n3657), .A1(Data_array_SWR[35]), .B0(n1917), .Y(n2973)
);
NAND2X1TS U4363 ( .A(n3681), .B(n3022), .Y(n2972) );
OAI211X1TS U4364 ( .A0(n2974), .A1(n2323), .B0(n2973), .C0(n2972), .Y(n3043)
);
AOI22X1TS U4365 ( .A0(n3049), .A1(n3043), .B0(final_result_ieee[22]), .B1(
n3044), .Y(n2975) );
NAND2X1TS U4366 ( .A(n3652), .B(Data_array_SWR[34]), .Y(n2980) );
NAND2X1TS U4367 ( .A(n2976), .B(n1944), .Y(n2979) );
NAND2X1TS U4368 ( .A(n2869), .B(Data_array_SWR[31]), .Y(n2978) );
NAND2X1TS U4369 ( .A(n2982), .B(Data_array_SWR[27]), .Y(n2977) );
NAND4X1TS U4370 ( .A(n2980), .B(n2979), .C(n2978), .D(n2977), .Y(n4299) );
INVX2TS U4371 ( .A(n4299), .Y(n2992) );
NAND2X1TS U4372 ( .A(n3652), .B(Data_array_SWR[50]), .Y(n2985) );
NAND2X1TS U4373 ( .A(n3651), .B(Data_array_SWR[46]), .Y(n2984) );
NAND2X1TS U4374 ( .A(n2982), .B(n1946), .Y(n2983) );
NAND4X1TS U4375 ( .A(n2986), .B(n2985), .C(n2984), .D(n2983), .Y(n4297) );
NAND2X1TS U4376 ( .A(n1923), .B(Data_array_SWR[11]), .Y(n2987) );
AOI21X1TS U4377 ( .A0(n3023), .A1(n4297), .B0(n2989), .Y(n2991) );
AOI22X1TS U4378 ( .A0(n1934), .A1(Data_array_SWR[23]), .B0(n1922), .B1(
Data_array_SWR[19]), .Y(n2990) );
OAI211X1TS U4379 ( .A0(n2992), .A1(n3659), .B0(n2991), .C0(n2990), .Y(n3019)
);
INVX2TS U4380 ( .A(n3019), .Y(n3627) );
INVX2TS U4381 ( .A(n3628), .Y(n2993) );
AOI22X1TS U4382 ( .A0(n3045), .A1(n2993), .B0(final_result_ieee[41]), .B1(
n3044), .Y(n2994) );
AOI21X1TS U4383 ( .A0(n1934), .A1(Data_array_SWR[36]), .B0(n1917), .Y(n2996)
);
NAND2X1TS U4384 ( .A(n3672), .B(n4296), .Y(n2995) );
OAI211X1TS U4385 ( .A0(n2997), .A1(n2323), .B0(n2996), .C0(n2995), .Y(n3014)
);
INVX2TS U4386 ( .A(n3014), .Y(n3622) );
INVX2TS U4387 ( .A(n3623), .Y(n3001) );
AOI22X1TS U4388 ( .A0(n3045), .A1(n3001), .B0(final_result_ieee[27]), .B1(
n3044), .Y(n3002) );
AOI22X1TS U4389 ( .A0(n3049), .A1(n3003), .B0(final_result_ieee[5]), .B1(
n4391), .Y(n3004) );
NAND2X1TS U4390 ( .A(n1921), .B(Data_array_SWR[18]), .Y(n3007) );
AOI21X1TS U4391 ( .A0(n3664), .A1(n3676), .B0(n3009), .Y(n3011) );
AOI22X1TS U4392 ( .A0(Data_array_SWR[14]), .A1(n1920), .B0(n1924), .B1(
Data_array_SWR[10]), .Y(n3010) );
OAI211X1TS U4393 ( .A0(n3012), .A1(n2398), .B0(n3011), .C0(n3010), .Y(n3040)
);
AOI22X1TS U4394 ( .A0(n3049), .A1(n3040), .B0(final_result_ieee[8]), .B1(
n4391), .Y(n3013) );
AOI22X1TS U4395 ( .A0(n3045), .A1(n3014), .B0(final_result_ieee[23]), .B1(
n3044), .Y(n3015) );
INVX2TS U4396 ( .A(n3016), .Y(n3625) );
INVX2TS U4397 ( .A(n3626), .Y(n3017) );
AOI22X1TS U4398 ( .A0(n3045), .A1(n3017), .B0(final_result_ieee[29]), .B1(
n3044), .Y(n3018) );
AOI22X1TS U4399 ( .A0(n3049), .A1(n3019), .B0(final_result_ieee[9]), .B1(
n4391), .Y(n3020) );
INVX2TS U4400 ( .A(n3021), .Y(n3026) );
AOI22X1TS U4401 ( .A0(n3027), .A1(n3023), .B0(n3022), .B1(n3030), .Y(n3025)
);
OAI211X1TS U4402 ( .A0(n3026), .A1(n2323), .B0(n3025), .C0(n3024), .Y(n3037)
);
INVX2TS U4403 ( .A(n3037), .Y(n3629) );
INVX2TS U4404 ( .A(n3027), .Y(n3028) );
INVX2TS U4405 ( .A(n3630), .Y(n3031) );
AOI22X1TS U4406 ( .A0(n3045), .A1(n3031), .B0(final_result_ieee[33]), .B1(
n3044), .Y(n3032) );
AOI22X1TS U4407 ( .A0(n3045), .A1(n3033), .B0(final_result_ieee[24]), .B1(
n3044), .Y(n3034) );
AOI22X1TS U4408 ( .A0(n3049), .A1(n3035), .B0(final_result_ieee[1]), .B1(
n4391), .Y(n3036) );
AOI22X1TS U4409 ( .A0(n3049), .A1(n3037), .B0(final_result_ieee[17]), .B1(
n4391), .Y(n3038) );
INVX2TS U4410 ( .A(n3040), .Y(n3638) );
INVX2TS U4411 ( .A(n3639), .Y(n3041) );
AOI22X1TS U4412 ( .A0(n3045), .A1(n3041), .B0(final_result_ieee[42]), .B1(
n3697), .Y(n3042) );
INVX2TS U4413 ( .A(n3043), .Y(n3621) );
AOI22X1TS U4414 ( .A0(n3045), .A1(n1900), .B0(final_result_ieee[28]), .B1(
n3044), .Y(n3046) );
AOI22X1TS U4415 ( .A0(n3049), .A1(n3048), .B0(final_result_ieee[0]), .B1(
n3697), .Y(n3050) );
AOI22X1TS U4416 ( .A0(intDX_EWSW[33]), .A1(n3113), .B0(DMP_EXP_EWSW[33]),
.B1(n3119), .Y(n3052) );
AOI22X1TS U4417 ( .A0(intDX_EWSW[43]), .A1(n3122), .B0(DMP_EXP_EWSW[43]),
.B1(n3147), .Y(n3053) );
AOI22X1TS U4418 ( .A0(intDX_EWSW[35]), .A1(n3122), .B0(DMP_EXP_EWSW[35]),
.B1(n3106), .Y(n3054) );
AOI22X1TS U4419 ( .A0(intDX_EWSW[45]), .A1(n3122), .B0(DMP_EXP_EWSW[45]),
.B1(n3119), .Y(n3055) );
AOI22X1TS U4420 ( .A0(intDX_EWSW[12]), .A1(n3066), .B0(DmP_EXP_EWSW[12]),
.B1(n3125), .Y(n3056) );
AOI222X1TS U4421 ( .A0(n3057), .A1(intDX_EWSW[52]), .B0(DMP_EXP_EWSW[52]),
.B1(n4432), .C0(intDY_EWSW[52]), .C1(n3148), .Y(n3058) );
INVX2TS U4422 ( .A(n3058), .Y(n1623) );
AOI22X1TS U4423 ( .A0(intDX_EWSW[20]), .A1(n3066), .B0(DmP_EXP_EWSW[20]),
.B1(n2310), .Y(n3059) );
AOI22X1TS U4424 ( .A0(intDX_EWSW[9]), .A1(n3126), .B0(DmP_EXP_EWSW[9]), .B1(
n3125), .Y(n3060) );
AOI22X1TS U4425 ( .A0(intDX_EWSW[21]), .A1(n3066), .B0(DmP_EXP_EWSW[21]),
.B1(n2907), .Y(n3061) );
AOI22X1TS U4426 ( .A0(intDX_EWSW[13]), .A1(n3066), .B0(DmP_EXP_EWSW[13]),
.B1(n3125), .Y(n3062) );
AOI22X1TS U4427 ( .A0(intDX_EWSW[19]), .A1(n3066), .B0(DmP_EXP_EWSW[19]),
.B1(n2928), .Y(n3063) );
AOI22X1TS U4428 ( .A0(intDX_EWSW[10]), .A1(n3126), .B0(DmP_EXP_EWSW[10]),
.B1(n3125), .Y(n3064) );
AOI22X1TS U4429 ( .A0(intDX_EWSW[6]), .A1(n3126), .B0(DmP_EXP_EWSW[6]), .B1(
n3125), .Y(n3065) );
AOI22X1TS U4430 ( .A0(intDX_EWSW[16]), .A1(n3066), .B0(DmP_EXP_EWSW[16]),
.B1(n2310), .Y(n3067) );
AOI22X1TS U4431 ( .A0(intDX_EWSW[2]), .A1(n3148), .B0(DmP_EXP_EWSW[2]), .B1(
n3547), .Y(n3069) );
AOI22X1TS U4432 ( .A0(intDX_EWSW[30]), .A1(n3078), .B0(DmP_EXP_EWSW[30]),
.B1(n3077), .Y(n3070) );
AOI22X1TS U4433 ( .A0(intDX_EWSW[28]), .A1(n3078), .B0(DmP_EXP_EWSW[28]),
.B1(n3077), .Y(n3071) );
AOI22X1TS U4434 ( .A0(intDX_EWSW[22]), .A1(n3078), .B0(DmP_EXP_EWSW[22]),
.B1(n2310), .Y(n3072) );
AOI22X1TS U4435 ( .A0(intDX_EWSW[24]), .A1(n3078), .B0(DmP_EXP_EWSW[24]),
.B1(n3077), .Y(n3073) );
AOI22X1TS U4436 ( .A0(intDX_EWSW[32]), .A1(n3087), .B0(DmP_EXP_EWSW[32]),
.B1(n3077), .Y(n3074) );
AOI22X1TS U4437 ( .A0(intDX_EWSW[4]), .A1(n3126), .B0(DmP_EXP_EWSW[4]), .B1(
n3125), .Y(n3075) );
AOI22X1TS U4438 ( .A0(intDX_EWSW[34]), .A1(n3087), .B0(DmP_EXP_EWSW[34]),
.B1(n3086), .Y(n3076) );
AOI22X1TS U4439 ( .A0(intDX_EWSW[27]), .A1(n3078), .B0(DmP_EXP_EWSW[27]),
.B1(n3077), .Y(n3079) );
AOI22X1TS U4440 ( .A0(intDX_EWSW[42]), .A1(n3090), .B0(DmP_EXP_EWSW[42]),
.B1(n3086), .Y(n3081) );
AOI22X1TS U4441 ( .A0(intDX_EWSW[41]), .A1(n3087), .B0(DmP_EXP_EWSW[41]),
.B1(n3086), .Y(n3082) );
AOI22X1TS U4442 ( .A0(intDX_EWSW[40]), .A1(n3087), .B0(DmP_EXP_EWSW[40]),
.B1(n3086), .Y(n3083) );
AOI22X1TS U4443 ( .A0(intDX_EWSW[48]), .A1(n3090), .B0(DmP_EXP_EWSW[48]),
.B1(n4397), .Y(n3084) );
AOI22X1TS U4444 ( .A0(intDX_EWSW[37]), .A1(n3087), .B0(DmP_EXP_EWSW[37]),
.B1(n3086), .Y(n3085) );
AOI22X1TS U4445 ( .A0(intDX_EWSW[38]), .A1(n3087), .B0(DmP_EXP_EWSW[38]),
.B1(n3086), .Y(n3088) );
AOI22X1TS U4446 ( .A0(intDX_EWSW[44]), .A1(n3090), .B0(DmP_EXP_EWSW[44]),
.B1(n4397), .Y(n3091) );
AOI22X1TS U4447 ( .A0(intDX_EWSW[12]), .A1(n2892), .B0(DMP_EXP_EWSW[12]),
.B1(n3110), .Y(n3093) );
AOI22X1TS U4448 ( .A0(intDX_EWSW[30]), .A1(n3113), .B0(DMP_EXP_EWSW[30]),
.B1(n3106), .Y(n3094) );
AOI22X1TS U4449 ( .A0(intDX_EWSW[28]), .A1(n3113), .B0(DMP_EXP_EWSW[28]),
.B1(n3106), .Y(n3095) );
AOI22X1TS U4450 ( .A0(intDX_EWSW[20]), .A1(n2892), .B0(DMP_EXP_EWSW[20]),
.B1(n3115), .Y(n3096) );
AOI22X1TS U4451 ( .A0(intDX_EWSW[22]), .A1(n2931), .B0(DMP_EXP_EWSW[22]),
.B1(n3115), .Y(n3097) );
AOI22X1TS U4452 ( .A0(intDX_EWSW[24]), .A1(n2931), .B0(DMP_EXP_EWSW[24]),
.B1(n3106), .Y(n3098) );
AOI22X1TS U4453 ( .A0(intDX_EWSW[9]), .A1(n2931), .B0(DMP_EXP_EWSW[9]), .B1(
n3110), .Y(n3099) );
AOI22X1TS U4454 ( .A0(intDX_EWSW[32]), .A1(n3113), .B0(DMP_EXP_EWSW[32]),
.B1(n3106), .Y(n3100) );
AOI22X1TS U4455 ( .A0(intDX_EWSW[34]), .A1(n3113), .B0(DMP_EXP_EWSW[34]),
.B1(n3119), .Y(n3101) );
AOI22X1TS U4456 ( .A0(intDX_EWSW[29]), .A1(n3113), .B0(DMP_EXP_EWSW[29]),
.B1(n3106), .Y(n3102) );
AOI22X1TS U4457 ( .A0(intDX_EWSW[13]), .A1(n2892), .B0(DMP_EXP_EWSW[13]),
.B1(n3115), .Y(n3103) );
AOI22X1TS U4458 ( .A0(intDX_EWSW[21]), .A1(n2896), .B0(DMP_EXP_EWSW[21]),
.B1(n3115), .Y(n3105) );
AOI22X1TS U4459 ( .A0(intDX_EWSW[27]), .A1(n3113), .B0(DMP_EXP_EWSW[27]),
.B1(n3106), .Y(n3107) );
AOI22X1TS U4460 ( .A0(intDX_EWSW[19]), .A1(n2896), .B0(DMP_EXP_EWSW[19]),
.B1(n3115), .Y(n3108) );
AOI22X1TS U4461 ( .A0(intDX_EWSW[42]), .A1(n3122), .B0(DMP_EXP_EWSW[42]),
.B1(n3119), .Y(n3109) );
AOI22X1TS U4462 ( .A0(intDX_EWSW[10]), .A1(n2892), .B0(DMP_EXP_EWSW[10]),
.B1(n3110), .Y(n3111) );
AOI22X1TS U4463 ( .A0(intDX_EWSW[41]), .A1(n3122), .B0(DMP_EXP_EWSW[41]),
.B1(n3119), .Y(n3112) );
AOI22X1TS U4464 ( .A0(intDX_EWSW[40]), .A1(n3113), .B0(DMP_EXP_EWSW[40]),
.B1(n3119), .Y(n3114) );
AOI22X1TS U4465 ( .A0(intDX_EWSW[16]), .A1(n2896), .B0(DMP_EXP_EWSW[16]),
.B1(n3115), .Y(n3116) );
AOI22X1TS U4466 ( .A0(intDX_EWSW[37]), .A1(n3122), .B0(DMP_EXP_EWSW[37]),
.B1(n3119), .Y(n3118) );
AOI22X1TS U4467 ( .A0(intDX_EWSW[38]), .A1(n3122), .B0(DMP_EXP_EWSW[38]),
.B1(n3119), .Y(n3120) );
AOI22X1TS U4468 ( .A0(intDX_EWSW[44]), .A1(n3122), .B0(DMP_EXP_EWSW[44]),
.B1(n3147), .Y(n3123) );
AOI22X1TS U4469 ( .A0(intDX_EWSW[5]), .A1(n3126), .B0(DmP_EXP_EWSW[5]), .B1(
n3125), .Y(n3124) );
AOI22X1TS U4470 ( .A0(intDX_EWSW[7]), .A1(n3126), .B0(DmP_EXP_EWSW[7]), .B1(
n3125), .Y(n3127) );
INVX2TS U4471 ( .A(n3129), .Y(n3131) );
NAND2X1TS U4472 ( .A(n3131), .B(n3130), .Y(n3134) );
INVX2TS U4473 ( .A(n3134), .Y(n3132) );
XOR2X1TS U4474 ( .A(n3135), .B(n3134), .Y(n3136) );
BUFX3TS U4475 ( .A(n4174), .Y(n3911) );
AOI22X1TS U4476 ( .A0(n3136), .A1(n3911), .B0(Raw_mant_NRM_SWR[53]), .B1(
n3747), .Y(n3137) );
AOI22X1TS U4477 ( .A0(intDX_EWSW[50]), .A1(n3144), .B0(DMP_EXP_EWSW[50]),
.B1(n3147), .Y(n3139) );
AOI22X1TS U4478 ( .A0(intDX_EWSW[0]), .A1(n3144), .B0(DMP_EXP_EWSW[0]), .B1(
n4432), .Y(n3140) );
AOI22X1TS U4479 ( .A0(intDX_EWSW[46]), .A1(n3144), .B0(DMP_EXP_EWSW[46]),
.B1(n3147), .Y(n3141) );
AOI22X1TS U4480 ( .A0(intDX_EWSW[48]), .A1(n3144), .B0(DMP_EXP_EWSW[48]),
.B1(n3147), .Y(n3142) );
AOI22X1TS U4481 ( .A0(intDX_EWSW[47]), .A1(n3144), .B0(DMP_EXP_EWSW[47]),
.B1(n3147), .Y(n3143) );
AOI22X1TS U4482 ( .A0(intDX_EWSW[51]), .A1(n3144), .B0(DMP_EXP_EWSW[51]),
.B1(n3147), .Y(n3145) );
AOI22X1TS U4483 ( .A0(intDY_EWSW[58]), .A1(n3148), .B0(DMP_EXP_EWSW[58]),
.B1(n3147), .Y(n3149) );
OAI22X1TS U4484 ( .A0(n3201), .A1(n4483), .B0(n4369), .B1(n4662), .Y(n3151)
);
INVX2TS U4485 ( .A(n3357), .Y(n3374) );
INVX2TS U4486 ( .A(n1995), .Y(n3584) );
OAI22X1TS U4487 ( .A0(n3201), .A1(n4533), .B0(n4369), .B1(n4663), .Y(n3153)
);
NOR2X1TS U4488 ( .A(n3365), .B(n4617), .Y(n3152) );
OA22X1TS U4489 ( .A0(n3584), .A1(n3232), .B0(n3233), .B1(n3558), .Y(n3155)
);
OAI211X1TS U4490 ( .A0(n3294), .A1(n3616), .B0(n3155), .C0(n3154), .Y(n1700)
);
OA22X1TS U4491 ( .A0(n3584), .A1(n3233), .B0(n3156), .B1(n3558), .Y(n3160)
);
OAI211X1TS U4492 ( .A0(n3232), .A1(n3616), .B0(n3160), .C0(n3159), .Y(n1699)
);
NAND2X1TS U4493 ( .A(n3380), .B(Raw_mant_NRM_SWR[26]), .Y(n3162) );
NAND2X1TS U4494 ( .A(n4374), .B(DmP_mant_SHT1_SW[26]), .Y(n3161) );
NAND3X1TS U4495 ( .A(n3163), .B(n3162), .C(n3161), .Y(n3596) );
INVX2TS U4496 ( .A(n3164), .Y(n3599) );
NAND2X1TS U4497 ( .A(n3361), .B(Raw_mant_NRM_SWR[25]), .Y(n3166) );
NAND2X1TS U4498 ( .A(n3382), .B(DmP_mant_SHT1_SW[27]), .Y(n3165) );
AOI22X1TS U4499 ( .A0(n1995), .A1(n3608), .B0(Data_array_SWR[27]), .B1(n3448), .Y(n3172) );
BUFX3TS U4500 ( .A(n3590), .Y(n3580) );
INVX2TS U4501 ( .A(n3201), .Y(n3375) );
NAND2X1TS U4502 ( .A(n3375), .B(Raw_mant_NRM_SWR[24]), .Y(n3170) );
NAND2X1TS U4503 ( .A(n3381), .B(Raw_mant_NRM_SWR[30]), .Y(n3169) );
NAND2X1TS U4504 ( .A(n3382), .B(DmP_mant_SHT1_SW[28]), .Y(n3168) );
INVX2TS U4505 ( .A(n3391), .Y(n3612) );
NAND2X1TS U4506 ( .A(n3580), .B(n3612), .Y(n3171) );
AOI22X1TS U4507 ( .A0(n3380), .A1(Raw_mant_NRM_SWR[28]), .B0(
DmP_mant_SHT1_SW[24]), .B1(n3382), .Y(n3173) );
BUFX3TS U4508 ( .A(n3551), .Y(n3441) );
NAND2X1TS U4509 ( .A(n3375), .B(Raw_mant_NRM_SWR[30]), .Y(n3178) );
NAND2X1TS U4510 ( .A(n3382), .B(DmP_mant_SHT1_SW[22]), .Y(n3177) );
AOI22X1TS U4511 ( .A0(n3441), .A1(n3589), .B0(Data_array_SWR[24]), .B1(n3425), .Y(n3184) );
NAND2X1TS U4512 ( .A(n3430), .B(Raw_mant_NRM_SWR[29]), .Y(n3181) );
NAND2X1TS U4513 ( .A(n3431), .B(DmP_mant_SHT1_SW[23]), .Y(n3180) );
NAND2X1TS U4514 ( .A(n3613), .B(n3552), .Y(n3183) );
OAI211X1TS U4515 ( .A0(n3600), .A1(n3555), .B0(n3184), .C0(n3183), .Y(n1722)
);
NAND2X1TS U4516 ( .A(n3430), .B(Raw_mant_NRM_SWR[4]), .Y(n3186) );
NAND2X1TS U4517 ( .A(n3696), .B(DmP_mant_SHT1_SW[48]), .Y(n3185) );
INVX2TS U4518 ( .A(n3256), .Y(n3199) );
NAND2X1TS U4519 ( .A(n3361), .B(Raw_mant_NRM_SWR[3]), .Y(n3189) );
NAND2X1TS U4520 ( .A(n3696), .B(DmP_mant_SHT1_SW[49]), .Y(n3188) );
BUFX3TS U4521 ( .A(n3588), .Y(n3423) );
NAND2X1TS U4522 ( .A(n3430), .B(Raw_mant_NRM_SWR[5]), .Y(n3192) );
NAND2X1TS U4523 ( .A(n3696), .B(DmP_mant_SHT1_SW[47]), .Y(n3191) );
AOI22X1TS U4524 ( .A0(n3580), .A1(n3340), .B0(n3423), .B1(n3396), .Y(n3198)
);
NAND2X1TS U4525 ( .A(n3380), .B(Raw_mant_NRM_SWR[6]), .Y(n3196) );
NAND2X1TS U4526 ( .A(n3357), .B(Raw_mant_NRM_SWR[48]), .Y(n3195) );
NAND2X1TS U4527 ( .A(n3323), .B(DmP_mant_SHT1_SW[46]), .Y(n3194) );
INVX2TS U4528 ( .A(n3400), .Y(n3200) );
AOI22X1TS U4529 ( .A0(n3441), .A1(n3200), .B0(Data_array_SWR[47]), .B1(n3439), .Y(n3197) );
INVX2TS U4530 ( .A(n3396), .Y(n3207) );
BUFX3TS U4531 ( .A(n3590), .Y(n3467) );
BUFX3TS U4532 ( .A(n3588), .Y(n3445) );
AOI22X1TS U4533 ( .A0(n3467), .A1(n3256), .B0(n3445), .B1(n3200), .Y(n3206)
);
BUFX3TS U4534 ( .A(n3551), .Y(n3470) );
INVX2TS U4535 ( .A(n3201), .Y(n3308) );
NAND2X1TS U4536 ( .A(n2785), .B(Raw_mant_NRM_SWR[7]), .Y(n3204) );
NAND2X1TS U4537 ( .A(n3357), .B(Raw_mant_NRM_SWR[47]), .Y(n3203) );
NAND2X1TS U4538 ( .A(n3376), .B(DmP_mant_SHT1_SW[45]), .Y(n3202) );
INVX2TS U4539 ( .A(n3403), .Y(n3395) );
AOI22X1TS U4540 ( .A0(n3470), .A1(n3395), .B0(Data_array_SWR[46]), .B1(n3448), .Y(n3205) );
OAI211X1TS U4541 ( .A0(n3207), .A1(n3459), .B0(n3206), .C0(n3205), .Y(n1745)
);
NAND2X1TS U4542 ( .A(n3361), .B(Raw_mant_NRM_SWR[17]), .Y(n3209) );
NAND2X1TS U4543 ( .A(n3376), .B(DmP_mant_SHT1_SW[35]), .Y(n3208) );
INVX2TS U4544 ( .A(n3352), .Y(n3222) );
NAND2X1TS U4545 ( .A(n3380), .B(Raw_mant_NRM_SWR[16]), .Y(n3213) );
NAND2X1TS U4546 ( .A(n3322), .B(Raw_mant_NRM_SWR[38]), .Y(n3212) );
NAND2X1TS U4547 ( .A(n3323), .B(DmP_mant_SHT1_SW[36]), .Y(n3211) );
INVX2TS U4548 ( .A(n3263), .Y(n3469) );
NAND2X1TS U4549 ( .A(n3430), .B(Raw_mant_NRM_SWR[18]), .Y(n3216) );
NAND2X1TS U4550 ( .A(n3381), .B(Raw_mant_NRM_SWR[36]), .Y(n3215) );
NAND2X1TS U4551 ( .A(n3376), .B(DmP_mant_SHT1_SW[34]), .Y(n3214) );
INVX2TS U4552 ( .A(n3356), .Y(n3226) );
AOI22X1TS U4553 ( .A0(n3467), .A1(n3469), .B0(n3445), .B1(n3226), .Y(n3221)
);
BUFX3TS U4554 ( .A(n3551), .Y(n3449) );
NAND2X1TS U4555 ( .A(n3380), .B(Raw_mant_NRM_SWR[19]), .Y(n3219) );
NAND2X1TS U4556 ( .A(n3322), .B(Raw_mant_NRM_SWR[35]), .Y(n3218) );
NAND2X1TS U4557 ( .A(n3323), .B(DmP_mant_SHT1_SW[33]), .Y(n3217) );
INVX2TS U4558 ( .A(n3332), .Y(n3351) );
AOI22X1TS U4559 ( .A0(n3449), .A1(n3351), .B0(Data_array_SWR[34]), .B1(n3448), .Y(n3220) );
BUFX3TS U4560 ( .A(n3590), .Y(n3447) );
NAND2X1TS U4561 ( .A(n3308), .B(Raw_mant_NRM_SWR[15]), .Y(n3224) );
NAND2X1TS U4562 ( .A(n3323), .B(DmP_mant_SHT1_SW[37]), .Y(n3223) );
AOI22X1TS U4563 ( .A0(n3447), .A1(n3464), .B0(n3423), .B1(n3352), .Y(n3228)
);
AOI22X1TS U4564 ( .A0(n3449), .A1(n3226), .B0(Data_array_SWR[35]), .B1(n3425), .Y(n3227) );
OAI211X1TS U4565 ( .A0(n3263), .A1(n3418), .B0(n3228), .C0(n3227), .Y(n1734)
);
NAND2X1TS U4566 ( .A(n3308), .B(Raw_mant_NRM_SWR[48]), .Y(n3231) );
NAND2X1TS U4567 ( .A(n3322), .B(Raw_mant_NRM_SWR[6]), .Y(n3230) );
NAND2X1TS U4568 ( .A(n3323), .B(DmP_mant_SHT1_SW[4]), .Y(n3229) );
INVX2TS U4569 ( .A(n3559), .Y(n3285) );
INVX2TS U4570 ( .A(n3232), .Y(n3295) );
AOI22X1TS U4571 ( .A0(n3447), .A1(n3285), .B0(n3423), .B1(n3295), .Y(n3236)
);
INVX2TS U4572 ( .A(n3233), .Y(n3234) );
AOI22X1TS U4573 ( .A0(n3449), .A1(n3234), .B0(Data_array_SWR[3]), .B1(n3425),
.Y(n3235) );
NAND2X1TS U4574 ( .A(n3308), .B(Raw_mant_NRM_SWR[37]), .Y(n3238) );
NAND2X1TS U4575 ( .A(n3382), .B(DmP_mant_SHT1_SW[15]), .Y(n3237) );
INVX2TS U4576 ( .A(n3581), .Y(n3251) );
NAND2X1TS U4577 ( .A(n3361), .B(Raw_mant_NRM_SWR[36]), .Y(n3241) );
NAND2X1TS U4578 ( .A(n4374), .B(DmP_mant_SHT1_SW[16]), .Y(n3240) );
NAND2X1TS U4579 ( .A(n2785), .B(Raw_mant_NRM_SWR[38]), .Y(n3244) );
NAND2X1TS U4580 ( .A(n3431), .B(DmP_mant_SHT1_SW[14]), .Y(n3243) );
AOI22X1TS U4581 ( .A0(n3447), .A1(n3578), .B0(n3423), .B1(n3573), .Y(n3250)
);
NAND2X1TS U4582 ( .A(n3308), .B(Raw_mant_NRM_SWR[39]), .Y(n3247) );
NAND2X1TS U4583 ( .A(n3376), .B(DmP_mant_SHT1_SW[13]), .Y(n3246) );
AOI22X1TS U4584 ( .A0(n3449), .A1(n3571), .B0(Data_array_SWR[15]), .B1(n3425), .Y(n3249) );
OAI211X1TS U4585 ( .A0(n3251), .A1(n3418), .B0(n3250), .C0(n3249), .Y(n1713)
);
INVX2TS U4586 ( .A(n3338), .Y(n3255) );
AOI22X1TS U4587 ( .A0(n3467), .A1(n3252), .B0(n3445), .B1(n3340), .Y(n3254)
);
AOI22X1TS U4588 ( .A0(n3470), .A1(n3256), .B0(Data_array_SWR[49]), .B1(n3468), .Y(n3253) );
OAI211X1TS U4589 ( .A0(n3255), .A1(n3459), .B0(n3254), .C0(n3253), .Y(n1748)
);
INVX2TS U4590 ( .A(n3340), .Y(n3259) );
BUFX3TS U4591 ( .A(n3590), .Y(n3603) );
AOI22X1TS U4592 ( .A0(n3603), .A1(n3338), .B0(n3588), .B1(n3256), .Y(n3258)
);
AOI22X1TS U4593 ( .A0(n3435), .A1(n3396), .B0(Data_array_SWR[48]), .B1(n3604), .Y(n3257) );
OAI211X1TS U4594 ( .A0(n3259), .A1(n3607), .B0(n3258), .C0(n3257), .Y(n1747)
);
INVX2TS U4595 ( .A(n3464), .Y(n3266) );
INVX2TS U4596 ( .A(n1995), .Y(n3594) );
NAND2X1TS U4597 ( .A(n2785), .B(Raw_mant_NRM_SWR[14]), .Y(n3262) );
NAND2X1TS U4598 ( .A(n3322), .B(Raw_mant_NRM_SWR[40]), .Y(n3261) );
NAND2X1TS U4599 ( .A(n3323), .B(DmP_mant_SHT1_SW[38]), .Y(n3260) );
OA22X1TS U4600 ( .A0(n3616), .A1(n3473), .B0(n3263), .B1(n3558), .Y(n3265)
);
AOI22X1TS U4601 ( .A0(n3435), .A1(n3352), .B0(Data_array_SWR[36]), .B1(n3604), .Y(n3264) );
INVX2TS U4602 ( .A(n3589), .Y(n3275) );
NAND2X1TS U4603 ( .A(n2785), .B(Raw_mant_NRM_SWR[31]), .Y(n3268) );
NAND2X1TS U4604 ( .A(n3382), .B(DmP_mant_SHT1_SW[21]), .Y(n3267) );
AOI22X1TS U4605 ( .A0(n3603), .A1(n3552), .B0(n3465), .B1(n3586), .Y(n3274)
);
NAND2X1TS U4606 ( .A(n3308), .B(Raw_mant_NRM_SWR[32]), .Y(n3271) );
NAND2X1TS U4607 ( .A(n4374), .B(DmP_mant_SHT1_SW[20]), .Y(n3270) );
AOI22X1TS U4608 ( .A0(n3435), .A1(n3587), .B0(Data_array_SWR[22]), .B1(n3468), .Y(n3273) );
OAI211X1TS U4609 ( .A0(n3275), .A1(n3607), .B0(n3274), .C0(n3273), .Y(n1720)
);
NAND2X1TS U4610 ( .A(n3308), .B(Raw_mant_NRM_SWR[46]), .Y(n3278) );
NAND2X1TS U4611 ( .A(n3322), .B(Raw_mant_NRM_SWR[8]), .Y(n3277) );
NAND2X1TS U4612 ( .A(n3323), .B(DmP_mant_SHT1_SW[6]), .Y(n3276) );
NAND2X1TS U4613 ( .A(n2785), .B(Raw_mant_NRM_SWR[45]), .Y(n3280) );
NAND2X1TS U4614 ( .A(n3431), .B(DmP_mant_SHT1_SW[7]), .Y(n3279) );
NAND2X1TS U4615 ( .A(n3375), .B(Raw_mant_NRM_SWR[47]), .Y(n3283) );
NAND2X1TS U4616 ( .A(n3376), .B(DmP_mant_SHT1_SW[5]), .Y(n3282) );
AOI22X1TS U4617 ( .A0(n3603), .A1(n3567), .B0(n3465), .B1(n3557), .Y(n3287)
);
AOI22X1TS U4618 ( .A0(n3435), .A1(n3285), .B0(Data_array_SWR[6]), .B1(n3468),
.Y(n3286) );
INVX2TS U4619 ( .A(n3567), .Y(n3293) );
NAND2X1TS U4620 ( .A(n3375), .B(Raw_mant_NRM_SWR[44]), .Y(n3289) );
NAND2X1TS U4621 ( .A(n3431), .B(DmP_mant_SHT1_SW[8]), .Y(n3288) );
INVX2TS U4622 ( .A(n3560), .Y(n3301) );
AOI22X1TS U4623 ( .A0(n3447), .A1(n3565), .B0(n3423), .B1(n3301), .Y(n3292)
);
AOI22X1TS U4624 ( .A0(n3449), .A1(n3557), .B0(Data_array_SWR[7]), .B1(n3468),
.Y(n3291) );
OAI211X1TS U4625 ( .A0(n3293), .A1(n3418), .B0(n3292), .C0(n3291), .Y(n1705)
);
INVX2TS U4626 ( .A(n3294), .Y(n3561) );
AOI22X1TS U4627 ( .A0(n3467), .A1(n3557), .B0(n3445), .B1(n3561), .Y(n3297)
);
AOI22X1TS U4628 ( .A0(n3470), .A1(n3295), .B0(n3439), .B1(Data_array_SWR[4]),
.Y(n3296) );
INVX2TS U4629 ( .A(n3565), .Y(n3304) );
NAND2X1TS U4630 ( .A(n3375), .B(Raw_mant_NRM_SWR[43]), .Y(n3300) );
NAND2X1TS U4631 ( .A(n3322), .B(Raw_mant_NRM_SWR[11]), .Y(n3299) );
NAND2X1TS U4632 ( .A(n3323), .B(DmP_mant_SHT1_SW[9]), .Y(n3298) );
INVX2TS U4633 ( .A(n3570), .Y(n3318) );
AOI22X1TS U4634 ( .A0(n3580), .A1(n3318), .B0(n3613), .B1(n3567), .Y(n3303)
);
AOI22X1TS U4635 ( .A0(n3441), .A1(n3301), .B0(Data_array_SWR[8]), .B1(n3425),
.Y(n3302) );
NAND2X1TS U4636 ( .A(n2785), .B(Raw_mant_NRM_SWR[41]), .Y(n3306) );
NAND2X1TS U4637 ( .A(n3376), .B(DmP_mant_SHT1_SW[11]), .Y(n3305) );
INVX2TS U4638 ( .A(n3574), .Y(n3317) );
NAND2X1TS U4639 ( .A(n3375), .B(Raw_mant_NRM_SWR[40]), .Y(n3310) );
NAND2X1TS U4640 ( .A(n3431), .B(DmP_mant_SHT1_SW[12]), .Y(n3309) );
NAND2X1TS U4641 ( .A(n3375), .B(Raw_mant_NRM_SWR[42]), .Y(n3313) );
NAND2X1TS U4642 ( .A(n3376), .B(DmP_mant_SHT1_SW[10]), .Y(n3312) );
AOI22X1TS U4643 ( .A0(n3447), .A1(n3572), .B0(n3423), .B1(n3566), .Y(n3316)
);
AOI22X1TS U4644 ( .A0(n3449), .A1(n3318), .B0(Data_array_SWR[11]), .B1(n3448), .Y(n3315) );
OAI211X1TS U4645 ( .A0(n3317), .A1(n3418), .B0(n3316), .C0(n3315), .Y(n1709)
);
INVX2TS U4646 ( .A(n3566), .Y(n3321) );
AOI22X1TS U4647 ( .A0(n3603), .A1(n3574), .B0(n3465), .B1(n3318), .Y(n3320)
);
AOI22X1TS U4648 ( .A0(n3435), .A1(n3565), .B0(Data_array_SWR[10]), .B1(n3468), .Y(n3319) );
NAND2X1TS U4649 ( .A(n3380), .B(Raw_mant_NRM_SWR[20]), .Y(n3326) );
NAND2X1TS U4650 ( .A(n3322), .B(Raw_mant_NRM_SWR[34]), .Y(n3325) );
NAND2X1TS U4651 ( .A(n3376), .B(DmP_mant_SHT1_SW[32]), .Y(n3324) );
OA22X1TS U4652 ( .A0(n3616), .A1(n3356), .B0(n3344), .B1(n3558), .Y(n3331)
);
NAND2X1TS U4653 ( .A(n3361), .B(Raw_mant_NRM_SWR[21]), .Y(n3328) );
NAND2X1TS U4654 ( .A(n3376), .B(DmP_mant_SHT1_SW[31]), .Y(n3327) );
AOI22X1TS U4655 ( .A0(n3435), .A1(n3602), .B0(Data_array_SWR[33]), .B1(n3604), .Y(n3330) );
AOI22X1TS U4656 ( .A0(n3580), .A1(n3351), .B0(n3423), .B1(n3602), .Y(n3337)
);
NAND2X1TS U4657 ( .A(n3361), .B(Raw_mant_NRM_SWR[22]), .Y(n3334) );
NAND2X1TS U4658 ( .A(n3696), .B(DmP_mant_SHT1_SW[30]), .Y(n3333) );
NAND3X1TS U4659 ( .A(n3335), .B(n3334), .C(n3333), .Y(n3601) );
AOI22X1TS U4660 ( .A0(n3441), .A1(n3601), .B0(Data_array_SWR[32]), .B1(n3425), .Y(n3336) );
OAI211X1TS U4661 ( .A0(n3344), .A1(n3418), .B0(n3337), .C0(n3336), .Y(n1730)
);
AOI22X1TS U4662 ( .A0(n3467), .A1(n1930), .B0(n3445), .B1(n3338), .Y(n3342)
);
AOI22X1TS U4663 ( .A0(n3470), .A1(n3340), .B0(Data_array_SWR[50]), .B1(n3448), .Y(n3341) );
INVX2TS U4664 ( .A(n3602), .Y(n3350) );
INVX2TS U4665 ( .A(n3344), .Y(n3353) );
AOI22X1TS U4666 ( .A0(n3447), .A1(n3353), .B0(n3445), .B1(n3601), .Y(n3349)
);
NAND2X1TS U4667 ( .A(n3430), .B(Raw_mant_NRM_SWR[23]), .Y(n3346) );
NAND2X1TS U4668 ( .A(n4374), .B(DmP_mant_SHT1_SW[29]), .Y(n3345) );
AOI22X1TS U4669 ( .A0(n3449), .A1(n3610), .B0(Data_array_SWR[31]), .B1(n3448), .Y(n3348) );
OAI211X1TS U4670 ( .A0(n3350), .A1(n3418), .B0(n3349), .C0(n3348), .Y(n1729)
);
AOI22X1TS U4671 ( .A0(n3467), .A1(n3352), .B0(n3465), .B1(n3351), .Y(n3355)
);
AOI22X1TS U4672 ( .A0(n3470), .A1(n3353), .B0(n1937), .B1(n3468), .Y(n3354)
);
NAND2X1TS U4673 ( .A(n3380), .B(Raw_mant_NRM_SWR[8]), .Y(n3360) );
NAND2X1TS U4674 ( .A(n3357), .B(Raw_mant_NRM_SWR[46]), .Y(n3359) );
NAND2X1TS U4675 ( .A(n3323), .B(DmP_mant_SHT1_SW[44]), .Y(n3358) );
NAND2X1TS U4676 ( .A(n3430), .B(Raw_mant_NRM_SWR[9]), .Y(n3363) );
NAND2X1TS U4677 ( .A(n3431), .B(DmP_mant_SHT1_SW[43]), .Y(n3362) );
AOI22X1TS U4678 ( .A0(n3580), .A1(n3395), .B0(n3613), .B1(n3455), .Y(n3370)
);
NAND2X1TS U4679 ( .A(n3361), .B(Raw_mant_NRM_SWR[10]), .Y(n3367) );
NAND2X1TS U4680 ( .A(n3431), .B(DmP_mant_SHT1_SW[42]), .Y(n3366) );
AOI22X1TS U4681 ( .A0(n3441), .A1(n3453), .B0(Data_array_SWR[43]), .B1(n3439), .Y(n3369) );
NAND2X1TS U4682 ( .A(n3430), .B(Raw_mant_NRM_SWR[34]), .Y(n3372) );
NAND2X1TS U4683 ( .A(n4374), .B(DmP_mant_SHT1_SW[18]), .Y(n3371) );
INVX2TS U4684 ( .A(n3579), .Y(n3388) );
NAND2X1TS U4685 ( .A(n3308), .B(Raw_mant_NRM_SWR[33]), .Y(n3378) );
NAND2X1TS U4686 ( .A(n3431), .B(DmP_mant_SHT1_SW[19]), .Y(n3377) );
NAND2X1TS U4687 ( .A(n3380), .B(Raw_mant_NRM_SWR[35]), .Y(n3385) );
NAND2X1TS U4688 ( .A(n3381), .B(Raw_mant_NRM_SWR[19]), .Y(n3384) );
NAND2X1TS U4689 ( .A(n4374), .B(DmP_mant_SHT1_SW[17]), .Y(n3383) );
INVX2TS U4690 ( .A(n3585), .Y(n3424) );
AOI22X1TS U4691 ( .A0(n3603), .A1(n3591), .B0(n3465), .B1(n3424), .Y(n3387)
);
AOI22X1TS U4692 ( .A0(n3435), .A1(n3578), .B0(Data_array_SWR[18]), .B1(n3604), .Y(n3386) );
AOI22X1TS U4693 ( .A0(n3447), .A1(n3610), .B0(n3423), .B1(n3608), .Y(n3390)
);
AOI22X1TS U4694 ( .A0(n3441), .A1(n3596), .B0(Data_array_SWR[28]), .B1(n3425), .Y(n3389) );
INVX2TS U4695 ( .A(n3572), .Y(n3394) );
AOI22X1TS U4696 ( .A0(n3580), .A1(n3571), .B0(n3423), .B1(n3574), .Y(n3393)
);
AOI22X1TS U4697 ( .A0(n3441), .A1(n3566), .B0(Data_array_SWR[12]), .B1(n3425), .Y(n3392) );
AOI22X1TS U4698 ( .A0(n3467), .A1(n3396), .B0(n3465), .B1(n3395), .Y(n3398)
);
INVX2TS U4699 ( .A(n3399), .Y(n3446) );
AOI22X1TS U4700 ( .A0(n3470), .A1(n3446), .B0(Data_array_SWR[45]), .B1(n3468), .Y(n3397) );
OAI211X1TS U4701 ( .A0(n3400), .A1(n3459), .B0(n3398), .C0(n3397), .Y(n1744)
);
OA22X1TS U4702 ( .A0(n3616), .A1(n3400), .B0(n3399), .B1(n3558), .Y(n3402)
);
AOI22X1TS U4703 ( .A0(n3435), .A1(n3455), .B0(Data_array_SWR[44]), .B1(n3604), .Y(n3401) );
NAND2X1TS U4704 ( .A(n3430), .B(Raw_mant_NRM_SWR[13]), .Y(n3405) );
NAND2X1TS U4705 ( .A(n3431), .B(DmP_mant_SHT1_SW[39]), .Y(n3404) );
INVX2TS U4706 ( .A(n3466), .Y(n3412) );
NAND2X1TS U4707 ( .A(n3361), .B(Raw_mant_NRM_SWR[12]), .Y(n3408) );
NAND2X1TS U4708 ( .A(n3431), .B(DmP_mant_SHT1_SW[40]), .Y(n3407) );
INVX2TS U4709 ( .A(n3473), .Y(n3440) );
AOI22X1TS U4710 ( .A0(n3467), .A1(n3456), .B0(n3445), .B1(n3440), .Y(n3411)
);
AOI22X1TS U4711 ( .A0(n3470), .A1(n3464), .B0(n1944), .B1(n3448), .Y(n3410)
);
INVX2TS U4712 ( .A(n3552), .Y(n3415) );
AOI22X1TS U4713 ( .A0(n3447), .A1(n1904), .B0(n3445), .B1(n3589), .Y(n3414)
);
AOI22X1TS U4714 ( .A0(n3449), .A1(n3586), .B0(Data_array_SWR[23]), .B1(n3448), .Y(n3413) );
OAI211X1TS U4715 ( .A0(n3415), .A1(n3418), .B0(n3414), .C0(n3413), .Y(n1721)
);
INVX2TS U4716 ( .A(n3591), .Y(n3419) );
AOI22X1TS U4717 ( .A0(n3447), .A1(n3587), .B0(n3445), .B1(n3579), .Y(n3417)
);
AOI22X1TS U4718 ( .A0(n3449), .A1(n3424), .B0(Data_array_SWR[19]), .B1(n3448), .Y(n3416) );
OAI211X1TS U4719 ( .A0(n3419), .A1(n3418), .B0(n3417), .C0(n3416), .Y(n1717)
);
INVX2TS U4720 ( .A(n3587), .Y(n3422) );
AOI22X1TS U4721 ( .A0(n3580), .A1(n3586), .B0(n3613), .B1(n3591), .Y(n3421)
);
AOI22X1TS U4722 ( .A0(n3441), .A1(n3579), .B0(Data_array_SWR[20]), .B1(n3425), .Y(n3420) );
INVX2TS U4723 ( .A(n3578), .Y(n3428) );
AOI22X1TS U4724 ( .A0(n3580), .A1(n3424), .B0(n3423), .B1(n3581), .Y(n3427)
);
AOI22X1TS U4725 ( .A0(n3441), .A1(n3573), .B0(Data_array_SWR[16]), .B1(n3425), .Y(n3426) );
NAND2X1TS U4726 ( .A(n3430), .B(Raw_mant_NRM_SWR[11]), .Y(n3433) );
NAND2X1TS U4727 ( .A(n3376), .B(DmP_mant_SHT1_SW[41]), .Y(n3432) );
INVX2TS U4728 ( .A(n3454), .Y(n3438) );
AOI22X1TS U4729 ( .A0(n3603), .A1(n3453), .B0(n3588), .B1(n3456), .Y(n3437)
);
AOI22X1TS U4730 ( .A0(n3435), .A1(n3466), .B0(Data_array_SWR[40]), .B1(n3604), .Y(n3436) );
OAI211X1TS U4731 ( .A0(n3438), .A1(n3607), .B0(n3437), .C0(n3436), .Y(n1739)
);
INVX2TS U4732 ( .A(n3456), .Y(n3444) );
AOI22X1TS U4733 ( .A0(n3580), .A1(n3454), .B0(n3613), .B1(n3466), .Y(n3443)
);
AOI22X1TS U4734 ( .A0(n3441), .A1(n3440), .B0(Data_array_SWR[39]), .B1(n3439), .Y(n3442) );
INVX2TS U4735 ( .A(n3455), .Y(n3452) );
AOI22X1TS U4736 ( .A0(n3447), .A1(n3446), .B0(n3445), .B1(n3453), .Y(n3451)
);
AOI22X1TS U4737 ( .A0(n3449), .A1(n3454), .B0(n1946), .B1(n3448), .Y(n3450)
);
INVX2TS U4738 ( .A(n3453), .Y(n3460) );
AOI22X1TS U4739 ( .A0(n3467), .A1(n3455), .B0(n3465), .B1(n3454), .Y(n3458)
);
AOI22X1TS U4740 ( .A0(n3470), .A1(n3456), .B0(n1948), .B1(n3468), .Y(n3457)
);
INVX2TS U4741 ( .A(n3573), .Y(n3463) );
AOI22X1TS U4742 ( .A0(n3603), .A1(n3581), .B0(n3465), .B1(n3571), .Y(n3462)
);
AOI22X1TS U4743 ( .A0(n3470), .A1(n3572), .B0(Data_array_SWR[14]), .B1(n3468), .Y(n3461) );
OAI211X1TS U4744 ( .A0(n3463), .A1(n3607), .B0(n3462), .C0(n3461), .Y(n1712)
);
AOI22X1TS U4745 ( .A0(n3467), .A1(n3466), .B0(n3465), .B1(n3464), .Y(n3472)
);
AOI22X1TS U4746 ( .A0(n3470), .A1(n3469), .B0(Data_array_SWR[37]), .B1(n3468), .Y(n3471) );
OAI211X1TS U4747 ( .A0(n3473), .A1(n3607), .B0(n3472), .C0(n3471), .Y(n1736)
);
AOI22X1TS U4748 ( .A0(n4516), .A1(intDX_EWSW[11]), .B0(n4581), .B1(
intDX_EWSW[50]), .Y(n3474) );
AOI221X1TS U4749 ( .A0(intDY_EWSW[49]), .A1(n4584), .B0(n4517), .B1(
intDX_EWSW[49]), .C0(n3475), .Y(n3489) );
OAI22X1TS U4750 ( .A0(n1987), .A1(intDX_EWSW[53]), .B0(n4482), .B1(
intDX_EWSW[54]), .Y(n3476) );
AOI221X1TS U4751 ( .A0(n1987), .A1(intDX_EWSW[53]), .B0(intDX_EWSW[54]),
.B1(n4482), .C0(n3476), .Y(n3488) );
OAI22X1TS U4752 ( .A0(n4603), .A1(intDX_EWSW[51]), .B0(n4518), .B1(
intDX_EWSW[52]), .Y(n3477) );
AOI22X1TS U4753 ( .A0(n4582), .A1(intDY_EWSW[58]), .B0(n4503), .B1(
intDX_EWSW[57]), .Y(n3478) );
AOI22X1TS U4754 ( .A0(n1988), .A1(intDX_EWSW[56]), .B0(n4481), .B1(
intDX_EWSW[55]), .Y(n3479) );
OAI221XLTS U4755 ( .A0(n1988), .A1(intDX_EWSW[56]), .B0(n4481), .B1(
intDX_EWSW[55]), .C0(n3479), .Y(n3484) );
AOI22X1TS U4756 ( .A0(n4504), .A1(intDY_EWSW[62]), .B0(n4568), .B1(
intDY_EWSW[61]), .Y(n3480) );
AOI22X1TS U4757 ( .A0(n4583), .A1(intDY_EWSW[60]), .B0(n4524), .B1(
intDY_EWSW[59]), .Y(n3481) );
NOR4X1TS U4758 ( .A(n3485), .B(n3484), .C(n3483), .D(n3482), .Y(n3486) );
OAI22X1TS U4759 ( .A0(n4600), .A1(intDX_EWSW[42]), .B0(n4515), .B1(
intDX_EWSW[43]), .Y(n3490) );
OAI22X1TS U4760 ( .A0(n4599), .A1(intDX_EWSW[40]), .B0(n4514), .B1(
intDX_EWSW[41]), .Y(n3491) );
AOI221X1TS U4761 ( .A0(n4599), .A1(intDX_EWSW[40]), .B0(intDX_EWSW[41]),
.B1(n4514), .C0(n3491), .Y(n3496) );
OAI22X1TS U4762 ( .A0(n4602), .A1(intDX_EWSW[46]), .B0(n4528), .B1(
intDX_EWSW[47]), .Y(n3492) );
OAI22X1TS U4763 ( .A0(n4601), .A1(intDX_EWSW[44]), .B0(n4527), .B1(
intDX_EWSW[45]), .Y(n3493) );
OAI22X1TS U4764 ( .A0(n4597), .A1(intDX_EWSW[34]), .B0(n4513), .B1(
intDX_EWSW[35]), .Y(n3498) );
OAI22X1TS U4765 ( .A0(n4595), .A1(intDX_EWSW[1]), .B0(n4512), .B1(
intDX_EWSW[33]), .Y(n3499) );
OAI22X1TS U4766 ( .A0(n4596), .A1(intDX_EWSW[38]), .B0(n4526), .B1(
intDX_EWSW[39]), .Y(n3500) );
AOI221X1TS U4767 ( .A0(n4596), .A1(intDX_EWSW[38]), .B0(intDX_EWSW[39]),
.B1(n4526), .C0(n3500), .Y(n3503) );
OAI22X1TS U4768 ( .A0(n4598), .A1(intDX_EWSW[36]), .B0(n4525), .B1(
intDX_EWSW[37]), .Y(n3501) );
AOI22X1TS U4769 ( .A0(n4502), .A1(intDX_EWSW[31]), .B0(n4564), .B1(
intDX_EWSW[30]), .Y(n3506) );
AOI22X1TS U4770 ( .A0(n4501), .A1(intDX_EWSW[29]), .B0(n4559), .B1(
intDX_EWSW[20]), .Y(n3507) );
AOI22X1TS U4771 ( .A0(n4495), .A1(intDX_EWSW[27]), .B0(n4562), .B1(
intDX_EWSW[26]), .Y(n3508) );
AOI22X1TS U4772 ( .A0(n4494), .A1(intDX_EWSW[25]), .B0(n4565), .B1(
intDX_EWSW[32]), .Y(n3509) );
NOR4X1TS U4773 ( .A(n3513), .B(n3512), .C(n3511), .D(n3510), .Y(n3541) );
AOI22X1TS U4774 ( .A0(n4500), .A1(intDX_EWSW[23]), .B0(n4560), .B1(
intDX_EWSW[22]), .Y(n3514) );
AOI22X1TS U4775 ( .A0(n4499), .A1(intDX_EWSW[21]), .B0(n4566), .B1(
intDX_EWSW[48]), .Y(n3515) );
AOI22X1TS U4776 ( .A0(n4493), .A1(intDX_EWSW[19]), .B0(n4558), .B1(
intDX_EWSW[18]), .Y(n3516) );
AOI22X1TS U4777 ( .A0(n4492), .A1(intDX_EWSW[17]), .B0(n4561), .B1(
intDX_EWSW[24]), .Y(n3517) );
NOR4X1TS U4778 ( .A(n3521), .B(n3520), .C(n3519), .D(n3518), .Y(n3540) );
AOI22X1TS U4779 ( .A0(n4498), .A1(intDX_EWSW[15]), .B0(n4557), .B1(
intDX_EWSW[14]), .Y(n3522) );
AOI22X1TS U4780 ( .A0(n4497), .A1(intDX_EWSW[13]), .B0(n4554), .B1(
intDX_EWSW[4]), .Y(n3523) );
AOI22X1TS U4781 ( .A0(n4507), .A1(intDX_EWSW[10]), .B0(n4556), .B1(
intDX_EWSW[12]), .Y(n3524) );
AOI22X1TS U4782 ( .A0(n4491), .A1(intDX_EWSW[9]), .B0(n4578), .B1(
intDX_EWSW[16]), .Y(n3525) );
NOR4X1TS U4783 ( .A(n3529), .B(n3528), .C(n3527), .D(n3526), .Y(n3539) );
AOI22X1TS U4784 ( .A0(n4508), .A1(intDX_EWSW[7]), .B0(n4579), .B1(
intDX_EWSW[6]), .Y(n3530) );
AOI22X1TS U4785 ( .A0(n4509), .A1(intDX_EWSW[5]), .B0(n4563), .B1(
intDX_EWSW[28]), .Y(n3531) );
AOI22X1TS U4786 ( .A0(n4496), .A1(intDX_EWSW[3]), .B0(n4553), .B1(
intDX_EWSW[2]), .Y(n3532) );
AOI22X1TS U4787 ( .A0(n4490), .A1(intDX_EWSW[0]), .B0(n4555), .B1(
intDX_EWSW[8]), .Y(n3533) );
NOR4X1TS U4788 ( .A(n3537), .B(n3536), .C(n3535), .D(n3534), .Y(n3538) );
CLKXOR2X2TS U4789 ( .A(intDY_EWSW[63]), .B(intAS), .Y(n4431) );
INVX2TS U4790 ( .A(n4431), .Y(n3550) );
AOI22X1TS U4791 ( .A0(intDX_EWSW[63]), .A1(n3548), .B0(SIGN_FLAG_EXP), .B1(
n3547), .Y(n3549) );
OAI31X1TS U4792 ( .A0(n4434), .A1(n3550), .A2(n4467), .B0(n3549), .Y(n1610)
);
BUFX3TS U4793 ( .A(n3551), .Y(n3609) );
AOI22X1TS U4794 ( .A0(n3609), .A1(n3552), .B0(Data_array_SWR[25]), .B1(n3611), .Y(n3554) );
NAND2X1TS U4795 ( .A(n3613), .B(n1904), .Y(n3553) );
OAI211X1TS U4796 ( .A0(n3556), .A1(n3555), .B0(n3554), .C0(n3553), .Y(n1723)
);
INVX2TS U4797 ( .A(n3557), .Y(n3564) );
OA22X1TS U4798 ( .A0(n3616), .A1(n3560), .B0(n3559), .B1(n3558), .Y(n3563)
);
AOI22X1TS U4799 ( .A0(n3609), .A1(n3561), .B0(Data_array_SWR[5]), .B1(n3611),
.Y(n3562) );
AOI22X1TS U4800 ( .A0(n3590), .A1(n3566), .B0(n3588), .B1(n3565), .Y(n3569)
);
AOI22X1TS U4801 ( .A0(n3609), .A1(n3567), .B0(Data_array_SWR[9]), .B1(n3611),
.Y(n3568) );
INVX2TS U4802 ( .A(n3571), .Y(n3577) );
AOI22X1TS U4803 ( .A0(n3603), .A1(n3573), .B0(n3588), .B1(n3572), .Y(n3576)
);
AOI22X1TS U4804 ( .A0(n3609), .A1(n3574), .B0(Data_array_SWR[13]), .B1(n3611), .Y(n3575) );
OAI211X1TS U4805 ( .A0(n3577), .A1(n3594), .B0(n3576), .C0(n3575), .Y(n1711)
);
AOI22X1TS U4806 ( .A0(n3580), .A1(n3579), .B0(n3613), .B1(n3578), .Y(n3583)
);
AOI22X1TS U4807 ( .A0(n3609), .A1(n3581), .B0(Data_array_SWR[17]), .B1(n3611), .Y(n3582) );
INVX2TS U4808 ( .A(n3586), .Y(n3595) );
AOI22X1TS U4809 ( .A0(n3590), .A1(n3589), .B0(n3588), .B1(n3587), .Y(n3593)
);
AOI22X1TS U4810 ( .A0(n3609), .A1(n3591), .B0(Data_array_SWR[21]), .B1(n3611), .Y(n3592) );
AOI22X1TS U4811 ( .A0(n3603), .A1(n3608), .B0(Data_array_SWR[26]), .B1(n3604), .Y(n3598) );
NAND2X1TS U4812 ( .A(n1995), .B(n3596), .Y(n3597) );
INVX2TS U4813 ( .A(n3601), .Y(n3617) );
AOI22X1TS U4814 ( .A0(n3603), .A1(n3602), .B0(n3609), .B1(n3612), .Y(n3606)
);
AOI22X1TS U4815 ( .A0(n3613), .A1(n3610), .B0(Data_array_SWR[30]), .B1(n3604), .Y(n3605) );
OAI211X1TS U4816 ( .A0(n3617), .A1(n3607), .B0(n3606), .C0(n3605), .Y(n1728)
);
AOI22X1TS U4817 ( .A0(n1995), .A1(n3610), .B0(n3609), .B1(n3608), .Y(n3615)
);
AOI22X1TS U4818 ( .A0(n3613), .A1(n3612), .B0(Data_array_SWR[29]), .B1(n3611), .Y(n3614) );
OAI211X1TS U4819 ( .A0(n3617), .A1(n3616), .B0(n3615), .C0(n3614), .Y(n1727)
);
OAI21XLTS U4820 ( .A0(Shift_reg_FLAGS_7[1]), .A1(n1918), .B0(n3618), .Y(
n1276) );
INVX2TS U4821 ( .A(n3631), .Y(n3670) );
INVX2TS U4822 ( .A(n3624), .Y(n3668) );
BUFX3TS U4823 ( .A(n4477), .Y(n3641) );
OAI222X1TS U4824 ( .A0(n3670), .A1(n3620), .B0(n3645), .B1(n3619), .C0(n4633), .C1(n3641), .Y(n1130) );
BUFX3TS U4825 ( .A(n4477), .Y(n3637) );
OAI222X1TS U4826 ( .A0(n3668), .A1(n3620), .B0(n3643), .B1(n3619), .C0(n4632), .C1(n3637), .Y(n1128) );
OAI222X1TS U4827 ( .A0(n3666), .A1(n3630), .B0(n3640), .B1(n3629), .C0(n4649), .C1(n3637), .Y(n1137) );
OAI222X1TS U4828 ( .A0(n3645), .A1(n3623), .B0(n3643), .B1(n3622), .C0(n4646), .C1(n3641), .Y(n1127) );
OAI222X1TS U4829 ( .A0(n3643), .A1(n3626), .B0(n3668), .B1(n3625), .C0(n4648), .C1(n3637), .Y(n1133) );
OAI222X1TS U4830 ( .A0(n3640), .A1(n1935), .B0(n3666), .B1(n3621), .C0(n4631), .C1(n3641), .Y(n1126) );
OAI222X1TS U4831 ( .A0(n3666), .A1(n1935), .B0(n3668), .B1(n3621), .C0(n4634), .C1(n3637), .Y(n1132) );
OAI222X1TS U4832 ( .A0(n3670), .A1(n3623), .B0(n3645), .B1(n3622), .C0(n4647), .C1(n3637), .Y(n1131) );
INVX2TS U4833 ( .A(n3624), .Y(n3640) );
OAI222X1TS U4834 ( .A0(n3645), .A1(n3626), .B0(n3666), .B1(n3625), .C0(n4645), .C1(n3641), .Y(n1125) );
OAI222X1TS U4835 ( .A0(n3645), .A1(n3630), .B0(n3670), .B1(n3629), .C0(n4644), .C1(n3641), .Y(n1121) );
INVX2TS U4836 ( .A(n3631), .Y(n3666) );
OAI222X1TS U4837 ( .A0(n3668), .A1(n1936), .B0(n3666), .B1(n3632), .C0(n4639), .C1(n3641), .Y(n1105) );
OAI222X1TS U4838 ( .A0(n3640), .A1(n3634), .B0(n3670), .B1(n3633), .C0(n4640), .C1(n4477), .Y(n1109) );
OAI222X1TS U4839 ( .A0(n3640), .A1(n3636), .B0(n3670), .B1(n3635), .C0(n4658), .C1(n3641), .Y(n1110) );
INVX2TS U4840 ( .A(n4330), .Y(n3650) );
AOI21X1TS U4841 ( .A0(n3650), .A1(n3649), .B0(n2369), .Y(n3667) );
INVX2TS U4842 ( .A(n4332), .Y(n3665) );
AOI22X1TS U4843 ( .A0(n3652), .A1(Data_array_SWR[24]), .B0(n2869), .B1(
Data_array_SWR[20]), .Y(n3656) );
AOI22X1TS U4844 ( .A0(n3654), .A1(Data_array_SWR[28]), .B0(n3653), .B1(
Data_array_SWR[16]), .Y(n3655) );
AOI22X1TS U4845 ( .A0(n1934), .A1(Data_array_SWR[12]), .B0(n1922), .B1(
Data_array_SWR[8]), .Y(n3658) );
AOI22X1TS U4846 ( .A0(n1924), .A1(Data_array_SWR[0]), .B0(n3660), .B1(n4302),
.Y(n3661) );
OAI2BB1X1TS U4847 ( .A0N(Data_array_SWR[4]), .A1N(n1920), .B0(n3661), .Y(
n3662) );
AOI211X1TS U4848 ( .A0(n3665), .A1(n3664), .B0(n3663), .C0(n3662), .Y(n3669)
);
OAI222X1TS U4849 ( .A0(n3666), .A1(n3667), .B0(n4668), .B1(n1913), .C0(n3668), .C1(n3669), .Y(n1156) );
OAI222X1TS U4850 ( .A0(n3643), .A1(n3669), .B0(n4659), .B1(n4286), .C0(n3640), .C1(n3667), .Y(n1102) );
OAI2BB2XLTS U4851 ( .B0(n3671), .B1(n4393), .A0N(final_result_ieee[63]),
.A1N(n4377), .Y(n1270) );
AOI21X1TS U4852 ( .A0(n3675), .A1(n3689), .B0(n3674), .Y(n4345) );
OAI2BB2XLTS U4853 ( .B0(n3680), .B1(n4345), .A0N(final_result_ieee[11]),
.A1N(n4377), .Y(n1181) );
AOI21X1TS U4854 ( .A0(n3679), .A1(n3689), .B0(n3678), .Y(n4346) );
OAI2BB2XLTS U4855 ( .B0(n3680), .B1(n4346), .A0N(final_result_ieee[10]),
.A1N(n4377), .Y(n1179) );
AOI21X1TS U4856 ( .A0(n3684), .A1(n1927), .B0(n3683), .Y(n4344) );
OAI2BB2XLTS U4857 ( .B0(n3693), .B1(n4344), .A0N(final_result_ieee[12]),
.A1N(n4391), .Y(n1183) );
AOI21X1TS U4858 ( .A0(n3690), .A1(n3689), .B0(n3688), .Y(n4343) );
OAI2BB2XLTS U4859 ( .B0(n3693), .B1(n4343), .A0N(final_result_ieee[13]),
.A1N(n4391), .Y(n1185) );
INVX2TS U4860 ( .A(n3691), .Y(n3692) );
OAI2BB2XLTS U4861 ( .B0(n3693), .B1(n3692), .A0N(final_result_ieee[62]),
.A1N(n4377), .Y(n1676) );
NOR2XLTS U4862 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n3694) );
AOI32X4TS U4863 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n3694), .B1(n4567), .Y(n4399)
);
MXI2X1TS U4864 ( .A(n4475), .B(n4458), .S0(n4399), .Y(n1888) );
MXI2X1TS U4865 ( .A(n3696), .B(n3747), .S0(n4399), .Y(n1885) );
MXI2X1TS U4866 ( .A(n3697), .B(n3696), .S0(n4399), .Y(n1884) );
BUFX3TS U4867 ( .A(n4286), .Y(n4452) );
CLKBUFX2TS U4868 ( .A(n4674), .Y(n4447) );
BUFX3TS U4869 ( .A(n4447), .Y(n4472) );
INVX2TS U4870 ( .A(n4452), .Y(n3700) );
NAND2X1TS U4871 ( .A(DmP_EXP_EWSW[55]), .B(n1960), .Y(n4261) );
NOR2X1TS U4872 ( .A(n1978), .B(DMP_EXP_EWSW[54]), .Y(n4257) );
NAND2X1TS U4873 ( .A(DmP_EXP_EWSW[53]), .B(n1959), .Y(n4253) );
AOI22X1TS U4874 ( .A0(DMP_EXP_EWSW[53]), .A1(n4486), .B0(n4255), .B1(n4253),
.Y(n4259) );
OAI22X1TS U4875 ( .A0(n4257), .A1(n4259), .B0(DmP_EXP_EWSW[54]), .B1(n4485),
.Y(n4263) );
AOI22X1TS U4876 ( .A0(DMP_EXP_EWSW[55]), .A1(n4488), .B0(n4261), .B1(n4263),
.Y(n3708) );
NOR2X1TS U4877 ( .A(n1964), .B(DMP_EXP_EWSW[56]), .Y(n3709) );
AOI21X1TS U4878 ( .A0(DMP_EXP_EWSW[56]), .A1(n1964), .B0(n3709), .Y(n3706)
);
XNOR2X1TS U4879 ( .A(n3708), .B(n3706), .Y(n3707) );
OAI22X1TS U4880 ( .A0(n3709), .A1(n3708), .B0(DmP_EXP_EWSW[56]), .B1(n4530),
.Y(n3711) );
XNOR2X1TS U4881 ( .A(DmP_EXP_EWSW[57]), .B(DMP_EXP_EWSW[57]), .Y(n3710) );
XOR2X1TS U4882 ( .A(n3711), .B(n3710), .Y(n3712) );
INVX2TS U4883 ( .A(n3714), .Y(n3715) );
AOI21X1TS U4884 ( .A0(n3951), .A1(n3716), .B0(n3715), .Y(n3940) );
INVX2TS U4885 ( .A(n3940), .Y(n3919) );
AOI21X1TS U4886 ( .A0(n3919), .A1(n3718), .B0(n3717), .Y(n3968) );
NAND2X1TS U4887 ( .A(n3723), .B(n3722), .Y(n3726) );
INVX2TS U4888 ( .A(n3726), .Y(n3724) );
XNOR2X1TS U4889 ( .A(n3725), .B(n3724), .Y(n3730) );
XOR2X1TS U4890 ( .A(n3727), .B(n3726), .Y(n3728) );
AOI22X1TS U4891 ( .A0(n3728), .A1(n4367), .B0(Raw_mant_NRM_SWR[32]), .B1(
n3747), .Y(n3729) );
OAI2BB1X1TS U4892 ( .A0N(n4275), .A1N(n3730), .B0(n3729), .Y(n1237) );
BUFX3TS U4893 ( .A(n3979), .Y(n3855) );
NAND2X1TS U4894 ( .A(n3732), .B(n3731), .Y(n3736) );
INVX2TS U4895 ( .A(n3736), .Y(n3733) );
XNOR2X1TS U4896 ( .A(n3735), .B(n3736), .Y(n3737) );
AOI22X1TS U4897 ( .A0(n3737), .A1(n4367), .B0(Raw_mant_NRM_SWR[52]), .B1(
n3747), .Y(n3738) );
OAI2BB1X1TS U4898 ( .A0N(n3855), .A1N(n3739), .B0(n3738), .Y(n1217) );
INVX2TS U4899 ( .A(n3740), .Y(n3742) );
NAND2X1TS U4900 ( .A(n3742), .B(n3741), .Y(n3745) );
INVX2TS U4901 ( .A(n3745), .Y(n3743) );
XNOR2X1TS U4902 ( .A(n3744), .B(n3743), .Y(n3750) );
XOR2X1TS U4903 ( .A(n3746), .B(n3745), .Y(n3748) );
AOI22X1TS U4904 ( .A0(n3748), .A1(n4367), .B0(Raw_mant_NRM_SWR[51]), .B1(
n3747), .Y(n3749) );
OAI2BB1X1TS U4905 ( .A0N(n3855), .A1N(n3750), .B0(n3749), .Y(n1218) );
NAND2X1TS U4906 ( .A(n3752), .B(n3751), .Y(n3756) );
INVX2TS U4907 ( .A(n3756), .Y(n3753) );
XNOR2X1TS U4908 ( .A(n3755), .B(n3756), .Y(n3757) );
BUFX3TS U4909 ( .A(n4448), .Y(n3872) );
AOI22X1TS U4910 ( .A0(n3757), .A1(n4367), .B0(Raw_mant_NRM_SWR[48]), .B1(
n3872), .Y(n3758) );
OAI2BB1X1TS U4911 ( .A0N(n3855), .A1N(n3759), .B0(n3758), .Y(n1221) );
INVX2TS U4912 ( .A(n3760), .Y(n3762) );
NAND2X1TS U4913 ( .A(n3762), .B(n3761), .Y(n3765) );
INVX2TS U4914 ( .A(n3765), .Y(n3763) );
XNOR2X1TS U4915 ( .A(n3764), .B(n3763), .Y(n3769) );
XOR2X1TS U4916 ( .A(n3766), .B(n3765), .Y(n3767) );
AOI22X1TS U4917 ( .A0(n3767), .A1(n4367), .B0(Raw_mant_NRM_SWR[49]), .B1(
n3872), .Y(n3768) );
OAI2BB1X1TS U4918 ( .A0N(n3855), .A1N(n3769), .B0(n3768), .Y(n1220) );
NAND2X1TS U4919 ( .A(n3771), .B(n3770), .Y(n3775) );
INVX2TS U4920 ( .A(n3775), .Y(n3772) );
XNOR2X1TS U4921 ( .A(n3774), .B(n3775), .Y(n3776) );
AOI22X1TS U4922 ( .A0(n3776), .A1(n3911), .B0(Raw_mant_NRM_SWR[50]), .B1(
n3872), .Y(n3777) );
OAI2BB1X1TS U4923 ( .A0N(n3855), .A1N(n3778), .B0(n3777), .Y(n1219) );
OAI21X1TS U4924 ( .A0(n3781), .A1(n3780), .B0(n3779), .Y(n3801) );
INVX2TS U4925 ( .A(n3801), .Y(n3814) );
NAND2X1TS U4926 ( .A(n3784), .B(n3783), .Y(n3792) );
INVX2TS U4927 ( .A(n3792), .Y(n3785) );
INVX1TS U4928 ( .A(n3786), .Y(n3789) );
OAI21X1TS U4929 ( .A0(n3849), .A1(n3789), .B0(n3788), .Y(n3910) );
AOI21X1TS U4930 ( .A0(n3910), .A1(n3906), .B0(n3791), .Y(n3793) );
XOR2X1TS U4931 ( .A(n3793), .B(n3792), .Y(n3794) );
AOI22X1TS U4932 ( .A0(n3794), .A1(n4367), .B0(Raw_mant_NRM_SWR[37]), .B1(
n3872), .Y(n3795) );
OAI2BB1X1TS U4933 ( .A0N(n3855), .A1N(n3796), .B0(n3795), .Y(n1232) );
AOI21X1TS U4934 ( .A0(n3801), .A1(n3800), .B0(n3799), .Y(n3804) );
NAND2X1TS U4935 ( .A(n3821), .B(n3819), .Y(n3805) );
INVX2TS U4936 ( .A(n3805), .Y(n3803) );
XOR2X1TS U4937 ( .A(n3806), .B(n3805), .Y(n3807) );
BUFX3TS U4938 ( .A(n4174), .Y(n4147) );
AOI22X1TS U4939 ( .A0(n3807), .A1(n4147), .B0(Raw_mant_NRM_SWR[38]), .B1(
n3872), .Y(n3808) );
OAI2BB1X1TS U4940 ( .A0N(n3855), .A1N(n3809), .B0(n3808), .Y(n1231) );
INVX2TS U4941 ( .A(n3811), .Y(n3812) );
OAI21X1TS U4942 ( .A0(n3814), .A1(n3813), .B0(n3812), .Y(n3832) );
NAND2X1TS U4943 ( .A(n3817), .B(n3816), .Y(n3823) );
INVX2TS U4944 ( .A(n3823), .Y(n3818) );
XNOR2X1TS U4945 ( .A(n3832), .B(n3818), .Y(n3827) );
AOI21X1TS U4946 ( .A0(n3822), .A1(n3821), .B0(n3820), .Y(n3824) );
XOR2X1TS U4947 ( .A(n3824), .B(n3823), .Y(n3825) );
AOI22X1TS U4948 ( .A0(n3825), .A1(n3911), .B0(Raw_mant_NRM_SWR[39]), .B1(
n3872), .Y(n3826) );
OAI2BB1X1TS U4949 ( .A0N(n3855), .A1N(n3827), .B0(n3826), .Y(n1230) );
INVX2TS U4950 ( .A(n3829), .Y(n3830) );
AOI21X1TS U4951 ( .A0(n3832), .A1(n3831), .B0(n3830), .Y(n3836) );
NAND2X1TS U4952 ( .A(n3834), .B(n3833), .Y(n3837) );
INVX2TS U4953 ( .A(n3837), .Y(n3835) );
XNOR2X1TS U4954 ( .A(n3838), .B(n3837), .Y(n3839) );
AOI22X1TS U4955 ( .A0(n3839), .A1(n3911), .B0(Raw_mant_NRM_SWR[40]), .B1(
n3872), .Y(n3840) );
OAI2BB1X1TS U4956 ( .A0N(n3855), .A1N(n3841), .B0(n3840), .Y(n1229) );
INVX2TS U4957 ( .A(n3842), .Y(n3844) );
NAND2X1TS U4958 ( .A(n3844), .B(n3843), .Y(n3850) );
INVX2TS U4959 ( .A(n3850), .Y(n3845) );
XNOR2X1TS U4960 ( .A(n3851), .B(n3850), .Y(n3852) );
AOI22X1TS U4961 ( .A0(n3852), .A1(n3911), .B0(Raw_mant_NRM_SWR[44]), .B1(
n3872), .Y(n3853) );
OAI2BB1X1TS U4962 ( .A0N(n3855), .A1N(n3854), .B0(n3853), .Y(n1225) );
BUFX3TS U4963 ( .A(n3979), .Y(n3978) );
INVX2TS U4964 ( .A(n3856), .Y(n3858) );
NAND2X1TS U4965 ( .A(n3858), .B(n3857), .Y(n3861) );
INVX2TS U4966 ( .A(n3861), .Y(n3859) );
XNOR2X1TS U4967 ( .A(n3860), .B(n3859), .Y(n3865) );
XOR2X1TS U4968 ( .A(n3862), .B(n3861), .Y(n3863) );
AOI22X1TS U4969 ( .A0(n3863), .A1(n3911), .B0(Raw_mant_NRM_SWR[45]), .B1(
n3872), .Y(n3864) );
OAI2BB1X1TS U4970 ( .A0N(n3978), .A1N(n3865), .B0(n3864), .Y(n1224) );
NAND2X1TS U4971 ( .A(n3867), .B(n3866), .Y(n3870) );
INVX2TS U4972 ( .A(n3870), .Y(n3868) );
XNOR2X1TS U4973 ( .A(n3871), .B(n3870), .Y(n3873) );
AOI22X1TS U4974 ( .A0(n3873), .A1(n3911), .B0(Raw_mant_NRM_SWR[46]), .B1(
n3872), .Y(n3874) );
OAI2BB1X1TS U4975 ( .A0N(n3978), .A1N(n3875), .B0(n3874), .Y(n1223) );
INVX2TS U4976 ( .A(n3877), .Y(n3878) );
AOI21X1TS U4977 ( .A0(n3880), .A1(n3879), .B0(n3878), .Y(n3884) );
NAND2X1TS U4978 ( .A(n3882), .B(n3881), .Y(n3885) );
INVX2TS U4979 ( .A(n3885), .Y(n3883) );
XNOR2X1TS U4980 ( .A(n3886), .B(n3885), .Y(n3887) );
AOI22X1TS U4981 ( .A0(n3887), .A1(n3911), .B0(Raw_mant_NRM_SWR[42]), .B1(
n3974), .Y(n3888) );
OAI2BB1X1TS U4982 ( .A0N(n3978), .A1N(n3889), .B0(n3888), .Y(n1227) );
INVX2TS U4983 ( .A(n3890), .Y(n3892) );
NAND2X1TS U4984 ( .A(n3892), .B(n3891), .Y(n3895) );
INVX2TS U4985 ( .A(n3895), .Y(n3893) );
XNOR2X1TS U4986 ( .A(n3894), .B(n3893), .Y(n3899) );
XOR2X1TS U4987 ( .A(n3896), .B(n3895), .Y(n3897) );
AOI22X1TS U4988 ( .A0(n3897), .A1(n3911), .B0(Raw_mant_NRM_SWR[47]), .B1(
n3974), .Y(n3898) );
OAI2BB1X1TS U4989 ( .A0N(n3978), .A1N(n3899), .B0(n3898), .Y(n1222) );
INVX2TS U4990 ( .A(n3901), .Y(n3902) );
AOI21X1TS U4991 ( .A0(n3904), .A1(n3903), .B0(n3902), .Y(n3908) );
NAND2X1TS U4992 ( .A(n3906), .B(n3905), .Y(n3909) );
INVX2TS U4993 ( .A(n3909), .Y(n3907) );
XNOR2X1TS U4994 ( .A(n3910), .B(n3909), .Y(n3912) );
AOI22X1TS U4995 ( .A0(n3912), .A1(n3911), .B0(Raw_mant_NRM_SWR[36]), .B1(
n3974), .Y(n3913) );
OAI2BB1X1TS U4996 ( .A0N(n3978), .A1N(n3914), .B0(n3913), .Y(n1233) );
NAND2X1TS U4997 ( .A(n3917), .B(n3916), .Y(n3922) );
INVX2TS U4998 ( .A(n3922), .Y(n3918) );
XNOR2X1TS U4999 ( .A(n3919), .B(n3918), .Y(n3926) );
AOI21X1TS U5000 ( .A0(n3934), .A1(n3921), .B0(n3920), .Y(n3960) );
XNOR2X1TS U5001 ( .A(n3923), .B(n3922), .Y(n3924) );
AOI22X1TS U5002 ( .A0(n3924), .A1(n4147), .B0(Raw_mant_NRM_SWR[29]), .B1(
n3974), .Y(n3925) );
OAI2BB1X1TS U5003 ( .A0N(n3978), .A1N(n3926), .B0(n3925), .Y(n1240) );
INVX2TS U5004 ( .A(n4357), .Y(n3930) );
NAND2X1TS U5005 ( .A(n3930), .B(n4356), .Y(n3933) );
INVX2TS U5006 ( .A(n3933), .Y(n3931) );
XNOR2X1TS U5007 ( .A(n3932), .B(n3931), .Y(n3937) );
XNOR2X1TS U5008 ( .A(n3934), .B(n3933), .Y(n3935) );
AOI22X1TS U5009 ( .A0(n3935), .A1(n4147), .B0(Raw_mant_NRM_SWR[26]), .B1(
n3974), .Y(n3936) );
OAI2BB1X1TS U5010 ( .A0N(n3978), .A1N(n3937), .B0(n3936), .Y(n1243) );
NAND2X1TS U5011 ( .A(n3941), .B(n3969), .Y(n3944) );
INVX2TS U5012 ( .A(n3944), .Y(n3942) );
XNOR2X1TS U5013 ( .A(n3943), .B(n3942), .Y(n3948) );
XNOR2X1TS U5014 ( .A(n3945), .B(n3944), .Y(n3946) );
AOI22X1TS U5015 ( .A0(n3946), .A1(n4147), .B0(Raw_mant_NRM_SWR[30]), .B1(
n3974), .Y(n3947) );
OAI2BB1X1TS U5016 ( .A0N(n3978), .A1N(n3948), .B0(n3947), .Y(n1239) );
AOI21X1TS U5017 ( .A0(n3951), .A1(n3950), .B0(n3949), .Y(n4355) );
NAND2X1TS U5018 ( .A(n3956), .B(n3955), .Y(n3959) );
INVX2TS U5019 ( .A(n3959), .Y(n3957) );
XNOR2X1TS U5020 ( .A(n3958), .B(n3957), .Y(n3963) );
XOR2X1TS U5021 ( .A(n3960), .B(n3959), .Y(n3961) );
AOI22X1TS U5022 ( .A0(n3961), .A1(n4147), .B0(Raw_mant_NRM_SWR[28]), .B1(
n3974), .Y(n3962) );
OAI2BB1X1TS U5023 ( .A0N(n3978), .A1N(n3963), .B0(n3962), .Y(n1241) );
NAND2X1TS U5024 ( .A(n3966), .B(n3965), .Y(n3972) );
INVX2TS U5025 ( .A(n3972), .Y(n3967) );
XNOR2X1TS U5026 ( .A(n3973), .B(n3972), .Y(n3975) );
AOI22X1TS U5027 ( .A0(n3975), .A1(n4147), .B0(Raw_mant_NRM_SWR[31]), .B1(
n3974), .Y(n3976) );
OAI2BB1X1TS U5028 ( .A0N(n3978), .A1N(n3977), .B0(n3976), .Y(n1238) );
BUFX3TS U5029 ( .A(n3979), .Y(n4365) );
INVX2TS U5030 ( .A(n3980), .Y(n3983) );
INVX2TS U5031 ( .A(n3981), .Y(n3982) );
AOI21X1TS U5032 ( .A0(n4011), .A1(n3983), .B0(n3982), .Y(n4033) );
NAND2X1TS U5033 ( .A(n3986), .B(n4053), .Y(n3989) );
INVX2TS U5034 ( .A(n3989), .Y(n3987) );
XNOR2X1TS U5035 ( .A(n3988), .B(n3987), .Y(n3993) );
XNOR2X1TS U5036 ( .A(n3990), .B(n3989), .Y(n3991) );
AOI22X1TS U5037 ( .A0(n3991), .A1(n4147), .B0(Raw_mant_NRM_SWR[22]), .B1(
n4090), .Y(n3992) );
OAI2BB1X1TS U5038 ( .A0N(n4365), .A1N(n3993), .B0(n3992), .Y(n1247) );
AOI21X1TS U5039 ( .A0(n4011), .A1(n3995), .B0(n3994), .Y(n4023) );
NAND2X1TS U5040 ( .A(n3998), .B(n4066), .Y(n4003) );
INVX2TS U5041 ( .A(n4003), .Y(n3999) );
XNOR2X1TS U5042 ( .A(n4000), .B(n3999), .Y(n4006) );
AOI21X1TS U5043 ( .A0(n4027), .A1(n4002), .B0(n4001), .Y(n4068) );
XOR2X1TS U5044 ( .A(n4068), .B(n4003), .Y(n4004) );
AOI22X1TS U5045 ( .A0(n4004), .A1(n4147), .B0(Raw_mant_NRM_SWR[20]), .B1(
n4090), .Y(n4005) );
OAI2BB1X1TS U5046 ( .A0N(n4365), .A1N(n4006), .B0(n4005), .Y(n1249) );
INVX2TS U5047 ( .A(n4007), .Y(n4010) );
INVX2TS U5048 ( .A(n4008), .Y(n4009) );
AOI21X1TS U5049 ( .A0(n4011), .A1(n4010), .B0(n4009), .Y(n4014) );
NAND2X1TS U5050 ( .A(n4026), .B(n4024), .Y(n4015) );
INVX2TS U5051 ( .A(n4015), .Y(n4013) );
XNOR2X1TS U5052 ( .A(n4027), .B(n4015), .Y(n4016) );
AOI22X1TS U5053 ( .A0(n4016), .A1(n4147), .B0(Raw_mant_NRM_SWR[18]), .B1(
n4090), .Y(n4017) );
OAI2BB1X1TS U5054 ( .A0N(n4365), .A1N(n4018), .B0(n4017), .Y(n1251) );
NAND2X1TS U5055 ( .A(n4021), .B(n4020), .Y(n4028) );
INVX2TS U5056 ( .A(n4028), .Y(n4022) );
AOI21X1TS U5057 ( .A0(n4027), .A1(n4026), .B0(n4025), .Y(n4029) );
XOR2X1TS U5058 ( .A(n4029), .B(n4028), .Y(n4030) );
AOI22X1TS U5059 ( .A0(n4030), .A1(n4160), .B0(Raw_mant_NRM_SWR[19]), .B1(
n4090), .Y(n4031) );
OAI2BB1X1TS U5060 ( .A0N(n4365), .A1N(n4032), .B0(n4031), .Y(n1250) );
INVX2TS U5061 ( .A(n4033), .Y(n4065) );
AOI21X1TS U5062 ( .A0(n4065), .A1(n4035), .B0(n4034), .Y(n4052) );
NAND2X1TS U5063 ( .A(n4040), .B(n4039), .Y(n4043) );
INVX2TS U5064 ( .A(n4043), .Y(n4041) );
XNOR2X1TS U5065 ( .A(n4042), .B(n4041), .Y(n4047) );
XOR2X1TS U5066 ( .A(n4044), .B(n4043), .Y(n4045) );
AOI22X1TS U5067 ( .A0(n4045), .A1(n4160), .B0(Raw_mant_NRM_SWR[24]), .B1(
n4090), .Y(n4046) );
OAI2BB1X1TS U5068 ( .A0N(n4365), .A1N(n4047), .B0(n4046), .Y(n1245) );
NAND2X1TS U5069 ( .A(n4050), .B(n4049), .Y(n4056) );
INVX2TS U5070 ( .A(n4056), .Y(n4051) );
XNOR2X1TS U5071 ( .A(n4057), .B(n4056), .Y(n4058) );
AOI22X1TS U5072 ( .A0(n4058), .A1(n4160), .B0(Raw_mant_NRM_SWR[23]), .B1(
n4090), .Y(n4059) );
OAI2BB1X1TS U5073 ( .A0N(n4365), .A1N(n4060), .B0(n4059), .Y(n1246) );
NAND2X1TS U5074 ( .A(n4063), .B(n4062), .Y(n4069) );
INVX2TS U5075 ( .A(n4069), .Y(n4064) );
XNOR2X1TS U5076 ( .A(n4065), .B(n4064), .Y(n4073) );
XNOR2X1TS U5077 ( .A(n4070), .B(n4069), .Y(n4071) );
AOI22X1TS U5078 ( .A0(n4071), .A1(n4160), .B0(Raw_mant_NRM_SWR[21]), .B1(
n4090), .Y(n4072) );
OAI2BB1X1TS U5079 ( .A0N(n4365), .A1N(n4073), .B0(n4072), .Y(n1248) );
OAI21X1TS U5080 ( .A0(n4166), .A1(n4075), .B0(n4074), .Y(n4182) );
INVX2TS U5081 ( .A(n4182), .Y(n4196) );
INVX2TS U5082 ( .A(n4076), .Y(n4079) );
INVX2TS U5083 ( .A(n4077), .Y(n4078) );
OAI21X1TS U5084 ( .A0(n4196), .A1(n4079), .B0(n4078), .Y(n4098) );
INVX2TS U5085 ( .A(n4081), .Y(n4082) );
AOI21X1TS U5086 ( .A0(n4098), .A1(n4083), .B0(n4082), .Y(n4087) );
NAND2X1TS U5087 ( .A(n4085), .B(n4084), .Y(n4088) );
INVX2TS U5088 ( .A(n4088), .Y(n4086) );
XNOR2X1TS U5089 ( .A(n4089), .B(n4088), .Y(n4091) );
AOI22X1TS U5090 ( .A0(n4091), .A1(n4160), .B0(Raw_mant_NRM_SWR[16]), .B1(
n4090), .Y(n4092) );
OAI2BB1X1TS U5091 ( .A0N(n4271), .A1N(n4093), .B0(n4092), .Y(n1253) );
NAND2X1TS U5092 ( .A(n4096), .B(n4095), .Y(n4102) );
INVX2TS U5093 ( .A(n4102), .Y(n4097) );
XNOR2X1TS U5094 ( .A(n4098), .B(n4097), .Y(n4106) );
AOI21X1TS U5095 ( .A0(n4101), .A1(n4184), .B0(n4100), .Y(n4103) );
XOR2X1TS U5096 ( .A(n4103), .B(n4102), .Y(n4104) );
AOI22X1TS U5097 ( .A0(n4104), .A1(n4160), .B0(Raw_mant_NRM_SWR[15]), .B1(
n4213), .Y(n4105) );
OAI2BB1X1TS U5098 ( .A0N(n4365), .A1N(n4106), .B0(n4105), .Y(n1254) );
INVX2TS U5099 ( .A(n4108), .Y(n4109) );
AOI21X1TS U5100 ( .A0(n4111), .A1(n4110), .B0(n4109), .Y(n4114) );
NAND2X1TS U5101 ( .A(n4199), .B(n4197), .Y(n4119) );
INVX2TS U5102 ( .A(n4119), .Y(n4113) );
OAI21X1TS U5103 ( .A0(n4173), .A1(n4118), .B0(n4117), .Y(n4200) );
XNOR2X1TS U5104 ( .A(n4200), .B(n4119), .Y(n4120) );
AOI22X1TS U5105 ( .A0(n4120), .A1(n4160), .B0(Raw_mant_NRM_SWR[12]), .B1(
n4213), .Y(n4121) );
OAI2BB1X1TS U5106 ( .A0N(n4271), .A1N(n4122), .B0(n4121), .Y(n1257) );
AOI21X1TS U5107 ( .A0(n4221), .A1(n4125), .B0(n4124), .Y(n4140) );
NAND2X1TS U5108 ( .A(n4128), .B(n4127), .Y(n4133) );
INVX2TS U5109 ( .A(n4133), .Y(n4129) );
INVX2TS U5110 ( .A(n4130), .Y(n4227) );
AOI21X1TS U5111 ( .A0(n4227), .A1(n4223), .B0(n4132), .Y(n4134) );
XOR2X1TS U5112 ( .A(n4134), .B(n4133), .Y(n4135) );
AOI22X1TS U5113 ( .A0(n4135), .A1(n4160), .B0(Raw_mant_NRM_SWR[7]), .B1(
n4213), .Y(n4136) );
OAI2BB1X1TS U5114 ( .A0N(n4365), .A1N(n4137), .B0(n4136), .Y(n1262) );
NAND2X1TS U5115 ( .A(n4141), .B(n4155), .Y(n4146) );
INVX2TS U5116 ( .A(n4146), .Y(n4142) );
XNOR2X1TS U5117 ( .A(n4143), .B(n4142), .Y(n4150) );
AOI21X1TS U5118 ( .A0(n4227), .A1(n4145), .B0(n4144), .Y(n4157) );
XOR2X1TS U5119 ( .A(n4157), .B(n4146), .Y(n4148) );
AOI22X1TS U5120 ( .A0(n4148), .A1(n4147), .B0(Raw_mant_NRM_SWR[8]), .B1(
n4213), .Y(n4149) );
OAI2BB1X1TS U5121 ( .A0N(n4271), .A1N(n4150), .B0(n4149), .Y(n1261) );
INVX2TS U5122 ( .A(n4151), .Y(n4153) );
NAND2X1TS U5123 ( .A(n4153), .B(n4152), .Y(n4158) );
INVX2TS U5124 ( .A(n4158), .Y(n4154) );
XNOR2X1TS U5125 ( .A(n4159), .B(n4158), .Y(n4161) );
AOI22X1TS U5126 ( .A0(n4161), .A1(n4160), .B0(Raw_mant_NRM_SWR[9]), .B1(
n4213), .Y(n4162) );
OAI2BB1X1TS U5127 ( .A0N(n4271), .A1N(n4163), .B0(n4162), .Y(n1260) );
NAND2X1TS U5128 ( .A(n4169), .B(n4168), .Y(n4172) );
INVX2TS U5129 ( .A(n4172), .Y(n4170) );
XNOR2X1TS U5130 ( .A(n4171), .B(n4170), .Y(n4177) );
XOR2X1TS U5131 ( .A(n4173), .B(n4172), .Y(n4175) );
BUFX3TS U5132 ( .A(n4174), .Y(n4361) );
AOI22X1TS U5133 ( .A0(n4175), .A1(n4361), .B0(Raw_mant_NRM_SWR[10]), .B1(
n4213), .Y(n4176) );
OAI2BB1X1TS U5134 ( .A0N(n4271), .A1N(n4177), .B0(n4176), .Y(n1259) );
INVX2TS U5135 ( .A(n4179), .Y(n4180) );
AOI21X1TS U5136 ( .A0(n4182), .A1(n4181), .B0(n4180), .Y(n4186) );
NAND2X1TS U5137 ( .A(n4184), .B(n4183), .Y(n4187) );
INVX2TS U5138 ( .A(n4187), .Y(n4185) );
XOR2X1TS U5139 ( .A(n4188), .B(n4187), .Y(n4189) );
AOI22X1TS U5140 ( .A0(n4189), .A1(n4361), .B0(Raw_mant_NRM_SWR[14]), .B1(
n4213), .Y(n4190) );
OAI2BB1X1TS U5141 ( .A0N(n4271), .A1N(n4191), .B0(n4190), .Y(n1255) );
NAND2X1TS U5142 ( .A(n4194), .B(n4193), .Y(n4201) );
INVX2TS U5143 ( .A(n4201), .Y(n4195) );
INVX2TS U5144 ( .A(n4197), .Y(n4198) );
AOI21X1TS U5145 ( .A0(n4200), .A1(n4199), .B0(n4198), .Y(n4202) );
XOR2X1TS U5146 ( .A(n4202), .B(n4201), .Y(n4203) );
AOI22X1TS U5147 ( .A0(n4203), .A1(n4361), .B0(Raw_mant_NRM_SWR[13]), .B1(
n4213), .Y(n4204) );
OAI2BB1X1TS U5148 ( .A0N(n4271), .A1N(n4205), .B0(n4204), .Y(n1256) );
NAND2X1TS U5149 ( .A(n4208), .B(n4207), .Y(n4211) );
INVX2TS U5150 ( .A(n4211), .Y(n4209) );
XNOR2X1TS U5151 ( .A(n4221), .B(n4209), .Y(n4216) );
XNOR2X1TS U5152 ( .A(n4212), .B(n4211), .Y(n4214) );
AOI22X1TS U5153 ( .A0(n4214), .A1(n4361), .B0(Raw_mant_NRM_SWR[5]), .B1(
n4213), .Y(n4215) );
OAI2BB1X1TS U5154 ( .A0N(n4275), .A1N(n4216), .B0(n4215), .Y(n1264) );
INVX2TS U5155 ( .A(n4217), .Y(n4220) );
INVX2TS U5156 ( .A(n4218), .Y(n4219) );
AOI21X1TS U5157 ( .A0(n4221), .A1(n4220), .B0(n4219), .Y(n4225) );
NAND2X1TS U5158 ( .A(n4223), .B(n4222), .Y(n4226) );
INVX2TS U5159 ( .A(n4226), .Y(n4224) );
XNOR2X1TS U5160 ( .A(n4227), .B(n4226), .Y(n4228) );
BUFX3TS U5161 ( .A(n4448), .Y(n4478) );
AOI22X1TS U5162 ( .A0(n4228), .A1(n4361), .B0(Raw_mant_NRM_SWR[6]), .B1(
n4478), .Y(n4229) );
OAI2BB1X1TS U5163 ( .A0N(n4275), .A1N(n4230), .B0(n4229), .Y(n1263) );
INVX2TS U5164 ( .A(n4231), .Y(n4248) );
NAND2X1TS U5165 ( .A(n4236), .B(n4235), .Y(n4239) );
INVX2TS U5166 ( .A(n4239), .Y(n4237) );
XNOR2X1TS U5167 ( .A(n4238), .B(n4237), .Y(n4243) );
XOR2X1TS U5168 ( .A(n4240), .B(n4239), .Y(n4241) );
AOI22X1TS U5169 ( .A0(n4241), .A1(n4361), .B0(Raw_mant_NRM_SWR[4]), .B1(
n4478), .Y(n4242) );
OAI2BB1X1TS U5170 ( .A0N(n4275), .A1N(n4243), .B0(n4242), .Y(n1265) );
INVX2TS U5171 ( .A(n4244), .Y(n4246) );
NAND2X1TS U5172 ( .A(n4246), .B(n4245), .Y(n4249) );
INVX2TS U5173 ( .A(n4249), .Y(n4247) );
XOR2X1TS U5174 ( .A(n4249), .B(n4265), .Y(n4250) );
AOI22X1TS U5175 ( .A0(n4250), .A1(n4361), .B0(Raw_mant_NRM_SWR[3]), .B1(
n4478), .Y(n4251) );
OAI2BB1X1TS U5176 ( .A0N(n4271), .A1N(n4252), .B0(n4251), .Y(n1266) );
XNOR2X1TS U5177 ( .A(n4255), .B(n4254), .Y(n4256) );
CLKBUFX2TS U5178 ( .A(n4629), .Y(n4464) );
BUFX3TS U5179 ( .A(n4464), .Y(n4435) );
AOI21X1TS U5180 ( .A0(DMP_EXP_EWSW[54]), .A1(n1978), .B0(n4257), .Y(n4258)
);
XNOR2X1TS U5181 ( .A(n4259), .B(n4258), .Y(n4260) );
XNOR2X1TS U5182 ( .A(n4263), .B(n4262), .Y(n4264) );
OR2X1TS U5183 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n4266) );
AOI22X1TS U5184 ( .A0(n4268), .A1(n4361), .B0(Raw_mant_NRM_SWR[2]), .B1(
n4478), .Y(n4269) );
OAI2BB1X1TS U5185 ( .A0N(n4271), .A1N(n4270), .B0(n4269), .Y(n1267) );
MXI2X1TS U5186 ( .A(n4587), .B(n4272), .S0(n1926), .Y(n1269) );
XNOR2X1TS U5187 ( .A(DmP_mant_SFG_SWR[1]), .B(n4272), .Y(n4274) );
AOI22X1TS U5188 ( .A0(n4361), .A1(DmP_mant_SFG_SWR[1]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n4478), .Y(n4273) );
OAI2BB1X1TS U5189 ( .A0N(n4275), .A1N(n4274), .B0(n4273), .Y(n1268) );
INVX2TS U5190 ( .A(n4302), .Y(n4334) );
OAI22X1TS U5191 ( .A0(n4334), .A1(n4292), .B0(n4332), .B1(n4329), .Y(n4283)
);
AOI211X1TS U5192 ( .A0(n4323), .A1(n4337), .B0(n4284), .C0(n4283), .Y(n4285)
);
OAI21X1TS U5193 ( .A0(n4341), .A1(n4325), .B0(n4285), .Y(n4384) );
AOI22X1TS U5194 ( .A0(n4318), .A1(n4307), .B0(n4316), .B1(n4308), .Y(n4290)
);
AOI21X1TS U5195 ( .A0(n4338), .A1(n4312), .B0(n4293), .Y(n4294) );
OAI21X1TS U5196 ( .A0(n4314), .A1(n4340), .B0(n4294), .Y(n4382) );
NAND2X1TS U5197 ( .A(n4297), .B(n3022), .Y(n4301) );
NAND2X1TS U5198 ( .A(n4299), .B(n4298), .Y(n4300) );
AOI22X1TS U5199 ( .A0(n4318), .A1(n4337), .B0(n4316), .B1(n4302), .Y(n4303)
);
AOI21X1TS U5200 ( .A0(n1938), .A1(n4305), .B0(n4304), .Y(n4306) );
OAI21X1TS U5201 ( .A0(n4332), .A1(n4325), .B0(n4306), .Y(n4379) );
AOI22X1TS U5202 ( .A0(n4318), .A1(n4308), .B0(n4316), .B1(n4307), .Y(n4309)
);
AOI21X1TS U5203 ( .A0(n1938), .A1(n4312), .B0(n4311), .Y(n4313) );
OAI21X1TS U5204 ( .A0(n4314), .A1(n4325), .B0(n4313), .Y(n4378) );
AOI22X1TS U5205 ( .A0(n4318), .A1(n4317), .B0(n4316), .B1(n4315), .Y(n4319)
);
AOI21X1TS U5206 ( .A0(n1938), .A1(n4322), .B0(n4321), .Y(n4324) );
OAI21X1TS U5207 ( .A0(n4326), .A1(n4325), .B0(n4324), .Y(n4376) );
OAI22X1TS U5208 ( .A0(n4334), .A1(n4333), .B0(n4332), .B1(n4331), .Y(n4335)
);
AOI211X1TS U5209 ( .A0(n4338), .A1(n4337), .B0(n4336), .C0(n4335), .Y(n4339)
);
OAI21X1TS U5210 ( .A0(n4341), .A1(n4340), .B0(n4339), .Y(n4375) );
MXI2X1TS U5211 ( .A(n4343), .B(n4654), .S0(n4349), .Y(n1141) );
MXI2X1TS U5212 ( .A(n4344), .B(n4637), .S0(n4349), .Y(n1142) );
MXI2X1TS U5213 ( .A(n4345), .B(n4655), .S0(n4349), .Y(n1143) );
MXI2X1TS U5214 ( .A(n4346), .B(n4638), .S0(n4349), .Y(n1144) );
INVX2TS U5215 ( .A(n4351), .Y(n4353) );
NAND2X1TS U5216 ( .A(n4353), .B(n4352), .Y(n4359) );
INVX2TS U5217 ( .A(n4359), .Y(n4354) );
XNOR2X1TS U5218 ( .A(n4360), .B(n4359), .Y(n4362) );
AOI22X1TS U5219 ( .A0(n4362), .A1(n4361), .B0(Raw_mant_NRM_SWR[27]), .B1(
n4478), .Y(n4363) );
OAI2BB1X1TS U5220 ( .A0N(n4365), .A1N(n4364), .B0(n4363), .Y(n1242) );
MX2X1TS U5221 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1429) );
OAI2BB1X1TS U5222 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n3382), .B0(n4373),
.Y(n1210) );
OA21XLTS U5223 ( .A0(n4675), .A1(overflow_flag), .B0(n4393), .Y(n1287) );
AOI22X1TS U5224 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n4395), .B1(n4511), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U5225 ( .A(n4395), .B(n4394), .Y(n1892) );
INVX2TS U5226 ( .A(n4399), .Y(n4398) );
AOI22X1TS U5227 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n4396), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n4511), .Y(n4400) );
AOI22X1TS U5228 ( .A0(n4399), .A1(n4397), .B0(n4435), .B1(n4398), .Y(n1889)
);
BUFX3TS U5229 ( .A(n4418), .Y(n4412) );
BUFX3TS U5230 ( .A(n4412), .Y(n4404) );
BUFX3TS U5231 ( .A(n4414), .Y(n4410) );
INVX2TS U5232 ( .A(n4410), .Y(n4427) );
BUFX3TS U5233 ( .A(n4415), .Y(n4421) );
INVX2TS U5234 ( .A(n4418), .Y(n4401) );
BUFX3TS U5235 ( .A(n4412), .Y(n4406) );
INVX2TS U5236 ( .A(n4415), .Y(n4402) );
BUFX3TS U5237 ( .A(n4412), .Y(n4407) );
INVX2TS U5238 ( .A(n4418), .Y(n4403) );
INVX2TS U5239 ( .A(n4410), .Y(n4405) );
BUFX3TS U5240 ( .A(n4412), .Y(n4409) );
INVX2TS U5241 ( .A(n4410), .Y(n4408) );
INVX2TS U5242 ( .A(n4415), .Y(n4417) );
BUFX3TS U5243 ( .A(n4412), .Y(n4429) );
INVX2TS U5244 ( .A(n4415), .Y(n4413) );
BUFX3TS U5245 ( .A(n4422), .Y(n4425) );
INVX2TS U5246 ( .A(n4415), .Y(n4411) );
BUFX3TS U5247 ( .A(n4422), .Y(n4416) );
INVX2TS U5248 ( .A(n4415), .Y(n4428) );
BUFX3TS U5249 ( .A(n4412), .Y(n4424) );
BUFX3TS U5250 ( .A(n4414), .Y(n4420) );
INVX2TS U5251 ( .A(n4415), .Y(n4419) );
INVX2TS U5252 ( .A(n4418), .Y(n4423) );
INVX2TS U5253 ( .A(n4421), .Y(n4426) );
OAI222X1TS U5254 ( .A0(n4465), .A1(n4529), .B0(n4485), .B1(n4466), .C0(n4482), .C1(n4467), .Y(n1621) );
OAI222X1TS U5255 ( .A0(n4465), .A1(n4532), .B0(n1960), .B1(n4466), .C0(n4481), .C1(n4467), .Y(n1620) );
OAI222X1TS U5256 ( .A0(n4465), .A1(n4487), .B0(n4530), .B1(n4466), .C0(n1988), .C1(n4467), .Y(n1619) );
AOI21X1TS U5257 ( .A0(n4431), .A1(intDX_EWSW[63]), .B0(n4430), .Y(n4433) );
BUFX3TS U5258 ( .A(n4629), .Y(n4459) );
INVX2TS U5259 ( .A(n4459), .Y(n4436) );
INVX2TS U5260 ( .A(n4459), .Y(n4438) );
BUFX3TS U5261 ( .A(n4458), .Y(n4437) );
INVX2TS U5262 ( .A(n4459), .Y(n4440) );
BUFX3TS U5263 ( .A(n4458), .Y(n4439) );
INVX2TS U5264 ( .A(n4459), .Y(n4442) );
BUFX3TS U5265 ( .A(n4464), .Y(n4450) );
BUFX3TS U5266 ( .A(n4473), .Y(n4443) );
INVX2TS U5267 ( .A(n4459), .Y(n4445) );
BUFX3TS U5268 ( .A(n4459), .Y(n4446) );
INVX2TS U5269 ( .A(n4475), .Y(n4453) );
INVX2TS U5270 ( .A(n4459), .Y(n4451) );
INVX2TS U5271 ( .A(n4452), .Y(n4476) );
CLKBUFX2TS U5272 ( .A(n4629), .Y(n4473) );
INVX2TS U5273 ( .A(n4473), .Y(n4455) );
BUFX3TS U5274 ( .A(n4464), .Y(n4454) );
INVX2TS U5275 ( .A(n4458), .Y(n4457) );
BUFX3TS U5276 ( .A(n4464), .Y(n4456) );
INVX2TS U5277 ( .A(n4458), .Y(n4461) );
BUFX3TS U5278 ( .A(n4459), .Y(n4460) );
INVX2TS U5279 ( .A(n4473), .Y(n4463) );
BUFX3TS U5280 ( .A(n4464), .Y(n4462) );
INVX2TS U5281 ( .A(n4473), .Y(n4471) );
BUFX3TS U5282 ( .A(n4464), .Y(n4470) );
OAI222X1TS U5283 ( .A0(n4467), .A1(n4529), .B0(n1978), .B1(n4466), .C0(n4482), .C1(n4465), .Y(n1292) );
OAI222X1TS U5284 ( .A0(n4467), .A1(n4532), .B0(n4488), .B1(n4466), .C0(n4481), .C1(n4465), .Y(n1291) );
OAI222X1TS U5285 ( .A0(n4467), .A1(n4487), .B0(n1964), .B1(n4466), .C0(n1988), .C1(n4465), .Y(n1290) );
INVX2TS U5286 ( .A(n4473), .Y(n4474) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_syn.sdf");
endmodule
|
// system_acl_iface_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.05.04.18:11:46
`timescale 1 ps / 1 ps
module system_acl_iface_mm_interconnect_0 (
input wire [11:0] hps_h2f_lw_axi_master_awid, // hps_h2f_lw_axi_master.awid
input wire [20:0] hps_h2f_lw_axi_master_awaddr, // .awaddr
input wire [3:0] hps_h2f_lw_axi_master_awlen, // .awlen
input wire [2:0] hps_h2f_lw_axi_master_awsize, // .awsize
input wire [1:0] hps_h2f_lw_axi_master_awburst, // .awburst
input wire [1:0] hps_h2f_lw_axi_master_awlock, // .awlock
input wire [3:0] hps_h2f_lw_axi_master_awcache, // .awcache
input wire [2:0] hps_h2f_lw_axi_master_awprot, // .awprot
input wire hps_h2f_lw_axi_master_awvalid, // .awvalid
output wire hps_h2f_lw_axi_master_awready, // .awready
input wire [11:0] hps_h2f_lw_axi_master_wid, // .wid
input wire [31:0] hps_h2f_lw_axi_master_wdata, // .wdata
input wire [3:0] hps_h2f_lw_axi_master_wstrb, // .wstrb
input wire hps_h2f_lw_axi_master_wlast, // .wlast
input wire hps_h2f_lw_axi_master_wvalid, // .wvalid
output wire hps_h2f_lw_axi_master_wready, // .wready
output wire [11:0] hps_h2f_lw_axi_master_bid, // .bid
output wire [1:0] hps_h2f_lw_axi_master_bresp, // .bresp
output wire hps_h2f_lw_axi_master_bvalid, // .bvalid
input wire hps_h2f_lw_axi_master_bready, // .bready
input wire [11:0] hps_h2f_lw_axi_master_arid, // .arid
input wire [20:0] hps_h2f_lw_axi_master_araddr, // .araddr
input wire [3:0] hps_h2f_lw_axi_master_arlen, // .arlen
input wire [2:0] hps_h2f_lw_axi_master_arsize, // .arsize
input wire [1:0] hps_h2f_lw_axi_master_arburst, // .arburst
input wire [1:0] hps_h2f_lw_axi_master_arlock, // .arlock
input wire [3:0] hps_h2f_lw_axi_master_arcache, // .arcache
input wire [2:0] hps_h2f_lw_axi_master_arprot, // .arprot
input wire hps_h2f_lw_axi_master_arvalid, // .arvalid
output wire hps_h2f_lw_axi_master_arready, // .arready
output wire [11:0] hps_h2f_lw_axi_master_rid, // .rid
output wire [31:0] hps_h2f_lw_axi_master_rdata, // .rdata
output wire [1:0] hps_h2f_lw_axi_master_rresp, // .rresp
output wire hps_h2f_lw_axi_master_rlast, // .rlast
output wire hps_h2f_lw_axi_master_rvalid, // .rvalid
input wire hps_h2f_lw_axi_master_rready, // .rready
input wire config_clk_out_clk_clk, // config_clk_out_clk.clk
input wire hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
input wire version_id_clk_reset_reset_bridge_in_reset_reset, // version_id_clk_reset_reset_bridge_in_reset.reset
output wire [10:0] acl_kernel_clk_ctrl_address, // acl_kernel_clk_ctrl.address
output wire acl_kernel_clk_ctrl_write, // .write
output wire acl_kernel_clk_ctrl_read, // .read
input wire [31:0] acl_kernel_clk_ctrl_readdata, // .readdata
output wire [31:0] acl_kernel_clk_ctrl_writedata, // .writedata
output wire [0:0] acl_kernel_clk_ctrl_burstcount, // .burstcount
output wire [3:0] acl_kernel_clk_ctrl_byteenable, // .byteenable
input wire acl_kernel_clk_ctrl_readdatavalid, // .readdatavalid
input wire acl_kernel_clk_ctrl_waitrequest, // .waitrequest
output wire acl_kernel_clk_ctrl_debugaccess, // .debugaccess
output wire [13:0] acl_kernel_interface_kernel_cntrl_address, // acl_kernel_interface_kernel_cntrl.address
output wire acl_kernel_interface_kernel_cntrl_write, // .write
output wire acl_kernel_interface_kernel_cntrl_read, // .read
input wire [31:0] acl_kernel_interface_kernel_cntrl_readdata, // .readdata
output wire [31:0] acl_kernel_interface_kernel_cntrl_writedata, // .writedata
output wire [0:0] acl_kernel_interface_kernel_cntrl_burstcount, // .burstcount
output wire [3:0] acl_kernel_interface_kernel_cntrl_byteenable, // .byteenable
input wire acl_kernel_interface_kernel_cntrl_readdatavalid, // .readdatavalid
input wire acl_kernel_interface_kernel_cntrl_waitrequest, // .waitrequest
output wire acl_kernel_interface_kernel_cntrl_debugaccess, // .debugaccess
output wire version_id_s_read, // version_id_s.read
input wire [31:0] version_id_s_readdata // .readdata
);
wire version_id_s_agent_m0_waitrequest; // version_id_s_translator:uav_waitrequest -> version_id_s_agent:m0_waitrequest
wire [2:0] version_id_s_agent_m0_burstcount; // version_id_s_agent:m0_burstcount -> version_id_s_translator:uav_burstcount
wire [31:0] version_id_s_agent_m0_writedata; // version_id_s_agent:m0_writedata -> version_id_s_translator:uav_writedata
wire [20:0] version_id_s_agent_m0_address; // version_id_s_agent:m0_address -> version_id_s_translator:uav_address
wire version_id_s_agent_m0_write; // version_id_s_agent:m0_write -> version_id_s_translator:uav_write
wire version_id_s_agent_m0_lock; // version_id_s_agent:m0_lock -> version_id_s_translator:uav_lock
wire version_id_s_agent_m0_read; // version_id_s_agent:m0_read -> version_id_s_translator:uav_read
wire [31:0] version_id_s_agent_m0_readdata; // version_id_s_translator:uav_readdata -> version_id_s_agent:m0_readdata
wire version_id_s_agent_m0_readdatavalid; // version_id_s_translator:uav_readdatavalid -> version_id_s_agent:m0_readdatavalid
wire version_id_s_agent_m0_debugaccess; // version_id_s_agent:m0_debugaccess -> version_id_s_translator:uav_debugaccess
wire [3:0] version_id_s_agent_m0_byteenable; // version_id_s_agent:m0_byteenable -> version_id_s_translator:uav_byteenable
wire version_id_s_agent_rf_source_endofpacket; // version_id_s_agent:rf_source_endofpacket -> version_id_s_agent_rsp_fifo:in_endofpacket
wire version_id_s_agent_rf_source_valid; // version_id_s_agent:rf_source_valid -> version_id_s_agent_rsp_fifo:in_valid
wire version_id_s_agent_rf_source_startofpacket; // version_id_s_agent:rf_source_startofpacket -> version_id_s_agent_rsp_fifo:in_startofpacket
wire [114:0] version_id_s_agent_rf_source_data; // version_id_s_agent:rf_source_data -> version_id_s_agent_rsp_fifo:in_data
wire version_id_s_agent_rf_source_ready; // version_id_s_agent_rsp_fifo:in_ready -> version_id_s_agent:rf_source_ready
wire version_id_s_agent_rsp_fifo_out_endofpacket; // version_id_s_agent_rsp_fifo:out_endofpacket -> version_id_s_agent:rf_sink_endofpacket
wire version_id_s_agent_rsp_fifo_out_valid; // version_id_s_agent_rsp_fifo:out_valid -> version_id_s_agent:rf_sink_valid
wire version_id_s_agent_rsp_fifo_out_startofpacket; // version_id_s_agent_rsp_fifo:out_startofpacket -> version_id_s_agent:rf_sink_startofpacket
wire [114:0] version_id_s_agent_rsp_fifo_out_data; // version_id_s_agent_rsp_fifo:out_data -> version_id_s_agent:rf_sink_data
wire version_id_s_agent_rsp_fifo_out_ready; // version_id_s_agent:rf_sink_ready -> version_id_s_agent_rsp_fifo:out_ready
wire version_id_s_agent_rdata_fifo_src_valid; // version_id_s_agent:rdata_fifo_src_valid -> version_id_s_agent_rdata_fifo:in_valid
wire [33:0] version_id_s_agent_rdata_fifo_src_data; // version_id_s_agent:rdata_fifo_src_data -> version_id_s_agent_rdata_fifo:in_data
wire version_id_s_agent_rdata_fifo_src_ready; // version_id_s_agent_rdata_fifo:in_ready -> version_id_s_agent:rdata_fifo_src_ready
wire version_id_s_agent_rdata_fifo_out_valid; // version_id_s_agent_rdata_fifo:out_valid -> version_id_s_agent:rdata_fifo_sink_valid
wire [33:0] version_id_s_agent_rdata_fifo_out_data; // version_id_s_agent_rdata_fifo:out_data -> version_id_s_agent:rdata_fifo_sink_data
wire version_id_s_agent_rdata_fifo_out_ready; // version_id_s_agent:rdata_fifo_sink_ready -> version_id_s_agent_rdata_fifo:out_ready
wire acl_kernel_interface_kernel_cntrl_agent_m0_waitrequest; // acl_kernel_interface_kernel_cntrl_translator:uav_waitrequest -> acl_kernel_interface_kernel_cntrl_agent:m0_waitrequest
wire [2:0] acl_kernel_interface_kernel_cntrl_agent_m0_burstcount; // acl_kernel_interface_kernel_cntrl_agent:m0_burstcount -> acl_kernel_interface_kernel_cntrl_translator:uav_burstcount
wire [31:0] acl_kernel_interface_kernel_cntrl_agent_m0_writedata; // acl_kernel_interface_kernel_cntrl_agent:m0_writedata -> acl_kernel_interface_kernel_cntrl_translator:uav_writedata
wire [20:0] acl_kernel_interface_kernel_cntrl_agent_m0_address; // acl_kernel_interface_kernel_cntrl_agent:m0_address -> acl_kernel_interface_kernel_cntrl_translator:uav_address
wire acl_kernel_interface_kernel_cntrl_agent_m0_write; // acl_kernel_interface_kernel_cntrl_agent:m0_write -> acl_kernel_interface_kernel_cntrl_translator:uav_write
wire acl_kernel_interface_kernel_cntrl_agent_m0_lock; // acl_kernel_interface_kernel_cntrl_agent:m0_lock -> acl_kernel_interface_kernel_cntrl_translator:uav_lock
wire acl_kernel_interface_kernel_cntrl_agent_m0_read; // acl_kernel_interface_kernel_cntrl_agent:m0_read -> acl_kernel_interface_kernel_cntrl_translator:uav_read
wire [31:0] acl_kernel_interface_kernel_cntrl_agent_m0_readdata; // acl_kernel_interface_kernel_cntrl_translator:uav_readdata -> acl_kernel_interface_kernel_cntrl_agent:m0_readdata
wire acl_kernel_interface_kernel_cntrl_agent_m0_readdatavalid; // acl_kernel_interface_kernel_cntrl_translator:uav_readdatavalid -> acl_kernel_interface_kernel_cntrl_agent:m0_readdatavalid
wire acl_kernel_interface_kernel_cntrl_agent_m0_debugaccess; // acl_kernel_interface_kernel_cntrl_agent:m0_debugaccess -> acl_kernel_interface_kernel_cntrl_translator:uav_debugaccess
wire [3:0] acl_kernel_interface_kernel_cntrl_agent_m0_byteenable; // acl_kernel_interface_kernel_cntrl_agent:m0_byteenable -> acl_kernel_interface_kernel_cntrl_translator:uav_byteenable
wire acl_kernel_interface_kernel_cntrl_agent_rf_source_endofpacket; // acl_kernel_interface_kernel_cntrl_agent:rf_source_endofpacket -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_endofpacket
wire acl_kernel_interface_kernel_cntrl_agent_rf_source_valid; // acl_kernel_interface_kernel_cntrl_agent:rf_source_valid -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_valid
wire acl_kernel_interface_kernel_cntrl_agent_rf_source_startofpacket; // acl_kernel_interface_kernel_cntrl_agent:rf_source_startofpacket -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_startofpacket
wire [114:0] acl_kernel_interface_kernel_cntrl_agent_rf_source_data; // acl_kernel_interface_kernel_cntrl_agent:rf_source_data -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_data
wire acl_kernel_interface_kernel_cntrl_agent_rf_source_ready; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_ready -> acl_kernel_interface_kernel_cntrl_agent:rf_source_ready
wire acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_endofpacket; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_endofpacket -> acl_kernel_interface_kernel_cntrl_agent:rf_sink_endofpacket
wire acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_valid; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_valid -> acl_kernel_interface_kernel_cntrl_agent:rf_sink_valid
wire acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_startofpacket; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_startofpacket -> acl_kernel_interface_kernel_cntrl_agent:rf_sink_startofpacket
wire [114:0] acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_data; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_data -> acl_kernel_interface_kernel_cntrl_agent:rf_sink_data
wire acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_ready; // acl_kernel_interface_kernel_cntrl_agent:rf_sink_ready -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_ready
wire acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_valid; // acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_src_valid -> acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:in_valid
wire [33:0] acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_data; // acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_src_data -> acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:in_data
wire acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_ready; // acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:in_ready -> acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_src_ready
wire acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_valid; // acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:out_valid -> acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_sink_valid
wire [33:0] acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_data; // acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:out_data -> acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_sink_data
wire acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_ready; // acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_sink_ready -> acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:out_ready
wire acl_kernel_clk_ctrl_agent_m0_waitrequest; // acl_kernel_clk_ctrl_translator:uav_waitrequest -> acl_kernel_clk_ctrl_agent:m0_waitrequest
wire [2:0] acl_kernel_clk_ctrl_agent_m0_burstcount; // acl_kernel_clk_ctrl_agent:m0_burstcount -> acl_kernel_clk_ctrl_translator:uav_burstcount
wire [31:0] acl_kernel_clk_ctrl_agent_m0_writedata; // acl_kernel_clk_ctrl_agent:m0_writedata -> acl_kernel_clk_ctrl_translator:uav_writedata
wire [20:0] acl_kernel_clk_ctrl_agent_m0_address; // acl_kernel_clk_ctrl_agent:m0_address -> acl_kernel_clk_ctrl_translator:uav_address
wire acl_kernel_clk_ctrl_agent_m0_write; // acl_kernel_clk_ctrl_agent:m0_write -> acl_kernel_clk_ctrl_translator:uav_write
wire acl_kernel_clk_ctrl_agent_m0_lock; // acl_kernel_clk_ctrl_agent:m0_lock -> acl_kernel_clk_ctrl_translator:uav_lock
wire acl_kernel_clk_ctrl_agent_m0_read; // acl_kernel_clk_ctrl_agent:m0_read -> acl_kernel_clk_ctrl_translator:uav_read
wire [31:0] acl_kernel_clk_ctrl_agent_m0_readdata; // acl_kernel_clk_ctrl_translator:uav_readdata -> acl_kernel_clk_ctrl_agent:m0_readdata
wire acl_kernel_clk_ctrl_agent_m0_readdatavalid; // acl_kernel_clk_ctrl_translator:uav_readdatavalid -> acl_kernel_clk_ctrl_agent:m0_readdatavalid
wire acl_kernel_clk_ctrl_agent_m0_debugaccess; // acl_kernel_clk_ctrl_agent:m0_debugaccess -> acl_kernel_clk_ctrl_translator:uav_debugaccess
wire [3:0] acl_kernel_clk_ctrl_agent_m0_byteenable; // acl_kernel_clk_ctrl_agent:m0_byteenable -> acl_kernel_clk_ctrl_translator:uav_byteenable
wire acl_kernel_clk_ctrl_agent_rf_source_endofpacket; // acl_kernel_clk_ctrl_agent:rf_source_endofpacket -> acl_kernel_clk_ctrl_agent_rsp_fifo:in_endofpacket
wire acl_kernel_clk_ctrl_agent_rf_source_valid; // acl_kernel_clk_ctrl_agent:rf_source_valid -> acl_kernel_clk_ctrl_agent_rsp_fifo:in_valid
wire acl_kernel_clk_ctrl_agent_rf_source_startofpacket; // acl_kernel_clk_ctrl_agent:rf_source_startofpacket -> acl_kernel_clk_ctrl_agent_rsp_fifo:in_startofpacket
wire [114:0] acl_kernel_clk_ctrl_agent_rf_source_data; // acl_kernel_clk_ctrl_agent:rf_source_data -> acl_kernel_clk_ctrl_agent_rsp_fifo:in_data
wire acl_kernel_clk_ctrl_agent_rf_source_ready; // acl_kernel_clk_ctrl_agent_rsp_fifo:in_ready -> acl_kernel_clk_ctrl_agent:rf_source_ready
wire acl_kernel_clk_ctrl_agent_rsp_fifo_out_endofpacket; // acl_kernel_clk_ctrl_agent_rsp_fifo:out_endofpacket -> acl_kernel_clk_ctrl_agent:rf_sink_endofpacket
wire acl_kernel_clk_ctrl_agent_rsp_fifo_out_valid; // acl_kernel_clk_ctrl_agent_rsp_fifo:out_valid -> acl_kernel_clk_ctrl_agent:rf_sink_valid
wire acl_kernel_clk_ctrl_agent_rsp_fifo_out_startofpacket; // acl_kernel_clk_ctrl_agent_rsp_fifo:out_startofpacket -> acl_kernel_clk_ctrl_agent:rf_sink_startofpacket
wire [114:0] acl_kernel_clk_ctrl_agent_rsp_fifo_out_data; // acl_kernel_clk_ctrl_agent_rsp_fifo:out_data -> acl_kernel_clk_ctrl_agent:rf_sink_data
wire acl_kernel_clk_ctrl_agent_rsp_fifo_out_ready; // acl_kernel_clk_ctrl_agent:rf_sink_ready -> acl_kernel_clk_ctrl_agent_rsp_fifo:out_ready
wire acl_kernel_clk_ctrl_agent_rdata_fifo_src_valid; // acl_kernel_clk_ctrl_agent:rdata_fifo_src_valid -> acl_kernel_clk_ctrl_agent_rdata_fifo:in_valid
wire [33:0] acl_kernel_clk_ctrl_agent_rdata_fifo_src_data; // acl_kernel_clk_ctrl_agent:rdata_fifo_src_data -> acl_kernel_clk_ctrl_agent_rdata_fifo:in_data
wire acl_kernel_clk_ctrl_agent_rdata_fifo_src_ready; // acl_kernel_clk_ctrl_agent_rdata_fifo:in_ready -> acl_kernel_clk_ctrl_agent:rdata_fifo_src_ready
wire acl_kernel_clk_ctrl_agent_rdata_fifo_out_valid; // acl_kernel_clk_ctrl_agent_rdata_fifo:out_valid -> acl_kernel_clk_ctrl_agent:rdata_fifo_sink_valid
wire [33:0] acl_kernel_clk_ctrl_agent_rdata_fifo_out_data; // acl_kernel_clk_ctrl_agent_rdata_fifo:out_data -> acl_kernel_clk_ctrl_agent:rdata_fifo_sink_data
wire acl_kernel_clk_ctrl_agent_rdata_fifo_out_ready; // acl_kernel_clk_ctrl_agent:rdata_fifo_sink_ready -> acl_kernel_clk_ctrl_agent_rdata_fifo:out_ready
wire hps_h2f_lw_axi_master_agent_write_cp_endofpacket; // hps_h2f_lw_axi_master_agent:write_cp_endofpacket -> router:sink_endofpacket
wire hps_h2f_lw_axi_master_agent_write_cp_valid; // hps_h2f_lw_axi_master_agent:write_cp_valid -> router:sink_valid
wire hps_h2f_lw_axi_master_agent_write_cp_startofpacket; // hps_h2f_lw_axi_master_agent:write_cp_startofpacket -> router:sink_startofpacket
wire [113:0] hps_h2f_lw_axi_master_agent_write_cp_data; // hps_h2f_lw_axi_master_agent:write_cp_data -> router:sink_data
wire hps_h2f_lw_axi_master_agent_write_cp_ready; // router:sink_ready -> hps_h2f_lw_axi_master_agent:write_cp_ready
wire hps_h2f_lw_axi_master_agent_read_cp_endofpacket; // hps_h2f_lw_axi_master_agent:read_cp_endofpacket -> router_001:sink_endofpacket
wire hps_h2f_lw_axi_master_agent_read_cp_valid; // hps_h2f_lw_axi_master_agent:read_cp_valid -> router_001:sink_valid
wire hps_h2f_lw_axi_master_agent_read_cp_startofpacket; // hps_h2f_lw_axi_master_agent:read_cp_startofpacket -> router_001:sink_startofpacket
wire [113:0] hps_h2f_lw_axi_master_agent_read_cp_data; // hps_h2f_lw_axi_master_agent:read_cp_data -> router_001:sink_data
wire hps_h2f_lw_axi_master_agent_read_cp_ready; // router_001:sink_ready -> hps_h2f_lw_axi_master_agent:read_cp_ready
wire version_id_s_agent_rp_endofpacket; // version_id_s_agent:rp_endofpacket -> router_002:sink_endofpacket
wire version_id_s_agent_rp_valid; // version_id_s_agent:rp_valid -> router_002:sink_valid
wire version_id_s_agent_rp_startofpacket; // version_id_s_agent:rp_startofpacket -> router_002:sink_startofpacket
wire [113:0] version_id_s_agent_rp_data; // version_id_s_agent:rp_data -> router_002:sink_data
wire version_id_s_agent_rp_ready; // router_002:sink_ready -> version_id_s_agent:rp_ready
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire [113:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire [2:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire acl_kernel_interface_kernel_cntrl_agent_rp_endofpacket; // acl_kernel_interface_kernel_cntrl_agent:rp_endofpacket -> router_003:sink_endofpacket
wire acl_kernel_interface_kernel_cntrl_agent_rp_valid; // acl_kernel_interface_kernel_cntrl_agent:rp_valid -> router_003:sink_valid
wire acl_kernel_interface_kernel_cntrl_agent_rp_startofpacket; // acl_kernel_interface_kernel_cntrl_agent:rp_startofpacket -> router_003:sink_startofpacket
wire [113:0] acl_kernel_interface_kernel_cntrl_agent_rp_data; // acl_kernel_interface_kernel_cntrl_agent:rp_data -> router_003:sink_data
wire acl_kernel_interface_kernel_cntrl_agent_rp_ready; // router_003:sink_ready -> acl_kernel_interface_kernel_cntrl_agent:rp_ready
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire [113:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire [2:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire acl_kernel_clk_ctrl_agent_rp_endofpacket; // acl_kernel_clk_ctrl_agent:rp_endofpacket -> router_004:sink_endofpacket
wire acl_kernel_clk_ctrl_agent_rp_valid; // acl_kernel_clk_ctrl_agent:rp_valid -> router_004:sink_valid
wire acl_kernel_clk_ctrl_agent_rp_startofpacket; // acl_kernel_clk_ctrl_agent:rp_startofpacket -> router_004:sink_startofpacket
wire [113:0] acl_kernel_clk_ctrl_agent_rp_data; // acl_kernel_clk_ctrl_agent:rp_data -> router_004:sink_data
wire acl_kernel_clk_ctrl_agent_rp_ready; // router_004:sink_ready -> acl_kernel_clk_ctrl_agent:rp_ready
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire [113:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire [2:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire router_src_endofpacket; // router:src_endofpacket -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_endofpacket
wire router_src_valid; // router:src_valid -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_startofpacket
wire [113:0] router_src_data; // router:src_data -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_data
wire [2:0] router_src_channel; // router:src_channel -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_channel
wire router_src_ready; // hps_h2f_lw_axi_master_wr_limiter:cmd_sink_ready -> router:src_ready
wire hps_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire hps_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire [113:0] hps_h2f_lw_axi_master_wr_limiter_cmd_src_data; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_data -> cmd_demux:sink_data
wire [2:0] hps_h2f_lw_axi_master_wr_limiter_cmd_src_channel; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire hps_h2f_lw_axi_master_wr_limiter_cmd_src_ready; // cmd_demux:sink_ready -> hps_h2f_lw_axi_master_wr_limiter:cmd_src_ready
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_startofpacket
wire [113:0] rsp_mux_src_data; // rsp_mux:src_data -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_data
wire [2:0] rsp_mux_src_channel; // rsp_mux:src_channel -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_channel
wire rsp_mux_src_ready; // hps_h2f_lw_axi_master_wr_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire hps_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_endofpacket -> hps_h2f_lw_axi_master_agent:write_rp_endofpacket
wire hps_h2f_lw_axi_master_wr_limiter_rsp_src_valid; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_valid -> hps_h2f_lw_axi_master_agent:write_rp_valid
wire hps_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_startofpacket -> hps_h2f_lw_axi_master_agent:write_rp_startofpacket
wire [113:0] hps_h2f_lw_axi_master_wr_limiter_rsp_src_data; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_data -> hps_h2f_lw_axi_master_agent:write_rp_data
wire [2:0] hps_h2f_lw_axi_master_wr_limiter_rsp_src_channel; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_channel -> hps_h2f_lw_axi_master_agent:write_rp_channel
wire hps_h2f_lw_axi_master_wr_limiter_rsp_src_ready; // hps_h2f_lw_axi_master_agent:write_rp_ready -> hps_h2f_lw_axi_master_wr_limiter:rsp_src_ready
wire router_001_src_endofpacket; // router_001:src_endofpacket -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_startofpacket
wire [113:0] router_001_src_data; // router_001:src_data -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_data
wire [2:0] router_001_src_channel; // router_001:src_channel -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_channel
wire router_001_src_ready; // hps_h2f_lw_axi_master_rd_limiter:cmd_sink_ready -> router_001:src_ready
wire hps_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
wire hps_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
wire [113:0] hps_h2f_lw_axi_master_rd_limiter_cmd_src_data; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_data -> cmd_demux_001:sink_data
wire [2:0] hps_h2f_lw_axi_master_rd_limiter_cmd_src_channel; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
wire hps_h2f_lw_axi_master_rd_limiter_cmd_src_ready; // cmd_demux_001:sink_ready -> hps_h2f_lw_axi_master_rd_limiter:cmd_src_ready
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_valid
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_startofpacket
wire [113:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_data
wire [2:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_channel
wire rsp_mux_001_src_ready; // hps_h2f_lw_axi_master_rd_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
wire hps_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_endofpacket -> hps_h2f_lw_axi_master_agent:read_rp_endofpacket
wire hps_h2f_lw_axi_master_rd_limiter_rsp_src_valid; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_valid -> hps_h2f_lw_axi_master_agent:read_rp_valid
wire hps_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_startofpacket -> hps_h2f_lw_axi_master_agent:read_rp_startofpacket
wire [113:0] hps_h2f_lw_axi_master_rd_limiter_rsp_src_data; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_data -> hps_h2f_lw_axi_master_agent:read_rp_data
wire [2:0] hps_h2f_lw_axi_master_rd_limiter_rsp_src_channel; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_channel -> hps_h2f_lw_axi_master_agent:read_rp_channel
wire hps_h2f_lw_axi_master_rd_limiter_rsp_src_ready; // hps_h2f_lw_axi_master_agent:read_rp_ready -> hps_h2f_lw_axi_master_rd_limiter:rsp_src_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> version_id_s_burst_adapter:sink0_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> version_id_s_burst_adapter:sink0_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> version_id_s_burst_adapter:sink0_startofpacket
wire [113:0] cmd_mux_src_data; // cmd_mux:src_data -> version_id_s_burst_adapter:sink0_data
wire [2:0] cmd_mux_src_channel; // cmd_mux:src_channel -> version_id_s_burst_adapter:sink0_channel
wire cmd_mux_src_ready; // version_id_s_burst_adapter:sink0_ready -> cmd_mux:src_ready
wire version_id_s_burst_adapter_source0_endofpacket; // version_id_s_burst_adapter:source0_endofpacket -> version_id_s_agent:cp_endofpacket
wire version_id_s_burst_adapter_source0_valid; // version_id_s_burst_adapter:source0_valid -> version_id_s_agent:cp_valid
wire version_id_s_burst_adapter_source0_startofpacket; // version_id_s_burst_adapter:source0_startofpacket -> version_id_s_agent:cp_startofpacket
wire [113:0] version_id_s_burst_adapter_source0_data; // version_id_s_burst_adapter:source0_data -> version_id_s_agent:cp_data
wire version_id_s_burst_adapter_source0_ready; // version_id_s_agent:cp_ready -> version_id_s_burst_adapter:source0_ready
wire [2:0] version_id_s_burst_adapter_source0_channel; // version_id_s_burst_adapter:source0_channel -> version_id_s_agent:cp_channel
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_valid
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_startofpacket
wire [113:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_data
wire [2:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_channel
wire cmd_mux_001_src_ready; // acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_ready -> cmd_mux_001:src_ready
wire acl_kernel_interface_kernel_cntrl_burst_adapter_source0_endofpacket; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_endofpacket -> acl_kernel_interface_kernel_cntrl_agent:cp_endofpacket
wire acl_kernel_interface_kernel_cntrl_burst_adapter_source0_valid; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_valid -> acl_kernel_interface_kernel_cntrl_agent:cp_valid
wire acl_kernel_interface_kernel_cntrl_burst_adapter_source0_startofpacket; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_startofpacket -> acl_kernel_interface_kernel_cntrl_agent:cp_startofpacket
wire [113:0] acl_kernel_interface_kernel_cntrl_burst_adapter_source0_data; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_data -> acl_kernel_interface_kernel_cntrl_agent:cp_data
wire acl_kernel_interface_kernel_cntrl_burst_adapter_source0_ready; // acl_kernel_interface_kernel_cntrl_agent:cp_ready -> acl_kernel_interface_kernel_cntrl_burst_adapter:source0_ready
wire [2:0] acl_kernel_interface_kernel_cntrl_burst_adapter_source0_channel; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_channel -> acl_kernel_interface_kernel_cntrl_agent:cp_channel
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> acl_kernel_clk_ctrl_burst_adapter:sink0_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> acl_kernel_clk_ctrl_burst_adapter:sink0_valid
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> acl_kernel_clk_ctrl_burst_adapter:sink0_startofpacket
wire [113:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> acl_kernel_clk_ctrl_burst_adapter:sink0_data
wire [2:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> acl_kernel_clk_ctrl_burst_adapter:sink0_channel
wire cmd_mux_002_src_ready; // acl_kernel_clk_ctrl_burst_adapter:sink0_ready -> cmd_mux_002:src_ready
wire acl_kernel_clk_ctrl_burst_adapter_source0_endofpacket; // acl_kernel_clk_ctrl_burst_adapter:source0_endofpacket -> acl_kernel_clk_ctrl_agent:cp_endofpacket
wire acl_kernel_clk_ctrl_burst_adapter_source0_valid; // acl_kernel_clk_ctrl_burst_adapter:source0_valid -> acl_kernel_clk_ctrl_agent:cp_valid
wire acl_kernel_clk_ctrl_burst_adapter_source0_startofpacket; // acl_kernel_clk_ctrl_burst_adapter:source0_startofpacket -> acl_kernel_clk_ctrl_agent:cp_startofpacket
wire [113:0] acl_kernel_clk_ctrl_burst_adapter_source0_data; // acl_kernel_clk_ctrl_burst_adapter:source0_data -> acl_kernel_clk_ctrl_agent:cp_data
wire acl_kernel_clk_ctrl_burst_adapter_source0_ready; // acl_kernel_clk_ctrl_agent:cp_ready -> acl_kernel_clk_ctrl_burst_adapter:source0_ready
wire [2:0] acl_kernel_clk_ctrl_burst_adapter_source0_channel; // acl_kernel_clk_ctrl_burst_adapter:source0_channel -> acl_kernel_clk_ctrl_agent:cp_channel
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire [113:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire [2:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire [113:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire [2:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire [113:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire [2:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire [113:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire [2:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink1_valid
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
wire [113:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink1_data
wire [2:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src1_ready
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink1_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_002:sink1_valid
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink1_startofpacket
wire [113:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_002:sink1_data
wire [2:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_001_src2_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src2_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire [113:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire [2:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire [113:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire [2:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire [113:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire [2:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink1_valid
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire [113:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink1_data
wire [2:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src1_ready
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire [113:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire [2:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink2_valid
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink2_startofpacket
wire [113:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink2_data
wire [2:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_002_src1_ready; // rsp_mux_001:sink2_ready -> rsp_demux_002:src1_ready
wire [2:0] hps_h2f_lw_axi_master_wr_limiter_cmd_valid_data; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_valid -> cmd_demux:sink_valid
wire [2:0] hps_h2f_lw_axi_master_rd_limiter_cmd_valid_data; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (21),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) version_id_s_translator (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (version_id_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (version_id_s_agent_m0_burstcount), // .burstcount
.uav_read (version_id_s_agent_m0_read), // .read
.uav_write (version_id_s_agent_m0_write), // .write
.uav_waitrequest (version_id_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (version_id_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (version_id_s_agent_m0_byteenable), // .byteenable
.uav_readdata (version_id_s_agent_m0_readdata), // .readdata
.uav_writedata (version_id_s_agent_m0_writedata), // .writedata
.uav_lock (version_id_s_agent_m0_lock), // .lock
.uav_debugaccess (version_id_s_agent_m0_debugaccess), // .debugaccess
.av_read (version_id_s_read), // avalon_anti_slave_0.read
.av_readdata (version_id_s_readdata), // .readdata
.av_address (), // (terminated)
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (14),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (21),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) acl_kernel_interface_kernel_cntrl_translator (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (acl_kernel_interface_kernel_cntrl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (acl_kernel_interface_kernel_cntrl_agent_m0_burstcount), // .burstcount
.uav_read (acl_kernel_interface_kernel_cntrl_agent_m0_read), // .read
.uav_write (acl_kernel_interface_kernel_cntrl_agent_m0_write), // .write
.uav_waitrequest (acl_kernel_interface_kernel_cntrl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (acl_kernel_interface_kernel_cntrl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (acl_kernel_interface_kernel_cntrl_agent_m0_byteenable), // .byteenable
.uav_readdata (acl_kernel_interface_kernel_cntrl_agent_m0_readdata), // .readdata
.uav_writedata (acl_kernel_interface_kernel_cntrl_agent_m0_writedata), // .writedata
.uav_lock (acl_kernel_interface_kernel_cntrl_agent_m0_lock), // .lock
.uav_debugaccess (acl_kernel_interface_kernel_cntrl_agent_m0_debugaccess), // .debugaccess
.av_address (acl_kernel_interface_kernel_cntrl_address), // avalon_anti_slave_0.address
.av_write (acl_kernel_interface_kernel_cntrl_write), // .write
.av_read (acl_kernel_interface_kernel_cntrl_read), // .read
.av_readdata (acl_kernel_interface_kernel_cntrl_readdata), // .readdata
.av_writedata (acl_kernel_interface_kernel_cntrl_writedata), // .writedata
.av_burstcount (acl_kernel_interface_kernel_cntrl_burstcount), // .burstcount
.av_byteenable (acl_kernel_interface_kernel_cntrl_byteenable), // .byteenable
.av_readdatavalid (acl_kernel_interface_kernel_cntrl_readdatavalid), // .readdatavalid
.av_waitrequest (acl_kernel_interface_kernel_cntrl_waitrequest), // .waitrequest
.av_debugaccess (acl_kernel_interface_kernel_cntrl_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (11),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (21),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) acl_kernel_clk_ctrl_translator (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (acl_kernel_clk_ctrl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (acl_kernel_clk_ctrl_agent_m0_burstcount), // .burstcount
.uav_read (acl_kernel_clk_ctrl_agent_m0_read), // .read
.uav_write (acl_kernel_clk_ctrl_agent_m0_write), // .write
.uav_waitrequest (acl_kernel_clk_ctrl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (acl_kernel_clk_ctrl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (acl_kernel_clk_ctrl_agent_m0_byteenable), // .byteenable
.uav_readdata (acl_kernel_clk_ctrl_agent_m0_readdata), // .readdata
.uav_writedata (acl_kernel_clk_ctrl_agent_m0_writedata), // .writedata
.uav_lock (acl_kernel_clk_ctrl_agent_m0_lock), // .lock
.uav_debugaccess (acl_kernel_clk_ctrl_agent_m0_debugaccess), // .debugaccess
.av_address (acl_kernel_clk_ctrl_address), // avalon_anti_slave_0.address
.av_write (acl_kernel_clk_ctrl_write), // .write
.av_read (acl_kernel_clk_ctrl_read), // .read
.av_readdata (acl_kernel_clk_ctrl_readdata), // .readdata
.av_writedata (acl_kernel_clk_ctrl_writedata), // .writedata
.av_burstcount (acl_kernel_clk_ctrl_burstcount), // .burstcount
.av_byteenable (acl_kernel_clk_ctrl_byteenable), // .byteenable
.av_readdatavalid (acl_kernel_clk_ctrl_readdatavalid), // .readdatavalid
.av_waitrequest (acl_kernel_clk_ctrl_waitrequest), // .waitrequest
.av_debugaccess (acl_kernel_clk_ctrl_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_axi_master_ni #(
.ID_WIDTH (12),
.ADDR_WIDTH (21),
.RDATA_WIDTH (32),
.WDATA_WIDTH (32),
.ADDR_USER_WIDTH (1),
.DATA_USER_WIDTH (1),
.AXI_BURST_LENGTH_WIDTH (4),
.AXI_LOCK_WIDTH (2),
.AXI_VERSION ("AXI3"),
.WRITE_ISSUING_CAPABILITY (8),
.READ_ISSUING_CAPABILITY (8),
.PKT_BEGIN_BURST (84),
.PKT_CACHE_H (108),
.PKT_CACHE_L (105),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_RESPONSE_STATUS_L (109),
.PKT_RESPONSE_STATUS_H (110),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_EXCLUSIVE (62),
.PKT_TRANS_LOCK (61),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_THREAD_ID_H (101),
.PKT_THREAD_ID_L (90),
.PKT_QOS_L (85),
.PKT_QOS_H (85),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_ORI_BURST_SIZE_H (113),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.ID (0)
) hps_h2f_lw_axi_master_agent (
.aclk (config_clk_out_clk_clk), // clk.clk
.aresetn (~hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
.write_cp_valid (hps_h2f_lw_axi_master_agent_write_cp_valid), // write_cp.valid
.write_cp_data (hps_h2f_lw_axi_master_agent_write_cp_data), // .data
.write_cp_startofpacket (hps_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.write_cp_endofpacket (hps_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.write_cp_ready (hps_h2f_lw_axi_master_agent_write_cp_ready), // .ready
.write_rp_valid (hps_h2f_lw_axi_master_wr_limiter_rsp_src_valid), // write_rp.valid
.write_rp_data (hps_h2f_lw_axi_master_wr_limiter_rsp_src_data), // .data
.write_rp_channel (hps_h2f_lw_axi_master_wr_limiter_rsp_src_channel), // .channel
.write_rp_startofpacket (hps_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket), // .startofpacket
.write_rp_endofpacket (hps_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket), // .endofpacket
.write_rp_ready (hps_h2f_lw_axi_master_wr_limiter_rsp_src_ready), // .ready
.read_cp_valid (hps_h2f_lw_axi_master_agent_read_cp_valid), // read_cp.valid
.read_cp_data (hps_h2f_lw_axi_master_agent_read_cp_data), // .data
.read_cp_startofpacket (hps_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.read_cp_endofpacket (hps_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.read_cp_ready (hps_h2f_lw_axi_master_agent_read_cp_ready), // .ready
.read_rp_valid (hps_h2f_lw_axi_master_rd_limiter_rsp_src_valid), // read_rp.valid
.read_rp_data (hps_h2f_lw_axi_master_rd_limiter_rsp_src_data), // .data
.read_rp_channel (hps_h2f_lw_axi_master_rd_limiter_rsp_src_channel), // .channel
.read_rp_startofpacket (hps_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket), // .startofpacket
.read_rp_endofpacket (hps_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket), // .endofpacket
.read_rp_ready (hps_h2f_lw_axi_master_rd_limiter_rsp_src_ready), // .ready
.awid (hps_h2f_lw_axi_master_awid), // altera_axi_slave.awid
.awaddr (hps_h2f_lw_axi_master_awaddr), // .awaddr
.awlen (hps_h2f_lw_axi_master_awlen), // .awlen
.awsize (hps_h2f_lw_axi_master_awsize), // .awsize
.awburst (hps_h2f_lw_axi_master_awburst), // .awburst
.awlock (hps_h2f_lw_axi_master_awlock), // .awlock
.awcache (hps_h2f_lw_axi_master_awcache), // .awcache
.awprot (hps_h2f_lw_axi_master_awprot), // .awprot
.awvalid (hps_h2f_lw_axi_master_awvalid), // .awvalid
.awready (hps_h2f_lw_axi_master_awready), // .awready
.wid (hps_h2f_lw_axi_master_wid), // .wid
.wdata (hps_h2f_lw_axi_master_wdata), // .wdata
.wstrb (hps_h2f_lw_axi_master_wstrb), // .wstrb
.wlast (hps_h2f_lw_axi_master_wlast), // .wlast
.wvalid (hps_h2f_lw_axi_master_wvalid), // .wvalid
.wready (hps_h2f_lw_axi_master_wready), // .wready
.bid (hps_h2f_lw_axi_master_bid), // .bid
.bresp (hps_h2f_lw_axi_master_bresp), // .bresp
.bvalid (hps_h2f_lw_axi_master_bvalid), // .bvalid
.bready (hps_h2f_lw_axi_master_bready), // .bready
.arid (hps_h2f_lw_axi_master_arid), // .arid
.araddr (hps_h2f_lw_axi_master_araddr), // .araddr
.arlen (hps_h2f_lw_axi_master_arlen), // .arlen
.arsize (hps_h2f_lw_axi_master_arsize), // .arsize
.arburst (hps_h2f_lw_axi_master_arburst), // .arburst
.arlock (hps_h2f_lw_axi_master_arlock), // .arlock
.arcache (hps_h2f_lw_axi_master_arcache), // .arcache
.arprot (hps_h2f_lw_axi_master_arprot), // .arprot
.arvalid (hps_h2f_lw_axi_master_arvalid), // .arvalid
.arready (hps_h2f_lw_axi_master_arready), // .arready
.rid (hps_h2f_lw_axi_master_rid), // .rid
.rdata (hps_h2f_lw_axi_master_rdata), // .rdata
.rresp (hps_h2f_lw_axi_master_rresp), // .rresp
.rlast (hps_h2f_lw_axi_master_rlast), // .rlast
.rvalid (hps_h2f_lw_axi_master_rvalid), // .rvalid
.rready (hps_h2f_lw_axi_master_rready), // .rready
.awuser (1'b0), // (terminated)
.aruser (1'b0), // (terminated)
.awqos (4'b0000), // (terminated)
.arqos (4'b0000), // (terminated)
.awregion (4'b0000), // (terminated)
.arregion (4'b0000), // (terminated)
.wuser (1'b0), // (terminated)
.ruser (), // (terminated)
.buser () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_TRANS_LOCK (61),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_RESPONSE_STATUS_H (110),
.PKT_RESPONSE_STATUS_L (109),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_ORI_BURST_SIZE_H (113),
.ST_CHANNEL_W (3),
.ST_DATA_W (114),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) version_id_s_agent (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (version_id_s_agent_m0_address), // m0.address
.m0_burstcount (version_id_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (version_id_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (version_id_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (version_id_s_agent_m0_lock), // .lock
.m0_readdata (version_id_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (version_id_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (version_id_s_agent_m0_read), // .read
.m0_waitrequest (version_id_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (version_id_s_agent_m0_writedata), // .writedata
.m0_write (version_id_s_agent_m0_write), // .write
.rp_endofpacket (version_id_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (version_id_s_agent_rp_ready), // .ready
.rp_valid (version_id_s_agent_rp_valid), // .valid
.rp_data (version_id_s_agent_rp_data), // .data
.rp_startofpacket (version_id_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (version_id_s_burst_adapter_source0_ready), // cp.ready
.cp_valid (version_id_s_burst_adapter_source0_valid), // .valid
.cp_data (version_id_s_burst_adapter_source0_data), // .data
.cp_startofpacket (version_id_s_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (version_id_s_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (version_id_s_burst_adapter_source0_channel), // .channel
.rf_sink_ready (version_id_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (version_id_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (version_id_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (version_id_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (version_id_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (version_id_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (version_id_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (version_id_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (version_id_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (version_id_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (version_id_s_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (version_id_s_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (version_id_s_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (version_id_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (version_id_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (version_id_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (115),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) version_id_s_agent_rsp_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (version_id_s_agent_rf_source_data), // in.data
.in_valid (version_id_s_agent_rf_source_valid), // .valid
.in_ready (version_id_s_agent_rf_source_ready), // .ready
.in_startofpacket (version_id_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (version_id_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (version_id_s_agent_rsp_fifo_out_data), // out.data
.out_valid (version_id_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (version_id_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (version_id_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (version_id_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) version_id_s_agent_rdata_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (version_id_s_agent_rdata_fifo_src_data), // in.data
.in_valid (version_id_s_agent_rdata_fifo_src_valid), // .valid
.in_ready (version_id_s_agent_rdata_fifo_src_ready), // .ready
.out_data (version_id_s_agent_rdata_fifo_out_data), // out.data
.out_valid (version_id_s_agent_rdata_fifo_out_valid), // .valid
.out_ready (version_id_s_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_TRANS_LOCK (61),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_RESPONSE_STATUS_H (110),
.PKT_RESPONSE_STATUS_L (109),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_ORI_BURST_SIZE_H (113),
.ST_CHANNEL_W (3),
.ST_DATA_W (114),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) acl_kernel_interface_kernel_cntrl_agent (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (acl_kernel_interface_kernel_cntrl_agent_m0_address), // m0.address
.m0_burstcount (acl_kernel_interface_kernel_cntrl_agent_m0_burstcount), // .burstcount
.m0_byteenable (acl_kernel_interface_kernel_cntrl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (acl_kernel_interface_kernel_cntrl_agent_m0_debugaccess), // .debugaccess
.m0_lock (acl_kernel_interface_kernel_cntrl_agent_m0_lock), // .lock
.m0_readdata (acl_kernel_interface_kernel_cntrl_agent_m0_readdata), // .readdata
.m0_readdatavalid (acl_kernel_interface_kernel_cntrl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (acl_kernel_interface_kernel_cntrl_agent_m0_read), // .read
.m0_waitrequest (acl_kernel_interface_kernel_cntrl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (acl_kernel_interface_kernel_cntrl_agent_m0_writedata), // .writedata
.m0_write (acl_kernel_interface_kernel_cntrl_agent_m0_write), // .write
.rp_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (acl_kernel_interface_kernel_cntrl_agent_rp_ready), // .ready
.rp_valid (acl_kernel_interface_kernel_cntrl_agent_rp_valid), // .valid
.rp_data (acl_kernel_interface_kernel_cntrl_agent_rp_data), // .data
.rp_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rp_startofpacket), // .startofpacket
.cp_ready (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_ready), // cp.ready
.cp_valid (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_valid), // .valid
.cp_data (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_data), // .data
.cp_startofpacket (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_channel), // .channel
.rf_sink_ready (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (acl_kernel_interface_kernel_cntrl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (acl_kernel_interface_kernel_cntrl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (acl_kernel_interface_kernel_cntrl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (115),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) acl_kernel_interface_kernel_cntrl_agent_rsp_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (acl_kernel_interface_kernel_cntrl_agent_rf_source_data), // in.data
.in_valid (acl_kernel_interface_kernel_cntrl_agent_rf_source_valid), // .valid
.in_ready (acl_kernel_interface_kernel_cntrl_agent_rf_source_ready), // .ready
.in_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rf_source_endofpacket), // .endofpacket
.out_data (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_data), // out.data
.out_valid (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_valid), // .valid
.out_ready (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) acl_kernel_interface_kernel_cntrl_agent_rdata_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_data), // in.data
.in_valid (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_valid), // .valid
.in_ready (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_ready), // .ready
.out_data (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_data), // out.data
.out_valid (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_valid), // .valid
.out_ready (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_TRANS_LOCK (61),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_RESPONSE_STATUS_H (110),
.PKT_RESPONSE_STATUS_L (109),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_ORI_BURST_SIZE_H (113),
.ST_CHANNEL_W (3),
.ST_DATA_W (114),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) acl_kernel_clk_ctrl_agent (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (acl_kernel_clk_ctrl_agent_m0_address), // m0.address
.m0_burstcount (acl_kernel_clk_ctrl_agent_m0_burstcount), // .burstcount
.m0_byteenable (acl_kernel_clk_ctrl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (acl_kernel_clk_ctrl_agent_m0_debugaccess), // .debugaccess
.m0_lock (acl_kernel_clk_ctrl_agent_m0_lock), // .lock
.m0_readdata (acl_kernel_clk_ctrl_agent_m0_readdata), // .readdata
.m0_readdatavalid (acl_kernel_clk_ctrl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (acl_kernel_clk_ctrl_agent_m0_read), // .read
.m0_waitrequest (acl_kernel_clk_ctrl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (acl_kernel_clk_ctrl_agent_m0_writedata), // .writedata
.m0_write (acl_kernel_clk_ctrl_agent_m0_write), // .write
.rp_endofpacket (acl_kernel_clk_ctrl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (acl_kernel_clk_ctrl_agent_rp_ready), // .ready
.rp_valid (acl_kernel_clk_ctrl_agent_rp_valid), // .valid
.rp_data (acl_kernel_clk_ctrl_agent_rp_data), // .data
.rp_startofpacket (acl_kernel_clk_ctrl_agent_rp_startofpacket), // .startofpacket
.cp_ready (acl_kernel_clk_ctrl_burst_adapter_source0_ready), // cp.ready
.cp_valid (acl_kernel_clk_ctrl_burst_adapter_source0_valid), // .valid
.cp_data (acl_kernel_clk_ctrl_burst_adapter_source0_data), // .data
.cp_startofpacket (acl_kernel_clk_ctrl_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (acl_kernel_clk_ctrl_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (acl_kernel_clk_ctrl_burst_adapter_source0_channel), // .channel
.rf_sink_ready (acl_kernel_clk_ctrl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (acl_kernel_clk_ctrl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (acl_kernel_clk_ctrl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (acl_kernel_clk_ctrl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (acl_kernel_clk_ctrl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (acl_kernel_clk_ctrl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (acl_kernel_clk_ctrl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (acl_kernel_clk_ctrl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (acl_kernel_clk_ctrl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (acl_kernel_clk_ctrl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (acl_kernel_clk_ctrl_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (acl_kernel_clk_ctrl_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (acl_kernel_clk_ctrl_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (acl_kernel_clk_ctrl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (acl_kernel_clk_ctrl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (acl_kernel_clk_ctrl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (115),
.FIFO_DEPTH (5),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) acl_kernel_clk_ctrl_agent_rsp_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (acl_kernel_clk_ctrl_agent_rf_source_data), // in.data
.in_valid (acl_kernel_clk_ctrl_agent_rf_source_valid), // .valid
.in_ready (acl_kernel_clk_ctrl_agent_rf_source_ready), // .ready
.in_startofpacket (acl_kernel_clk_ctrl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (acl_kernel_clk_ctrl_agent_rf_source_endofpacket), // .endofpacket
.out_data (acl_kernel_clk_ctrl_agent_rsp_fifo_out_data), // out.data
.out_valid (acl_kernel_clk_ctrl_agent_rsp_fifo_out_valid), // .valid
.out_ready (acl_kernel_clk_ctrl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (acl_kernel_clk_ctrl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (acl_kernel_clk_ctrl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) acl_kernel_clk_ctrl_agent_rdata_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (acl_kernel_clk_ctrl_agent_rdata_fifo_src_data), // in.data
.in_valid (acl_kernel_clk_ctrl_agent_rdata_fifo_src_valid), // .valid
.in_ready (acl_kernel_clk_ctrl_agent_rdata_fifo_src_ready), // .ready
.out_data (acl_kernel_clk_ctrl_agent_rdata_fifo_out_data), // out.data
.out_valid (acl_kernel_clk_ctrl_agent_rdata_fifo_out_valid), // .valid
.out_ready (acl_kernel_clk_ctrl_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_mm_interconnect_0_router router (
.sink_ready (hps_h2f_lw_axi_master_agent_write_cp_ready), // sink.ready
.sink_valid (hps_h2f_lw_axi_master_agent_write_cp_valid), // .valid
.sink_data (hps_h2f_lw_axi_master_agent_write_cp_data), // .data
.sink_startofpacket (hps_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_router router_001 (
.sink_ready (hps_h2f_lw_axi_master_agent_read_cp_ready), // sink.ready
.sink_valid (hps_h2f_lw_axi_master_agent_read_cp_valid), // .valid
.sink_data (hps_h2f_lw_axi_master_agent_read_cp_data), // .data
.sink_startofpacket (hps_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_router_002 router_002 (
.sink_ready (version_id_s_agent_rp_ready), // sink.ready
.sink_valid (version_id_s_agent_rp_valid), // .valid
.sink_data (version_id_s_agent_rp_data), // .data
.sink_startofpacket (version_id_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (version_id_s_agent_rp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_router_002 router_003 (
.sink_ready (acl_kernel_interface_kernel_cntrl_agent_rp_ready), // sink.ready
.sink_valid (acl_kernel_interface_kernel_cntrl_agent_rp_valid), // .valid
.sink_data (acl_kernel_interface_kernel_cntrl_agent_rp_data), // .data
.sink_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_router_002 router_004 (
.sink_ready (acl_kernel_clk_ctrl_agent_rp_ready), // sink.ready
.sink_valid (acl_kernel_clk_ctrl_agent_rp_valid), // .valid
.sink_data (acl_kernel_clk_ctrl_agent_rp_data), // .data
.sink_startofpacket (acl_kernel_clk_ctrl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (acl_kernel_clk_ctrl_agent_rp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.MAX_OUTSTANDING_RESPONSES (6),
.PIPELINED (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.VALID_WIDTH (3),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) hps_h2f_lw_axi_master_wr_limiter (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (hps_h2f_lw_axi_master_wr_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (hps_h2f_lw_axi_master_wr_limiter_cmd_src_data), // .data
.cmd_src_channel (hps_h2f_lw_axi_master_wr_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (hps_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (hps_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (hps_h2f_lw_axi_master_wr_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (hps_h2f_lw_axi_master_wr_limiter_rsp_src_valid), // .valid
.rsp_src_data (hps_h2f_lw_axi_master_wr_limiter_rsp_src_data), // .data
.rsp_src_channel (hps_h2f_lw_axi_master_wr_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (hps_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (hps_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (hps_h2f_lw_axi_master_wr_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.MAX_OUTSTANDING_RESPONSES (6),
.PIPELINED (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.VALID_WIDTH (3),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) hps_h2f_lw_axi_master_rd_limiter (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_001_src_valid), // .valid
.cmd_sink_data (router_001_src_data), // .data
.cmd_sink_channel (router_001_src_channel), // .channel
.cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (hps_h2f_lw_axi_master_rd_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (hps_h2f_lw_axi_master_rd_limiter_cmd_src_data), // .data
.cmd_src_channel (hps_h2f_lw_axi_master_rd_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (hps_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (hps_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (hps_h2f_lw_axi_master_rd_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (hps_h2f_lw_axi_master_rd_limiter_rsp_src_valid), // .valid
.rsp_src_data (hps_h2f_lw_axi_master_rd_limiter_rsp_src_data), // .data
.rsp_src_channel (hps_h2f_lw_axi_master_rd_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (hps_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (hps_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (hps_h2f_lw_axi_master_rd_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (84),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.OUT_BYTE_CNT_H (65),
.OUT_BURSTWRAP_H (76),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) version_id_s_burst_adapter (
.clk (config_clk_out_clk_clk), // cr0.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_src_valid), // sink0.valid
.sink0_data (cmd_mux_src_data), // .data
.sink0_channel (cmd_mux_src_channel), // .channel
.sink0_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_src_ready), // .ready
.source0_valid (version_id_s_burst_adapter_source0_valid), // source0.valid
.source0_data (version_id_s_burst_adapter_source0_data), // .data
.source0_channel (version_id_s_burst_adapter_source0_channel), // .channel
.source0_startofpacket (version_id_s_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (version_id_s_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (version_id_s_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (84),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.OUT_BYTE_CNT_H (65),
.OUT_BURSTWRAP_H (76),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) acl_kernel_interface_kernel_cntrl_burst_adapter (
.clk (config_clk_out_clk_clk), // cr0.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_001_src_valid), // sink0.valid
.sink0_data (cmd_mux_001_src_data), // .data
.sink0_channel (cmd_mux_001_src_channel), // .channel
.sink0_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_001_src_ready), // .ready
.source0_valid (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_valid), // source0.valid
.source0_data (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_data), // .data
.source0_channel (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_channel), // .channel
.source0_startofpacket (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (84),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.OUT_BYTE_CNT_H (65),
.OUT_BURSTWRAP_H (76),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) acl_kernel_clk_ctrl_burst_adapter (
.clk (config_clk_out_clk_clk), // cr0.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_002_src_valid), // sink0.valid
.sink0_data (cmd_mux_002_src_data), // .data
.sink0_channel (cmd_mux_002_src_channel), // .channel
.sink0_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_002_src_ready), // .ready
.source0_valid (acl_kernel_clk_ctrl_burst_adapter_source0_valid), // source0.valid
.source0_data (acl_kernel_clk_ctrl_burst_adapter_source0_data), // .data
.source0_channel (acl_kernel_clk_ctrl_burst_adapter_source0_channel), // .channel
.source0_startofpacket (acl_kernel_clk_ctrl_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (acl_kernel_clk_ctrl_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (acl_kernel_clk_ctrl_burst_adapter_source0_ready) // .ready
);
system_acl_iface_mm_interconnect_0_cmd_demux cmd_demux (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_h2f_lw_axi_master_wr_limiter_cmd_src_ready), // sink.ready
.sink_channel (hps_h2f_lw_axi_master_wr_limiter_cmd_src_channel), // .channel
.sink_data (hps_h2f_lw_axi_master_wr_limiter_cmd_src_data), // .data
.sink_startofpacket (hps_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (hps_h2f_lw_axi_master_wr_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_cmd_demux cmd_demux_001 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_h2f_lw_axi_master_rd_limiter_cmd_src_ready), // sink.ready
.sink_channel (hps_h2f_lw_axi_master_rd_limiter_cmd_src_channel), // .channel
.sink_data (hps_h2f_lw_axi_master_rd_limiter_cmd_src_data), // .data
.sink_startofpacket (hps_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (hps_h2f_lw_axi_master_rd_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_cmd_mux cmd_mux (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_cmd_mux cmd_mux_002 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src2_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src2_valid), // .valid
.sink1_channel (cmd_demux_001_src2_channel), // .channel
.sink1_data (cmd_demux_001_src2_data), // .data
.sink1_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_demux rsp_demux (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_demux rsp_demux_001 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_demux rsp_demux_002 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_mux rsp_mux (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_mux rsp_mux_001 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src1_valid), // .valid
.sink1_channel (rsp_demux_001_src1_channel), // .channel
.sink1_data (rsp_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src1_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src1_valid), // .valid
.sink2_channel (rsp_demux_002_src1_channel), // .channel
.sink2_data (rsp_demux_002_src1_data), // .data
.sink2_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
endmodule
|
//Test bench for the computation Module
module computation_tb();
reg asel_SIM, bsel_SIM, loadc_SIM, loads_SIM, clk_SIM;
reg [1:0] ALUop_SIM, shift_SIM;
reg [15:0] A_SIM, B_SIM;
wire status_SIM;
wire [15:0] C_SIM, datapath_in_SIM;
//Constants
`define WIDTH 16
`define STATUSWIDTH 1
computation #(
.width(`WIDTH),
.statusWidth(`STATUSWIDTH)
) DUT(
.clk (clk_SIM),
.asel (asel_SIM),
.bsel (bsel_SIM),
.loadc (loadc_SIM),
.loads (loads_SIM),
.shift (shift_SIM),
.ALUop (ALUop_SIM),
.datapath_in (datapath_in_SIM),
.A (A_SIM),
.B (B_SIM),
.status (status_SIM),
.C (C_SIM)
);
initial begin
loadc_SIM= 1;
loads_SIM= 1;
asel_SIM= 1;
bsel_SIM= 0;
B_SIM [15:0]= 16'b0000000000011101; //1+4+8+16= 29
A_SIM [15:0]= 16'b0000000000101110; //2+4+8+32= 46
ALUop_SIM [1:0]= 00; //add Ain + Bin
shift_SIM [1:0]= 10; // B = shifted right one and left bit = 0 -> 2+4+8 =14 //ALUComputed= 60
$display("ALUComputed = 60 = 00111100");
#10;
repeat(2) begin
#10;
clk_SIM = 1;
#10;
clk_SIM = 0;
end
#10;
asel_SIM= 1;
#10;
bsel_SIM= 0;
#10;
B_SIM [15:0]= 16'b0000000000011101; //1+4+8+16= 29
#10;
A_SIM [15:0]= 16'b0000000000101110; //2+4+8+32= 46
#10;
ALUop_SIM [1:0]= 00; //add Ain + Bin
#10;
shift_SIM [1:0]= 01; // B = shifted left one and right bit = 0 -> 2+8+16+32= 58 //ALUcomputed = 104
$display("ALUComputed = 104 = 01101000");
#10;
repeat(2) begin
#10;
clk_SIM = 1;
#10;
clk_SIM = 0;
end
end
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/counter.v
*/
// Behavioral model for the 32-bit program counter
module program_counter (next_pc,cur_pc,rst,clk);
// Output signals...
// Incremented value of the program counter
output [0:31] next_pc;
// ===============================================================
// Input signals
// Current value of the program counter
input [0:31] cur_pc;
// Clock signal for the program counter
input clk;
// Reset signal for the program counter
input rst;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*/
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:31] next_pc; // Output signals
// ===============================================================
always @(posedge clk)
begin
// If the reset signal sis set to HIGH
if(rst)
begin
// Set its value to ZERO
next_pc<=32'd0;
end
else
begin
next_pc<=cur_pc+32'd4;
end
end
endmodule
|
(** * Maps: Total and Partial Maps *)
(** Maps (or dictionaries) are ubiquitous data structures both
generally and in the theory of programming languages in
particular; we're going to need them in many places in the coming
chapters. They also make a nice case study using ideas we've seen
in previous chapters, including building data structures out of
higher-order functions (from [Basics] and [Poly]) and the use of
reflection to streamline proofs (from [IndProp]).
We'll define two flavors of maps: _total_ maps, which include a
"default" element to be returned when a key being looked up
doesn't exist, and _partial_ maps, which return an [option] to
indicate success or failure. The latter is defined in terms of
the former, using [None] as the default element. *)
(* ################################################################# *)
(** * The Coq Standard Library *)
(** One small digression before we get to maps.
Unlike the chapters we have seen so far, this one does not
[Require Import] the chapter before it (and, transitively, all the
earlier chapters). Instead, in this chapter and from now, on
we're going to import the definitions and theorems we need
directly from Coq's standard library stuff. You should not notice
much difference, though, because we've been careful to name our
own definitions and theorems the same as their counterparts in the
standard library, wherever they overlap. *)
Require Import Coq.Arith.Arith.
Require Import Coq.Bool.Bool.
Require Import Coq.Strings.String.
Require Import Coq.Logic.FunctionalExtensionality.
(** Documentation for the standard library can be found at
http://coq.inria.fr/library/.
The [Search] command is a good way to look for theorems involving
objects of specific types. Take a minute now to experiment with it. *)
(* ################################################################# *)
(** * Identifiers *)
(** First, we need a type for the keys that we use to index into our
maps. For this purpose, we again use the type [id] from the
[Lists] chapter. To make this chapter self contained, we repeat
its definition here, together with the equality comparison
function for [id]s and its fundamental property. *)
Inductive id : Type :=
| Id : string -> id.
Definition beq_id x y :=
match x,y with
| Id n1, Id n2 => if string_dec n1 n2 then true else false
end.
(** (The function [string_dec] comes from Coq's string library.
If you check its result type, you'll see that it does not actually
return a [bool], but rather a type that looks like [{x = y} + {x
<> y}], called a [sumbool], which can be thought of as an
"evidence-carrying boolean." Formally, an element of [sumbool] is
either a proof that two things are equal or a proof that they are
unequal, together with a tag indicating which. But for present
purposes you can think of it as just a fancy [bool].) *)
Theorem beq_id_refl : forall id, true = beq_id id id.
Proof.
intros [n]. simpl. destruct (string_dec n n).
- reflexivity.
- destruct n0. reflexivity.
Qed.
(** The following useful property of [beq_id] follows from an
analogous lemma about strings: *)
Theorem beq_id_true_iff : forall x y : id,
beq_id x y = true <-> x = y.
Proof.
intros [n1] [n2].
unfold beq_id.
destruct (string_dec n1 n2).
- subst. split. reflexivity. reflexivity.
- split.
+ intros contra. inversion contra.
+ intros H. inversion H. subst. destruct n. reflexivity.
Qed.
(** Similarly: *)
Theorem beq_id_false_iff : forall x y : id,
beq_id x y = false
<-> x <> y.
Proof.
intros x y. rewrite <- beq_id_true_iff.
rewrite not_true_iff_false. reflexivity. Qed.
(** This useful variant follows just by rewriting: *)
Theorem false_beq_id : forall x y : id,
x <> y
-> beq_id x y = false.
Proof.
intros x y. rewrite beq_id_false_iff.
intros H. apply H. Qed.
(* ################################################################# *)
(** * Total Maps *)
(** Our main job in this chapter will be to build a definition of
partial maps that is similar in behavior to the one we saw in the
[Lists] chapter, plus accompanying lemmas about its behavior.
This time around, though, we're going to use _functions_, rather
than lists of key-value pairs, to build maps. The advantage of
this representation is that it offers a more _extensional_ view of
maps, where two maps that respond to queries in the same way will
be represented as literally the same thing (the very same function),
rather than just "equivalent" data structures. This, in turn,
simplifies proofs that use maps.
We build partial maps in two steps. First, we define a type of
_total maps_ that return a default value when we look up a key
that is not present in the map. *)
Definition total_map (A:Type) := id -> A.
(** Intuitively, a total map over an element type [A] is just a
function that can be used to look up [id]s, yielding [A]s.
The function [t_empty] yields an empty total map, given a default
element; this map always returns the default element when applied
to any id. *)
Definition t_empty {A:Type} (v : A) : total_map A :=
(fun _ => v).
(** More interesting is the [update] function, which (as before) takes
a map [m], a key [x], and a value [v] and returns a new map that
takes [x] to [v] and takes every other key to whatever [m] does. *)
Definition t_update {A:Type} (m : total_map A)
(x : id) (v : A) :=
fun x' => if beq_id x x' then v else m x'.
(** This definition is a nice example of higher-order programming:
[t_update] takes a _function_ [m] and yields a new function
[fun x' => ...] that behaves like the desired map.
For example, we can build a map taking [id]s to [bool]s, where [Id
3] is mapped to [true] and every other key is mapped to [false],
like this: *)
Definition examplemap :=
t_update (t_update (t_empty false) (Id "foo") false)
(Id "bar") true.
(** This completes the definition of total maps. Note that we don't
need to define a [find] operation because it is just function
application! *)
Example update_example1 : examplemap (Id "baz") = false.
Proof. reflexivity. Qed.
Example update_example2 : examplemap (Id "foo") = false.
Proof. reflexivity. Qed.
Example update_example3 : examplemap (Id "quux") = false.
Proof. reflexivity. Qed.
Example update_example4 : examplemap (Id "bar") = true.
Proof. reflexivity. Qed.
(** To use maps in later chapters, we'll need several fundamental
facts about how they behave. Even if you don't work the following
exercises, make sure you thoroughly understand the statements of
the lemmas! (Some of the proofs require the functional
extensionality axiom, which is discussed in the [Logic]
chapter.) *)
(** **** Exercise: 1 star, optional (t_apply_empty) *)
(** First, the empty map returns its default element for all keys: *)
Lemma t_apply_empty: forall A x v, @t_empty A v x = v.
Proof.
intros A x v. unfold t_empty. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (t_update_eq) *)
(** Next, if we update a map [m] at a key [x] with a new value [v]
and then look up [x] in the map resulting from the [update], we
get back [v]: *)
Lemma t_update_eq : forall A (m: total_map A) x v,
(t_update m x v) x = v.
Proof.
intros A m x v. unfold t_update. rewrite <- beq_id_refl.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (t_update_neq) *)
(** On the other hand, if we update a map [m] at a key [x1] and then
look up a _different_ key [x2] in the resulting map, we get the
same result that [m] would have given: *)
Theorem t_update_neq : forall (X:Type) v x1 x2
(m : total_map X),
x1 <> x2 ->
(t_update m x1 v) x2 = m x2.
Proof.
intros X v x1 x2 m H. unfold t_update.
destruct (beq_id x1 x2) eqn: Heq.
- destruct H. apply beq_id_true_iff. apply Heq.
- reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (t_update_shadow) *)
(** If we update a map [m] at a key [x] with a value [v1] and then
update again with the same key [x] and another value [v2], the
resulting map behaves the same (gives the same result when applied
to any key) as the simpler map obtained by performing just
the second [update] on [m]: *)
Lemma t_update_shadow : forall A (m: total_map A) v1 v2 x,
t_update (t_update m x v1) x v2
= t_update m x v2.
Proof.
intros A m v1 v2 x. remember (t_update m x v1) as m'.
unfold t_update. apply functional_extensionality. intros x0.
destruct (beq_id x x0) eqn : Heq.
- reflexivity.
- rewrite -> Heqm'. unfold t_update. rewrite -> Heq. reflexivity.
Qed.
(** [] *)
(** For the final two lemmas about total maps, it's convenient to use
the reflection idioms introduced in chapter [IndProp]. We begin
by proving a fundamental _reflection lemma_ relating the equality
proposition on [id]s with the boolean function [beq_id]. *)
(** **** Exercise: 2 stars, optional (beq_idP) *)
(** Use the proof of [beq_natP] in chapter [IndProp] as a template to
prove the following: *)
Lemma beq_idP : forall x y, reflect (x = y) (beq_id x y).
Proof.
intros x y. apply iff_reflect. symmetry. apply beq_id_true_iff.
Qed.
(** [] *)
(** Now, given [id]s [x1] and [x2], we can use the [destruct (beq_idP
x1 x2)] to simultaneously perform case analysis on the result of
[beq_id x1 x2] and generate hypotheses about the equality (in the
sense of [=]) of [x1] and [x2]. *)
(** **** Exercise: 2 stars (t_update_same) *)
(** With the example in chapter [IndProp] as a template, use
[beq_idP] to prove the following theorem, which states that if we
update a map to assign key [x] the same value as it already has in
[m], then the result is equal to [m]: *)
Theorem t_update_same : forall X x (m : total_map X),
t_update m x (m x) = m.
Proof.
intros X x m. unfold t_update.
apply functional_extensionality. intros x0.
destruct (beq_id x x0) eqn : Heq.
- apply f_equal. apply beq_id_true_iff. apply Heq.
- reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, recommended (t_update_permute) *)
(** Use [beq_idP] to prove one final property of the [update]
function: If we update a map [m] at two distinct keys, it doesn't
matter in which order we do the updates. *)
Theorem t_update_permute : forall (X:Type) v1 v2 x1 x2
(m : total_map X),
x2 <> x1 ->
(t_update (t_update m x2 v2) x1 v1)
= (t_update (t_update m x1 v1) x2 v2).
Proof.
intros X v1 v2 x1 x2 m H. unfold t_update.
apply functional_extensionality. intros x.
destruct (beq_id x1 x) eqn : Heq1.
destruct (beq_id x2 x) eqn : Heq2.
specialize (beq_id_true_iff x1 x). intros. destruct H0.
specialize (beq_id_true_iff x2 x). intros. destruct H2.
specialize (H0 Heq1). specialize (H2 Heq2). congruence. reflexivity.
reflexivity.
Qed.
(** [] *)
(* ################################################################# *)
(** * Partial maps *)
(** Finally, we define _partial maps_ on top of total maps. A partial
map with elements of type [A] is simply a total map with elements
of type [option A] and default element [None]. *)
Definition partial_map (A:Type) := total_map (option A).
Definition empty {A:Type} : partial_map A :=
t_empty None.
Definition update {A:Type} (m : partial_map A)
(x : id) (v : A) :=
t_update m x (Some v).
(** We now straightforwardly lift all of the basic lemmas about total
maps to partial maps. *)
Lemma apply_empty : forall A x, @empty A x = None.
Proof.
intros. unfold empty. rewrite t_apply_empty.
reflexivity.
Qed.
Lemma update_eq : forall A (m: partial_map A) x v,
(update m x v) x = Some v.
Proof.
intros. unfold update. rewrite t_update_eq.
reflexivity.
Qed.
Theorem update_neq : forall (X:Type) v x1 x2
(m : partial_map X),
x2 <> x1 ->
(update m x2 v) x1 = m x1.
Proof.
intros X v x1 x2 m H.
unfold update. rewrite t_update_neq. reflexivity.
apply H. Qed.
Lemma update_shadow : forall A (m: partial_map A) v1 v2 x,
update (update m x v1) x v2 = update m x v2.
Proof.
intros A m v1 v2 x1. unfold update. rewrite t_update_shadow.
reflexivity.
Qed.
Theorem update_same : forall X v x (m : partial_map X),
m x = Some v ->
update m x v = m.
Proof.
intros X v x m H. unfold update. rewrite <- H.
apply t_update_same.
Qed.
Theorem update_permute : forall (X:Type) v1 v2 x1 x2
(m : partial_map X),
x2 <> x1 ->
(update (update m x2 v2) x1 v1)
= (update (update m x1 v1) x2 v2).
Proof.
intros X v1 v2 x1 x2 m. unfold update.
apply t_update_permute.
Qed.
(** $Date: 2016-11-22 16:39:52 -0500 (Tue, 22 Nov 2016) $ *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O221A_FUNCTIONAL_PP_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o221a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X , or0_out, or1_out, C1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221A_FUNCTIONAL_PP_V |
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : db_top.v
// Author : Chewein
// Created : 2014-04-18
// Description : TOP module of Deblocking Filter
//-------------------------------------------------------------------
`include "enc_defines.v"
module db_top(
clk ,
rst_n ,
mb_x_total_i ,
mb_y_total_i ,
mb_x_i ,
mb_y_i ,
qp_i ,
start_i ,
done_o ,
mb_type_i ,
mb_partition_i ,
mb_p_pu_mode_i ,
mb_cbf_i ,
mb_cbf_u_i ,
mb_cbf_v_i ,
mb_mv_ren_o ,
mb_mv_raddr_o ,
mb_mv_rdata_i ,
tq_ren_o ,
tq_raddr_o ,
tq_rdata_i ,
tq_ori_data_i ,
mb_db_en_o ,
mb_db_rw_o ,
mb_db_addr_o ,
mb_db_data_o ,
db_wen_o ,
db_w4x4_x_o ,
db_w4x4_y_o ,
db_wprevious_o ,
db_wdone_o ,
db_wsel_o ,
db_wdata_o ,
mb_db_ren_o ,
mb_db_r4x4_o ,
mb_db_ridx_o ,
mb_db_data_i
);
// *********************************************************************
//
// Parameter DECLARATION
//
// *********************************************************************
parameter DATA_WIDTH = 128 ;
parameter IDLE = 3'b000, LOAD = 3'b001, YVER = 3'b011,YHOR =3'b010;
parameter CVER = 3'b110, CHOR = 3'b111, OUTLT = 3'b101,OUT =3'b100;
// *********************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// *********************************************************************
input clk ;//clock
input rst_n ;//reset signal
// CTRL IF
input [`PIC_X_WIDTH-1:0] mb_x_total_i ;// Total LCU number-1 in X ,PIC_X_WIDTH = 8
input [`PIC_Y_WIDTH-1:0] mb_y_total_i ;// Total LCU number-1 in y ,PIC_Y_WIDTH = 8
input [`PIC_X_WIDTH-1:0] mb_x_i ;// Current LCU in X
input [`PIC_Y_WIDTH-1:0] mb_y_i ;// Current LCU in y
input [5:0] qp_i ;// QP
input start_i ;// cabac start
output done_o ;// cabac done
// Intra/Inter IF
input mb_type_i ;// 1: I MB, 0: P/B MB
input [20:0] mb_partition_i ;// CU partition mode,0:not split,1:split,[0] for 64x64
input [41:0] mb_p_pu_mode_i ;// Inter PU partition mode for every CU size
input [255:0] mb_cbf_i ;// cbf for every 4x4 cu in zig-zag scan order
input [255:0] mb_cbf_u_i ;// cbf for every 4x4 cu in zig-zag scan order
input [255:0] mb_cbf_v_i ;// cbf for every 4x4 cu in zig-zag scan order
// MV RAM IF
output mb_mv_ren_o ; // Inter MVD MEM IF
output [6:0] mb_mv_raddr_o ; // CU_DEPTH = 3,each 8x8 cu,include mv top,0-63:lcu
input [`FMV_WIDTH*2-1:0] mb_mv_rdata_i ; // FMV_WIDTH = 10
// TQ IF rec data of current LCU
output tq_ren_o ; // tq read enable
output [8:0] tq_raddr_o ; // tq read address
input [4*32-1:0] tq_rdata_i ; // tq read data of an 4x4cu ,COEFF_WIDTH = 4
input [DATA_WIDTH-1:0] tq_ori_data_i ; //tq read data of original pixels
// MB deblocking pixel IF :write pixels
output mb_db_en_o ; // db pixel RW enable
output mb_db_rw_o ; // db pixel read/write 0: read, 1: write
output [8:0] mb_db_addr_o ; // db address
output [DATA_WIDTH-1:0] mb_db_data_o ; // db pixel
output [1-1:0] db_wen_o ;// db write enable
output [5-1:0] db_w4x4_x_o ;// db write 4x4 block index in x
output [5-1:0] db_w4x4_y_o ;// db write 4x4 block index in y
output [1-1:0] db_wprevious_o ;// db write previous lcu data , 1: previous,0:current
output [1-1:0] db_wdone_o ;// db write previous lcu done
output [2-1:0] db_wsel_o ;// db write 4x4 block sel : 0x:luma, 10: u, 11:v
output [DATA_WIDTH-1:0] db_wdata_o ;// db write 4x4 block data
// MB deblocking pixel IF :read top
output mb_db_ren_o ; // read top pixels enable
output [5-1:0] mb_db_r4x4_o ; // the index x
output [2-1:0] mb_db_ridx_o ; // the index y
input [DATA_WIDTH-1:0] mb_db_data_i ; // db pixel
reg [DATA_WIDTH-1:0] mb_db_data_o ; // db pixel
reg [DATA_WIDTH-1:0] db_wdata_o ;// db write 4x4 block data
// *********************************************************************
//
// Register DECLARATION
//
// *********************************************************************
// *********************************************************************
//
// Wire DECLARATION
//
// *********************************************************************
wire op_enable_w ; // original pixel enable
wire oq_enable_w ; // original pixel enable
wire [DATA_WIDTH-1:0] op_w ; // original pixels
wire [DATA_WIDTH-1:0] oq_w ; // original pixels
wire [DATA_WIDTH-1:0] f_p_w ; // filtered p
wire [DATA_WIDTH-1:0] f_q_w ; // filtered q
wire [DATA_WIDTH-1:0] p_w ; // pixels before deblocking
wire [DATA_WIDTH-1:0] q_w ; // pixels before deblocking
wire tu_edge_w ;
wire pu_edge_w ;
wire [ 5:0] qp_p_w ;
wire [ 5:0] qp_q_w ;
wire cbf_p_w ;
wire cbf_q_w ;
wire [`FMV_WIDTH*2-1:0] mv_p_w ;
wire [`FMV_WIDTH*2-1:0] mv_q_w ;
wire is_ver_w ;
wire is_luma_w ;
wire is_tran_w ;
wire sao_data_end_w ;
wire [ 1:0] bs_w ;
wire [ 8:0] cnt_w ;
wire [ 2:0] state_w ;
// sao signals
wire [16:0] sao_curr_w ;
reg [16:0] sao_curr_r ;
reg [16:0] sao_left_r ;
reg [16:0] sao_top_r ;
reg [16:0] sao_tl_r ;
reg [16:0] sao_add_r ;
reg sao_left_valid_r ;
reg sao_top_valid_r ;
reg sao_tl_valid_r ;
reg sao_curr_valid_r ;
reg sao_oen_r ;
reg sao_wen_r ;
wire [`PIC_X_WIDTH-1:0] sao_addr_w ;
wire [16:0] sao_data_w ;
wire [DATA_WIDTH-1:0] mb_db_data_w ; // db pixel
wire [DATA_WIDTH-1:0] db_wdata_w ; // db pixel
// *********************************************************************
//
// Logic DECLARATION
//
// *********************************************************************
db_controller ucontro(
.clk (clk ),
.rst_n (rst_n ),
.start_i (start_i ),
//output
.done_o (done_o ),
.cnt_r (cnt_w ),
.state (state_w )
);
db_ram_contro uram(
//input
.clk ( clk ),
.rst_n ( rst_n ),
.start_i ( start_i ),
.cnt_i ( cnt_w ),
.state_i ( state_w ),
.mb_x_i ( mb_x_i ),
.mb_y_i ( mb_y_i ),
.mb_x_total_i ( mb_x_total_i ),
.f_p_i ( f_p_w ),
.f_q_i ( f_q_w ),
//output
.op_enable_o (op_enable_w ),
.oq_enable_o (oq_enable_w ),
.op_o (op_w ),
.oq_o (oq_w ),
.p_o (p_w ),
.q_o (q_w ),
.tq_ren_o (tq_ren_o ),
.tq_raddr_o (tq_raddr_o ),
.tq_rdata_i (tq_rdata_i ),
.tq_ori_data_i (tq_ori_data_i ),
.mb_db_en_o (mb_db_en_o ),
.mb_db_rw_o (mb_db_rw_o ),
.mb_db_addr_o (mb_db_addr_o ),
.mb_db_data_o (mb_db_data_w ),
.db_wen_o (db_wen_o ),
.db_w4x4_x_o (db_w4x4_x_o ),
.db_w4x4_y_o (db_w4x4_y_o ),
.db_wprevious_o(db_wprevious_o),
.db_wdone_o (db_wdone_o ),
.db_wsel_o (db_wsel_o ),
.db_wdata_o (db_wdata_w ),
.mb_db_ren_o (mb_db_ren_o ),
.mb_db_r4x4_o (mb_db_r4x4_o ),
.mb_db_ridx_o (mb_db_ridx_o ),
.mb_db_data_i (mb_db_data_i ),
.is_ver_o (is_ver_w ),
.is_luma_o (is_luma_w ),
.sao_data_end_o(sao_data_end_w)
);
db_bs ubs (
//input
.clk (clk ),
.rst_n (rst_n ),
.cnt_i (cnt_w ),
.state_i (state_w ),
.mb_x_total_i (mb_x_total_i ),
.mb_y_total_i (mb_y_total_i ),
.mb_x_i (mb_x_i ),
.mb_y_i (mb_y_i ),
.mb_partition_i(mb_partition_i),
.mb_p_pu_mode_i(mb_p_pu_mode_i),
.mb_cbf_i (mb_cbf_i ),
.mb_cbf_u_i (mb_cbf_u_i ),
.mb_cbf_v_i (mb_cbf_v_i ),
.qp_i (qp_i ),
//output
.tu_edge_o (tu_edge_w ),
.pu_edge_o (pu_edge_w ),
.qp_p_o (qp_p_w ),
.qp_q_o (qp_q_w ),
.cbf_p_o (cbf_p_w ),
.cbf_q_o (cbf_q_w ),
.is_tran_o (is_tran_w )
);
db_mv udbmv(
.clk (clk ),
.rst_n (rst_n ),
.cnt_i (cnt_w ),
.state_i (state_w ),
.mb_x_total_i (mb_x_total_i ),
.mb_y_total_i (mb_y_total_i ),
.mb_x_i (mb_x_i ),
.mb_y_i (mb_y_i ),
.mb_mv_ren_o (mb_mv_ren_o ),
.mb_mv_raddr_o(mb_mv_raddr_o ),
.mb_mv_rdata_i(mb_mv_rdata_i ),
.mv_p_o (mv_p_w ),
.mv_q_o (mv_q_w )
);
db_pipeline udbf(
//input
.clk (clk ),
.rst_n (rst_n ),
.tu_edge_i (tu_edge_w ),
.pu_edge_i (pu_edge_w ),
.qp_p_i (qp_p_w ),
.qp_q_i (qp_q_w ),
.cbf_p_i (cbf_p_w ),
.cbf_q_i (cbf_q_w ),
.mv_p_i (mv_p_w ),
.mv_q_i (mv_q_w ),
.mb_type_i (mb_type_i ),
.is_ver_i (is_ver_w ),
.is_luma_i (is_luma_w ),
.is_tran_i (is_tran_w ),
.p_i (p_w ),
.q_i (q_w ),
.f_p_o (f_p_w ),
.f_q_o (f_q_w )
);
db_sao_top u_sao(
.clk (clk ),
.rst_n (rst_n ),
.dp_i (f_p_w ),
.dq_i (f_q_w ),
.op_i (op_w ),
.oq_i (oq_w ),
.op_enable_i (op_enable_w ),
.oq_enable_i (oq_enable_w ),
.is_luma_i (is_luma_w ),
.is_ver_i (is_ver_w ),
.data_end_i (sao_data_end_w),
.sao_data_o (sao_curr_w )
);
// sao data ram organization
// read from ram
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
sao_oen_r <= 1'b1 ;
else if((state_w==LOAD)&&(cnt_w==9'd0))
sao_oen_r <= 1'b0 ;
else
sao_oen_r <= 1'b1 ;
end
// write to ram
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
sao_wen_r <= 1'b1 ;
else if((state_w==CVER)&&(cnt_w==9'd0))
sao_wen_r <= 1'b0 ;
else
sao_wen_r <= 1'b1 ;
end
assign sao_addr_w = mb_x_i ;
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
sao_curr_r <= 18'd0 ;
else if(state_w==CVER&&(cnt_w==9'd0))
sao_curr_r <= sao_curr_w;
end
db_ram_1p #(.Word_Width(17),.Addr_Width(`PIC_X_WIDTH))
db_sao_top(
.clk ( clk ),
.cen_i ( 1'b0 ),
.oen_i ( sao_oen_r ),
.wen_i ( sao_wen_r ),
.addr_i ( sao_addr_w ),
.data_i ( sao_curr_r ),
.data_o ( sao_data_w )
);
// sao top and left data
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
sao_top_r <= 18'd0 ;
else if((state_w==LOAD)&&(cnt_w==9'd1))
sao_top_r <= sao_data_w ;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
sao_left_r <= 18'd0 ;
else if((state_w==OUT)&&(cnt_w==9'd384))
sao_left_r <= sao_curr_r ;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
sao_tl_r <= 18'd0 ;
else if((state_w==OUT)&&(cnt_w==9'd384)&&mb_y_i)
sao_tl_r <= sao_top_r ;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
sao_tl_valid_r <= 1'b0 ;
else if((state_w==OUTLT)&&(cnt_w==9'd64)&&mb_y_i&&mb_x_i)
sao_tl_valid_r <= 1'b1 ;
else
sao_tl_valid_r <= 1'b0 ;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
sao_left_valid_r <= 1'b0 ;
else if(state_w==OUTLT&&(!cnt_w[8:4])&&mb_y_i==mb_y_total_i) // mb_x_i==mb_x_total_i 0...15
sao_left_valid_r <= 1'b1 ;
else if(state_w==OUTLT&&(!cnt_w[8:4])&&mb_x_i&&cnt_w[3:0]!=4'b1111) // 0...14, !=15
sao_left_valid_r <= 1'b1 ;
else
sao_left_valid_r <= 1'b0 ;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
sao_top_valid_r <= 1'b0 ;
else if(state_w==OUTLT&&(cnt_w[5:4]==2'b10)&&mb_y_i) // 32....47
sao_top_valid_r <= 1'b1 ;
else
sao_top_valid_r <= 1'b0 ;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
sao_curr_valid_r <= 1'b0 ;
else if(state_w==OUT&&(!cnt_w[8]))begin // <256
if(mb_x_i==mb_x_total_i&&mb_y_i==mb_y_total_i)
sao_curr_valid_r <= 1'b1 ;
else if(mb_x_i==mb_x_total_i)
sao_curr_valid_r <= (!(cnt_w[7:4]==4'b1111));
else if(mb_y_i==mb_y_total_i)
sao_curr_valid_r <= (!(cnt_w[3:0]==4'b1111));
else
sao_curr_valid_r <= (!(cnt_w[7:4]==4'b1111))&&(!(cnt_w[3:0]==4'b1111));
end
else
sao_curr_valid_r <= 1'b0 ;
end
always @* begin
if(sao_tl_valid_r)//??sao_tl_valid_r
sao_add_r = sao_tl_r ;
else if(sao_left_valid_r)
sao_add_r = sao_left_r ;
else if(sao_top_valid_r)
sao_add_r = sao_top_r ;
else if(sao_curr_valid_r)
sao_add_r = sao_curr_r ;
else
sao_add_r = 18'd0 ;
end
wire [DATA_WIDTH-1:0] mb_db_data_sao_w ; // db pixel
db_sao_add_offset udbaddoffset(
.mb_db_data_i (mb_db_data_w ),
.sao_add_i (sao_add_r ),
.mb_db_data_o (mb_db_data_sao_w )
);
always @* begin
if(`SAO_OPEN==1) begin
mb_db_data_o = mb_db_data_sao_w;
db_wdata_o = mb_db_data_sao_w;
end
else begin
mb_db_data_o = mb_db_data_w ;
db_wdata_o = mb_db_data_w ;
end
end
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// Simulation only, not synthesisable
`include "include/mbus_def.v"
module int_action_rom(
int_func_id,
int_payload
);
parameter LC_INT_DEPTH = 8;
parameter LC_RF_DEPTH = 128; // 1 ~ 2^8
parameter LC_MEM_DEPTH = 65536; // 1 ~ 2^30
output [`FUNC_WIDTH*LC_INT_DEPTH-1:0] int_func_id;
output [(`DATA_WIDTH<<1)*LC_INT_DEPTH-1:0] int_payload;
reg [`FUNC_WIDTH-1:0] int_func_array [0:LC_INT_DEPTH-1];
reg [(`DATA_WIDTH<<1)-1:0] int_payload_array [0:LC_INT_DEPTH-1];
genvar idx;
generate
for (idx=0; idx<LC_INT_DEPTH; idx=idx+1)
begin: INT_ACTION
assign int_func_id[`FUNC_WIDTH*(idx+1)-1:`FUNC_WIDTH*idx] = int_func_array[idx];
assign int_payload[(`DATA_WIDTH<<1)*(idx+1)-1:(`DATA_WIDTH<<1)*idx] = int_payload_array[idx];
end
endgenerate
integer i;
initial
begin
for (i=0; i<LC_INT_DEPTH; i=i+1)
begin
int_func_array[i] <= 0;
int_payload_array[i] <= 0;
end
// read 2 x 3 bytes from address 0, send it to 0x03 (broadcast, ch 3)
int_func_array[0] <= `LC_CMD_RF_READ;
int_payload_array[0] <= (((8'h0<<24 | 8'h1<<16 | 8'h03<<8 | 8'h0)<<`DATA_WIDTH) | {(`DATA_WIDTH){1'b0}}); // from, length, destination, don't care, 32-bit un-use
// read 3 x 3 bytes from address LC_RF_DEPTH-1 , send it to 0x0c (broadcast, ch 3)
// should only read 1 x 3 bytes,
int_func_array[1] <= `LC_CMD_RF_READ;
int_payload_array[1] <= ((((LC_RF_DEPTH-1'b1)<<24 | 8'h2<<16 | 8'h03<<8 | 8'h0)<<`DATA_WIDTH) | {(`DATA_WIDTH){1'b0}}); // from, length, destination, don't care, 32-bit un-use
// read 2 words from address 0, send it to 0x03
int_func_array[2] <= `LC_CMD_MEM_READ;
int_payload_array[2] <= (((30'h0<<2) | 2'b0)<<32) | ((8'h03<<24) | 24'h1); // from (30-bit), destination (8-bit), length (24-bit)
// read 3 words from address LC_MEM_DEPTH-1, send it to 0x03
// should only read 1 word
int_func_array[3] <= `LC_CMD_MEM_READ;
int_payload_array[3] <= ((((LC_MEM_DEPTH-1'b1)<<2) | 2'b0)<<32) | ((8'h03<<24) | 24'h2); // from (30-bit), destination (8-bit), length (24-bit)
// Error commands
int_func_array[4] <= `LC_CMD_RF_WRITE;
int_func_array[5] <= `LC_CMD_RF_WRITE;
int_func_array[6] <= `LC_CMD_MEM_WRITE;
int_func_array[7] <= `LC_CMD_MEM_WRITE;
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad9250_pnmon (
// adc interface
adc_clk,
adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
// processor interface
adc_pnseq_sel);
// adc interface
input adc_clk;
input [27:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// processor interface PN9 (0x0), PN23 (0x1)
input [ 3:0] adc_pnseq_sel;
// internal registers
reg [27:0] adc_pn_data_in = 'd0;
reg [27:0] adc_pn_data_pn = 'd0;
// internal signals
wire [27:0] adc_pn_data_pn_s;
// PN23 function
function [27:0] pn23;
input [27:0] din;
reg [27:0] dout;
begin
dout[27] = din[22] ^ din[17];
dout[26] = din[21] ^ din[16];
dout[25] = din[20] ^ din[15];
dout[24] = din[19] ^ din[14];
dout[23] = din[18] ^ din[13];
dout[22] = din[17] ^ din[12];
dout[21] = din[16] ^ din[11];
dout[20] = din[15] ^ din[10];
dout[19] = din[14] ^ din[ 9];
dout[18] = din[13] ^ din[ 8];
dout[17] = din[12] ^ din[ 7];
dout[16] = din[11] ^ din[ 6];
dout[15] = din[10] ^ din[ 5];
dout[14] = din[ 9] ^ din[ 4];
dout[13] = din[ 8] ^ din[ 3];
dout[12] = din[ 7] ^ din[ 2];
dout[11] = din[ 6] ^ din[ 1];
dout[10] = din[ 5] ^ din[ 0];
dout[ 9] = din[ 4] ^ din[22] ^ din[17];
dout[ 8] = din[ 3] ^ din[21] ^ din[16];
dout[ 7] = din[ 2] ^ din[20] ^ din[15];
dout[ 6] = din[ 1] ^ din[19] ^ din[14];
dout[ 5] = din[ 0] ^ din[18] ^ din[13];
dout[ 4] = din[22] ^ din[12];
dout[ 3] = din[21] ^ din[11];
dout[ 2] = din[20] ^ din[10];
dout[ 1] = din[19] ^ din[ 9];
dout[ 0] = din[18] ^ din[ 8];
pn23 = dout;
end
endfunction
// PN9 function
function [27:0] pn9;
input [27:0] din;
reg [27:0] dout;
begin
dout[27] = din[ 8] ^ din[ 4];
dout[26] = din[ 7] ^ din[ 3];
dout[25] = din[ 6] ^ din[ 2];
dout[24] = din[ 5] ^ din[ 1];
dout[23] = din[ 4] ^ din[ 0];
dout[22] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[21] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[20] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[19] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[18] = din[ 8] ^ din[ 0];
dout[17] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[16] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[15] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[14] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[13] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[12] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[11] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[10] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 9] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[ 8] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[ 7] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[ 6] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 5] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 4] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 3] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[ 2] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 1] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 0] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
pn9 = dout;
end
endfunction
// pn sequence select
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
always @(posedge adc_clk) begin
adc_pn_data_in <= {~adc_data[13], adc_data[12:0], ~adc_data[27], adc_data[26:14]};
if (adc_pnseq_sel == 4'd0) begin
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
end else begin
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
end
end
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(28)) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (1'b1),
.adc_data_in (adc_pn_data_in),
.adc_data_pn (adc_pn_data_pn),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns/10ps
module AluSim;
reg clock;
reg reset;
reg [11:0] inst;
reg inst_en;
wire [7:0] result;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#1000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
#8 inst = {`Alu_LDI,8'hAB};
inst_en = 1;
#4 inst = {`Alu_ADD,8'h01};
inst_en = 1;
#4 inst = {`Alu_SUB,8'h02};
inst_en = 1;
#4 inst = {`Alu_NOT,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Alu_AND,8'h16};
inst_en = 1;
#4 inst = {`Alu_IOR,8'h22};
inst_en = 1;
#4 inst = {`Alu_XOR,8'hF9};
inst_en = 1;
#4 inst = {`Alu_SHL,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Alu_SHR,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Alu_LDI,8'hAB};
inst_en = 1;
#4 inst = {`Alu_EQL,8'hAB};
inst_en = 1;
#4 inst = {`Alu_EQL,8'h0F};
inst_en = 1;
#4 inst = {`Alu_LDI,8'hAB};
inst_en = 1;
#4 inst = {`Alu_NEQ,8'h0F};
inst_en = 1;
#4 inst = {`Alu_NEQ,8'h01};
inst_en = 1;
#4 inst = {`Alu_LDI,8'hAA};
inst_en = 1;
#4 inst = {`Alu_LTS,8'hBB};
inst_en = 1;
#4 inst = {`Alu_LTE,8'h01};
inst_en = 1;
#4 inst = {`Alu_LDI,8'hAA};
inst_en = 1;
#4 inst = {`Alu_LTS,8'h43};
inst_en = 1;
#4 inst = {`Alu_LTE,8'h00};
inst_en = 1;
#4 inst = {`Alu_LDI,8'hAA};
inst_en = 1;
#4 inst = {`Alu_GTS,8'h43};
inst_en = 1;
#4 inst = {`Alu_GTE,8'h01};
inst_en = 1;
#4 inst = {`Alu_LDI,8'hAA};
inst_en = 1;
#4 inst = {`Alu_GTS,8'hBB};
inst_en = 1;
#4 inst = {`Alu_GTE,8'hCC};
inst_en = 1;
#4 inst = {`Alu_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test disabled instruction.
#4 inst = {`Alu_LDI,8'h0A};
inst_en = 0;
#4 inst = {`Alu_ADD,8'h01};
inst_en = 1;
// Test bad instruction.
#4 inst = {8'hF,8'h10};
inst_en = 1;
#4 inst = {`Alu_LDI,8'hA0};
inst_en = 1;
#4 reset = 1;
#8 reset = 0;
#4 inst = {`Alu_LDI,8'hB0};
inst_en = 1;
#4 inst = {`Alu_NOP,8'bxxxxxxxx};
inst_en = 1;
end
Alu
alu (.clock(clock),
.reset(reset),
.inst(inst),
.inst_en(inst_en),
.result(result));
endmodule // AluSim
|
//======================================================================
//
// sha1_core.v
// -----------
// Verilog 2001 implementation of the SHA-1 hash function.
// This is the internal core with wide interfaces.
//
//
// Copyright (c) 2013 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module sha1_core(
input wire clk,
input wire reset_n,
input wire init,
input wire next,
input wire [511 : 0] block,
output wire ready,
output wire [159 : 0] digest,
output wire digest_valid
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter H0_0 = 32'h67452301;
parameter H0_1 = 32'hefcdab89;
parameter H0_2 = 32'h98badcfe;
parameter H0_3 = 32'h10325476;
parameter H0_4 = 32'hc3d2e1f0;
parameter SHA1_ROUNDS = 79;
parameter CTRL_IDLE = 0;
parameter CTRL_ROUNDS = 1;
parameter CTRL_DONE = 2;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] a_reg;
reg [31 : 0] a_new;
reg [31 : 0] b_reg;
reg [31 : 0] b_new;
reg [31 : 0] c_reg;
reg [31 : 0] c_new;
reg [31 : 0] d_reg;
reg [31 : 0] d_new;
reg [31 : 0] e_reg;
reg [31 : 0] e_new;
reg a_e_we;
reg [31 : 0] H0_reg;
reg [31 : 0] H0_new;
reg [31 : 0] H1_reg;
reg [31 : 0] H1_new;
reg [31 : 0] H2_reg;
reg [31 : 0] H2_new;
reg [31 : 0] H3_reg;
reg [31 : 0] H3_new;
reg [31 : 0] H4_reg;
reg [31 : 0] H4_new;
reg H_we;
reg [6 : 0] round_ctr_reg;
reg [6 : 0] round_ctr_new;
reg round_ctr_we;
reg round_ctr_inc;
reg round_ctr_rst;
reg digest_valid_reg;
reg digest_valid_new;
reg digest_valid_we;
reg [1 : 0] sha1_ctrl_reg;
reg [1 : 0] sha1_ctrl_new;
reg sha1_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg digest_init;
reg digest_update;
reg state_init;
reg state_update;
reg first_block;
reg ready_flag;
reg w_init;
reg w_next;
wire [31 : 0] w;
//----------------------------------------------------------------
// Module instantiantions.
//----------------------------------------------------------------
sha1_w_mem w_mem_inst(
.clk(clk),
.reset_n(reset_n),
.block(block),
.init(w_init),
.next(w_next),
.w(w)
);
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_flag;
assign digest = {H0_reg, H1_reg, H2_reg, H3_reg, H4_reg};
assign digest_valid = digest_valid_reg;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with
// asynchronous active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
a_reg <= 32'h0;
b_reg <= 32'h0;
c_reg <= 32'h0;
d_reg <= 32'h0;
e_reg <= 32'h0;
H0_reg <= 32'h0;
H1_reg <= 32'h0;
H2_reg <= 32'h0;
H3_reg <= 32'h0;
H4_reg <= 32'h0;
digest_valid_reg <= 1'h0;
round_ctr_reg <= 7'h0;
sha1_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (a_e_we)
begin
a_reg <= a_new;
b_reg <= b_new;
c_reg <= c_new;
d_reg <= d_new;
e_reg <= e_new;
end
if (H_we)
begin
H0_reg <= H0_new;
H1_reg <= H1_new;
H2_reg <= H2_new;
H3_reg <= H3_new;
H4_reg <= H4_new;
end
if (round_ctr_we)
round_ctr_reg <= round_ctr_new;
if (digest_valid_we)
digest_valid_reg <= digest_valid_new;
if (sha1_ctrl_we)
sha1_ctrl_reg <= sha1_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// digest_logic
//
// The logic needed to init as well as update the digest.
//----------------------------------------------------------------
always @*
begin : digest_logic
H0_new = 32'h0;
H1_new = 32'h0;
H2_new = 32'h0;
H3_new = 32'h0;
H4_new = 32'h0;
H_we = 0;
if (digest_init)
begin
H0_new = H0_0;
H1_new = H0_1;
H2_new = H0_2;
H3_new = H0_3;
H4_new = H0_4;
H_we = 1;
end
if (digest_update)
begin
H0_new = H0_reg + a_reg;
H1_new = H1_reg + b_reg;
H2_new = H2_reg + c_reg;
H3_new = H3_reg + d_reg;
H4_new = H4_reg + e_reg;
H_we = 1;
end
end // digest_logic
//----------------------------------------------------------------
// state_logic
//
// The logic needed to init as well as update the state during
// round processing.
//----------------------------------------------------------------
always @*
begin : state_logic
reg [31 : 0] a5;
reg [31 : 0] f;
reg [31 : 0] k;
reg [31 : 0] t;
a5 = 32'h0;
f = 32'h0;
k = 32'h0;
t = 32'h0;
a_new = 32'h0;
b_new = 32'h0;
c_new = 32'h0;
d_new = 32'h0;
e_new = 32'h0;
a_e_we = 1'h0;
if (state_init)
begin
if (first_block)
begin
a_new = H0_0;
b_new = H0_1;
c_new = H0_2;
d_new = H0_3;
e_new = H0_4;
a_e_we = 1;
end
else
begin
a_new = H0_reg;
b_new = H1_reg;
c_new = H2_reg;
d_new = H3_reg;
e_new = H4_reg;
a_e_we = 1;
end
end
if (state_update)
begin
if (round_ctr_reg <= 19)
begin
k = 32'h5a827999;
f = ((b_reg & c_reg) ^ (~b_reg & d_reg));
end
else if ((round_ctr_reg >= 20) && (round_ctr_reg <= 39))
begin
k = 32'h6ed9eba1;
f = b_reg ^ c_reg ^ d_reg;
end
else if ((round_ctr_reg >= 40) && (round_ctr_reg <= 59))
begin
k = 32'h8f1bbcdc;
f = ((b_reg | c_reg) ^ (b_reg | d_reg) ^ (c_reg | d_reg));
end
else if (round_ctr_reg >= 60)
begin
k = 32'hca62c1d6;
f = b_reg ^ c_reg ^ d_reg;
end
a5 = {a_reg[26 : 0], a_reg[31 : 27]};
t = a5 + e_reg + f + k + w;
a_new = t;
b_new = a_reg;
c_new = {b_reg[1 : 0], b_reg[31 : 2]};
d_new = c_reg;
e_new = d_reg;
a_e_we = 1;
end
end // state_logic
//----------------------------------------------------------------
// round_ctr
//
// Update logic for the round counter, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : round_ctr
round_ctr_new = 7'h0;
round_ctr_we = 1'h0;
if (round_ctr_rst)
begin
round_ctr_new = 7'h0;
round_ctr_we = 1'h1;
end
if (round_ctr_inc)
begin
round_ctr_new = round_ctr_reg + 1'h1;
round_ctr_we = 1;
end
end // round_ctr
//----------------------------------------------------------------
// sha1_ctrl_fsm
// Logic for the state machine controlling the core behaviour.
//----------------------------------------------------------------
always @*
begin : sha1_ctrl_fsm
digest_init = 1'h0;
digest_update = 1'h0;
state_init = 1'h0;
state_update = 1'h0;
first_block = 1'h0;
ready_flag = 1'h0;
w_init = 1'h0;
w_next = 1'h0;
round_ctr_inc = 1'h0;
round_ctr_rst = 1'h0;
digest_valid_new = 1'h0;
digest_valid_we = 1'h0;
sha1_ctrl_new = CTRL_IDLE;
sha1_ctrl_we = 1'h0;
case (sha1_ctrl_reg)
CTRL_IDLE:
begin
ready_flag = 1;
if (init)
begin
digest_init = 1'h1;
w_init = 1'h1;
state_init = 1'h1;
first_block = 1'h1;
round_ctr_rst = 1'h1;
digest_valid_new = 1'h0;
digest_valid_we = 1'h1;
sha1_ctrl_new = CTRL_ROUNDS;
sha1_ctrl_we = 1'h1;
end
if (next)
begin
w_init = 1'h1;
state_init = 1'h1;
round_ctr_rst = 1'h1;
digest_valid_new = 1'h0;
digest_valid_we = 1'h1;
sha1_ctrl_new = CTRL_ROUNDS;
sha1_ctrl_we = 1'h1;
end
end
CTRL_ROUNDS:
begin
state_update = 1'h1;
round_ctr_inc = 1'h1;
w_next = 1'h1;
if (round_ctr_reg == SHA1_ROUNDS)
begin
sha1_ctrl_new = CTRL_DONE;
sha1_ctrl_we = 1'h1;
end
end
CTRL_DONE:
begin
digest_update = 1'h1;
digest_valid_new = 1'h1;
digest_valid_we = 1'h1;
sha1_ctrl_new = CTRL_IDLE;
sha1_ctrl_we = 1'h1;
end
endcase // case (sha1_ctrl_reg)
end // sha1_ctrl_fsm
endmodule // sha1_core
//======================================================================
// EOF sha1_core.v
//======================================================================
|
// --------------------------------------------------------------------
// Button Debouncer
// --------------------------------------------------------------------
module Button_Debouncer(
input clk, // "clk" is the clock
input PB, // "PB" is the glitched, asynchronous, active low push-button signal
output reg PB_state // 1 while the push-button is active (down)
);
reg PB_sync_0;
reg PB_sync_1;
reg [1:0] PB_cnt; // declare a 2-bit counter
// use two flipflops to synchronize the PB signal the "clk" clock domain
always @(posedge clk) PB_sync_0 <= ~PB; // invert PB to make PB_sync_0 active high
always @(posedge clk) PB_sync_1 <= PB_sync_0;
// When the push-button is pushed or released, we increment the counter
// The counter has to be maxed out before we decide that the push-button state has changed
wire PB_idle = (PB_state==PB_sync_1);
wire PB_cnt_max = &PB_cnt; // true when all bits of PB_cnt are 1's
always @(posedge clk) begin
if(PB_idle) PB_cnt <= 2'd0; // nothing's going on
else begin
PB_cnt <= PB_cnt + 2'd1; // something's going on, increment the counter
if(PB_cnt_max) PB_state <= ~PB_state; // if the counter is maxed out, PB changed!
end
end
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2111OI_TB_V
`define SKY130_FD_SC_HD__A2111OI_TB_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a2111oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 C1 = 1'b1;
#280 D1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 C1 = 1'b0;
#460 D1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 D1 = 1'b1;
#660 C1 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 D1 = 1'bx;
#840 C1 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__a2111oi dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2111OI_TB_V
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define M 593 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 1187
/* PE: processing element */
module PE(clk, reset, ctrl, d0, d1, d2, out);
input clk;
input reset;
input [10:0] ctrl;
input [`WIDTH_D0:0] d0;
input [`WIDTH:0] d1, d2;
output [`WIDTH:0] out;
reg [`WIDTH_D0:0] R0;
reg [`WIDTH:0] R1, R2, R3;
wire [1:0] e0, e1, e2; /* part of R0 */
wire [`WIDTH:0] ppg0, ppg1, ppg2, /* output of PPG */
mx0, mx1, mx2, mx3, mx4, mx5, mx6, /* output of MUX */
ad0, ad1, ad2, /* output of GF(3^m) adder */
cu0, cu1, cu2, /* output of cubic */
mo0, mo1, mo2, /* output of mod_p */
t0, t1, t2;
wire c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10;
assign {c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10} = ctrl;
assign mx0 = c0 ? d1 : ad2;
assign mx1 = c2 ? d2 : ad2;
always @ (posedge clk)
if(reset) R1 <= 0;
else if (c1) R1 <= mx0;
always @ (posedge clk)
if(reset) R2 <= 0;
else if (c3) R2 <= mx1;
always @ (posedge clk)
if(reset) R0 <= 0;
else if (c4) R0 <= d0;
else if (c5) R0 <= R0 << 6;
assign {e2,e1,e0} = R0[`WIDTH_D0:(`WIDTH_D0-5)];
PPG
ppg_0 (e0, R1, ppg0),
ppg_1 (e1, R2, ppg1),
ppg_2 (e2, R1, ppg2);
v0 v0_ (ppg0, cu0);
v1 v1_ (ppg1, cu1);
v2 v2_ (ppg2, cu2);
assign mx2 = c6 ? ppg0 : cu0;
assign mx3 = c6 ? ppg1 : cu1;
assign mx4 = c6 ? mo1 : cu2;
assign mx5 = c7 ? mo2 : R3;
mod_p
mod_p_0 (mx3, mo0),
mod_p_1 (ppg2, t0),
mod_p_2 (t0, mo1),
mod_p_3 (R3, t1),
mod_p_4 (t1, t2),
mod_p_5 (t2, mo2);
assign mx6 = c9 ? mo0 : mx3;
f3m_add
f3m_add_0 (mx2, mx6, ad0),
f3m_add_1 (mx4, c8 ? mx5 : 0, ad1),
f3m_add_2 (ad0, ad1, ad2);
always @ (posedge clk)
if (reset) R3 <= 0;
else if (c10) R3 <= ad2;
else R3 <= 0; /* change */
assign out = R3;
endmodule
// C = (x*B mod p(x))
module mod_p(B, C);
input [`WIDTH:0] B;
output [`WIDTH:0] C;
wire [`WIDTH+2:0] A;
assign A = {B[`WIDTH:0], 2'd0}; // A == B*x
wire [1:0] w0;
f3_mult m0 (A[1187:1186], 2'd2, w0);
f3_sub s0 (A[1:0], w0, C[1:0]);
assign C[223:2] = A[223:2];
wire [1:0] w112;
f3_mult m112 (A[1187:1186], 2'd1, w112);
f3_sub s112 (A[225:224], w112, C[225:224]);
assign C[1185:226] = A[1185:226];
endmodule
// PPG: partial product generator, C == A*d in GF(3^m)
module PPG(d, A, C);
input [1:0] d;
input [`WIDTH:0] A;
output [`WIDTH:0] C;
genvar i;
generate
for (i=0; i < `M; i=i+1)
begin: ppg0
f3_mult f3_mult_0 (d, A[2*i+1:2*i], C[2*i+1:2*i]);
end
endgenerate
endmodule
// f3m_add: C = A + B, in field F_{3^M}
module f3m_add(A, B, C);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for(i=0; i<`M; i=i+1) begin: aa
f3_add aa(A[(2*i+1) : 2*i], B[(2*i+1) : 2*i], C[(2*i+1) : 2*i]);
end
endgenerate
endmodule
// f3_add: C == A+B (mod 3)
module f3_add(A, B, C);
input [1:0] A, B;
output [1:0] C;
wire a0, a1, b0, b1, c0, c1;
assign {a1, a0} = A;
assign {b1, b0} = B;
assign C = {c1, c0};
assign c0 = ( a0 & ~a1 & ~b0 & ~b1) |
(~a0 & ~a1 & b0 & ~b1) |
(~a0 & a1 & ~b0 & b1) ;
assign c1 = (~a0 & a1 & ~b0 & ~b1) |
( a0 & ~a1 & b0 & ~b1) |
(~a0 & ~a1 & ~b0 & b1) ;
endmodule
// f3_sub: C == A-B (mod 3)
module f3_sub(A, B, C);
input [1:0] A, B;
output [1:0] C;
f3_add a0(A, {B[0],B[1]}, C);
endmodule
// f3_mult: C = A*B (mod 3)
module f3_mult(A, B, C);
input [1:0] A;
input [1:0] B;
output [1:0] C;
wire a0, a1, b0, b1;
assign {a1, a0} = A;
assign {b1, b0} = B;
assign C[0] = (~a1 & a0 & ~b1 & b0) | (a1 & ~a0 & b1 & ~b0);
assign C[1] = (~a1 & a0 & b1 & ~b0) | (a1 & ~a0 & ~b1 & b0);
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 125MHz LVDS
* Reset: Push button, active low
*/
input wire clk_125mhz_p,
input wire clk_125mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* I2C for board management
*/
inout wire i2c_scl,
inout wire i2c_sda,
/*
* Ethernet: QSFP28
*/
input wire qsfp_rx1_p,
input wire qsfp_rx1_n,
input wire qsfp_rx2_p,
input wire qsfp_rx2_n,
input wire qsfp_rx3_p,
input wire qsfp_rx3_n,
input wire qsfp_rx4_p,
input wire qsfp_rx4_n,
output wire qsfp_tx1_p,
output wire qsfp_tx1_n,
output wire qsfp_tx2_p,
output wire qsfp_tx2_n,
output wire qsfp_tx3_p,
output wire qsfp_tx3_n,
output wire qsfp_tx4_p,
output wire qsfp_tx4_n,
input wire qsfp_mgt_refclk_0_p,
input wire qsfp_mgt_refclk_0_n,
// input wire qsfp_mgt_refclk_1_p,
// input wire qsfp_mgt_refclk_1_n,
// output wire qsfp_recclk_p,
// output wire qsfp_recclk_n,
output wire qsfp_modsell,
output wire qsfp_resetl,
input wire qsfp_modprsl,
input wire qsfp_intl,
output wire qsfp_lpmode,
/*
* Ethernet: 1000BASE-T SGMII
*/
input wire phy_sgmii_rx_p,
input wire phy_sgmii_rx_n,
output wire phy_sgmii_tx_p,
output wire phy_sgmii_tx_n,
input wire phy_sgmii_clk_p,
input wire phy_sgmii_clk_n,
output wire phy_reset_n,
input wire phy_int_n,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// Clock and reset
wire clk_125mhz_ibufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_125mhz_ibufg_inst (
.O (clk_125mhz_ibufg),
.I (clk_125mhz_p),
.IB (clk_125mhz_n)
);
// MMCM instance
// 125 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 600 MHz to 1440 MHz
// M = 5, D = 1 sets Fvco = 625 MHz (in range)
// Divide by 5 to get output frequency of 125 MHz
MMCME3_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(5),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(5),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(8.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_125mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(4),
.RATE(156000)
)
debounce_switch_inst (
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_cts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_156mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
);
// SI570 I2C
wire i2c_scl_i;
wire i2c_scl_o = 1'b1;
wire i2c_scl_t = 1'b1;
wire i2c_sda_i;
wire i2c_sda_o = 1'b1;
wire i2c_sda_t = 1'b1;
assign i2c_scl_i = i2c_scl;
assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
assign i2c_sda_i = i2c_sda;
assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
// XGMII 10G PHY
assign qsfp_modsell = 1'b0;
assign qsfp_resetl = 1'b1;
assign qsfp_lpmode = 1'b0;
wire qsfp_tx_clk_1_int;
wire qsfp_tx_rst_1_int;
wire [63:0] qsfp_txd_1_int;
wire [7:0] qsfp_txc_1_int;
wire qsfp_rx_clk_1_int;
wire qsfp_rx_rst_1_int;
wire [63:0] qsfp_rxd_1_int;
wire [7:0] qsfp_rxc_1_int;
wire qsfp_tx_clk_2_int;
wire qsfp_tx_rst_2_int;
wire [63:0] qsfp_txd_2_int;
wire [7:0] qsfp_txc_2_int;
wire qsfp_rx_clk_2_int;
wire qsfp_rx_rst_2_int;
wire [63:0] qsfp_rxd_2_int;
wire [7:0] qsfp_rxc_2_int;
wire qsfp_tx_clk_3_int;
wire qsfp_tx_rst_3_int;
wire [63:0] qsfp_txd_3_int;
wire [7:0] qsfp_txc_3_int;
wire qsfp_rx_clk_3_int;
wire qsfp_rx_rst_3_int;
wire [63:0] qsfp_rxd_3_int;
wire [7:0] qsfp_rxc_3_int;
wire qsfp_tx_clk_4_int;
wire qsfp_tx_rst_4_int;
wire [63:0] qsfp_txd_4_int;
wire [7:0] qsfp_txc_4_int;
wire qsfp_rx_clk_4_int;
wire qsfp_rx_rst_4_int;
wire [63:0] qsfp_rxd_4_int;
wire [7:0] qsfp_rxc_4_int;
wire qsfp_rx_block_lock_1;
wire qsfp_rx_block_lock_2;
wire qsfp_rx_block_lock_3;
wire qsfp_rx_block_lock_4;
wire qsfp_mgt_refclk_0;
wire [3:0] gt_txclkout;
wire gt_txusrclk;
wire [3:0] gt_rxclkout;
wire [3:0] gt_rxusrclk;
wire gt_reset_tx_done;
wire gt_reset_rx_done;
wire [3:0] gt_txprgdivresetdone;
wire [3:0] gt_txpmaresetdone;
wire [3:0] gt_rxprgdivresetdone;
wire [3:0] gt_rxpmaresetdone;
wire gt_tx_reset = ~((>_txprgdivresetdone) & (>_txpmaresetdone));
wire gt_rx_reset = ~>_rxpmaresetdone;
reg gt_userclk_tx_active = 1'b0;
reg [3:0] gt_userclk_rx_active = 1'b0;
IBUFDS_GTE3 ibufds_gte3_qsfp_mgt_refclk_0_inst (
.I (qsfp_mgt_refclk_0_p),
.IB (qsfp_mgt_refclk_0_n),
.CEB (1'b0),
.O (qsfp_mgt_refclk_0),
.ODIV2 ()
);
BUFG_GT bufg_gt_tx_usrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_tx_reset),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (gt_txclkout[0]),
.O (gt_txusrclk)
);
assign clk_156mhz_int = gt_txusrclk;
always @(posedge gt_txusrclk, posedge gt_tx_reset) begin
if (gt_tx_reset) begin
gt_userclk_tx_active <= 1'b0;
end else begin
gt_userclk_tx_active <= 1'b1;
end
end
genvar n;
generate
for (n = 0; n < 4; n = n + 1) begin
BUFG_GT bufg_gt_rx_usrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_rx_reset),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (gt_rxclkout[n]),
.O (gt_rxusrclk[n])
);
always @(posedge gt_rxusrclk[n], posedge gt_rx_reset) begin
if (gt_rx_reset) begin
gt_userclk_rx_active[n] <= 1'b0;
end else begin
gt_userclk_rx_active[n] <= 1'b1;
end
end
end
endgenerate
sync_reset #(
.N(4)
)
sync_reset_156mhz_inst (
.clk(clk_156mhz_int),
.rst(~gt_reset_tx_done),
.out(rst_156mhz_int)
);
wire [5:0] qsfp_gt_txheader_1;
wire [63:0] qsfp_gt_txdata_1;
wire qsfp_gt_rxgearboxslip_1;
wire [5:0] qsfp_gt_rxheader_1;
wire [1:0] qsfp_gt_rxheadervalid_1;
wire [63:0] qsfp_gt_rxdata_1;
wire [1:0] qsfp_gt_rxdatavalid_1;
wire [5:0] qsfp_gt_txheader_2;
wire [63:0] qsfp_gt_txdata_2;
wire qsfp_gt_rxgearboxslip_2;
wire [5:0] qsfp_gt_rxheader_2;
wire [1:0] qsfp_gt_rxheadervalid_2;
wire [63:0] qsfp_gt_rxdata_2;
wire [1:0] qsfp_gt_rxdatavalid_2;
wire [5:0] qsfp_gt_txheader_3;
wire [63:0] qsfp_gt_txdata_3;
wire qsfp_gt_rxgearboxslip_3;
wire [5:0] qsfp_gt_rxheader_3;
wire [1:0] qsfp_gt_rxheadervalid_3;
wire [63:0] qsfp_gt_rxdata_3;
wire [1:0] qsfp_gt_rxdatavalid_3;
wire [5:0] qsfp_gt_txheader_4;
wire [63:0] qsfp_gt_txdata_4;
wire qsfp_gt_rxgearboxslip_4;
wire [5:0] qsfp_gt_rxheader_4;
wire [1:0] qsfp_gt_rxheadervalid_4;
wire [63:0] qsfp_gt_rxdata_4;
wire [1:0] qsfp_gt_rxdatavalid_4;
gtwizard_ultrascale_0
qsfp_gty_inst (
.gtwiz_userclk_tx_active_in(>_userclk_tx_active),
.gtwiz_userclk_rx_active_in(>_userclk_rx_active),
.gtwiz_reset_clk_freerun_in(clk_125mhz_int),
.gtwiz_reset_all_in(rst_125mhz_int),
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
.gtwiz_reset_tx_datapath_in(1'b0),
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
.gtwiz_reset_rx_datapath_in(1'b0),
.gtwiz_reset_rx_cdr_stable_out(),
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
.gtrefclk00_in({1{qsfp_mgt_refclk_0}}),
.qpll0outclk_out(),
.qpll0outrefclk_out(),
.gtyrxn_in({qsfp_rx4_n, qsfp_rx3_n, qsfp_rx2_n, qsfp_rx1_n}),
.gtyrxp_in({qsfp_rx4_p, qsfp_rx3_p, qsfp_rx2_p, qsfp_rx1_p}),
.rxusrclk_in(gt_rxusrclk),
.rxusrclk2_in(gt_rxusrclk),
.gtwiz_userdata_tx_in({qsfp_gt_txdata_4, qsfp_gt_txdata_3, qsfp_gt_txdata_2, qsfp_gt_txdata_1}),
.txheader_in({qsfp_gt_txheader_4, qsfp_gt_txheader_3, qsfp_gt_txheader_2, qsfp_gt_txheader_1}),
.txsequence_in({4{1'b0}}),
.txusrclk_in({4{gt_txusrclk}}),
.txusrclk2_in({4{gt_txusrclk}}),
.gtpowergood_out(),
.gtytxn_out({qsfp_tx4_n, qsfp_tx3_n, qsfp_tx2_n, qsfp_tx1_n}),
.gtytxp_out({qsfp_tx4_p, qsfp_tx3_p, qsfp_tx2_p, qsfp_tx1_p}),
.rxgearboxslip_in({qsfp_gt_rxgearboxslip_4, qsfp_gt_rxgearboxslip_3, qsfp_gt_rxgearboxslip_2, qsfp_gt_rxgearboxslip_1}),
.gtwiz_userdata_rx_out({qsfp_gt_rxdata_4, qsfp_gt_rxdata_3, qsfp_gt_rxdata_2, qsfp_gt_rxdata_1}),
.rxdatavalid_out({qsfp_gt_rxdatavalid_4, qsfp_gt_rxdatavalid_3, qsfp_gt_rxdatavalid_2, qsfp_gt_rxdatavalid_1}),
.rxheader_out({qsfp_gt_rxheader_4, qsfp_gt_rxheader_3, qsfp_gt_rxheader_2, qsfp_gt_rxheader_1}),
.rxheadervalid_out({qsfp_gt_rxheadervalid_4, qsfp_gt_rxheadervalid_3, qsfp_gt_rxheadervalid_2, qsfp_gt_rxheadervalid_1}),
.rxoutclk_out(gt_rxclkout),
.rxpmaresetdone_out(gt_rxpmaresetdone),
.rxprgdivresetdone_out(gt_rxprgdivresetdone),
.rxstartofseq_out(),
.txoutclk_out(gt_txclkout),
.txpmaresetdone_out(gt_txpmaresetdone),
.txprgdivresetdone_out(gt_txprgdivresetdone)
);
assign qsfp_tx_clk_1_int = clk_156mhz_int;
assign qsfp_tx_rst_1_int = rst_156mhz_int;
assign qsfp_rx_clk_1_int = gt_rxusrclk[0];
sync_reset #(
.N(4)
)
qsfp_rx_rst_1_reset_sync_inst (
.clk(qsfp_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.out(qsfp_rx_rst_1_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp_phy_1_inst (
.tx_clk(qsfp_tx_clk_1_int),
.tx_rst(qsfp_tx_rst_1_int),
.rx_clk(qsfp_rx_clk_1_int),
.rx_rst(qsfp_rx_rst_1_int),
.xgmii_txd(qsfp_txd_1_int),
.xgmii_txc(qsfp_txc_1_int),
.xgmii_rxd(qsfp_rxd_1_int),
.xgmii_rxc(qsfp_rxc_1_int),
.serdes_tx_data(qsfp_gt_txdata_1),
.serdes_tx_hdr(qsfp_gt_txheader_1),
.serdes_rx_data(qsfp_gt_rxdata_1),
.serdes_rx_hdr(qsfp_gt_rxheader_1),
.serdes_rx_bitslip(qsfp_gt_rxgearboxslip_1),
.rx_block_lock(qsfp_rx_block_lock_1),
.rx_high_ber()
);
assign qsfp_tx_clk_2_int = clk_156mhz_int;
assign qsfp_tx_rst_2_int = rst_156mhz_int;
assign qsfp_rx_clk_2_int = gt_rxusrclk[1];
sync_reset #(
.N(4)
)
qsfp_rx_rst_2_reset_sync_inst (
.clk(qsfp_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.out(qsfp_rx_rst_2_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp_phy_2_inst (
.tx_clk(qsfp_tx_clk_2_int),
.tx_rst(qsfp_tx_rst_2_int),
.rx_clk(qsfp_rx_clk_2_int),
.rx_rst(qsfp_rx_rst_2_int),
.xgmii_txd(qsfp_txd_2_int),
.xgmii_txc(qsfp_txc_2_int),
.xgmii_rxd(qsfp_rxd_2_int),
.xgmii_rxc(qsfp_rxc_2_int),
.serdes_tx_data(qsfp_gt_txdata_2),
.serdes_tx_hdr(qsfp_gt_txheader_2),
.serdes_rx_data(qsfp_gt_rxdata_2),
.serdes_rx_hdr(qsfp_gt_rxheader_2),
.serdes_rx_bitslip(qsfp_gt_rxgearboxslip_2),
.rx_block_lock(qsfp_rx_block_lock_2),
.rx_high_ber()
);
assign qsfp_tx_clk_3_int = clk_156mhz_int;
assign qsfp_tx_rst_3_int = rst_156mhz_int;
assign qsfp_rx_clk_3_int = gt_rxusrclk[2];
sync_reset #(
.N(4)
)
qsfp_rx_rst_3_reset_sync_inst (
.clk(qsfp_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.out(qsfp_rx_rst_3_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp_phy_3_inst (
.tx_clk(qsfp_tx_clk_3_int),
.tx_rst(qsfp_tx_rst_3_int),
.rx_clk(qsfp_rx_clk_3_int),
.rx_rst(qsfp_rx_rst_3_int),
.xgmii_txd(qsfp_txd_3_int),
.xgmii_txc(qsfp_txc_3_int),
.xgmii_rxd(qsfp_rxd_3_int),
.xgmii_rxc(qsfp_rxc_3_int),
.serdes_tx_data(qsfp_gt_txdata_3),
.serdes_tx_hdr(qsfp_gt_txheader_3),
.serdes_rx_data(qsfp_gt_rxdata_3),
.serdes_rx_hdr(qsfp_gt_rxheader_3),
.serdes_rx_bitslip(qsfp_gt_rxgearboxslip_3),
.rx_block_lock(qsfp_rx_block_lock_3),
.rx_high_ber()
);
assign qsfp_tx_clk_4_int = clk_156mhz_int;
assign qsfp_tx_rst_4_int = rst_156mhz_int;
assign qsfp_rx_clk_4_int = gt_rxusrclk[3];
sync_reset #(
.N(4)
)
qsfp_rx_rst_4_reset_sync_inst (
.clk(qsfp_rx_clk_4_int),
.rst(~gt_reset_rx_done),
.out(qsfp_rx_rst_4_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp_phy_4_inst (
.tx_clk(qsfp_tx_clk_4_int),
.tx_rst(qsfp_tx_rst_4_int),
.rx_clk(qsfp_rx_clk_4_int),
.rx_rst(qsfp_rx_rst_4_int),
.xgmii_txd(qsfp_txd_4_int),
.xgmii_txc(qsfp_txc_4_int),
.xgmii_rxd(qsfp_rxd_4_int),
.xgmii_rxc(qsfp_rxc_4_int),
.serdes_tx_data(qsfp_gt_txdata_4),
.serdes_tx_hdr(qsfp_gt_txheader_4),
.serdes_rx_data(qsfp_gt_rxdata_4),
.serdes_rx_hdr(qsfp_gt_rxheader_4),
.serdes_rx_bitslip(qsfp_gt_rxgearboxslip_4),
.rx_block_lock(qsfp_rx_block_lock_4),
.rx_high_ber()
);
// SGMII interface to PHY
wire phy_gmii_clk_int;
wire phy_gmii_rst_int;
wire phy_gmii_clk_en_int;
wire [7:0] phy_gmii_txd_int;
wire phy_gmii_tx_en_int;
wire phy_gmii_tx_er_int;
wire [7:0] phy_gmii_rxd_int;
wire phy_gmii_rx_dv_int;
wire phy_gmii_rx_er_int;
wire [15:0] gig_eth_pcspma_status_vector;
wire gig_eth_pcspma_status_link_status = gig_eth_pcspma_status_vector[0];
wire gig_eth_pcspma_status_link_synchronization = gig_eth_pcspma_status_vector[1];
wire gig_eth_pcspma_status_rudi_c = gig_eth_pcspma_status_vector[2];
wire gig_eth_pcspma_status_rudi_i = gig_eth_pcspma_status_vector[3];
wire gig_eth_pcspma_status_rudi_invalid = gig_eth_pcspma_status_vector[4];
wire gig_eth_pcspma_status_rxdisperr = gig_eth_pcspma_status_vector[5];
wire gig_eth_pcspma_status_rxnotintable = gig_eth_pcspma_status_vector[6];
wire gig_eth_pcspma_status_phy_link_status = gig_eth_pcspma_status_vector[7];
wire [1:0] gig_eth_pcspma_status_remote_fault_encdg = gig_eth_pcspma_status_vector[9:8];
wire [1:0] gig_eth_pcspma_status_speed = gig_eth_pcspma_status_vector[11:10];
wire gig_eth_pcspma_status_duplex = gig_eth_pcspma_status_vector[12];
wire gig_eth_pcspma_status_remote_fault = gig_eth_pcspma_status_vector[13];
wire [1:0] gig_eth_pcspma_status_pause = gig_eth_pcspma_status_vector[15:14];
wire [4:0] gig_eth_pcspma_config_vector;
assign gig_eth_pcspma_config_vector[4] = 1'b1; // autonegotiation enable
assign gig_eth_pcspma_config_vector[3] = 1'b0; // isolate
assign gig_eth_pcspma_config_vector[2] = 1'b0; // power down
assign gig_eth_pcspma_config_vector[1] = 1'b0; // loopback enable
assign gig_eth_pcspma_config_vector[0] = 1'b0; // unidirectional enable
wire [15:0] gig_eth_pcspma_an_config_vector;
assign gig_eth_pcspma_an_config_vector[15] = 1'b1; // SGMII link status
assign gig_eth_pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge
assign gig_eth_pcspma_an_config_vector[13:12] = 2'b01; // full duplex
assign gig_eth_pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed
assign gig_eth_pcspma_an_config_vector[9] = 1'b0; // reserved
assign gig_eth_pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved
assign gig_eth_pcspma_an_config_vector[6] = 1'b0; // reserved
assign gig_eth_pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved
assign gig_eth_pcspma_an_config_vector[4:1] = 4'b0000; // reserved
assign gig_eth_pcspma_an_config_vector[0] = 1'b1; // SGMII
gig_ethernet_pcs_pma_0
gig_eth_pcspma (
// SGMII
.txp (phy_sgmii_tx_p),
.txn (phy_sgmii_tx_n),
.rxp (phy_sgmii_rx_p),
.rxn (phy_sgmii_rx_n),
// Ref clock from PHY
.refclk625_p (phy_sgmii_clk_p),
.refclk625_n (phy_sgmii_clk_n),
// async reset
.reset (rst_125mhz_int),
// clock and reset outputs
.clk125_out (phy_gmii_clk_int),
.clk625_out (),
.clk312_out (),
.rst_125_out (phy_gmii_rst_int),
.idelay_rdy_out (),
.mmcm_locked_out (),
// MAC clocking
.sgmii_clk_r (),
.sgmii_clk_f (),
.sgmii_clk_en (phy_gmii_clk_en_int),
// Speed control
.speed_is_10_100 (gig_eth_pcspma_status_speed != 2'b10),
.speed_is_100 (gig_eth_pcspma_status_speed == 2'b01),
// Internal GMII
.gmii_txd (phy_gmii_txd_int),
.gmii_tx_en (phy_gmii_tx_en_int),
.gmii_tx_er (phy_gmii_tx_er_int),
.gmii_rxd (phy_gmii_rxd_int),
.gmii_rx_dv (phy_gmii_rx_dv_int),
.gmii_rx_er (phy_gmii_rx_er_int),
.gmii_isolate (),
// Configuration
.configuration_vector (gig_eth_pcspma_config_vector),
.an_interrupt (),
.an_adv_config_vector (gig_eth_pcspma_an_config_vector),
.an_restart_config (1'b0),
// Status
.status_vector (gig_eth_pcspma_status_vector),
.signal_detect (1'b1)
);
wire [7:0] led_int;
assign led = sw[0] ? {4'd0, qsfp_rx_block_lock_4, qsfp_rx_block_lock_3, qsfp_rx_block_lock_2, qsfp_rx_block_lock_1} : led_int;
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led_int),
/*
* Ethernet: QSFP28
*/
.qsfp_tx_clk_1(qsfp_tx_clk_1_int),
.qsfp_tx_rst_1(qsfp_tx_rst_1_int),
.qsfp_txd_1(qsfp_txd_1_int),
.qsfp_txc_1(qsfp_txc_1_int),
.qsfp_rx_clk_1(qsfp_rx_clk_1_int),
.qsfp_rx_rst_1(qsfp_rx_rst_1_int),
.qsfp_rxd_1(qsfp_rxd_1_int),
.qsfp_rxc_1(qsfp_rxc_1_int),
.qsfp_tx_clk_2(qsfp_tx_clk_2_int),
.qsfp_tx_rst_2(qsfp_tx_rst_2_int),
.qsfp_txd_2(qsfp_txd_2_int),
.qsfp_txc_2(qsfp_txc_2_int),
.qsfp_rx_clk_2(qsfp_rx_clk_2_int),
.qsfp_rx_rst_2(qsfp_rx_rst_2_int),
.qsfp_rxd_2(qsfp_rxd_2_int),
.qsfp_rxc_2(qsfp_rxc_2_int),
.qsfp_tx_clk_3(qsfp_tx_clk_3_int),
.qsfp_tx_rst_3(qsfp_tx_rst_3_int),
.qsfp_txd_3(qsfp_txd_3_int),
.qsfp_txc_3(qsfp_txc_3_int),
.qsfp_rx_clk_3(qsfp_rx_clk_3_int),
.qsfp_rx_rst_3(qsfp_rx_rst_3_int),
.qsfp_rxd_3(qsfp_rxd_3_int),
.qsfp_rxc_3(qsfp_rxc_3_int),
.qsfp_tx_clk_4(qsfp_tx_clk_4_int),
.qsfp_tx_rst_4(qsfp_tx_rst_4_int),
.qsfp_txd_4(qsfp_txd_4_int),
.qsfp_txc_4(qsfp_txc_4_int),
.qsfp_rx_clk_4(qsfp_rx_clk_4_int),
.qsfp_rx_rst_4(qsfp_rx_rst_4_int),
.qsfp_rxd_4(qsfp_rxd_4_int),
.qsfp_rxc_4(qsfp_rxc_4_int),
/*
* Ethernet: 1000BASE-T SGMII
*/
.phy_gmii_clk(phy_gmii_clk_int),
.phy_gmii_rst(phy_gmii_rst_int),
.phy_gmii_clk_en(phy_gmii_clk_en_int),
.phy_gmii_rxd(phy_gmii_rxd_int),
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
.phy_gmii_rx_er(phy_gmii_rx_er_int),
.phy_gmii_txd(phy_gmii_txd_int),
.phy_gmii_tx_en(phy_gmii_tx_en_int),
.phy_gmii_tx_er(phy_gmii_tx_er_int),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int)
);
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant I2C Master bit-controller ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_bit_ctrl.v,v 1.11 2004/05/07 11:02:26 rherveille Exp $
//
// $Date: 2004/05/07 11:02:26 $
// $Revision: 1.11 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: i2c_master_bit_ctrl.v,v $
// Revision 1.11 2004/05/07 11:02:26 rherveille
// Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
//
// Revision 1.10 2003/08/09 07:01:33 rherveille
// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
// Fixed a potential bug in the byte controller's host-acknowledge generation.
//
// Revision 1.9 2003/03/10 14:26:37 rherveille
// Fixed cmd_ack generation item (no bug).
//
// Revision 1.8 2003/02/05 00:06:10 rherveille
// Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
//
// Revision 1.7 2002/12/26 16:05:12 rherveille
// Small code simplifications
//
// Revision 1.6 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.5 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.4 2002/10/30 18:10:07 rherveille
// Fixed some reported minor start/stop generation timing issuess.
//
// Revision 1.3 2002/06/15 07:37:03 rherveille
// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
//
// Revision 1.2 2001/11/05 11:59:25 rherveille
// Fixed wb_ack_o generation bug.
// Fixed bug in the byte_controller statemachine.
// Added headers.
//
//
/////////////////////////////////////
// Bit controller section
/////////////////////////////////////
//
// Translate simple commands into SCL/SDA transitions
// Each command has 5 states, A/B/C/D/idle
//
// start: SCL ~~~~~~~~~~\____
// SDA ~~~~~~~~\______
// x | A | B | C | D | i
//
// repstart SCL ____/~~~~\___
// SDA __/~~~\______
// x | A | B | C | D | i
//
// stop SCL ____/~~~~~~~~
// SDA ==\____/~~~~~
// x | A | B | C | D | i
//
//- write SCL ____/~~~~\____
// SDA ==X=========X=
// x | A | B | C | D | i
//
//- read SCL ____/~~~~\____
// SDA XXXX=====XXXX
// x | A | B | C | D | i
//
// Timing: Normal mode Fast mode
///////////////////////////////////////////////////////////////////////
// Fscl 100KHz 400KHz
// Th_scl 4.0us 0.6us High period of SCL
// Tl_scl 4.7us 1.3us Low period of SCL
// Tsu:sta 4.7us 0.6us setup time for a repeated start condition
// Tsu:sto 4.0us 0.6us setup time for a stop conditon
// Tbuf 4.7us 1.3us Bus free time between a stop and start condition
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "i2c_master_defines.v"
module i2c_master_bit_ctrl(
clk, rst, nReset,
clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout,
scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen, spi_miso
);
// parameters
parameter dedicated_spi = 0;
//
// inputs & outputs
//
input clk;
input rst;
input nReset;
input ena; // core enable signal
input [15:0] clk_cnt; // clock prescale value
input [5:0] cmd;
output cmd_ack; // command complete acknowledge
reg cmd_ack;
output busy; // i2c bus busy
reg busy;
output al; // i2c bus arbitration lost
reg al;
input din;
output dout;
reg dout;
// I2C lines
input scl_i; // i2c clock line input
output scl_o; // i2c clock line output
output scl_oen; // i2c clock line output enable (active low)
reg scl_oen;
input sda_i; // i2c data line input
output sda_o; // i2c data line output
output sda_oen; // i2c data line output enable (active low)
reg sda_oen;
// SPI MISO
input spi_miso;
reg spi_rden;
//
// variable declarations
//
reg sSCL, sSDA; // synchronized SCL and SDA inputs
reg dscl_oen; // delayed scl_oen
reg sda_chk; // check SDA output (Multi-master arbitration)
reg clk_en; // clock generation signals
wire slave_wait;
// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
reg [15:0] cnt; // clock divider counter (synthesis)
// state machine variable
reg [24:0] c_state;
//
// module body
//
// whenever the slave is not ready it can delay the cycle by pulling SCL low
// delay scl_oen
always @(posedge clk)
dscl_oen <= #1 scl_oen;
assign slave_wait = dscl_oen && !sSCL;
// generate clk enable signal
always @(posedge clk or negedge nReset)
if(~nReset)
begin
cnt <= #1 16'h0;
clk_en <= #1 1'b1;
end
else if (rst)
begin
cnt <= #1 16'h0;
clk_en <= #1 1'b1;
end
else if ( ~|cnt || ~ena)
if (~slave_wait)
begin
cnt <= #1 clk_cnt;
clk_en <= #1 1'b1;
end
else
begin
cnt <= #1 cnt;
clk_en <= #1 1'b0;
end
else
begin
cnt <= #1 cnt - 16'h1;
clk_en <= #1 1'b0;
end
// generate bus status controller
reg dSCL, dSDA;
reg sta_condition;
reg sto_condition;
// synchronize SCL and SDA inputs
// reduce metastability risc
always @(posedge clk or negedge nReset)
if (~nReset)
begin
sSCL <= #1 1'b1;
sSDA <= #1 1'b1;
dSCL <= #1 1'b1;
dSDA <= #1 1'b1;
end
else if (rst)
begin
sSCL <= #1 1'b1;
sSDA <= #1 1'b1;
dSCL <= #1 1'b1;
dSDA <= #1 1'b1;
end
else
begin
sSCL <= #1 scl_i;
sSDA <= #1 spi_rden ? spi_miso : sda_i;
dSCL <= #1 sSCL;
dSDA <= #1 sSDA;
end
// detect start condition => detect falling edge on SDA while SCL is high
// detect stop condition => detect rising edge on SDA while SCL is high
always @(posedge clk or negedge nReset)
if (~nReset)
begin
sta_condition <= #1 1'b0;
sto_condition <= #1 1'b0;
end
else if (rst)
begin
sta_condition <= #1 1'b0;
sto_condition <= #1 1'b0;
end
else
begin
sta_condition <= #1 ~sSDA & dSDA & sSCL;
sto_condition <= #1 sSDA & ~dSDA & sSCL;
end
// generate i2c bus busy signal
always @(posedge clk or negedge nReset)
if(!nReset)
busy <= #1 1'b0;
else if (rst)
busy <= #1 1'b0;
else
busy <= #1 (sta_condition | busy) & ~sto_condition;
// generate arbitration lost signal
// aribitration lost when:
// 1) master drives SDA high, but the i2c bus is low
// 2) stop detected while not requested
reg cmd_stop;
always @(posedge clk or negedge nReset)
if (~nReset)
cmd_stop <= #1 1'b0;
else if (rst)
cmd_stop <= #1 1'b0;
else if (clk_en)
cmd_stop <= #1 (cmd & (`I2C_CMD_STOP|`SPI_CMD_WRITE|`SPI_CMD_READ)) != 6'b000000;
always @(posedge clk or negedge nReset)
if (~nReset)
al <= #1 1'b0;
else if (rst)
al <= #1 1'b0;
else
al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
// generate dout signal (store SDA on rising edge of SCL)
always @(posedge clk)
if(sSCL & ~dSCL)
dout <= #1 sSDA;
// generate statemachine
// nxt_state decoder
parameter [24:0] idle = 25'b0_0000_0000_0000_0000_0000_0000;
parameter [24:0] start_a = 25'b0_0000_0000_0000_0000_0000_0001;
parameter [24:0] start_b = 25'b0_0000_0000_0000_0000_0000_0010;
parameter [24:0] start_c = 25'b0_0000_0000_0000_0000_0000_0100;
parameter [24:0] start_d = 25'b0_0000_0000_0000_0000_0000_1000;
parameter [24:0] start_e = 25'b0_0000_0000_0000_0000_0001_0000;
parameter [24:0] stop_a = 25'b0_0000_0000_0000_0000_0010_0000;
parameter [24:0] stop_b = 25'b0_0000_0000_0000_0000_0100_0000;
parameter [24:0] stop_c = 25'b0_0000_0000_0000_0000_1000_0000;
parameter [24:0] stop_d = 25'b0_0000_0000_0000_0001_0000_0000;
parameter [24:0] rd_a = 25'b0_0000_0000_0000_0010_0000_0000;
parameter [24:0] rd_b = 25'b0_0000_0000_0000_0100_0000_0000;
parameter [24:0] rd_c = 25'b0_0000_0000_0000_1000_0000_0000;
parameter [24:0] rd_d = 25'b0_0000_0000_0001_0000_0000_0000;
parameter [24:0] wr_a = 25'b0_0000_0000_0010_0000_0000_0000;
parameter [24:0] wr_b = 25'b0_0000_0000_0100_0000_0000_0000;
parameter [24:0] wr_c = 25'b0_0000_0000_1000_0000_0000_0000;
parameter [24:0] wr_d = 25'b0_0000_0001_0000_0000_0000_0000;
parameter [24:0] spi_rd_a = 25'b0_0000_0010_0000_0000_0000_0000;
parameter [24:0] spi_rd_b = 25'b0_0000_0100_0000_0000_0000_0000;
parameter [24:0] spi_rd_c = 25'b0_0000_1000_0000_0000_0000_0000;
parameter [24:0] spi_rd_d = 25'b0_0001_0000_0000_0000_0000_0000;
parameter [24:0] spi_wr_a = 25'b0_0010_0000_0000_0000_0000_0000;
parameter [24:0] spi_wr_b = 25'b0_0100_0000_0000_0000_0000_0000;
parameter [24:0] spi_wr_c = 25'b0_1000_0000_0000_0000_0000_0000;
parameter [24:0] spi_wr_d = 25'b1_0000_0000_0000_0000_0000_0000;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b0;
scl_oen <= #1 1'b1;
sda_oen <= #1 1'b1;
sda_chk <= #1 1'b0;
spi_rden <= #1 1'b0;
end
else if (rst | al)
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b0;
scl_oen <= #1 1'b1;
sda_oen <= #1 1'b1;
sda_chk <= #1 1'b0;
spi_rden <= #1 1'b0;
end
else
begin
cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
if (clk_en)
case (c_state)
// idle state
idle:
begin
case (cmd)
`I2C_CMD_START:
c_state <= #1 start_a;
`I2C_CMD_STOP:
c_state <= #1 stop_a;
`I2C_CMD_WRITE:
c_state <= #1 wr_a;
`I2C_CMD_READ:
c_state <= #1 rd_a;
`SPI_CMD_WRITE:
c_state <= #1 spi_wr_a;
`SPI_CMD_READ:
c_state <= #1 spi_rd_a;
default:
c_state <= #1 idle;
endcase
scl_oen <= #1 scl_oen; // keep SCL in same state
sda_oen <= #1 sda_oen; // keep SDA in same state
sda_chk <= #1 1'b0; // don't check SDA output
end
// start
start_a:
begin
c_state <= #1 start_b;
scl_oen <= #1 scl_oen; // keep SCL in same state
sda_oen <= #1 1'b1; // set SDA high
sda_chk <= #1 1'b0; // don't check SDA output
end
start_b:
begin
c_state <= #1 start_c;
scl_oen <= #1 1'b1; // set SCL high
sda_oen <= #1 1'b1; // keep SDA high
sda_chk <= #1 1'b0; // don't check SDA output
end
start_c:
begin
c_state <= #1 start_d;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b0; // set SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
start_d:
begin
c_state <= #1 start_e;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b0; // keep SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
start_e:
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b1;
scl_oen <= #1 1'b0; // set SCL low
sda_oen <= #1 1'b0; // keep SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
// stop
stop_a:
begin
c_state <= #1 stop_b;
scl_oen <= #1 1'b0; // keep SCL low
sda_oen <= #1 1'b0; // set SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
stop_b:
begin
c_state <= #1 stop_c;
scl_oen <= #1 1'b1; // set SCL high
sda_oen <= #1 1'b0; // keep SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
stop_c:
begin
c_state <= #1 stop_d;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b0; // keep SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
stop_d:
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b1;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b1; // set SDA high
sda_chk <= #1 1'b0; // don't check SDA output
end
// read
rd_a:
begin
c_state <= #1 rd_b;
scl_oen <= #1 1'b0; // keep SCL low
sda_oen <= #1 1'b1; // tri-state SDA
sda_chk <= #1 1'b0; // don't check SDA output
end
rd_b:
begin
c_state <= #1 rd_c;
scl_oen <= #1 1'b1; // set SCL high
sda_oen <= #1 1'b1; // keep SDA tri-stated
sda_chk <= #1 1'b0; // don't check SDA output
end
rd_c:
begin
c_state <= #1 rd_d;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b1; // keep SDA tri-stated
sda_chk <= #1 1'b0; // don't check SDA output
end
rd_d:
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b1;
scl_oen <= #1 1'b0; // set SCL low
sda_oen <= #1 1'b1; // keep SDA tri-stated
sda_chk <= #1 1'b0; // don't check SDA output
end
// write
wr_a:
begin
c_state <= #1 wr_b;
scl_oen <= #1 1'b0; // keep SCL low
sda_oen <= #1 din; // set SDA
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
end
wr_b:
begin
c_state <= #1 wr_c;
scl_oen <= #1 1'b1; // set SCL high
sda_oen <= #1 din; // keep SDA
sda_chk <= #1 1'b1; // check SDA output
end
wr_c:
begin
c_state <= #1 wr_d;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 din;
sda_chk <= #1 1'b1; // check SDA output
end
wr_d:
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b1;
scl_oen <= #1 1'b0; // set SCL low
sda_oen <= #1 din;
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
end
// read (last SPI bit)
spi_rd_a:
begin
c_state <= #1 spi_rd_b;
scl_oen <= #1 1'b0; // set SCL low
sda_oen <= #1 1'b1; // tri-state SDA
sda_chk <= #1 1'b0; // don't check SDA output
spi_rden <= #1 1'b0; //clear SPI read enable
end
spi_rd_b:
begin
c_state <= #1 spi_rd_c;
scl_oen <= #1 1'b0; // keep SCL low
sda_oen <= #1 1'b1; // keep SDA tri-stated
sda_chk <= #1 1'b0; // don't check SDA output
spi_rden <= #1 1'b1; //set SPI read enable
end
spi_rd_c:
begin
c_state <= #1 spi_rd_d;
scl_oen <= #1 1'b1; // set SCL high
sda_oen <= #1 1'b1; // keep SDA tri-stated
sda_chk <= #1 1'b0; // don't check SDA output
spi_rden <= #1 1'b1; //set SPI read enable
end
spi_rd_d:
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b1;
scl_oen <= #1 1'b1; // tri-state SCL
sda_oen <= #1 1'b1; // keep SDA tri-stated
sda_chk <= #1 1'b0; // don't check SDA output
spi_rden <= #1 1'b0; //clear SPI read enable
end
// write (last SPI bit)
spi_wr_a:
begin
c_state <= #1 spi_wr_b;
scl_oen <= #1 1'b0; // set SCL low
sda_oen <= #1 dedicated_spi ? din : 1'b1; // keep SDA tri-stated by default to avoid generating I2C start condition
sda_chk <= #1 1'b0; // don't check SDA output
end
spi_wr_b:
begin
c_state <= #1 spi_wr_c;
scl_oen <= #1 1'b0; // keep SCL low
sda_oen <= #1 din; // set/keep SDA
sda_chk <= #1 1'b0; // don't check SDA output
end
spi_wr_c:
begin
c_state <= #1 spi_wr_d;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 din; // keep SDA
sda_chk <= #1 1'b0; // don't check SDA output
end
spi_wr_d:
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b1;
scl_oen <= #1 1'b1; // tri-state SCL
sda_oen <= #1 dedicated_spi ? din : 1'b1; // tri-state SDA by default to release bus for I2C mode
sda_chk <= #1 1'b0; // don't check SDA output
end
default:
c_state <= #1 idle;
endcase
end
// assign scl and sda output (always gnd)
assign scl_o = 1'b0;
assign sda_o = 1'b0;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:09:23 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_counter_d_W4_60 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FSM_Add_Subtract_59 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W11 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W55_1_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W55_1_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W64_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W64_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_5 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_10 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_CORDIC_Arch2_W64_EW11_SW52_SWR55_EWR6_1 ( CLK, EN,
ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module CORDIC_Arch2_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, r_mode,
ready_cordic, overflow_flag, underflow_flag, data_output );
input [63:0] data_in;
input [1:0] shift_region_flag;
input [1:0] r_mode;
output [63:0] data_output;
input clk, rst, beg_fsm_cordic, ack_cordic, operation;
output ready_cordic, overflow_flag, underflow_flag;
wire enab_cont_iter, load_cont_iter, load_cont_var, enab_d_ff2_RB2,
enab_d_ff4_Xn, enab_d_ff4_Yn, enab_d_ff4_Zn, enab_d_ff5_data_out,
enab_dff_5, sel_mux_1_reg, d_ff3_sign_out, data_output2_63_,
cordic_FSM_state_next_1_, cont_iter_net3719283,
add_subt_module_sign_final_result, add_subt_module_FSM_selector_D,
add_subt_module_FSM_Final_Result_load, add_subt_module_FSM_LZA_load,
add_subt_module_FSM_Add_Subt_Sgf_load,
add_subt_module_FSM_barrel_shifter_load,
add_subt_module_FSM_exp_operation_load_diff,
add_subt_module_add_overflow_flag, add_subt_module_FSM_selector_C,
d_ff5_data_out_net3719139, reg_Z0_net3719139,
reg_val_muxZ_2stage_net3719139, reg_shift_y_net3719139,
d_ff4_Xn_net3719139, d_ff4_Yn_net3719139, d_ff4_Zn_net3719139,
d_ff5_net3719139, add_subt_module_FS_Module_net3719247,
add_subt_module_final_result_ieee_Module_Sign_S_mux,
add_subt_module_YRegister_net3719157,
add_subt_module_Exp_Operation_Module_exp_result_net3719211,
add_subt_module_Leading_Zero_Detector_Module_Output_Reg_net3719175,
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157,
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193,
add_subt_module_Oper_Start_in_module_MRegister_net3719229,
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193, n134,
n1135, n1137, n1138, n1139, n1140, n1145, n1146, n1148, n1149, n1150,
n1151, n1152, n1155, n1156, n1157, n1159, n1160, n1161, n1162, n1164,
n1165, n1166, n1167, n1169, n1170, n1171, n1172, n1173, n1174, n1176,
n1179, n1180, n1181, n1182, n1183, n1184, n1187, n1188, n1189, n1190,
n1192, n1194, n1197, n1198, n1199, n1200, n1201, n1202, n1204, n1206,
n1207, n1208, n1211, n1212, n1214, n1216, n1218, n1219, n1221, n1222,
n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232,
n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242,
n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252,
n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262,
n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272,
n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282,
n1283, n1284, n1285, n1286, n1288, DP_OP_92J185_122_9081_n26,
DP_OP_92J185_122_9081_n25, DP_OP_92J185_122_9081_n24,
DP_OP_92J185_122_9081_n23, DP_OP_92J185_122_9081_n22,
DP_OP_92J185_122_9081_n21, DP_OP_92J185_122_9081_n20,
DP_OP_92J185_122_9081_n19, DP_OP_92J185_122_9081_n18,
DP_OP_92J185_122_9081_n17, DP_OP_92J185_122_9081_n16,
DP_OP_92J185_122_9081_n11, DP_OP_92J185_122_9081_n10,
DP_OP_92J185_122_9081_n9, DP_OP_92J185_122_9081_n8,
DP_OP_92J185_122_9081_n7, DP_OP_92J185_122_9081_n6,
DP_OP_92J185_122_9081_n5, DP_OP_92J185_122_9081_n4,
DP_OP_92J185_122_9081_n3, DP_OP_92J185_122_9081_n2,
DP_OP_92J185_122_9081_n1, intadd_435_CI, intadd_435_n3, intadd_435_n2,
intadd_435_n1, intadd_436_CI, intadd_436_n3, intadd_436_n2,
intadd_436_n1, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304,
n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314,
n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324,
n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334,
n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344,
n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354,
n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364,
n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374,
n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384,
n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394,
n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404,
n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414,
n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424,
n1425, n1426, n1427, n1428, n1429, n1430, n1432, n1433, n1434, n1435,
n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445,
n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455,
n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465,
n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475,
n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625,
n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635,
n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645,
n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655,
n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665,
n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675,
n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685,
n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695,
n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705,
n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715,
n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725,
n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735,
n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745,
n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755,
n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765,
n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775,
n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785,
n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795,
n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805,
n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815,
n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825,
n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835,
n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845,
n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1855, n1857,
n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867,
n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877,
n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887,
n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897,
n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908,
n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918,
n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928,
n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938,
n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948,
n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958,
n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968,
n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978,
n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988,
n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998,
n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008,
n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018,
n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028,
n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038,
n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048,
n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058,
n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068,
n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078,
n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088,
n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098,
n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108,
n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118,
n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128,
n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138,
n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148,
n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158,
n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168,
n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178,
n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188,
n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198,
n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208,
n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218,
n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228,
n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238,
n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248,
n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258,
n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268,
n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278,
n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288,
n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298,
n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308,
n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318,
n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328,
n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338,
n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348,
n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358,
n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368,
n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378,
n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388,
n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398,
n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408,
n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418,
n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428,
n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438,
n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448,
n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458,
n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468,
n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478,
n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2489,
n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499,
n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509,
n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519,
n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529,
n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539,
n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549,
n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559,
n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569,
n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579,
n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589,
n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599,
n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609,
n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619,
n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629,
n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639,
n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649,
n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659,
n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669,
n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679,
n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689,
n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699,
n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709,
n2710, n2711, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720,
n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730,
n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740,
n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750,
n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760,
n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770,
n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780,
n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790,
n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800,
n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810,
n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820,
n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830,
n2832, n2833, n2834, n2835, n2836, n2837, n2840, n2841, n2843, n2844,
n2845, n2846, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855,
n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865,
n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875,
n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885,
n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895,
n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905,
n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915,
n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925,
n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935,
n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945,
n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955,
n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965,
n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975,
n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985,
n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995,
n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005,
n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015,
n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025,
n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035,
n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045,
n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055,
n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065,
n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075,
n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084, n3085,
n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094, n3095,
n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104, n3105,
n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115,
n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124, n3125,
n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134, n3135,
n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144, n3145,
n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154, n3155,
n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164, n3165,
n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174, n3175,
n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184, n3185,
n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194, n3195,
n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205,
n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214, n3215,
n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224, n3225,
n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234, n3235,
n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244, n3245,
n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254, n3255,
n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264, n3265,
n3266, n3267, n3269, n3270, n3271, n3272, n3273, n3274, n3275, n3276,
n3277;
wire [1:0] d_ff1_shift_region_flag_out;
wire [1:0] cont_var_out;
wire [3:1] cont_iter_out;
wire [63:0] d_ff1_Z;
wire [63:0] d_ff_Xn;
wire [63:0] first_mux_X;
wire [63:0] d_ff_Yn;
wire [63:0] first_mux_Y;
wire [63:0] d_ff_Zn;
wire [63:0] first_mux_Z;
wire [63:0] d_ff2_X;
wire [63:0] d_ff2_Y;
wire [63:0] d_ff2_Z;
wire [10:0] sh_exp_x;
wire [10:0] sh_exp_y;
wire [56:0] data_out_LUT;
wire [63:0] d_ff3_sh_x_out;
wire [63:0] d_ff3_sh_y_out;
wire [56:0] d_ff3_LUT_out;
wire [1:0] sel_mux_2_reg;
wire [62:13] result_add_subt;
wire [63:0] mux_sal;
wire [63:0] sign_inv_out;
wire [3:0] cordic_FSM_state_reg;
wire [54:1] add_subt_module_Sgf_normalized_result;
wire [54:1] add_subt_module_Add_Subt_result;
wire [5:0] add_subt_module_LZA_output;
wire [10:0] add_subt_module_S_Oper_A_exp;
wire [10:0] add_subt_module_exp_oper_result;
wire [62:0] add_subt_module_DmP;
wire [62:0] add_subt_module_DMP;
wire [62:0] add_subt_module_intDY;
wire [63:0] add_subt_module_intDX;
wire [1:0] add_subt_module_FSM_selector_B;
wire [3:0] add_subt_module_FS_Module_state_next;
wire [3:0] add_subt_module_FS_Module_state_reg;
wire [62:0] add_subt_module_Oper_Start_in_module_intm;
wire [62:0] add_subt_module_Oper_Start_in_module_intM;
wire [10:0] add_subt_module_Exp_Operation_Module_Data_S;
wire [54:0] add_subt_module_Barrel_Shifter_module_Data_Reg;
wire [55:0] add_subt_module_Add_Subt_Sgf_module_S_to_D;
wire [5:0] add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg;
wire [51:0] add_subt_module_final_result_ieee_Module_Sgf_S_mux;
wire [10:0] add_subt_module_final_result_ieee_Module_Exp_S_mux;
wire [102:0] add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array;
SNPS_CLOCK_GATE_HIGH_counter_d_W4_60 cont_iter_clk_gate_count_reg ( .CLK(clk), .EN(enab_cont_iter), .ENCLK(cont_iter_net3719283), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_0 d_ff5_data_out_clk_gate_Q_reg ( .CLK(
clk), .EN(enab_d_ff5_data_out), .ENCLK(d_ff5_data_out_net3719139),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_10 reg_Z0_clk_gate_Q_reg ( .CLK(clk),
.EN(load_cont_iter), .ENCLK(reg_Z0_net3719139), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_7 reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(enab_d_ff2_RB2), .ENCLK(reg_val_muxZ_2stage_net3719139),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_5 reg_shift_y_clk_gate_Q_reg ( .CLK(clk),
.EN(load_cont_var), .ENCLK(reg_shift_y_net3719139), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_4 d_ff4_Xn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Xn), .ENCLK(d_ff4_Xn_net3719139), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_3 d_ff4_Yn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Yn), .ENCLK(d_ff4_Yn_net3719139), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_2 d_ff4_Zn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Zn), .ENCLK(d_ff4_Zn_net3719139), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_1 d_ff5_clk_gate_Q_reg ( .CLK(clk), .EN(
enab_dff_5), .ENCLK(d_ff5_net3719139), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_FSM_Add_Subtract_59 add_subt_module_FS_Module_clk_gate_state_reg_reg (
.CLK(clk), .EN(n1159), .ENCLK(add_subt_module_FS_Module_net3719247),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W64_0_1 add_subt_module_YRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n1288), .ENCLK(add_subt_module_YRegister_net3719157),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W11 add_subt_module_Exp_Operation_Module_exp_result_clk_gate_Q_reg (
.CLK(clk), .EN(add_subt_module_FSM_exp_operation_load_diff), .ENCLK(
add_subt_module_Exp_Operation_Module_exp_result_net3719211), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W6 add_subt_module_Leading_Zero_Detector_Module_Output_Reg_clk_gate_Q_reg (
.CLK(clk), .EN(add_subt_module_FSM_LZA_load), .ENCLK(
add_subt_module_Leading_Zero_Detector_Module_Output_Reg_net3719175),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W64_0_0 add_subt_module_final_result_ieee_Module_Final_Result_IEEE_clk_gate_Q_reg (
.CLK(clk), .EN(add_subt_module_FSM_Final_Result_load), .ENCLK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W55_1_0 add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_clk_gate_Q_reg (
.CLK(clk), .EN(add_subt_module_FSM_Add_Subt_Sgf_load), .ENCLK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .TE(
1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_1 add_subt_module_Oper_Start_in_module_MRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n3245), .ENCLK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W55_1_1 add_subt_module_Barrel_Shifter_module_Output_Reg_clk_gate_Q_reg (
.CLK(clk), .EN(add_subt_module_FSM_barrel_shifter_load), .ENCLK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .TE(1'b0) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[32]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3165), .QN(n1333) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Zn_net3719139), .RN(n3195), .Q(d_ff_Zn[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(first_mux_Z[30]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3224), .Q(d_ff2_Z[30]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(
add_subt_module_Oper_Start_in_module_intm[30]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3149),
.Q(add_subt_module_DmP[30]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[15]),
.CK(clk), .RN(n3149), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[70]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[45]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3149), .QN(n1320) );
DFFRXLTS d_ff4_Zn_Q_reg_45_ ( .D(n1399), .CK(d_ff4_Zn_net3719139), .RN(n3215), .Q(d_ff_Zn[45]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_45_ ( .D(first_mux_Z[45]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3237), .Q(d_ff2_Z[45]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_45_ ( .D(
add_subt_module_Oper_Start_in_module_intm[45]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3149),
.Q(add_subt_module_DmP[45]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[0]),
.CK(clk), .RN(n3149), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[55]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[0]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3180), .QN(n1321) );
DFFRXLTS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_10_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[10]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3719211), .RN(n3178), .Q(add_subt_module_exp_oper_result[10]) );
DFFRXLTS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_9_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[9]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3719211), .RN(n3170), .Q(add_subt_module_exp_oper_result[9]) );
DFFRXLTS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_8_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[8]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3719211), .RN(n3154), .Q(add_subt_module_exp_oper_result[8]) );
DFFRXLTS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[7]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3719211), .RN(n3178), .Q(add_subt_module_exp_oper_result[7]) );
DFFRXLTS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[6]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3719211), .RN(n3169), .Q(add_subt_module_exp_oper_result[6]) );
DFFRXLTS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[0]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3719211), .RN(n3162), .Q(add_subt_module_exp_oper_result[0]), .QN(n3003) );
DFFRXLTS d_ff4_Zn_Q_reg_51_ ( .D(result_add_subt[51]), .CK(
d_ff4_Zn_net3719139), .RN(n3243), .Q(d_ff_Zn[51]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_51_ ( .D(first_mux_Z[51]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3209), .Q(d_ff2_Z[51]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_51_ ( .D(
add_subt_module_Oper_Start_in_module_intm[51]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3150),
.Q(add_subt_module_DmP[51]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[46]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3150), .QN(n1368) );
DFFRXLTS d_ff4_Zn_Q_reg_46_ ( .D(n1398), .CK(d_ff4_Zn_net3719139), .RN(n3204), .Q(d_ff_Zn[46]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_46_ ( .D(first_mux_Z[46]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3222), .Q(d_ff2_Z[46]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_46_ ( .D(
add_subt_module_Oper_Start_in_module_intm[46]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3150),
.Q(add_subt_module_DmP[46]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[5]),
.CK(clk), .RN(n3150), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[60]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[47]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3150), .QN(n1367) );
DFFRXLTS d_ff4_Zn_Q_reg_47_ ( .D(n1397), .CK(d_ff4_Zn_net3719139), .RN(n3227), .Q(d_ff_Zn[47]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_47_ ( .D(first_mux_Z[47]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3229), .Q(d_ff2_Z[47]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_47_ ( .D(
add_subt_module_Oper_Start_in_module_intm[47]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3150),
.Q(add_subt_module_DmP[47]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[2]),
.CK(clk), .RN(n3150), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[57]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[50]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3150), .QN(n1366) );
DFFRXLTS d_ff4_Zn_Q_reg_50_ ( .D(n1396), .CK(d_ff4_Zn_net3719139), .RN(n3227), .Q(d_ff_Zn[50]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_50_ ( .D(first_mux_Z[50]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3226), .Q(d_ff2_Z[50]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_50_ ( .D(
add_subt_module_Oper_Start_in_module_intm[50]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3151),
.Q(add_subt_module_DmP[50]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[37]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3166), .QN(n1340) );
DFFRXLTS d_ff4_Zn_Q_reg_35_ ( .D(result_add_subt[35]), .CK(
d_ff4_Zn_net3719139), .RN(n3194), .Q(d_ff_Zn[35]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_35_ ( .D(first_mux_Z[35]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3238), .Q(d_ff2_Z[35]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_35_ ( .D(
add_subt_module_Oper_Start_in_module_intm[35]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3151),
.Q(add_subt_module_DmP[35]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[10]),
.CK(clk), .RN(n3151), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[65]) );
DFFRXLTS d_ff4_Zn_Q_reg_42_ ( .D(result_add_subt[42]), .CK(
d_ff4_Zn_net3719139), .RN(n3238), .Q(d_ff_Zn[42]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_42_ ( .D(first_mux_Z[42]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3234), .Q(d_ff2_Z[42]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_42_ ( .D(
add_subt_module_Oper_Start_in_module_intm[42]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3151),
.Q(add_subt_module_DmP[42]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[3]),
.CK(clk), .RN(n3151), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[58]) );
DFFRXLTS d_ff4_Zn_Q_reg_49_ ( .D(result_add_subt[49]), .CK(
d_ff4_Zn_net3719139), .RN(n3238), .Q(d_ff_Zn[49]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_49_ ( .D(first_mux_Z[49]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3194), .Q(d_ff2_Z[49]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_49_ ( .D(
add_subt_module_Oper_Start_in_module_intm[49]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3153),
.Q(add_subt_module_DmP[49]) );
DFFRXLTS d_ff4_Zn_Q_reg_48_ ( .D(result_add_subt[48]), .CK(
d_ff4_Zn_net3719139), .RN(n3239), .Q(d_ff_Zn[48]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_48_ ( .D(first_mux_Z[48]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3239), .Q(d_ff2_Z[48]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_48_ ( .D(
add_subt_module_Oper_Start_in_module_intm[48]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3171),
.Q(add_subt_module_DmP[48]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[35]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3166), .QN(n1337) );
DFFRXLTS d_ff4_Zn_Q_reg_33_ ( .D(result_add_subt[33]), .CK(
d_ff4_Zn_net3719139), .RN(n3219), .Q(d_ff_Zn[33]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_33_ ( .D(first_mux_Z[33]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3219), .Q(d_ff2_Z[33]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_33_ ( .D(
add_subt_module_Oper_Start_in_module_intm[33]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3180),
.Q(add_subt_module_DmP[33]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[12]),
.CK(clk), .RN(n3169), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[67]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[40]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3167), .QN(n1365) );
DFFRXLTS d_ff4_Zn_Q_reg_40_ ( .D(n1395), .CK(d_ff4_Zn_net3719139), .RN(n3194), .Q(d_ff_Zn[40]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_40_ ( .D(first_mux_Z[40]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3194), .Q(d_ff2_Z[40]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_40_ ( .D(
add_subt_module_Oper_Start_in_module_intm[40]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3185),
.Q(add_subt_module_DmP[40]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[9]),
.CK(clk), .RN(n3154), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[64]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[43]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3185), .QN(n1319) );
DFFRXLTS d_ff4_Zn_Q_reg_43_ ( .D(n1394), .CK(d_ff4_Zn_net3719139), .RN(n3221), .Q(d_ff_Zn[43]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_43_ ( .D(first_mux_Z[43]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3240), .Q(d_ff2_Z[43]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_43_ ( .D(
add_subt_module_Oper_Start_in_module_intm[43]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3185),
.Q(add_subt_module_DmP[43]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[8]),
.CK(clk), .RN(n3161), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[63]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[44]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3246), .QN(n1318) );
DFFRXLTS d_ff4_Zn_Q_reg_44_ ( .D(n1393), .CK(d_ff4_Zn_net3719139), .RN(n3226), .Q(d_ff_Zn[44]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_44_ ( .D(first_mux_Z[44]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3194), .Q(d_ff2_Z[44]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_44_ ( .D(
add_subt_module_Oper_Start_in_module_intm[44]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3246),
.Q(add_subt_module_DmP[44]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[39]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3167), .QN(n1339) );
DFFRXLTS d_ff4_Zn_Q_reg_37_ ( .D(result_add_subt[37]), .CK(
d_ff4_Zn_net3719139), .RN(n3241), .Q(d_ff_Zn[37]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_37_ ( .D(first_mux_Z[37]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3242), .Q(d_ff2_Z[37]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_37_ ( .D(
add_subt_module_Oper_Start_in_module_intm[37]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3152),
.Q(add_subt_module_DmP[37]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[13]),
.CK(clk), .RN(n3152), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[68]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[41]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3167), .QN(n1341) );
DFFRXLTS d_ff4_Zn_Q_reg_39_ ( .D(result_add_subt[39]), .CK(
d_ff4_Zn_net3719139), .RN(n3241), .Q(d_ff_Zn[39]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_39_ ( .D(first_mux_Z[39]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3205), .Q(d_ff2_Z[39]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_39_ ( .D(
add_subt_module_Oper_Start_in_module_intm[39]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3152),
.Q(add_subt_module_DmP[39]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[11]),
.CK(clk), .RN(n3152), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[66]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[41]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3152), .QN(n1364) );
DFFRXLTS d_ff4_Zn_Q_reg_41_ ( .D(n1392), .CK(d_ff4_Zn_net3719139), .RN(n3240), .Q(d_ff_Zn[41]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_41_ ( .D(first_mux_Z[41]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3201), .Q(d_ff2_Z[41]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_41_ ( .D(
add_subt_module_Oper_Start_in_module_intm[41]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3152),
.Q(add_subt_module_DmP[41]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_36_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]),
.CK(clk), .RN(n3152), .QN(n1353) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[34]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3166), .QN(n1335) );
DFFRXLTS d_ff4_Zn_Q_reg_32_ ( .D(result_add_subt[32]), .CK(
d_ff4_Zn_net3719139), .RN(n3241), .Q(d_ff_Zn[32]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_32_ ( .D(first_mux_Z[32]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3227), .Q(d_ff2_Z[32]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_32_ ( .D(
add_subt_module_Oper_Start_in_module_intm[32]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3185),
.Q(add_subt_module_DmP[32]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[17]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3164), .QN(n1325) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Zn_net3719139), .RN(n3218), .Q(d_ff_Zn[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(first_mux_Z[15]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3242), .Q(d_ff2_Z[15]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(
add_subt_module_Oper_Start_in_module_intm[15]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3153),
.Q(add_subt_module_DmP[15]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[40]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3167), .QN(n1342) );
DFFRXLTS d_ff4_Zn_Q_reg_38_ ( .D(result_add_subt[38]), .CK(
d_ff4_Zn_net3719139), .RN(n3243), .Q(d_ff_Zn[38]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_38_ ( .D(first_mux_Z[38]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3236), .Q(d_ff2_Z[38]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_38_ ( .D(
add_subt_module_Oper_Start_in_module_intm[38]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3185),
.Q(add_subt_module_DmP[38]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_33_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[33]),
.CK(clk), .RN(n3153), .QN(n1346) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[33]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3166), .QN(n1334) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Zn_net3719139), .RN(n3241), .Q(d_ff_Zn[31]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_31_ ( .D(first_mux_Z[31]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3231), .Q(d_ff2_Z[31]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_31_ ( .D(
add_subt_module_Oper_Start_in_module_intm[31]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3167),
.Q(add_subt_module_DmP[31]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[36]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3166), .QN(n1336) );
DFFRXLTS d_ff4_Zn_Q_reg_34_ ( .D(result_add_subt[34]), .CK(
d_ff4_Zn_net3719139), .RN(n3198), .Q(d_ff_Zn[34]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_34_ ( .D(first_mux_Z[34]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3241), .Q(d_ff2_Z[34]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_34_ ( .D(
add_subt_module_Oper_Start_in_module_intm[34]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3179),
.Q(add_subt_module_DmP[34]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[21]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3150), .QN(n1302) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Zn_net3719139), .RN(n3243), .Q(d_ff_Zn[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(first_mux_Z[19]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3215), .Q(d_ff2_Z[19]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(
add_subt_module_Oper_Start_in_module_intm[19]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3183),
.Q(add_subt_module_DmP[19]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[28]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3165), .QN(n1329) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Zn_net3719139), .RN(n3222), .Q(d_ff_Zn[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(first_mux_Z[26]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3206), .Q(d_ff2_Z[26]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(
add_subt_module_Oper_Start_in_module_intm[26]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3179),
.Q(add_subt_module_DmP[26]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[19]),
.CK(clk), .RN(n3181), .QN(n1311) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[19]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3164), .QN(n1324) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Zn_net3719139), .RN(n3240), .Q(d_ff_Zn[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(first_mux_Z[17]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3227), .Q(d_ff2_Z[17]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(
add_subt_module_Oper_Start_in_module_intm[17]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3175),
.Q(add_subt_module_DmP[17]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[26]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3171), .QN(n1307) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Zn_net3719139), .RN(n3229), .Q(d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(first_mux_Z[24]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3240), .Q(d_ff2_Z[24]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(
add_subt_module_Oper_Start_in_module_intm[24]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3173),
.Q(add_subt_module_DmP[24]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[29]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3165), .QN(n1330) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Zn_net3719139), .RN(n3223), .Q(d_ff_Zn[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(first_mux_Z[27]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3206), .Q(d_ff2_Z[27]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(
add_subt_module_Oper_Start_in_module_intm[27]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3159),
.Q(add_subt_module_DmP[27]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[38]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3166), .QN(n1338) );
DFFRXLTS d_ff4_Zn_Q_reg_36_ ( .D(result_add_subt[36]), .CK(
d_ff4_Zn_net3719139), .RN(n3205), .Q(d_ff_Zn[36]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_36_ ( .D(first_mux_Z[36]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3227), .Q(d_ff2_Z[36]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_36_ ( .D(
add_subt_module_Oper_Start_in_module_intm[36]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3182),
.Q(add_subt_module_DmP[36]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Zn_net3719139), .RN(n3217), .Q(d_ff_Zn[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(first_mux_Z[13]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3227), .Q(d_ff2_Z[13]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(
add_subt_module_Oper_Start_in_module_intm[13]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3185),
.Q(add_subt_module_DmP[13]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[22]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3154), .QN(n1303) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Zn_net3719139), .RN(n3210), .Q(d_ff_Zn[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(first_mux_Z[20]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3243), .Q(d_ff2_Z[20]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(
add_subt_module_Oper_Start_in_module_intm[20]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3175),
.Q(add_subt_module_DmP[20]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(
n3277), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3165), .QN(n1327) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Zn_net3719139), .RN(n3243), .Q(d_ff_Zn[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(first_mux_Z[25]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3198), .Q(d_ff2_Z[25]) );
DFFRXLTS add_subt_module_FS_Module_state_reg_reg_0_ ( .D(
add_subt_module_FS_Module_state_next[0]), .CK(
add_subt_module_FS_Module_net3719247), .RN(n3174), .Q(
add_subt_module_FS_Module_state_reg[0]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[2]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3181), .QN(n1363) );
DFFRXLTS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[8]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3171), .QN(n1344) );
DFFRXLTS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[4]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3171), .QN(n1349) );
DFFRXLTS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[0]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3154), .QN(n1345) );
DFFRXLTS reg_operation_Q_reg_0_ ( .D(operation), .CK(reg_Z0_net3719139),
.RN(n3221), .QN(n1348) );
DFFRXLTS reg_LUT_Q_reg_56_ ( .D(data_out_LUT[56]), .CK(
reg_shift_y_net3719139), .RN(n3211), .Q(d_ff3_LUT_out[56]) );
DFFRXLTS reg_LUT_Q_reg_55_ ( .D(data_out_LUT[55]), .CK(
reg_shift_y_net3719139), .RN(n3241), .Q(d_ff3_LUT_out[55]) );
DFFRXLTS reg_LUT_Q_reg_54_ ( .D(data_out_LUT[54]), .CK(
reg_shift_y_net3719139), .RN(n3226), .Q(d_ff3_LUT_out[54]) );
DFFRXLTS reg_LUT_Q_reg_53_ ( .D(data_out_LUT[53]), .CK(
reg_shift_y_net3719139), .RN(n3226), .Q(d_ff3_LUT_out[53]) );
DFFRXLTS reg_LUT_Q_reg_52_ ( .D(n3146), .CK(reg_shift_y_net3719139), .RN(
n3226), .Q(d_ff3_LUT_out[52]) );
DFFRXLTS reg_LUT_Q_reg_50_ ( .D(data_out_LUT[50]), .CK(
reg_shift_y_net3719139), .RN(n3226), .Q(d_ff3_LUT_out[50]) );
DFFRXLTS reg_LUT_Q_reg_45_ ( .D(data_out_LUT[45]), .CK(
reg_shift_y_net3719139), .RN(n3226), .Q(d_ff3_LUT_out[45]) );
DFFRXLTS reg_LUT_Q_reg_44_ ( .D(data_out_LUT[49]), .CK(
reg_shift_y_net3719139), .RN(n3226), .Q(d_ff3_LUT_out[44]) );
DFFRXLTS reg_LUT_Q_reg_42_ ( .D(data_out_LUT[47]), .CK(
reg_shift_y_net3719139), .RN(n3226), .Q(d_ff3_LUT_out[42]) );
DFFRXLTS reg_LUT_Q_reg_41_ ( .D(data_out_LUT[41]), .CK(
reg_shift_y_net3719139), .RN(n3226), .Q(d_ff3_LUT_out[41]) );
DFFRXLTS reg_LUT_Q_reg_39_ ( .D(data_out_LUT[39]), .CK(
reg_shift_y_net3719139), .RN(n3226), .Q(d_ff3_LUT_out[39]) );
DFFRXLTS reg_LUT_Q_reg_37_ ( .D(data_out_LUT[37]), .CK(
reg_shift_y_net3719139), .RN(n3226), .Q(d_ff3_LUT_out[37]) );
DFFRXLTS reg_LUT_Q_reg_35_ ( .D(data_out_LUT[35]), .CK(
reg_shift_y_net3719139), .RN(n3226), .Q(d_ff3_LUT_out[35]) );
DFFRXLTS reg_LUT_Q_reg_34_ ( .D(data_out_LUT[43]), .CK(
reg_shift_y_net3719139), .RN(n3226), .Q(d_ff3_LUT_out[34]) );
DFFRXLTS reg_LUT_Q_reg_33_ ( .D(data_out_LUT[33]), .CK(
reg_shift_y_net3719139), .RN(n3225), .Q(d_ff3_LUT_out[33]) );
DFFRXLTS reg_LUT_Q_reg_32_ ( .D(data_out_LUT[38]), .CK(
reg_shift_y_net3719139), .RN(n3225), .Q(d_ff3_LUT_out[32]) );
DFFRXLTS reg_LUT_Q_reg_31_ ( .D(data_out_LUT[31]), .CK(
reg_shift_y_net3719139), .RN(n3225), .Q(d_ff3_LUT_out[31]) );
DFFRXLTS reg_LUT_Q_reg_29_ ( .D(data_out_LUT[29]), .CK(
reg_shift_y_net3719139), .RN(n3199), .Q(d_ff3_LUT_out[29]) );
DFFRXLTS reg_LUT_Q_reg_28_ ( .D(data_out_LUT[40]), .CK(
reg_shift_y_net3719139), .RN(n3225), .Q(d_ff3_LUT_out[28]) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(data_out_LUT[27]), .CK(
reg_shift_y_net3719139), .RN(n3199), .Q(d_ff3_LUT_out[27]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(data_out_LUT[26]), .CK(
reg_shift_y_net3719139), .RN(n3225), .Q(d_ff3_LUT_out[26]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(data_out_LUT[25]), .CK(
reg_shift_y_net3719139), .RN(n3199), .Q(d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(data_out_LUT[24]), .CK(
reg_shift_y_net3719139), .RN(n3225), .Q(d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(data_out_LUT[23]), .CK(
reg_shift_y_net3719139), .RN(n3199), .Q(d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(data_out_LUT[22]), .CK(
reg_shift_y_net3719139), .RN(n3225), .Q(d_ff3_LUT_out[22]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(data_out_LUT[21]), .CK(
reg_shift_y_net3719139), .RN(n3199), .Q(d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(data_out_LUT[20]), .CK(
reg_shift_y_net3719139), .RN(n3224), .Q(d_ff3_LUT_out[20]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(data_out_LUT[19]), .CK(
reg_shift_y_net3719139), .RN(n3224), .Q(d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_18_ ( .D(data_out_LUT[18]), .CK(
reg_shift_y_net3719139), .RN(n3212), .Q(d_ff3_LUT_out[18]) );
DFFRXLTS reg_LUT_Q_reg_17_ ( .D(data_out_LUT[17]), .CK(
reg_shift_y_net3719139), .RN(n3224), .Q(d_ff3_LUT_out[17]) );
DFFRXLTS reg_LUT_Q_reg_16_ ( .D(data_out_LUT[16]), .CK(
reg_shift_y_net3719139), .RN(n3212), .Q(d_ff3_LUT_out[16]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(data_out_LUT[15]), .CK(
reg_shift_y_net3719139), .RN(n3224), .Q(d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_14_ ( .D(data_out_LUT[14]), .CK(
reg_shift_y_net3719139), .RN(n3212), .Q(d_ff3_LUT_out[14]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(data_out_LUT[13]), .CK(
reg_shift_y_net3719139), .RN(n3224), .Q(d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(data_out_LUT[12]), .CK(
reg_shift_y_net3719139), .RN(n3212), .Q(d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_11_ ( .D(data_out_LUT[11]), .CK(
reg_shift_y_net3719139), .RN(n3224), .Q(d_ff3_LUT_out[11]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(data_out_LUT[10]), .CK(
reg_shift_y_net3719139), .RN(n3212), .Q(d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(data_out_LUT[9]), .CK(reg_shift_y_net3719139),
.RN(n3223), .Q(d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(data_out_LUT[8]), .CK(reg_shift_y_net3719139),
.RN(n3223), .Q(d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(data_out_LUT[7]), .CK(reg_shift_y_net3719139),
.RN(n3223), .Q(d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(data_out_LUT[6]), .CK(reg_shift_y_net3719139),
.RN(n3208), .Q(d_ff3_LUT_out[6]) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(data_out_LUT[5]), .CK(reg_shift_y_net3719139),
.RN(n3223), .Q(d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(data_out_LUT[30]), .CK(reg_shift_y_net3719139), .RN(n3208), .Q(d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(data_out_LUT[3]), .CK(reg_shift_y_net3719139),
.RN(n3223), .Q(d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(data_out_LUT[2]), .CK(reg_shift_y_net3719139),
.RN(n3208), .Q(d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(data_out_LUT[1]), .CK(reg_shift_y_net3719139),
.RN(n3223), .Q(d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(data_out_LUT[0]), .CK(reg_shift_y_net3719139),
.RN(n3208), .Q(d_ff3_LUT_out[0]) );
DFFRXLTS reg_Z0_Q_reg_62_ ( .D(data_in[62]), .CK(reg_Z0_net3719139), .RN(
n3223), .Q(d_ff1_Z[62]) );
DFFRXLTS reg_Z0_Q_reg_61_ ( .D(data_in[61]), .CK(reg_Z0_net3719139), .RN(
n3208), .Q(d_ff1_Z[61]) );
DFFRXLTS reg_Z0_Q_reg_60_ ( .D(data_in[60]), .CK(reg_Z0_net3719139), .RN(
n3222), .Q(d_ff1_Z[60]) );
DFFRXLTS reg_Z0_Q_reg_59_ ( .D(data_in[59]), .CK(reg_Z0_net3719139), .RN(
n3231), .Q(d_ff1_Z[59]) );
DFFRXLTS reg_Z0_Q_reg_58_ ( .D(data_in[58]), .CK(reg_Z0_net3719139), .RN(
n3222), .Q(d_ff1_Z[58]) );
DFFRXLTS reg_Z0_Q_reg_57_ ( .D(data_in[57]), .CK(reg_Z0_net3719139), .RN(
n3231), .Q(d_ff1_Z[57]) );
DFFRXLTS reg_Z0_Q_reg_56_ ( .D(data_in[56]), .CK(reg_Z0_net3719139), .RN(
n3222), .Q(d_ff1_Z[56]) );
DFFRXLTS reg_Z0_Q_reg_55_ ( .D(data_in[55]), .CK(reg_Z0_net3719139), .RN(
n3231), .Q(d_ff1_Z[55]) );
DFFRXLTS reg_Z0_Q_reg_54_ ( .D(data_in[54]), .CK(reg_Z0_net3719139), .RN(
n3222), .Q(d_ff1_Z[54]) );
DFFRXLTS reg_Z0_Q_reg_53_ ( .D(data_in[53]), .CK(reg_Z0_net3719139), .RN(
n3231), .Q(d_ff1_Z[53]) );
DFFRXLTS reg_Z0_Q_reg_52_ ( .D(data_in[52]), .CK(reg_Z0_net3719139), .RN(
n3222), .Q(d_ff1_Z[52]) );
DFFRXLTS reg_Z0_Q_reg_51_ ( .D(data_in[51]), .CK(reg_Z0_net3719139), .RN(
n3231), .Q(d_ff1_Z[51]) );
DFFRXLTS reg_Z0_Q_reg_50_ ( .D(data_in[50]), .CK(reg_Z0_net3719139), .RN(
n3222), .Q(d_ff1_Z[50]) );
DFFRXLTS reg_Z0_Q_reg_49_ ( .D(data_in[49]), .CK(reg_Z0_net3719139), .RN(
n3231), .Q(d_ff1_Z[49]) );
DFFRXLTS reg_Z0_Q_reg_48_ ( .D(data_in[48]), .CK(reg_Z0_net3719139), .RN(
n3221), .Q(d_ff1_Z[48]) );
DFFRXLTS reg_Z0_Q_reg_47_ ( .D(data_in[47]), .CK(reg_Z0_net3719139), .RN(
n3221), .Q(d_ff1_Z[47]) );
DFFRXLTS reg_Z0_Q_reg_46_ ( .D(data_in[46]), .CK(reg_Z0_net3719139), .RN(
n3221), .Q(d_ff1_Z[46]) );
DFFRXLTS reg_Z0_Q_reg_45_ ( .D(data_in[45]), .CK(reg_Z0_net3719139), .RN(
n3221), .Q(d_ff1_Z[45]) );
DFFRXLTS reg_Z0_Q_reg_44_ ( .D(data_in[44]), .CK(reg_Z0_net3719139), .RN(
n3221), .Q(d_ff1_Z[44]) );
DFFRXLTS reg_Z0_Q_reg_43_ ( .D(data_in[43]), .CK(reg_Z0_net3719139), .RN(
n3221), .Q(d_ff1_Z[43]) );
DFFRXLTS reg_Z0_Q_reg_42_ ( .D(data_in[42]), .CK(reg_Z0_net3719139), .RN(
n3221), .Q(d_ff1_Z[42]) );
DFFRXLTS reg_Z0_Q_reg_41_ ( .D(data_in[41]), .CK(reg_Z0_net3719139), .RN(
n3221), .Q(d_ff1_Z[41]) );
DFFRXLTS reg_Z0_Q_reg_40_ ( .D(data_in[40]), .CK(reg_Z0_net3719139), .RN(
n3221), .Q(d_ff1_Z[40]) );
DFFRXLTS reg_Z0_Q_reg_39_ ( .D(data_in[39]), .CK(reg_Z0_net3719139), .RN(
n3221), .Q(d_ff1_Z[39]) );
DFFRXLTS reg_Z0_Q_reg_38_ ( .D(data_in[38]), .CK(reg_Z0_net3719139), .RN(
n3221), .Q(d_ff1_Z[38]) );
DFFRXLTS reg_Z0_Q_reg_37_ ( .D(data_in[37]), .CK(reg_Z0_net3719139), .RN(
n3221), .Q(d_ff1_Z[37]) );
DFFRXLTS reg_Z0_Q_reg_36_ ( .D(data_in[36]), .CK(reg_Z0_net3719139), .RN(
n3216), .Q(d_ff1_Z[36]) );
DFFRXLTS reg_Z0_Q_reg_35_ ( .D(data_in[35]), .CK(reg_Z0_net3719139), .RN(
n3219), .Q(d_ff1_Z[35]) );
DFFRXLTS reg_Z0_Q_reg_34_ ( .D(data_in[34]), .CK(reg_Z0_net3719139), .RN(
n3239), .Q(d_ff1_Z[34]) );
DFFRXLTS reg_Z0_Q_reg_33_ ( .D(data_in[33]), .CK(reg_Z0_net3719139), .RN(
n3239), .Q(d_ff1_Z[33]) );
DFFRXLTS reg_Z0_Q_reg_32_ ( .D(data_in[32]), .CK(reg_Z0_net3719139), .RN(
n3218), .Q(d_ff1_Z[32]) );
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(data_in[31]), .CK(reg_Z0_net3719139), .RN(
n3219), .Q(d_ff1_Z[31]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(data_in[30]), .CK(reg_Z0_net3719139), .RN(
n3194), .Q(d_ff1_Z[30]) );
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(data_in[29]), .CK(reg_Z0_net3719139), .RN(
n3194), .Q(d_ff1_Z[29]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(data_in[28]), .CK(reg_Z0_net3719139), .RN(
n3194), .Q(d_ff1_Z[28]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(data_in[27]), .CK(reg_Z0_net3719139), .RN(
n3239), .Q(d_ff1_Z[27]) );
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(data_in[26]), .CK(reg_Z0_net3719139), .RN(
n3239), .Q(d_ff1_Z[26]) );
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(data_in[25]), .CK(reg_Z0_net3719139), .RN(
n3219), .Q(d_ff1_Z[25]) );
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(data_in[24]), .CK(reg_Z0_net3719139), .RN(
n3218), .Q(d_ff1_Z[24]) );
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(data_in[23]), .CK(reg_Z0_net3719139), .RN(
n3217), .Q(d_ff1_Z[23]) );
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(data_in[22]), .CK(reg_Z0_net3719139), .RN(
n3232), .Q(d_ff1_Z[22]) );
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(data_in[21]), .CK(reg_Z0_net3719139), .RN(
n3232), .Q(d_ff1_Z[21]) );
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(data_in[20]), .CK(reg_Z0_net3719139), .RN(
n3217), .Q(d_ff1_Z[20]) );
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(data_in[19]), .CK(reg_Z0_net3719139), .RN(
n3217), .Q(d_ff1_Z[19]) );
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(data_in[18]), .CK(reg_Z0_net3719139), .RN(
n3228), .Q(d_ff1_Z[18]) );
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(data_in[17]), .CK(reg_Z0_net3719139), .RN(
n3228), .Q(d_ff1_Z[17]) );
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(data_in[16]), .CK(reg_Z0_net3719139), .RN(
n3228), .Q(d_ff1_Z[16]) );
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(data_in[15]), .CK(reg_Z0_net3719139), .RN(
n3232), .Q(d_ff1_Z[15]) );
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(data_in[14]), .CK(reg_Z0_net3719139), .RN(
n3234), .Q(d_ff1_Z[14]) );
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(data_in[13]), .CK(reg_Z0_net3719139), .RN(
n3218), .Q(d_ff1_Z[13]) );
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(data_in[12]), .CK(reg_Z0_net3719139), .RN(
n3217), .Q(d_ff1_Z[12]) );
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(data_in[11]), .CK(reg_Z0_net3719139), .RN(
n3234), .Q(d_ff1_Z[11]) );
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(data_in[10]), .CK(reg_Z0_net3719139), .RN(
n3220), .Q(d_ff1_Z[10]) );
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(data_in[9]), .CK(reg_Z0_net3719139), .RN(n3220), .Q(d_ff1_Z[9]) );
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(data_in[8]), .CK(reg_Z0_net3719139), .RN(n3234), .Q(d_ff1_Z[8]) );
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(data_in[7]), .CK(reg_Z0_net3719139), .RN(n3234), .Q(d_ff1_Z[7]) );
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(data_in[6]), .CK(reg_Z0_net3719139), .RN(n3216), .Q(d_ff1_Z[6]) );
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(data_in[5]), .CK(reg_Z0_net3719139), .RN(n3216), .Q(d_ff1_Z[5]) );
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(data_in[4]), .CK(reg_Z0_net3719139), .RN(n3220), .Q(d_ff1_Z[4]) );
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(data_in[3]), .CK(reg_Z0_net3719139), .RN(n3234), .Q(d_ff1_Z[3]) );
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(data_in[2]), .CK(reg_Z0_net3719139), .RN(n3232), .Q(d_ff1_Z[2]) );
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(data_in[1]), .CK(reg_Z0_net3719139), .RN(n3217), .Q(d_ff1_Z[1]) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(data_in[0]), .CK(reg_Z0_net3719139), .RN(n3234), .Q(d_ff1_Z[0]) );
DFFRXLTS reg_Z0_Q_reg_63_ ( .D(data_in[63]), .CK(reg_Z0_net3719139), .RN(
n3239), .Q(d_ff1_Z[63]) );
DFFRXLTS reg_shift_x_Q_reg_62_ ( .D(sh_exp_x[10]), .CK(
reg_shift_y_net3719139), .RN(n3194), .Q(d_ff3_sh_x_out[62]) );
DFFRXLTS reg_shift_x_Q_reg_61_ ( .D(sh_exp_x[9]), .CK(reg_shift_y_net3719139), .RN(n3194), .Q(d_ff3_sh_x_out[61]) );
DFFRXLTS reg_shift_x_Q_reg_60_ ( .D(sh_exp_x[8]), .CK(reg_shift_y_net3719139), .RN(n3216), .Q(d_ff3_sh_x_out[60]) );
DFFRXLTS reg_shift_x_Q_reg_59_ ( .D(sh_exp_x[7]), .CK(reg_shift_y_net3719139), .RN(n3239), .Q(d_ff3_sh_x_out[59]) );
DFFRXLTS reg_shift_x_Q_reg_58_ ( .D(sh_exp_x[6]), .CK(reg_shift_y_net3719139), .RN(n3219), .Q(d_ff3_sh_x_out[58]) );
DFFRXLTS reg_shift_x_Q_reg_57_ ( .D(sh_exp_x[5]), .CK(reg_shift_y_net3719139), .RN(n3219), .Q(d_ff3_sh_x_out[57]) );
DFFRXLTS reg_shift_x_Q_reg_56_ ( .D(sh_exp_x[4]), .CK(reg_shift_y_net3719139), .RN(n3220), .Q(d_ff3_sh_x_out[56]) );
DFFRXLTS reg_shift_x_Q_reg_55_ ( .D(sh_exp_x[3]), .CK(reg_shift_y_net3719139), .RN(n3220), .Q(d_ff3_sh_x_out[55]) );
DFFRXLTS reg_shift_x_Q_reg_54_ ( .D(sh_exp_x[2]), .CK(reg_shift_y_net3719139), .RN(n3220), .Q(d_ff3_sh_x_out[54]) );
DFFRXLTS reg_shift_x_Q_reg_53_ ( .D(sh_exp_x[1]), .CK(reg_shift_y_net3719139), .RN(n3234), .Q(d_ff3_sh_x_out[53]) );
DFFRXLTS reg_shift_x_Q_reg_52_ ( .D(sh_exp_x[0]), .CK(reg_shift_y_net3719139), .RN(n3224), .Q(d_ff3_sh_x_out[52]) );
DFFRXLTS reg_shift_y_Q_reg_62_ ( .D(sh_exp_y[10]), .CK(
reg_shift_y_net3719139), .RN(n3241), .Q(d_ff3_sh_y_out[62]) );
DFFRXLTS reg_shift_y_Q_reg_61_ ( .D(sh_exp_y[9]), .CK(reg_shift_y_net3719139), .RN(n3240), .Q(d_ff3_sh_y_out[61]) );
DFFRXLTS reg_shift_y_Q_reg_60_ ( .D(sh_exp_y[8]), .CK(reg_shift_y_net3719139), .RN(n3229), .Q(d_ff3_sh_y_out[60]) );
DFFRXLTS reg_shift_y_Q_reg_59_ ( .D(sh_exp_y[7]), .CK(reg_shift_y_net3719139), .RN(n3209), .Q(d_ff3_sh_y_out[59]) );
DFFRXLTS reg_shift_y_Q_reg_58_ ( .D(sh_exp_y[6]), .CK(reg_shift_y_net3719139), .RN(n3197), .Q(d_ff3_sh_y_out[58]) );
DFFRXLTS reg_shift_y_Q_reg_57_ ( .D(sh_exp_y[5]), .CK(reg_shift_y_net3719139), .RN(n3229), .Q(d_ff3_sh_y_out[57]) );
DFFRXLTS reg_shift_y_Q_reg_56_ ( .D(sh_exp_y[4]), .CK(reg_shift_y_net3719139), .RN(n3240), .Q(d_ff3_sh_y_out[56]) );
DFFRXLTS reg_shift_y_Q_reg_55_ ( .D(sh_exp_y[3]), .CK(reg_shift_y_net3719139), .RN(n3236), .Q(d_ff3_sh_y_out[55]) );
DFFRXLTS reg_shift_y_Q_reg_54_ ( .D(sh_exp_y[2]), .CK(reg_shift_y_net3719139), .RN(n3207), .Q(d_ff3_sh_y_out[54]) );
DFFRXLTS reg_shift_y_Q_reg_53_ ( .D(sh_exp_y[1]), .CK(reg_shift_y_net3719139), .RN(n3206), .Q(d_ff3_sh_y_out[53]) );
DFFRXLTS reg_shift_y_Q_reg_52_ ( .D(sh_exp_y[0]), .CK(reg_shift_y_net3719139), .RN(n3227), .Q(d_ff3_sh_y_out[52]) );
DFFRXLTS d_ff4_Xn_Q_reg_62_ ( .D(result_add_subt[62]), .CK(
d_ff4_Xn_net3719139), .RN(n3207), .Q(d_ff_Xn[62]) );
DFFRXLTS d_ff4_Xn_Q_reg_61_ ( .D(result_add_subt[61]), .CK(
d_ff4_Xn_net3719139), .RN(n3243), .Q(d_ff_Xn[61]) );
DFFRXLTS d_ff4_Xn_Q_reg_60_ ( .D(result_add_subt[60]), .CK(
d_ff4_Xn_net3719139), .RN(n3220), .Q(d_ff_Xn[60]) );
DFFRXLTS d_ff4_Xn_Q_reg_59_ ( .D(result_add_subt[59]), .CK(
d_ff4_Xn_net3719139), .RN(n3193), .Q(d_ff_Xn[59]) );
DFFRXLTS d_ff4_Xn_Q_reg_58_ ( .D(result_add_subt[58]), .CK(
d_ff4_Xn_net3719139), .RN(n3215), .Q(d_ff_Xn[58]) );
DFFRXLTS d_ff4_Xn_Q_reg_57_ ( .D(result_add_subt[57]), .CK(
d_ff4_Xn_net3719139), .RN(n3241), .Q(d_ff_Xn[57]) );
DFFRXLTS d_ff4_Xn_Q_reg_56_ ( .D(result_add_subt[56]), .CK(
d_ff4_Xn_net3719139), .RN(n3229), .Q(d_ff_Xn[56]) );
DFFRXLTS d_ff4_Xn_Q_reg_55_ ( .D(result_add_subt[55]), .CK(
d_ff4_Xn_net3719139), .RN(n3240), .Q(d_ff_Xn[55]) );
DFFRXLTS d_ff4_Xn_Q_reg_54_ ( .D(n1391), .CK(d_ff4_Xn_net3719139), .RN(n3210), .Q(d_ff_Xn[54]) );
DFFRXLTS d_ff4_Xn_Q_reg_53_ ( .D(result_add_subt[53]), .CK(
d_ff4_Xn_net3719139), .RN(n3214), .Q(d_ff_Xn[53]) );
DFFRXLTS d_ff4_Xn_Q_reg_52_ ( .D(result_add_subt[52]), .CK(
d_ff4_Xn_net3719139), .RN(n3195), .Q(d_ff_Xn[52]) );
DFFRXLTS d_ff4_Xn_Q_reg_51_ ( .D(result_add_subt[51]), .CK(
d_ff4_Xn_net3719139), .RN(n3243), .Q(d_ff_Xn[51]) );
DFFRXLTS d_ff4_Xn_Q_reg_50_ ( .D(n1396), .CK(d_ff4_Xn_net3719139), .RN(n1301), .Q(d_ff_Xn[50]) );
DFFRXLTS d_ff4_Xn_Q_reg_49_ ( .D(result_add_subt[49]), .CK(
d_ff4_Xn_net3719139), .RN(n3243), .Q(d_ff_Xn[49]) );
DFFRXLTS d_ff4_Xn_Q_reg_48_ ( .D(result_add_subt[48]), .CK(
d_ff4_Xn_net3719139), .RN(n3201), .Q(d_ff_Xn[48]) );
DFFRXLTS d_ff4_Xn_Q_reg_47_ ( .D(n1397), .CK(d_ff4_Xn_net3719139), .RN(n3200), .Q(d_ff_Xn[47]) );
DFFRXLTS d_ff4_Xn_Q_reg_46_ ( .D(n1398), .CK(d_ff4_Xn_net3719139), .RN(n3241), .Q(d_ff_Xn[46]) );
DFFRXLTS d_ff4_Xn_Q_reg_45_ ( .D(n1399), .CK(d_ff4_Xn_net3719139), .RN(n3229), .Q(d_ff_Xn[45]) );
DFFRXLTS d_ff4_Xn_Q_reg_44_ ( .D(n1393), .CK(d_ff4_Xn_net3719139), .RN(n3243), .Q(d_ff_Xn[44]) );
DFFRXLTS d_ff4_Xn_Q_reg_43_ ( .D(n1394), .CK(d_ff4_Xn_net3719139), .RN(n3241), .Q(d_ff_Xn[43]) );
DFFRXLTS d_ff4_Xn_Q_reg_42_ ( .D(result_add_subt[42]), .CK(
d_ff4_Xn_net3719139), .RN(n1301), .Q(d_ff_Xn[42]) );
DFFRXLTS d_ff4_Xn_Q_reg_41_ ( .D(n1392), .CK(d_ff4_Xn_net3719139), .RN(n3242), .Q(d_ff_Xn[41]) );
DFFRXLTS d_ff4_Xn_Q_reg_40_ ( .D(n1395), .CK(d_ff4_Xn_net3719139), .RN(n3203), .Q(d_ff_Xn[40]) );
DFFRXLTS d_ff4_Xn_Q_reg_39_ ( .D(result_add_subt[39]), .CK(
d_ff4_Xn_net3719139), .RN(n3230), .Q(d_ff_Xn[39]) );
DFFRXLTS d_ff4_Xn_Q_reg_38_ ( .D(result_add_subt[38]), .CK(
d_ff4_Xn_net3719139), .RN(n3232), .Q(d_ff_Xn[38]) );
DFFRXLTS d_ff4_Xn_Q_reg_37_ ( .D(result_add_subt[37]), .CK(
d_ff4_Xn_net3719139), .RN(n3228), .Q(d_ff_Xn[37]) );
DFFRXLTS d_ff4_Xn_Q_reg_36_ ( .D(result_add_subt[36]), .CK(
d_ff4_Xn_net3719139), .RN(n3228), .Q(d_ff_Xn[36]) );
DFFRXLTS d_ff4_Xn_Q_reg_35_ ( .D(result_add_subt[35]), .CK(
d_ff4_Xn_net3719139), .RN(n3220), .Q(d_ff_Xn[35]) );
DFFRXLTS d_ff4_Xn_Q_reg_34_ ( .D(result_add_subt[34]), .CK(
d_ff4_Xn_net3719139), .RN(n3232), .Q(d_ff_Xn[34]) );
DFFRXLTS d_ff4_Xn_Q_reg_33_ ( .D(result_add_subt[33]), .CK(
d_ff4_Xn_net3719139), .RN(n3220), .Q(d_ff_Xn[33]) );
DFFRXLTS d_ff4_Xn_Q_reg_32_ ( .D(result_add_subt[32]), .CK(
d_ff4_Xn_net3719139), .RN(n3218), .Q(d_ff_Xn[32]) );
DFFRXLTS d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Xn_net3719139), .RN(n3238), .Q(d_ff_Xn[31]) );
DFFRXLTS d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Xn_net3719139), .RN(n3238), .Q(d_ff_Xn[30]) );
DFFRXLTS d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Xn_net3719139), .RN(n3238), .Q(d_ff_Xn[27]) );
DFFRXLTS d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Xn_net3719139), .RN(n3230), .Q(d_ff_Xn[26]) );
DFFRXLTS d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Xn_net3719139), .RN(n3238), .Q(d_ff_Xn[25]) );
DFFRXLTS d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Xn_net3719139), .RN(n3228), .Q(d_ff_Xn[24]) );
DFFRXLTS d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Xn_net3719139), .RN(n3234), .Q(d_ff_Xn[20]) );
DFFRXLTS d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Xn_net3719139), .RN(n3218), .Q(d_ff_Xn[19]) );
DFFRXLTS d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Xn_net3719139), .RN(n3228), .Q(d_ff_Xn[17]) );
DFFRXLTS d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Xn_net3719139), .RN(n3238), .Q(d_ff_Xn[15]) );
DFFRXLTS d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Xn_net3719139), .RN(n3230), .Q(d_ff_Xn[13]) );
DFFRXLTS d_ff4_Yn_Q_reg_62_ ( .D(result_add_subt[62]), .CK(
d_ff4_Yn_net3719139), .RN(n3230), .Q(d_ff_Yn[62]) );
DFFRXLTS d_ff4_Yn_Q_reg_61_ ( .D(result_add_subt[61]), .CK(
d_ff4_Yn_net3719139), .RN(n3218), .Q(d_ff_Yn[61]) );
DFFRXLTS d_ff4_Yn_Q_reg_60_ ( .D(result_add_subt[60]), .CK(
d_ff4_Yn_net3719139), .RN(n3218), .Q(d_ff_Yn[60]) );
DFFRXLTS d_ff4_Yn_Q_reg_59_ ( .D(result_add_subt[59]), .CK(
d_ff4_Yn_net3719139), .RN(n3238), .Q(d_ff_Yn[59]) );
DFFRXLTS d_ff4_Yn_Q_reg_58_ ( .D(result_add_subt[58]), .CK(
d_ff4_Yn_net3719139), .RN(n3238), .Q(d_ff_Yn[58]) );
DFFRXLTS d_ff4_Yn_Q_reg_57_ ( .D(result_add_subt[57]), .CK(
d_ff4_Yn_net3719139), .RN(n3191), .Q(d_ff_Yn[57]) );
DFFRXLTS d_ff4_Yn_Q_reg_56_ ( .D(result_add_subt[56]), .CK(
d_ff4_Yn_net3719139), .RN(n3192), .Q(d_ff_Yn[56]) );
DFFRXLTS d_ff4_Yn_Q_reg_55_ ( .D(result_add_subt[55]), .CK(
d_ff4_Yn_net3719139), .RN(n3195), .Q(d_ff_Yn[55]) );
DFFRXLTS d_ff4_Yn_Q_reg_54_ ( .D(n1391), .CK(d_ff4_Yn_net3719139), .RN(n3191), .Q(d_ff_Yn[54]) );
DFFRXLTS d_ff4_Yn_Q_reg_53_ ( .D(result_add_subt[53]), .CK(
d_ff4_Yn_net3719139), .RN(n3193), .Q(d_ff_Yn[53]) );
DFFRXLTS d_ff4_Yn_Q_reg_52_ ( .D(result_add_subt[52]), .CK(
d_ff4_Yn_net3719139), .RN(n3196), .Q(d_ff_Yn[52]) );
DFFRXLTS d_ff4_Yn_Q_reg_51_ ( .D(result_add_subt[51]), .CK(
d_ff4_Yn_net3719139), .RN(n3188), .Q(d_ff_Yn[51]) );
DFFRXLTS d_ff4_Yn_Q_reg_50_ ( .D(n1396), .CK(d_ff4_Yn_net3719139), .RN(n3186), .Q(d_ff_Yn[50]) );
DFFRXLTS d_ff4_Yn_Q_reg_49_ ( .D(result_add_subt[49]), .CK(
d_ff4_Yn_net3719139), .RN(n3193), .Q(d_ff_Yn[49]) );
DFFRXLTS d_ff4_Yn_Q_reg_48_ ( .D(result_add_subt[48]), .CK(
d_ff4_Yn_net3719139), .RN(n3191), .Q(d_ff_Yn[48]) );
DFFRXLTS d_ff4_Yn_Q_reg_47_ ( .D(n1397), .CK(d_ff4_Yn_net3719139), .RN(n3196), .Q(d_ff_Yn[47]) );
DFFRXLTS d_ff4_Yn_Q_reg_46_ ( .D(n1398), .CK(d_ff4_Yn_net3719139), .RN(n3192), .Q(d_ff_Yn[46]) );
DFFRXLTS d_ff4_Yn_Q_reg_45_ ( .D(n1399), .CK(d_ff4_Yn_net3719139), .RN(n3236), .Q(d_ff_Yn[45]) );
DFFRXLTS d_ff4_Yn_Q_reg_44_ ( .D(n1393), .CK(d_ff4_Yn_net3719139), .RN(n3236), .Q(d_ff_Yn[44]) );
DFFRXLTS d_ff4_Yn_Q_reg_43_ ( .D(n1394), .CK(d_ff4_Yn_net3719139), .RN(n3236), .Q(d_ff_Yn[43]) );
DFFRXLTS d_ff4_Yn_Q_reg_42_ ( .D(result_add_subt[42]), .CK(
d_ff4_Yn_net3719139), .RN(n3236), .Q(d_ff_Yn[42]) );
DFFRXLTS d_ff4_Yn_Q_reg_41_ ( .D(n1392), .CK(d_ff4_Yn_net3719139), .RN(n3236), .Q(d_ff_Yn[41]) );
DFFRXLTS d_ff4_Yn_Q_reg_40_ ( .D(n1395), .CK(d_ff4_Yn_net3719139), .RN(n3236), .Q(d_ff_Yn[40]) );
DFFRXLTS d_ff4_Yn_Q_reg_39_ ( .D(result_add_subt[39]), .CK(
d_ff4_Yn_net3719139), .RN(n3236), .Q(d_ff_Yn[39]) );
DFFRXLTS d_ff4_Yn_Q_reg_38_ ( .D(result_add_subt[38]), .CK(
d_ff4_Yn_net3719139), .RN(n3236), .Q(d_ff_Yn[38]) );
DFFRXLTS d_ff4_Yn_Q_reg_37_ ( .D(result_add_subt[37]), .CK(
d_ff4_Yn_net3719139), .RN(n3236), .Q(d_ff_Yn[37]) );
DFFRXLTS d_ff4_Yn_Q_reg_36_ ( .D(result_add_subt[36]), .CK(
d_ff4_Yn_net3719139), .RN(n3236), .Q(d_ff_Yn[36]) );
DFFRXLTS d_ff4_Yn_Q_reg_35_ ( .D(result_add_subt[35]), .CK(
d_ff4_Yn_net3719139), .RN(n3236), .Q(d_ff_Yn[35]) );
DFFRXLTS d_ff4_Yn_Q_reg_34_ ( .D(result_add_subt[34]), .CK(
d_ff4_Yn_net3719139), .RN(n3236), .Q(d_ff_Yn[34]) );
DFFRXLTS d_ff4_Yn_Q_reg_33_ ( .D(result_add_subt[33]), .CK(
d_ff4_Yn_net3719139), .RN(n3235), .Q(d_ff_Yn[33]) );
DFFRXLTS d_ff4_Yn_Q_reg_32_ ( .D(result_add_subt[32]), .CK(
d_ff4_Yn_net3719139), .RN(n3235), .Q(d_ff_Yn[32]) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Yn_net3719139), .RN(n3235), .Q(d_ff_Yn[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Yn_net3719139), .RN(n3235), .Q(d_ff_Yn[30]) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Yn_net3719139), .RN(n3235), .Q(d_ff_Yn[27]) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Yn_net3719139), .RN(n3235), .Q(d_ff_Yn[26]) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Yn_net3719139), .RN(n3235), .Q(d_ff_Yn[25]) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Yn_net3719139), .RN(n3235), .Q(d_ff_Yn[24]) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Yn_net3719139), .RN(n3235), .Q(d_ff_Yn[20]) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Yn_net3719139), .RN(n3235), .Q(d_ff_Yn[19]) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Yn_net3719139), .RN(n3223), .Q(d_ff_Yn[17]) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Yn_net3719139), .RN(n3223), .Q(d_ff_Yn[15]) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Yn_net3719139), .RN(n3239), .Q(d_ff_Yn[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_62_ ( .D(result_add_subt[62]), .CK(
d_ff4_Zn_net3719139), .RN(n3238), .Q(d_ff_Zn[62]) );
DFFRXLTS d_ff4_Zn_Q_reg_61_ ( .D(result_add_subt[61]), .CK(
d_ff4_Zn_net3719139), .RN(n3238), .Q(d_ff_Zn[61]) );
DFFRXLTS d_ff4_Zn_Q_reg_60_ ( .D(result_add_subt[60]), .CK(
d_ff4_Zn_net3719139), .RN(n3232), .Q(d_ff_Zn[60]) );
DFFRXLTS d_ff4_Zn_Q_reg_59_ ( .D(result_add_subt[59]), .CK(
d_ff4_Zn_net3719139), .RN(n3230), .Q(d_ff_Zn[59]) );
DFFRXLTS d_ff4_Zn_Q_reg_58_ ( .D(result_add_subt[58]), .CK(
d_ff4_Zn_net3719139), .RN(n3218), .Q(d_ff_Zn[58]) );
DFFRXLTS d_ff4_Zn_Q_reg_57_ ( .D(result_add_subt[57]), .CK(
d_ff4_Zn_net3719139), .RN(n3220), .Q(d_ff_Zn[57]) );
DFFRXLTS d_ff4_Zn_Q_reg_56_ ( .D(result_add_subt[56]), .CK(
d_ff4_Zn_net3719139), .RN(n3194), .Q(d_ff_Zn[56]) );
DFFRXLTS d_ff4_Zn_Q_reg_55_ ( .D(result_add_subt[55]), .CK(
d_ff4_Zn_net3719139), .RN(n3194), .Q(d_ff_Zn[55]) );
DFFRXLTS d_ff4_Zn_Q_reg_54_ ( .D(n1391), .CK(d_ff4_Zn_net3719139), .RN(n3194), .Q(d_ff_Zn[54]) );
DFFRXLTS d_ff4_Zn_Q_reg_53_ ( .D(result_add_subt[53]), .CK(
d_ff4_Zn_net3719139), .RN(n3239), .Q(d_ff_Zn[53]) );
DFFRXLTS d_ff4_Zn_Q_reg_52_ ( .D(result_add_subt[52]), .CK(
d_ff4_Zn_net3719139), .RN(n3233), .Q(d_ff_Zn[52]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_13_ ( .D(first_mux_Y[13]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3233), .Q(d_ff2_Y[13]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(d_ff2_Y[13]), .CK(reg_shift_y_net3719139), .RN(n3233), .Q(d_ff3_sh_y_out[13]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_15_ ( .D(first_mux_Y[15]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3233), .Q(d_ff2_Y[15]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(d_ff2_Y[15]), .CK(reg_shift_y_net3719139), .RN(n3233), .Q(d_ff3_sh_y_out[15]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_17_ ( .D(first_mux_Y[17]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3233), .Q(d_ff2_Y[17]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(d_ff2_Y[17]), .CK(reg_shift_y_net3719139), .RN(n3233), .Q(d_ff3_sh_y_out[17]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_19_ ( .D(first_mux_Y[19]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3225), .Q(d_ff2_Y[19]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(d_ff2_Y[19]), .CK(reg_shift_y_net3719139), .RN(n3225), .Q(d_ff3_sh_y_out[19]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_20_ ( .D(first_mux_Y[20]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3233), .Q(d_ff2_Y[20]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(d_ff2_Y[20]), .CK(reg_shift_y_net3719139), .RN(n3233), .Q(d_ff3_sh_y_out[20]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_24_ ( .D(first_mux_Y[24]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3220), .Q(d_ff2_Y[24]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(d_ff2_Y[24]), .CK(reg_shift_y_net3719139), .RN(n3194), .Q(d_ff3_sh_y_out[24]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_25_ ( .D(first_mux_Y[25]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3194), .Q(d_ff2_Y[25]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(d_ff2_Y[25]), .CK(reg_shift_y_net3719139), .RN(n3219), .Q(d_ff3_sh_y_out[25]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_26_ ( .D(first_mux_Y[26]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3219), .Q(d_ff2_Y[26]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(d_ff2_Y[26]), .CK(reg_shift_y_net3719139), .RN(n3220), .Q(d_ff3_sh_y_out[26]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_27_ ( .D(first_mux_Y[27]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3234), .Q(d_ff2_Y[27]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(d_ff2_Y[27]), .CK(reg_shift_y_net3719139), .RN(n3234), .Q(d_ff3_sh_y_out[27]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_30_ ( .D(first_mux_Y[30]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3216), .Q(d_ff2_Y[30]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(d_ff2_Y[30]), .CK(reg_shift_y_net3719139), .RN(n3216), .Q(d_ff3_sh_y_out[30]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_31_ ( .D(first_mux_Y[31]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3220), .Q(d_ff2_Y[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(d_ff2_Y[31]), .CK(reg_shift_y_net3719139), .RN(n3220), .Q(d_ff3_sh_y_out[31]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_32_ ( .D(first_mux_Y[32]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3222), .Q(d_ff2_Y[32]) );
DFFRXLTS reg_shift_y_Q_reg_32_ ( .D(d_ff2_Y[32]), .CK(reg_shift_y_net3719139), .RN(n3231), .Q(d_ff3_sh_y_out[32]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_33_ ( .D(first_mux_Y[33]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3222), .Q(d_ff2_Y[33]) );
DFFRXLTS reg_shift_y_Q_reg_33_ ( .D(d_ff2_Y[33]), .CK(reg_shift_y_net3719139), .RN(n3231), .Q(d_ff3_sh_y_out[33]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_34_ ( .D(first_mux_Y[34]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3222), .Q(d_ff2_Y[34]) );
DFFRXLTS reg_shift_y_Q_reg_34_ ( .D(d_ff2_Y[34]), .CK(reg_shift_y_net3719139), .RN(n3231), .Q(d_ff3_sh_y_out[34]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_35_ ( .D(first_mux_Y[35]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3222), .Q(d_ff2_Y[35]) );
DFFRXLTS reg_shift_y_Q_reg_35_ ( .D(d_ff2_Y[35]), .CK(reg_shift_y_net3719139), .RN(n3231), .Q(d_ff3_sh_y_out[35]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_36_ ( .D(first_mux_Y[36]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3222), .Q(d_ff2_Y[36]) );
DFFRXLTS reg_shift_y_Q_reg_36_ ( .D(d_ff2_Y[36]), .CK(reg_shift_y_net3719139), .RN(n3231), .Q(d_ff3_sh_y_out[36]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_37_ ( .D(first_mux_Y[37]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3222), .Q(d_ff2_Y[37]) );
DFFRXLTS reg_shift_y_Q_reg_37_ ( .D(d_ff2_Y[37]), .CK(reg_shift_y_net3719139), .RN(n3231), .Q(d_ff3_sh_y_out[37]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_38_ ( .D(first_mux_Y[38]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3229), .Q(d_ff2_Y[38]) );
DFFRXLTS reg_shift_y_Q_reg_38_ ( .D(d_ff2_Y[38]), .CK(reg_shift_y_net3719139), .RN(n3206), .Q(d_ff3_sh_y_out[38]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_39_ ( .D(first_mux_Y[39]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3214), .Q(d_ff2_Y[39]) );
DFFRXLTS reg_shift_y_Q_reg_39_ ( .D(d_ff2_Y[39]), .CK(reg_shift_y_net3719139), .RN(n3213), .Q(d_ff3_sh_y_out[39]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_40_ ( .D(first_mux_Y[40]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3243), .Q(d_ff2_Y[40]) );
DFFRXLTS reg_shift_y_Q_reg_40_ ( .D(d_ff2_Y[40]), .CK(reg_shift_y_net3719139), .RN(n3198), .Q(d_ff3_sh_y_out[40]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_41_ ( .D(first_mux_Y[41]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3227), .Q(d_ff2_Y[41]) );
DFFRXLTS reg_shift_y_Q_reg_41_ ( .D(d_ff2_Y[41]), .CK(reg_shift_y_net3719139), .RN(n3240), .Q(d_ff3_sh_y_out[41]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_42_ ( .D(first_mux_Y[42]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3216), .Q(d_ff2_Y[42]) );
DFFRXLTS reg_shift_y_Q_reg_42_ ( .D(d_ff2_Y[42]), .CK(reg_shift_y_net3719139), .RN(n3226), .Q(d_ff3_sh_y_out[42]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_43_ ( .D(first_mux_Y[43]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3192), .Q(d_ff2_Y[43]) );
DFFRXLTS reg_shift_y_Q_reg_43_ ( .D(d_ff2_Y[43]), .CK(reg_shift_y_net3719139), .RN(n3201), .Q(d_ff3_sh_y_out[43]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_44_ ( .D(first_mux_Y[44]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3232), .Q(d_ff2_Y[44]) );
DFFRXLTS reg_shift_y_Q_reg_44_ ( .D(d_ff2_Y[44]), .CK(reg_shift_y_net3719139), .RN(n3220), .Q(d_ff3_sh_y_out[44]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_45_ ( .D(first_mux_Y[45]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3220), .Q(d_ff2_Y[45]) );
DFFRXLTS reg_shift_y_Q_reg_45_ ( .D(d_ff2_Y[45]), .CK(reg_shift_y_net3719139), .RN(n3216), .Q(d_ff3_sh_y_out[45]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_46_ ( .D(first_mux_Y[46]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3194), .Q(d_ff2_Y[46]) );
DFFRXLTS reg_shift_y_Q_reg_46_ ( .D(d_ff2_Y[46]), .CK(reg_shift_y_net3719139), .RN(n3216), .Q(d_ff3_sh_y_out[46]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_47_ ( .D(first_mux_Y[47]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3217), .Q(d_ff2_Y[47]) );
DFFRXLTS reg_shift_y_Q_reg_47_ ( .D(d_ff2_Y[47]), .CK(reg_shift_y_net3719139), .RN(n3217), .Q(d_ff3_sh_y_out[47]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_48_ ( .D(first_mux_Y[48]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3228), .Q(d_ff2_Y[48]) );
DFFRXLTS reg_shift_y_Q_reg_48_ ( .D(d_ff2_Y[48]), .CK(reg_shift_y_net3719139), .RN(n3228), .Q(d_ff3_sh_y_out[48]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_49_ ( .D(first_mux_Y[49]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3228), .Q(d_ff2_Y[49]) );
DFFRXLTS reg_shift_y_Q_reg_49_ ( .D(d_ff2_Y[49]), .CK(reg_shift_y_net3719139), .RN(n3232), .Q(d_ff3_sh_y_out[49]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_50_ ( .D(first_mux_Y[50]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3241), .Q(d_ff2_Y[50]) );
DFFRXLTS reg_shift_y_Q_reg_50_ ( .D(d_ff2_Y[50]), .CK(reg_shift_y_net3719139), .RN(n3227), .Q(d_ff3_sh_y_out[50]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_51_ ( .D(first_mux_Y[51]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3229), .Q(d_ff2_Y[51]) );
DFFRXLTS reg_shift_y_Q_reg_51_ ( .D(d_ff2_Y[51]), .CK(reg_shift_y_net3719139), .RN(n3240), .Q(d_ff3_sh_y_out[51]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_52_ ( .D(first_mux_Y[52]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3213), .Q(d_ff2_Y[52]), .QN(
n1449) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_59_ ( .D(first_mux_Y[59]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3219), .Q(d_ff2_Y[59]), .QN(
n1447) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_62_ ( .D(first_mux_Y[62]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3204), .Q(d_ff2_Y[62]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_52_ ( .D(first_mux_Z[52]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3241), .Q(d_ff2_Z[52]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_53_ ( .D(first_mux_Z[53]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3243), .Q(d_ff2_Z[53]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_54_ ( .D(first_mux_Z[54]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3236), .Q(d_ff2_Z[54]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_55_ ( .D(first_mux_Z[55]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3229), .Q(d_ff2_Z[55]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_56_ ( .D(first_mux_Z[56]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3240), .Q(d_ff2_Z[56]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_57_ ( .D(first_mux_Z[57]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3186), .Q(d_ff2_Z[57]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_58_ ( .D(first_mux_Z[58]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3229), .Q(d_ff2_Z[58]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_59_ ( .D(first_mux_Z[59]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3204), .Q(d_ff2_Z[59]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_60_ ( .D(first_mux_Z[60]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3207), .Q(d_ff2_Z[60]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_61_ ( .D(first_mux_Z[61]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3229), .Q(d_ff2_Z[61]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_62_ ( .D(first_mux_Z[62]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3230), .Q(d_ff2_Z[62]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_13_ ( .D(first_mux_X[13]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3201), .Q(d_ff2_X[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(d_ff2_X[13]), .CK(reg_shift_y_net3719139), .RN(n3201), .Q(d_ff3_sh_x_out[13]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_15_ ( .D(first_mux_X[15]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3201), .Q(d_ff2_X[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(d_ff2_X[15]), .CK(reg_shift_y_net3719139), .RN(n3201), .Q(d_ff3_sh_x_out[15]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_17_ ( .D(first_mux_X[17]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3201), .Q(d_ff2_X[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(d_ff2_X[17]), .CK(reg_shift_y_net3719139), .RN(n3201), .Q(d_ff3_sh_x_out[17]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_19_ ( .D(first_mux_X[19]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3201), .Q(d_ff2_X[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(d_ff2_X[19]), .CK(reg_shift_y_net3719139), .RN(n3201), .Q(d_ff3_sh_x_out[19]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_20_ ( .D(first_mux_X[20]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3201), .Q(d_ff2_X[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(d_ff2_X[20]), .CK(reg_shift_y_net3719139), .RN(n3201), .Q(d_ff3_sh_x_out[20]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_24_ ( .D(first_mux_X[24]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3201), .Q(d_ff2_X[24]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(d_ff2_X[24]), .CK(reg_shift_y_net3719139), .RN(n3201), .Q(d_ff3_sh_x_out[24]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_25_ ( .D(first_mux_X[25]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3200), .Q(d_ff2_X[25]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(d_ff2_X[25]), .CK(reg_shift_y_net3719139), .RN(n3200), .Q(d_ff3_sh_x_out[25]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_26_ ( .D(first_mux_X[26]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3200), .Q(d_ff2_X[26]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(d_ff2_X[26]), .CK(reg_shift_y_net3719139), .RN(n3200), .Q(d_ff3_sh_x_out[26]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_27_ ( .D(first_mux_X[27]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3200), .Q(d_ff2_X[27]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(d_ff2_X[27]), .CK(reg_shift_y_net3719139), .RN(n3200), .Q(d_ff3_sh_x_out[27]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_30_ ( .D(first_mux_X[30]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3200), .Q(d_ff2_X[30]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(d_ff2_X[30]), .CK(reg_shift_y_net3719139), .RN(n3200), .Q(d_ff3_sh_x_out[30]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_31_ ( .D(first_mux_X[31]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3224), .Q(d_ff2_X[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(d_ff2_X[31]), .CK(reg_shift_y_net3719139), .RN(n3200), .Q(d_ff3_sh_x_out[31]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_32_ ( .D(first_mux_X[32]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3224), .Q(d_ff2_X[32]) );
DFFRXLTS reg_shift_x_Q_reg_32_ ( .D(d_ff2_X[32]), .CK(reg_shift_y_net3719139), .RN(n3200), .Q(d_ff3_sh_x_out[32]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_33_ ( .D(first_mux_X[33]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3225), .Q(d_ff2_X[33]) );
DFFRXLTS reg_shift_x_Q_reg_33_ ( .D(d_ff2_X[33]), .CK(reg_shift_y_net3719139), .RN(n3199), .Q(d_ff3_sh_x_out[33]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_34_ ( .D(first_mux_X[34]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3225), .Q(d_ff2_X[34]) );
DFFRXLTS reg_shift_x_Q_reg_34_ ( .D(d_ff2_X[34]), .CK(reg_shift_y_net3719139), .RN(n3199), .Q(d_ff3_sh_x_out[34]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_35_ ( .D(first_mux_X[35]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3225), .Q(d_ff2_X[35]) );
DFFRXLTS reg_shift_x_Q_reg_35_ ( .D(d_ff2_X[35]), .CK(reg_shift_y_net3719139), .RN(n3199), .Q(d_ff3_sh_x_out[35]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_36_ ( .D(first_mux_X[36]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3225), .Q(d_ff2_X[36]) );
DFFRXLTS reg_shift_x_Q_reg_36_ ( .D(d_ff2_X[36]), .CK(reg_shift_y_net3719139), .RN(n3199), .Q(d_ff3_sh_x_out[36]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_37_ ( .D(first_mux_X[37]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3225), .Q(d_ff2_X[37]) );
DFFRXLTS reg_shift_x_Q_reg_37_ ( .D(d_ff2_X[37]), .CK(reg_shift_y_net3719139), .RN(n3199), .Q(d_ff3_sh_x_out[37]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_38_ ( .D(first_mux_X[38]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3225), .Q(d_ff2_X[38]) );
DFFRXLTS reg_shift_x_Q_reg_38_ ( .D(d_ff2_X[38]), .CK(reg_shift_y_net3719139), .RN(n3199), .Q(d_ff3_sh_x_out[38]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_39_ ( .D(first_mux_X[39]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3198), .Q(d_ff2_X[39]) );
DFFRXLTS reg_shift_x_Q_reg_39_ ( .D(d_ff2_X[39]), .CK(reg_shift_y_net3719139), .RN(n3198), .Q(d_ff3_sh_x_out[39]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_40_ ( .D(first_mux_X[40]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3198), .Q(d_ff2_X[40]) );
DFFRXLTS reg_shift_x_Q_reg_40_ ( .D(d_ff2_X[40]), .CK(reg_shift_y_net3719139), .RN(n3198), .Q(d_ff3_sh_x_out[40]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_41_ ( .D(first_mux_X[41]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3198), .Q(d_ff2_X[41]) );
DFFRXLTS reg_shift_x_Q_reg_41_ ( .D(d_ff2_X[41]), .CK(reg_shift_y_net3719139), .RN(n3198), .Q(d_ff3_sh_x_out[41]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_42_ ( .D(first_mux_X[42]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3198), .Q(d_ff2_X[42]) );
DFFRXLTS reg_shift_x_Q_reg_42_ ( .D(d_ff2_X[42]), .CK(reg_shift_y_net3719139), .RN(n3198), .Q(d_ff3_sh_x_out[42]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_43_ ( .D(first_mux_X[43]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3198), .Q(d_ff2_X[43]) );
DFFRXLTS reg_shift_x_Q_reg_43_ ( .D(d_ff2_X[43]), .CK(reg_shift_y_net3719139), .RN(n3198), .Q(d_ff3_sh_x_out[43]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_44_ ( .D(first_mux_X[44]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3198), .Q(d_ff2_X[44]) );
DFFRXLTS reg_shift_x_Q_reg_44_ ( .D(d_ff2_X[44]), .CK(reg_shift_y_net3719139), .RN(n3198), .Q(d_ff3_sh_x_out[44]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_45_ ( .D(first_mux_X[45]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3188), .Q(d_ff2_X[45]) );
DFFRXLTS reg_shift_x_Q_reg_45_ ( .D(d_ff2_X[45]), .CK(reg_shift_y_net3719139), .RN(n3191), .Q(d_ff3_sh_x_out[45]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_46_ ( .D(first_mux_X[46]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3188), .Q(d_ff2_X[46]) );
DFFRXLTS reg_shift_x_Q_reg_46_ ( .D(d_ff2_X[46]), .CK(reg_shift_y_net3719139), .RN(n3195), .Q(d_ff3_sh_x_out[46]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_47_ ( .D(first_mux_X[47]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3189), .Q(d_ff2_X[47]) );
DFFRXLTS reg_shift_x_Q_reg_47_ ( .D(d_ff2_X[47]), .CK(reg_shift_y_net3719139), .RN(n3191), .Q(d_ff3_sh_x_out[47]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_48_ ( .D(first_mux_X[48]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3196), .Q(d_ff2_X[48]) );
DFFRXLTS reg_shift_x_Q_reg_48_ ( .D(d_ff2_X[48]), .CK(reg_shift_y_net3719139), .RN(n3237), .Q(d_ff3_sh_x_out[48]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_49_ ( .D(first_mux_X[49]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3193), .Q(d_ff2_X[49]) );
DFFRXLTS reg_shift_x_Q_reg_49_ ( .D(d_ff2_X[49]), .CK(reg_shift_y_net3719139), .RN(n3237), .Q(d_ff3_sh_x_out[49]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_50_ ( .D(first_mux_X[50]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3186), .Q(d_ff2_X[50]) );
DFFRXLTS reg_shift_x_Q_reg_50_ ( .D(d_ff2_X[50]), .CK(reg_shift_y_net3719139), .RN(n3191), .Q(d_ff3_sh_x_out[50]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_51_ ( .D(first_mux_X[51]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3186), .Q(d_ff2_X[51]) );
DFFRXLTS reg_shift_x_Q_reg_51_ ( .D(d_ff2_X[51]), .CK(reg_shift_y_net3719139), .RN(n3196), .Q(d_ff3_sh_x_out[51]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_52_ ( .D(first_mux_X[52]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3189), .Q(d_ff2_X[52]), .QN(
n1448) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_57_ ( .D(first_mux_X[57]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3191), .Q(d_ff2_X[57]), .QN(
n3143) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_62_ ( .D(first_mux_X[62]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3193), .Q(d_ff2_X[62]) );
DFFRXLTS d_ff5_Q_reg_13_ ( .D(mux_sal[13]), .CK(d_ff5_net3719139), .RN(n3197), .Q(sign_inv_out[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(sign_inv_out[13]), .CK(
d_ff5_data_out_net3719139), .RN(n3237), .Q(data_output[13]) );
DFFRXLTS d_ff5_Q_reg_15_ ( .D(mux_sal[15]), .CK(d_ff5_net3719139), .RN(n3193), .Q(sign_inv_out[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(sign_inv_out[15]), .CK(
d_ff5_data_out_net3719139), .RN(n3196), .Q(data_output[15]) );
DFFRXLTS d_ff5_Q_reg_17_ ( .D(mux_sal[17]), .CK(d_ff5_net3719139), .RN(n3197), .Q(sign_inv_out[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(sign_inv_out[17]), .CK(
d_ff5_data_out_net3719139), .RN(n3195), .Q(data_output[17]) );
DFFRXLTS d_ff5_Q_reg_19_ ( .D(mux_sal[19]), .CK(d_ff5_net3719139), .RN(n3190), .Q(sign_inv_out[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(sign_inv_out[19]), .CK(
d_ff5_data_out_net3719139), .RN(n3189), .Q(data_output[19]) );
DFFRXLTS d_ff5_Q_reg_20_ ( .D(mux_sal[20]), .CK(d_ff5_net3719139), .RN(n3228), .Q(sign_inv_out[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(sign_inv_out[20]), .CK(
d_ff5_data_out_net3719139), .RN(n3216), .Q(data_output[20]) );
DFFRXLTS d_ff5_Q_reg_24_ ( .D(mux_sal[24]), .CK(d_ff5_net3719139), .RN(n3228), .Q(sign_inv_out[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(sign_inv_out[24]), .CK(
d_ff5_data_out_net3719139), .RN(n3217), .Q(data_output[24]) );
DFFRXLTS d_ff5_Q_reg_25_ ( .D(mux_sal[25]), .CK(d_ff5_net3719139), .RN(n3239), .Q(sign_inv_out[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(sign_inv_out[25]), .CK(
d_ff5_data_out_net3719139), .RN(n3228), .Q(data_output[25]) );
DFFRXLTS d_ff5_Q_reg_26_ ( .D(mux_sal[26]), .CK(d_ff5_net3719139), .RN(n3232), .Q(sign_inv_out[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(sign_inv_out[26]), .CK(
d_ff5_data_out_net3719139), .RN(n3232), .Q(data_output[26]) );
DFFRXLTS d_ff5_Q_reg_27_ ( .D(mux_sal[27]), .CK(d_ff5_net3719139), .RN(n3217), .Q(sign_inv_out[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(sign_inv_out[27]), .CK(
d_ff5_data_out_net3719139), .RN(n3217), .Q(data_output[27]) );
DFFRXLTS d_ff5_Q_reg_30_ ( .D(mux_sal[30]), .CK(d_ff5_net3719139), .RN(n3228), .Q(sign_inv_out[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(sign_inv_out[30]), .CK(
d_ff5_data_out_net3719139), .RN(n3228), .Q(data_output[30]) );
DFFRXLTS d_ff5_Q_reg_31_ ( .D(mux_sal[31]), .CK(d_ff5_net3719139), .RN(n3195), .Q(sign_inv_out[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(sign_inv_out[31]), .CK(
d_ff5_data_out_net3719139), .RN(n3190), .Q(data_output[31]) );
DFFRXLTS d_ff5_Q_reg_32_ ( .D(mux_sal[32]), .CK(d_ff5_net3719139), .RN(n3192), .Q(sign_inv_out[32]) );
DFFRXLTS d_ff5_data_out_Q_reg_32_ ( .D(sign_inv_out[32]), .CK(
d_ff5_data_out_net3719139), .RN(n3187), .Q(data_output[32]) );
DFFRXLTS d_ff5_Q_reg_33_ ( .D(mux_sal[33]), .CK(d_ff5_net3719139), .RN(n3195), .Q(sign_inv_out[33]) );
DFFRXLTS d_ff5_data_out_Q_reg_33_ ( .D(sign_inv_out[33]), .CK(
d_ff5_data_out_net3719139), .RN(n3186), .Q(data_output[33]) );
DFFRXLTS d_ff5_Q_reg_34_ ( .D(mux_sal[34]), .CK(d_ff5_net3719139), .RN(n3189), .Q(sign_inv_out[34]) );
DFFRXLTS d_ff5_data_out_Q_reg_34_ ( .D(sign_inv_out[34]), .CK(
d_ff5_data_out_net3719139), .RN(n3188), .Q(data_output[34]) );
DFFRXLTS d_ff5_Q_reg_35_ ( .D(mux_sal[35]), .CK(d_ff5_net3719139), .RN(n3187), .Q(sign_inv_out[35]) );
DFFRXLTS d_ff5_data_out_Q_reg_35_ ( .D(sign_inv_out[35]), .CK(
d_ff5_data_out_net3719139), .RN(n3196), .Q(data_output[35]) );
DFFRXLTS d_ff5_Q_reg_36_ ( .D(mux_sal[36]), .CK(d_ff5_net3719139), .RN(n3186), .Q(sign_inv_out[36]) );
DFFRXLTS d_ff5_data_out_Q_reg_36_ ( .D(sign_inv_out[36]), .CK(
d_ff5_data_out_net3719139), .RN(n3192), .Q(data_output[36]) );
DFFRXLTS d_ff5_Q_reg_37_ ( .D(mux_sal[37]), .CK(d_ff5_net3719139), .RN(n3186), .Q(sign_inv_out[37]) );
DFFRXLTS d_ff5_data_out_Q_reg_37_ ( .D(sign_inv_out[37]), .CK(
d_ff5_data_out_net3719139), .RN(n3189), .Q(data_output[37]) );
DFFRXLTS d_ff5_Q_reg_38_ ( .D(mux_sal[38]), .CK(d_ff5_net3719139), .RN(n3197), .Q(sign_inv_out[38]) );
DFFRXLTS d_ff5_data_out_Q_reg_38_ ( .D(sign_inv_out[38]), .CK(
d_ff5_data_out_net3719139), .RN(n3190), .Q(data_output[38]) );
DFFRXLTS d_ff5_Q_reg_39_ ( .D(mux_sal[39]), .CK(d_ff5_net3719139), .RN(n3186), .Q(sign_inv_out[39]) );
DFFRXLTS d_ff5_data_out_Q_reg_39_ ( .D(sign_inv_out[39]), .CK(
d_ff5_data_out_net3719139), .RN(n3191), .Q(data_output[39]) );
DFFRXLTS d_ff5_Q_reg_40_ ( .D(mux_sal[40]), .CK(d_ff5_net3719139), .RN(n3188), .Q(sign_inv_out[40]) );
DFFRXLTS d_ff5_data_out_Q_reg_40_ ( .D(sign_inv_out[40]), .CK(
d_ff5_data_out_net3719139), .RN(n3237), .Q(data_output[40]) );
DFFRXLTS d_ff5_Q_reg_41_ ( .D(mux_sal[41]), .CK(d_ff5_net3719139), .RN(n3190), .Q(sign_inv_out[41]) );
DFFRXLTS d_ff5_data_out_Q_reg_41_ ( .D(sign_inv_out[41]), .CK(
d_ff5_data_out_net3719139), .RN(n3195), .Q(data_output[41]) );
DFFRXLTS d_ff5_Q_reg_42_ ( .D(mux_sal[42]), .CK(d_ff5_net3719139), .RN(n3187), .Q(sign_inv_out[42]) );
DFFRXLTS d_ff5_data_out_Q_reg_42_ ( .D(sign_inv_out[42]), .CK(
d_ff5_data_out_net3719139), .RN(n3186), .Q(data_output[42]) );
DFFRXLTS d_ff5_Q_reg_43_ ( .D(mux_sal[43]), .CK(d_ff5_net3719139), .RN(n3189), .Q(sign_inv_out[43]) );
DFFRXLTS d_ff5_data_out_Q_reg_43_ ( .D(sign_inv_out[43]), .CK(
d_ff5_data_out_net3719139), .RN(n3193), .Q(data_output[43]) );
DFFRXLTS d_ff5_Q_reg_44_ ( .D(mux_sal[44]), .CK(d_ff5_net3719139), .RN(n3190), .Q(sign_inv_out[44]) );
DFFRXLTS d_ff5_data_out_Q_reg_44_ ( .D(sign_inv_out[44]), .CK(
d_ff5_data_out_net3719139), .RN(n3190), .Q(data_output[44]) );
DFFRXLTS d_ff5_Q_reg_45_ ( .D(mux_sal[45]), .CK(d_ff5_net3719139), .RN(n3196), .Q(sign_inv_out[45]) );
DFFRXLTS d_ff5_data_out_Q_reg_45_ ( .D(sign_inv_out[45]), .CK(
d_ff5_data_out_net3719139), .RN(n3188), .Q(data_output[45]) );
DFFRXLTS d_ff5_Q_reg_46_ ( .D(mux_sal[46]), .CK(d_ff5_net3719139), .RN(n3189), .Q(sign_inv_out[46]) );
DFFRXLTS d_ff5_data_out_Q_reg_46_ ( .D(sign_inv_out[46]), .CK(
d_ff5_data_out_net3719139), .RN(n3197), .Q(data_output[46]) );
DFFRXLTS d_ff5_Q_reg_47_ ( .D(mux_sal[47]), .CK(d_ff5_net3719139), .RN(n3195), .Q(sign_inv_out[47]) );
DFFRXLTS d_ff5_data_out_Q_reg_47_ ( .D(sign_inv_out[47]), .CK(
d_ff5_data_out_net3719139), .RN(n3186), .Q(data_output[47]) );
DFFRXLTS d_ff5_Q_reg_48_ ( .D(mux_sal[48]), .CK(d_ff5_net3719139), .RN(n3196), .Q(sign_inv_out[48]) );
DFFRXLTS d_ff5_data_out_Q_reg_48_ ( .D(sign_inv_out[48]), .CK(
d_ff5_data_out_net3719139), .RN(n3196), .Q(data_output[48]) );
DFFRXLTS d_ff5_Q_reg_49_ ( .D(mux_sal[49]), .CK(d_ff5_net3719139), .RN(n3188), .Q(sign_inv_out[49]) );
DFFRXLTS d_ff5_data_out_Q_reg_49_ ( .D(sign_inv_out[49]), .CK(
d_ff5_data_out_net3719139), .RN(n3192), .Q(data_output[49]) );
DFFRXLTS d_ff5_Q_reg_50_ ( .D(mux_sal[50]), .CK(d_ff5_net3719139), .RN(n3189), .Q(sign_inv_out[50]) );
DFFRXLTS d_ff5_data_out_Q_reg_50_ ( .D(sign_inv_out[50]), .CK(
d_ff5_data_out_net3719139), .RN(n3189), .Q(data_output[50]) );
DFFRXLTS d_ff5_Q_reg_51_ ( .D(mux_sal[51]), .CK(d_ff5_net3719139), .RN(n3195), .Q(sign_inv_out[51]) );
DFFRXLTS d_ff5_data_out_Q_reg_51_ ( .D(sign_inv_out[51]), .CK(
d_ff5_data_out_net3719139), .RN(n3187), .Q(data_output[51]) );
DFFRXLTS d_ff5_Q_reg_52_ ( .D(mux_sal[52]), .CK(d_ff5_net3719139), .RN(n3192), .Q(sign_inv_out[52]) );
DFFRXLTS d_ff5_data_out_Q_reg_52_ ( .D(sign_inv_out[52]), .CK(
d_ff5_data_out_net3719139), .RN(n3196), .Q(data_output[52]) );
DFFRXLTS d_ff5_Q_reg_53_ ( .D(mux_sal[53]), .CK(d_ff5_net3719139), .RN(n3195), .Q(sign_inv_out[53]) );
DFFRXLTS d_ff5_data_out_Q_reg_53_ ( .D(sign_inv_out[53]), .CK(
d_ff5_data_out_net3719139), .RN(n3186), .Q(data_output[53]) );
DFFRXLTS d_ff5_Q_reg_54_ ( .D(mux_sal[54]), .CK(d_ff5_net3719139), .RN(n3191), .Q(sign_inv_out[54]) );
DFFRXLTS d_ff5_data_out_Q_reg_54_ ( .D(sign_inv_out[54]), .CK(
d_ff5_data_out_net3719139), .RN(n3195), .Q(data_output[54]) );
DFFRXLTS d_ff5_Q_reg_55_ ( .D(mux_sal[55]), .CK(d_ff5_net3719139), .RN(n3237), .Q(sign_inv_out[55]) );
DFFRXLTS d_ff5_data_out_Q_reg_55_ ( .D(sign_inv_out[55]), .CK(
d_ff5_data_out_net3719139), .RN(n3197), .Q(data_output[55]) );
DFFRXLTS d_ff5_Q_reg_56_ ( .D(mux_sal[56]), .CK(d_ff5_net3719139), .RN(n3188), .Q(sign_inv_out[56]) );
DFFRXLTS d_ff5_data_out_Q_reg_56_ ( .D(sign_inv_out[56]), .CK(
d_ff5_data_out_net3719139), .RN(n3188), .Q(data_output[56]) );
DFFRXLTS d_ff5_Q_reg_57_ ( .D(mux_sal[57]), .CK(d_ff5_net3719139), .RN(n3190), .Q(sign_inv_out[57]) );
DFFRXLTS d_ff5_data_out_Q_reg_57_ ( .D(sign_inv_out[57]), .CK(
d_ff5_data_out_net3719139), .RN(n3197), .Q(data_output[57]) );
DFFRXLTS d_ff5_Q_reg_58_ ( .D(mux_sal[58]), .CK(d_ff5_net3719139), .RN(n3188), .Q(sign_inv_out[58]) );
DFFRXLTS d_ff5_data_out_Q_reg_58_ ( .D(sign_inv_out[58]), .CK(
d_ff5_data_out_net3719139), .RN(n3187), .Q(data_output[58]) );
DFFRXLTS d_ff5_Q_reg_59_ ( .D(mux_sal[59]), .CK(d_ff5_net3719139), .RN(n3191), .Q(sign_inv_out[59]) );
DFFRXLTS d_ff5_data_out_Q_reg_59_ ( .D(sign_inv_out[59]), .CK(
d_ff5_data_out_net3719139), .RN(n3196), .Q(data_output[59]) );
DFFRXLTS d_ff5_Q_reg_60_ ( .D(mux_sal[60]), .CK(d_ff5_net3719139), .RN(n3186), .Q(sign_inv_out[60]) );
DFFRXLTS d_ff5_data_out_Q_reg_60_ ( .D(sign_inv_out[60]), .CK(
d_ff5_data_out_net3719139), .RN(n3193), .Q(data_output[60]) );
DFFRXLTS d_ff5_Q_reg_61_ ( .D(mux_sal[61]), .CK(d_ff5_net3719139), .RN(n3195), .Q(sign_inv_out[61]) );
DFFRXLTS d_ff5_data_out_Q_reg_61_ ( .D(sign_inv_out[61]), .CK(
d_ff5_data_out_net3719139), .RN(n3237), .Q(data_output[61]) );
DFFRXLTS d_ff5_Q_reg_62_ ( .D(mux_sal[62]), .CK(d_ff5_net3719139), .RN(n3237), .Q(sign_inv_out[62]) );
DFFRXLTS d_ff5_data_out_Q_reg_62_ ( .D(sign_inv_out[62]), .CK(
d_ff5_data_out_net3719139), .RN(n3186), .Q(data_output[62]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_62_ ( .D(
add_subt_module_Oper_Start_in_module_intM[62]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3170),
.Q(add_subt_module_DMP[62]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_61_ ( .D(
add_subt_module_Oper_Start_in_module_intM[61]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3154),
.Q(add_subt_module_DMP[61]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_60_ ( .D(
add_subt_module_Oper_Start_in_module_intM[60]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3178),
.Q(add_subt_module_DMP[60]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_59_ ( .D(
add_subt_module_Oper_Start_in_module_intM[59]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3170),
.Q(add_subt_module_DMP[59]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_58_ ( .D(
add_subt_module_Oper_Start_in_module_intM[58]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3169),
.Q(add_subt_module_DMP[58]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_57_ ( .D(
add_subt_module_Oper_Start_in_module_intM[57]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3169),
.Q(add_subt_module_DMP[57]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_56_ ( .D(
add_subt_module_Oper_Start_in_module_intM[56]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3169),
.Q(add_subt_module_DMP[56]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_55_ ( .D(
add_subt_module_Oper_Start_in_module_intM[55]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3169),
.Q(add_subt_module_DMP[55]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_54_ ( .D(
add_subt_module_Oper_Start_in_module_intM[54]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3169),
.Q(add_subt_module_DMP[54]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_53_ ( .D(
add_subt_module_Oper_Start_in_module_intM[53]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3169),
.Q(add_subt_module_DMP[53]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_52_ ( .D(
add_subt_module_Oper_Start_in_module_intM[52]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3169),
.Q(add_subt_module_DMP[52]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_62_ ( .D(
add_subt_module_Oper_Start_in_module_intm[62]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3168),
.Q(add_subt_module_DmP[62]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_61_ ( .D(
add_subt_module_Oper_Start_in_module_intm[61]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3180),
.Q(add_subt_module_DmP[61]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_60_ ( .D(
add_subt_module_Oper_Start_in_module_intm[60]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3162),
.Q(add_subt_module_DmP[60]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_59_ ( .D(
add_subt_module_Oper_Start_in_module_intm[59]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3168),
.Q(add_subt_module_DmP[59]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_58_ ( .D(
add_subt_module_Oper_Start_in_module_intm[58]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3180),
.Q(add_subt_module_DmP[58]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_57_ ( .D(
add_subt_module_Oper_Start_in_module_intm[57]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3162),
.Q(add_subt_module_DmP[57]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_56_ ( .D(
add_subt_module_Oper_Start_in_module_intm[56]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3168),
.Q(add_subt_module_DmP[56]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_55_ ( .D(
add_subt_module_Oper_Start_in_module_intm[55]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3180),
.Q(add_subt_module_DmP[55]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_54_ ( .D(
add_subt_module_Oper_Start_in_module_intm[54]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3168),
.Q(add_subt_module_DmP[54]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_53_ ( .D(
add_subt_module_Oper_Start_in_module_intm[53]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3246),
.Q(add_subt_module_DmP[53]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_52_ ( .D(
add_subt_module_Oper_Start_in_module_intm[52]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3163),
.Q(add_subt_module_DmP[52]) );
DFFRXLTS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ (
.D(add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[2]), .CK(
add_subt_module_Leading_Zero_Detector_Module_Output_Reg_net3719175),
.RN(n3152), .Q(add_subt_module_LZA_output[2]) );
DFFRXLTS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ (
.D(add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[1]), .CK(
add_subt_module_Leading_Zero_Detector_Module_Output_Reg_net3719175),
.RN(n3164), .Q(add_subt_module_LZA_output[1]) );
DFFRXLTS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ (
.D(add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[0]), .CK(
add_subt_module_Leading_Zero_Detector_Module_Output_Reg_net3719175),
.RN(n3164), .Q(add_subt_module_LZA_output[0]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[16]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3164), .QN(n1322) );
DFFRXLTS d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Xn_net3719139), .RN(n3191), .Q(d_ff_Xn[14]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_14_ ( .D(first_mux_X[14]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3189), .Q(d_ff2_X[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(d_ff2_X[14]), .CK(reg_shift_y_net3719139), .RN(n3195), .Q(d_ff3_sh_x_out[14]) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Yn_net3719139), .RN(n3237), .Q(d_ff_Yn[14]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_14_ ( .D(first_mux_Y[14]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3186), .Q(d_ff2_Y[14]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(d_ff2_Y[14]), .CK(reg_shift_y_net3719139), .RN(n3193), .Q(d_ff3_sh_y_out[14]) );
DFFRXLTS d_ff5_Q_reg_14_ ( .D(mux_sal[14]), .CK(d_ff5_net3719139), .RN(n3187), .Q(sign_inv_out[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(sign_inv_out[14]), .CK(
d_ff5_data_out_net3719139), .RN(n3196), .Q(data_output[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Zn_net3719139), .RN(n3197), .Q(d_ff_Zn[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(first_mux_Z[14]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3186), .Q(d_ff2_Z[14]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(
add_subt_module_Oper_Start_in_module_intm[14]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3176),
.Q(add_subt_module_DmP[14]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(
add_subt_module_Oper_Start_in_module_intM[14]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3164),
.Q(add_subt_module_DMP[14]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[18]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3164), .QN(n1323) );
DFFRXLTS d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Xn_net3719139), .RN(n3196), .Q(d_ff_Xn[16]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_16_ ( .D(first_mux_X[16]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3192), .Q(d_ff2_X[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(d_ff2_X[16]), .CK(reg_shift_y_net3719139), .RN(n3187), .Q(d_ff3_sh_x_out[16]) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Yn_net3719139), .RN(n3237), .Q(d_ff_Yn[16]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_16_ ( .D(first_mux_Y[16]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3191), .Q(d_ff2_Y[16]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(d_ff2_Y[16]), .CK(reg_shift_y_net3719139), .RN(n3192), .Q(d_ff3_sh_y_out[16]) );
DFFRXLTS d_ff5_Q_reg_16_ ( .D(mux_sal[16]), .CK(d_ff5_net3719139), .RN(n3196), .Q(sign_inv_out[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(sign_inv_out[16]), .CK(
d_ff5_data_out_net3719139), .RN(n3187), .Q(data_output[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Zn_net3719139), .RN(n3190), .Q(d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(first_mux_Z[16]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3195), .Q(d_ff2_Z[16]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(
add_subt_module_Oper_Start_in_module_intm[16]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3180),
.Q(add_subt_module_DmP[16]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(
add_subt_module_Oper_Start_in_module_intM[16]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3164),
.Q(add_subt_module_DMP[16]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[6]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3169), .QN(n1317) );
DFFRXLTS d_ff4_Xn_Q_reg_6_ ( .D(n1390), .CK(d_ff4_Xn_net3719139), .RN(n3190),
.Q(d_ff_Xn[6]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_6_ ( .D(first_mux_X[6]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3191), .Q(d_ff2_X[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(d_ff2_X[6]), .CK(reg_shift_y_net3719139),
.RN(n3187), .Q(d_ff3_sh_x_out[6]) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(n1390), .CK(d_ff4_Yn_net3719139), .RN(n3187),
.Q(d_ff_Yn[6]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_6_ ( .D(first_mux_Y[6]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3191), .Q(d_ff2_Y[6]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(d_ff2_Y[6]), .CK(reg_shift_y_net3719139),
.RN(n3186), .Q(d_ff3_sh_y_out[6]) );
DFFRXLTS d_ff5_Q_reg_6_ ( .D(mux_sal[6]), .CK(d_ff5_net3719139), .RN(n3193),
.Q(sign_inv_out[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(sign_inv_out[6]), .CK(
d_ff5_data_out_net3719139), .RN(n3190), .Q(data_output[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n1390), .CK(d_ff4_Zn_net3719139), .RN(n3192),
.Q(d_ff_Zn[6]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(first_mux_Z[6]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3197), .Q(d_ff2_Z[6]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(
add_subt_module_Oper_Start_in_module_intm[6]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3168),
.Q(add_subt_module_DmP[6]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(
add_subt_module_Oper_Start_in_module_intM[6]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3182),
.Q(add_subt_module_DMP[6]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ (
.D(add_subt_module_final_result_ieee_Module_Sign_S_mux), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3162), .QN(n1316) );
DFFRXLTS d_ff4_Xn_Q_reg_63_ ( .D(n1389), .CK(d_ff4_Xn_net3719139), .RN(n3195), .Q(d_ff_Xn[63]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_63_ ( .D(first_mux_X[63]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3202), .Q(d_ff2_X[63]) );
DFFRXLTS reg_shift_x_Q_reg_63_ ( .D(d_ff2_X[63]), .CK(reg_shift_y_net3719139), .RN(n3202), .Q(d_ff3_sh_x_out[63]) );
DFFRXLTS d_ff4_Yn_Q_reg_63_ ( .D(n1389), .CK(d_ff4_Yn_net3719139), .RN(n3218), .Q(d_ff_Yn[63]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_63_ ( .D(first_mux_Y[63]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3219), .Q(d_ff2_Y[63]) );
DFFRXLTS reg_shift_y_Q_reg_63_ ( .D(d_ff2_Y[63]), .CK(reg_shift_y_net3719139), .RN(n3209), .Q(d_ff3_sh_y_out[63]) );
DFFRXLTS d_ff5_Q_reg_63_ ( .D(mux_sal[63]), .CK(d_ff5_net3719139), .RN(n3230), .Q(data_output2_63_) );
DFFRXLTS d_ff5_data_out_Q_reg_63_ ( .D(sign_inv_out[63]), .CK(
d_ff5_data_out_net3719139), .RN(n3230), .Q(data_output[63]) );
DFFRXLTS d_ff4_Zn_Q_reg_63_ ( .D(n1389), .CK(d_ff4_Zn_net3719139), .RN(n3230), .Q(d_ff_Zn[63]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_63_ ( .D(first_mux_Z[63]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3202), .Q(d_ff2_Z[63]) );
DFFRXLTS reg_sign_Q_reg_0_ ( .D(d_ff2_Z[63]), .CK(reg_shift_y_net3719139),
.RN(n3202), .Q(d_ff3_sign_out) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[2]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3169), .QN(n1315) );
DFFRXLTS d_ff4_Xn_Q_reg_2_ ( .D(n1388), .CK(d_ff4_Xn_net3719139), .RN(n3218),
.Q(d_ff_Xn[2]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_2_ ( .D(first_mux_X[2]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3238), .Q(d_ff2_X[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(d_ff2_X[2]), .CK(reg_shift_y_net3719139),
.RN(n3238), .Q(d_ff3_sh_x_out[2]) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(n1388), .CK(d_ff4_Yn_net3719139), .RN(n3238),
.Q(d_ff_Yn[2]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_2_ ( .D(first_mux_Y[2]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3230), .Q(d_ff2_Y[2]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(d_ff2_Y[2]), .CK(reg_shift_y_net3719139),
.RN(n3230), .Q(d_ff3_sh_y_out[2]) );
DFFRXLTS d_ff5_Q_reg_2_ ( .D(mux_sal[2]), .CK(d_ff5_net3719139), .RN(n3216),
.Q(sign_inv_out[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(sign_inv_out[2]), .CK(
d_ff5_data_out_net3719139), .RN(n3215), .Q(data_output[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n1388), .CK(d_ff4_Zn_net3719139), .RN(n3215),
.Q(d_ff_Zn[2]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(first_mux_Z[2]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3215), .Q(d_ff2_Z[2]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(
add_subt_module_Oper_Start_in_module_intm[2]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3180),
.Q(add_subt_module_DmP[2]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(
add_subt_module_Oper_Start_in_module_intM[2]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3173),
.Q(add_subt_module_DMP[2]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[7]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3153), .QN(n1314) );
DFFRXLTS d_ff4_Xn_Q_reg_7_ ( .D(n1387), .CK(d_ff4_Xn_net3719139), .RN(n3215),
.Q(d_ff_Xn[7]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_7_ ( .D(first_mux_X[7]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3215), .Q(d_ff2_X[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(d_ff2_X[7]), .CK(reg_shift_y_net3719139),
.RN(n3215), .Q(d_ff3_sh_x_out[7]) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(n1387), .CK(d_ff4_Yn_net3719139), .RN(n3215),
.Q(d_ff_Yn[7]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_7_ ( .D(first_mux_Y[7]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3215), .Q(d_ff2_Y[7]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(d_ff2_Y[7]), .CK(reg_shift_y_net3719139),
.RN(n3215), .Q(d_ff3_sh_y_out[7]) );
DFFRXLTS d_ff5_Q_reg_7_ ( .D(mux_sal[7]), .CK(d_ff5_net3719139), .RN(n3215),
.Q(sign_inv_out[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(sign_inv_out[7]), .CK(
d_ff5_data_out_net3719139), .RN(n3215), .Q(data_output[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n1387), .CK(d_ff4_Zn_net3719139), .RN(n3215),
.Q(d_ff_Zn[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(first_mux_Z[7]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3214), .Q(d_ff2_Z[7]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(
add_subt_module_Oper_Start_in_module_intm[7]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3172),
.Q(add_subt_module_DmP[7]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(
add_subt_module_Oper_Start_in_module_intM[7]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3163),
.Q(add_subt_module_DMP[7]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[3]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3163), .QN(n1313) );
DFFRXLTS d_ff4_Xn_Q_reg_3_ ( .D(n1386), .CK(d_ff4_Xn_net3719139), .RN(n3214),
.Q(d_ff_Xn[3]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_3_ ( .D(first_mux_X[3]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3214), .Q(d_ff2_X[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(d_ff2_X[3]), .CK(reg_shift_y_net3719139),
.RN(n3214), .Q(d_ff3_sh_x_out[3]) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(n1386), .CK(d_ff4_Yn_net3719139), .RN(n3214),
.Q(d_ff_Yn[3]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_3_ ( .D(first_mux_Y[3]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3214), .Q(d_ff2_Y[3]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(d_ff2_Y[3]), .CK(reg_shift_y_net3719139),
.RN(n3214), .Q(d_ff3_sh_y_out[3]) );
DFFRXLTS d_ff5_Q_reg_3_ ( .D(mux_sal[3]), .CK(d_ff5_net3719139), .RN(n3214),
.Q(sign_inv_out[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(sign_inv_out[3]), .CK(
d_ff5_data_out_net3719139), .RN(n3214), .Q(data_output[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n1386), .CK(d_ff4_Zn_net3719139), .RN(n3214),
.Q(d_ff_Zn[3]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(first_mux_Z[3]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3214), .Q(d_ff2_Z[3]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(
add_subt_module_Oper_Start_in_module_intm[3]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3174),
.Q(add_subt_module_DmP[3]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(
add_subt_module_Oper_Start_in_module_intM[3]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3182),
.Q(add_subt_module_DMP[3]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[8]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3153), .QN(n1312) );
DFFRXLTS d_ff4_Xn_Q_reg_8_ ( .D(n1385), .CK(d_ff4_Xn_net3719139), .RN(n3214),
.Q(d_ff_Xn[8]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_8_ ( .D(first_mux_X[8]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3213), .Q(d_ff2_X[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(d_ff2_X[8]), .CK(reg_shift_y_net3719139),
.RN(n3213), .Q(d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(n1385), .CK(d_ff4_Yn_net3719139), .RN(n3213),
.Q(d_ff_Yn[8]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_8_ ( .D(first_mux_Y[8]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3213), .Q(d_ff2_Y[8]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(d_ff2_Y[8]), .CK(reg_shift_y_net3719139),
.RN(n3213), .Q(d_ff3_sh_y_out[8]) );
DFFRXLTS d_ff5_Q_reg_8_ ( .D(mux_sal[8]), .CK(d_ff5_net3719139), .RN(n3213),
.Q(sign_inv_out[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(sign_inv_out[8]), .CK(
d_ff5_data_out_net3719139), .RN(n3213), .Q(data_output[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n1385), .CK(d_ff4_Zn_net3719139), .RN(n3213),
.Q(d_ff_Zn[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(first_mux_Z[8]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3213), .Q(d_ff2_Z[8]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(
add_subt_module_Oper_Start_in_module_intm[8]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3156),
.Q(add_subt_module_DmP[8]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(
add_subt_module_Oper_Start_in_module_intM[8]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3163),
.Q(add_subt_module_DMP[8]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[0]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3174), .QN(n1362) );
DFFRXLTS d_ff4_Xn_Q_reg_0_ ( .D(n1384), .CK(d_ff4_Xn_net3719139), .RN(n3213),
.Q(d_ff_Xn[0]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_0_ ( .D(first_mux_X[0]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3213), .Q(d_ff2_X[0]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(d_ff2_X[0]), .CK(reg_shift_y_net3719139),
.RN(n3213), .Q(d_ff3_sh_x_out[0]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(n1384), .CK(d_ff4_Yn_net3719139), .RN(n3243),
.Q(d_ff_Yn[0]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_0_ ( .D(first_mux_Y[0]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3207), .Q(d_ff2_Y[0]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(d_ff2_Y[0]), .CK(reg_shift_y_net3719139),
.RN(n3211), .Q(d_ff3_sh_y_out[0]) );
DFFRXLTS d_ff5_Q_reg_0_ ( .D(mux_sal[0]), .CK(d_ff5_net3719139), .RN(n3211),
.Q(sign_inv_out[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(sign_inv_out[0]), .CK(
d_ff5_data_out_net3719139), .RN(n1301), .Q(data_output[0]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n1384), .CK(d_ff4_Zn_net3719139), .RN(n1301),
.Q(d_ff_Zn[0]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(first_mux_Z[0]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3240), .Q(d_ff2_Z[0]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(
add_subt_module_Oper_Start_in_module_intm[0]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3156),
.Q(add_subt_module_DmP[0]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(
add_subt_module_Oper_Start_in_module_intM[0]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3162),
.Q(add_subt_module_DMP[0]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[4]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3174), .QN(n1361) );
DFFRXLTS d_ff4_Xn_Q_reg_4_ ( .D(n1383), .CK(d_ff4_Xn_net3719139), .RN(n1301),
.Q(d_ff_Xn[4]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_4_ ( .D(first_mux_X[4]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n1301), .Q(d_ff2_X[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(d_ff2_X[4]), .CK(reg_shift_y_net3719139),
.RN(n1301), .Q(d_ff3_sh_x_out[4]) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(n1383), .CK(d_ff4_Yn_net3719139), .RN(n1301),
.Q(d_ff_Yn[4]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_4_ ( .D(first_mux_Y[4]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3227), .Q(d_ff2_Y[4]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(d_ff2_Y[4]), .CK(reg_shift_y_net3719139),
.RN(n3224), .Q(d_ff3_sh_y_out[4]) );
DFFRXLTS d_ff5_Q_reg_4_ ( .D(mux_sal[4]), .CK(d_ff5_net3719139), .RN(n3212),
.Q(sign_inv_out[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(sign_inv_out[4]), .CK(
d_ff5_data_out_net3719139), .RN(n3224), .Q(data_output[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n1383), .CK(d_ff4_Zn_net3719139), .RN(n3212),
.Q(d_ff_Zn[4]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(first_mux_Z[4]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3224), .Q(d_ff2_Z[4]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(
add_subt_module_Oper_Start_in_module_intm[4]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3156),
.Q(add_subt_module_DmP[4]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(
add_subt_module_Oper_Start_in_module_intM[4]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3182),
.Q(add_subt_module_DMP[4]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[9]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3157), .QN(n1360) );
DFFRXLTS d_ff4_Xn_Q_reg_9_ ( .D(n1382), .CK(d_ff4_Xn_net3719139), .RN(n3212),
.Q(d_ff_Xn[9]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_9_ ( .D(first_mux_X[9]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3224), .Q(d_ff2_X[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(d_ff2_X[9]), .CK(reg_shift_y_net3719139),
.RN(n3212), .Q(d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(n1382), .CK(d_ff4_Yn_net3719139), .RN(n3224),
.Q(d_ff_Yn[9]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_9_ ( .D(first_mux_Y[9]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3212), .Q(d_ff2_Y[9]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(d_ff2_Y[9]), .CK(reg_shift_y_net3719139),
.RN(n3224), .Q(d_ff3_sh_y_out[9]) );
DFFRXLTS d_ff5_Q_reg_9_ ( .D(mux_sal[9]), .CK(d_ff5_net3719139), .RN(n3212),
.Q(sign_inv_out[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(sign_inv_out[9]), .CK(
d_ff5_data_out_net3719139), .RN(n3211), .Q(data_output[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n1382), .CK(d_ff4_Zn_net3719139), .RN(n3211),
.Q(d_ff_Zn[9]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(first_mux_Z[9]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3211), .Q(d_ff2_Z[9]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(
add_subt_module_Oper_Start_in_module_intm[9]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3157),
.Q(add_subt_module_DmP[9]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(
add_subt_module_Oper_Start_in_module_intM[9]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3163),
.Q(add_subt_module_DMP[9]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[1]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3157), .QN(n1359) );
DFFRXLTS d_ff4_Xn_Q_reg_1_ ( .D(n1381), .CK(d_ff4_Xn_net3719139), .RN(n3211),
.Q(d_ff_Xn[1]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_1_ ( .D(first_mux_X[1]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3211), .Q(d_ff2_X[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(d_ff2_X[1]), .CK(reg_shift_y_net3719139),
.RN(n3211), .Q(d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(n1381), .CK(d_ff4_Yn_net3719139), .RN(n3211),
.Q(d_ff_Yn[1]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_1_ ( .D(first_mux_Y[1]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3211), .Q(d_ff2_Y[1]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(d_ff2_Y[1]), .CK(reg_shift_y_net3719139),
.RN(n3211), .Q(d_ff3_sh_y_out[1]) );
DFFRXLTS d_ff5_Q_reg_1_ ( .D(mux_sal[1]), .CK(d_ff5_net3719139), .RN(n3211),
.Q(sign_inv_out[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(sign_inv_out[1]), .CK(
d_ff5_data_out_net3719139), .RN(n3211), .Q(data_output[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n1381), .CK(d_ff4_Zn_net3719139), .RN(n3211),
.Q(d_ff_Zn[1]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(first_mux_Z[1]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3210), .Q(d_ff2_Z[1]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(
add_subt_module_Oper_Start_in_module_intm[1]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3157),
.Q(add_subt_module_DmP[1]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(
add_subt_module_Oper_Start_in_module_intM[1]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3166),
.Q(add_subt_module_DMP[1]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[5]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3157), .QN(n1358) );
DFFRXLTS d_ff4_Xn_Q_reg_5_ ( .D(n1380), .CK(d_ff4_Xn_net3719139), .RN(n3210),
.Q(d_ff_Xn[5]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_5_ ( .D(first_mux_X[5]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3210), .Q(d_ff2_X[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(d_ff2_X[5]), .CK(reg_shift_y_net3719139),
.RN(n3210), .Q(d_ff3_sh_x_out[5]) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(n1380), .CK(d_ff4_Yn_net3719139), .RN(n3210),
.Q(d_ff_Yn[5]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_5_ ( .D(first_mux_Y[5]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3210), .Q(d_ff2_Y[5]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(d_ff2_Y[5]), .CK(reg_shift_y_net3719139),
.RN(n3210), .Q(d_ff3_sh_y_out[5]) );
DFFRXLTS d_ff5_Q_reg_5_ ( .D(mux_sal[5]), .CK(d_ff5_net3719139), .RN(n3210),
.Q(sign_inv_out[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(sign_inv_out[5]), .CK(
d_ff5_data_out_net3719139), .RN(n3210), .Q(data_output[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n1380), .CK(d_ff4_Zn_net3719139), .RN(n3210),
.Q(d_ff_Zn[5]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(first_mux_Z[5]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3210), .Q(d_ff2_Z[5]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(
add_subt_module_Oper_Start_in_module_intm[5]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3158),
.Q(add_subt_module_DmP[5]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(
add_subt_module_Oper_Start_in_module_intM[5]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3174),
.Q(add_subt_module_DMP[5]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_40_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]),
.CK(clk), .RN(n3177), .QN(n1350) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[12]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3159), .QN(n1357) );
DFFRXLTS d_ff4_Xn_Q_reg_12_ ( .D(n1379), .CK(d_ff4_Xn_net3719139), .RN(n3210), .Q(d_ff_Xn[12]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_12_ ( .D(first_mux_X[12]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3209), .Q(d_ff2_X[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(d_ff2_X[12]), .CK(reg_shift_y_net3719139), .RN(n3209), .Q(d_ff3_sh_x_out[12]) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(n1379), .CK(d_ff4_Yn_net3719139), .RN(n3209), .Q(d_ff_Yn[12]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_12_ ( .D(first_mux_Y[12]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3209), .Q(d_ff2_Y[12]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(d_ff2_Y[12]), .CK(reg_shift_y_net3719139), .RN(n3209), .Q(d_ff3_sh_y_out[12]) );
DFFRXLTS d_ff5_Q_reg_12_ ( .D(mux_sal[12]), .CK(d_ff5_net3719139), .RN(n3209), .Q(sign_inv_out[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(sign_inv_out[12]), .CK(
d_ff5_data_out_net3719139), .RN(n3209), .Q(data_output[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n1379), .CK(d_ff4_Zn_net3719139), .RN(n3209), .Q(d_ff_Zn[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(first_mux_Z[12]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3209), .Q(d_ff2_Z[12]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(
add_subt_module_Oper_Start_in_module_intm[12]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3158),
.Q(add_subt_module_DmP[12]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(
add_subt_module_Oper_Start_in_module_intM[12]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3163),
.Q(add_subt_module_DMP[12]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[10]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3177), .QN(n1356) );
DFFRXLTS d_ff4_Xn_Q_reg_10_ ( .D(n1378), .CK(d_ff4_Xn_net3719139), .RN(n3209), .Q(d_ff_Xn[10]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_10_ ( .D(first_mux_X[10]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3209), .Q(d_ff2_X[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(d_ff2_X[10]), .CK(reg_shift_y_net3719139), .RN(n3223), .Q(d_ff3_sh_x_out[10]) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(n1378), .CK(d_ff4_Yn_net3719139), .RN(n3208), .Q(d_ff_Yn[10]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_10_ ( .D(first_mux_Y[10]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3223), .Q(d_ff2_Y[10]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(d_ff2_Y[10]), .CK(reg_shift_y_net3719139), .RN(n3208), .Q(d_ff3_sh_y_out[10]) );
DFFRXLTS d_ff5_Q_reg_10_ ( .D(mux_sal[10]), .CK(d_ff5_net3719139), .RN(n3223), .Q(sign_inv_out[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(sign_inv_out[10]), .CK(
d_ff5_data_out_net3719139), .RN(n3208), .Q(data_output[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n1378), .CK(d_ff4_Zn_net3719139), .RN(n3223), .Q(d_ff_Zn[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(first_mux_Z[10]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3208), .Q(d_ff2_Z[10]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(
add_subt_module_Oper_Start_in_module_intm[10]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3159),
.Q(add_subt_module_DmP[10]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(
add_subt_module_Oper_Start_in_module_intM[10]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3163),
.Q(add_subt_module_DMP[10]) );
DFFRXLTS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[11]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3159), .QN(n1355) );
DFFRXLTS d_ff4_Xn_Q_reg_11_ ( .D(n1377), .CK(d_ff4_Xn_net3719139), .RN(n3223), .Q(d_ff_Xn[11]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_11_ ( .D(first_mux_X[11]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3208), .Q(d_ff2_X[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(d_ff2_X[11]), .CK(reg_shift_y_net3719139), .RN(n3223), .Q(d_ff3_sh_x_out[11]) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(n1377), .CK(d_ff4_Yn_net3719139), .RN(n3208), .Q(d_ff_Yn[11]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_11_ ( .D(first_mux_Y[11]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3207), .Q(d_ff2_Y[11]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(d_ff2_Y[11]), .CK(reg_shift_y_net3719139), .RN(n3207), .Q(d_ff3_sh_y_out[11]) );
DFFRXLTS d_ff5_Q_reg_11_ ( .D(mux_sal[11]), .CK(d_ff5_net3719139), .RN(n3207), .Q(sign_inv_out[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(sign_inv_out[11]), .CK(
d_ff5_data_out_net3719139), .RN(n3207), .Q(data_output[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n1377), .CK(d_ff4_Zn_net3719139), .RN(n3207), .Q(d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(first_mux_Z[11]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3207), .Q(d_ff2_Z[11]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(
add_subt_module_Oper_Start_in_module_intm[11]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3158),
.Q(add_subt_module_DmP[11]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(
add_subt_module_Oper_Start_in_module_intM[11]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3163),
.Q(add_subt_module_DMP[11]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_37_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]),
.CK(clk), .RN(n3177), .QN(n1352) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[25]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3171), .QN(n1306) );
DFFRXLTS d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Xn_net3719139), .RN(n3207), .Q(d_ff_Xn[23]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_23_ ( .D(first_mux_X[23]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3207), .Q(d_ff2_X[23]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(d_ff2_X[23]), .CK(reg_shift_y_net3719139), .RN(n3207), .Q(d_ff3_sh_x_out[23]) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Yn_net3719139), .RN(n3207), .Q(d_ff_Yn[23]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_23_ ( .D(first_mux_Y[23]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3207), .Q(d_ff2_Y[23]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(d_ff2_Y[23]), .CK(reg_shift_y_net3719139), .RN(n3207), .Q(d_ff3_sh_y_out[23]) );
DFFRXLTS d_ff5_Q_reg_23_ ( .D(mux_sal[23]), .CK(d_ff5_net3719139), .RN(n3206), .Q(sign_inv_out[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(sign_inv_out[23]), .CK(
d_ff5_data_out_net3719139), .RN(n3206), .Q(data_output[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Zn_net3719139), .RN(n3206), .Q(d_ff_Zn[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(first_mux_Z[23]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3206), .Q(d_ff2_Z[23]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(
add_subt_module_Oper_Start_in_module_intm[23]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3177),
.Q(add_subt_module_DmP[23]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(
add_subt_module_Oper_Start_in_module_intM[23]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3171),
.Q(add_subt_module_DMP[23]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_38_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]),
.CK(clk), .RN(n3159), .QN(n1351) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[24]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3156), .QN(n1305) );
DFFRXLTS d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Xn_net3719139), .RN(n3206), .Q(d_ff_Xn[22]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_22_ ( .D(first_mux_X[22]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3206), .Q(d_ff2_X[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(d_ff2_X[22]), .CK(reg_shift_y_net3719139), .RN(n3206), .Q(d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Yn_net3719139), .RN(n3206), .Q(d_ff_Yn[22]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_22_ ( .D(first_mux_Y[22]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3206), .Q(d_ff2_Y[22]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(d_ff2_Y[22]), .CK(reg_shift_y_net3719139), .RN(n3206), .Q(d_ff3_sh_y_out[22]) );
DFFRXLTS d_ff5_Q_reg_22_ ( .D(mux_sal[22]), .CK(d_ff5_net3719139), .RN(n3206), .Q(sign_inv_out[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(sign_inv_out[22]), .CK(
d_ff5_data_out_net3719139), .RN(n3206), .Q(data_output[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Zn_net3719139), .RN(n3205), .Q(d_ff_Zn[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(first_mux_Z[22]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3205), .Q(d_ff2_Z[22]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(
add_subt_module_Oper_Start_in_module_intm[22]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3160),
.Q(add_subt_module_DmP[22]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(
add_subt_module_Oper_Start_in_module_intM[22]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3149),
.Q(add_subt_module_DMP[22]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[30]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3179), .QN(n1331) );
DFFRXLTS d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Xn_net3719139), .RN(n3205), .Q(d_ff_Xn[28]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_28_ ( .D(first_mux_X[28]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3205), .Q(d_ff2_X[28]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(d_ff2_X[28]), .CK(reg_shift_y_net3719139), .RN(n3205), .Q(d_ff3_sh_x_out[28]) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Yn_net3719139), .RN(n3205), .Q(d_ff_Yn[28]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_28_ ( .D(first_mux_Y[28]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3205), .Q(d_ff2_Y[28]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(d_ff2_Y[28]), .CK(reg_shift_y_net3719139), .RN(n3205), .Q(d_ff3_sh_y_out[28]) );
DFFRXLTS d_ff5_Q_reg_28_ ( .D(mux_sal[28]), .CK(d_ff5_net3719139), .RN(n3205), .Q(sign_inv_out[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(sign_inv_out[28]), .CK(
d_ff5_data_out_net3719139), .RN(n3205), .Q(data_output[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Zn_net3719139), .RN(n3205), .Q(d_ff_Zn[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(first_mux_Z[28]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3205), .Q(d_ff2_Z[28]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(
add_subt_module_Oper_Start_in_module_intm[28]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3160),
.Q(add_subt_module_DmP[28]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(
add_subt_module_Oper_Start_in_module_intM[28]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3165),
.Q(add_subt_module_DMP[28]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_34_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[34]),
.CK(clk), .RN(n3160), .QN(n1354) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[20]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3164), .QN(n1326) );
DFFRXLTS d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Xn_net3719139), .RN(n3204), .Q(d_ff_Xn[18]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_18_ ( .D(first_mux_X[18]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3204), .Q(d_ff2_X[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(d_ff2_X[18]), .CK(reg_shift_y_net3719139), .RN(n3204), .Q(d_ff3_sh_x_out[18]) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Yn_net3719139), .RN(n3204), .Q(d_ff_Yn[18]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_18_ ( .D(first_mux_Y[18]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3204), .Q(d_ff2_Y[18]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(d_ff2_Y[18]), .CK(reg_shift_y_net3719139), .RN(n3204), .Q(d_ff3_sh_y_out[18]) );
DFFRXLTS d_ff5_Q_reg_18_ ( .D(mux_sal[18]), .CK(d_ff5_net3719139), .RN(n3204), .Q(sign_inv_out[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(sign_inv_out[18]), .CK(
d_ff5_data_out_net3719139), .RN(n3204), .Q(data_output[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Zn_net3719139), .RN(n3204), .Q(d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(first_mux_Z[18]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3204), .Q(d_ff2_Z[18]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(
add_subt_module_Oper_Start_in_module_intm[18]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3160),
.Q(add_subt_module_DmP[18]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(
add_subt_module_Oper_Start_in_module_intM[18]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3164),
.Q(add_subt_module_DMP[18]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(
n3276), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3149), .QN(n1304) );
DFFRXLTS d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Xn_net3719139), .RN(n3204), .Q(d_ff_Xn[21]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_21_ ( .D(first_mux_X[21]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3204), .Q(d_ff2_X[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(d_ff2_X[21]), .CK(reg_shift_y_net3719139), .RN(n3203), .Q(d_ff3_sh_x_out[21]) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Yn_net3719139), .RN(n3203), .Q(d_ff_Yn[21]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_21_ ( .D(first_mux_Y[21]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3203), .Q(d_ff2_Y[21]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(d_ff2_Y[21]), .CK(reg_shift_y_net3719139), .RN(n3203), .Q(d_ff3_sh_y_out[21]) );
DFFRXLTS d_ff5_Q_reg_21_ ( .D(mux_sal[21]), .CK(d_ff5_net3719139), .RN(n3203), .Q(sign_inv_out[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(sign_inv_out[21]), .CK(
d_ff5_data_out_net3719139), .RN(n3203), .Q(data_output[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Zn_net3719139), .RN(n3203), .Q(d_ff_Zn[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(first_mux_Z[21]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3231), .Q(d_ff2_Z[21]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(
add_subt_module_Oper_Start_in_module_intm[21]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3161),
.Q(add_subt_module_DmP[21]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(
add_subt_module_Oper_Start_in_module_intM[21]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3150),
.Q(add_subt_module_DMP[21]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(
n3275), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3165), .QN(n1332) );
DFFRXLTS d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Xn_net3719139), .RN(n3203), .Q(d_ff_Xn[29]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_29_ ( .D(first_mux_X[29]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3222), .Q(d_ff2_X[29]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(d_ff2_X[29]), .CK(reg_shift_y_net3719139), .RN(n3231), .Q(d_ff3_sh_x_out[29]) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Yn_net3719139), .RN(n3203), .Q(d_ff_Yn[29]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_29_ ( .D(first_mux_Y[29]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3202), .Q(d_ff2_Y[29]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(d_ff2_Y[29]), .CK(reg_shift_y_net3719139), .RN(n3202), .Q(d_ff3_sh_y_out[29]) );
DFFRXLTS d_ff5_Q_reg_29_ ( .D(mux_sal[29]), .CK(d_ff5_net3719139), .RN(n3202), .Q(sign_inv_out[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(sign_inv_out[29]), .CK(
d_ff5_data_out_net3719139), .RN(n3202), .Q(data_output[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Zn_net3719139), .RN(n3202), .Q(d_ff_Zn[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(first_mux_Z[29]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3202), .Q(d_ff2_Z[29]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(
add_subt_module_Oper_Start_in_module_intm[29]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3161),
.Q(add_subt_module_DmP[29]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(
add_subt_module_Oper_Start_in_module_intM[29]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3165),
.Q(add_subt_module_DMP[29]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(
add_subt_module_Oper_Start_in_module_intm[25]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3161),
.Q(add_subt_module_DmP[25]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(
add_subt_module_Oper_Start_in_module_intM[25]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3165),
.Q(add_subt_module_DMP[25]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(
add_subt_module_Oper_Start_in_module_intM[20]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3156),
.Q(add_subt_module_DMP[20]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(
add_subt_module_Oper_Start_in_module_intM[13]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3164),
.Q(add_subt_module_DMP[13]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_36_ ( .D(
add_subt_module_Oper_Start_in_module_intM[36]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3166),
.Q(add_subt_module_DMP[36]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(
add_subt_module_Oper_Start_in_module_intM[27]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3165),
.Q(add_subt_module_DMP[27]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(
add_subt_module_Oper_Start_in_module_intM[24]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3154),
.Q(add_subt_module_DMP[24]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(
add_subt_module_Oper_Start_in_module_intM[17]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3164),
.Q(add_subt_module_DMP[17]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(
add_subt_module_Oper_Start_in_module_intM[26]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3165),
.Q(add_subt_module_DMP[26]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(
add_subt_module_Oper_Start_in_module_intM[19]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3150),
.Q(add_subt_module_DMP[19]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_34_ ( .D(
add_subt_module_Oper_Start_in_module_intM[34]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3166),
.Q(add_subt_module_DMP[34]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[14]),
.CK(clk), .RN(n3168), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[69]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_31_ ( .D(
add_subt_module_Oper_Start_in_module_intM[31]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3166),
.Q(add_subt_module_DMP[31]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_38_ ( .D(
add_subt_module_Oper_Start_in_module_intM[38]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3167),
.Q(add_subt_module_DMP[38]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(
add_subt_module_Oper_Start_in_module_intM[15]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3164),
.Q(add_subt_module_DMP[15]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_32_ ( .D(
add_subt_module_Oper_Start_in_module_intM[32]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3166),
.Q(add_subt_module_DMP[32]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_41_ ( .D(
add_subt_module_Oper_Start_in_module_intM[41]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3167),
.Q(add_subt_module_DMP[41]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[7]),
.CK(clk), .RN(n3162), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[62]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_39_ ( .D(
add_subt_module_Oper_Start_in_module_intM[39]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3167),
.Q(add_subt_module_DMP[39]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_37_ ( .D(
add_subt_module_Oper_Start_in_module_intM[37]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3167),
.Q(add_subt_module_DMP[37]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_44_ ( .D(
add_subt_module_Oper_Start_in_module_intM[44]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3246),
.Q(add_subt_module_DMP[44]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[4]),
.CK(clk), .RN(n3180), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[59]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[6]),
.CK(clk), .RN(n3168), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[61]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_43_ ( .D(
add_subt_module_Oper_Start_in_module_intM[43]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3179),
.Q(add_subt_module_DMP[43]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_40_ ( .D(
add_subt_module_Oper_Start_in_module_intM[40]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3167),
.Q(add_subt_module_DMP[40]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_33_ ( .D(
add_subt_module_Oper_Start_in_module_intM[33]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3166),
.Q(add_subt_module_DMP[33]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_48_ ( .D(
add_subt_module_Oper_Start_in_module_intM[48]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3179),
.Q(add_subt_module_DMP[48]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_49_ ( .D(
add_subt_module_Oper_Start_in_module_intM[49]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3184),
.Q(add_subt_module_DMP[49]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_42_ ( .D(
add_subt_module_Oper_Start_in_module_intM[42]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3167),
.Q(add_subt_module_DMP[42]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_35_ ( .D(
add_subt_module_Oper_Start_in_module_intM[35]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3166),
.Q(add_subt_module_DMP[35]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_50_ ( .D(
add_subt_module_Oper_Start_in_module_intM[50]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3246),
.Q(add_subt_module_DMP[50]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_47_ ( .D(
add_subt_module_Oper_Start_in_module_intM[47]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3174),
.Q(add_subt_module_DMP[47]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_46_ ( .D(
add_subt_module_Oper_Start_in_module_intM[46]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3152),
.Q(add_subt_module_DMP[46]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[1]),
.CK(clk), .RN(n3162), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[56]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_53_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[53]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3150), .QN(n1347) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_51_ ( .D(
add_subt_module_Oper_Start_in_module_intM[51]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3172),
.Q(add_subt_module_DMP[51]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_45_ ( .D(
add_subt_module_Oper_Start_in_module_intM[45]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3178),
.Q(add_subt_module_DMP[45]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(
add_subt_module_Oper_Start_in_module_intM[30]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3719229), .RN(n3165),
.Q(add_subt_module_DMP[30]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_54_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[54]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3246), .Q(add_subt_module_Sgf_normalized_result[54]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(
n3270), .CK(add_subt_module_Oper_Start_in_module_MRegister_net3719229),
.RN(n3156), .Q(add_subt_module_sign_final_result), .QN(n1450) );
SNPS_CLOCK_GATE_HIGH_CORDIC_Arch2_W64_EW11_SW52_SWR55_EWR6_1 clk_gate_reg_ch_mux_2_Q_reg (
.CLK(clk), .EN(n3269), .ENCLK(n3267), .TE(1'b0) );
CMPR32X2TS DP_OP_92J185_122_9081_U9 ( .A(DP_OP_92J185_122_9081_n23), .B(
add_subt_module_S_Oper_A_exp[3]), .C(DP_OP_92J185_122_9081_n9), .CO(
DP_OP_92J185_122_9081_n8), .S(
add_subt_module_Exp_Operation_Module_Data_S[3]) );
CMPR32X2TS DP_OP_92J185_122_9081_U8 ( .A(DP_OP_92J185_122_9081_n22), .B(
add_subt_module_S_Oper_A_exp[4]), .C(DP_OP_92J185_122_9081_n8), .CO(
DP_OP_92J185_122_9081_n7), .S(
add_subt_module_Exp_Operation_Module_Data_S[4]) );
CMPR32X2TS DP_OP_92J185_122_9081_U7 ( .A(DP_OP_92J185_122_9081_n21), .B(
add_subt_module_S_Oper_A_exp[5]), .C(DP_OP_92J185_122_9081_n7), .CO(
DP_OP_92J185_122_9081_n6), .S(
add_subt_module_Exp_Operation_Module_Data_S[5]) );
CMPR32X2TS DP_OP_92J185_122_9081_U6 ( .A(DP_OP_92J185_122_9081_n20), .B(
add_subt_module_S_Oper_A_exp[6]), .C(DP_OP_92J185_122_9081_n6), .CO(
DP_OP_92J185_122_9081_n5), .S(
add_subt_module_Exp_Operation_Module_Data_S[6]) );
CMPR32X2TS DP_OP_92J185_122_9081_U5 ( .A(DP_OP_92J185_122_9081_n19), .B(
add_subt_module_S_Oper_A_exp[7]), .C(DP_OP_92J185_122_9081_n5), .CO(
DP_OP_92J185_122_9081_n4), .S(
add_subt_module_Exp_Operation_Module_Data_S[7]) );
CMPR32X2TS DP_OP_92J185_122_9081_U4 ( .A(DP_OP_92J185_122_9081_n18), .B(
add_subt_module_S_Oper_A_exp[8]), .C(DP_OP_92J185_122_9081_n4), .CO(
DP_OP_92J185_122_9081_n3), .S(
add_subt_module_Exp_Operation_Module_Data_S[8]) );
CMPR32X2TS DP_OP_92J185_122_9081_U3 ( .A(DP_OP_92J185_122_9081_n17), .B(
add_subt_module_S_Oper_A_exp[9]), .C(DP_OP_92J185_122_9081_n3), .CO(
DP_OP_92J185_122_9081_n2), .S(
add_subt_module_Exp_Operation_Module_Data_S[9]) );
DFFRXLTS reg_LUT_Q_reg_48_ ( .D(1'b1), .CK(reg_shift_y_net3719139), .RN(
n3209), .Q(d_ff3_LUT_out[48]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n1151),
.CK(add_subt_module_Exp_Operation_Module_exp_result_net3719211), .RN(
n3162), .Q(underflow_flag), .QN(n3141) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(shift_region_flag[0]), .CK(
reg_Z0_net3719139), .RN(n3240), .Q(d_ff1_shift_region_flag_out[0]),
.QN(n3139) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[6]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3171), .Q(add_subt_module_Add_Subt_result[6]), .QN(n3138) );
DFFRX1TS cont_var_count_reg_1_ ( .D(n1145), .CK(n3267), .RN(n3214), .Q(
cont_var_out[1]), .QN(n3135) );
DFFRX2TS add_subt_module_XRegister_Q_reg_23_ ( .D(n1183), .CK(
add_subt_module_YRegister_net3719157), .RN(n3158), .Q(
add_subt_module_intDX[23]), .QN(n3133) );
DFFRX1TS add_subt_module_YRegister_Q_reg_61_ ( .D(n1285), .CK(
add_subt_module_YRegister_net3719157), .RN(n3163), .Q(
add_subt_module_intDY[61]), .QN(n3131) );
DFFRX2TS add_subt_module_YRegister_Q_reg_5_ ( .D(n1229), .CK(
add_subt_module_YRegister_net3719157), .RN(n3174), .Q(
add_subt_module_intDY[5]), .QN(n3129) );
DFFRX2TS add_subt_module_YRegister_Q_reg_7_ ( .D(n1231), .CK(
add_subt_module_YRegister_net3719157), .RN(n3174), .Q(
add_subt_module_intDY[7]), .QN(n3127) );
DFFRX1TS add_subt_module_YRegister_Q_reg_40_ ( .D(n1264), .CK(
add_subt_module_YRegister_net3719157), .RN(n3154), .Q(
add_subt_module_intDY[40]), .QN(n3116) );
DFFRX1TS add_subt_module_YRegister_Q_reg_42_ ( .D(n1266), .CK(
add_subt_module_YRegister_net3719157), .RN(n3154), .Q(
add_subt_module_intDY[42]), .QN(n3112) );
DFFRX1TS add_subt_module_YRegister_Q_reg_59_ ( .D(n1283), .CK(
add_subt_module_YRegister_net3719157), .RN(n3181), .Q(
add_subt_module_intDY[59]), .QN(n3110) );
DFFRX1TS add_subt_module_YRegister_Q_reg_51_ ( .D(n1275), .CK(
add_subt_module_YRegister_net3719157), .RN(n3184), .Q(
add_subt_module_intDY[51]), .QN(n3109) );
DFFRX1TS add_subt_module_YRegister_Q_reg_48_ ( .D(n1272), .CK(
add_subt_module_YRegister_net3719157), .RN(n3170), .Q(
add_subt_module_intDY[48]), .QN(n3103) );
DFFRX1TS add_subt_module_YRegister_Q_reg_44_ ( .D(n1268), .CK(
add_subt_module_YRegister_net3719157), .RN(n3178), .Q(
add_subt_module_intDY[44]), .QN(n3102) );
DFFRX1TS add_subt_module_YRegister_Q_reg_28_ ( .D(n1252), .CK(
add_subt_module_YRegister_net3719157), .RN(n3160), .Q(
add_subt_module_intDY[28]), .QN(n3100) );
DFFRX1TS add_subt_module_YRegister_Q_reg_58_ ( .D(n1282), .CK(
add_subt_module_YRegister_net3719157), .RN(n3181), .Q(
add_subt_module_intDY[58]), .QN(n3097) );
DFFRX1TS add_subt_module_YRegister_Q_reg_60_ ( .D(n1284), .CK(
add_subt_module_YRegister_net3719157), .RN(n3152), .Q(
add_subt_module_intDY[60]), .QN(n3095) );
DFFRX1TS add_subt_module_YRegister_Q_reg_36_ ( .D(n1260), .CK(
add_subt_module_YRegister_net3719157), .RN(n3155), .Q(
add_subt_module_intDY[36]), .QN(n3093) );
DFFRX1TS add_subt_module_YRegister_Q_reg_57_ ( .D(n1281), .CK(
add_subt_module_YRegister_net3719157), .RN(n3181), .Q(
add_subt_module_intDY[57]), .QN(n3092) );
DFFRX1TS add_subt_module_YRegister_Q_reg_49_ ( .D(n1273), .CK(
add_subt_module_YRegister_net3719157), .RN(n3183), .Q(
add_subt_module_intDY[49]), .QN(n3091) );
DFFRX1TS add_subt_module_YRegister_Q_reg_46_ ( .D(n1270), .CK(
add_subt_module_YRegister_net3719157), .RN(n3170), .Q(
add_subt_module_intDY[46]), .QN(n3087) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[21]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3172), .Q(add_subt_module_Add_Subt_result[21]), .QN(n3086) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_42_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[42]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3156), .Q(add_subt_module_Add_Subt_result[42]), .QN(n3085) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_27_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[27]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3172), .Q(add_subt_module_Add_Subt_result[27]), .QN(n3084) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[18]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3172), .Q(add_subt_module_Add_Subt_result[18]), .QN(n3083) );
DFFRX1TS reg_ch_mux_2_Q_reg_0_ ( .D(n1139), .CK(n3267), .RN(n3187), .Q(
sel_mux_2_reg[0]), .QN(n3082) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_51_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[51]),
.CK(clk), .RN(n3156), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[99]), .QN(
n3081) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[14]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3171), .Q(add_subt_module_Add_Subt_result[14]), .QN(n3079) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_32_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[32]),
.CK(clk), .RN(n3158), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[86]), .QN(
n3078) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[23]),
.CK(clk), .RN(n3161), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[77]), .QN(
n3077) );
DFFRX2TS add_subt_module_YRegister_Q_reg_29_ ( .D(n1253), .CK(
add_subt_module_YRegister_net3719157), .RN(n3161), .Q(
add_subt_module_intDY[29]), .QN(n3076) );
DFFRX2TS add_subt_module_YRegister_Q_reg_21_ ( .D(n1245), .CK(
add_subt_module_YRegister_net3719157), .RN(n3161), .Q(
add_subt_module_intDY[21]), .QN(n3075) );
DFFRX2TS add_subt_module_YRegister_Q_reg_15_ ( .D(n1239), .CK(
add_subt_module_YRegister_net3719157), .RN(n3168), .Q(
add_subt_module_intDY[15]), .QN(n3074) );
DFFRX2TS add_subt_module_YRegister_Q_reg_13_ ( .D(n1237), .CK(
add_subt_module_YRegister_net3719157), .RN(n3168), .Q(
add_subt_module_intDY[13]), .QN(n3073) );
DFFRX2TS add_subt_module_YRegister_Q_reg_41_ ( .D(n1265), .CK(
add_subt_module_YRegister_net3719157), .RN(n3170), .Q(
add_subt_module_intDY[41]), .QN(n3072) );
DFFRX2TS add_subt_module_YRegister_Q_reg_43_ ( .D(n1267), .CK(
add_subt_module_YRegister_net3719157), .RN(n3154), .Q(
add_subt_module_intDY[43]), .QN(n3071) );
DFFRX2TS add_subt_module_YRegister_Q_reg_35_ ( .D(n1259), .CK(
add_subt_module_YRegister_net3719157), .RN(n3155), .Q(
add_subt_module_intDY[35]), .QN(n3070) );
DFFRX2TS add_subt_module_YRegister_Q_reg_31_ ( .D(n1255), .CK(
add_subt_module_YRegister_net3719157), .RN(n3155), .Q(
add_subt_module_intDY[31]), .QN(n3069) );
DFFRX2TS add_subt_module_YRegister_Q_reg_33_ ( .D(n1257), .CK(
add_subt_module_YRegister_net3719157), .RN(n3154), .Q(
add_subt_module_intDY[33]), .QN(n3068) );
DFFRX2TS add_subt_module_YRegister_Q_reg_55_ ( .D(n1279), .CK(
add_subt_module_YRegister_net3719157), .RN(n3181), .Q(
add_subt_module_intDY[55]), .QN(n3067) );
DFFRX2TS add_subt_module_YRegister_Q_reg_3_ ( .D(n1227), .CK(
add_subt_module_YRegister_net3719157), .RN(n3172), .Q(
add_subt_module_intDY[3]), .QN(n3066) );
DFFRX2TS add_subt_module_YRegister_Q_reg_53_ ( .D(n1277), .CK(
add_subt_module_YRegister_net3719157), .RN(n3184), .Q(
add_subt_module_intDY[53]), .QN(n3065) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_31_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[31]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3183), .Q(add_subt_module_Add_Subt_result[31]), .QN(n3064) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_37_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[37]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3183), .Q(add_subt_module_Add_Subt_result[37]), .QN(n3063) );
DFFRX2TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[5]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3719211), .RN(n3183), .Q(add_subt_module_exp_oper_result[5]), .QN(n3062) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[11]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3171), .Q(add_subt_module_Add_Subt_result[11]), .QN(n3061) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[9]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3171), .Q(add_subt_module_Add_Subt_result[9]), .QN(n3060) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_51_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[51]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3174), .Q(add_subt_module_Add_Subt_result[51]), .QN(n3059) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_52_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[52]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3160), .Q(add_subt_module_Add_Subt_result[52]), .QN(n3058) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_46_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[46]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3246), .Q(add_subt_module_Add_Subt_result[46]), .QN(n3057) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_36_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[36]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3173), .Q(add_subt_module_Add_Subt_result[36]), .QN(n3056) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ (
.D(add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[3]), .CK(
add_subt_module_Leading_Zero_Detector_Module_Output_Reg_net3719175),
.RN(n3180), .Q(add_subt_module_LZA_output[3]), .QN(n3055) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_50_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[50]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3246), .Q(add_subt_module_Add_Subt_result[50]), .QN(n3054) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_26_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[26]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3172), .Q(add_subt_module_Add_Subt_result[26]), .QN(n3053) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_39_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]),
.CK(clk), .RN(n3246), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]), .QN(
n3052) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_43_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[43]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3246), .Q(add_subt_module_Add_Subt_result[43]), .QN(n3051) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_42_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]),
.CK(clk), .RN(n3158), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[90]), .QN(
n3049) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_44_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]),
.CK(clk), .RN(n3166), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[92]), .QN(
n3048) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_41_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]),
.CK(clk), .RN(n3177), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[89]), .QN(
n3047) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_45_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]),
.CK(clk), .RN(n3151), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[93]), .QN(
n3046) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_46_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]),
.CK(clk), .RN(n3150), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[94]), .QN(
n3045) );
DFFRX1TS reg_ch_mux_2_Q_reg_1_ ( .D(n1138), .CK(n3267), .RN(n3196), .Q(
sel_mux_2_reg[1]), .QN(n3044) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_34_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[34]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3173), .Q(add_subt_module_Add_Subt_result[34]), .QN(n3043) );
DFFRX2TS add_subt_module_XRegister_Q_reg_20_ ( .D(n1180), .CK(
add_subt_module_YRegister_net3719157), .RN(n3175), .Q(
add_subt_module_intDX[20]), .QN(n3042) );
DFFRX2TS add_subt_module_XRegister_Q_reg_14_ ( .D(n1174), .CK(
add_subt_module_YRegister_net3719157), .RN(n3162), .Q(
add_subt_module_intDX[14]), .QN(n3040) );
DFFRX2TS add_subt_module_XRegister_Q_reg_30_ ( .D(n1190), .CK(
add_subt_module_YRegister_net3719157), .RN(n3149), .Q(
add_subt_module_intDX[30]), .QN(n3036) );
DFFRX2TS add_subt_module_XRegister_Q_reg_28_ ( .D(n1188), .CK(
add_subt_module_YRegister_net3719157), .RN(n3160), .Q(
add_subt_module_intDX[28]), .QN(n3035) );
DFFRX2TS add_subt_module_XRegister_Q_reg_21_ ( .D(n1181), .CK(
add_subt_module_YRegister_net3719157), .RN(n3161), .Q(
add_subt_module_intDX[21]), .QN(n3034) );
DFFRX2TS add_subt_module_XRegister_Q_reg_41_ ( .D(n1201), .CK(
add_subt_module_YRegister_net3719157), .RN(n3152), .Q(
add_subt_module_intDX[41]), .QN(n3030) );
DFFRX2TS add_subt_module_XRegister_Q_reg_46_ ( .D(n1206), .CK(
add_subt_module_YRegister_net3719157), .RN(n3150), .Q(
add_subt_module_intDX[46]), .QN(n3019) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_5_ (
.D(add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[5]), .CK(
add_subt_module_Leading_Zero_Detector_Module_Output_Reg_net3719175),
.RN(n3170), .Q(add_subt_module_LZA_output[5]), .QN(n3014) );
DFFRX2TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ (
.D(add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[4]), .CK(
add_subt_module_Leading_Zero_Detector_Module_Output_Reg_net3719175),
.RN(n3162), .Q(add_subt_module_LZA_output[4]), .QN(n3013) );
DFFRX2TS add_subt_module_XRegister_Q_reg_29_ ( .D(n1189), .CK(
add_subt_module_YRegister_net3719157), .RN(n3161), .Q(
add_subt_module_intDX[29]), .QN(n3012) );
DFFRX2TS add_subt_module_XRegister_Q_reg_12_ ( .D(n1172), .CK(
add_subt_module_YRegister_net3719157), .RN(n3159), .Q(
add_subt_module_intDX[12]), .QN(n3009) );
DFFRX2TS add_subt_module_XRegister_Q_reg_13_ ( .D(n1173), .CK(
add_subt_module_YRegister_net3719157), .RN(n3182), .Q(
add_subt_module_intDX[13]), .QN(n3004) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[16]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3172), .Q(add_subt_module_Add_Subt_result[16]), .QN(n3002) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_2_ ( .D(
add_subt_module_FS_Module_state_next[2]), .CK(
add_subt_module_FS_Module_net3719247), .RN(n3182), .Q(
add_subt_module_FS_Module_state_reg[2]), .QN(n3001) );
DFFRX2TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[4]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3719211), .RN(n3169), .Q(add_subt_module_exp_oper_result[4]), .QN(n3000) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[24]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3172), .Q(add_subt_module_Add_Subt_result[24]), .QN(n2999) );
DFFRX2TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[3]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3719211), .RN(n3169), .Q(add_subt_module_exp_oper_result[3]), .QN(n2998) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_30_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[30]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3173), .Q(add_subt_module_Add_Subt_result[30]), .QN(n2997) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_41_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[41]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3183), .Q(add_subt_module_Add_Subt_result[41]), .QN(n2996) );
DFFRX2TS cordic_FSM_state_reg_reg_2_ ( .D(n1156), .CK(clk), .RN(n3181), .Q(
cordic_FSM_state_reg[2]), .QN(n2995) );
DFFRX2TS cont_iter_count_reg_1_ ( .D(n3272), .CK(cont_iter_net3719283), .RN(
n3227), .Q(cont_iter_out[1]), .QN(n2994) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[2]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3154), .Q(add_subt_module_Add_Subt_result[2]), .QN(n2990) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_43_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]),
.CK(clk), .RN(n3168), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[91]), .QN(
n2989) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_40_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[40]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3173), .Q(add_subt_module_Add_Subt_result[40]), .QN(n2988) );
DFFRX2TS cont_var_count_reg_0_ ( .D(n1146), .CK(n3267), .RN(n3202), .Q(
cont_var_out[0]), .QN(n2987) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_29_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[29]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3156), .Q(add_subt_module_Add_Subt_result[29]), .QN(n2986) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_49_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[49]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3246), .Q(add_subt_module_Add_Subt_result[49]), .QN(n2985) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_45_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[45]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3246), .Q(add_subt_module_Add_Subt_result[45]), .QN(n2984) );
DFFRX2TS add_subt_module_XRegister_Q_reg_22_ ( .D(n1182), .CK(
add_subt_module_YRegister_net3719157), .RN(n3160), .Q(
add_subt_module_intDX[22]), .QN(n2982) );
DFFRX2TS add_subt_module_XRegister_Q_reg_19_ ( .D(n1179), .CK(
add_subt_module_YRegister_net3719157), .RN(n3175), .Q(
add_subt_module_intDX[19]), .QN(n2979) );
DFFRX2TS add_subt_module_XRegister_Q_reg_42_ ( .D(n1202), .CK(
add_subt_module_YRegister_net3719157), .RN(n3151), .Q(
add_subt_module_intDX[42]), .QN(n2975) );
DFFRX2TS add_subt_module_XRegister_Q_reg_51_ ( .D(n1211), .CK(
add_subt_module_YRegister_net3719157), .RN(n3150), .Q(
add_subt_module_intDX[51]), .QN(n2974) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[13]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3171), .Q(add_subt_module_Add_Subt_result[13]), .QN(n2972) );
DFFRX2TS add_subt_module_Sel_B_Q_reg_1_ ( .D(n1152), .CK(
add_subt_module_FS_Module_net3719247), .RN(n1135), .Q(
add_subt_module_FSM_selector_B[1]), .QN(n2971) );
DFFRX2TS add_subt_module_XRegister_Q_reg_27_ ( .D(n1187), .CK(
add_subt_module_YRegister_net3719157), .RN(n3182), .Q(
add_subt_module_intDX[27]), .QN(n2970) );
DFFRX2TS add_subt_module_XRegister_Q_reg_54_ ( .D(n1214), .CK(
add_subt_module_YRegister_net3719157), .RN(n3174), .Q(
add_subt_module_intDX[54]), .QN(n2963) );
DFFRX2TS add_subt_module_XRegister_Q_reg_34_ ( .D(n1194), .CK(
add_subt_module_YRegister_net3719157), .RN(n3167), .Q(
add_subt_module_intDX[34]), .QN(n2961) );
DFFRX2TS cordic_FSM_state_reg_reg_1_ ( .D(cordic_FSM_state_next_1_), .CK(clk), .RN(n3173), .Q(cordic_FSM_state_reg[1]), .QN(n2956) );
DFFRX2TS add_subt_module_Sel_C_Q_reg_0_ ( .D(n1148), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n1135), .Q(add_subt_module_FSM_selector_C), .QN(n3015) );
DFFRX2TS cont_iter_count_reg_2_ ( .D(n3271), .CK(cont_iter_net3719283), .RN(
n3213), .Q(cont_iter_out[2]), .QN(n2955) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_1_ ( .D(
add_subt_module_FS_Module_state_next[1]), .CK(
add_subt_module_FS_Module_net3719247), .RN(n3149), .Q(
add_subt_module_FS_Module_state_reg[1]), .QN(n2950) );
CMPR32X2TS DP_OP_92J185_122_9081_U12 ( .A(add_subt_module_S_Oper_A_exp[0]),
.B(n3145), .C(DP_OP_92J185_122_9081_n26), .CO(
DP_OP_92J185_122_9081_n11), .S(
add_subt_module_Exp_Operation_Module_Data_S[0]) );
CMPR32X2TS DP_OP_92J185_122_9081_U2 ( .A(DP_OP_92J185_122_9081_n16), .B(
add_subt_module_S_Oper_A_exp[10]), .C(DP_OP_92J185_122_9081_n2), .CO(
DP_OP_92J185_122_9081_n1), .S(
add_subt_module_Exp_Operation_Module_Data_S[10]) );
DFFRX4TS cont_iter_count_reg_0_ ( .D(n3273), .CK(cont_iter_net3719283), .RN(
n3229), .Q(n3146), .QN(n3247) );
DFFSX2TS add_subt_module_XRegister_Q_reg_57_ ( .D(n3249), .CK(
add_subt_module_YRegister_net3719157), .SN(n3176), .Q(n3028) );
DFFSX2TS add_subt_module_XRegister_Q_reg_60_ ( .D(n3248), .CK(
add_subt_module_YRegister_net3719157), .SN(n3181), .Q(n3018) );
DFFSX2TS add_subt_module_XRegister_Q_reg_36_ ( .D(n3256), .CK(
add_subt_module_YRegister_net3719157), .SN(n3182), .Q(n3016) );
DFFSX2TS add_subt_module_XRegister_Q_reg_35_ ( .D(n3257), .CK(
add_subt_module_YRegister_net3719157), .SN(n3151), .Q(n3022) );
DFFSX2TS add_subt_module_XRegister_Q_reg_33_ ( .D(n3258), .CK(
add_subt_module_YRegister_net3719157), .SN(n3156), .Q(n3021) );
DFFSX2TS add_subt_module_XRegister_Q_reg_31_ ( .D(n3259), .CK(
add_subt_module_YRegister_net3719157), .SN(n3183), .Q(n2976) );
DFFSX2TS add_subt_module_XRegister_Q_reg_26_ ( .D(n3260), .CK(
add_subt_module_YRegister_net3719157), .SN(n3173), .Q(n3033) );
DFFSX2TS add_subt_module_XRegister_Q_reg_25_ ( .D(n3261), .CK(
add_subt_module_YRegister_net3719157), .SN(n3182), .Q(n3038) );
DFFSX2TS add_subt_module_XRegister_Q_reg_55_ ( .D(n3250), .CK(
add_subt_module_YRegister_net3719157), .SN(n3181), .Q(n3027) );
DFFSX2TS add_subt_module_XRegister_Q_reg_53_ ( .D(n3251), .CK(
add_subt_module_YRegister_net3719157), .SN(n3184), .Q(n3026) );
DFFSX2TS add_subt_module_XRegister_Q_reg_50_ ( .D(n3252), .CK(
add_subt_module_YRegister_net3719157), .SN(n3151), .Q(n3017) );
DFFSX2TS add_subt_module_XRegister_Q_reg_49_ ( .D(n3253), .CK(
add_subt_module_YRegister_net3719157), .SN(n3149), .Q(n3025) );
DFFSX2TS add_subt_module_XRegister_Q_reg_45_ ( .D(n3254), .CK(
add_subt_module_YRegister_net3719157), .SN(n3149), .Q(n3024) );
DFFSX2TS add_subt_module_XRegister_Q_reg_43_ ( .D(n3255), .CK(
add_subt_module_YRegister_net3719157), .SN(n3246), .Q(n3023) );
DFFSX2TS add_subt_module_XRegister_Q_reg_17_ ( .D(n3263), .CK(
add_subt_module_YRegister_net3719157), .SN(n3183), .Q(n3032) );
DFFSX2TS add_subt_module_XRegister_Q_reg_15_ ( .D(n3264), .CK(
add_subt_module_YRegister_net3719157), .SN(n3153), .Q(n2978) );
DFFSX2TS add_subt_module_XRegister_Q_reg_18_ ( .D(n3262), .CK(
add_subt_module_YRegister_net3719157), .SN(n3160), .Q(n3037) );
DFFSX2TS add_subt_module_XRegister_Q_reg_8_ ( .D(n3265), .CK(
add_subt_module_YRegister_net3719157), .SN(n3156), .Q(n3020) );
DFFSX2TS add_subt_module_XRegister_Q_reg_3_ ( .D(n3266), .CK(
add_subt_module_YRegister_net3719157), .SN(n3183), .Q(n3031) );
DFFSXLTS R_0 ( .D(n3144), .CK(add_subt_module_YRegister_net3719157), .SN(
n3174), .Q(n3244) );
DFFRX2TS add_subt_module_XRegister_Q_reg_58_ ( .D(n1218), .CK(
add_subt_module_YRegister_net3719157), .RN(n3156), .QN(n3148) );
DFFRX2TS add_subt_module_XRegister_Q_reg_11_ ( .D(n1171), .CK(
add_subt_module_YRegister_net3719157), .RN(n3158), .QN(n3147) );
DFFRX2TS add_subt_module_XRegister_Q_reg_59_ ( .D(n1219), .CK(
add_subt_module_YRegister_net3719157), .RN(n3180), .Q(
add_subt_module_intDX[59]), .QN(n2973) );
DFFRX1TS add_subt_module_YRegister_Q_reg_0_ ( .D(n1224), .CK(
add_subt_module_YRegister_net3719157), .RN(n3174), .Q(
add_subt_module_intDY[0]), .QN(n3050) );
DFFRX1TS add_subt_module_XRegister_Q_reg_0_ ( .D(n1160), .CK(
add_subt_module_YRegister_net3719157), .RN(n3156), .Q(
add_subt_module_intDX[0]), .QN(n2983) );
DFFRX1TS add_subt_module_XRegister_Q_reg_5_ ( .D(n1165), .CK(
add_subt_module_YRegister_net3719157), .RN(n3157), .Q(
add_subt_module_intDX[5]), .QN(n2969) );
DFFRX1TS add_subt_module_YRegister_Q_reg_4_ ( .D(n1228), .CK(
add_subt_module_YRegister_net3719157), .RN(n3174), .Q(
add_subt_module_intDY[4]), .QN(n2992) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[3]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3178), .Q(add_subt_module_Add_Subt_result[3]) );
DFFRX2TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_31_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[31]),
.CK(clk), .RN(n3179), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[10]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3171), .Q(add_subt_module_Add_Subt_result[10]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[20]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3172), .Q(add_subt_module_Add_Subt_result[20]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[23]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3172), .Q(add_subt_module_Add_Subt_result[23]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[12]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3171), .Q(add_subt_module_Add_Subt_result[12]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_28_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[28]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3156), .Q(add_subt_module_Add_Subt_result[28]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_47_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[47]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3170), .Q(add_subt_module_Add_Subt_result[47]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_48_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]),
.CK(clk), .RN(n3156), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[96]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_52_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[52]),
.CK(clk), .RN(n3173), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_49_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[49]),
.CK(clk), .RN(n3174), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[97]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_53_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[53]),
.CK(clk), .RN(n3168), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[101]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_50_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[50]),
.CK(clk), .RN(n3180), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[98]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_54_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[54]),
.CK(clk), .RN(n3149), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[5]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3171), .Q(add_subt_module_Add_Subt_result[5]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[22]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3172), .Q(add_subt_module_Add_Subt_result[22]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[25]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3172), .Q(add_subt_module_Add_Subt_result[25]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_39_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[39]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3183), .Q(add_subt_module_Add_Subt_result[39]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_38_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[38]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3173), .Q(add_subt_module_Add_Subt_result[38]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_35_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[35]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3183), .Q(add_subt_module_Add_Subt_result[35]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[17]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3172), .Q(add_subt_module_Add_Subt_result[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_56_ ( .D(first_mux_Y[56]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3229), .Q(d_ff2_Y[56]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[15]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3171), .Q(add_subt_module_Add_Subt_result[15]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_48_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[48]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3177), .Q(add_subt_module_Add_Subt_result[48]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_56_ ( .D(first_mux_X[56]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3192), .Q(d_ff2_X[56]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_33_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[33]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3173), .Q(add_subt_module_Add_Subt_result[33]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_54_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[54]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3246), .Q(add_subt_module_Add_Subt_result[54]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_35_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[35]),
.CK(clk), .RN(n3159), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_32_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[32]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3183), .Q(add_subt_module_Add_Subt_result[32]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_53_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[53]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3178), .Q(add_subt_module_Add_Subt_result[53]) );
DFFRX4TS cordic_FSM_state_reg_reg_0_ ( .D(n1157), .CK(clk), .RN(n3181), .Q(
cordic_FSM_state_reg[0]), .QN(n2951) );
DFFRX4TS cont_iter_count_reg_3_ ( .D(n3274), .CK(cont_iter_net3719283), .RN(
n3242), .Q(cont_iter_out[3]), .QN(n2957) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ (
.D(add_subt_module_Add_Subt_Sgf_module_S_to_D[55]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3168), .Q(add_subt_module_add_overflow_flag) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(shift_region_flag[1]), .CK(
reg_Z0_net3719139), .RN(n3205), .Q(d_ff1_shift_region_flag_out[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_61_ ( .D(first_mux_Y[61]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3203), .Q(d_ff2_Y[61]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_61_ ( .D(first_mux_X[61]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3197), .Q(d_ff2_X[61]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_60_ ( .D(first_mux_Y[60]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3242), .Q(d_ff2_Y[60]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_58_ ( .D(first_mux_Y[58]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3222), .Q(d_ff2_Y[58]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_60_ ( .D(first_mux_X[60]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3193), .Q(d_ff2_X[60]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_58_ ( .D(first_mux_X[58]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3189), .Q(d_ff2_X[58]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[2]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3162), .Q(add_subt_module_Sgf_normalized_result[2]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[1]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3719211), .RN(n3169), .Q(add_subt_module_exp_oper_result[1]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[2]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3719211), .RN(n3169), .Q(add_subt_module_exp_oper_result[2]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[13]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3163), .Q(add_subt_module_Sgf_normalized_result[13]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[12]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3163), .Q(add_subt_module_Sgf_normalized_result[12]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[14]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3163), .Q(add_subt_module_Sgf_normalized_result[14]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[7]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3179), .Q(add_subt_module_Sgf_normalized_result[7]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[3]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3185), .Q(add_subt_module_Sgf_normalized_result[3]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[11]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3163), .Q(add_subt_module_Sgf_normalized_result[11]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[6]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3175), .Q(add_subt_module_Sgf_normalized_result[6]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[10]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3163), .Q(add_subt_module_Sgf_normalized_result[10]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[5]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3183), .Q(add_subt_module_Sgf_normalized_result[5]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[9]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3163), .Q(add_subt_module_Sgf_normalized_result[9]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[4]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3166), .Q(add_subt_module_Sgf_normalized_result[4]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[8]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3153), .Q(add_subt_module_Sgf_normalized_result[8]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[15]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3164), .Q(add_subt_module_Sgf_normalized_result[15]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[43]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3167), .Q(add_subt_module_Sgf_normalized_result[43]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[46]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3178), .Q(add_subt_module_Sgf_normalized_result[46]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[45]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3161), .Q(add_subt_module_Sgf_normalized_result[45]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[42]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3167), .Q(add_subt_module_Sgf_normalized_result[42]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[50]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3160), .Q(add_subt_module_Sgf_normalized_result[50]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[51]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3179), .Q(add_subt_module_Sgf_normalized_result[51]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[44]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3167), .Q(add_subt_module_Sgf_normalized_result[44]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[52]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3158), .Q(add_subt_module_Sgf_normalized_result[52]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[49]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3179), .Q(add_subt_module_Sgf_normalized_result[49]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[48]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3160), .Q(add_subt_module_Sgf_normalized_result[48]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[47]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3173), .Q(add_subt_module_Sgf_normalized_result[47]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[21]),
.CK(clk), .RN(n3180), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[75]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[22]),
.CK(clk), .RN(n3162), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[76]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[20]),
.CK(clk), .RN(n3161), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[74]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[18]),
.CK(clk), .RN(n3175), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[73]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[17]),
.CK(clk), .RN(n3153), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[72]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[16]),
.CK(clk), .RN(n3161), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[71]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n134),
.CK(add_subt_module_Exp_Operation_Module_exp_result_net3719211), .RN(
n3149), .Q(overflow_flag) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(
add_subt_module_Barrel_Shifter_module_Data_Reg[1]), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3719193), .RN(
n3168), .Q(add_subt_module_Sgf_normalized_result[1]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[29]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3161), .Q(result_add_subt[29]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[21]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3161), .Q(result_add_subt[21]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[18]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3160), .Q(result_add_subt[18]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[28]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3160), .Q(result_add_subt[28]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[22]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3158), .Q(result_add_subt[22]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[23]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3177), .Q(result_add_subt[23]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[16]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3164), .Q(result_add_subt[16]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[14]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3180), .Q(result_add_subt[14]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[0]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3152), .Q(result_add_subt[52]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[3]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3153), .Q(result_add_subt[55]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[4]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3184), .Q(result_add_subt[56]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[5]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3181), .Q(result_add_subt[57]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[6]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3177), .Q(result_add_subt[58]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[7]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3160), .Q(result_add_subt[59]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[8]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3185), .Q(result_add_subt[60]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[9]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3182), .Q(result_add_subt[61]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[10]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3159), .Q(result_add_subt[62]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[25]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3153), .Q(result_add_subt[25]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[20]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3183), .Q(result_add_subt[20]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[36]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3161), .Q(result_add_subt[36]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[27]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3175), .Q(result_add_subt[27]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[24]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3181), .Q(result_add_subt[24]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[17]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3173), .Q(result_add_subt[17]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[26]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3183), .Q(result_add_subt[26]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[19]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3167), .Q(result_add_subt[19]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[34]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3173), .Q(result_add_subt[34]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[31]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3185), .Q(result_add_subt[31]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[38]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3153), .Q(result_add_subt[38]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[15]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3185), .Q(result_add_subt[15]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[32]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3152), .Q(result_add_subt[32]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[39]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3152), .Q(result_add_subt[39]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[37]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3246), .Q(result_add_subt[37]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[33]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3154), .Q(result_add_subt[33]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[35]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3151), .Q(result_add_subt[35]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[51]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3149), .Q(result_add_subt[51]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[30]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3149), .Q(result_add_subt[30]) );
DFFRX1TS add_subt_module_XRegister_Q_reg_63_ ( .D(n1223), .CK(
add_subt_module_YRegister_net3719157), .RN(n3174), .Q(
add_subt_module_intDX[63]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_55_ ( .D(first_mux_X[55]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3188), .Q(d_ff2_X[55]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_54_ ( .D(first_mux_X[54]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3237), .Q(d_ff2_X[54]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_53_ ( .D(first_mux_X[53]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3191), .Q(d_ff2_X[53]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_55_ ( .D(first_mux_Y[55]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3242), .Q(d_ff2_Y[55]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_54_ ( .D(first_mux_Y[54]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3235), .Q(d_ff2_Y[54]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_53_ ( .D(first_mux_Y[53]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3233), .Q(d_ff2_Y[53]) );
DFFRX2TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_47_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]),
.CK(clk), .RN(n3157), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_27_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[27]),
.CK(clk), .RN(n3182), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_30_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[30]),
.CK(clk), .RN(n3153), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_29_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[29]),
.CK(clk), .RN(n3183), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_26_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[26]),
.CK(clk), .RN(n3166), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_28_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[28]),
.CK(clk), .RN(n3173), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[25]),
.CK(clk), .RN(n3181), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_44_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[44]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3178), .Q(add_subt_module_Add_Subt_result[44]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[24]),
.CK(clk), .RN(n3185), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[78]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[19]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3172), .Q(add_subt_module_Add_Subt_result[19]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[42]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3151), .Q(result_add_subt[42]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[49]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3151), .Q(result_add_subt[49]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[48]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3180), .Q(result_add_subt[48]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[13]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3153), .Q(result_add_subt[13]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[1]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3719157),
.RN(n3184), .Q(result_add_subt[53]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[7]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3171), .Q(add_subt_module_Add_Subt_result[7]) );
DFFRX1TS add_subt_module_Sel_B_Q_reg_0_ ( .D(n1149), .CK(
add_subt_module_FS_Module_net3719247), .RN(n1135), .Q(
add_subt_module_FSM_selector_B[0]), .QN(n2993) );
DFFRX1TS add_subt_module_YRegister_Q_reg_18_ ( .D(n1242), .CK(
add_subt_module_YRegister_net3719157), .RN(n3160), .Q(
add_subt_module_intDY[18]), .QN(n3107) );
DFFRX1TS add_subt_module_XRegister_Q_reg_40_ ( .D(n1200), .CK(
add_subt_module_YRegister_net3719157), .RN(n3246), .Q(
add_subt_module_intDX[40]), .QN(n2952) );
DFFRX1TS add_subt_module_XRegister_Q_reg_44_ ( .D(n1204), .CK(
add_subt_module_YRegister_net3719157), .RN(n3246), .Q(
add_subt_module_intDX[44]), .QN(n3005) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_59_ ( .D(first_mux_X[59]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3190), .Q(d_ff2_X[59]), .QN(
n3080) );
DFFRX1TS add_subt_module_YRegister_Q_reg_62_ ( .D(n1286), .CK(
add_subt_module_YRegister_net3719157), .RN(n3181), .Q(
add_subt_module_intDY[62]), .QN(n3119) );
DFFRX1TS add_subt_module_XRegister_Q_reg_2_ ( .D(n1162), .CK(
add_subt_module_YRegister_net3719157), .RN(n3169), .Q(
add_subt_module_intDX[2]), .QN(n2981) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_57_ ( .D(first_mux_Y[57]), .CK(
reg_val_muxZ_2stage_net3719139), .RN(n3238), .Q(d_ff2_Y[57]), .QN(
n3142) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[1]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3719193), .RN(
n3174), .Q(add_subt_module_Add_Subt_result[1]), .QN(n3137) );
DFFRX1TS add_subt_module_XRegister_Q_reg_62_ ( .D(n1222), .CK(
add_subt_module_YRegister_net3719157), .RN(n3180), .Q(
add_subt_module_intDX[62]), .QN(n2966) );
DFFRX1TS add_subt_module_XRegister_Q_reg_6_ ( .D(n1166), .CK(
add_subt_module_YRegister_net3719157), .RN(n3168), .Q(
add_subt_module_intDX[6]), .QN(n3008) );
DFFRX1TS add_subt_module_XRegister_Q_reg_9_ ( .D(n1169), .CK(
add_subt_module_YRegister_net3719157), .RN(n3157), .Q(
add_subt_module_intDX[9]), .QN(n2959) );
DFFRX1TS add_subt_module_XRegister_Q_reg_24_ ( .D(n1184), .CK(
add_subt_module_YRegister_net3719157), .RN(n3175), .Q(
add_subt_module_intDX[24]), .QN(n2980) );
DFFRX1TS add_subt_module_XRegister_Q_reg_16_ ( .D(n1176), .CK(
add_subt_module_YRegister_net3719157), .RN(n3176), .Q(
add_subt_module_intDX[16]), .QN(n3041) );
DFFRX1TS add_subt_module_XRegister_Q_reg_39_ ( .D(n1199), .CK(
add_subt_module_YRegister_net3719157), .RN(n3152), .Q(
add_subt_module_intDX[39]), .QN(n2977) );
DFFRX1TS add_subt_module_XRegister_Q_reg_38_ ( .D(n1198), .CK(
add_subt_module_YRegister_net3719157), .RN(n3185), .Q(
add_subt_module_intDX[38]), .QN(n2962) );
DFFRX1TS add_subt_module_XRegister_Q_reg_32_ ( .D(n1192), .CK(
add_subt_module_YRegister_net3719157), .RN(n3153), .Q(
add_subt_module_intDX[32]), .QN(n2960) );
DFFRX1TS add_subt_module_XRegister_Q_reg_7_ ( .D(n1167), .CK(
add_subt_module_YRegister_net3719157), .RN(n3183), .Q(
add_subt_module_intDX[7]), .QN(n2967) );
DFFRX1TS add_subt_module_XRegister_Q_reg_4_ ( .D(n1164), .CK(
add_subt_module_YRegister_net3719157), .RN(n3156), .Q(
add_subt_module_intDX[4]), .QN(n3039) );
DFFRX1TS add_subt_module_XRegister_Q_reg_1_ ( .D(n1161), .CK(
add_subt_module_YRegister_net3719157), .RN(n3157), .Q(
add_subt_module_intDX[1]), .QN(n3029) );
DFFRX1TS add_subt_module_YRegister_Q_reg_12_ ( .D(n1236), .CK(
add_subt_module_YRegister_net3719157), .RN(n3158), .Q(
add_subt_module_intDY[12]), .QN(n3088) );
DFFRX1TS add_subt_module_YRegister_Q_reg_10_ ( .D(n1234), .CK(
add_subt_module_YRegister_net3719157), .RN(n3177), .Q(
add_subt_module_intDY[10]), .QN(n3128) );
DFFRX1TS add_subt_module_YRegister_Q_reg_9_ ( .D(n1233), .CK(
add_subt_module_YRegister_net3719157), .RN(n3157), .Q(
add_subt_module_intDY[9]), .QN(n3118) );
DFFRX1TS add_subt_module_YRegister_Q_reg_8_ ( .D(n1232), .CK(
add_subt_module_YRegister_net3719157), .RN(n3163), .Q(
add_subt_module_intDY[8]), .QN(n3089) );
DFFRX1TS add_subt_module_YRegister_Q_reg_6_ ( .D(n1230), .CK(
add_subt_module_YRegister_net3719157), .RN(n3162), .Q(
add_subt_module_intDY[6]), .QN(n2991) );
DFFRX1TS add_subt_module_YRegister_Q_reg_2_ ( .D(n1226), .CK(
add_subt_module_YRegister_net3719157), .RN(n3180), .Q(
add_subt_module_intDY[2]), .QN(n3126) );
DFFRX1TS add_subt_module_YRegister_Q_reg_1_ ( .D(n1225), .CK(
add_subt_module_YRegister_net3719157), .RN(n3157), .Q(
add_subt_module_intDY[1]), .QN(n3132) );
DFFRX1TS add_subt_module_XRegister_Q_reg_52_ ( .D(n1212), .CK(
add_subt_module_YRegister_net3719157), .RN(n3176), .Q(
add_subt_module_intDX[52]), .QN(n3007) );
DFFRX1TS add_subt_module_XRegister_Q_reg_48_ ( .D(n1208), .CK(
add_subt_module_YRegister_net3719157), .RN(n3149), .Q(
add_subt_module_intDX[48]), .QN(n3006) );
DFFRX1TS add_subt_module_XRegister_Q_reg_47_ ( .D(n1207), .CK(
add_subt_module_YRegister_net3719157), .RN(n3150), .Q(
add_subt_module_intDX[47]), .QN(n2968) );
DFFRX1TS add_subt_module_XRegister_Q_reg_37_ ( .D(n1197), .CK(
add_subt_module_YRegister_net3719157), .RN(n3152), .Q(
add_subt_module_intDX[37]), .QN(n3010) );
DFFRX1TS add_subt_module_YRegister_Q_reg_56_ ( .D(n1280), .CK(
add_subt_module_YRegister_net3719157), .RN(n3184), .Q(
add_subt_module_intDY[56]), .QN(n3099) );
DFFRX1TS add_subt_module_YRegister_Q_reg_54_ ( .D(n1278), .CK(
add_subt_module_YRegister_net3719157), .RN(n3184), .Q(
add_subt_module_intDY[54]), .QN(n3094) );
DFFRX1TS add_subt_module_YRegister_Q_reg_52_ ( .D(n1276), .CK(
add_subt_module_YRegister_net3719157), .RN(n3164), .Q(
add_subt_module_intDY[52]), .QN(n3105) );
DFFRX1TS add_subt_module_YRegister_Q_reg_50_ ( .D(n1274), .CK(
add_subt_module_YRegister_net3719157), .RN(n3184), .Q(
add_subt_module_intDY[50]), .QN(n3096) );
DFFRX1TS add_subt_module_YRegister_Q_reg_45_ ( .D(n1269), .CK(
add_subt_module_YRegister_net3719157), .RN(n3154), .Q(
add_subt_module_intDY[45]), .QN(n3090) );
DFFRX1TS add_subt_module_YRegister_Q_reg_39_ ( .D(n1263), .CK(
add_subt_module_YRegister_net3719157), .RN(n3170), .Q(
add_subt_module_intDY[39]), .QN(n3117) );
DFFRX1TS add_subt_module_YRegister_Q_reg_37_ ( .D(n1261), .CK(
add_subt_module_YRegister_net3719157), .RN(n3154), .Q(
add_subt_module_intDY[37]), .QN(n3130) );
DFFRX1TS add_subt_module_YRegister_Q_reg_27_ ( .D(n1251), .CK(
add_subt_module_YRegister_net3719157), .RN(n3155), .Q(
add_subt_module_intDY[27]), .QN(n3124) );
DFFRX1TS add_subt_module_YRegister_Q_reg_25_ ( .D(n1249), .CK(
add_subt_module_YRegister_net3719157), .RN(n3155), .Q(
add_subt_module_intDY[25]), .QN(n3113) );
DFFRX1TS add_subt_module_XRegister_Q_reg_61_ ( .D(n1221), .CK(
add_subt_module_YRegister_net3719157), .RN(n3176), .Q(
add_subt_module_intDX[61]), .QN(n2965) );
DFFRX1TS add_subt_module_XRegister_Q_reg_10_ ( .D(n1170), .CK(
add_subt_module_YRegister_net3719157), .RN(n3159), .Q(
add_subt_module_intDX[10]), .QN(n2958) );
DFFRX1TS add_subt_module_YRegister_Q_reg_26_ ( .D(n1250), .CK(
add_subt_module_YRegister_net3719157), .RN(n3155), .Q(
add_subt_module_intDY[26]), .QN(n3101) );
DFFRX1TS add_subt_module_YRegister_Q_reg_24_ ( .D(n1248), .CK(
add_subt_module_YRegister_net3719157), .RN(n3155), .Q(
add_subt_module_intDY[24]), .QN(n3108) );
DFFRX1TS add_subt_module_YRegister_Q_reg_23_ ( .D(n1247), .CK(
add_subt_module_YRegister_net3719157), .RN(n3177), .Q(
add_subt_module_intDY[23]), .QN(n3011) );
DFFRX1TS add_subt_module_YRegister_Q_reg_22_ ( .D(n1246), .CK(
add_subt_module_YRegister_net3719157), .RN(n3160), .Q(
add_subt_module_intDY[22]), .QN(n3123) );
DFFRX1TS add_subt_module_YRegister_Q_reg_20_ ( .D(n1244), .CK(
add_subt_module_YRegister_net3719157), .RN(n3155), .Q(
add_subt_module_intDY[20]), .QN(n3104) );
DFFRX1TS add_subt_module_YRegister_Q_reg_19_ ( .D(n1243), .CK(
add_subt_module_YRegister_net3719157), .RN(n3162), .Q(
add_subt_module_intDY[19]), .QN(n3121) );
DFFRX1TS add_subt_module_YRegister_Q_reg_17_ ( .D(n1241), .CK(
add_subt_module_YRegister_net3719157), .RN(n3176), .Q(
add_subt_module_intDY[17]), .QN(n3106) );
DFFRX1TS add_subt_module_YRegister_Q_reg_16_ ( .D(n1240), .CK(
add_subt_module_YRegister_net3719157), .RN(n3176), .Q(
add_subt_module_intDY[16]), .QN(n3114) );
DFFRX1TS add_subt_module_YRegister_Q_reg_14_ ( .D(n1238), .CK(
add_subt_module_YRegister_net3719157), .RN(n3168), .Q(
add_subt_module_intDY[14]), .QN(n3122) );
DFFRX1TS add_subt_module_YRegister_Q_reg_11_ ( .D(n1235), .CK(
add_subt_module_YRegister_net3719157), .RN(n3159), .Q(
add_subt_module_intDY[11]), .QN(n3098) );
DFFRX1TS add_subt_module_XRegister_Q_reg_56_ ( .D(n1216), .CK(
add_subt_module_YRegister_net3719157), .RN(n3176), .Q(
add_subt_module_intDX[56]), .QN(n2964) );
DFFRX1TS add_subt_module_YRegister_Q_reg_30_ ( .D(n1254), .CK(
add_subt_module_YRegister_net3719157), .RN(n3155), .Q(
add_subt_module_intDY[30]), .QN(n3120) );
DFFRX1TS add_subt_module_YRegister_Q_reg_47_ ( .D(n1271), .CK(
add_subt_module_YRegister_net3719157), .RN(n3170), .Q(
add_subt_module_intDY[47]), .QN(n3125) );
DFFRX1TS add_subt_module_YRegister_Q_reg_38_ ( .D(n1262), .CK(
add_subt_module_YRegister_net3719157), .RN(n3178), .Q(
add_subt_module_intDY[38]), .QN(n3134) );
DFFRX1TS add_subt_module_YRegister_Q_reg_34_ ( .D(n1258), .CK(
add_subt_module_YRegister_net3719157), .RN(n3155), .Q(
add_subt_module_intDY[34]), .QN(n3111) );
DFFRX1TS add_subt_module_YRegister_Q_reg_32_ ( .D(n1256), .CK(
add_subt_module_YRegister_net3719157), .RN(n3155), .Q(
add_subt_module_intDY[32]), .QN(n3115) );
ADDFX1TS intadd_436_U4 ( .A(d_ff2_Y[53]), .B(n2994), .CI(intadd_436_CI),
.CO(intadd_436_n3), .S(sh_exp_y[1]) );
DFFRX4TS add_subt_module_FS_Module_state_reg_reg_3_ ( .D(
add_subt_module_FS_Module_state_next[3]), .CK(
add_subt_module_FS_Module_net3719247), .RN(n3173), .Q(
add_subt_module_FS_Module_state_reg[3]), .QN(n2954) );
DFFRX4TS add_subt_module_Sel_D_Q_reg_0_ ( .D(n1150), .CK(
add_subt_module_FS_Module_net3719247), .RN(n1135), .Q(
add_subt_module_FSM_selector_D) );
CMPR32X2TS DP_OP_92J185_122_9081_U11 ( .A(DP_OP_92J185_122_9081_n25), .B(
add_subt_module_S_Oper_A_exp[1]), .C(DP_OP_92J185_122_9081_n11), .CO(
DP_OP_92J185_122_9081_n10), .S(
add_subt_module_Exp_Operation_Module_Data_S[1]) );
CMPR32X2TS DP_OP_92J185_122_9081_U10 ( .A(DP_OP_92J185_122_9081_n24), .B(
add_subt_module_S_Oper_A_exp[2]), .C(DP_OP_92J185_122_9081_n10), .CO(
DP_OP_92J185_122_9081_n9), .S(
add_subt_module_Exp_Operation_Module_Data_S[2]) );
CMPR32X2TS intadd_435_U4 ( .A(d_ff2_X[53]), .B(n2994), .C(intadd_435_CI),
.CO(intadd_435_n3), .S(sh_exp_x[1]) );
CMPR32X2TS intadd_435_U3 ( .A(d_ff2_X[54]), .B(n2955), .C(intadd_435_n3),
.CO(intadd_435_n2), .S(sh_exp_x[2]) );
CMPR32X2TS intadd_436_U3 ( .A(d_ff2_Y[54]), .B(n2955), .C(intadd_436_n3),
.CO(intadd_436_n2), .S(sh_exp_y[2]) );
DFFRX4TS cordic_FSM_state_reg_reg_3_ ( .D(n1155), .CK(n3267), .RN(n3184),
.Q(cordic_FSM_state_reg[3]), .QN(n2949) );
CMPR32X2TS intadd_435_U2 ( .A(d_ff2_X[55]), .B(n2957), .C(intadd_435_n2),
.CO(intadd_435_n1), .S(sh_exp_x[3]) );
CMPR32X2TS intadd_436_U2 ( .A(d_ff2_Y[55]), .B(n2957), .C(intadd_436_n2),
.CO(intadd_436_n1), .S(sh_exp_y[3]) );
DFFRX4TS reg_ch_mux_1_Q_reg_0_ ( .D(n1140), .CK(n3267), .RN(n3233), .Q(
sel_mux_1_reg), .QN(n3140) );
DFFRX4TS reg_ch_mux_3_Q_reg_0_ ( .D(n1137), .CK(n3267), .RN(n3197), .Q(n2953), .QN(n3136) );
AOI222X1TS U2076 ( .A0(d_ff2_Y[62]), .A1(n2891), .B0(d_ff2_X[62]), .B1(n2899), .C0(n2048), .C1(d_ff2_Z[62]), .Y(n2057) );
CMPR32X2TS U2077 ( .A(n1581), .B(n1580), .C(n1579), .CO(n2394), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[53]) );
AOI211X2TS U2078 ( .A0(n2224), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]), .B0(
n2223), .C0(n2116), .Y(n2551) );
AOI211X2TS U2079 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[96]), .A1(
n2224), .B0(n2223), .C0(n2195), .Y(n2553) );
AOI211X2TS U2080 ( .A0(n2224), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[99]), .B0(
n2223), .C0(n2210), .Y(n2559) );
AOI211X2TS U2081 ( .A0(n2224), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]), .B0(
n2223), .C0(n2199), .Y(n2565) );
AOI211X2TS U2082 ( .A0(n2224), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[98]), .B0(
n2223), .C0(n2201), .Y(n2557) );
AOI211X2TS U2083 ( .A0(n2224), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[101]), .B0(
n2223), .C0(n2218), .Y(n2563) );
AOI211X2TS U2084 ( .A0(n2224), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[97]), .B0(
n2223), .C0(n2222), .Y(n2555) );
AOI211X2TS U2085 ( .A0(n2224), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]), .B0(
n2223), .C0(n2204), .Y(n2561) );
CMPR32X2TS U2086 ( .A(n1578), .B(n1577), .C(n1576), .CO(n1600), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[51]) );
INVX4TS U2087 ( .A(n2119), .Y(n2718) );
INVX4TS U2088 ( .A(n2119), .Y(n2111) );
CMPR32X2TS U2089 ( .A(n1575), .B(n1574), .C(n1573), .CO(n1606), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[48]) );
NAND2X4TS U2090 ( .A(n2119), .B(add_subt_module_FSM_selector_C), .Y(n1766)
);
AND2X6TS U2091 ( .A(n2468), .B(n1752), .Y(n2196) );
CMPR32X2TS U2092 ( .A(n1572), .B(n1571), .C(n1570), .CO(n1603), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[46]) );
CMPR32X2TS U2093 ( .A(n1569), .B(n1568), .C(n1567), .CO(n1594), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[44]) );
CMPR32X2TS U2094 ( .A(n1584), .B(n1583), .C(n1582), .CO(n1585), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[40]) );
NOR2X4TS U2095 ( .A(n2993), .B(add_subt_module_FSM_selector_B[1]), .Y(n1736)
);
NOR2X6TS U2096 ( .A(add_subt_module_FSM_selector_B[1]), .B(
add_subt_module_FSM_selector_B[0]), .Y(n1297) );
XOR2X1TS U2097 ( .A(n1566), .B(n1565), .Y(
add_subt_module_Add_Subt_Sgf_module_S_to_D[55]) );
NAND3X1TS U2098 ( .A(n2823), .B(n2508), .C(n2507), .Y(
add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[3]) );
NAND3X1TS U2099 ( .A(n1958), .B(n2485), .C(n1957), .Y(
add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[1]) );
NAND3X1TS U2100 ( .A(n2798), .B(n1642), .C(n1641), .Y(n2503) );
BUFX4TS U2101 ( .A(n2612), .Y(n2601) );
AOI222X1TS U2102 ( .A0(n1842), .A1(n2130), .B0(n1828), .B1(n2129), .C0(n1847), .C1(n1812), .Y(n1852) );
AOI222X1TS U2103 ( .A0(n2158), .A1(n1825), .B0(n2636), .B1(n2124), .C0(n1826), .C1(n1812), .Y(n2157) );
INVX4TS U2104 ( .A(n2391), .Y(n2612) );
AOI222X1TS U2105 ( .A0(n1826), .A1(n1825), .B0(n2158), .B1(n2124), .C0(n2154), .C1(n1812), .Y(n2168) );
AOI222X1TS U2106 ( .A0(n2143), .A1(n2130), .B0(n2141), .B1(n1812), .C0(n1838), .C1(n2129), .Y(n2139) );
AOI222X1TS U2107 ( .A0(n2159), .A1(n1825), .B0(n2165), .B1(n2124), .C0(n1824), .C1(n1812), .Y(n2632) );
BUFX3TS U2108 ( .A(n2213), .Y(n2208) );
BUFX3TS U2109 ( .A(n1815), .Y(n2732) );
BUFX3TS U2110 ( .A(n2770), .Y(n2761) );
NOR2X4TS U2111 ( .A(n2652), .B(n1814), .Y(n1819) );
CLKBUFX3TS U2112 ( .A(n2783), .Y(n1369) );
BUFX3TS U2113 ( .A(n1793), .Y(n1298) );
NAND2X4TS U2114 ( .A(n2196), .B(n2759), .Y(n2534) );
CLKINVX6TS U2115 ( .A(n1811), .Y(n1812) );
INVX3TS U2116 ( .A(n2194), .Y(n1299) );
CLKINVX6TS U2117 ( .A(n1774), .Y(n1300) );
NAND2X2TS U2118 ( .A(n1801), .B(n1765), .Y(n2119) );
NOR2X2TS U2119 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(n1899), .Y(
n1328) );
INVX4TS U2120 ( .A(n2243), .Y(n1301) );
NAND2X4TS U2121 ( .A(n2854), .B(n2871), .Y(n1618) );
BUFX4TS U2122 ( .A(n1987), .Y(n2055) );
NOR2XLTS U2123 ( .A(add_subt_module_add_overflow_flag), .B(n1764), .Y(n1765)
);
NOR3X1TS U2124 ( .A(add_subt_module_Add_Subt_result[50]), .B(
add_subt_module_Add_Subt_result[48]), .C(
add_subt_module_Add_Subt_result[49]), .Y(n1648) );
NAND2BXLTS U2125 ( .AN(add_subt_module_intDY[62]), .B(
add_subt_module_intDX[62]), .Y(n2331) );
NOR2X4TS U2126 ( .A(underflow_flag), .B(overflow_flag), .Y(n2827) );
CLKINVX6TS U2127 ( .A(rst), .Y(n3246) );
BUFX6TS U2128 ( .A(n2461), .Y(n1565) );
MX2X1TS U2129 ( .A(add_subt_module_DMP[26]), .B(n1422), .S0(n1475), .Y(n2417) );
AFHCINX2TS U2130 ( .CIN(n1532), .B(n1533), .A(n1534), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[7]), .CO(n2445) );
MX2X1TS U2131 ( .A(add_subt_module_DMP[5]), .B(
add_subt_module_Sgf_normalized_result[7]), .S0(n2487), .Y(n1534) );
AFHCINX2TS U2132 ( .CIN(n1514), .B(n1515), .A(n1516), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[19]), .CO(n2427) );
MX2X1TS U2133 ( .A(add_subt_module_DMP[17]), .B(n1421), .S0(n1475), .Y(n1516) );
MX2X1TS U2134 ( .A(add_subt_module_DMP[42]), .B(
add_subt_module_Sgf_normalized_result[44]), .S0(n2489), .Y(n1568) );
MX2X1TS U2135 ( .A(add_subt_module_DMP[51]), .B(n1407), .S0(n2489), .Y(n1580) );
MX2X1TS U2136 ( .A(add_subt_module_DMP[30]), .B(n1429), .S0(n1475), .Y(n2411) );
MX2X1TS U2137 ( .A(add_subt_module_DMP[13]), .B(
add_subt_module_Sgf_normalized_result[15]), .S0(n2487), .Y(n1522) );
MX2X1TS U2138 ( .A(add_subt_module_DMP[15]), .B(n1425), .S0(n1475), .Y(n1519) );
MX2X1TS U2139 ( .A(add_subt_module_DMP[36]), .B(n1418), .S0(n2489), .Y(n2402) );
MX2X1TS U2140 ( .A(add_subt_module_DMP[23]), .B(n1413), .S0(n1475), .Y(n1507) );
MX2X1TS U2141 ( .A(add_subt_module_DMP[20]), .B(n1417), .S0(n1475), .Y(n2426) );
AFHCINX2TS U2142 ( .CIN(n1535), .B(n1536), .A(n1537), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[5]), .CO(n2448) );
MX2X1TS U2143 ( .A(add_subt_module_DMP[3]), .B(
add_subt_module_Sgf_normalized_result[5]), .S0(n2487), .Y(n1537) );
MX2X1TS U2144 ( .A(add_subt_module_DMP[45]), .B(
add_subt_module_Sgf_normalized_result[47]), .S0(n2489), .Y(n1604) );
MX2X1TS U2145 ( .A(add_subt_module_DMP[10]), .B(
add_subt_module_Sgf_normalized_result[12]), .S0(n2487), .Y(n2441) );
MX2X1TS U2146 ( .A(add_subt_module_DMP[8]), .B(
add_subt_module_Sgf_normalized_result[10]), .S0(n2487), .Y(n2444) );
MX2X1TS U2147 ( .A(add_subt_module_DMP[1]), .B(
add_subt_module_Sgf_normalized_result[3]), .S0(n2487), .Y(n1492) );
CLKAND2X2TS U2148 ( .A(n2487), .B(add_subt_module_Sgf_normalized_result[1]),
.Y(n2459) );
XOR2X1TS U2149 ( .A(n2461), .B(n1454), .Y(n2458) );
AFHCINX2TS U2150 ( .CIN(n1499), .B(n1500), .A(n1501), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[29]), .CO(n2412) );
MX2X1TS U2151 ( .A(add_subt_module_DMP[27]), .B(n1419), .S0(n1475), .Y(n1501) );
MX2X1TS U2152 ( .A(add_subt_module_DMP[39]), .B(n1427), .S0(n2489), .Y(n1586) );
MX2X1TS U2153 ( .A(add_subt_module_DMP[48]), .B(
add_subt_module_Sgf_normalized_result[50]), .S0(n2489), .Y(n1615) );
AFHCINX2TS U2154 ( .CIN(n1493), .B(n1494), .A(n1495), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[33]), .CO(n2406) );
AFHCINX2TS U2155 ( .CIN(n1508), .B(n1509), .A(n1510), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[23]), .CO(n2421) );
MX2X1TS U2156 ( .A(add_subt_module_DMP[21]), .B(n1409), .S0(n1475), .Y(n1510) );
MX2X1TS U2157 ( .A(add_subt_module_DMP[18]), .B(n1410), .S0(n1475), .Y(n2429) );
AFHCINX2TS U2158 ( .CIN(n1523), .B(n1524), .A(n1525), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[13]), .CO(n2436) );
MX2X1TS U2159 ( .A(add_subt_module_DMP[11]), .B(
add_subt_module_Sgf_normalized_result[13]), .S0(n2487), .Y(n1525) );
MX2X1TS U2160 ( .A(add_subt_module_DMP[43]), .B(
add_subt_module_Sgf_normalized_result[45]), .S0(n2489), .Y(n1595) );
MX2X1TS U2161 ( .A(add_subt_module_DMP[47]), .B(
add_subt_module_Sgf_normalized_result[49]), .S0(n2489), .Y(n1607) );
MX2X1TS U2162 ( .A(add_subt_module_DMP[0]), .B(
add_subt_module_Sgf_normalized_result[2]), .S0(n2487), .Y(n2456) );
MX2X1TS U2163 ( .A(add_subt_module_DMP[28]), .B(n1411), .S0(n1475), .Y(n2414) );
MX2X1TS U2164 ( .A(add_subt_module_DMP[14]), .B(n1415), .S0(n1475), .Y(n2435) );
MX2X1TS U2165 ( .A(add_subt_module_DMP[41]), .B(
add_subt_module_Sgf_normalized_result[43]), .S0(n2489), .Y(n1592) );
MX2X1TS U2166 ( .A(add_subt_module_DMP[24]), .B(n1420), .S0(n1475), .Y(n2420) );
MX2X1TS U2167 ( .A(add_subt_module_DMP[34]), .B(n1424), .S0(n2487), .Y(n2405) );
MX2X1TS U2168 ( .A(add_subt_module_DMP[50]), .B(
add_subt_module_Sgf_normalized_result[52]), .S0(n2489), .Y(n1601) );
AFHCINX2TS U2169 ( .CIN(n1529), .B(n1530), .A(n1531), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[9]), .CO(n2442) );
MX2X1TS U2170 ( .A(add_subt_module_DMP[7]), .B(
add_subt_module_Sgf_normalized_result[9]), .S0(n2487), .Y(n1531) );
MX2X1TS U2171 ( .A(add_subt_module_DMP[4]), .B(
add_subt_module_Sgf_normalized_result[6]), .S0(n2487), .Y(n2450) );
OR2X1TS U2172 ( .A(add_subt_module_Add_Subt_result[43]), .B(
add_subt_module_Add_Subt_result[42]), .Y(n1621) );
OR2X1TS U2173 ( .A(add_subt_module_Add_Subt_result[52]), .B(
add_subt_module_Add_Subt_result[51]), .Y(n1947) );
NAND3XLTS U2174 ( .A(n1916), .B(n1915), .C(
add_subt_module_Add_Subt_result[24]), .Y(n2499) );
NAND3XLTS U2175 ( .A(n1939), .B(n1938), .C(
add_subt_module_Add_Subt_result[7]), .Y(n2494) );
NAND3XLTS U2176 ( .A(n1945), .B(n1911), .C(n1909), .Y(n1622) );
AOI211X1TS U2177 ( .A0(n1637), .A1(add_subt_module_Add_Subt_result[3]), .B0(
n1636), .C0(n1635), .Y(n2798) );
OAI21XLTS U2178 ( .A0(n1634), .A1(n2801), .B0(n1926), .Y(n1635) );
CLKINVX3TS U2179 ( .A(n2526), .Y(n2231) );
OAI2BB2XLTS U2180 ( .B0(n2196), .B1(n2553), .A0N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[78]), .A1N(
n1433), .Y(n2197) );
AOI211X1TS U2181 ( .A0(n2518), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]), .B0(
n2192), .C0(n2191), .Y(n2574) );
AO22XLTS U2182 ( .A0(n2522), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[59]), .B0(
n1434), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[74]), .Y(
n2192) );
OAI2BB2XLTS U2183 ( .B0(n2196), .B1(n2555), .A0N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]), .A1N(
n1433), .Y(n2227) );
AOI211X1TS U2184 ( .A0(n2518), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]), .B0(
n2185), .C0(n2184), .Y(n2572) );
AO22XLTS U2185 ( .A0(n2522), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[60]), .B0(
n1434), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[75]), .Y(
n2185) );
OAI2BB2XLTS U2186 ( .B0(n2196), .B1(n2557), .A0N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]), .A1N(
n1433), .Y(n2202) );
AOI211X1TS U2187 ( .A0(n2518), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(
n2182), .C0(n2181), .Y(n2570) );
AO22XLTS U2188 ( .A0(n2522), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[61]), .B0(
n1434), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[76]), .Y(
n2182) );
AOI211X1TS U2189 ( .A0(n2518), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]), .B0(
n2179), .C0(n2178), .Y(n2576) );
AO22XLTS U2190 ( .A0(n2522), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[58]), .B0(
n1434), .B1(n1406), .Y(n2179) );
OAI2BB2XLTS U2191 ( .B0(n2196), .B1(n2561), .A0N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]), .A1N(
n1433), .Y(n2206) );
AOI211X1TS U2192 ( .A0(n2518), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]), .B0(
n2176), .C0(n2175), .Y(n2578) );
AO22XLTS U2193 ( .A0(n2208), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[57]), .B0(
n1434), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[73]), .Y(
n2176) );
AOI222X1TS U2194 ( .A0(n2141), .A1(n2130), .B0(n1813), .B1(n2617), .C0(n2143), .C1(n2129), .Y(n2105) );
OR2X1TS U2195 ( .A(n1936), .B(n1443), .Y(n1928) );
NAND3XLTS U2196 ( .A(n1914), .B(n1633), .C(
add_subt_module_Add_Subt_result[21]), .Y(n1926) );
CLKAND2X2TS U2197 ( .A(n2476), .B(n1405), .Y(n2486) );
AOI222X1TS U2198 ( .A0(n2165), .A1(n1825), .B0(n2154), .B1(n2124), .C0(n1824), .C1(n1813), .Y(n1786) );
AOI211X1TS U2199 ( .A0(n2518), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]), .B0(
n2188), .C0(n2187), .Y(n2580) );
AO22XLTS U2200 ( .A0(n2208), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[56]), .B0(
n1434), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[72]), .Y(
n2188) );
NAND3XLTS U2201 ( .A(n2814), .B(n1940), .C(
add_subt_module_Add_Subt_result[15]), .Y(n2818) );
NAND3XLTS U2202 ( .A(n2494), .B(n2493), .C(n2492), .Y(n2496) );
NAND3XLTS U2203 ( .A(n1917), .B(n2492), .C(n2499), .Y(n1918) );
NOR2XLTS U2204 ( .A(n1908), .B(n1907), .Y(n1919) );
AO22XLTS U2205 ( .A0(n1923), .A1(n1644), .B0(n1643), .B1(
add_subt_module_Add_Subt_result[47]), .Y(n1645) );
AO22XLTS U2206 ( .A0(add_subt_module_LZA_output[4]), .A1(n2067), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]), .B1(
n2089), .Y(n2071) );
OAI2BB2XLTS U2207 ( .B0(n2196), .B1(n2565), .A0N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]), .A1N(
n1433), .Y(n2215) );
AOI222X1TS U2208 ( .A0(n1832), .A1(n1825), .B0(n2630), .B1(n2129), .C0(n1828), .C1(n1813), .Y(n2628) );
OAI2BB2XLTS U2209 ( .B0(n2196), .B1(n2563), .A0N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]), .A1N(
n1433), .Y(n2219) );
AO22XLTS U2210 ( .A0(n2522), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[70]), .B0(
n1433), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(
n2173) );
AO22XLTS U2211 ( .A0(n2208), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[55]), .B0(
n1433), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[71]), .Y(
n2170) );
AO22XLTS U2212 ( .A0(n2769), .A1(add_subt_module_Add_Subt_result[1]), .B0(
n2778), .B1(add_subt_module_Add_Subt_result[53]), .Y(n2784) );
AO22XLTS U2213 ( .A0(n1800), .A1(n2060), .B0(n1959), .B1(n1798), .Y(
add_subt_module_FSM_exp_operation_load_diff) );
NAND2BXLTS U2214 ( .AN(add_subt_module_exp_oper_result[1]), .B(n2828), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[1]) );
NAND2BXLTS U2215 ( .AN(n2567), .B(n2229), .Y(n2122) );
OAI211XLTS U2216 ( .A0(n2570), .A1(n2226), .B0(n2231), .C0(n2183), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[48]) );
OAI211XLTS U2217 ( .A0(n2572), .A1(n2226), .B0(n2231), .C0(n2186), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[49]) );
OAI211XLTS U2218 ( .A0(n2578), .A1(n2226), .B0(n2231), .C0(n2177), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[52]) );
OAI211XLTS U2219 ( .A0(n2576), .A1(n2226), .B0(n2231), .C0(n2180), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[51]) );
OAI211XLTS U2220 ( .A0(n2574), .A1(n2226), .B0(n2231), .C0(n2193), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[50]) );
NAND2BXLTS U2221 ( .AN(n2559), .B(n2229), .Y(n2214) );
NAND2BXLTS U2222 ( .AN(add_subt_module_Sgf_normalized_result[54]), .B(n1544),
.Y(n2395) );
MX2X1TS U2223 ( .A(add_subt_module_DMP[46]), .B(
add_subt_module_Sgf_normalized_result[48]), .S0(n2489), .Y(n1574) );
MX2X1TS U2224 ( .A(add_subt_module_DMP[37]), .B(n1428), .S0(n2489), .Y(n2399) );
AOI222X1TS U2225 ( .A0(n2046), .A1(d_ff2_Z[5]), .B0(n2891), .B1(d_ff2_Y[5]),
.C0(n2896), .C1(d_ff2_X[5]), .Y(n1971) );
AOI222X1TS U2226 ( .A0(d_ff2_Y[56]), .A1(n2897), .B0(d_ff2_X[56]), .B1(n2885), .C0(n1445), .C1(d_ff2_Z[56]), .Y(n1996) );
AOI222X1TS U2227 ( .A0(d_ff2_Y[61]), .A1(n2921), .B0(d_ff2_X[61]), .B1(n2919), .C0(n2052), .C1(d_ff2_Z[61]), .Y(n1992) );
AOI222X1TS U2228 ( .A0(n2046), .A1(d_ff2_Z[24]), .B0(n2921), .B1(d_ff2_Y[24]), .C0(n2055), .C1(d_ff2_X[24]), .Y(n1966) );
AOI222X1TS U2229 ( .A0(n1445), .A1(d_ff2_Z[3]), .B0(n1444), .B1(d_ff2_Y[3]),
.C0(n1374), .C1(d_ff2_X[3]), .Y(n3266) );
AOI222X1TS U2230 ( .A0(n2918), .A1(d_ff2_Z[8]), .B0(n2909), .B1(d_ff2_Y[8]),
.C0(n2055), .C1(d_ff2_X[8]), .Y(n3265) );
AOI222X1TS U2231 ( .A0(n2046), .A1(d_ff2_Z[18]), .B0(n2897), .B1(d_ff2_Y[18]), .C0(n1374), .C1(d_ff2_X[18]), .Y(n3262) );
AOI222X1TS U2232 ( .A0(n2918), .A1(d_ff2_Z[15]), .B0(n2903), .B1(d_ff2_Y[15]), .C0(n2919), .C1(d_ff2_X[15]), .Y(n3264) );
AOI222X1TS U2233 ( .A0(n1445), .A1(d_ff2_Z[17]), .B0(n2913), .B1(d_ff2_Y[17]), .C0(n2896), .C1(d_ff2_X[17]), .Y(n3263) );
AOI222X1TS U2234 ( .A0(n1445), .A1(d_ff2_Z[53]), .B0(n2909), .B1(d_ff2_Y[53]), .C0(n2885), .C1(d_ff2_X[53]), .Y(n3251) );
AOI222X1TS U2235 ( .A0(n2046), .A1(d_ff2_Z[55]), .B0(n2897), .B1(d_ff2_Y[55]), .C0(n2912), .C1(d_ff2_X[55]), .Y(n3250) );
AOI222X1TS U2236 ( .A0(n2046), .A1(d_ff2_Z[26]), .B0(n2897), .B1(d_ff2_Y[26]), .C0(n2912), .C1(d_ff2_X[26]), .Y(n3260) );
AOI222X1TS U2237 ( .A0(n2918), .A1(d_ff2_Z[31]), .B0(n2897), .B1(d_ff2_Y[31]), .C0(n2896), .C1(d_ff2_X[31]), .Y(n3259) );
AOI222X1TS U2238 ( .A0(n1445), .A1(d_ff2_Z[33]), .B0(n2905), .B1(d_ff2_Y[33]), .C0(n2899), .C1(d_ff2_X[33]), .Y(n3258) );
AOI222X1TS U2239 ( .A0(n2046), .A1(d_ff2_Z[35]), .B0(n2921), .B1(d_ff2_Y[35]), .C0(n2885), .C1(d_ff2_X[35]), .Y(n3257) );
AOI222X1TS U2240 ( .A0(d_ff2_Y[60]), .A1(n2897), .B0(d_ff2_X[60]), .B1(n2919), .C0(n2918), .C1(d_ff2_Z[60]), .Y(n3248) );
MX2X1TS U2241 ( .A(add_subt_module_DMP[22]), .B(n1412), .S0(n1475), .Y(n2423) );
NAND4BXLTS U2242 ( .AN(n2486), .B(n2825), .C(n2485), .D(n2484), .Y(
add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[5]) );
AOI222X1TS U2243 ( .A0(n2048), .A1(d_ff2_Z[21]), .B0(n1444), .B1(d_ff2_Y[21]), .C0(n2885), .C1(d_ff2_X[21]), .Y(n2032) );
AOI222X1TS U2244 ( .A0(n2918), .A1(d_ff2_Z[14]), .B0(n2913), .B1(d_ff2_Y[14]), .C0(n2912), .C1(d_ff2_X[14]), .Y(n1984) );
MX2X1TS U2245 ( .A(add_subt_module_DMP[32]), .B(n1426), .S0(n1475), .Y(n2408) );
MX2X1TS U2246 ( .A(add_subt_module_DMP[44]), .B(
add_subt_module_Sgf_normalized_result[46]), .S0(n2489), .Y(n1571) );
MX2X1TS U2247 ( .A(add_subt_module_DMP[49]), .B(
add_subt_module_Sgf_normalized_result[51]), .S0(n2489), .Y(n1577) );
AFHCINX2TS U2248 ( .CIN(n1526), .B(n1527), .A(n1528), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[11]), .CO(n2439) );
MX2X1TS U2249 ( .A(add_subt_module_DMP[9]), .B(
add_subt_module_Sgf_normalized_result[11]), .S0(n2487), .Y(n1528) );
AFHCINX2TS U2250 ( .CIN(n1562), .B(n1563), .A(n1564), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[37]), .CO(n2400) );
AFHCINX2TS U2251 ( .CIN(n1496), .B(n1497), .A(n1498), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[31]), .CO(n2409) );
MX2X1TS U2252 ( .A(add_subt_module_DMP[29]), .B(n1408), .S0(n1475), .Y(n1498) );
AOI222X1TS U2253 ( .A0(n1981), .A1(d_ff3_LUT_out[53]), .B0(n2897), .B1(
d_ff3_sh_x_out[53]), .C0(n2899), .C1(d_ff3_sh_y_out[53]), .Y(n1982) );
AOI222X1TS U2254 ( .A0(n2050), .A1(d_ff3_LUT_out[15]), .B0(n2903), .B1(
d_ff3_sh_x_out[15]), .C0(n2885), .C1(d_ff3_sh_y_out[15]), .Y(n1979) );
MX2X1TS U2255 ( .A(add_subt_module_DMP[12]), .B(
add_subt_module_Sgf_normalized_result[14]), .S0(n2487), .Y(n2438) );
MX2X1TS U2256 ( .A(add_subt_module_DMP[16]), .B(n1414), .S0(n1475), .Y(n2432) );
AFHCINX2TS U2257 ( .CIN(n1502), .B(n1503), .A(n1504), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[27]), .CO(n2415) );
MX2X1TS U2258 ( .A(add_subt_module_DMP[25]), .B(n1416), .S0(n1475), .Y(n1504) );
MX2X1TS U2259 ( .A(add_subt_module_DMP[40]), .B(
add_subt_module_Sgf_normalized_result[42]), .S0(n2489), .Y(n1589) );
AFHCINX2TS U2260 ( .CIN(n1511), .B(n1512), .A(n1513), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[21]), .CO(n2424) );
MX2X1TS U2261 ( .A(add_subt_module_DMP[19]), .B(n1423), .S0(n1475), .Y(n1513) );
AOI222X1TS U2262 ( .A0(n2052), .A1(d_ff2_Z[23]), .B0(n2905), .B1(d_ff2_Y[23]), .C0(n2055), .C1(d_ff2_X[23]), .Y(n2053) );
AOI32X1TS U2263 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(n3139), .A2(n1430), .B0(n2851), .B1(d_ff1_shift_region_flag_out[0]), .Y(n2852) );
NAND4XLTS U2264 ( .A(n2825), .B(n2824), .C(n2823), .D(n2822), .Y(
add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[0]) );
NAND3BXLTS U2265 ( .AN(n2503), .B(n2821), .C(n1656), .Y(
add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[2]) );
NAND2BXLTS U2266 ( .AN(data_out_LUT[16]), .B(n2874), .Y(data_out_LUT[12]) );
NAND2BXLTS U2267 ( .AN(data_out_LUT[16]), .B(n1618), .Y(data_out_LUT[43]) );
CLKAND2X2TS U2268 ( .A(n2487), .B(n1400), .Y(n2462) );
MX2X1TS U2269 ( .A(add_subt_module_DMP[2]), .B(
add_subt_module_Sgf_normalized_result[4]), .S0(n2487), .Y(n2453) );
MX2X1TS U2270 ( .A(add_subt_module_DMP[6]), .B(
add_subt_module_Sgf_normalized_result[8]), .S0(n2487), .Y(n2447) );
NAND2BXLTS U2271 ( .AN(add_subt_module_exp_oper_result[2]), .B(n2828), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[2]) );
NAND2BXLTS U2272 ( .AN(n2551), .B(n2229), .Y(n2174) );
OR4X2TS U2273 ( .A(cordic_FSM_state_reg[1]), .B(ack_cordic), .C(n2949), .D(
n2995), .Y(n1308) );
OR2X1TS U2274 ( .A(n1808), .B(n1807), .Y(n1309) );
OR4X2TS U2275 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[0]),
.C(n2956), .D(n2995), .Y(n1310) );
OR2X1TS U2276 ( .A(n2123), .B(n2634), .Y(n1343) );
NOR2X6TS U2277 ( .A(n2652), .B(n2142), .Y(n2783) );
CLKINVX6TS U2278 ( .A(n2547), .Y(n2778) );
CLKINVX3TS U2279 ( .A(n1343), .Y(n1370) );
INVX3TS U2280 ( .A(n1343), .Y(n1371) );
INVX2TS U2281 ( .A(n2055), .Y(n1372) );
CLKINVX3TS U2282 ( .A(n1372), .Y(n1373) );
INVX4TS U2283 ( .A(n1372), .Y(n1374) );
OAI221X1TS U2284 ( .A0(n3034), .A1(add_subt_module_intDY[21]), .B0(n3042),
.B1(add_subt_module_intDY[20]), .C0(n1687), .Y(n1690) );
OAI221X1TS U2285 ( .A0(n3036), .A1(add_subt_module_intDY[30]), .B0(n3012),
.B1(add_subt_module_intDY[29]), .C0(n1679), .Y(n1682) );
OAI21XLTS U2286 ( .A0(add_subt_module_FS_Module_state_reg[3]), .A1(n1800),
.B0(n1610), .Y(n1611) );
NOR4X1TS U2287 ( .A(cordic_FSM_state_reg[1]), .B(n2949), .C(n2951), .D(n2995), .Y(ready_cordic) );
BUFX4TS U2288 ( .A(n1301), .Y(n3240) );
BUFX4TS U2289 ( .A(n1301), .Y(n3243) );
BUFX4TS U2290 ( .A(n1301), .Y(n3229) );
INVX1TS U2291 ( .A(n2808), .Y(n1643) );
CLKINVX6TS U2292 ( .A(n2547), .Y(n2582) );
NOR4X2TS U2293 ( .A(n1959), .B(n2950), .C(n2954), .D(n3001), .Y(n2923) );
BUFX4TS U2294 ( .A(n3153), .Y(n3149) );
NOR2X2TS U2295 ( .A(n1647), .B(add_subt_module_Add_Subt_result[14]), .Y(
n2481) );
NOR2X2TS U2296 ( .A(add_subt_module_FS_Module_state_reg[2]), .B(n2950), .Y(
n1798) );
BUFX4TS U2297 ( .A(n3178), .Y(n3160) );
BUFX4TS U2298 ( .A(n3243), .Y(n3220) );
BUFX4TS U2299 ( .A(n3228), .Y(n3194) );
BUFX4TS U2300 ( .A(n3196), .Y(n3238) );
BUFX4TS U2301 ( .A(n3243), .Y(n3228) );
BUFX3TS U2302 ( .A(n3185), .Y(n3179) );
BUFX4TS U2303 ( .A(n3162), .Y(n3166) );
BUFX4TS U2304 ( .A(n3162), .Y(n3181) );
BUFX4TS U2305 ( .A(n3243), .Y(n3198) );
BUFX4TS U2306 ( .A(n3240), .Y(n3211) );
BUFX4TS U2307 ( .A(n3221), .Y(n3205) );
BUFX4TS U2308 ( .A(n3240), .Y(n3213) );
BUFX4TS U2309 ( .A(n3221), .Y(n3206) );
BUFX4TS U2310 ( .A(n3226), .Y(n3214) );
BUFX4TS U2311 ( .A(n3241), .Y(n3221) );
BUFX4TS U2312 ( .A(n3227), .Y(n3236) );
BUFX4TS U2313 ( .A(n3241), .Y(n3207) );
BUFX4TS U2314 ( .A(n3227), .Y(n3210) );
BUFX4TS U2315 ( .A(n3240), .Y(n3226) );
BUFX4TS U2316 ( .A(n3229), .Y(n3204) );
BUFX4TS U2317 ( .A(n3229), .Y(n3201) );
BUFX4TS U2318 ( .A(n3227), .Y(n3215) );
NOR2X1TS U2319 ( .A(n3003), .B(add_subt_module_FSM_selector_B[0]), .Y(n1770)
);
BUFX4TS U2320 ( .A(n3159), .Y(n3164) );
BUFX4TS U2321 ( .A(n3240), .Y(n3209) );
BUFX4TS U2322 ( .A(n3168), .Y(n3167) );
AOI222X1TS U2323 ( .A0(n2995), .A1(cordic_FSM_state_reg[1]), .B0(n2995),
.B1(n2094), .C0(n2956), .C1(n2951), .Y(n1893) );
INVX2TS U2324 ( .A(n1308), .Y(n1375) );
BUFX4TS U2325 ( .A(n3158), .Y(n3163) );
BUFX4TS U2326 ( .A(n3176), .Y(n3169) );
BUFX4TS U2327 ( .A(n3176), .Y(n3180) );
BUFX4TS U2328 ( .A(n3176), .Y(n3162) );
BUFX4TS U2329 ( .A(n3176), .Y(n3168) );
BUFX4TS U2330 ( .A(n3241), .Y(n3196) );
BUFX4TS U2331 ( .A(n3227), .Y(n3186) );
BUFX4TS U2332 ( .A(n3210), .Y(n3195) );
BUFX4TS U2333 ( .A(n3209), .Y(n3191) );
BUFX4TS U2334 ( .A(n3184), .Y(n3150) );
BUFX4TS U2335 ( .A(n3175), .Y(n3152) );
BUFX4TS U2336 ( .A(n3172), .Y(n3153) );
BUFX4TS U2337 ( .A(n3246), .Y(n3185) );
NOR2X2TS U2338 ( .A(n2994), .B(n3247), .Y(n2058) );
OAI211X2TS U2339 ( .A0(n1888), .A1(n3046), .B0(n1872), .C0(n1890), .Y(n2545)
);
OAI211X2TS U2340 ( .A0(n1888), .A1(n3048), .B0(n1876), .C0(n1890), .Y(n2543)
);
OAI211X2TS U2341 ( .A0(n1888), .A1(n3049), .B0(n1880), .C0(n1890), .Y(n2539)
);
OAI211X2TS U2342 ( .A0(n1888), .A1(n3047), .B0(n1884), .C0(n1890), .Y(n2537)
);
OAI211X2TS U2343 ( .A0(n1888), .A1(n2989), .B0(n1868), .C0(n1890), .Y(n2541)
);
BUFX4TS U2344 ( .A(n3154), .Y(n3171) );
OAI211X2TS U2345 ( .A0(n1888), .A1(n3045), .B0(n1864), .C0(n1890), .Y(n2550)
);
BUFX4TS U2346 ( .A(n3170), .Y(n3161) );
BUFX4TS U2347 ( .A(n3175), .Y(n3172) );
BUFX4TS U2348 ( .A(n3179), .Y(n3183) );
BUFX4TS U2349 ( .A(n3175), .Y(n3173) );
BUFX4TS U2350 ( .A(n3153), .Y(n3156) );
BUFX4TS U2351 ( .A(n3177), .Y(n3174) );
AOI211X1TS U2352 ( .A0(n2535), .A1(n2190), .B0(n2170), .C0(n2169), .Y(n2583)
);
OAI211X2TS U2353 ( .A0(n3078), .A1(n2221), .B0(n1891), .C0(n1890), .Y(n2535)
);
BUFX3TS U2354 ( .A(n3246), .Y(n3178) );
BUFX4TS U2355 ( .A(n3161), .Y(n3154) );
OAI21X4TS U2356 ( .A0(n2997), .A1(n1766), .B0(n1779), .Y(n2158) );
NOR2X4TS U2357 ( .A(cont_iter_out[2]), .B(n2994), .Y(n2871) );
NOR2X2TS U2358 ( .A(n2957), .B(n3146), .Y(n2078) );
OAI21X4TS U2359 ( .A0(n3043), .A1(n1766), .B0(n1778), .Y(n2159) );
NOR2X4TS U2360 ( .A(cont_iter_out[3]), .B(n3247), .Y(n2586) );
INVX4TS U2361 ( .A(n2841), .Y(n1376) );
BUFX3TS U2362 ( .A(n3140), .Y(n2841) );
INVX4TS U2363 ( .A(n2841), .Y(n2883) );
NAND2X2TS U2364 ( .A(n2854), .B(n2855), .Y(data_out_LUT[50]) );
NOR2X4TS U2365 ( .A(cont_iter_out[2]), .B(cont_iter_out[1]), .Y(n2855) );
OAI211XLTS U2366 ( .A0(n2568), .A1(n2226), .B0(n2231), .C0(n2122), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[47]) );
OAI211XLTS U2367 ( .A0(n2562), .A1(n2547), .B0(n2231), .C0(n2205), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[44]) );
OAI211XLTS U2368 ( .A0(n2558), .A1(n2226), .B0(n2231), .C0(n2209), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[42]) );
OAI211XLTS U2369 ( .A0(n2564), .A1(n2547), .B0(n2231), .C0(n2230), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[45]) );
OAI211XLTS U2370 ( .A0(n2566), .A1(n2226), .B0(n2231), .C0(n2200), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[46]) );
OAI211XLTS U2371 ( .A0(n2560), .A1(n2547), .B0(n2231), .C0(n2214), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[43]) );
BUFX4TS U2372 ( .A(n2788), .Y(n2771) );
AOI211X2TS U2373 ( .A0(n2587), .A1(n2854), .B0(n2094), .C0(n1761), .Y(n2875)
);
INVX2TS U2374 ( .A(n2870), .Y(n1761) );
INVX2TS U2375 ( .A(n1355), .Y(n1377) );
INVX2TS U2376 ( .A(n1356), .Y(n1378) );
INVX2TS U2377 ( .A(n1357), .Y(n1379) );
INVX2TS U2378 ( .A(n1358), .Y(n1380) );
INVX2TS U2379 ( .A(n1359), .Y(n1381) );
INVX2TS U2380 ( .A(n1360), .Y(n1382) );
INVX2TS U2381 ( .A(n1361), .Y(n1383) );
INVX2TS U2382 ( .A(n1362), .Y(n1384) );
INVX2TS U2383 ( .A(n1312), .Y(n1385) );
INVX2TS U2384 ( .A(n1313), .Y(n1386) );
INVX2TS U2385 ( .A(n1314), .Y(n1387) );
INVX2TS U2386 ( .A(n1315), .Y(n1388) );
INVX2TS U2387 ( .A(n1316), .Y(n1389) );
INVX2TS U2388 ( .A(n1317), .Y(n1390) );
INVX2TS U2389 ( .A(n1363), .Y(n1391) );
INVX2TS U2390 ( .A(n1364), .Y(n1392) );
INVX2TS U2391 ( .A(n1318), .Y(n1393) );
INVX2TS U2392 ( .A(n1319), .Y(n1394) );
INVX2TS U2393 ( .A(n1365), .Y(n1395) );
INVX2TS U2394 ( .A(n1366), .Y(n1396) );
INVX2TS U2395 ( .A(n1367), .Y(n1397) );
INVX2TS U2396 ( .A(n1368), .Y(n1398) );
INVX2TS U2397 ( .A(n1320), .Y(n1399) );
BUFX6TS U2398 ( .A(n2055), .Y(n2885) );
NAND2X2TS U2399 ( .A(n2617), .B(n2637), .Y(n2140) );
BUFX4TS U2400 ( .A(n1300), .Y(n2637) );
INVX2TS U2401 ( .A(n1321), .Y(n1400) );
INVX2TS U2402 ( .A(n1334), .Y(n1401) );
INVX2TS U2403 ( .A(n1342), .Y(n1402) );
INVX2TS U2404 ( .A(n1337), .Y(n1403) );
INVX2TS U2405 ( .A(n1340), .Y(n1404) );
INVX2TS U2406 ( .A(n1345), .Y(n1405) );
INVX2TS U2407 ( .A(n1311), .Y(n1406) );
INVX2TS U2408 ( .A(n1347), .Y(n1407) );
INVX2TS U2409 ( .A(n1332), .Y(n1408) );
INVX2TS U2410 ( .A(n1304), .Y(n1409) );
INVX2TS U2411 ( .A(n1326), .Y(n1410) );
INVX2TS U2412 ( .A(n1331), .Y(n1411) );
INVX2TS U2413 ( .A(n1305), .Y(n1412) );
INVX2TS U2414 ( .A(n1306), .Y(n1413) );
INVX2TS U2415 ( .A(n1323), .Y(n1414) );
INVX2TS U2416 ( .A(n1322), .Y(n1415) );
INVX2TS U2417 ( .A(n1327), .Y(n1416) );
INVX2TS U2418 ( .A(n1303), .Y(n1417) );
INVX2TS U2419 ( .A(n1338), .Y(n1418) );
INVX2TS U2420 ( .A(n1330), .Y(n1419) );
INVX2TS U2421 ( .A(n1307), .Y(n1420) );
INVX2TS U2422 ( .A(n1324), .Y(n1421) );
INVX2TS U2423 ( .A(n1329), .Y(n1422) );
INVX2TS U2424 ( .A(n1302), .Y(n1423) );
INVX2TS U2425 ( .A(n1336), .Y(n1424) );
INVX2TS U2426 ( .A(n1325), .Y(n1425) );
INVX2TS U2427 ( .A(n1335), .Y(n1426) );
INVX2TS U2428 ( .A(n1341), .Y(n1427) );
INVX2TS U2429 ( .A(n1339), .Y(n1428) );
INVX2TS U2430 ( .A(n1333), .Y(n1429) );
NAND3X2TS U2431 ( .A(cordic_FSM_state_reg[2]), .B(n2956), .C(n2951), .Y(
n3269) );
BUFX4TS U2432 ( .A(n1301), .Y(n3227) );
BUFX4TS U2433 ( .A(n1301), .Y(n3241) );
BUFX4TS U2434 ( .A(n3243), .Y(n3231) );
BUFX4TS U2435 ( .A(n3229), .Y(n3225) );
BUFX4TS U2436 ( .A(n3210), .Y(n3224) );
BUFX4TS U2437 ( .A(n3225), .Y(n3223) );
BUFX4TS U2438 ( .A(n3211), .Y(n3222) );
INVX2TS U2439 ( .A(n1348), .Y(n1430) );
NAND3X2TS U2440 ( .A(n2587), .B(n3146), .C(cont_iter_out[3]), .Y(
data_out_LUT[56]) );
INVX2TS U2441 ( .A(n1310), .Y(n1432) );
AOI222X1TS U2442 ( .A0(n2636), .A1(n2130), .B0(n2635), .B1(n2124), .C0(n1826), .C1(n1813), .Y(n2115) );
OAI21X2TS U2443 ( .A0(n3064), .A1(n1766), .B0(n1777), .Y(n1826) );
CLKINVX6TS U2444 ( .A(n2221), .Y(n2121) );
NAND2X4TS U2445 ( .A(n1857), .B(n1862), .Y(n2221) );
OAI22X2TS U2446 ( .A0(add_subt_module_LZA_output[4]), .A1(n2066), .B0(n2068),
.B1(n1748), .Y(n2089) );
NOR3X1TS U2447 ( .A(n1857), .B(n1862), .C(n2190), .Y(n1858) );
CLKINVX3TS U2448 ( .A(n2196), .Y(n2190) );
BUFX4TS U2449 ( .A(n1858), .Y(n2518) );
BUFX4TS U2450 ( .A(n2761), .Y(n2781) );
AOI222X4TS U2451 ( .A0(n2629), .A1(n1825), .B0(n1824), .B1(n2124), .C0(n1831), .C1(n1812), .Y(n1823) );
AOI222X4TS U2452 ( .A0(n1831), .A1(n1825), .B0(n2629), .B1(n2124), .C0(n1818), .C1(n1813), .Y(n2627) );
AOI222X1TS U2453 ( .A0(n2623), .A1(n1825), .B0(n1831), .B1(n2124), .C0(n1818), .C1(n1812), .Y(n2633) );
INVX3TS U2454 ( .A(n2142), .Y(n1825) );
CLKINVX3TS U2455 ( .A(n2524), .Y(n1433) );
INVX3TS U2456 ( .A(n2524), .Y(n1434) );
INVX2TS U2457 ( .A(n1309), .Y(n1435) );
CLKINVX6TS U2458 ( .A(n2614), .Y(n2616) );
NOR2X4TS U2459 ( .A(n1862), .B(n1863), .Y(n1889) );
OAI2BB1X2TS U2460 ( .A0N(add_subt_module_Add_Subt_result[45]), .A1N(n2752),
.B0(n1787), .Y(n1847) );
OAI2BB1X2TS U2461 ( .A0N(add_subt_module_Add_Subt_result[36]), .A1N(n2752),
.B0(n1782), .Y(n2629) );
OAI2BB1X2TS U2462 ( .A0N(add_subt_module_Add_Subt_result[41]), .A1N(n2752),
.B0(n1790), .Y(n1832) );
OAI2BB1X2TS U2463 ( .A0N(add_subt_module_Add_Subt_result[40]), .A1N(n2752),
.B0(n1791), .Y(n2630) );
OAI2BB1X1TS U2464 ( .A0N(add_subt_module_Add_Subt_result[51]), .A1N(n2752),
.B0(n1806), .Y(n1838) );
OAI2BB1X1TS U2465 ( .A0N(add_subt_module_Add_Subt_result[35]), .A1N(n2752),
.B0(n1773), .Y(n1824) );
BUFX4TS U2466 ( .A(n2779), .Y(n2752) );
BUFX6TS U2467 ( .A(add_subt_module_FSM_selector_D), .Y(n2489) );
OAI21X2TS U2468 ( .A0(n3053), .A1(n1766), .B0(n2112), .Y(n2643) );
NOR2X1TS U2469 ( .A(add_subt_module_Add_Subt_result[20]), .B(
add_subt_module_Add_Subt_result[19]), .Y(n1907) );
NOR3X1TS U2470 ( .A(add_subt_module_Add_Subt_result[46]), .B(
add_subt_module_Add_Subt_result[44]), .C(
add_subt_module_Add_Subt_result[45]), .Y(n2497) );
OAI2BB1X2TS U2471 ( .A0N(add_subt_module_Add_Subt_result[44]), .A1N(n2752),
.B0(n1788), .Y(n1842) );
INVX2TS U2472 ( .A(n1354), .Y(n1436) );
INVX2TS U2473 ( .A(n1351), .Y(n1437) );
INVX2TS U2474 ( .A(n1352), .Y(n1438) );
INVX2TS U2475 ( .A(n1346), .Y(n1439) );
INVX2TS U2476 ( .A(n1353), .Y(n1440) );
INVX2TS U2477 ( .A(n1350), .Y(n1441) );
AOI22X2TS U2478 ( .A0(add_subt_module_LZA_output[4]), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]), .B1(
n3013), .Y(n2083) );
AOI21X2TS U2479 ( .A0(n2121), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]), .B0(
n2120), .Y(n2567) );
INVX2TS U2480 ( .A(n1344), .Y(n1442) );
INVX2TS U2481 ( .A(n1349), .Y(n1443) );
OAI221X1TS U2482 ( .A0(n3032), .A1(add_subt_module_intDY[17]), .B0(n3041),
.B1(add_subt_module_intDY[16]), .C0(n1685), .Y(n1692) );
OAI221X1TS U2483 ( .A0(add_subt_module_intDX[0]), .A1(n3050), .B0(n2983),
.B1(add_subt_module_intDY[0]), .C0(n1663), .Y(n1676) );
OAI221X1TS U2484 ( .A0(n3033), .A1(add_subt_module_intDY[26]), .B0(n3038),
.B1(add_subt_module_intDY[25]), .C0(n1677), .Y(n1684) );
OAI21X2TS U2485 ( .A0(cont_iter_out[1]), .A1(n2866), .B0(n2873), .Y(
data_out_LUT[16]) );
NOR4X2TS U2486 ( .A(n2248), .B(n2321), .C(n2333), .D(n2325), .Y(n2378) );
AOI222X1TS U2487 ( .A0(n2048), .A1(d_ff2_Z[54]), .B0(n2921), .B1(d_ff2_Y[54]), .C0(n2885), .C1(d_ff2_X[54]), .Y(n2034) );
NOR2X2TS U2488 ( .A(n1764), .B(n1620), .Y(
add_subt_module_FSM_Final_Result_load) );
OAI211X1TS U2489 ( .A0(n3015), .A1(n2926), .B0(n2927), .C0(n2059), .Y(n2593)
);
NAND3X2TS U2490 ( .A(n1800), .B(add_subt_module_FS_Module_state_reg[3]), .C(
n1899), .Y(n2927) );
OAI211X2TS U2491 ( .A0(add_subt_module_intDY[20]), .A1(n3042), .B0(n2312),
.C0(n2265), .Y(n2306) );
OAI211X2TS U2492 ( .A0(add_subt_module_intDY[12]), .A1(n3009), .B0(n2293),
.C0(n2266), .Y(n2297) );
INVX3TS U2493 ( .A(n2119), .Y(n2759) );
OAI211X2TS U2494 ( .A0(add_subt_module_intDY[28]), .A1(n3035), .B0(n2264),
.C0(n2255), .Y(n2315) );
BUFX3TS U2495 ( .A(n3179), .Y(n3177) );
CLKXOR2X2TS U2496 ( .A(add_subt_module_intDX[63]), .B(n3244), .Y(n1733) );
AOI22X2TS U2497 ( .A0(n2149), .A1(n2148), .B0(n2635), .B1(n2147), .Y(n2645)
);
AOI22X2TS U2498 ( .A0(n2149), .A1(n2643), .B0(n2148), .B1(n2147), .Y(n2650)
);
NOR2X4TS U2499 ( .A(n2149), .B(n2651), .Y(n1813) );
NOR2X4TS U2500 ( .A(n2474), .B(n1770), .Y(n2149) );
NOR3X4TS U2501 ( .A(add_subt_module_FS_Module_state_reg[2]), .B(n1959), .C(
n2954), .Y(n1994) );
CLKBUFX3TS U2502 ( .A(add_subt_module_FS_Module_state_reg[0]), .Y(n1959) );
AOI211X2TS U2503 ( .A0(add_subt_module_intDX[44]), .A1(n3102), .B0(n2335),
.C0(n2344), .Y(n2342) );
OAI2BB1X2TS U2504 ( .A0N(n1443), .A1N(n2769), .B0(n2744), .Y(n2786) );
AOI222X4TS U2505 ( .A0(n1838), .A1(n2130), .B0(n2619), .B1(n2129), .C0(n2143), .C1(n1812), .Y(n2127) );
OAI2BB1X2TS U2506 ( .A0N(add_subt_module_Add_Subt_result[52]), .A1N(n2779),
.B0(n1803), .Y(n2143) );
AOI222X1TS U2507 ( .A0(d_ff2_Y[58]), .A1(n2905), .B0(d_ff2_X[58]), .B1(n2055), .C0(n2052), .C1(d_ff2_Z[58]), .Y(n1995) );
NOR2X2TS U2508 ( .A(d_ff2_X[58]), .B(n2945), .Y(n2944) );
NOR2X2TS U2509 ( .A(d_ff2_X[60]), .B(n2943), .Y(n2947) );
NOR2X2TS U2510 ( .A(d_ff2_Y[58]), .B(n2939), .Y(n2938) );
NOR2X2TS U2511 ( .A(d_ff2_Y[60]), .B(n2937), .Y(n2941) );
BUFX4TS U2512 ( .A(n2909), .Y(n1444) );
AOI222X1TS U2513 ( .A0(n2052), .A1(d_ff2_Z[28]), .B0(n2921), .B1(d_ff2_Y[28]), .C0(n2885), .C1(d_ff2_X[28]), .Y(n2049) );
AOI222X1TS U2514 ( .A0(n2052), .A1(d_ff2_Z[34]), .B0(n2903), .B1(d_ff2_Y[34]), .C0(n1373), .C1(d_ff2_X[34]), .Y(n2037) );
AOI222X1TS U2515 ( .A0(n2050), .A1(d_ff2_Z[27]), .B0(n2891), .B1(d_ff2_Y[27]), .C0(n2919), .C1(d_ff2_X[27]), .Y(n2033) );
AOI222X1TS U2516 ( .A0(n2052), .A1(d_ff2_Z[1]), .B0(n2913), .B1(d_ff2_Y[1]),
.C0(n2912), .C1(d_ff2_X[1]), .Y(n2013) );
AOI222X1TS U2517 ( .A0(n2918), .A1(d_ff2_Z[32]), .B0(n2905), .B1(d_ff2_Y[32]), .C0(n2896), .C1(d_ff2_X[32]), .Y(n2011) );
AOI222X1TS U2518 ( .A0(n2048), .A1(d_ff2_Z[16]), .B0(n2903), .B1(d_ff2_Y[16]), .C0(n2055), .C1(d_ff2_X[16]), .Y(n1964) );
AOI222X1TS U2519 ( .A0(n2050), .A1(d_ff3_LUT_out[39]), .B0(n2913), .B1(
d_ff3_sh_x_out[39]), .C0(n2899), .C1(d_ff3_sh_y_out[39]), .Y(n2023) );
BUFX3TS U2520 ( .A(n1963), .Y(n2909) );
BUFX4TS U2521 ( .A(n2732), .Y(n2791) );
OAI32X1TS U2522 ( .A0(n1432), .A1(n2243), .A2(n3082), .B0(n2242), .B1(n1310),
.Y(n1139) );
OAI31X1TS U2523 ( .A0(n2243), .A1(n1661), .A2(n2840), .B0(n1660), .Y(n1140)
);
OAI32X1TS U2524 ( .A0(n1659), .A1(n2243), .A2(n2849), .B0(n2065), .B1(n1658),
.Y(n1137) );
NOR2X2TS U2525 ( .A(n1897), .B(cordic_FSM_state_reg[0]), .Y(n2243) );
AOI22X2TS U2526 ( .A0(n2957), .A1(n2587), .B0(n2855), .B1(n2078), .Y(n2858)
);
NOR2X4TS U2527 ( .A(n2955), .B(n2994), .Y(n2587) );
NOR2X4TS U2528 ( .A(n3146), .B(cont_iter_out[3]), .Y(n2854) );
AOI222X1TS U2529 ( .A0(n2625), .A1(n2130), .B0(n1832), .B1(n2129), .C0(n1828), .C1(n1812), .Y(n1844) );
AOI222X1TS U2530 ( .A0(n1828), .A1(n2130), .B0(n2625), .B1(n2129), .C0(n1842), .C1(n1812), .Y(n1849) );
OAI21X2TS U2531 ( .A0(n3051), .A1(n1766), .B0(n1792), .Y(n1828) );
BUFX4TS U2532 ( .A(n2025), .Y(n1445) );
AOI222X1TS U2533 ( .A0(n2050), .A1(d_ff2_Z[9]), .B0(n2905), .B1(d_ff2_Y[9]),
.C0(n2055), .C1(d_ff2_X[9]), .Y(n1965) );
AOI222X1TS U2534 ( .A0(n2052), .A1(d_ff2_Z[4]), .B0(n2921), .B1(d_ff2_Y[4]),
.C0(n2055), .C1(d_ff2_X[4]), .Y(n2015) );
AOI222X1TS U2535 ( .A0(n2048), .A1(d_ff2_Z[7]), .B0(n2921), .B1(d_ff2_Y[7]),
.C0(n2885), .C1(d_ff2_X[7]), .Y(n1998) );
AOI222X1TS U2536 ( .A0(n2050), .A1(d_ff2_Z[20]), .B0(n2903), .B1(d_ff2_Y[20]), .C0(n2896), .C1(d_ff2_X[20]), .Y(n2038) );
AOI222X1TS U2537 ( .A0(n2052), .A1(d_ff2_Z[13]), .B0(n2891), .B1(d_ff2_Y[13]), .C0(n2899), .C1(d_ff2_X[13]), .Y(n2028) );
AOI222X1TS U2538 ( .A0(n2048), .A1(d_ff3_LUT_out[8]), .B0(n2903), .B1(
d_ff3_sh_x_out[8]), .C0(n1373), .C1(d_ff3_sh_y_out[8]), .Y(n2006) );
AOI222X1TS U2539 ( .A0(n2048), .A1(d_ff3_LUT_out[1]), .B0(n2913), .B1(
d_ff3_sh_x_out[1]), .C0(n2919), .C1(d_ff3_sh_y_out[1]), .Y(n2005) );
AOI222X1TS U2540 ( .A0(n2050), .A1(d_ff3_LUT_out[10]), .B0(n2897), .B1(
d_ff3_sh_x_out[10]), .C0(n2912), .C1(d_ff3_sh_y_out[10]), .Y(n2000) );
AOI222X1TS U2541 ( .A0(n2052), .A1(d_ff3_LUT_out[31]), .B0(n2905), .B1(
d_ff3_sh_x_out[31]), .C0(n1373), .C1(d_ff3_sh_y_out[31]), .Y(n2051) );
AOI222X1TS U2542 ( .A0(n2048), .A1(d_ff2_Z[22]), .B0(n1444), .B1(d_ff2_Y[22]), .C0(n1373), .C1(d_ff2_X[22]), .Y(n2044) );
AOI222X1TS U2543 ( .A0(n2052), .A1(d_ff3_LUT_out[21]), .B0(n1444), .B1(
d_ff3_sh_x_out[21]), .C0(n2919), .C1(d_ff3_sh_y_out[21]), .Y(n1978) );
AOI222X1TS U2544 ( .A0(n2048), .A1(d_ff3_LUT_out[18]), .B0(n2891), .B1(
d_ff3_sh_x_out[18]), .C0(n2912), .C1(d_ff3_sh_y_out[18]), .Y(n1974) );
BUFX4TS U2545 ( .A(n1981), .Y(n2025) );
NOR4X2TS U2546 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[1]),
.C(n2951), .D(n2995), .Y(load_cont_var) );
AOI21X2TS U2547 ( .A0(n2121), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[99]), .B0(
n2120), .Y(n2575) );
NOR2X4TS U2548 ( .A(n2121), .B(n2107), .Y(n2120) );
NOR2X2TS U2549 ( .A(add_subt_module_Add_Subt_result[31]), .B(
add_subt_module_Add_Subt_result[32]), .Y(n1930) );
OAI2BB1X2TS U2550 ( .A0N(add_subt_module_Add_Subt_result[32]), .A1N(n2769),
.B0(n1772), .Y(n2154) );
CLKBUFX2TS U2551 ( .A(n2229), .Y(n1446) );
OR2X1TS U2552 ( .A(add_subt_module_Add_Subt_result[54]), .B(
add_subt_module_Add_Subt_result[53]), .Y(n1949) );
OAI2BB1X2TS U2553 ( .A0N(add_subt_module_Add_Subt_result[33]), .A1N(n2769),
.B0(n1767), .Y(n2165) );
CLKINVX6TS U2554 ( .A(n2614), .Y(n2610) );
OAI2BB1X2TS U2555 ( .A0N(add_subt_module_Add_Subt_result[48]), .A1N(n2752),
.B0(n1805), .Y(n1841) );
AFHCINX2TS U2556 ( .CIN(n1520), .B(n1521), .A(n1522), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[15]), .CO(n2433) );
AFHCINX2TS U2557 ( .CIN(n1517), .B(n1518), .A(n1519), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[17]), .CO(n2430) );
AFHCINX2TS U2558 ( .CIN(n1540), .B(n1541), .A(n1542), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[35]), .CO(n2403) );
NOR2X2TS U2559 ( .A(add_subt_module_Add_Subt_result[39]), .B(
add_subt_module_Add_Subt_result[40]), .Y(n1945) );
AFHCINX2TS U2560 ( .CIN(n1505), .B(n1506), .A(n1507), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[25]), .CO(n2418) );
NOR2X1TS U2561 ( .A(add_subt_module_Add_Subt_result[23]), .B(
add_subt_module_Add_Subt_result[22]), .Y(n1633) );
NOR2X2TS U2562 ( .A(add_subt_module_Add_Subt_result[5]), .B(
add_subt_module_Add_Subt_result[6]), .Y(n2477) );
AOI31XLTS U2563 ( .A0(n2800), .A1(add_subt_module_Add_Subt_result[5]), .A2(
n3138), .B0(n2799), .Y(n2824) );
AOI21X2TS U2564 ( .A0(n2121), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]), .B0(
n2120), .Y(n2581) );
AOI21X2TS U2565 ( .A0(n2121), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[98]), .B0(
n2120), .Y(n2573) );
AOI21X2TS U2566 ( .A0(n2121), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[101]), .B0(
n2120), .Y(n2579) );
AOI21X2TS U2567 ( .A0(n2121), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[97]), .B0(
n2120), .Y(n2571) );
AOI21X2TS U2568 ( .A0(n2121), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]), .B0(
n2120), .Y(n2577) );
AOI21X2TS U2569 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[96]), .A1(
n2121), .B0(n2120), .Y(n2569) );
INVX3TS U2570 ( .A(n2526), .Y(n2509) );
BUFX6TS U2571 ( .A(add_subt_module_FSM_selector_D), .Y(n1475) );
AOI222X4TS U2572 ( .A0(n2630), .A1(n1825), .B0(n1818), .B1(n2124), .C0(n1832), .C1(n1812), .Y(n1830) );
AOI222X1TS U2573 ( .A0(n1818), .A1(n1825), .B0(n2623), .B1(n2124), .C0(n2630), .C1(n1812), .Y(n1835) );
AOI222X4TS U2574 ( .A0(n1824), .A1(n1825), .B0(n2159), .B1(n2124), .C0(n2629), .C1(n1812), .Y(n1834) );
INVX3TS U2575 ( .A(n2123), .Y(n2124) );
INVX4TS U2576 ( .A(n2194), .Y(n2527) );
OAI2BB1X2TS U2577 ( .A0N(add_subt_module_Add_Subt_result[47]), .A1N(n2752),
.B0(n1789), .Y(n1839) );
OAI2BB1X2TS U2578 ( .A0N(add_subt_module_Add_Subt_result[28]), .A1N(n2769),
.B0(n1776), .Y(n2635) );
NOR2X2TS U2579 ( .A(n1646), .B(add_subt_module_Add_Subt_result[12]), .Y(
n2506) );
AOI211XLTS U2580 ( .A0(n1941), .A1(add_subt_module_Add_Subt_result[12]),
.B0(n1655), .C0(n1654), .Y(n1656) );
OAI31X1TS U2581 ( .A0(add_subt_module_Add_Subt_result[12]), .A1(
add_subt_module_Add_Subt_result[11]), .A2(n1942), .B0(n1941), .Y(n1943) );
NOR3BX1TS U2582 ( .AN(n1442), .B(add_subt_module_Add_Subt_result[10]), .C(
add_subt_module_Add_Subt_result[9]), .Y(n1942) );
OAI2BB1X1TS U2583 ( .A0N(add_subt_module_Add_Subt_result[3]), .A1N(n2752),
.B0(n2751), .Y(n2790) );
BUFX6TS U2584 ( .A(n1451), .Y(n2461) );
NOR2XLTS U2585 ( .A(n3147), .B(add_subt_module_intDY[11]), .Y(n2281) );
OAI21XLTS U2586 ( .A0(add_subt_module_intDY[35]), .A1(n3022), .B0(
add_subt_module_intDY[34]), .Y(n2353) );
NOR2XLTS U2587 ( .A(n2370), .B(add_subt_module_intDX[48]), .Y(n2371) );
NOR2XLTS U2588 ( .A(n2301), .B(add_subt_module_intDX[16]), .Y(n2302) );
OAI21XLTS U2589 ( .A0(add_subt_module_Add_Subt_result[50]), .A1(n2985), .B0(
n3059), .Y(n2805) );
NOR2XLTS U2590 ( .A(n2804), .B(add_subt_module_Add_Subt_result[38]), .Y(
n2810) );
AOI211XLTS U2591 ( .A0(add_subt_module_intDY[46]), .A1(n2348), .B0(n2347),
.C0(n2346), .Y(n2385) );
NOR2XLTS U2592 ( .A(add_subt_module_Add_Subt_result[34]), .B(
add_subt_module_Add_Subt_result[33]), .Y(n1623) );
OR2X1TS U2593 ( .A(n2815), .B(n1930), .Y(n1910) );
OAI21XLTS U2594 ( .A0(add_subt_module_Add_Subt_result[26]), .A1(n1924), .B0(
n1923), .Y(n1925) );
OAI211XLTS U2595 ( .A0(n2501), .A1(n3053), .B0(n2500), .C0(n2499), .Y(n2502)
);
OAI21XLTS U2596 ( .A0(n2524), .A1(n3045), .B0(n2512), .Y(n2513) );
NOR2XLTS U2597 ( .A(n2221), .B(n2989), .Y(n2210) );
NOR2XLTS U2598 ( .A(n2221), .B(n3045), .Y(n2199) );
OAI21XLTS U2599 ( .A0(n1954), .A1(add_subt_module_Add_Subt_result[29]), .B0(
n1953), .Y(n1955) );
OAI21XLTS U2600 ( .A0(n2524), .A1(n3047), .B0(n2516), .Y(n2517) );
AOI31XLTS U2601 ( .A0(add_subt_module_exp_oper_result[4]), .A1(n2084), .A2(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(
n2073), .Y(n2074) );
OR2X1TS U2602 ( .A(n1901), .B(n2487), .Y(n1150) );
OAI211XLTS U2603 ( .A0(n2152), .A1(n2637), .B0(n2151), .C0(n2150), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[23]) );
AOI211XLTS U2604 ( .A0(cont_var_out[1]), .A1(n2099), .B0(load_cont_var),
.C0(n2098), .Y(n1145) );
OAI211XLTS U2605 ( .A0(n2580), .A1(n2226), .B0(n2509), .C0(n2189), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[53]) );
AFHCINX2TS U2606 ( .CIN(n1490), .B(n1491), .A(n1492), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[3]), .CO(n2451) );
BUFX6TS U2607 ( .A(add_subt_module_FSM_selector_D), .Y(n2487) );
BUFX4TS U2608 ( .A(add_subt_module_FSM_selector_D), .Y(n1544) );
NOR2X8TS U2609 ( .A(n1733), .B(n1544), .Y(n1451) );
NOR2BX1TS U2610 ( .AN(add_subt_module_Sgf_normalized_result[3]), .B(n1544),
.Y(n1452) );
XOR2X1TS U2611 ( .A(n1565), .B(n1452), .Y(n1491) );
OR2X1TS U2612 ( .A(n1544), .B(add_subt_module_Sgf_normalized_result[2]), .Y(
n1453) );
XOR2X1TS U2613 ( .A(n2461), .B(n1453), .Y(n2455) );
NOR2BX1TS U2614 ( .AN(add_subt_module_Sgf_normalized_result[1]), .B(n1544),
.Y(n1454) );
NOR2BX1TS U2615 ( .AN(n1400), .B(n1544), .Y(n1455) );
XOR2X1TS U2616 ( .A(n2461), .B(n1455), .Y(n2460) );
MX2X1TS U2617 ( .A(add_subt_module_DMP[33]), .B(n1403), .S0(n1475), .Y(n1542) );
BUFX4TS U2618 ( .A(add_subt_module_FSM_selector_D), .Y(n1560) );
NOR2BX1TS U2619 ( .AN(n1403), .B(n1560), .Y(n1456) );
XOR2X1TS U2620 ( .A(n1451), .B(n1456), .Y(n1541) );
BUFX4TS U2621 ( .A(add_subt_module_FSM_selector_D), .Y(n1476) );
NOR2BX1TS U2622 ( .AN(n1426), .B(n1476), .Y(n1457) );
XOR2X1TS U2623 ( .A(n1451), .B(n1457), .Y(n2407) );
MX2X1TS U2624 ( .A(add_subt_module_DMP[31]), .B(n1401), .S0(n1475), .Y(n1495) );
NOR2BX1TS U2625 ( .AN(n1401), .B(n1476), .Y(n1458) );
XOR2X1TS U2626 ( .A(n1451), .B(n1458), .Y(n1494) );
NOR2BX1TS U2627 ( .AN(n1429), .B(n1476), .Y(n1459) );
XOR2X1TS U2628 ( .A(n1451), .B(n1459), .Y(n2410) );
NOR2BX1TS U2629 ( .AN(n1408), .B(n1476), .Y(n1460) );
XOR2X1TS U2630 ( .A(n1451), .B(n1460), .Y(n1497) );
NOR2BX1TS U2631 ( .AN(n1411), .B(n1476), .Y(n1461) );
XOR2X1TS U2632 ( .A(n1451), .B(n1461), .Y(n2413) );
NOR2BX1TS U2633 ( .AN(n1419), .B(n1476), .Y(n1462) );
XOR2X1TS U2634 ( .A(n1451), .B(n1462), .Y(n1500) );
NOR2BX1TS U2635 ( .AN(n1422), .B(n1476), .Y(n1463) );
XOR2X1TS U2636 ( .A(n1451), .B(n1463), .Y(n2416) );
NOR2BX1TS U2637 ( .AN(n1416), .B(n1476), .Y(n1464) );
XOR2X1TS U2638 ( .A(n1451), .B(n1464), .Y(n1503) );
NOR2BX1TS U2639 ( .AN(n1420), .B(n1476), .Y(n1465) );
XOR2X1TS U2640 ( .A(n1451), .B(n1465), .Y(n2419) );
NOR2BX1TS U2641 ( .AN(n1413), .B(n1476), .Y(n1466) );
XOR2X1TS U2642 ( .A(n1451), .B(n1466), .Y(n1506) );
NOR2BX1TS U2643 ( .AN(n1412), .B(n1476), .Y(n1467) );
XOR2X1TS U2644 ( .A(n1451), .B(n1467), .Y(n2422) );
NOR2BX1TS U2645 ( .AN(n1409), .B(n1476), .Y(n1468) );
XOR2X1TS U2646 ( .A(n1451), .B(n1468), .Y(n1509) );
NOR2BX1TS U2647 ( .AN(n1417), .B(n1476), .Y(n1469) );
XOR2X1TS U2648 ( .A(n1451), .B(n1469), .Y(n2425) );
NOR2BX1TS U2649 ( .AN(n1423), .B(n1476), .Y(n1470) );
XOR2X1TS U2650 ( .A(n1565), .B(n1470), .Y(n1512) );
NOR2BX1TS U2651 ( .AN(n1410), .B(n1476), .Y(n1471) );
XOR2X1TS U2652 ( .A(n1565), .B(n1471), .Y(n2428) );
NOR2BX1TS U2653 ( .AN(n1421), .B(n1476), .Y(n1472) );
XOR2X1TS U2654 ( .A(n1565), .B(n1472), .Y(n1515) );
NOR2BX1TS U2655 ( .AN(n1414), .B(n1476), .Y(n1473) );
XOR2X1TS U2656 ( .A(n1565), .B(n1473), .Y(n2431) );
NOR2BX1TS U2657 ( .AN(n1425), .B(n1476), .Y(n1474) );
XOR2X1TS U2658 ( .A(n1565), .B(n1474), .Y(n1518) );
NOR2BX1TS U2659 ( .AN(n1415), .B(n1476), .Y(n1477) );
XOR2X1TS U2660 ( .A(n1565), .B(n1477), .Y(n2434) );
NOR2BX1TS U2661 ( .AN(add_subt_module_Sgf_normalized_result[15]), .B(n1544),
.Y(n1478) );
XOR2X1TS U2662 ( .A(n1565), .B(n1478), .Y(n1521) );
NOR2BX1TS U2663 ( .AN(add_subt_module_Sgf_normalized_result[14]), .B(n1544),
.Y(n1479) );
XOR2X1TS U2664 ( .A(n1565), .B(n1479), .Y(n2437) );
NOR2BX1TS U2665 ( .AN(add_subt_module_Sgf_normalized_result[13]), .B(n1544),
.Y(n1480) );
XOR2X1TS U2666 ( .A(n1565), .B(n1480), .Y(n1524) );
NOR2BX1TS U2667 ( .AN(add_subt_module_Sgf_normalized_result[12]), .B(n1544),
.Y(n1481) );
XOR2X1TS U2668 ( .A(n1565), .B(n1481), .Y(n2440) );
NOR2BX1TS U2669 ( .AN(add_subt_module_Sgf_normalized_result[11]), .B(n1544),
.Y(n1482) );
XOR2X1TS U2670 ( .A(n1565), .B(n1482), .Y(n1527) );
NOR2BX1TS U2671 ( .AN(add_subt_module_Sgf_normalized_result[10]), .B(n1544),
.Y(n1483) );
XOR2X1TS U2672 ( .A(n1565), .B(n1483), .Y(n2443) );
NOR2BX1TS U2673 ( .AN(add_subt_module_Sgf_normalized_result[9]), .B(n1544),
.Y(n1484) );
XOR2X1TS U2674 ( .A(n1565), .B(n1484), .Y(n1530) );
NOR2BX1TS U2675 ( .AN(add_subt_module_Sgf_normalized_result[8]), .B(n1544),
.Y(n1485) );
XOR2X1TS U2676 ( .A(n1565), .B(n1485), .Y(n2446) );
NOR2BX1TS U2677 ( .AN(add_subt_module_Sgf_normalized_result[7]), .B(n1544),
.Y(n1486) );
XOR2X1TS U2678 ( .A(n1565), .B(n1486), .Y(n1533) );
NOR2BX1TS U2679 ( .AN(add_subt_module_Sgf_normalized_result[6]), .B(n1544),
.Y(n1487) );
XOR2X1TS U2680 ( .A(n1565), .B(n1487), .Y(n2449) );
NOR2BX1TS U2681 ( .AN(add_subt_module_Sgf_normalized_result[5]), .B(n1544),
.Y(n1488) );
XOR2X1TS U2682 ( .A(n1565), .B(n1488), .Y(n1536) );
NOR2BX1TS U2683 ( .AN(add_subt_module_Sgf_normalized_result[4]), .B(n1544),
.Y(n1489) );
XOR2X1TS U2684 ( .A(n1565), .B(n1489), .Y(n2452) );
MX2X1TS U2685 ( .A(add_subt_module_DMP[35]), .B(n1404), .S0(n2489), .Y(n1564) );
NOR2BX1TS U2686 ( .AN(n1404), .B(n1560), .Y(n1538) );
XOR2X1TS U2687 ( .A(n1451), .B(n1538), .Y(n1563) );
NOR2BX1TS U2688 ( .AN(n1424), .B(n1560), .Y(n1539) );
XOR2X1TS U2689 ( .A(n1451), .B(n1539), .Y(n2404) );
NOR2BX1TS U2690 ( .AN(add_subt_module_Sgf_normalized_result[54]), .B(n1560),
.Y(n1543) );
XOR2X1TS U2691 ( .A(n2461), .B(n1543), .Y(n2396) );
NOR2BX1TS U2692 ( .AN(n1407), .B(n2487), .Y(n1545) );
XOR2X1TS U2693 ( .A(n2461), .B(n1545), .Y(n1581) );
NOR2BX1TS U2694 ( .AN(add_subt_module_Sgf_normalized_result[52]), .B(n1560),
.Y(n1546) );
XOR2X1TS U2695 ( .A(n2461), .B(n1546), .Y(n1602) );
NOR2BX1TS U2696 ( .AN(add_subt_module_Sgf_normalized_result[51]), .B(n1560),
.Y(n1547) );
XOR2X1TS U2697 ( .A(n2461), .B(n1547), .Y(n1578) );
NOR2BX1TS U2698 ( .AN(add_subt_module_Sgf_normalized_result[50]), .B(n1560),
.Y(n1548) );
XOR2X1TS U2699 ( .A(n2461), .B(n1548), .Y(n1616) );
NOR2BX1TS U2700 ( .AN(add_subt_module_Sgf_normalized_result[49]), .B(n1560),
.Y(n1549) );
XOR2X1TS U2701 ( .A(n2461), .B(n1549), .Y(n1608) );
NOR2BX1TS U2702 ( .AN(add_subt_module_Sgf_normalized_result[48]), .B(n1560),
.Y(n1550) );
XOR2X1TS U2703 ( .A(n2461), .B(n1550), .Y(n1575) );
NOR2BX1TS U2704 ( .AN(add_subt_module_Sgf_normalized_result[47]), .B(n1560),
.Y(n1551) );
XOR2X1TS U2705 ( .A(n2461), .B(n1551), .Y(n1605) );
NOR2BX1TS U2706 ( .AN(add_subt_module_Sgf_normalized_result[46]), .B(n1560),
.Y(n1552) );
XOR2X1TS U2707 ( .A(n2461), .B(n1552), .Y(n1572) );
NOR2BX1TS U2708 ( .AN(add_subt_module_Sgf_normalized_result[45]), .B(n1560),
.Y(n1553) );
XOR2X1TS U2709 ( .A(n2461), .B(n1553), .Y(n1596) );
NOR2BX1TS U2710 ( .AN(add_subt_module_Sgf_normalized_result[44]), .B(n1560),
.Y(n1554) );
XOR2X1TS U2711 ( .A(n2461), .B(n1554), .Y(n1569) );
NOR2BX1TS U2712 ( .AN(add_subt_module_Sgf_normalized_result[43]), .B(n1560),
.Y(n1555) );
XOR2X1TS U2713 ( .A(n2461), .B(n1555), .Y(n1593) );
NOR2BX1TS U2714 ( .AN(add_subt_module_Sgf_normalized_result[42]), .B(n1560),
.Y(n1556) );
XOR2X1TS U2715 ( .A(n1451), .B(n1556), .Y(n1590) );
NOR2BX1TS U2716 ( .AN(n1427), .B(n1560), .Y(n1557) );
XOR2X1TS U2717 ( .A(n2461), .B(n1557), .Y(n1587) );
NOR2BX1TS U2718 ( .AN(n1402), .B(n1560), .Y(n1558) );
XOR2X1TS U2719 ( .A(n2461), .B(n1558), .Y(n1584) );
MX2X1TS U2720 ( .A(add_subt_module_DMP[38]), .B(n1402), .S0(n2489), .Y(n1583) );
NOR2BX1TS U2721 ( .AN(n1428), .B(n1560), .Y(n1559) );
XOR2X1TS U2722 ( .A(n2461), .B(n1559), .Y(n2398) );
NOR2BX1TS U2723 ( .AN(n1418), .B(n1560), .Y(n1561) );
XOR2X1TS U2724 ( .A(n1451), .B(n1561), .Y(n2401) );
CMPR32X2TS U2725 ( .A(n1587), .B(n1586), .C(n1585), .CO(n1588), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[41]) );
CMPR32X2TS U2726 ( .A(n1590), .B(n1589), .C(n1588), .CO(n1591), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[42]) );
CMPR32X2TS U2727 ( .A(n1593), .B(n1592), .C(n1591), .CO(n1567), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[43]) );
CMPR32X2TS U2728 ( .A(n1596), .B(n1595), .C(n1594), .CO(n1570), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[45]) );
AOI2BB2XLTS U2729 ( .B0(r_mode[0]), .B1(r_mode[1]), .A0N(
add_subt_module_Sgf_normalized_result[1]), .A1N(n1400), .Y(n1597) );
OA21XLTS U2730 ( .A0(r_mode[1]), .A1(add_subt_module_sign_final_result),
.B0(n1597), .Y(n1598) );
OAI21X1TS U2731 ( .A0(r_mode[0]), .A1(n1450), .B0(n1598), .Y(n2594) );
NOR2X2TS U2732 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(
add_subt_module_FS_Module_state_reg[2]), .Y(n1960) );
NAND2X1TS U2733 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(n1959), .Y(
n1620) );
INVX2TS U2734 ( .A(n1620), .Y(n1599) );
NAND2X1TS U2735 ( .A(n1960), .B(n1599), .Y(n1609) );
NOR2X1TS U2736 ( .A(n2594), .B(n1609), .Y(n1901) );
CMPR32X2TS U2737 ( .A(n1602), .B(n1601), .C(n1600), .CO(n1579), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[52]) );
CMPR32X2TS U2738 ( .A(n1605), .B(n1604), .C(n1603), .CO(n1573), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[47]) );
CMPR32X2TS U2739 ( .A(n1608), .B(n1607), .C(n1606), .CO(n1614), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[49]) );
NOR2X2TS U2740 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(n1959), .Y(
n2060) );
NAND2X1TS U2741 ( .A(add_subt_module_FS_Module_state_reg[2]), .B(n2950), .Y(
n1764) );
INVX2TS U2742 ( .A(n1764), .Y(n1800) );
NAND2X1TS U2743 ( .A(n2060), .B(n1800), .Y(n2933) );
INVX2TS U2744 ( .A(n1609), .Y(n2595) );
INVX2TS U2745 ( .A(add_subt_module_add_overflow_flag), .Y(n1961) );
INVX2TS U2746 ( .A(n1959), .Y(n1899) );
NOR3XLTS U2747 ( .A(n1961), .B(n1328), .C(n1994), .Y(n1610) );
AOI211XLTS U2748 ( .A0(add_subt_module_FS_Module_state_reg[2]), .A1(
add_subt_module_FS_Module_state_reg[3]), .B0(n2595), .C0(n1611), .Y(
n1612) );
OAI21XLTS U2749 ( .A0(add_subt_module_FSM_selector_C), .A1(n2933), .B0(n1612), .Y(n1613) );
BUFX3TS U2750 ( .A(n1613), .Y(n3145) );
CMPR32X2TS U2751 ( .A(n1616), .B(n1615), .C(n1614), .CO(n1576), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[50]) );
NAND3XLTS U2752 ( .A(n2949), .B(n2956), .C(n2995), .Y(n1897) );
CLKBUFX2TS U2753 ( .A(n1301), .Y(n3242) );
NOR2XLTS U2754 ( .A(n3146), .B(n2951), .Y(n3273) );
INVX2TS U2755 ( .A(n2854), .Y(n1617) );
INVX2TS U2756 ( .A(n2855), .Y(n2859) );
NAND2X1TS U2757 ( .A(cont_iter_out[3]), .B(n2859), .Y(n2861) );
NOR2X2TS U2758 ( .A(cont_iter_out[1]), .B(n2955), .Y(n2876) );
NAND2X1TS U2759 ( .A(n2586), .B(n2876), .Y(n2870) );
OAI211XLTS U2760 ( .A0(n1617), .A1(n2955), .B0(n2861), .C0(n2870), .Y(
data_out_LUT[14]) );
INVX2TS U2761 ( .A(n2858), .Y(data_out_LUT[17]) );
INVX2TS U2762 ( .A(n2586), .Y(n2866) );
INVX2TS U2763 ( .A(n1618), .Y(n1619) );
NOR2X1TS U2764 ( .A(n1619), .B(data_out_LUT[17]), .Y(n2865) );
INVX2TS U2765 ( .A(n2587), .Y(n2585) );
OAI211XLTS U2766 ( .A0(cont_iter_out[1]), .A1(n2866), .B0(n2865), .C0(n2585),
.Y(data_out_LUT[0]) );
INVX2TS U2767 ( .A(data_out_LUT[56]), .Y(n2094) );
OAI21XLTS U2768 ( .A0(n2994), .A1(n2866), .B0(n2875), .Y(data_out_LUT[23])
);
NAND2X1TS U2769 ( .A(n2855), .B(n2586), .Y(data_out_LUT[40]) );
NAND2X1TS U2770 ( .A(n2871), .B(n2586), .Y(data_out_LUT[38]) );
NOR2X1TS U2771 ( .A(add_subt_module_Add_Subt_result[9]), .B(n1442), .Y(n1938) );
NOR2X1TS U2772 ( .A(n1949), .B(n1947), .Y(n1650) );
NAND2X1TS U2773 ( .A(n1650), .B(n1648), .Y(n2808) );
NOR2X1TS U2774 ( .A(n2808), .B(add_subt_module_Add_Subt_result[47]), .Y(
n2505) );
NAND2X1TS U2775 ( .A(n2505), .B(n2497), .Y(n1946) );
NOR2X1TS U2776 ( .A(n1946), .B(n1621), .Y(n1632) );
NAND2X1TS U2777 ( .A(n1632), .B(n2996), .Y(n2803) );
NOR2X1TS U2778 ( .A(add_subt_module_Add_Subt_result[36]), .B(
add_subt_module_Add_Subt_result[35]), .Y(n1911) );
NOR2X1TS U2779 ( .A(add_subt_module_Add_Subt_result[38]), .B(
add_subt_module_Add_Subt_result[37]), .Y(n1909) );
NOR2X2TS U2780 ( .A(n2803), .B(n1622), .Y(n1651) );
NAND2X1TS U2781 ( .A(n1651), .B(n1623), .Y(n2815) );
NAND2X1TS U2782 ( .A(n1930), .B(n2997), .Y(n1624) );
NOR2X2TS U2783 ( .A(n2815), .B(n1624), .Y(n1923) );
NOR2X1TS U2784 ( .A(add_subt_module_Add_Subt_result[29]), .B(
add_subt_module_Add_Subt_result[28]), .Y(n1913) );
INVX2TS U2785 ( .A(n1913), .Y(n1924) );
NOR2X1TS U2786 ( .A(n1924), .B(add_subt_module_Add_Subt_result[27]), .Y(
n1625) );
NAND2X2TS U2787 ( .A(n1923), .B(n1625), .Y(n2501) );
NOR2X1TS U2788 ( .A(add_subt_module_Add_Subt_result[26]), .B(
add_subt_module_Add_Subt_result[25]), .Y(n1915) );
NAND2X1TS U2789 ( .A(n1915), .B(n2999), .Y(n1626) );
NOR2X2TS U2790 ( .A(n2501), .B(n1626), .Y(n1914) );
INVX2TS U2791 ( .A(n1633), .Y(n1627) );
NOR2XLTS U2792 ( .A(n1627), .B(add_subt_module_Add_Subt_result[21]), .Y(
n1628) );
NAND2X2TS U2793 ( .A(n1914), .B(n1628), .Y(n1908) );
INVX2TS U2794 ( .A(n1907), .Y(n1629) );
NOR2X2TS U2795 ( .A(n1908), .B(n1629), .Y(n2814) );
NOR2X1TS U2796 ( .A(add_subt_module_Add_Subt_result[18]), .B(
add_subt_module_Add_Subt_result[17]), .Y(n1956) );
NAND2X1TS U2797 ( .A(n1956), .B(n3002), .Y(n2479) );
NOR2XLTS U2798 ( .A(n2479), .B(add_subt_module_Add_Subt_result[15]), .Y(
n1630) );
NAND2X1TS U2799 ( .A(n2814), .B(n1630), .Y(n1647) );
NAND2X1TS U2800 ( .A(n2481), .B(n2972), .Y(n1646) );
NOR2XLTS U2801 ( .A(add_subt_module_Add_Subt_result[11]), .B(
add_subt_module_Add_Subt_result[10]), .Y(n1631) );
NAND2X1TS U2802 ( .A(n2506), .B(n1631), .Y(n2478) );
NOR3BX2TS U2803 ( .AN(n1938), .B(n2478), .C(
add_subt_module_Add_Subt_result[7]), .Y(n2800) );
NAND2X1TS U2804 ( .A(n2800), .B(n2477), .Y(n1936) );
INVX2TS U2805 ( .A(n1928), .Y(n1637) );
NOR3BX1TS U2806 ( .AN(add_subt_module_Add_Subt_result[19]), .B(n1908), .C(
add_subt_module_Add_Subt_result[20]), .Y(n1636) );
AOI21X1TS U2807 ( .A0(n2988), .A1(add_subt_module_Add_Subt_result[39]), .B0(
add_subt_module_Add_Subt_result[41]), .Y(n1634) );
INVX2TS U2808 ( .A(n1632), .Y(n2801) );
INVX2TS U2809 ( .A(n1908), .Y(n1639) );
AOI211X1TS U2810 ( .A0(n3085), .A1(n2988), .B0(n1946), .C0(
add_subt_module_Add_Subt_result[43]), .Y(n1638) );
AOI21X1TS U2811 ( .A0(n1639), .A1(add_subt_module_Add_Subt_result[20]), .B0(
n1638), .Y(n1642) );
INVX2TS U2812 ( .A(n2477), .Y(n1640) );
OAI21XLTS U2813 ( .A0(n1443), .A1(n1640), .B0(n2800), .Y(n1641) );
OAI21XLTS U2814 ( .A0(add_subt_module_Add_Subt_result[28]), .A1(n3084), .B0(
n2986), .Y(n1644) );
AOI21X1TS U2815 ( .A0(n2506), .A1(add_subt_module_Add_Subt_result[11]), .B0(
n1645), .Y(n2821) );
INVX2TS U2816 ( .A(n1646), .Y(n1941) );
AOI21X1TS U2817 ( .A0(n2972), .A1(n3079), .B0(n1647), .Y(n1655) );
NAND2X1TS U2818 ( .A(n1914), .B(add_subt_module_Add_Subt_result[22]), .Y(
n1931) );
NAND2X1TS U2819 ( .A(n1923), .B(add_subt_module_Add_Subt_result[28]), .Y(
n1954) );
INVX2TS U2820 ( .A(n1648), .Y(n1649) );
AOI22X1TS U2821 ( .A0(n1651), .A1(add_subt_module_Add_Subt_result[34]), .B0(
n1650), .B1(n1649), .Y(n1652) );
NAND2X1TS U2822 ( .A(n1651), .B(add_subt_module_Add_Subt_result[33]), .Y(
n2813) );
AND4X1TS U2823 ( .A(n1954), .B(n1652), .C(n1910), .D(n2813), .Y(n1653) );
OAI21XLTS U2824 ( .A0(n1931), .A1(add_subt_module_Add_Subt_result[23]), .B0(
n1653), .Y(n1654) );
BUFX3TS U2825 ( .A(n3231), .Y(n3239) );
BUFX3TS U2826 ( .A(n3227), .Y(n3216) );
BUFX3TS U2827 ( .A(n3204), .Y(n3208) );
BUFX3TS U2828 ( .A(n3241), .Y(n3219) );
BUFX3TS U2829 ( .A(n3227), .Y(n3218) );
BUFX3TS U2830 ( .A(n3213), .Y(n3217) );
BUFX3TS U2831 ( .A(n3241), .Y(n3212) );
BUFX3TS U2832 ( .A(n3154), .Y(n3176) );
BUFX3TS U2833 ( .A(n3243), .Y(n3197) );
BUFX3TS U2834 ( .A(n3191), .Y(n3230) );
BUFX3TS U2835 ( .A(n3236), .Y(n3199) );
BUFX3TS U2836 ( .A(n3214), .Y(n3200) );
BUFX3TS U2837 ( .A(n3236), .Y(n3187) );
BUFX3TS U2838 ( .A(n3201), .Y(n3235) );
BUFX3TS U2839 ( .A(n3210), .Y(n3234) );
BUFX3TS U2840 ( .A(n3205), .Y(n3237) );
BUFX3TS U2841 ( .A(n3204), .Y(n3188) );
BUFX3TS U2842 ( .A(n3221), .Y(n3189) );
BUFX3TS U2843 ( .A(n3198), .Y(n3190) );
BUFX3TS U2844 ( .A(n3215), .Y(n3233) );
BUFX3TS U2845 ( .A(n3240), .Y(n3192) );
BUFX3TS U2846 ( .A(n3215), .Y(n3232) );
BUFX3TS U2847 ( .A(n3229), .Y(n3193) );
BUFX3TS U2848 ( .A(n3185), .Y(n3175) );
BUFX3TS U2849 ( .A(n3181), .Y(n3184) );
BUFX3TS U2850 ( .A(n3182), .Y(n3151) );
BUFX3TS U2851 ( .A(n3198), .Y(n3203) );
BUFX3TS U2852 ( .A(n3185), .Y(n3155) );
BUFX3TS U2853 ( .A(n3175), .Y(n3158) );
BUFX3TS U2854 ( .A(n3181), .Y(n3157) );
BUFX3TS U2855 ( .A(n3179), .Y(n3159) );
BUFX3TS U2856 ( .A(n3201), .Y(n3202) );
BUFX3TS U2857 ( .A(n3185), .Y(n3170) );
BUFX3TS U2858 ( .A(n3153), .Y(n3182) );
BUFX3TS U2859 ( .A(n3185), .Y(n3165) );
CLKBUFX2TS U2860 ( .A(n3140), .Y(n2832) );
INVX4TS U2861 ( .A(n2832), .Y(n2834) );
AO22XLTS U2862 ( .A0(n2836), .A1(d_ff_Zn[4]), .B0(n2841), .B1(d_ff1_Z[4]),
.Y(first_mux_Z[4]) );
AO22XLTS U2863 ( .A0(n2830), .A1(d_ff_Zn[2]), .B0(n2841), .B1(d_ff1_Z[2]),
.Y(first_mux_Z[2]) );
AO22XLTS U2864 ( .A0(n2834), .A1(d_ff_Zn[5]), .B0(n2841), .B1(d_ff1_Z[5]),
.Y(first_mux_Z[5]) );
AO22XLTS U2865 ( .A0(n2837), .A1(d_ff_Zn[3]), .B0(n2841), .B1(d_ff1_Z[3]),
.Y(first_mux_Z[3]) );
BUFX4TS U2866 ( .A(n2827), .Y(n2828) );
NAND2X1TS U2867 ( .A(n2828), .B(n3000), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[4]) );
NAND2X1TS U2868 ( .A(n2828), .B(n3062), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[5]) );
NAND2X1TS U2869 ( .A(n2828), .B(n2998), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[3]) );
BUFX3TS U2870 ( .A(n3140), .Y(n2833) );
AO22XLTS U2871 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[44]), .B0(n2833), .B1(
d_ff1_Z[44]), .Y(first_mux_Z[44]) );
AO22XLTS U2872 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[32]), .B0(n2833), .B1(
d_ff1_Z[32]), .Y(first_mux_Z[32]) );
AO22XLTS U2873 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[1]), .B0(n3140), .B1(
d_ff1_Z[1]), .Y(first_mux_Z[1]) );
INVX4TS U2874 ( .A(n2832), .Y(n2837) );
AO22XLTS U2875 ( .A0(n2837), .A1(d_ff_Zn[29]), .B0(n2833), .B1(d_ff1_Z[29]),
.Y(first_mux_Z[29]) );
AO22XLTS U2876 ( .A0(n2836), .A1(d_ff_Zn[34]), .B0(n2833), .B1(d_ff1_Z[34]),
.Y(first_mux_Z[34]) );
AO22XLTS U2877 ( .A0(n2830), .A1(d_ff_Zn[36]), .B0(n2833), .B1(d_ff1_Z[36]),
.Y(first_mux_Z[36]) );
INVX4TS U2878 ( .A(n2832), .Y(n2836) );
AO22XLTS U2879 ( .A0(n2834), .A1(d_ff_Zn[18]), .B0(n2833), .B1(d_ff1_Z[18]),
.Y(first_mux_Z[18]) );
AO22XLTS U2880 ( .A0(n2834), .A1(d_ff_Zn[28]), .B0(n2833), .B1(d_ff1_Z[28]),
.Y(first_mux_Z[28]) );
AO22XLTS U2881 ( .A0(n2837), .A1(d_ff_Zn[19]), .B0(n2833), .B1(d_ff1_Z[19]),
.Y(first_mux_Z[19]) );
AO22XLTS U2882 ( .A0(n2837), .A1(d_ff_Zn[33]), .B0(n2833), .B1(d_ff1_Z[33]),
.Y(first_mux_Z[33]) );
AO22XLTS U2883 ( .A0(n2836), .A1(d_ff_Zn[35]), .B0(n2833), .B1(d_ff1_Z[35]),
.Y(first_mux_Z[35]) );
AO22XLTS U2884 ( .A0(n2830), .A1(d_ff_Zn[31]), .B0(n2833), .B1(d_ff1_Z[31]),
.Y(first_mux_Z[31]) );
AO22XLTS U2885 ( .A0(n2834), .A1(d_ff_Zn[30]), .B0(n2833), .B1(d_ff1_Z[30]),
.Y(first_mux_Z[30]) );
AO22XLTS U2886 ( .A0(n2837), .A1(d_ff_Zn[37]), .B0(n2833), .B1(d_ff1_Z[37]),
.Y(first_mux_Z[37]) );
NOR3X1TS U2887 ( .A(cordic_FSM_state_reg[0]), .B(cordic_FSM_state_reg[2]),
.C(n2956), .Y(n1894) );
INVX2TS U2888 ( .A(n1894), .Y(n2591) );
NOR2X1TS U2889 ( .A(n2949), .B(n2591), .Y(n1659) );
BUFX3TS U2890 ( .A(n3136), .Y(n2849) );
NOR2X1TS U2891 ( .A(d_ff1_shift_region_flag_out[1]), .B(n1430), .Y(n2851) );
AOI21X1TS U2892 ( .A0(n1430), .A1(d_ff1_shift_region_flag_out[1]), .B0(n2851), .Y(n1657) );
XNOR2X1TS U2893 ( .A(d_ff1_shift_region_flag_out[0]), .B(n1657), .Y(n2065)
);
INVX2TS U2894 ( .A(n1659), .Y(n1658) );
NAND2X1TS U2895 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[0]),
.Y(n2241) );
NOR3X1TS U2896 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[2]),
.C(n2241), .Y(n1661) );
BUFX4TS U2897 ( .A(n3140), .Y(n2840) );
NAND2X1TS U2898 ( .A(n1661), .B(data_out_LUT[50]), .Y(n1660) );
NAND2X1TS U2899 ( .A(n2060), .B(n1798), .Y(n2062) );
INVX2TS U2900 ( .A(n2062), .Y(n3245) );
NAND2X1TS U2901 ( .A(n1800), .B(n1328), .Y(n2926) );
OAI22X1TS U2902 ( .A0(n3029), .A1(add_subt_module_intDY[1]), .B0(n2966),
.B1(add_subt_module_intDY[62]), .Y(n1662) );
AOI221X1TS U2903 ( .A0(n3029), .A1(add_subt_module_intDY[1]), .B0(
add_subt_module_intDY[62]), .B1(n2966), .C0(n1662), .Y(n1663) );
AOI22X1TS U2904 ( .A0(n2969), .A1(add_subt_module_intDY[5]), .B0(n3039),
.B1(add_subt_module_intDY[4]), .Y(n1664) );
OAI221XLTS U2905 ( .A0(n2969), .A1(add_subt_module_intDY[5]), .B0(n3039),
.B1(add_subt_module_intDY[4]), .C0(n1664), .Y(n1675) );
AOI22X1TS U2906 ( .A0(n3031), .A1(add_subt_module_intDY[3]), .B0(n2981),
.B1(add_subt_module_intDY[2]), .Y(n1665) );
OAI221XLTS U2907 ( .A0(n3031), .A1(add_subt_module_intDY[3]), .B0(n2981),
.B1(add_subt_module_intDY[2]), .C0(n1665), .Y(n1674) );
OAI22X1TS U2908 ( .A0(n3020), .A1(add_subt_module_intDY[8]), .B0(n2959),
.B1(add_subt_module_intDY[9]), .Y(n1666) );
AOI221X1TS U2909 ( .A0(n3020), .A1(add_subt_module_intDY[8]), .B0(
add_subt_module_intDY[9]), .B1(n2959), .C0(n1666), .Y(n1672) );
OAI22X1TS U2910 ( .A0(n3008), .A1(add_subt_module_intDY[6]), .B0(n2967),
.B1(add_subt_module_intDY[7]), .Y(n1667) );
AOI221X1TS U2911 ( .A0(n3008), .A1(add_subt_module_intDY[6]), .B0(
add_subt_module_intDY[7]), .B1(n2967), .C0(n1667), .Y(n1671) );
OAI22X1TS U2912 ( .A0(n3009), .A1(add_subt_module_intDY[12]), .B0(n3004),
.B1(add_subt_module_intDY[13]), .Y(n1668) );
AOI221X1TS U2913 ( .A0(n3009), .A1(add_subt_module_intDY[12]), .B0(
add_subt_module_intDY[13]), .B1(n3004), .C0(n1668), .Y(n1670) );
OAI22X1TS U2914 ( .A0(n2958), .A1(add_subt_module_intDY[10]), .B0(n3147),
.B1(add_subt_module_intDY[11]), .Y(n2279) );
AOI221X1TS U2915 ( .A0(n2958), .A1(add_subt_module_intDY[10]), .B0(
add_subt_module_intDY[11]), .B1(n3147), .C0(n2279), .Y(n1669) );
NAND4XLTS U2916 ( .A(n1672), .B(n1671), .C(n1670), .D(n1669), .Y(n1673) );
NOR4X1TS U2917 ( .A(n1676), .B(n1675), .C(n1673), .D(n1674), .Y(n1732) );
AOI22X1TS U2918 ( .A0(n3033), .A1(add_subt_module_intDY[26]), .B0(n3038),
.B1(add_subt_module_intDY[25]), .Y(n1677) );
AOI22X1TS U2919 ( .A0(n2980), .A1(add_subt_module_intDY[24]), .B0(n2982),
.B1(add_subt_module_intDY[22]), .Y(n1678) );
OAI221XLTS U2920 ( .A0(n2980), .A1(add_subt_module_intDY[24]), .B0(n2982),
.B1(add_subt_module_intDY[22]), .C0(n1678), .Y(n1683) );
AOI22X1TS U2921 ( .A0(n3036), .A1(add_subt_module_intDY[30]), .B0(n3012),
.B1(add_subt_module_intDY[29]), .Y(n1679) );
AOI22X1TS U2922 ( .A0(n3035), .A1(add_subt_module_intDY[28]), .B0(n2970),
.B1(add_subt_module_intDY[27]), .Y(n1680) );
OAI221XLTS U2923 ( .A0(n3035), .A1(add_subt_module_intDY[28]), .B0(n2970),
.B1(add_subt_module_intDY[27]), .C0(n1680), .Y(n1681) );
NOR4X1TS U2924 ( .A(n1684), .B(n1683), .C(n1682), .D(n1681), .Y(n1731) );
AOI22X1TS U2925 ( .A0(n3032), .A1(add_subt_module_intDY[17]), .B0(n3041),
.B1(add_subt_module_intDY[16]), .Y(n1685) );
AOI22X1TS U2926 ( .A0(n2978), .A1(add_subt_module_intDY[15]), .B0(n3040),
.B1(add_subt_module_intDY[14]), .Y(n1686) );
OAI221XLTS U2927 ( .A0(n2978), .A1(add_subt_module_intDY[15]), .B0(n3040),
.B1(add_subt_module_intDY[14]), .C0(n1686), .Y(n1691) );
AOI22X1TS U2928 ( .A0(n3034), .A1(add_subt_module_intDY[21]), .B0(n3042),
.B1(add_subt_module_intDY[20]), .Y(n1687) );
AOI22X1TS U2929 ( .A0(n2979), .A1(add_subt_module_intDY[19]), .B0(n3037),
.B1(add_subt_module_intDY[18]), .Y(n1688) );
OAI221XLTS U2930 ( .A0(n2979), .A1(add_subt_module_intDY[19]), .B0(n3037),
.B1(add_subt_module_intDY[18]), .C0(n1688), .Y(n1689) );
NOR4X1TS U2931 ( .A(n1692), .B(n1691), .C(n1690), .D(n1689), .Y(n1730) );
OAI22X1TS U2932 ( .A0(n3030), .A1(add_subt_module_intDY[41]), .B0(n2975),
.B1(add_subt_module_intDY[42]), .Y(n1693) );
AOI221X1TS U2933 ( .A0(n3030), .A1(add_subt_module_intDY[41]), .B0(
add_subt_module_intDY[42]), .B1(n2975), .C0(n1693), .Y(n1700) );
OAI22X1TS U2934 ( .A0(n2977), .A1(add_subt_module_intDY[39]), .B0(n2952),
.B1(add_subt_module_intDY[40]), .Y(n1694) );
AOI221X1TS U2935 ( .A0(n2977), .A1(add_subt_module_intDY[39]), .B0(
add_subt_module_intDY[40]), .B1(n2952), .C0(n1694), .Y(n1699) );
OAI22X1TS U2936 ( .A0(n3024), .A1(add_subt_module_intDY[45]), .B0(n3019),
.B1(add_subt_module_intDY[46]), .Y(n1695) );
AOI221X1TS U2937 ( .A0(n3024), .A1(add_subt_module_intDY[45]), .B0(
add_subt_module_intDY[46]), .B1(n3019), .C0(n1695), .Y(n1698) );
OAI22X1TS U2938 ( .A0(n3023), .A1(add_subt_module_intDY[43]), .B0(n3005),
.B1(add_subt_module_intDY[44]), .Y(n1696) );
AOI221X1TS U2939 ( .A0(n3023), .A1(add_subt_module_intDY[43]), .B0(
add_subt_module_intDY[44]), .B1(n3005), .C0(n1696), .Y(n1697) );
NAND4XLTS U2940 ( .A(n1700), .B(n1699), .C(n1698), .D(n1697), .Y(n1728) );
OAI22X1TS U2941 ( .A0(n3021), .A1(add_subt_module_intDY[33]), .B0(n2961),
.B1(add_subt_module_intDY[34]), .Y(n1701) );
AOI221X1TS U2942 ( .A0(n3021), .A1(add_subt_module_intDY[33]), .B0(
add_subt_module_intDY[34]), .B1(n2961), .C0(n1701), .Y(n1708) );
OAI22X1TS U2943 ( .A0(n2976), .A1(add_subt_module_intDY[31]), .B0(n2960),
.B1(add_subt_module_intDY[32]), .Y(n1702) );
AOI221X1TS U2944 ( .A0(n2976), .A1(add_subt_module_intDY[31]), .B0(
add_subt_module_intDY[32]), .B1(n2960), .C0(n1702), .Y(n1707) );
OAI22X1TS U2945 ( .A0(n3010), .A1(add_subt_module_intDY[37]), .B0(n2962),
.B1(add_subt_module_intDY[38]), .Y(n1703) );
AOI221X1TS U2946 ( .A0(n3010), .A1(add_subt_module_intDY[37]), .B0(
add_subt_module_intDY[38]), .B1(n2962), .C0(n1703), .Y(n1706) );
OAI22X1TS U2947 ( .A0(n3022), .A1(add_subt_module_intDY[35]), .B0(n3016),
.B1(add_subt_module_intDY[36]), .Y(n1704) );
AOI221X1TS U2948 ( .A0(n3022), .A1(add_subt_module_intDY[35]), .B0(
add_subt_module_intDY[36]), .B1(n3016), .C0(n1704), .Y(n1705) );
NAND4XLTS U2949 ( .A(n1708), .B(n1707), .C(n1706), .D(n1705), .Y(n1727) );
OAI22X1TS U2950 ( .A0(n3028), .A1(add_subt_module_intDY[57]), .B0(n3148),
.B1(add_subt_module_intDY[58]), .Y(n1709) );
AOI221X1TS U2951 ( .A0(n3028), .A1(add_subt_module_intDY[57]), .B0(
add_subt_module_intDY[58]), .B1(n3148), .C0(n1709), .Y(n1716) );
OAI22X1TS U2952 ( .A0(n3027), .A1(add_subt_module_intDY[55]), .B0(n2964),
.B1(add_subt_module_intDY[56]), .Y(n1710) );
AOI221X1TS U2953 ( .A0(n3027), .A1(add_subt_module_intDY[55]), .B0(
add_subt_module_intDY[56]), .B1(n2964), .C0(n1710), .Y(n1715) );
OAI22X1TS U2954 ( .A0(n3011), .A1(add_subt_module_intDX[23]), .B0(n2965),
.B1(add_subt_module_intDY[61]), .Y(n1711) );
AOI221X1TS U2955 ( .A0(n3011), .A1(add_subt_module_intDX[23]), .B0(
add_subt_module_intDY[61]), .B1(n2965), .C0(n1711), .Y(n1714) );
OAI22X1TS U2956 ( .A0(n2973), .A1(add_subt_module_intDY[59]), .B0(n3018),
.B1(add_subt_module_intDY[60]), .Y(n1712) );
AOI221X1TS U2957 ( .A0(n2973), .A1(add_subt_module_intDY[59]), .B0(
add_subt_module_intDY[60]), .B1(n3018), .C0(n1712), .Y(n1713) );
NAND4XLTS U2958 ( .A(n1716), .B(n1715), .C(n1714), .D(n1713), .Y(n1726) );
OAI22X1TS U2959 ( .A0(n3025), .A1(add_subt_module_intDY[49]), .B0(n3017),
.B1(add_subt_module_intDY[50]), .Y(n1717) );
AOI221X1TS U2960 ( .A0(n3025), .A1(add_subt_module_intDY[49]), .B0(
add_subt_module_intDY[50]), .B1(n3017), .C0(n1717), .Y(n1724) );
OAI22X1TS U2961 ( .A0(n2968), .A1(add_subt_module_intDY[47]), .B0(n3006),
.B1(add_subt_module_intDY[48]), .Y(n1718) );
AOI221X1TS U2962 ( .A0(n2968), .A1(add_subt_module_intDY[47]), .B0(
add_subt_module_intDY[48]), .B1(n3006), .C0(n1718), .Y(n1723) );
OAI22X1TS U2963 ( .A0(n3026), .A1(add_subt_module_intDY[53]), .B0(n2963),
.B1(add_subt_module_intDY[54]), .Y(n1719) );
AOI221X1TS U2964 ( .A0(n3026), .A1(add_subt_module_intDY[53]), .B0(
add_subt_module_intDY[54]), .B1(n2963), .C0(n1719), .Y(n1722) );
OAI22X1TS U2965 ( .A0(n2974), .A1(add_subt_module_intDY[51]), .B0(n3007),
.B1(add_subt_module_intDY[52]), .Y(n1720) );
AOI221X1TS U2966 ( .A0(n2974), .A1(add_subt_module_intDY[51]), .B0(
add_subt_module_intDY[52]), .B1(n3007), .C0(n1720), .Y(n1721) );
NAND4XLTS U2967 ( .A(n1724), .B(n1723), .C(n1722), .D(n1721), .Y(n1725) );
NOR4X1TS U2968 ( .A(n1728), .B(n1727), .C(n1726), .D(n1725), .Y(n1729) );
NAND4XLTS U2969 ( .A(n1732), .B(n1731), .C(n1730), .D(n1729), .Y(n2392) );
NOR2X1TS U2970 ( .A(n1733), .B(n2392), .Y(n2063) );
AOI21X1TS U2971 ( .A0(n2063), .A1(n3245), .B0(
add_subt_module_FSM_Final_Result_load), .Y(n2598) );
INVX2TS U2972 ( .A(n2927), .Y(n1734) );
AOI211XLTS U2973 ( .A0(add_subt_module_FS_Module_state_reg[3]), .A1(n1960),
.B0(n1734), .C0(add_subt_module_FSM_exp_operation_load_diff), .Y(n1735) );
OAI211XLTS U2974 ( .A0(add_subt_module_FSM_selector_C), .A1(n2926), .B0(
n2598), .C0(n1735), .Y(add_subt_module_FS_Module_state_next[2]) );
CLKAND2X2TS U2975 ( .A(n1736), .B(n3014), .Y(n1741) );
INVX2TS U2976 ( .A(n1741), .Y(n1737) );
NOR2X1TS U2977 ( .A(add_subt_module_LZA_output[3]), .B(n1737), .Y(n2082) );
INVX2TS U2978 ( .A(n2082), .Y(n2069) );
NOR2XLTS U2979 ( .A(add_subt_module_exp_oper_result[5]), .B(
add_subt_module_exp_oper_result[3]), .Y(n1738) );
CLKAND2X2TS U2980 ( .A(n1297), .B(n1738), .Y(n2084) );
NAND2X1TS U2981 ( .A(n3000), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(
n1740) );
NAND2X1TS U2982 ( .A(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]), .B(
add_subt_module_exp_oper_result[4]), .Y(n1739) );
NAND2X1TS U2983 ( .A(n1740), .B(n1739), .Y(n1745) );
AOI22X1TS U2984 ( .A0(add_subt_module_FSM_selector_B[1]), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]), .B0(
n2084), .B1(n1745), .Y(n1743) );
NAND2X1TS U2985 ( .A(add_subt_module_LZA_output[3]), .B(n1741), .Y(n2066) );
NOR2X1TS U2986 ( .A(add_subt_module_exp_oper_result[5]), .B(
add_subt_module_FSM_selector_B[0]), .Y(n1750) );
NAND2X1TS U2987 ( .A(n1750), .B(n3000), .Y(n2068) );
OR2X1TS U2988 ( .A(n2998), .B(add_subt_module_FSM_selector_B[1]), .Y(n1748)
);
NAND2X1TS U2989 ( .A(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]), .B(
n2089), .Y(n1742) );
OAI211X1TS U2990 ( .A0(n2083), .A1(n2069), .B0(n1743), .C0(n1742), .Y(n2080)
);
NAND2X1TS U2991 ( .A(n1959), .B(add_subt_module_FSM_selector_C), .Y(n2081)
);
INVX2TS U2992 ( .A(n2081), .Y(n1757) );
NAND2X1TS U2993 ( .A(n1757), .B(n1961), .Y(n2092) );
INVX2TS U2994 ( .A(n2092), .Y(n1759) );
AOI22X1TS U2995 ( .A0(add_subt_module_LZA_output[4]), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[77]), .B1(
n3013), .Y(n1744) );
AOI22X1TS U2996 ( .A0(add_subt_module_LZA_output[3]), .A1(n2083), .B0(n1744),
.B1(n3055), .Y(n1754) );
INVX2TS U2997 ( .A(n1745), .Y(n2085) );
AOI21X1TS U2998 ( .A0(n2971), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(
n3000), .Y(n1747) );
OAI21XLTS U2999 ( .A0(add_subt_module_exp_oper_result[4]), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[77]), .B0(
n2998), .Y(n1746) );
OAI22X1TS U3000 ( .A0(n2085), .A1(n1748), .B0(n1747), .B1(n1746), .Y(n1749)
);
NAND2X1TS U3001 ( .A(n1750), .B(n1749), .Y(n1751) );
OAI21X1TS U3002 ( .A0(n3077), .A1(n2971), .B0(n1751), .Y(n1753) );
AOI31X1TS U3003 ( .A0(n1736), .A1(n1754), .A2(n3014), .B0(n1753), .Y(n2093)
);
NAND2X1TS U3004 ( .A(n1736), .B(add_subt_module_LZA_output[5]), .Y(n2468) );
NAND2X1TS U3005 ( .A(n1297), .B(add_subt_module_exp_oper_result[5]), .Y(
n1752) );
AOI211X1TS U3006 ( .A0(n1736), .A1(n1754), .B0(n2190), .C0(n1753), .Y(n1756)
);
NOR2XLTS U3007 ( .A(n1899), .B(add_subt_module_FSM_selector_C), .Y(n1755) );
NOR2X1TS U3008 ( .A(n1755), .B(n1961), .Y(n2087) );
INVX2TS U3009 ( .A(n2087), .Y(n2076) );
OAI22X1TS U3010 ( .A0(n2093), .A1(n1757), .B0(n1756), .B1(n2076), .Y(n1758)
);
AO21XLTS U3011 ( .A0(n2080), .A1(n1759), .B0(n1758), .Y(n3276) );
NAND2X1TS U3012 ( .A(n2871), .B(n2957), .Y(data_out_LUT[45]) );
NAND2X1TS U3013 ( .A(n2587), .B(n2078), .Y(n1760) );
NAND3XLTS U3014 ( .A(n3146), .B(cont_iter_out[3]), .C(n2876), .Y(n2853) );
NAND4XLTS U3015 ( .A(n2875), .B(n1760), .C(n2853), .D(data_out_LUT[45]), .Y(
data_out_LUT[27]) );
NAND2X2TS U3016 ( .A(n2854), .B(n2876), .Y(n2874) );
NAND2X1TS U3017 ( .A(data_out_LUT[38]), .B(n2874), .Y(n1762) );
NOR2X2TS U3018 ( .A(n1761), .B(n1762), .Y(n2864) );
OAI21XLTS U3019 ( .A0(n2586), .A1(n2585), .B0(n2864), .Y(data_out_LUT[25])
);
NOR2X1TS U3020 ( .A(cordic_FSM_state_reg[3]), .B(n2591), .Y(load_cont_iter)
);
NAND2X1TS U3021 ( .A(n2585), .B(n2957), .Y(data_out_LUT[20]) );
NAND2X1TS U3022 ( .A(n2957), .B(n2859), .Y(data_out_LUT[22]) );
NAND2X1TS U3023 ( .A(n2855), .B(n2957), .Y(data_out_LUT[49]) );
INVX2TS U3024 ( .A(n1762), .Y(n2863) );
CLKAND2X2TS U3025 ( .A(data_out_LUT[49]), .B(n2863), .Y(n2879) );
NAND2X1TS U3026 ( .A(n2879), .B(n2861), .Y(data_out_LUT[33]) );
NAND2X1TS U3027 ( .A(n1736), .B(add_subt_module_LZA_output[2]), .Y(n1905) );
NAND2X1TS U3028 ( .A(n1297), .B(add_subt_module_exp_oper_result[2]), .Y(
n1763) );
CLKAND2X2TS U3029 ( .A(n1905), .B(n1763), .Y(n1774) );
INVX4TS U3030 ( .A(n2637), .Y(n2634) );
BUFX4TS U3031 ( .A(n3015), .Y(n2758) );
NOR2X1TS U3032 ( .A(n2758), .B(add_subt_module_FS_Module_state_reg[3]), .Y(
n1801) );
INVX2TS U3033 ( .A(n1766), .Y(n2779) );
BUFX4TS U3034 ( .A(n2779), .Y(n2769) );
BUFX4TS U3035 ( .A(n3015), .Y(n2692) );
AOI22X1TS U3036 ( .A0(n2111), .A1(add_subt_module_Add_Subt_result[21]), .B0(
add_subt_module_DmP[31]), .B1(n2692), .Y(n1767) );
NAND2X1TS U3037 ( .A(n1736), .B(add_subt_module_LZA_output[0]), .Y(n1769) );
NAND2X1TS U3038 ( .A(n2993), .B(add_subt_module_FSM_selector_B[1]), .Y(n1768) );
NAND2X1TS U3039 ( .A(n1769), .B(n1768), .Y(n2474) );
NAND2X1TS U3040 ( .A(n1736), .B(add_subt_module_LZA_output[1]), .Y(n1903) );
NAND2X1TS U3041 ( .A(n1297), .B(add_subt_module_exp_oper_result[1]), .Y(
n1771) );
CLKAND2X2TS U3042 ( .A(n1903), .B(n1771), .Y(n2651) );
INVX2TS U3043 ( .A(n2651), .Y(n2164) );
OR2X2TS U3044 ( .A(n2149), .B(n2164), .Y(n2142) );
AOI22X1TS U3045 ( .A0(n2111), .A1(add_subt_module_Add_Subt_result[22]), .B0(
add_subt_module_DmP[30]), .B1(n2692), .Y(n1772) );
INVX2TS U3046 ( .A(n2149), .Y(n2147) );
OR2X2TS U3047 ( .A(n2147), .B(n2164), .Y(n2123) );
AOI22X1TS U3048 ( .A0(n2111), .A1(add_subt_module_Add_Subt_result[19]), .B0(
add_subt_module_DmP[33]), .B1(n2692), .Y(n1773) );
AOI22X1TS U3049 ( .A0(n2111), .A1(add_subt_module_Add_Subt_result[25]), .B0(
add_subt_module_DmP[27]), .B1(n2692), .Y(n1775) );
OAI2BB1X2TS U3050 ( .A0N(add_subt_module_Add_Subt_result[29]), .A1N(n2769),
.B0(n1775), .Y(n2636) );
INVX4TS U3051 ( .A(n2142), .Y(n2130) );
AOI22X1TS U3052 ( .A0(n2111), .A1(add_subt_module_Add_Subt_result[26]), .B0(
add_subt_module_DmP[26]), .B1(n2692), .Y(n1776) );
AOI22X1TS U3053 ( .A0(n2111), .A1(add_subt_module_Add_Subt_result[23]), .B0(
add_subt_module_DmP[29]), .B1(n2692), .Y(n1777) );
INVX4TS U3054 ( .A(n1300), .Y(n2652) );
NAND2X1TS U3055 ( .A(n2149), .B(n2164), .Y(n1811) );
NOR2XLTS U3056 ( .A(n2652), .B(n1811), .Y(n1793) );
AOI22X1TS U3057 ( .A0(n2111), .A1(add_subt_module_Add_Subt_result[20]), .B0(
add_subt_module_DmP[32]), .B1(n2692), .Y(n1778) );
NOR2X1TS U3058 ( .A(n1300), .B(n1811), .Y(n2624) );
BUFX4TS U3059 ( .A(n2624), .Y(n2788) );
AOI22X1TS U3060 ( .A0(n2111), .A1(add_subt_module_Add_Subt_result[24]), .B0(
add_subt_module_DmP[28]), .B1(n2692), .Y(n1779) );
AOI22X1TS U3061 ( .A0(n1298), .A1(n2159), .B0(n2788), .B1(n2158), .Y(n1780)
);
OAI221XLTS U3062 ( .A0(n1774), .A1(n1786), .B0(n2637), .B1(n2115), .C0(n1780), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[28]) );
BUFX4TS U3063 ( .A(n3015), .Y(n2934) );
AOI22X1TS U3064 ( .A0(n2111), .A1(add_subt_module_Add_Subt_result[17]), .B0(
add_subt_module_DmP[35]), .B1(n2934), .Y(n1781) );
OAI21X2TS U3065 ( .A0(n3063), .A1(n1766), .B0(n1781), .Y(n1831) );
AOI22X1TS U3066 ( .A0(n2111), .A1(add_subt_module_Add_Subt_result[18]), .B0(
add_subt_module_DmP[34]), .B1(n2692), .Y(n1782) );
AOI22X1TS U3067 ( .A0(n2111), .A1(add_subt_module_Add_Subt_result[15]), .B0(
add_subt_module_DmP[37]), .B1(n2934), .Y(n1783) );
OAI2BB1X1TS U3068 ( .A0N(add_subt_module_Add_Subt_result[39]), .A1N(n2752),
.B0(n1783), .Y(n1818) );
AOI22X1TS U3069 ( .A0(n2111), .A1(add_subt_module_Add_Subt_result[16]), .B0(
add_subt_module_DmP[36]), .B1(n2934), .Y(n1784) );
OAI2BB1X2TS U3070 ( .A0N(add_subt_module_Add_Subt_result[38]), .A1N(n2752),
.B0(n1784), .Y(n2623) );
AOI22X1TS U3071 ( .A0(n1298), .A1(n2623), .B0(n2788), .B1(n2159), .Y(n1785)
);
OAI221XLTS U3072 ( .A0(n1774), .A1(n2627), .B0(n2637), .B1(n1786), .C0(n1785), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[32]) );
BUFX3TS U3073 ( .A(n2119), .Y(n2547) );
AOI22X1TS U3074 ( .A0(n2778), .A1(add_subt_module_Add_Subt_result[9]), .B0(
add_subt_module_DmP[43]), .B1(n2934), .Y(n1787) );
AOI22X1TS U3075 ( .A0(n2582), .A1(add_subt_module_Add_Subt_result[10]), .B0(
add_subt_module_DmP[42]), .B1(n2934), .Y(n1788) );
INVX4TS U3076 ( .A(n2123), .Y(n2129) );
AOI22X1TS U3077 ( .A0(n2778), .A1(add_subt_module_Add_Subt_result[7]), .B0(
add_subt_module_DmP[45]), .B1(n2934), .Y(n1789) );
AOI222X1TS U3078 ( .A0(n1847), .A1(n2130), .B0(n1842), .B1(n2129), .C0(n1839), .C1(n1813), .Y(n2621) );
AOI22X1TS U3079 ( .A0(n2111), .A1(add_subt_module_Add_Subt_result[13]), .B0(
add_subt_module_DmP[39]), .B1(n2934), .Y(n1790) );
AOI22X1TS U3080 ( .A0(n2111), .A1(add_subt_module_Add_Subt_result[14]), .B0(
add_subt_module_DmP[38]), .B1(n2934), .Y(n1791) );
AOI22X1TS U3081 ( .A0(n2582), .A1(add_subt_module_Add_Subt_result[11]), .B0(
add_subt_module_DmP[41]), .B1(n2934), .Y(n1792) );
AOI22X1TS U3082 ( .A0(n2778), .A1(n1442), .B0(add_subt_module_DmP[44]), .B1(
n2934), .Y(n1794) );
OAI2BB1X2TS U3083 ( .A0N(add_subt_module_Add_Subt_result[46]), .A1N(n2752),
.B0(n1794), .Y(n2618) );
AOI22X1TS U3084 ( .A0(n2111), .A1(add_subt_module_Add_Subt_result[12]), .B0(
add_subt_module_DmP[40]), .B1(n2934), .Y(n1795) );
OAI2BB1X2TS U3085 ( .A0N(add_subt_module_Add_Subt_result[42]), .A1N(n2752),
.B0(n1795), .Y(n2625) );
AOI22X1TS U3086 ( .A0(n1298), .A1(n2618), .B0(n2788), .B1(n2625), .Y(n1796)
);
OAI221XLTS U3087 ( .A0(n2634), .A1(n2621), .B0(n2637), .B1(n2628), .C0(n1796), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]) );
AOI22X1TS U3088 ( .A0(n2778), .A1(add_subt_module_Add_Subt_result[1]), .B0(
add_subt_module_DmP[51]), .B1(n2934), .Y(n1797) );
OAI2BB1X2TS U3089 ( .A0N(add_subt_module_Add_Subt_result[53]), .A1N(n2779),
.B0(n1797), .Y(n2141) );
NAND3X1TS U3090 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(n1959), .C(
n1798), .Y(n2932) );
NAND2X1TS U3091 ( .A(n2932), .B(n2927), .Y(n1799) );
AOI21X1TS U3092 ( .A0(n1801), .A1(n1800), .B0(n1799), .Y(n1802) );
NOR2X2TS U3093 ( .A(n1802), .B(n1961), .Y(n2617) );
AOI22X1TS U3094 ( .A0(n2582), .A1(add_subt_module_Add_Subt_result[2]), .B0(
add_subt_module_DmP[50]), .B1(n2934), .Y(n1803) );
AOI22X1TS U3095 ( .A0(n2582), .A1(add_subt_module_Add_Subt_result[5]), .B0(
add_subt_module_DmP[47]), .B1(n2934), .Y(n1804) );
OAI21X2TS U3096 ( .A0(n2985), .A1(n1766), .B0(n1804), .Y(n1846) );
AOI22X1TS U3097 ( .A0(n2582), .A1(add_subt_module_Add_Subt_result[6]), .B0(
add_subt_module_DmP[46]), .B1(n2934), .Y(n1805) );
AOI22X1TS U3098 ( .A0(n2582), .A1(add_subt_module_Add_Subt_result[3]), .B0(
add_subt_module_DmP[49]), .B1(n2934), .Y(n1806) );
AOI222X1TS U3099 ( .A0(n1846), .A1(n2130), .B0(n1841), .B1(n2129), .C0(n1838), .C1(n1813), .Y(n2622) );
BUFX4TS U3100 ( .A(n1298), .Y(n2768) );
NOR2XLTS U3101 ( .A(n1766), .B(add_subt_module_Add_Subt_result[54]), .Y(
n1808) );
NOR2XLTS U3102 ( .A(n2547), .B(n1405), .Y(n1807) );
AOI22X1TS U3103 ( .A0(n2778), .A1(n1443), .B0(add_subt_module_DmP[48]), .B1(
n2934), .Y(n1809) );
OAI2BB1X2TS U3104 ( .A0N(add_subt_module_Add_Subt_result[50]), .A1N(n2752),
.B0(n1809), .Y(n2619) );
AOI22X1TS U3105 ( .A0(n2768), .A1(n1435), .B0(n2788), .B1(n2619), .Y(n1810)
);
OAI221XLTS U3106 ( .A0(n2634), .A1(n2105), .B0(n2637), .B1(n2622), .C0(n1810), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]) );
INVX2TS U3107 ( .A(n1813), .Y(n1814) );
BUFX4TS U3108 ( .A(n1819), .Y(n2746) );
NOR2XLTS U3109 ( .A(n1300), .B(n1814), .Y(n1815) );
AOI22X1TS U3110 ( .A0(n2746), .A1(n1847), .B0(n2772), .B1(n1832), .Y(n1816)
);
OAI221XLTS U3111 ( .A0(n2634), .A1(n1849), .B0(n2637), .B1(n1835), .C0(n1816), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]) );
AOI22X1TS U3112 ( .A0(n2746), .A1(n2625), .B0(n2791), .B1(n2623), .Y(n1817)
);
OAI221XLTS U3113 ( .A0(n2634), .A1(n1830), .B0(n2637), .B1(n1823), .C0(n1817), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[35]) );
BUFX4TS U3114 ( .A(n1819), .Y(n2793) );
AOI22X1TS U3115 ( .A0(n2793), .A1(n1842), .B0(n2791), .B1(n2630), .Y(n1820)
);
OAI221XLTS U3116 ( .A0(n2634), .A1(n1844), .B0(n2637), .B1(n2633), .C0(n1820), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]) );
AOI22X1TS U3117 ( .A0(n2793), .A1(n2629), .B0(n2791), .B1(n2154), .Y(n1821)
);
OAI221XLTS U3118 ( .A0(n2634), .A1(n2632), .B0(n2637), .B1(n2157), .C0(n1821), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[29]) );
AOI222X1TS U3119 ( .A0(n2154), .A1(n1825), .B0(n1826), .B1(n2124), .C0(n2165), .C1(n1812), .Y(n2163) );
AOI22X1TS U3120 ( .A0(n2793), .A1(n2623), .B0(n2772), .B1(n2159), .Y(n1822)
);
OAI221XLTS U3121 ( .A0(n2652), .A1(n1823), .B0(n2637), .B1(n2163), .C0(n1822), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[31]) );
AOI22X1TS U3122 ( .A0(n2793), .A1(n1831), .B0(n2772), .B1(n2165), .Y(n1827)
);
OAI221XLTS U3123 ( .A0(n1774), .A1(n1834), .B0(n2637), .B1(n2168), .C0(n1827), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[30]) );
AOI22X1TS U3124 ( .A0(n2746), .A1(n2618), .B0(n2772), .B1(n2625), .Y(n1829)
);
OAI221XLTS U3125 ( .A0(n1774), .A1(n1852), .B0(n2637), .B1(n1830), .C0(n1829), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]) );
AOI22X1TS U3126 ( .A0(n2793), .A1(n1832), .B0(n2791), .B1(n1831), .Y(n1833)
);
OAI221XLTS U3127 ( .A0(n2634), .A1(n1835), .B0(n2637), .B1(n1834), .C0(n1833), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[34]) );
AOI222X1TS U3128 ( .A0(n1841), .A1(n2130), .B0(n1839), .B1(n2129), .C0(n1846), .C1(n1812), .Y(n1853) );
AOI22X1TS U3129 ( .A0(n1435), .A1(n2746), .B0(n2791), .B1(n2619), .Y(n1836)
);
OAI221XLTS U3130 ( .A0(n2634), .A1(n2139), .B0(n2637), .B1(n1853), .C0(n1836), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]) );
AOI222X1TS U3131 ( .A0(n1839), .A1(n2130), .B0(n2618), .B1(n2129), .C0(n1841), .C1(n1812), .Y(n1850) );
BUFX4TS U3132 ( .A(n2732), .Y(n2772) );
AOI22X1TS U3133 ( .A0(n2732), .A1(n1846), .B0(n2746), .B1(n2141), .Y(n1837)
);
OAI221XLTS U3134 ( .A0(n2634), .A1(n2127), .B0(n1300), .B1(n1850), .C0(n1837), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]) );
AOI222X1TS U3135 ( .A0(n2619), .A1(n2130), .B0(n1846), .B1(n2129), .C0(n1838), .C1(n1812), .Y(n2146) );
AOI222X1TS U3136 ( .A0(n2618), .A1(n2130), .B0(n1847), .B1(n2129), .C0(n1839), .C1(n1812), .Y(n1845) );
AOI22X1TS U3137 ( .A0(n2772), .A1(n1841), .B0(n2746), .B1(n2143), .Y(n1840)
);
OAI221XLTS U3138 ( .A0(n2634), .A1(n2146), .B0(n1300), .B1(n1845), .C0(n1840), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]) );
AOI22X1TS U3139 ( .A0(n2791), .A1(n1842), .B0(n2746), .B1(n1841), .Y(n1843)
);
OAI221XLTS U3140 ( .A0(n2634), .A1(n1845), .B0(n1300), .B1(n1844), .C0(n1843), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]) );
AOI22X1TS U3141 ( .A0(n2772), .A1(n1847), .B0(n2746), .B1(n1846), .Y(n1848)
);
OAI221XLTS U3142 ( .A0(n2634), .A1(n1850), .B0(n1300), .B1(n1849), .C0(n1848), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]) );
AOI22X1TS U3143 ( .A0(n2732), .A1(n2618), .B0(n2746), .B1(n2619), .Y(n1851)
);
OAI221XLTS U3144 ( .A0(n2634), .A1(n1853), .B0(n1300), .B1(n1852), .C0(n1851), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]) );
NAND2X1TS U3145 ( .A(n1736), .B(add_subt_module_LZA_output[3]), .Y(n2472) );
NAND2X1TS U3146 ( .A(n1297), .B(add_subt_module_exp_oper_result[3]), .Y(
n1855) );
CLKAND2X2TS U3147 ( .A(n2472), .B(n1855), .Y(n1857) );
NAND2X1TS U3148 ( .A(n1736), .B(add_subt_module_LZA_output[4]), .Y(n2470) );
NAND2X1TS U3149 ( .A(n1297), .B(add_subt_module_exp_oper_result[4]), .Y(
n2072) );
CLKAND2X2TS U3150 ( .A(n2470), .B(n2072), .Y(n1862) );
INVX2TS U3151 ( .A(n2617), .Y(n2107) );
INVX2TS U3152 ( .A(n1857), .Y(n1863) );
NAND2X2TS U3153 ( .A(n2196), .B(n1889), .Y(n2524) );
NOR2X1TS U3154 ( .A(n2190), .B(n2221), .Y(n2213) );
BUFX4TS U3155 ( .A(n2208), .Y(n2522) );
AOI22X1TS U3156 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[86]), .A1(
n1433), .B0(n2522), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[71]), .Y(
n1860) );
INVX2TS U3157 ( .A(n2089), .Y(n2194) );
AOI22X1TS U3158 ( .A0(n1441), .A1(n2518), .B0(n2527), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[78]), .Y(
n1859) );
OAI211X1TS U3159 ( .A0(n2196), .A1(n2569), .B0(n1860), .C0(n1859), .Y(n2548)
);
NOR2XLTS U3160 ( .A(n2778), .B(n2190), .Y(n1861) );
BUFX4TS U3161 ( .A(n1861), .Y(n2229) );
NAND2X2TS U3162 ( .A(n1863), .B(n1862), .Y(n1888) );
AOI22X1TS U3163 ( .A0(n1889), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]), .B0(
n2121), .B1(n1437), .Y(n1864) );
NOR2X4TS U3164 ( .A(n1862), .B(n2107), .Y(n2223) );
NAND2X2TS U3165 ( .A(n2223), .B(n1863), .Y(n1890) );
AOI22X1TS U3166 ( .A0(n2582), .A1(n2548), .B0(n2229), .B1(n2550), .Y(n1865)
);
AND2X2TS U3167 ( .A(n2617), .B(n2190), .Y(n2526) );
NAND2X1TS U3168 ( .A(n1865), .B(n2509), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[38]) );
AOI22X1TS U3169 ( .A0(n2522), .A1(n1406), .B0(n1434), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]), .Y(
n1867) );
BUFX3TS U3170 ( .A(n1858), .Y(n2521) );
AOI22X1TS U3171 ( .A0(n2527), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]), .B0(
n2521), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[91]), .Y(
n1866) );
OAI211X1TS U3172 ( .A0(n2196), .A1(n2575), .B0(n1867), .C0(n1866), .Y(n2542)
);
AOI22X1TS U3173 ( .A0(n1889), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[99]), .B0(
n2121), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]), .Y(
n1868) );
AOI22X1TS U3174 ( .A0(n2778), .A1(n2542), .B0(n2229), .B1(n2541), .Y(n1869)
);
NAND2X1TS U3175 ( .A(n1869), .B(n2509), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[35]) );
AOI22X1TS U3176 ( .A0(n2522), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[72]), .B0(
n1434), .B1(n1439), .Y(n1871) );
AOI22X1TS U3177 ( .A0(n2527), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]), .B0(
n2521), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[89]), .Y(
n1870) );
OAI211X1TS U3178 ( .A0(n2196), .A1(n2571), .B0(n1871), .C0(n1870), .Y(n2546)
);
AOI22X1TS U3179 ( .A0(n1889), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[101]), .B0(
n2121), .B1(n1438), .Y(n1872) );
AOI22X1TS U3180 ( .A0(n2582), .A1(n2546), .B0(n1446), .B1(n2545), .Y(n1873)
);
NAND2X1TS U3181 ( .A(n1873), .B(n2509), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[37]) );
AOI22X1TS U3182 ( .A0(n2522), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[73]), .B0(
n1434), .B1(n1436), .Y(n1875) );
AOI22X1TS U3183 ( .A0(n1299), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]), .B0(
n2521), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[90]), .Y(
n1874) );
OAI211X1TS U3184 ( .A0(n2196), .A1(n2573), .B0(n1875), .C0(n1874), .Y(n2544)
);
AOI22X1TS U3185 ( .A0(n1889), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]), .B0(
n2121), .B1(n1440), .Y(n1876) );
AOI22X1TS U3186 ( .A0(n2778), .A1(n2544), .B0(n1446), .B1(n2543), .Y(n1877)
);
NAND2X1TS U3187 ( .A(n1877), .B(n2509), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[36]) );
AOI22X1TS U3188 ( .A0(n2522), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(
n1434), .B1(n1440), .Y(n1879) );
AOI22X1TS U3189 ( .A0(n2527), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]), .B0(
n2518), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[92]), .Y(
n1878) );
OAI211X1TS U3190 ( .A0(n2196), .A1(n2577), .B0(n1879), .C0(n1878), .Y(n2540)
);
AOI22X1TS U3191 ( .A0(n1889), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[98]), .B0(
n2121), .B1(n1436), .Y(n1880) );
AOI22X1TS U3192 ( .A0(n2582), .A1(n2540), .B0(n1446), .B1(n2539), .Y(n1881)
);
NAND2X1TS U3193 ( .A(n1881), .B(n2509), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[34]) );
AOI22X1TS U3194 ( .A0(n2208), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[75]), .B0(
n1434), .B1(n1438), .Y(n1883) );
AOI22X1TS U3195 ( .A0(n1299), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]), .B0(
n2518), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[93]), .Y(
n1882) );
OAI211X1TS U3196 ( .A0(n2196), .A1(n2579), .B0(n1883), .C0(n1882), .Y(n2538)
);
AOI22X1TS U3197 ( .A0(n1889), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[97]), .B0(
n2121), .B1(n1439), .Y(n1884) );
AOI22X1TS U3198 ( .A0(n2778), .A1(n2538), .B0(n1446), .B1(n2537), .Y(n1885)
);
NAND2X1TS U3199 ( .A(n1885), .B(n2509), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[33]) );
AOI22X1TS U3200 ( .A0(n2527), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(
n2518), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[94]), .Y(
n1887) );
AOI22X1TS U3201 ( .A0(n2522), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(
n1434), .B1(n1437), .Y(n1886) );
OAI211X1TS U3202 ( .A0(n2196), .A1(n2581), .B0(n1887), .C0(n1886), .Y(n2536)
);
INVX2TS U3203 ( .A(n1888), .Y(n2224) );
AOI22X1TS U3204 ( .A0(n2224), .A1(n1441), .B0(n1889), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[96]), .Y(
n1891) );
AOI22X1TS U3205 ( .A0(n2582), .A1(n2536), .B0(n1446), .B1(n2535), .Y(n1892)
);
NAND2X1TS U3206 ( .A(n1892), .B(n2509), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[32]) );
NAND4XLTS U3207 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[0]),
.C(cordic_FSM_state_reg[2]), .D(n2949), .Y(n2924) );
OAI211XLTS U3208 ( .A0(n1893), .A1(n2949), .B0(n1308), .C0(n2924), .Y(n1155)
);
NAND4X1TS U3209 ( .A(n2956), .B(n2995), .C(cordic_FSM_state_reg[3]), .D(
cordic_FSM_state_reg[0]), .Y(n2922) );
OR2X1TS U3210 ( .A(n2922), .B(n2094), .Y(n2101) );
NAND2X1TS U3211 ( .A(cont_var_out[1]), .B(n2987), .Y(n2232) );
NOR2X1TS U3212 ( .A(n2101), .B(n2232), .Y(n2240) );
NAND2X1TS U3213 ( .A(n2923), .B(n2956), .Y(n2064) );
AOI21X1TS U3214 ( .A0(cordic_FSM_state_reg[3]), .A1(n2064), .B0(
cordic_FSM_state_reg[0]), .Y(n1895) );
NOR4X1TS U3215 ( .A(n2240), .B(n1895), .C(n1894), .D(n1375), .Y(n1896) );
OAI211XLTS U3216 ( .A0(beg_fsm_cordic), .A1(n1897), .B0(n1896), .C0(n3269),
.Y(n1157) );
CLKAND2X2TS U3217 ( .A(n1328), .B(n1960), .Y(n1288) );
NOR3X1TS U3218 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(n2950), .C(
n3001), .Y(add_subt_module_FSM_Add_Subt_Sgf_load) );
INVX2TS U3219 ( .A(add_subt_module_FSM_Add_Subt_Sgf_load), .Y(n2596) );
OAI22X1TS U3220 ( .A0(add_subt_module_FSM_selector_C), .A1(n2926), .B0(n2596), .B1(n1899), .Y(n1900) );
NOR4X1TS U3221 ( .A(n3245), .B(add_subt_module_FSM_Final_Result_load), .C(
n1901), .D(n1900), .Y(n1902) );
NAND2X1TS U3222 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(n1994), .Y(
n2059) );
NAND3BXLTS U3223 ( .AN(n1288), .B(n1902), .C(n2059), .Y(
add_subt_module_FS_Module_state_next[1]) );
OAI2BB1X1TS U3224 ( .A0N(n1297), .A1N(add_subt_module_DmP[53]), .B0(n1903),
.Y(n1904) );
XOR2X1TS U3225 ( .A(n3145), .B(n1904), .Y(DP_OP_92J185_122_9081_n25) );
OAI2BB1X1TS U3226 ( .A0N(n1297), .A1N(add_subt_module_DmP[54]), .B0(n1905),
.Y(n1906) );
XOR2X1TS U3227 ( .A(n3145), .B(n1906), .Y(DP_OP_92J185_122_9081_n24) );
NOR3X1TS U3228 ( .A(n1928), .B(add_subt_module_Add_Subt_result[3]), .C(
add_subt_module_Add_Subt_result[2]), .Y(n2476) );
INVX2TS U3229 ( .A(n1909), .Y(n1920) );
INVX2TS U3230 ( .A(n2803), .Y(n1952) );
NAND2X1TS U3231 ( .A(n1952), .B(n1945), .Y(n1921) );
OAI31X1TS U3232 ( .A0(n1911), .A1(n1920), .A2(n1921), .B0(n1910), .Y(n1912)
);
AOI31XLTS U3233 ( .A0(n1923), .A1(n1913), .A2(
add_subt_module_Add_Subt_result[27]), .B0(n1912), .Y(n1917) );
NAND2X1TS U3234 ( .A(n1914), .B(add_subt_module_Add_Subt_result[23]), .Y(
n2492) );
INVX2TS U3235 ( .A(n2501), .Y(n1916) );
AOI211X1TS U3236 ( .A0(n2486), .A1(n3137), .B0(n1919), .C0(n1918), .Y(n1958)
);
AOI21X1TS U3237 ( .A0(add_subt_module_Add_Subt_result[34]), .A1(n3056), .B0(
n1920), .Y(n1922) );
OR2X1TS U3238 ( .A(n1922), .B(n1921), .Y(n1927) );
AND4X1TS U3239 ( .A(n1927), .B(n1926), .C(n2813), .D(n1925), .Y(n1934) );
AOI211X1TS U3240 ( .A0(n3137), .A1(n2990), .B0(n1928), .C0(
add_subt_module_Add_Subt_result[3]), .Y(n1933) );
NAND2X1TS U3241 ( .A(n3053), .B(add_subt_module_Add_Subt_result[25]), .Y(
n1929) );
NOR2X1TS U3242 ( .A(n2501), .B(n1929), .Y(n2491) );
INVX2TS U3243 ( .A(n1930), .Y(n1932) );
OAI31X1TS U3244 ( .A0(n1932), .A1(n2815), .A2(n2997), .B0(n1931), .Y(n2498)
);
NOR4BX1TS U3245 ( .AN(n1934), .B(n1933), .C(n2491), .D(n2498), .Y(n1935) );
NAND2X1TS U3246 ( .A(n1958), .B(n1935), .Y(
add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[4]) );
INVX2TS U3247 ( .A(n1936), .Y(n1937) );
OAI21XLTS U3248 ( .A0(n1443), .A1(add_subt_module_Add_Subt_result[3]), .B0(
n1937), .Y(n1944) );
INVX2TS U3249 ( .A(n2478), .Y(n1939) );
INVX2TS U3250 ( .A(n2479), .Y(n1940) );
AND4X1TS U3251 ( .A(n1944), .B(n2494), .C(n2818), .D(n1943), .Y(n2485) );
INVX2TS U3252 ( .A(n1945), .Y(n2804) );
NOR2X1TS U3253 ( .A(n1946), .B(n3051), .Y(n2490) );
AOI31XLTS U3254 ( .A0(add_subt_module_Add_Subt_result[48]), .A1(n3054), .A2(
n2985), .B0(n1947), .Y(n1950) );
AOI31XLTS U3255 ( .A0(n3057), .A1(add_subt_module_Add_Subt_result[44]), .A2(
n2984), .B0(add_subt_module_Add_Subt_result[47]), .Y(n1948) );
OAI22X1TS U3256 ( .A0(n1950), .A1(n1949), .B0(n1948), .B1(n2808), .Y(n1951)
);
AOI211XLTS U3257 ( .A0(n1952), .A1(n2804), .B0(n2490), .C0(n1951), .Y(n1953)
);
AOI31XLTS U3258 ( .A0(n2814), .A1(n1956), .A2(
add_subt_module_Add_Subt_result[16]), .B0(n1955), .Y(n1957) );
NAND2X1TS U3259 ( .A(n1449), .B(n3146), .Y(intadd_436_CI) );
OAI21XLTS U3260 ( .A0(n3146), .A1(n1449), .B0(intadd_436_CI), .Y(sh_exp_y[0]) );
NAND2X1TS U3261 ( .A(n1448), .B(n3146), .Y(intadd_435_CI) );
OAI21XLTS U3262 ( .A0(n3146), .A1(n1448), .B0(intadd_435_CI), .Y(sh_exp_x[0]) );
NOR2XLTS U3263 ( .A(cordic_FSM_state_reg[3]), .B(n3269), .Y(enab_d_ff2_RB2)
);
OAI21XLTS U3264 ( .A0(n2596), .A1(n1959), .B0(n2934), .Y(n1148) );
NAND2X2TS U3265 ( .A(n1960), .B(n2060), .Y(n1135) );
OAI2BB1X1TS U3266 ( .A0N(n2950), .A1N(n1961), .B0(n1994), .Y(n1962) );
OAI21XLTS U3267 ( .A0(n1994), .A1(n2971), .B0(n1962), .Y(n1152) );
NOR2X1TS U3268 ( .A(n3044), .B(sel_mux_2_reg[0]), .Y(n1981) );
BUFX4TS U3269 ( .A(n2025), .Y(n2052) );
NOR2XLTS U3270 ( .A(sel_mux_2_reg[1]), .B(n3082), .Y(n1963) );
BUFX4TS U3271 ( .A(n2909), .Y(n2905) );
NOR2X1TS U3272 ( .A(sel_mux_2_reg[1]), .B(sel_mux_2_reg[0]), .Y(n1987) );
INVX2TS U3273 ( .A(n1964), .Y(n1176) );
BUFX4TS U3274 ( .A(n2025), .Y(n2050) );
BUFX4TS U3275 ( .A(n2909), .Y(n2903) );
INVX2TS U3276 ( .A(n1965), .Y(n1169) );
INVX2TS U3277 ( .A(n1966), .Y(n1184) );
BUFX4TS U3278 ( .A(n2025), .Y(n2048) );
BUFX4TS U3279 ( .A(n2909), .Y(n2913) );
AOI222X1TS U3280 ( .A0(n2050), .A1(d_ff3_LUT_out[22]), .B0(n2913), .B1(
d_ff3_sh_x_out[22]), .C0(n2896), .C1(d_ff3_sh_y_out[22]), .Y(n1967) );
INVX2TS U3281 ( .A(n1967), .Y(n1246) );
AOI222X1TS U3282 ( .A0(n2048), .A1(d_ff3_LUT_out[11]), .B0(n2891), .B1(
d_ff3_sh_x_out[11]), .C0(n2912), .C1(d_ff3_sh_y_out[11]), .Y(n1968) );
INVX2TS U3283 ( .A(n1968), .Y(n1235) );
AOI222X1TS U3284 ( .A0(n2052), .A1(d_ff3_LUT_out[19]), .B0(n1444), .B1(
d_ff3_sh_x_out[19]), .C0(n2919), .C1(d_ff3_sh_y_out[19]), .Y(n1969) );
INVX2TS U3285 ( .A(n1969), .Y(n1243) );
AOI222X1TS U3286 ( .A0(n2052), .A1(d_ff3_LUT_out[14]), .B0(n2903), .B1(
d_ff3_sh_x_out[14]), .C0(n1373), .C1(d_ff3_sh_y_out[14]), .Y(n1970) );
INVX2TS U3287 ( .A(n1970), .Y(n1238) );
INVX2TS U3288 ( .A(n1971), .Y(n1165) );
BUFX4TS U3289 ( .A(n2909), .Y(n2897) );
AOI222X1TS U3290 ( .A0(n2050), .A1(d_ff3_LUT_out[26]), .B0(n1444), .B1(
d_ff3_sh_x_out[26]), .C0(n2885), .C1(d_ff3_sh_y_out[26]), .Y(n1972) );
INVX2TS U3291 ( .A(n1972), .Y(n1250) );
AOI222X1TS U3292 ( .A0(n2025), .A1(d_ff3_LUT_out[16]), .B0(n2921), .B1(
d_ff3_sh_x_out[16]), .C0(n2899), .C1(d_ff3_sh_y_out[16]), .Y(n1973) );
INVX2TS U3293 ( .A(n1973), .Y(n1240) );
INVX2TS U3294 ( .A(n1974), .Y(n1242) );
AOI222X1TS U3295 ( .A0(n2048), .A1(d_ff3_LUT_out[20]), .B0(n2905), .B1(
d_ff3_sh_x_out[20]), .C0(n2896), .C1(d_ff3_sh_y_out[20]), .Y(n1975) );
INVX2TS U3296 ( .A(n1975), .Y(n1244) );
AOI222X1TS U3297 ( .A0(n2050), .A1(d_ff3_LUT_out[17]), .B0(n2891), .B1(
d_ff3_sh_x_out[17]), .C0(n2912), .C1(d_ff3_sh_y_out[17]), .Y(n1976) );
INVX2TS U3298 ( .A(n1976), .Y(n1241) );
AOI222X1TS U3299 ( .A0(n2048), .A1(d_ff3_LUT_out[24]), .B0(n2903), .B1(
d_ff3_sh_x_out[24]), .C0(n2919), .C1(d_ff3_sh_y_out[24]), .Y(n1977) );
INVX2TS U3300 ( .A(n1977), .Y(n1248) );
INVX2TS U3301 ( .A(n1978), .Y(n1245) );
INVX2TS U3302 ( .A(n1979), .Y(n1239) );
BUFX4TS U3303 ( .A(n2909), .Y(n2921) );
AOI222X1TS U3304 ( .A0(n2025), .A1(d_ff3_LUT_out[55]), .B0(n1444), .B1(
d_ff3_sh_x_out[55]), .C0(n1374), .C1(d_ff3_sh_y_out[55]), .Y(n1980) );
INVX2TS U3305 ( .A(n1980), .Y(n1279) );
INVX2TS U3306 ( .A(n1982), .Y(n1277) );
AOI222X1TS U3307 ( .A0(n2025), .A1(d_ff3_LUT_out[41]), .B0(n2921), .B1(
d_ff3_sh_x_out[41]), .C0(n2885), .C1(d_ff3_sh_y_out[41]), .Y(n1983) );
INVX2TS U3308 ( .A(n1983), .Y(n1265) );
INVX2TS U3309 ( .A(n1984), .Y(n1174) );
BUFX4TS U3310 ( .A(n2025), .Y(n2918) );
AOI222X1TS U3311 ( .A0(n1445), .A1(d_ff2_Z[63]), .B0(n2903), .B1(d_ff2_Y[63]), .C0(n2899), .C1(d_ff2_X[63]), .Y(n1985) );
INVX2TS U3312 ( .A(n1985), .Y(n1223) );
AOI222X1TS U3313 ( .A0(n2046), .A1(d_ff2_Z[10]), .B0(n2905), .B1(d_ff2_Y[10]), .C0(n2899), .C1(d_ff2_X[10]), .Y(n1986) );
INVX2TS U3314 ( .A(n1986), .Y(n1170) );
AOI222X1TS U3315 ( .A0(n1445), .A1(d_ff2_Z[6]), .B0(n2891), .B1(d_ff2_Y[6]),
.C0(n1987), .C1(d_ff2_X[6]), .Y(n1988) );
INVX2TS U3316 ( .A(n1988), .Y(n1166) );
AOI222X1TS U3317 ( .A0(n2918), .A1(d_ff2_Z[2]), .B0(n2905), .B1(d_ff2_Y[2]),
.C0(n2055), .C1(d_ff2_X[2]), .Y(n1989) );
INVX2TS U3318 ( .A(n1989), .Y(n1162) );
AOI222X1TS U3319 ( .A0(n2050), .A1(d_ff2_Z[12]), .B0(n2913), .B1(d_ff2_Y[12]), .C0(n1374), .C1(d_ff2_X[12]), .Y(n1990) );
INVX2TS U3320 ( .A(n1990), .Y(n1172) );
BUFX4TS U3321 ( .A(n2025), .Y(n2046) );
AOI222X1TS U3322 ( .A0(n1445), .A1(d_ff3_LUT_out[23]), .B0(n2921), .B1(
d_ff3_sh_x_out[23]), .C0(n1373), .C1(d_ff3_sh_y_out[23]), .Y(n1991) );
INVX2TS U3323 ( .A(n1991), .Y(n1247) );
INVX2TS U3324 ( .A(n1992), .Y(n1221) );
AOI222X1TS U3325 ( .A0(n2918), .A1(d_ff3_LUT_out[13]), .B0(n2897), .B1(
d_ff3_sh_x_out[13]), .C0(n2885), .C1(d_ff3_sh_y_out[13]), .Y(n1993) );
INVX2TS U3326 ( .A(n1993), .Y(n1237) );
INVX2TS U3327 ( .A(n1994), .Y(n2584) );
NOR2XLTS U3328 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(n2584), .Y(
add_subt_module_FSM_LZA_load) );
INVX2TS U3329 ( .A(n1995), .Y(n1218) );
INVX2TS U3330 ( .A(n1996), .Y(n1216) );
BUFX4TS U3331 ( .A(n2055), .Y(n2899) );
AOI222X1TS U3332 ( .A0(n2048), .A1(d_ff2_Z[37]), .B0(n2913), .B1(d_ff2_Y[37]), .C0(n1374), .C1(d_ff2_X[37]), .Y(n1997) );
INVX2TS U3333 ( .A(n1997), .Y(n1197) );
BUFX4TS U3334 ( .A(n2055), .Y(n2912) );
INVX2TS U3335 ( .A(n1998), .Y(n1167) );
AOI222X1TS U3336 ( .A0(n2048), .A1(d_ff2_Z[39]), .B0(n1444), .B1(d_ff2_Y[39]), .C0(n2912), .C1(d_ff2_X[39]), .Y(n1999) );
INVX2TS U3337 ( .A(n1999), .Y(n1199) );
BUFX4TS U3338 ( .A(n2055), .Y(n2896) );
INVX2TS U3339 ( .A(n2000), .Y(n1234) );
BUFX4TS U3340 ( .A(n2909), .Y(n2891) );
AOI222X1TS U3341 ( .A0(n1445), .A1(d_ff3_LUT_out[0]), .B0(n2913), .B1(
d_ff3_sh_x_out[0]), .C0(n2912), .C1(d_ff3_sh_y_out[0]), .Y(n2001) );
INVX2TS U3342 ( .A(n2001), .Y(n1224) );
AOI222X1TS U3343 ( .A0(n2052), .A1(d_ff2_Z[40]), .B0(n2903), .B1(d_ff2_Y[40]), .C0(n2919), .C1(d_ff2_X[40]), .Y(n2002) );
INVX2TS U3344 ( .A(n2002), .Y(n1200) );
AOI222X1TS U3345 ( .A0(n2046), .A1(d_ff2_Z[38]), .B0(n2891), .B1(d_ff2_Y[38]), .C0(n2919), .C1(d_ff2_X[38]), .Y(n2003) );
INVX2TS U3346 ( .A(n2003), .Y(n1198) );
AOI222X1TS U3347 ( .A0(n2050), .A1(d_ff3_LUT_out[6]), .B0(n2921), .B1(
d_ff3_sh_x_out[6]), .C0(n2912), .C1(d_ff3_sh_y_out[6]), .Y(n2004) );
INVX2TS U3348 ( .A(n2004), .Y(n1230) );
INVX2TS U3349 ( .A(n2005), .Y(n1225) );
INVX2TS U3350 ( .A(n2006), .Y(n1232) );
AOI222X1TS U3351 ( .A0(n2050), .A1(d_ff2_Z[44]), .B0(n2921), .B1(d_ff2_Y[44]), .C0(n2896), .C1(d_ff2_X[44]), .Y(n2007) );
INVX2TS U3352 ( .A(n2007), .Y(n1204) );
AOI222X1TS U3353 ( .A0(n2046), .A1(d_ff2_Z[48]), .B0(n2905), .B1(d_ff2_Y[48]), .C0(n2896), .C1(d_ff2_X[48]), .Y(n2008) );
INVX2TS U3354 ( .A(n2008), .Y(n1208) );
AOI222X1TS U3355 ( .A0(n1445), .A1(d_ff2_Z[52]), .B0(n2891), .B1(d_ff2_Y[52]), .C0(n1374), .C1(d_ff2_X[52]), .Y(n2009) );
INVX2TS U3356 ( .A(n2009), .Y(n1212) );
AOI222X1TS U3357 ( .A0(n2025), .A1(d_ff2_Z[47]), .B0(n2905), .B1(d_ff2_Y[47]), .C0(n2912), .C1(d_ff2_X[47]), .Y(n2010) );
INVX2TS U3358 ( .A(n2010), .Y(n1207) );
INVX2TS U3359 ( .A(n2011), .Y(n1192) );
AOI222X1TS U3360 ( .A0(n2050), .A1(d_ff3_LUT_out[2]), .B0(n2905), .B1(
d_ff3_sh_x_out[2]), .C0(n2919), .C1(d_ff3_sh_y_out[2]), .Y(n2012) );
INVX2TS U3361 ( .A(n2012), .Y(n1226) );
INVX2TS U3362 ( .A(n2013), .Y(n1161) );
AOI222X1TS U3363 ( .A0(n2052), .A1(d_ff3_LUT_out[12]), .B0(n2913), .B1(
d_ff3_sh_x_out[12]), .C0(n2899), .C1(d_ff3_sh_y_out[12]), .Y(n2014) );
INVX2TS U3364 ( .A(n2014), .Y(n1236) );
INVX2TS U3365 ( .A(n2015), .Y(n1164) );
AOI222X1TS U3366 ( .A0(n2052), .A1(d_ff3_LUT_out[9]), .B0(n1444), .B1(
d_ff3_sh_x_out[9]), .C0(n1374), .C1(d_ff3_sh_y_out[9]), .Y(n2016) );
INVX2TS U3367 ( .A(n2016), .Y(n1233) );
BUFX4TS U3368 ( .A(n2055), .Y(n2919) );
AOI222X1TS U3369 ( .A0(n2048), .A1(d_ff3_LUT_out[52]), .B0(n2905), .B1(
d_ff3_sh_x_out[52]), .C0(n1374), .C1(d_ff3_sh_y_out[52]), .Y(n2017) );
INVX2TS U3370 ( .A(n2017), .Y(n1276) );
AOI222X1TS U3371 ( .A0(n2025), .A1(d_ff3_LUT_out[56]), .B0(n2921), .B1(
d_ff3_sh_x_out[56]), .C0(n2896), .C1(d_ff3_sh_y_out[56]), .Y(n2018) );
INVX2TS U3372 ( .A(n2018), .Y(n1280) );
AOI222X1TS U3373 ( .A0(n2025), .A1(d_ff3_LUT_out[27]), .B0(n2913), .B1(
d_ff3_sh_x_out[27]), .C0(n2912), .C1(d_ff3_sh_y_out[27]), .Y(n2019) );
INVX2TS U3374 ( .A(n2019), .Y(n1251) );
AOI222X1TS U3375 ( .A0(n2025), .A1(d_ff3_LUT_out[54]), .B0(n2891), .B1(
d_ff3_sh_x_out[54]), .C0(n2919), .C1(d_ff3_sh_y_out[54]), .Y(n2020) );
INVX2TS U3376 ( .A(n2020), .Y(n1278) );
AOI222X1TS U3377 ( .A0(n1445), .A1(d_ff3_LUT_out[37]), .B0(n2921), .B1(
d_ff3_sh_x_out[37]), .C0(n2899), .C1(d_ff3_sh_y_out[37]), .Y(n2021) );
INVX2TS U3378 ( .A(n2021), .Y(n1261) );
AOI222X1TS U3379 ( .A0(n2025), .A1(d_ff3_LUT_out[50]), .B0(n1444), .B1(
d_ff3_sh_x_out[50]), .C0(n1374), .C1(d_ff3_sh_y_out[50]), .Y(n2022) );
INVX2TS U3380 ( .A(n2022), .Y(n1274) );
INVX2TS U3381 ( .A(n2023), .Y(n1263) );
AOI222X1TS U3382 ( .A0(n2050), .A1(d_ff3_LUT_out[25]), .B0(n2903), .B1(
d_ff3_sh_x_out[25]), .C0(n2896), .C1(d_ff3_sh_y_out[25]), .Y(n2024) );
INVX2TS U3383 ( .A(n2024), .Y(n1249) );
AOI222X1TS U3384 ( .A0(n2025), .A1(d_ff3_LUT_out[45]), .B0(n2921), .B1(
d_ff3_sh_x_out[45]), .C0(n2912), .C1(d_ff3_sh_y_out[45]), .Y(n2026) );
INVX2TS U3385 ( .A(n2026), .Y(n1269) );
AOI222X1TS U3386 ( .A0(n2046), .A1(d_ff2_Z[0]), .B0(n1444), .B1(d_ff2_Y[0]),
.C0(n2885), .C1(d_ff2_X[0]), .Y(n2027) );
INVX2TS U3387 ( .A(n2027), .Y(n1160) );
AOI222X1TS U3388 ( .A0(n2046), .A1(d_ff2_Z[49]), .B0(n1444), .B1(d_ff2_Y[49]), .C0(n2896), .C1(d_ff2_X[49]), .Y(n3253) );
AOI222X1TS U3389 ( .A0(n1445), .A1(d_ff2_Z[45]), .B0(n2913), .B1(d_ff2_Y[45]), .C0(n2885), .C1(d_ff2_X[45]), .Y(n3254) );
AOI222X1TS U3390 ( .A0(n2918), .A1(d_ff2_Z[43]), .B0(n2903), .B1(d_ff2_Y[43]), .C0(n2899), .C1(d_ff2_X[43]), .Y(n3255) );
INVX2TS U3391 ( .A(n2028), .Y(n1173) );
AOI222X1TS U3392 ( .A0(n2918), .A1(d_ff2_Z[50]), .B0(n2921), .B1(d_ff2_Y[50]), .C0(n2912), .C1(d_ff2_X[50]), .Y(n3252) );
AOI222X1TS U3393 ( .A0(n2048), .A1(d_ff2_Z[41]), .B0(n2897), .B1(d_ff2_Y[41]), .C0(n2919), .C1(d_ff2_X[41]), .Y(n2029) );
INVX2TS U3394 ( .A(n2029), .Y(n1201) );
AOI222X1TS U3395 ( .A0(n2918), .A1(d_ff2_Z[51]), .B0(n2891), .B1(d_ff2_Y[51]), .C0(n2899), .C1(d_ff2_X[51]), .Y(n2030) );
INVX2TS U3396 ( .A(n2030), .Y(n1211) );
AOI222X1TS U3397 ( .A0(n2050), .A1(d_ff3_LUT_out[3]), .B0(n1444), .B1(
d_ff3_sh_x_out[3]), .C0(n2885), .C1(d_ff3_sh_y_out[3]), .Y(n2031) );
INVX2TS U3398 ( .A(n2031), .Y(n1227) );
INVX2TS U3399 ( .A(n2032), .Y(n1181) );
INVX2TS U3400 ( .A(n2033), .Y(n1187) );
INVX2TS U3401 ( .A(n2034), .Y(n1214) );
AOI222X1TS U3402 ( .A0(n2052), .A1(d_ff2_Z[30]), .B0(n2905), .B1(d_ff2_Y[30]), .C0(n2896), .C1(d_ff2_X[30]), .Y(n2035) );
INVX2TS U3403 ( .A(n2035), .Y(n1190) );
AOI222X1TS U3404 ( .A0(n2052), .A1(d_ff2_Z[46]), .B0(n2897), .B1(d_ff2_Y[46]), .C0(n1374), .C1(d_ff2_X[46]), .Y(n2036) );
INVX2TS U3405 ( .A(n2036), .Y(n1206) );
AOI222X1TS U3406 ( .A0(n1445), .A1(d_ff2_Z[25]), .B0(n2905), .B1(d_ff2_Y[25]), .C0(n2919), .C1(d_ff2_X[25]), .Y(n3261) );
INVX2TS U3407 ( .A(n2037), .Y(n1194) );
INVX2TS U3408 ( .A(n2038), .Y(n1180) );
AOI222X1TS U3409 ( .A0(n2918), .A1(d_ff2_Z[36]), .B0(n2891), .B1(d_ff2_Y[36]), .C0(n1374), .C1(d_ff2_X[36]), .Y(n3256) );
AOI222X1TS U3410 ( .A0(n1445), .A1(d_ff2_Z[42]), .B0(n2913), .B1(d_ff2_Y[42]), .C0(n2899), .C1(d_ff2_X[42]), .Y(n2039) );
INVX2TS U3411 ( .A(n2039), .Y(n1202) );
AOI222X1TS U3412 ( .A0(n2025), .A1(d_ff2_Z[29]), .B0(n2897), .B1(d_ff2_Y[29]), .C0(n2885), .C1(d_ff2_X[29]), .Y(n2040) );
INVX2TS U3413 ( .A(n2040), .Y(n1189) );
AOI222X1TS U3414 ( .A0(n2046), .A1(d_ff3_LUT_out[7]), .B0(n2903), .B1(
d_ff3_sh_x_out[7]), .C0(n1374), .C1(d_ff3_sh_y_out[7]), .Y(n2041) );
INVX2TS U3415 ( .A(n2041), .Y(n1231) );
AOI222X1TS U3416 ( .A0(n2050), .A1(d_ff2_Z[19]), .B0(n1444), .B1(d_ff2_Y[19]), .C0(n2896), .C1(d_ff2_X[19]), .Y(n2042) );
INVX2TS U3417 ( .A(n2042), .Y(n1179) );
AOI222X1TS U3418 ( .A0(n2025), .A1(d_ff3_LUT_out[5]), .B0(n2913), .B1(
d_ff3_sh_x_out[5]), .C0(n1374), .C1(d_ff3_sh_y_out[5]), .Y(n2043) );
INVX2TS U3419 ( .A(n2043), .Y(n1229) );
INVX2TS U3420 ( .A(n2044), .Y(n1182) );
AOI222X1TS U3421 ( .A0(n2048), .A1(d_ff3_LUT_out[33]), .B0(n2905), .B1(
d_ff3_sh_x_out[33]), .C0(n2919), .C1(d_ff3_sh_y_out[33]), .Y(n2045) );
INVX2TS U3422 ( .A(n2045), .Y(n1257) );
AOI222X1TS U3423 ( .A0(n2052), .A1(d_ff3_LUT_out[35]), .B0(n2905), .B1(
d_ff3_sh_x_out[35]), .C0(n2899), .C1(d_ff3_sh_y_out[35]), .Y(n2047) );
INVX2TS U3424 ( .A(n2047), .Y(n1259) );
INVX2TS U3425 ( .A(n2049), .Y(n1188) );
INVX2TS U3426 ( .A(n2051), .Y(n1255) );
INVX2TS U3427 ( .A(n2053), .Y(n1183) );
AOI222X1TS U3428 ( .A0(n2918), .A1(d_ff3_LUT_out[29]), .B0(n2897), .B1(
d_ff3_sh_x_out[29]), .C0(n1374), .C1(d_ff3_sh_y_out[29]), .Y(n2054) );
INVX2TS U3429 ( .A(n2054), .Y(n1253) );
AOI222X1TS U3430 ( .A0(n2048), .A1(d_ff2_Z[11]), .B0(n2891), .B1(d_ff2_Y[11]), .C0(n1374), .C1(d_ff2_X[11]), .Y(n2056) );
INVX2TS U3431 ( .A(n2056), .Y(n1171) );
INVX2TS U3432 ( .A(n2057), .Y(n1222) );
AOI222X1TS U3433 ( .A0(d_ff2_Y[57]), .A1(n1444), .B0(d_ff2_X[57]), .B1(n2899), .C0(n2046), .C1(d_ff2_Z[57]), .Y(n3249) );
INVX2TS U3434 ( .A(n2058), .Y(n2872) );
OAI21X1TS U3435 ( .A0(cont_iter_out[1]), .A1(n3146), .B0(n2872), .Y(
data_out_LUT[53]) );
NOR2XLTS U3436 ( .A(n2951), .B(data_out_LUT[53]), .Y(n3272) );
NOR2X1TS U3437 ( .A(cont_iter_out[2]), .B(n2058), .Y(n2244) );
AO21XLTS U3438 ( .A0(n2058), .A1(cont_iter_out[2]), .B0(n2244), .Y(
data_out_LUT[54]) );
NOR2XLTS U3439 ( .A(n2951), .B(data_out_LUT[54]), .Y(n3271) );
NOR2X1TS U3440 ( .A(d_ff2_X[56]), .B(intadd_435_n1), .Y(n2946) );
OR3X1TS U3441 ( .A(d_ff2_X[57]), .B(d_ff2_X[56]), .C(intadd_435_n1), .Y(
n2945) );
OAI21XLTS U3442 ( .A0(n2946), .A1(n3143), .B0(n2945), .Y(sh_exp_x[5]) );
NOR2X1TS U3443 ( .A(d_ff2_Y[56]), .B(intadd_436_n1), .Y(n2940) );
OR3X1TS U3444 ( .A(d_ff2_Y[57]), .B(d_ff2_Y[56]), .C(intadd_436_n1), .Y(
n2939) );
OAI21XLTS U3445 ( .A0(n2940), .A1(n3142), .B0(n2939), .Y(sh_exp_y[5]) );
AOI211XLTS U3446 ( .A0(n2060), .A1(n2950), .B0(n2593), .C0(n2595), .Y(n2061)
);
OAI21XLTS U3447 ( .A0(n2063), .A1(n2062), .B0(n2061), .Y(
add_subt_module_FS_Module_state_next[0]) );
NAND4BX1TS U3448 ( .AN(n2064), .B(cordic_FSM_state_reg[3]), .C(n2995), .D(
n2951), .Y(n2095) );
NOR3XLTS U3449 ( .A(n2094), .B(n2232), .C(n2095), .Y(enab_d_ff4_Zn) );
NOR2X1TS U3450 ( .A(data_out_LUT[56]), .B(n2065), .Y(n2097) );
AOI21X1TS U3451 ( .A0(cont_var_out[0]), .A1(data_out_LUT[56]), .B0(n2097),
.Y(n2242) );
NOR2XLTS U3452 ( .A(n2242), .B(n2095), .Y(enab_d_ff4_Yn) );
OAI22X1TS U3453 ( .A0(n2989), .A1(n2069), .B0(n3081), .B1(n2066), .Y(n2067)
);
OAI22X1TS U3454 ( .A0(n2069), .A1(add_subt_module_LZA_output[4]), .B0(n2068),
.B1(add_subt_module_exp_oper_result[3]), .Y(n2070) );
OAI32X1TS U3455 ( .A0(n2071), .A1(add_subt_module_FSM_selector_B[1]), .A2(
n2070), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]), .B1(
n2071), .Y(n2075) );
NOR4BX1TS U3456 ( .AN(add_subt_module_exp_oper_result[3]), .B(n2072), .C(
add_subt_module_exp_oper_result[5]), .D(n3081), .Y(n2073) );
OAI211XLTS U3457 ( .A0(n2196), .A1(n2076), .B0(n2075), .C0(n2074), .Y(n3277)
);
NAND2X1TS U3458 ( .A(sel_mux_2_reg[1]), .B(n1301), .Y(n2077) );
OAI32X1TS U3459 ( .A0(n1310), .A1(n2094), .A2(n3135), .B0(n1432), .B1(n2077),
.Y(n1138) );
INVX2TS U3460 ( .A(n2861), .Y(n2079) );
INVX2TS U3461 ( .A(data_out_LUT[20]), .Y(n2873) );
NAND2X1TS U3462 ( .A(n2871), .B(n2078), .Y(n2857) );
OAI211XLTS U3463 ( .A0(n2079), .A1(n2873), .B0(n2866), .C0(n2857), .Y(
data_out_LUT[9]) );
NAND2X1TS U3464 ( .A(n2081), .B(n2080), .Y(n2091) );
AOI22X1TS U3465 ( .A0(n2085), .A1(n2084), .B0(n2083), .B1(n2082), .Y(n2086)
);
OAI211XLTS U3466 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]), .A1(
n2971), .B0(n2087), .C0(n2086), .Y(n2088) );
AO21XLTS U3467 ( .A0(n3052), .A1(n2089), .B0(n2088), .Y(n2090) );
OAI211XLTS U3468 ( .A0(n2093), .A1(n2092), .B0(n2091), .C0(n2090), .Y(n3275)
);
AOI21X1TS U3469 ( .A0(n3135), .A1(n2987), .B0(n2094), .Y(n2096) );
NOR3XLTS U3470 ( .A(n2097), .B(n2096), .C(n2095), .Y(enab_d_ff4_Xn) );
NAND2X1TS U3471 ( .A(n3080), .B(n2944), .Y(n2943) );
OAI21XLTS U3472 ( .A0(n2944), .A1(n3080), .B0(n2943), .Y(sh_exp_x[7]) );
NAND2X1TS U3473 ( .A(n1447), .B(n2938), .Y(n2937) );
OAI21XLTS U3474 ( .A0(n2938), .A1(n1447), .B0(n2937), .Y(sh_exp_y[7]) );
NOR2X1TS U3475 ( .A(n2987), .B(n2101), .Y(n2099) );
NOR2XLTS U3476 ( .A(cont_var_out[1]), .B(n2099), .Y(n2098) );
AOI21X1TS U3477 ( .A0(n2232), .A1(n2987), .B0(n2101), .Y(n2100) );
AOI21X1TS U3478 ( .A0(n2101), .A1(n2987), .B0(n2100), .Y(n2102) );
NAND2BXLTS U3479 ( .AN(load_cont_var), .B(n2102), .Y(n2103) );
INVX2TS U3480 ( .A(n2103), .Y(n1146) );
NAND2X1TS U3481 ( .A(n1435), .B(n2771), .Y(n2104) );
OAI211XLTS U3482 ( .A0(n2105), .A1(n1300), .B0(n2140), .C0(n2104), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[52]) );
NOR2X1TS U3483 ( .A(n1300), .B(n2142), .Y(n2109) );
BUFX3TS U3484 ( .A(n2109), .Y(n2767) );
NOR2X1TS U3485 ( .A(n1300), .B(n2123), .Y(n2770) );
AOI22X1TS U3486 ( .A0(n2767), .A1(n1435), .B0(n2781), .B1(n2141), .Y(n2106)
);
OAI211XLTS U3487 ( .A0(n2651), .A1(n2107), .B0(n2106), .C0(n2140), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[53]) );
AOI22X1TS U3488 ( .A0(n2718), .A1(add_subt_module_Add_Subt_result[30]), .B0(
add_subt_module_DmP[22]), .B1(n2692), .Y(n2108) );
OAI2BB1X2TS U3489 ( .A0N(add_subt_module_Add_Subt_result[24]), .A1N(n2769),
.B0(n2108), .Y(n2663) );
BUFX3TS U3490 ( .A(n2109), .Y(n2785) );
AOI22X1TS U3491 ( .A0(n2111), .A1(add_subt_module_Add_Subt_result[29]), .B0(
add_subt_module_DmP[23]), .B1(n2692), .Y(n2110) );
OAI2BB1X2TS U3492 ( .A0N(add_subt_module_Add_Subt_result[25]), .A1N(n2769),
.B0(n2110), .Y(n2657) );
AOI22X1TS U3493 ( .A0(n2761), .A1(n2663), .B0(n2785), .B1(n2657), .Y(n2114)
);
AOI22X1TS U3494 ( .A0(n2111), .A1(add_subt_module_Add_Subt_result[28]), .B0(
add_subt_module_DmP[24]), .B1(n2692), .Y(n2112) );
MX2X1TS U3495 ( .A(add_subt_module_DmP[25]), .B(
add_subt_module_Add_Subt_result[27]), .S0(
add_subt_module_FSM_selector_C), .Y(n2148) );
NAND2X1TS U3496 ( .A(n2652), .B(n2164), .Y(n2153) );
AOI2BB2XLTS U3497 ( .B0(n1298), .B1(n2158), .A0N(n2650), .A1N(n2153), .Y(
n2113) );
OAI211XLTS U3498 ( .A0(n2652), .A1(n2115), .B0(n2114), .C0(n2113), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[24]) );
AO22XLTS U3499 ( .A0(n2527), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[70]), .B0(
n2518), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(
n2118) );
NOR2XLTS U3500 ( .A(n2221), .B(n3052), .Y(n2116) );
OAI22X1TS U3501 ( .A0(n2196), .A1(n2551), .B0(n3077), .B1(n2524), .Y(n2117)
);
AOI211X1TS U3502 ( .A0(n2522), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[62]), .B0(
n2118), .C0(n2117), .Y(n2568) );
BUFX3TS U3503 ( .A(n2119), .Y(n2226) );
OAI2BB2XLTS U3504 ( .B0(n2124), .B1(n2140), .A0N(n1370), .A1N(n1435), .Y(
n2125) );
AOI21X1TS U3505 ( .A0(n2772), .A1(n2141), .B0(n2125), .Y(n2126) );
OAI21XLTS U3506 ( .A0(n2127), .A1(n1300), .B0(n2126), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[50]) );
AOI22X1TS U3507 ( .A0(n2718), .A1(add_subt_module_Add_Subt_result[31]), .B0(
add_subt_module_DmP[21]), .B1(n2692), .Y(n2128) );
OAI2BB1X2TS U3508 ( .A0N(add_subt_module_Add_Subt_result[23]), .A1N(n2769),
.B0(n2128), .Y(n2669) );
AOI222X1TS U3509 ( .A0(n2663), .A1(n2130), .B0(n2669), .B1(n2129), .C0(n2657), .C1(n1812), .Y(n2152) );
AOI22X1TS U3510 ( .A0(n2718), .A1(add_subt_module_Add_Subt_result[33]), .B0(
add_subt_module_DmP[19]), .B1(n2692), .Y(n2131) );
OAI21X4TS U3511 ( .A0(n3086), .A1(n1766), .B0(n2131), .Y(n2681) );
AOI22X1TS U3512 ( .A0(n2718), .A1(add_subt_module_Add_Subt_result[34]), .B0(
add_subt_module_DmP[18]), .B1(n2692), .Y(n2132) );
OAI2BB1X2TS U3513 ( .A0N(add_subt_module_Add_Subt_result[20]), .A1N(n2769),
.B0(n2132), .Y(n2687) );
AOI22X1TS U3514 ( .A0(n2788), .A1(n2681), .B0(n2785), .B1(n2687), .Y(n2137)
);
AOI22X1TS U3515 ( .A0(n2718), .A1(add_subt_module_Add_Subt_result[32]), .B0(
add_subt_module_DmP[20]), .B1(n2692), .Y(n2133) );
OAI2BB1X2TS U3516 ( .A0N(add_subt_module_Add_Subt_result[22]), .A1N(n2769),
.B0(n2133), .Y(n2675) );
AOI22X1TS U3517 ( .A0(n2718), .A1(add_subt_module_Add_Subt_result[35]), .B0(
add_subt_module_DmP[17]), .B1(n2692), .Y(n2134) );
OAI2BB1X2TS U3518 ( .A0N(add_subt_module_Add_Subt_result[19]), .A1N(n2769),
.B0(n2134), .Y(n2694) );
AO22XLTS U3519 ( .A0(n2694), .A1(n2781), .B0(n2643), .B1(n2793), .Y(n2135)
);
AOI21X1TS U3520 ( .A0(n2791), .A1(n2675), .B0(n2135), .Y(n2136) );
OAI211XLTS U3521 ( .A0(n2652), .A1(n2152), .B0(n2137), .C0(n2136), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[19]) );
NAND2X1TS U3522 ( .A(n1435), .B(n2772), .Y(n2138) );
OAI211XLTS U3523 ( .A0(n2139), .A1(n1300), .B0(n2140), .C0(n2138), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[51]) );
AOI2BB2XLTS U3524 ( .B0(n1370), .B1(n2141), .A0N(n2140), .A1N(n2651), .Y(
n2145) );
AOI22X1TS U3525 ( .A0(n2783), .A1(n1435), .B0(n2732), .B1(n2143), .Y(n2144)
);
OAI211XLTS U3526 ( .A0(n2146), .A1(n1300), .B0(n2145), .C0(n2144), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[49]) );
AOI22X1TS U3527 ( .A0(n2768), .A1(n2636), .B0(n2791), .B1(n2643), .Y(n2151)
);
NOR2X1TS U3528 ( .A(n2164), .B(n2645), .Y(n2160) );
AOI22X1TS U3529 ( .A0(n2793), .A1(n2158), .B0(n2160), .B1(n2637), .Y(n2150)
);
AOI22X1TS U3530 ( .A0(n2761), .A1(n2657), .B0(n2767), .B1(n2643), .Y(n2156)
);
AOI2BB2XLTS U3531 ( .B0(n2746), .B1(n2154), .A0N(n2645), .A1N(n2153), .Y(
n2155) );
OAI211XLTS U3532 ( .A0(n2652), .A1(n2157), .B0(n2156), .C0(n2155), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[25]) );
AOI22X1TS U3533 ( .A0(n2788), .A1(n2636), .B0(n2791), .B1(n2158), .Y(n2162)
);
AOI22X1TS U3534 ( .A0(n2652), .A1(n2160), .B0(n2746), .B1(n2159), .Y(n2161)
);
OAI211XLTS U3535 ( .A0(n2652), .A1(n2163), .B0(n2162), .C0(n2161), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[27]) );
AOI22X1TS U3536 ( .A0(n2788), .A1(n2635), .B0(n2772), .B1(n2636), .Y(n2167)
);
NOR2X1TS U3537 ( .A(n2164), .B(n2650), .Y(n2638) );
AOI22X1TS U3538 ( .A0(n2652), .A1(n2638), .B0(n2746), .B1(n2165), .Y(n2166)
);
OAI211XLTS U3539 ( .A0(n2652), .A1(n2168), .B0(n2167), .C0(n2166), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[26]) );
AO22XLTS U3540 ( .A0(n2521), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(
n1299), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[63]), .Y(
n2169) );
NAND2BXLTS U3541 ( .AN(n2581), .B(n2229), .Y(n2171) );
OAI211XLTS U3542 ( .A0(n2583), .A1(n2226), .B0(n2509), .C0(n2171), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[54]) );
OAI2BB2XLTS U3543 ( .B0(n2196), .B1(n2567), .A0N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]), .A1N(
n2521), .Y(n2172) );
AOI211X1TS U3544 ( .A0(n2527), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[77]), .B0(
n2173), .C0(n2172), .Y(n2552) );
OAI211XLTS U3545 ( .A0(n2552), .A1(n2226), .B0(n2509), .C0(n2174), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[39]) );
AO22XLTS U3546 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[65]), .A1(
n2527), .B0(n2190), .B1(n2539), .Y(n2175) );
NAND2BXLTS U3547 ( .AN(n2577), .B(n2229), .Y(n2177) );
AO22XLTS U3548 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[66]), .A1(
n1299), .B0(n2190), .B1(n2541), .Y(n2178) );
NAND2BXLTS U3549 ( .AN(n2575), .B(n2229), .Y(n2180) );
AO22XLTS U3550 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[69]), .A1(
n2527), .B0(n2190), .B1(n2550), .Y(n2181) );
NAND2BXLTS U3551 ( .AN(n2569), .B(n2229), .Y(n2183) );
AO22XLTS U3552 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[68]), .A1(
n2527), .B0(n2190), .B1(n2545), .Y(n2184) );
NAND2BXLTS U3553 ( .AN(n2571), .B(n2229), .Y(n2186) );
AO22XLTS U3554 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[64]), .A1(
n1299), .B0(n2190), .B1(n2537), .Y(n2187) );
NAND2BXLTS U3555 ( .AN(n2579), .B(n2229), .Y(n2189) );
AO22XLTS U3556 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[67]), .A1(
n1299), .B0(n2190), .B1(n2543), .Y(n2191) );
NAND2BXLTS U3557 ( .AN(n2573), .B(n2229), .Y(n2193) );
AO22XLTS U3558 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[86]), .A1(
n2518), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[71]), .B1(
n1299), .Y(n2198) );
NOR2BX1TS U3559 ( .AN(n1441), .B(n2221), .Y(n2195) );
AOI211X1TS U3560 ( .A0(n2208), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[63]), .B0(
n2198), .C0(n2197), .Y(n2566) );
NAND2BXLTS U3561 ( .AN(n2565), .B(n2229), .Y(n2200) );
AO22XLTS U3562 ( .A0(n2527), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[73]), .B0(
n2518), .B1(n1436), .Y(n2203) );
NOR2XLTS U3563 ( .A(n2221), .B(n3049), .Y(n2201) );
AOI211X1TS U3564 ( .A0(n2208), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[65]), .B0(
n2203), .C0(n2202), .Y(n2562) );
NOR2XLTS U3565 ( .A(n2221), .B(n3048), .Y(n2204) );
NAND2BXLTS U3566 ( .AN(n2561), .B(n2229), .Y(n2205) );
AO22XLTS U3567 ( .A0(n2527), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(
n2521), .B1(n1440), .Y(n2207) );
AOI211X1TS U3568 ( .A0(n2208), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[67]), .B0(
n2207), .C0(n2206), .Y(n2558) );
NAND2BXLTS U3569 ( .AN(n2557), .B(n2229), .Y(n2209) );
AO22XLTS U3570 ( .A0(n1299), .A1(n1406), .B0(n2521), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]), .Y(
n2212) );
OAI2BB2XLTS U3571 ( .B0(n2196), .B1(n2559), .A0N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]), .A1N(
n1433), .Y(n2211) );
AOI211X1TS U3572 ( .A0(n2213), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[66]), .B0(
n2212), .C0(n2211), .Y(n2560) );
AO22XLTS U3573 ( .A0(n1299), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(
n2521), .B1(n1437), .Y(n2216) );
AOI211X1TS U3574 ( .A0(n2522), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[69]), .B0(
n2216), .C0(n2215), .Y(n2554) );
NAND2BXLTS U3575 ( .AN(n2553), .B(n2229), .Y(n2217) );
OAI211XLTS U3576 ( .A0(n2554), .A1(n2226), .B0(n2509), .C0(n2217), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[40]) );
AO22XLTS U3577 ( .A0(n1299), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[75]), .B0(
n2521), .B1(n1438), .Y(n2220) );
NOR2XLTS U3578 ( .A(n2221), .B(n3046), .Y(n2218) );
AOI211X1TS U3579 ( .A0(n2522), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[68]), .B0(
n2220), .C0(n2219), .Y(n2556) );
NOR2XLTS U3580 ( .A(n2221), .B(n3047), .Y(n2222) );
NAND2BXLTS U3581 ( .AN(n2555), .B(n2229), .Y(n2225) );
OAI211XLTS U3582 ( .A0(n2556), .A1(n2226), .B0(n2509), .C0(n2225), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[41]) );
AO22XLTS U3583 ( .A0(n1299), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[72]), .B0(
n2521), .B1(n1439), .Y(n2228) );
AOI211X1TS U3584 ( .A0(n2522), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[64]), .B0(
n2228), .C0(n2227), .Y(n2564) );
NAND2BXLTS U3585 ( .AN(n2563), .B(n2229), .Y(n2230) );
AOI31XLTS U3586 ( .A0(cordic_FSM_state_reg[3]), .A1(data_out_LUT[56]), .A2(
n2232), .B0(cordic_FSM_state_reg[1]), .Y(n2236) );
OAI2BB2XLTS U3587 ( .B0(cordic_FSM_state_reg[1]), .B1(ack_cordic), .A0N(
n2949), .A1N(n2241), .Y(n2234) );
INVX2TS U3588 ( .A(n3269), .Y(n2233) );
AOI21X1TS U3589 ( .A0(cordic_FSM_state_reg[2]), .A1(n2234), .B0(n2233), .Y(
n2235) );
OAI31X1TS U3590 ( .A0(cordic_FSM_state_reg[2]), .A1(n2236), .A2(n2951), .B0(
n2235), .Y(n1156) );
XOR2X1TS U3591 ( .A(DP_OP_92J185_122_9081_n1), .B(n3145), .Y(n2931) );
AND4X1TS U3592 ( .A(add_subt_module_Exp_Operation_Module_Data_S[3]), .B(
add_subt_module_Exp_Operation_Module_Data_S[2]), .C(
add_subt_module_Exp_Operation_Module_Data_S[1]), .D(
add_subt_module_Exp_Operation_Module_Data_S[0]), .Y(n2237) );
AND4X1TS U3593 ( .A(add_subt_module_Exp_Operation_Module_Data_S[6]), .B(
add_subt_module_Exp_Operation_Module_Data_S[5]), .C(
add_subt_module_Exp_Operation_Module_Data_S[4]), .D(n2237), .Y(n2238)
);
AND4X1TS U3594 ( .A(add_subt_module_Exp_Operation_Module_Data_S[9]), .B(
add_subt_module_Exp_Operation_Module_Data_S[8]), .C(
add_subt_module_Exp_Operation_Module_Data_S[7]), .D(n2238), .Y(n2239)
);
AND3X1TS U3595 ( .A(n2931), .B(
add_subt_module_Exp_Operation_Module_Data_S[10]), .C(n2239), .Y(n134)
);
NAND2X1TS U3596 ( .A(n2854), .B(n2955), .Y(data_out_LUT[47]) );
OR2X1TS U3597 ( .A(n2240), .B(load_cont_iter), .Y(enab_cont_iter) );
NOR3XLTS U3598 ( .A(cordic_FSM_state_reg[2]), .B(n2949), .C(n2241), .Y(
enab_dff_5) );
NOR2XLTS U3599 ( .A(n2949), .B(n3269), .Y(enab_d_ff5_data_out) );
OAI21XLTS U3600 ( .A0(cont_iter_out[2]), .A1(n2957), .B0(n2864), .Y(
data_out_LUT[5]) );
OAI211XLTS U3601 ( .A0(n2244), .A1(n2957), .B0(n2864), .C0(data_out_LUT[50]),
.Y(data_out_LUT[10]) );
XNOR2X1TS U3602 ( .A(cont_var_out[0]), .B(d_ff3_sign_out), .Y(n2246) );
AO22XLTS U3603 ( .A0(n2897), .A1(d_ff3_sh_x_out[63]), .B0(n2885), .B1(
d_ff3_sh_y_out[63]), .Y(n2245) );
XNOR2X1TS U3604 ( .A(n2246), .B(n2245), .Y(n3144) );
NOR2XLTS U3605 ( .A(n3026), .B(add_subt_module_intDY[53]), .Y(n2247) );
OAI22X1TS U3606 ( .A0(n3027), .A1(add_subt_module_intDY[55]), .B0(
add_subt_module_intDY[54]), .B1(n2963), .Y(n2367) );
AOI211X1TS U3607 ( .A0(add_subt_module_intDX[52]), .A1(n3105), .B0(n2247),
.C0(n2367), .Y(n2369) );
NOR2BX1TS U3608 ( .AN(add_subt_module_intDX[56]), .B(
add_subt_module_intDY[56]), .Y(n2248) );
NOR2X1TS U3609 ( .A(n3028), .B(add_subt_module_intDY[57]), .Y(n2321) );
NAND2X1TS U3610 ( .A(n3131), .B(add_subt_module_intDX[61]), .Y(n2327) );
OAI211X1TS U3611 ( .A0(add_subt_module_intDY[60]), .A1(n3018), .B0(n2331),
.C0(n2327), .Y(n2333) );
NAND2BXLTS U3612 ( .AN(add_subt_module_intDY[59]), .B(
add_subt_module_intDX[59]), .Y(n2323) );
OAI21X1TS U3613 ( .A0(add_subt_module_intDY[58]), .A1(n3148), .B0(n2323),
.Y(n2325) );
NOR2X1TS U3614 ( .A(n3025), .B(add_subt_module_intDY[49]), .Y(n2370) );
NAND2BXLTS U3615 ( .AN(add_subt_module_intDY[51]), .B(
add_subt_module_intDX[51]), .Y(n2372) );
OAI21X1TS U3616 ( .A0(add_subt_module_intDY[50]), .A1(n3017), .B0(n2372),
.Y(n2376) );
AOI211X1TS U3617 ( .A0(add_subt_module_intDX[48]), .A1(n3103), .B0(n2370),
.C0(n2376), .Y(n2249) );
NAND3X1TS U3618 ( .A(n2369), .B(n2378), .C(n2249), .Y(n2386) );
NOR2BX1TS U3619 ( .AN(add_subt_module_intDX[39]), .B(
add_subt_module_intDY[39]), .Y(n2361) );
AOI21X1TS U3620 ( .A0(add_subt_module_intDX[38]), .A1(n3134), .B0(n2361),
.Y(n2360) );
NAND2X1TS U3621 ( .A(n3130), .B(add_subt_module_intDX[37]), .Y(n2349) );
OAI211X1TS U3622 ( .A0(add_subt_module_intDY[36]), .A1(n3016), .B0(n2360),
.C0(n2349), .Y(n2351) );
NOR2X1TS U3623 ( .A(n3024), .B(add_subt_module_intDY[45]), .Y(n2335) );
NAND2BXLTS U3624 ( .AN(add_subt_module_intDY[47]), .B(
add_subt_module_intDX[47]), .Y(n2334) );
OAI21X1TS U3625 ( .A0(add_subt_module_intDY[46]), .A1(n3019), .B0(n2334),
.Y(n2344) );
OA22X1TS U3626 ( .A0(n2975), .A1(add_subt_module_intDY[42]), .B0(n3023),
.B1(add_subt_module_intDY[43]), .Y(n2340) );
NAND2BXLTS U3627 ( .AN(add_subt_module_intDY[41]), .B(
add_subt_module_intDX[41]), .Y(n2251) );
NAND2BXLTS U3628 ( .AN(add_subt_module_intDY[40]), .B(
add_subt_module_intDX[40]), .Y(n2250) );
NAND4XLTS U3629 ( .A(n2342), .B(n2340), .C(n2251), .D(n2250), .Y(n2384) );
NAND2BXLTS U3630 ( .AN(add_subt_module_intDY[32]), .B(
add_subt_module_intDX[32]), .Y(n2252) );
OA22X1TS U3631 ( .A0(n2961), .A1(add_subt_module_intDY[34]), .B0(n3022),
.B1(add_subt_module_intDY[35]), .Y(n2355) );
OAI211XLTS U3632 ( .A0(n3021), .A1(add_subt_module_intDY[33]), .B0(n2252),
.C0(n2355), .Y(n2253) );
NOR4X1TS U3633 ( .A(n2386), .B(n2351), .C(n2384), .D(n2253), .Y(n2390) );
OA22X1TS U3634 ( .A0(n3036), .A1(add_subt_module_intDY[30]), .B0(n2976),
.B1(add_subt_module_intDY[31]), .Y(n2264) );
OAI21XLTS U3635 ( .A0(add_subt_module_intDY[29]), .A1(n3012), .B0(
add_subt_module_intDY[28]), .Y(n2254) );
OAI2BB2XLTS U3636 ( .B0(add_subt_module_intDX[28]), .B1(n2254), .A0N(
add_subt_module_intDY[29]), .A1N(n3012), .Y(n2263) );
NAND2BXLTS U3637 ( .AN(add_subt_module_intDY[27]), .B(
add_subt_module_intDX[27]), .Y(n2257) );
OAI21X1TS U3638 ( .A0(add_subt_module_intDY[26]), .A1(n3033), .B0(n2257),
.Y(n2316) );
NAND2BXLTS U3639 ( .AN(add_subt_module_intDY[29]), .B(
add_subt_module_intDX[29]), .Y(n2255) );
NOR2X1TS U3640 ( .A(n3038), .B(add_subt_module_intDY[25]), .Y(n2313) );
NOR2XLTS U3641 ( .A(n2313), .B(add_subt_module_intDX[24]), .Y(n2256) );
AOI22X1TS U3642 ( .A0(n2256), .A1(add_subt_module_intDY[24]), .B0(
add_subt_module_intDY[25]), .B1(n3038), .Y(n2259) );
AOI32X1TS U3643 ( .A0(n3033), .A1(n2257), .A2(add_subt_module_intDY[26]),
.B0(add_subt_module_intDY[27]), .B1(n2970), .Y(n2258) );
OAI32X1TS U3644 ( .A0(n2316), .A1(n2315), .A2(n2259), .B0(n2258), .B1(n2315),
.Y(n2262) );
OAI21XLTS U3645 ( .A0(add_subt_module_intDY[31]), .A1(n2976), .B0(
add_subt_module_intDY[30]), .Y(n2260) );
OAI2BB2XLTS U3646 ( .B0(add_subt_module_intDX[30]), .B1(n2260), .A0N(
add_subt_module_intDY[31]), .A1N(n2976), .Y(n2261) );
AOI211X1TS U3647 ( .A0(n2264), .A1(n2263), .B0(n2262), .C0(n2261), .Y(n2320)
);
OA22X1TS U3648 ( .A0(n2982), .A1(add_subt_module_intDY[22]), .B0(n3133),
.B1(add_subt_module_intDY[23]), .Y(n2312) );
NAND2BXLTS U3649 ( .AN(add_subt_module_intDY[21]), .B(
add_subt_module_intDX[21]), .Y(n2265) );
OA22X1TS U3650 ( .A0(n3040), .A1(add_subt_module_intDY[14]), .B0(n2978),
.B1(add_subt_module_intDY[15]), .Y(n2293) );
NAND2BXLTS U3651 ( .AN(add_subt_module_intDY[13]), .B(
add_subt_module_intDX[13]), .Y(n2266) );
OAI2BB1X1TS U3652 ( .A0N(n3129), .A1N(add_subt_module_intDX[5]), .B0(
add_subt_module_intDY[4]), .Y(n2267) );
OAI22X1TS U3653 ( .A0(add_subt_module_intDX[4]), .A1(n2267), .B0(n3129),
.B1(add_subt_module_intDX[5]), .Y(n2278) );
OAI2BB1X1TS U3654 ( .A0N(n3127), .A1N(add_subt_module_intDX[7]), .B0(
add_subt_module_intDY[6]), .Y(n2268) );
OAI22X1TS U3655 ( .A0(add_subt_module_intDX[6]), .A1(n2268), .B0(n3127),
.B1(add_subt_module_intDX[7]), .Y(n2277) );
NAND2BXLTS U3656 ( .AN(add_subt_module_intDY[2]), .B(
add_subt_module_intDX[2]), .Y(n2271) );
OAI21XLTS U3657 ( .A0(add_subt_module_intDX[1]), .A1(n3132), .B0(
add_subt_module_intDX[0]), .Y(n2269) );
AOI2BB2XLTS U3658 ( .B0(add_subt_module_intDX[1]), .B1(n3132), .A0N(
add_subt_module_intDY[0]), .A1N(n2269), .Y(n2270) );
OAI211XLTS U3659 ( .A0(n3031), .A1(add_subt_module_intDY[3]), .B0(n2271),
.C0(n2270), .Y(n2274) );
OAI21XLTS U3660 ( .A0(add_subt_module_intDY[3]), .A1(n3031), .B0(
add_subt_module_intDY[2]), .Y(n2272) );
AOI2BB2XLTS U3661 ( .B0(add_subt_module_intDY[3]), .B1(n3031), .A0N(
add_subt_module_intDX[2]), .A1N(n2272), .Y(n2273) );
AOI222X1TS U3662 ( .A0(add_subt_module_intDX[4]), .A1(n2992), .B0(
add_subt_module_intDX[5]), .B1(n3129), .C0(n2274), .C1(n2273), .Y(
n2276) );
AOI22X1TS U3663 ( .A0(add_subt_module_intDX[7]), .A1(n3127), .B0(
add_subt_module_intDX[6]), .B1(n2991), .Y(n2275) );
OAI32X1TS U3664 ( .A0(n2278), .A1(n2277), .A2(n2276), .B0(n2275), .B1(n2277),
.Y(n2296) );
NAND2BXLTS U3665 ( .AN(add_subt_module_intDY[9]), .B(
add_subt_module_intDX[9]), .Y(n2283) );
INVX2TS U3666 ( .A(n2279), .Y(n2286) );
OAI211XLTS U3667 ( .A0(add_subt_module_intDY[8]), .A1(n3020), .B0(n2283),
.C0(n2286), .Y(n2295) );
OAI21XLTS U3668 ( .A0(add_subt_module_intDY[13]), .A1(n3004), .B0(
add_subt_module_intDY[12]), .Y(n2280) );
OAI2BB2XLTS U3669 ( .B0(add_subt_module_intDX[12]), .B1(n2280), .A0N(
add_subt_module_intDY[13]), .A1N(n3004), .Y(n2292) );
NOR2XLTS U3670 ( .A(n2281), .B(add_subt_module_intDX[10]), .Y(n2282) );
AOI22X1TS U3671 ( .A0(add_subt_module_intDY[11]), .A1(n3147), .B0(
add_subt_module_intDY[10]), .B1(n2282), .Y(n2288) );
NAND3XLTS U3672 ( .A(n3020), .B(n2283), .C(add_subt_module_intDY[8]), .Y(
n2285) );
NAND2BXLTS U3673 ( .AN(add_subt_module_intDX[9]), .B(
add_subt_module_intDY[9]), .Y(n2284) );
AOI21X1TS U3674 ( .A0(n2285), .A1(n2284), .B0(n2297), .Y(n2287) );
OAI2BB2XLTS U3675 ( .B0(n2288), .B1(n2297), .A0N(n2287), .A1N(n2286), .Y(
n2291) );
OAI21XLTS U3676 ( .A0(add_subt_module_intDY[15]), .A1(n2978), .B0(
add_subt_module_intDY[14]), .Y(n2289) );
OAI2BB2XLTS U3677 ( .B0(add_subt_module_intDX[14]), .B1(n2289), .A0N(
add_subt_module_intDY[15]), .A1N(n2978), .Y(n2290) );
AOI211X1TS U3678 ( .A0(n2293), .A1(n2292), .B0(n2291), .C0(n2290), .Y(n2294)
);
OAI31X1TS U3679 ( .A0(n2297), .A1(n2296), .A2(n2295), .B0(n2294), .Y(n2299)
);
NOR2X1TS U3680 ( .A(n3032), .B(add_subt_module_intDY[17]), .Y(n2301) );
NAND2BXLTS U3681 ( .AN(add_subt_module_intDY[19]), .B(
add_subt_module_intDX[19]), .Y(n2303) );
OAI21X1TS U3682 ( .A0(add_subt_module_intDY[18]), .A1(n3037), .B0(n2303),
.Y(n2307) );
AOI211XLTS U3683 ( .A0(add_subt_module_intDX[16]), .A1(n3114), .B0(n2301),
.C0(n2307), .Y(n2298) );
NAND3BXLTS U3684 ( .AN(n2306), .B(n2299), .C(n2298), .Y(n2319) );
OAI21XLTS U3685 ( .A0(add_subt_module_intDY[21]), .A1(n3034), .B0(
add_subt_module_intDY[20]), .Y(n2300) );
OAI2BB2XLTS U3686 ( .B0(add_subt_module_intDX[20]), .B1(n2300), .A0N(
add_subt_module_intDY[21]), .A1N(n3034), .Y(n2311) );
AOI22X1TS U3687 ( .A0(n2302), .A1(add_subt_module_intDY[16]), .B0(
add_subt_module_intDY[17]), .B1(n3032), .Y(n2305) );
AOI32X1TS U3688 ( .A0(n3037), .A1(n2303), .A2(add_subt_module_intDY[18]),
.B0(add_subt_module_intDY[19]), .B1(n2979), .Y(n2304) );
OAI32X1TS U3689 ( .A0(n2307), .A1(n2306), .A2(n2305), .B0(n2304), .B1(n2306),
.Y(n2310) );
OAI21XLTS U3690 ( .A0(add_subt_module_intDY[23]), .A1(n3133), .B0(
add_subt_module_intDY[22]), .Y(n2308) );
OAI2BB2XLTS U3691 ( .B0(add_subt_module_intDX[22]), .B1(n2308), .A0N(
add_subt_module_intDY[23]), .A1N(n3133), .Y(n2309) );
AOI211X1TS U3692 ( .A0(n2312), .A1(n2311), .B0(n2310), .C0(n2309), .Y(n2318)
);
NOR2BX1TS U3693 ( .AN(add_subt_module_intDX[24]), .B(
add_subt_module_intDY[24]), .Y(n2314) );
OR4X2TS U3694 ( .A(n2316), .B(n2315), .C(n2314), .D(n2313), .Y(n2317) );
AOI32X1TS U3695 ( .A0(n2320), .A1(n2319), .A2(n2318), .B0(n2317), .B1(n2320),
.Y(n2389) );
NOR2XLTS U3696 ( .A(n2321), .B(add_subt_module_intDX[56]), .Y(n2322) );
AOI22X1TS U3697 ( .A0(add_subt_module_intDY[57]), .A1(n3028), .B0(
add_subt_module_intDY[56]), .B1(n2322), .Y(n2326) );
AOI32X1TS U3698 ( .A0(n3148), .A1(n2323), .A2(add_subt_module_intDY[58]),
.B0(add_subt_module_intDY[59]), .B1(n2973), .Y(n2324) );
OA21XLTS U3699 ( .A0(n2326), .A1(n2325), .B0(n2324), .Y(n2332) );
NAND2BXLTS U3700 ( .AN(add_subt_module_intDX[62]), .B(
add_subt_module_intDY[62]), .Y(n2329) );
NAND3XLTS U3701 ( .A(n3018), .B(n2327), .C(add_subt_module_intDY[60]), .Y(
n2328) );
OAI211XLTS U3702 ( .A0(add_subt_module_intDX[61]), .A1(n3131), .B0(n2329),
.C0(n2328), .Y(n2330) );
OAI2BB2XLTS U3703 ( .B0(n2333), .B1(n2332), .A0N(n2331), .A1N(n2330), .Y(
n2388) );
NOR2BX1TS U3704 ( .AN(n2334), .B(add_subt_module_intDX[46]), .Y(n2348) );
NOR2XLTS U3705 ( .A(n2335), .B(add_subt_module_intDX[44]), .Y(n2336) );
AOI22X1TS U3706 ( .A0(add_subt_module_intDY[45]), .A1(n3024), .B0(
add_subt_module_intDY[44]), .B1(n2336), .Y(n2345) );
OAI21XLTS U3707 ( .A0(add_subt_module_intDY[41]), .A1(n3030), .B0(
add_subt_module_intDY[40]), .Y(n2337) );
OAI2BB2XLTS U3708 ( .B0(add_subt_module_intDX[40]), .B1(n2337), .A0N(
add_subt_module_intDY[41]), .A1N(n3030), .Y(n2341) );
OAI21XLTS U3709 ( .A0(add_subt_module_intDY[43]), .A1(n3023), .B0(
add_subt_module_intDY[42]), .Y(n2338) );
OAI2BB2XLTS U3710 ( .B0(add_subt_module_intDX[42]), .B1(n2338), .A0N(
add_subt_module_intDY[43]), .A1N(n3023), .Y(n2339) );
AOI32X1TS U3711 ( .A0(n2342), .A1(n2341), .A2(n2340), .B0(n2339), .B1(n2342),
.Y(n2343) );
OAI21XLTS U3712 ( .A0(n2345), .A1(n2344), .B0(n2343), .Y(n2347) );
NOR2BX1TS U3713 ( .AN(add_subt_module_intDY[47]), .B(
add_subt_module_intDX[47]), .Y(n2346) );
NAND3XLTS U3714 ( .A(n3016), .B(n2349), .C(add_subt_module_intDY[36]), .Y(
n2350) );
OAI21XLTS U3715 ( .A0(add_subt_module_intDX[37]), .A1(n3130), .B0(n2350),
.Y(n2359) );
INVX2TS U3716 ( .A(n2351), .Y(n2357) );
OAI21XLTS U3717 ( .A0(add_subt_module_intDY[33]), .A1(n3021), .B0(
add_subt_module_intDY[32]), .Y(n2352) );
OAI2BB2XLTS U3718 ( .B0(add_subt_module_intDX[32]), .B1(n2352), .A0N(
add_subt_module_intDY[33]), .A1N(n3021), .Y(n2356) );
OAI2BB2XLTS U3719 ( .B0(add_subt_module_intDX[34]), .B1(n2353), .A0N(
add_subt_module_intDY[35]), .A1N(n3022), .Y(n2354) );
AOI32X1TS U3720 ( .A0(n2357), .A1(n2356), .A2(n2355), .B0(n2354), .B1(n2357),
.Y(n2358) );
OAI2BB1X1TS U3721 ( .A0N(n2360), .A1N(n2359), .B0(n2358), .Y(n2365) );
NOR2BX1TS U3722 ( .AN(add_subt_module_intDY[39]), .B(
add_subt_module_intDX[39]), .Y(n2364) );
NOR3X1TS U3723 ( .A(n3134), .B(n2361), .C(add_subt_module_intDX[38]), .Y(
n2363) );
INVX2TS U3724 ( .A(n2386), .Y(n2362) );
OAI31X1TS U3725 ( .A0(n2365), .A1(n2364), .A2(n2363), .B0(n2362), .Y(n2383)
);
OAI21XLTS U3726 ( .A0(add_subt_module_intDY[53]), .A1(n3026), .B0(
add_subt_module_intDY[52]), .Y(n2366) );
AOI2BB2XLTS U3727 ( .B0(add_subt_module_intDY[53]), .B1(n3026), .A0N(
add_subt_module_intDX[52]), .A1N(n2366), .Y(n2368) );
NOR2XLTS U3728 ( .A(n2368), .B(n2367), .Y(n2381) );
INVX2TS U3729 ( .A(n2369), .Y(n2375) );
AOI22X1TS U3730 ( .A0(add_subt_module_intDY[49]), .A1(n3025), .B0(
add_subt_module_intDY[48]), .B1(n2371), .Y(n2374) );
AOI32X1TS U3731 ( .A0(n3017), .A1(n2372), .A2(add_subt_module_intDY[50]),
.B0(add_subt_module_intDY[51]), .B1(n2974), .Y(n2373) );
OAI32X1TS U3732 ( .A0(n2376), .A1(n2375), .A2(n2374), .B0(n2373), .B1(n2375),
.Y(n2380) );
OAI21XLTS U3733 ( .A0(add_subt_module_intDY[55]), .A1(n3027), .B0(
add_subt_module_intDY[54]), .Y(n2377) );
OAI2BB2XLTS U3734 ( .B0(add_subt_module_intDX[54]), .B1(n2377), .A0N(
add_subt_module_intDY[55]), .A1N(n3027), .Y(n2379) );
OAI31X1TS U3735 ( .A0(n2381), .A1(n2380), .A2(n2379), .B0(n2378), .Y(n2382)
);
OAI221XLTS U3736 ( .A0(n2386), .A1(n2385), .B0(n2384), .B1(n2383), .C0(n2382), .Y(n2387) );
AOI211X1TS U3737 ( .A0(n2390), .A1(n2389), .B0(n2388), .C0(n2387), .Y(n2391)
);
CLKBUFX2TS U3738 ( .A(n2612), .Y(n2600) );
BUFX4TS U3739 ( .A(n2612), .Y(n2608) );
AOI21X1TS U3740 ( .A0(n2608), .A1(n2392), .B0(add_subt_module_intDX[63]),
.Y(n2393) );
AOI21X1TS U3741 ( .A0(n2600), .A1(n3244), .B0(n2393), .Y(n3270) );
CMPR32X2TS U3742 ( .A(n2396), .B(n2395), .C(n2394), .CO(n1566), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[54]) );
AFHCINX2TS U3743 ( .CIN(n2397), .B(n2398), .A(n2399), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[39]), .CO(n1582) );
AFHCONX2TS U3744 ( .A(n2402), .B(n2401), .CI(n2400), .CON(n2397), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[38]) );
AFHCONX2TS U3745 ( .A(n2405), .B(n2404), .CI(n2403), .CON(n1562), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[36]) );
AFHCONX2TS U3746 ( .A(n2408), .B(n2407), .CI(n2406), .CON(n1540), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[34]) );
AFHCONX2TS U3747 ( .A(n2411), .B(n2410), .CI(n2409), .CON(n1493), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[32]) );
AFHCONX2TS U3748 ( .A(n2414), .B(n2413), .CI(n2412), .CON(n1496), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[30]) );
AFHCONX2TS U3749 ( .A(n2417), .B(n2416), .CI(n2415), .CON(n1499), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[28]) );
AFHCONX2TS U3750 ( .A(n2420), .B(n2419), .CI(n2418), .CON(n1502), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[26]) );
AFHCONX2TS U3751 ( .A(n2423), .B(n2422), .CI(n2421), .CON(n1505), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[24]) );
AFHCONX2TS U3752 ( .A(n2426), .B(n2425), .CI(n2424), .CON(n1508), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[22]) );
AFHCONX2TS U3753 ( .A(n2429), .B(n2428), .CI(n2427), .CON(n1511), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[20]) );
AFHCONX2TS U3754 ( .A(n2432), .B(n2431), .CI(n2430), .CON(n1514), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[18]) );
AFHCONX2TS U3755 ( .A(n2435), .B(n2434), .CI(n2433), .CON(n1517), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[16]) );
AFHCONX2TS U3756 ( .A(n2438), .B(n2437), .CI(n2436), .CON(n1520), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[14]) );
AFHCONX2TS U3757 ( .A(n2441), .B(n2440), .CI(n2439), .CON(n1523), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[12]) );
AFHCONX2TS U3758 ( .A(n2444), .B(n2443), .CI(n2442), .CON(n1526), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[10]) );
AFHCONX2TS U3759 ( .A(n2447), .B(n2446), .CI(n2445), .CON(n1529), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[8]) );
AFHCONX2TS U3760 ( .A(n2450), .B(n2449), .CI(n2448), .CON(n1532), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[6]) );
AFHCONX2TS U3761 ( .A(n2453), .B(n2452), .CI(n2451), .CON(n1535), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[4]) );
AFHCONX2TS U3762 ( .A(n2456), .B(n2455), .CI(n2454), .CON(n1490), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[2]) );
AFHCINX2TS U3763 ( .CIN(n2457), .B(n2458), .A(n2459), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[1]), .CO(n2454) );
AFHCONX2TS U3764 ( .A(n2462), .B(n2461), .CI(n2460), .CON(n2457), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[0]) );
CLKAND2X2TS U3765 ( .A(n1297), .B(add_subt_module_DmP[62]), .Y(n2463) );
XOR2X1TS U3766 ( .A(n3145), .B(n2463), .Y(DP_OP_92J185_122_9081_n16) );
CLKAND2X2TS U3767 ( .A(n1297), .B(add_subt_module_DmP[61]), .Y(n2464) );
XOR2X1TS U3768 ( .A(n3145), .B(n2464), .Y(DP_OP_92J185_122_9081_n17) );
CLKAND2X2TS U3769 ( .A(n1297), .B(add_subt_module_DmP[60]), .Y(n2465) );
XOR2X1TS U3770 ( .A(n3145), .B(n2465), .Y(DP_OP_92J185_122_9081_n18) );
CLKAND2X2TS U3771 ( .A(n1297), .B(add_subt_module_DmP[59]), .Y(n2466) );
XOR2X1TS U3772 ( .A(n3145), .B(n2466), .Y(DP_OP_92J185_122_9081_n19) );
CLKAND2X2TS U3773 ( .A(n1297), .B(add_subt_module_DmP[58]), .Y(n2467) );
XOR2X1TS U3774 ( .A(n3145), .B(n2467), .Y(DP_OP_92J185_122_9081_n20) );
OAI2BB1X1TS U3775 ( .A0N(n1297), .A1N(add_subt_module_DmP[57]), .B0(n2468),
.Y(n2469) );
XOR2X1TS U3776 ( .A(n3145), .B(n2469), .Y(DP_OP_92J185_122_9081_n21) );
OAI2BB1X1TS U3777 ( .A0N(n1297), .A1N(add_subt_module_DmP[56]), .B0(n2470),
.Y(n2471) );
XOR2X1TS U3778 ( .A(n3145), .B(n2471), .Y(DP_OP_92J185_122_9081_n22) );
OAI2BB1X1TS U3779 ( .A0N(n1297), .A1N(add_subt_module_DmP[55]), .B0(n2472),
.Y(n2473) );
XOR2X1TS U3780 ( .A(n3145), .B(n2473), .Y(DP_OP_92J185_122_9081_n23) );
AO21XLTS U3781 ( .A0(add_subt_module_DmP[52]), .A1(n2993), .B0(n2474), .Y(
n2475) );
XOR2X1TS U3782 ( .A(n3145), .B(n2475), .Y(DP_OP_92J185_122_9081_n26) );
AOI22X1TS U3783 ( .A0(n2476), .A1(add_subt_module_Add_Subt_result[1]), .B0(
n2481), .B1(add_subt_module_Add_Subt_result[13]), .Y(n2825) );
NAND2X1TS U3784 ( .A(n2990), .B(n2477), .Y(n2483) );
NOR2X1TS U3785 ( .A(n2478), .B(n3060), .Y(n2495) );
OAI21XLTS U3786 ( .A0(add_subt_module_Add_Subt_result[14]), .A1(n2479), .B0(
n2814), .Y(n2480) );
OAI2BB1X1TS U3787 ( .A0N(add_subt_module_Add_Subt_result[10]), .A1N(n2481),
.B0(n2480), .Y(n2482) );
AOI211XLTS U3788 ( .A0(n2800), .A1(n2483), .B0(n2495), .C0(n2482), .Y(n2484)
);
MX2X1TS U3789 ( .A(add_subt_module_DMP[62]), .B(
add_subt_module_exp_oper_result[10]), .S0(n2487), .Y(
add_subt_module_S_Oper_A_exp[10]) );
MX2X1TS U3790 ( .A(add_subt_module_DMP[61]), .B(
add_subt_module_exp_oper_result[9]), .S0(
add_subt_module_FSM_selector_D), .Y(add_subt_module_S_Oper_A_exp[9])
);
MX2X1TS U3791 ( .A(add_subt_module_DMP[60]), .B(
add_subt_module_exp_oper_result[8]), .S0(
add_subt_module_FSM_selector_D), .Y(add_subt_module_S_Oper_A_exp[8])
);
MX2X1TS U3792 ( .A(add_subt_module_DMP[59]), .B(
add_subt_module_exp_oper_result[7]), .S0(
add_subt_module_FSM_selector_D), .Y(add_subt_module_S_Oper_A_exp[7])
);
MX2X1TS U3793 ( .A(add_subt_module_DMP[58]), .B(
add_subt_module_exp_oper_result[6]), .S0(
add_subt_module_FSM_selector_D), .Y(add_subt_module_S_Oper_A_exp[6])
);
MX2X1TS U3794 ( .A(add_subt_module_DMP[57]), .B(
add_subt_module_exp_oper_result[5]), .S0(
add_subt_module_FSM_selector_D), .Y(add_subt_module_S_Oper_A_exp[5])
);
MX2X1TS U3795 ( .A(add_subt_module_DMP[56]), .B(
add_subt_module_exp_oper_result[4]), .S0(
add_subt_module_FSM_selector_D), .Y(add_subt_module_S_Oper_A_exp[4])
);
MX2X1TS U3796 ( .A(add_subt_module_DMP[55]), .B(
add_subt_module_exp_oper_result[3]), .S0(
add_subt_module_FSM_selector_D), .Y(add_subt_module_S_Oper_A_exp[3])
);
MX2X1TS U3797 ( .A(add_subt_module_DMP[54]), .B(
add_subt_module_exp_oper_result[2]), .S0(n2489), .Y(
add_subt_module_S_Oper_A_exp[2]) );
MX2X1TS U3798 ( .A(add_subt_module_DMP[53]), .B(
add_subt_module_exp_oper_result[1]), .S0(n2489), .Y(
add_subt_module_S_Oper_A_exp[1]) );
MX2X1TS U3799 ( .A(add_subt_module_DMP[52]), .B(
add_subt_module_exp_oper_result[0]), .S0(n2489), .Y(
add_subt_module_S_Oper_A_exp[0]) );
NOR2XLTS U3800 ( .A(n2491), .B(n2490), .Y(n2493) );
NOR2X1TS U3801 ( .A(n2496), .B(n2495), .Y(n2823) );
INVX2TS U3802 ( .A(n2497), .Y(n2504) );
INVX2TS U3803 ( .A(n2498), .Y(n2500) );
AOI211X1TS U3804 ( .A0(n2505), .A1(n2504), .B0(n2503), .C0(n2502), .Y(n2508)
);
OAI211XLTS U3805 ( .A0(add_subt_module_Add_Subt_result[10]), .A1(n1442),
.B0(n2506), .C0(n3061), .Y(n2507) );
AOI22X1TS U3806 ( .A0(n1441), .A1(n1433), .B0(n2522), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[78]), .Y(
n2510) );
OAI211XLTS U3807 ( .A0(n2194), .A1(n3078), .B0(n2510), .C0(n2509), .Y(n2511)
);
AOI21X1TS U3808 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[96]), .A1(
n2521), .B0(n2511), .Y(n2533) );
AOI22X1TS U3809 ( .A0(n2208), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(
n2521), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]), .Y(
n2512) );
AOI211X1TS U3810 ( .A0(n1437), .A1(n2527), .B0(n2526), .C0(n2513), .Y(n2532)
);
MXI2X1TS U3811 ( .A(n2533), .B(n2532), .S0(n2547), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[30]) );
AOI22X1TS U3812 ( .A0(n2208), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]), .B0(
n2518), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[101]), .Y(
n2514) );
OAI21XLTS U3813 ( .A0(n2524), .A1(n3046), .B0(n2514), .Y(n2515) );
AOI211X1TS U3814 ( .A0(n1438), .A1(n1299), .B0(n2526), .C0(n2515), .Y(n2530)
);
AOI22X1TS U3815 ( .A0(n2522), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]), .B0(
n2518), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[97]), .Y(
n2516) );
AOI211X1TS U3816 ( .A0(n1439), .A1(n2527), .B0(n2526), .C0(n2517), .Y(n2531)
);
MXI2X1TS U3817 ( .A(n2530), .B(n2531), .S0(n2759), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[29]) );
AOI22X1TS U3818 ( .A0(n2208), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]), .B0(
n2518), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]), .Y(
n2519) );
OAI21XLTS U3819 ( .A0(n2524), .A1(n3048), .B0(n2519), .Y(n2520) );
AOI211X1TS U3820 ( .A0(n1440), .A1(n2527), .B0(n2526), .C0(n2520), .Y(n2528)
);
AOI22X1TS U3821 ( .A0(n2522), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]), .B0(
n2521), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[98]), .Y(
n2523) );
OAI21XLTS U3822 ( .A0(n2524), .A1(n3049), .B0(n2523), .Y(n2525) );
AOI211X1TS U3823 ( .A0(n1436), .A1(n1299), .B0(n2526), .C0(n2525), .Y(n2529)
);
MXI2X1TS U3824 ( .A(n2528), .B(n2529), .S0(n2759), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[28]) );
MXI2X1TS U3825 ( .A(n2529), .B(n2528), .S0(n2759), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[26]) );
MXI2X1TS U3826 ( .A(n2531), .B(n2530), .S0(n2759), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[25]) );
MXI2X1TS U3827 ( .A(n2533), .B(n2532), .S0(n2759), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[24]) );
INVX2TS U3828 ( .A(n2534), .Y(n2549) );
AO22XLTS U3829 ( .A0(n2536), .A1(n2547), .B0(n2535), .B1(n2549), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[22]) );
AO22XLTS U3830 ( .A0(n2538), .A1(n2119), .B0(n2537), .B1(n2549), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[21]) );
AO22XLTS U3831 ( .A0(n2540), .A1(n2547), .B0(n2539), .B1(n2549), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[20]) );
AO22XLTS U3832 ( .A0(n2542), .A1(n2547), .B0(n2541), .B1(n2549), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[19]) );
AO22XLTS U3833 ( .A0(n2544), .A1(n2119), .B0(n2543), .B1(n2549), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[18]) );
AO22XLTS U3834 ( .A0(n2546), .A1(n2547), .B0(n2545), .B1(n2549), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[17]) );
AO22XLTS U3835 ( .A0(n2550), .A1(n2549), .B0(n2548), .B1(n2547), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[16]) );
OAI22X1TS U3836 ( .A0(n2552), .A1(n2778), .B0(n2551), .B1(n2534), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[15]) );
OAI22X1TS U3837 ( .A0(n2554), .A1(n2582), .B0(n2553), .B1(n2534), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[14]) );
OAI22X1TS U3838 ( .A0(n2556), .A1(n2778), .B0(n2555), .B1(n2534), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[13]) );
OAI22X1TS U3839 ( .A0(n2558), .A1(n2582), .B0(n2557), .B1(n2534), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[12]) );
OAI22X1TS U3840 ( .A0(n2560), .A1(n2778), .B0(n2559), .B1(n2534), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[11]) );
OAI22X1TS U3841 ( .A0(n2562), .A1(n2582), .B0(n2561), .B1(n2534), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[10]) );
OAI22X1TS U3842 ( .A0(n2564), .A1(n2778), .B0(n2563), .B1(n2534), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[9]) );
OAI22X1TS U3843 ( .A0(n2566), .A1(n2582), .B0(n2565), .B1(n2534), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[8]) );
OAI22X1TS U3844 ( .A0(n2568), .A1(n2778), .B0(n2567), .B1(n2534), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[7]) );
OAI22X1TS U3845 ( .A0(n2570), .A1(n2582), .B0(n2569), .B1(n2534), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[6]) );
OAI22X1TS U3846 ( .A0(n2572), .A1(n2778), .B0(n2571), .B1(n2534), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[5]) );
OAI22X1TS U3847 ( .A0(n2574), .A1(n2582), .B0(n2573), .B1(n2534), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[4]) );
OAI22X1TS U3848 ( .A0(n2576), .A1(n2778), .B0(n2575), .B1(n2534), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[3]) );
OAI22X1TS U3849 ( .A0(n2578), .A1(n2582), .B0(n2577), .B1(n2534), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[2]) );
OAI22X1TS U3850 ( .A0(n2580), .A1(n2778), .B0(n2579), .B1(n2534), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[1]) );
OAI22X1TS U3851 ( .A0(n2583), .A1(n2582), .B0(n2581), .B1(n2534), .Y(
add_subt_module_Barrel_Shifter_module_Data_Reg[0]) );
MXI2X1TS U3852 ( .A(add_subt_module_add_overflow_flag), .B(n2993), .S0(n2584), .Y(n1149) );
NAND2BXLTS U3853 ( .AN(add_subt_module_exp_oper_result[0]), .B(n2828), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[0]) );
NAND2BXLTS U3854 ( .AN(add_subt_module_exp_oper_result[6]), .B(n2828), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[6]) );
NAND2BXLTS U3855 ( .AN(add_subt_module_exp_oper_result[7]), .B(n2828), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[7]) );
NAND2BXLTS U3856 ( .AN(add_subt_module_exp_oper_result[8]), .B(n2828), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[8]) );
NAND2BXLTS U3857 ( .AN(add_subt_module_exp_oper_result[9]), .B(n2828), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[9]) );
NAND2BXLTS U3858 ( .AN(add_subt_module_exp_oper_result[10]), .B(n2828), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[10]) );
OAI21XLTS U3860 ( .A0(n3247), .A1(n2585), .B0(cont_iter_out[3]), .Y(n2588)
);
NAND2X1TS U3861 ( .A(n2587), .B(n2586), .Y(n2867) );
AOI21X1TS U3862 ( .A0(n2588), .A1(n2867), .B0(n2951), .Y(n3274) );
AOI21X1TS U3863 ( .A0(n1450), .A1(n3141), .B0(overflow_flag), .Y(
add_subt_module_final_result_ieee_Module_Sign_S_mux) );
NOR2XLTS U3864 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[1]),
.Y(n2590) );
NOR2XLTS U3865 ( .A(cordic_FSM_state_reg[3]), .B(n2956), .Y(n2589) );
AOI32X1TS U3866 ( .A0(n2590), .A1(cordic_FSM_state_reg[0]), .A2(
beg_fsm_cordic), .B0(n2589), .B1(n2951), .Y(n2592) );
NAND4BXLTS U3867 ( .AN(load_cont_var), .B(n2922), .C(n2592), .D(n2591), .Y(
cordic_FSM_state_next_1_) );
AOI21X1TS U3868 ( .A0(n2595), .A1(n2594), .B0(n2593), .Y(n2597) );
NAND4XLTS U3869 ( .A(n2598), .B(n2597), .C(n2932), .D(n2596), .Y(
add_subt_module_FS_Module_state_next[3]) );
INVX2TS U3870 ( .A(n2600), .Y(n2599) );
AOI22X1TS U3871 ( .A0(n2599), .A1(n3050), .B0(n2983), .B1(n2608), .Y(
add_subt_module_Oper_Start_in_module_intm[0]) );
AOI22X1TS U3872 ( .A0(n2599), .A1(n3132), .B0(n3029), .B1(n2608), .Y(
add_subt_module_Oper_Start_in_module_intm[1]) );
AOI22X1TS U3873 ( .A0(n2599), .A1(n3126), .B0(n2981), .B1(n2608), .Y(
add_subt_module_Oper_Start_in_module_intm[2]) );
AOI22X1TS U3874 ( .A0(n2599), .A1(n3066), .B0(n3031), .B1(n2608), .Y(
add_subt_module_Oper_Start_in_module_intm[3]) );
AOI22X1TS U3875 ( .A0(n2599), .A1(n2992), .B0(n3039), .B1(n2608), .Y(
add_subt_module_Oper_Start_in_module_intm[4]) );
AOI22X1TS U3876 ( .A0(n2599), .A1(n3129), .B0(n2969), .B1(n2608), .Y(
add_subt_module_Oper_Start_in_module_intm[5]) );
AOI22X1TS U3877 ( .A0(n2599), .A1(n2991), .B0(n3008), .B1(n2608), .Y(
add_subt_module_Oper_Start_in_module_intm[6]) );
AOI22X1TS U3878 ( .A0(n2599), .A1(n3127), .B0(n2967), .B1(n2608), .Y(
add_subt_module_Oper_Start_in_module_intm[7]) );
AOI22X1TS U3879 ( .A0(n2599), .A1(n3089), .B0(n3020), .B1(n2608), .Y(
add_subt_module_Oper_Start_in_module_intm[8]) );
INVX4TS U3880 ( .A(n2600), .Y(n2607) );
BUFX3TS U3881 ( .A(n2612), .Y(n2611) );
AOI22X1TS U3882 ( .A0(n2607), .A1(n3118), .B0(n2959), .B1(n2611), .Y(
add_subt_module_Oper_Start_in_module_intm[9]) );
AOI22X1TS U3883 ( .A0(n2607), .A1(n3128), .B0(n2958), .B1(n2612), .Y(
add_subt_module_Oper_Start_in_module_intm[10]) );
AOI22X1TS U3884 ( .A0(n2607), .A1(n3098), .B0(n3147), .B1(n2602), .Y(
add_subt_module_Oper_Start_in_module_intm[11]) );
AOI22X1TS U3885 ( .A0(n2607), .A1(n3088), .B0(n3009), .B1(n2608), .Y(
add_subt_module_Oper_Start_in_module_intm[12]) );
AOI22X1TS U3886 ( .A0(n2607), .A1(n3073), .B0(n3004), .B1(n2608), .Y(
add_subt_module_Oper_Start_in_module_intm[13]) );
AOI22X1TS U3887 ( .A0(n2607), .A1(n3122), .B0(n3040), .B1(n2608), .Y(
add_subt_module_Oper_Start_in_module_intm[14]) );
AOI22X1TS U3888 ( .A0(n2607), .A1(n3074), .B0(n2978), .B1(n2608), .Y(
add_subt_module_Oper_Start_in_module_intm[15]) );
AOI22X1TS U3889 ( .A0(n2607), .A1(n3114), .B0(n3041), .B1(n2608), .Y(
add_subt_module_Oper_Start_in_module_intm[16]) );
AOI22X1TS U3890 ( .A0(n2607), .A1(n3106), .B0(n3032), .B1(n2608), .Y(
add_subt_module_Oper_Start_in_module_intm[17]) );
AOI22X1TS U3891 ( .A0(n2607), .A1(n3107), .B0(n3037), .B1(n2608), .Y(
add_subt_module_Oper_Start_in_module_intm[18]) );
BUFX4TS U3892 ( .A(n2601), .Y(n2615) );
AOI22X1TS U3893 ( .A0(n2607), .A1(n3121), .B0(n2979), .B1(n2615), .Y(
add_subt_module_Oper_Start_in_module_intm[19]) );
AOI22X1TS U3894 ( .A0(n2607), .A1(n3104), .B0(n3042), .B1(n2615), .Y(
add_subt_module_Oper_Start_in_module_intm[20]) );
BUFX4TS U3895 ( .A(n2601), .Y(n2609) );
AOI22X1TS U3896 ( .A0(n2607), .A1(n3075), .B0(n3034), .B1(n2609), .Y(
add_subt_module_Oper_Start_in_module_intm[21]) );
INVX4TS U3897 ( .A(n2600), .Y(n2606) );
AOI22X1TS U3898 ( .A0(n2606), .A1(n3123), .B0(n2982), .B1(n2615), .Y(
add_subt_module_Oper_Start_in_module_intm[22]) );
AOI22X1TS U3899 ( .A0(n2606), .A1(n3011), .B0(n3133), .B1(n2615), .Y(
add_subt_module_Oper_Start_in_module_intm[23]) );
AOI22X1TS U3900 ( .A0(n2606), .A1(n3108), .B0(n2980), .B1(n2609), .Y(
add_subt_module_Oper_Start_in_module_intm[24]) );
AOI22X1TS U3901 ( .A0(n2606), .A1(n3113), .B0(n3038), .B1(n2609), .Y(
add_subt_module_Oper_Start_in_module_intm[25]) );
BUFX3TS U3902 ( .A(n2601), .Y(n2602) );
AOI22X1TS U3903 ( .A0(n2606), .A1(n3101), .B0(n3033), .B1(n2602), .Y(
add_subt_module_Oper_Start_in_module_intm[26]) );
AOI22X1TS U3904 ( .A0(n2606), .A1(n3124), .B0(n2970), .B1(n2609), .Y(
add_subt_module_Oper_Start_in_module_intm[27]) );
AOI22X1TS U3905 ( .A0(n2606), .A1(n3100), .B0(n3035), .B1(n2601), .Y(
add_subt_module_Oper_Start_in_module_intm[28]) );
AOI22X1TS U3906 ( .A0(n2606), .A1(n3076), .B0(n3012), .B1(n2601), .Y(
add_subt_module_Oper_Start_in_module_intm[29]) );
AOI22X1TS U3907 ( .A0(n2606), .A1(n3120), .B0(n3036), .B1(n2602), .Y(
add_subt_module_Oper_Start_in_module_intm[30]) );
AOI22X1TS U3908 ( .A0(n2606), .A1(n3069), .B0(n2976), .B1(n2615), .Y(
add_subt_module_Oper_Start_in_module_intm[31]) );
AOI22X1TS U3909 ( .A0(n2606), .A1(n3115), .B0(n2960), .B1(n2609), .Y(
add_subt_module_Oper_Start_in_module_intm[32]) );
AOI22X1TS U3910 ( .A0(n2606), .A1(n3068), .B0(n3021), .B1(n2615), .Y(
add_subt_module_Oper_Start_in_module_intm[33]) );
AOI22X1TS U3911 ( .A0(n2606), .A1(n3111), .B0(n2961), .B1(n2615), .Y(
add_subt_module_Oper_Start_in_module_intm[34]) );
INVX4TS U3912 ( .A(n2600), .Y(n2604) );
AOI22X1TS U3913 ( .A0(n2604), .A1(n3070), .B0(n3022), .B1(n2609), .Y(
add_subt_module_Oper_Start_in_module_intm[35]) );
AOI22X1TS U3914 ( .A0(n2604), .A1(n3093), .B0(n3016), .B1(n2601), .Y(
add_subt_module_Oper_Start_in_module_intm[36]) );
AOI22X1TS U3915 ( .A0(n2604), .A1(n3130), .B0(n3010), .B1(n2601), .Y(
add_subt_module_Oper_Start_in_module_intm[37]) );
AOI22X1TS U3916 ( .A0(n2604), .A1(n3134), .B0(n2962), .B1(n2609), .Y(
add_subt_module_Oper_Start_in_module_intm[38]) );
BUFX4TS U3917 ( .A(n2612), .Y(n2613) );
AOI22X1TS U3918 ( .A0(n2604), .A1(n3117), .B0(n2977), .B1(n2613), .Y(
add_subt_module_Oper_Start_in_module_intm[39]) );
AOI22X1TS U3919 ( .A0(n2604), .A1(n3116), .B0(n2952), .B1(n2613), .Y(
add_subt_module_Oper_Start_in_module_intm[40]) );
AOI22X1TS U3920 ( .A0(n2604), .A1(n3072), .B0(n3030), .B1(n2613), .Y(
add_subt_module_Oper_Start_in_module_intm[41]) );
AOI22X1TS U3921 ( .A0(n2604), .A1(n3112), .B0(n2975), .B1(n2613), .Y(
add_subt_module_Oper_Start_in_module_intm[42]) );
AOI22X1TS U3922 ( .A0(n2604), .A1(n3071), .B0(n3023), .B1(n2613), .Y(
add_subt_module_Oper_Start_in_module_intm[43]) );
AOI22X1TS U3923 ( .A0(n2604), .A1(n3102), .B0(n3005), .B1(n2613), .Y(
add_subt_module_Oper_Start_in_module_intm[44]) );
AOI22X1TS U3924 ( .A0(n2604), .A1(n3090), .B0(n3024), .B1(n2613), .Y(
add_subt_module_Oper_Start_in_module_intm[45]) );
AOI22X1TS U3925 ( .A0(n2604), .A1(n3087), .B0(n3019), .B1(n2613), .Y(
add_subt_module_Oper_Start_in_module_intm[46]) );
AOI22X1TS U3926 ( .A0(n2604), .A1(n3125), .B0(n2968), .B1(n2613), .Y(
add_subt_module_Oper_Start_in_module_intm[47]) );
INVX4TS U3927 ( .A(n2612), .Y(n2603) );
AOI22X1TS U3928 ( .A0(n2603), .A1(n3103), .B0(n3006), .B1(n2613), .Y(
add_subt_module_Oper_Start_in_module_intm[48]) );
AOI22X1TS U3929 ( .A0(n2603), .A1(n3091), .B0(n3025), .B1(n2611), .Y(
add_subt_module_Oper_Start_in_module_intm[49]) );
AOI22X1TS U3930 ( .A0(n2603), .A1(n3096), .B0(n3017), .B1(n2611), .Y(
add_subt_module_Oper_Start_in_module_intm[50]) );
AOI22X1TS U3931 ( .A0(n2603), .A1(n3109), .B0(n2974), .B1(n2611), .Y(
add_subt_module_Oper_Start_in_module_intm[51]) );
AOI22X1TS U3932 ( .A0(n2603), .A1(n3105), .B0(n3007), .B1(n2611), .Y(
add_subt_module_Oper_Start_in_module_intm[52]) );
AOI22X1TS U3933 ( .A0(n2603), .A1(n3065), .B0(n3026), .B1(n2611), .Y(
add_subt_module_Oper_Start_in_module_intm[53]) );
AOI22X1TS U3934 ( .A0(n2603), .A1(n3094), .B0(n2963), .B1(n2611), .Y(
add_subt_module_Oper_Start_in_module_intm[54]) );
AOI22X1TS U3935 ( .A0(n2603), .A1(n3067), .B0(n3027), .B1(n2611), .Y(
add_subt_module_Oper_Start_in_module_intm[55]) );
AOI22X1TS U3936 ( .A0(n2603), .A1(n3099), .B0(n2964), .B1(n2611), .Y(
add_subt_module_Oper_Start_in_module_intm[56]) );
AOI22X1TS U3937 ( .A0(n2603), .A1(n3092), .B0(n3028), .B1(n2611), .Y(
add_subt_module_Oper_Start_in_module_intm[57]) );
AOI22X1TS U3938 ( .A0(n2603), .A1(n3097), .B0(n3148), .B1(n2611), .Y(
add_subt_module_Oper_Start_in_module_intm[58]) );
AOI22X1TS U3939 ( .A0(n2603), .A1(n3110), .B0(n2973), .B1(n2615), .Y(
add_subt_module_Oper_Start_in_module_intm[59]) );
AOI22X1TS U3940 ( .A0(n2603), .A1(n3095), .B0(n3018), .B1(n2615), .Y(
add_subt_module_Oper_Start_in_module_intm[60]) );
INVX4TS U3941 ( .A(n2612), .Y(n2605) );
AOI22X1TS U3942 ( .A0(n2605), .A1(n3131), .B0(n2965), .B1(n2615), .Y(
add_subt_module_Oper_Start_in_module_intm[61]) );
AOI22X1TS U3943 ( .A0(n2605), .A1(n3119), .B0(n2966), .B1(n2615), .Y(
add_subt_module_Oper_Start_in_module_intm[62]) );
AOI22X1TS U3944 ( .A0(n2605), .A1(n2983), .B0(n3050), .B1(n2615), .Y(
add_subt_module_Oper_Start_in_module_intM[0]) );
AOI22X1TS U3945 ( .A0(n2605), .A1(n3029), .B0(n3132), .B1(n2615), .Y(
add_subt_module_Oper_Start_in_module_intM[1]) );
AOI22X1TS U3946 ( .A0(n2605), .A1(n2981), .B0(n3126), .B1(n2615), .Y(
add_subt_module_Oper_Start_in_module_intM[2]) );
AOI22X1TS U3947 ( .A0(n2605), .A1(n3031), .B0(n3066), .B1(n2615), .Y(
add_subt_module_Oper_Start_in_module_intM[3]) );
AOI22X1TS U3948 ( .A0(n2605), .A1(n3039), .B0(n2992), .B1(n2615), .Y(
add_subt_module_Oper_Start_in_module_intM[4]) );
AOI22X1TS U3949 ( .A0(n2605), .A1(n2969), .B0(n3129), .B1(n2602), .Y(
add_subt_module_Oper_Start_in_module_intM[5]) );
AOI22X1TS U3950 ( .A0(n2605), .A1(n3008), .B0(n2991), .B1(n2602), .Y(
add_subt_module_Oper_Start_in_module_intM[6]) );
AOI22X1TS U3951 ( .A0(n2605), .A1(n2967), .B0(n3127), .B1(n2602), .Y(
add_subt_module_Oper_Start_in_module_intM[7]) );
AOI22X1TS U3952 ( .A0(n2605), .A1(n3020), .B0(n3089), .B1(n2602), .Y(
add_subt_module_Oper_Start_in_module_intM[8]) );
AOI22X1TS U3953 ( .A0(n2605), .A1(n2959), .B0(n3118), .B1(n2602), .Y(
add_subt_module_Oper_Start_in_module_intM[9]) );
AOI22X1TS U3954 ( .A0(n2605), .A1(n2958), .B0(n3128), .B1(n2602), .Y(
add_subt_module_Oper_Start_in_module_intM[10]) );
BUFX3TS U3955 ( .A(n2612), .Y(n2614) );
AOI22X1TS U3956 ( .A0(n2616), .A1(n3147), .B0(n3098), .B1(n2602), .Y(
add_subt_module_Oper_Start_in_module_intM[11]) );
AOI22X1TS U3957 ( .A0(n2610), .A1(n3009), .B0(n3088), .B1(n2602), .Y(
add_subt_module_Oper_Start_in_module_intM[12]) );
AOI22X1TS U3958 ( .A0(n2616), .A1(n3004), .B0(n3073), .B1(n2602), .Y(
add_subt_module_Oper_Start_in_module_intM[13]) );
AOI22X1TS U3959 ( .A0(n2610), .A1(n3040), .B0(n3122), .B1(n2602), .Y(
add_subt_module_Oper_Start_in_module_intM[14]) );
AOI22X1TS U3960 ( .A0(n2616), .A1(n2978), .B0(n3074), .B1(n2609), .Y(
add_subt_module_Oper_Start_in_module_intM[15]) );
AOI22X1TS U3961 ( .A0(n2610), .A1(n3041), .B0(n3114), .B1(n2609), .Y(
add_subt_module_Oper_Start_in_module_intM[16]) );
AOI22X1TS U3962 ( .A0(n2616), .A1(n3032), .B0(n3106), .B1(n2609), .Y(
add_subt_module_Oper_Start_in_module_intM[17]) );
AOI22X1TS U3963 ( .A0(n2603), .A1(n3037), .B0(n3107), .B1(n2609), .Y(
add_subt_module_Oper_Start_in_module_intM[18]) );
AOI22X1TS U3964 ( .A0(n2604), .A1(n2979), .B0(n3121), .B1(n2609), .Y(
add_subt_module_Oper_Start_in_module_intM[19]) );
AOI22X1TS U3965 ( .A0(n2605), .A1(n3042), .B0(n3104), .B1(n2609), .Y(
add_subt_module_Oper_Start_in_module_intM[20]) );
AOI22X1TS U3966 ( .A0(n2603), .A1(n3034), .B0(n3075), .B1(n2609), .Y(
add_subt_module_Oper_Start_in_module_intM[21]) );
AOI22X1TS U3967 ( .A0(n2604), .A1(n2982), .B0(n3123), .B1(n2609), .Y(
add_subt_module_Oper_Start_in_module_intM[22]) );
AOI22X1TS U3968 ( .A0(n2605), .A1(n3133), .B0(n3011), .B1(n2609), .Y(
add_subt_module_Oper_Start_in_module_intM[23]) );
AOI22X1TS U3969 ( .A0(n2610), .A1(n2980), .B0(n3108), .B1(n2609), .Y(
add_subt_module_Oper_Start_in_module_intM[24]) );
AOI22X1TS U3970 ( .A0(n2616), .A1(n3038), .B0(n3113), .B1(n2601), .Y(
add_subt_module_Oper_Start_in_module_intM[25]) );
AOI22X1TS U3971 ( .A0(n2610), .A1(n3033), .B0(n3101), .B1(n2601), .Y(
add_subt_module_Oper_Start_in_module_intM[26]) );
AOI22X1TS U3972 ( .A0(n2616), .A1(n2970), .B0(n3124), .B1(n2601), .Y(
add_subt_module_Oper_Start_in_module_intM[27]) );
AOI22X1TS U3973 ( .A0(n2610), .A1(n3035), .B0(n3100), .B1(n2601), .Y(
add_subt_module_Oper_Start_in_module_intM[28]) );
AOI22X1TS U3974 ( .A0(n2616), .A1(n3012), .B0(n3076), .B1(n2601), .Y(
add_subt_module_Oper_Start_in_module_intM[29]) );
AOI22X1TS U3975 ( .A0(n2606), .A1(n3036), .B0(n3120), .B1(n2601), .Y(
add_subt_module_Oper_Start_in_module_intM[30]) );
AOI22X1TS U3976 ( .A0(n2607), .A1(n2976), .B0(n3069), .B1(n2601), .Y(
add_subt_module_Oper_Start_in_module_intM[31]) );
AOI22X1TS U3977 ( .A0(n2606), .A1(n2960), .B0(n3115), .B1(n2601), .Y(
add_subt_module_Oper_Start_in_module_intM[32]) );
AOI22X1TS U3978 ( .A0(n2607), .A1(n3021), .B0(n3068), .B1(n2601), .Y(
add_subt_module_Oper_Start_in_module_intM[33]) );
AOI22X1TS U3979 ( .A0(n2606), .A1(n2961), .B0(n3111), .B1(n2601), .Y(
add_subt_module_Oper_Start_in_module_intM[34]) );
AOI22X1TS U3980 ( .A0(n2610), .A1(n3022), .B0(n3070), .B1(n2614), .Y(
add_subt_module_Oper_Start_in_module_intM[35]) );
AOI22X1TS U3981 ( .A0(n2607), .A1(n3016), .B0(n3093), .B1(n2612), .Y(
add_subt_module_Oper_Start_in_module_intM[36]) );
AOI22X1TS U3982 ( .A0(n2610), .A1(n3010), .B0(n3130), .B1(n2612), .Y(
add_subt_module_Oper_Start_in_module_intM[37]) );
AOI22X1TS U3983 ( .A0(n2610), .A1(n2962), .B0(n3134), .B1(n2613), .Y(
add_subt_module_Oper_Start_in_module_intM[38]) );
AOI22X1TS U3984 ( .A0(n2610), .A1(n2977), .B0(n3117), .B1(n2613), .Y(
add_subt_module_Oper_Start_in_module_intM[39]) );
AOI22X1TS U3985 ( .A0(n2610), .A1(n2952), .B0(n3116), .B1(n2613), .Y(
add_subt_module_Oper_Start_in_module_intM[40]) );
AOI22X1TS U3986 ( .A0(n2610), .A1(n3030), .B0(n3072), .B1(n2612), .Y(
add_subt_module_Oper_Start_in_module_intM[41]) );
AOI22X1TS U3987 ( .A0(n2610), .A1(n2975), .B0(n3112), .B1(n2613), .Y(
add_subt_module_Oper_Start_in_module_intM[42]) );
AOI22X1TS U3988 ( .A0(n2610), .A1(n3023), .B0(n3071), .B1(n2608), .Y(
add_subt_module_Oper_Start_in_module_intM[43]) );
AOI22X1TS U3989 ( .A0(n2610), .A1(n3005), .B0(n3102), .B1(n2614), .Y(
add_subt_module_Oper_Start_in_module_intM[44]) );
AOI22X1TS U3990 ( .A0(n2610), .A1(n3024), .B0(n3090), .B1(n2609), .Y(
add_subt_module_Oper_Start_in_module_intM[45]) );
AOI22X1TS U3991 ( .A0(n2610), .A1(n3019), .B0(n3087), .B1(n2612), .Y(
add_subt_module_Oper_Start_in_module_intM[46]) );
AOI22X1TS U3992 ( .A0(n2610), .A1(n2968), .B0(n3125), .B1(n2613), .Y(
add_subt_module_Oper_Start_in_module_intM[47]) );
AOI22X1TS U3993 ( .A0(n2610), .A1(n3006), .B0(n3103), .B1(n2615), .Y(
add_subt_module_Oper_Start_in_module_intM[48]) );
AOI22X1TS U3994 ( .A0(n2610), .A1(n3025), .B0(n3091), .B1(n2611), .Y(
add_subt_module_Oper_Start_in_module_intM[49]) );
AOI22X1TS U3995 ( .A0(n2616), .A1(n3017), .B0(n3096), .B1(n2613), .Y(
add_subt_module_Oper_Start_in_module_intM[50]) );
AOI22X1TS U3996 ( .A0(n2616), .A1(n2974), .B0(n3109), .B1(n2613), .Y(
add_subt_module_Oper_Start_in_module_intM[51]) );
AOI22X1TS U3997 ( .A0(n2616), .A1(n3007), .B0(n3105), .B1(n2611), .Y(
add_subt_module_Oper_Start_in_module_intM[52]) );
AOI22X1TS U3998 ( .A0(n2616), .A1(n3026), .B0(n3065), .B1(n2612), .Y(
add_subt_module_Oper_Start_in_module_intM[53]) );
AOI22X1TS U3999 ( .A0(n2616), .A1(n2963), .B0(n3094), .B1(n2613), .Y(
add_subt_module_Oper_Start_in_module_intM[54]) );
AOI22X1TS U4000 ( .A0(n2616), .A1(n3027), .B0(n3067), .B1(n2614), .Y(
add_subt_module_Oper_Start_in_module_intM[55]) );
AOI22X1TS U4001 ( .A0(n2616), .A1(n2964), .B0(n3099), .B1(n2614), .Y(
add_subt_module_Oper_Start_in_module_intM[56]) );
AOI22X1TS U4002 ( .A0(n2616), .A1(n3028), .B0(n3092), .B1(n2614), .Y(
add_subt_module_Oper_Start_in_module_intM[57]) );
AOI22X1TS U4003 ( .A0(n2616), .A1(n3148), .B0(n3097), .B1(n2614), .Y(
add_subt_module_Oper_Start_in_module_intM[58]) );
AOI22X1TS U4004 ( .A0(n2616), .A1(n2973), .B0(n3110), .B1(n2614), .Y(
add_subt_module_Oper_Start_in_module_intM[59]) );
AOI22X1TS U4005 ( .A0(n2616), .A1(n3018), .B0(n3095), .B1(n2614), .Y(
add_subt_module_Oper_Start_in_module_intM[60]) );
AOI22X1TS U4006 ( .A0(n2616), .A1(n2965), .B0(n3131), .B1(n2614), .Y(
add_subt_module_Oper_Start_in_module_intM[61]) );
AOI22X1TS U4007 ( .A0(n2616), .A1(n2966), .B0(n3119), .B1(n2615), .Y(
add_subt_module_Oper_Start_in_module_intM[62]) );
AOI2BB2XLTS U4008 ( .B0(n2781), .B1(n1309), .A0N(n2617), .A1N(n2781), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[54]) );
AOI22X1TS U4009 ( .A0(n1298), .A1(n2619), .B0(n2788), .B1(n2618), .Y(n2620)
);
OAI221XLTS U4010 ( .A0(n2652), .A1(n2622), .B0(n1300), .B1(n2621), .C0(n2620), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]) );
AOI22X1TS U4011 ( .A0(n1298), .A1(n2625), .B0(n2624), .B1(n2623), .Y(n2626)
);
OAI221XLTS U4012 ( .A0(n2634), .A1(n2628), .B0(n1300), .B1(n2627), .C0(n2626), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]) );
AOI22X1TS U4013 ( .A0(n2793), .A1(n2630), .B0(n2772), .B1(n2629), .Y(n2631)
);
OAI221XLTS U4014 ( .A0(n2634), .A1(n2633), .B0(n1300), .B1(n2632), .C0(n2631), .Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[33]) );
AOI22X1TS U4015 ( .A0(n1298), .A1(n2635), .B0(n2785), .B1(n2669), .Y(n2642)
);
AOI22X1TS U4016 ( .A0(n2791), .A1(n2657), .B0(n2781), .B1(n2675), .Y(n2641)
);
AOI22X1TS U4017 ( .A0(n2788), .A1(n2663), .B0(n2746), .B1(n2636), .Y(n2640)
);
NAND2X1TS U4018 ( .A(n2638), .B(n2637), .Y(n2639) );
NAND4XLTS U4019 ( .A(n2642), .B(n2641), .C(n2640), .D(n2639), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[22]) );
AOI22X1TS U4020 ( .A0(n2767), .A1(n2675), .B0(n1369), .B1(n2643), .Y(n2644)
);
OAI31X1TS U4021 ( .A0(n2652), .A1(n2651), .A2(n2645), .B0(n2644), .Y(n2648)
);
AOI22X1TS U4022 ( .A0(n2772), .A1(n2663), .B0(n2781), .B1(n2681), .Y(n2647)
);
AOI22X1TS U4023 ( .A0(n2788), .A1(n2669), .B0(n1371), .B1(n2657), .Y(n2646)
);
NAND3BXLTS U4024 ( .AN(n2648), .B(n2647), .C(n2646), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[21]) );
AOI22X1TS U4025 ( .A0(n2788), .A1(n2675), .B0(n2781), .B1(n2687), .Y(n2649)
);
OAI31X1TS U4026 ( .A0(n2652), .A1(n2651), .A2(n2650), .B0(n2649), .Y(n2655)
);
AOI22X1TS U4027 ( .A0(n1371), .A1(n2663), .B0(n2783), .B1(n2657), .Y(n2654)
);
AOI22X1TS U4028 ( .A0(n2791), .A1(n2669), .B0(n2785), .B1(n2681), .Y(n2653)
);
NAND3BXLTS U4029 ( .AN(n2655), .B(n2654), .C(n2653), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[20]) );
AOI22X1TS U4030 ( .A0(n1371), .A1(n2675), .B0(n2783), .B1(n2669), .Y(n2661)
);
AOI22X1TS U4031 ( .A0(n2768), .A1(n2663), .B0(n2785), .B1(n2694), .Y(n2660)
);
AOI22X1TS U4032 ( .A0(n2718), .A1(add_subt_module_Add_Subt_result[36]), .B0(
add_subt_module_DmP[16]), .B1(n2758), .Y(n2656) );
OAI2BB1X2TS U4033 ( .A0N(add_subt_module_Add_Subt_result[18]), .A1N(n2769),
.B0(n2656), .Y(n2700) );
AOI22X1TS U4034 ( .A0(n2788), .A1(n2687), .B0(n2781), .B1(n2700), .Y(n2659)
);
AOI22X1TS U4035 ( .A0(n2793), .A1(n2657), .B0(n2791), .B1(n2681), .Y(n2658)
);
NAND4XLTS U4036 ( .A(n2661), .B(n2660), .C(n2659), .D(n2658), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[18]) );
AOI22X1TS U4037 ( .A0(n1371), .A1(n2681), .B0(n2783), .B1(n2675), .Y(n2667)
);
AOI22X1TS U4038 ( .A0(n2768), .A1(n2669), .B0(n2785), .B1(n2700), .Y(n2666)
);
AOI22X1TS U4039 ( .A0(n2718), .A1(add_subt_module_Add_Subt_result[37]), .B0(
add_subt_module_DmP[15]), .B1(n2758), .Y(n2662) );
OAI2BB1X2TS U4040 ( .A0N(add_subt_module_Add_Subt_result[17]), .A1N(n2769),
.B0(n2662), .Y(n2706) );
AOI22X1TS U4041 ( .A0(n2788), .A1(n2694), .B0(n2781), .B1(n2706), .Y(n2665)
);
AOI22X1TS U4042 ( .A0(n2793), .A1(n2663), .B0(n2732), .B1(n2687), .Y(n2664)
);
NAND4XLTS U4043 ( .A(n2667), .B(n2666), .C(n2665), .D(n2664), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[17]) );
AOI22X1TS U4044 ( .A0(n1371), .A1(n2687), .B0(n2783), .B1(n2681), .Y(n2673)
);
AOI22X1TS U4045 ( .A0(n2768), .A1(n2675), .B0(n2785), .B1(n2706), .Y(n2672)
);
AOI22X1TS U4046 ( .A0(n2718), .A1(add_subt_module_Add_Subt_result[38]), .B0(
add_subt_module_DmP[14]), .B1(n2758), .Y(n2668) );
OAI2BB1X2TS U4047 ( .A0N(add_subt_module_Add_Subt_result[16]), .A1N(n2769),
.B0(n2668), .Y(n2713) );
AOI22X1TS U4048 ( .A0(n2788), .A1(n2700), .B0(n2781), .B1(n2713), .Y(n2671)
);
AOI22X1TS U4049 ( .A0(n2793), .A1(n2669), .B0(n2772), .B1(n2694), .Y(n2670)
);
NAND4XLTS U4050 ( .A(n2673), .B(n2672), .C(n2671), .D(n2670), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[16]) );
AOI22X1TS U4051 ( .A0(n1371), .A1(n2694), .B0(n2783), .B1(n2687), .Y(n2679)
);
AOI22X1TS U4052 ( .A0(n1298), .A1(n2681), .B0(n2785), .B1(n2713), .Y(n2678)
);
AOI22X1TS U4053 ( .A0(n2718), .A1(add_subt_module_Add_Subt_result[39]), .B0(
add_subt_module_DmP[13]), .B1(n2758), .Y(n2674) );
OAI2BB1X2TS U4054 ( .A0N(add_subt_module_Add_Subt_result[15]), .A1N(n2769),
.B0(n2674), .Y(n2720) );
AOI22X1TS U4055 ( .A0(n2788), .A1(n2706), .B0(n2781), .B1(n2720), .Y(n2677)
);
AOI22X1TS U4056 ( .A0(n2793), .A1(n2675), .B0(n2732), .B1(n2700), .Y(n2676)
);
NAND4XLTS U4057 ( .A(n2679), .B(n2678), .C(n2677), .D(n2676), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[15]) );
AOI22X1TS U4058 ( .A0(n1371), .A1(n2700), .B0(n2783), .B1(n2694), .Y(n2685)
);
AOI22X1TS U4059 ( .A0(n1298), .A1(n2687), .B0(n2785), .B1(n2720), .Y(n2684)
);
AOI22X1TS U4060 ( .A0(n2718), .A1(add_subt_module_Add_Subt_result[40]), .B0(
add_subt_module_DmP[12]), .B1(n2758), .Y(n2680) );
OAI2BB1X2TS U4061 ( .A0N(add_subt_module_Add_Subt_result[14]), .A1N(n2779),
.B0(n2680), .Y(n2726) );
AOI22X1TS U4062 ( .A0(n2788), .A1(n2713), .B0(n2781), .B1(n2726), .Y(n2683)
);
AOI22X1TS U4063 ( .A0(n2793), .A1(n2681), .B0(n2732), .B1(n2706), .Y(n2682)
);
NAND4XLTS U4064 ( .A(n2685), .B(n2684), .C(n2683), .D(n2682), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[14]) );
AOI22X1TS U4065 ( .A0(n1370), .A1(n2706), .B0(n1369), .B1(n2700), .Y(n2691)
);
AOI22X1TS U4066 ( .A0(n1298), .A1(n2694), .B0(n2785), .B1(n2726), .Y(n2690)
);
AOI22X1TS U4067 ( .A0(n2718), .A1(add_subt_module_Add_Subt_result[41]), .B0(
add_subt_module_DmP[11]), .B1(n2758), .Y(n2686) );
OAI2BB1X2TS U4068 ( .A0N(add_subt_module_Add_Subt_result[13]), .A1N(n2769),
.B0(n2686), .Y(n2733) );
AOI22X1TS U4069 ( .A0(n2771), .A1(n2720), .B0(n2781), .B1(n2733), .Y(n2689)
);
AOI22X1TS U4070 ( .A0(n2746), .A1(n2687), .B0(n2732), .B1(n2713), .Y(n2688)
);
NAND4XLTS U4071 ( .A(n2691), .B(n2690), .C(n2689), .D(n2688), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[13]) );
AOI22X1TS U4072 ( .A0(n1371), .A1(n2713), .B0(n1369), .B1(n2706), .Y(n2698)
);
AOI22X1TS U4073 ( .A0(n2768), .A1(n2700), .B0(n2785), .B1(n2733), .Y(n2697)
);
AOI22X1TS U4074 ( .A0(n2718), .A1(add_subt_module_Add_Subt_result[42]), .B0(
add_subt_module_DmP[10]), .B1(n2692), .Y(n2693) );
OAI2BB1X2TS U4075 ( .A0N(add_subt_module_Add_Subt_result[12]), .A1N(n2769),
.B0(n2693), .Y(n2739) );
AOI22X1TS U4076 ( .A0(n2771), .A1(n2726), .B0(n2781), .B1(n2739), .Y(n2696)
);
AOI22X1TS U4077 ( .A0(n2746), .A1(n2694), .B0(n2791), .B1(n2720), .Y(n2695)
);
NAND4XLTS U4078 ( .A(n2698), .B(n2697), .C(n2696), .D(n2695), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[12]) );
AOI22X1TS U4079 ( .A0(n1370), .A1(n2720), .B0(n1369), .B1(n2713), .Y(n2704)
);
AOI22X1TS U4080 ( .A0(n2768), .A1(n2706), .B0(n2785), .B1(n2739), .Y(n2703)
);
AOI22X1TS U4081 ( .A0(n2718), .A1(add_subt_module_Add_Subt_result[43]), .B0(
add_subt_module_DmP[9]), .B1(n2758), .Y(n2699) );
OAI2BB1X2TS U4082 ( .A0N(add_subt_module_Add_Subt_result[11]), .A1N(n2769),
.B0(n2699), .Y(n2745) );
AOI22X1TS U4083 ( .A0(n2771), .A1(n2733), .B0(n2761), .B1(n2745), .Y(n2702)
);
AOI22X1TS U4084 ( .A0(n1819), .A1(n2700), .B0(n2791), .B1(n2726), .Y(n2701)
);
NAND4XLTS U4085 ( .A(n2704), .B(n2703), .C(n2702), .D(n2701), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[11]) );
AOI22X1TS U4086 ( .A0(n1370), .A1(n2726), .B0(n1369), .B1(n2720), .Y(n2710)
);
AOI22X1TS U4087 ( .A0(n2768), .A1(n2713), .B0(n2767), .B1(n2745), .Y(n2709)
);
AOI22X1TS U4088 ( .A0(n2718), .A1(add_subt_module_Add_Subt_result[44]), .B0(
add_subt_module_DmP[8]), .B1(n2758), .Y(n2705) );
OAI2BB1X2TS U4089 ( .A0N(add_subt_module_Add_Subt_result[10]), .A1N(n2752),
.B0(n2705), .Y(n2753) );
AOI22X1TS U4090 ( .A0(n2771), .A1(n2739), .B0(n2761), .B1(n2753), .Y(n2708)
);
AOI22X1TS U4091 ( .A0(n1819), .A1(n2706), .B0(n2732), .B1(n2733), .Y(n2707)
);
NAND4XLTS U4092 ( .A(n2710), .B(n2709), .C(n2708), .D(n2707), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[10]) );
AOI22X1TS U4093 ( .A0(n1371), .A1(n2733), .B0(n2783), .B1(n2726), .Y(n2717)
);
AOI22X1TS U4094 ( .A0(n2768), .A1(n2720), .B0(n2767), .B1(n2753), .Y(n2716)
);
AOI22X1TS U4095 ( .A0(n2718), .A1(add_subt_module_Add_Subt_result[45]), .B0(
add_subt_module_DmP[7]), .B1(n2758), .Y(n2711) );
OAI21X4TS U4096 ( .A0(n3060), .A1(n1766), .B0(n2711), .Y(n2762) );
AOI22X1TS U4097 ( .A0(n2771), .A1(n2745), .B0(n2761), .B1(n2762), .Y(n2715)
);
AOI22X1TS U4098 ( .A0(n1819), .A1(n2713), .B0(n2772), .B1(n2739), .Y(n2714)
);
NAND4XLTS U4099 ( .A(n2717), .B(n2716), .C(n2715), .D(n2714), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[9]) );
AOI22X1TS U4100 ( .A0(n1370), .A1(n2739), .B0(n1369), .B1(n2733), .Y(n2724)
);
AOI22X1TS U4101 ( .A0(n2768), .A1(n2726), .B0(n2767), .B1(n2762), .Y(n2723)
);
AOI22X1TS U4102 ( .A0(n2718), .A1(add_subt_module_Add_Subt_result[46]), .B0(
add_subt_module_DmP[6]), .B1(n2758), .Y(n2719) );
OAI2BB1X2TS U4103 ( .A0N(n1442), .A1N(n2752), .B0(n2719), .Y(n2773) );
AOI22X1TS U4104 ( .A0(n2771), .A1(n2753), .B0(n2761), .B1(n2773), .Y(n2722)
);
AOI22X1TS U4105 ( .A0(n1819), .A1(n2720), .B0(n2772), .B1(n2745), .Y(n2721)
);
NAND4XLTS U4106 ( .A(n2724), .B(n2723), .C(n2722), .D(n2721), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[8]) );
AOI22X1TS U4107 ( .A0(n1371), .A1(n2745), .B0(n2783), .B1(n2739), .Y(n2730)
);
AOI22X1TS U4108 ( .A0(n2768), .A1(n2733), .B0(n2767), .B1(n2773), .Y(n2729)
);
AOI22X1TS U4109 ( .A0(n2759), .A1(add_subt_module_Add_Subt_result[47]), .B0(
add_subt_module_DmP[5]), .B1(n2758), .Y(n2725) );
OAI2BB1X2TS U4110 ( .A0N(add_subt_module_Add_Subt_result[7]), .A1N(n2779),
.B0(n2725), .Y(n2792) );
AOI22X1TS U4111 ( .A0(n2771), .A1(n2762), .B0(n2761), .B1(n2792), .Y(n2728)
);
AOI22X1TS U4112 ( .A0(n1819), .A1(n2726), .B0(n2791), .B1(n2753), .Y(n2727)
);
NAND4XLTS U4113 ( .A(n2730), .B(n2729), .C(n2728), .D(n2727), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[7]) );
AOI22X1TS U4114 ( .A0(n1370), .A1(n2753), .B0(n1369), .B1(n2745), .Y(n2737)
);
AOI22X1TS U4115 ( .A0(n2768), .A1(n2739), .B0(n2767), .B1(n2792), .Y(n2736)
);
AOI22X1TS U4116 ( .A0(n2759), .A1(add_subt_module_Add_Subt_result[48]), .B0(
add_subt_module_DmP[4]), .B1(n2758), .Y(n2731) );
OAI2BB1X2TS U4117 ( .A0N(add_subt_module_Add_Subt_result[6]), .A1N(n2752),
.B0(n2731), .Y(n2789) );
AOI22X1TS U4118 ( .A0(n2771), .A1(n2773), .B0(n2761), .B1(n2789), .Y(n2735)
);
AOI22X1TS U4119 ( .A0(n2793), .A1(n2733), .B0(n2732), .B1(n2762), .Y(n2734)
);
NAND4XLTS U4120 ( .A(n2737), .B(n2736), .C(n2735), .D(n2734), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[6]) );
AOI22X1TS U4121 ( .A0(n1371), .A1(n2762), .B0(n2783), .B1(n2753), .Y(n2743)
);
AOI22X1TS U4122 ( .A0(n2768), .A1(n2745), .B0(n2767), .B1(n2789), .Y(n2742)
);
AOI22X1TS U4123 ( .A0(n2759), .A1(add_subt_module_Add_Subt_result[49]), .B0(
add_subt_module_DmP[3]), .B1(n2758), .Y(n2738) );
OAI2BB1X2TS U4124 ( .A0N(add_subt_module_Add_Subt_result[5]), .A1N(n2769),
.B0(n2738), .Y(n2782) );
AOI22X1TS U4125 ( .A0(n2771), .A1(n2792), .B0(n2761), .B1(n2782), .Y(n2741)
);
AOI22X1TS U4126 ( .A0(n2746), .A1(n2739), .B0(n2772), .B1(n2773), .Y(n2740)
);
NAND4XLTS U4127 ( .A(n2743), .B(n2742), .C(n2741), .D(n2740), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[5]) );
AOI22X1TS U4128 ( .A0(n1370), .A1(n2773), .B0(n1369), .B1(n2762), .Y(n2750)
);
AOI22X1TS U4129 ( .A0(n2768), .A1(n2753), .B0(n2767), .B1(n2782), .Y(n2749)
);
AOI22X1TS U4130 ( .A0(n2759), .A1(add_subt_module_Add_Subt_result[50]), .B0(
add_subt_module_DmP[2]), .B1(n2758), .Y(n2744) );
AOI22X1TS U4131 ( .A0(n2771), .A1(n2789), .B0(n2761), .B1(n2786), .Y(n2748)
);
AOI22X1TS U4132 ( .A0(n2746), .A1(n2745), .B0(n2791), .B1(n2792), .Y(n2747)
);
NAND4XLTS U4133 ( .A(n2750), .B(n2749), .C(n2748), .D(n2747), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[4]) );
AOI22X1TS U4134 ( .A0(n1370), .A1(n2792), .B0(n1369), .B1(n2773), .Y(n2757)
);
AOI22X1TS U4135 ( .A0(n2768), .A1(n2762), .B0(n2767), .B1(n2786), .Y(n2756)
);
AOI22X1TS U4136 ( .A0(n2759), .A1(add_subt_module_Add_Subt_result[51]), .B0(
add_subt_module_DmP[1]), .B1(n2758), .Y(n2751) );
AOI22X1TS U4137 ( .A0(n2771), .A1(n2782), .B0(n2781), .B1(n2790), .Y(n2755)
);
AOI22X1TS U4138 ( .A0(n2793), .A1(n2753), .B0(n2772), .B1(n2789), .Y(n2754)
);
NAND4XLTS U4139 ( .A(n2757), .B(n2756), .C(n2755), .D(n2754), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[3]) );
AOI22X1TS U4140 ( .A0(n1371), .A1(n2789), .B0(n2783), .B1(n2792), .Y(n2766)
);
AOI22X1TS U4141 ( .A0(n2768), .A1(n2773), .B0(n2767), .B1(n2790), .Y(n2765)
);
AOI22X1TS U4142 ( .A0(n2759), .A1(add_subt_module_Add_Subt_result[52]), .B0(
add_subt_module_DmP[0]), .B1(n2758), .Y(n2760) );
OAI2BB1X1TS U4143 ( .A0N(add_subt_module_Add_Subt_result[2]), .A1N(n2779),
.B0(n2760), .Y(n2787) );
AOI22X1TS U4144 ( .A0(n2771), .A1(n2786), .B0(n2761), .B1(n2787), .Y(n2764)
);
AOI22X1TS U4145 ( .A0(n2793), .A1(n2762), .B0(n2772), .B1(n2782), .Y(n2763)
);
NAND4XLTS U4146 ( .A(n2766), .B(n2765), .C(n2764), .D(n2763), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[2]) );
AOI22X1TS U4147 ( .A0(n1371), .A1(n2782), .B0(n2783), .B1(n2789), .Y(n2777)
);
AOI22X1TS U4148 ( .A0(n2768), .A1(n2792), .B0(n2767), .B1(n2787), .Y(n2776)
);
AOI22X1TS U4149 ( .A0(n2771), .A1(n2790), .B0(n2770), .B1(n2784), .Y(n2775)
);
AOI22X1TS U4150 ( .A0(n2793), .A1(n2773), .B0(n2791), .B1(n2786), .Y(n2774)
);
NAND4XLTS U4151 ( .A(n2777), .B(n2776), .C(n2775), .D(n2774), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[1]) );
AO22XLTS U4152 ( .A0(n2779), .A1(n1405), .B0(n2582), .B1(
add_subt_module_Add_Subt_result[54]), .Y(n2780) );
AOI22X1TS U4153 ( .A0(n1369), .A1(n2782), .B0(n2781), .B1(n2780), .Y(n2797)
);
AOI22X1TS U4154 ( .A0(n1370), .A1(n2786), .B0(n2785), .B1(n2784), .Y(n2796)
);
AOI22X1TS U4155 ( .A0(n1298), .A1(n2789), .B0(n2788), .B1(n2787), .Y(n2795)
);
AOI22X1TS U4156 ( .A0(n2793), .A1(n2792), .B0(n2772), .B1(n2790), .Y(n2794)
);
NAND4XLTS U4157 ( .A(n2797), .B(n2796), .C(n2795), .D(n2794), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[0]) );
INVX2TS U4158 ( .A(n2798), .Y(n2799) );
NAND2X1TS U4159 ( .A(n3056), .B(add_subt_module_Add_Subt_result[35]), .Y(
n2802) );
OAI22X1TS U4160 ( .A0(n2803), .A1(n2802), .B0(n2801), .B1(n3063), .Y(n2811)
);
NAND2X1TS U4161 ( .A(n3057), .B(add_subt_module_Add_Subt_result[45]), .Y(
n2807) );
AOI21X1TS U4162 ( .A0(n2805), .A1(n3058), .B0(
add_subt_module_Add_Subt_result[53]), .Y(n2806) );
OAI22X1TS U4163 ( .A0(n2808), .A1(n2807), .B0(
add_subt_module_Add_Subt_result[54]), .B1(n2806), .Y(n2809) );
AOI21X1TS U4164 ( .A0(n2811), .A1(n2810), .B0(n2809), .Y(n2812) );
OAI21XLTS U4165 ( .A0(n2813), .A1(add_subt_module_Add_Subt_result[34]), .B0(
n2812), .Y(n2819) );
NAND3XLTS U4166 ( .A(n2814), .B(add_subt_module_Add_Subt_result[17]), .C(
n3083), .Y(n2817) );
OR3X1TS U4167 ( .A(n2815), .B(add_subt_module_Add_Subt_result[32]), .C(n3064), .Y(n2816) );
NAND4BXLTS U4168 ( .AN(n2819), .B(n2818), .C(n2817), .D(n2816), .Y(n2820) );
NOR2BX1TS U4169 ( .AN(n2821), .B(n2820), .Y(n2822) );
CLKAND2X2TS U4170 ( .A(n2828), .B(add_subt_module_Sgf_normalized_result[2]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[0]) );
CLKAND2X2TS U4171 ( .A(n2827), .B(add_subt_module_Sgf_normalized_result[3]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[1]) );
CLKAND2X2TS U4172 ( .A(n2827), .B(add_subt_module_Sgf_normalized_result[4]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[2]) );
CLKAND2X2TS U4173 ( .A(n2827), .B(add_subt_module_Sgf_normalized_result[5]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[3]) );
CLKAND2X2TS U4174 ( .A(n2827), .B(add_subt_module_Sgf_normalized_result[6]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[4]) );
BUFX4TS U4175 ( .A(n2827), .Y(n2826) );
CLKAND2X2TS U4176 ( .A(n2826), .B(add_subt_module_Sgf_normalized_result[7]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[5]) );
CLKAND2X2TS U4177 ( .A(n2826), .B(add_subt_module_Sgf_normalized_result[8]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[6]) );
CLKAND2X2TS U4178 ( .A(n2826), .B(add_subt_module_Sgf_normalized_result[9]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[7]) );
CLKAND2X2TS U4179 ( .A(n2826), .B(add_subt_module_Sgf_normalized_result[10]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[8]) );
CLKAND2X2TS U4180 ( .A(n2826), .B(add_subt_module_Sgf_normalized_result[11]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[9]) );
CLKAND2X2TS U4181 ( .A(n2826), .B(add_subt_module_Sgf_normalized_result[12]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[10]) );
CLKAND2X2TS U4182 ( .A(n2826), .B(add_subt_module_Sgf_normalized_result[13]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[11]) );
CLKAND2X2TS U4183 ( .A(n2826), .B(add_subt_module_Sgf_normalized_result[14]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[12]) );
CLKAND2X2TS U4184 ( .A(n2826), .B(add_subt_module_Sgf_normalized_result[15]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[13]) );
CLKAND2X2TS U4185 ( .A(n2826), .B(n1415), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[14]) );
CLKAND2X2TS U4186 ( .A(n2826), .B(n1425), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[15]) );
CLKAND2X2TS U4187 ( .A(n2826), .B(n1414), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[16]) );
CLKAND2X2TS U4188 ( .A(n2826), .B(n1421), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[17]) );
CLKAND2X2TS U4189 ( .A(n2826), .B(n1410), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[18]) );
CLKAND2X2TS U4190 ( .A(n2826), .B(n1423), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[19]) );
CLKAND2X2TS U4191 ( .A(n2826), .B(n1417), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[20]) );
CLKAND2X2TS U4192 ( .A(n2826), .B(n1409), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[21]) );
CLKAND2X2TS U4193 ( .A(n2826), .B(n1412), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[22]) );
CLKAND2X2TS U4194 ( .A(n2826), .B(n1413), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[23]) );
CLKAND2X2TS U4195 ( .A(n2826), .B(n1420), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[24]) );
BUFX4TS U4196 ( .A(n2827), .Y(n2829) );
CLKAND2X2TS U4197 ( .A(n2829), .B(n1416), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[25]) );
CLKAND2X2TS U4198 ( .A(n2829), .B(n1422), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[26]) );
CLKAND2X2TS U4199 ( .A(n2829), .B(n1419), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[27]) );
CLKAND2X2TS U4200 ( .A(n2829), .B(n1411), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[28]) );
CLKAND2X2TS U4201 ( .A(n2829), .B(n1408), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[29]) );
CLKAND2X2TS U4202 ( .A(n2829), .B(n1429), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[30]) );
CLKAND2X2TS U4203 ( .A(n2829), .B(n1401), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[31]) );
CLKAND2X2TS U4204 ( .A(n2829), .B(n1426), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[32]) );
CLKAND2X2TS U4205 ( .A(n2829), .B(n1403), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[33]) );
CLKAND2X2TS U4206 ( .A(n2829), .B(n1424), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[34]) );
CLKAND2X2TS U4207 ( .A(n2829), .B(n1404), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[35]) );
CLKAND2X2TS U4208 ( .A(n2829), .B(n1418), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[36]) );
CLKAND2X2TS U4209 ( .A(n2829), .B(n1428), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[37]) );
CLKAND2X2TS U4210 ( .A(n2829), .B(n1402), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[38]) );
CLKAND2X2TS U4211 ( .A(n2829), .B(n1427), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[39]) );
CLKAND2X2TS U4212 ( .A(n2829), .B(add_subt_module_Sgf_normalized_result[42]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[40]) );
CLKAND2X2TS U4213 ( .A(n2829), .B(add_subt_module_Sgf_normalized_result[43]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[41]) );
CLKAND2X2TS U4214 ( .A(n2829), .B(add_subt_module_Sgf_normalized_result[44]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[42]) );
CLKAND2X2TS U4215 ( .A(n2829), .B(add_subt_module_Sgf_normalized_result[45]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[43]) );
CLKAND2X2TS U4216 ( .A(n2828), .B(add_subt_module_Sgf_normalized_result[46]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[44]) );
CLKAND2X2TS U4217 ( .A(n2828), .B(add_subt_module_Sgf_normalized_result[47]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[45]) );
CLKAND2X2TS U4218 ( .A(n2828), .B(add_subt_module_Sgf_normalized_result[48]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[46]) );
CLKAND2X2TS U4219 ( .A(n2828), .B(add_subt_module_Sgf_normalized_result[49]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[47]) );
CLKAND2X2TS U4220 ( .A(n2828), .B(add_subt_module_Sgf_normalized_result[50]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[48]) );
CLKAND2X2TS U4221 ( .A(n2828), .B(add_subt_module_Sgf_normalized_result[51]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[49]) );
CLKAND2X2TS U4222 ( .A(n2828), .B(add_subt_module_Sgf_normalized_result[52]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[50]) );
CLKAND2X2TS U4223 ( .A(n2829), .B(n1407), .Y(
add_subt_module_final_result_ieee_Module_Sgf_S_mux[51]) );
CLKAND2X2TS U4224 ( .A(d_ff_Yn[0]), .B(n2882), .Y(first_mux_Y[0]) );
CLKAND2X2TS U4225 ( .A(d_ff_Yn[1]), .B(sel_mux_1_reg), .Y(first_mux_Y[1]) );
INVX3TS U4226 ( .A(n2841), .Y(n2880) );
CLKAND2X2TS U4227 ( .A(d_ff_Yn[2]), .B(n2882), .Y(first_mux_Y[2]) );
CLKAND2X2TS U4228 ( .A(d_ff_Yn[3]), .B(n2883), .Y(first_mux_Y[3]) );
INVX3TS U4229 ( .A(n2841), .Y(n2881) );
CLKAND2X2TS U4230 ( .A(d_ff_Yn[4]), .B(n2883), .Y(first_mux_Y[4]) );
CLKAND2X2TS U4231 ( .A(d_ff_Yn[5]), .B(n2881), .Y(first_mux_Y[5]) );
INVX3TS U4232 ( .A(n2841), .Y(n2882) );
CLKAND2X2TS U4233 ( .A(d_ff_Yn[6]), .B(n2881), .Y(first_mux_Y[6]) );
CLKAND2X2TS U4234 ( .A(d_ff_Yn[7]), .B(n2880), .Y(first_mux_Y[7]) );
CLKAND2X2TS U4235 ( .A(d_ff_Yn[8]), .B(n2880), .Y(first_mux_Y[8]) );
CLKAND2X2TS U4236 ( .A(d_ff_Yn[9]), .B(n2882), .Y(first_mux_Y[9]) );
CLKAND2X2TS U4237 ( .A(d_ff_Yn[10]), .B(n2881), .Y(first_mux_Y[10]) );
CLKAND2X2TS U4238 ( .A(d_ff_Yn[11]), .B(n1376), .Y(first_mux_Y[11]) );
INVX4TS U4239 ( .A(n2832), .Y(n2830) );
CLKAND2X2TS U4240 ( .A(d_ff_Yn[12]), .B(n2830), .Y(first_mux_Y[12]) );
CLKAND2X2TS U4241 ( .A(d_ff_Yn[13]), .B(n2834), .Y(first_mux_Y[13]) );
CLKAND2X2TS U4242 ( .A(d_ff_Yn[14]), .B(n2837), .Y(first_mux_Y[14]) );
CLKAND2X2TS U4243 ( .A(d_ff_Yn[15]), .B(n2836), .Y(first_mux_Y[15]) );
CLKAND2X2TS U4244 ( .A(d_ff_Yn[16]), .B(n2830), .Y(first_mux_Y[16]) );
CLKAND2X2TS U4245 ( .A(d_ff_Yn[17]), .B(n2834), .Y(first_mux_Y[17]) );
CLKAND2X2TS U4246 ( .A(d_ff_Yn[18]), .B(n2837), .Y(first_mux_Y[18]) );
CLKAND2X2TS U4247 ( .A(d_ff_Yn[19]), .B(n2836), .Y(first_mux_Y[19]) );
CLKAND2X2TS U4248 ( .A(d_ff_Yn[20]), .B(n2830), .Y(first_mux_Y[20]) );
CLKAND2X2TS U4249 ( .A(d_ff_Yn[21]), .B(n2834), .Y(first_mux_Y[21]) );
CLKAND2X2TS U4250 ( .A(d_ff_Yn[22]), .B(n2837), .Y(first_mux_Y[22]) );
CLKAND2X2TS U4251 ( .A(d_ff_Yn[23]), .B(n2836), .Y(first_mux_Y[23]) );
CLKAND2X2TS U4252 ( .A(d_ff_Yn[24]), .B(n2830), .Y(first_mux_Y[24]) );
CLKAND2X2TS U4253 ( .A(d_ff_Yn[25]), .B(sel_mux_1_reg), .Y(first_mux_Y[25])
);
CLKAND2X2TS U4254 ( .A(d_ff_Yn[26]), .B(sel_mux_1_reg), .Y(first_mux_Y[26])
);
CLKAND2X2TS U4255 ( .A(d_ff_Yn[27]), .B(sel_mux_1_reg), .Y(first_mux_Y[27])
);
CLKAND2X2TS U4256 ( .A(d_ff_Yn[28]), .B(sel_mux_1_reg), .Y(first_mux_Y[28])
);
CLKAND2X2TS U4257 ( .A(d_ff_Yn[29]), .B(sel_mux_1_reg), .Y(first_mux_Y[29])
);
CLKAND2X2TS U4258 ( .A(d_ff_Yn[30]), .B(sel_mux_1_reg), .Y(first_mux_Y[30])
);
CLKAND2X2TS U4259 ( .A(d_ff_Yn[31]), .B(sel_mux_1_reg), .Y(first_mux_Y[31])
);
CLKAND2X2TS U4260 ( .A(d_ff_Yn[32]), .B(sel_mux_1_reg), .Y(first_mux_Y[32])
);
CLKAND2X2TS U4261 ( .A(d_ff_Yn[33]), .B(sel_mux_1_reg), .Y(first_mux_Y[33])
);
CLKAND2X2TS U4262 ( .A(d_ff_Yn[34]), .B(sel_mux_1_reg), .Y(first_mux_Y[34])
);
CLKAND2X2TS U4263 ( .A(d_ff_Yn[35]), .B(sel_mux_1_reg), .Y(first_mux_Y[35])
);
CLKAND2X2TS U4264 ( .A(d_ff_Yn[36]), .B(sel_mux_1_reg), .Y(first_mux_Y[36])
);
CLKAND2X2TS U4265 ( .A(d_ff_Yn[37]), .B(n2834), .Y(first_mux_Y[37]) );
CLKAND2X2TS U4266 ( .A(d_ff_Yn[38]), .B(n2830), .Y(first_mux_Y[38]) );
CLKAND2X2TS U4267 ( .A(d_ff_Yn[39]), .B(n2830), .Y(first_mux_Y[39]) );
CLKAND2X2TS U4268 ( .A(d_ff_Yn[40]), .B(n2837), .Y(first_mux_Y[40]) );
CLKAND2X2TS U4269 ( .A(d_ff_Yn[41]), .B(n2837), .Y(first_mux_Y[41]) );
CLKAND2X2TS U4270 ( .A(d_ff_Yn[42]), .B(n2834), .Y(first_mux_Y[42]) );
CLKAND2X2TS U4271 ( .A(d_ff_Yn[43]), .B(n2834), .Y(first_mux_Y[43]) );
CLKAND2X2TS U4272 ( .A(d_ff_Yn[44]), .B(n2836), .Y(first_mux_Y[44]) );
CLKAND2X2TS U4273 ( .A(d_ff_Yn[45]), .B(n2836), .Y(first_mux_Y[45]) );
CLKAND2X2TS U4274 ( .A(d_ff_Yn[46]), .B(n2830), .Y(first_mux_Y[46]) );
CLKAND2X2TS U4275 ( .A(d_ff_Yn[47]), .B(n2834), .Y(first_mux_Y[47]) );
CLKAND2X2TS U4276 ( .A(d_ff_Yn[48]), .B(n2837), .Y(first_mux_Y[48]) );
CLKAND2X2TS U4277 ( .A(d_ff_Yn[49]), .B(n2836), .Y(first_mux_Y[49]) );
CLKAND2X2TS U4278 ( .A(d_ff_Yn[50]), .B(sel_mux_1_reg), .Y(first_mux_Y[50])
);
CLKAND2X2TS U4279 ( .A(d_ff_Yn[51]), .B(sel_mux_1_reg), .Y(first_mux_Y[51])
);
CLKAND2X2TS U4280 ( .A(d_ff_Yn[52]), .B(sel_mux_1_reg), .Y(first_mux_Y[52])
);
CLKAND2X2TS U4281 ( .A(d_ff_Yn[53]), .B(sel_mux_1_reg), .Y(first_mux_Y[53])
);
CLKAND2X2TS U4282 ( .A(d_ff_Yn[54]), .B(sel_mux_1_reg), .Y(first_mux_Y[54])
);
CLKAND2X2TS U4283 ( .A(d_ff_Yn[55]), .B(sel_mux_1_reg), .Y(first_mux_Y[55])
);
CLKAND2X2TS U4284 ( .A(d_ff_Yn[56]), .B(sel_mux_1_reg), .Y(first_mux_Y[56])
);
CLKAND2X2TS U4285 ( .A(d_ff_Yn[57]), .B(sel_mux_1_reg), .Y(first_mux_Y[57])
);
CLKAND2X2TS U4286 ( .A(d_ff_Yn[58]), .B(sel_mux_1_reg), .Y(first_mux_Y[58])
);
CLKAND2X2TS U4287 ( .A(d_ff_Yn[59]), .B(sel_mux_1_reg), .Y(first_mux_Y[59])
);
CLKAND2X2TS U4288 ( .A(d_ff_Yn[60]), .B(sel_mux_1_reg), .Y(first_mux_Y[60])
);
CLKAND2X2TS U4289 ( .A(d_ff_Yn[61]), .B(sel_mux_1_reg), .Y(first_mux_Y[61])
);
CLKAND2X2TS U4290 ( .A(d_ff_Yn[62]), .B(sel_mux_1_reg), .Y(first_mux_Y[62])
);
CLKAND2X2TS U4291 ( .A(d_ff_Yn[63]), .B(sel_mux_1_reg), .Y(first_mux_Y[63])
);
AO22XLTS U4292 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[0]), .B0(n2832), .B1(
d_ff1_Z[0]), .Y(first_mux_Z[0]) );
BUFX4TS U4293 ( .A(n2833), .Y(n2835) );
AO22XLTS U4294 ( .A0(n2836), .A1(d_ff_Zn[6]), .B0(n2835), .B1(d_ff1_Z[6]),
.Y(first_mux_Z[6]) );
AO22XLTS U4295 ( .A0(n2830), .A1(d_ff_Zn[7]), .B0(n2835), .B1(d_ff1_Z[7]),
.Y(first_mux_Z[7]) );
AO22XLTS U4296 ( .A0(n2834), .A1(d_ff_Zn[8]), .B0(n2835), .B1(d_ff1_Z[8]),
.Y(first_mux_Z[8]) );
AO22XLTS U4297 ( .A0(n2837), .A1(d_ff_Zn[9]), .B0(n2835), .B1(d_ff1_Z[9]),
.Y(first_mux_Z[9]) );
AO22XLTS U4298 ( .A0(n2836), .A1(d_ff_Zn[10]), .B0(n2835), .B1(d_ff1_Z[10]),
.Y(first_mux_Z[10]) );
AO22XLTS U4299 ( .A0(n2830), .A1(d_ff_Zn[11]), .B0(n2835), .B1(d_ff1_Z[11]),
.Y(first_mux_Z[11]) );
AO22XLTS U4300 ( .A0(n2834), .A1(d_ff_Zn[12]), .B0(n2835), .B1(d_ff1_Z[12]),
.Y(first_mux_Z[12]) );
AO22XLTS U4301 ( .A0(n2837), .A1(d_ff_Zn[13]), .B0(n2835), .B1(d_ff1_Z[13]),
.Y(first_mux_Z[13]) );
AO22XLTS U4302 ( .A0(n2836), .A1(d_ff_Zn[14]), .B0(n2835), .B1(d_ff1_Z[14]),
.Y(first_mux_Z[14]) );
AO22XLTS U4303 ( .A0(n2836), .A1(d_ff_Zn[15]), .B0(n2835), .B1(d_ff1_Z[15]),
.Y(first_mux_Z[15]) );
AO22XLTS U4304 ( .A0(n2830), .A1(d_ff_Zn[16]), .B0(n2835), .B1(d_ff1_Z[16]),
.Y(first_mux_Z[16]) );
AO22XLTS U4305 ( .A0(n2834), .A1(d_ff_Zn[17]), .B0(n2835), .B1(d_ff1_Z[17]),
.Y(first_mux_Z[17]) );
AO22XLTS U4306 ( .A0(n2837), .A1(d_ff_Zn[20]), .B0(n2835), .B1(d_ff1_Z[20]),
.Y(first_mux_Z[20]) );
AO22XLTS U4307 ( .A0(n2836), .A1(d_ff_Zn[21]), .B0(n2835), .B1(d_ff1_Z[21]),
.Y(first_mux_Z[21]) );
AO22XLTS U4308 ( .A0(n2830), .A1(d_ff_Zn[22]), .B0(n2835), .B1(d_ff1_Z[22]),
.Y(first_mux_Z[22]) );
AO22XLTS U4309 ( .A0(n2834), .A1(d_ff_Zn[23]), .B0(n2835), .B1(d_ff1_Z[23]),
.Y(first_mux_Z[23]) );
AO22XLTS U4310 ( .A0(n2837), .A1(d_ff_Zn[24]), .B0(n2835), .B1(d_ff1_Z[24]),
.Y(first_mux_Z[24]) );
AO22XLTS U4311 ( .A0(n2836), .A1(d_ff_Zn[25]), .B0(n2835), .B1(d_ff1_Z[25]),
.Y(first_mux_Z[25]) );
AO22XLTS U4312 ( .A0(n2830), .A1(d_ff_Zn[26]), .B0(n2835), .B1(d_ff1_Z[26]),
.Y(first_mux_Z[26]) );
AO22XLTS U4313 ( .A0(n2834), .A1(d_ff_Zn[27]), .B0(n2835), .B1(d_ff1_Z[27]),
.Y(first_mux_Z[27]) );
AO22XLTS U4314 ( .A0(n2836), .A1(d_ff_Zn[38]), .B0(n2840), .B1(d_ff1_Z[38]),
.Y(first_mux_Z[38]) );
AO22XLTS U4315 ( .A0(n2830), .A1(d_ff_Zn[39]), .B0(n2840), .B1(d_ff1_Z[39]),
.Y(first_mux_Z[39]) );
AO22XLTS U4316 ( .A0(n2834), .A1(d_ff_Zn[40]), .B0(n2840), .B1(d_ff1_Z[40]),
.Y(first_mux_Z[40]) );
AO22XLTS U4317 ( .A0(n2837), .A1(d_ff_Zn[41]), .B0(n2840), .B1(d_ff1_Z[41]),
.Y(first_mux_Z[41]) );
AO22XLTS U4318 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[42]), .B0(n2840), .B1(
d_ff1_Z[42]), .Y(first_mux_Z[42]) );
AO22XLTS U4319 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[43]), .B0(n2840), .B1(
d_ff1_Z[43]), .Y(first_mux_Z[43]) );
AO22XLTS U4320 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[45]), .B0(n2840), .B1(
d_ff1_Z[45]), .Y(first_mux_Z[45]) );
AO22XLTS U4321 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[46]), .B0(n2840), .B1(
d_ff1_Z[46]), .Y(first_mux_Z[46]) );
AO22XLTS U4322 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[47]), .B0(n3140), .B1(
d_ff1_Z[47]), .Y(first_mux_Z[47]) );
AO22XLTS U4323 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[48]), .B0(n2840), .B1(
d_ff1_Z[48]), .Y(first_mux_Z[48]) );
AO22XLTS U4324 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[49]), .B0(n3140), .B1(
d_ff1_Z[49]), .Y(first_mux_Z[49]) );
AO22XLTS U4325 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[50]), .B0(n2840), .B1(
d_ff1_Z[50]), .Y(first_mux_Z[50]) );
AO22XLTS U4326 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[51]), .B0(n2840), .B1(
d_ff1_Z[51]), .Y(first_mux_Z[51]) );
AO22XLTS U4327 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[52]), .B0(n2840), .B1(
d_ff1_Z[52]), .Y(first_mux_Z[52]) );
AO22XLTS U4328 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[53]), .B0(n2840), .B1(
d_ff1_Z[53]), .Y(first_mux_Z[53]) );
AO22XLTS U4329 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[54]), .B0(n2840), .B1(
d_ff1_Z[54]), .Y(first_mux_Z[54]) );
AO22XLTS U4330 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[55]), .B0(n2840), .B1(
d_ff1_Z[55]), .Y(first_mux_Z[55]) );
AO22XLTS U4331 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[56]), .B0(n2840), .B1(
d_ff1_Z[56]), .Y(first_mux_Z[56]) );
AO22XLTS U4332 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[57]), .B0(n2840), .B1(
d_ff1_Z[57]), .Y(first_mux_Z[57]) );
AO22XLTS U4333 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[58]), .B0(n2840), .B1(
d_ff1_Z[58]), .Y(first_mux_Z[58]) );
AO22XLTS U4334 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[59]), .B0(n2840), .B1(
d_ff1_Z[59]), .Y(first_mux_Z[59]) );
AO22XLTS U4335 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[60]), .B0(n2841), .B1(
d_ff1_Z[60]), .Y(first_mux_Z[60]) );
AO22XLTS U4336 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[61]), .B0(n2841), .B1(
d_ff1_Z[61]), .Y(first_mux_Z[61]) );
AO22XLTS U4337 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[62]), .B0(n3140), .B1(
d_ff1_Z[62]), .Y(first_mux_Z[62]) );
AO22XLTS U4338 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[63]), .B0(n3140), .B1(
d_ff1_Z[63]), .Y(first_mux_Z[63]) );
INVX4TS U4339 ( .A(n3136), .Y(n2848) );
AO22XLTS U4340 ( .A0(n2848), .A1(d_ff_Yn[0]), .B0(n3136), .B1(d_ff_Xn[0]),
.Y(mux_sal[0]) );
BUFX3TS U4341 ( .A(n3136), .Y(n2844) );
AO22XLTS U4342 ( .A0(n2848), .A1(d_ff_Yn[1]), .B0(n2844), .B1(d_ff_Xn[1]),
.Y(mux_sal[1]) );
AO22XLTS U4343 ( .A0(n2848), .A1(d_ff_Yn[2]), .B0(n2844), .B1(d_ff_Xn[2]),
.Y(mux_sal[2]) );
AO22XLTS U4344 ( .A0(n2848), .A1(d_ff_Yn[3]), .B0(n2844), .B1(d_ff_Xn[3]),
.Y(mux_sal[3]) );
AO22XLTS U4345 ( .A0(n2848), .A1(d_ff_Yn[4]), .B0(n2844), .B1(d_ff_Xn[4]),
.Y(mux_sal[4]) );
AO22XLTS U4346 ( .A0(n2848), .A1(d_ff_Yn[5]), .B0(n2844), .B1(d_ff_Xn[5]),
.Y(mux_sal[5]) );
AO22XLTS U4347 ( .A0(n2848), .A1(d_ff_Yn[6]), .B0(n2844), .B1(d_ff_Xn[6]),
.Y(mux_sal[6]) );
AO22XLTS U4348 ( .A0(n2848), .A1(d_ff_Yn[7]), .B0(n2844), .B1(d_ff_Xn[7]),
.Y(mux_sal[7]) );
AO22XLTS U4349 ( .A0(n2848), .A1(d_ff_Yn[8]), .B0(n2844), .B1(d_ff_Xn[8]),
.Y(mux_sal[8]) );
BUFX3TS U4350 ( .A(n3136), .Y(n2843) );
AO22XLTS U4351 ( .A0(n2848), .A1(d_ff_Yn[9]), .B0(n2843), .B1(d_ff_Xn[9]),
.Y(mux_sal[9]) );
AO22XLTS U4352 ( .A0(n2848), .A1(d_ff_Yn[10]), .B0(n2843), .B1(d_ff_Xn[10]),
.Y(mux_sal[10]) );
AO22XLTS U4353 ( .A0(n2848), .A1(d_ff_Yn[11]), .B0(n2843), .B1(d_ff_Xn[11]),
.Y(mux_sal[11]) );
INVX4TS U4354 ( .A(n3136), .Y(n2850) );
AO22XLTS U4355 ( .A0(n2850), .A1(d_ff_Yn[12]), .B0(n2843), .B1(d_ff_Xn[12]),
.Y(mux_sal[12]) );
AO22XLTS U4356 ( .A0(n2848), .A1(d_ff_Yn[13]), .B0(n2843), .B1(d_ff_Xn[13]),
.Y(mux_sal[13]) );
AO22XLTS U4357 ( .A0(n2850), .A1(d_ff_Yn[14]), .B0(n2843), .B1(d_ff_Xn[14]),
.Y(mux_sal[14]) );
INVX4TS U4358 ( .A(n3136), .Y(n2846) );
AO22XLTS U4359 ( .A0(n2846), .A1(d_ff_Yn[15]), .B0(n2843), .B1(d_ff_Xn[15]),
.Y(mux_sal[15]) );
AO22XLTS U4360 ( .A0(n2848), .A1(d_ff_Yn[16]), .B0(n2843), .B1(d_ff_Xn[16]),
.Y(mux_sal[16]) );
AO22XLTS U4361 ( .A0(n2850), .A1(d_ff_Yn[17]), .B0(n2843), .B1(d_ff_Xn[17]),
.Y(mux_sal[17]) );
AO22XLTS U4362 ( .A0(n2846), .A1(d_ff_Yn[18]), .B0(n2843), .B1(d_ff_Xn[18]),
.Y(mux_sal[18]) );
AO22XLTS U4363 ( .A0(n2846), .A1(d_ff_Yn[19]), .B0(n2843), .B1(d_ff_Xn[19]),
.Y(mux_sal[19]) );
BUFX3TS U4364 ( .A(n3136), .Y(n2845) );
AO22XLTS U4365 ( .A0(n2848), .A1(d_ff_Yn[20]), .B0(n2845), .B1(d_ff_Xn[20]),
.Y(mux_sal[20]) );
AO22XLTS U4366 ( .A0(n2850), .A1(d_ff_Yn[21]), .B0(n2843), .B1(d_ff_Xn[21]),
.Y(mux_sal[21]) );
AO22XLTS U4367 ( .A0(n2846), .A1(d_ff_Yn[22]), .B0(n2844), .B1(d_ff_Xn[22]),
.Y(mux_sal[22]) );
AO22XLTS U4368 ( .A0(n2846), .A1(d_ff_Yn[23]), .B0(n2849), .B1(d_ff_Xn[23]),
.Y(mux_sal[23]) );
AO22XLTS U4369 ( .A0(n2846), .A1(d_ff_Yn[24]), .B0(n2844), .B1(d_ff_Xn[24]),
.Y(mux_sal[24]) );
AO22XLTS U4370 ( .A0(n2846), .A1(d_ff_Yn[25]), .B0(n2845), .B1(d_ff_Xn[25]),
.Y(mux_sal[25]) );
AO22XLTS U4371 ( .A0(n2846), .A1(d_ff_Yn[26]), .B0(n2849), .B1(d_ff_Xn[26]),
.Y(mux_sal[26]) );
AO22XLTS U4372 ( .A0(n2846), .A1(d_ff_Yn[27]), .B0(n2843), .B1(d_ff_Xn[27]),
.Y(mux_sal[27]) );
AO22XLTS U4373 ( .A0(n2846), .A1(d_ff_Yn[28]), .B0(n2845), .B1(d_ff_Xn[28]),
.Y(mux_sal[28]) );
AO22XLTS U4374 ( .A0(n2846), .A1(d_ff_Yn[29]), .B0(n2843), .B1(d_ff_Xn[29]),
.Y(mux_sal[29]) );
AO22XLTS U4375 ( .A0(n2846), .A1(d_ff_Yn[30]), .B0(n2844), .B1(d_ff_Xn[30]),
.Y(mux_sal[30]) );
AO22XLTS U4376 ( .A0(n2846), .A1(d_ff_Yn[31]), .B0(n3136), .B1(d_ff_Xn[31]),
.Y(mux_sal[31]) );
AO22XLTS U4377 ( .A0(n2846), .A1(d_ff_Yn[32]), .B0(n3136), .B1(d_ff_Xn[32]),
.Y(mux_sal[32]) );
AO22XLTS U4378 ( .A0(n2846), .A1(d_ff_Yn[33]), .B0(n2844), .B1(d_ff_Xn[33]),
.Y(mux_sal[33]) );
AO22XLTS U4379 ( .A0(n2846), .A1(d_ff_Yn[34]), .B0(n3136), .B1(d_ff_Xn[34]),
.Y(mux_sal[34]) );
AO22XLTS U4380 ( .A0(n2846), .A1(d_ff_Yn[35]), .B0(n3136), .B1(d_ff_Xn[35]),
.Y(mux_sal[35]) );
AO22XLTS U4381 ( .A0(n2850), .A1(d_ff_Yn[36]), .B0(n3136), .B1(d_ff_Xn[36]),
.Y(mux_sal[36]) );
AO22XLTS U4382 ( .A0(n2850), .A1(d_ff_Yn[37]), .B0(n2844), .B1(d_ff_Xn[37]),
.Y(mux_sal[37]) );
AO22XLTS U4383 ( .A0(n2850), .A1(d_ff_Yn[38]), .B0(n2844), .B1(d_ff_Xn[38]),
.Y(mux_sal[38]) );
AO22XLTS U4384 ( .A0(n2850), .A1(d_ff_Yn[39]), .B0(n3136), .B1(d_ff_Xn[39]),
.Y(mux_sal[39]) );
AO22XLTS U4385 ( .A0(n2850), .A1(d_ff_Yn[40]), .B0(n2849), .B1(d_ff_Xn[40]),
.Y(mux_sal[40]) );
AO22XLTS U4386 ( .A0(n2850), .A1(d_ff_Yn[41]), .B0(n2845), .B1(d_ff_Xn[41]),
.Y(mux_sal[41]) );
AO22XLTS U4387 ( .A0(n2850), .A1(d_ff_Yn[42]), .B0(n2845), .B1(d_ff_Xn[42]),
.Y(mux_sal[42]) );
AO22XLTS U4388 ( .A0(n2850), .A1(d_ff_Yn[43]), .B0(n2845), .B1(d_ff_Xn[43]),
.Y(mux_sal[43]) );
AO22XLTS U4389 ( .A0(n2850), .A1(d_ff_Yn[44]), .B0(n2845), .B1(d_ff_Xn[44]),
.Y(mux_sal[44]) );
AO22XLTS U4390 ( .A0(n2850), .A1(d_ff_Yn[45]), .B0(n2845), .B1(d_ff_Xn[45]),
.Y(mux_sal[45]) );
AO22XLTS U4391 ( .A0(n2850), .A1(d_ff_Yn[46]), .B0(n2845), .B1(d_ff_Xn[46]),
.Y(mux_sal[46]) );
AO22XLTS U4392 ( .A0(n2850), .A1(d_ff_Yn[47]), .B0(n2845), .B1(d_ff_Xn[47]),
.Y(mux_sal[47]) );
AO22XLTS U4393 ( .A0(n2848), .A1(d_ff_Yn[48]), .B0(n3136), .B1(d_ff_Xn[48]),
.Y(mux_sal[48]) );
AO22XLTS U4394 ( .A0(n2850), .A1(d_ff_Yn[49]), .B0(n2845), .B1(d_ff_Xn[49]),
.Y(mux_sal[49]) );
AO22XLTS U4395 ( .A0(n2953), .A1(d_ff_Yn[50]), .B0(n2845), .B1(d_ff_Xn[50]),
.Y(mux_sal[50]) );
AO22XLTS U4396 ( .A0(n2953), .A1(d_ff_Yn[51]), .B0(n2845), .B1(d_ff_Xn[51]),
.Y(mux_sal[51]) );
AO22XLTS U4397 ( .A0(n2953), .A1(d_ff_Yn[52]), .B0(n2849), .B1(d_ff_Xn[52]),
.Y(mux_sal[52]) );
AO22XLTS U4398 ( .A0(n2953), .A1(d_ff_Yn[53]), .B0(n2849), .B1(d_ff_Xn[53]),
.Y(mux_sal[53]) );
AO22XLTS U4399 ( .A0(n2953), .A1(d_ff_Yn[54]), .B0(n2845), .B1(d_ff_Xn[54]),
.Y(mux_sal[54]) );
AO22XLTS U4400 ( .A0(n2953), .A1(d_ff_Yn[55]), .B0(n2849), .B1(d_ff_Xn[55]),
.Y(mux_sal[55]) );
AO22XLTS U4401 ( .A0(n2953), .A1(d_ff_Yn[56]), .B0(n2849), .B1(d_ff_Xn[56]),
.Y(mux_sal[56]) );
AO22XLTS U4402 ( .A0(n2953), .A1(d_ff_Yn[57]), .B0(n2849), .B1(d_ff_Xn[57]),
.Y(mux_sal[57]) );
AO22XLTS U4403 ( .A0(n2953), .A1(d_ff_Yn[58]), .B0(n2849), .B1(d_ff_Xn[58]),
.Y(mux_sal[58]) );
AO22XLTS U4404 ( .A0(n2953), .A1(d_ff_Yn[59]), .B0(n2849), .B1(d_ff_Xn[59]),
.Y(mux_sal[59]) );
AO22XLTS U4405 ( .A0(n2846), .A1(d_ff_Yn[60]), .B0(n2849), .B1(d_ff_Xn[60]),
.Y(mux_sal[60]) );
AO22XLTS U4406 ( .A0(n2848), .A1(d_ff_Yn[61]), .B0(n2849), .B1(d_ff_Xn[61]),
.Y(mux_sal[61]) );
AO22XLTS U4407 ( .A0(n2848), .A1(d_ff_Yn[62]), .B0(n3136), .B1(d_ff_Xn[62]),
.Y(mux_sal[62]) );
AO22XLTS U4408 ( .A0(n2850), .A1(d_ff_Yn[63]), .B0(n2849), .B1(d_ff_Xn[63]),
.Y(mux_sal[63]) );
XNOR2X1TS U4409 ( .A(data_output2_63_), .B(n2852), .Y(sign_inv_out[63]) );
NAND4XLTS U4410 ( .A(n2858), .B(n2863), .C(n2853), .D(data_out_LUT[40]), .Y(
data_out_LUT[1]) );
INVX2TS U4411 ( .A(n2871), .Y(n2856) );
NAND2X1TS U4412 ( .A(n2854), .B(n2856), .Y(data_out_LUT[2]) );
NAND2X1TS U4413 ( .A(cont_iter_out[2]), .B(cont_iter_out[3]), .Y(n2869) );
NAND4XLTS U4414 ( .A(n2863), .B(n1618), .C(data_out_LUT[40]), .D(n2869), .Y(
data_out_LUT[6]) );
NAND3X1TS U4415 ( .A(n3146), .B(cont_iter_out[3]), .C(n2855), .Y(n2862) );
OA21XLTS U4416 ( .A0(n2856), .A1(n2957), .B0(n2862), .Y(n2878) );
NAND4XLTS U4417 ( .A(n2858), .B(n2878), .C(n1618), .D(n2874), .Y(
data_out_LUT[7]) );
INVX2TS U4418 ( .A(data_out_LUT[22]), .Y(n2868) );
NAND2X1TS U4419 ( .A(n2863), .B(n2868), .Y(data_out_LUT[8]) );
NAND4XLTS U4420 ( .A(n2863), .B(n2859), .C(n2867), .D(n2857), .Y(
data_out_LUT[11]) );
NAND4XLTS U4421 ( .A(n2879), .B(n2858), .C(n2862), .D(n2870), .Y(
data_out_LUT[13]) );
OA21XLTS U4422 ( .A0(n2859), .A1(n2957), .B0(n2867), .Y(n2860) );
NAND4XLTS U4423 ( .A(n2860), .B(n1618), .C(n2874), .D(data_out_LUT[40]), .Y(
data_out_LUT[15]) );
NAND4XLTS U4424 ( .A(n2863), .B(data_out_LUT[50]), .C(n2862), .D(n2861), .Y(
data_out_LUT[35]) );
NAND2BXLTS U4425 ( .AN(data_out_LUT[35]), .B(n1618), .Y(data_out_LUT[18]) );
NAND2X1TS U4426 ( .A(n2865), .B(n2864), .Y(data_out_LUT[19]) );
NAND2X1TS U4427 ( .A(n2866), .B(data_out_LUT[22]), .Y(data_out_LUT[21]) );
NAND3XLTS U4428 ( .A(n2868), .B(n2874), .C(n2867), .Y(data_out_LUT[26]) );
NAND2X1TS U4429 ( .A(n2873), .B(data_out_LUT[47]), .Y(data_out_LUT[30]) );
NAND4XLTS U4430 ( .A(n1618), .B(n2874), .C(n2870), .D(n2869), .Y(
data_out_LUT[29]) );
AO21XLTS U4431 ( .A0(n3146), .A1(n2871), .B0(data_out_LUT[29]), .Y(
data_out_LUT[31]) );
NAND2X1TS U4432 ( .A(cont_iter_out[2]), .B(n2957), .Y(data_out_LUT[37]) );
NAND3XLTS U4433 ( .A(n2957), .B(data_out_LUT[50]), .C(n2872), .Y(
data_out_LUT[39]) );
NAND2X1TS U4434 ( .A(n2873), .B(n1618), .Y(data_out_LUT[41]) );
NAND2BXLTS U4435 ( .AN(data_out_LUT[12]), .B(n1618), .Y(data_out_LUT[24]) );
NAND3XLTS U4436 ( .A(n2879), .B(n2875), .C(n1618), .Y(data_out_LUT[55]) );
OAI21XLTS U4437 ( .A0(n2876), .A1(n2957), .B0(n3247), .Y(n2877) );
NAND3XLTS U4438 ( .A(n2879), .B(n2878), .C(n2877), .Y(data_out_LUT[3]) );
NAND2BXLTS U4439 ( .AN(d_ff_Xn[0]), .B(n1376), .Y(first_mux_X[0]) );
CLKAND2X2TS U4440 ( .A(d_ff_Xn[1]), .B(n2880), .Y(first_mux_X[1]) );
CLKAND2X2TS U4441 ( .A(d_ff_Xn[2]), .B(n2883), .Y(first_mux_X[2]) );
NAND2BXLTS U4442 ( .AN(d_ff_Xn[3]), .B(n2883), .Y(first_mux_X[3]) );
CLKAND2X2TS U4443 ( .A(d_ff_Xn[4]), .B(n2882), .Y(first_mux_X[4]) );
CLKAND2X2TS U4444 ( .A(d_ff_Xn[5]), .B(n2882), .Y(first_mux_X[5]) );
NAND2BXLTS U4445 ( .AN(d_ff_Xn[6]), .B(n1376), .Y(first_mux_X[6]) );
NAND2BXLTS U4446 ( .AN(d_ff_Xn[7]), .B(n2883), .Y(first_mux_X[7]) );
NAND2BXLTS U4447 ( .AN(d_ff_Xn[8]), .B(n1376), .Y(first_mux_X[8]) );
NAND2BXLTS U4448 ( .AN(d_ff_Xn[9]), .B(n2883), .Y(first_mux_X[9]) );
CLKAND2X2TS U4449 ( .A(d_ff_Xn[10]), .B(n2881), .Y(first_mux_X[10]) );
NAND2BXLTS U4450 ( .AN(d_ff_Xn[11]), .B(n1376), .Y(first_mux_X[11]) );
CLKAND2X2TS U4451 ( .A(d_ff_Xn[12]), .B(n1376), .Y(first_mux_X[12]) );
NAND2BXLTS U4452 ( .AN(d_ff_Xn[13]), .B(n1376), .Y(first_mux_X[13]) );
NAND2BXLTS U4453 ( .AN(d_ff_Xn[14]), .B(n2883), .Y(first_mux_X[14]) );
CLKAND2X2TS U4454 ( .A(d_ff_Xn[15]), .B(n2883), .Y(first_mux_X[15]) );
CLKAND2X2TS U4455 ( .A(d_ff_Xn[16]), .B(n2880), .Y(first_mux_X[16]) );
CLKAND2X2TS U4456 ( .A(d_ff_Xn[17]), .B(n2881), .Y(first_mux_X[17]) );
CLKAND2X2TS U4457 ( .A(d_ff_Xn[18]), .B(n2883), .Y(first_mux_X[18]) );
NAND2BXLTS U4458 ( .AN(d_ff_Xn[19]), .B(n1376), .Y(first_mux_X[19]) );
CLKAND2X2TS U4459 ( .A(d_ff_Xn[20]), .B(n2880), .Y(first_mux_X[20]) );
CLKAND2X2TS U4460 ( .A(d_ff_Xn[21]), .B(n2881), .Y(first_mux_X[21]) );
CLKAND2X2TS U4461 ( .A(d_ff_Xn[22]), .B(n2883), .Y(first_mux_X[22]) );
CLKAND2X2TS U4462 ( .A(d_ff_Xn[23]), .B(n2880), .Y(first_mux_X[23]) );
NAND2BXLTS U4463 ( .AN(d_ff_Xn[24]), .B(n1376), .Y(first_mux_X[24]) );
CLKAND2X2TS U4464 ( .A(d_ff_Xn[25]), .B(n2882), .Y(first_mux_X[25]) );
NAND2BXLTS U4465 ( .AN(d_ff_Xn[26]), .B(n2883), .Y(first_mux_X[26]) );
CLKAND2X2TS U4466 ( .A(d_ff_Xn[27]), .B(n2883), .Y(first_mux_X[27]) );
NAND2BXLTS U4467 ( .AN(d_ff_Xn[28]), .B(n2881), .Y(first_mux_X[28]) );
NAND2BXLTS U4468 ( .AN(d_ff_Xn[29]), .B(n2883), .Y(first_mux_X[29]) );
CLKAND2X2TS U4469 ( .A(d_ff_Xn[30]), .B(n2882), .Y(first_mux_X[30]) );
NAND2BXLTS U4470 ( .AN(d_ff_Xn[31]), .B(n2881), .Y(first_mux_X[31]) );
NAND2BXLTS U4471 ( .AN(d_ff_Xn[32]), .B(n2880), .Y(first_mux_X[32]) );
CLKAND2X2TS U4472 ( .A(d_ff_Xn[33]), .B(n2881), .Y(first_mux_X[33]) );
NAND2BXLTS U4473 ( .AN(d_ff_Xn[34]), .B(n2882), .Y(first_mux_X[34]) );
NAND2BXLTS U4474 ( .AN(d_ff_Xn[35]), .B(n1376), .Y(first_mux_X[35]) );
NAND2BXLTS U4475 ( .AN(d_ff_Xn[36]), .B(n2881), .Y(first_mux_X[36]) );
CLKAND2X2TS U4476 ( .A(d_ff_Xn[37]), .B(n2880), .Y(first_mux_X[37]) );
CLKAND2X2TS U4477 ( .A(d_ff_Xn[38]), .B(n2883), .Y(first_mux_X[38]) );
NAND2BXLTS U4478 ( .AN(d_ff_Xn[39]), .B(n2883), .Y(first_mux_X[39]) );
CLKAND2X2TS U4479 ( .A(d_ff_Xn[40]), .B(n2882), .Y(first_mux_X[40]) );
NAND2BXLTS U4480 ( .AN(d_ff_Xn[41]), .B(n2882), .Y(first_mux_X[41]) );
NAND2BXLTS U4481 ( .AN(d_ff_Xn[42]), .B(n2880), .Y(first_mux_X[42]) );
NAND2BXLTS U4482 ( .AN(d_ff_Xn[43]), .B(n2881), .Y(first_mux_X[43]) );
CLKAND2X2TS U4483 ( .A(d_ff_Xn[44]), .B(n1376), .Y(first_mux_X[44]) );
NAND2BXLTS U4484 ( .AN(d_ff_Xn[45]), .B(n2882), .Y(first_mux_X[45]) );
NAND2BXLTS U4485 ( .AN(d_ff_Xn[46]), .B(n2880), .Y(first_mux_X[46]) );
CLKAND2X2TS U4486 ( .A(d_ff_Xn[47]), .B(n2883), .Y(first_mux_X[47]) );
NAND2BXLTS U4487 ( .AN(d_ff_Xn[48]), .B(n2881), .Y(first_mux_X[48]) );
NAND2BXLTS U4488 ( .AN(d_ff_Xn[49]), .B(n1376), .Y(first_mux_X[49]) );
CLKAND2X2TS U4489 ( .A(d_ff_Xn[50]), .B(n2880), .Y(first_mux_X[50]) );
CLKAND2X2TS U4490 ( .A(d_ff_Xn[51]), .B(n2881), .Y(first_mux_X[51]) );
CLKAND2X2TS U4491 ( .A(d_ff_Xn[52]), .B(n2882), .Y(first_mux_X[52]) );
NAND2BXLTS U4492 ( .AN(d_ff_Xn[53]), .B(n1376), .Y(first_mux_X[53]) );
NAND2BXLTS U4493 ( .AN(d_ff_Xn[54]), .B(n1376), .Y(first_mux_X[54]) );
NAND2BXLTS U4494 ( .AN(d_ff_Xn[55]), .B(n1376), .Y(first_mux_X[55]) );
NAND2BXLTS U4495 ( .AN(d_ff_Xn[56]), .B(n2882), .Y(first_mux_X[56]) );
NAND2BXLTS U4496 ( .AN(d_ff_Xn[57]), .B(n2880), .Y(first_mux_X[57]) );
NAND2BXLTS U4497 ( .AN(d_ff_Xn[58]), .B(n2881), .Y(first_mux_X[58]) );
NAND2BXLTS U4498 ( .AN(d_ff_Xn[59]), .B(n1376), .Y(first_mux_X[59]) );
NAND2BXLTS U4499 ( .AN(d_ff_Xn[60]), .B(n2882), .Y(first_mux_X[60]) );
NAND2BXLTS U4500 ( .AN(d_ff_Xn[61]), .B(n2880), .Y(first_mux_X[61]) );
CLKAND2X2TS U4501 ( .A(d_ff_Xn[62]), .B(n2880), .Y(first_mux_X[62]) );
CLKAND2X2TS U4502 ( .A(d_ff_Xn[63]), .B(n1376), .Y(first_mux_X[63]) );
AO22XLTS U4503 ( .A0(n2903), .A1(d_ff3_sh_x_out[62]), .B0(n2899), .B1(
d_ff3_sh_y_out[62]), .Y(n1286) );
AOI22X1TS U4504 ( .A0(n2903), .A1(d_ff3_sh_x_out[61]), .B0(n1373), .B1(
d_ff3_sh_y_out[61]), .Y(n2884) );
NAND2X2TS U4505 ( .A(n2918), .B(d_ff3_LUT_out[48]), .Y(n2893) );
NAND2X1TS U4506 ( .A(n2884), .B(n2893), .Y(n1285) );
AOI22X1TS U4507 ( .A0(n1444), .A1(d_ff3_sh_x_out[60]), .B0(n2899), .B1(
d_ff3_sh_y_out[60]), .Y(n2886) );
NAND2X1TS U4508 ( .A(n2886), .B(n2893), .Y(n1284) );
AOI22X1TS U4509 ( .A0(n2891), .A1(d_ff3_sh_x_out[59]), .B0(n1373), .B1(
d_ff3_sh_y_out[59]), .Y(n2887) );
NAND2X1TS U4510 ( .A(n2887), .B(n2893), .Y(n1283) );
AOI22X1TS U4511 ( .A0(n2921), .A1(d_ff3_sh_x_out[58]), .B0(n2912), .B1(
d_ff3_sh_y_out[58]), .Y(n2888) );
NAND2X1TS U4512 ( .A(n2888), .B(n2893), .Y(n1282) );
AOI22X1TS U4513 ( .A0(n2903), .A1(d_ff3_sh_x_out[57]), .B0(n2055), .B1(
d_ff3_sh_y_out[57]), .Y(n2889) );
NAND2X1TS U4514 ( .A(n2889), .B(n2893), .Y(n1281) );
AOI22X1TS U4515 ( .A0(n1444), .A1(d_ff3_sh_x_out[51]), .B0(n2919), .B1(
d_ff3_sh_y_out[51]), .Y(n2890) );
NAND2X1TS U4516 ( .A(n2890), .B(n2893), .Y(n1275) );
AOI22X1TS U4517 ( .A0(n2913), .A1(d_ff3_sh_x_out[49]), .B0(n2896), .B1(
d_ff3_sh_y_out[49]), .Y(n2892) );
NAND2X1TS U4518 ( .A(n2046), .B(d_ff3_LUT_out[44]), .Y(n2900) );
NAND2X1TS U4519 ( .A(n2892), .B(n2900), .Y(n1273) );
AOI22X1TS U4520 ( .A0(n2891), .A1(d_ff3_sh_x_out[48]), .B0(n2912), .B1(
d_ff3_sh_y_out[48]), .Y(n2894) );
NAND2X1TS U4521 ( .A(n2894), .B(n2893), .Y(n1272) );
AOI22X1TS U4522 ( .A0(n2909), .A1(d_ff3_sh_x_out[47]), .B0(n2896), .B1(
d_ff3_sh_y_out[47]), .Y(n2895) );
OAI2BB1X1TS U4523 ( .A0N(n2050), .A1N(d_ff3_LUT_out[42]), .B0(n2895), .Y(
n1271) );
AOI22X1TS U4524 ( .A0(n2891), .A1(d_ff3_sh_x_out[46]), .B0(n1373), .B1(
d_ff3_sh_y_out[46]), .Y(n2898) );
NAND2X1TS U4525 ( .A(n2898), .B(n2900), .Y(n1270) );
AOI22X1TS U4526 ( .A0(n2903), .A1(d_ff3_sh_x_out[44]), .B0(n2896), .B1(
d_ff3_sh_y_out[44]), .Y(n2901) );
NAND2X1TS U4527 ( .A(n2901), .B(n2900), .Y(n1268) );
AOI22X1TS U4528 ( .A0(n2905), .A1(d_ff3_sh_x_out[43]), .B0(n1373), .B1(
d_ff3_sh_y_out[43]), .Y(n2902) );
OAI2BB1X1TS U4529 ( .A0N(n2918), .A1N(d_ff3_LUT_out[34]), .B0(n2902), .Y(
n1267) );
AOI22X1TS U4530 ( .A0(n2913), .A1(d_ff3_sh_x_out[42]), .B0(n2885), .B1(
d_ff3_sh_y_out[42]), .Y(n2904) );
OAI2BB1X1TS U4531 ( .A0N(n2046), .A1N(d_ff3_LUT_out[42]), .B0(n2904), .Y(
n1266) );
AOI22X1TS U4532 ( .A0(n2903), .A1(d_ff3_sh_x_out[40]), .B0(n2885), .B1(
d_ff3_sh_y_out[40]), .Y(n2906) );
NAND2X1TS U4533 ( .A(n1445), .B(d_ff3_LUT_out[28]), .Y(n2915) );
NAND2X1TS U4534 ( .A(n2906), .B(n2915), .Y(n1264) );
AOI22X1TS U4535 ( .A0(n2909), .A1(d_ff3_sh_x_out[38]), .B0(n2912), .B1(
d_ff3_sh_y_out[38]), .Y(n2907) );
OAI2BB1X1TS U4536 ( .A0N(n2046), .A1N(d_ff3_LUT_out[32]), .B0(n2907), .Y(
n1262) );
AOI22X1TS U4537 ( .A0(n2913), .A1(d_ff3_sh_x_out[36]), .B0(n2919), .B1(
d_ff3_sh_y_out[36]), .Y(n2908) );
NAND2X1TS U4538 ( .A(n2908), .B(n2915), .Y(n1260) );
AOI22X1TS U4539 ( .A0(n2909), .A1(d_ff3_sh_x_out[34]), .B0(n2919), .B1(
d_ff3_sh_y_out[34]), .Y(n2910) );
OAI2BB1X1TS U4540 ( .A0N(n1445), .A1N(d_ff3_LUT_out[34]), .B0(n2910), .Y(
n1258) );
AOI22X1TS U4541 ( .A0(n1444), .A1(d_ff3_sh_x_out[32]), .B0(n2885), .B1(
d_ff3_sh_y_out[32]), .Y(n2911) );
OAI2BB1X1TS U4542 ( .A0N(n2918), .A1N(d_ff3_LUT_out[32]), .B0(n2911), .Y(
n1256) );
AOI22X1TS U4543 ( .A0(n2921), .A1(d_ff3_sh_x_out[30]), .B0(n2899), .B1(
d_ff3_sh_y_out[30]), .Y(n2914) );
OAI2BB1X1TS U4544 ( .A0N(n2046), .A1N(d_ff3_LUT_out[4]), .B0(n2914), .Y(
n1254) );
AOI22X1TS U4545 ( .A0(n2897), .A1(d_ff3_sh_x_out[28]), .B0(n2885), .B1(
d_ff3_sh_y_out[28]), .Y(n2916) );
NAND2X1TS U4546 ( .A(n2916), .B(n2915), .Y(n1252) );
AOI22X1TS U4547 ( .A0(n2891), .A1(d_ff3_sh_x_out[4]), .B0(n2896), .B1(
d_ff3_sh_y_out[4]), .Y(n2917) );
OAI2BB1X1TS U4548 ( .A0N(n1445), .A1N(d_ff3_LUT_out[4]), .B0(n2917), .Y(
n1228) );
AOI22X1TS U4549 ( .A0(d_ff2_X[59]), .A1(n1373), .B0(n2050), .B1(d_ff2_Z[59]),
.Y(n2920) );
OAI2BB1X1TS U4550 ( .A0N(d_ff2_Y[59]), .A1N(n2913), .B0(n2920), .Y(n1219) );
INVX2TS U4551 ( .A(n1135), .Y(n2925) );
AOI22X1TS U4552 ( .A0(n2925), .A1(n2924), .B0(n2923), .B1(n2922), .Y(n1159)
);
NAND2X1TS U4553 ( .A(n2927), .B(n2926), .Y(
add_subt_module_FSM_barrel_shifter_load) );
OR4X2TS U4554 ( .A(add_subt_module_Exp_Operation_Module_Data_S[3]), .B(
add_subt_module_Exp_Operation_Module_Data_S[2]), .C(
add_subt_module_Exp_Operation_Module_Data_S[1]), .D(
add_subt_module_Exp_Operation_Module_Data_S[0]), .Y(n2928) );
OR4X2TS U4555 ( .A(add_subt_module_Exp_Operation_Module_Data_S[6]), .B(
add_subt_module_Exp_Operation_Module_Data_S[5]), .C(
add_subt_module_Exp_Operation_Module_Data_S[4]), .D(n2928), .Y(n2929)
);
OR4X2TS U4556 ( .A(add_subt_module_Exp_Operation_Module_Data_S[9]), .B(
add_subt_module_Exp_Operation_Module_Data_S[8]), .C(
add_subt_module_Exp_Operation_Module_Data_S[7]), .D(n2929), .Y(n2930)
);
OR3X1TS U4557 ( .A(n2931), .B(
add_subt_module_Exp_Operation_Module_Data_S[10]), .C(n2930), .Y(n2936)
);
OAI21XLTS U4558 ( .A0(n2934), .A1(n2933), .B0(n2932), .Y(n2935) );
MXI2X1TS U4559 ( .A(n3141), .B(n2936), .S0(n2935), .Y(n1151) );
XOR2XLTS U4561 ( .A(d_ff2_Y[61]), .B(n2941), .Y(sh_exp_y[9]) );
AO21XLTS U4562 ( .A0(d_ff2_Y[60]), .A1(n2937), .B0(n2941), .Y(sh_exp_y[8])
);
AO21XLTS U4563 ( .A0(d_ff2_Y[58]), .A1(n2939), .B0(n2938), .Y(sh_exp_y[6])
);
AO21XLTS U4564 ( .A0(intadd_436_n1), .A1(d_ff2_Y[56]), .B0(n2940), .Y(
sh_exp_y[4]) );
NOR2BX1TS U4565 ( .AN(n2941), .B(d_ff2_Y[61]), .Y(n2942) );
XOR2XLTS U4566 ( .A(n2942), .B(d_ff2_Y[62]), .Y(sh_exp_y[10]) );
XOR2XLTS U4567 ( .A(d_ff2_X[61]), .B(n2947), .Y(sh_exp_x[9]) );
AO21XLTS U4568 ( .A0(d_ff2_X[60]), .A1(n2943), .B0(n2947), .Y(sh_exp_x[8])
);
AO21XLTS U4569 ( .A0(d_ff2_X[58]), .A1(n2945), .B0(n2944), .Y(sh_exp_x[6])
);
AO21XLTS U4570 ( .A0(intadd_435_n1), .A1(d_ff2_X[56]), .B0(n2946), .Y(
sh_exp_x[4]) );
NOR2BX1TS U4571 ( .AN(n2947), .B(d_ff2_X[61]), .Y(n2948) );
XOR2XLTS U4572 ( .A(n2948), .B(d_ff2_X[62]), .Y(sh_exp_x[10]) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
|
//°´¼ü¼ì²âÄ£¿é ÑÓʱÏû¶¶
module Key
( input clk,
input rst,
input left,
input right,
input up,
input down,
output reg left_key_press,
output reg right_key_press,
output reg up_key_press,
output reg down_key_press
);
reg [31:0]clk_cnt;
reg left_key_last;
reg right_key_last;
reg up_key_last;
reg down_key_last;
always@(posedge clk or negedge rst) begin
if(!rst) begin
clk_cnt <= 0;
left_key_press <= 0;
right_key_press <= 0;
up_key_press <= 0;
down_key_press <= 0;
left_key_last <= 0;
right_key_last <= 0;
up_key_last <= 0;
down_key_last <= 0;
end
else begin
if(clk_cnt == 5_0000) begin
clk_cnt <= 0;
left_key_last <= left;
right_key_last <= right;
up_key_last <= up;
down_key_last <= down;
if(left_key_last == 0 && left == 1)
left_key_press <= 1;
if(right_key_last == 0 && right == 1)
right_key_press <= 1;
if(up_key_last == 0 && up == 1)
up_key_press <= 1;
if(down_key_last == 0 && down == 1)
down_key_press <= 1;
end
else begin
clk_cnt <= clk_cnt + 1;
left_key_press <= 0;
right_key_press <= 0;
up_key_press <= 0;
down_key_press <= 0;
end
end
end
endmodule |
/**
* bsg_fpu_classify.v
*
* in the spirit of RISC-V FCLASS instruction.
*
* o[0] = neg infty.
* o[1] = neg normal number
* o[2] = neg subnormal number
* o[3] = neg zero
* o[4] = pos zero
* o[5] = pos subnormal number
* o[6] = pos normal number
* o[7] = pos infty
* o[8] = sig nan
* o[9] = quite nan
*/
`include "bsg_defines.v"
module bsg_fpu_classify
#(parameter `BSG_INV_PARAM(e_p)
, parameter `BSG_INV_PARAM(m_p)
, parameter width_lp=(e_p+m_p+1)
, parameter out_width_lp=width_lp
)
(
input [width_lp-1:0] a_i
, output [out_width_lp-1:0] class_o
);
logic zero;
logic nan;
logic sig_nan;
logic infty;
logic denormal;
logic sign;
bsg_fpu_preprocess #(
.e_p(e_p)
,.m_p(m_p)
) prep (
.a_i(a_i)
,.zero_o(zero)
,.nan_o(nan)
,.sig_nan_o(sig_nan)
,.infty_o(infty)
,.exp_zero_o()
,.man_zero_o()
,.denormal_o(denormal)
,.sign_o(sign)
,.exp_o()
,.man_o()
);
assign class_o[0] = sign & infty;
assign class_o[1] = sign & (~infty) & (~denormal) & (~nan) & (~zero);
assign class_o[2] = sign & denormal;
assign class_o[3] = sign & zero;
assign class_o[4] = ~sign & zero;
assign class_o[5] = ~sign & denormal;
assign class_o[6] = ~sign & (~infty) & (~denormal) & (~nan) & (~zero);
assign class_o[7] = ~sign & infty;
assign class_o[8] = sig_nan;
assign class_o[9] = nan & ~sig_nan;
assign class_o[out_width_lp-1:10] = '0;
endmodule
`BSG_ABSTRACT_MODULE(bsg_fpu_classify)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFBBP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__SDFBBP_FUNCTIONAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr/sky130_fd_sc_hdll__udp_dff_nsr.v"
`celldefine
module sky130_fd_sc_hdll__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFBBP_FUNCTIONAL_V |
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
module op_lut_hdr_parser
#(parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter NUM_QUEUES = 8,
parameter NUM_QUEUES_WIDTH = log2(NUM_QUEUES),
parameter INPUT_ARBITER_STAGE_NUM = 2,
parameter IO_QUEUE_STAGE_NUM = `IO_QUEUE_STAGE_NUM
)
(// --- Interface to the previous stage
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
// --- Interface to process block
output is_from_cpu,
output [NUM_QUEUES-1:0] to_cpu_output_port, // where to send pkts this pkt if it has to go to the CPU
output [NUM_QUEUES-1:0] from_cpu_output_port, // where to send this pkt if it is coming from the CPU
output [NUM_QUEUES_WIDTH-1:0] input_port_num,
input rd_hdr_parser,
output is_from_cpu_vld,
// --- Misc
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//------------------ Internal Parameter ---------------------------
parameter PARSE_HDRS = 0;
parameter WAIT_EOP = 1;
//---------------------- Wires/Regs -------------------------------
reg state, state_next;
reg wr_en;
wire empty;
wire is_from_cpu_found;
wire [NUM_QUEUES-1:0] to_cpu_output_port_result;
wire [NUM_QUEUES-1:0] from_cpu_output_port_result;
wire [NUM_QUEUES-1:0] in_port_decoded;
wire [NUM_QUEUES-1:0] decoded_value[NUM_QUEUES-1:0];
wire [NUM_QUEUES_WIDTH-1:0] input_port_num_result;
//----------------------- Modules ---------------------------------
fallthrough_small_fifo #(.WIDTH(1 + 2*NUM_QUEUES + NUM_QUEUES_WIDTH), .MAX_DEPTH_BITS(2))
is_from_cpu_fifo
(.din ({is_from_cpu_found, to_cpu_output_port_result, from_cpu_output_port_result, input_port_num_result}), // Data in
.wr_en (wr_en), // Write enable
.rd_en (rd_hdr_parser), // Read the next word
.dout ({is_from_cpu, to_cpu_output_port, from_cpu_output_port, input_port_num}),
.full (),
.nearly_full (),
.prog_full (),
.empty (empty),
.reset (reset),
.clk (clk)
);
//------------------------ Logic ----------------------------------
assign is_from_cpu_vld = !empty;
/* decode the source port number */
generate
genvar i;
for(i=0; i<NUM_QUEUES; i=i+1) begin: decoder
assign decoded_value[i] = 2**i;
end
endgenerate
assign in_port_decoded = decoded_value[input_port_num_result];
// Note: you cannot do [`IOQ_SRC_PORT_POS +: NUM_QUEUES_WIDTH] in the
// statement below as it does not work with ModelSim SE 6.2F
assign input_port_num_result = in_data[`IOQ_SRC_PORT_POS +: 16];
assign is_from_cpu_found = |(in_port_decoded & {(NUM_QUEUES/2){2'b10}}) ;
assign to_cpu_output_port_result = {in_port_decoded[NUM_QUEUES-2:0], 1'b0}; // odd numbers are CPU ports
assign from_cpu_output_port_result = {1'b0, in_port_decoded[NUM_QUEUES-1:1]};// even numbers are MAC ports
always@(*) begin
state_next = state;
wr_en = 0;
case(state)
PARSE_HDRS: begin
if( in_ctrl==0 && in_wr) begin
state_next = WAIT_EOP;
end
if( in_ctrl==IO_QUEUE_STAGE_NUM && in_wr) begin
wr_en = 1;
end
end
WAIT_EOP: begin
if(in_wr && in_ctrl != 0) begin
state_next = PARSE_HDRS;
end
end
endcase // case(state)
end // always@ (*)
always @(posedge clk) begin
if(reset) begin
state <= PARSE_HDRS;
end
else begin
state <= state_next;
end
end
endmodule // eth_parser
|
`timescale 1us/100ns
module framing_crc(
output reg [7:0] dout,
output next_indicator,
input [7:0] din,
input indicator,
input clk,
input reset_n
);
localparam CRC_INIT = 16'hffff;
localparam WAITING = 0,
SHR = 1,
PHR_PSDU = 2,
FCS = 3;
reg [1:0] state, next_state;
reg [6:0] count, next_count;
reg [15:0] crc, next_crc;
wire crc_in = din[(count[2:0])-:1] ^ crc[0];
always @(*) begin
case (state)
WAITING: begin
if (indicator)
next_state = SHR;
else
next_state = WAITING;
next_count = 0;
next_crc = CRC_INIT;
end
SHR: begin
if (count < 79) begin
next_state = SHR;
next_count = count + 1;
end else begin
next_state = PHR_PSDU;
next_count = 0;
end
next_crc = CRC_INIT;
end
PHR_PSDU: begin
next_state = (indicator ? FCS : PHR_PSDU);
next_count = (count == 7 ? 0 : count + 1);
next_crc = {crc_in,
crc[15:12],
crc[11] ^ crc_in,
crc[10:5],
crc[4] ^ crc_in,
crc[3:1]};
end
FCS: begin
if (count < 15) begin
next_state = FCS;
next_count = count + 1;
next_crc = crc;
end else begin
next_state = WAITING;
next_count = 0;
next_crc = CRC_INIT;
end
end
default: begin
next_state = WAITING;
next_count = 0;
next_crc = CRC_INIT;
end
endcase
end
// Update states.
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
state <= WAITING;
count <= 0;
crc <= CRC_INIT;
end else begin
state <= next_state;
count <= next_count;
crc <= next_crc;
end
end
always @(*) begin
case (state)
SHR:
if (count < 64)
dout = 8'haa;
else if (count < 72)
dout = 8'h98;
else
dout = 8'hf3;
PHR_PSDU:
dout = din;
FCS:
dout = ~(count < 8 ? crc[7:0] : crc[15:8]);
default:
dout = 0;
endcase
end
assign next_indicator = (state == WAITING && indicator ||
state == FCS && count == 15);
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 3
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_blk_mem_gen_0_0 (
clka,
rsta,
ena,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
web,
addrb,
dinb,
doutb
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *)
input wire rsta;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [3 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [31 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [31 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [31 : 0] douta;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input wire clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB RST" *)
input wire rstb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *)
input wire enb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *)
input wire [3 : 0] web;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input wire [31 : 0] addrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *)
input wire [31 : 0] dinb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output wire [31 : 0] doutb;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(1),
.C_ENABLE_32BIT_ADDRESS(1),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(2),
.C_BYTE_SIZE(8),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("NONE"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(1),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(1),
.C_WEA_WIDTH(4),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_READ_WIDTH_A(32),
.C_WRITE_DEPTH_A(2048),
.C_READ_DEPTH_A(2048),
.C_ADDRA_WIDTH(32),
.C_HAS_RSTB(1),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(1),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(1),
.C_WEB_WIDTH(4),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(32),
.C_READ_WIDTH_B(32),
.C_WRITE_DEPTH_B(2048),
.C_READ_DEPTH_B(2048),
.C_ADDRB_WIDTH(32),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("2"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 10.7492 mW")
) inst (
.clka(clka),
.rsta(rsta),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(clkb),
.rstb(rstb),
.enb(enb),
.regceb(1'D0),
.web(web),
.addrb(addrb),
.dinb(dinb),
.doutb(doutb),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(32'B0),
.s_axi_wstrb(4'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / GND Connection
// /___/ /\ Filename : GND.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:19 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
`timescale 1 ps / 1 ps
`celldefine
module GND(G);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output G;
assign G = 1'b0;
endmodule
`endcelldefine
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Phy_sim.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao ([email protected]) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: Phy_sim.v,v $
// Revision 1.3 2006/11/17 17:53:07 maverickist
// no message
//
// Revision 1.2 2006/01/19 14:07:50 maverickist
// verification is complete.
//
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
`timescale 1ns/100ps
module phy_sim(
input Gtx_clk, // Used only in GMII mode
output Rx_clk,
output Tx_clk, // Used only in MII mode
input Tx_er,
input Tx_en,
input [7:0] Txd,
output Rx_er,
output Rx_dv,
output [7:0] Rxd,
output Crs,
output Col,
input [2:0] Speed,
input Done
);
//////////////////////////////////////////////////////////////////////
// this file used to simulate Phy.
// generate clk and loop the Tx data to Rx data
// full duplex mode can be verified on loop mode.
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// internal signals
//////////////////////////////////////////////////////////////////////
reg Clk_25m; // Used for 100 Mbps mode
reg Clk_2_5m; // Used for 10 Mbps mode
//wire Rx_clk;
//wire Tx_clk; // Used only in MII mode
initial
begin
#10;
while ( !Done )
begin
#20 Clk_25m = 0;
#20 Clk_25m = 1;
end
end
initial
begin
#10;
while ( !Done )
begin
#200 Clk_2_5m = 0;
#200 Clk_2_5m = 1;
end
end
assign Rx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0;
assign Tx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0;
assign Rx_dv = Tx_en;
assign Rxd = Txd;
assign Rx_er = Tx_er;
assign Crs = Tx_en;
assign Col = 0;
endmodule
|
(** * ProofObjects: The Curry-Howard Correspondence *)
(** "_Algorithms are the computational content of proofs_." --Robert Harper *)
Require Export IndProp.
(** We have seen that Coq has mechanisms both for _programming_,
using inductive data types like [nat] or [list] and functions over
these types, and for _proving_ properties of these programs, using
inductive propositions (like [ev]), implication, universal
quantification, and the like. So far, we have mostly treated
these mechanisms as if they were quite separate, and for many
purposes this is a good way to think. But we have also seen hints
that Coq's programming and proving facilities are closely related.
For example, the keyword [Inductive] is used to declare both data
types and propositions, and [->] is used both to describe the type
of functions on data and logical implication. This is not just a
syntactic accident! In fact, programs and proofs in Coq are
almost the same thing. In this chapter we will study how this
works.
We have already seen the fundamental idea: provability in Coq is
represented by concrete _evidence_. When we construct the proof
of a basic proposition, we are actually building a tree of
evidence, which can be thought of as a data structure.
If the proposition is an implication like [A -> B], then its proof
will be an evidence _transformer_: a recipe for converting
evidence for A into evidence for B. So at a fundamental level,
proofs are simply programs that manipulate evidence. *)
(** Question: If evidence is data, what are propositions themselves?
Answer: They are types!
Look again at the formal definition of the [ev] property. *)
Print ev.
(* ==>
Inductive ev : nat -> Prop :=
| ev_0 : ev 0
| ev_SS : forall n, ev n -> ev (S (S n)).
*)
(** Suppose we introduce an alternative pronunciation of "[:]".
Instead of "has type," we can say "is a proof of." For example,
the second line in the definition of [ev] declares that [ev_0 : ev
0]. Instead of "[ev_0] has type [ev 0]," we can say that "[ev_0]
is a proof of [ev 0]." *)
(** This pun between types and propositions -- between [:] as "has type"
and [:] as "is a proof of" or "is evidence for" -- is called the
_Curry-Howard correspondence_. It proposes a deep connection
between the world of logic and the world of computation:
propositions ~ types
proofs ~ data values
See [Wadler 2015] for a brief history and an up-to-date exposition.
Many useful insights follow from this connection. To begin with,
it gives us a natural interpretation of the type of the [ev_SS]
constructor: *)
Check ev_SS.
(* ===> ev_SS : forall n,
ev n ->
ev (S (S n)) *)
(** This can be read "[ev_SS] is a constructor that takes two
arguments -- a number [n] and evidence for the proposition [ev
n] -- and yields evidence for the proposition [ev (S (S n))]." *)
(** Now let's look again at a previous proof involving [ev]. *)
Theorem ev_4 : ev 4.
Proof.
apply ev_SS. apply ev_SS. apply ev_0. Qed.
(** As with ordinary data values and functions, we can use the [Print]
command to see the _proof object_ that results from this proof
script. *)
Print ev_4.
(* ===> ev_4 = ev_SS 2 (ev_SS 0 ev_0)
: ev 4 *)
(** As a matter of fact, we can also write down this proof object
_directly_, without the need for a separate proof script: *)
Check (ev_SS 2 (ev_SS 0 ev_0)).
(* ===> ev 4 *)
(** The expression [ev_SS 2 (ev_SS 0 ev_0)] can be thought of as
instantiating the parameterized constructor [ev_SS] with the
specific arguments [2] and [0] plus the corresponding proof
objects for its premises [ev 2] and [ev 0]. Alternatively, we can
think of [ev_SS] as a primitive "evidence constructor" that, when
applied to a particular number, wants to be further applied to
evidence that that number is even; its type,
forall n, ev n -> ev (S (S n)),
expresses this functionality, in the same way that the polymorphic
type [forall X, list X] expresses the fact that the constructor
[nil] can be thought of as a function from types to empty lists
with elements of that type. *)
(** We saw in the [Logic] chapter that we can use function
application syntax to instantiate universally quantified variables
in lemmas, as well as to supply evidence for assumptions that
these lemmas impose. For instance: *)
Theorem ev_4': ev 4.
Proof.
apply (ev_SS 2 (ev_SS 0 ev_0)).
Qed.
(** We can now see that this feature is a trivial consequence of the
status the Coq grants to proofs and propositions: Lemmas and
hypotheses can be combined in expressions (i.e., proof objects)
according to the same basic rules used for programs in the
language. *)
(* ################################################################# *)
(** * Proof Scripts *)
(** The _proof objects_ we've been discussing lie at the core of how
Coq operates. When Coq is following a proof script, what is
happening internally is that it is gradually constructing a proof
object -- a term whose type is the proposition being proved. The
tactics between [Proof] and [Qed] tell it how to build up a term
of the required type. To see this process in action, let's use
the [Show Proof] command to display the current state of the proof
tree at various points in the following tactic proof. *)
Theorem ev_4'' : ev 4.
Proof.
Show Proof.
apply ev_SS.
Show Proof.
apply ev_SS.
Show Proof.
apply ev_0.
Show Proof.
Qed.
(** At any given moment, Coq has constructed a term with a
"hole" (indicated by [?Goal] here, and so on), and it knows what
type of evidence is needed to fill this hole.
Each hole corresponds to a subgoal, and the proof is
finished when there are no more subgoals. At this point, the
evidence we've built stored in the global context under the name
given in the [Theorem] command. *)
(** Tactic proofs are useful and convenient, but they are not
essential: in principle, we can always construct the required
evidence by hand, as shown above. Then we can use [Definition]
(rather than [Theorem]) to give a global name directly to a
piece of evidence. *)
Definition ev_4''' : ev 4 :=
ev_SS 2 (ev_SS 0 ev_0).
(** All these different ways of building the proof lead to exactly the
same evidence being saved in the global environment. *)
Print ev_4.
(* ===> ev_4 = ev_SS 2 (ev_SS 0 ev_0) : ev 4 *)
Print ev_4'.
(* ===> ev_4' = ev_SS 2 (ev_SS 0 ev_0) : ev 4 *)
Print ev_4''.
(* ===> ev_4'' = ev_SS 2 (ev_SS 0 ev_0) : ev 4 *)
Print ev_4'''.
(* ===> ev_4''' = ev_SS 2 (ev_SS 0 ev_0) : ev 4 *)
(** **** Exercise: 1 star (eight_is_even) *)
(** Give a tactic proof and a proof object showing that [ev 8]. *)
Theorem ev_8 : ev 8.
Proof. repeat constructor. Qed.
Definition ev_8' : ev 8 := ev_SS 6 (ev_SS 4 ev_4''').
(** [] *)
(* ################################################################# *)
(** * Quantifiers, Implications, Functions *)
(** In Coq's computational universe (where data structures and
programs live), there are two sorts of values with arrows in their
types: _constructors_ introduced by [Inductive]-ly defined data
types, and _functions_.
Similarly, in Coq's logical universe (where we carry out proofs),
there are two ways of giving evidence for an implication:
constructors introduced by [Inductive]-ly defined propositions,
and... functions!
For example, consider this statement: *)
Theorem ev_plus4 : forall n, ev n -> ev (4 + n).
Proof.
intros n H. simpl.
apply ev_SS.
apply ev_SS.
apply H.
Qed.
(** What is the proof object corresponding to [ev_plus4]?
We're looking for an expression whose _type_ is [forall n, ev n ->
ev (4 + n)] -- that is, a _function_ that takes two arguments (one
number and a piece of evidence) and returns a piece of evidence!
Here it is: *)
Definition ev_plus4' : forall n, ev n -> ev (4 + n) :=
fun (n : nat) => fun (H : ev n) =>
ev_SS (S (S n)) (ev_SS n H).
(** Recall that [fun n => blah] means "the function that, given [n],
yields [blah]," and that Coq treats [4 + n] and [S (S (S (S n)))]
as synonyms. Another equivalent way to write this definition is: *)
Definition ev_plus4'' (n : nat) (H : ev n) : ev (4 + n) :=
ev_SS (S (S n)) (ev_SS n H).
Check ev_plus4''.
(* ===> ev_plus4'' : forall n : nat, ev n -> ev (4 + n) *)
(** When we view the proposition being proved by [ev_plus4] as a
function type, one aspect of it may seem a little unusual. The
second argument's type, [ev n], mentions the _value_ of the first
argument, [n]. While such _dependent types_ are not found in
conventional programming languages, they can be useful in
programming too, as the recent flurry of activity in the
functional programming community demonstrates.
Notice that both implication ([->]) and quantification ([forall])
correspond to functions on evidence. In fact, they are really the
same thing: [->] is just a shorthand for a degenerate use of
[forall] where there is no dependency, i.e., no need to give a
name to the type on the left-hand side of the arrow. *)
(** For example, consider this proposition: *)
Definition ev_plus2 : Prop :=
forall n, forall (E : ev n), ev (n + 2).
(** A proof term inhabiting this proposition would be a function
with two arguments: a number [n] and some evidence [E] that [n] is
even. But the name [E] for this evidence is not used in the rest
of the statement of [ev_plus2], so it's a bit silly to bother
making up a name for it. We could write it like this instead,
using the dummy identifier [_] in place of a real name: *)
Definition ev_plus2' : Prop :=
forall n, forall (_ : ev n), ev (n + 2).
(** Or, equivalently, we can write it in more familiar notation: *)
Definition ev_plus2'' : Prop :=
forall n, ev n -> ev (n + 2).
(** In general, "[P -> Q]" is just syntactic sugar for
"[forall (_:P), Q]". *)
(* ################################################################# *)
(** * Programming with Tactics *)
(** If we can build proofs by giving explicit terms rather than
executing tactic scripts, you may be wondering whether we can
build _programs_ using _tactics_ rather than explicit terms.
Naturally, the answer is yes! *)
Definition add1 : nat -> nat.
intro n.
Show Proof.
apply S.
Show Proof.
apply n. Defined.
Print add1.
(* ==>
add1 = fun n : nat => S n
: nat -> nat
*)
Compute add1 2.
(* ==> 3 : nat *)
(** Notice that we terminate the [Definition] with a [.] rather than
with [:=] followed by a term. This tells Coq to enter _proof
scripting mode_ to build an object of type [nat -> nat]. Also, we
terminate the proof with [Defined] rather than [Qed]; this makes
the definition _transparent_ so that it can be used in computation
like a normally-defined function. ([Qed]-defined objects are
opaque during computation.)
This feature is mainly useful for writing functions with dependent
types, which we won't explore much further in this book. But it
does illustrate the uniformity and orthogonality of the basic
ideas in Coq. *)
(* ################################################################# *)
(** * Logical Connectives as Inductive Types *)
(** Inductive definitions are powerful enough to express most of the
connectives and quantifiers we have seen so far. Indeed, only
universal quantification (and thus implication) is built into Coq;
all the others are defined inductively. We'll see these
definitions in this section. *)
Module Props.
(** ** Conjunction
To prove that [P /\ Q] holds, we must present evidence for both
[P] and [Q]. Thus, it makes sense to define a proof object for [P
/\ Q] as consisting of a pair of two proofs: one for [P] and
another one for [Q]. This leads to the following definition. *)
Module And.
Inductive and (P Q : Prop) : Prop :=
| conj : P -> Q -> and P Q.
End And.
(** Notice the similarity with the definition of the [prod] type,
given in chapter [Poly]; the only difference is that [prod] takes
[Type] arguments, whereas [and] takes [Prop] arguments. *)
Print prod.
(* ===>
Inductive prod (X Y : Type) : Type :=
| pair : X -> Y -> X * Y. *)
(** This should clarify why [destruct] and [intros] patterns can be
used on a conjunctive hypothesis. Case analysis allows us to
consider all possible ways in which [P /\ Q] was proved -- here
just one (the [conj] constructor). Similarly, the [split] tactic
actually works for any inductively defined proposition with only
one constructor. In particular, it works for [and]: *)
Lemma and_comm : forall P Q : Prop, P /\ Q <-> Q /\ P.
Proof.
intros P Q. split.
- intros [HP HQ]. split.
+ apply HQ.
+ apply HP.
- intros [HP HQ]. split.
+ apply HQ.
+ apply HP.
Qed.
(** This shows why the inductive definition of [and] can be
manipulated by tactics as we've been doing. We can also use it to
build proofs directly, using pattern-matching. For instance: *)
Definition and_comm'_aux P Q (H : P /\ Q) :=
match H with
| conj HP HQ => conj HQ HP
end.
Definition and_comm' P Q : P /\ Q <-> Q /\ P :=
conj (and_comm'_aux P Q) (and_comm'_aux Q P).
(** **** Exercise: 2 stars, optional (conj_fact) *)
(** Construct a proof object demonstrating the following proposition. *)
Definition conj_fact : forall P Q R, P /\ Q -> Q /\ R -> P /\ R :=
fun (P Q R : Prop) =>
fun (H1 : P /\ Q) =>
fun (H2 : Q /\ R)
=> match H1, H2 with
| conj Hp Hq, conj _ Hr => conj Hp Hr
end.
(** [] *)
(** ** Disjunction
The inductive definition of disjunction uses two constructors, one
for each side of the disjunct: *)
Module Or.
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
End Or.
(** This declaration explains the behavior of the [destruct] tactic on
a disjunctive hypothesis, since the generated subgoals match the
shape of the [or_introl] and [or_intror] constructors.
Once again, we can also directly write proof objects for theorems
involving [or], without resorting to tactics. *)
(** **** Exercise: 2 stars, optional (or_commut'') *)
(** Try to write down an explicit proof object for [or_commut] (without
using [Print] to peek at the ones we already defined!). *)
Definition or_comm : forall P Q, P \/ Q -> Q \/ P :=
fun (P Q : Prop) => fun (H : P \/ Q) =>
match H with
| or_introl Hp => or_intror Hp
| or_intror Hq => or_introl Hq
end.
(** [] *)
(** ** Existential Quantification
To give evidence for an existential quantifier, we package a
witness [x] together with a proof that [x] satisfies the property
[P]: *)
Module Ex.
Inductive ex {A : Type} (P : A -> Prop) : Prop :=
| ex_intro : forall x : A, P x -> ex P.
End Ex.
(** This may benefit from a little unpacking. The core definition is
for a type former [ex] that can be used to build propositions of
the form [ex P], where [P] itself is a _function_ from witness
values in the type [A] to propositions. The [ex_intro]
constructor then offers a way of constructing evidence for [ex P],
given a witness [x] and a proof of [P x].
The more familiar form [exists x, P x] desugars to an expression
involving [ex]: *)
Check ex (fun n => ev n).
(* ===> exists n : nat, ev n
: Prop *)
(** Here's how to define an explicit proof object involving [ex]: *)
Definition some_nat_is_even : exists n, ev n :=
ex_intro ev 4 (ev_SS 2 (ev_SS 0 ev_0)).
(** **** Exercise: 2 stars, optional (ex_ev_Sn) *)
(** Complete the definition of the following proof object: *)
Definition ex_ev_Sn : ex (fun n => ev (S n)) :=
ex_intro (fun n => ev (S n)) 1 (ev_SS 0 ev_0).
(** [] *)
(* ================================================================= *)
(** ** [True] and [False] *)
(** The inductive definition of the [True] proposition is simple: *)
Inductive True : Prop :=
| I : True.
(** It has one constructor (so every proof of [True] is the same, so
being given a proof of [True] is not informative.) *)
(** [False] is equally simple -- indeed, so simple it may look
syntactically wrong at first glance! *)
Inductive False : Prop :=.
(** That is, [False] is an inductive type with _no_ constructors --
i.e., no way to build evidence for it. *)
End Props.
(* ################################################################# *)
(** * Equality *)
(** Even Coq's equality relation is not built in. It has the
following inductive definition. (Actually, the definition in the
standard library is a small variant of this, which gives an
induction principle that is slightly easier to use.) *)
Module MyEquality.
Inductive eq {X:Type} : X -> X -> Prop :=
| eq_refl : forall x, eq x x.
Notation "x = y" := (eq x y)
(at level 70, no associativity)
: type_scope.
(** The way to think about this definition is that, given a set [X],
it defines a _family_ of propositions "[x] is equal to [y],"
indexed by pairs of values ([x] and [y]) from [X]. There is just
one way of constructing evidence for each member of this family:
applying the constructor [eq_refl] to a type [X] and a value [x :
X] yields evidence that [x] is equal to [x]. *)
(** **** Exercise: 2 stars (leibniz_equality) *)
(** The inductive definition of equality corresponds to _Leibniz
equality_: what we mean when we say "[x] and [y] are equal" is
that every property on [P] that is true of [x] is also true of
[y]. *)
Lemma leibniz_equality : forall (X : Type) (x y: X),
x = y -> forall P:X->Prop, P x -> P y.
Proof.
intros X x y Hxy HP HPx. destruct Hxy. apply HPx.
Qed.
(** [] *)
(** We can use [eq_refl] to construct evidence that, for example, [2 =
2]. Can we also use it to construct evidence that [1 + 1 = 2]?
Yes, we can. Indeed, it is the very same piece of evidence! The
reason is that Coq treats as "the same" any two terms that are
_convertible_ according to a simple set of computation rules.
These rules, which are similar to those used by [Compute], include
evaluation of function application, inlining of definitions, and
simplification of [match]es. *)
Lemma four: 2 + 2 = 1 + 3.
Proof.
apply eq_refl.
Qed.
(** The [reflexivity] tactic that we have used to prove equalities up
to now is essentially just short-hand for [apply refl_equal].
In tactic-based proofs of equality, the conversion rules are
normally hidden in uses of [simpl] (either explicit or implicit in
other tactics such as [reflexivity]). But you can see them
directly at work in the following explicit proof objects: *)
Definition four' : 2 + 2 = 1 + 3 :=
eq_refl 4.
Definition singleton : forall (X:Set) (x:X), []++[x] = x::[] :=
fun (X:Set) (x:X) => eq_refl [x].
End MyEquality.
Definition quiz6 : exists x, x + 3 = 4
:= ex_intro (fun z => (z + 3 = 4)) 1 (refl_equal 4).
(* ================================================================= *)
(** ** Inversion, Again *)
(** We've seen [inversion] used with both equality hypotheses and
hypotheses about inductively defined propositions. Now that we've
seen that these are actually the same thing, we're in a position
to take a closer look at how [inversion] behaves.
In general, the [inversion] tactic...
- takes a hypothesis [H] whose type [P] is inductively defined,
and
- for each constructor [C] in [P]'s definition,
- generates a new subgoal in which we assume [H] was
built with [C],
- adds the arguments (premises) of [C] to the context of
the subgoal as extra hypotheses,
- matches the conclusion (result type) of [C] against the
current goal and calculates a set of equalities that must
hold in order for [C] to be applicable,
- adds these equalities to the context (and, for convenience,
rewrites them in the goal), and
- if the equalities are not satisfiable (e.g., they involve
things like [S n = O]), immediately solves the subgoal. *)
(** _Example_: If we invert a hypothesis built with [or], there are two
constructors, so two subgoals get generated. The
conclusion (result type) of the constructor ([P \/ Q]) doesn't
place any restrictions on the form of [P] or [Q], so we don't get
any extra equalities in the context of the subgoal.
_Example_: If we invert a hypothesis built with [and], there is
only one constructor, so only one subgoal gets generated. Again,
the conclusion (result type) of the constructor ([P /\ Q]) doesn't
place any restrictions on the form of [P] or [Q], so we don't get
any extra equalities in the context of the subgoal. The
constructor does have two arguments, though, and these can be seen
in the context in the subgoal.
_Example_: If we invert a hypothesis built with [eq], there is
again only one constructor, so only one subgoal gets generated.
Now, though, the form of the [refl_equal] constructor does give us
some extra information: it tells us that the two arguments to [eq]
must be the same! The [inversion] tactic adds this fact to the
context. *)
(** $Date: 2017-01-30 18:47:45 -0500 (Mon, 30 Jan 2017) $ *)
|
// Basic Components; muxes, flip-flops, etc.
//
// Author: Ivan Castellanos
// email: [email protected]
// VLSI Computer Architecture Research Group,
// Oklahoma Stata University
//Reduced Full Adder Cell (for CLA, 8 gates instead of 9)
module rfa (sum, g, p, a, b, cin);
output sum;
output g;
output p;
input a;
input b;
input cin;
xor x1(sum, a, b, cin);
and a1(g, a, b);
or o1(p, a, b);
endmodule
//17-bit Register with reset
module dffr_17 (q, d, clk, reset);
output [16:0] q;
input [16:0] d;
input clk, reset;
reg [16:0] q;
always @ (posedge clk or negedge reset)
if (reset == 0)
q <= 0;
else
q <= d;
endmodule
//Basic adders for Multiplier
module FA (Sum, Cout, A, B, Cin);
input A;
input B;
input Cin;
output Sum;
output Cout;
wire w1;
wire w2;
wire w3;
wire w4;
xor x1(w1, A, B);
xor x2(Sum, w1, Cin);
nand n1(w2, A, B);
nand n2(w3, A, Cin);
nand n3(w4, B, Cin);
nand n4(Cout, w2, w3, w4);
endmodule // FA
module MFA (Sum, Cout, A, B, Sin, Cin);
input A;
input B;
input Sin;
input Cin;
output Sum;
output Cout;
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
and a1(w0, A, B);
xor x1(w1, w0, Sin);
xor x2(Sum, w1, Cin);
nand n1(w2, w0, Sin);
nand n2(w3, w0, Cin);
nand n3(w4, Sin, Cin);
nand n4(Cout, w2, w3, w4);
endmodule // MFA
module NMFA (Sum, Cout, A, B, Sin, Cin);
input A;
input B;
input Sin;
input Cin;
output Sum;
output Cout;
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
nand n0(w0, A, B);
xor x1(w1, w0, Sin);
xor x2(Sum, w1, Cin);
nand n1(w2, w0, Sin);
nand n2(w3, w0, Cin);
nand n3(w4, Sin, Cin);
nand n4(Cout, w2, w3, w4);
endmodule // NMFA
module MHA (Sum, Cout, A, B, Sin);
input A;
input B;
input Sin;
output Sum;
output Cout;
wire w1;
and a0(w1, A, B);
xor x1(Sum, w1, Sin);
and a1(Cout, w1, Sin);
endmodule // MHA
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2B_BLACKBOX_V
`define SKY130_FD_SC_LP__AND2B_BLACKBOX_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and2b (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2B_BLACKBOX_V
|
/**
* This is written by Zhiyang Ong ([email protected]; 6004 9194 12)
* and Andrew Mattheisen ([email protected]; 2134 5147 11)
* for EE577b Troy WideWord Processor Project
*
*
* @reminder December 1, 2007
* Remember to remove wrbyteen and ctrl_ppp from the inputs to
* the ALU and its testbench
*/
// GOLD VERSION
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/alu.v
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*
* ALU is a combinational logic block without clock signals
*/
`include "control.h"
// Behavioral model for the ALU
module alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result,wrbyteen);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
/**
* Overflow fromn arithmetic operations are ignored; use
* saturating mode for arithmetic operations - cap the value
* at the maximum value.
*
* Also, an output signal to indicate that an overflow has
* occurred will not be provided
*/
// ===============================================================
// Input signals
// Input register A
input [0:127] reg_A;
// Input register B
input [0:127] reg_B;
// Clock signal
//input clock;
// Control signal bits - ppp
input [0:2] ctrl_ppp;
// Control signal bits - ww
input [0:1] ctrl_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform
*/
input [0:4] alu_op;
/**
* Byte-write enable signals: one for each byte of the data
*
* Asserted high when each byte of the address word needs to be
* updated during the write operation
*/
input [15:0] wrbyteen;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*
* The reset signal for the ALU is ignored
*/
// Defining constants: parameter [name_of_constant] = value;
parameter max_128_bits = 128'hffffffffffffffffffffffffffffffff;
//parameter max_128_bits = 128'hfffffffffffffffffffffffffffffffff;
//parameter max_128_bits = 128'h00112233445566778899aabbccddeeff1;
//parameter max_128_bits = 128'h123415678901234567890123456789012;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:127] result; // Output signals
// ===============================================================
always @(reg_A or reg_B or ctrl_ppp or ctrl_ww or alu_op or wrbyteen)
begin
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
/**
* In computer science, a logical shift is a shift operator
* that shifts all the bits of its operand. Unlike an
* arithmetic shift, a logical shift does not preserve
* a number's sign bit or distinguish a number's exponent
* from its mantissa; every bit in the operand is simply
* moved a given number of bit positions, and the vacant
* bit-positions are filled in, generally with zeros
* (compare with a circular shift).
*
* SRL,SLL,Srli,sra,srai...
*/
// ================================================
// ======================================================
// SLL instruction << mv to LSB << bit 127
`aluwsll:
begin
case(ctrl_ww)
`w8: // aluwsll AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]<<reg_B[5:7];
result[8:15]<=reg_A[8:15]<<reg_B[13:15];
result[16:23]<=reg_A[16:23]<<reg_B[21:23];
result[24:31]<=reg_A[24:31]<<reg_B[29:31];
result[32:39]<=reg_A[32:39]<<reg_B[37:39];
result[40:47]<=reg_A[40:47]<<reg_B[45:47];
result[48:55]<=reg_A[48:55]<<reg_B[53:55];
result[56:63]<=reg_A[56:63]<<reg_B[61:63];
result[64:71]<=reg_A[64:71]<<reg_B[69:71];
result[72:79]<=reg_A[72:79]<<reg_B[77:79];
result[80:87]<=reg_A[80:87]<<reg_B[85:87];
result[88:95]<=reg_A[88:95]<<reg_B[93:95];
result[96:103]<=reg_A[96:103]<<reg_B[101:103];
result[104:111]<=reg_A[104:111]<<reg_B[109:111];
result[112:119]<=reg_A[112:119]<<reg_B[117:119];
result[120:127]<=reg_A[120:127]<<reg_B[125:127];
end
`w16: // aluwsll AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]<<reg_B[12:15];
result[16:31]<=reg_A[16:31]<<reg_B[28:31];
result[32:47]<=reg_A[32:47]<<reg_B[44:47];
result[48:63]<=reg_A[48:63]<<reg_B[60:63];
result[64:79]<=reg_A[64:79]<<reg_B[76:79];
result[80:95]<=reg_A[80:95]<<reg_B[92:95];
result[96:111]<=reg_A[96:111]<<reg_B[108:111];
result[112:127]<=reg_A[112:127]<<reg_B[124:127];
end
`w32: // aluwsll AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]<<reg_B[27:31];
result[32:63]<=reg_A[32:63]<<reg_B[59:63];
result[64:95]<=reg_A[64:95]<<reg_B[91:95];
result[96:127]<=reg_A[96:127]<<reg_B[123:127];
end
default: // aluwsll AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
/*
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
*/
// ======================================================
// SRL instruction >> mv to MSB >> bit 0
`aluwsrl:
begin
case(ctrl_ppp)
`aa: // aluwsrl AND `aa
begin
case(ctrl_ww)
`w8: // aluwsrl AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default: // aluwsrl AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwsrl AND `uu
begin
case(ctrl_ww)
`w8: // aluwsrl AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
end
`w16: // aluwsrl AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
end
`w32: // aluwsrl AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
end
default:
begin
// aluwsrl AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwsrl AND `dd
begin
case(ctrl_ww)
`w8: // aluwsrl AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwsrl AND `ee
begin
case(ctrl_ww)
`w8: // aluwsrl AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
end
`w16: // aluwsrl AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
end
`w32: // aluwsrl AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
end
default:
begin
// aluwsrl AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwsrl AND `oo
begin
case(ctrl_ww)
`w8: // aluwsrl AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwsrl AND `mm
begin
case(ctrl_ww)
`w8: // aluwsrl AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
end
`w16: // aluwsrl AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
end
`w32: // aluwsrl AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
end
default:
begin
// aluwsrl AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwsrl AND `ll
begin
case(ctrl_ww)
`w8: // aluwsrl AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwsrl AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
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//================================================================================
//================================================================================
//================================================================================
// ================================================
// ADD instruction
`aluwadd:
begin
case(ctrl_ppp)
`aa: // aluwadd AND `aa
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwadd AND `uu
begin
case(ctrl_ww)
`w8: // aluwadd AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
end
`w16: // aluwadd AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
end
`w32: // aluwadd AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwadd AND `dd
begin
case(ctrl_ww)
`w8: // aluwadd AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwadd AND `ee
begin
case(ctrl_ww)
`w8: // aluwadd AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
end
`w16: // aluwadd AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
end
`w32: // aluwadd AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
end
default:
begin
// aluwadd AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwadd AND `oo
begin
case(ctrl_ww)
`w8: // aluwadd AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwadd AND `mm
begin
case(ctrl_ww)
`w8: // aluwadd AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
end
`w16: // aluwadd AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
end
`w32: // aluwadd AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
end
default:
begin
// aluwadd AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwadd AND `ll
begin
case(ctrl_ww)
`w8: // aluwadd AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwadd AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// AND instruction
`aluwand:
begin
case(ctrl_ppp)
`aa: // aluwand AND `aa
begin
case(ctrl_ww)
`w8: // aluwand AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default: // aluwand AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwand AND `uu
begin
case(ctrl_ww)
`w8: // aluwand AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
end
`w16: // aluwand AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
end
`w32: // aluwand AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
end
default:
begin
// aluwand AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwand AND `dd
begin
case(ctrl_ww)
`w8: // aluwand AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwand AND `ee
begin
case(ctrl_ww)
`w8: // aluwand AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[112:119]<=reg_A[112:119]®_B[112:119];
end
`w16: // aluwand AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[96:111]<=reg_A[96:111]®_B[96:111];
end
`w32: // aluwand AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[64:95]<=reg_A[64:95]®_B[64:95];
end
default:
begin
// aluwand AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwand AND `oo
begin
case(ctrl_ww)
`w8: // aluwand AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]®_B[8:15];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]®_B[16:31];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]®_B[32:63];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwand AND `mm
begin
case(ctrl_ww)
`w8: // aluwand AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
end
`w16: // aluwand AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
end
`w32: // aluwand AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
end
default:
begin
// aluwand AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwand AND `ll
begin
case(ctrl_ww)
`w8: // aluwand AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwand AND Default
begin
result<=128'd0;
end
endcase
end
// ==============================================
// ================================================
// NOT instruction
`aluwnot:
begin
case(ctrl_ppp)
`aa: // aluwnot AND `aa
begin
case(ctrl_ww)
`w8: // aluwnot AND `aa AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `aa AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `aa AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default: // aluwnot AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwnot AND `uu
begin
case(ctrl_ww)
`w8: // aluwnot AND `uu AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
end
`w16: // aluwnot AND `uu AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
end
`w32: // aluwnot AND `uu AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
end
default:
begin
// aluwnot AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwnot AND `dd
begin
case(ctrl_ww)
`w8: // aluwnot AND `dd AND `w8
begin
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `dd AND `w16
begin
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `dd AND `w32
begin
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwnot AND `ee
begin
case(ctrl_ww)
`w8: // aluwnot AND `ee AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[16:23]<=~reg_A[16:23];
result[32:39]<=~reg_A[32:39];
result[48:55]<=~reg_A[48:55];
result[64:71]<=~reg_A[64:71];
result[80:87]<=~reg_A[80:87];
result[96:103]<=~reg_A[96:103];
result[112:119]<=~reg_A[112:119];
end
`w16: // aluwnot AND `ee AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[32:47]<=~reg_A[32:47];
result[64:79]<=~reg_A[64:79];
result[96:111]<=~reg_A[96:111];
end
`w32: // aluwnot AND `ee AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[64:95]<=~reg_A[64:95];
end
default:
begin
// aluwnot AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwnot AND `oo
begin
case(ctrl_ww)
`w8: // aluwnot AND `oo AND `w8
begin
result[8:15]<=~reg_A[8:15];
result[24:31]<=~reg_A[24:31];
result[40:47]<=~reg_A[40:47];
result[56:63]<=~reg_A[56:63];
result[72:79]<=~reg_A[72:79];
result[88:95]<=~reg_A[88:95];
result[104:111]<=~reg_A[104:111];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `oo AND `w16
begin
result[16:31]<=~reg_A[16:31];
result[48:63]<=~reg_A[48:63];
result[80:95]<=~reg_A[80:95];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `oo AND `w32
begin
result[32:63]<=~reg_A[32:63];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwnot AND `mm
begin
case(ctrl_ww)
`w8: // aluwnot AND `mm AND `w8
begin
result[0:7]<=~reg_A[0:7];
end
`w16: // aluwnot AND `mm AND `w16
begin
result[0:15]<=~reg_A[0:15];
end
`w32: // aluwnot AND `mm AND `w32
begin
result[0:31]<=~reg_A[0:31];
end
default:
begin
// aluwnot AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwnot AND `ll
begin
case(ctrl_ww)
`w8: // aluwnot AND `ll AND `w8
begin
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `ll AND `w16
begin
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `ll AND `w32
begin
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwnot AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// OR instruction
`aluwor:
begin
case(ctrl_ppp)
`aa: // aluwor AND `aa
begin
case(ctrl_ww)
`w8: // aluwor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default: // aluwor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwor AND `uu
begin
case(ctrl_ww)
`w8: // aluwor AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
end
`w16: // aluwor AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
end
`w32: // aluwor AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
end
default:
begin
// aluwor AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwor AND `dd
begin
case(ctrl_ww)
`w8: // aluwor AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwor AND `ee
begin
case(ctrl_ww)
`w8: // aluwor AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
end
`w16: // aluwor AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
end
`w32: // aluwor AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
end
default:
begin
// aluwor AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwor AND `oo
begin
case(ctrl_ww)
`w8: // aluwor AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwor AND `mm
begin
case(ctrl_ww)
`w8: // aluwor AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
end
`w16: // aluwor AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
end
`w32: // aluwor AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
end
default:
begin
// aluwor AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwor AND `ll
begin
case(ctrl_ww)
`w8: // aluwor AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwor AND Default
begin
result<=128'd0;
end
endcase
end
// ========================================================
// XOR instruction
`aluwxor:
begin
case(ctrl_ppp)
`aa: // aluwxor AND `aa
begin
case(ctrl_ww)
`w8: // aluwxor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default: // aluwxor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwxor AND `uu
begin
case(ctrl_ww)
`w8: // aluwxor AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
end
`w16: // aluwxor AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
end
`w32: // aluwxor AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
end
default:
begin
// aluwxor AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwxor AND `dd
begin
case(ctrl_ww)
`w8: // aluwxor AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwxor AND `ee
begin
case(ctrl_ww)
`w8: // aluwxor AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
end
`w16: // aluwxor AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
end
`w32: // aluwxor AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
end
default:
begin
// aluwxor AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwxor AND `oo
begin
case(ctrl_ww)
`w8: // aluwxor AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwxor AND `mm
begin
case(ctrl_ww)
`w8: // aluwxor AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
end
`w16: // aluwxor AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
end
`w32: // aluwxor AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
end
default:
begin
// aluwxor AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwxor AND `ll
begin
case(ctrl_ww)
`w8: // aluwxor AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwxor AND Default
begin
result<=128'd0;
end
endcase
end
// ======================================================
// SUB instruction
`aluwsub:
begin
case(ctrl_ppp)
`aa: // aluwsub AND `aa
begin
case(ctrl_ww)
`w8: // aluwsub AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default: // aluwsub AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwsub AND `uu
begin
case(ctrl_ww)
`w8: // aluwsub AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
end
`w16: // aluwsub AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
end
`w32: // aluwsub AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
end
default:
begin
// aluwsub AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwsub AND `dd
begin
case(ctrl_ww)
`w8: // aluwsub AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwsub AND `ee
begin
case(ctrl_ww)
`w8: // aluwsub AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
end
`w16: // aluwsub AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
end
`w32: // aluwsub AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
end
default:
begin
// aluwsub AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwsub AND `oo
begin
case(ctrl_ww)
`w8: // aluwsub AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwsub AND `mm
begin
case(ctrl_ww)
`w8: // aluwsub AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
end
`w16: // aluwsub AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
end
`w32: // aluwsub AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
end
default:
begin
// aluwsub AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwsub AND `ll
begin
case(ctrl_ww)
`w8: // aluwsub AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwsub AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
// ==============================================================
// PRM instruction
`aluwprm:
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
/*
* ========================================================
*=========================================================
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*=======================================================
*=======================================================
*=========================================================
*========================================================
*=========================================================
*========================================================
*========================================================
*=======================================================
*========================================================
*=======================================================
*=======================================================
*=========================================================
*========================================================
*=========================================================
*========================================================
*========================================================
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*=======================================================
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*=======================================================
*=======================================================
*/
// ==============================================================
// SLLI instruction
`aluwslli:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
// ==============================================================
// SRLI instruction
`aluwsrli:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={{1'b0},reg_A[0:6]};
result[8:15]<={{1'b0},reg_A[8:14]};
result[16:23]<={{1'b0},reg_A[16:22]};
result[24:31]<={{1'b0},reg_A[24:30]};
result[32:39]<={{1'b0},reg_A[32:38]};
result[40:47]<={{1'b0},reg_A[40:46]};
result[48:55]<={{1'b0},reg_A[48:54]};
result[56:63]<={{1'b0},reg_A[56:62]};
result[64:71]<={{1'b0},reg_A[64:70]};
result[72:79]<={{1'b0},reg_A[72:78]};
result[80:87]<={{1'b0},reg_A[80:86]};
result[88:95]<={{1'b0},reg_A[88:94]};
result[96:103]<={{1'b0},reg_A[96:102]};
result[104:111]<={{1'b0},reg_A[104:110]};
result[112:119]<={{1'b0},reg_A[112:118]};
result[120:127]<={{1'b0},reg_A[120:126]};
end
3'd2:
begin
result[0:7]<={{2{1'b0}},reg_A[0:5]};
result[8:15]<={{2{1'b0}},reg_A[8:13]};
result[16:23]<={{2{1'b0}},reg_A[16:21]};
result[24:31]<={{2{1'b0}},reg_A[24:29]};
result[32:39]<={{2{1'b0}},reg_A[32:37]};
result[40:47]<={{2{1'b0}},reg_A[40:45]};
result[48:55]<={{2{1'b0}},reg_A[48:53]};
result[56:63]<={{2{1'b0}},reg_A[56:61]};
result[64:71]<={{2{1'b0}},reg_A[64:69]};
result[72:79]<={{2{1'b0}},reg_A[72:77]};
result[80:87]<={{2{1'b0}},reg_A[80:85]};
result[88:95]<={{2{1'b0}},reg_A[88:93]};
result[96:103]<={{2{1'b0}},reg_A[96:101]};
result[104:111]<={{2{1'b0}},reg_A[104:109]};
result[112:119]<={{2{1'b0}},reg_A[112:117]};
result[120:127]<={{2{1'b0}},reg_A[120:125]};
end
3'd3:
begin
result[0:7]<={{3{1'b0}},reg_A[0:4]};
result[8:15]<={{3{1'b0}},reg_A[8:12]};
result[16:23]<={{3{1'b0}},reg_A[16:20]};
result[24:31]<={{3{1'b0}},reg_A[24:28]};
result[32:39]<={{3{1'b0}},reg_A[32:36]};
result[40:47]<={{3{1'b0}},reg_A[40:44]};
result[48:55]<={{3{1'b0}},reg_A[48:52]};
result[56:63]<={{3{1'b0}},reg_A[56:60]};
result[64:71]<={{3{1'b0}},reg_A[64:68]};
result[72:79]<={{3{1'b0}},reg_A[72:76]};
result[80:87]<={{3{1'b0}},reg_A[80:84]};
result[88:95]<={{3{1'b0}},reg_A[88:92]};
result[96:103]<={{3{1'b0}},reg_A[96:100]};
result[104:111]<={{3{1'b0}},reg_A[104:108]};
result[112:119]<={{3{1'b0}},reg_A[112:116]};
result[120:127]<={{3{1'b0}},reg_A[120:124]};
end
3'd4:
begin
result[0:7]<={{4{1'b0}},reg_A[0:3]};
result[8:15]<={{4{1'b0}},reg_A[8:11]};
result[16:23]<={{4{1'b0}},reg_A[16:19]};
result[24:31]<={{4{1'b0}},reg_A[24:27]};
result[32:39]<={{4{1'b0}},reg_A[32:35]};
result[40:47]<={{4{1'b0}},reg_A[40:43]};
result[48:55]<={{4{1'b0}},reg_A[48:51]};
result[56:63]<={{4{1'b0}},reg_A[56:69]};
result[64:71]<={{4{1'b0}},reg_A[64:67]};
result[72:79]<={{4{1'b0}},reg_A[72:75]};
result[80:87]<={{4{1'b0}},reg_A[80:83]};
result[88:95]<={{4{1'b0}},reg_A[88:91]};
result[96:103]<={{4{1'b0}},reg_A[96:99]};
result[104:111]<={{4{1'b0}},reg_A[104:107]};
result[112:119]<={{4{1'b0}},reg_A[112:115]};
result[120:127]<={{4{1'b0}},reg_A[120:123]};
end
3'd5:
begin
result[0:7]<={{5{1'b0}},reg_A[0:2]};
result[8:15]<={{5{1'b0}},reg_A[8:10]};
result[16:23]<={{5{1'b0}},reg_A[16:18]};
result[24:31]<={{5{1'b0}},reg_A[24:26]};
result[32:39]<={{5{1'b0}},reg_A[32:34]};
result[40:47]<={{5{1'b0}},reg_A[40:42]};
result[48:55]<={{5{1'b0}},reg_A[48:50]};
result[56:63]<={{5{1'b0}},reg_A[56:68]};
result[64:71]<={{5{1'b0}},reg_A[64:66]};
result[72:79]<={{5{1'b0}},reg_A[72:74]};
result[80:87]<={{5{1'b0}},reg_A[80:82]};
result[88:95]<={{5{1'b0}},reg_A[88:90]};
result[96:103]<={{5{1'b0}},reg_A[96:98]};
result[104:111]<={{5{1'b0}},reg_A[104:106]};
result[112:119]<={{5{1'b0}},reg_A[112:114]};
result[120:127]<={{5{1'b0}},reg_A[120:122]};
end
3'd6:
begin
result[0:7]<={{6{1'b0}},reg_A[0:1]};
result[8:15]<={{6{1'b0}},reg_A[8:9]};
result[16:23]<={{6{1'b0}},reg_A[16:17]};
result[24:31]<={{6{1'b0}},reg_A[24:25]};
result[32:39]<={{6{1'b0}},reg_A[32:33]};
result[40:47]<={{6{1'b0}},reg_A[40:41]};
result[48:55]<={{6{1'b0}},reg_A[48:49]};
result[56:63]<={{6{1'b0}},reg_A[56:67]};
result[64:71]<={{6{1'b0}},reg_A[64:65]};
result[72:79]<={{6{1'b0}},reg_A[72:73]};
result[80:87]<={{6{1'b0}},reg_A[80:81]};
result[88:95]<={{6{1'b0}},reg_A[88:89]};
result[96:103]<={{6{1'b0}},reg_A[96:97]};
result[104:111]<={{6{1'b0}},reg_A[104:105]};
result[112:119]<={{6{1'b0}},reg_A[112:113]};
result[120:127]<={{6{1'b0}},reg_A[120:121]};
end
3'd7:
begin
result[0:7]<={{7{1'b0}},reg_A[0]};
result[8:15]<={{7{1'b0}},reg_A[8]};
result[16:23]<={{7{1'b0}},reg_A[16]};
result[24:31]<={{7{1'b0}},reg_A[24]};
result[32:39]<={{7{1'b0}},reg_A[32]};
result[40:47]<={{7{1'b0}},reg_A[40]};
result[48:55]<={{7{1'b0}},reg_A[48]};
result[56:63]<={{7{1'b0}},reg_A[56]};
result[64:71]<={{7{1'b0}},reg_A[64]};
result[72:79]<={{7{1'b0}},reg_A[72]};
result[80:87]<={{7{1'b0}},reg_A[80]};
result[88:95]<={{7{1'b0}},reg_A[88]};
result[96:103]<={{7{1'b0}},reg_A[96]};
result[104:111]<={{7{1'b0}},reg_A[104]};
result[112:119]<={{7{1'b0}},reg_A[112]};
result[120:127]<={{7{1'b0}},reg_A[120]};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={{1'b0},reg_A[0:14]};
result[16:31]<={{1'b0},reg_A[16:30]};
result[32:47]<={{1'b0},reg_A[32:46]};
result[48:63]<={{1'b0},reg_A[48:62]};
result[64:79]<={{1'b0},reg_A[64:78]};
result[80:95]<={{1'b0},reg_A[80:94]};
result[96:111]<={{1'b0},reg_A[96:110]};
result[112:127]<={{1'b0},reg_A[112:126]};
end
4'd2:
begin
result[0:15]<={{2{1'b0}},reg_A[0:13]};
result[16:31]<={{2{1'b0}},reg_A[16:29]};
result[32:47]<={{2{1'b0}},reg_A[32:45]};
result[48:63]<={{2{1'b0}},reg_A[48:61]};
result[64:79]<={{2{1'b0}},reg_A[64:77]};
result[80:95]<={{2{1'b0}},reg_A[80:93]};
result[96:111]<={{2{1'b0}},reg_A[96:109]};
result[112:127]<={{2{1'b0}},reg_A[112:125]};
end
4'd3:
begin
result[0:15]<={{3{1'b0}},reg_A[0:12]};
result[16:31]<={{3{1'b0}},reg_A[16:28]};
result[32:47]<={{3{1'b0}},reg_A[32:44]};
result[48:63]<={{3{1'b0}},reg_A[48:60]};
result[64:79]<={{3{1'b0}},reg_A[64:76]};
result[80:95]<={{3{1'b0}},reg_A[80:92]};
result[96:111]<={{3{1'b0}},reg_A[96:108]};
result[112:127]<={{3{1'b0}},reg_A[112:124]};
end
4'd4:
begin
result[0:15]<={{4{1'b0}},reg_A[0:11]};
result[16:31]<={{4{1'b0}},reg_A[16:27]};
result[32:47]<={{4{1'b0}},reg_A[32:43]};
result[48:63]<={{4{1'b0}},reg_A[48:59]};
result[64:79]<={{4{1'b0}},reg_A[64:75]};
result[80:95]<={{4{1'b0}},reg_A[80:91]};
result[96:111]<={{4{1'b0}},reg_A[96:107]};
result[112:127]<={{4{1'b0}},reg_A[112:123]};
end
4'd5:
begin
result[0:15]<={{5{1'b0}},reg_A[0:10]};
result[16:31]<={{5{1'b0}},reg_A[16:26]};
result[32:47]<={{5{1'b0}},reg_A[32:42]};
result[48:63]<={{5{1'b0}},reg_A[48:58]};
result[64:79]<={{5{1'b0}},reg_A[64:74]};
result[80:95]<={{5{1'b0}},reg_A[80:90]};
result[96:111]<={{5{1'b0}},reg_A[96:106]};
result[112:127]<={{5{1'b0}},reg_A[112:122]};
end
4'd6:
begin
result[0:15]<={{6{1'b0}},reg_A[0:9]};
result[16:31]<={{6{1'b0}},reg_A[16:25]};
result[32:47]<={{6{1'b0}},reg_A[32:41]};
result[48:63]<={{6{1'b0}},reg_A[48:57]};
result[64:79]<={{6{1'b0}},reg_A[64:73]};
result[80:95]<={{6{1'b0}},reg_A[80:89]};
result[96:111]<={{6{1'b0}},reg_A[96:105]};
result[112:127]<={{6{1'b0}},reg_A[112:121]};
end
4'd7:
begin
result[0:15]<={{7{1'b0}},reg_A[0:8]};
result[16:31]<={{7{1'b0}},reg_A[16:24]};
result[32:47]<={{7{1'b0}},reg_A[32:40]};
result[48:63]<={{7{1'b0}},reg_A[48:56]};
result[64:79]<={{7{1'b0}},reg_A[64:72]};
result[80:95]<={{7{1'b0}},reg_A[80:88]};
result[96:111]<={{7{1'b0}},reg_A[96:104]};
result[112:127]<={{7{1'b0}},reg_A[112:120]};
end
4'd8:
begin
result[0:15]<={{8{1'b0}},reg_A[0:7]};
result[16:31]<={{8{1'b0}},reg_A[16:23]};
result[32:47]<={{8{1'b0}},reg_A[32:39]};
result[48:63]<={{8{1'b0}},reg_A[48:55]};
result[64:79]<={{8{1'b0}},reg_A[64:71]};
result[80:95]<={{8{1'b0}},reg_A[80:87]};
result[96:111]<={{8{1'b0}},reg_A[96:103]};
result[112:127]<={{8{1'b0}},reg_A[112:119]};
end
4'd9:
begin
result[0:15]<={{9{1'b0}},reg_A[0:6]};
result[16:31]<={{9{1'b0}},reg_A[16:22]};
result[32:47]<={{9{1'b0}},reg_A[32:38]};
result[48:63]<={{9{1'b0}},reg_A[48:54]};
result[64:79]<={{9{1'b0}},reg_A[64:70]};
result[80:95]<={{9{1'b0}},reg_A[80:86]};
result[96:111]<={{9{1'b0}},reg_A[96:102]};
result[112:127]<={{9{1'b0}},reg_A[112:118]};
end
4'd10:
begin
result[0:15]<={{10{1'b0}},reg_A[0:5]};
result[16:31]<={{10{1'b0}},reg_A[16:21]};
result[32:47]<={{10{1'b0}},reg_A[32:37]};
result[48:63]<={{10{1'b0}},reg_A[48:53]};
result[64:79]<={{10{1'b0}},reg_A[64:69]};
result[80:95]<={{10{1'b0}},reg_A[80:85]};
result[96:111]<={{10{1'b0}},reg_A[96:101]};
result[112:127]<={{10{1'b0}},reg_A[112:117]};
end
4'd11:
begin
result[0:15]<={{11{1'b0}},reg_A[0:4]};
result[16:31]<={{11{1'b0}},reg_A[16:20]};
result[32:47]<={{11{1'b0}},reg_A[32:36]};
result[48:63]<={{11{1'b0}},reg_A[48:52]};
result[64:79]<={{11{1'b0}},reg_A[64:68]};
result[80:95]<={{11{1'b0}},reg_A[80:84]};
result[96:111]<={{11{1'b0}},reg_A[96:100]};
result[112:127]<={{11{1'b0}},reg_A[112:116]};
end
4'd12:
begin
result[0:15]<={{12{1'b0}},reg_A[0:3]};
result[16:31]<={{12{1'b0}},reg_A[16:19]};
result[32:47]<={{12{1'b0}},reg_A[32:35]};
result[48:63]<={{12{1'b0}},reg_A[48:51]};
result[64:79]<={{12{1'b0}},reg_A[64:67]};
result[80:95]<={{12{1'b0}},reg_A[80:83]};
result[96:111]<={{12{1'b0}},reg_A[96:99]};
result[112:127]<={{12{1'b0}},reg_A[112:115]};
end
4'd13:
begin
result[0:15]<={{13{1'b0}},reg_A[0:2]};
result[16:31]<={{13{1'b0}},reg_A[16:18]};
result[32:47]<={{13{1'b0}},reg_A[32:34]};
result[48:63]<={{13{1'b0}},reg_A[48:50]};
result[64:79]<={{13{1'b0}},reg_A[64:66]};
result[80:95]<={{13{1'b0}},reg_A[80:82]};
result[96:111]<={{13{1'b0}},reg_A[96:98]};
result[112:127]<={{13{1'b0}},reg_A[112:114]};
end
4'd14:
begin
result[0:15]<={{14{1'b0}},reg_A[0:1]};
result[16:31]<={{14{1'b0}},reg_A[16:17]};
result[32:47]<={{14{1'b0}},reg_A[32:33]};
result[48:63]<={{14{1'b0}},reg_A[48:49]};
result[64:79]<={{14{1'b0}},reg_A[64:65]};
result[80:95]<={{14{1'b0}},reg_A[80:81]};
result[96:111]<={{14{1'b0}},reg_A[96:97]};
result[112:127]<={{14{1'b0}},reg_A[112:113]};
end
4'd15:
begin
result[0:15]<={{15{1'b0}},reg_A[0]};
result[16:31]<={{15{1'b0}},reg_A[16]};
result[32:47]<={{15{1'b0}},reg_A[32]};
result[48:63]<={{15{1'b0}},reg_A[48]};
result[64:79]<={{15{1'b0}},reg_A[64]};
result[80:95]<={{15{1'b0}},reg_A[80]};
result[96:111]<={{15{1'b0}},reg_A[96]};
result[112:127]<={{15{1'b0}},reg_A[112]};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={{1'b0},reg_A[0:30]};
result[32:63]<={{1'b0},reg_A[32:62]};
result[64:95]<={{1'b0},reg_A[64:94]};
result[96:127]<={{1'b0},reg_A[96:126]};
end
5'd2:
begin
result[0:31]<={{2{1'b0}},reg_A[0:29]};
result[32:63]<={{2{1'b0}},reg_A[32:61]};
result[64:95]<={{2{1'b0}},reg_A[64:93]};
result[96:127]<={{2{1'b0}},reg_A[96:125]};
end
5'd3:
begin
result[0:31]<={{3{1'b0}},reg_A[0:28]};
result[32:63]<={{3{1'b0}},reg_A[32:60]};
result[64:95]<={{3{1'b0}},reg_A[64:92]};
result[96:127]<={{3{1'b0}},reg_A[96:124]};
end
5'd4:
begin
result[0:31]<={{4{1'b0}},reg_A[0:27]};
result[32:63]<={{4{1'b0}},reg_A[32:59]};
result[64:95]<={{4{1'b0}},reg_A[64:91]};
result[96:127]<={{4{1'b0}},reg_A[96:123]};
end
5'd5:
begin
result[0:31]<={{5{1'b0}},reg_A[0:26]};
result[32:63]<={{5{1'b0}},reg_A[32:58]};
result[64:95]<={{5{1'b0}},reg_A[64:90]};
result[96:127]<={{5{1'b0}},reg_A[96:122]};
end
5'd6:
begin
result[0:31]<={{6{1'b0}},reg_A[0:25]};
result[32:63]<={{6{1'b0}},reg_A[32:57]};
result[64:95]<={{6{1'b0}},reg_A[64:89]};
result[96:127]<={{6{1'b0}},reg_A[96:121]};
end
5'd7:
begin
result[0:31]<={{7{1'b0}},reg_A[0:24]};
result[32:63]<={{7{1'b0}},reg_A[32:56]};
result[64:95]<={{7{1'b0}},reg_A[64:88]};
result[96:127]<={{7{1'b0}},reg_A[96:120]};
end
5'd8:
begin
result[0:31]<={{8{1'b0}},reg_A[0:23]};
result[32:63]<={{8{1'b0}},reg_A[32:55]};
result[64:95]<={{8{1'b0}},reg_A[64:87]};
result[96:127]<={{8{1'b0}},reg_A[96:119]};
end
5'd9:
begin
result[0:31]<={{9{1'b0}},reg_A[0:22]};
result[32:63]<={{9{1'b0}},reg_A[32:54]};
result[64:95]<={{9{1'b0}},reg_A[64:86]};
result[96:127]<={{9{1'b0}},reg_A[96:118]};
end
5'd10:
begin
result[0:31]<={{10{1'b0}},reg_A[0:21]};
result[32:63]<={{10{1'b0}},reg_A[32:53]};
result[64:95]<={{10{1'b0}},reg_A[64:85]};
result[96:127]<={{10{1'b0}},reg_A[96:117]};
end
5'd11:
begin
result[0:31]<={{11{1'b0}},reg_A[0:20]};
result[32:63]<={{11{1'b0}},reg_A[32:52]};
result[64:95]<={{11{1'b0}},reg_A[64:84]};
result[96:127]<={{11{1'b0}},reg_A[96:116]};
end
5'd12:
begin
result[0:31]<={{12{1'b0}},reg_A[0:19]};
result[32:63]<={{12{1'b0}},reg_A[32:51]};
result[64:95]<={{12{1'b0}},reg_A[64:83]};
result[96:127]<={{12{1'b0}},reg_A[96:115]};
end
5'd13:
begin
result[0:31]<={{13{1'b0}},reg_A[0:18]};
result[32:63]<={{13{1'b0}},reg_A[32:50]};
result[64:95]<={{13{1'b0}},reg_A[64:82]};
result[96:127]<={{13{1'b0}},reg_A[96:114]};
end
5'd14:
begin
result[0:31]<={{14{1'b0}},reg_A[0:17]};
result[32:63]<={{14{1'b0}},reg_A[32:49]};
result[64:95]<={{14{1'b0}},reg_A[64:81]};
result[96:127]<={{14{1'b0}},reg_A[96:113]};
end
5'd15:
begin
result[0:31]<={{15{1'b0}},reg_A[0:16]};
result[32:63]<={{15{1'b0}},reg_A[32:48]};
result[64:95]<={{15{1'b0}},reg_A[64:80]};
result[96:127]<={{15{1'b0}},reg_A[96:112]};
end
5'd16:
begin
result[0:31]<={{16{1'b0}},reg_A[0:15]};
result[32:63]<={{16{1'b0}},reg_A[32:47]};
result[64:95]<={{16{1'b0}},reg_A[64:79]};
result[96:127]<={{16{1'b0}},reg_A[96:111]};
end
5'd17:
begin
result[0:31]<={{17{1'b0}},reg_A[0:14]};
result[32:63]<={{17{1'b0}},reg_A[32:46]};
result[64:95]<={{17{1'b0}},reg_A[64:78]};
result[96:127]<={{17{1'b0}},reg_A[96:110]};
end
5'd18:
begin
result[0:31]<={{18{1'b0}},reg_A[0:13]};
result[32:63]<={{18{1'b0}},reg_A[32:45]};
result[64:95]<={{18{1'b0}},reg_A[64:77]};
result[96:127]<={{18{1'b0}},reg_A[96:109]};
end
5'd19:
begin
result[0:31]<={{19{1'b0}},reg_A[0:12]};
result[32:63]<={{19{1'b0}},reg_A[32:44]};
result[64:95]<={{19{1'b0}},reg_A[64:76]};
result[96:127]<={{19{1'b0}},reg_A[96:108]};
end
5'd20:
begin
result[0:31]<={{20{1'b0}},reg_A[0:11]};
result[32:63]<={{20{1'b0}},reg_A[32:43]};
result[64:95]<={{20{1'b0}},reg_A[64:75]};
result[96:127]<={{20{1'b0}},reg_A[96:107]};
end
5'd21:
begin
result[0:31]<={{21{1'b0}},reg_A[0:10]};
result[32:63]<={{21{1'b0}},reg_A[32:42]};
result[64:95]<={{21{1'b0}},reg_A[64:74]};
result[96:127]<={{21{1'b0}},reg_A[96:106]};
end
5'd22:
begin
result[0:31]<={{22{1'b0}},reg_A[0:9]};
result[32:63]<={{22{1'b0}},reg_A[32:41]};
result[64:95]<={{22{1'b0}},reg_A[64:73]};
result[96:127]<={{22{1'b0}},reg_A[96:105]};
end
5'd23:
begin
result[0:31]<={{23{1'b0}},reg_A[0:8]};
result[32:63]<={{23{1'b0}},reg_A[32:40]};
result[64:95]<={{23{1'b0}},reg_A[64:72]};
result[96:127]<={{23{1'b0}},reg_A[96:104]};
end
5'd24:
begin
result[0:31]<={{24{1'b0}},reg_A[0:7]};
result[32:63]<={{24{1'b0}},reg_A[32:39]};
result[64:95]<={{24{1'b0}},reg_A[64:71]};
result[96:127]<={{24{1'b0}},reg_A[96:103]};
end
5'd25:
begin
result[0:31]<={{25{1'b0}},reg_A[0:6]};
result[32:63]<={{25{1'b0}},reg_A[32:38]};
result[64:95]<={{25{1'b0}},reg_A[64:70]};
result[96:127]<={{25{1'b0}},reg_A[96:102]};
end
5'd26:
begin
result[0:31]<={{26{1'b0}},reg_A[0:5]};
result[32:63]<={{26{1'b0}},reg_A[32:37]};
result[64:95]<={{26{1'b0}},reg_A[64:69]};
result[96:127]<={{26{1'b0}},reg_A[96:101]};
end
5'd27:
begin
result[0:31]<={{27{1'b0}},reg_A[0:4]};
result[32:63]<={{27{1'b0}},reg_A[32:36]};
result[64:95]<={{27{1'b0}},reg_A[64:68]};
result[96:127]<={{27{1'b0}},reg_A[96:100]};
end
5'd28:
begin
result[0:31]<={{28{1'b0}},reg_A[0:3]};
result[32:63]<={{28{1'b0}},reg_A[32:35]};
result[64:95]<={{28{1'b0}},reg_A[64:67]};
result[96:127]<={{28{1'b0}},reg_A[96:99]};
end
5'd29:
begin
result[0:31]<={{29{1'b0}},reg_A[0:2]};
result[32:63]<={{29{1'b0}},reg_A[32:34]};
result[64:95]<={{29{1'b0}},reg_A[64:66]};
result[96:127]<={{29{1'b0}},reg_A[96:98]};
end
5'd30:
begin
result[0:31]<={{30{1'b0}},reg_A[0:1]};
result[32:63]<={{30{1'b0}},reg_A[32:33]};
result[64:95]<={{30{1'b0}},reg_A[64:65]};
result[96:127]<={{30{1'b0}},reg_A[96:97]};
end
5'd31:
begin
result[0:31]<={{31{1'b0}},reg_A[0]};
result[32:63]<={{31{1'b0}},reg_A[32]};
result[64:95]<={{31{1'b0}},reg_A[64]};
result[96:127]<={{31{1'b0}},reg_A[96]};
end
endcase
end
endcase
end
// ==============================================================
// SRAI instruction
`aluwsrai:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={{reg_A[0]},reg_A[0:6]};
result[8:15]<={{reg_A[8]},reg_A[8:14]};
result[16:23]<={{reg_A[16]},reg_A[16:22]};
result[24:31]<={{reg_A[24]},reg_A[24:30]};
result[32:39]<={{reg_A[32]},reg_A[32:38]};
result[40:47]<={{reg_A[40]},reg_A[40:46]};
result[48:55]<={{reg_A[48]},reg_A[48:54]};
result[56:63]<={{reg_A[56]},reg_A[56:62]};
result[64:71]<={{reg_A[64]},reg_A[64:70]};
result[72:79]<={{reg_A[72]},reg_A[72:78]};
result[80:87]<={{reg_A[80]},reg_A[80:86]};
result[88:95]<={{reg_A[88]},reg_A[88:94]};
result[96:103]<={{reg_A[96]},reg_A[96:102]};
result[104:111]<={{reg_A[104]},reg_A[104:110]};
result[112:119]<={{reg_A[112]},reg_A[112:118]};
result[120:127]<={{reg_A[120]},reg_A[120:126]};
end
3'd2:
begin
result[0:7]<={{2{reg_A[0]}},reg_A[0:5]};
result[8:15]<={{2{reg_A[8]}},reg_A[8:13]};
result[16:23]<={{2{reg_A[16]}},reg_A[16:21]};
result[24:31]<={{2{reg_A[24]}},reg_A[24:29]};
result[32:39]<={{2{reg_A[32]}},reg_A[32:37]};
result[40:47]<={{2{reg_A[40]}},reg_A[40:45]};
result[48:55]<={{2{reg_A[48]}},reg_A[48:53]};
result[56:63]<={{2{reg_A[56]}},reg_A[56:61]};
result[64:71]<={{2{reg_A[64]}},reg_A[64:69]};
result[72:79]<={{2{reg_A[72]}},reg_A[72:77]};
result[80:87]<={{2{reg_A[80]}},reg_A[80:85]};
result[88:95]<={{2{reg_A[88]}},reg_A[88:93]};
result[96:103]<={{2{reg_A[96]}},reg_A[96:101]};
result[104:111]<={{2{reg_A[104]}},reg_A[104:109]};
result[112:119]<={{2{reg_A[112]}},reg_A[112:117]};
result[120:127]<={{2{reg_A[120]}},reg_A[120:125]};
end
3'd3:
begin
result[0:7]<={{3{reg_A[0]}},reg_A[0:4]};
result[8:15]<={{3{reg_A[8]}},reg_A[8:12]};
result[16:23]<={{3{reg_A[16]}},reg_A[16:20]};
result[24:31]<={{3{reg_A[24]}},reg_A[24:28]};
result[32:39]<={{3{reg_A[32]}},reg_A[32:36]};
result[40:47]<={{3{reg_A[40]}},reg_A[40:44]};
result[48:55]<={{3{reg_A[48]}},reg_A[48:52]};
result[56:63]<={{3{reg_A[56]}},reg_A[56:60]};
result[64:71]<={{3{reg_A[64]}},reg_A[64:68]};
result[72:79]<={{3{reg_A[72]}},reg_A[72:76]};
result[80:87]<={{3{reg_A[80]}},reg_A[80:84]};
result[88:95]<={{3{reg_A[88]}},reg_A[88:92]};
result[96:103]<={{3{reg_A[96]}},reg_A[96:100]};
result[104:111]<={{3{reg_A[104]}},reg_A[104:108]};
result[112:119]<={{3{reg_A[112]}},reg_A[112:116]};
result[120:127]<={{3{reg_A[120]}},reg_A[120:124]};
end
3'd4:
begin
result[0:7]<={{4{reg_A[0]}},reg_A[0:3]};
result[8:15]<={{4{reg_A[8]}},reg_A[8:11]};
result[16:23]<={{4{reg_A[16]}},reg_A[16:19]};
result[24:31]<={{4{reg_A[24]}},reg_A[24:27]};
result[32:39]<={{4{reg_A[32]}},reg_A[32:35]};
result[40:47]<={{4{reg_A[40]}},reg_A[40:43]};
result[48:55]<={{4{reg_A[48]}},reg_A[48:51]};
result[56:63]<={{4{reg_A[56]}},reg_A[56:69]};
result[64:71]<={{4{reg_A[64]}},reg_A[64:67]};
result[72:79]<={{4{reg_A[72]}},reg_A[72:75]};
result[80:87]<={{4{reg_A[80]}},reg_A[80:83]};
result[88:95]<={{4{reg_A[88]}},reg_A[88:91]};
result[96:103]<={{4{reg_A[96]}},reg_A[96:99]};
result[104:111]<={{4{reg_A[104]}},reg_A[104:107]};
result[112:119]<={{4{reg_A[112]}},reg_A[112:115]};
result[120:127]<={{4{reg_A[120]}},reg_A[120:123]};
end
3'd5:
begin
result[0:7]<={{5{reg_A[0]}},reg_A[0:2]};
result[8:15]<={{5{reg_A[8]}},reg_A[8:10]};
result[16:23]<={{5{reg_A[16]}},reg_A[16:18]};
result[24:31]<={{5{reg_A[24]}},reg_A[24:26]};
result[32:39]<={{5{reg_A[32]}},reg_A[32:34]};
result[40:47]<={{5{reg_A[40]}},reg_A[40:42]};
result[48:55]<={{5{reg_A[48]}},reg_A[48:50]};
result[56:63]<={{5{reg_A[56]}},reg_A[56:68]};
result[64:71]<={{5{reg_A[64]}},reg_A[64:66]};
result[72:79]<={{5{reg_A[72]}},reg_A[72:74]};
result[80:87]<={{5{reg_A[80]}},reg_A[80:82]};
result[88:95]<={{5{reg_A[88]}},reg_A[88:90]};
result[96:103]<={{5{reg_A[96]}},reg_A[96:98]};
result[104:111]<={{5{reg_A[104]}},reg_A[104:106]};
result[112:119]<={{5{reg_A[112]}},reg_A[112:114]};
result[120:127]<={{5{reg_A[120]}},reg_A[120:122]};
end
3'd6:
begin
result[0:7]<={{6{reg_A[0]}},reg_A[0:1]};
result[8:15]<={{6{reg_A[8]}},reg_A[8:9]};
result[16:23]<={{6{reg_A[16]}},reg_A[16:17]};
result[24:31]<={{6{reg_A[24]}},reg_A[24:25]};
result[32:39]<={{6{reg_A[32]}},reg_A[32:33]};
result[40:47]<={{6{reg_A[40]}},reg_A[40:41]};
result[48:55]<={{6{reg_A[48]}},reg_A[48:49]};
result[56:63]<={{6{reg_A[56]}},reg_A[56:67]};
result[64:71]<={{6{reg_A[64]}},reg_A[64:65]};
result[72:79]<={{6{reg_A[72]}},reg_A[72:73]};
result[80:87]<={{6{reg_A[80]}},reg_A[80:81]};
result[88:95]<={{6{reg_A[88]}},reg_A[88:89]};
result[96:103]<={{6{reg_A[96]}},reg_A[96:97]};
result[104:111]<={{6{reg_A[104]}},reg_A[104:105]};
result[112:119]<={{6{reg_A[112]}},reg_A[112:113]};
result[120:127]<={{6{reg_A[120]}},reg_A[120:121]};
end
3'd7:
begin
result[0:7]<={{7{reg_A[0]}},reg_A[0]};
result[8:15]<={{7{reg_A[8]}},reg_A[8]};
result[16:23]<={{7{reg_A[16]}},reg_A[16]};
result[24:31]<={{7{reg_A[24]}},reg_A[24]};
result[32:39]<={{7{reg_A[32]}},reg_A[32]};
result[40:47]<={{7{reg_A[40]}},reg_A[40]};
result[48:55]<={{7{reg_A[48]}},reg_A[48]};
result[56:63]<={{7{reg_A[56]}},reg_A[56]};
result[64:71]<={{7{reg_A[64]}},reg_A[64]};
result[72:79]<={{7{reg_A[72]}},reg_A[72]};
result[80:87]<={{7{reg_A[80]}},reg_A[80]};
result[88:95]<={{7{reg_A[88]}},reg_A[88]};
result[96:103]<={{7{reg_A[96]}},reg_A[96]};
result[104:111]<={{7{reg_A[104]}},reg_A[104]};
result[112:119]<={{7{reg_A[112]}},reg_A[112]};
result[120:127]<={{7{reg_A[120]}},reg_A[120]};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={{reg_A[0]},reg_A[0:14]};
result[16:31]<={{reg_A[16]},reg_A[16:30]};
result[32:47]<={{reg_A[32]},reg_A[32:46]};
result[48:63]<={{reg_A[48]},reg_A[48:62]};
result[64:79]<={{reg_A[64]},reg_A[64:78]};
result[80:95]<={{reg_A[80]},reg_A[80:94]};
result[96:111]<={{reg_A[96]},reg_A[96:110]};
result[112:127]<={{reg_A[112]},reg_A[112:126]};
end
4'd2:
begin
result[0:15]<={{2{reg_A[0]}},reg_A[0:13]};
result[16:31]<={{2{reg_A[16]}},reg_A[16:29]};
result[32:47]<={{2{reg_A[32]}},reg_A[32:45]};
result[48:63]<={{2{reg_A[48]}},reg_A[48:61]};
result[64:79]<={{2{reg_A[64]}},reg_A[64:77]};
result[80:95]<={{2{reg_A[80]}},reg_A[80:93]};
result[96:111]<={{2{reg_A[96]}},reg_A[96:109]};
result[112:127]<={{2{reg_A[112]}},reg_A[112:125]};
end
4'd3:
begin
result[0:15]<={{3{reg_A[0]}},reg_A[0:12]};
result[16:31]<={{3{reg_A[16]}},reg_A[16:28]};
result[32:47]<={{3{reg_A[32]}},reg_A[32:44]};
result[48:63]<={{3{reg_A[48]}},reg_A[48:60]};
result[64:79]<={{3{reg_A[64]}},reg_A[64:76]};
result[80:95]<={{3{reg_A[80]}},reg_A[80:92]};
result[96:111]<={{3{reg_A[96]}},reg_A[96:108]};
result[112:127]<={{3{reg_A[112]}},reg_A[112:124]};
end
4'd4:
begin
result[0:15]<={{4{reg_A[0]}},reg_A[0:11]};
result[16:31]<={{4{reg_A[8]}},reg_A[16:27]};
result[32:47]<={{4{reg_A[16]}},reg_A[32:43]};
result[48:63]<={{4{reg_A[32]}},reg_A[48:59]};
result[64:79]<={{4{reg_A[48]}},reg_A[64:75]};
result[80:95]<={{4{reg_A[64]}},reg_A[80:91]};
result[96:111]<={{4{reg_A[80]}},reg_A[96:107]};
result[112:127]<={{4{reg_A[112]}},reg_A[112:123]};
end
4'd5:
begin
result[0:15]<={{5{reg_A[0]}},reg_A[0:10]};
result[16:31]<={{5{reg_A[16]}},reg_A[16:26]};
result[32:47]<={{5{reg_A[32]}},reg_A[32:42]};
result[48:63]<={{5{reg_A[48]}},reg_A[48:58]};
result[64:79]<={{5{reg_A[64]}},reg_A[64:74]};
result[80:95]<={{5{reg_A[80]}},reg_A[80:90]};
result[96:111]<={{5{reg_A[96]}},reg_A[96:106]};
result[112:127]<={{5{reg_A[112]}},reg_A[112:122]};
end
4'd6:
begin
result[0:15]<={{6{reg_A[0]}},reg_A[0:9]};
result[16:31]<={{6{reg_A[16]}},reg_A[16:25]};
result[32:47]<={{6{reg_A[32]}},reg_A[32:41]};
result[48:63]<={{6{reg_A[48]}},reg_A[48:57]};
result[64:79]<={{6{reg_A[64]}},reg_A[64:73]};
result[80:95]<={{6{reg_A[80]}},reg_A[80:89]};
result[96:111]<={{6{reg_A[96]}},reg_A[96:105]};
result[112:127]<={{6{reg_A[112]}},reg_A[112:121]};
end
4'd7:
begin
result[0:15]<={{7{reg_A[0]}},reg_A[0:8]};
result[16:31]<={{7{reg_A[16]}},reg_A[16:24]};
result[32:47]<={{7{reg_A[32]}},reg_A[32:40]};
result[48:63]<={{7{reg_A[48]}},reg_A[48:56]};
result[64:79]<={{7{reg_A[64]}},reg_A[64:72]};
result[80:95]<={{7{reg_A[80]}},reg_A[80:88]};
result[96:111]<={{7{reg_A[96]}},reg_A[96:104]};
result[112:127]<={{7{reg_A[112]}},reg_A[112:120]};
end
4'd8:
begin
result[0:15]<={{8{reg_A[0]}},reg_A[0:7]};
result[16:31]<={{8{reg_A[16]}},reg_A[16:23]};
result[32:47]<={{8{reg_A[32]}},reg_A[32:39]};
result[48:63]<={{8{reg_A[48]}},reg_A[48:55]};
result[64:79]<={{8{reg_A[64]}},reg_A[64:71]};
result[80:95]<={{8{reg_A[80]}},reg_A[80:87]};
result[96:111]<={{8{reg_A[96]}},reg_A[96:103]};
result[112:127]<={{8{reg_A[112]}},reg_A[112:119]};
end
4'd9:
begin
result[0:15]<={{9{reg_A[0]}},reg_A[0:6]};
result[16:31]<={{9{reg_A[16]}},reg_A[16:22]};
result[32:47]<={{9{reg_A[32]}},reg_A[32:38]};
result[48:63]<={{9{reg_A[48]}},reg_A[48:54]};
result[64:79]<={{9{reg_A[64]}},reg_A[64:70]};
result[80:95]<={{9{reg_A[80]}},reg_A[80:86]};
result[96:111]<={{9{reg_A[96]}},reg_A[96:102]};
result[112:127]<={{9{reg_A[112]}},reg_A[112:118]};
end
4'd10:
begin
result[0:15]<={{10{reg_A[0]}},reg_A[0:5]};
result[16:31]<={{10{reg_A[16]}},reg_A[16:21]};
result[32:47]<={{10{reg_A[32]}},reg_A[32:37]};
result[48:63]<={{10{reg_A[48]}},reg_A[48:53]};
result[64:79]<={{10{reg_A[64]}},reg_A[64:69]};
result[80:95]<={{10{reg_A[80]}},reg_A[80:85]};
result[96:111]<={{10{reg_A[96]}},reg_A[96:101]};
result[112:127]<={{10{reg_A[112]}},reg_A[112:117]};
end
4'd11:
begin
result[0:15]<={{11{reg_A[0]}},reg_A[0:4]};
result[16:31]<={{11{reg_A[16]}},reg_A[16:20]};
result[32:47]<={{11{reg_A[32]}},reg_A[32:36]};
result[48:63]<={{11{reg_A[48]}},reg_A[48:52]};
result[64:79]<={{11{reg_A[64]}},reg_A[64:68]};
result[80:95]<={{11{reg_A[80]}},reg_A[80:84]};
result[96:111]<={{11{reg_A[96]}},reg_A[96:100]};
result[112:127]<={{11{reg_A[112]}},reg_A[112:116]};
end
4'd12:
begin
result[0:15]<={{12{reg_A[0]}},reg_A[0:3]};
result[16:31]<={{12{reg_A[16]}},reg_A[16:19]};
result[32:47]<={{12{reg_A[32]}},reg_A[32:35]};
result[48:63]<={{12{reg_A[48]}},reg_A[48:51]};
result[64:79]<={{12{reg_A[64]}},reg_A[64:67]};
result[80:95]<={{12{reg_A[80]}},reg_A[80:83]};
result[96:111]<={{12{reg_A[96]}},reg_A[96:99]};
result[112:127]<={{12{reg_A[112]}},reg_A[112:115]};
end
4'd13:
begin
result[0:15]<={{13{reg_A[0]}},reg_A[0:2]};
result[16:31]<={{13{reg_A[16]}},reg_A[16:18]};
result[32:47]<={{13{reg_A[32]}},reg_A[32:34]};
result[48:63]<={{13{reg_A[48]}},reg_A[48:50]};
result[64:79]<={{13{reg_A[64]}},reg_A[64:66]};
result[80:95]<={{13{reg_A[80]}},reg_A[80:82]};
result[96:111]<={{13{reg_A[96]}},reg_A[96:98]};
result[112:127]<={{13{reg_A[112]}},reg_A[112:114]};
end
4'd14:
begin
result[0:15]<={{14{reg_A[0]}},reg_A[0:1]};
result[16:31]<={{14{reg_A[16]}},reg_A[16:17]};
result[32:47]<={{14{reg_A[32]}},reg_A[32:33]};
result[48:63]<={{14{reg_A[48]}},reg_A[48:49]};
result[64:79]<={{14{reg_A[64]}},reg_A[64:65]};
result[80:95]<={{14{reg_A[80]}},reg_A[80:81]};
result[96:111]<={{14{reg_A[96]}},reg_A[96:97]};
result[112:127]<={{14{reg_A[112]}},reg_A[112:113]};
end
4'd15:
begin
result[0:15]<={{15{reg_A[0]}},reg_A[0]};
result[16:31]<={{15{reg_A[16]}},reg_A[16]};
result[32:47]<={{15{reg_A[32]}},reg_A[32]};
result[48:63]<={{15{reg_A[48]}},reg_A[48]};
result[64:79]<={{15{reg_A[64]}},reg_A[64]};
result[80:95]<={{15{reg_A[80]}},reg_A[80]};
result[96:111]<={{15{reg_A[96]}},reg_A[96]};
result[112:127]<={{15{reg_A[112]}},reg_A[112]};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={{reg_A[0]},reg_A[0:30]};
result[32:63]<={{reg_A[32]},reg_A[32:62]};
result[64:95]<={{reg_A[64]},reg_A[64:94]};
result[96:127]<={{reg_A[96]},reg_A[96:126]};
end
5'd2:
begin
result[0:31]<={{2{reg_A[0]}},reg_A[0:29]};
result[32:63]<={{2{reg_A[32]}},reg_A[32:61]};
result[64:95]<={{2{reg_A[64]}},reg_A[64:93]};
result[96:127]<={{2{reg_A[96]}},reg_A[96:125]};
end
5'd3:
begin
result[0:31]<={{3{reg_A[0]}},reg_A[0:28]};
result[32:63]<={{3{reg_A[32]}},reg_A[32:60]};
result[64:95]<={{3{reg_A[64]}},reg_A[64:92]};
result[96:127]<={{3{reg_A[96]}},reg_A[96:124]};
end
5'd4:
begin
result[0:31]<={{4{reg_A[0]}},reg_A[0:27]};
result[32:63]<={{4{reg_A[32]}},reg_A[32:59]};
result[64:95]<={{4{reg_A[64]}},reg_A[64:91]};
result[96:127]<={{4{reg_A[96]}},reg_A[96:123]};
end
5'd5:
begin
result[0:31]<={{5{reg_A[0]}},reg_A[0:26]};
result[32:63]<={{5{reg_A[32]}},reg_A[32:58]};
result[64:95]<={{5{reg_A[64]}},reg_A[64:90]};
result[96:127]<={{5{reg_A[96]}},reg_A[96:122]};
end
5'd6:
begin
result[0:31]<={{6{reg_A[0]}},reg_A[0:25]};
result[32:63]<={{6{reg_A[32]}},reg_A[32:57]};
result[64:95]<={{6{reg_A[64]}},reg_A[64:89]};
result[96:127]<={{6{reg_A[96]}},reg_A[96:121]};
end
5'd7:
begin
result[0:31]<={{7{reg_A[0]}},reg_A[0:24]};
result[32:63]<={{7{reg_A[32]}},reg_A[32:56]};
result[64:95]<={{7{reg_A[64]}},reg_A[64:88]};
result[96:127]<={{7{reg_A[96]}},reg_A[96:120]};
end
5'd8:
begin
result[0:31]<={{8{reg_A[0]}},reg_A[0:23]};
result[32:63]<={{8{reg_A[32]}},reg_A[32:55]};
result[64:95]<={{8{reg_A[64]}},reg_A[64:87]};
result[96:127]<={{8{reg_A[96]}},reg_A[96:119]};
end
5'd9:
begin
result[0:31]<={{9{reg_A[0]}},reg_A[0:22]};
result[32:63]<={{9{reg_A[32]}},reg_A[32:54]};
result[64:95]<={{9{reg_A[64]}},reg_A[64:86]};
result[96:127]<={{9{reg_A[96]}},reg_A[96:118]};
end
5'd10:
begin
result[0:31]<={{10{reg_A[0]}},reg_A[0:21]};
result[32:63]<={{10{reg_A[32]}},reg_A[32:53]};
result[64:95]<={{10{reg_A[64]}},reg_A[64:85]};
result[96:127]<={{10{reg_A[96]}},reg_A[96:117]};
end
5'd11:
begin
result[0:31]<={{11{reg_A[0]}},reg_A[0:20]};
result[32:63]<={{11{reg_A[32]}},reg_A[32:52]};
result[64:95]<={{11{reg_A[64]}},reg_A[64:84]};
result[96:127]<={{11{reg_A[96]}},reg_A[96:116]};
end
5'd12:
begin
result[0:31]<={{12{reg_A[0]}},reg_A[0:19]};
result[32:63]<={{12{reg_A[32]}},reg_A[32:51]};
result[64:95]<={{12{reg_A[64]}},reg_A[64:83]};
result[96:127]<={{12{reg_A[96]}},reg_A[96:115]};
end
5'd13:
begin
result[0:31]<={{13{reg_A[0]}},reg_A[0:18]};
result[32:63]<={{13{reg_A[32]}},reg_A[32:50]};
result[64:95]<={{13{reg_A[64]}},reg_A[64:82]};
result[96:127]<={{13{reg_A[96]}},reg_A[96:114]};
end
5'd14:
begin
result[0:31]<={{14{reg_A[0]}},reg_A[0:17]};
result[32:63]<={{14{reg_A[32]}},reg_A[32:49]};
result[64:95]<={{14{reg_A[64]}},reg_A[64:81]};
result[96:127]<={{14{reg_A[96]}},reg_A[96:113]};
end
5'd15:
begin
result[0:31]<={{15{reg_A[0]}},reg_A[0:16]};
result[32:63]<={{15{reg_A[32]}},reg_A[32:48]};
result[64:95]<={{15{reg_A[64]}},reg_A[64:80]};
result[96:127]<={{15{reg_A[96]}},reg_A[96:112]};
end
5'd16:
begin
result[0:31]<={{16{reg_A[0]}},reg_A[0:15]};
result[32:63]<={{16{reg_A[32]}},reg_A[32:47]};
result[64:95]<={{16{reg_A[64]}},reg_A[64:79]};
result[96:127]<={{16{reg_A[96]}},reg_A[96:111]};
end
5'd17:
begin
result[0:31]<={{17{reg_A[0]}},reg_A[0:14]};
result[32:63]<={{17{reg_A[32]}},reg_A[32:46]};
result[64:95]<={{17{reg_A[64]}},reg_A[64:78]};
result[96:127]<={{17{reg_A[96]}},reg_A[96:110]};
end
5'd18:
begin
result[0:31]<={{18{reg_A[0]}},reg_A[0:13]};
result[32:63]<={{18{reg_A[32]}},reg_A[32:45]};
result[64:95]<={{18{reg_A[64]}},reg_A[64:77]};
result[96:127]<={{18{reg_A[96]}},reg_A[96:109]};
end
5'd19:
begin
result[0:31]<={{19{reg_A[0]}},reg_A[0:12]};
result[32:63]<={{19{reg_A[32]}},reg_A[32:44]};
result[64:95]<={{19{reg_A[64]}},reg_A[64:76]};
result[96:127]<={{19{reg_A[96]}},reg_A[96:108]};
end
5'd20:
begin
result[0:31]<={{20{reg_A[0]}},reg_A[0:11]};
result[32:63]<={{20{reg_A[32]}},reg_A[32:43]};
result[64:95]<={{20{reg_A[64]}},reg_A[64:75]};
result[96:127]<={{20{reg_A[96]}},reg_A[96:107]};
end
5'd21:
begin
result[0:31]<={{21{reg_A[0]}},reg_A[0:10]};
result[32:63]<={{21{reg_A[32]}},reg_A[32:42]};
result[64:95]<={{21{reg_A[64]}},reg_A[64:74]};
result[96:127]<={{21{reg_A[96]}},reg_A[96:106]};
end
5'd22:
begin
result[0:31]<={{22{reg_A[0]}},reg_A[0:9]};
result[32:63]<={{22{reg_A[32]}},reg_A[32:41]};
result[64:95]<={{22{reg_A[64]}},reg_A[64:73]};
result[96:127]<={{22{reg_A[96]}},reg_A[96:105]};
end
5'd23:
begin
result[0:31]<={{23{reg_A[0]}},reg_A[0:8]};
result[32:63]<={{23{reg_A[32]}},reg_A[32:40]};
result[64:95]<={{23{reg_A[64]}},reg_A[64:72]};
result[96:127]<={{23{reg_A[96]}},reg_A[96:104]};
end
5'd24:
begin
result[0:31]<={{24{reg_A[0]}},reg_A[0:7]};
result[32:63]<={{24{reg_A[32]}},reg_A[32:39]};
result[64:95]<={{24{reg_A[64]}},reg_A[64:71]};
result[96:127]<={{24{reg_A[96]}},reg_A[96:103]};
end
5'd25:
begin
result[0:31]<={{25{reg_A[0]}},reg_A[0:6]};
result[32:63]<={{25{reg_A[32]}},reg_A[32:38]};
result[64:95]<={{25{reg_A[64]}},reg_A[64:70]};
result[96:127]<={{25{reg_A[96]}},reg_A[96:102]};
end
5'd26:
begin
result[0:31]<={{26{reg_A[0]}},reg_A[0:5]};
result[32:63]<={{26{reg_A[32]}},reg_A[32:37]};
result[64:95]<={{26{reg_A[64]}},reg_A[64:69]};
result[96:127]<={{26{reg_A[96]}},reg_A[96:101]};
end
5'd27:
begin
result[0:31]<={{27{reg_A[0]}},reg_A[0:4]};
result[32:63]<={{27{reg_A[32]}},reg_A[32:36]};
result[64:95]<={{27{reg_A[64]}},reg_A[64:68]};
result[96:127]<={{27{reg_A[96]}},reg_A[96:100]};
end
5'd28:
begin
result[0:31]<={{28{reg_A[0]}},reg_A[0:3]};
result[32:63]<={{28{reg_A[32]}},reg_A[32:35]};
result[64:95]<={{28{reg_A[64]}},reg_A[64:67]};
result[96:127]<={{28{reg_A[96]}},reg_A[96:99]};
end
5'd29:
begin
result[0:31]<={{29{reg_A[0]}},reg_A[0:2]};
result[32:63]<={{29{reg_A[32]}},reg_A[32:34]};
result[64:95]<={{29{reg_A[64]}},reg_A[64:66]};
result[96:127]<={{29{reg_A[96]}},reg_A[96:98]};
end
5'd30:
begin
result[0:31]<={{30{reg_A[0]}},reg_A[0:1]};
result[32:63]<={{30{reg_A[32]}},reg_A[32:33]};
result[64:95]<={{30{reg_A[64]}},reg_A[64:65]};
result[96:127]<={{30{reg_A[96]}},reg_A[96:97]};
end
5'd31:
begin
result[0:31]<={{31{reg_A[0]}},reg_A[0]};
result[32:63]<={{31{reg_A[32]}},reg_A[32]};
result[64:95]<={{31{reg_A[64]}},reg_A[64]};
result[96:127]<={{31{reg_A[96]}},reg_A[96]};
end
endcase
end
endcase
end
// ==============================================================
// SRA instruction
`aluwsra:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[5:7]) // byte 0
3'd0:
result[0:7]<=reg_A[0:7];
3'd1:
result[0:7]<={{1{reg_A[0]}},reg_A[0:6]};
3'd2:
result[0:7]<={{2{reg_A[0]}},reg_A[0:5]};
3'd3:
result[0:7]<={{3{reg_A[0]}},reg_A[0:4]};
3'd4:
result[0:7]<={{4{reg_A[0]}},reg_A[0:3]};
3'd5:
result[0:7]<={{5{reg_A[0]}},reg_A[0:2]};
3'd6:
result[0:7]<={{6{reg_A[0]}},reg_A[0:1]};
3'd7:
result[0:7]<={{7{reg_A[0]}},reg_A[0]};
endcase
case(reg_B[13:15]) // byte 1
3'd0:
result[8:15]<=reg_A[8:15];
3'd1:
result[8:15]<={{1{reg_A[8]}},reg_A[8:14]};
3'd2:
result[8:15]<={{2{reg_A[8]}},reg_A[8:13]};
3'd3:
result[8:15]<={{3{reg_A[8]}},reg_A[8:12]};
3'd4:
result[8:15]<={{4{reg_A[8]}},reg_A[8:11]};
3'd5:
result[8:15]<={{5{reg_A[8]}},reg_A[8:10]};
3'd6:
result[8:15]<={{6{reg_A[8]}},reg_A[8:9]};
3'd7:
result[8:15]<={{7{reg_A[8]}},reg_A[8]};
endcase
case(reg_B[21:23]) // byte 2
3'd0:
result[16:23]<=reg_A[16:23];
3'd1:
result[16:23]<={{1{reg_A[16]}},reg_A[16:22]};
3'd2:
result[16:23]<={{2{reg_A[16]}},reg_A[16:21]};
3'd3:
result[16:23]<={{3{reg_A[16]}},reg_A[16:20]};
3'd4:
result[16:23]<={{4{reg_A[16]}},reg_A[16:19]};
3'd5:
result[16:23]<={{5{reg_A[16]}},reg_A[16:18]};
3'd6:
result[16:23]<={{6{reg_A[16]}},reg_A[16:17]};
3'd7:
result[16:23]<={{7{reg_A[16]}},reg_A[16]};
endcase
case(reg_B[29:31]) // byte 3
3'd0:
result[24:31]<=reg_A[24:31];
3'd1:
result[24:31]<={{1{reg_A[24]}},reg_A[24:30]};
3'd2:
result[24:31]<={{2{reg_A[24]}},reg_A[24:29]};
3'd3:
result[24:31]<={{3{reg_A[24]}},reg_A[24:28]};
3'd4:
result[24:31]<={{4{reg_A[24]}},reg_A[24:27]};
3'd5:
result[24:31]<={{5{reg_A[24]}},reg_A[24:26]};
3'd6:
result[24:31]<={{6{reg_A[24]}},reg_A[24:25]};
3'd7:
result[24:31]<={{7{reg_A[24]}},reg_A[24]};
endcase
case(reg_B[37:39]) // byte 4
3'd0:
result[32:39]<=reg_A[32:39];
3'd1:
result[32:39]<={{1{reg_A[32]}},reg_A[32:38]};
3'd2:
result[32:39]<={{2{reg_A[32]}},reg_A[32:37]};
3'd3:
result[32:39]<={{3{reg_A[32]}},reg_A[32:36]};
3'd4:
result[32:39]<={{4{reg_A[32]}},reg_A[32:35]};
3'd5:
result[32:39]<={{5{reg_A[32]}},reg_A[32:34]};
3'd6:
result[32:39]<={{6{reg_A[32]}},reg_A[32:33]};
3'd7:
result[32:39]<={{7{reg_A[32]}},reg_A[32]};
endcase
case(reg_B[45:47]) // byte 5
3'd0:
result[40:47]<=reg_A[40:47];
3'd1:
result[40:47]<={{1{reg_A[40]}},reg_A[40:46]};
3'd2:
result[40:47]<={{2{reg_A[40]}},reg_A[40:45]};
3'd3:
result[40:47]<={{3{reg_A[40]}},reg_A[40:44]};
3'd4:
result[40:47]<={{4{reg_A[40]}},reg_A[40:43]};
3'd5:
result[40:47]<={{5{reg_A[40]}},reg_A[40:42]};
3'd6:
result[40:47]<={{6{reg_A[40]}},reg_A[40:41]};
3'd7:
result[40:47]<={{7{reg_A[40]}},reg_A[40]};
endcase
case(reg_B[53:55]) // byte 6
3'd0:
result[48:55]<=reg_A[48:55];
3'd1:
result[48:55]<={{1{reg_A[48]}},reg_A[48:54]};
3'd2:
result[48:55]<={{2{reg_A[48]}},reg_A[48:53]};
3'd3:
result[48:55]<={{3{reg_A[48]}},reg_A[48:52]};
3'd4:
result[48:55]<={{4{reg_A[48]}},reg_A[48:51]};
3'd5:
result[48:55]<={{5{reg_A[48]}},reg_A[48:50]};
3'd6:
result[48:55]<={{6{reg_A[48]}},reg_A[48:49]};
3'd7:
result[48:55]<={{7{reg_A[48]}},reg_A[48]};
endcase
case(reg_B[61:63]) // byte 7
3'd0:
result[56:63]<=reg_A[56:63];
3'd1:
result[56:63]<={{1{reg_A[56]}},reg_A[56:62]};
3'd2:
result[56:63]<={{2{reg_A[56]}},reg_A[56:61]};
3'd3:
result[56:63]<={{3{reg_A[56]}},reg_A[56:60]};
3'd4:
result[56:63]<={{4{reg_A[56]}},reg_A[56:59]};
3'd5:
result[56:63]<={{5{reg_A[56]}},reg_A[56:58]};
3'd6:
result[56:63]<={{6{reg_A[56]}},reg_A[56:57]};
3'd7:
result[56:63]<={{7{reg_A[56]}},reg_A[56]};
endcase
case(reg_B[69:71]) // byte 8
3'd0:
result[64:71]<=reg_A[64:71];
3'd1:
result[64:71]<={{1{reg_A[64]}},reg_A[64:70]};
3'd2:
result[64:71]<={{2{reg_A[64]}},reg_A[64:69]};
3'd3:
result[64:71]<={{3{reg_A[64]}},reg_A[64:68]};
3'd4:
result[64:71]<={{4{reg_A[64]}},reg_A[64:67]};
3'd5:
result[64:71]<={{5{reg_A[64]}},reg_A[64:66]};
3'd6:
result[64:71]<={{6{reg_A[64]}},reg_A[64:65]};
3'd7:
result[64:71]<={{7{reg_A[64]}},reg_A[64]};
endcase
case(reg_B[77:79]) // byte 9
3'd0:
result[72:79]<=reg_A[72:79];
3'd1:
result[72:79]<={{1{reg_A[72]}},reg_A[72:78]};
3'd2:
result[72:79]<={{2{reg_A[72]}},reg_A[72:77]};
3'd3:
result[72:79]<={{3{reg_A[72]}},reg_A[72:76]};
3'd4:
result[72:79]<={{4{reg_A[72]}},reg_A[72:75]};
3'd5:
result[72:79]<={{5{reg_A[72]}},reg_A[72:74]};
3'd6:
result[72:79]<={{6{reg_A[72]}},reg_A[72:73]};
3'd7:
result[72:79]<={{7{reg_A[72]}},reg_A[72]};
endcase
case(reg_B[85:87]) // byte 10
3'd0:
result[80:87]<=reg_A[80:87];
3'd1:
result[80:87]<={{1{reg_A[80]}},reg_A[80:86]};
3'd2:
result[80:87]<={{2{reg_A[80]}},reg_A[80:85]};
3'd3:
result[80:87]<={{3{reg_A[80]}},reg_A[80:84]};
3'd4:
result[80:87]<={{4{reg_A[80]}},reg_A[80:83]};
3'd5:
result[80:87]<={{5{reg_A[80]}},reg_A[80:82]};
3'd6:
result[80:87]<={{6{reg_A[80]}},reg_A[80:81]};
3'd7:
result[80:87]<={{7{reg_A[80]}},reg_A[80]};
endcase
case(reg_B[93:95]) // byte 11
3'd0:
result[88:95]<=reg_A[88:95];
3'd1:
result[88:95]<={{1{reg_A[88]}},reg_A[88:94]};
3'd2:
result[88:95]<={{2{reg_A[88]}},reg_A[88:93]};
3'd3:
result[88:95]<={{3{reg_A[88]}},reg_A[88:92]};
3'd4:
result[88:95]<={{4{reg_A[88]}},reg_A[88:91]};
3'd5:
result[88:95]<={{5{reg_A[88]}},reg_A[88:90]};
3'd6:
result[88:95]<={{6{reg_A[88]}},reg_A[88:89]};
3'd7:
result[88:95]<={{7{reg_A[88]}},reg_A[88]};
endcase
case(reg_B[101:103]) // byte 12
3'd0:
result[96:103]<=reg_A[96:103];
3'd1:
result[96:103]<={{1{reg_A[96]}},reg_A[96:102]};
3'd2:
result[96:103]<={{2{reg_A[96]}},reg_A[96:101]};
3'd3:
result[96:103]<={{3{reg_A[96]}},reg_A[96:100]};
3'd4:
result[96:103]<={{4{reg_A[96]}},reg_A[96:99]};
3'd5:
result[96:103]<={{5{reg_A[96]}},reg_A[96:98]};
3'd6:
result[96:103]<={{6{reg_A[96]}},reg_A[96:97]};
3'd7:
result[96:103]<={{7{reg_A[96]}},reg_A[96]};
endcase
case(reg_B[109:111]) // byte 13
3'd0:
result[104:111]<=reg_A[104:111];
3'd1:
result[104:111]<={{1{reg_A[104]}},reg_A[104:110]};
3'd2:
result[104:111]<={{2{reg_A[104]}},reg_A[104:109]};
3'd3:
result[104:111]<={{3{reg_A[104]}},reg_A[104:108]};
3'd4:
result[104:111]<={{4{reg_A[104]}},reg_A[104:107]};
3'd5:
result[104:111]<={{5{reg_A[104]}},reg_A[104:106]};
3'd6:
result[104:111]<={{6{reg_A[104]}},reg_A[104:105]};
3'd7:
result[104:111]<={{7{reg_A[104]}},reg_A[104]};
endcase
case(reg_B[117:119]) // byte 14
3'd0:
result[112:119]<=reg_A[112:119];
3'd1:
result[112:119]<={{1{reg_A[112]}},reg_A[112:118]};
3'd2:
result[112:119]<={{2{reg_A[112]}},reg_A[112:117]};
3'd3:
result[112:119]<={{3{reg_A[112]}},reg_A[112:116]};
3'd4:
result[112:119]<={{4{reg_A[112]}},reg_A[112:115]};
3'd5:
result[112:119]<={{5{reg_A[112]}},reg_A[112:114]};
3'd6:
result[112:119]<={{6{reg_A[112]}},reg_A[112:113]};
3'd7:
result[112:119]<={{7{reg_A[112]}},reg_A[112]};
endcase
case(reg_B[125:127]) // byte 15
3'd0:
result[120:127]<=reg_A[120:127];
3'd1:
result[120:127]<={{1{reg_A[120]}},reg_A[120:126]};
3'd2:
result[120:127]<={{2{reg_A[120]}},reg_A[120:125]};
3'd3:
result[120:127]<={{3{reg_A[120]}},reg_A[120:124]};
3'd4:
result[120:127]<={{4{reg_A[120]}},reg_A[120:123]};
3'd5:
result[120:127]<={{5{reg_A[120]}},reg_A[120:122]};
3'd6:
result[120:127]<={{6{reg_A[120]}},reg_A[120:121]};
3'd7:
result[120:127]<={{7{reg_A[120]}},reg_A[120]};
endcase
end
`w16:
begin
case(reg_B[12:15]) // word0
4'd0:
result[0:15]<=reg_A[0:15];
4'd1:
result[0:15]<={{1{reg_A[0]}},reg_A[0:14]};
4'd2:
result[0:15]<={{2{reg_A[0]}},reg_A[0:13]};
4'd3:
result[0:15]<={{3{reg_A[0]}},reg_A[0:12]};
4'd4:
result[0:15]<={{4{reg_A[0]}},reg_A[0:11]};
4'd5:
result[0:15]<={{5{reg_A[0]}},reg_A[0:10]};
4'd6:
result[0:15]<={{6{reg_A[0]}},reg_A[0:9]};
4'd7:
result[0:15]<={{7{reg_A[0]}},reg_A[0:8]};
4'd8:
result[0:15]<={{8{reg_A[0]}},reg_A[0:7]};
4'd9:
result[0:15]<={{9{reg_A[0]}},reg_A[0:6]};
4'd10:
result[0:15]<={{10{reg_A[0]}},reg_A[0:5]};
4'd11:
result[0:15]<={{11{reg_A[0]}},reg_A[0:4]};
4'd12:
result[0:15]<={{12{reg_A[0]}},reg_A[0:3]};
4'd13:
result[0:15]<={{13{reg_A[0]}},reg_A[0:2]};
4'd14:
result[0:15]<={{14{reg_A[0]}},reg_A[0:1]};
4'd15:
result[0:15]<={{15{reg_A[0]}},reg_A[0]};
endcase
case(reg_B[28:31]) //word1
4'd0:
result[16:31]<=reg_A[16:31];
4'd1:
result[16:31]<={{1{reg_A[16]}},reg_A[16:30]};
4'd2:
result[16:31]<={{2{reg_A[16]}},reg_A[16:29]};
4'd3:
result[16:31]<={{3{reg_A[16]}},reg_A[16:28]};
4'd4:
result[16:31]<={{4{reg_A[16]}},reg_A[16:27]};
4'd5:
result[16:31]<={{5{reg_A[16]}},reg_A[16:26]};
4'd6:
result[16:31]<={{6{reg_A[16]}},reg_A[16:25]};
4'd7:
result[16:31]<={{7{reg_A[16]}},reg_A[16:24]};
4'd8:
result[16:31]<={{8{reg_A[16]}},reg_A[16:23]};
4'd9:
result[16:31]<={{9{reg_A[16]}},reg_A[16:22]};
4'd10:
result[16:31]<={{10{reg_A[16]}},reg_A[16:21]};
4'd11:
result[16:31]<={{11{reg_A[16]}},reg_A[16:20]};
4'd12:
result[16:31]<={{12{reg_A[16]}},reg_A[16:19]};
4'd13:
result[16:31]<={{13{reg_A[16]}},reg_A[16:18]};
4'd14:
result[16:31]<={{14{reg_A[16]}},reg_A[16:17]};
4'd15:
result[16:31]<={{15{reg_A[16]}},reg_A[16]};
endcase
case(reg_B[44:47]) // word2
4'd0:
result[32:47]<=reg_A[32:47];
4'd1:
result[32:47]<={{1{reg_A[32]}},reg_A[32:46]};
4'd2:
result[32:47]<={{2{reg_A[32]}},reg_A[32:45]};
4'd3:
result[32:47]<={{3{reg_A[32]}},reg_A[32:44]};
4'd4:
result[32:47]<={{4{reg_A[32]}},reg_A[32:43]};
4'd5:
result[32:47]<={{5{reg_A[32]}},reg_A[32:42]};
4'd6:
result[32:47]<={{6{reg_A[32]}},reg_A[32:41]};
4'd7:
result[32:47]<={{7{reg_A[32]}},reg_A[32:40]};
4'd8:
result[32:47]<={{8{reg_A[32]}},reg_A[32:39]};
4'd9:
result[32:47]<={{9{reg_A[32]}},reg_A[32:38]};
4'd10:
result[32:47]<={{10{reg_A[32]}},reg_A[32:37]};
4'd11:
result[32:47]<={{11{reg_A[32]}},reg_A[32:36]};
4'd12:
result[32:47]<={{12{reg_A[32]}},reg_A[32:35]};
4'd13:
result[32:47]<={{13{reg_A[32]}},reg_A[32:34]};
4'd14:
result[32:47]<={{14{reg_A[32]}},reg_A[32:33]};
4'd15:
result[32:47]<={{15{reg_A[32]}},reg_A[32]};
endcase
case(reg_B[60:63]) // word3
4'd0:
result[48:63]<=reg_A[48:63];
4'd1:
result[48:63]<={{1{reg_A[48]}},reg_A[48:62]};
4'd2:
result[48:63]<={{2{reg_A[48]}},reg_A[48:61]};
4'd3:
result[48:63]<={{3{reg_A[48]}},reg_A[48:60]};
4'd4:
result[48:63]<={{4{reg_A[48]}},reg_A[48:59]};
4'd5:
result[48:63]<={{5{reg_A[48]}},reg_A[48:58]};
4'd6:
result[48:63]<={{6{reg_A[48]}},reg_A[48:57]};
4'd7:
result[48:63]<={{7{reg_A[48]}},reg_A[48:56]};
4'd8:
result[48:63]<={{8{reg_A[48]}},reg_A[48:55]};
4'd9:
result[48:63]<={{9{reg_A[48]}},reg_A[48:54]};
4'd10:
result[48:63]<={{10{reg_A[48]}},reg_A[48:53]};
4'd11:
result[48:63]<={{11{reg_A[48]}},reg_A[48:52]};
4'd12:
result[48:63]<={{12{reg_A[48]}},reg_A[48:51]};
4'd13:
result[48:63]<={{13{reg_A[48]}},reg_A[48:50]};
4'd14:
result[48:63]<={{14{reg_A[48]}},reg_A[48:49]};
4'd15:
result[48:63]<={{15{reg_A[48]}},reg_A[48]};
endcase
case(reg_B[76:79]) // word4
4'd0:
result[64:79]<=reg_A[64:79];
4'd1:
result[64:79]<={{1{reg_A[64]}},reg_A[64:78]};
4'd2:
result[64:79]<={{2{reg_A[64]}},reg_A[64:77]};
4'd3:
result[64:79]<={{3{reg_A[64]}},reg_A[64:76]};
4'd4:
result[64:79]<={{4{reg_A[64]}},reg_A[64:75]};
4'd5:
result[64:79]<={{5{reg_A[64]}},reg_A[64:74]};
4'd6:
result[64:79]<={{6{reg_A[64]}},reg_A[64:73]};
4'd7:
result[64:79]<={{7{reg_A[64]}},reg_A[64:72]};
4'd8:
result[64:79]<={{8{reg_A[64]}},reg_A[64:71]};
4'd9:
result[64:79]<={{9{reg_A[64]}},reg_A[64:70]};
4'd10:
result[64:79]<={{10{reg_A[64]}},reg_A[64:69]};
4'd11:
result[64:79]<={{11{reg_A[64]}},reg_A[64:68]};
4'd12:
result[64:79]<={{12{reg_A[64]}},reg_A[64:67]};
4'd13:
result[64:79]<={{13{reg_A[64]}},reg_A[64:66]};
4'd14:
result[64:79]<={{14{reg_A[64]}},reg_A[64:65]};
4'd15:
result[64:79]<={{15{reg_A[64]}},reg_A[64]};
endcase
case(reg_B[92:95]) // word5
4'd0:
result[80:95]<=reg_A[80:95];
4'd1:
result[80:95]<={{1{reg_A[80]}},reg_A[80:94]};
4'd2:
result[80:95]<={{2{reg_A[80]}},reg_A[80:93]};
4'd3:
result[80:95]<={{3{reg_A[80]}},reg_A[80:92]};
4'd4:
result[80:95]<={{4{reg_A[80]}},reg_A[80:91]};
4'd5:
result[80:95]<={{5{reg_A[80]}},reg_A[80:90]};
4'd6:
result[80:95]<={{6{reg_A[80]}},reg_A[80:89]};
4'd7:
result[80:95]<={{7{reg_A[80]}},reg_A[80:88]};
4'd8:
result[80:95]<={{8{reg_A[80]}},reg_A[80:87]};
4'd9:
result[80:95]<={{9{reg_A[80]}},reg_A[80:86]};
4'd10:
result[80:95]<={{10{reg_A[80]}},reg_A[80:85]};
4'd11:
result[80:95]<={{11{reg_A[80]}},reg_A[80:84]};
4'd12:
result[80:95]<={{12{reg_A[80]}},reg_A[80:83]};
4'd13:
result[80:95]<={{13{reg_A[80]}},reg_A[80:82]};
4'd14:
result[80:95]<={{14{reg_A[80]}},reg_A[80:81]};
4'd15:
result[80:95]<={{15{reg_A[80]}},reg_A[80]};
endcase
case(reg_B[92:111]) // word6
4'd0:
result[96:111]<=reg_A[96:111];
4'd1:
result[96:111]<={{1{reg_A[96]}},reg_A[96:110]};
4'd2:
result[96:111]<={{2{reg_A[96]}},reg_A[96:109]};
4'd3:
result[96:111]<={{3{reg_A[96]}},reg_A[96:108]};
4'd4:
result[96:111]<={{4{reg_A[96]}},reg_A[96:107]};
4'd5:
result[96:111]<={{5{reg_A[96]}},reg_A[96:106]};
4'd6:
result[96:111]<={{6{reg_A[96]}},reg_A[96:105]};
4'd7:
result[96:111]<={{7{reg_A[96]}},reg_A[96:104]};
4'd8:
result[96:111]<={{8{reg_A[96]}},reg_A[96:103]};
4'd9:
result[96:111]<={{9{reg_A[96]}},reg_A[96:102]};
4'd10:
result[96:111]<={{10{reg_A[96]}},reg_A[96:101]};
4'd11:
result[96:111]<={{11{reg_A[96]}},reg_A[96:100]};
4'd12:
result[96:111]<={{12{reg_A[96]}},reg_A[96:99]};
4'd13:
result[96:111]<={{13{reg_A[96]}},reg_A[96:98]};
4'd14:
result[96:111]<={{14{reg_A[96]}},reg_A[96:97]};
4'd15:
result[96:111]<={{15{reg_A[96]}},reg_A[96]};
endcase
case(reg_B[92:127]) // word7
4'd0:
result[112:127]<=reg_A[112:127];
4'd1:
result[112:127]<={{1{reg_A[112]}},reg_A[112:126]};
4'd2:
result[112:127]<={{2{reg_A[112]}},reg_A[112:125]};
4'd3:
result[112:127]<={{3{reg_A[112]}},reg_A[112:124]};
4'd4:
result[112:127]<={{4{reg_A[112]}},reg_A[112:123]};
4'd5:
result[112:127]<={{5{reg_A[112]}},reg_A[112:122]};
4'd6:
result[112:127]<={{6{reg_A[112]}},reg_A[112:121]};
4'd7:
result[112:127]<={{7{reg_A[112]}},reg_A[112:120]};
4'd8:
result[112:127]<={{8{reg_A[112]}},reg_A[112:119]};
4'd9:
result[112:127]<={{9{reg_A[112]}},reg_A[112:118]};
4'd10:
result[112:127]<={{10{reg_A[112]}},reg_A[112:117]};
4'd11:
result[112:127]<={{11{reg_A[112]}},reg_A[112:116]};
4'd12:
result[112:127]<={{12{reg_A[112]}},reg_A[112:115]};
4'd13:
result[112:127]<={{13{reg_A[112]}},reg_A[112:114]};
4'd14:
result[112:127]<={{14{reg_A[112]}},reg_A[112:113]};
4'd15:
result[112:127]<={{15{reg_A[112]}},reg_A[112]};
endcase
end
`w32:
begin
case(reg_B[27:31])
5'd0:
result[0:31]<=reg_A[0:31];
5'd1:
result[0:31]<={{1{reg_A[0]}},reg_A[0:30]};
5'd2:
result[0:31]<={{2{reg_A[0]}},reg_A[0:29]};
5'd3:
result[0:31]<={{3{reg_A[0]}},reg_A[0:28]};
5'd4:
result[0:31]<={{4{reg_A[0]}},reg_A[0:27]};
5'd5:
result[0:31]<={{5{reg_A[0]}},reg_A[0:26]};
5'd6:
result[0:31]<={{6{reg_A[0]}},reg_A[0:25]};
5'd7:
result[0:31]<={{7{reg_A[0]}},reg_A[0:24]};
5'd8:
result[0:31]<={{8{reg_A[0]}},reg_A[0:23]};
5'd9:
result[0:31]<={{9{reg_A[0]}},reg_A[0:22]};
5'd10:
result[0:31]<={{10{reg_A[0]}},reg_A[0:21]};
5'd11:
result[0:31]<={{11{reg_A[0]}},reg_A[0:20]};
5'd12:
result[0:31]<={{12{reg_A[0]}},reg_A[0:19]};
5'd13:
result[0:31]<={{13{reg_A[0]}},reg_A[0:18]};
5'd14:
result[0:31]<={{14{reg_A[0]}},reg_A[0:17]};
5'd15:
result[0:31]<={{15{reg_A[0]}},reg_A[0:16]};
5'd16:
result[0:31]<={{16{reg_A[0]}},reg_A[0:15]};
5'd17:
result[0:31]<={{17{reg_A[0]}},reg_A[0:14]};
5'd18:
result[0:31]<={{18{reg_A[0]}},reg_A[0:13]};
5'd19:
result[0:31]<={{19{reg_A[0]}},reg_A[0:12]};
5'd20:
result[0:31]<={{20{reg_A[0]}},reg_A[0:11]};
5'd21:
result[0:31]<={{21{reg_A[0]}},reg_A[0:10]};
5'd22:
result[0:31]<={{22{reg_A[0]}},reg_A[0:9]};
5'd23:
result[0:31]<={{23{reg_A[0]}},reg_A[0:8]};
5'd24:
result[0:31]<={{24{reg_A[0]}},reg_A[0:7]};
5'd25:
result[0:31]<={{25{reg_A[0]}},reg_A[0:6]};
5'd26:
result[0:31]<={{26{reg_A[0]}},reg_A[0:5]};
5'd27:
result[0:31]<={{27{reg_A[0]}},reg_A[0:4]};
5'd28:
result[0:31]<={{28{reg_A[0]}},reg_A[0:3]};
5'd29:
result[0:31]<={{29{reg_A[0]}},reg_A[0:2]};
5'd30:
result[0:31]<={{30{reg_A[0]}},reg_A[0:1]};
5'd31:
result[0:31]<={{31{reg_A[0]}},reg_A[0]};
endcase
case(reg_B[59:63])
5'd0:
result[32:63]<=reg_A[32:63];
5'd1:
result[32:63]<={{1{reg_A[32]}},reg_A[32:62]};
5'd2:
result[32:63]<={{2{reg_A[32]}},reg_A[32:61]};
5'd3:
result[32:63]<={{3{reg_A[32]}},reg_A[32:60]};
5'd4:
result[32:63]<={{4{reg_A[32]}},reg_A[32:59]};
5'd5:
result[32:63]<={{5{reg_A[32]}},reg_A[32:58]};
5'd6:
result[32:63]<={{6{reg_A[32]}},reg_A[32:57]};
5'd7:
result[32:63]<={{7{reg_A[32]}},reg_A[32:56]};
5'd8:
result[32:63]<={{8{reg_A[32]}},reg_A[32:55]};
5'd9:
result[32:63]<={{9{reg_A[32]}},reg_A[32:54]};
5'd10:
result[32:63]<={{10{reg_A[32]}},reg_A[32:53]};
5'd11:
result[32:63]<={{11{reg_A[32]}},reg_A[32:52]};
5'd12:
result[32:63]<={{12{reg_A[32]}},reg_A[32:51]};
5'd13:
result[32:63]<={{13{reg_A[32]}},reg_A[32:50]};
5'd14:
result[32:63]<={{14{reg_A[32]}},reg_A[32:49]};
5'd15:
result[32:63]<={{15{reg_A[32]}},reg_A[32:48]};
5'd16:
result[32:63]<={{16{reg_A[32]}},reg_A[32:47]};
5'd17:
result[32:63]<={{17{reg_A[32]}},reg_A[32:46]};
5'd18:
result[32:63]<={{18{reg_A[32]}},reg_A[32:45]};
5'd19:
result[32:63]<={{19{reg_A[32]}},reg_A[32:44]};
5'd20:
result[32:63]<={{20{reg_A[32]}},reg_A[32:43]};
5'd21:
result[32:63]<={{21{reg_A[32]}},reg_A[32:42]};
5'd22:
result[32:63]<={{22{reg_A[32]}},reg_A[32:41]};
5'd23:
result[32:63]<={{23{reg_A[32]}},reg_A[32:40]};
5'd24:
result[32:63]<={{24{reg_A[32]}},reg_A[32:39]};
5'd25:
result[32:63]<={{25{reg_A[32]}},reg_A[32:38]};
5'd26:
result[32:63]<={{26{reg_A[32]}},reg_A[32:37]};
5'd27:
result[32:63]<={{27{reg_A[32]}},reg_A[32:36]};
5'd28:
result[32:63]<={{28{reg_A[32]}},reg_A[32:35]};
5'd29:
result[32:63]<={{29{reg_A[32]}},reg_A[32:34]};
5'd30:
result[32:63]<={{30{reg_A[32]}},reg_A[32:33]};
5'd31:
result[32:63]<={{31{reg_A[32]}},reg_A[32]};
endcase
case(reg_B[91:95])
5'd0:
result[64:95]<=reg_A[64:95];
5'd1:
result[64:95]<={{1{reg_A[64]}},reg_A[64:94]};
5'd2:
result[64:95]<={{2{reg_A[64]}},reg_A[64:93]};
5'd3:
result[64:95]<={{3{reg_A[64]}},reg_A[64:92]};
5'd4:
result[64:95]<={{4{reg_A[64]}},reg_A[64:91]};
5'd5:
result[64:95]<={{5{reg_A[64]}},reg_A[64:90]};
5'd6:
result[64:95]<={{6{reg_A[64]}},reg_A[64:89]};
5'd7:
result[64:95]<={{7{reg_A[64]}},reg_A[64:88]};
5'd8:
result[64:95]<={{8{reg_A[64]}},reg_A[64:87]};
5'd9:
result[64:95]<={{9{reg_A[64]}},reg_A[64:86]};
5'd10:
result[64:95]<={{10{reg_A[64]}},reg_A[64:85]};
5'd11:
result[64:95]<={{11{reg_A[64]}},reg_A[64:84]};
5'd12:
result[64:95]<={{12{reg_A[64]}},reg_A[64:83]};
5'd13:
result[64:95]<={{13{reg_A[64]}},reg_A[64:82]};
5'd14:
result[64:95]<={{14{reg_A[64]}},reg_A[64:81]};
5'd15:
result[64:95]<={{15{reg_A[64]}},reg_A[64:80]};
5'd16:
result[64:95]<={{16{reg_A[64]}},reg_A[64:79]};
5'd17:
result[64:95]<={{17{reg_A[64]}},reg_A[64:78]};
5'd18:
result[64:95]<={{18{reg_A[64]}},reg_A[64:77]};
5'd19:
result[64:95]<={{19{reg_A[64]}},reg_A[64:76]};
5'd20:
result[64:95]<={{20{reg_A[64]}},reg_A[64:75]};
5'd21:
result[64:95]<={{21{reg_A[64]}},reg_A[64:74]};
5'd22:
result[64:95]<={{22{reg_A[64]}},reg_A[64:73]};
5'd23:
result[64:95]<={{23{reg_A[64]}},reg_A[64:72]};
5'd24:
result[64:95]<={{24{reg_A[64]}},reg_A[64:71]};
5'd25:
result[64:95]<={{25{reg_A[64]}},reg_A[64:70]};
5'd26:
result[64:95]<={{26{reg_A[64]}},reg_A[64:69]};
5'd27:
result[64:95]<={{27{reg_A[64]}},reg_A[64:68]};
5'd28:
result[64:95]<={{28{reg_A[64]}},reg_A[64:67]};
5'd29:
result[64:95]<={{29{reg_A[64]}},reg_A[64:66]};
5'd30:
result[64:95]<={{30{reg_A[64]}},reg_A[64:65]};
5'd31:
result[64:95]<={{31{reg_A[64]}},reg_A[64]};
endcase
case(reg_B[123:127])
5'd0:
result[96:127]<=reg_A[96:127];
5'd1:
result[96:127]<={{1{reg_A[96]}},reg_A[96:126]};
5'd2:
result[96:127]<={{2{reg_A[96]}},reg_A[96:125]};
5'd3:
result[96:127]<={{3{reg_A[96]}},reg_A[96:124]};
5'd4:
result[96:127]<={{4{reg_A[96]}},reg_A[96:123]};
5'd5:
result[96:127]<={{5{reg_A[96]}},reg_A[96:122]};
5'd6:
result[96:127]<={{6{reg_A[96]}},reg_A[96:121]};
5'd7:
result[96:127]<={{7{reg_A[96]}},reg_A[96:120]};
5'd8:
result[96:127]<={{8{reg_A[96]}},reg_A[96:119]};
5'd9:
result[96:127]<={{9{reg_A[96]}},reg_A[96:118]};
5'd10:
result[96:127]<={{10{reg_A[96]}},reg_A[96:117]};
5'd11:
result[96:127]<={{11{reg_A[96]}},reg_A[96:116]};
5'd12:
result[96:127]<={{12{reg_A[96]}},reg_A[96:115]};
5'd13:
result[96:127]<={{13{reg_A[96]}},reg_A[96:114]};
5'd14:
result[96:127]<={{14{reg_A[96]}},reg_A[96:113]};
5'd15:
result[96:127]<={{15{reg_A[96]}},reg_A[96:112]};
5'd16:
result[96:127]<={{16{reg_A[96]}},reg_A[96:111]};
5'd17:
result[96:127]<={{17{reg_A[96]}},reg_A[96:110]};
5'd18:
result[96:127]<={{18{reg_A[96]}},reg_A[96:109]};
5'd19:
result[96:127]<={{19{reg_A[96]}},reg_A[96:108]};
5'd20:
result[96:127]<={{20{reg_A[96]}},reg_A[96:107]};
5'd21:
result[96:127]<={{21{reg_A[96]}},reg_A[96:106]};
5'd22:
result[96:127]<={{22{reg_A[96]}},reg_A[96:105]};
5'd23:
result[96:127]<={{23{reg_A[96]}},reg_A[96:104]};
5'd24:
result[96:127]<={{24{reg_A[96]}},reg_A[96:103]};
5'd25:
result[96:127]<={{25{reg_A[96]}},reg_A[96:102]};
5'd26:
result[96:127]<={{26{reg_A[96]}},reg_A[96:101]};
5'd27:
result[96:127]<={{27{reg_A[96]}},reg_A[96:100]};
5'd28:
result[96:127]<={{28{reg_A[96]}},reg_A[96:99]};
5'd29:
result[96:127]<={{29{reg_A[96]}},reg_A[96:98]};
5'd30:
result[96:127]<={{30{reg_A[96]}},reg_A[96:97]};
5'd31:
result[96:127]<={{31{reg_A[96]}},reg_A[96]};
endcase
end
endcase
end
// ==================================================================
default:
begin
// Default arithmetic/logic operation
result<=128'd0;
end
endcase
end
endmodule
|
// Listing 14.7
module textMenu_graph
(
input wire clk, reset,
input wire [2:0] item_selector,
input wire [9:0] pix_x, pix_y,
input wire window_selector,
output wire graph_on,
output reg [2:0] graph_rgb
);
// costant and signal declaration
// x, y coordinates (0,0) to (639,479)
localparam MAX_X = 640;
localparam MAX_Y = 480;
//Top menu text window sections
localparam itemTextMenu1 = 4'd1;
localparam itemTextMenu2 = 4'd2;
localparam itemTextMenu3 = 4'd3;
localparam itemTextMenu4 = 4'd4;
localparam itemTextMenu5 = 4'd5;
localparam itemTextMenu6 = 4'd6;
//Main menu dialog sections
localparam itemMainMenu1=1'b0;
localparam itemMainMenu2=1'b1;
//Menu main window vertical limits
localparam topMenu_main_y_limit_top = 115;
localparam topMenu_main_y_limit_bottom = 288;
//Top menu text window vertical limits
localparam topMenu_y_limit_top = 0;
localparam topMenu_y_limit_bottom = 80;
//Top menu text window horizontal limits
localparam topMenu_x_limit_left=0;
localparam topMenu_x_limit_right=640;
//Top menu main window horizontal limits
localparam topMenu_main_x_limit_left=186;
localparam topMenu_main_x_limit_right=416;
//Top menu items sections horizontal each region
localparam topMenu_x_open_limit_left=10;
localparam topMenu_x_open_limit_right=topMenu_x_open_limit_left+60;
localparam topMenu_x_save_limit_left=topMenu_x_open_limit_right+10;
localparam topMenu_x_save_limit_right=topMenu_x_save_limit_left+60;
localparam topMenu_x_exit_limit_left=topMenu_x_save_limit_right+10;
localparam topMenu_x_exit_limit_right=topMenu_x_exit_limit_left+60;
localparam topMenu_x_center_width=topMenu_x_exit_limit_right+210;
localparam topMenu_x_caps_limit_left=topMenu_x_center_width+10;
localparam topMenu_x_caps_limit_right=topMenu_x_caps_limit_left+60;
localparam topMenu_x_color_limit_left=topMenu_x_caps_limit_right+10;
localparam topMenu_x_color_limit_right=topMenu_x_color_limit_left+60;
localparam topMenu_x_size_limit_left=topMenu_x_color_limit_right+10;
localparam topMenu_x_size_limit_right=topMenu_x_size_limit_left+60;
localparam topMenu_main_y_item_top_limit= topMenu_main_y_limit_top+10; //////////
localparam topMenu_main_y_item_bottom_limit= topMenu_main_y_item_top_limit+45;
localparam topMenu_main_x_item_left_limit= topMenu_main_x_limit_left;
localparam topMenu_main_x_item_right_limit= topMenu_main_x_limit_left+60;
//Top menu items vertical limits
localparam topMenu_y_item_top_limit=topMenu_y_limit_top+17;
localparam topMenu_y_item_bottom_limit=topMenu_y_item_top_limit+45;
wire menu_mostrar_separador;
wire menu_mostrar;
assign menu_mostrar_separador = (topMenu_x_limit_left<=pix_x) && (pix_x <= topMenu_x_limit_right) &&
(topMenu_y_limit_bottom-2<=pix_y) && (pix_y <= topMenu_y_limit_bottom);
assign menu_mostrar=((topMenu_main_y_limit_top<=pix_y) && (pix_y <= topMenu_main_y_limit_top+1) &&
(topMenu_main_x_limit_left<=pix_x) && (pix_x <= topMenu_main_x_limit_right)) ||
((topMenu_main_y_limit_bottom-1<=pix_y) && (pix_y <= topMenu_main_y_limit_bottom) &&
(topMenu_main_x_limit_left<=pix_x) && (pix_x <= topMenu_main_x_limit_right)) ||
((topMenu_main_y_limit_top<=pix_y) && (pix_y <= topMenu_main_y_limit_bottom) &&
(topMenu_main_x_limit_left<=pix_x) && (pix_x <= topMenu_main_x_limit_left+1)) ||
((topMenu_main_y_limit_top<=pix_y) && (pix_y <= topMenu_main_y_limit_bottom) &&
(topMenu_main_x_limit_right-1<=pix_x) && (pix_x <= topMenu_main_x_limit_right));
reg[5:0] show_item_selector;
reg [1:0] show_item_main_selector;
reg [2:0] currentItemTextMenu;
reg currentItemMainMenu;
always @ (*) begin
currentItemTextMenu= item_selector;
case(currentItemTextMenu)
itemTextMenu1: begin
show_item_selector[0] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
(topMenu_x_open_limit_left<=pix_x) && (pix_x <= topMenu_x_open_limit_right)) ||
((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_open_limit_left<=pix_x) && (pix_x <= topMenu_x_open_limit_right)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_open_limit_left<=pix_x) && (pix_x <= topMenu_x_open_limit_left+1)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_open_limit_right-1<=pix_x) && (pix_x <= topMenu_x_open_limit_right));
end
itemTextMenu2: begin
show_item_selector[1] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
(topMenu_x_save_limit_left<=pix_x) && (pix_x <= topMenu_x_save_limit_right)) ||
((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_save_limit_left<=pix_x) && (pix_x <= topMenu_x_save_limit_right)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_save_limit_left<=pix_x) && (pix_x <= topMenu_x_save_limit_left+1)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_save_limit_right-1<=pix_x) && (pix_x <= topMenu_x_save_limit_right));
end
itemTextMenu3: begin
show_item_selector[2] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
(topMenu_x_exit_limit_left<=pix_x) && (pix_x <= topMenu_x_exit_limit_right)) ||
((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_exit_limit_left<=pix_x) && (pix_x <= topMenu_x_exit_limit_right)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_exit_limit_left<=pix_x) && (pix_x <= topMenu_x_exit_limit_left+1)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_exit_limit_right-1<=pix_x) && (pix_x <= topMenu_x_exit_limit_right));
end
itemTextMenu4: begin
show_item_selector[3] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
(topMenu_x_caps_limit_left<=pix_x) && (pix_x <= topMenu_x_caps_limit_right)) ||
((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_caps_limit_left<=pix_x) && (pix_x <= topMenu_x_caps_limit_right)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_caps_limit_left<=pix_x) && (pix_x <= topMenu_x_caps_limit_left+1)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_caps_limit_right-1<=pix_x) && (pix_x <= topMenu_x_caps_limit_right));
end
itemTextMenu5: begin
show_item_selector[4] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
(topMenu_x_color_limit_left<=pix_x) && (pix_x <= topMenu_x_color_limit_right)) ||
((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_color_limit_left<=pix_x) && (pix_x <= topMenu_x_color_limit_right)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_color_limit_left<=pix_x) && (pix_x <= topMenu_x_color_limit_left+1)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_color_limit_right-1<=pix_x) && (pix_x <= topMenu_x_color_limit_right));
end
itemTextMenu6: begin
show_item_selector[5] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
(topMenu_x_size_limit_left<=pix_x) && (pix_x <= topMenu_x_size_limit_right)) ||
((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_size_limit_left<=pix_x) && (pix_x <= topMenu_x_size_limit_right)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_size_limit_left<=pix_x) && (pix_x <= topMenu_x_size_limit_left+1)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_size_limit_right-1<=pix_x) && (pix_x <= topMenu_x_size_limit_right));
end
default: begin
show_item_selector= 3'b000;
end
endcase
end
always @ (*) begin
currentItemMainMenu =item_selector[1:0];
case(currentItemMainMenu)
itemMainMenu1: begin
show_item_main_selector[0] = ((topMenu_main_y_item_top_limit<=pix_y) && (pix_y <= topMenu_main_y_item_top_limit+1) &&
(topMenu_main_x_item_left_limit<=pix_x) && (pix_x <= topMenu_main_x_item_right_limit)) ||
((topMenu_main_y_item_top_limit-1<=pix_y) && (pix_y <= topMenu_main_y_item_bottom_limit) &&
(topMenu_main_x_item_left_limit<=pix_x) && (pix_x <= topMenu_main_x_item_right_limit)) ||
((topMenu_main_y_item_top_limit<=pix_y) && (pix_y <= topMenu_main_y_item_bottom_limit) &&
(topMenu_main_x_item_left_limit<=pix_x) && (pix_x <= topMenu_main_x_item_left_limit+1)) ||
((topMenu_main_y_item_top_limit<=pix_y) && (pix_y <= topMenu_main_y_item_bottom_limit) &&
(topMenu_main_x_item_right_limit-1<=pix_x) && (pix_x <= topMenu_main_x_item_right_limit));
end
itemMainMenu2: begin
show_item_main_selector[1] = ((topMenu_main_y_item_top_limit+50<=pix_y) && (pix_y <= topMenu_main_y_item_top_limit+50+1) &&
(topMenu_main_x_item_left_limit<=pix_x) && (pix_x <= topMenu_main_x_item_right_limit)) ||
((topMenu_main_y_item_top_limit+50-1<=pix_y) && (pix_y <= topMenu_main_y_item_bottom_limit+50) &&
(topMenu_main_x_item_left_limit<=pix_x) && (pix_x <= topMenu_main_x_item_right_limit)) ||
((topMenu_main_y_item_top_limit+50<=pix_y) && (pix_y <= topMenu_main_y_item_bottom_limit+50) &&
(topMenu_main_x_item_left_limit<=pix_x) && (pix_x <= topMenu_main_x_item_left_limit+1)) ||
((topMenu_main_y_item_top_limit+50<=pix_y) && (pix_y <= topMenu_main_y_item_bottom_limit+50) &&
(topMenu_main_x_item_right_limit-1<=pix_x) && (pix_x <= topMenu_main_x_item_right_limit));
end
default: begin
show_item_main_selector= 2'b00;
end
endcase
end
//--------------------------------------------
// rgb multiplexing circuit
//--------------------------------------------
always @* begin
graph_rgb = 3'b111;
if(window_selector) begin
if (menu_mostrar_separador)
graph_rgb = 3'b000;
else if (show_item_selector[0] || show_item_selector[1] || show_item_selector[2] ||
show_item_selector[3] || show_item_selector[4] || show_item_selector[5])
graph_rgb = 3'b000;
else
graph_rgb = 3'b111; // black background
end
else if (!window_selector) begin
if(menu_mostrar)
graph_rgb=3'b000;
else if(show_item_main_selector[0] || show_item_main_selector[1])
graph_rgb =3'b000;
else
graph_rgb = 3'b111; // black background
end
end
assign graph_on=((show_item_selector[0] || show_item_selector[1] || show_item_selector[2] ||
show_item_selector[3] || show_item_selector[4] || show_item_selector[5] || menu_mostrar_separador) && window_selector) ||
((/*show_item_main_selector[0]||show_item_main_selector[1]||*/ menu_mostrar) && !window_selector);
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//Register map:
//addr register type
//0 read data r
//1 write data w
//2 status r/w
//3 control r/w
//4 reserved
//5 slave-enable r/w
//6 end-of-packet-value r/w
//INPUT_CLOCK: 116000000
//ISMASTER: 1
//DATABITS: 8
//TARGETCLOCK: 20000000
//NUMSLAVES: 1
//CPOL: 0
//CPHA: 0
//LSBFIRST: 0
//EXTRADELAY: 0
//TARGETSSDELAY: 0
module wasca_spi_sd_card (
// inputs:
MISO,
clk,
data_from_cpu,
mem_addr,
read_n,
reset_n,
spi_select,
write_n,
// outputs:
MOSI,
SCLK,
SS_n,
data_to_cpu,
dataavailable,
endofpacket,
irq,
readyfordata
)
;
output MOSI;
output SCLK;
output SS_n;
output [ 15: 0] data_to_cpu;
output dataavailable;
output endofpacket;
output irq;
output readyfordata;
input MISO;
input clk;
input [ 15: 0] data_from_cpu;
input [ 2: 0] mem_addr;
input read_n;
input reset_n;
input spi_select;
input write_n;
wire E;
reg EOP;
reg MISO_reg;
wire MOSI;
reg ROE;
reg RRDY;
wire SCLK;
reg SCLK_reg;
reg SSO_reg;
wire SS_n;
wire TMT;
reg TOE;
wire TRDY;
wire control_wr_strobe;
reg data_rd_strobe;
reg [ 15: 0] data_to_cpu;
reg data_wr_strobe;
wire dataavailable;
wire ds_MISO;
wire enableSS;
wire endofpacket;
reg [ 15: 0] endofpacketvalue_reg;
wire endofpacketvalue_wr_strobe;
reg iEOP_reg;
reg iE_reg;
reg iROE_reg;
reg iRRDY_reg;
reg iTMT_reg;
reg iTOE_reg;
reg iTRDY_reg;
wire irq;
reg irq_reg;
wire p1_data_rd_strobe;
wire [ 15: 0] p1_data_to_cpu;
wire p1_data_wr_strobe;
wire p1_rd_strobe;
wire [ 1: 0] p1_slowcount;
wire p1_wr_strobe;
reg rd_strobe;
wire readyfordata;
reg [ 7: 0] rx_holding_reg;
reg [ 7: 0] shift_reg;
wire slaveselect_wr_strobe;
wire slowclock;
reg [ 1: 0] slowcount;
wire [ 10: 0] spi_control;
reg [ 15: 0] spi_slave_select_holding_reg;
reg [ 15: 0] spi_slave_select_reg;
wire [ 10: 0] spi_status;
reg [ 4: 0] state;
reg stateZero;
wire status_wr_strobe;
reg transmitting;
reg tx_holding_primed;
reg [ 7: 0] tx_holding_reg;
reg wr_strobe;
wire write_shift_reg;
wire write_tx_holding;
//spi_control_port, which is an e_avalon_slave
assign p1_rd_strobe = ~rd_strobe & spi_select & ~read_n;
// Read is a two-cycle event.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_strobe <= 0;
else
rd_strobe <= p1_rd_strobe;
end
assign p1_data_rd_strobe = p1_rd_strobe & (mem_addr == 0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_rd_strobe <= 0;
else
data_rd_strobe <= p1_data_rd_strobe;
end
assign p1_wr_strobe = ~wr_strobe & spi_select & ~write_n;
// Write is a two-cycle event.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wr_strobe <= 0;
else
wr_strobe <= p1_wr_strobe;
end
assign p1_data_wr_strobe = p1_wr_strobe & (mem_addr == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_wr_strobe <= 0;
else
data_wr_strobe <= p1_data_wr_strobe;
end
assign control_wr_strobe = wr_strobe & (mem_addr == 3);
assign status_wr_strobe = wr_strobe & (mem_addr == 2);
assign slaveselect_wr_strobe = wr_strobe & (mem_addr == 5);
assign endofpacketvalue_wr_strobe = wr_strobe & (mem_addr == 6);
assign TMT = ~transmitting & ~tx_holding_primed;
assign E = ROE | TOE;
assign spi_status = {EOP, E, RRDY, TRDY, TMT, TOE, ROE, 3'b0};
// Streaming data ready for pickup.
assign dataavailable = RRDY;
// Ready to accept streaming data.
assign readyfordata = TRDY;
// Endofpacket condition detected.
assign endofpacket = EOP;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
iEOP_reg <= 0;
iE_reg <= 0;
iRRDY_reg <= 0;
iTRDY_reg <= 0;
iTMT_reg <= 0;
iTOE_reg <= 0;
iROE_reg <= 0;
SSO_reg <= 0;
end
else if (control_wr_strobe)
begin
iEOP_reg <= data_from_cpu[9];
iE_reg <= data_from_cpu[8];
iRRDY_reg <= data_from_cpu[7];
iTRDY_reg <= data_from_cpu[6];
iTMT_reg <= data_from_cpu[5];
iTOE_reg <= data_from_cpu[4];
iROE_reg <= data_from_cpu[3];
SSO_reg <= data_from_cpu[10];
end
end
assign spi_control = {SSO_reg, iEOP_reg, iE_reg, iRRDY_reg, iTRDY_reg, 1'b0, iTOE_reg, iROE_reg, 3'b0};
// IRQ output.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_reg <= 0;
else
irq_reg <= (EOP & iEOP_reg) | ((TOE | ROE) & iE_reg) | (RRDY & iRRDY_reg) | (TRDY & iTRDY_reg) | (TOE & iTOE_reg) | (ROE & iROE_reg);
end
assign irq = irq_reg;
// Slave select register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
spi_slave_select_reg <= 1;
else if (write_shift_reg || control_wr_strobe & data_from_cpu[10] & ~SSO_reg)
spi_slave_select_reg <= spi_slave_select_holding_reg;
end
// Slave select holding register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
spi_slave_select_holding_reg <= 1;
else if (slaveselect_wr_strobe)
spi_slave_select_holding_reg <= data_from_cpu;
end
// slowclock is active once every 3 system clock pulses.
assign slowclock = slowcount == 2'h2;
assign p1_slowcount = ({2 {(transmitting && !slowclock)}} & (slowcount + 1)) |
({2 {(~((transmitting && !slowclock)))}} & 0);
// Divide counter for SPI clock.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
slowcount <= 0;
else
slowcount <= p1_slowcount;
end
// End-of-packet value register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
endofpacketvalue_reg <= 0;
else if (endofpacketvalue_wr_strobe)
endofpacketvalue_reg <= data_from_cpu;
end
assign p1_data_to_cpu = ((mem_addr == 2))? spi_status :
((mem_addr == 3))? spi_control :
((mem_addr == 6))? endofpacketvalue_reg :
((mem_addr == 5))? spi_slave_select_reg :
rx_holding_reg;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_to_cpu <= 0;
else
// Data to cpu.
data_to_cpu <= p1_data_to_cpu;
end
// 'state' counts from 0 to 17.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
state <= 0;
stateZero <= 1;
end
else if (transmitting & slowclock)
begin
stateZero <= state == 17;
if (state == 17)
state <= 0;
else
state <= state + 1;
end
end
assign enableSS = transmitting & ~stateZero;
assign MOSI = shift_reg[7];
assign SS_n = (enableSS | SSO_reg) ? ~spi_slave_select_reg : {1 {1'b1} };
assign SCLK = SCLK_reg;
// As long as there's an empty spot somewhere,
//it's safe to write data.
assign TRDY = ~(transmitting & tx_holding_primed);
// Enable write to tx_holding_register.
assign write_tx_holding = data_wr_strobe & TRDY;
// Enable write to shift register.
assign write_shift_reg = tx_holding_primed & ~transmitting;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
shift_reg <= 0;
rx_holding_reg <= 0;
EOP <= 0;
RRDY <= 0;
ROE <= 0;
TOE <= 0;
tx_holding_reg <= 0;
tx_holding_primed <= 0;
transmitting <= 0;
SCLK_reg <= 0;
MISO_reg <= 0;
end
else
begin
if (write_tx_holding)
begin
tx_holding_reg <= data_from_cpu;
tx_holding_primed <= 1;
end
if (data_wr_strobe & ~TRDY)
// You wrote when I wasn't ready.
TOE <= 1;
// EOP must be updated by the last (2nd) cycle of access.
if ((p1_data_rd_strobe && (rx_holding_reg == endofpacketvalue_reg)) || (p1_data_wr_strobe && (data_from_cpu[7 : 0] == endofpacketvalue_reg)))
EOP <= 1;
if (write_shift_reg)
begin
shift_reg <= tx_holding_reg;
transmitting <= 1;
end
if (write_shift_reg & ~write_tx_holding)
// Clear tx_holding_primed
tx_holding_primed <= 0;
if (data_rd_strobe)
// On data read, clear the RRDY bit.
RRDY <= 0;
if (status_wr_strobe)
begin
// On status write, clear all status bits (ignore the data).
EOP <= 0;
RRDY <= 0;
ROE <= 0;
TOE <= 0;
end
if (slowclock)
begin
if (state == 17)
begin
transmitting <= 0;
RRDY <= 1;
rx_holding_reg <= shift_reg;
SCLK_reg <= 0;
if (RRDY)
ROE <= 1;
end
else if (state != 0)
if (transmitting)
SCLK_reg <= ~SCLK_reg;
if (SCLK_reg ^ 0 ^ 0)
begin
if (1)
shift_reg <= {shift_reg[6 : 0], MISO_reg};
end
else
MISO_reg <= ds_MISO;
end
end
end
assign ds_MISO = MISO;
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module CvtColor_1 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
p_src_rows_V_dout,
p_src_rows_V_empty_n,
p_src_rows_V_read,
p_src_cols_V_dout,
p_src_cols_V_empty_n,
p_src_cols_V_read,
p_src_data_stream_0_V_dout,
p_src_data_stream_0_V_empty_n,
p_src_data_stream_0_V_read,
p_src_data_stream_1_V_dout,
p_src_data_stream_1_V_empty_n,
p_src_data_stream_1_V_read,
p_src_data_stream_2_V_dout,
p_src_data_stream_2_V_empty_n,
p_src_data_stream_2_V_read,
p_dst_data_stream_0_V_din,
p_dst_data_stream_0_V_full_n,
p_dst_data_stream_0_V_write,
p_dst_data_stream_1_V_din,
p_dst_data_stream_1_V_full_n,
p_dst_data_stream_1_V_write,
p_dst_data_stream_2_V_din,
p_dst_data_stream_2_V_full_n,
p_dst_data_stream_2_V_write
);
parameter ap_ST_fsm_state1 = 4'd1;
parameter ap_ST_fsm_state2 = 4'd2;
parameter ap_ST_fsm_pp0_stage0 = 4'd4;
parameter ap_ST_fsm_state12 = 4'd8;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] p_src_rows_V_dout;
input p_src_rows_V_empty_n;
output p_src_rows_V_read;
input [15:0] p_src_cols_V_dout;
input p_src_cols_V_empty_n;
output p_src_cols_V_read;
input [7:0] p_src_data_stream_0_V_dout;
input p_src_data_stream_0_V_empty_n;
output p_src_data_stream_0_V_read;
input [7:0] p_src_data_stream_1_V_dout;
input p_src_data_stream_1_V_empty_n;
output p_src_data_stream_1_V_read;
input [7:0] p_src_data_stream_2_V_dout;
input p_src_data_stream_2_V_empty_n;
output p_src_data_stream_2_V_read;
output [7:0] p_dst_data_stream_0_V_din;
input p_dst_data_stream_0_V_full_n;
output p_dst_data_stream_0_V_write;
output [7:0] p_dst_data_stream_1_V_din;
input p_dst_data_stream_1_V_full_n;
output p_dst_data_stream_1_V_write;
output [7:0] p_dst_data_stream_2_V_din;
input p_dst_data_stream_2_V_full_n;
output p_dst_data_stream_2_V_write;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg p_src_rows_V_read;
reg p_src_cols_V_read;
reg p_src_data_stream_0_V_read;
reg p_src_data_stream_1_V_read;
reg p_src_data_stream_2_V_read;
reg p_dst_data_stream_0_V_write;
reg p_dst_data_stream_1_V_write;
reg p_dst_data_stream_2_V_write;
reg ap_done_reg;
(* fsm_encoding = "none" *) reg [3:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg p_src_rows_V_blk_n;
reg p_src_cols_V_blk_n;
reg p_src_data_stream_0_V_blk_n;
wire ap_CS_fsm_pp0_stage0;
reg ap_enable_reg_pp0_iter1;
wire ap_block_pp0_stage0;
reg [0:0] tmp_36_i_reg_692;
reg p_src_data_stream_1_V_blk_n;
reg p_src_data_stream_2_V_blk_n;
reg p_dst_data_stream_0_V_blk_n;
reg ap_enable_reg_pp0_iter8;
reg [0:0] ap_reg_pp0_iter7_tmp_36_i_reg_692;
reg p_dst_data_stream_1_V_blk_n;
reg p_dst_data_stream_2_V_blk_n;
reg [10:0] j_i_reg_176;
reg [15:0] p_src_cols_V_read_reg_673;
reg ap_block_state1;
reg [15:0] p_src_rows_V_read_reg_678;
wire [0:0] tmp_i_fu_191_p2;
wire ap_CS_fsm_state2;
wire [10:0] i_fu_196_p2;
reg [10:0] i_reg_687;
wire [0:0] tmp_36_i_fu_206_p2;
wire ap_block_state3_pp0_stage0_iter0;
reg ap_block_state4_pp0_stage0_iter1;
wire ap_block_state5_pp0_stage0_iter2;
wire ap_block_state6_pp0_stage0_iter3;
wire ap_block_state7_pp0_stage0_iter4;
wire ap_block_state8_pp0_stage0_iter5;
wire ap_block_state9_pp0_stage0_iter6;
wire ap_block_state10_pp0_stage0_iter7;
reg ap_block_state11_pp0_stage0_iter8;
reg ap_block_pp0_stage0_11001;
reg [0:0] ap_reg_pp0_iter1_tmp_36_i_reg_692;
reg [0:0] ap_reg_pp0_iter2_tmp_36_i_reg_692;
reg [0:0] ap_reg_pp0_iter3_tmp_36_i_reg_692;
reg [0:0] ap_reg_pp0_iter4_tmp_36_i_reg_692;
reg [0:0] ap_reg_pp0_iter5_tmp_36_i_reg_692;
reg [0:0] ap_reg_pp0_iter6_tmp_36_i_reg_692;
wire [10:0] j_fu_211_p2;
reg ap_enable_reg_pp0_iter0;
reg [7:0] tmp_23_reg_701;
reg [7:0] ap_reg_pp0_iter2_tmp_23_reg_701;
reg [7:0] ap_reg_pp0_iter3_tmp_23_reg_701;
reg [7:0] ap_reg_pp0_iter4_tmp_23_reg_701;
reg [7:0] tmp_24_reg_707;
reg [7:0] ap_reg_pp0_iter2_tmp_24_reg_707;
reg [7:0] ap_reg_pp0_iter3_tmp_24_reg_707;
reg [7:0] tmp_25_reg_712;
reg [7:0] ap_reg_pp0_iter2_tmp_25_reg_712;
reg [7:0] ap_reg_pp0_iter3_tmp_25_reg_712;
reg [7:0] ap_reg_pp0_iter4_tmp_25_reg_712;
wire [28:0] r_V_6_i_fu_626_p2;
reg [28:0] r_V_6_i_reg_718;
wire [28:0] grp_fu_632_p3;
reg [28:0] p_Val2_2_reg_723;
reg ap_enable_reg_pp0_iter3;
wire [29:0] grp_fu_639_p3;
reg [29:0] r_V_1_reg_728;
reg ap_enable_reg_pp0_iter4;
reg [7:0] p_Val2_4_reg_733;
reg [0:0] tmp_reg_738;
wire [7:0] p_Val2_20_fu_280_p3;
reg [7:0] p_Val2_20_reg_743;
reg [7:0] ap_reg_pp0_iter6_p_Val2_20_reg_743;
reg [7:0] ap_reg_pp0_iter7_p_Val2_20_reg_743;
wire [8:0] i_op_assign_5_fu_295_p2;
reg signed [8:0] i_op_assign_5_reg_748;
wire [8:0] i_op_assign_6_fu_304_p2;
reg signed [8:0] i_op_assign_6_reg_753;
wire signed [31:0] grp_fu_649_p3;
reg signed [31:0] r_V_2_reg_758;
reg ap_enable_reg_pp0_iter6;
reg [0:0] signbit_reg_763;
reg [0:0] ap_reg_pp0_iter7_signbit_reg_763;
reg [7:0] p_Val2_7_reg_770;
reg [0:0] tmp_13_reg_775;
reg [1:0] tmp_s_reg_780;
wire signed [31:0] grp_fu_661_p3;
reg signed [31:0] r_V_3_reg_786;
reg [0:0] signbit_1_reg_791;
reg [0:0] ap_reg_pp0_iter7_signbit_1_reg_791;
reg [7:0] p_Val2_16_reg_798;
reg [0:0] tmp_17_reg_803;
reg [1:0] tmp_1_reg_808;
wire [7:0] p_Val2_8_fu_390_p2;
reg [7:0] p_Val2_8_reg_814;
wire [0:0] p_38_i_i_i_i_fu_433_p2;
reg [0:0] p_38_i_i_i_i_reg_820;
wire [0:0] p_39_demorgan_i_i_i_i_fu_439_p2;
reg [0:0] p_39_demorgan_i_i_i_i_reg_826;
wire [7:0] p_Val2_18_fu_454_p2;
reg [7:0] p_Val2_18_reg_832;
wire [0:0] p_38_i_i_i15_i_fu_497_p2;
reg [0:0] p_38_i_i_i15_i_reg_838;
wire [0:0] p_39_demorgan_i_i_i_fu_503_p2;
reg [0:0] p_39_demorgan_i_i_i_reg_844;
reg ap_block_pp0_stage0_subdone;
reg ap_condition_pp0_exit_iter0_state3;
reg ap_enable_reg_pp0_iter2;
reg ap_enable_reg_pp0_iter5;
reg ap_enable_reg_pp0_iter7;
reg [10:0] i_i_reg_165;
wire ap_CS_fsm_state12;
reg ap_block_pp0_stage0_01001;
wire [15:0] i_cast_i_cast_fu_187_p1;
wire [15:0] j_cast_i_cast_fu_202_p1;
wire [7:0] tmp_19_i_i_i_fu_245_p1;
wire [7:0] p_Val2_5_fu_255_p2;
wire [0:0] tmp_10_fu_248_p3;
wire [0:0] tmp_11_fu_260_p3;
wire [0:0] p_Result_2_i_i_not_fu_268_p2;
wire [0:0] not_carry_i_fu_274_p2;
wire [8:0] tmp_30_cast_i_fu_288_p1;
wire [8:0] tmp_31_cast_i_fu_291_p1;
wire [8:0] tmp_33_cast_i_fu_301_p1;
wire [7:0] tmp_16_i_i_i_fu_380_p1;
wire [0:0] tmp_15_fu_395_p3;
wire [0:0] tmp_14_fu_383_p3;
wire [0:0] tmp_17_i_i_i_fu_403_p2;
wire [0:0] carry_fu_409_p2;
wire [0:0] Range1_all_ones_fu_415_p2;
wire [0:0] Range1_all_zeros_fu_420_p2;
wire [0:0] deleted_zeros_fu_425_p3;
wire [7:0] tmp_16_i_i6_i_fu_444_p1;
wire [0:0] tmp_19_fu_459_p3;
wire [0:0] tmp_18_fu_447_p3;
wire [0:0] tmp_17_i_i10_i_fu_467_p2;
wire [0:0] carry_1_fu_473_p2;
wire [0:0] Range1_all_ones_1_fu_479_p2;
wire [0:0] Range1_all_zeros_1_fu_484_p2;
wire [0:0] deleted_zeros_1_fu_489_p3;
wire [0:0] tmp_18_i_i_i_fu_508_p2;
wire [0:0] signbit_not_i_i_fu_518_p2;
wire [0:0] neg_src_not_i_i_i_fu_523_p2;
wire [0:0] p_39_demorgan_i_not_i_fu_533_p2;
wire [0:0] brmerge_i_i_not_i_i_s_fu_528_p2;
wire [0:0] neg_src_fu_513_p2;
wire [0:0] brmerge_i_i_i_fu_538_p2;
wire [7:0] p_mux_i_i2_i_fu_544_p3;
wire [7:0] p_i_i_i_fu_551_p3;
wire [0:0] tmp_18_i_i16_i_fu_567_p2;
wire [0:0] signbit_not_i19_i_fu_577_p2;
wire [0:0] neg_src_not_i_i20_i_fu_582_p2;
wire [0:0] p_39_demorgan_i_not_i_1_fu_592_p2;
wire [0:0] brmerge_i_i_not_i_i2_fu_587_p2;
wire [0:0] neg_src_4_fu_572_p2;
wire [0:0] brmerge_i_i23_i_fu_597_p2;
wire [7:0] p_mux_i_i24_i_fu_603_p3;
wire [7:0] p_i_i25_i_fu_610_p3;
wire [7:0] r_V_6_i_fu_626_p0;
wire [21:0] r_V_6_i_fu_626_p1;
wire [7:0] grp_fu_632_p0;
wire [19:0] grp_fu_632_p1;
wire [7:0] grp_fu_639_p0;
wire [22:0] grp_fu_639_p1;
wire [28:0] grp_fu_639_p2;
wire [22:0] grp_fu_649_p1;
wire [30:0] grp_fu_649_p2;
wire [22:0] grp_fu_661_p1;
wire [30:0] grp_fu_661_p2;
reg [3:0] ap_NS_fsm;
reg ap_idle_pp0;
wire ap_enable_pp0;
wire [27:0] grp_fu_632_p00;
wire [29:0] grp_fu_639_p00;
wire [29:0] grp_fu_639_p20;
wire [28:0] r_V_6_i_fu_626_p00;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 4'd1;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter8 = 1'b0;
#0 ap_enable_reg_pp0_iter0 = 1'b0;
#0 ap_enable_reg_pp0_iter3 = 1'b0;
#0 ap_enable_reg_pp0_iter4 = 1'b0;
#0 ap_enable_reg_pp0_iter6 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 ap_enable_reg_pp0_iter5 = 1'b0;
#0 ap_enable_reg_pp0_iter7 = 1'b0;
end
hls_contrast_strebkb #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 22 ),
.dout_WIDTH( 29 ))
hls_contrast_strebkb_U30(
.din0(r_V_6_i_fu_626_p0),
.din1(r_V_6_i_fu_626_p1),
.dout(r_V_6_i_fu_626_p2)
);
hls_contrast_strecud #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 20 ),
.din2_WIDTH( 29 ),
.dout_WIDTH( 29 ))
hls_contrast_strecud_U31(
.din0(grp_fu_632_p0),
.din1(grp_fu_632_p1),
.din2(r_V_6_i_reg_718),
.dout(grp_fu_632_p3)
);
hls_contrast_stredEe #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 23 ),
.din2_WIDTH( 29 ),
.dout_WIDTH( 30 ))
hls_contrast_stredEe_U32(
.din0(grp_fu_639_p0),
.din1(grp_fu_639_p1),
.din2(grp_fu_639_p2),
.dout(grp_fu_639_p3)
);
hls_contrast_streeOg #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 9 ),
.din1_WIDTH( 23 ),
.din2_WIDTH( 31 ),
.dout_WIDTH( 32 ))
hls_contrast_streeOg_U33(
.din0(i_op_assign_5_reg_748),
.din1(grp_fu_649_p1),
.din2(grp_fu_649_p2),
.dout(grp_fu_649_p3)
);
hls_contrast_streeOg #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 9 ),
.din1_WIDTH( 23 ),
.din2_WIDTH( 31 ),
.dout_WIDTH( 32 ))
hls_contrast_streeOg_U34(
.din0(i_op_assign_6_reg_753),
.din1(grp_fu_661_p1),
.din2(grp_fu_661_p2),
.dout(grp_fu_661_p3)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_191_p2 == 1'd0))) begin
ap_done_reg <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else begin
if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else if (((tmp_i_fu_191_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
ap_enable_reg_pp0_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
if ((1'b1 == ap_condition_pp0_exit_iter0_state3)) begin
ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state3);
end else if ((1'b1 == 1'b1)) begin
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter2 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter3 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter4 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter5 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter6 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter7 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter8 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end else if (((tmp_i_fu_191_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
ap_enable_reg_pp0_iter8 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state12)) begin
i_i_reg_165 <= i_reg_687;
end else if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
i_i_reg_165 <= 11'd0;
end
end
always @ (posedge ap_clk) begin
if (((tmp_36_i_fu_206_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
j_i_reg_176 <= j_fu_211_p2;
end else if (((tmp_i_fu_191_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
j_i_reg_176 <= 11'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
ap_reg_pp0_iter1_tmp_36_i_reg_692 <= tmp_36_i_reg_692;
tmp_36_i_reg_692 <= tmp_36_i_fu_206_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b0 == ap_block_pp0_stage0_11001)) begin
ap_reg_pp0_iter2_tmp_23_reg_701 <= tmp_23_reg_701;
ap_reg_pp0_iter2_tmp_24_reg_707 <= tmp_24_reg_707;
ap_reg_pp0_iter2_tmp_25_reg_712 <= tmp_25_reg_712;
ap_reg_pp0_iter2_tmp_36_i_reg_692 <= ap_reg_pp0_iter1_tmp_36_i_reg_692;
ap_reg_pp0_iter3_tmp_23_reg_701 <= ap_reg_pp0_iter2_tmp_23_reg_701;
ap_reg_pp0_iter3_tmp_24_reg_707 <= ap_reg_pp0_iter2_tmp_24_reg_707;
ap_reg_pp0_iter3_tmp_25_reg_712 <= ap_reg_pp0_iter2_tmp_25_reg_712;
ap_reg_pp0_iter3_tmp_36_i_reg_692 <= ap_reg_pp0_iter2_tmp_36_i_reg_692;
ap_reg_pp0_iter4_tmp_23_reg_701 <= ap_reg_pp0_iter3_tmp_23_reg_701;
ap_reg_pp0_iter4_tmp_25_reg_712 <= ap_reg_pp0_iter3_tmp_25_reg_712;
ap_reg_pp0_iter4_tmp_36_i_reg_692 <= ap_reg_pp0_iter3_tmp_36_i_reg_692;
ap_reg_pp0_iter5_tmp_36_i_reg_692 <= ap_reg_pp0_iter4_tmp_36_i_reg_692;
ap_reg_pp0_iter6_p_Val2_20_reg_743 <= p_Val2_20_reg_743;
ap_reg_pp0_iter6_tmp_36_i_reg_692 <= ap_reg_pp0_iter5_tmp_36_i_reg_692;
ap_reg_pp0_iter7_p_Val2_20_reg_743 <= ap_reg_pp0_iter6_p_Val2_20_reg_743;
ap_reg_pp0_iter7_signbit_1_reg_791 <= signbit_1_reg_791;
ap_reg_pp0_iter7_signbit_reg_763 <= signbit_reg_763;
ap_reg_pp0_iter7_tmp_36_i_reg_692 <= ap_reg_pp0_iter6_tmp_36_i_reg_692;
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter4_tmp_36_i_reg_692 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
i_op_assign_5_reg_748 <= i_op_assign_5_fu_295_p2;
i_op_assign_6_reg_753 <= i_op_assign_6_fu_304_p2;
p_Val2_20_reg_743 <= p_Val2_20_fu_280_p3;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
i_reg_687 <= i_fu_196_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter6_tmp_36_i_reg_692 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_38_i_i_i15_i_reg_838 <= p_38_i_i_i15_i_fu_497_p2;
p_38_i_i_i_i_reg_820 <= p_38_i_i_i_i_fu_433_p2;
p_39_demorgan_i_i_i_i_reg_826 <= p_39_demorgan_i_i_i_i_fu_439_p2;
p_39_demorgan_i_i_i_reg_844 <= p_39_demorgan_i_i_i_fu_503_p2;
p_Val2_18_reg_832 <= p_Val2_18_fu_454_p2;
p_Val2_8_reg_814 <= p_Val2_8_fu_390_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter5_tmp_36_i_reg_692 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_Val2_16_reg_798 <= {{grp_fu_661_p3[29:22]}};
p_Val2_7_reg_770 <= {{grp_fu_649_p3[29:22]}};
signbit_1_reg_791 <= grp_fu_661_p3[32'd31];
signbit_reg_763 <= grp_fu_649_p3[32'd31];
tmp_13_reg_775 <= grp_fu_649_p3[32'd21];
tmp_17_reg_803 <= grp_fu_661_p3[32'd21];
tmp_1_reg_808 <= {{grp_fu_661_p3[31:30]}};
tmp_s_reg_780 <= {{grp_fu_649_p3[31:30]}};
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter2_tmp_36_i_reg_692 == 1'd1) & (ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_Val2_2_reg_723 <= grp_fu_632_p3;
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter3_tmp_36_i_reg_692 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_Val2_4_reg_733 <= {{grp_fu_639_p3[29:22]}};
tmp_reg_738 <= grp_fu_639_p3[32'd21];
end
end
always @ (posedge ap_clk) begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_cols_V_read_reg_673 <= p_src_cols_V_dout;
p_src_rows_V_read_reg_678 <= p_src_rows_V_dout;
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter3_tmp_36_i_reg_692 == 1'd1) & (ap_enable_reg_pp0_iter4 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
r_V_1_reg_728 <= grp_fu_639_p3;
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter5_tmp_36_i_reg_692 == 1'd1) & (ap_enable_reg_pp0_iter6 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
r_V_2_reg_758 <= grp_fu_649_p3;
r_V_3_reg_786 <= grp_fu_661_p3;
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter1_tmp_36_i_reg_692 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
r_V_6_i_reg_718 <= r_V_6_i_fu_626_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_36_i_reg_692 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
tmp_23_reg_701 <= p_src_data_stream_0_V_dout;
tmp_24_reg_707 <= p_src_data_stream_1_V_dout;
tmp_25_reg_712 <= p_src_data_stream_2_V_dout;
end
end
always @ (*) begin
if ((tmp_36_i_fu_206_p2 == 1'd0)) begin
ap_condition_pp0_exit_iter0_state3 = 1'b1;
end else begin
ap_condition_pp0_exit_iter0_state3 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_191_p2 == 1'd0))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @ (*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_191_p2 == 1'd0))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (((ap_reg_pp0_iter7_tmp_36_i_reg_692 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter8 == 1'b1))) begin
p_dst_data_stream_0_V_blk_n = p_dst_data_stream_0_V_full_n;
end else begin
p_dst_data_stream_0_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((ap_reg_pp0_iter7_tmp_36_i_reg_692 == 1'd1) & (ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_dst_data_stream_0_V_write = 1'b1;
end else begin
p_dst_data_stream_0_V_write = 1'b0;
end
end
always @ (*) begin
if (((ap_reg_pp0_iter7_tmp_36_i_reg_692 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter8 == 1'b1))) begin
p_dst_data_stream_1_V_blk_n = p_dst_data_stream_1_V_full_n;
end else begin
p_dst_data_stream_1_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((ap_reg_pp0_iter7_tmp_36_i_reg_692 == 1'd1) & (ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_dst_data_stream_1_V_write = 1'b1;
end else begin
p_dst_data_stream_1_V_write = 1'b0;
end
end
always @ (*) begin
if (((ap_reg_pp0_iter7_tmp_36_i_reg_692 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter8 == 1'b1))) begin
p_dst_data_stream_2_V_blk_n = p_dst_data_stream_2_V_full_n;
end else begin
p_dst_data_stream_2_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((ap_reg_pp0_iter7_tmp_36_i_reg_692 == 1'd1) & (ap_enable_reg_pp0_iter8 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_dst_data_stream_2_V_write = 1'b1;
end else begin
p_dst_data_stream_2_V_write = 1'b0;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_cols_V_blk_n = p_src_cols_V_empty_n;
end else begin
p_src_cols_V_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_cols_V_read = 1'b1;
end else begin
p_src_cols_V_read = 1'b0;
end
end
always @ (*) begin
if (((tmp_36_i_reg_692 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
p_src_data_stream_0_V_blk_n = p_src_data_stream_0_V_empty_n;
end else begin
p_src_data_stream_0_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((tmp_36_i_reg_692 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_src_data_stream_0_V_read = 1'b1;
end else begin
p_src_data_stream_0_V_read = 1'b0;
end
end
always @ (*) begin
if (((tmp_36_i_reg_692 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
p_src_data_stream_1_V_blk_n = p_src_data_stream_1_V_empty_n;
end else begin
p_src_data_stream_1_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((tmp_36_i_reg_692 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_src_data_stream_1_V_read = 1'b1;
end else begin
p_src_data_stream_1_V_read = 1'b0;
end
end
always @ (*) begin
if (((tmp_36_i_reg_692 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
p_src_data_stream_2_V_blk_n = p_src_data_stream_2_V_empty_n;
end else begin
p_src_data_stream_2_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((tmp_36_i_reg_692 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_src_data_stream_2_V_read = 1'b1;
end else begin
p_src_data_stream_2_V_read = 1'b0;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_rows_V_blk_n = p_src_rows_V_empty_n;
end else begin
p_src_rows_V_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_rows_V_read = 1'b1;
end else begin
p_src_rows_V_read = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_191_p2 == 1'd0))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_pp0_stage0 : begin
if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (tmp_36_i_fu_206_p2 == 1'd0)) & ~((ap_enable_reg_pp0_iter7 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter8 == 1'b1)))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else if ((((ap_enable_reg_pp0_iter7 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter8 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (tmp_36_i_fu_206_p2 == 1'd0)))) begin
ap_NS_fsm = ap_ST_fsm_state12;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_state12 : begin
ap_NS_fsm = ap_ST_fsm_state2;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign Range1_all_ones_1_fu_479_p2 = ((tmp_1_reg_808 == 2'd3) ? 1'b1 : 1'b0);
assign Range1_all_ones_fu_415_p2 = ((tmp_s_reg_780 == 2'd3) ? 1'b1 : 1'b0);
assign Range1_all_zeros_1_fu_484_p2 = ((tmp_1_reg_808 == 2'd0) ? 1'b1 : 1'b0);
assign Range1_all_zeros_fu_420_p2 = ((tmp_s_reg_780 == 2'd0) ? 1'b1 : 1'b0);
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state12 = ap_CS_fsm[32'd3];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage0_01001 = (((ap_enable_reg_pp0_iter8 == 1'b1) & (((ap_reg_pp0_iter7_tmp_36_i_reg_692 == 1'd1) & (p_dst_data_stream_2_V_full_n == 1'b0)) | ((ap_reg_pp0_iter7_tmp_36_i_reg_692 == 1'd1) & (p_dst_data_stream_1_V_full_n == 1'b0)) | ((ap_reg_pp0_iter7_tmp_36_i_reg_692 == 1'd1) & (p_dst_data_stream_0_V_full_n == 1'b0)))) | ((ap_enable_reg_pp0_iter1 == 1'b1) & (((tmp_36_i_reg_692 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_36_i_reg_692 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_36_i_reg_692 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)))));
end
always @ (*) begin
ap_block_pp0_stage0_11001 = (((ap_enable_reg_pp0_iter8 == 1'b1) & (((ap_reg_pp0_iter7_tmp_36_i_reg_692 == 1'd1) & (p_dst_data_stream_2_V_full_n == 1'b0)) | ((ap_reg_pp0_iter7_tmp_36_i_reg_692 == 1'd1) & (p_dst_data_stream_1_V_full_n == 1'b0)) | ((ap_reg_pp0_iter7_tmp_36_i_reg_692 == 1'd1) & (p_dst_data_stream_0_V_full_n == 1'b0)))) | ((ap_enable_reg_pp0_iter1 == 1'b1) & (((tmp_36_i_reg_692 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_36_i_reg_692 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_36_i_reg_692 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)))));
end
always @ (*) begin
ap_block_pp0_stage0_subdone = (((ap_enable_reg_pp0_iter8 == 1'b1) & (((ap_reg_pp0_iter7_tmp_36_i_reg_692 == 1'd1) & (p_dst_data_stream_2_V_full_n == 1'b0)) | ((ap_reg_pp0_iter7_tmp_36_i_reg_692 == 1'd1) & (p_dst_data_stream_1_V_full_n == 1'b0)) | ((ap_reg_pp0_iter7_tmp_36_i_reg_692 == 1'd1) & (p_dst_data_stream_0_V_full_n == 1'b0)))) | ((ap_enable_reg_pp0_iter1 == 1'b1) & (((tmp_36_i_reg_692 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_36_i_reg_692 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_36_i_reg_692 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)))));
end
always @ (*) begin
ap_block_state1 = ((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1));
end
assign ap_block_state10_pp0_stage0_iter7 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state11_pp0_stage0_iter8 = (((ap_reg_pp0_iter7_tmp_36_i_reg_692 == 1'd1) & (p_dst_data_stream_2_V_full_n == 1'b0)) | ((ap_reg_pp0_iter7_tmp_36_i_reg_692 == 1'd1) & (p_dst_data_stream_1_V_full_n == 1'b0)) | ((ap_reg_pp0_iter7_tmp_36_i_reg_692 == 1'd1) & (p_dst_data_stream_0_V_full_n == 1'b0)));
end
assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state4_pp0_stage0_iter1 = (((tmp_36_i_reg_692 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_36_i_reg_692 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_36_i_reg_692 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)));
end
assign ap_block_state5_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state6_pp0_stage0_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state7_pp0_stage0_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state8_pp0_stage0_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state9_pp0_stage0_iter6 = ~(1'b1 == 1'b1);
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
assign brmerge_i_i23_i_fu_597_p2 = (p_39_demorgan_i_not_i_1_fu_592_p2 | neg_src_not_i_i20_i_fu_582_p2);
assign brmerge_i_i_i_fu_538_p2 = (p_39_demorgan_i_not_i_fu_533_p2 | neg_src_not_i_i_i_fu_523_p2);
assign brmerge_i_i_not_i_i2_fu_587_p2 = (p_39_demorgan_i_i_i_reg_844 & neg_src_not_i_i20_i_fu_582_p2);
assign brmerge_i_i_not_i_i_s_fu_528_p2 = (p_39_demorgan_i_i_i_i_reg_826 & neg_src_not_i_i_i_fu_523_p2);
assign carry_1_fu_473_p2 = (tmp_18_fu_447_p3 & tmp_17_i_i10_i_fu_467_p2);
assign carry_fu_409_p2 = (tmp_17_i_i_i_fu_403_p2 & tmp_14_fu_383_p3);
assign deleted_zeros_1_fu_489_p3 = ((carry_1_fu_473_p2[0:0] === 1'b1) ? Range1_all_ones_1_fu_479_p2 : Range1_all_zeros_1_fu_484_p2);
assign deleted_zeros_fu_425_p3 = ((carry_fu_409_p2[0:0] === 1'b1) ? Range1_all_ones_fu_415_p2 : Range1_all_zeros_fu_420_p2);
assign grp_fu_632_p0 = grp_fu_632_p00;
assign grp_fu_632_p00 = ap_reg_pp0_iter2_tmp_25_reg_712;
assign grp_fu_632_p1 = 28'd478150;
assign grp_fu_639_p0 = grp_fu_639_p00;
assign grp_fu_639_p00 = ap_reg_pp0_iter3_tmp_24_reg_707;
assign grp_fu_639_p1 = 30'd2462056;
assign grp_fu_639_p2 = grp_fu_639_p20;
assign grp_fu_639_p20 = p_Val2_2_reg_723;
assign grp_fu_649_p1 = 32'd2990538;
assign grp_fu_649_p2 = 32'd536870912;
assign grp_fu_661_p1 = 32'd2365587;
assign grp_fu_661_p2 = 32'd536870912;
assign i_cast_i_cast_fu_187_p1 = i_i_reg_165;
assign i_fu_196_p2 = (i_i_reg_165 + 11'd1);
assign i_op_assign_5_fu_295_p2 = (tmp_30_cast_i_fu_288_p1 - tmp_31_cast_i_fu_291_p1);
assign i_op_assign_6_fu_304_p2 = (tmp_33_cast_i_fu_301_p1 - tmp_31_cast_i_fu_291_p1);
assign j_cast_i_cast_fu_202_p1 = j_i_reg_176;
assign j_fu_211_p2 = (j_i_reg_176 + 11'd1);
assign neg_src_4_fu_572_p2 = (tmp_18_i_i16_i_fu_567_p2 & ap_reg_pp0_iter7_signbit_1_reg_791);
assign neg_src_fu_513_p2 = (tmp_18_i_i_i_fu_508_p2 & ap_reg_pp0_iter7_signbit_reg_763);
assign neg_src_not_i_i20_i_fu_582_p2 = (signbit_not_i19_i_fu_577_p2 | p_38_i_i_i15_i_reg_838);
assign neg_src_not_i_i_i_fu_523_p2 = (signbit_not_i_i_fu_518_p2 | p_38_i_i_i_i_reg_820);
assign not_carry_i_fu_274_p2 = (tmp_11_fu_260_p3 | p_Result_2_i_i_not_fu_268_p2);
assign p_38_i_i_i15_i_fu_497_p2 = (carry_1_fu_473_p2 & Range1_all_ones_1_fu_479_p2);
assign p_38_i_i_i_i_fu_433_p2 = (carry_fu_409_p2 & Range1_all_ones_fu_415_p2);
assign p_39_demorgan_i_i_i_fu_503_p2 = (signbit_1_reg_791 | deleted_zeros_1_fu_489_p3);
assign p_39_demorgan_i_i_i_i_fu_439_p2 = (signbit_reg_763 | deleted_zeros_fu_425_p3);
assign p_39_demorgan_i_not_i_1_fu_592_p2 = (p_39_demorgan_i_i_i_reg_844 ^ 1'd1);
assign p_39_demorgan_i_not_i_fu_533_p2 = (p_39_demorgan_i_i_i_i_reg_826 ^ 1'd1);
assign p_Result_2_i_i_not_fu_268_p2 = (tmp_10_fu_248_p3 ^ 1'd1);
assign p_Val2_18_fu_454_p2 = (p_Val2_16_reg_798 + tmp_16_i_i6_i_fu_444_p1);
assign p_Val2_20_fu_280_p3 = ((not_carry_i_fu_274_p2[0:0] === 1'b1) ? p_Val2_5_fu_255_p2 : 8'd255);
assign p_Val2_5_fu_255_p2 = (p_Val2_4_reg_733 + tmp_19_i_i_i_fu_245_p1);
assign p_Val2_8_fu_390_p2 = (p_Val2_7_reg_770 + tmp_16_i_i_i_fu_380_p1);
assign p_dst_data_stream_0_V_din = ap_reg_pp0_iter7_p_Val2_20_reg_743;
assign p_dst_data_stream_1_V_din = ((brmerge_i_i_i_fu_538_p2[0:0] === 1'b1) ? p_mux_i_i2_i_fu_544_p3 : p_i_i_i_fu_551_p3);
assign p_dst_data_stream_2_V_din = ((brmerge_i_i23_i_fu_597_p2[0:0] === 1'b1) ? p_mux_i_i24_i_fu_603_p3 : p_i_i25_i_fu_610_p3);
assign p_i_i25_i_fu_610_p3 = ((neg_src_4_fu_572_p2[0:0] === 1'b1) ? 8'd0 : p_Val2_18_reg_832);
assign p_i_i_i_fu_551_p3 = ((neg_src_fu_513_p2[0:0] === 1'b1) ? 8'd0 : p_Val2_8_reg_814);
assign p_mux_i_i24_i_fu_603_p3 = ((brmerge_i_i_not_i_i2_fu_587_p2[0:0] === 1'b1) ? p_Val2_18_reg_832 : 8'd255);
assign p_mux_i_i2_i_fu_544_p3 = ((brmerge_i_i_not_i_i_s_fu_528_p2[0:0] === 1'b1) ? p_Val2_8_reg_814 : 8'd255);
assign r_V_6_i_fu_626_p0 = r_V_6_i_fu_626_p00;
assign r_V_6_i_fu_626_p00 = tmp_23_reg_701;
assign r_V_6_i_fu_626_p1 = 29'd1254096;
assign signbit_not_i19_i_fu_577_p2 = (ap_reg_pp0_iter7_signbit_1_reg_791 ^ 1'd1);
assign signbit_not_i_i_fu_518_p2 = (ap_reg_pp0_iter7_signbit_reg_763 ^ 1'd1);
assign tmp_10_fu_248_p3 = r_V_1_reg_728[32'd29];
assign tmp_11_fu_260_p3 = p_Val2_5_fu_255_p2[32'd7];
assign tmp_14_fu_383_p3 = r_V_2_reg_758[32'd29];
assign tmp_15_fu_395_p3 = p_Val2_8_fu_390_p2[32'd7];
assign tmp_16_i_i6_i_fu_444_p1 = tmp_17_reg_803;
assign tmp_16_i_i_i_fu_380_p1 = tmp_13_reg_775;
assign tmp_17_i_i10_i_fu_467_p2 = (tmp_19_fu_459_p3 ^ 1'd1);
assign tmp_17_i_i_i_fu_403_p2 = (tmp_15_fu_395_p3 ^ 1'd1);
assign tmp_18_fu_447_p3 = r_V_3_reg_786[32'd29];
assign tmp_18_i_i16_i_fu_567_p2 = (p_38_i_i_i15_i_reg_838 ^ 1'd1);
assign tmp_18_i_i_i_fu_508_p2 = (p_38_i_i_i_i_reg_820 ^ 1'd1);
assign tmp_19_fu_459_p3 = p_Val2_18_fu_454_p2[32'd7];
assign tmp_19_i_i_i_fu_245_p1 = tmp_reg_738;
assign tmp_30_cast_i_fu_288_p1 = ap_reg_pp0_iter4_tmp_23_reg_701;
assign tmp_31_cast_i_fu_291_p1 = p_Val2_20_fu_280_p3;
assign tmp_33_cast_i_fu_301_p1 = ap_reg_pp0_iter4_tmp_25_reg_712;
assign tmp_36_i_fu_206_p2 = ((j_cast_i_cast_fu_202_p1 < p_src_cols_V_read_reg_673) ? 1'b1 : 1'b0);
assign tmp_i_fu_191_p2 = ((i_cast_i_cast_fu_187_p1 < p_src_rows_V_read_reg_678) ? 1'b1 : 1'b0);
endmodule //CvtColor_1
|
/*
* phase_shift_check.v: Helper module to check the phase shift of an input
* signal (clk_shifted) relative to another signal (clk) and compare it
* with the desired shift.
* author: Till Mahlburg
* year: 2020
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
/* checks the phase shift of the input signal in relation to clk */
module phase_shift_check (
input [31:0] desired_shift_1000,
input [31:0] clk_period_1000,
input clk_shifted,
input clk,
input rst,
/* input to tell the module, that the inputs are ready */
input LOCKED,
output reg fail);
always @(posedge clk or posedge rst) begin
if (rst) begin
fail <= 0;
end else if (LOCKED) begin
if (desired_shift_1000 > 0) begin
#(((desired_shift_1000 / 1000.0) * ((clk_period_1000 / 1000.0) / 360.0)) - 0.1);
if (clk_shifted !== 0) begin
fail <= 1;
end
end else if (desired_shift_1000 < 0) begin
#(((clk_period_1000 / 1000.0) + ((desired_shift_1000 / 1000.0) * ((clk_period_1000 / 1000.0) / 360.0))) - 0.1);
if (clk_shifted !== 0) begin
fail <= 1;
end
end
#0.2;
if (clk_shifted !== 1 && desired_shift_1000 !== 0) begin
fail <= 1;
end
end
end
endmodule
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP0} dataWidth={32} clockFreq={100} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=525, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=-0.073, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=-0.034, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.03, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.082, PCW_UIPARAM_DDR_BOARD_DELAY0=0.176, PCW_UIPARAM_DDR_BOARD_DELAY1=0.159, PCW_UIPARAM_DDR_BOARD_DELAY2=0.162, PCW_UIPARAM_DDR_BOARD_DELAY3=0.187, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=50.000000, PCW_APU_PERIPHERAL_FREQMHZ=650, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=100, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100, PCW_FPGA1_PERIPHERAL_FREQMHZ=50, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=26, PCW_IOPLL_CTRL_FBDIV=20, PCW_DDRPLL_CTRL_FBDIV=21, PCW_CPU_CPU_PLL_FREQMHZ=1300.000, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1050.000, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=1, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=100, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=32, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K128M16 JT-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=1, PCW_QSPI_GRP_FBCLK_IO=MIO 8, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=EMIO, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=1, PCW_USB0_RESET_IO=MIO 46, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *)
(* HW_HANDOFF = "design_TEST_processing_system7_0_0.hwdef" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0,
// Enable and disable AFI Secure transaction
parameter C_USE_AXI_NONSECURE = 0,
//parameters for HP enable ports
parameter C_USE_S_AXI_HP0 = 0,
parameter C_USE_S_AXI_HP1 = 0,
parameter C_USE_S_AXI_HP2 = 0,
parameter C_USE_S_AXI_HP3 = 0,
//parameters for GP and ACP enable ports */
parameter C_USE_M_AXI_GP0 = 0,
parameter C_USE_M_AXI_GP1 = 0,
parameter C_USE_S_AXI_GP0 = 0,
parameter C_USE_S_AXI_GP1 = 0,
parameter C_USE_S_AXI_ACP = 0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN = 'b0,
output reg ENET0_GMII_TX_ER = 'b0,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN = 'b0,
output reg ENET1_GMII_TX_ER = 'b0,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
// Wires for connecting to the PS7
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
wire FCLK_CLK0_temp;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
else
begin
always @*
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= 1'b0;
TRACE_DATA_PIPE[j-1] <= 1'b0;
end
TRACE_CLK_OUT <= 1'b0;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
wire S_AXI_GP0_ARESETN_shim;
wire S_AXI_GP0_ARREADY_shim;
wire S_AXI_GP0_AWREADY_shim;
wire S_AXI_GP0_BVALID_shim;
wire S_AXI_GP0_RLAST_shim;
wire S_AXI_GP0_RVALID_shim;
wire S_AXI_GP0_WREADY_shim;
wire [1:0] S_AXI_GP0_BRESP_shim;
wire [1:0] S_AXI_GP0_RRESP_shim;
wire [31:0] S_AXI_GP0_RDATA_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID_out_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID_out_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID_shim;
wire S_AXI_GP0_ACLK_shim;
wire S_AXI_GP0_ARVALID_shim;
wire S_AXI_GP0_AWVALID_shim;
wire S_AXI_GP0_BREADY_shim;
wire S_AXI_GP0_RREADY_shim;
wire S_AXI_GP0_WLAST_shim;
wire S_AXI_GP0_WVALID_shim;
wire [1:0] S_AXI_GP0_ARBURST_shim;
wire [1:0] S_AXI_GP0_ARLOCK_shim;
wire [2:0] S_AXI_GP0_ARSIZE_shim;
wire [1:0] S_AXI_GP0_AWBURST_shim;
wire [1:0] S_AXI_GP0_AWLOCK_shim;
wire [2:0] S_AXI_GP0_AWSIZE_shim;
wire [2:0] S_AXI_GP0_ARPROT_shim;
wire [2:0] S_AXI_GP0_AWPROT_shim;
wire [31:0] S_AXI_GP0_ARADDR_shim;
wire [31:0] S_AXI_GP0_AWADDR_shim;
wire [31:0] S_AXI_GP0_WDATA_shim;
wire [3:0] S_AXI_GP0_ARCACHE_shim;
wire [3:0] S_AXI_GP0_ARLEN_shim;
wire [3:0] S_AXI_GP0_ARQOS_shim;
wire [3:0] S_AXI_GP0_AWCACHE_shim;
wire [3:0] S_AXI_GP0_AWLEN_shim;
wire [3:0] S_AXI_GP0_AWQOS_shim;
wire [3:0] S_AXI_GP0_WSTRB_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID_in_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID_in_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID_in_shim;
xlnx_axi_wrshim_unwrap #
(
.ID_WIDTH(C_S_AXI_GP0_ID_WIDTH),
.D_WIDTH(32)
)xlnx_axi_wrshim_unwrap_inst_gp0
(
.clk(S_AXI_GP0_ACLK_temp),
.rst_n(S_AXI_GP0_ARESETN),
.awqos_in(S_AXI_GP0_AWQOS),
.awid_in(S_AXI_GP0_AWID_in),
.awaddr_in(S_AXI_GP0_AWADDR),
.awlen_in(S_AXI_GP0_AWLEN),
.awsize_in(S_AXI_GP0_AWSIZE),
.awburst_in(S_AXI_GP0_AWBURST),
.awlock_in(S_AXI_GP0_AWLOCK),
.awcache_in(S_AXI_GP0_AWCACHE),
.awprot_in(S_AXI_GP0_AWPROT),
.awvalid_in(S_AXI_GP0_AWVALID),
.wdata_in(S_AXI_GP0_WDATA),
.wid_in(S_AXI_GP0_WID_in),
.wstrb_in(S_AXI_GP0_WSTRB),
.wlast_in(S_AXI_GP0_WLAST),
.wvalid_in(S_AXI_GP0_WVALID),
.bready_in(S_AXI_GP0_BREADY),
.arqos_in(S_AXI_GP0_ARQOS),
.arid_in(S_AXI_GP0_ARID_in),
.araddr_in(S_AXI_GP0_ARADDR),
.arlen_in(S_AXI_GP0_ARLEN),
.arsize_in(S_AXI_GP0_ARSIZE),
.arburst_in(S_AXI_GP0_ARBURST),
.arlock_in(S_AXI_GP0_ARLOCK),
.arcache_in(S_AXI_GP0_ARCACHE),
.arprot_in(S_AXI_GP0_ARPROT),
.arvalid_in(S_AXI_GP0_ARVALID),
.rready_in(S_AXI_GP0_RREADY),
.awready_in(S_AXI_GP0_AWREADY),
.arready_in(S_AXI_GP0_ARREADY),
.rid_in(S_AXI_GP0_RID),
.rdata_in(S_AXI_GP0_RDATA),
.rresp_in(S_AXI_GP0_RRESP),
.rlast_in(S_AXI_GP0_RLAST),
.rvalid_in(S_AXI_GP0_RVALID),
.wready_in(S_AXI_GP0_WREADY),
.bid_in(S_AXI_GP0_BID),
.bresp_in(S_AXI_GP0_BRESP),
.bvalid_in(S_AXI_GP0_BVALID),
.awqos_out(S_AXI_GP0_AWQOS_shim),
.awid_out(S_AXI_GP0_AWID_in_shim),
.awaddr_out(S_AXI_GP0_AWADDR_shim),
.awlen_out(S_AXI_GP0_AWLEN_shim),
.awsize_out(S_AXI_GP0_AWSIZE_shim),
.awburst_out(S_AXI_GP0_AWBURST_shim),
.awlock_out(S_AXI_GP0_AWLOCK_shim),
.awcache_out(S_AXI_GP0_AWCACHE_shim),
.awprot_out(S_AXI_GP0_AWPROT_shim),
.awvalid_out(S_AXI_GP0_AWVALID_shim),
.wdata_out(S_AXI_GP0_WDATA_shim),
.wid_out(S_AXI_GP0_WID_in_shim),
.wstrb_out(S_AXI_GP0_WSTRB_shim),
.wlast_out(S_AXI_GP0_WLAST_shim),
.wvalid_out(S_AXI_GP0_WVALID_shim),
.bready_out(S_AXI_GP0_BREADY_shim),
.arqos_out(S_AXI_GP0_ARQOS_shim),
.arid_out(S_AXI_GP0_ARID_in_shim),
.araddr_out(S_AXI_GP0_ARADDR_shim),
.arlen_out(S_AXI_GP0_ARLEN_shim),
.arsize_out(S_AXI_GP0_ARSIZE_shim),
.arburst_out(S_AXI_GP0_ARBURST_shim),
.arlock_out(S_AXI_GP0_ARLOCK_shim),
.arcache_out(S_AXI_GP0_ARCACHE_shim),
.arprot_out(S_AXI_GP0_ARPROT_shim),
.arvalid_out(S_AXI_GP0_ARVALID_shim),
.rready_out(S_AXI_GP0_RREADY_shim),
.awready_out(S_AXI_GP0_AWREADY_shim),
.arready_out(S_AXI_GP0_ARREADY_shim),
.rid_out(S_AXI_GP0_RID_shim),
.rdata_out(S_AXI_GP0_RDATA_shim),
.rresp_out(S_AXI_GP0_RRESP_shim),
.rlast_out(S_AXI_GP0_RLAST_shim),
.rvalid_out(S_AXI_GP0_RVALID_shim),
.wready_out(S_AXI_GP0_WREADY_shim),
.bid_out(S_AXI_GP0_BID_shim),
.bresp_out(S_AXI_GP0_BRESP_shim),
.bvalid_out(S_AXI_GP0_BVALID_shim));
wire S_AXI_GP1_ARESETN_shim;
wire S_AXI_GP1_ARREADY_shim;
wire S_AXI_GP1_AWREADY_shim;
wire S_AXI_GP1_BVALID_shim;
wire S_AXI_GP1_RLAST_shim;
wire S_AXI_GP1_RVALID_shim;
wire S_AXI_GP1_WREADY_shim;
wire [1:0] S_AXI_GP1_BRESP_shim;
wire [1:0] S_AXI_GP1_RRESP_shim;
wire [31:0] S_AXI_GP1_RDATA_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID_out_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID_out_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID_shim;
// -- Input
wire S_AXI_GP1_ACLK_shim;
wire S_AXI_GP1_ARVALID_shim;
wire S_AXI_GP1_AWVALID_shim;
wire S_AXI_GP1_BREADY_shim;
wire S_AXI_GP1_RREADY_shim;
wire S_AXI_GP1_WLAST_shim;
wire S_AXI_GP1_WVALID_shim;
wire [1:0] S_AXI_GP1_ARBURST_shim;
wire [1:0] S_AXI_GP1_ARLOCK_shim;
wire [2:0] S_AXI_GP1_ARSIZE_shim;
wire [1:0] S_AXI_GP1_AWBURST_shim;
wire [1:0] S_AXI_GP1_AWLOCK_shim;
wire [2:0] S_AXI_GP1_AWSIZE_shim;
wire [2:0] S_AXI_GP1_ARPROT_shim;
wire [2:0] S_AXI_GP1_AWPROT_shim;
wire [31:0] S_AXI_GP1_ARADDR_shim;
wire [31:0] S_AXI_GP1_AWADDR_shim;
wire [31:0] S_AXI_GP1_WDATA_shim;
wire [3:0] S_AXI_GP1_ARCACHE_shim;
wire [3:0] S_AXI_GP1_ARLEN_shim;
wire [3:0] S_AXI_GP1_ARQOS_shim;
wire [3:0] S_AXI_GP1_AWCACHE_shim;
wire [3:0] S_AXI_GP1_AWLEN_shim;
wire [3:0] S_AXI_GP1_AWQOS_shim;
wire [3:0] S_AXI_GP1_WSTRB_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID_in_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID_in_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID_in_shim;
xlnx_axi_wrshim_unwrap #
(
.ID_WIDTH(C_S_AXI_GP1_ID_WIDTH),
.D_WIDTH(32)
)xlnx_axi_wrshim_unwrap_inst_gp1
(
.clk(S_AXI_GP1_ACLK_temp),
.rst_n(S_AXI_GP1_ARESETN),
.awqos_in(S_AXI_GP1_AWQOS),
.awid_in(S_AXI_GP1_AWID_in),
.awaddr_in(S_AXI_GP1_AWADDR),
.awlen_in(S_AXI_GP1_AWLEN),
.awsize_in(S_AXI_GP1_AWSIZE),
.awburst_in(S_AXI_GP1_AWBURST),
.awlock_in(S_AXI_GP1_AWLOCK),
.awcache_in(S_AXI_GP1_AWCACHE),
.awprot_in(S_AXI_GP1_AWPROT),
.awvalid_in(S_AXI_GP1_AWVALID),
.wdata_in(S_AXI_GP1_WDATA),
.wid_in(S_AXI_GP1_WID_in),
.wstrb_in(S_AXI_GP1_WSTRB),
.wlast_in(S_AXI_GP1_WLAST),
.wvalid_in(S_AXI_GP1_WVALID),
.bready_in(S_AXI_GP1_BREADY),
.arqos_in(S_AXI_GP1_ARQOS),
.arid_in(S_AXI_GP1_ARID_in),
.araddr_in(S_AXI_GP1_ARADDR),
.arlen_in(S_AXI_GP1_ARLEN),
.arsize_in(S_AXI_GP1_ARSIZE),
.arburst_in(S_AXI_GP1_ARBURST),
.arlock_in(S_AXI_GP1_ARLOCK),
.arcache_in(S_AXI_GP1_ARCACHE),
.arprot_in(S_AXI_GP1_ARPROT),
.arvalid_in(S_AXI_GP1_ARVALID),
.rready_in(S_AXI_GP1_RREADY),
.awready_in(S_AXI_GP1_AWREADY),
.arready_in(S_AXI_GP1_ARREADY),
.rid_in(S_AXI_GP1_RID),
.rdata_in(S_AXI_GP1_RDATA),
.rresp_in(S_AXI_GP1_RRESP),
.rlast_in(S_AXI_GP1_RLAST),
.rvalid_in(S_AXI_GP1_RVALID),
.wready_in(S_AXI_GP1_WREADY),
.bid_in(S_AXI_GP1_BID),
.bresp_in(S_AXI_GP1_BRESP),
.bvalid_in(S_AXI_GP1_BVALID),
.awqos_out(S_AXI_GP1_AWQOS_shim),
.awid_out(S_AXI_GP1_AWID_in_shim),
.awaddr_out(S_AXI_GP1_AWADDR_shim),
.awlen_out(S_AXI_GP1_AWLEN_shim),
.awsize_out(S_AXI_GP1_AWSIZE_shim),
.awburst_out(S_AXI_GP1_AWBURST_shim),
.awlock_out(S_AXI_GP1_AWLOCK_shim),
.awcache_out(S_AXI_GP1_AWCACHE_shim),
.awprot_out(S_AXI_GP1_AWPROT_shim),
.awvalid_out(S_AXI_GP1_AWVALID_shim),
.wdata_out(S_AXI_GP1_WDATA_shim),
.wid_out(S_AXI_GP1_WID_in_shim),
.wstrb_out(S_AXI_GP1_WSTRB_shim),
.wlast_out(S_AXI_GP1_WLAST_shim),
.wvalid_out(S_AXI_GP1_WVALID_shim),
.bready_out(S_AXI_GP1_BREADY_shim),
.arqos_out(S_AXI_GP1_ARQOS_shim),
.arid_out(S_AXI_GP1_ARID_in_shim),
.araddr_out(S_AXI_GP1_ARADDR_shim),
.arlen_out(S_AXI_GP1_ARLEN_shim),
.arsize_out(S_AXI_GP1_ARSIZE_shim),
.arburst_out(S_AXI_GP1_ARBURST_shim),
.arlock_out(S_AXI_GP1_ARLOCK_shim),
.arcache_out(S_AXI_GP1_ARCACHE_shim),
.arprot_out(S_AXI_GP1_ARPROT_shim),
.arvalid_out(S_AXI_GP1_ARVALID_shim),
.rready_out(S_AXI_GP1_RREADY_shim),
.awready_out(S_AXI_GP1_AWREADY_shim),
.arready_out(S_AXI_GP1_ARREADY_shim),
.rid_out(S_AXI_GP1_RID_shim),
.rdata_out(S_AXI_GP1_RDATA_shim),
.rresp_out(S_AXI_GP1_RRESP_shim),
.rlast_out(S_AXI_GP1_RLAST_shim),
.rvalid_out(S_AXI_GP1_RVALID_shim),
.wready_out(S_AXI_GP1_WREADY_shim),
.bid_out(S_AXI_GP1_BID_shim),
.bresp_out(S_AXI_GP1_BRESP_shim),
.bvalid_out(S_AXI_GP1_BVALID_shim));
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
else
always@*
begin
ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= 'b0;
ENET0_GMII_CRS_i <= 'b0;
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET0_GMII_RXD_i <= 0;
ENET0_GMII_RX_DV_i <= 0;
ENET0_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
else
begin
always@*
begin
ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET1_GMII_COL_i <= 0;
ENET1_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET1_GMII_RXD_i <= 'b0;
ENET1_GMII_RX_DV_i <= 'b0;
ENET1_GMII_RX_ER_i <= 'b0;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
else
begin
assign FTMD_TRACEIN_DATA_i = 1'b0;
assign FTMD_TRACEIN_VALID_i = 1'b0;
assign FTMD_TRACEIN_ATID_i = 1'b0;
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID_shim = id_out_gp0(S_AXI_GP0_BID_out_shim);
assign S_AXI_GP0_RID_shim = id_out_gp0(S_AXI_GP0_RID_out_shim);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID_shim = id_out_gp1(S_AXI_GP1_BID_out_shim);
assign S_AXI_GP1_RID_shim = id_out_gp1(S_AXI_GP1_RID_out_shim);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
else
begin
assign PJTAG_TDO = 1'b0;
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
assign FCLK_CLK0 = FCLK_CLK0_temp;
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
// Connect FCLK in case of disable the AXI port for non Secure Transaction
//Start
wire S_AXI_HP0_ACLK_temp;
wire S_AXI_HP1_ACLK_temp;
wire S_AXI_HP2_ACLK_temp;
wire S_AXI_HP3_ACLK_temp;
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin
assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin
assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin
assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin
assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK;
end
endgenerate
//Start
wire M_AXI_GP0_ACLK_temp;
wire M_AXI_GP1_ACLK_temp;
wire S_AXI_GP0_ACLK_temp;
wire S_AXI_GP1_ACLK_temp;
wire S_AXI_ACP_ACLK_temp;
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin
assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin
assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin
assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin
assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin
assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;
end
endgenerate
//END
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY_shim),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY_shim),
.SAXIGP0BID (S_AXI_GP0_BID_out_shim),
.SAXIGP0BRESP (S_AXI_GP0_BRESP_shim ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID_shim ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA_shim ),
.SAXIGP0RID (S_AXI_GP0_RID_out_shim ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST_shim ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP_shim ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID_shim ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY_shim ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY_shim),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY_shim),
.SAXIGP1BID (S_AXI_GP1_BID_out_shim ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP_shim ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID_shim ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA_shim ),
.SAXIGP1RID (S_AXI_GP1_RID_out_shim ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST_shim ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP_shim ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID_shim ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY_shim ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR_shim ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST_shim),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE_shim),
.SAXIGP0ARID (S_AXI_GP0_ARID_in_shim ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN_shim ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK_shim ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT_shim ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS_shim ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE_shim[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID_shim),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR_shim ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST_shim),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE_shim),
.SAXIGP0AWID (S_AXI_GP0_AWID_in_shim ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN_shim ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK_shim ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT_shim ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS_shim ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE_shim[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID_shim),
.SAXIGP0BREADY (S_AXI_GP0_BREADY_shim ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY_shim ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA_shim ),
.SAXIGP0WID (S_AXI_GP0_WID_in_shim ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST_shim ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB_shim ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID_shim ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR_shim ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST_shim),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE_shim),
.SAXIGP1ARID (S_AXI_GP1_ARID_in_shim ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN_shim ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK_shim ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT_shim ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS_shim ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE_shim[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID_shim),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR_shim ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST_shim),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE_shim),
.SAXIGP1AWID (S_AXI_GP1_AWID_in_shim ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN_shim ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK_shim ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT_shim ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS_shim ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE_shim[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID_shim),
.SAXIGP1BREADY (S_AXI_GP1_BREADY_shim ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY_shim ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA_shim ),
.SAXIGP1WID (S_AXI_GP1_WID_in_shim ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST_shim ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB_shim ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID_shim ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY_shim),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY_shim),
.SAXIGP0BID (S_AXI_GP0_BID_out_shim),
.SAXIGP0BRESP (S_AXI_GP0_BRESP_shim ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID_shim ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA_shim ),
.SAXIGP0RID (S_AXI_GP0_RID_out_shim ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST_shim ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP_shim ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID_shim ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY_shim ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY_shim),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY_shim),
.SAXIGP1BID (S_AXI_GP1_BID_out_shim ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP_shim ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID_shim ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA_shim ),
.SAXIGP1RID (S_AXI_GP1_RID_out_shim ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST_shim ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP_shim ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID_shim ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY_shim ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR_shim ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST_shim),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE_shim),
.SAXIGP0ARID (S_AXI_GP0_ARID_in_shim ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN_shim ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK_shim ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT_shim ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS_shim ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE_shim[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID_shim),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR_shim ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST_shim),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE_shim),
.SAXIGP0AWID (S_AXI_GP0_AWID_in_shim ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN_shim ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK_shim ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT_shim ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS_shim ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE_shim[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID_shim),
.SAXIGP0BREADY (S_AXI_GP0_BREADY_shim ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY_shim ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA_shim ),
.SAXIGP0WID (S_AXI_GP0_WID_in_shim ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST_shim ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB_shim ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID_shim ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR_shim ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST_shim),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE_shim),
.SAXIGP1ARID (S_AXI_GP1_ARID_in_shim ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN_shim ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK_shim ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT_shim ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS_shim ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE_shim[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID_shim),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR_shim ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST_shim),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE_shim),
.SAXIGP1AWID (S_AXI_GP1_AWID_in_shim ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN_shim ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK_shim ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT_shim ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS_shim ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE_shim[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID_shim),
.SAXIGP1BREADY (S_AXI_GP1_BREADY_shim ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY_shim ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA_shim ),
.SAXIGP1WID (S_AXI_GP1_WID_in_shim ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST_shim ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB_shim ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID_shim ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK_temp),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
/****************************************************************************
* Xilinx Confidential
* Copyright 2013 Xilinx, Inc. All rights reserved
*
* File: xlnx_axi_wrshim_unwrap.sv
* Owner: jmurray
* Initial Date: 22-May-2013
*
*
* Description:
* - Wr Shim to prevent PCIe lockup scenario
* - Should be inserted inline with any masters WrData and WrCmd AXI
* channels
* - Will not allow the wrCmd to be issued unless the first beat of
* the associated wrBurst is available
* - Likewise, will not allow the first beat of wrData to be issued
* unless the associated wrCmd is available
*
****************************************************************************/
module xlnx_axi_wrshim_unwrap #(
parameter ID_WIDTH = 6, // ID width
parameter AD_WIDTH = 32, // Address Width
parameter D_WIDTH = 64 // Data Width
)
(
//
//*********** MISC Signals *****************
//
input clk,
input rst_n,
//input apb_en_wrshim,
//
//*********** FUll AXI Interface Input (from Master) *****************
//
input[3:0] awqos_in,
input[ID_WIDTH-1:0] awid_in,
input[AD_WIDTH-1:0] awaddr_in,
input[3:0] awlen_in,
input[2:0] awsize_in,
input[1:0] awburst_in,
input[1:0] awlock_in,
input[3:0] awcache_in,
input[2:0] awprot_in,
input awvalid_in,
output awready_in,
input[D_WIDTH-1:0] wdata_in,
input[ID_WIDTH-1:0] wid_in,
input[D_WIDTH/8-1:0] wstrb_in,
input wlast_in,
input wvalid_in,
output wready_in,
output[ID_WIDTH-1:0] bid_in,
output[1:0] bresp_in,
output bvalid_in,
input bready_in,
input[3:0] arqos_in,
input[ID_WIDTH-1:0] arid_in,
input[AD_WIDTH-1:0] araddr_in,
input[3:0] arlen_in,
input[2:0] arsize_in,
input[1:0] arburst_in,
input[1:0] arlock_in,
input[3:0] arcache_in,
input[2:0] arprot_in,
input arvalid_in,
output arready_in,
output[ID_WIDTH-1:0] rid_in,
output[D_WIDTH-1:0] rdata_in,
output[1:0] rresp_in,
output rlast_in,
output rvalid_in,
input rready_in,
//
//*********** FUll AXI Interface Input (to Slave ) *****************
//
output[3:0] awqos_out,
output[ID_WIDTH-1:0] awid_out,
output[AD_WIDTH-1:0] awaddr_out,
output[3:0] awlen_out,
output[2:0] awsize_out,
output[1:0] awburst_out,
output[1:0] awlock_out,
output[3:0] awcache_out,
output[2:0] awprot_out,
output awvalid_out,
input awready_out,
output[D_WIDTH-1:0] wdata_out,
output[ID_WIDTH-1:0] wid_out,
output[D_WIDTH/8-1:0] wstrb_out,
output wlast_out,
output wvalid_out,
input wready_out,
input[ID_WIDTH-1:0] bid_out,
input[1:0] bresp_out,
input bvalid_out,
output bready_out,
output[3:0] arqos_out,
output[ID_WIDTH-1:0] arid_out,
output[AD_WIDTH-1:0] araddr_out,
output[3:0] arlen_out,
output[2:0] arsize_out,
output[1:0] arburst_out,
output[1:0] arlock_out,
output[3:0] arcache_out,
output[2:0] arprot_out,
output arvalid_out,
input arready_out,
input[ID_WIDTH-1:0] rid_out,
input[D_WIDTH-1:0] rdata_out,
input[1:0] rresp_out,
input rlast_out,
input rvalid_out,
output rready_out
);
/* ========================================================================== */
// Register and Wire Declarations
/* ========================================================================== */
wire wlast_consumed;
wire en_wrshim;
reg wlast_detect;
reg stall_awvalid;
reg store_first_beat;
reg previous_cmd_done;
reg burst_still_active;
reg [2:0] awsize_i;
reg [D_WIDTH-1:0] wdata_i;
reg [1:0] address_offset;
localparam AXI_WRSHIM_APB_SYNC_LEVELS = 2;
/* ========================================================================== */
// Code the Shim
/* ========================================================================== */
// Sync the APB enable signal for the shim
/*
xlnx_sync_bit #(AXI_WRSHIM_APB_SYNC_LEVELS, 0) axi_wrshim_en_sync (
.clk (clk),
.rst_n (rst_n),
.raw_input (apb_en_wrshim),
.sync_out (en_wrshim)
);
*/
wire axi_burst_length_is_zero= (awvalid_in && (awlen_in==0))?1'b1:1'b0;
wire zero_length_transfer=axi_burst_length_is_zero ;
//assign en_wrshim=zero_length_transfer;
assign en_wrshim=1'b1;
//
//*********** AXI signals Flow Throughs *****************
//
assign bid_in = bid_out;
assign bresp_in = bresp_out;
assign bvalid_in = bvalid_out;
assign arready_in = arready_out;
assign rid_in = rid_out;
assign rdata_in = rdata_out;
assign rresp_in = rresp_out;
assign rlast_in = rlast_out;
assign rvalid_in = rvalid_out;
assign awqos_out = awqos_in;
assign awid_out = awid_in;
assign awaddr_out[31:2] = awaddr_in[31:2];
assign awaddr_out[1:0] = (zero_length_transfer==1)?address_offset:awaddr_in[1:0];
assign awlen_out = awlen_in;
assign awsize_out = (zero_length_transfer==1)?awsize_i:awsize_in;
assign awburst_out = awburst_in;
assign awlock_out = awlock_in;
assign awcache_out = awcache_in;
assign awprot_out = awprot_in;
//assign wdata_out = (zero_length_transfer==1)?wdata_i:wdata_in;
assign wdata_out = wdata_in;
assign wid_out = wid_in;
assign wstrb_out = wstrb_in;
assign wlast_out = wlast_in;
assign bready_out = bready_in;
assign arqos_out = arqos_in;
assign arid_out = arid_in;
assign araddr_out = araddr_in;
assign arlen_out = arlen_in;
assign arsize_out = arsize_in;
assign arburst_out = arburst_in;
assign arlock_out = arlock_in;
assign arcache_out = arcache_in;
assign arprot_out = arprot_in;
assign arvalid_out = arvalid_in;
assign rready_out = rready_in;
// *****************************************************************
// ************************* WRITE COMMAND ****************************
// *****************************************************************
// Detect a Wlast. This is required since we cannot release the next AwCmd
// before we have seen a wlast from the previous WrBurst
always @(posedge clk )
if (!rst_n)
wlast_detect <= 1'b1;
else begin
if (wlast_consumed)
wlast_detect <= 1'b1;
else if (en_wrshim && wvalid_out && wready_out)
wlast_detect <= 1'b0;
end
// Detect the First WrData Beat of a wrBurst - only need to determine if
// it is available, NOT that it is consumed
wire first_beat_detect = wlast_detect && wvalid_in;
// Enable the Write Command to be issued
wire awcmd_en = en_wrshim ? ((first_beat_detect && !stall_awvalid) ||
store_first_beat) : 1'b1;
//assign awvalid_out = (zero_length_transfer==1)?awvalid_in && awcmd_en:awvalid_in;
assign awvalid_out = awvalid_in && awcmd_en;
// Also need to flow control the AwReady
//assign awready_in = (zero_length_transfer==1)?awready_out && awcmd_en:awready_out;
assign awready_in = awready_out && awcmd_en;
// Detect the case where AwCmd is released, but the wrData is not consumed
always @(posedge clk )
if (!rst_n)
stall_awvalid <= 1'b0;
else begin
if (en_wrshim && awvalid_out && awready_out && !wready_out)
stall_awvalid <= 1'b1;
else if (wready_out)
stall_awvalid <= 1'b0;
end
// Detect the case where AwValid=1, WValid=1, but AWReady=0 (WReady=1)
always @(posedge clk )
if (!rst_n)
store_first_beat <= 1'b0;
else begin
if (en_wrshim && first_beat_detect && !awready_out)
store_first_beat <= 1'b1;
else if (awready_out)
store_first_beat <= 1'b0;
end
// *****************************************************************
// ************************* WRITE DATA ****************************
// *****************************************************************
assign wlast_consumed = (wvalid_out && wready_out && wlast_in);
// For the Write Data, We need to enable the entire wrBurst
wire start_wr = wlast_detect && awvalid_in && previous_cmd_done;
// Detect if the previous AwCmd was consumed - May be backpressure
always @(posedge clk )
if (!rst_n)
previous_cmd_done <= 1'b1;
else begin
if (awvalid_out && awready_out)
previous_cmd_done <= 1'b1;
else if (awvalid_out && en_wrshim)
previous_cmd_done <= 1'b0;
end
// Store the enable unless it is a single beat wrCmd
always @(posedge clk )
if (!rst_n)
burst_still_active <= 1'b0;
else begin
if (start_wr && !wlast_consumed && en_wrshim)
burst_still_active <= 1'b1;
else if (wlast_consumed)
burst_still_active <= 1'b0;
end
wire write_data_en = en_wrshim ? (burst_still_active || start_wr) : 1'b1;
//assign wvalid_out = (zero_length_transfer==1)? wvalid_in && write_data_en:wvalid_in;
//assign wready_in = (zero_length_transfer==1)? wready_out && write_data_en:wready_out;
assign wvalid_out = wvalid_in && write_data_en;
assign wready_in = wready_out && write_data_en;
always @ *
case (wstrb_in)
4'b0001:begin
awsize_i=0;
wdata_i=wdata_in[7:0];
address_offset<=0;
end
4'b0010:begin
awsize_i=0;
wdata_i=wdata_in[15:8];
address_offset<=1;
end
4'b0100:begin
awsize_i=0;
wdata_i=wdata_in[23:16];
address_offset<=2;
end
4'b1000:begin
awsize_i=0;
wdata_i=wdata_in[31:24];
address_offset<=3;
end
4'b1100:begin
awsize_i=1;
wdata_i=wdata_in[31:16];
address_offset<=2;
end
4'b0011:begin
awsize_i=1;
wdata_i=wdata_in[15:0];
address_offset<=0;
end
default: begin
awsize_i=awsize_in;
wdata_i=wdata_in;
address_offset<=0;
end
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_SYMBOL_V
`define SKY130_FD_SC_HVL__SDFRTP_SYMBOL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_SYMBOL_V
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012, Ameer M. Abdelhadi; [email protected]. All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// FreqPhaseSweeping.v: Dynamic clock freqyency/phase sweep testing //
// using Altera's DE-115 board with Cyclone IV //
// //
// Ameer M.S. Abdelhadi ([email protected]; [email protected]), Sept. 2012 //
////////////////////////////////////////////////////////////////////////////////////
module FreqPhaseSweeping (
// PORT declarations
input CLOCK_50, // 50MHz clock 1
output [8:0] LEDG , // green LED
output [17:0] LEDR , // red LED
input [3:0] KEY , // keys
input [17:0] SW , // switches
output [6:0] HEX0 , // 7-segments 0
output [6:0] HEX1 , // 7-segments 1
output [6:0] HEX2 , // 7-segments 2
output [6:0] HEX3 , // 7-segments 3
output [6:0] HEX4 , // 7-segments 4
output [6:0] HEX5 , // 7-segments 5
output [6:0] HEX6 , // 7-segments 6
output [6:0] HEX7 // 7-segments 7
);
// assign high-Z for unused output ports
assign {LEDG[8],LEDG[5],LEDG[3:0]} = { 4{1'bz}};
// assign SW to LEDR
assign LEDR[17:0] = SW[17:0];
// reset generators
wire rst ; rstgen #(20) rstgen_sys (CLOCK_50, 1'b0, rst ); // system reset generator
wire rstpll; rstgen #(17) rstgen_pll (CLOCK_50, 1'b0, rstpll); // pll reset (longer than system reset)
// instantiate PLL for 500MHz clock generation
wire clk_500 ;
wire [3:0] NC;
pll #( .MUL0(10 ), // clk0 parameters : multiply
.DIV0(1 ), // clk0 parameters : divide
.PHS0("-200" )) // clk0 parameters : phase shift (ps)
pll_inst ( .rst (rstpll ), // asynchronous reset
.clki(CLOCK_50 ), // pll input clock // 50MHz
.clko({NC,clk_500})); // pll output clocks // details above
// instantiate PLL for dynamic frequency/phase sweeping
wire clk_ref,clk_phs;
pll_dyn #(
.INIT_FRQ("2"), // initial frequency - MHz
.INIT_PHS("0") // initial clock phase shift - ps(clk_phs only)
)pll_dyn_inst (
.areset (rstpll ), // asynchronous reset
.clk_50 (CLOCK_50), // 50Mhz clock source
.phasestep (fkey[2] ), // shift phase one step forward
.freq (SW[8:0] ), // new frequeny value to be changed
.write_freq(fkey[3] ), // performe frequeny change
.clk_ref (clk_ref ), // reference output clock
.clk_phs (clk_phs ), // output clock with phase shifting
.busy (LEDG[7] ) // PLL busy, operation not done yet
);
// filtered keys
wire [3:0] fkey;
keyfilter keyfilter_02 (CLOCK_50,KEY[2],fkey[2]);
keyfilter keyfilter_03 (CLOCK_50,KEY[3],fkey[3]);
assign {LEDG[6],LEDG[4]} = {fkey[3],fkey[2]};
//phase meter
wire phs_sgn;
wire [11:0] phs_bcd;
phasemeter
phasemeter_inst ( .clk_500(clk_500), // sampling clock, 500Mhz
.clk_ref(clk_ref), // reference clock
.clk_phs(clk_phs), // phase-shifted clock, same frequency as reference clock
.phs_sgn(phs_sgn), // measured pahse shift / sign
.phs_bcd(phs_bcd)); // measured pahse shift / BCD {ones,tens,hundreds}
hex7seg hex7seg_00 (phs_bcd[3 :0 ],HEX0);
hex7seg hex7seg_01 (phs_bcd[7 :4 ],HEX1);
hex7seg hex7seg_02 (phs_bcd[11:8 ],HEX2);
assign HEX3 = {phs_sgn,6'b111111};
// frequency meter
wire [15:0] frq_bcd;
freqmeter
freqmeter_inst
( .clk_50 (CLOCK_50), // sampling clock, 50Mhz
.clk_ref(clk_phs ), // reference clock / frequency to measure
.frq_bcd(frq_bcd )); // measured frequency / BCD {thousands,hundreds,tens,ones}
hex7seg hex7seg_04 (frq_bcd[3 :0 ],HEX4);
hex7seg hex7seg_05 (frq_bcd[7 :4 ],HEX5);
hex7seg hex7seg_06 (frq_bcd[11:8 ],HEX6);
hex7seg hex7seg_07 (frq_bcd[15:12],HEX7);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22AI_4_V
`define SKY130_FD_SC_MS__O22AI_4_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o22ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o22ai_4 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22AI_4_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of avfb_logic
//
// Generated
// by: wig
// on: Tue Apr 18 07:50:26 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: avfb_logic.v,v 1.1 2006/04/19 07:33:13 wig Exp $
// $Date: 2006/04/19 07:33:13 $
// $Log: avfb_logic.v,v $
// Revision 1.1 2006/04/19 07:33:13 wig
// Updated/added testcase for 20060404c issue. Needs more work!
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.82 2006/04/13 13:31:52 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of avfb_logic
//
// No user `defines in this module
`define top_rs_selclk_out2_par_c 'b0 // __I_VectorConv
module avfb_logic
//
// Generated module i_avfb_logic
//
(
top_rs_selclk_out2_par_go
);
// Generated Module Outputs:
output [4:0] top_rs_selclk_out2_par_go;
// Generated Wires:
wire [4:0] top_rs_selclk_out2_par_go;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [4:0] top_rs_selclk_out2_par; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign top_rs_selclk_out2_par[4:4] = `top_rs_selclk_out2_par_c;
assign top_rs_selclk_out2_par_go = top_rs_selclk_out2_par; // __I_O_BUS_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for i_avfb_top_rs
avfb_top_rs i_avfb_top_rs (
.selclk_out2_par_o(top_rs_selclk_out2_par)
);
// End of Generated Instance Port Map for i_avfb_top_rs
endmodule
//
// End of Generated Module rtl of avfb_logic
//
//
//!End of Module/s
// --------------------------------------------------------------
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_state.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Primary bank state machine. All bank specific timing is generated here.
//
// Conceptually, when a bank machine is assigned a request, conflicts are
// checked. If there is a conflict, then the new request is added
// to the queue for that rank-bank.
//
// Eventually, that request will find itself at the head of the queue for
// its rank-bank. Forthwith, the bank machine will begin arbitration to send an
// activate command to the DRAM. Once arbitration is successful and the
// activate is sent, the row state machine waits the RCD delay. The RAS
// counter is also started when the activate is sent.
//
// Upon completion of the RCD delay, the bank state machine will begin
// arbitration for sending out the column command. Once the column
// command has been sent, the bank state machine waits the RTP latency, and
// if the command is a write, the RAS counter is loaded with the WR latency.
//
// When the RTP counter reaches zero, the pre charge wait state is entered.
// Once the RAS timer reaches zero, arbitration to send a precharge command
// begins.
//
// Upon successful transmission of the precharge command, the bank state
// machine waits the precharge period and then rejoins the idle list.
//
// For an open rank-bank hit, a bank machine passes management of the rank-bank to
// a bank machine that is managing the subsequent request to the same page. A bank
// machine can either be a "passer" or a "passee" in this handoff. There
// are two conditions that have to occur before an open bank can be passed.
// A spatial condition, ie same rank-bank and row address. And a temporal condition,
// ie the passee has completed it work with the bank, but has not issued a precharge.
//
// The spatial condition is signalled by pass_open_bank_ns. The temporal condition
// is when the column command is issued, or when the bank_wait_in_progress
// signal is true. Bank_wait_in_progress is true when the RTP timer is not
// zero, or when the RAS/WR timer is not zero and the state machine is waiting
// to send out a precharge command.
//
// On an open bank pass, the passer transitions from the temporal condition
// noted above and performs the end of request processing and eventually lands
// in the act_wait_r state.
//
// On an open bank pass, the passee lands in the col_wait_r state and waits
// for its chance to send out a column command.
//
// Since there is a single data bus shared by all columns in all ranks, there
// is a single column machine. The column machine is primarily in charge of
// managing the timing on the DQ data bus. It reserves states for data transfer,
// driver turnaround states, and preambles. It also has the ability to add
// additional programmable delay for read to write changeovers. This read to write
// delay is generated in the column machine which inhibits writes via the
// inhbt_wr signal.
//
// There is a rank machine for every rank. The rank machines are responsible
// for enforcing rank specific timing such as FAW, and WTR. RRD is guaranteed
// in the bank machine since it is closely coupled to the operation of the
// bank machine and is timing critical.
//
// Since a bank machine can be working on a request for any rank, all rank machines
// inhibits are input to all bank machines. Based on the rank of the current
// request, each bank machine selects the rank information corresponding
// to the rank of its current request.
//
// Since driver turnaround states and WTR delays are so severe with DDRIII, the
// memory interface has the ability to promote requests that use the same
// driver as the most recent request. There is logic in this block that
// detects when the driver for its request is the same as the driver for
// the most recent request. In such a case, this block will send out special
// "same" request early enough to eliminate dead states when there is no
// driver changeover.
`timescale 1ps/1ps
`define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1)
module mig_7series_v2_0_bank_state #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter ECC = "OFF",
parameter ID = 0,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nOP_WAIT = 0,
parameter nRAS_CLKS = 10,
parameter nRP = 10,
parameter nRTP = 4,
parameter nRCD = 5,
parameter nWTP_CLKS = 5,
parameter ORDERING = "NORM",
parameter RANKS = 4,
parameter RANK_WIDTH = 4,
parameter RAS_TIMER_WIDTH = 5,
parameter STARVE_LIMIT = 2
)
(/*AUTOARG*/
// Outputs
start_rcd, act_wait_r, rd_half_rmw, ras_timer_ns, end_rtp,
bank_wait_in_progress, start_pre_wait, op_exit_req, pre_wait_r,
allow_auto_pre, precharge_bm_end, demand_act_priority, rts_row,
act_this_rank_r, demand_priority, col_rdy_wr, rts_col, wr_this_rank_r,
rd_this_rank_r, rts_pre, rtc,
// Inputs
clk, rst, bm_end, pass_open_bank_r, sending_row, sending_pre, rcv_open_bank,
sending_col, rd_wr_r, req_wr_r, rd_data_addr, req_data_buf_addr_r,
phy_rddata_valid, rd_rmw, ras_timer_ns_in, rb_hit_busies_r, idle_r,
passing_open_bank, low_idle_cnt_r, op_exit_grant, tail_r,
auto_pre_r, pass_open_bank_ns, req_rank_r, req_rank_r_in,
start_rcd_in, inhbt_act_faw_r, wait_for_maint_r, head_r, sent_row,
demand_act_priority_in, order_q_zero, sent_col, q_has_rd,
q_has_priority, req_priority_r, idle_ns, demand_priority_in, inhbt_rd,
inhbt_wr, dq_busy_data, rnk_config_strobe, rnk_config_valid_r, rnk_config,
rnk_config_kill_rts_col, phy_mc_cmd_full, phy_mc_ctl_full, phy_mc_data_full
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
input clk;
input rst;
// Activate wait state machine.
input bm_end;
reg bm_end_r1;
always @(posedge clk) bm_end_r1 <= #TCQ bm_end;
reg col_wait_r;
input pass_open_bank_r;
input sending_row;
reg act_wait_r_lcl;
input rcv_open_bank;
wire start_rcd_lcl = act_wait_r_lcl && sending_row;
output wire start_rcd;
assign start_rcd = start_rcd_lcl;
wire act_wait_ns = rst ||
((act_wait_r_lcl && ~start_rcd_lcl && ~rcv_open_bank) ||
bm_end_r1 || (pass_open_bank_r && bm_end));
always @(posedge clk) act_wait_r_lcl <= #TCQ act_wait_ns;
output wire act_wait_r;
assign act_wait_r = act_wait_r_lcl;
// RCD timer
//
// When CWL is even, CAS commands are issued on slot 0 and RAS commands are
// issued on slot 1. This implies that the RCD can never expire in the same
// cycle as the RAS (otherwise the CAS for a given transaction would precede
// the RAS). Similarly, this can also cause premature expiration for longer
// RCD. An offset must be added to RCD before translating it to the FPGA clock
// domain. In this mode, CAS are on the first DRAM clock cycle corresponding to
// a given FPGA cycle. In 2:1 mode add 2 to generate this offset aligned to
// the FPGA cycle. Likewise, add 4 to generate an aligned offset in 4:1 mode.
//
// When CWL is odd, RAS commands are issued on slot 0 and CAS commands are
// issued on slot 1. There is a natural 1 cycle seperation between RAS and CAS
// in the DRAM clock domain so the RCD can expire in the same FPGA cycle as the
// RAS command. In 2:1 mode, there are only 2 slots so direct translation
// correctly places the CAS with respect to the corresponding RAS. In 4:1 mode,
// there are two slots after CAS, so 2 is added to shift the timer into the
// next FPGA cycle for cases that can't expire in the current cycle.
//
// In 2T mode, the offset from ROW to COL commands is fixed at 2. In 2:1 mode,
// It is sufficient to translate to the half-rate domain and add the remainder.
// In 4:1 mode, we must translate to the quarter-rate domain and add an
// additional fabric cycle only if the remainder exceeds the fixed offset of 2
localparam nRCD_CLKS =
nCK_PER_CLK == 1 ?
nRCD :
nCK_PER_CLK == 2 ?
ADDR_CMD_MODE == "2T" ?
(nRCD/2) + (nRCD%2) :
CWL % 2 ?
(nRCD/2) :
(nRCD+2) / 2 :
// (nCK_PER_CLK == 4)
ADDR_CMD_MODE == "2T" ?
(nRCD/4) + (nRCD%4 > 2 ? 1 : 0) :
CWL % 2 ?
(nRCD-2 ? (nRCD-2) / 4 + 1 : 1) :
nRCD/4 + 1;
localparam nRCD_CLKS_M2 = (nRCD_CLKS-2 <0) ? 0 : nRCD_CLKS-2;
localparam RCD_TIMER_WIDTH = clogb2(nRCD_CLKS_M2+1);
localparam ZERO = 0;
localparam ONE = 1;
reg [RCD_TIMER_WIDTH-1:0] rcd_timer_r = {RCD_TIMER_WIDTH{1'b0}};
reg end_rcd;
reg rcd_active_r = 1'b0;
generate
if (nRCD_CLKS <= 2) begin : rcd_timer_leq_2
always @(/*AS*/start_rcd_lcl) end_rcd = start_rcd_lcl;
end
else if (nRCD_CLKS > 2) begin : rcd_timer_gt_2
reg [RCD_TIMER_WIDTH-1:0] rcd_timer_ns;
always @(/*AS*/rcd_timer_r or rst or start_rcd_lcl) begin
if (rst) rcd_timer_ns = ZERO[RCD_TIMER_WIDTH-1:0];
else begin
rcd_timer_ns = rcd_timer_r;
if (start_rcd_lcl) rcd_timer_ns = nRCD_CLKS_M2[RCD_TIMER_WIDTH-1:0];
else if (|rcd_timer_r) rcd_timer_ns =
rcd_timer_r - ONE[RCD_TIMER_WIDTH-1:0];
end
end
always @(posedge clk) rcd_timer_r <= #TCQ rcd_timer_ns;
wire end_rcd_ns = (rcd_timer_ns == ONE[RCD_TIMER_WIDTH-1:0]);
always @(posedge clk) end_rcd = end_rcd_ns;
wire rcd_active_ns = |rcd_timer_ns;
always @(posedge clk) rcd_active_r <= #TCQ rcd_active_ns;
end
endgenerate
// Figure out if the read that's completing is for an RMW for
// this bank machine. Delay by a state if CWL != 8 since the
// data is not ready in the RMW buffer for the early write
// data fetch that happens with ECC and CWL != 8.
// Create a state bit indicating we're waiting for the read
// half of the rmw to complete.
input sending_col;
input rd_wr_r;
input req_wr_r;
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
input phy_rddata_valid;
input rd_rmw;
reg rmw_rd_done = 1'b0;
reg rd_half_rmw_lcl = 1'b0;
output wire rd_half_rmw;
assign rd_half_rmw = rd_half_rmw_lcl;
reg rmw_wait_r = 1'b0;
generate
if (ECC != "OFF") begin : rmw_on
// Delay phy_rddata_valid and rd_rmw by one cycle to align them
// to req_data_buf_addr_r so that rmw_wait_r clears properly
reg phy_rddata_valid_r;
reg rd_rmw_r;
always @(posedge clk) begin
phy_rddata_valid_r <= #TCQ phy_rddata_valid;
rd_rmw_r <= #TCQ rd_rmw;
end
wire my_rmw_rd_ns = phy_rddata_valid_r && rd_rmw_r &&
(rd_data_addr == req_data_buf_addr_r);
if (CWL == 8) always @(my_rmw_rd_ns) rmw_rd_done = my_rmw_rd_ns;
else always @(posedge clk) rmw_rd_done = #TCQ my_rmw_rd_ns;
always @(/*AS*/rd_wr_r or req_wr_r) rd_half_rmw_lcl = req_wr_r && rd_wr_r;
wire rmw_wait_ns = ~rst &&
((rmw_wait_r && ~rmw_rd_done) || (rd_half_rmw_lcl && sending_col));
always @(posedge clk) rmw_wait_r <= #TCQ rmw_wait_ns;
end
endgenerate
// column wait state machine.
wire col_wait_ns = ~rst && ((col_wait_r && ~sending_col) || end_rcd
|| rcv_open_bank || (rmw_rd_done && rmw_wait_r));
always @(posedge clk) col_wait_r <= #TCQ col_wait_ns;
// Set up various RAS timer parameters, wires, etc.
localparam TWO = 2;
output reg [RAS_TIMER_WIDTH-1:0] ras_timer_ns;
reg [RAS_TIMER_WIDTH-1:0] ras_timer_r;
input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;
input [(nBANK_MACHS*2)-1:0] rb_hit_busies_r;
// On a bank pass, select the RAS timer from the passing bank machine.
reg [RAS_TIMER_WIDTH-1:0] passed_ras_timer;
integer i;
always @(/*AS*/ras_timer_ns_in or rb_hit_busies_r) begin
passed_ras_timer = {RAS_TIMER_WIDTH{1'b0}};
for (i=ID+1; i<(ID+nBANK_MACHS); i=i+1)
if (rb_hit_busies_r[i])
passed_ras_timer = ras_timer_ns_in[i*RAS_TIMER_WIDTH+:RAS_TIMER_WIDTH];
end
// RAS and (reused for) WTP timer. When an open bank is passed, this
// timer is passed to the new owner. The existing RAS prevents
// an activate from occuring too early.
wire start_wtp_timer = sending_col && ~rd_wr_r;
input idle_r;
always @(/*AS*/bm_end_r1 or ras_timer_r or rst or start_rcd_lcl
or start_wtp_timer) begin
if (bm_end_r1 || rst) ras_timer_ns = ZERO[RAS_TIMER_WIDTH-1:0];
else begin
ras_timer_ns = ras_timer_r;
if (start_rcd_lcl) ras_timer_ns =
nRAS_CLKS[RAS_TIMER_WIDTH-1:0] - TWO[RAS_TIMER_WIDTH-1:0];
if (start_wtp_timer) ras_timer_ns =
// As the timer is being reused, it is essential to compare
// before new value is loaded.
(ras_timer_r <= (nWTP_CLKS-2)) ? nWTP_CLKS[RAS_TIMER_WIDTH-1:0] - TWO[RAS_TIMER_WIDTH-1:0]
: ras_timer_r - ONE[RAS_TIMER_WIDTH-1:0];
if (|ras_timer_r && ~start_wtp_timer) ras_timer_ns =
ras_timer_r - ONE[RAS_TIMER_WIDTH-1:0];
end
end // always @ (...
wire [RAS_TIMER_WIDTH-1:0] ras_timer_passed_ns = rcv_open_bank
? passed_ras_timer
: ras_timer_ns;
always @(posedge clk) ras_timer_r <= #TCQ ras_timer_passed_ns;
wire ras_timer_zero_ns = (ras_timer_ns == ZERO[RAS_TIMER_WIDTH-1:0]);
reg ras_timer_zero_r;
always @(posedge clk) ras_timer_zero_r <= #TCQ ras_timer_zero_ns;
// RTP timer. Unless 2T mode, add one for 2:1 mode. This accounts for loss of
// one DRAM CK due to column command to row command fixed offset. In 2T mode,
// Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T
// mode, in which case we add 1 if the remainder exceeds the fixed offset.
localparam nRTP_CLKS = (nCK_PER_CLK == 1)
? nRTP :
(nCK_PER_CLK == 2)
? (nRTP/2) + ((ADDR_CMD_MODE == "2T") ? nRTP%2 : 1) :
(nRTP/4) + ((ADDR_CMD_MODE == "2T") ? (nRTP%4 > 2 ? 2 : 1) : 2);
localparam nRTP_CLKS_M1 = ((nRTP_CLKS-1) <= 0) ? 0 : nRTP_CLKS-1;
localparam RTP_TIMER_WIDTH = clogb2(nRTP_CLKS_M1 + 1);
reg [RTP_TIMER_WIDTH-1:0] rtp_timer_ns;
reg [RTP_TIMER_WIDTH-1:0] rtp_timer_r;
wire sending_col_not_rmw_rd = sending_col && ~rd_half_rmw_lcl;
always @(/*AS*/pass_open_bank_r or rst or rtp_timer_r
or sending_col_not_rmw_rd) begin
rtp_timer_ns = rtp_timer_r;
if (rst || pass_open_bank_r)
rtp_timer_ns = ZERO[RTP_TIMER_WIDTH-1:0];
else begin
if (sending_col_not_rmw_rd)
rtp_timer_ns = nRTP_CLKS_M1[RTP_TIMER_WIDTH-1:0];
if (|rtp_timer_r) rtp_timer_ns = rtp_timer_r - ONE[RTP_TIMER_WIDTH-1:0];
end
end
always @(posedge clk) rtp_timer_r <= #TCQ rtp_timer_ns;
wire end_rtp_lcl = ~pass_open_bank_r &&
((rtp_timer_r == ONE[RTP_TIMER_WIDTH-1:0]) ||
((nRTP_CLKS_M1 == 0) && sending_col_not_rmw_rd));
output wire end_rtp;
assign end_rtp = end_rtp_lcl;
// Optionally implement open page mode timer.
localparam OP_WIDTH = clogb2(nOP_WAIT + 1);
output wire bank_wait_in_progress;
output wire start_pre_wait;
input passing_open_bank;
input low_idle_cnt_r;
output wire op_exit_req;
input op_exit_grant;
input tail_r;
output reg pre_wait_r;
generate
if (nOP_WAIT == 0) begin : op_mode_disabled
assign bank_wait_in_progress = sending_col_not_rmw_rd || |rtp_timer_r ||
(pre_wait_r && ~ras_timer_zero_r);
assign start_pre_wait = end_rtp_lcl;
assign op_exit_req = 1'b0;
end
else begin : op_mode_enabled
reg op_wait_r;
assign bank_wait_in_progress = sending_col || |rtp_timer_r ||
(pre_wait_r && ~ras_timer_zero_r) ||
op_wait_r;
wire op_active = ~rst && ~passing_open_bank && ((end_rtp_lcl && tail_r)
|| op_wait_r);
wire op_wait_ns = ~op_exit_grant && op_active;
always @(posedge clk) op_wait_r <= #TCQ op_wait_ns;
assign start_pre_wait = op_exit_grant ||
(end_rtp_lcl && ~tail_r && ~passing_open_bank);
if (nOP_WAIT == -1)
assign op_exit_req = (low_idle_cnt_r && op_active);
else begin : op_cnt
reg [OP_WIDTH-1:0] op_cnt_r;
wire [OP_WIDTH-1:0] op_cnt_ns =
(passing_open_bank || op_exit_grant || rst)
? ZERO[OP_WIDTH-1:0]
: end_rtp_lcl
? nOP_WAIT[OP_WIDTH-1:0]
: |op_cnt_r
? op_cnt_r - ONE[OP_WIDTH-1:0]
: op_cnt_r;
always @(posedge clk) op_cnt_r <= #TCQ op_cnt_ns;
assign op_exit_req = (low_idle_cnt_r && op_active) ||
(op_wait_r && ~|op_cnt_r);
end
end
endgenerate
output allow_auto_pre;
wire allow_auto_pre = act_wait_r_lcl || rcd_active_r ||
(col_wait_r && ~sending_col);
// precharge wait state machine.
input auto_pre_r;
wire start_pre;
input pass_open_bank_ns;
wire pre_wait_ns = ~rst && (~pass_open_bank_ns &&
(start_pre_wait || (pre_wait_r && ~start_pre)));
always @(posedge clk) pre_wait_r <= #TCQ pre_wait_ns;
wire pre_request = pre_wait_r && ras_timer_zero_r && ~auto_pre_r;
// precharge timer.
localparam nRP_CLKS = (nCK_PER_CLK == 1) ? nRP :
(nCK_PER_CLK == 2) ? ((nRP/2) + (nRP%2)) :
/*(nCK_PER_CLK == 4)*/ ((nRP/4) + ((nRP%4) ? 1 : 0));
// Subtract two because there are a minimum of two fabric states from
// end of RP timer until earliest possible arb to send act.
localparam nRP_CLKS_M2 = (nRP_CLKS-2 < 0) ? 0 : nRP_CLKS-2;
localparam RP_TIMER_WIDTH = clogb2(nRP_CLKS_M2 + 1);
input sending_pre;
output rts_pre;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin
assign start_pre = pre_wait_r && ras_timer_zero_r &&
(sending_pre || auto_pre_r);
assign rts_pre = ~sending_pre && pre_request;
end
else begin
assign start_pre = pre_wait_r && ras_timer_zero_r &&
(sending_row || auto_pre_r);
assign rts_pre = 1'b0;
end
endgenerate
reg [RP_TIMER_WIDTH-1:0] rp_timer_r = ZERO[RP_TIMER_WIDTH-1:0];
generate
if (nRP_CLKS_M2 > ZERO) begin : rp_timer
reg [RP_TIMER_WIDTH-1:0] rp_timer_ns;
always @(/*AS*/rp_timer_r or rst or start_pre)
if (rst) rp_timer_ns = ZERO[RP_TIMER_WIDTH-1:0];
else begin
rp_timer_ns = rp_timer_r;
if (start_pre) rp_timer_ns = nRP_CLKS_M2[RP_TIMER_WIDTH-1:0];
else if (|rp_timer_r) rp_timer_ns =
rp_timer_r - ONE[RP_TIMER_WIDTH-1:0];
end
always @(posedge clk) rp_timer_r <= #TCQ rp_timer_ns;
end // block: rp_timer
endgenerate
output wire precharge_bm_end;
assign precharge_bm_end = (rp_timer_r == ONE[RP_TIMER_WIDTH-1:0]) ||
(start_pre && (nRP_CLKS_M2 == ZERO));
// Compute RRD related activate inhibit.
// Compare this bank machine's rank with others, then
// select result based on grant. An alternative is to
// select the just issued rank with the grant and simply
// compare against this bank machine's rank. However, this
// serializes the selection of the rank and the compare processes.
// As implemented below, the compare occurs first, then the
// selection based on grant. This is faster.
input [RANK_WIDTH-1:0] req_rank_r;
input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;
reg inhbt_act_rrd;
input [(nBANK_MACHS*2)-1:0] start_rcd_in;
generate
integer j;
if (RANKS == 1)
always @(/*AS*/req_rank_r or req_rank_r_in or start_rcd_in) begin
inhbt_act_rrd = 1'b0;
for (j=(ID+1); j<(ID+nBANK_MACHS); j=j+1)
inhbt_act_rrd = inhbt_act_rrd || start_rcd_in[j];
end
else begin
always @(/*AS*/req_rank_r or req_rank_r_in or start_rcd_in) begin
inhbt_act_rrd = 1'b0;
for (j=(ID+1); j<(ID+nBANK_MACHS); j=j+1)
inhbt_act_rrd = inhbt_act_rrd ||
(start_rcd_in[j] &&
(req_rank_r_in[(j*RANK_WIDTH)+:RANK_WIDTH] == req_rank_r));
end
end
endgenerate
// Extract the activate command inhibit for the rank associated
// with this request. FAW and RRD are computed separately so that
// gate level timing can be carefully managed.
input [RANKS-1:0] inhbt_act_faw_r;
wire my_inhbt_act_faw = inhbt_act_faw_r[req_rank_r];
input wait_for_maint_r;
input head_r;
wire act_req = ~idle_r && head_r && act_wait_r && ras_timer_zero_r &&
~wait_for_maint_r;
// Implement simple starvation avoidance for act requests. Precharge
// requests don't need this because they are never gated off by
// timing events such as inhbt_act_rrd. Priority request timeout
// is fixed at a single trip around the round robin arbiter.
input sent_row;
wire rts_act_denied = act_req && sent_row && ~sending_row;
reg [BM_CNT_WIDTH-1:0] act_starve_limit_cntr_ns;
reg [BM_CNT_WIDTH-1:0] act_starve_limit_cntr_r;
generate
if (BM_CNT_WIDTH > 1) // Number of Bank Machs > 2
begin :BM_MORE_THAN_2
always @(/*AS*/act_req or act_starve_limit_cntr_r or rts_act_denied)
begin
act_starve_limit_cntr_ns = act_starve_limit_cntr_r;
if (~act_req)
act_starve_limit_cntr_ns = {BM_CNT_WIDTH{1'b0}};
else
if (rts_act_denied && &act_starve_limit_cntr_r)
act_starve_limit_cntr_ns = act_starve_limit_cntr_r +
{{BM_CNT_WIDTH-1{1'b0}}, 1'b1};
end
end
else // Number of Bank Machs == 2
begin :BM_EQUAL_2
always @(/*AS*/act_req or act_starve_limit_cntr_r or rts_act_denied)
begin
act_starve_limit_cntr_ns = act_starve_limit_cntr_r;
if (~act_req)
act_starve_limit_cntr_ns = {BM_CNT_WIDTH{1'b0}};
else
if (rts_act_denied && &act_starve_limit_cntr_r)
act_starve_limit_cntr_ns = act_starve_limit_cntr_r +
{1'b1};
end
end
endgenerate
always @(posedge clk) act_starve_limit_cntr_r <=
#TCQ act_starve_limit_cntr_ns;
reg demand_act_priority_r;
wire demand_act_priority_ns = act_req &&
(demand_act_priority_r || (rts_act_denied && &act_starve_limit_cntr_r));
always @(posedge clk) demand_act_priority_r <= #TCQ demand_act_priority_ns;
`ifdef MC_SVA
cover_demand_act_priority:
cover property (@(posedge clk) (~rst && demand_act_priority_r));
`endif
output wire demand_act_priority;
assign demand_act_priority = demand_act_priority_r && ~sending_row;
// compute act_demanded from other demand_act_priorities
input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;
reg act_demanded = 1'b0;
generate
if (nBANK_MACHS > 1) begin : compute_act_demanded
always @(demand_act_priority_in[`BM_SHARED_BV])
act_demanded = |demand_act_priority_in[`BM_SHARED_BV];
end
endgenerate
wire row_demand_ok = demand_act_priority_r || ~act_demanded;
// Generate the Request To Send row arbitation signal.
output wire rts_row;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T"))
assign rts_row = ~sending_row && row_demand_ok &&
(act_req && ~my_inhbt_act_faw && ~inhbt_act_rrd);
else
assign rts_row = ~sending_row && row_demand_ok &&
((act_req && ~my_inhbt_act_faw && ~inhbt_act_rrd) ||
pre_request);
endgenerate
`ifdef MC_SVA
four_activate_window_wait:
cover property (@(posedge clk)
(~rst && ~sending_row && act_req && my_inhbt_act_faw));
ras_ras_delay_wait:
cover property (@(posedge clk)
(~rst && ~sending_row && act_req && inhbt_act_rrd));
`endif
// Provide rank machines early knowledge that this bank machine is
// going to send an activate to the rank. In this way, the rank
// machines just need to use the sending_row wire to figure out if
// they need to keep track of the activate.
output reg [RANKS-1:0] act_this_rank_r;
reg [RANKS-1:0] act_this_rank_ns;
always @(/*AS*/act_wait_r or req_rank_r) begin
act_this_rank_ns = {RANKS{1'b0}};
for (i = 0; i < RANKS; i = i + 1)
act_this_rank_ns[i] = act_wait_r && (i[RANK_WIDTH-1:0] == req_rank_r);
end
always @(posedge clk) act_this_rank_r <= #TCQ act_this_rank_ns;
// Generate request to send column command signal.
input order_q_zero;
wire req_bank_rdy_ns = order_q_zero && col_wait_r;
reg req_bank_rdy_r;
always @(posedge clk) req_bank_rdy_r <= #TCQ req_bank_rdy_ns;
// Determine is we have been denied a column command request.
input sent_col;
wire rts_col_denied = req_bank_rdy_r && sent_col && ~sending_col;
// Implement a starvation limit counter. Count the number of times a
// request to send a column command has been denied.
localparam STARVE_LIMIT_CNT = STARVE_LIMIT * nBANK_MACHS;
localparam STARVE_LIMIT_WIDTH = clogb2(STARVE_LIMIT_CNT);
reg [STARVE_LIMIT_WIDTH-1:0] starve_limit_cntr_r;
reg [STARVE_LIMIT_WIDTH-1:0] starve_limit_cntr_ns;
always @(/*AS*/col_wait_r or rts_col_denied or starve_limit_cntr_r)
if (~col_wait_r)
starve_limit_cntr_ns = {STARVE_LIMIT_WIDTH{1'b0}};
else
if (rts_col_denied && (starve_limit_cntr_r != STARVE_LIMIT_CNT-1))
starve_limit_cntr_ns = starve_limit_cntr_r +
{{STARVE_LIMIT_WIDTH-1{1'b0}}, 1'b1};
else starve_limit_cntr_ns = starve_limit_cntr_r;
always @(posedge clk) starve_limit_cntr_r <= #TCQ starve_limit_cntr_ns;
input q_has_rd;
input q_has_priority;
// Decide if this bank machine should demand priority. Priority is demanded
// when starvation limit counter is reached, or a bit in the request.
wire starved = ((starve_limit_cntr_r == (STARVE_LIMIT_CNT-1)) &&
rts_col_denied);
input req_priority_r;
input idle_ns;
reg demand_priority_r;
wire demand_priority_ns = ~idle_ns && col_wait_ns &&
(demand_priority_r ||
(order_q_zero &&
(req_priority_r || q_has_priority)) ||
(starved && (q_has_rd || ~req_wr_r)));
always @(posedge clk) demand_priority_r <= #TCQ demand_priority_ns;
`ifdef MC_SVA
wire rdy_for_priority = ~rst && ~demand_priority_r && ~idle_ns &&
col_wait_ns;
req_triggers_demand_priority:
cover property (@(posedge clk)
(rdy_for_priority && req_priority_r && ~q_has_priority && ~starved));
q_priority_triggers_demand_priority:
cover property (@(posedge clk)
(rdy_for_priority && ~req_priority_r && q_has_priority && ~starved));
wire not_req_or_q_rdy_for_priority =
rdy_for_priority && ~req_priority_r && ~q_has_priority;
starved_req_triggers_demand_priority:
cover property (@(posedge clk)
(not_req_or_q_rdy_for_priority && starved && ~q_has_rd && ~req_wr_r));
starved_q_triggers_demand_priority:
cover property (@(posedge clk)
(not_req_or_q_rdy_for_priority && starved && q_has_rd && req_wr_r));
`endif
// compute demanded from other demand_priorities
input [(nBANK_MACHS*2)-1:0] demand_priority_in;
reg demanded = 1'b0;
generate
if (nBANK_MACHS > 1) begin : compute_demanded
always @(demand_priority_in[`BM_SHARED_BV]) demanded =
|demand_priority_in[`BM_SHARED_BV];
end
endgenerate
// In order to make sure that there is no starvation amongst a possibly
// unlimited stream of priority requests, add a second stage to the demand
// priority signal. If there are no other requests demanding priority, then
// go ahead and assert demand_priority. If any other requests are asserting
// demand_priority, hold off asserting demand_priority until these clear, then
// assert demand priority. Its possible to get multiple requests asserting
// demand priority simultaneously, but that's OK. Those requests will be
// serviced, demanded will fall, and another group of requests will be
// allowed to assert demand_priority.
reg demanded_prior_r;
wire demanded_prior_ns = demanded &&
(demanded_prior_r || ~demand_priority_r);
always @(posedge clk) demanded_prior_r <= #TCQ demanded_prior_ns;
output wire demand_priority;
assign demand_priority = demand_priority_r && ~demanded_prior_r &&
~sending_col;
`ifdef MC_SVA
demand_priority_gated:
cover property (@(posedge clk) (demand_priority_r && ~demand_priority));
generate
if (nBANK_MACHS >1) multiple_demand_priority:
cover property (@(posedge clk)
($countones(demand_priority_in[`BM_SHARED_BV]) > 1));
endgenerate
`endif
wire demand_ok = demand_priority_r || ~demanded;
// Figure out if the request in this bank machine matches the current rank
// configuration.
input rnk_config_strobe;
input rnk_config_kill_rts_col;
input rnk_config_valid_r;
input [RANK_WIDTH-1:0] rnk_config;
output wire rtc;
wire rnk_config_match = rnk_config_valid_r && (rnk_config == req_rank_r);
assign rtc = ~rnk_config_match && ~rnk_config_kill_rts_col && order_q_zero && col_wait_r && demand_ok;
// Using rank state provided by the rank machines, figure out if
// a read requests should wait for WTR or RTW.
input [RANKS-1:0] inhbt_rd;
wire my_inhbt_rd = inhbt_rd[req_rank_r];
input [RANKS-1:0] inhbt_wr;
wire my_inhbt_wr = inhbt_wr[req_rank_r];
wire allow_rw = ~rd_wr_r ? ~my_inhbt_wr : ~my_inhbt_rd;
// DQ bus timing constraints.
input dq_busy_data;
// Column command is ready to arbitrate, except for databus restrictions.
wire col_rdy = (col_wait_r || ((nRCD_CLKS <= 1) && end_rcd) ||
(rcv_open_bank && nCK_PER_CLK == 2 && DRAM_TYPE=="DDR2" && BURST_MODE == "4") ||
(rcv_open_bank && nCK_PER_CLK == 4 && BURST_MODE == "8")) &&
order_q_zero;
// Column command is ready to arbitrate for sending a write. Used
// to generate early wr_data_addr for ECC mode.
output wire col_rdy_wr;
assign col_rdy_wr = col_rdy && ~rd_wr_r;
// Figure out if we're ready to send a column command based on all timing
// constraints.
// if timing is an issue.
wire col_cmd_rts = col_rdy && ~dq_busy_data && allow_rw && rnk_config_match;
`ifdef MC_SVA
col_wait_for_order_q: cover property
(@(posedge clk)
(~rst && col_wait_r && ~order_q_zero && ~dq_busy_data &&
allow_rw));
col_wait_for_dq_busy: cover property
(@(posedge clk)
(~rst && col_wait_r && order_q_zero && dq_busy_data &&
allow_rw));
col_wait_for_allow_rw: cover property
(@(posedge clk)
(~rst && col_wait_r && order_q_zero && ~dq_busy_data &&
~allow_rw));
`endif
// Implement flow control for the command and control FIFOs and for the data
// FIFO during writes
input phy_mc_ctl_full;
input phy_mc_cmd_full;
input phy_mc_data_full;
// Register ctl_full and cmd_full
reg phy_mc_ctl_full_r = 1'b0;
reg phy_mc_cmd_full_r = 1'b0;
always @(posedge clk)
if(rst) begin
phy_mc_ctl_full_r <= #TCQ 1'b0;
phy_mc_cmd_full_r <= #TCQ 1'b0;
end else begin
phy_mc_ctl_full_r <= #TCQ phy_mc_ctl_full;
phy_mc_cmd_full_r <= #TCQ phy_mc_cmd_full;
end
// register output data pre-fifo almost full condition and fold in WR status
reg ofs_rdy_r = 1'b0;
always @(posedge clk)
if(rst)
ofs_rdy_r <= #TCQ 1'b0;
else
ofs_rdy_r <= #TCQ ~phy_mc_cmd_full_r && ~phy_mc_ctl_full_r && ~(phy_mc_data_full && ~rd_wr_r);
// Disable priority feature for one state after a config to insure
// forward progress on the just installed io config.
reg override_demand_r;
wire override_demand_ns = rnk_config_strobe || rnk_config_kill_rts_col;
always @(posedge clk) override_demand_r <= override_demand_ns;
output wire rts_col;
assign rts_col = ~sending_col && (demand_ok || override_demand_r) &&
col_cmd_rts && ofs_rdy_r;
// As in act_this_rank, wr/rd_this_rank informs rank machines
// that this bank machine is doing a write/rd. Removes logic
// after the grant.
reg [RANKS-1:0] wr_this_rank_ns;
reg [RANKS-1:0] rd_this_rank_ns;
always @(/*AS*/rd_wr_r or req_rank_r) begin
wr_this_rank_ns = {RANKS{1'b0}};
rd_this_rank_ns = {RANKS{1'b0}};
for (i=0; i<RANKS; i=i+1) begin
wr_this_rank_ns[i] = ~rd_wr_r && (i[RANK_WIDTH-1:0] == req_rank_r);
rd_this_rank_ns[i] = rd_wr_r && (i[RANK_WIDTH-1:0] == req_rank_r);
end
end
output reg [RANKS-1:0] wr_this_rank_r;
always @(posedge clk) wr_this_rank_r <= #TCQ wr_this_rank_ns;
output reg [RANKS-1:0] rd_this_rank_r;
always @(posedge clk) rd_this_rank_r <= #TCQ rd_this_rank_ns;
endmodule // bank_state
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 13:00:13 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_0_sim_netlist.v
// Design : fifo_generator_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "fifo_generator_0,fifo_generator_v13_1_2,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
rd_data_count,
wr_data_count,
prog_full,
prog_empty);
input rst;
(* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) input wr_clk;
(* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) input rd_clk;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [63:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [63:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
output [8:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire prog_empty;
wire prog_full;
wire rd_clk;
wire [8:0]rd_data_count;
wire rd_en;
wire rst;
wire wr_clk;
wire [9:0]wr_data_count;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [9:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "64" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "1" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "1" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "1kx36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "313" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "314" *)
(* C_PROG_EMPTY_TYPE = "1" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "66" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "65" *)
(* C_PROG_FULL_TYPE = "1" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "9" *)
(* C_RD_DEPTH = "1024" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(NLW_U0_data_count_UNCONNECTED[9:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(prog_empty),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(prog_full),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [0:0]E;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r
(.E(E),
.din(din[35:0]),
.dout(dout[35:0]),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.E(E),
.din(din[63:36]),
.dout(dout[63:36]),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [35:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [35:0]din;
wire [0:0]E;
wire [35:0]din;
wire [35:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.E(E),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [27:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [27:0]din;
wire [0:0]E;
wire [27:0]din;
wire [27:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.E(E),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [35:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [35:0]din;
wire [0:0]E;
wire [35:0]din;
wire [35:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\gic0.gc0.count_d2_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({din[34:27],din[25:18],din[16:9],din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({din[35],din[26],din[17],din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({dout[34:27],dout[25:18],dout[16:9],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({dout[35],dout[26],dout[17],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(E),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({E,E,E,E}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [27:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [27:0]din;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire [27:0]din;
wire [27:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\gic0.gc0.count_d2_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,din[27:21],1'b0,din[20:14],1'b0,din[13:7],1'b0,din[6:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ,dout[27:21],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ,dout[20:14],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ,dout[13:7],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,dout[6:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(E),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({E,E,E,E}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [0:0]E;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr
(.E(E),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [0:0]E;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen
(.E(E),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [0:0]E;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.E(E),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs
(v1_reg,
v1_reg_0,
D,
\rd_dc_i_reg[9] ,
v1_reg_1,
RD_PNTR_WR,
v1_reg_2,
Q,
\gc0.count_reg[9] ,
p_0_out,
\gic0.gc0.count_d1_reg[7] ,
\gic0.gc0.count_reg[9] ,
\gic0.gc0.count_d2_reg[9] ,
wr_clk,
AR,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [4:0]v1_reg;
output [4:0]v1_reg_0;
output [8:0]D;
output [8:0]\rd_dc_i_reg[9] ;
output [3:0]v1_reg_1;
output [9:0]RD_PNTR_WR;
output [4:0]v1_reg_2;
input [9:0]Q;
input [9:0]\gc0.count_reg[9] ;
input p_0_out;
input [7:0]\gic0.gc0.count_d1_reg[7] ;
input [9:0]\gic0.gc0.count_reg[9] ;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input wr_clk;
input [0:0]AR;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]AR;
wire [8:0]D;
wire [9:0]Q;
wire [9:0]RD_PNTR_WR;
wire [8:0]bin2gray;
wire [9:0]\gc0.count_reg[9] ;
wire \gdiff.diff_pntr_pad[10]_i_2_n_0 ;
wire \gdiff.diff_pntr_pad[10]_i_3_n_0 ;
wire \gdiff.diff_pntr_pad[4]_i_3_n_0 ;
wire \gdiff.diff_pntr_pad[4]_i_4_n_0 ;
wire \gdiff.diff_pntr_pad[4]_i_5_n_0 ;
wire \gdiff.diff_pntr_pad[4]_i_6_n_0 ;
wire \gdiff.diff_pntr_pad[8]_i_2_n_0 ;
wire \gdiff.diff_pntr_pad[8]_i_3_n_0 ;
wire \gdiff.diff_pntr_pad[8]_i_4_n_0 ;
wire \gdiff.diff_pntr_pad[8]_i_5_n_0 ;
wire \gdiff.diff_pntr_pad_reg[10]_i_1_n_3 ;
wire \gdiff.diff_pntr_pad_reg[4]_i_1_n_0 ;
wire \gdiff.diff_pntr_pad_reg[4]_i_1_n_1 ;
wire \gdiff.diff_pntr_pad_reg[4]_i_1_n_2 ;
wire \gdiff.diff_pntr_pad_reg[4]_i_1_n_3 ;
wire \gdiff.diff_pntr_pad_reg[8]_i_1_n_0 ;
wire \gdiff.diff_pntr_pad_reg[8]_i_1_n_1 ;
wire \gdiff.diff_pntr_pad_reg[8]_i_1_n_2 ;
wire \gdiff.diff_pntr_pad_reg[8]_i_1_n_3 ;
wire [7:0]\gic0.gc0.count_d1_reg[7] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [9:0]\gic0.gc0.count_reg[9] ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ;
wire \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ;
wire [7:0]gray2bin;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire p_0_out;
wire p_0_out_0;
wire [9:0]p_22_out;
wire [9:0]p_3_out;
wire [9:0]p_4_out;
wire [9:9]p_5_out;
wire [9:9]p_6_out;
wire rd_clk;
wire \rd_dc_i[3]_i_2_n_0 ;
wire \rd_dc_i[3]_i_3_n_0 ;
wire \rd_dc_i[3]_i_4_n_0 ;
wire \rd_dc_i[3]_i_5_n_0 ;
wire \rd_dc_i[7]_i_2_n_0 ;
wire \rd_dc_i[7]_i_3_n_0 ;
wire \rd_dc_i[7]_i_4_n_0 ;
wire \rd_dc_i[7]_i_5_n_0 ;
wire \rd_dc_i[9]_i_2_n_0 ;
wire \rd_dc_i[9]_i_3_n_0 ;
wire \rd_dc_i_reg[3]_i_1_n_0 ;
wire \rd_dc_i_reg[3]_i_1_n_1 ;
wire \rd_dc_i_reg[3]_i_1_n_2 ;
wire \rd_dc_i_reg[3]_i_1_n_3 ;
wire \rd_dc_i_reg[7]_i_1_n_0 ;
wire \rd_dc_i_reg[7]_i_1_n_1 ;
wire \rd_dc_i_reg[7]_i_1_n_2 ;
wire \rd_dc_i_reg[7]_i_1_n_3 ;
wire [8:0]\rd_dc_i_reg[9] ;
wire \rd_dc_i_reg[9]_i_1_n_3 ;
wire [9:0]rd_pntr_gc;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire [3:0]v1_reg_1;
wire [4:0]v1_reg_2;
wire wr_clk;
wire [9:0]wr_pntr_gc;
wire [3:1]\NLW_gdiff.diff_pntr_pad_reg[10]_i_1_CO_UNCONNECTED ;
wire [3:2]\NLW_gdiff.diff_pntr_pad_reg[10]_i_1_O_UNCONNECTED ;
wire [0:0]\NLW_gdiff.diff_pntr_pad_reg[4]_i_1_O_UNCONNECTED ;
wire [0:0]\NLW_rd_dc_i_reg[3]_i_1_O_UNCONNECTED ;
wire [3:1]\NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED ;
wire [3:2]\NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED ;
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[10]_i_2
(.I0(p_22_out[9]),
.I1(Q[9]),
.O(\gdiff.diff_pntr_pad[10]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[10]_i_3
(.I0(p_22_out[8]),
.I1(Q[8]),
.O(\gdiff.diff_pntr_pad[10]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[4]_i_3
(.I0(p_22_out[3]),
.I1(Q[3]),
.O(\gdiff.diff_pntr_pad[4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[4]_i_4
(.I0(p_22_out[2]),
.I1(Q[2]),
.O(\gdiff.diff_pntr_pad[4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[4]_i_5
(.I0(p_22_out[1]),
.I1(Q[1]),
.O(\gdiff.diff_pntr_pad[4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[4]_i_6
(.I0(p_22_out[0]),
.I1(Q[0]),
.O(\gdiff.diff_pntr_pad[4]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[8]_i_2
(.I0(p_22_out[7]),
.I1(Q[7]),
.O(\gdiff.diff_pntr_pad[8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[8]_i_3
(.I0(p_22_out[6]),
.I1(Q[6]),
.O(\gdiff.diff_pntr_pad[8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[8]_i_4
(.I0(p_22_out[5]),
.I1(Q[5]),
.O(\gdiff.diff_pntr_pad[8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[8]_i_5
(.I0(p_22_out[4]),
.I1(Q[4]),
.O(\gdiff.diff_pntr_pad[8]_i_5_n_0 ));
CARRY4 \gdiff.diff_pntr_pad_reg[10]_i_1
(.CI(\gdiff.diff_pntr_pad_reg[8]_i_1_n_0 ),
.CO({\NLW_gdiff.diff_pntr_pad_reg[10]_i_1_CO_UNCONNECTED [3:1],\gdiff.diff_pntr_pad_reg[10]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,p_22_out[8]}),
.O({\NLW_gdiff.diff_pntr_pad_reg[10]_i_1_O_UNCONNECTED [3:2],D[8:7]}),
.S({1'b0,1'b0,\gdiff.diff_pntr_pad[10]_i_2_n_0 ,\gdiff.diff_pntr_pad[10]_i_3_n_0 }));
CARRY4 \gdiff.diff_pntr_pad_reg[4]_i_1
(.CI(1'b0),
.CO({\gdiff.diff_pntr_pad_reg[4]_i_1_n_0 ,\gdiff.diff_pntr_pad_reg[4]_i_1_n_1 ,\gdiff.diff_pntr_pad_reg[4]_i_1_n_2 ,\gdiff.diff_pntr_pad_reg[4]_i_1_n_3 }),
.CYINIT(p_0_out),
.DI(p_22_out[3:0]),
.O({D[2:0],\NLW_gdiff.diff_pntr_pad_reg[4]_i_1_O_UNCONNECTED [0]}),
.S({\gdiff.diff_pntr_pad[4]_i_3_n_0 ,\gdiff.diff_pntr_pad[4]_i_4_n_0 ,\gdiff.diff_pntr_pad[4]_i_5_n_0 ,\gdiff.diff_pntr_pad[4]_i_6_n_0 }));
CARRY4 \gdiff.diff_pntr_pad_reg[8]_i_1
(.CI(\gdiff.diff_pntr_pad_reg[4]_i_1_n_0 ),
.CO({\gdiff.diff_pntr_pad_reg[8]_i_1_n_0 ,\gdiff.diff_pntr_pad_reg[8]_i_1_n_1 ,\gdiff.diff_pntr_pad_reg[8]_i_1_n_2 ,\gdiff.diff_pntr_pad_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(p_22_out[7:4]),
.O(D[6:3]),
.S({\gdiff.diff_pntr_pad[8]_i_2_n_0 ,\gdiff.diff_pntr_pad[8]_i_3_n_0 ,\gdiff.diff_pntr_pad[8]_i_4_n_0 ,\gdiff.diff_pntr_pad[8]_i_5_n_0 }));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(p_22_out[0]),
.I1(Q[0]),
.I2(p_22_out[1]),
.I3(Q[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(p_22_out[0]),
.I1(\gc0.count_reg[9] [0]),
.I2(p_22_out[1]),
.I3(\gc0.count_reg[9] [1]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(RD_PNTR_WR[0]),
.I1(\gic0.gc0.count_d1_reg[7] [0]),
.I2(RD_PNTR_WR[1]),
.I3(\gic0.gc0.count_d1_reg[7] [1]),
.O(v1_reg_1[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(RD_PNTR_WR[0]),
.I1(\gic0.gc0.count_reg[9] [0]),
.I2(RD_PNTR_WR[1]),
.I3(\gic0.gc0.count_reg[9] [1]),
.O(v1_reg_2[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(p_22_out[2]),
.I1(Q[2]),
.I2(p_22_out[3]),
.I3(Q[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(p_22_out[2]),
.I1(\gc0.count_reg[9] [2]),
.I2(p_22_out[3]),
.I3(\gc0.count_reg[9] [3]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(RD_PNTR_WR[2]),
.I1(\gic0.gc0.count_d1_reg[7] [2]),
.I2(RD_PNTR_WR[3]),
.I3(\gic0.gc0.count_d1_reg[7] [3]),
.O(v1_reg_1[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(RD_PNTR_WR[2]),
.I1(\gic0.gc0.count_reg[9] [2]),
.I2(RD_PNTR_WR[3]),
.I3(\gic0.gc0.count_reg[9] [3]),
.O(v1_reg_2[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(p_22_out[4]),
.I1(Q[4]),
.I2(p_22_out[5]),
.I3(Q[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(p_22_out[4]),
.I1(\gc0.count_reg[9] [4]),
.I2(p_22_out[5]),
.I3(\gc0.count_reg[9] [5]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(RD_PNTR_WR[4]),
.I1(\gic0.gc0.count_d1_reg[7] [4]),
.I2(RD_PNTR_WR[5]),
.I3(\gic0.gc0.count_d1_reg[7] [5]),
.O(v1_reg_1[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(RD_PNTR_WR[4]),
.I1(\gic0.gc0.count_reg[9] [4]),
.I2(RD_PNTR_WR[5]),
.I3(\gic0.gc0.count_reg[9] [5]),
.O(v1_reg_2[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(p_22_out[6]),
.I1(Q[6]),
.I2(p_22_out[7]),
.I3(Q[7]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(p_22_out[6]),
.I1(\gc0.count_reg[9] [6]),
.I2(p_22_out[7]),
.I3(\gc0.count_reg[9] [7]),
.O(v1_reg_0[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(RD_PNTR_WR[6]),
.I1(\gic0.gc0.count_d1_reg[7] [6]),
.I2(RD_PNTR_WR[7]),
.I3(\gic0.gc0.count_d1_reg[7] [7]),
.O(v1_reg_1[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(RD_PNTR_WR[6]),
.I1(\gic0.gc0.count_reg[9] [6]),
.I2(RD_PNTR_WR[7]),
.I3(\gic0.gc0.count_reg[9] [7]),
.O(v1_reg_2[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(p_22_out[8]),
.I1(Q[8]),
.I2(p_22_out[9]),
.I3(Q[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__0
(.I0(p_22_out[8]),
.I1(\gc0.count_reg[9] [8]),
.I2(p_22_out[9]),
.I3(\gc0.count_reg[9] [9]),
.O(v1_reg_0[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__2
(.I0(RD_PNTR_WR[8]),
.I1(\gic0.gc0.count_reg[9] [8]),
.I2(RD_PNTR_WR[9]),
.I3(\gic0.gc0.count_reg[9] [9]),
.O(v1_reg_2[4]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q(wr_pntr_gc),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.rd_clk(rd_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q(rd_pntr_gc),
.wr_clk(wr_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_3_out),
.\gnxpm_cdc.wr_pntr_bin_reg[8] ({p_0_out_0,gray2bin}),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(p_5_out),
.rd_clk(rd_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.\gnxpm_cdc.rd_pntr_bin_reg[8] ({\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 }),
.out(p_6_out),
.wr_clk(wr_clk));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ),
.Q(RD_PNTR_WR[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ),
.Q(RD_PNTR_WR[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ),
.Q(RD_PNTR_WR[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ),
.Q(RD_PNTR_WR[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ),
.Q(RD_PNTR_WR[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ),
.Q(RD_PNTR_WR[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ),
.Q(RD_PNTR_WR[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ),
.Q(RD_PNTR_WR[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ),
.Q(RD_PNTR_WR[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(p_6_out),
.Q(RD_PNTR_WR[9]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1
(.I0(Q[1]),
.I1(Q[2]),
.O(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.O(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[3]_i_1
(.I0(Q[3]),
.I1(Q[4]),
.O(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[4]_i_1
(.I0(Q[4]),
.I1(Q[5]),
.O(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[5]_i_1
(.I0(Q[5]),
.I1(Q[6]),
.O(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[6]_i_1
(.I0(Q[6]),
.I1(Q[7]),
.O(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[7]_i_1
(.I0(Q[7]),
.I1(Q[8]),
.O(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[8]_i_1
(.I0(Q[8]),
.I1(Q[9]),
.O(\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ),
.Q(rd_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ),
.Q(rd_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ),
.Q(rd_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ),
.Q(rd_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ),
.Q(rd_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[9]),
.Q(rd_pntr_gc[9]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[0]),
.Q(p_22_out[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[1]),
.Q(p_22_out[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[2]),
.Q(p_22_out[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[3]),
.Q(p_22_out[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[4]),
.Q(p_22_out[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[5]),
.Q(p_22_out[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[6]),
.Q(p_22_out[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[7]),
.Q(p_22_out[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_out_0),
.Q(p_22_out[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_5_out),
.Q(p_22_out[9]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [0]),
.I1(\gic0.gc0.count_d2_reg[9] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [1]),
.I1(\gic0.gc0.count_d2_reg[9] [2]),
.O(bin2gray[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [2]),
.I1(\gic0.gc0.count_d2_reg[9] [3]),
.O(bin2gray[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[3]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [3]),
.I1(\gic0.gc0.count_d2_reg[9] [4]),
.O(bin2gray[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[4]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [4]),
.I1(\gic0.gc0.count_d2_reg[9] [5]),
.O(bin2gray[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[5]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [5]),
.I1(\gic0.gc0.count_d2_reg[9] [6]),
.O(bin2gray[5]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[6]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [6]),
.I1(\gic0.gc0.count_d2_reg[9] [7]),
.O(bin2gray[6]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[7]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [7]),
.I1(\gic0.gc0.count_d2_reg[9] [8]),
.O(bin2gray[7]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[8]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [8]),
.I1(\gic0.gc0.count_d2_reg[9] [9]),
.O(bin2gray[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[3]),
.Q(wr_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[4]),
.Q(wr_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[5]),
.Q(wr_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[6]),
.Q(wr_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[7]),
.Q(wr_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[8]),
.Q(wr_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[9] [9]),
.Q(wr_pntr_gc[9]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_2
(.I0(p_22_out[3]),
.I1(Q[3]),
.O(\rd_dc_i[3]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_3
(.I0(p_22_out[2]),
.I1(Q[2]),
.O(\rd_dc_i[3]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_4
(.I0(p_22_out[1]),
.I1(Q[1]),
.O(\rd_dc_i[3]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_5
(.I0(p_22_out[0]),
.I1(Q[0]),
.O(\rd_dc_i[3]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_2
(.I0(p_22_out[7]),
.I1(Q[7]),
.O(\rd_dc_i[7]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_3
(.I0(p_22_out[6]),
.I1(Q[6]),
.O(\rd_dc_i[7]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_4
(.I0(p_22_out[5]),
.I1(Q[5]),
.O(\rd_dc_i[7]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_5
(.I0(p_22_out[4]),
.I1(Q[4]),
.O(\rd_dc_i[7]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[9]_i_2
(.I0(p_22_out[9]),
.I1(Q[9]),
.O(\rd_dc_i[9]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[9]_i_3
(.I0(p_22_out[8]),
.I1(Q[8]),
.O(\rd_dc_i[9]_i_3_n_0 ));
CARRY4 \rd_dc_i_reg[3]_i_1
(.CI(1'b0),
.CO({\rd_dc_i_reg[3]_i_1_n_0 ,\rd_dc_i_reg[3]_i_1_n_1 ,\rd_dc_i_reg[3]_i_1_n_2 ,\rd_dc_i_reg[3]_i_1_n_3 }),
.CYINIT(1'b1),
.DI(p_22_out[3:0]),
.O({\rd_dc_i_reg[9] [2:0],\NLW_rd_dc_i_reg[3]_i_1_O_UNCONNECTED [0]}),
.S({\rd_dc_i[3]_i_2_n_0 ,\rd_dc_i[3]_i_3_n_0 ,\rd_dc_i[3]_i_4_n_0 ,\rd_dc_i[3]_i_5_n_0 }));
CARRY4 \rd_dc_i_reg[7]_i_1
(.CI(\rd_dc_i_reg[3]_i_1_n_0 ),
.CO({\rd_dc_i_reg[7]_i_1_n_0 ,\rd_dc_i_reg[7]_i_1_n_1 ,\rd_dc_i_reg[7]_i_1_n_2 ,\rd_dc_i_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(p_22_out[7:4]),
.O(\rd_dc_i_reg[9] [6:3]),
.S({\rd_dc_i[7]_i_2_n_0 ,\rd_dc_i[7]_i_3_n_0 ,\rd_dc_i[7]_i_4_n_0 ,\rd_dc_i[7]_i_5_n_0 }));
CARRY4 \rd_dc_i_reg[9]_i_1
(.CI(\rd_dc_i_reg[7]_i_1_n_0 ),
.CO({\NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED [3:1],\rd_dc_i_reg[9]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,p_22_out[8]}),
.O({\NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED [3:2],\rd_dc_i_reg[9] [8:7]}),
.S({1'b0,1'b0,\rd_dc_i[9]_i_2_n_0 ,\rd_dc_i[9]_i_3_n_0 }));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
(comp1,
\gnxpm_cdc.rd_pntr_bin_reg[6] ,
v1_reg_0);
output comp1;
input [3:0]\gnxpm_cdc.rd_pntr_bin_reg[6] ;
input [0:0]v1_reg_0;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp1;
wire [3:0]\gnxpm_cdc.rd_pntr_bin_reg[6] ;
wire [0:0]v1_reg_0;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(\gnxpm_cdc.rd_pntr_bin_reg[6] ));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3
(ram_full_fb_i_reg,
v1_reg,
out,
wr_en,
wr_rst_busy,
comp1);
output ram_full_fb_i_reg;
input [4:0]v1_reg;
input out;
input wr_en;
input wr_rst_busy;
input comp1;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp1;
wire comp2;
wire out;
wire ram_full_fb_i_reg;
wire [4:0]v1_reg;
wire wr_en;
wire wr_rst_busy;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp2}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]}));
LUT5 #(
.INIT(32'h00FF0020))
ram_full_i_i_1
(.I0(comp2),
.I1(out),
.I2(wr_en),
.I3(wr_rst_busy),
.I4(comp1),
.O(ram_full_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4
(ram_empty_fb_i_reg,
v1_reg,
rd_en,
out,
comp1);
output ram_empty_fb_i_reg;
input [4:0]v1_reg;
input rd_en;
input out;
input comp1;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp0;
wire comp1;
wire out;
wire ram_empty_fb_i_reg;
wire rd_en;
wire [4:0]v1_reg;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]}));
LUT4 #(
.INIT(16'hAEAA))
ram_empty_i_i_1
(.I0(comp0),
.I1(rd_en),
.I2(out),
.I3(comp1),
.O(ram_empty_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5
(comp1,
v1_reg_0);
output comp1;
input [4:0]v1_reg_0;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp1;
wire [4:0]v1_reg_0;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
(wr_rst_busy,
dout,
empty,
full,
rd_data_count,
wr_data_count,
prog_empty,
prog_full,
rd_en,
wr_clk,
rd_clk,
din,
rst,
wr_en);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
output [8:0]rd_data_count;
output [9:0]wr_data_count;
output prog_empty;
output prog_full;
input rd_en;
input wr_clk;
input rd_clk;
input [63:0]din;
input rst;
input wr_en;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire [4:0]\gras.rsts/c0/v1_reg ;
wire [4:0]\gras.rsts/c1/v1_reg ;
wire [3:0]\gwas.wsts/c1/v1_reg ;
wire [4:0]\gwas.wsts/c2/v1_reg ;
wire [9:1]minusOp;
wire p_0_out;
wire [9:0]p_0_out_0;
wire [9:0]p_12_out;
wire [7:0]p_13_out;
wire p_18_out;
wire [9:0]p_23_out;
wire p_2_out;
wire [10:2]plusOp;
wire prog_empty;
wire prog_full;
wire rd_clk;
wire [8:0]rd_data_count;
wire rd_en;
wire [9:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst;
wire rst_full_ff_i;
wire tmp_ram_rd_en;
wire wr_clk;
wire [9:0]wr_data_count;
wire wr_en;
wire [9:0]wr_pntr_plus2;
wire wr_rst_busy;
wire [1:0]wr_rst_i;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D(plusOp),
.Q(p_0_out_0),
.RD_PNTR_WR(p_23_out),
.\gc0.count_reg[9] (rd_pntr_plus1),
.\gic0.gc0.count_d1_reg[7] (p_13_out),
.\gic0.gc0.count_d2_reg[9] (p_12_out),
.\gic0.gc0.count_reg[9] (wr_pntr_plus2),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.p_0_out(p_0_out),
.rd_clk(rd_clk),
.\rd_dc_i_reg[9] (minusOp),
.v1_reg(\gras.rsts/c0/v1_reg ),
.v1_reg_0(\gras.rsts/c1/v1_reg ),
.v1_reg_1(\gwas.wsts/c1/v1_reg ),
.v1_reg_2(\gwas.wsts/c2/v1_reg ),
.wr_clk(wr_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic \gntv_or_sync_fifo.gl0.rd
(.AR(rd_rst_i[2]),
.D(plusOp),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (p_0_out_0),
.Q(rd_pntr_plus1),
.empty(empty),
.\gnxpm_cdc.wr_pntr_bin_reg[8] (minusOp),
.out(p_2_out),
.p_0_out(p_0_out),
.prog_empty(prog_empty),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.v1_reg(\gras.rsts/c0/v1_reg ),
.v1_reg_0(\gras.rsts/c1/v1_reg ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (p_12_out),
.E(p_18_out),
.Q(p_13_out),
.RD_PNTR_WR(p_23_out),
.full(full),
.\gic0.gc0.count_d1_reg[9] (wr_pntr_plus2),
.\gnxpm_cdc.rd_pntr_bin_reg[6] (\gwas.wsts/c1/v1_reg ),
.out(rst_full_ff_i),
.prog_full(prog_full),
.v1_reg(\gwas.wsts/c2/v1_reg ),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory \gntv_or_sync_fifo.mem
(.E(p_18_out),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (p_0_out_0),
.\gic0.gc0.count_d2_reg[9] (p_12_out),
.out(rd_rst_i[0]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.out(wr_rst_i),
.ram_empty_fb_i_reg(p_2_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
(wr_rst_busy,
dout,
empty,
full,
rd_data_count,
wr_data_count,
prog_empty,
prog_full,
rd_en,
wr_clk,
rd_clk,
din,
rst,
wr_en);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
output [8:0]rd_data_count;
output [9:0]wr_data_count;
output prog_empty;
output prog_full;
input rd_en;
input wr_clk;
input rd_clk;
input [63:0]din;
input rst;
input wr_en;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire prog_empty;
wire prog_full;
wire rd_clk;
wire [8:0]rd_data_count;
wire rd_en;
wire rst;
wire wr_clk;
wire [9:0]wr_data_count;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo \grf.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.prog_empty(prog_empty),
.prog_full(prog_full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "64" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "1" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "1" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "1kx36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "313" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "314" *) (* C_PROG_EMPTY_TYPE = "1" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "66" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "65" *) (* C_PROG_FULL_TYPE = "1" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "9" *)
(* C_RD_DEPTH = "1024" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [63:0]din;
input wr_en;
input rd_en;
input [9:0]prog_empty_thresh;
input [9:0]prog_empty_thresh_assert;
input [9:0]prog_empty_thresh_negate;
input [9:0]prog_full_thresh;
input [9:0]prog_full_thresh_assert;
input [9:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [63:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [9:0]data_count;
output [8:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire prog_empty;
wire prog_full;
wire rd_clk;
wire [8:0]rd_data_count;
wire rd_en;
wire rst;
wire wr_clk;
wire [9:0]wr_data_count;
wire wr_en;
wire wr_rst_busy;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth inst_fifo_gen
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.prog_empty(prog_empty),
.prog_full(prog_full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
(wr_rst_busy,
dout,
empty,
full,
rd_data_count,
wr_data_count,
prog_empty,
prog_full,
rd_en,
wr_clk,
rd_clk,
din,
rst,
wr_en);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
output [8:0]rd_data_count;
output [9:0]wr_data_count;
output prog_empty;
output prog_full;
input rd_en;
input wr_clk;
input rd_clk;
input [63:0]din;
input rst;
input wr_en;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire prog_empty;
wire prog_full;
wire rd_clk;
wire [8:0]rd_data_count;
wire rd_en;
wire rst;
wire wr_clk;
wire [9:0]wr_data_count;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top \gconvfifo.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.prog_empty(prog_empty),
.prog_full(prog_full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [0:0]E;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 \gbm.gbmg.gbmga.ngecc.bmg
(.E(E),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
(Q,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
E,
rd_clk,
AR);
output [9:0]Q;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
input [0:0]E;
input rd_clk;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [9:0]Q;
wire \gc0.count[9]_i_2_n_0 ;
wire [9:0]plusOp__0;
wire rd_clk;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp__0[0]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gc0.count[5]_i_1
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(plusOp__0[5]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[6]_i_1
(.I0(\gc0.count[9]_i_2_n_0 ),
.I1(Q[6]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[7]_i_1
(.I0(\gc0.count[9]_i_2_n_0 ),
.I1(Q[6]),
.I2(Q[7]),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[8]_i_1
(.I0(Q[6]),
.I1(\gc0.count[9]_i_2_n_0 ),
.I2(Q[7]),
.I3(Q[8]),
.O(plusOp__0[8]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[9]_i_1
(.I0(Q[7]),
.I1(\gc0.count[9]_i_2_n_0 ),
.I2(Q[6]),
.I3(Q[8]),
.I4(Q[9]),
.O(plusOp__0[9]));
LUT6 #(
.INIT(64'h8000000000000000))
\gc0.count[9]_i_2
(.I0(Q[5]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.I4(Q[2]),
.I5(Q[4]),
.O(\gc0.count[9]_i_2_n_0 ));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[8]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[9]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(rd_clk),
.CE(E),
.D(plusOp__0[0]),
.PRE(AR),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[9]),
.Q(Q[9]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as
(rd_data_count,
\gnxpm_cdc.wr_pntr_bin_reg[8] ,
rd_clk,
AR);
output [8:0]rd_data_count;
input [8:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
input rd_clk;
input [0:0]AR;
wire [0:0]AR;
wire [8:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
wire rd_clk;
wire [8:0]rd_data_count;
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [0]),
.Q(rd_data_count[0]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [1]),
.Q(rd_data_count[1]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [2]),
.Q(rd_data_count[2]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [3]),
.Q(rd_data_count[3]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [4]),
.Q(rd_data_count[4]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [5]),
.Q(rd_data_count[5]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [6]),
.Q(rd_data_count[6]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [7]),
.Q(rd_data_count[7]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [8]),
.Q(rd_data_count[8]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
(empty,
out,
prog_empty,
Q,
p_0_out,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
rd_data_count,
v1_reg,
v1_reg_0,
rd_clk,
AR,
rd_en,
D,
\gnxpm_cdc.wr_pntr_bin_reg[8] );
output empty;
output out;
output prog_empty;
output [9:0]Q;
output p_0_out;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output [8:0]rd_data_count;
input [4:0]v1_reg;
input [4:0]v1_reg_0;
input rd_clk;
input [0:0]AR;
input rd_en;
input [8:0]D;
input [8:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
wire [0:0]AR;
wire [8:0]D;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [9:0]Q;
wire empty;
wire [8:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
wire \gras.rsts_n_2 ;
wire out;
wire p_0_out;
wire prog_empty;
wire rd_clk;
wire [8:0]rd_data_count;
wire rd_en;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as \gras.gpe.rdpe
(.AR(AR),
.D(D),
.out(out),
.prog_empty(prog_empty),
.rd_clk(rd_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as \gras.grdc1.rdc
(.AR(AR),
.\gnxpm_cdc.wr_pntr_bin_reg[8] (\gnxpm_cdc.wr_pntr_bin_reg[8] ),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as \gras.rsts
(.AR(AR),
.E(\gras.rsts_n_2 ),
.empty(empty),
.out(out),
.p_0_out(p_0_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.v1_reg(v1_reg),
.v1_reg_0(v1_reg_0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr rpntr
(.AR(AR),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
.E(\gras.rsts_n_2 ),
.Q(Q),
.rd_clk(rd_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as
(prog_empty,
rd_clk,
AR,
out,
D);
output prog_empty;
input rd_clk;
input [0:0]AR;
input out;
input [8:0]D;
wire [0:0]AR;
wire [8:0]D;
wire \gdiff.diff_pntr_pad_reg_n_0_[10] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[2] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[3] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[4] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[5] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[6] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[7] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[8] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[9] ;
wire \gpe1.prog_empty_i_i_1_n_0 ;
wire \gpe1.prog_empty_i_i_2_n_0 ;
wire \gpe1.prog_empty_i_i_3_n_0 ;
wire out;
wire prog_empty;
wire rd_clk;
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[10]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[8]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[10] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[0]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[1]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[2]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[4] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[3]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[5] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[4]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[6] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[5]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[7] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[6]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[8] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[7]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[9] ));
LUT4 #(
.INIT(16'h88B8))
\gpe1.prog_empty_i_i_1
(.I0(prog_empty),
.I1(out),
.I2(\gpe1.prog_empty_i_i_2_n_0 ),
.I3(\gpe1.prog_empty_i_i_3_n_0 ),
.O(\gpe1.prog_empty_i_i_1_n_0 ));
LUT6 #(
.INIT(64'h7F7F7FFFFFFFFFFF))
\gpe1.prog_empty_i_i_2
(.I0(\gdiff.diff_pntr_pad_reg_n_0_[9] ),
.I1(\gdiff.diff_pntr_pad_reg_n_0_[4] ),
.I2(\gdiff.diff_pntr_pad_reg_n_0_[6] ),
.I3(\gdiff.diff_pntr_pad_reg_n_0_[3] ),
.I4(\gdiff.diff_pntr_pad_reg_n_0_[2] ),
.I5(\gdiff.diff_pntr_pad_reg_n_0_[5] ),
.O(\gpe1.prog_empty_i_i_2_n_0 ));
LUT4 #(
.INIT(16'hFAEA))
\gpe1.prog_empty_i_i_3
(.I0(\gdiff.diff_pntr_pad_reg_n_0_[10] ),
.I1(\gdiff.diff_pntr_pad_reg_n_0_[7] ),
.I2(\gdiff.diff_pntr_pad_reg_n_0_[9] ),
.I3(\gdiff.diff_pntr_pad_reg_n_0_[8] ),
.O(\gpe1.prog_empty_i_i_3_n_0 ));
FDPE #(
.INIT(1'b1))
\gpe1.prog_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(\gpe1.prog_empty_i_i_1_n_0 ),
.PRE(AR),
.Q(prog_empty));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as
(empty,
out,
E,
p_0_out,
v1_reg,
v1_reg_0,
rd_clk,
AR,
rd_en);
output empty;
output out;
output [0:0]E;
output p_0_out;
input [4:0]v1_reg;
input [4:0]v1_reg_0;
input rd_clk;
input [0:0]AR;
input rd_en;
wire [0:0]AR;
wire [0:0]E;
wire c0_n_0;
wire comp1;
wire p_0_out;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire rd_clk;
wire rd_en;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
assign empty = ram_empty_i;
assign out = ram_empty_fb_i;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 c0
(.comp1(comp1),
.out(ram_empty_fb_i),
.ram_empty_fb_i_reg(c0_n_0),
.rd_en(rd_en),
.v1_reg(v1_reg));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 c1
(.comp1(comp1),
.v1_reg_0(v1_reg_0));
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[9]_i_1
(.I0(rd_en),
.I1(ram_empty_fb_i),
.O(E));
LUT2 #(
.INIT(4'hB))
\gdiff.diff_pntr_pad[4]_i_2
(.I0(ram_empty_fb_i),
.I1(rd_en),
.O(p_0_out));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(c0_n_0),
.PRE(AR),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(c0_n_0),
.PRE(AR),
.Q(ram_empty_i));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
wr_rst_busy,
tmp_ram_rd_en,
rd_clk,
wr_clk,
rst,
ram_empty_fb_i_reg,
rd_en);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output wr_rst_busy;
output tmp_ram_rd_en;
input rd_clk;
input wr_clk;
input rst;
input ram_empty_fb_i_reg;
input rd_en;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ;
wire p_7_out;
wire p_8_out;
wire ram_empty_fb_i_reg;
wire rd_clk;
wire rd_en;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
wire rst;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire tmp_ram_rd_en;
wire wr_clk;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign wr_rst_busy = rst_d3;
LUT3 #(
.INIT(8'hBA))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(rd_rst_reg[0]),
.I1(ram_empty_fb_i_reg),
.I2(rd_en),
.O(tmp_ram_rd_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.out(p_7_out),
.rd_clk(rd_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.out(p_8_out),
.wr_clk(wr_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.in0(rd_rst_asreg),
.out(p_7_out),
.rd_clk(rd_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.in0(wr_rst_asreg),
.out(p_8_out),
.wr_clk(wr_clk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(rd_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(rst),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(rst),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(wr_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[2]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
(out,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ,
in0,
rd_clk);
output out;
output \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
input [0:0]in0;
input rd_clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
wire rd_clk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
(out,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ,
in0,
wr_clk);
output out;
output \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
input [0:0]in0;
input wr_clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
wire wr_clk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
(AS,
out,
rd_clk,
in0);
output [0:0]AS;
input out;
input rd_clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire rd_clk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
(AS,
out,
wr_clk,
in0);
output [0:0]AS;
input out;
input wr_clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire wr_clk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0
(D,
Q,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [9:0]D;
input [9:0]Q;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [9:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign D[9:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[9]),
.Q(Q_reg[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1
(D,
Q,
wr_clk,
AR);
output [9:0]D;
input [9:0]Q;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire wr_clk;
assign D[9:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[9]),
.Q(Q_reg[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2
(out,
\gnxpm_cdc.wr_pntr_bin_reg[8] ,
D,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [0:0]out;
output [8:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
input [9:0]D;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [9:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ;
wire \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ;
wire \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ;
wire [8:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign out[0] = Q_reg[9];
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[9]),
.Q(Q_reg[9]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.wr_pntr_bin[0]_i_1
(.I0(Q_reg[1]),
.I1(Q_reg[0]),
.I2(Q_reg[2]),
.I3(\gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ),
.I4(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [0]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.wr_pntr_bin[0]_i_2
(.I0(Q_reg[4]),
.I1(Q_reg[3]),
.I2(Q_reg[9]),
.O(\gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.wr_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[9]),
.I2(Q_reg[3]),
.I3(Q_reg[4]),
.I4(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ),
.I5(Q_reg[1]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [1]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.wr_pntr_bin[2]_i_1
(.I0(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ),
.I1(Q_reg[4]),
.I2(Q_reg[3]),
.I3(Q_reg[9]),
.I4(Q_reg[2]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [2]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.wr_pntr_bin[2]_i_2
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[6]),
.I3(Q_reg[5]),
.O(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.wr_pntr_bin[3]_i_1
(.I0(Q_reg[9]),
.I1(Q_reg[3]),
.I2(Q_reg[4]),
.I3(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[3]_i_2
(.I0(Q_reg[5]),
.I1(Q_reg[6]),
.O(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.wr_pntr_bin[4]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[4]),
.I2(Q_reg[5]),
.I3(Q_reg[9]),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [4]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.wr_pntr_bin[5]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[5]),
.I2(Q_reg[6]),
.I3(Q_reg[9]),
.I4(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [5]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.wr_pntr_bin[6]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[6]),
.I2(Q_reg[9]),
.I3(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [6]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.wr_pntr_bin[7]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[9]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [7]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[8]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[9]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [8]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3
(out,
\gnxpm_cdc.rd_pntr_bin_reg[8] ,
D,
wr_clk,
AR);
output [0:0]out;
output [8:0]\gnxpm_cdc.rd_pntr_bin_reg[8] ;
input [9:0]D;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0 ;
wire \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ;
wire \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ;
wire [8:0]\gnxpm_cdc.rd_pntr_bin_reg[8] ;
wire wr_clk;
assign out[0] = Q_reg[9];
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[9]),
.Q(Q_reg[9]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.rd_pntr_bin[0]_i_1
(.I0(Q_reg[1]),
.I1(Q_reg[0]),
.I2(Q_reg[2]),
.I3(\gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0 ),
.I4(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [0]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.rd_pntr_bin[0]_i_2
(.I0(Q_reg[4]),
.I1(Q_reg[3]),
.I2(Q_reg[9]),
.O(\gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.rd_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[9]),
.I2(Q_reg[3]),
.I3(Q_reg[4]),
.I4(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ),
.I5(Q_reg[1]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [1]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.rd_pntr_bin[2]_i_1
(.I0(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ),
.I1(Q_reg[4]),
.I2(Q_reg[3]),
.I3(Q_reg[9]),
.I4(Q_reg[2]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [2]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.rd_pntr_bin[2]_i_2
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[6]),
.I3(Q_reg[5]),
.O(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.rd_pntr_bin[3]_i_1
(.I0(Q_reg[9]),
.I1(Q_reg[3]),
.I2(Q_reg[4]),
.I3(\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[3]_i_2
(.I0(Q_reg[5]),
.I1(Q_reg[6]),
.O(\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.rd_pntr_bin[4]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[4]),
.I2(Q_reg[5]),
.I3(Q_reg[9]),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [4]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.rd_pntr_bin[5]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[5]),
.I2(Q_reg[6]),
.I3(Q_reg[9]),
.I4(Q_reg[8]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [5]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.rd_pntr_bin[6]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[6]),
.I2(Q_reg[9]),
.I3(Q_reg[8]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [6]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.rd_pntr_bin[7]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[9]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [7]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[8]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[9]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [8]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
(\wr_data_count_i_reg[9] ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
\gdiff.diff_pntr_pad_reg[10] ,
Q,
\wr_data_count_i_reg[7] ,
\gdiff.diff_pntr_pad_reg[8] ,
S,
\gdiff.diff_pntr_pad_reg[4] ,
\gic0.gc0.count_d1_reg[9]_0 ,
v1_reg,
RD_PNTR_WR,
E,
wr_clk,
AR);
output [1:0]\wr_data_count_i_reg[9] ;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output [1:0]\gdiff.diff_pntr_pad_reg[10] ;
output [8:0]Q;
output [3:0]\wr_data_count_i_reg[7] ;
output [3:0]\gdiff.diff_pntr_pad_reg[8] ;
output [3:0]S;
output [3:0]\gdiff.diff_pntr_pad_reg[4] ;
output [9:0]\gic0.gc0.count_d1_reg[9]_0 ;
output [0:0]v1_reg;
input [9:0]RD_PNTR_WR;
input [0:0]E;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [8:0]Q;
wire [9:0]RD_PNTR_WR;
wire [3:0]S;
wire [1:0]\gdiff.diff_pntr_pad_reg[10] ;
wire [3:0]\gdiff.diff_pntr_pad_reg[4] ;
wire [3:0]\gdiff.diff_pntr_pad_reg[8] ;
wire \gic0.gc0.count[9]_i_2_n_0 ;
wire [9:0]\gic0.gc0.count_d1_reg[9]_0 ;
wire [9:9]p_13_out;
wire [9:0]plusOp__1;
wire [0:0]v1_reg;
wire wr_clk;
wire [3:0]\wr_data_count_i_reg[7] ;
wire [1:0]\wr_data_count_i_reg[9] ;
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [0]),
.O(plusOp__1[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [1]),
.O(plusOp__1[1]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [2]),
.O(plusOp__1[2]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [2]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [3]),
.O(plusOp__1[3]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gic0.gc0.count[4]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [2]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [3]),
.I4(\gic0.gc0.count_d1_reg[9]_0 [4]),
.O(plusOp__1[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gic0.gc0.count[5]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [3]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [2]),
.I4(\gic0.gc0.count_d1_reg[9]_0 [4]),
.I5(\gic0.gc0.count_d1_reg[9]_0 [5]),
.O(plusOp__1[5]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h9))
\gic0.gc0.count[6]_i_1
(.I0(\gic0.gc0.count[9]_i_2_n_0 ),
.I1(\gic0.gc0.count_d1_reg[9]_0 [6]),
.O(plusOp__1[6]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB4))
\gic0.gc0.count[7]_i_1
(.I0(\gic0.gc0.count[9]_i_2_n_0 ),
.I1(\gic0.gc0.count_d1_reg[9]_0 [6]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [7]),
.O(plusOp__1[7]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hDF20))
\gic0.gc0.count[8]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [6]),
.I1(\gic0.gc0.count[9]_i_2_n_0 ),
.I2(\gic0.gc0.count_d1_reg[9]_0 [7]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [8]),
.O(plusOp__1[8]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'hF7FF0800))
\gic0.gc0.count[9]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [8]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [7]),
.I2(\gic0.gc0.count[9]_i_2_n_0 ),
.I3(\gic0.gc0.count_d1_reg[9]_0 [6]),
.I4(\gic0.gc0.count_d1_reg[9]_0 [9]),
.O(plusOp__1[9]));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\gic0.gc0.count[9]_i_2
(.I0(\gic0.gc0.count_d1_reg[9]_0 [5]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [3]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I4(\gic0.gc0.count_d1_reg[9]_0 [2]),
.I5(\gic0.gc0.count_d1_reg[9]_0 [4]),
.O(\gic0.gc0.count[9]_i_2_n_0 ));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(wr_clk),
.CE(E),
.D(\gic0.gc0.count_d1_reg[9]_0 [0]),
.PRE(AR),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [9]),
.Q(p_13_out));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[8]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[0]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(wr_clk),
.CE(E),
.D(plusOp__1[1]),
.PRE(AR),
.Q(\gic0.gc0.count_d1_reg[9]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[2]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[3]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[4]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[5]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[6]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[7]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[8]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[9]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [9]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__1
(.I0(p_13_out),
.I1(RD_PNTR_WR[9]),
.I2(RD_PNTR_WR[8]),
.I3(Q[8]),
.O(v1_reg));
LUT2 #(
.INIT(4'h9))
minusOp_carry__0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]),
.I1(RD_PNTR_WR[7]),
.O(\wr_data_count_i_reg[7] [3]));
LUT2 #(
.INIT(4'h9))
minusOp_carry__0_i_2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]),
.I1(RD_PNTR_WR[6]),
.O(\wr_data_count_i_reg[7] [2]));
LUT2 #(
.INIT(4'h9))
minusOp_carry__0_i_3
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]),
.I1(RD_PNTR_WR[5]),
.O(\wr_data_count_i_reg[7] [1]));
LUT2 #(
.INIT(4'h9))
minusOp_carry__0_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]),
.I1(RD_PNTR_WR[4]),
.O(\wr_data_count_i_reg[7] [0]));
LUT2 #(
.INIT(4'h9))
minusOp_carry__1_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]),
.I1(RD_PNTR_WR[9]),
.O(\wr_data_count_i_reg[9] [1]));
LUT2 #(
.INIT(4'h9))
minusOp_carry__1_i_2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]),
.I1(RD_PNTR_WR[8]),
.O(\wr_data_count_i_reg[9] [0]));
LUT2 #(
.INIT(4'h9))
minusOp_carry_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]),
.I1(RD_PNTR_WR[3]),
.O(S[3]));
LUT2 #(
.INIT(4'h9))
minusOp_carry_i_2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]),
.I1(RD_PNTR_WR[2]),
.O(S[2]));
LUT2 #(
.INIT(4'h9))
minusOp_carry_i_3
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.I1(RD_PNTR_WR[1]),
.O(S[1]));
LUT2 #(
.INIT(4'h9))
minusOp_carry_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.I1(RD_PNTR_WR[0]),
.O(S[0]));
LUT2 #(
.INIT(4'h9))
plusOp_carry__0_i_1
(.I0(Q[7]),
.I1(RD_PNTR_WR[7]),
.O(\gdiff.diff_pntr_pad_reg[8] [3]));
LUT2 #(
.INIT(4'h9))
plusOp_carry__0_i_2
(.I0(Q[6]),
.I1(RD_PNTR_WR[6]),
.O(\gdiff.diff_pntr_pad_reg[8] [2]));
LUT2 #(
.INIT(4'h9))
plusOp_carry__0_i_3
(.I0(Q[5]),
.I1(RD_PNTR_WR[5]),
.O(\gdiff.diff_pntr_pad_reg[8] [1]));
LUT2 #(
.INIT(4'h9))
plusOp_carry__0_i_4
(.I0(Q[4]),
.I1(RD_PNTR_WR[4]),
.O(\gdiff.diff_pntr_pad_reg[8] [0]));
LUT2 #(
.INIT(4'h9))
plusOp_carry__1_i_1
(.I0(p_13_out),
.I1(RD_PNTR_WR[9]),
.O(\gdiff.diff_pntr_pad_reg[10] [1]));
LUT2 #(
.INIT(4'h9))
plusOp_carry__1_i_2
(.I0(Q[8]),
.I1(RD_PNTR_WR[8]),
.O(\gdiff.diff_pntr_pad_reg[10] [0]));
LUT2 #(
.INIT(4'h9))
plusOp_carry_i_1
(.I0(Q[3]),
.I1(RD_PNTR_WR[3]),
.O(\gdiff.diff_pntr_pad_reg[4] [3]));
LUT2 #(
.INIT(4'h9))
plusOp_carry_i_2
(.I0(Q[2]),
.I1(RD_PNTR_WR[2]),
.O(\gdiff.diff_pntr_pad_reg[4] [2]));
LUT2 #(
.INIT(4'h9))
plusOp_carry_i_3
(.I0(Q[1]),
.I1(RD_PNTR_WR[1]),
.O(\gdiff.diff_pntr_pad_reg[4] [1]));
LUT2 #(
.INIT(4'h9))
plusOp_carry_i_4
(.I0(Q[0]),
.I1(RD_PNTR_WR[0]),
.O(\gdiff.diff_pntr_pad_reg[4] [0]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as
(wr_data_count,
\gic0.gc0.count_d2_reg[8] ,
S,
\gic0.gc0.count_d2_reg[7] ,
\gic0.gc0.count_d2_reg[9] ,
wr_clk,
AR);
output [9:0]wr_data_count;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [3:0]S;
input [3:0]\gic0.gc0.count_d2_reg[7] ;
input [1:0]\gic0.gc0.count_d2_reg[9] ;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [3:0]S;
wire [3:0]\gic0.gc0.count_d2_reg[7] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire [1:0]\gic0.gc0.count_d2_reg[9] ;
wire minusOp_carry__0_n_0;
wire minusOp_carry__0_n_1;
wire minusOp_carry__0_n_2;
wire minusOp_carry__0_n_3;
wire minusOp_carry__0_n_4;
wire minusOp_carry__0_n_5;
wire minusOp_carry__0_n_6;
wire minusOp_carry__0_n_7;
wire minusOp_carry__1_n_3;
wire minusOp_carry__1_n_6;
wire minusOp_carry__1_n_7;
wire minusOp_carry_n_0;
wire minusOp_carry_n_1;
wire minusOp_carry_n_2;
wire minusOp_carry_n_3;
wire minusOp_carry_n_4;
wire minusOp_carry_n_5;
wire minusOp_carry_n_6;
wire minusOp_carry_n_7;
wire wr_clk;
wire [9:0]wr_data_count;
wire [3:1]NLW_minusOp_carry__1_CO_UNCONNECTED;
wire [3:2]NLW_minusOp_carry__1_O_UNCONNECTED;
CARRY4 minusOp_carry
(.CI(1'b0),
.CO({minusOp_carry_n_0,minusOp_carry_n_1,minusOp_carry_n_2,minusOp_carry_n_3}),
.CYINIT(1'b1),
.DI(\gic0.gc0.count_d2_reg[8] [3:0]),
.O({minusOp_carry_n_4,minusOp_carry_n_5,minusOp_carry_n_6,minusOp_carry_n_7}),
.S(S));
CARRY4 minusOp_carry__0
(.CI(minusOp_carry_n_0),
.CO({minusOp_carry__0_n_0,minusOp_carry__0_n_1,minusOp_carry__0_n_2,minusOp_carry__0_n_3}),
.CYINIT(1'b0),
.DI(\gic0.gc0.count_d2_reg[8] [7:4]),
.O({minusOp_carry__0_n_4,minusOp_carry__0_n_5,minusOp_carry__0_n_6,minusOp_carry__0_n_7}),
.S(\gic0.gc0.count_d2_reg[7] ));
CARRY4 minusOp_carry__1
(.CI(minusOp_carry__0_n_0),
.CO({NLW_minusOp_carry__1_CO_UNCONNECTED[3:1],minusOp_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\gic0.gc0.count_d2_reg[8] [8]}),
.O({NLW_minusOp_carry__1_O_UNCONNECTED[3:2],minusOp_carry__1_n_6,minusOp_carry__1_n_7}),
.S({1'b0,1'b0,\gic0.gc0.count_d2_reg[9] }));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry_n_7),
.Q(wr_data_count[0]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry_n_6),
.Q(wr_data_count[1]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry_n_5),
.Q(wr_data_count[2]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry_n_4),
.Q(wr_data_count[3]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry__0_n_7),
.Q(wr_data_count[4]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry__0_n_6),
.Q(wr_data_count[5]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry__0_n_5),
.Q(wr_data_count[6]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry__0_n_4),
.Q(wr_data_count[7]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry__1_n_7),
.Q(wr_data_count[8]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry__1_n_6),
.Q(wr_data_count[9]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
(full,
E,
Q,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
prog_full,
\gic0.gc0.count_d1_reg[9] ,
wr_data_count,
\gnxpm_cdc.rd_pntr_bin_reg[6] ,
v1_reg,
wr_clk,
out,
RD_PNTR_WR,
wr_en,
wr_rst_busy,
AR);
output full;
output [0:0]E;
output [7:0]Q;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output prog_full;
output [9:0]\gic0.gc0.count_d1_reg[9] ;
output [9:0]wr_data_count;
input [3:0]\gnxpm_cdc.rd_pntr_bin_reg[6] ;
input [4:0]v1_reg;
input wr_clk;
input out;
input [9:0]RD_PNTR_WR;
input wr_en;
input wr_rst_busy;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [7:0]Q;
wire [9:0]RD_PNTR_WR;
wire [4:4]\c1/v1_reg ;
wire full;
wire [9:0]\gic0.gc0.count_d1_reg[9] ;
wire [3:0]\gnxpm_cdc.rd_pntr_bin_reg[6] ;
wire \gwas.wsts_n_1 ;
wire out;
wire [8:8]p_13_out;
wire prog_full;
wire [4:0]v1_reg;
wire wpntr_n_0;
wire wpntr_n_1;
wire wpntr_n_12;
wire wpntr_n_13;
wire wpntr_n_23;
wire wpntr_n_24;
wire wpntr_n_25;
wire wpntr_n_26;
wire wpntr_n_27;
wire wpntr_n_28;
wire wpntr_n_29;
wire wpntr_n_30;
wire wpntr_n_31;
wire wpntr_n_32;
wire wpntr_n_33;
wire wpntr_n_34;
wire wpntr_n_35;
wire wpntr_n_36;
wire wpntr_n_37;
wire wpntr_n_38;
wire wr_clk;
wire [9:0]wr_data_count;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as \gwas.gpf.wrpf
(.AR(AR),
.E(E),
.Q({p_13_out,Q}),
.S({wpntr_n_35,wpntr_n_36,wpntr_n_37,wpntr_n_38}),
.\gic0.gc0.count_d1_reg[7] ({wpntr_n_27,wpntr_n_28,wpntr_n_29,wpntr_n_30}),
.\gic0.gc0.count_d1_reg[9] ({wpntr_n_12,wpntr_n_13}),
.out(out),
.prog_full(prog_full),
.ram_full_fb_i_reg(\gwas.wsts_n_1 ),
.wr_clk(wr_clk),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as \gwas.gwdc0.wdc
(.AR(AR),
.S({wpntr_n_31,wpntr_n_32,wpntr_n_33,wpntr_n_34}),
.\gic0.gc0.count_d2_reg[7] ({wpntr_n_23,wpntr_n_24,wpntr_n_25,wpntr_n_26}),
.\gic0.gc0.count_d2_reg[8] (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8:0]),
.\gic0.gc0.count_d2_reg[9] ({wpntr_n_0,wpntr_n_1}),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as \gwas.wsts
(.E(E),
.full(full),
.\gnxpm_cdc.rd_pntr_bin_reg[6] (\gnxpm_cdc.rd_pntr_bin_reg[6] ),
.\grstd1.grst_full.grst_f.rst_d2_reg (out),
.out(\gwas.wsts_n_1 ),
.v1_reg(v1_reg),
.v1_reg_0(\c1/v1_reg ),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr wpntr
(.AR(AR),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
.E(E),
.Q({p_13_out,Q}),
.RD_PNTR_WR(RD_PNTR_WR),
.S({wpntr_n_31,wpntr_n_32,wpntr_n_33,wpntr_n_34}),
.\gdiff.diff_pntr_pad_reg[10] ({wpntr_n_12,wpntr_n_13}),
.\gdiff.diff_pntr_pad_reg[4] ({wpntr_n_35,wpntr_n_36,wpntr_n_37,wpntr_n_38}),
.\gdiff.diff_pntr_pad_reg[8] ({wpntr_n_27,wpntr_n_28,wpntr_n_29,wpntr_n_30}),
.\gic0.gc0.count_d1_reg[9]_0 (\gic0.gc0.count_d1_reg[9] ),
.v1_reg(\c1/v1_reg ),
.wr_clk(wr_clk),
.\wr_data_count_i_reg[7] ({wpntr_n_23,wpntr_n_24,wpntr_n_25,wpntr_n_26}),
.\wr_data_count_i_reg[9] ({wpntr_n_0,wpntr_n_1}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as
(prog_full,
E,
Q,
S,
\gic0.gc0.count_d1_reg[7] ,
\gic0.gc0.count_d1_reg[9] ,
wr_clk,
out,
wr_rst_busy,
ram_full_fb_i_reg,
AR);
output prog_full;
input [0:0]E;
input [8:0]Q;
input [3:0]S;
input [3:0]\gic0.gc0.count_d1_reg[7] ;
input [1:0]\gic0.gc0.count_d1_reg[9] ;
input wr_clk;
input out;
input wr_rst_busy;
input ram_full_fb_i_reg;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [8:0]Q;
wire [3:0]S;
wire [9:1]diff_pntr;
wire [3:0]\gic0.gc0.count_d1_reg[7] ;
wire [1:0]\gic0.gc0.count_d1_reg[9] ;
wire \gpf1.prog_full_i_i_1_n_0 ;
wire \gpf1.prog_full_i_i_2_n_0 ;
wire \gpf1.prog_full_i_i_3_n_0 ;
wire out;
wire plusOp_carry__0_n_0;
wire plusOp_carry__0_n_1;
wire plusOp_carry__0_n_2;
wire plusOp_carry__0_n_3;
wire plusOp_carry__0_n_4;
wire plusOp_carry__0_n_5;
wire plusOp_carry__0_n_6;
wire plusOp_carry__0_n_7;
wire plusOp_carry__1_n_3;
wire plusOp_carry__1_n_6;
wire plusOp_carry__1_n_7;
wire plusOp_carry_n_0;
wire plusOp_carry_n_1;
wire plusOp_carry_n_2;
wire plusOp_carry_n_3;
wire plusOp_carry_n_4;
wire plusOp_carry_n_5;
wire plusOp_carry_n_6;
wire prog_full;
wire ram_full_fb_i_reg;
wire wr_clk;
wire wr_rst_busy;
wire [0:0]NLW_plusOp_carry_O_UNCONNECTED;
wire [3:1]NLW_plusOp_carry__1_CO_UNCONNECTED;
wire [3:2]NLW_plusOp_carry__1_O_UNCONNECTED;
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[10]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry__1_n_6),
.Q(diff_pntr[9]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry_n_6),
.Q(diff_pntr[1]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry_n_5),
.Q(diff_pntr[2]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry_n_4),
.Q(diff_pntr[3]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry__0_n_7),
.Q(diff_pntr[4]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry__0_n_6),
.Q(diff_pntr[5]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry__0_n_5),
.Q(diff_pntr[6]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry__0_n_4),
.Q(diff_pntr[7]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry__1_n_7),
.Q(diff_pntr[8]));
LUT5 #(
.INIT(32'h0F070007))
\gpf1.prog_full_i_i_1
(.I0(\gpf1.prog_full_i_i_2_n_0 ),
.I1(\gpf1.prog_full_i_i_3_n_0 ),
.I2(wr_rst_busy),
.I3(ram_full_fb_i_reg),
.I4(prog_full),
.O(\gpf1.prog_full_i_i_1_n_0 ));
LUT6 #(
.INIT(64'h00000001FFFFFFFF))
\gpf1.prog_full_i_i_2
(.I0(diff_pntr[4]),
.I1(diff_pntr[5]),
.I2(diff_pntr[3]),
.I3(diff_pntr[2]),
.I4(diff_pntr[1]),
.I5(diff_pntr[6]),
.O(\gpf1.prog_full_i_i_2_n_0 ));
LUT3 #(
.INIT(8'h01))
\gpf1.prog_full_i_i_3
(.I0(diff_pntr[9]),
.I1(diff_pntr[8]),
.I2(diff_pntr[7]),
.O(\gpf1.prog_full_i_i_3_n_0 ));
FDPE #(
.INIT(1'b1))
\gpf1.prog_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(\gpf1.prog_full_i_i_1_n_0 ),
.PRE(out),
.Q(prog_full));
CARRY4 plusOp_carry
(.CI(1'b0),
.CO({plusOp_carry_n_0,plusOp_carry_n_1,plusOp_carry_n_2,plusOp_carry_n_3}),
.CYINIT(E),
.DI(Q[3:0]),
.O({plusOp_carry_n_4,plusOp_carry_n_5,plusOp_carry_n_6,NLW_plusOp_carry_O_UNCONNECTED[0]}),
.S(S));
CARRY4 plusOp_carry__0
(.CI(plusOp_carry_n_0),
.CO({plusOp_carry__0_n_0,plusOp_carry__0_n_1,plusOp_carry__0_n_2,plusOp_carry__0_n_3}),
.CYINIT(1'b0),
.DI(Q[7:4]),
.O({plusOp_carry__0_n_4,plusOp_carry__0_n_5,plusOp_carry__0_n_6,plusOp_carry__0_n_7}),
.S(\gic0.gc0.count_d1_reg[7] ));
CARRY4 plusOp_carry__1
(.CI(plusOp_carry__0_n_0),
.CO({NLW_plusOp_carry__1_CO_UNCONNECTED[3:1],plusOp_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,Q[8]}),
.O({NLW_plusOp_carry__1_O_UNCONNECTED[3:2],plusOp_carry__1_n_6,plusOp_carry__1_n_7}),
.S({1'b0,1'b0,\gic0.gc0.count_d1_reg[9] }));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as
(full,
out,
E,
\gnxpm_cdc.rd_pntr_bin_reg[6] ,
v1_reg_0,
v1_reg,
wr_clk,
\grstd1.grst_full.grst_f.rst_d2_reg ,
wr_en,
wr_rst_busy);
output full;
output out;
output [0:0]E;
input [3:0]\gnxpm_cdc.rd_pntr_bin_reg[6] ;
input [0:0]v1_reg_0;
input [4:0]v1_reg;
input wr_clk;
input \grstd1.grst_full.grst_f.rst_d2_reg ;
input wr_en;
input wr_rst_busy;
wire [0:0]E;
wire c2_n_0;
wire comp1;
wire [3:0]\gnxpm_cdc.rd_pntr_bin_reg[6] ;
wire \grstd1.grst_full.grst_f.rst_d2_reg ;
(* DONT_TOUCH *) wire ram_full_fb_i;
(* DONT_TOUCH *) wire ram_full_i;
wire [4:0]v1_reg;
wire [0:0]v1_reg_0;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
assign full = ram_full_i;
assign out = ram_full_fb_i;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1
(.I0(wr_en),
.I1(ram_full_fb_i),
.O(E));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare c1
(.comp1(comp1),
.\gnxpm_cdc.rd_pntr_bin_reg[6] (\gnxpm_cdc.rd_pntr_bin_reg[6] ),
.v1_reg_0(v1_reg_0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 c2
(.comp1(comp1),
.out(ram_full_fb_i),
.ram_full_fb_i_reg(c2_n_0),
.v1_reg(v1_reg),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(c2_n_0),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(c2_n_0),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_i));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module Counter32_RV1 (
input Reset_n_i,
input Clk_i,
input Preset_i,
input Enable_i,
input[31:0] PresetVal_i,
output Zero_o
);
wire ResetSig_s;
wire Direction_s;
wire [15:0] DH_s;
wire [15:0] DL_s;
wire Overflow_s;
assign ResetSig_s = 1'b0;
assign Direction_s = 1'b1;
Counter32 ThisCounter (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
.ResetSig_i (ResetSig_s),
.Preset_i (Preset_i),
.Enable_i (Enable_i),
.Direction_i (Direction_s),
.PresetValH_i(PresetVal_i[31:16]),
.PresetValL_i(PresetVal_i[15:0]),
.DH_o (DH_s),
.DL_o (DL_s),
.Overflow_o (Overflow_s),
.Zero_o (Zero_o)
);
endmodule
module Counter32_RV1_Timer (
input Reset_n_i,
input Clk_i,
input Preset_i,
input Enable_i,
input[31:0] PresetVal_i,
output Zero_o
);
reg [31:0] Value;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Value <= 'd0;
end
else
begin
if (Preset_i) begin
Value <= PresetVal_i;
end else if (Enable_i)
begin
Value <= Value - 1'b1;
end
end
end
assign Zero_o = (Value == 0 ? 1'b1 : 1'b0);
endmodule
|
`timescale 1 ns / 1 ps
module hapara_axis_barrier_v1_0 #
(
// Users to add parameters here
parameter integer NUM_SLAVES = 2,
parameter integer DATA_WIDTH = 32
)
(
// Ports of Axi Master Bus Interface M00_AXIS
input wire aclk,
input wire aresetn,
input wire m00_axis_tvalid,
input wire [DATA_WIDTH-1 : 0] m00_axis_tdata,
output wire m00_axis_tready,
// Ports of Axi Master Bus Interface M01_AXIS
input wire m01_axis_tvalid,
input wire [DATA_WIDTH-1 : 0] m01_axis_tdata,
output wire m01_axis_tready,
// Ports of Axi Master Bus Interface M02_AXIS
input wire m02_axis_tvalid,
input wire [DATA_WIDTH-1 : 0] m02_axis_tdata,
output wire m02_axis_tready,
// Ports of Axi Master Bus Interface M03_AXIS
input wire m03_axis_tvalid,
input wire [DATA_WIDTH-1 : 0] m03_axis_tdata,
output wire m03_axis_tready,
// Ports of Axi Master Bus Interface M04_AXIS
input wire m04_axis_tvalid,
input wire [DATA_WIDTH-1 : 0] m04_axis_tdata,
output wire m04_axis_tready,
// Ports of Axi Master Bus Interface M05_AXIS
input wire m05_axis_tvalid,
input wire [DATA_WIDTH-1 : 0] m05_axis_tdata,
output wire m05_axis_tready,
// Ports of Axi Master Bus Interface M06_AXIS
input wire m06_axis_tvalid,
input wire [DATA_WIDTH-1 : 0] m06_axis_tdata,
output wire m06_axis_tready,
// Ports of Axi Master Bus Interface M07_AXIS
input wire m07_axis_tvalid,
input wire [DATA_WIDTH-1 : 0] m07_axis_tdata,
output wire m07_axis_tready,
// Ports of Axi Master Bus Interface M08_AXIS
input wire m08_axis_tvalid,
input wire [DATA_WIDTH-1 : 0] m08_axis_tdata,
output wire m08_axis_tready,
// Connect to as master to slaves
output wire s00_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] s00_axis_tdata,
input wire s00_axis_tready,
// Ports of Axi Master Bus Interface s01_AXIS
output wire s01_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] s01_axis_tdata,
input wire s01_axis_tready,
// Ports of Axi Master Bus Interface s02_AXIS
output wire s02_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] s02_axis_tdata,
input wire s02_axis_tready,
// Ports of Axi Master Bus Interface s03_AXIS
output wire s03_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] s03_axis_tdata,
input wire s03_axis_tready,
// Ports of Axi Master Bus Interface s04_AXIS
output wire s04_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] s04_axis_tdata,
input wire s04_axis_tready,
// Ports of Axi Master Bus Interface s05_AXIS
output wire s05_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] s05_axis_tdata,
input wire s05_axis_tready,
// Ports of Axi Master Bus Interface s06_AXIS
output wire s06_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] s06_axis_tdata,
input wire s06_axis_tready,
// Ports of Axi Master Bus Interface s07_AXIS
output wire s07_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] s07_axis_tdata,
input wire s07_axis_tready,
// Ports of Axi Master Bus Interface s08_AXIS
output wire s08_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] s08_axis_tdata,
input wire s08_axis_tready
);
// Add user logic here
// assumption NUM_SLAVES is alway greater than 0
// clk and reset can use the first master port
wire notRelease;
wire syn;
generate if (NUM_SLAVES == 1)
begin: NUM_SLAVES_1
assign notRelease = m00_axis_tvalid;
assign syn = m00_axis_tvalid;
assign m00_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign s00_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s00_axis_tdata = 32'd0;
// wire notRelease;
// wire syn;
localparam waiting = 2'b01;
localparam locking = 2'b10;
localparam releasing = 2'b11;
reg [1 : 0] curr_state;
reg [1 : 0] next_state;
always @(posedge aclk or negedge aresetn) begin
if (!aresetn) begin
// reset
curr_state <= waiting;
end
else begin
curr_state <= next_state;
end
end
always @(curr_state or syn or notRelease) begin
case(curr_state)
waiting:
if (syn) begin
next_state = locking;
end
else begin
next_state = waiting;
end
locking:
if (!notRelease) begin
next_state = releasing;
end
else begin
next_state = locking;
end
releasing:
next_state = waiting;
default:
next_state = 2'bxx;
endcase
end
end
endgenerate
generate if (NUM_SLAVES == 2)
begin: NUM_SLAVES_2
assign notRelease = m00_axis_tvalid | m01_axis_tvalid;
assign syn = m00_axis_tvalid & m01_axis_tvalid;
assign m00_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m01_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign s00_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s01_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s00_axis_tdata = 32'd0;
assign s01_axis_tdata = 32'd1;
// wire notRelease;
// wire syn;
localparam waiting = 2'b01;
localparam locking = 2'b10;
localparam releasing = 2'b11;
reg [1 : 0] curr_state;
reg [1 : 0] next_state;
always @(posedge aclk or negedge aresetn) begin
if (!aresetn) begin
// reset
curr_state <= waiting;
end
else begin
curr_state <= next_state;
end
end
always @(curr_state or syn or notRelease) begin
case(curr_state)
waiting:
if (syn) begin
next_state = locking;
end
else begin
next_state = waiting;
end
locking:
if (!notRelease) begin
next_state = releasing;
end
else begin
next_state = locking;
end
releasing:
next_state = waiting;
default:
next_state = 2'bxx;
endcase
end
end
endgenerate
generate if (NUM_SLAVES == 3)
begin: NUM_SLAVES_3
assign notRelease = m00_axis_tvalid | m01_axis_tvalid | m02_axis_tvalid;
assign syn = m00_axis_tvalid & m01_axis_tvalid & m02_axis_tvalid;
assign m00_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m01_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m02_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign s00_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s01_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s02_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s00_axis_tdata = 32'd0;
assign s01_axis_tdata = 32'd1;
assign s02_axis_tdata = 32'd1;
// wire notRelease;
// wire syn;
localparam waiting = 2'b01;
localparam locking = 2'b10;
localparam releasing = 2'b11;
reg [1 : 0] curr_state;
reg [1 : 0] next_state;
always @(posedge aclk or negedge aresetn) begin
if (!aresetn) begin
// reset
curr_state <= waiting;
end
else begin
curr_state <= next_state;
end
end
always @(curr_state or syn or notRelease) begin
case(curr_state)
waiting:
if (syn) begin
next_state = locking;
end
else begin
next_state = waiting;
end
locking:
if (!notRelease) begin
next_state = releasing;
end
else begin
next_state = locking;
end
releasing:
next_state = waiting;
default:
next_state = 2'bxx;
endcase
end
end
endgenerate
generate if (NUM_SLAVES == 4)
begin: NUM_SLAVES_4
assign notRelease = m00_axis_tvalid | m01_axis_tvalid |
m02_axis_tvalid | m03_axis_tvalid;
assign syn = m00_axis_tvalid & m01_axis_tvalid & m02_axis_tvalid &
m03_axis_tvalid;
assign m00_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m01_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m02_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m03_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign s00_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s01_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s02_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s03_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s00_axis_tdata = 32'd0;
assign s01_axis_tdata = 32'd1;
assign s02_axis_tdata = 32'd2;
assign s03_axis_tdata = 32'd3;
// wire notRelease;
// wire syn;
localparam waiting = 2'b01;
localparam locking = 2'b10;
localparam releasing = 2'b11;
reg [1 : 0] curr_state;
reg [1 : 0] next_state;
always @(posedge aclk or negedge aresetn) begin
if (!aresetn) begin
// reset
curr_state <= waiting;
end
else begin
curr_state <= next_state;
end
end
always @(curr_state or syn or notRelease) begin
case(curr_state)
waiting:
if (syn) begin
next_state = locking;
end
else begin
next_state = waiting;
end
locking:
if (!notRelease) begin
next_state = releasing;
end
else begin
next_state = locking;
end
releasing:
next_state = waiting;
default:
next_state = 2'bxx;
endcase
end
end
endgenerate
generate if (NUM_SLAVES == 5)
begin: NUM_SLAVES_5
assign notRelease = m00_axis_tvalid | m01_axis_tvalid |
m02_axis_tvalid | m03_axis_tvalid |
m04_axis_tvalid;
assign syn = m00_axis_tvalid & m01_axis_tvalid & m02_axis_tvalid &
m03_axis_tvalid & m04_axis_tvalid;
assign m00_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m01_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m02_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m03_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m04_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign s00_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s01_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s02_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s03_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s04_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s00_axis_tdata = 32'd0;
assign s01_axis_tdata = 32'd1;
assign s02_axis_tdata = 32'd2;
assign s03_axis_tdata = 32'd3;
assign s04_axis_tdata = 32'd4;
// wire notRelease;
// wire syn;
localparam waiting = 2'b01;
localparam locking = 2'b10;
localparam releasing = 2'b11;
reg [1 : 0] curr_state;
reg [1 : 0] next_state;
always @(posedge aclk or negedge aresetn) begin
if (!aresetn) begin
// reset
curr_state <= waiting;
end
else begin
curr_state <= next_state;
end
end
always @(curr_state or syn or notRelease) begin
case(curr_state)
waiting:
if (syn) begin
next_state = locking;
end
else begin
next_state = waiting;
end
locking:
if (!notRelease) begin
next_state = releasing;
end
else begin
next_state = locking;
end
releasing:
next_state = waiting;
default:
next_state = 2'bxx;
endcase
end
end
endgenerate
generate if (NUM_SLAVES == 6)
begin: NUM_SLAVES_6
assign notRelease = m00_axis_tvalid | m01_axis_tvalid |
m02_axis_tvalid | m03_axis_tvalid |
m04_axis_tvalid | m05_axis_tvalid;
assign syn = m00_axis_tvalid & m01_axis_tvalid & m02_axis_tvalid &
m03_axis_tvalid & m04_axis_tvalid & m05_axis_tvalid;
assign m00_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m01_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m02_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m03_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m04_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m05_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign s00_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s01_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s02_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s03_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s04_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s05_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s00_axis_tdata = 32'd0;
assign s01_axis_tdata = 32'd1;
assign s02_axis_tdata = 32'd2;
assign s03_axis_tdata = 32'd3;
assign s04_axis_tdata = 32'd4;
assign s05_axis_tdata = 32'd5;
// wire notRelease;
// wire syn;
localparam waiting = 2'b01;
localparam locking = 2'b10;
localparam releasing = 2'b11;
reg [1 : 0] curr_state;
reg [1 : 0] next_state;
always @(posedge aclk or negedge aresetn) begin
if (!aresetn) begin
// reset
curr_state <= waiting;
end
else begin
curr_state <= next_state;
end
end
always @(curr_state or syn or notRelease) begin
case(curr_state)
waiting:
if (syn) begin
next_state = locking;
end
else begin
next_state = waiting;
end
locking:
if (!notRelease) begin
next_state = releasing;
end
else begin
next_state = locking;
end
releasing:
next_state = waiting;
default:
next_state = 2'bxx;
endcase
end
end
endgenerate
generate if (NUM_SLAVES == 7)
begin: NUM_SLAVES_7
assign notRelease = m00_axis_tvalid | m01_axis_tvalid |
m02_axis_tvalid | m03_axis_tvalid |
m04_axis_tvalid | m05_axis_tvalid |
m06_axis_tvalid;
assign syn = m00_axis_tvalid & m01_axis_tvalid & m02_axis_tvalid &
m03_axis_tvalid & m04_axis_tvalid & m05_axis_tvalid &
m06_axis_tvalid;
assign m00_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m01_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m02_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m03_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m04_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m05_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m06_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign s00_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s01_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s02_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s03_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s04_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s05_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s06_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s00_axis_tdata = 32'd0;
assign s01_axis_tdata = 32'd1;
assign s02_axis_tdata = 32'd2;
assign s03_axis_tdata = 32'd3;
assign s04_axis_tdata = 32'd4;
assign s05_axis_tdata = 32'd5;
assign s06_axis_tdata = 32'd6;
// wire notRelease;
// wire syn;
localparam waiting = 2'b01;
localparam locking = 2'b10;
localparam releasing = 2'b11;
reg [1 : 0] curr_state;
reg [1 : 0] next_state;
always @(posedge aclk or negedge aresetn) begin
if (!aresetn) begin
// reset
curr_state <= waiting;
end
else begin
curr_state <= next_state;
end
end
always @(curr_state or syn or notRelease) begin
case(curr_state)
waiting:
if (syn) begin
next_state = locking;
end
else begin
next_state = waiting;
end
locking:
if (!notRelease) begin
next_state = releasing;
end
else begin
next_state = locking;
end
releasing:
next_state = waiting;
default:
next_state = 2'bxx;
endcase
end
end
endgenerate
generate if (NUM_SLAVES == 8)
begin: NUM_SLAVES_8
assign notRelease = m00_axis_tvalid | m01_axis_tvalid |
m02_axis_tvalid | m03_axis_tvalid |
m04_axis_tvalid | m05_axis_tvalid |
m06_axis_tvalid | m07_axis_tvalid;
assign syn = m00_axis_tvalid & m01_axis_tvalid & m02_axis_tvalid &
m03_axis_tvalid & m04_axis_tvalid & m05_axis_tvalid &
m06_axis_tvalid & m07_axis_tvalid;
assign m00_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m01_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m02_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m03_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m04_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m05_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m06_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m07_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign s00_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s01_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s02_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s03_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s04_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s05_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s06_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s07_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s00_axis_tdata = 32'd0;
assign s01_axis_tdata = 32'd1;
assign s02_axis_tdata = 32'd2;
assign s03_axis_tdata = 32'd3;
assign s04_axis_tdata = 32'd4;
assign s05_axis_tdata = 32'd5;
assign s06_axis_tdata = 32'd6;
assign s07_axis_tdata = 32'd7;
// wire notRelease;
// wire syn;
localparam waiting = 2'b01;
localparam locking = 2'b10;
localparam releasing = 2'b11;
reg [1 : 0] curr_state;
reg [1 : 0] next_state;
always @(posedge aclk or negedge aresetn) begin
if (!aresetn) begin
// reset
curr_state <= waiting;
end
else begin
curr_state <= next_state;
end
end
always @(curr_state or syn or notRelease) begin
case(curr_state)
waiting:
if (syn) begin
next_state = locking;
end
else begin
next_state = waiting;
end
locking:
if (!notRelease) begin
next_state = releasing;
end
else begin
next_state = locking;
end
releasing:
next_state = waiting;
default:
next_state = 2'bxx;
endcase
end
end
endgenerate
generate if (NUM_SLAVES == 9)
begin: NUM_SLAVES_9
assign notRelease = m00_axis_tvalid | m01_axis_tvalid |
m02_axis_tvalid | m03_axis_tvalid |
m04_axis_tvalid | m05_axis_tvalid |
m06_axis_tvalid | m07_axis_tvalid |
m08_axis_tvalid;
assign syn = m00_axis_tvalid & m01_axis_tvalid & m02_axis_tvalid &
m03_axis_tvalid & m04_axis_tvalid & m05_axis_tvalid &
m06_axis_tvalid & m07_axis_tvalid & m08_axis_tvalid;
assign m00_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m01_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m02_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m03_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m04_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m05_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m06_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m07_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign m08_axis_tready = (curr_state == locking)?1'b1:1'b0;
assign s00_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s01_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s02_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s03_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s04_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s05_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s06_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s07_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s08_axis_tvalid = (curr_state == releasing)?1'b1:1'b0;
assign s00_axis_tdata = 32'd0;
assign s01_axis_tdata = 32'd1;
assign s02_axis_tdata = 32'd2;
assign s03_axis_tdata = 32'd3;
assign s04_axis_tdata = 32'd4;
assign s05_axis_tdata = 32'd5;
assign s06_axis_tdata = 32'd6;
assign s07_axis_tdata = 32'd7;
assign s08_axis_tdata = 32'd7;
// wire notRelease;
// wire syn;
localparam waiting = 2'b01;
localparam locking = 2'b10;
localparam releasing = 2'b11;
reg [1 : 0] curr_state;
reg [1 : 0] next_state;
always @(posedge aclk or negedge aresetn) begin
if (!aresetn) begin
// reset
curr_state <= waiting;
end
else begin
curr_state <= next_state;
end
end
always @(curr_state or syn or notRelease) begin
case(curr_state)
waiting:
if (syn) begin
next_state = locking;
end
else begin
next_state = waiting;
end
locking:
if (!notRelease) begin
next_state = releasing;
end
else begin
next_state = locking;
end
releasing:
next_state = waiting;
default:
next_state = 2'bxx;
endcase
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__AND2_PP_BLACKBOX_V
/**
* and2: 2-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2_PP_BLACKBOX_V
|
// ============================================================================
// Copyright (c) 2013 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// ============================================================================
// Major Functions: This function is used for configuring si570 register value via
// i2c_bus_controller .
//
//
// ============================================================================
// Design Description:
//
//
//
//
// ===========================================================================
// Revision History :
// ============================================================================
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny Fan :| 11/09/30 :| Initial Version
// ============================================================================
`define REG_NUM 9
module i2c_reg_controller(
iCLK, // system clock 50mhz
iRST_n, // system reset
iENABLE, // i2c reg contorl enable signale , high for enable
iI2C_CONTROLLER_STATE, // i2c controller state , high for i2c controller state not in idel
iI2C_CONTROLLER_CONFIG_DONE,
oController_Ready,
iFREQ_MODE,
oSLAVE_ADDR,
oBYTE_ADDR,
oBYTE_DATA,
oWR_CMD, // write or read commnad for i2c controller , 1 for write command
oStart, // i2c controller start control signal, high for start to send signal
HS_DIV_reg,
N1_reg,
RFREG_reg,
oSI570_ONE_CLK_CONFIG_DONE,
);
//=============================================================================
// PARAMETER declarations
//=============================================================================
parameter write_cmd = 1'b1;
parameter read_cmd = 1'b0;
//===========================================================================
// PORT declarations
//===========================================================================
input iCLK;
input iRST_n;
input iENABLE;
input iI2C_CONTROLLER_STATE;
input iI2C_CONTROLLER_CONFIG_DONE;
input [2:0] iFREQ_MODE;
output [6:0] oSLAVE_ADDR;
output [7:0] oBYTE_ADDR;
output [7:0] oBYTE_DATA ;
output oWR_CMD;
output oStart;
output oSI570_ONE_CLK_CONFIG_DONE;
output [2:0] HS_DIV_reg;
output [6:0] N1_reg;
output [37:0] RFREG_reg;
output oController_Ready;
//=============================================================================
// REG/WIRE declarations
//=============================================================================
wire [2:0] iFREQ_MODE;
reg [2:0] HS_DIV_reg;
reg [6:0] N1_reg;
reg [37:0] RFREG_reg;
////////////// write data ////
//wire [7:0] regx_data = 8'h01; // RECALL
wire [7:0] reg0_data = 8'h10; // free DCO
wire [7:0] reg1_data = {HS_DIV_reg,N1_reg[6:2]};
wire [7:0] reg2_data = {N1_reg[1:0],RFREG_reg[37:32]};
wire [7:0] reg3_data = RFREG_reg[31:24];
wire [7:0] reg4_data = RFREG_reg[23:16];
wire [7:0] reg5_data = RFREG_reg[15:8];
wire [7:0] reg6_data = RFREG_reg[7:0];
wire [7:0] reg7_data = 8'h00; // unfree DCO
wire [7:0] reg8_data = 8'h40; //New Freq
////////////// ctrl addr ////
//wire [7:0] byte_addrx = 8'd135;
wire [7:0] byte_addr0 = 8'd137;
wire [7:0] byte_addr1 = 8'd7;
wire [7:0] byte_addr2 = 8'd8;
wire [7:0] byte_addr3 = 8'd9;
wire [7:0] byte_addr4 = 8'd10;
wire [7:0] byte_addr5 = 8'd11;
wire [7:0] byte_addr6 = 8'd12;
wire [7:0] byte_addr7 = 8'd137;
wire [7:0] byte_addr8 = 8'd135;
wire [6:0] slave_addr = 0;
reg [`REG_NUM/2:0] i2c_reg_state;
wire [6:0] oSLAVE_ADDR = i2c_ctrl_data[23:17];
wire [7:0] oBYTE_ADDR = i2c_ctrl_data[16:9];
wire [7:0] oBYTE_DATA = i2c_ctrl_data[8:1];
wire oWR_CMD = i2c_ctrl_data[0];
wire oStart = access_next_i2c_reg_cmd;
wire i2c_controller_config_done;
reg [23:0] i2c_ctrl_data;// slave_addr(7bit) + byte_addr(8bit) + byte_data(8bit)+ wr_cmd (1bit) = 24bit
wire access_next_i2c_reg_cmd ;
wire access_i2c_reg_start;
wire oSI570_ONE_CLK_CONFIG_DONE;
reg oController_Ready;
//=============================================================================
// Structural coding
//=============================================================================
//=====================================
// Write & Read reg flow control
//=====================================
always@(iFREQ_MODE or HS_DIV_reg or N1_reg or RFREG_reg)
begin
case (iFREQ_MODE)
0: //100Mhz
begin
HS_DIV_reg <= 3'b101;
N1_reg <= 7'b0000101;
RFREG_reg <= 38'h2F40135A9;
end
1: //125Mhz
begin
HS_DIV_reg <= 3'b111;
N1_reg <= 7'b0000011;
RFREG_reg <= 38'h302013B65;
end
2: //156.25Mhz
begin
HS_DIV_reg <= 3'b101;
N1_reg <= 7'b0000011;
RFREG_reg <= 38'h313814290;
end
3: //250Mhz
begin
HS_DIV_reg <= 3'b111;
N1_reg <= 7'b0000001;
RFREG_reg <= 38'h302013B65;
end
4: //312.5Mhz
begin
HS_DIV_reg <= 3'b101;
N1_reg <= 7'b0000001;
RFREG_reg <= 38'h313814290;
end
5: //322.265625Mhz
begin
HS_DIV_reg <= 3'b000;
N1_reg <= 7'b000011;
RFREG_reg <= 38'h2D1E127AF;
end
6: //644.53125Mhz
begin
HS_DIV_reg <= 3'b000;
N1_reg <= 7'b000001;
RFREG_reg <= 38'h2D1E127AF;
end
7: //100Mhz
begin
HS_DIV_reg <= 3'b101;
N1_reg <= 7'b0000101;
RFREG_reg <= 38'h2F40135A9;
end
endcase
end
//=====================================
// State control
//=====================================
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
i2c_reg_state <= 0;
end
else
begin
if (access_i2c_reg_start)
i2c_reg_state <= 1'b1;
else if (i2c_controller_config_done)
i2c_reg_state <= i2c_reg_state+1;
else if (i2c_reg_state == (`REG_NUM+1))
i2c_reg_state <= 0;
end
end
//=====================================
// i2c bus address & data control
//=====================================
always@(i2c_reg_state or i2c_ctrl_data)
begin
i2c_ctrl_data = 0;
case (i2c_reg_state)
0: i2c_ctrl_data = 0; // don't forget to change REG_NUM value
1: i2c_ctrl_data = {slave_addr,byte_addr0,reg0_data,write_cmd};
2: i2c_ctrl_data = {slave_addr,byte_addr1,reg1_data,write_cmd};
3: i2c_ctrl_data = {slave_addr,byte_addr2,reg2_data,write_cmd};
4: i2c_ctrl_data = {slave_addr,byte_addr3,reg3_data,write_cmd};
5: i2c_ctrl_data = {slave_addr,byte_addr4,reg4_data,write_cmd};
6: i2c_ctrl_data = {slave_addr,byte_addr5,reg5_data,write_cmd};
7: i2c_ctrl_data = {slave_addr,byte_addr6,reg6_data,write_cmd};
8: i2c_ctrl_data = {slave_addr,byte_addr7,reg7_data,write_cmd};
9: i2c_ctrl_data = {slave_addr,byte_addr8,reg8_data,write_cmd};
// 10: i2c_ctrl_data = {slave_addr,byte_addr8,reg8_data,write_cmd};
endcase
end
edge_detector u1(
.iCLK(iCLK),
.iRST_n(iRST_n),
.iTrigger_in(iI2C_CONTROLLER_CONFIG_DONE),
.oFalling_edge(i2c_controller_config_done),
.oRising_edge()
);
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
oController_Ready <= 1'b1;
end
else if (i2c_reg_state == `REG_NUM+1)
begin
oController_Ready <= 1'b1;
end
else if (i2c_reg_state >0)
begin
oController_Ready <= 1'b0;
end
end
assign oSI570_ONE_CLK_CONFIG_DONE = ((i2c_reg_state == `REG_NUM) &&(i2c_controller_config_done)) ? 1'b1 : 1'b0;
assign access_next_i2c_reg_cmd = ((iI2C_CONTROLLER_STATE == 1'b0)&&(i2c_reg_state <= `REG_NUM)&&(i2c_reg_state >0)) ? 1'b1 : 1'b0;
assign access_i2c_reg_start = ((iENABLE == 1'b1)&&(iI2C_CONTROLLER_STATE == 1'b0)) ? 1'b1 : 1'b0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2I_FUNCTIONAL_V
`define SKY130_FD_SC_HS__MUX2I_FUNCTIONAL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`include "../u_mux_2_1_inv/sky130_fd_sc_hs__u_mux_2_1_inv.v"
`celldefine
module sky130_fd_sc_hs__mux2i (
VPWR,
VGND,
Y ,
A0 ,
A1 ,
S
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A0 ;
input A1 ;
input S ;
// Local signals
wire u_mux_2_1_inv0_out_Y;
wire u_vpwr_vgnd0_out_Y ;
// Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1_inv u_mux_2_1_inv0 (u_mux_2_1_inv0_out_Y, A0, A1, S );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y , u_mux_2_1_inv0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2I_FUNCTIONAL_V |
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module ultra_slice_memory #(
parameter [1023:0] LOC = "",
parameter [63:0] ALUT_INIT = 64'h00C0FFEE,
parameter [63:0] BLUT_INIT = 64'h00C0FFEE,
parameter [63:0] CLUT_INIT = 64'h00C0FFEE,
parameter [63:0] DLUT_INIT = 64'h00C0FFEE,
parameter [63:0] ELUT_INIT = 64'h00C0FFEE,
parameter [63:0] FLUT_INIT = 64'h00C0FFEE,
parameter [63:0] GLUT_INIT = 64'h00C0FFEE,
parameter [63:0] HLUT_INIT = 64'h00C0FFEE,
parameter [1023:0] A_MODE = "LOGIC",
parameter [1023:0] B_MODE = "LOGIC",
parameter [1023:0] C_MODE = "LOGIC",
parameter [1023:0] D_MODE = "LOGIC",
parameter [1023:0] E_MODE = "LOGIC",
parameter [1023:0] F_MODE = "LOGIC",
parameter [1023:0] G_MODE = "LOGIC",
parameter [1023:0] H_MODE = "LOGIC",
parameter [1023:0] AFF_TYPE = "NONE",
parameter [1023:0] AFF2_TYPE = "NONE",
parameter [1023:0] BFF_TYPE = "NONE",
parameter [1023:0] BFF2_TYPE = "NONE",
parameter [1023:0] CFF_TYPE = "NONE",
parameter [1023:0] CFF2_TYPE = "NONE",
parameter [1023:0] DFF_TYPE = "NONE",
parameter [1023:0] DFF2_TYPE = "NONE",
parameter [1023:0] EFF_TYPE = "NONE",
parameter [1023:0] EFF2_TYPE = "NONE",
parameter [1023:0] FFF_TYPE = "NONE",
parameter [1023:0] FFF2_TYPE = "NONE",
parameter [1023:0] GFF_TYPE = "NONE",
parameter [1023:0] GFF2_TYPE = "NONE",
parameter [1023:0] HFF_TYPE = "NONE",
parameter [1023:0] HFF2_TYPE = "NONE",
parameter [15:0] FF_INIT = 16'h0000,
parameter [1023:0] FFMUXA1 = "BYP",
parameter [1023:0] FFMUXA2 = "BYP",
parameter [1023:0] FFMUXB1 = "BYP",
parameter [1023:0] FFMUXB2 = "BYP",
parameter [1023:0] FFMUXC1 = "BYP",
parameter [1023:0] FFMUXC2 = "BYP",
parameter [1023:0] FFMUXD1 = "BYP",
parameter [1023:0] FFMUXD2 = "BYP",
parameter [1023:0] FFMUXE1 = "BYP",
parameter [1023:0] FFMUXE2 = "BYP",
parameter [1023:0] FFMUXF1 = "BYP",
parameter [1023:0] FFMUXF2 = "BYP",
parameter [1023:0] FFMUXG1 = "BYP",
parameter [1023:0] FFMUXG2 = "BYP",
parameter [1023:0] FFMUXH1 = "BYP",
parameter [1023:0] FFMUXH2 = "BYP",
parameter [1023:0] OUTMUXA = "D5",
parameter [1023:0] OUTMUXB = "D5",
parameter [1023:0] OUTMUXC = "D5",
parameter [1023:0] OUTMUXD = "D5",
parameter [1023:0] OUTMUXE = "D5",
parameter [1023:0] OUTMUXF = "D5",
parameter [1023:0] OUTMUXG = "D5",
parameter [1023:0] OUTMUXH = "D5",
parameter [1023:0] DIMUXA = "DI",
parameter [1023:0] DIMUXB = "DI",
parameter [1023:0] DIMUXC = "DI",
parameter [1023:0] DIMUXD = "DI",
parameter [1023:0] DIMUXE = "DI",
parameter [1023:0] DIMUXF = "DI",
parameter [1023:0] DIMUXG = "DI",
parameter WA6USED = 0, WA7USED = 0, WA8USED = 0, WCLKINV = 0,
parameter [1:0] CLKINV = 2'b00, SRINV = 2'b00
) (
input [7:0] A1, A2, A3, A4, A5, A6, I, X,
input [1:0] CLK, SR,
input WCLK, WE,
input [3:0] CE,
output [7:0] O, Q, Q2, MUX
);
wire [8:0] wa;
assign wa[5:0] = {A6[7], A5[7], A4[7], A3[7], A2[7], A1[7]};
generate
if (WA6USED) assign wa[6] = X[6];
if (WA7USED) assign wa[7] = X[5];
if (WA8USED) assign wa[8] = X[3];
endgenerate
wire [7:0] di0;
wire [7:0] mc31;
assign di0[7] = I[7];
ultra_slice_logic_dimux #(.SEL(DIMUXA)) dimuxa_i (.DI(I[0]), .SIN(mc31[1]), .OUT(di0[0]));
ultra_slice_logic_dimux #(.SEL(DIMUXB)) dimuxb_i (.DI(I[1]), .SIN(mc31[2]), .OUT(di0[1]));
ultra_slice_logic_dimux #(.SEL(DIMUXC)) dimuxc_i (.DI(I[2]), .SIN(mc31[3]), .OUT(di0[2]));
ultra_slice_logic_dimux #(.SEL(DIMUXD)) dimuxd_i (.DI(I[3]), .SIN(mc31[4]), .OUT(di0[3]));
ultra_slice_logic_dimux #(.SEL(DIMUXE)) dimuxe_i (.DI(I[4]), .SIN(mc31[5]), .OUT(di0[4]));
ultra_slice_logic_dimux #(.SEL(DIMUXF)) dimuxf_i (.DI(I[5]), .SIN(mc31[6]), .OUT(di0[5]));
ultra_slice_logic_dimux #(.SEL(DIMUXG)) dimuxg_i (.DI(I[6]), .SIN(mc31[7]), .OUT(di0[6]));
wire [7:0] out5;
ultra_slice_memory_lut #(.LOC(LOC), .BEL5("H5LUT"), .BEL6("H6LUT"), .MODE(H_MODE), .INIT(HLUT_INIT), .CLKINV(WCLKINV), .WA6USED(WA6USED), .WA7USED(WA7USED), .WA8USED(WA8USED), .OUTPUT_MC31(DIMUXG=="SIN")) hlut_i (.CLK(WCLK), .CE(WE), .A({A6[7], A5[7], A4[7], A3[7], A2[7], A1[7]}), .WA(wa), .DI({X[7], di0[7]}), .DO({O[7], out5[7]}), .MC31(mc31[7]));
ultra_slice_memory_lut #(.LOC(LOC), .BEL5("A5LUT"), .BEL6("A6LUT"), .MODE(A_MODE), .INIT(ALUT_INIT), .CLKINV(WCLKINV), .WA6USED(WA6USED), .WA7USED(WA7USED), .WA8USED(WA8USED), .OUTPUT_MC31(1)) alut_i (.CLK(WCLK), .CE(WE), .A({A6[0], A5[0], A4[0], A3[0], A2[0], A1[0]}), .WA(wa), .DI({X[0], di0[0]}), .DO({O[0], out5[0]}), .MC31(mc31[0]));
ultra_slice_memory_lut #(.LOC(LOC), .BEL5("B5LUT"), .BEL6("B6LUT"), .MODE(B_MODE), .INIT(BLUT_INIT), .CLKINV(WCLKINV), .WA6USED(WA6USED), .WA7USED(WA7USED), .WA8USED(WA8USED), .OUTPUT_MC31(DIMUXA=="SIN")) blut_i (.CLK(WCLK), .CE(WE), .A({A6[1], A5[1], A4[1], A3[1], A2[1], A1[1]}), .WA(wa), .DI({X[1], di0[1]}), .DO({O[1], out5[1]}), .MC31(mc31[1]));
ultra_slice_memory_lut #(.LOC(LOC), .BEL5("C5LUT"), .BEL6("C6LUT"), .MODE(C_MODE), .INIT(CLUT_INIT), .CLKINV(WCLKINV), .WA6USED(WA6USED), .WA7USED(WA7USED), .WA8USED(WA8USED), .OUTPUT_MC31(DIMUXB=="SIN")) clut_i (.CLK(WCLK), .CE(WE), .A({A6[2], A5[2], A4[2], A3[2], A2[2], A1[2]}), .WA(wa), .DI({X[2], di0[2]}), .DO({O[2], out5[2]}), .MC31(mc31[2]));
ultra_slice_memory_lut #(.LOC(LOC), .BEL5("D5LUT"), .BEL6("D6LUT"), .MODE(D_MODE), .INIT(DLUT_INIT), .CLKINV(WCLKINV), .WA6USED(WA6USED), .WA7USED(WA7USED), .WA8USED(WA8USED), .OUTPUT_MC31(DIMUXC=="SIN")) dlut_i (.CLK(WCLK), .CE(WE), .A({A6[3], A5[3], A4[3], A3[3], A2[3], A1[3]}), .WA(wa), .DI({X[3], di0[3]}), .DO({O[3], out5[3]}), .MC31(mc31[3]));
ultra_slice_memory_lut #(.LOC(LOC), .BEL5("E5LUT"), .BEL6("E6LUT"), .MODE(E_MODE), .INIT(ELUT_INIT), .CLKINV(WCLKINV), .WA6USED(WA6USED), .WA7USED(WA7USED), .WA8USED(WA8USED), .OUTPUT_MC31(DIMUXD=="SIN")) elut_i (.CLK(WCLK), .CE(WE), .A({A6[4], A5[4], A4[4], A3[4], A2[4], A1[4]}), .WA(wa), .DI({X[4], di0[4]}), .DO({O[4], out5[4]}), .MC31(mc31[4]));
ultra_slice_memory_lut #(.LOC(LOC), .BEL5("F5LUT"), .BEL6("F6LUT"), .MODE(F_MODE), .INIT(FLUT_INIT), .CLKINV(WCLKINV), .WA6USED(WA6USED), .WA7USED(WA7USED), .WA8USED(WA8USED), .OUTPUT_MC31(DIMUXE=="SIN")) flut_i (.CLK(WCLK), .CE(WE), .A({A6[5], A5[5], A4[5], A3[5], A2[5], A1[5]}), .WA(wa), .DI({X[5], di0[5]}), .DO({O[5], out5[5]}), .MC31(mc31[5]));
ultra_slice_memory_lut #(.LOC(LOC), .BEL5("G5LUT"), .BEL6("G6LUT"), .MODE(G_MODE), .INIT(GLUT_INIT), .CLKINV(WCLKINV), .WA6USED(WA6USED), .WA7USED(WA7USED), .WA8USED(WA8USED), .OUTPUT_MC31(DIMUXF=="SIN")) glut_i (.CLK(WCLK), .CE(WE), .A({A6[6], A5[6], A4[6], A3[6], A2[6], A1[6]}), .WA(wa), .DI({X[6], di0[6]}), .DO({O[6], out5[6]}), .MC31(mc31[6]));
wire [7:0] f7f8;
assign f7f8[0] = mc31[0] ^ 1;
/*
(* BEL="F7MUX_AB", LOC=LOC, keep, dont_touch *) MUXF7 f7muxab_i (.I0(O[1]), .I1(O[0]), .S(X[0]), .O(f7f8[1]));
(* BEL="F7MUX_CD", LOC=LOC, keep, dont_touch *) MUXF7 f7muxcd_i (.I0(O[3]), .I1(O[2]), .S(X[2]), .O(f7f8[3]));
(* BEL="F7MUX_EF", LOC=LOC, keep, dont_touch *) MUXF7 f7muxef_i (.I0(O[5]), .I1(O[4]), .S(X[4]), .O(f7f8[5]));
(* BEL="F7MUX_GH", LOC=LOC, keep, dont_touch *) MUXF7 f7muxgh_i (.I0(O[7]), .I1(O[6]), .S(X[6]), .O(f7f8[7]));
(* BEL="F8MUX_BOT", LOC=LOC, keep, dont_touch *) MUXF8 f8muxabcd_i (.I0(f7f8[3]), .I1(f7f8[1]), .S(X[1]), .O(f7f8[2]));
(* BEL="F8MUX_TOP", LOC=LOC, keep, dont_touch *) MUXF8 f8muxefgh_i (.I0(f7f8[7]), .I1(f7f8[5]), .S(X[5]), .O(f7f8[6]));
(* BEL="F9MUX", LOC=LOC, keep, dont_touch *) MUXF9 f9_i (.I0(f7f8[6]), .I1(f7f8[2]), .S(X[3]), .O(f7f8[4]));
*/
assign f7f8[7:1] = O[7:1];
wire [15:0] ffin;
ultra_slice_logic_ffmux #(.SEL(FFMUXA1)) ffmuxa1_i (.XORIN(), .F7F8(f7f8[0]), .D6(O[0]), .D5(out5[0]), .CY(), .BYP(X[0]), .OUT(ffin[0]));
ultra_slice_logic_ffmux #(.SEL(FFMUXA2)) ffmuxa2_i (.XORIN(), .F7F8(f7f8[0]), .D6(O[0]), .D5(out5[0]), .CY(), .BYP(I[0]), .OUT(ffin[1]));
ultra_slice_logic_ffmux #(.SEL(FFMUXB1)) ffmuxb1_i (.XORIN(), .F7F8(f7f8[1]), .D6(O[1]), .D5(out5[1]), .CY(), .BYP(X[1]), .OUT(ffin[2]));
ultra_slice_logic_ffmux #(.SEL(FFMUXB2)) ffmuxb2_i (.XORIN(), .F7F8(f7f8[1]), .D6(O[1]), .D5(out5[1]), .CY(), .BYP(I[1]), .OUT(ffin[3]));
ultra_slice_logic_ffmux #(.SEL(FFMUXC1)) ffmuxc1_i (.XORIN(), .F7F8(f7f8[2]), .D6(O[2]), .D5(out5[2]), .CY(), .BYP(X[2]), .OUT(ffin[4]));
ultra_slice_logic_ffmux #(.SEL(FFMUXC2)) ffmuxc2_i (.XORIN(), .F7F8(f7f8[2]), .D6(O[2]), .D5(out5[2]), .CY(), .BYP(I[2]), .OUT(ffin[5]));
ultra_slice_logic_ffmux #(.SEL(FFMUXD1)) ffmuxd1_i (.XORIN(), .F7F8(f7f8[3]), .D6(O[3]), .D5(out5[3]), .CY(), .BYP(X[3]), .OUT(ffin[6]));
ultra_slice_logic_ffmux #(.SEL(FFMUXD2)) ffmuxd2_i (.XORIN(), .F7F8(f7f8[3]), .D6(O[3]), .D5(out5[3]), .CY(), .BYP(I[3]), .OUT(ffin[7]));
ultra_slice_logic_ffmux #(.SEL(FFMUXE1)) ffmuxe1_i (.XORIN(), .F7F8(f7f8[4]), .D6(O[4]), .D5(out5[4]), .CY(), .BYP(X[4]), .OUT(ffin[8]));
ultra_slice_logic_ffmux #(.SEL(FFMUXE2)) ffmuxe2_i (.XORIN(), .F7F8(f7f8[4]), .D6(O[4]), .D5(out5[4]), .CY(), .BYP(I[4]), .OUT(ffin[9]));
ultra_slice_logic_ffmux #(.SEL(FFMUXF1)) ffmuxf1_i (.XORIN(), .F7F8(f7f8[5]), .D6(O[5]), .D5(out5[5]), .CY(), .BYP(X[5]), .OUT(ffin[10]));
ultra_slice_logic_ffmux #(.SEL(FFMUXF2)) ffmuxf2_i (.XORIN(), .F7F8(f7f8[5]), .D6(O[5]), .D5(out5[5]), .CY(), .BYP(I[5]), .OUT(ffin[11]));
ultra_slice_logic_ffmux #(.SEL(FFMUXG1)) ffmuxg1_i (.XORIN(), .F7F8(f7f8[6]), .D6(O[6]), .D5(out5[6]), .CY(), .BYP(X[6]), .OUT(ffin[12]));
ultra_slice_logic_ffmux #(.SEL(FFMUXG2)) ffmuxg2_i (.XORIN(), .F7F8(f7f8[6]), .D6(O[6]), .D5(out5[6]), .CY(), .BYP(I[6]), .OUT(ffin[13]));
ultra_slice_logic_ffmux #(.SEL(FFMUXH1)) ffmuxh1_i (.XORIN(), .F7F8(f7f8[7]), .D6(O[7]), .D5(out5[7]), .CY(), .BYP(X[7]), .OUT(ffin[14]));
ultra_slice_logic_ffmux #(.SEL(FFMUXH2)) ffmuxh2_i (.XORIN(), .F7F8(f7f8[7]), .D6(O[7]), .D5(out5[7]), .CY(), .BYP(I[7]), .OUT(ffin[15]));
ultra_slice_logic_ffx #(.LOC(LOC), .BEL("AFF"), .TYPE(AFF_TYPE), .CLKINV(CLKINV[0]), .SRINV(SRINV[0]), .INIT(FF_INIT[0])) aff_i (.C(CLK[0]), .SR(SR[0]), .CE(CE[0]), .D(ffin[0]), .Q(Q[0]));
ultra_slice_logic_ffx #(.LOC(LOC), .BEL("AFF2"), .TYPE(AFF2_TYPE), .CLKINV(CLKINV[0]), .SRINV(SRINV[0]), .INIT(FF_INIT[1])) aff2_i (.C(CLK[0]), .SR(SR[0]), .CE(CE[1]), .D(ffin[1]), .Q(Q2[0]));
ultra_slice_logic_ffx #(.LOC(LOC), .BEL("BFF"), .TYPE(BFF_TYPE), .CLKINV(CLKINV[0]), .SRINV(SRINV[0]), .INIT(FF_INIT[2])) bff_i (.C(CLK[0]), .SR(SR[0]), .CE(CE[0]), .D(ffin[2]), .Q(Q[1]));
ultra_slice_logic_ffx #(.LOC(LOC), .BEL("BFF2"), .TYPE(BFF2_TYPE), .CLKINV(CLKINV[0]), .SRINV(SRINV[0]), .INIT(FF_INIT[3])) bff2_i (.C(CLK[0]), .SR(SR[0]), .CE(CE[1]), .D(ffin[3]), .Q(Q2[1]));
ultra_slice_logic_ffx #(.LOC(LOC), .BEL("CFF"), .TYPE(CFF_TYPE), .CLKINV(CLKINV[0]), .SRINV(SRINV[0]), .INIT(FF_INIT[4])) cff_i (.C(CLK[0]), .SR(SR[0]), .CE(CE[0]), .D(ffin[4]), .Q(Q[2]));
ultra_slice_logic_ffx #(.LOC(LOC), .BEL("CFF2"), .TYPE(CFF2_TYPE), .CLKINV(CLKINV[0]), .SRINV(SRINV[0]), .INIT(FF_INIT[5])) cff2_i (.C(CLK[0]), .SR(SR[0]), .CE(CE[1]), .D(ffin[5]), .Q(Q2[2]));
ultra_slice_logic_ffx #(.LOC(LOC), .BEL("DFF"), .TYPE(DFF_TYPE), .CLKINV(CLKINV[0]), .SRINV(SRINV[0]), .INIT(FF_INIT[6])) dff_i (.C(CLK[0]), .SR(SR[0]), .CE(CE[0]), .D(ffin[6]), .Q(Q[3]));
ultra_slice_logic_ffx #(.LOC(LOC), .BEL("DFF2"), .TYPE(DFF2_TYPE), .CLKINV(CLKINV[0]), .SRINV(SRINV[0]), .INIT(FF_INIT[7])) dff2_i (.C(CLK[0]), .SR(SR[0]), .CE(CE[1]), .D(ffin[7]), .Q(Q2[3]));
ultra_slice_logic_ffx #(.LOC(LOC), .BEL("EFF"), .TYPE(EFF_TYPE), .CLKINV(CLKINV[1]), .SRINV(SRINV[1]), .INIT(FF_INIT[8])) eff_i (.C(CLK[1]), .SR(SR[1]), .CE(CE[2]), .D(ffin[8]), .Q(Q[4]));
ultra_slice_logic_ffx #(.LOC(LOC), .BEL("EFF2"), .TYPE(EFF2_TYPE), .CLKINV(CLKINV[1]), .SRINV(SRINV[1]), .INIT(FF_INIT[9])) eff2_i (.C(CLK[1]), .SR(SR[1]), .CE(CE[3]), .D(ffin[9]), .Q(Q2[4]));
ultra_slice_logic_ffx #(.LOC(LOC), .BEL("FFF"), .TYPE(FFF_TYPE), .CLKINV(CLKINV[1]), .SRINV(SRINV[1]), .INIT(FF_INIT[10])) fff_i (.C(CLK[1]), .SR(SR[1]), .CE(CE[2]), .D(ffin[10]), .Q(Q[5]));
ultra_slice_logic_ffx #(.LOC(LOC), .BEL("FFF2"), .TYPE(FFF2_TYPE), .CLKINV(CLKINV[1]), .SRINV(SRINV[1]), .INIT(FF_INIT[11])) fff2_i (.C(CLK[1]), .SR(SR[1]), .CE(CE[3]), .D(ffin[11]), .Q(Q2[5]));
ultra_slice_logic_ffx #(.LOC(LOC), .BEL("GFF"), .TYPE(GFF_TYPE), .CLKINV(CLKINV[1]), .SRINV(SRINV[1]), .INIT(FF_INIT[12])) gff_i (.C(CLK[1]), .SR(SR[1]), .CE(CE[2]), .D(ffin[12]), .Q(Q[6]));
ultra_slice_logic_ffx #(.LOC(LOC), .BEL("GFF2"), .TYPE(GFF2_TYPE), .CLKINV(CLKINV[1]), .SRINV(SRINV[1]), .INIT(FF_INIT[13])) gff2_i (.C(CLK[1]), .SR(SR[1]), .CE(CE[3]), .D(ffin[13]), .Q(Q2[6]));
ultra_slice_logic_ffx #(.LOC(LOC), .BEL("HFF"), .TYPE(HFF_TYPE), .CLKINV(CLKINV[1]), .SRINV(SRINV[1]), .INIT(FF_INIT[14])) hff_i (.C(CLK[1]), .SR(SR[1]), .CE(CE[2]), .D(ffin[14]), .Q(Q[7]));
ultra_slice_logic_ffx #(.LOC(LOC), .BEL("HFF2"), .TYPE(HFF2_TYPE), .CLKINV(CLKINV[1]), .SRINV(SRINV[1]), .INIT(FF_INIT[15])) hff2_i (.C(CLK[1]), .SR(SR[1]), .CE(CE[3]), .D(ffin[15]), .Q(Q2[7]));
ultra_slice_logic_outmux #(.SEL(OUTMUXA)) outmuxa_i (.XORIN(), .F7F8(f7f8[0]), .D6(O[0]), .D5(out5[0]), .CY(), .OUT(MUX[0]));
ultra_slice_logic_outmux #(.SEL(OUTMUXB)) outmuxb_i (.XORIN(), .F7F8(f7f8[1]), .D6(O[1]), .D5(out5[1]), .CY(), .OUT(MUX[1]));
ultra_slice_logic_outmux #(.SEL(OUTMUXC)) outmuxc_i (.XORIN(), .F7F8(f7f8[2]), .D6(O[2]), .D5(out5[2]), .CY(), .OUT(MUX[2]));
ultra_slice_logic_outmux #(.SEL(OUTMUXD)) outmuxd_i (.XORIN(), .F7F8(f7f8[3]), .D6(O[3]), .D5(out5[3]), .CY(), .OUT(MUX[3]));
ultra_slice_logic_outmux #(.SEL(OUTMUXE)) outmuxe_i (.XORIN(), .F7F8(f7f8[4]), .D6(O[4]), .D5(out5[4]), .CY(), .OUT(MUX[4]));
ultra_slice_logic_outmux #(.SEL(OUTMUXF)) outmuxf_i (.XORIN(), .F7F8(f7f8[5]), .D6(O[5]), .D5(out5[5]), .CY(), .OUT(MUX[5]));
ultra_slice_logic_outmux #(.SEL(OUTMUXG)) outmuxg_i (.XORIN(), .F7F8(f7f8[6]), .D6(O[6]), .D5(out5[6]), .CY(), .OUT(MUX[6]));
ultra_slice_logic_outmux #(.SEL(OUTMUXH)) outmuxh_i (.XORIN(), .F7F8(f7f8[7]), .D6(O[7]), .D5(out5[7]), .CY(), .OUT(MUX[7]));
endmodule
module ultra_slice_logic_ffmux #(
parameter [1023:0] SEL = "BYP"
) (
input XORIN, F7F8, D6, D5, CY, BYP,
output OUT
);
generate
case(SEL)
"XORIN": assign OUT = XORIN;
"F7F8": assign OUT = F7F8;
"D6": assign OUT = D6;
"D5": assign OUT = D5;
"CY": assign OUT = CY;
"BYP": assign OUT = BYP;
endcase
endgenerate
endmodule
module ultra_slice_logic_ffx #(
parameter [1023:0] LOC = "",
parameter [1023:0] BEL = "",
parameter [1023:0] TYPE = "",
parameter CLKINV = 1'b0,
parameter SRINV = 1'b0,
parameter INIT = 1'b0
) (
input C, CE, SR, D,
output Q
);
generate
case (TYPE)
"FDPE": (* LOC=LOC, BEL=BEL, keep, dont_touch *) FDPE #(.IS_C_INVERTED(CLKINV), .IS_PRE_INVERTED(SRINV), .INIT(INIT)) ff_i (.C(C), .CE(CE), .PRE(SR), .D(D), .Q(Q));
"FDCE": (* LOC=LOC, BEL=BEL, keep, dont_touch *) FDCE #(.IS_C_INVERTED(CLKINV), .IS_CLR_INVERTED(SRINV), .INIT(INIT)) ff_i (.C(C), .CE(CE), .CLR(SR), .D(D), .Q(Q));
"FDSE": (* LOC=LOC, BEL=BEL, keep, dont_touch *) FDSE #(.IS_C_INVERTED(CLKINV), .IS_S_INVERTED(SRINV), .INIT(INIT)) ff_i (.C(C), .CE(CE), .S(SR), .D(D), .Q(Q));
"FDRE": (* LOC=LOC, BEL=BEL, keep, dont_touch *) FDRE #(.IS_C_INVERTED(CLKINV), .IS_R_INVERTED(SRINV), .INIT(INIT)) ff_i (.C(C), .CE(CE), .R(SR), .D(D), .Q(Q));
"LDPE": (* LOC=LOC, BEL=BEL, keep, dont_touch *) LDPE #(.IS_G_INVERTED(CLKINV), .IS_PRE_INVERTED(SRINV), .INIT(INIT)) ff_i (.G(C), .GE(CE), .PRE(SR), .D(D), .Q(Q));
"LDCE": (* LOC=LOC, BEL=BEL, keep, dont_touch *) LDCE #(.IS_G_INVERTED(CLKINV), .IS_CLR_INVERTED(SRINV), .INIT(INIT)) ff_i (.G(C), .GE(CE), .CLR(SR), .D(D), .Q(Q));
"NONE": assign Q = INIT;
endcase
endgenerate
endmodule
module ultra_slice_logic_outmux #(
parameter SEL = "D5"
) (
input XORIN, F7F8, D6, D5, CY,
output OUT
);
generate
case(SEL)
"XORIN": assign OUT = XORIN;
"F7F8": assign OUT = F7F8;
"D6": assign OUT = D6;
"D5": assign OUT = D5;
"CY": assign OUT = CY;
endcase
endgenerate
endmodule
module ultra_slice_logic_dimux #(
parameter [1023:0] SEL = "DI"
) (
input DI, SIN,
output OUT
);
generate
case(SEL)
"DI": assign OUT = DI;
"SIN": assign OUT = SIN;
endcase
endgenerate
endmodule
module ultra_slice_memory_lut #(
parameter [1023:0] LOC = "",
parameter [1023:0] BEL5 = "",
parameter [1023:0] BEL6 = "",
parameter [1023:0] MODE = "LOGIC",
parameter [63:0] INIT = 64'h0,
parameter CLKINV = 0, WA6USED = 0, WA7USED = 0, WA8USED = 0, OUTPUT_MC31 = 0
) (
input CLK, CE,
input [5:0] A,
input [8:0] WA,
input [1:0] DI,
output [1:0] DO,
output MC31
);
generate
if (MODE == "LOGIC") begin
(* keep, dont_touch *) LUT5 #(.INIT(INIT[63:32])) lut6 (.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]), .I4(A[4]), .O(DO[1]));
(* keep, dont_touch *) LUT5 #(.INIT(INIT[31:0])) lut5 (.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]), .I4(A[4]), .O(DO[0]));
assign MC31 = DO[1];
end else if (MODE == "SRL16") begin
(* keep, dont_touch *) SRL16E #(.INIT(INIT[63:32]), .IS_CLK_INVERTED(CLKINV)) srl6 (.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .D(DI[1]), .CLK(CLK), .CE(CE), .Q(DO[1]));
(* keep, dont_touch *) SRL16E #(.INIT(INIT[31:0]), .IS_CLK_INVERTED(CLKINV)) srl5 (.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .D(DI[0]), .CLK(CLK), .CE(CE), .Q(DO[0]));
assign MC31 = DO[1];
end else if (MODE == "SRL32") begin
if (OUTPUT_MC31) begin
(* keep, dont_touch *) SRLC32E #(.INIT(INIT[31:0]), .IS_CLK_INVERTED(CLKINV)) srl6(.A(5'b11111), .D(DI[0]), .CLK(CLK), .CE(CE), .Q(DO[1]), .Q31(MC31));
end else begin
(* keep, dont_touch *) SRLC32E #(.INIT(INIT[31:0]), .IS_CLK_INVERTED(CLKINV)) srl6(.A(5'b11111), .D(DI[0]), .CLK(CLK), .CE(CE), .Q(DO[1]));
end
assign DO[0] = DO[1];
end else if (MODE == "RAMD64") begin
if (WA6USED && WA7USED) begin
(* keep, dont_touch *) RAMD64E #(.INIT(INIT), .IS_CLK_INVERTED(CLKINV)) ram_i (
.RADR0(A[0]), .RADR1(A[1]), .RADR2(A[2]), .RADR3(A[3]), .RADR4(A[4]), .RADR5(A[5]),
.WADR0(WA[0]), .WADR1(WA[1]), .WADR2(WA[2]), .WADR3(WA[3]), .WADR4(WA[4]), .WADR5(WA[5]), .WADR6(WA[6]), .WADR7(WA[7]),
.CLK(CLK), .WE(CE),
.I(DI[0]), .O(DO[1])
);
end else if (WA6USED) begin
(* keep, dont_touch *) RAMD64E #(.INIT(INIT), .IS_CLK_INVERTED(CLKINV)) ram_i (
.RADR0(A[0]), .RADR1(A[1]), .RADR2(A[2]), .RADR3(A[3]), .RADR4(A[4]), .RADR5(A[5]),
.WADR0(WA[0]), .WADR1(WA[1]), .WADR2(WA[2]), .WADR3(WA[3]), .WADR4(WA[4]), .WADR5(WA[5]), .WADR6(WA[6]),
.CLK(CLK), .WE(CE),
.I(DI[0]), .O(DO[1])
);
end else begin
(* keep, dont_touch *) RAMD64E #(.INIT(INIT), .IS_CLK_INVERTED(CLKINV)) ram_i (
.RADR0(A[0]), .RADR1(A[1]), .RADR2(A[2]), .RADR3(A[3]), .RADR4(A[4]), .RADR5(A[5]),
.WADR0(WA[0]), .WADR1(WA[1]), .WADR2(WA[2]), .WADR3(WA[3]), .WADR4(WA[4]), .WADR5(WA[5]),
.CLK(CLK), .WE(CE),
.I(DI[0]), .O(DO[1])
);
end
assign DO[0] = DO[1];
assign MC31 = DO[1];
end else if (MODE == "RAMS64") begin
if (WA6USED && WA7USED && WA8USED) begin
(* keep, dont_touch *) RAMS64E1 #(.INIT(INIT), .IS_CLK_INVERTED(CLKINV)) ram_i (
.ADR0(WA[0]), .ADR1(WA[1]), .ADR2(WA[2]), .ADR3(WA[3]), .ADR4(WA[4]), .ADR5(WA[5]),
.WADR6(WA[6]), .WADR7(WA[7]), .WADR8(WA[8]),
.CLK(CLK), .WE(CE),
.I(DI[0]), .O(DO[1])
);
end else if (WA6USED && WA7USED) begin
(* keep, dont_touch *) RAMS64E1 #(.INIT(INIT), .IS_CLK_INVERTED(CLKINV)) ram_i (
.ADR0(WA[0]), .ADR1(WA[1]), .ADR2(WA[2]), .ADR3(WA[3]), .ADR4(WA[4]), .ADR5(WA[5]),
.WADR6(WA[6]), .WADR7(WA[7]),
.CLK(CLK), .WE(CE),
.I(DI[0]), .O(DO[1])
);
end else if (WA6USED) begin
(* keep, dont_touch *) RAMS64E1 #(.INIT(INIT), .IS_CLK_INVERTED(CLKINV)) ram_i (
.ADR0(WA[0]), .ADR1(WA[1]), .ADR2(WA[2]), .ADR3(WA[3]), .ADR4(WA[4]), .ADR5(WA[5]),
.WADR6(WA[6]),
.CLK(CLK), .WE(CE),
.I(DI[0]), .O(DO[1])
);
end else begin
(* keep, dont_touch *) RAMS64E1 #(.INIT(INIT), .IS_CLK_INVERTED(CLKINV)) ram_i (
.ADR0(WA[0]), .ADR1(WA[1]), .ADR2(WA[2]), .ADR3(WA[3]), .ADR4(WA[4]), .ADR5(WA[5]),
.CLK(CLK), .WE(CE),
.I(DI[0]), .O(DO[1])
);
end
assign DO[0] = DO[1];
assign MC31 = DO[1];
end else if (MODE == "RAMS32") begin
(* keep, dont_touch *) RAMS32 #(.INIT(INIT[63:32]), .IS_CLK_INVERTED(CLKINV)) ram1_i (
.ADR0(WA[0]), .ADR1(WA[1]), .ADR2(WA[2]), .ADR3(WA[3]), .ADR4(WA[4]),
.CLK(CLK), .WE(CE),
.I(DI[1]), .O(DO[1])
);
(* keep, dont_touch *) RAMS32 #(.INIT(INIT[31:0]), .IS_CLK_INVERTED(CLKINV)) ram0_i (
.ADR0(WA[0]), .ADR1(WA[1]), .ADR2(WA[2]), .ADR3(WA[3]), .ADR4(WA[4]),
.CLK(CLK), .WE(CE),
.I(DI[0]), .O(DO[0])
);
assign MC31 = DO[1];
end else if (MODE == "RAMD32") begin
(* keep, dont_touch *) RAMD32 #(.INIT(INIT[63:32]), .IS_CLK_INVERTED(CLKINV)) ram1_i (
.WADR0(WA[0]), .WADR1(WA[1]), .WADR2(WA[2]), .WADR3(WA[3]), .WADR4(WA[4]),
.RADR0(A[0]), .RADR1(A[1]), .RADR2(A[2]), .RADR3(A[3]), .RADR4(A[4]),
.CLK(CLK), .WE(CE),
.I(DI[1]), .O(DO[1])
);
(* keep, dont_touch *) RAMD32 #(.INIT(INIT[31:0]), .IS_CLK_INVERTED(CLKINV)) ram0_i (
.WADR0(WA[0]), .WADR1(WA[1]), .WADR2(WA[2]), .WADR3(WA[3]), .WADR4(WA[4]),
.RADR0(A[0]), .RADR1(A[1]), .RADR2(A[2]), .RADR3(A[3]), .RADR4(A[4]),
.CLK(CLK), .WE(CE),
.I(DI[0]), .O(DO[0])
);
assign MC31 = DO[1];
end else begin
$error("unsupported mode");
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3_TB_V
`define SKY130_FD_SC_MS__AND3_TB_V
/**
* and3: 3-input AND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ms__and3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: Lisa Liu
//
// Create Date: 06/30/2014 03:42:37 PM
// Design Name:
// Module Name: rx_isolation
// Project Name:
// Target Devices:
// Tool Versions:
// Description: read back presure signal (tready) from 8K byte FIFO and drop packets from xgmac whenever the empty space in the FIFO is less than 5K.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rx_isolation #(
FIFO_FULL_THRESHOLD = 11'd256
)
(
input [63:0] axi_str_tdata_from_xgmac,
input [7:0] axi_str_tkeep_from_xgmac,
input axi_str_tvalid_from_xgmac,
input axi_str_tlast_from_xgmac,
//input axi_str_tuser_from_xgmac,
input axi_str_tready_from_fifo,
output [63:0] axi_str_tdata_to_fifo,
output [7:0] axi_str_tkeep_to_fifo,
output axi_str_tvalid_to_fifo,
output axi_str_tlast_to_fifo,
input user_clk,
input reset
);
reg [63:0] axi_str_tdata_from_xgmac_r;
reg [7:0] axi_str_tkeep_from_xgmac_r;
reg axi_str_tvalid_from_xgmac_r;
reg axi_str_tlast_from_xgmac_r;
wire[10:0] fifo_occupacy_count;
wire s_axis_tvalid;
reg [10:0] wcount_r; //number of words in the current xgmac packet
wire fifo_has_space;
localparam IDLE = 1'd0,
STREAMING = 1'd1;
reg curr_state_r;
rx_fifo rx_fifo_inst (
.s_aclk(user_clk), // input wire s_aclk
.s_aresetn(~reset), // input wire s_aresetn
.s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid
.s_axis_tready(), // output wire s_axis_tready
.s_axis_tdata(axi_str_tdata_from_xgmac_r), // input wire [63 : 0] s_axis_tdata
.s_axis_tkeep(axi_str_tkeep_from_xgmac_r), // input wire [7 : 0] s_axis_tkeep
.s_axis_tlast(axi_str_tlast_from_xgmac_r), // input wire s_axis_tlast
.m_axis_tvalid(axi_str_tvalid_to_fifo), // output wire m_axis_tvalid
.m_axis_tready(axi_str_tready_from_fifo), // input wire m_axis_tready
.m_axis_tdata(axi_str_tdata_to_fifo), // output wire [63 : 0] m_axis_tdata
.m_axis_tkeep(axi_str_tkeep_to_fifo), // output wire [7 : 0] m_axis_tkeep
.m_axis_tlast(axi_str_tlast_to_fifo), // output wire m_axis_tlast
.axis_data_count(fifo_occupacy_count) // output wire [10 : 0] axis_data_count
);
assign fifo_has_space = (fifo_occupacy_count < FIFO_FULL_THRESHOLD);
assign s_axis_tvalid = axi_str_tvalid_from_xgmac_r & (((wcount_r == 0) & fifo_has_space) | (curr_state_r == STREAMING));
always @(posedge user_clk) begin
axi_str_tdata_from_xgmac_r <= axi_str_tdata_from_xgmac;
axi_str_tkeep_from_xgmac_r <= axi_str_tkeep_from_xgmac;
axi_str_tvalid_from_xgmac_r <= axi_str_tvalid_from_xgmac;
axi_str_tlast_from_xgmac_r <= axi_str_tlast_from_xgmac;
end
always @(posedge user_clk)
if (reset)
wcount_r <= 0;
else if (axi_str_tvalid_from_xgmac_r & ~axi_str_tlast_from_xgmac_r)
wcount_r <= wcount_r + 1;
else if (axi_str_tvalid_from_xgmac_r & axi_str_tlast_from_xgmac_r)
wcount_r <= 0;
always @(posedge user_clk)
if (reset)
curr_state_r <= IDLE;
else
case (curr_state_r)
IDLE: if ((wcount_r == 0) & fifo_has_space & axi_str_tvalid_from_xgmac_r)
curr_state_r <= STREAMING;
STREAMING: if (axi_str_tvalid_from_xgmac_r & axi_str_tlast_from_xgmac_r)
curr_state_r <= IDLE;
endcase
/* always @(posedge user_clk) begin
data [63:0] <= axi_str_tdata_from_xgmac_r;
data [71:64] <= axi_str_tkeep_from_xgmac_r;
data[72] <= axi_str_tvalid_from_xgmac_r;
data[73] <= axi_str_tlast_from_xgmac_r;
data[74] <= axi_str_tready_from_fifo;
data[138:75] <= axi_str_tdata_to_fifo;
data[146:139] <= axi_str_tkeep_to_fifo;
data[147] <= axi_str_tvalid_to_fifo;
data[148] <= axi_str_tlast_to_fifo;
data[159:149] <= wcount_r;
data[160] <= curr_state_r;
data[171:161] <= fifo_occupacy_count;
trig0[10:0] <= wcount_r;
trig0[11] <= axi_str_tvalid_to_fifo;
trig0[12] <= axi_str_tready_from_fifo;
end*/
endmodule |
module serial_wb_wbmaster(
// This assumes that the wishbone port and the MCU operates on the
// same clock
input wire clk_i,
input wire rst_i,
// Simple MCU port
input wire [7:0] data_i,
output reg [7:0] data_o,
input wire writestrobe_i,
input wire [7:0] address_i,
// Wishbone master interface wbm_*:
input wire [31:0] wbm_dat_i,
output reg [31:0] wbm_dat_o,
input wire wbm_ack_i,
output reg [31:0] wbm_adr_o,
output reg wbm_cyc_o,
input wire wbm_err_i,
output wire wbm_lock_o,
input wire wbm_rty_i,
output reg [3:0] wbm_sel_o,
output reg wbm_stb_o,
output reg wbm_we_o
);
// Status register on control port 8
reg [7:0] statusreg_r;
reg [7:0] next_statusreg;
// data read from wishbone bus
reg [31:0] read_reg_r;
reg [31:0] next_read_reg;
// Control Port for Wishbone Master
// 0-3 WB address
// 4-7 WB data
// 8
// Bit 0: Start wishbone transaction (bit is 1 until transaction is terminated) Write a 0 to abort transaction
// Bit 1: transaction terminated by err_i
// Bit 2: transaction terminated by rty_i
// Bit 3: read/write: 1 is write, 0 is read transaction
// 4-7: sel signals
assign wbm_lock_o = 0; // This core does not use the lock interface
// This block handles the address port of the wishbone interface
always @(posedge clk_i) begin
if(rst_i == 1'b1) begin
wbm_adr_o <= 32'b0;
end else if(writestrobe_i) begin
case(address_i[3:0])
4'd0: wbm_adr_o[7:0] <= data_i;
4'd1: wbm_adr_o[15:8] <= data_i;
4'd2: wbm_adr_o[23:16] <= data_i;
4'd3: wbm_adr_o[31:24] <= data_i;
endcase // case(address_i[3:0])
end
end
always @(posedge clk_i) begin
if(rst_i == 1'b1) begin
wbm_dat_o <= 32'b0;
end else if(writestrobe_i) begin
case(address_i[3:0])
4'd4: wbm_dat_o[7:0] <= data_i;
4'd5: wbm_dat_o[15:8] <= data_i;
4'd6: wbm_dat_o[23:16] <= data_i;
4'd7: wbm_dat_o[31:24] <= data_i;
endcase // case(address_i[3:0])
end
end
////////////////////////////////////////////////////////////////////////
//
// Wishbone transaction state machine
//
////////////////////////////////////////////////////////////////////////
reg [1:0] next_wb_state;
reg [1:0] wb_state_r;
`define WB_STATE_IDLE 2'b00
`define WB_STATE_READ 2'b01
`define WB_STATE_WRITE 2'b10
// true if the slave responds with a termination cycle
wire cycle_terminated;
assign cycle_terminated = wbm_ack_i || wbm_err_i || wbm_rty_i;
wire ctrl_write;
assign ctrl_write = (address_i[3:0] == 4'd8) && writestrobe_i;
always @(address_i or statusreg_r) begin
case(address_i[3:0])
4'd4: data_o = read_reg_r[7:0];
4'd5: data_o = read_reg_r[15:8];
4'd6: data_o = read_reg_r[23:16];
4'd7: data_o = read_reg_r[31:24];
default: data_o = statusreg_r;
endcase // case(address_i)
end
// State machine for the wishbone master
always @(ctrl_write or cycle_terminated
or data_i or statusreg_r or wb_state_r
or wbm_err_i or wbm_rty_i) begin
next_wb_state = wb_state_r;
// Default value for these:
wbm_cyc_o = (next_wb_state != `WB_STATE_IDLE);
wbm_stb_o = (next_wb_state != `WB_STATE_IDLE);
next_statusreg = statusreg_r;
wbm_we_o = statusreg_r[3];
wbm_sel_o = statusreg_r[7:4];
next_read_reg = read_reg_r;
if(ctrl_write && !data_i[0]) begin
// Abort transaction immediately
next_wb_state = `WB_STATE_IDLE;
wbm_cyc_o = 0;
wbm_stb_o = 0;
next_statusreg = {data_i[7:3],3'b000};
end else if(ctrl_write && (wb_state_r == `WB_STATE_IDLE) && data_i[0]) begin
// Start a transaction
wbm_cyc_o = 1;
wbm_stb_o = 1;
next_statusreg = {data_i[7:3],3'b001};
wbm_we_o = data_i[3];
wbm_sel_o = data_i[7:4];
if(cycle_terminated) begin
// Transaction terminated on first cycle
next_wb_state = `WB_STATE_IDLE;
next_statusreg[0] = 0;
next_statusreg[1] = wbm_err_i;
next_statusreg[2] = wbm_rty_i;
if(!data_i[3]) begin
next_read_reg = wbm_dat_i;
end
end else begin
// Wait for the transaction to end
if(data_i[3]) begin
next_wb_state = `WB_STATE_WRITE;
end else begin
next_wb_state = `WB_STATE_READ;
end
end // else: !if(cycle_terminated)
end else if(cycle_terminated && (wb_state_r != `WB_STATE_IDLE)) begin
// Terminate this cycle
next_wb_state = `WB_STATE_IDLE;
next_statusreg[0] = 0;
next_statusreg[1] = wbm_err_i;
next_statusreg[2] = wbm_rty_i;
if(wb_state_r == `WB_STATE_READ) begin
next_read_reg = wbm_dat_i;
end
end
end // always @ (ctrl_write or cycle_terminated...
always @(posedge clk_i) begin
if(rst_i == 1'b1) begin
wb_state_r <= `WB_STATE_IDLE;
statusreg_r <= 0;
read_reg_r <= 0;
end else begin
wb_state_r <= next_wb_state;
statusreg_r <= next_statusreg;
read_reg_r <= next_read_reg;
end
end // always @ (posedge clk_i)
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
// Date : Sat Jan 21 14:55:25 2017
// Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mul17_16_stub.v
// Design : mul17_16
// Purpose : Stub declaration of top-level module interface
// Device : xcku035-fbva676-3-e
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mult_gen_v12_0_12,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(CLK, A, B, P)
/* synthesis syn_black_box black_box_pad_pin="CLK,A[16:0],B[15:0],P[8:0]" */;
input CLK;
input [16:0]A;
input [15:0]B;
output [8:0]P;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:09:44 06/18/2014
// Design Name: washing_machine
// Module Name: F:/ISE/work/final_exp/washing_machine/washing_machine_test.v
// Project Name: washing_machine
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: washing_machine
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module washing_machine_test;
// Inputs
reg clk;
reg power_button;
reg pause_button;
reg mode_button;
reg stage_button;
// Outputs
wire power_led;
wire pause_led;
wire [2:0] wash_led;
wire [3:0] stage_led;
wire [4:0] time_led;
wire warning_led;
parameter PERIOD = 10;
// Instantiate the Unit Under Test (UUT)
washing_machine uut (
.clk(clk),
.power_button(power_button),
.pause_button(pause_button),
.mode_button(mode_button),
.stage_button(stage_button),
.power_led(power_led),
.pause_led(pause_led),
.wash_led(wash_led),
.stage_led(stage_led),
.time_led(time_led),
.warning_led(warning_led)
);
always begin
clk = 1;
#(PERIOD/2);
clk = 0;
#(PERIOD/2);
end
initial begin
// Initialize Inputs
clk = 0;
power_button = 0;
pause_button = 0;
mode_button = 0;
stage_button = 0;
// Wait 100 ns for global reset to finish
#20;
power_button = 1;
#3;
power_button = 0;
#10;
pause_button = 1;
#3;
pause_button = 0;
#40;
pause_button = 1;
#3;
pause_button = 0;
//#3;
//mode_button = 1;
//#3;
//mode_button = 0;
#30;
pause_button = 1;
#3;
pause_button = 0;
// Add stimulus here
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: reorder_queue_input.v
// Version: 1.00
// Verilog Standard: Verilog-2005
// Description: Input stage to the reorder-queue.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`timescale 1ns / 1ps
module reorder_queue_input
#(parameter C_PCI_DATA_WIDTH = 9'd128,
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_TAG_DW_COUNT_WIDTH = 8,// Width of max count DWs per packet
parameter C_DATA_ADDR_STRIDE_WIDTH = 5,// Width of max num stored data addr positions per tag
parameter C_DATA_ADDR_WIDTH = 10, // Width of stored data address
// Local parameters
parameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,
parameter C_PCI_DATA_WORD_WIDTH = clog2s(C_PCI_DATA_WORD),
parameter C_PCI_DATA_COUNT_WIDTH = clog2s(C_PCI_DATA_WORD+1),
parameter C_NUM_TAGS = 2**C_TAG_WIDTH)
(input CLK, // Clock
input RST, // Synchronous reset
input VALID, // Valid input packet
input [C_PCI_DATA_WIDTH-1:0] DATA, // Input packet payload data enable
input [(C_PCI_DATA_WIDTH/32)-1:0] DATA_EN, // Input packet payload data enable
input DATA_START_FLAG, // Input packet payload
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] DATA_START_OFFSET, // Input packet payload data enable count
input DATA_END_FLAG, // Input packet payload
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] DATA_END_OFFSET, // Input packet payload data enable count
input DONE, // Input packet done
input ERR, // Input packet has error
input [C_TAG_WIDTH-1:0] TAG, // Input packet tag (external tag)
output [C_NUM_TAGS-1:0] TAG_FINISH, // Bitmap of tags to finish
input [C_NUM_TAGS-1:0] TAG_CLEAR, // Bitmap of tags to clear
output [(C_DATA_ADDR_WIDTH*C_PCI_DATA_WORD)-1:0] STORED_DATA_ADDR, // Address of stored packet data for RAMs
output [C_PCI_DATA_WIDTH-1:0] STORED_DATA, // Stored packet data for RAMs
output [C_PCI_DATA_WORD-1:0] STORED_DATA_EN, // Stored packet data enable for RAMs
output PKT_VALID, // Valid flag for packet data
output [C_TAG_WIDTH-1:0] PKT_TAG, // Tag for stored packet data
output [C_TAG_DW_COUNT_WIDTH-1:0] PKT_WORDS, // Total count of stored packet payload in DWs
output PKT_WORDS_LTE1, // True if total count of stored packet payload is <= 4 DWs
output PKT_WORDS_LTE2, // True if total count of stored packet payload is <= 8 DWs
output PKT_DONE, // Stored packet done flag
output PKT_ERR); // Stored packet error flag
wire [C_PCI_DATA_COUNT_WIDTH-1:0] wDECount;
wire [C_PCI_DATA_WORD-1:0] wDE;
wire [C_PCI_DATA_WIDTH-1:0] wData;
wire [C_PCI_DATA_WORD-1:0] wStartMask;
wire [C_PCI_DATA_WORD-1:0] wEndMask;
reg [5:0] rValid=0;
reg [(C_PCI_DATA_WIDTH*5)-1:0] rData=0;
reg [(C_PCI_DATA_WORD*3)-1:0] rDE=0;
reg [(C_PCI_DATA_COUNT_WIDTH*2)-1:0] rDECount=0;
reg [5:0] rDone=0;
reg [5:0] rErr=0;
reg [(C_TAG_WIDTH*6)-1:0] rTag=0;
reg [C_PCI_DATA_WORD-1:0] rDEShift=0;
reg [(C_PCI_DATA_WORD*2)-1:0] rDEShifted=0;
reg rCountValid=0;
reg [C_NUM_TAGS-1:0] rCountRst=0;
reg [C_NUM_TAGS-1:0] rValidCount=0;
reg rUseCurrCount=0;
reg rUsePrevCount=0;
reg [C_TAG_DW_COUNT_WIDTH-1:0] rPrevCount=0;
reg [C_TAG_DW_COUNT_WIDTH-1:0] rCount=0;
wire [C_TAG_DW_COUNT_WIDTH-1:0] wCount;
wire [C_TAG_DW_COUNT_WIDTH-1:0] wCountClr = wCount & {C_TAG_DW_COUNT_WIDTH{rCountValid}};
reg [(C_TAG_DW_COUNT_WIDTH*3)-1:0] rWords=0;
reg [C_PCI_DATA_WORD_WIDTH-1:0] rShift=0;
reg [C_PCI_DATA_WORD_WIDTH-1:0] rShifted=0;
reg rPosValid=0;
reg [C_NUM_TAGS-1:0] rPosRst=0;
reg [C_NUM_TAGS-1:0] rValidPos=0;
reg rUseCurrPos=0;
reg rUsePrevPos=0;
reg [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] rPrevPos=0;
reg [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] rPosNow=0;
reg [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] rPos=0;
wire [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] wPos;
wire [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] wPosClr = wPos & {C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD{rPosValid}};
reg [(C_DATA_ADDR_WIDTH*C_PCI_DATA_WORD)-1:0] rAddr=0;
reg [(C_PCI_DATA_WORD_WIDTH+5)-1:0] rShiftUp=0;
reg [(C_PCI_DATA_WORD_WIDTH+5)-1:0] rShiftDown=0;
reg [C_DATA_ADDR_WIDTH-1:0] rBaseAddr=0;
reg [C_PCI_DATA_WIDTH-1:0] rDataShifted=0;
reg rLTE1Pkt=0;
reg rLTE2Pkt=0;
reg [C_NUM_TAGS-1:0] rFinish=0;
wire [31:0] wZero=32'd0;
integer i;
assign wDE = DATA_EN >> (DATA_START_FLAG ? DATA_START_OFFSET : 0);/* TODO: Could move this to the RX Engine*/
assign wData = DATA >> (DATA_START_FLAG ? {DATA_START_OFFSET,5'b0} : 0);
generate
if(C_PCI_DATA_WIDTH == 32) begin
assign wDECount = VALID ? 1 : 0;
end
if(C_PCI_DATA_WIDTH == 64) begin
assign wDECount = VALID ? DATA_EN[1] + DATA_EN[0] : 0;
end
if(C_PCI_DATA_WIDTH == 128) begin
assign wDECount = VALID ? DATA_EN[3] + DATA_EN[2] + DATA_EN[1] + DATA_EN[0] : 0;
end
if(C_PCI_DATA_WIDTH == 256) begin
assign wDECount = VALID ? DATA_EN[7] + DATA_EN[6] + DATA_EN[5] + DATA_EN[4] +
DATA_EN[3] + DATA_EN[2] + DATA_EN[1] + DATA_EN[0] : 0;
end
endgenerate
assign TAG_FINISH = rFinish;
assign STORED_DATA_ADDR = rAddr;
assign STORED_DATA = rDataShifted;
assign STORED_DATA_EN = rDEShifted[1*C_PCI_DATA_WORD +:C_PCI_DATA_WORD];
assign PKT_VALID = rValid[5];
assign PKT_TAG = rTag[5*C_TAG_WIDTH +:C_TAG_WIDTH];
assign PKT_WORDS = rWords[2*C_TAG_DW_COUNT_WIDTH +:C_TAG_DW_COUNT_WIDTH];
assign PKT_WORDS_LTE1 = rLTE1Pkt;
assign PKT_WORDS_LTE2 = rLTE2Pkt;
assign PKT_DONE = rDone[5];
assign PKT_ERR = rErr[5];
// Pipeline the input and intermediate data
always @ (posedge CLK) begin
if (RST) begin
rValid <= #1 0;
rTag <= #1 0;
end
else begin
rValid <= #1 (rValid<<1) | VALID;
rTag <= #1 (rTag<<C_TAG_WIDTH) | TAG;
end
rData <= #1 (rData<<C_PCI_DATA_WIDTH) | wData;
rDE <= #1 (rDE<<C_PCI_DATA_WORD) | wDE;//DATA_EN;
rDECount <= #1 (rDECount<<C_PCI_DATA_COUNT_WIDTH) | wDECount;//DATA_EN_COUNT;
rDone <= #1 (rDone<<1) | DONE;
rErr <= #1 (rErr<<1) | ERR;
rDEShifted <= #1 (rDEShifted<<C_PCI_DATA_WORD) | rDEShift;
rWords <= #1 (rWords<<C_TAG_DW_COUNT_WIDTH) | rCount;
rShifted <= #1 (rShifted<<C_PCI_DATA_WORD_WIDTH) | rShift;
end
// Input processing pipeline
always @ (posedge CLK) begin
// STAGE 0: Register the incoming data
// STAGE 1: Request existing count from RAM
// To cover the gap b/t reads and writes to RAM, next cycle we might need
// to use the existing or even the previous rCount value if the tags match.
rUseCurrCount <= #1 (rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[1*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[1]);
rUsePrevCount <= #1 (rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[2]);
rPrevCount <= #1 rCount;
// See if we need to reset the count
rCountValid <= #1 (RST ? 1'd0 : rCountRst>>rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH]);
rValidCount <= #1 (RST ? 0 : rValid[0]<<rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH]);
// STAGE 2: Calculate new count (saves next cycle)
if (rUseCurrCount) begin
rShift <= #1 rCount[0 +:C_PCI_DATA_WORD_WIDTH];
rCount <= #1 rCount + rDECount[1*C_PCI_DATA_COUNT_WIDTH +:C_PCI_DATA_COUNT_WIDTH];
end
else if (rUsePrevCount) begin
rShift <= #1 rPrevCount[0 +:C_PCI_DATA_WORD_WIDTH];
rCount <= #1 rPrevCount + rDECount[1*C_PCI_DATA_COUNT_WIDTH +:C_PCI_DATA_COUNT_WIDTH];
end
else begin
rShift <= #1 wCountClr[0 +:C_PCI_DATA_WORD_WIDTH];
rCount <= #1 wCountClr + rDECount[1*C_PCI_DATA_COUNT_WIDTH +:C_PCI_DATA_COUNT_WIDTH];
end
// STAGE 3: Request existing positions from RAM
// Barrel shift the DE
rDEShift <= #1 (rDE[2*C_PCI_DATA_WORD +:C_PCI_DATA_WORD]<<rShift) |
(rDE[2*C_PCI_DATA_WORD +:C_PCI_DATA_WORD]>>(C_PCI_DATA_WORD-rShift));
// To cover the gap b/t reads and writes to RAM, next cycle we might need
// to use the existing or even the previous rPos values if the tags match.
rUseCurrPos <= #1 (rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[3*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[3]);
rUsePrevPos <= #1 (rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[4*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[4]);
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rPrevPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ? wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] : rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH]);
end
// See if we need to reset the positions
rPosValid <= #1 (RST ? 1'd0 : rPosRst>>rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]);
rValidPos <= #1 (RST ? 0 : rValid[2]<<rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]);
// STAGE 4: Calculate new positions (saves next cycle)
if (rUseCurrPos) begin
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH]);
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] + rDEShift[i]);
end
end
else if (rUsePrevPos) begin
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
rPrevPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH]);
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
rPrevPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] + rDEShift[i]);
end
end
else begin
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
wPosClr[i*C_DATA_ADDR_STRIDE_WIDTH +:C_DATA_ADDR_STRIDE_WIDTH]);
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
wPosClr[i*C_DATA_ADDR_STRIDE_WIDTH +:C_DATA_ADDR_STRIDE_WIDTH] + rDEShift[i]);
end
end
// Calculate the base address offset
rBaseAddr <= #1 rTag[3*C_TAG_WIDTH +:C_TAG_WIDTH]<<C_DATA_ADDR_STRIDE_WIDTH;
// Calculate the shift amounts for barrel shifting payload data
rShiftUp <= #1 rShifted[0*C_PCI_DATA_WORD_WIDTH +:C_PCI_DATA_WORD_WIDTH]<<5;
rShiftDown <= #1 (C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0] - rShifted[0*C_PCI_DATA_WORD_WIDTH +:C_PCI_DATA_WORD_WIDTH])<<5;
// STAGE 5: Prepare to write data, final info
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rAddr[C_DATA_ADDR_WIDTH*i +:C_DATA_ADDR_WIDTH] <= #1
rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] + rBaseAddr;
end
rDataShifted <= #1 (rData[4*C_PCI_DATA_WIDTH +:C_PCI_DATA_WIDTH]<<rShiftUp) |
(rData[4*C_PCI_DATA_WIDTH +:C_PCI_DATA_WIDTH]>>rShiftDown);
rLTE1Pkt <= #1 (rWords[1*C_TAG_DW_COUNT_WIDTH +:C_TAG_DW_COUNT_WIDTH] <= C_PCI_DATA_WORD);
rLTE2Pkt <= #1 (rWords[1*C_TAG_DW_COUNT_WIDTH +:C_TAG_DW_COUNT_WIDTH] <= (C_PCI_DATA_WORD*2));
rFinish <= #1 (rValid[4] & (rDone[4] | rErr[4]))<<rTag[4*C_TAG_WIDTH +:C_TAG_WIDTH];
// STAGE 6: Write data, final info
end
// Reset the count and positions when needed
always @ (posedge CLK) begin
if (RST) begin
rCountRst <= #1 0;
rPosRst <= #1 0;
end
else begin
rCountRst <= #1 (rCountRst | rValidCount) & ~TAG_CLEAR;
rPosRst <= #1 (rPosRst | rValidPos) & ~TAG_CLEAR;
end
end
// RAM for counts
(* RAM_STYLE="DISTRIBUTED" *)
ram_1clk_1w_1r
#(
.C_RAM_WIDTH(C_TAG_DW_COUNT_WIDTH),
.C_RAM_DEPTH(C_NUM_TAGS))
countRam
(
.CLK(CLK),
.ADDRA(rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]),
.WEA(rValid[2]),
.DINA(rCount),
.ADDRB(rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH]),
.DOUTB(wCount)
);
// RAM for positions
(* RAM_STYLE="DISTRIBUTED" *)
ram_1clk_1w_1r
#(
.C_RAM_WIDTH(C_PCI_DATA_WORD*C_DATA_ADDR_STRIDE_WIDTH),
.C_RAM_DEPTH(C_NUM_TAGS))
posRam
(
.CLK(CLK),
.ADDRA(rTag[4*C_TAG_WIDTH +:C_TAG_WIDTH]),
.WEA(rValid[4]),
.DINA(rPos),
.ADDRB(rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]),
.DOUTB(wPos)
);
endmodule
// Local Variables:
// verilog-library-directories:("." "registers/" "../common/")
// End:
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pipe_rate.v
// Version : 4.1
//----------------------------------------------------------------------------//
// Filename : pcie3_7x_0_pipe_rate.v
// Description : PIPE Rate Module for 7 Series Transceiver
// Version : 20.1
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Rate Module --------------------------------------------------
module pcie3_7x_0_pipe_rate #
(
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
parameter TXDATA_WAIT_MAX = 4'd15 // TXDATA wait max
)
(
//---------- Input -------------------------------------
input RATE_CLK,
input RATE_RST_N,
input RATE_RST_IDLE,
input RATE_ACTIVE_LANE,
input [ 1:0] RATE_RATE_IN,
input RATE_CPLLLOCK,
input RATE_QPLLLOCK,
input RATE_MMCM_LOCK,
input RATE_DRP_DONE,
input RATE_RXPMARESETDONE,
input RATE_TXRESETDONE,
input RATE_RXRESETDONE,
input RATE_TXRATEDONE,
input RATE_RXRATEDONE,
input RATE_PHYSTATUS,
input RATE_RESETOVRD_DONE,
input RATE_TXSYNC_DONE,
input RATE_RXSYNC_DONE,
//---------- Output ------------------------------------
output RATE_CPLLPD,
output RATE_QPLLPD,
output RATE_CPLLRESET,
output RATE_QPLLRESET,
output RATE_TXPMARESET,
output RATE_RXPMARESET,
output RATE_DRP_START,
output [ 1:0] RATE_SYSCLKSEL,
output RATE_PCLK_SEL,
output RATE_GEN3,
output RATE_DRP_X16X20_MODE,
output RATE_DRP_X16,
output [ 2:0] RATE_RATE_OUT,
output RATE_RESETOVRD_START,
output RATE_TXSYNC_START,
output RATE_DONE,
output RATE_RXSYNC_START,
output RATE_RXSYNC,
output RATE_IDLE,
output [4:0] RATE_FSM
);
//---------- Input FF or Buffer ------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg2;
//---------- Internal Signals --------------------------
wire pll_lock;
wire [ 2:0] rate;
reg [ 3:0] txdata_wait_cnt = 4'd0;
reg txratedone = 1'd0;
reg rxratedone = 1'd0;
reg phystatus = 1'd0;
reg ratedone = 1'd0;
reg gen3_exit = 1'd0;
//---------- Output FF or Buffer -----------------------
reg cpllpd = 1'd0;
reg qpllpd = 1'd0;
reg cpllreset = 1'd0;
reg qpllreset = 1'd0;
reg txpmareset = 1'd0;
reg rxpmareset = 1'd0;
reg [ 1:0] sysclksel = (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
reg gen3 = 1'd0;
reg pclk_sel = 1'd0;
reg [ 2:0] rate_out = 3'd0;
reg drp_start = 1'd0;
reg drp_x16x20_mode = 1'd0;
reg drp_x16 = 1'd0;
reg [4:0] fsm = 0;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 0;
localparam FSM_PLL_PU = 1; // Gen 3 only
localparam FSM_PLL_PURESET = 2; // Gen 3 only
localparam FSM_PLL_LOCK = 3; // Gen 3 or reset only
localparam FSM_DRP_X16_GEN3_START = 4;
localparam FSM_DRP_X16_GEN3_DONE = 5;
localparam FSM_PMARESET_HOLD = 6; // Gen 3 or reset only
localparam FSM_PLL_SEL = 7; // Gen 3 or reset only
localparam FSM_MMCM_LOCK = 8; // Gen 3 or reset only
localparam FSM_DRP_START = 9; // Gen 3 or reset only
localparam FSM_DRP_DONE = 10; // Gen 3 or reset only
localparam FSM_PMARESET_RELEASE = 11; // Gen 3 only
localparam FSM_PMARESET_DONE = 12; // Gen 3 only
localparam FSM_TXDATA_WAIT = 13;
localparam FSM_PCLK_SEL = 14;
localparam FSM_DRP_X16_START = 15;
localparam FSM_DRP_X16_DONE = 16;
localparam FSM_RATE_SEL = 17;
localparam FSM_RXPMARESETDONE = 18;
localparam FSM_DRP_X20_START = 19;
localparam FSM_DRP_X20_DONE = 20;
localparam FSM_RATE_DONE = 21;
localparam FSM_RESETOVRD_START = 22; // PCIe use mode 1.0 only
localparam FSM_RESETOVRD_DONE = 23; // PCIe use mode 1.0 only
localparam FSM_PLL_PDRESET = 24;
localparam FSM_PLL_PD = 25;
localparam FSM_TXSYNC_START = 26;
localparam FSM_TXSYNC_DONE = 27;
localparam FSM_DONE = 28; // Must sync value to pipe_user.v
localparam FSM_RXSYNC_START = 29; // Gen 3 only
localparam FSM_RXSYNC_DONE = 30; // Gen 3 only
//---------- Input FF ----------------------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
//---------- 1st Stage FF --------------------------
rst_idle_reg1 <= 1'd0;
rate_in_reg1 <= 2'd0;
cplllock_reg1 <= 1'd0;
qplllock_reg1 <= 1'd0;
mmcm_lock_reg1 <= 1'd0;
drp_done_reg1 <= 1'd0;
rxpmaresetdone_reg1 <= 1'd0;
txresetdone_reg1 <= 1'd0;
rxresetdone_reg1 <= 1'd0;
txratedone_reg1 <= 1'd0;
rxratedone_reg1 <= 1'd0;
phystatus_reg1 <= 1'd0;
resetovrd_done_reg1 <= 1'd0;
txsync_done_reg1 <= 1'd0;
rxsync_done_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
rst_idle_reg2 <= 1'd0;
rate_in_reg2 <= 2'd0;
cplllock_reg2 <= 1'd0;
qplllock_reg2 <= 1'd0;
mmcm_lock_reg2 <= 1'd0;
drp_done_reg2 <= 1'd0;
rxpmaresetdone_reg2 <= 1'd0;
txresetdone_reg2 <= 1'd0;
rxresetdone_reg2 <= 1'd0;
txratedone_reg2 <= 1'd0;
rxratedone_reg2 <= 1'd0;
phystatus_reg2 <= 1'd0;
resetovrd_done_reg2 <= 1'd0;
txsync_done_reg2 <= 1'd0;
rxsync_done_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
rst_idle_reg1 <= RATE_RST_IDLE;
rate_in_reg1 <= RATE_RATE_IN;
cplllock_reg1 <= RATE_CPLLLOCK;
qplllock_reg1 <= RATE_QPLLLOCK;
mmcm_lock_reg1 <= RATE_MMCM_LOCK;
drp_done_reg1 <= RATE_DRP_DONE;
rxpmaresetdone_reg1 <= RATE_RXPMARESETDONE;
txresetdone_reg1 <= RATE_TXRESETDONE;
rxresetdone_reg1 <= RATE_RXRESETDONE;
txratedone_reg1 <= RATE_TXRATEDONE;
rxratedone_reg1 <= RATE_RXRATEDONE;
phystatus_reg1 <= RATE_PHYSTATUS;
resetovrd_done_reg1 <= RATE_RESETOVRD_DONE;
txsync_done_reg1 <= RATE_TXSYNC_DONE;
rxsync_done_reg1 <= RATE_RXSYNC_DONE;
//---------- 2nd Stage FF --------------------------
rst_idle_reg2 <= rst_idle_reg1;
rate_in_reg2 <= rate_in_reg1;
cplllock_reg2 <= cplllock_reg1;
qplllock_reg2 <= qplllock_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
drp_done_reg2 <= drp_done_reg1;
rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
txresetdone_reg2 <= txresetdone_reg1;
rxresetdone_reg2 <= rxresetdone_reg1;
txratedone_reg2 <= txratedone_reg1;
rxratedone_reg2 <= rxratedone_reg1;
phystatus_reg2 <= phystatus_reg1;
resetovrd_done_reg2 <= resetovrd_done_reg1;
txsync_done_reg2 <= txsync_done_reg1;
rxsync_done_reg2 <= rxsync_done_reg1;
end
end
//---------- Select CPLL or QPLL Lock ------------------------------------------
// Gen1 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock
// Gen2 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock
// Gen3 : Wait for QPLL lock
//------------------------------------------------------------------------------
assign pll_lock = (rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL") ? qplllock_reg2 : cplllock_reg2;
//---------- Select Rate -------------------------------------------------------
// Gen1 : Div 4 using [TX/RX]OUT_DIV = 4 if QPLL is used for Gen1/Gen2, else div 2 using [TX/RX]OUT_DIV = 2
// Gen2 : Div 2 using [TX/RX]RATE = 3'd2 if QPLL is used for Gen1/Gen2, else div 1 using [TX/RX]RATE = 3'd1
// Gen3 : Div 1 using [TX/RX]OUT_DIV = 1
//------------------------------------------------------------------------------
assign rate = (rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "QPLL") ? 3'd2 :
(rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "CPLL") ? 3'd1 : 3'd0;
//---------- TXDATA Wait Counter -----------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
txdata_wait_cnt <= 4'd0;
else
//---------- Increment Wait Counter ----------------
if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt < TXDATA_WAIT_MAX))
txdata_wait_cnt <= txdata_wait_cnt + 4'd1;
//---------- Hold Wait Counter ---------------------
else if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt == TXDATA_WAIT_MAX))
txdata_wait_cnt <= txdata_wait_cnt;
//---------- Reset Wait Counter --------------------
else
txdata_wait_cnt <= 4'd0;
end
//---------- Latch TXRATEDONE, RXRATEDONE, and PHYSTATUS -----------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
txratedone <= 1'd0;
rxratedone <= 1'd0;
phystatus <= 1'd0;
ratedone <= 1'd0;
end
else
begin
if (fsm == FSM_RATE_DONE)
begin
//---------- Latch TXRATEDONE ------------------
if (txratedone_reg2)
txratedone <= 1'd1;
else
txratedone <= txratedone;
//---------- Latch RXRATEDONE ------------------
if (rxratedone_reg2)
rxratedone <= 1'd1;
else
rxratedone <= rxratedone;
//---------- Latch PHYSTATUS -------------------
if (phystatus_reg2)
phystatus <= 1'd1;
else
phystatus <= phystatus;
//---------- Latch Rate Done -------------------
if (rxratedone && txratedone && phystatus)
ratedone <= 1'd1;
else
ratedone <= ratedone;
end
else
begin
txratedone <= 1'd0;
rxratedone <= 1'd0;
phystatus <= 1'd0;
ratedone <= 1'd0;
end
end
end
//---------- PIPE Rate FSM -----------------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
fsm <= FSM_PLL_LOCK;
gen3_exit <= 1'd0;
cpllpd <= 1'd0;
qpllpd <= 1'd0;
cpllreset <= 1'd0;
qpllreset <= 1'd0;
txpmareset <= 1'd0;
rxpmareset <= 1'd0;
sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
pclk_sel <= 1'd0;
gen3 <= 1'd0;
rate_out <= 3'd0;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Detect Rate Change ----------------
if (rate_in_reg2 != rate_in_reg1)
begin
fsm <= ((rate_in_reg2 == 2'd2) || (rate_in_reg1 == 2'd2)) ? FSM_PLL_PU : FSM_TXDATA_WAIT;
gen3_exit <= (rate_in_reg2 == 2'd2);
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
end
//---------- Power-up PLL --------------------------
FSM_PLL_PU :
begin
fsm <= FSM_PLL_PURESET;
gen3_exit <= gen3_exit;
cpllpd <= (PCIE_PLL_SEL == "QPLL");
qpllpd <= 1'd0;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Release PLL Resets --------------------
FSM_PLL_PURESET :
begin
fsm <= FSM_PLL_LOCK;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= (PCIE_PLL_SEL == "QPLL");
qpllreset <= 1'd0;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for PLL Lock ---------------------
FSM_PLL_LOCK :
begin
fsm <= (pll_lock ? ((!rst_idle_reg2 || (rate_in_reg2 == 2'd1)) ? FSM_PMARESET_HOLD : FSM_DRP_X16_GEN3_START) : FSM_PLL_LOCK);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_GEN3_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_GEN3_DONE : FSM_DRP_X16_GEN3_START;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_GEN3_DONE :
begin
fsm <= drp_done_reg2 ? FSM_PMARESET_HOLD : FSM_DRP_X16_GEN3_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Hold both PMA in Reset ----------------
// Gen1 : Release PMA Reset
// Gen2 : Release PMA Reset
// Gen3 : Hold PMA Reset
//--------------------------------------------------
FSM_PMARESET_HOLD :
begin
fsm <= FSM_PLL_SEL;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit);
rxpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit);
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Select PLL ----------------------------
// Gen1 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL
// Gen2 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL
// Gen3 : QPLL
//--------------------------------------------------
FSM_PLL_SEL :
begin
fsm <= FSM_MMCM_LOCK;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= ((rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL")) ? 2'd1 : 2'd0;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Check for MMCM Lock -------------------
FSM_MMCM_LOCK :
begin
fsm <= (mmcm_lock_reg2 && !rxpmaresetdone_reg2 ? FSM_DRP_START : FSM_MMCM_LOCK);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP -----------------------------
FSM_DRP_START:
begin
fsm <= (!drp_done_reg2 ? FSM_DRP_DONE : FSM_DRP_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2));
gen3 <= (rate_in_reg2 == 2'd2);
rate_out <= (((rate_in_reg2 == 2'd2) || gen3_exit) ? rate : rate_out);
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for DRP Done ---------------------
FSM_DRP_DONE :
begin
fsm <= ((drp_done_reg2 && pll_lock) ? (rst_idle_reg2 ? FSM_PMARESET_RELEASE : FSM_IDLE): FSM_DRP_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Release PMA Resets --------------------
FSM_PMARESET_RELEASE :
begin
fsm <= FSM_PMARESET_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= 1'd0;
rxpmareset <= 1'd0;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for both TX/RX PMA Reset Dones and PHYSTATUS Deassertion
FSM_PMARESET_DONE :
begin
fsm <= (((rxresetdone_reg2 && txresetdone_reg2 && !phystatus_reg2) || !RATE_ACTIVE_LANE) ? FSM_TXDATA_WAIT : FSM_PMARESET_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for TXDATA to TX[P/N] Latency ----
FSM_TXDATA_WAIT :
begin
fsm <= (txdata_wait_cnt == TXDATA_WAIT_MAX) ? FSM_PCLK_SEL : FSM_TXDATA_WAIT;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Select PCLK Frequency -----------------
// Gen1 : PCLK = 125 MHz
// Gen2 : PCLK = 250 MHz
// Gen3 : PCLK = 250 MHz
//--------------------------------------------------
FSM_PCLK_SEL :
begin
fsm <= ((PCIE_GT_DEVICE == "GTH") && ((rate_in_reg2 == 2'd1) || ((!gen3_exit) && (rate_in_reg2 == 2'd0)))) ? FSM_DRP_X16_START : FSM_RATE_SEL;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2));
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_DONE :
begin
fsm <= drp_done_reg2 ? FSM_RATE_SEL : FSM_DRP_X16_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Select Rate ---------------------------
FSM_RATE_SEL :
begin
fsm <= ((PCIE_GT_DEVICE == "GTH") && ((rate_in_reg2 == 2'd1) || ((!gen3_exit) && (rate_in_reg2 == 2'd0)))) ? FSM_RXPMARESETDONE : FSM_RATE_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate; // Update [TX/RX]RATE
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for RXPMARESETDONE De-assertion --
FSM_RXPMARESETDONE :
begin
fsm <= (!rxpmaresetdone_reg2) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP x20 -------------------------
FSM_DRP_X20_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd0;
end
//---------- Wait for DRP x20 Done -----------------
FSM_DRP_X20_DONE :
begin
fsm <= drp_done_reg2 ? FSM_RATE_DONE : FSM_DRP_X20_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd0;
end
//---------- Wait for Rate Change Done -------------
FSM_RATE_DONE :
begin
if (ratedone || (rate_in_reg2 == 2'd2) || (gen3_exit) || !RATE_ACTIVE_LANE)
if ((PCIE_USE_MODE == "1.0") && (rate_in_reg2 != 2'd2) && (!gen3_exit))
fsm <= FSM_RESETOVRD_START;
else
fsm <= FSM_PLL_PDRESET;
else
fsm <= FSM_RATE_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Reset Override Start ------------------
FSM_RESETOVRD_START:
begin
fsm <= (!resetovrd_done_reg2 ? FSM_RESETOVRD_DONE : FSM_RESETOVRD_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Reset Override Done -------------------
FSM_RESETOVRD_DONE :
begin
fsm <= (resetovrd_done_reg2 ? FSM_PLL_PDRESET : FSM_RESETOVRD_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Hold PLL Not Used in Reset ------------
FSM_PLL_PDRESET :
begin
fsm <= FSM_PLL_PD;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2);
qpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2);
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Power-Down PLL Not Used ---------------
FSM_PLL_PD :
begin
fsm <= (((rate_in_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? FSM_TXSYNC_START : FSM_DONE);
gen3_exit <= gen3_exit;
cpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2);
qpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2);
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start TX Sync -------------------------
FSM_TXSYNC_START:
begin
fsm <= (!txsync_done_reg2 ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for TX Sync Done -----------------
FSM_TXSYNC_DONE:
begin
fsm <= (txsync_done_reg2 ? FSM_DONE : FSM_TXSYNC_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Rate Change Done ----------------------
FSM_DONE :
begin
fsm <= (((rate_in_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE") && (PCIE_ASYNC_EN == "TRUE")) ? FSM_RXSYNC_START : FSM_IDLE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start RX Sync -------------------------
FSM_RXSYNC_START:
begin
fsm <= (!rxsync_done_reg2 ? FSM_RXSYNC_DONE : FSM_RXSYNC_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for RX Sync Done -----------------
FSM_RXSYNC_DONE:
begin
fsm <= (rxsync_done_reg2 ? FSM_IDLE : FSM_RXSYNC_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
gen3_exit <= 1'd0;
cpllpd <= 1'd0;
qpllpd <= 1'd0;
cpllreset <= 1'd0;
qpllreset <= 1'd0;
txpmareset <= 1'd0;
rxpmareset <= 1'd0;
sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
pclk_sel <= 1'd0;
gen3 <= 1'd0;
rate_out <= 3'd0;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
endcase
end
end
//---------- PIPE Rate Output --------------------------------------------------
assign RATE_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd);
assign RATE_QPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd);
assign RATE_CPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllreset);
assign RATE_QPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllreset);
assign RATE_TXPMARESET = txpmareset;
assign RATE_RXPMARESET = rxpmareset;
assign RATE_SYSCLKSEL = sysclksel;
//assign RATE_DRP_START = (fsm == FSM_DRP_START) || (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
assign RATE_DRP_START = drp_start;
//assign RATE_DRP_X16X20_MODE = (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_GEN3_DONE) ||
// (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) ||
// (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE);
assign RATE_DRP_X16X20_MODE = drp_x16x20_mode;
//assign RATE_DRP_X16 = (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_GEN3_DONE) ||
// (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
assign RATE_DRP_X16 = drp_x16;
assign RATE_PCLK_SEL = pclk_sel;
assign RATE_GEN3 = gen3;
assign RATE_RATE_OUT = rate_out;
assign RATE_RESETOVRD_START = (fsm == FSM_RESETOVRD_START);
assign RATE_TXSYNC_START = (fsm == FSM_TXSYNC_START);
assign RATE_DONE = (fsm == FSM_DONE);
assign RATE_RXSYNC_START = (fsm == FSM_RXSYNC_START);
assign RATE_RXSYNC = ((fsm == FSM_RXSYNC_START) || (fsm == FSM_RXSYNC_DONE));
assign RATE_IDLE = (fsm == FSM_IDLE);
assign RATE_FSM = fsm;
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE DMA Top Level ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_dma_top.v,v 1.5 2002-02-01 01:54:45 rudi Exp $
//
// $Date: 2002-02-01 01:54:45 $
// $Revision: 1.5 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.4 2001/10/19 04:35:04 rudi
//
// - Made the core parameterized
//
// Revision 1.3 2001/09/07 15:34:38 rudi
//
// Changed reset to active high.
//
// Revision 1.2 2001/08/15 05:40:30 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Added Section 3.10, describing DMA restart.
//
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.3 2001/06/13 02:26:50 rudi
//
//
// Small changes after running lint.
//
// Revision 1.2 2001/06/05 10:22:37 rudi
//
//
// - Added Support of up to 31 channels
// - Added support for 2,4 and 8 priority levels
// - Now can have up to 31 channels
// - Added many configuration items
// - Changed reset to async
//
// Revision 1.1.1.1 2001/03/19 13:10:23 rudi
// Initial Release
//
//
//
`include "wb_dma_defines.v"
module wb_dma_top(clk_i, rst_i,
wb0s_data_i, wb0s_data_o, wb0_addr_i, wb0_sel_i, wb0_we_i, wb0_cyc_i,
wb0_stb_i, wb0_ack_o, wb0_err_o, wb0_rty_o,
wb0m_data_i, wb0m_data_o, wb0_addr_o, wb0_sel_o, wb0_we_o, wb0_cyc_o,
wb0_stb_o, wb0_ack_i, wb0_err_i, wb0_rty_i,
wb1s_data_i, wb1s_data_o, wb1_addr_i, wb1_sel_i, wb1_we_i, wb1_cyc_i,
wb1_stb_i, wb1_ack_o, wb1_err_o, wb1_rty_o,
wb1m_data_i, wb1m_data_o, wb1_addr_o, wb1_sel_o, wb1_we_o, wb1_cyc_o,
wb1_stb_o, wb1_ack_i, wb1_err_i, wb1_rty_i,
dma_req_i, dma_ack_o, dma_nd_i, dma_rest_i,
inta_o, intb_o
);
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
// chXX_conf = { CBUF, ED, ARS, EN }
parameter rf_addr = 0;
parameter [1:0] pri_sel = 2'h0;
parameter ch_count = 1;
parameter [3:0] ch0_conf = 4'hf;
parameter [3:0] ch1_conf = 4'hf;
parameter [3:0] ch2_conf = 4'hf;
parameter [3:0] ch3_conf = 4'hf;
parameter [3:0] ch4_conf = 4'hf;
parameter [3:0] ch5_conf = 4'hf;
parameter [3:0] ch6_conf = 4'hf;
parameter [3:0] ch7_conf = 4'hf;
parameter [3:0] ch8_conf = 4'hf;
parameter [3:0] ch9_conf = 4'hf;
parameter [3:0] ch10_conf = 4'hf;
parameter [3:0] ch11_conf = 4'hf;
parameter [3:0] ch12_conf = 4'hf;
parameter [3:0] ch13_conf = 4'hf;
parameter [3:0] ch14_conf = 4'hf;
parameter [3:0] ch15_conf = 4'hf;
parameter [3:0] ch16_conf = 4'hf;
parameter [3:0] ch17_conf = 4'hf;
parameter [3:0] ch18_conf = 4'hf;
parameter [3:0] ch19_conf = 4'hf;
parameter [3:0] ch20_conf = 4'hf;
parameter [3:0] ch21_conf = 4'hf;
parameter [3:0] ch22_conf = 4'hf;
parameter [3:0] ch23_conf = 4'hf;
parameter [3:0] ch24_conf = 4'hf;
parameter [3:0] ch25_conf = 4'hf;
parameter [3:0] ch26_conf = 4'hf;
parameter [3:0] ch27_conf = 4'hf;
parameter [3:0] ch28_conf = 4'hf;
parameter [3:0] ch29_conf = 4'hf;
parameter [3:0] ch30_conf = 4'hf;
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
input clk_i, rst_i;
// --------------------------------------
// WISHBONE INTERFACE 0
// Slave Interface
input [31:0] wb0s_data_i;
output [31:0] wb0s_data_o;
input [31:0] wb0_addr_i;
input [3:0] wb0_sel_i;
input wb0_we_i;
input wb0_cyc_i;
input wb0_stb_i;
output wb0_ack_o;
output wb0_err_o;
output wb0_rty_o;
// Master Interface
input [31:0] wb0m_data_i;
output [31:0] wb0m_data_o;
output [31:0] wb0_addr_o;
output [3:0] wb0_sel_o;
output wb0_we_o;
output wb0_cyc_o;
output wb0_stb_o;
input wb0_ack_i;
input wb0_err_i;
input wb0_rty_i;
// --------------------------------------
// WISHBONE INTERFACE 1
// Slave Interface
input [31:0] wb1s_data_i;
output [31:0] wb1s_data_o;
input [31:0] wb1_addr_i;
input [3:0] wb1_sel_i;
input wb1_we_i;
input wb1_cyc_i;
input wb1_stb_i;
output wb1_ack_o;
output wb1_err_o;
output wb1_rty_o;
// Master Interface
input [31:0] wb1m_data_i;
output [31:0] wb1m_data_o;
output [31:0] wb1_addr_o;
output [3:0] wb1_sel_o;
output wb1_we_o;
output wb1_cyc_o;
output wb1_stb_o;
input wb1_ack_i;
input wb1_err_i;
input wb1_rty_i;
// --------------------------------------
// Misc Signals
input [ch_count-1:0] dma_req_i;
input [ch_count-1:0] dma_nd_i;
output [ch_count-1:0] dma_ack_o;
input [ch_count-1:0] dma_rest_i;
output inta_o;
output intb_o;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire [31:0] pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1;
wire [31:0] pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1;
wire [31:0] pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1;
wire [31:0] pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1;
wire [31:0] pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1;
wire [31:0] pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1;
wire [31:0] pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1;
wire [31:0] pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1;
wire [31:0] pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1;
wire [31:0] pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1;
wire [31:0] pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1;
wire [31:0] pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1;
wire [31:0] pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1;
wire [31:0] pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1;
wire [31:0] pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1;
wire [31:0] pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1;
wire [31:0] pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1;
wire [31:0] pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1;
wire [31:0] pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1;
wire [31:0] pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1;
wire [31:0] pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1;
wire [31:0] pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1;
wire [31:0] pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1;
wire [31:0] pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1;
wire [31:0] pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1;
wire [31:0] pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1;
wire [31:0] pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1;
wire [31:0] pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1;
wire [31:0] pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1;
wire [31:0] pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1;
wire [31:0] pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1;
wire [4:0] ch_sel; // Write Back Channel Select
wire [30:0] ndnr; // Next Descriptor No Request
wire de_start; // Start DMA Engine
wire ndr; // Next Descriptor With Request
wire [31:0] csr; // Selected Channel CSR
wire [31:0] pointer;
wire [31:0] pointer_s;
wire [31:0] txsz; // Selected Channel Transfer Size
wire [31:0] adr0, adr1; // Selected Channel Addresses
wire [31:0] am0, am1; // Selected Channel Address Masks
wire next_ch; // Indicates the DMA Engine is done
wire inta_o, intb_o;
wire dma_abort;
wire dma_busy, dma_err, dma_done, dma_done_all;
wire [31:0] de_csr;
wire [11:0] de_txsz;
wire [31:0] de_adr0;
wire [31:0] de_adr1;
wire de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we;
wire de_fetch_descr;
wire ptr_set;
wire de_ack;
wire pause_req;
wire paused;
wire mast0_go; // Perform a Master Cycle (as long as this
wire mast0_we; // Read/Write
wire [31:0] mast0_adr; // Address for the transfer
wire [3:0] mast0_sel;
wire [31:0] mast0_din; // Internal Input Data
wire [31:0] mast0_dout; // Internal Output Data
wire mast0_err; // Indicates an error has occurred
wire mast0_drdy; // Indicated that either data is available
wire mast0_wait; // Tells the master to insert wait cycles
wire [31:0] slv0_adr; // Slave Address
wire [31:0] slv0_din; // Slave Input Data
wire [31:0] slv0_dout; // Slave Output Data
wire slv0_re; // Slave Read Enable
wire slv0_we; // Slave Write Enable
wire pt0_sel_i; // Pass Through Mode Selected
wire [70:0] mast0_pt_in; // Grouped WISHBONE inputs
wire [34:0] mast0_pt_out; // Grouped WISHBONE outputs
wire pt0_sel_o; // Pass Through Mode Active
wire [70:0] slv0_pt_out; // Grouped WISHBONE out signals
wire [34:0] slv0_pt_in; // Grouped WISHBONE in signals
wire mast1_go; // Perform a Master Cycle (as long as this
wire mast1_we; // Read/Write
wire [31:0] mast1_adr; // Address for the transfer
wire [3:0] mast1_sel;
wire [31:0] mast1_din; // Internal Input Data
wire [31:0] mast1_dout; // Internal Output Data
wire mast1_err; // Indicates an error has occurred
wire mast1_drdy; // Indicated that either data is available
wire mast1_wait; // Tells the master to insert wait cycles
wire [31:0] slv1_adr; // Slave Address
wire [31:0] slv1_dout; // Slave Output Data
wire slv1_re; // Slave Read Enable
wire slv1_we; // Slave Write Enable
wire pt1_sel_i; // Pass Through Mode Selected
wire [70:0] mast1_pt_in; // Grouped WISHBONE inputs
wire [34:0] mast1_pt_out; // Grouped WISHBONE outputs
wire pt1_sel_o; // Pass Through Mode Active
wire [70:0] slv1_pt_out; // Grouped WISHBONE out signals
wire [34:0] slv1_pt_in; // Grouped WISHBONE in signals
wire [30:0] dma_req;
wire [30:0] dma_nd;
wire [30:0] dma_ack;
wire [30:0] dma_rest;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
wire [31:0] tmp_gnd = 32'h0;
assign dma_req[ch_count-1:0] = dma_req_i;
assign dma_nd[ch_count-1:0] = dma_nd_i;
assign dma_rest[ch_count-1:0] = dma_rest_i;
assign dma_ack_o = {tmp_gnd[31-ch_count:0], dma_ack[ch_count-1:0]};
// --------------------------------------------------
// This should go in to a separate Pass Through Block
assign pt1_sel_i = pt0_sel_o;
assign pt0_sel_i = pt1_sel_o;
assign mast1_pt_in = slv0_pt_out;
assign slv0_pt_in = mast1_pt_out;
assign mast0_pt_in = slv1_pt_out;
assign slv1_pt_in = mast0_pt_out;
// --------------------------------------------------
////////////////////////////////////////////////////////////////////
//
// Modules
//
// DMA Register File
wb_dma_rf #( ch0_conf,
ch1_conf,
ch2_conf,
ch3_conf,
ch4_conf,
ch5_conf,
ch6_conf,
ch7_conf,
ch8_conf,
ch9_conf,
ch10_conf,
ch11_conf,
ch12_conf,
ch13_conf,
ch14_conf,
ch15_conf,
ch16_conf,
ch17_conf,
ch18_conf,
ch19_conf,
ch20_conf,
ch21_conf,
ch22_conf,
ch23_conf,
ch24_conf,
ch25_conf,
ch26_conf,
ch27_conf,
ch28_conf,
ch29_conf,
ch30_conf)
u0(
.clk( clk_i ),
.rst( ~rst_i ),
.wb_rf_adr( slv0_adr[9:2] ),
.wb_rf_din( slv0_dout ),
.wb_rf_dout( slv0_din ),
.wb_rf_re( slv0_re ),
.wb_rf_we( slv0_we ),
.inta_o( inta_o ),
.intb_o( intb_o ),
.pointer0( pointer0 ),
.pointer0_s( pointer0_s ),
.ch0_csr( ch0_csr ),
.ch0_txsz( ch0_txsz ),
.ch0_adr0( ch0_adr0 ),
.ch0_adr1( ch0_adr1 ),
.ch0_am0( ch0_am0 ),
.ch0_am1( ch0_am1 ),
.pointer1( pointer1 ),
.pointer1_s( pointer1_s ),
.ch1_csr( ch1_csr ),
.ch1_txsz( ch1_txsz ),
.ch1_adr0( ch1_adr0 ),
.ch1_adr1( ch1_adr1 ),
.ch1_am0( ch1_am0 ),
.ch1_am1( ch1_am1 ),
.pointer2( pointer2 ),
.pointer2_s( pointer2_s ),
.ch2_csr( ch2_csr ),
.ch2_txsz( ch2_txsz ),
.ch2_adr0( ch2_adr0 ),
.ch2_adr1( ch2_adr1 ),
.ch2_am0( ch2_am0 ),
.ch2_am1( ch2_am1 ),
.pointer3( pointer3 ),
.pointer3_s( pointer3_s ),
.ch3_csr( ch3_csr ),
.ch3_txsz( ch3_txsz ),
.ch3_adr0( ch3_adr0 ),
.ch3_adr1( ch3_adr1 ),
.ch3_am0( ch3_am0 ),
.ch3_am1( ch3_am1 ),
.pointer4( pointer4 ),
.pointer4_s( pointer4_s ),
.ch4_csr( ch4_csr ),
.ch4_txsz( ch4_txsz ),
.ch4_adr0( ch4_adr0 ),
.ch4_adr1( ch4_adr1 ),
.ch4_am0( ch4_am0 ),
.ch4_am1( ch4_am1 ),
.pointer5( pointer5 ),
.pointer5_s( pointer5_s ),
.ch5_csr( ch5_csr ),
.ch5_txsz( ch5_txsz ),
.ch5_adr0( ch5_adr0 ),
.ch5_adr1( ch5_adr1 ),
.ch5_am0( ch5_am0 ),
.ch5_am1( ch5_am1 ),
.pointer6( pointer6 ),
.pointer6_s( pointer6_s ),
.ch6_csr( ch6_csr ),
.ch6_txsz( ch6_txsz ),
.ch6_adr0( ch6_adr0 ),
.ch6_adr1( ch6_adr1 ),
.ch6_am0( ch6_am0 ),
.ch6_am1( ch6_am1 ),
.pointer7( pointer7 ),
.pointer7_s( pointer7_s ),
.ch7_csr( ch7_csr ),
.ch7_txsz( ch7_txsz ),
.ch7_adr0( ch7_adr0 ),
.ch7_adr1( ch7_adr1 ),
.ch7_am0( ch7_am0 ),
.ch7_am1( ch7_am1 ),
.pointer8( pointer8 ),
.pointer8_s( pointer8_s ),
.ch8_csr( ch8_csr ),
.ch8_txsz( ch8_txsz ),
.ch8_adr0( ch8_adr0 ),
.ch8_adr1( ch8_adr1 ),
.ch8_am0( ch8_am0 ),
.ch8_am1( ch8_am1 ),
.pointer9( pointer9 ),
.pointer9_s( pointer9_s ),
.ch9_csr( ch9_csr ),
.ch9_txsz( ch9_txsz ),
.ch9_adr0( ch9_adr0 ),
.ch9_adr1( ch9_adr1 ),
.ch9_am0( ch9_am0 ),
.ch9_am1( ch9_am1 ),
.pointer10( pointer10 ),
.pointer10_s( pointer10_s ),
.ch10_csr( ch10_csr ),
.ch10_txsz( ch10_txsz ),
.ch10_adr0( ch10_adr0 ),
.ch10_adr1( ch10_adr1 ),
.ch10_am0( ch10_am0 ),
.ch10_am1( ch10_am1 ),
.pointer11( pointer11 ),
.pointer11_s( pointer11_s ),
.ch11_csr( ch11_csr ),
.ch11_txsz( ch11_txsz ),
.ch11_adr0( ch11_adr0 ),
.ch11_adr1( ch11_adr1 ),
.ch11_am0( ch11_am0 ),
.ch11_am1( ch11_am1 ),
.pointer12( pointer12 ),
.pointer12_s( pointer12_s ),
.ch12_csr( ch12_csr ),
.ch12_txsz( ch12_txsz ),
.ch12_adr0( ch12_adr0 ),
.ch12_adr1( ch12_adr1 ),
.ch12_am0( ch12_am0 ),
.ch12_am1( ch12_am1 ),
.pointer13( pointer13 ),
.pointer13_s( pointer13_s ),
.ch13_csr( ch13_csr ),
.ch13_txsz( ch13_txsz ),
.ch13_adr0( ch13_adr0 ),
.ch13_adr1( ch13_adr1 ),
.ch13_am0( ch13_am0 ),
.ch13_am1( ch13_am1 ),
.pointer14( pointer14 ),
.pointer14_s( pointer14_s ),
.ch14_csr( ch14_csr ),
.ch14_txsz( ch14_txsz ),
.ch14_adr0( ch14_adr0 ),
.ch14_adr1( ch14_adr1 ),
.ch14_am0( ch14_am0 ),
.ch14_am1( ch14_am1 ),
.pointer15( pointer15 ),
.pointer15_s( pointer15_s ),
.ch15_csr( ch15_csr ),
.ch15_txsz( ch15_txsz ),
.ch15_adr0( ch15_adr0 ),
.ch15_adr1( ch15_adr1 ),
.ch15_am0( ch15_am0 ),
.ch15_am1( ch15_am1 ),
.pointer16( pointer16 ),
.pointer16_s( pointer16_s ),
.ch16_csr( ch16_csr ),
.ch16_txsz( ch16_txsz ),
.ch16_adr0( ch16_adr0 ),
.ch16_adr1( ch16_adr1 ),
.ch16_am0( ch16_am0 ),
.ch16_am1( ch16_am1 ),
.pointer17( pointer17 ),
.pointer17_s( pointer17_s ),
.ch17_csr( ch17_csr ),
.ch17_txsz( ch17_txsz ),
.ch17_adr0( ch17_adr0 ),
.ch17_adr1( ch17_adr1 ),
.ch17_am0( ch17_am0 ),
.ch17_am1( ch17_am1 ),
.pointer18( pointer18 ),
.pointer18_s( pointer18_s ),
.ch18_csr( ch18_csr ),
.ch18_txsz( ch18_txsz ),
.ch18_adr0( ch18_adr0 ),
.ch18_adr1( ch18_adr1 ),
.ch18_am0( ch18_am0 ),
.ch18_am1( ch18_am1 ),
.pointer19( pointer19 ),
.pointer19_s( pointer19_s ),
.ch19_csr( ch19_csr ),
.ch19_txsz( ch19_txsz ),
.ch19_adr0( ch19_adr0 ),
.ch19_adr1( ch19_adr1 ),
.ch19_am0( ch19_am0 ),
.ch19_am1( ch19_am1 ),
.pointer20( pointer20 ),
.pointer20_s( pointer20_s ),
.ch20_csr( ch20_csr ),
.ch20_txsz( ch20_txsz ),
.ch20_adr0( ch20_adr0 ),
.ch20_adr1( ch20_adr1 ),
.ch20_am0( ch20_am0 ),
.ch20_am1( ch20_am1 ),
.pointer21( pointer21 ),
.pointer21_s( pointer21_s ),
.ch21_csr( ch21_csr ),
.ch21_txsz( ch21_txsz ),
.ch21_adr0( ch21_adr0 ),
.ch21_adr1( ch21_adr1 ),
.ch21_am0( ch21_am0 ),
.ch21_am1( ch21_am1 ),
.pointer22( pointer22 ),
.pointer22_s( pointer22_s ),
.ch22_csr( ch22_csr ),
.ch22_txsz( ch22_txsz ),
.ch22_adr0( ch22_adr0 ),
.ch22_adr1( ch22_adr1 ),
.ch22_am0( ch22_am0 ),
.ch22_am1( ch22_am1 ),
.pointer23( pointer23 ),
.pointer23_s( pointer23_s ),
.ch23_csr( ch23_csr ),
.ch23_txsz( ch23_txsz ),
.ch23_adr0( ch23_adr0 ),
.ch23_adr1( ch23_adr1 ),
.ch23_am0( ch23_am0 ),
.ch23_am1( ch23_am1 ),
.pointer24( pointer24 ),
.pointer24_s( pointer24_s ),
.ch24_csr( ch24_csr ),
.ch24_txsz( ch24_txsz ),
.ch24_adr0( ch24_adr0 ),
.ch24_adr1( ch24_adr1 ),
.ch24_am0( ch24_am0 ),
.ch24_am1( ch24_am1 ),
.pointer25( pointer25 ),
.pointer25_s( pointer25_s ),
.ch25_csr( ch25_csr ),
.ch25_txsz( ch25_txsz ),
.ch25_adr0( ch25_adr0 ),
.ch25_adr1( ch25_adr1 ),
.ch25_am0( ch25_am0 ),
.ch25_am1( ch25_am1 ),
.pointer26( pointer26 ),
.pointer26_s( pointer26_s ),
.ch26_csr( ch26_csr ),
.ch26_txsz( ch26_txsz ),
.ch26_adr0( ch26_adr0 ),
.ch26_adr1( ch26_adr1 ),
.ch26_am0( ch26_am0 ),
.ch26_am1( ch26_am1 ),
.pointer27( pointer27 ),
.pointer27_s( pointer27_s ),
.ch27_csr( ch27_csr ),
.ch27_txsz( ch27_txsz ),
.ch27_adr0( ch27_adr0 ),
.ch27_adr1( ch27_adr1 ),
.ch27_am0( ch27_am0 ),
.ch27_am1( ch27_am1 ),
.pointer28( pointer28 ),
.pointer28_s( pointer28_s ),
.ch28_csr( ch28_csr ),
.ch28_txsz( ch28_txsz ),
.ch28_adr0( ch28_adr0 ),
.ch28_adr1( ch28_adr1 ),
.ch28_am0( ch28_am0 ),
.ch28_am1( ch28_am1 ),
.pointer29( pointer29 ),
.pointer29_s( pointer29_s ),
.ch29_csr( ch29_csr ),
.ch29_txsz( ch29_txsz ),
.ch29_adr0( ch29_adr0 ),
.ch29_adr1( ch29_adr1 ),
.ch29_am0( ch29_am0 ),
.ch29_am1( ch29_am1 ),
.pointer30( pointer30 ),
.pointer30_s( pointer30_s ),
.ch30_csr( ch30_csr ),
.ch30_txsz( ch30_txsz ),
.ch30_adr0( ch30_adr0 ),
.ch30_adr1( ch30_adr1 ),
.ch30_am0( ch30_am0 ),
.ch30_am1( ch30_am1 ),
.ch_sel( ch_sel ),
.ndnr( ndnr ),
.pause_req( pause_req ),
.paused( paused ),
.dma_abort( dma_abort ),
.dma_busy( dma_busy ),
.dma_err( dma_err ),
.dma_done( dma_done ),
.dma_done_all( dma_done_all ),
.de_csr( de_csr ),
.de_txsz( de_txsz ),
.de_adr0( de_adr0 ),
.de_adr1( de_adr1 ),
.de_csr_we( de_csr_we ),
.de_txsz_we( de_txsz_we ),
.de_adr0_we( de_adr0_we ),
.de_adr1_we( de_adr1_we ),
.de_fetch_descr(de_fetch_descr ),
.dma_rest( dma_rest ),
.ptr_set( ptr_set )
);
// Channel Select
wb_dma_ch_sel #(pri_sel,
ch0_conf,
ch1_conf,
ch2_conf,
ch3_conf,
ch4_conf,
ch5_conf,
ch6_conf,
ch7_conf,
ch8_conf,
ch9_conf,
ch10_conf,
ch11_conf,
ch12_conf,
ch13_conf,
ch14_conf,
ch15_conf,
ch16_conf,
ch17_conf,
ch18_conf,
ch19_conf,
ch20_conf,
ch21_conf,
ch22_conf,
ch23_conf,
ch24_conf,
ch25_conf,
ch26_conf,
ch27_conf,
ch28_conf,
ch29_conf,
ch30_conf)
u1(
.clk( clk_i ),
.rst( ~rst_i ),
.req_i( dma_req ),
.ack_o( dma_ack ),
.nd_i( dma_nd ),
.pointer0( pointer0 ),
.pointer0_s( pointer0_s ),
.ch0_csr( ch0_csr ),
.ch0_txsz( ch0_txsz ),
.ch0_adr0( ch0_adr0 ),
.ch0_adr1( ch0_adr1 ),
.ch0_am0( ch0_am0 ),
.ch0_am1( ch0_am1 ),
.pointer1( pointer1 ),
.pointer1_s( pointer1_s ),
.ch1_csr( ch1_csr ),
.ch1_txsz( ch1_txsz ),
.ch1_adr0( ch1_adr0 ),
.ch1_adr1( ch1_adr1 ),
.ch1_am0( ch1_am0 ),
.ch1_am1( ch1_am1 ),
.pointer2( pointer2 ),
.pointer2_s( pointer2_s ),
.ch2_csr( ch2_csr ),
.ch2_txsz( ch2_txsz ),
.ch2_adr0( ch2_adr0 ),
.ch2_adr1( ch2_adr1 ),
.ch2_am0( ch2_am0 ),
.ch2_am1( ch2_am1 ),
.pointer3( pointer3 ),
.pointer3_s( pointer3_s ),
.ch3_csr( ch3_csr ),
.ch3_txsz( ch3_txsz ),
.ch3_adr0( ch3_adr0 ),
.ch3_adr1( ch3_adr1 ),
.ch3_am0( ch3_am0 ),
.ch3_am1( ch3_am1 ),
.pointer4( pointer4 ),
.pointer4_s( pointer4_s ),
.ch4_csr( ch4_csr ),
.ch4_txsz( ch4_txsz ),
.ch4_adr0( ch4_adr0 ),
.ch4_adr1( ch4_adr1 ),
.ch4_am0( ch4_am0 ),
.ch4_am1( ch4_am1 ),
.pointer5( pointer5 ),
.pointer5_s( pointer5_s ),
.ch5_csr( ch5_csr ),
.ch5_txsz( ch5_txsz ),
.ch5_adr0( ch5_adr0 ),
.ch5_adr1( ch5_adr1 ),
.ch5_am0( ch5_am0 ),
.ch5_am1( ch5_am1 ),
.pointer6( pointer6 ),
.pointer6_s( pointer6_s ),
.ch6_csr( ch6_csr ),
.ch6_txsz( ch6_txsz ),
.ch6_adr0( ch6_adr0 ),
.ch6_adr1( ch6_adr1 ),
.ch6_am0( ch6_am0 ),
.ch6_am1( ch6_am1 ),
.pointer7( pointer7 ),
.pointer7_s( pointer7_s ),
.ch7_csr( ch7_csr ),
.ch7_txsz( ch7_txsz ),
.ch7_adr0( ch7_adr0 ),
.ch7_adr1( ch7_adr1 ),
.ch7_am0( ch7_am0 ),
.ch7_am1( ch7_am1 ),
.pointer8( pointer8 ),
.pointer8_s( pointer8_s ),
.ch8_csr( ch8_csr ),
.ch8_txsz( ch8_txsz ),
.ch8_adr0( ch8_adr0 ),
.ch8_adr1( ch8_adr1 ),
.ch8_am0( ch8_am0 ),
.ch8_am1( ch8_am1 ),
.pointer9( pointer9 ),
.pointer9_s( pointer9_s ),
.ch9_csr( ch9_csr ),
.ch9_txsz( ch9_txsz ),
.ch9_adr0( ch9_adr0 ),
.ch9_adr1( ch9_adr1 ),
.ch9_am0( ch9_am0 ),
.ch9_am1( ch9_am1 ),
.pointer10( pointer10 ),
.pointer10_s( pointer10_s ),
.ch10_csr( ch10_csr ),
.ch10_txsz( ch10_txsz ),
.ch10_adr0( ch10_adr0 ),
.ch10_adr1( ch10_adr1 ),
.ch10_am0( ch10_am0 ),
.ch10_am1( ch10_am1 ),
.pointer11( pointer11 ),
.pointer11_s( pointer11_s ),
.ch11_csr( ch11_csr ),
.ch11_txsz( ch11_txsz ),
.ch11_adr0( ch11_adr0 ),
.ch11_adr1( ch11_adr1 ),
.ch11_am0( ch11_am0 ),
.ch11_am1( ch11_am1 ),
.pointer12( pointer12 ),
.pointer12_s( pointer12_s ),
.ch12_csr( ch12_csr ),
.ch12_txsz( ch12_txsz ),
.ch12_adr0( ch12_adr0 ),
.ch12_adr1( ch12_adr1 ),
.ch12_am0( ch12_am0 ),
.ch12_am1( ch12_am1 ),
.pointer13( pointer13 ),
.pointer13_s( pointer13_s ),
.ch13_csr( ch13_csr ),
.ch13_txsz( ch13_txsz ),
.ch13_adr0( ch13_adr0 ),
.ch13_adr1( ch13_adr1 ),
.ch13_am0( ch13_am0 ),
.ch13_am1( ch13_am1 ),
.pointer14( pointer14 ),
.pointer14_s( pointer14_s ),
.ch14_csr( ch14_csr ),
.ch14_txsz( ch14_txsz ),
.ch14_adr0( ch14_adr0 ),
.ch14_adr1( ch14_adr1 ),
.ch14_am0( ch14_am0 ),
.ch14_am1( ch14_am1 ),
.pointer15( pointer15 ),
.pointer15_s( pointer15_s ),
.ch15_csr( ch15_csr ),
.ch15_txsz( ch15_txsz ),
.ch15_adr0( ch15_adr0 ),
.ch15_adr1( ch15_adr1 ),
.ch15_am0( ch15_am0 ),
.ch15_am1( ch15_am1 ),
.pointer16( pointer16 ),
.pointer16_s( pointer16_s ),
.ch16_csr( ch16_csr ),
.ch16_txsz( ch16_txsz ),
.ch16_adr0( ch16_adr0 ),
.ch16_adr1( ch16_adr1 ),
.ch16_am0( ch16_am0 ),
.ch16_am1( ch16_am1 ),
.pointer17( pointer17 ),
.pointer17_s( pointer17_s ),
.ch17_csr( ch17_csr ),
.ch17_txsz( ch17_txsz ),
.ch17_adr0( ch17_adr0 ),
.ch17_adr1( ch17_adr1 ),
.ch17_am0( ch17_am0 ),
.ch17_am1( ch17_am1 ),
.pointer18( pointer18 ),
.pointer18_s( pointer18_s ),
.ch18_csr( ch18_csr ),
.ch18_txsz( ch18_txsz ),
.ch18_adr0( ch18_adr0 ),
.ch18_adr1( ch18_adr1 ),
.ch18_am0( ch18_am0 ),
.ch18_am1( ch18_am1 ),
.pointer19( pointer19 ),
.pointer19_s( pointer19_s ),
.ch19_csr( ch19_csr ),
.ch19_txsz( ch19_txsz ),
.ch19_adr0( ch19_adr0 ),
.ch19_adr1( ch19_adr1 ),
.ch19_am0( ch19_am0 ),
.ch19_am1( ch19_am1 ),
.pointer20( pointer20 ),
.pointer20_s( pointer20_s ),
.ch20_csr( ch20_csr ),
.ch20_txsz( ch20_txsz ),
.ch20_adr0( ch20_adr0 ),
.ch20_adr1( ch20_adr1 ),
.ch20_am0( ch20_am0 ),
.ch20_am1( ch20_am1 ),
.pointer21( pointer21 ),
.pointer21_s( pointer21_s ),
.ch21_csr( ch21_csr ),
.ch21_txsz( ch21_txsz ),
.ch21_adr0( ch21_adr0 ),
.ch21_adr1( ch21_adr1 ),
.ch21_am0( ch21_am0 ),
.ch21_am1( ch21_am1 ),
.pointer22( pointer22 ),
.pointer22_s( pointer22_s ),
.ch22_csr( ch22_csr ),
.ch22_txsz( ch22_txsz ),
.ch22_adr0( ch22_adr0 ),
.ch22_adr1( ch22_adr1 ),
.ch22_am0( ch22_am0 ),
.ch22_am1( ch22_am1 ),
.pointer23( pointer23 ),
.pointer23_s( pointer23_s ),
.ch23_csr( ch23_csr ),
.ch23_txsz( ch23_txsz ),
.ch23_adr0( ch23_adr0 ),
.ch23_adr1( ch23_adr1 ),
.ch23_am0( ch23_am0 ),
.ch23_am1( ch23_am1 ),
.pointer24( pointer24 ),
.pointer24_s( pointer24_s ),
.ch24_csr( ch24_csr ),
.ch24_txsz( ch24_txsz ),
.ch24_adr0( ch24_adr0 ),
.ch24_adr1( ch24_adr1 ),
.ch24_am0( ch24_am0 ),
.ch24_am1( ch24_am1 ),
.pointer25( pointer25 ),
.pointer25_s( pointer25_s ),
.ch25_csr( ch25_csr ),
.ch25_txsz( ch25_txsz ),
.ch25_adr0( ch25_adr0 ),
.ch25_adr1( ch25_adr1 ),
.ch25_am0( ch25_am0 ),
.ch25_am1( ch25_am1 ),
.pointer26( pointer26 ),
.pointer26_s( pointer26_s ),
.ch26_csr( ch26_csr ),
.ch26_txsz( ch26_txsz ),
.ch26_adr0( ch26_adr0 ),
.ch26_adr1( ch26_adr1 ),
.ch26_am0( ch26_am0 ),
.ch26_am1( ch26_am1 ),
.pointer27( pointer27 ),
.pointer27_s( pointer27_s ),
.ch27_csr( ch27_csr ),
.ch27_txsz( ch27_txsz ),
.ch27_adr0( ch27_adr0 ),
.ch27_adr1( ch27_adr1 ),
.ch27_am0( ch27_am0 ),
.ch27_am1( ch27_am1 ),
.pointer28( pointer28 ),
.pointer28_s( pointer28_s ),
.ch28_csr( ch28_csr ),
.ch28_txsz( ch28_txsz ),
.ch28_adr0( ch28_adr0 ),
.ch28_adr1( ch28_adr1 ),
.ch28_am0( ch28_am0 ),
.ch28_am1( ch28_am1 ),
.pointer29( pointer29 ),
.pointer29_s( pointer29_s ),
.ch29_csr( ch29_csr ),
.ch29_txsz( ch29_txsz ),
.ch29_adr0( ch29_adr0 ),
.ch29_adr1( ch29_adr1 ),
.ch29_am0( ch29_am0 ),
.ch29_am1( ch29_am1 ),
.pointer30( pointer30 ),
.pointer30_s( pointer30_s ),
.ch30_csr( ch30_csr ),
.ch30_txsz( ch30_txsz ),
.ch30_adr0( ch30_adr0 ),
.ch30_adr1( ch30_adr1 ),
.ch30_am0( ch30_am0 ),
.ch30_am1( ch30_am1 ),
.ch_sel( ch_sel ),
.ndnr( ndnr ),
.de_start( de_start ),
.ndr( ndr ),
.csr( csr ),
.pointer( pointer ),
.txsz( txsz ),
.adr0( adr0 ),
.adr1( adr1 ),
.am0( am0 ),
.am1( am1 ),
.pointer_s( pointer_s ),
.next_ch( next_ch ),
.de_ack( de_ack ),
.dma_busy( dma_busy )
);
// DMA Engine
wb_dma_de u2(
.clk( clk_i ),
.rst( ~rst_i ),
.mast0_go( mast0_go ),
.mast0_we( mast0_we ),
.mast0_adr( mast0_adr ),
.mast0_sel( mast0_sel ),
.mast0_din( mast0_dout ),
.mast0_dout( mast0_din ),
.mast0_err( mast0_err ),
.mast0_drdy( mast0_drdy ),
.mast0_wait( mast0_wait ),
.mast1_go( mast1_go ),
.mast1_we( mast1_we ),
.mast1_adr( mast1_adr ),
.mast1_sel( mast1_sel ),
.mast1_din( mast1_dout ),
.mast1_dout( mast1_din ),
.mast1_err( mast1_err ),
.mast1_drdy( mast1_drdy ),
.mast1_wait( mast1_wait ),
.de_start( de_start ),
.nd( ndr ),
.csr( csr ),
.pointer( pointer ),
.pointer_s( pointer_s ),
.txsz( txsz ),
.adr0( adr0 ),
.adr1( adr1 ),
.am0( am0 ),
.am1( am1 ),
.de_csr_we( de_csr_we ),
.de_txsz_we( de_txsz_we ),
.de_adr0_we( de_adr0_we ),
.de_adr1_we( de_adr1_we ),
.de_fetch_descr(de_fetch_descr ),
.ptr_set( ptr_set ),
.de_csr( de_csr ),
.de_txsz( de_txsz ),
.de_adr0( de_adr0 ),
.de_adr1( de_adr1 ),
.next_ch( next_ch ),
.de_ack( de_ack ),
.pause_req( pause_req ),
.paused( paused ),
.dma_abort( dma_abort ),
.dma_busy( dma_busy ),
.dma_err( dma_err ),
.dma_done( dma_done ),
.dma_done_all( dma_done_all )
);
// Wishbone Interface 0
wb_dma_wb_if #(rf_addr) u3(
.clk( clk_i ),
.rst( ~rst_i ),
.wbs_data_i( wb0s_data_i ),
.wbs_data_o( wb0s_data_o ),
.wb_addr_i( wb0_addr_i ),
.wb_sel_i( wb0_sel_i ),
.wb_we_i( wb0_we_i ),
.wb_cyc_i( wb0_cyc_i ),
.wb_stb_i( wb0_stb_i ),
.wb_ack_o( wb0_ack_o ),
.wb_err_o( wb0_err_o ),
.wb_rty_o( wb0_rty_o ),
.wbm_data_i( wb0m_data_i ),
.wbm_data_o( wb0m_data_o ),
.wb_addr_o( wb0_addr_o ),
.wb_sel_o( wb0_sel_o ),
.wb_we_o( wb0_we_o ),
.wb_cyc_o( wb0_cyc_o ),
.wb_stb_o( wb0_stb_o ),
.wb_ack_i( wb0_ack_i ),
.wb_err_i( wb0_err_i ),
.wb_rty_i( wb0_rty_i ),
.mast_go( mast0_go ),
.mast_we( mast0_we ),
.mast_adr( mast0_adr ),
.mast_sel( mast0_sel ),
.mast_din( mast0_din ),
.mast_dout( mast0_dout ),
.mast_err( mast0_err ),
.mast_drdy( mast0_drdy ),
.mast_wait( mast0_wait ),
.pt_sel_i( pt0_sel_i ),
.mast_pt_in( mast0_pt_in ),
.mast_pt_out( mast0_pt_out ),
.slv_adr( slv0_adr ),
.slv_din( slv0_din ),
.slv_dout( slv0_dout ),
.slv_re( slv0_re ),
.slv_we( slv0_we ),
.pt_sel_o( pt0_sel_o ),
.slv_pt_out( slv0_pt_out ),
.slv_pt_in( slv0_pt_in )
);
// Wishbone Interface 1
wb_dma_wb_if #(rf_addr) u4(
.clk( clk_i ),
.rst( ~rst_i ),
.wbs_data_i( wb1s_data_i ),
.wbs_data_o( wb1s_data_o ),
.wb_addr_i( wb1_addr_i ),
.wb_sel_i( wb1_sel_i ),
.wb_we_i( wb1_we_i ),
.wb_cyc_i( wb1_cyc_i ),
.wb_stb_i( wb1_stb_i ),
.wb_ack_o( wb1_ack_o ),
.wb_err_o( wb1_err_o ),
.wb_rty_o( wb1_rty_o ),
.wbm_data_i( wb1m_data_i ),
.wbm_data_o( wb1m_data_o ),
.wb_addr_o( wb1_addr_o ),
.wb_sel_o( wb1_sel_o ),
.wb_we_o( wb1_we_o ),
.wb_cyc_o( wb1_cyc_o ),
.wb_stb_o( wb1_stb_o ),
.wb_ack_i( wb1_ack_i ),
.wb_err_i( wb1_err_i ),
.wb_rty_i( wb1_rty_i ),
.mast_go( mast1_go ),
.mast_we( mast1_we ),
.mast_adr( mast1_adr ),
.mast_sel( mast1_sel ),
.mast_din( mast1_din ),
.mast_dout( mast1_dout ),
.mast_err( mast1_err ),
.mast_drdy( mast1_drdy ),
.mast_wait( mast1_wait ),
.pt_sel_i( pt1_sel_i ),
.mast_pt_in( mast1_pt_in ),
.mast_pt_out( mast1_pt_out ),
.slv_adr( slv1_adr ),
.slv_din( 32'h0 ), // Not Connected
.slv_dout( slv1_dout ), // Not Connected
.slv_re( slv1_re ), // Not Connected
.slv_we( slv1_we ), // Not Connected
.pt_sel_o( pt1_sel_o ),
.slv_pt_out( slv1_pt_out ),
.slv_pt_in( slv1_pt_in )
);
endmodule
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