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// megafunction wizard: %ALTGX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt4gxb
// ============================================================
// File Name: pcie_hip_s4gx_gen2_x4_128_serdes.v
// Megafunction Name(s):
// alt4gxb
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//alt4gxb CBX_AUTO_BLACKBOX="ALL" coreclkout_control_width=1 device_family="Stratix IV" effective_data_rate="5000 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=1 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="AUTO" gxb_powerdown_width=1 hip_enable="true" input_clock_frequency="100.0 MHz" intended_device_speed_grade="2" intended_device_variant="GX" loopback_mode="none" number_of_channels=4 number_of_quads=1 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 protocol="pcie2" rateswitch_control_width=1 receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=1 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x4" rx_channel_width=8 rx_common_mode="0.82v" rx_cru_bandwidth_type="auto" rx_cru_inclock0_period=10000 rx_cru_m_divider=0 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=1 rx_data_rate=5000 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_bonding="x4" tx_channel_width=8 tx_clkout_width=4 tx_common_mode="0.65v" tx_data_rate=5000 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=10000 tx_pll_m_divider=0 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=1 tx_slew_rate="off" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=3 cal_blk_clk coreclkout fixedclk gxb_powerdown hip_tx_clkout pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked pll_powerdown powerdn rateswitch rateswitchbaseclock reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_elecidleinfersel rx_freqlocked rx_patterndetect rx_pll_locked rx_signaldetect rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle tx_pipedeemph tx_pipemargin
//VERSION_BEGIN 10.1SP1 cbx_alt4gxb 2011:01:19:21:23:40:SJ cbx_mgl 2011:01:19:21:24:50:SJ cbx_tgx 2011:01:19:21:23:40:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = reg 14 stratixiv_hssi_calibration_block 1 stratixiv_hssi_clock_divider 1 stratixiv_hssi_cmu 1 stratixiv_hssi_pll 5 stratixiv_hssi_rx_pcs 4 stratixiv_hssi_rx_pma 4 stratixiv_hssi_tx_pcs 4 stratixiv_hssi_tx_pma 4
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=c104"} *)
module pcie_hip_s4gx_gen2_x4_128_serdes_alt4gxb_svoa
(
cal_blk_clk,
coreclkout,
fixedclk,
gxb_powerdown,
hip_tx_clkout,
pipe8b10binvpolarity,
pipedatavalid,
pipeelecidle,
pipephydonestatus,
pipestatus,
pll_inclk,
pll_locked,
pll_powerdown,
powerdn,
rateswitch,
rateswitchbaseclock,
reconfig_clk,
reconfig_fromgxb,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_ctrldetect,
rx_datain,
rx_dataout,
rx_digitalreset,
rx_elecidleinfersel,
rx_freqlocked,
rx_patterndetect,
rx_pll_locked,
rx_signaldetect,
rx_syncstatus,
tx_ctrlenable,
tx_datain,
tx_dataout,
tx_detectrxloop,
tx_digitalreset,
tx_forcedispcompliance,
tx_forceelecidle,
tx_pipedeemph,
tx_pipemargin) /* synthesis synthesis_clearbox=2 */;
input cal_blk_clk;
output [0:0] coreclkout;
input fixedclk;
input [0:0] gxb_powerdown;
output [3:0] hip_tx_clkout;
input [3:0] pipe8b10binvpolarity;
output [3:0] pipedatavalid;
output [3:0] pipeelecidle;
output [3:0] pipephydonestatus;
output [11:0] pipestatus;
input pll_inclk;
output [0:0] pll_locked;
input [0:0] pll_powerdown;
input [7:0] powerdn;
input [0:0] rateswitch;
output [0:0] rateswitchbaseclock;
input reconfig_clk;
output [16:0] reconfig_fromgxb;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [3:0] rx_cruclk;
output [3:0] rx_ctrldetect;
input [3:0] rx_datain;
output [31:0] rx_dataout;
input [0:0] rx_digitalreset;
input [11:0] rx_elecidleinfersel;
output [3:0] rx_freqlocked;
output [3:0] rx_patterndetect;
output [3:0] rx_pll_locked;
output [3:0] rx_signaldetect;
output [3:0] rx_syncstatus;
input [3:0] tx_ctrlenable;
input [31:0] tx_datain;
output [3:0] tx_dataout;
input [3:0] tx_detectrxloop;
input [0:0] tx_digitalreset;
input [3:0] tx_forcedispcompliance;
input [3:0] tx_forceelecidle;
input [3:0] tx_pipedeemph;
input [11:0] tx_pipemargin;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 cal_blk_clk;
tri0 fixedclk;
tri0 [0:0] gxb_powerdown;
tri0 [3:0] pipe8b10binvpolarity;
tri0 pll_inclk;
tri0 [0:0] pll_powerdown;
tri0 [7:0] powerdn;
tri0 [0:0] rateswitch;
tri0 reconfig_clk;
tri0 [0:0] rx_analogreset;
tri0 [3:0] rx_cruclk;
tri0 [0:0] rx_digitalreset;
tri0 [11:0] rx_elecidleinfersel;
tri0 [3:0] tx_ctrlenable;
tri0 [31:0] tx_datain;
tri0 [3:0] tx_detectrxloop;
tri0 [0:0] tx_digitalreset;
tri0 [3:0] tx_forcedispcompliance;
tri0 [3:0] tx_forceelecidle;
tri0 [3:0] tx_pipedeemph;
tri0 [11:0] tx_pipemargin;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
reg fixedclk_div0quad0c;
wire wire_fixedclk_div0quad0c_clk;
reg fixedclk_div1quad0c;
wire wire_fixedclk_div1quad0c_clk;
reg fixedclk_div2quad0c;
wire wire_fixedclk_div2quad0c_clk;
reg fixedclk_div3quad0c;
wire wire_fixedclk_div3quad0c_clk;
reg fixedclk_div4quad0c;
wire wire_fixedclk_div4quad0c_clk;
reg fixedclk_div5quad0c;
wire wire_fixedclk_div5quad0c_clk;
reg [1:0] reconfig_togxb_busy_reg;
wire [2:0] wire_rx_digitalreset_reg0c_d;
reg [2:0] rx_digitalreset_reg0c;
wire [2:0] wire_rx_digitalreset_reg0c_clk;
wire [2:0] wire_tx_digitalreset_reg0c_d;
reg [2:0] tx_digitalreset_reg0c;
wire [2:0] wire_tx_digitalreset_reg0c_clk;
wire wire_cal_blk0_nonusertocmu;
wire [1:0] wire_central_clk_div0_analogfastrefclkout;
wire [1:0] wire_central_clk_div0_analogrefclkout;
wire wire_central_clk_div0_analogrefclkpulse;
wire wire_central_clk_div0_coreclkout;
wire [99:0] wire_central_clk_div0_dprioout;
wire wire_central_clk_div0_rateswitchbaseclock;
wire wire_central_clk_div0_rateswitchdone;
wire wire_central_clk_div0_refclkout;
wire wire_cent_unit0_autospdx4configsel;
wire wire_cent_unit0_autospdx4rateswitchout;
wire wire_cent_unit0_autospdx4spdchg;
wire [1:0] wire_cent_unit0_clkdivpowerdn;
wire [599:0] wire_cent_unit0_cmudividerdprioout;
wire [1799:0] wire_cent_unit0_cmuplldprioout;
wire wire_cent_unit0_dpriodisableout;
wire wire_cent_unit0_dprioout;
wire wire_cent_unit0_phfifiox4ptrsreset;
wire [1:0] wire_cent_unit0_pllpowerdn;
wire [1:0] wire_cent_unit0_pllresetout;
wire wire_cent_unit0_quadresetout;
wire [5:0] wire_cent_unit0_rxanalogresetout;
wire [5:0] wire_cent_unit0_rxcrupowerdown;
wire [5:0] wire_cent_unit0_rxcruresetout;
wire [3:0] wire_cent_unit0_rxdigitalresetout;
wire [5:0] wire_cent_unit0_rxibpowerdown;
wire [1599:0] wire_cent_unit0_rxpcsdprioout;
wire wire_cent_unit0_rxphfifox4byteselout;
wire wire_cent_unit0_rxphfifox4rdenableout;
wire wire_cent_unit0_rxphfifox4wrclkout;
wire wire_cent_unit0_rxphfifox4wrenableout;
wire [1799:0] wire_cent_unit0_rxpmadprioout;
wire [5:0] wire_cent_unit0_txanalogresetout;
wire [3:0] wire_cent_unit0_txctrlout;
wire [31:0] wire_cent_unit0_txdataout;
wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
wire [3:0] wire_cent_unit0_txdigitalresetout;
wire [5:0] wire_cent_unit0_txobpowerdown;
wire [599:0] wire_cent_unit0_txpcsdprioout;
wire wire_cent_unit0_txphfifox4byteselout;
wire wire_cent_unit0_txphfifox4rdclkout;
wire wire_cent_unit0_txphfifox4rdenableout;
wire wire_cent_unit0_txphfifox4wrenableout;
wire [1799:0] wire_cent_unit0_txpmadprioout;
wire [3:0] wire_rx_cdr_pll0_clk;
wire [1:0] wire_rx_cdr_pll0_dataout;
wire [299:0] wire_rx_cdr_pll0_dprioout;
wire wire_rx_cdr_pll0_freqlocked;
wire wire_rx_cdr_pll0_locked;
wire wire_rx_cdr_pll0_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll1_clk;
wire [1:0] wire_rx_cdr_pll1_dataout;
wire [299:0] wire_rx_cdr_pll1_dprioout;
wire wire_rx_cdr_pll1_freqlocked;
wire wire_rx_cdr_pll1_locked;
wire wire_rx_cdr_pll1_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll2_clk;
wire [1:0] wire_rx_cdr_pll2_dataout;
wire [299:0] wire_rx_cdr_pll2_dprioout;
wire wire_rx_cdr_pll2_freqlocked;
wire wire_rx_cdr_pll2_locked;
wire wire_rx_cdr_pll2_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll3_clk;
wire [1:0] wire_rx_cdr_pll3_dataout;
wire [299:0] wire_rx_cdr_pll3_dprioout;
wire wire_rx_cdr_pll3_freqlocked;
wire wire_rx_cdr_pll3_locked;
wire wire_rx_cdr_pll3_pfdrefclkout;
wire [3:0] wire_tx_pll0_clk;
wire [299:0] wire_tx_pll0_dprioout;
wire wire_tx_pll0_locked;
wire wire_receive_pcs0_autospdrateswitchout;
wire wire_receive_pcs0_cdrctrlearlyeios;
wire wire_receive_pcs0_cdrctrllocktorefclkout;
wire wire_receive_pcs0_coreclkout;
wire [399:0] wire_receive_pcs0_dprioout;
wire [8:0] wire_receive_pcs0_hipdataout;
wire wire_receive_pcs0_hipdatavalid;
wire wire_receive_pcs0_hipelecidle;
wire wire_receive_pcs0_hipphydonestatus;
wire [2:0] wire_receive_pcs0_hipstatus;
wire wire_receive_pcs0_phfifobyteserdisableout;
wire wire_receive_pcs0_phfifoptrsresetout;
wire wire_receive_pcs0_phfifordenableout;
wire wire_receive_pcs0_phfiforesetout;
wire wire_receive_pcs0_phfifowrdisableout;
wire wire_receive_pcs0_pipestatetransdoneout;
wire wire_receive_pcs0_rateswitchout;
wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
wire wire_receive_pcs0_signaldetect;
wire wire_receive_pcs1_autospdrateswitchout;
wire wire_receive_pcs1_cdrctrlearlyeios;
wire wire_receive_pcs1_cdrctrllocktorefclkout;
wire wire_receive_pcs1_coreclkout;
wire [399:0] wire_receive_pcs1_dprioout;
wire [8:0] wire_receive_pcs1_hipdataout;
wire wire_receive_pcs1_hipdatavalid;
wire wire_receive_pcs1_hipelecidle;
wire wire_receive_pcs1_hipphydonestatus;
wire [2:0] wire_receive_pcs1_hipstatus;
wire wire_receive_pcs1_phfifobyteserdisableout;
wire wire_receive_pcs1_phfifoptrsresetout;
wire wire_receive_pcs1_phfifordenableout;
wire wire_receive_pcs1_phfiforesetout;
wire wire_receive_pcs1_phfifowrdisableout;
wire wire_receive_pcs1_pipestatetransdoneout;
wire wire_receive_pcs1_rateswitchout;
wire [19:0] wire_receive_pcs1_revparallelfdbkdata;
wire wire_receive_pcs1_signaldetect;
wire wire_receive_pcs2_autospdrateswitchout;
wire wire_receive_pcs2_cdrctrlearlyeios;
wire wire_receive_pcs2_cdrctrllocktorefclkout;
wire wire_receive_pcs2_coreclkout;
wire [399:0] wire_receive_pcs2_dprioout;
wire [8:0] wire_receive_pcs2_hipdataout;
wire wire_receive_pcs2_hipdatavalid;
wire wire_receive_pcs2_hipelecidle;
wire wire_receive_pcs2_hipphydonestatus;
wire [2:0] wire_receive_pcs2_hipstatus;
wire wire_receive_pcs2_phfifobyteserdisableout;
wire wire_receive_pcs2_phfifoptrsresetout;
wire wire_receive_pcs2_phfifordenableout;
wire wire_receive_pcs2_phfiforesetout;
wire wire_receive_pcs2_phfifowrdisableout;
wire wire_receive_pcs2_pipestatetransdoneout;
wire wire_receive_pcs2_rateswitchout;
wire [19:0] wire_receive_pcs2_revparallelfdbkdata;
wire wire_receive_pcs2_signaldetect;
wire wire_receive_pcs3_autospdrateswitchout;
wire wire_receive_pcs3_cdrctrlearlyeios;
wire wire_receive_pcs3_cdrctrllocktorefclkout;
wire wire_receive_pcs3_coreclkout;
wire [399:0] wire_receive_pcs3_dprioout;
wire [8:0] wire_receive_pcs3_hipdataout;
wire wire_receive_pcs3_hipdatavalid;
wire wire_receive_pcs3_hipelecidle;
wire wire_receive_pcs3_hipphydonestatus;
wire [2:0] wire_receive_pcs3_hipstatus;
wire wire_receive_pcs3_phfifobyteserdisableout;
wire wire_receive_pcs3_phfifoptrsresetout;
wire wire_receive_pcs3_phfifordenableout;
wire wire_receive_pcs3_phfiforesetout;
wire wire_receive_pcs3_phfifowrdisableout;
wire wire_receive_pcs3_pipestatetransdoneout;
wire wire_receive_pcs3_rateswitchout;
wire [19:0] wire_receive_pcs3_revparallelfdbkdata;
wire wire_receive_pcs3_signaldetect;
wire [7:0] wire_receive_pma0_analogtestbus;
wire wire_receive_pma0_clockout;
wire wire_receive_pma0_dataout;
wire [299:0] wire_receive_pma0_dprioout;
wire wire_receive_pma0_locktorefout;
wire [63:0] wire_receive_pma0_recoverdataout;
wire wire_receive_pma0_signaldetect;
wire [7:0] wire_receive_pma1_analogtestbus;
wire wire_receive_pma1_clockout;
wire wire_receive_pma1_dataout;
wire [299:0] wire_receive_pma1_dprioout;
wire wire_receive_pma1_locktorefout;
wire [63:0] wire_receive_pma1_recoverdataout;
wire wire_receive_pma1_signaldetect;
wire [7:0] wire_receive_pma2_analogtestbus;
wire wire_receive_pma2_clockout;
wire wire_receive_pma2_dataout;
wire [299:0] wire_receive_pma2_dprioout;
wire wire_receive_pma2_locktorefout;
wire [63:0] wire_receive_pma2_recoverdataout;
wire wire_receive_pma2_signaldetect;
wire [7:0] wire_receive_pma3_analogtestbus;
wire wire_receive_pma3_clockout;
wire wire_receive_pma3_dataout;
wire [299:0] wire_receive_pma3_dprioout;
wire wire_receive_pma3_locktorefout;
wire [63:0] wire_receive_pma3_recoverdataout;
wire wire_receive_pma3_signaldetect;
wire wire_transmit_pcs0_coreclkout;
wire [19:0] wire_transmit_pcs0_dataout;
wire [149:0] wire_transmit_pcs0_dprioout;
wire wire_transmit_pcs0_forceelecidleout;
wire [2:0] wire_transmit_pcs0_grayelecidleinferselout;
wire wire_transmit_pcs0_phfiforddisableout;
wire wire_transmit_pcs0_phfiforesetout;
wire wire_transmit_pcs0_phfifowrenableout;
wire wire_transmit_pcs0_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs0_pipepowerdownout;
wire [3:0] wire_transmit_pcs0_pipepowerstateout;
wire wire_transmit_pcs0_txdetectrx;
wire wire_transmit_pcs1_coreclkout;
wire [19:0] wire_transmit_pcs1_dataout;
wire [149:0] wire_transmit_pcs1_dprioout;
wire wire_transmit_pcs1_forceelecidleout;
wire [2:0] wire_transmit_pcs1_grayelecidleinferselout;
wire wire_transmit_pcs1_phfiforddisableout;
wire wire_transmit_pcs1_phfiforesetout;
wire wire_transmit_pcs1_phfifowrenableout;
wire wire_transmit_pcs1_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs1_pipepowerdownout;
wire [3:0] wire_transmit_pcs1_pipepowerstateout;
wire wire_transmit_pcs1_txdetectrx;
wire wire_transmit_pcs2_coreclkout;
wire [19:0] wire_transmit_pcs2_dataout;
wire [149:0] wire_transmit_pcs2_dprioout;
wire wire_transmit_pcs2_forceelecidleout;
wire [2:0] wire_transmit_pcs2_grayelecidleinferselout;
wire wire_transmit_pcs2_phfiforddisableout;
wire wire_transmit_pcs2_phfiforesetout;
wire wire_transmit_pcs2_phfifowrenableout;
wire wire_transmit_pcs2_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs2_pipepowerdownout;
wire [3:0] wire_transmit_pcs2_pipepowerstateout;
wire wire_transmit_pcs2_txdetectrx;
wire wire_transmit_pcs3_coreclkout;
wire [19:0] wire_transmit_pcs3_dataout;
wire [149:0] wire_transmit_pcs3_dprioout;
wire wire_transmit_pcs3_forceelecidleout;
wire [2:0] wire_transmit_pcs3_grayelecidleinferselout;
wire wire_transmit_pcs3_phfiforddisableout;
wire wire_transmit_pcs3_phfiforesetout;
wire wire_transmit_pcs3_phfifowrenableout;
wire wire_transmit_pcs3_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs3_pipepowerdownout;
wire [3:0] wire_transmit_pcs3_pipepowerstateout;
wire wire_transmit_pcs3_txdetectrx;
wire wire_transmit_pma0_clockout;
wire wire_transmit_pma0_dataout;
wire [299:0] wire_transmit_pma0_dprioout;
wire wire_transmit_pma0_rxdetectvalidout;
wire wire_transmit_pma0_rxfoundout;
wire wire_transmit_pma1_clockout;
wire wire_transmit_pma1_dataout;
wire [299:0] wire_transmit_pma1_dprioout;
wire wire_transmit_pma1_rxdetectvalidout;
wire wire_transmit_pma1_rxfoundout;
wire wire_transmit_pma2_clockout;
wire wire_transmit_pma2_dataout;
wire [299:0] wire_transmit_pma2_dprioout;
wire wire_transmit_pma2_rxdetectvalidout;
wire wire_transmit_pma2_rxfoundout;
wire wire_transmit_pma3_clockout;
wire wire_transmit_pma3_dataout;
wire [299:0] wire_transmit_pma3_dprioout;
wire wire_transmit_pma3_rxdetectvalidout;
wire wire_transmit_pma3_rxfoundout;
wire cal_blk_powerdown;
wire [0:0] cent_unit_clkdivpowerdn;
wire [599:0] cent_unit_cmudividerdprioout;
wire [1799:0] cent_unit_cmuplldprioout;
wire [1:0] cent_unit_pllpowerdn;
wire [1:0] cent_unit_pllresetout;
wire [0:0] cent_unit_quadresetout;
wire [5:0] cent_unit_rxcrupowerdn;
wire [5:0] cent_unit_rxibpowerdn;
wire [1599:0] cent_unit_rxpcsdprioin;
wire [1599:0] cent_unit_rxpcsdprioout;
wire [1799:0] cent_unit_rxpmadprioin;
wire [1799:0] cent_unit_rxpmadprioout;
wire [1199:0] cent_unit_tx_dprioin;
wire [31:0] cent_unit_tx_xgmdataout;
wire [3:0] cent_unit_txctrlout;
wire [5:0] cent_unit_txdetectrxpowerdn;
wire [599:0] cent_unit_txdprioout;
wire [5:0] cent_unit_txobpowerdn;
wire [1799:0] cent_unit_txpmadprioin;
wire [1799:0] cent_unit_txpmadprioout;
wire [3:0] clk_div_clk0in;
wire [599:0] clk_div_cmudividerdprioin;
wire [1:0] cmu_analogfastrefclkout;
wire [1:0] cmu_analogrefclkout;
wire [0:0] cmu_analogrefclkpulse;
wire [0:0] coreclkout_wire;
wire [5:0] fixedclk_div_in;
wire [0:0] fixedclk_enable;
wire [5:0] fixedclk_fast;
wire [5:0] fixedclk_in;
wire [0:0] fixedclk_sel;
wire [5:0] fixedclk_to_cmu;
wire [0:0] int_autospdx4configsel;
wire [0:0] int_autospdx4rateswitchout;
wire [0:0] int_autospdx4spdchg;
wire [3:0] int_hipautospdrateswitchout;
wire [0:0] int_hiprateswtichdone;
wire [0:0] int_phfifiox4ptrsreset;
wire [3:0] int_pipeenrevparallellpbkfromtx;
wire [0:0] int_rateswitch;
wire [11:0] int_rx_autospdxnconfigsel;
wire [11:0] int_rx_autospdxnspdchg;
wire [3:0] int_rx_coreclkout;
wire [0:0] int_rx_digitalreset_reg;
wire [11:0] int_rx_phfifioxnptrsreset;
wire [3:0] int_rx_phfifobyteserdisable;
wire [3:0] int_rx_phfifoptrsresetout;
wire [3:0] int_rx_phfifordenableout;
wire [3:0] int_rx_phfiforesetout;
wire [3:0] int_rx_phfifowrdisableout;
wire [11:0] int_rx_phfifoxnbytesel;
wire [11:0] int_rx_phfifoxnrdenable;
wire [11:0] int_rx_phfifoxnwrclk;
wire [11:0] int_rx_phfifoxnwrenable;
wire [3:0] int_rx_rateswitchout;
wire [0:0] int_rxcoreclk;
wire [3:0] int_rxpcs_cdrctrlearlyeios;
wire [0:0] int_rxphfifordenable;
wire [0:0] int_rxphfiforeset;
wire [0:0] int_rxphfifox4byteselout;
wire [0:0] int_rxphfifox4rdenableout;
wire [0:0] int_rxphfifox4wrclkout;
wire [0:0] int_rxphfifox4wrenableout;
wire [3:0] int_tx_coreclkout;
wire [0:0] int_tx_digitalreset_reg;
wire [11:0] int_tx_phfifioxnptrsreset;
wire [3:0] int_tx_phfiforddisableout;
wire [3:0] int_tx_phfiforesetout;
wire [3:0] int_tx_phfifowrenableout;
wire [11:0] int_tx_phfifoxnbytesel;
wire [11:0] int_tx_phfifoxnrdclk;
wire [11:0] int_tx_phfifoxnrdenable;
wire [11:0] int_tx_phfifoxnwrenable;
wire [0:0] int_txcoreclk;
wire [0:0] int_txphfiforddisable;
wire [0:0] int_txphfiforeset;
wire [0:0] int_txphfifowrenable;
wire [0:0] int_txphfifox4byteselout;
wire [0:0] int_txphfifox4rdclkout;
wire [0:0] int_txphfifox4rdenableout;
wire [0:0] int_txphfifox4wrenableout;
wire [0:0] nonusertocmu_out;
wire [3:0] pipedatavalid_out;
wire [3:0] pipeelecidle_out;
wire [9:0] pll0_clkin;
wire [299:0] pll0_dprioin;
wire [299:0] pll0_dprioout;
wire [3:0] pll0_out;
wire [7:0] pll_ch_dataout_wire;
wire [1199:0] pll_ch_dprioout;
wire [1799:0] pll_cmuplldprioout;
wire [0:0] pll_inclk_wire;
wire [0:0] pll_locked_out;
wire [1:0] pllpowerdn_in;
wire [1:0] pllreset_in;
wire [0:0] reconfig_togxb_busy;
wire [0:0] reconfig_togxb_disable;
wire [0:0] reconfig_togxb_in;
wire [0:0] reconfig_togxb_load;
wire [0:0] refclk_pma;
wire [5:0] rx_analogreset_in;
wire [5:0] rx_analogreset_out;
wire [39:0] rx_cruclk_in;
wire [15:0] rx_deserclock_in;
wire [3:0] rx_digitalreset_in;
wire [3:0] rx_digitalreset_out;
wire [3:0] rx_enapatternalign;
wire [3:0] rx_freqlocked_wire;
wire [3:0] rx_locktodata;
wire [3:0] rx_locktodata_wire;
wire [3:0] rx_locktorefclk_wire;
wire [31:0] rx_out_wire;
wire [7:0] rx_pcs_rxfound_wire;
wire [1599:0] rx_pcsdprioin_wire;
wire [1599:0] rx_pcsdprioout;
wire [3:0] rx_phfifordenable;
wire [3:0] rx_phfiforeset;
wire [3:0] rx_phfifowrdisable;
wire [3:0] rx_pipestatetransdoneout;
wire [3:0] rx_pldcruclk_in;
wire [15:0] rx_pll_clkout;
wire [3:0] rx_pll_pfdrefclkout_wire;
wire [3:0] rx_plllocked_wire;
wire [67:0] rx_pma_analogtestbus;
wire [3:0] rx_pma_clockout;
wire [3:0] rx_pma_dataout;
wire [3:0] rx_pma_locktorefout;
wire [79:0] rx_pma_recoverdataout_wire;
wire [1799:0] rx_pmadprioin_wire;
wire [1799:0] rx_pmadprioout;
wire [3:0] rx_powerdown;
wire [5:0] rx_powerdown_in;
wire [3:0] rx_prbscidenable;
wire [79:0] rx_revparallelfdbkdata;
wire [3:0] rx_rmfiforeset;
wire [5:0] rx_rxcruresetout;
wire [3:0] rx_signaldetect_wire;
wire [3:0] rx_signaldetectout_wire;
wire [0:0] rxphfifowrdisable;
wire [1799:0] rxpll_dprioin;
wire [5:0] tx_analogreset_out;
wire [3:0] tx_clkout_int_wire;
wire [31:0] tx_datain_wire;
wire [79:0] tx_dataout_pcs_to_pma;
wire [3:0] tx_digitalreset_in;
wire [3:0] tx_digitalreset_out;
wire [1199:0] tx_dprioin_wire;
wire [3:0] tx_invpolarity;
wire [3:0] tx_localrefclk;
wire [3:0] tx_pcs_forceelecidleout;
wire [3:0] tx_phfiforeset;
wire [7:0] tx_pipepowerdownout;
wire [15:0] tx_pipepowerstateout;
wire [3:0] tx_pipeswing;
wire [1799:0] tx_pmadprioin_wire;
wire [1799:0] tx_pmadprioout;
wire [3:0] tx_revparallellpbken;
wire [3:0] tx_rxdetectvalidout;
wire [3:0] tx_rxfoundout;
wire [599:0] tx_txdprioout;
wire [3:0] txdetectrxout;
wire [0:0] w_cent_unit_dpriodisableout1w;
// synopsys translate_off
initial
fixedclk_div0quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div0quad0c_clk)
fixedclk_div0quad0c <= (~ fixedclk_div_in[0]);
assign
wire_fixedclk_div0quad0c_clk = fixedclk_in[0];
// synopsys translate_off
initial
fixedclk_div1quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div1quad0c_clk)
fixedclk_div1quad0c <= (~ fixedclk_div_in[1]);
assign
wire_fixedclk_div1quad0c_clk = fixedclk_in[1];
// synopsys translate_off
initial
fixedclk_div2quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div2quad0c_clk)
fixedclk_div2quad0c <= (~ fixedclk_div_in[2]);
assign
wire_fixedclk_div2quad0c_clk = fixedclk_in[2];
// synopsys translate_off
initial
fixedclk_div3quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div3quad0c_clk)
fixedclk_div3quad0c <= (~ fixedclk_div_in[3]);
assign
wire_fixedclk_div3quad0c_clk = fixedclk_in[3];
// synopsys translate_off
initial
fixedclk_div4quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div4quad0c_clk)
fixedclk_div4quad0c <= (~ fixedclk_div_in[4]);
assign
wire_fixedclk_div4quad0c_clk = fixedclk_in[4];
// synopsys translate_off
initial
fixedclk_div5quad0c = 0;
// synopsys translate_on
always @ ( posedge wire_fixedclk_div5quad0c_clk)
fixedclk_div5quad0c <= (~ fixedclk_div_in[5]);
assign
wire_fixedclk_div5quad0c_clk = fixedclk_in[5];
// synopsys translate_off
initial
reconfig_togxb_busy_reg = 0;
// synopsys translate_on
always @ ( negedge fixedclk)
reconfig_togxb_busy_reg <= {reconfig_togxb_busy_reg[0], reconfig_togxb_busy};
// synopsys translate_off
initial
rx_digitalreset_reg0c[0:0] = 0;
// synopsys translate_on
always @ ( posedge wire_rx_digitalreset_reg0c_clk[0:0])
rx_digitalreset_reg0c[0:0] <= wire_rx_digitalreset_reg0c_d[0:0];
// synopsys translate_off
initial
rx_digitalreset_reg0c[1:1] = 0;
// synopsys translate_on
always @ ( posedge wire_rx_digitalreset_reg0c_clk[1:1])
rx_digitalreset_reg0c[1:1] <= wire_rx_digitalreset_reg0c_d[1:1];
// synopsys translate_off
initial
rx_digitalreset_reg0c[2:2] = 0;
// synopsys translate_on
always @ ( posedge wire_rx_digitalreset_reg0c_clk[2:2])
rx_digitalreset_reg0c[2:2] <= wire_rx_digitalreset_reg0c_d[2:2];
assign
wire_rx_digitalreset_reg0c_d = {rx_digitalreset_reg0c[1:0], rx_digitalreset[0]};
assign
wire_rx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
// synopsys translate_off
initial
tx_digitalreset_reg0c[0:0] = 0;
// synopsys translate_on
always @ ( posedge wire_tx_digitalreset_reg0c_clk[0:0])
tx_digitalreset_reg0c[0:0] <= wire_tx_digitalreset_reg0c_d[0:0];
// synopsys translate_off
initial
tx_digitalreset_reg0c[1:1] = 0;
// synopsys translate_on
always @ ( posedge wire_tx_digitalreset_reg0c_clk[1:1])
tx_digitalreset_reg0c[1:1] <= wire_tx_digitalreset_reg0c_d[1:1];
// synopsys translate_off
initial
tx_digitalreset_reg0c[2:2] = 0;
// synopsys translate_on
always @ ( posedge wire_tx_digitalreset_reg0c_clk[2:2])
tx_digitalreset_reg0c[2:2] <= wire_tx_digitalreset_reg0c_d[2:2];
assign
wire_tx_digitalreset_reg0c_d = {tx_digitalreset_reg0c[1:0], tx_digitalreset[0]};
assign
wire_tx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
stratixiv_hssi_calibration_block cal_blk0
(
.calibrationstatus(),
.clk(cal_blk_clk),
.enabletestbus(1'b1),
.nonusertocmu(wire_cal_blk0_nonusertocmu),
.powerdn(cal_blk_powerdown)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.testctrl(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
stratixiv_hssi_clock_divider central_clk_div0
(
.analogfastrefclkout(wire_central_clk_div0_analogfastrefclkout),
.analogfastrefclkoutshifted(),
.analogrefclkout(wire_central_clk_div0_analogrefclkout),
.analogrefclkoutshifted(),
.analogrefclkpulse(wire_central_clk_div0_analogrefclkpulse),
.analogrefclkpulseshifted(),
.clk0in(clk_div_clk0in[3:0]),
.coreclkout(wire_central_clk_div0_coreclkout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(cent_unit_cmudividerdprioout[499:400]),
.dprioout(wire_central_clk_div0_dprioout),
.powerdn(cent_unit_clkdivpowerdn[0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitch(int_autospdx4rateswitchout[0]),
.rateswitchbaseclock(wire_central_clk_div0_rateswitchbaseclock),
.rateswitchdone(wire_central_clk_div0_rateswitchdone),
.rateswitchout(),
.refclkout(wire_central_clk_div0_refclkout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1in({4{1'b0}}),
.rateswitchbaseclkin({2{1'b0}}),
.rateswitchdonein({2{1'b0}}),
.refclkdig(1'b0),
.refclkin({2{1'b0}}),
.vcobypassin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
central_clk_div0.divide_by = 5,
central_clk_div0.divider_type = "CENTRAL_ENHANCED",
central_clk_div0.effective_data_rate = "5000 Mbps",
central_clk_div0.enable_dynamic_divider = "true",
central_clk_div0.enable_refclk_out = "true",
central_clk_div0.inclk_select = 0,
central_clk_div0.logical_channel_address = 0,
central_clk_div0.pre_divide_by = 1,
central_clk_div0.refclkin_select = 0,
central_clk_div0.select_local_rate_switch_base_clock = "true",
central_clk_div0.select_local_rate_switch_done = "true",
central_clk_div0.select_local_refclk = "true",
central_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
central_clk_div0.sim_analogrefclkout_phase_shift = 0,
central_clk_div0.sim_coreclkout_phase_shift = 0,
central_clk_div0.sim_refclkout_phase_shift = 0,
central_clk_div0.use_coreclk_out_post_divider = "false",
central_clk_div0.use_refclk_post_divider = "false",
central_clk_div0.use_vco_bypass = "false",
central_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
stratixiv_hssi_cmu cent_unit0
(
.adet({4{1'b0}}),
.alignstatus(),
.autospdx4configsel(wire_cent_unit0_autospdx4configsel),
.autospdx4rateswitchout(wire_cent_unit0_autospdx4rateswitchout),
.autospdx4spdchg(wire_cent_unit0_autospdx4spdchg),
.clkdivpowerdn(wire_cent_unit0_clkdivpowerdn),
.cmudividerdprioin({clk_div_cmudividerdprioin[599:0]}),
.cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
.cmuplldprioin(pll_cmuplldprioout[1799:0]),
.cmuplldprioout(wire_cent_unit0_cmuplldprioout),
.digitaltestout(),
.dpclk(reconfig_clk),
.dpriodisable(reconfig_togxb_disable),
.dpriodisableout(wire_cent_unit0_dpriodisableout),
.dprioin(reconfig_togxb_in),
.dprioload(reconfig_togxb_load),
.dpriooe(),
.dprioout(wire_cent_unit0_dprioout),
.enabledeskew(),
.extra10gout(),
.fiforesetrd(),
.fixedclk({{2{1'b0}}, fixedclk_to_cmu[3:0]}),
.lccmutestbus(),
.nonuserfromcal(nonusertocmu_out[0]),
.phfifiox4ptrsreset(wire_cent_unit0_phfifiox4ptrsreset),
.pllpowerdn(wire_cent_unit0_pllpowerdn),
.pllresetout(wire_cent_unit0_pllresetout),
.quadreset(gxb_powerdown[0]),
.quadresetout(wire_cent_unit0_quadresetout),
.rateswitch(int_rateswitch[0]),
.rateswitchdonein(int_hiprateswtichdone[0]),
.rdalign({4{1'b0}}),
.rdenablesync(1'b0),
.recovclk(1'b0),
.refclkdividerdprioin({2{1'b0}}),
.refclkdividerdprioout(),
.rxadcepowerdown(),
.rxadceresetout(),
.rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
.rxanalogresetout(wire_cent_unit0_rxanalogresetout),
.rxclk(refclk_pma[0]),
.rxcoreclk(int_rxcoreclk[0]),
.rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
.rxcruresetout(wire_cent_unit0_rxcruresetout),
.rxctrl({4{1'b0}}),
.rxctrlout(),
.rxdatain({32{1'b0}}),
.rxdataout(),
.rxdatavalid({4{1'b0}}),
.rxdigitalreset({rx_digitalreset_in[3:0]}),
.rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
.rxibpowerdown(wire_cent_unit0_rxibpowerdown),
.rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
.rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
.rxphfifordenable(int_rxphfifordenable[0]),
.rxphfiforeset(int_rxphfiforeset[0]),
.rxphfifowrdisable(rxphfifowrdisable[0]),
.rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
.rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
.rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
.rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
.rxpmadprioin({cent_unit_rxpmadprioin[1799:0]}),
.rxpmadprioout(wire_cent_unit0_rxpmadprioout),
.rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
.rxrunningdisp({4{1'b0}}),
.scanout(),
.syncstatus({4{1'b0}}),
.testout(),
.txanalogresetout(wire_cent_unit0_txanalogresetout),
.txclk(refclk_pma[0]),
.txcoreclk(int_txcoreclk[0]),
.txctrl({4{1'b0}}),
.txctrlout(wire_cent_unit0_txctrlout),
.txdatain({32{1'b0}}),
.txdataout(wire_cent_unit0_txdataout),
.txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
.txdigitalreset({tx_digitalreset_in[3:0]}),
.txdigitalresetout(wire_cent_unit0_txdigitalresetout),
.txdividerpowerdown(),
.txobpowerdown(wire_cent_unit0_txobpowerdown),
.txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
.txpcsdprioout(wire_cent_unit0_txpcsdprioout),
.txphfiforddisable(int_txphfiforddisable[0]),
.txphfiforeset(int_txphfiforeset[0]),
.txphfifowrenable(int_txphfifowrenable[0]),
.txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
.txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
.txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
.txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
.txpllreset({{1{1'b0}}, pll_powerdown[0]}),
.txpmadprioin({cent_unit_txpmadprioin[1799:0]}),
.txpmadprioout(wire_cent_unit0_txpmadprioout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({7{1'b0}}),
.lccmurtestbussel({3{1'b0}}),
.pmacramtest(1'b0),
.scanclk(1'b0),
.scanin({23{1'b0}}),
.scanmode(1'b0),
.scanshift(1'b0),
.testin({10000{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
cent_unit0.auto_spd_phystatus_notify_count = 14,
cent_unit0.bonded_quad_mode = "none",
cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
cent_unit0.in_xaui_mode = "false",
cent_unit0.offset_all_errors_align = "false",
cent_unit0.pipe_auto_speed_nego_enable = "true",
cent_unit0.pipe_freq_scale_mode = "Frequency",
cent_unit0.pma_done_count = 249950,
cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
cent_unit0.rx0_auto_spd_self_switch_enable = "false",
cent_unit0.rx0_channel_bonding = "x4",
cent_unit0.rx0_clk1_mux_select = "recovered clock",
cent_unit0.rx0_clk2_mux_select = "digital reference clock",
cent_unit0.rx0_ph_fifo_reg_mode = "true",
cent_unit0.rx0_rd_clk_mux_select = "int clock",
cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
cent_unit0.rx0_use_double_data_mode = "false",
cent_unit0.tx0_auto_spd_self_switch_enable = "false",
cent_unit0.tx0_channel_bonding = "x4",
cent_unit0.tx0_ph_fifo_reg_mode = "true",
cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
cent_unit0.tx0_use_double_data_mode = "false",
cent_unit0.tx0_wr_clk_mux_select = "int_clk",
cent_unit0.use_deskew_fifo = "false",
cent_unit0.vcceh_voltage = "Auto",
cent_unit0.lpm_type = "stratixiv_hssi_cmu";
stratixiv_hssi_pll rx_cdr_pll0
(
.areset(rx_rxcruresetout[0]),
.clk(wire_rx_cdr_pll0_clk),
.datain(rx_pma_dataout[0]),
.dataout(wire_rx_cdr_pll0_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[299:0]),
.dprioout(wire_rx_cdr_pll0_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[0]),
.freqlocked(wire_rx_cdr_pll0_freqlocked),
.inclk({rx_cruclk_in[9:0]}),
.locked(wire_rx_cdr_pll0_locked),
.locktorefclk(rx_pma_locktorefout[0]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[0]),
.rateswitch(int_hipautospdrateswitchout[0]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll0.bandwidth_type = "Auto",
rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
rx_cdr_pll0.dprio_config_mode = 6'h00,
rx_cdr_pll0.effective_data_rate = "5000 Mbps",
rx_cdr_pll0.enable_dynamic_divider = "true",
rx_cdr_pll0.fast_lock_control = "false",
rx_cdr_pll0.inclk0_input_period = 10000,
rx_cdr_pll0.input_clock_frequency = "100.0 MHz",
rx_cdr_pll0.m = 25,
rx_cdr_pll0.n = 1,
rx_cdr_pll0.pfd_clk_select = 0,
rx_cdr_pll0.pll_type = "RX CDR",
rx_cdr_pll0.use_refclk_pin = "false",
rx_cdr_pll0.vco_post_scale = 1,
rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll1
(
.areset(rx_rxcruresetout[1]),
.clk(wire_rx_cdr_pll1_clk),
.datain(rx_pma_dataout[1]),
.dataout(wire_rx_cdr_pll1_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[599:300]),
.dprioout(wire_rx_cdr_pll1_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[1]),
.freqlocked(wire_rx_cdr_pll1_freqlocked),
.inclk({rx_cruclk_in[19:10]}),
.locked(wire_rx_cdr_pll1_locked),
.locktorefclk(rx_pma_locktorefout[1]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll1_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[1]),
.rateswitch(int_hipautospdrateswitchout[1]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll1.bandwidth_type = "Auto",
rx_cdr_pll1.channel_num = ((starting_channel_number + 1) % 4),
rx_cdr_pll1.dprio_config_mode = 6'h00,
rx_cdr_pll1.effective_data_rate = "5000 Mbps",
rx_cdr_pll1.enable_dynamic_divider = "true",
rx_cdr_pll1.fast_lock_control = "false",
rx_cdr_pll1.inclk0_input_period = 10000,
rx_cdr_pll1.input_clock_frequency = "100.0 MHz",
rx_cdr_pll1.m = 25,
rx_cdr_pll1.n = 1,
rx_cdr_pll1.pfd_clk_select = 0,
rx_cdr_pll1.pll_type = "RX CDR",
rx_cdr_pll1.use_refclk_pin = "false",
rx_cdr_pll1.vco_post_scale = 1,
rx_cdr_pll1.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll2
(
.areset(rx_rxcruresetout[2]),
.clk(wire_rx_cdr_pll2_clk),
.datain(rx_pma_dataout[2]),
.dataout(wire_rx_cdr_pll2_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[899:600]),
.dprioout(wire_rx_cdr_pll2_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[2]),
.freqlocked(wire_rx_cdr_pll2_freqlocked),
.inclk({rx_cruclk_in[29:20]}),
.locked(wire_rx_cdr_pll2_locked),
.locktorefclk(rx_pma_locktorefout[2]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll2_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[2]),
.rateswitch(int_hipautospdrateswitchout[2]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll2.bandwidth_type = "Auto",
rx_cdr_pll2.channel_num = ((starting_channel_number + 2) % 4),
rx_cdr_pll2.dprio_config_mode = 6'h00,
rx_cdr_pll2.effective_data_rate = "5000 Mbps",
rx_cdr_pll2.enable_dynamic_divider = "true",
rx_cdr_pll2.fast_lock_control = "false",
rx_cdr_pll2.inclk0_input_period = 10000,
rx_cdr_pll2.input_clock_frequency = "100.0 MHz",
rx_cdr_pll2.m = 25,
rx_cdr_pll2.n = 1,
rx_cdr_pll2.pfd_clk_select = 0,
rx_cdr_pll2.pll_type = "RX CDR",
rx_cdr_pll2.use_refclk_pin = "false",
rx_cdr_pll2.vco_post_scale = 1,
rx_cdr_pll2.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll3
(
.areset(rx_rxcruresetout[3]),
.clk(wire_rx_cdr_pll3_clk),
.datain(rx_pma_dataout[3]),
.dataout(wire_rx_cdr_pll3_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[1199:900]),
.dprioout(wire_rx_cdr_pll3_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[3]),
.freqlocked(wire_rx_cdr_pll3_freqlocked),
.inclk({rx_cruclk_in[39:30]}),
.locked(wire_rx_cdr_pll3_locked),
.locktorefclk(rx_pma_locktorefout[3]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll3_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[3]),
.rateswitch(int_hipautospdrateswitchout[3]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll3.bandwidth_type = "Auto",
rx_cdr_pll3.channel_num = ((starting_channel_number + 3) % 4),
rx_cdr_pll3.dprio_config_mode = 6'h00,
rx_cdr_pll3.effective_data_rate = "5000 Mbps",
rx_cdr_pll3.enable_dynamic_divider = "true",
rx_cdr_pll3.fast_lock_control = "false",
rx_cdr_pll3.inclk0_input_period = 10000,
rx_cdr_pll3.input_clock_frequency = "100.0 MHz",
rx_cdr_pll3.m = 25,
rx_cdr_pll3.n = 1,
rx_cdr_pll3.pfd_clk_select = 0,
rx_cdr_pll3.pll_type = "RX CDR",
rx_cdr_pll3.use_refclk_pin = "false",
rx_cdr_pll3.vco_post_scale = 1,
rx_cdr_pll3.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll tx_pll0
(
.areset(pllreset_in[0]),
.clk(wire_tx_pll0_clk),
.dataout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(pll0_dprioin[299:0]),
.dprioout(wire_tx_pll0_dprioout),
.freqlocked(),
.inclk({pll0_clkin[9:0]}),
.locked(wire_tx_pll0_locked),
.pfdfbclkout(),
.pfdrefclkout(),
.powerdown(pllpowerdn_in[0]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datain(1'b0),
.earlyeios(1'b0),
.extra10gin({6{1'b0}}),
.locktorefclk(1'b1),
.pfdfbclk(1'b0),
.rateswitch(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
tx_pll0.bandwidth_type = "High",
tx_pll0.channel_num = 4,
tx_pll0.dprio_config_mode = 6'h00,
tx_pll0.inclk0_input_period = 10000,
tx_pll0.input_clock_frequency = "100.0 MHz",
tx_pll0.logical_tx_pll_number = 0,
tx_pll0.m = 25,
tx_pll0.n = 1,
tx_pll0.pfd_clk_select = 0,
tx_pll0.pfd_fb_select = "internal",
tx_pll0.pll_type = "CMU",
tx_pll0.use_refclk_pin = "false",
tx_pll0.vco_post_scale = 1,
tx_pll0.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_rx_pcs receive_pcs0
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs0_autospdrateswitchout),
.autospdspdchgout(),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[2:0]),
.autospdxnspdchg(int_rx_autospdxnspdchg[2:0]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs0_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
.clkout(),
.coreclkout(wire_receive_pcs0_coreclkout),
.ctrldetect(),
.datain(rx_pma_recoverdataout_wire[19:0]),
.dataout(),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[0]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[399:0]),
.dprioout(wire_receive_pcs0_dprioout),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[0]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hip8b10binvpolarity(pipe8b10binvpolarity[0]),
.hipdataout(wire_receive_pcs0_hipdataout),
.hipdatavalid(wire_receive_pcs0_hipdatavalid),
.hipelecidle(wire_receive_pcs0_hipelecidle),
.hipelecidleinfersel({3{1'b0}}),
.hipphydonestatus(wire_receive_pcs0_hipphydonestatus),
.hippowerdown(powerdn[1:0]),
.hiprateswitch(rateswitch[0]),
.hipstatus(wire_receive_pcs0_hipstatus),
.invpol(1'b0),
.iqpphfifobyteselout(),
.iqpphfifoptrsresetout(),
.iqpphfifordenableout(),
.iqpphfifowrclkout(),
.iqpphfifowrenableout(),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs0_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs0_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[0]),
.phfifordenableout(wire_receive_pcs0_phfifordenableout),
.phfiforeset(rx_phfiforeset[0]),
.phfiforesetout(wire_receive_pcs0_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[0]),
.phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[2:0]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[2:0]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[2:0]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[2:0]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[2:0]),
.pipebufferstat(),
.pipedatavalid(),
.pipeelecidle(),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[0]),
.pipephydonestatus(),
.pipepowerdown(tx_pipepowerdownout[1:0]),
.pipepowerstate(tx_pipepowerstateout[3:0]),
.pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
.pipestatus(),
.prbscidenable(rx_prbscidenable[0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(wire_receive_pcs0_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[0]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[0]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[0]),
.rxfound(rx_pcs_rxfound_wire[1:0]),
.signaldetect(wire_receive_pcs0_signaldetect),
.signaldetected(rx_signaldetect_wire[0]),
.syncstatus(),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.coreclk(1'b0),
.elecidleinfersel({3{1'b0}}),
.grayelecidleinferselfromtx({3{1'b0}}),
.iqpautospdxnspgchg({2{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnptrsreset({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrclk({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pipe8b10binvpolarity(1'b0),
.pmatestbusin({8{1'b0}}),
.powerdn({2{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs0.align_pattern = "0101111100",
receive_pcs0.align_pattern_length = 10,
receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs0.allow_align_polarity_inversion = "false",
receive_pcs0.allow_pipe_polarity_inversion = "true",
receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs0.auto_spd_phystatus_notify_count = 14,
receive_pcs0.auto_spd_self_switch_enable = "false",
receive_pcs0.bit_slip_enable = "false",
receive_pcs0.byte_order_double_data_mode_mask_enable = "false",
receive_pcs0.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs0.byte_order_mode = "none",
receive_pcs0.byte_order_pad_pattern = "0",
receive_pcs0.byte_order_pattern = "0",
receive_pcs0.byte_order_pld_ctrl_enable = "false",
receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs0.cdrctrl_cid_mode_enable = "true",
receive_pcs0.cdrctrl_enable = "true",
receive_pcs0.cdrctrl_rxvalid_mask = "true",
receive_pcs0.channel_bonding = "x4",
receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
receive_pcs0.channel_width = 8,
receive_pcs0.clk1_mux_select = "recovered clock",
receive_pcs0.clk2_mux_select = "digital reference clock",
receive_pcs0.core_clock_0ppm = "false",
receive_pcs0.datapath_low_latency_mode = "false",
receive_pcs0.datapath_protocol = "pipe",
receive_pcs0.dec_8b_10b_compatibility_mode = "true",
receive_pcs0.dec_8b_10b_mode = "normal",
receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs0.deskew_pattern = "0",
receive_pcs0.disable_auto_idle_insertion = "false",
receive_pcs0.disable_running_disp_in_word_align = "false",
receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs0.dprio_config_mode = 6'h01,
receive_pcs0.elec_idle_gen1_sigdet_enable = "true",
receive_pcs0.elec_idle_infer_enable = "false",
receive_pcs0.elec_idle_num_com_detect = 3,
receive_pcs0.enable_bit_reversal = "false",
receive_pcs0.enable_deep_align = "false",
receive_pcs0.enable_deep_align_byte_swap = "false",
receive_pcs0.enable_self_test_mode = "false",
receive_pcs0.enable_true_complement_match_in_word_align = "false",
receive_pcs0.force_signal_detect_dig = "true",
receive_pcs0.hip_enable = "true",
receive_pcs0.infiniband_invalid_code = 0,
receive_pcs0.insert_pad_on_underflow = "false",
receive_pcs0.logical_channel_address = (starting_channel_number + 0),
receive_pcs0.num_align_code_groups_in_ordered_set = 0,
receive_pcs0.num_align_cons_good_data = 16,
receive_pcs0.num_align_cons_pat = 4,
receive_pcs0.num_align_loss_sync_error = 17,
receive_pcs0.ph_fifo_low_latency_enable = "true",
receive_pcs0.ph_fifo_reg_mode = "true",
receive_pcs0.ph_fifo_xn_mapping0 = "none",
receive_pcs0.ph_fifo_xn_mapping1 = "none",
receive_pcs0.ph_fifo_xn_mapping2 = "central",
receive_pcs0.ph_fifo_xn_select = 2,
receive_pcs0.pipe_auto_speed_nego_enable = "true",
receive_pcs0.pipe_freq_scale_mode = "Frequency",
receive_pcs0.pma_done_count = 249950,
receive_pcs0.protocol_hint = "pcie2",
receive_pcs0.rate_match_almost_empty_threshold = 11,
receive_pcs0.rate_match_almost_full_threshold = 13,
receive_pcs0.rate_match_back_to_back = "false",
receive_pcs0.rate_match_delete_threshold = 13,
receive_pcs0.rate_match_empty_threshold = 5,
receive_pcs0.rate_match_fifo_mode = "true",
receive_pcs0.rate_match_full_threshold = 20,
receive_pcs0.rate_match_insert_threshold = 11,
receive_pcs0.rate_match_ordered_set_based = "false",
receive_pcs0.rate_match_pattern1 = "11010000111010000011",
receive_pcs0.rate_match_pattern2 = "00101111000101111100",
receive_pcs0.rate_match_pattern_size = 20,
receive_pcs0.rate_match_pipe_enable = "true",
receive_pcs0.rate_match_reset_enable = "false",
receive_pcs0.rate_match_skip_set_based = "true",
receive_pcs0.rate_match_start_threshold = 7,
receive_pcs0.rd_clk_mux_select = "int clock",
receive_pcs0.recovered_clk_mux_select = "recovered clock",
receive_pcs0.run_length = 40,
receive_pcs0.run_length_enable = "true",
receive_pcs0.rx_detect_bypass = "false",
receive_pcs0.rx_phfifo_wait_cnt = 32,
receive_pcs0.rxstatus_error_report_mode = 1,
receive_pcs0.self_test_mode = "incremental",
receive_pcs0.use_alignment_state_machine = "true",
receive_pcs0.use_deserializer_double_data_mode = "false",
receive_pcs0.use_deskew_fifo = "false",
receive_pcs0.use_double_data_mode = "false",
receive_pcs0.use_parallel_loopback = "false",
receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs1
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs1_autospdrateswitchout),
.autospdspdchgout(),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[5:3]),
.autospdxnspdchg(int_rx_autospdxnspdchg[5:3]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs1_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
.clkout(),
.coreclkout(wire_receive_pcs1_coreclkout),
.ctrldetect(),
.datain(rx_pma_recoverdataout_wire[39:20]),
.dataout(),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[1]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[799:400]),
.dprioout(wire_receive_pcs1_dprioout),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[1]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hip8b10binvpolarity(pipe8b10binvpolarity[1]),
.hipdataout(wire_receive_pcs1_hipdataout),
.hipdatavalid(wire_receive_pcs1_hipdatavalid),
.hipelecidle(wire_receive_pcs1_hipelecidle),
.hipelecidleinfersel({3{1'b0}}),
.hipphydonestatus(wire_receive_pcs1_hipphydonestatus),
.hippowerdown(powerdn[3:2]),
.hiprateswitch(rateswitch[0]),
.hipstatus(wire_receive_pcs1_hipstatus),
.invpol(1'b0),
.iqpphfifobyteselout(),
.iqpphfifoptrsresetout(),
.iqpphfifordenableout(),
.iqpphfifowrclkout(),
.iqpphfifowrenableout(),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs1_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs1_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[1]),
.phfifordenableout(wire_receive_pcs1_phfifordenableout),
.phfiforeset(rx_phfiforeset[1]),
.phfiforesetout(wire_receive_pcs1_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[1]),
.phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[5:3]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[5:3]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[5:3]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[5:3]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[5:3]),
.pipebufferstat(),
.pipedatavalid(),
.pipeelecidle(),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[1]),
.pipephydonestatus(),
.pipepowerdown(tx_pipepowerdownout[3:2]),
.pipepowerstate(tx_pipepowerstateout[7:4]),
.pipestatetransdoneout(wire_receive_pcs1_pipestatetransdoneout),
.pipestatus(),
.prbscidenable(rx_prbscidenable[1]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(wire_receive_pcs1_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[1]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs1_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[1]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[1]),
.rxfound(rx_pcs_rxfound_wire[3:2]),
.signaldetect(wire_receive_pcs1_signaldetect),
.signaldetected(rx_signaldetect_wire[1]),
.syncstatus(),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.coreclk(1'b0),
.elecidleinfersel({3{1'b0}}),
.grayelecidleinferselfromtx({3{1'b0}}),
.iqpautospdxnspgchg({2{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnptrsreset({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrclk({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pipe8b10binvpolarity(1'b0),
.pmatestbusin({8{1'b0}}),
.powerdn({2{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs1.align_pattern = "0101111100",
receive_pcs1.align_pattern_length = 10,
receive_pcs1.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs1.allow_align_polarity_inversion = "false",
receive_pcs1.allow_pipe_polarity_inversion = "true",
receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs1.auto_spd_phystatus_notify_count = 14,
receive_pcs1.auto_spd_self_switch_enable = "false",
receive_pcs1.bit_slip_enable = "false",
receive_pcs1.byte_order_double_data_mode_mask_enable = "false",
receive_pcs1.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs1.byte_order_mode = "none",
receive_pcs1.byte_order_pad_pattern = "0",
receive_pcs1.byte_order_pattern = "0",
receive_pcs1.byte_order_pld_ctrl_enable = "false",
receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs1.cdrctrl_cid_mode_enable = "true",
receive_pcs1.cdrctrl_enable = "true",
receive_pcs1.cdrctrl_rxvalid_mask = "true",
receive_pcs1.channel_bonding = "x4",
receive_pcs1.channel_number = ((starting_channel_number + 1) % 4),
receive_pcs1.channel_width = 8,
receive_pcs1.clk1_mux_select = "recovered clock",
receive_pcs1.clk2_mux_select = "digital reference clock",
receive_pcs1.core_clock_0ppm = "false",
receive_pcs1.datapath_low_latency_mode = "false",
receive_pcs1.datapath_protocol = "pipe",
receive_pcs1.dec_8b_10b_compatibility_mode = "true",
receive_pcs1.dec_8b_10b_mode = "normal",
receive_pcs1.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs1.deskew_pattern = "0",
receive_pcs1.disable_auto_idle_insertion = "false",
receive_pcs1.disable_running_disp_in_word_align = "false",
receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs1.dprio_config_mode = 6'h01,
receive_pcs1.elec_idle_gen1_sigdet_enable = "true",
receive_pcs1.elec_idle_infer_enable = "false",
receive_pcs1.elec_idle_num_com_detect = 3,
receive_pcs1.enable_bit_reversal = "false",
receive_pcs1.enable_deep_align = "false",
receive_pcs1.enable_deep_align_byte_swap = "false",
receive_pcs1.enable_self_test_mode = "false",
receive_pcs1.enable_true_complement_match_in_word_align = "false",
receive_pcs1.force_signal_detect_dig = "true",
receive_pcs1.hip_enable = "true",
receive_pcs1.infiniband_invalid_code = 0,
receive_pcs1.insert_pad_on_underflow = "false",
receive_pcs1.logical_channel_address = (starting_channel_number + 1),
receive_pcs1.num_align_code_groups_in_ordered_set = 0,
receive_pcs1.num_align_cons_good_data = 16,
receive_pcs1.num_align_cons_pat = 4,
receive_pcs1.num_align_loss_sync_error = 17,
receive_pcs1.ph_fifo_low_latency_enable = "true",
receive_pcs1.ph_fifo_reg_mode = "true",
receive_pcs1.ph_fifo_xn_mapping0 = "none",
receive_pcs1.ph_fifo_xn_mapping1 = "none",
receive_pcs1.ph_fifo_xn_mapping2 = "central",
receive_pcs1.ph_fifo_xn_select = 2,
receive_pcs1.pipe_auto_speed_nego_enable = "true",
receive_pcs1.pipe_freq_scale_mode = "Frequency",
receive_pcs1.pma_done_count = 249950,
receive_pcs1.protocol_hint = "pcie2",
receive_pcs1.rate_match_almost_empty_threshold = 11,
receive_pcs1.rate_match_almost_full_threshold = 13,
receive_pcs1.rate_match_back_to_back = "false",
receive_pcs1.rate_match_delete_threshold = 13,
receive_pcs1.rate_match_empty_threshold = 5,
receive_pcs1.rate_match_fifo_mode = "true",
receive_pcs1.rate_match_full_threshold = 20,
receive_pcs1.rate_match_insert_threshold = 11,
receive_pcs1.rate_match_ordered_set_based = "false",
receive_pcs1.rate_match_pattern1 = "11010000111010000011",
receive_pcs1.rate_match_pattern2 = "00101111000101111100",
receive_pcs1.rate_match_pattern_size = 20,
receive_pcs1.rate_match_pipe_enable = "true",
receive_pcs1.rate_match_reset_enable = "false",
receive_pcs1.rate_match_skip_set_based = "true",
receive_pcs1.rate_match_start_threshold = 7,
receive_pcs1.rd_clk_mux_select = "int clock",
receive_pcs1.recovered_clk_mux_select = "recovered clock",
receive_pcs1.run_length = 40,
receive_pcs1.run_length_enable = "true",
receive_pcs1.rx_detect_bypass = "false",
receive_pcs1.rx_phfifo_wait_cnt = 32,
receive_pcs1.rxstatus_error_report_mode = 1,
receive_pcs1.self_test_mode = "incremental",
receive_pcs1.use_alignment_state_machine = "true",
receive_pcs1.use_deserializer_double_data_mode = "false",
receive_pcs1.use_deskew_fifo = "false",
receive_pcs1.use_double_data_mode = "false",
receive_pcs1.use_parallel_loopback = "false",
receive_pcs1.use_rising_edge_triggered_pattern_align = "false",
receive_pcs1.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs2
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs2_autospdrateswitchout),
.autospdspdchgout(),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[8:6]),
.autospdxnspdchg(int_rx_autospdxnspdchg[8:6]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs2_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs2_cdrctrllocktorefclkout),
.clkout(),
.coreclkout(wire_receive_pcs2_coreclkout),
.ctrldetect(),
.datain(rx_pma_recoverdataout_wire[59:40]),
.dataout(),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[2]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[1199:800]),
.dprioout(wire_receive_pcs2_dprioout),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[2]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hip8b10binvpolarity(pipe8b10binvpolarity[2]),
.hipdataout(wire_receive_pcs2_hipdataout),
.hipdatavalid(wire_receive_pcs2_hipdatavalid),
.hipelecidle(wire_receive_pcs2_hipelecidle),
.hipelecidleinfersel({3{1'b0}}),
.hipphydonestatus(wire_receive_pcs2_hipphydonestatus),
.hippowerdown(powerdn[5:4]),
.hiprateswitch(rateswitch[0]),
.hipstatus(wire_receive_pcs2_hipstatus),
.invpol(1'b0),
.iqpphfifobyteselout(),
.iqpphfifoptrsresetout(),
.iqpphfifordenableout(),
.iqpphfifowrclkout(),
.iqpphfifowrenableout(),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs2_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs2_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[2]),
.phfifordenableout(wire_receive_pcs2_phfifordenableout),
.phfiforeset(rx_phfiforeset[2]),
.phfiforesetout(wire_receive_pcs2_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[2]),
.phfifowrdisableout(wire_receive_pcs2_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[8:6]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[8:6]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[8:6]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[8:6]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[8:6]),
.pipebufferstat(),
.pipedatavalid(),
.pipeelecidle(),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[2]),
.pipephydonestatus(),
.pipepowerdown(tx_pipepowerdownout[5:4]),
.pipepowerstate(tx_pipepowerstateout[11:8]),
.pipestatetransdoneout(wire_receive_pcs2_pipestatetransdoneout),
.pipestatus(),
.prbscidenable(rx_prbscidenable[2]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(wire_receive_pcs2_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[2]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs2_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[2]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[2]),
.rxfound(rx_pcs_rxfound_wire[5:4]),
.signaldetect(wire_receive_pcs2_signaldetect),
.signaldetected(rx_signaldetect_wire[2]),
.syncstatus(),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.coreclk(1'b0),
.elecidleinfersel({3{1'b0}}),
.grayelecidleinferselfromtx({3{1'b0}}),
.iqpautospdxnspgchg({2{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnptrsreset({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrclk({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pipe8b10binvpolarity(1'b0),
.pmatestbusin({8{1'b0}}),
.powerdn({2{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs2.align_pattern = "0101111100",
receive_pcs2.align_pattern_length = 10,
receive_pcs2.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs2.allow_align_polarity_inversion = "false",
receive_pcs2.allow_pipe_polarity_inversion = "true",
receive_pcs2.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs2.auto_spd_phystatus_notify_count = 14,
receive_pcs2.auto_spd_self_switch_enable = "false",
receive_pcs2.bit_slip_enable = "false",
receive_pcs2.byte_order_double_data_mode_mask_enable = "false",
receive_pcs2.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs2.byte_order_mode = "none",
receive_pcs2.byte_order_pad_pattern = "0",
receive_pcs2.byte_order_pattern = "0",
receive_pcs2.byte_order_pld_ctrl_enable = "false",
receive_pcs2.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs2.cdrctrl_cid_mode_enable = "true",
receive_pcs2.cdrctrl_enable = "true",
receive_pcs2.cdrctrl_rxvalid_mask = "true",
receive_pcs2.channel_bonding = "x4",
receive_pcs2.channel_number = ((starting_channel_number + 2) % 4),
receive_pcs2.channel_width = 8,
receive_pcs2.clk1_mux_select = "recovered clock",
receive_pcs2.clk2_mux_select = "digital reference clock",
receive_pcs2.core_clock_0ppm = "false",
receive_pcs2.datapath_low_latency_mode = "false",
receive_pcs2.datapath_protocol = "pipe",
receive_pcs2.dec_8b_10b_compatibility_mode = "true",
receive_pcs2.dec_8b_10b_mode = "normal",
receive_pcs2.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs2.deskew_pattern = "0",
receive_pcs2.disable_auto_idle_insertion = "false",
receive_pcs2.disable_running_disp_in_word_align = "false",
receive_pcs2.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs2.dprio_config_mode = 6'h01,
receive_pcs2.elec_idle_gen1_sigdet_enable = "true",
receive_pcs2.elec_idle_infer_enable = "false",
receive_pcs2.elec_idle_num_com_detect = 3,
receive_pcs2.enable_bit_reversal = "false",
receive_pcs2.enable_deep_align = "false",
receive_pcs2.enable_deep_align_byte_swap = "false",
receive_pcs2.enable_self_test_mode = "false",
receive_pcs2.enable_true_complement_match_in_word_align = "false",
receive_pcs2.force_signal_detect_dig = "true",
receive_pcs2.hip_enable = "true",
receive_pcs2.infiniband_invalid_code = 0,
receive_pcs2.insert_pad_on_underflow = "false",
receive_pcs2.logical_channel_address = (starting_channel_number + 2),
receive_pcs2.num_align_code_groups_in_ordered_set = 0,
receive_pcs2.num_align_cons_good_data = 16,
receive_pcs2.num_align_cons_pat = 4,
receive_pcs2.num_align_loss_sync_error = 17,
receive_pcs2.ph_fifo_low_latency_enable = "true",
receive_pcs2.ph_fifo_reg_mode = "true",
receive_pcs2.ph_fifo_xn_mapping0 = "none",
receive_pcs2.ph_fifo_xn_mapping1 = "none",
receive_pcs2.ph_fifo_xn_mapping2 = "central",
receive_pcs2.ph_fifo_xn_select = 2,
receive_pcs2.pipe_auto_speed_nego_enable = "true",
receive_pcs2.pipe_freq_scale_mode = "Frequency",
receive_pcs2.pma_done_count = 249950,
receive_pcs2.protocol_hint = "pcie2",
receive_pcs2.rate_match_almost_empty_threshold = 11,
receive_pcs2.rate_match_almost_full_threshold = 13,
receive_pcs2.rate_match_back_to_back = "false",
receive_pcs2.rate_match_delete_threshold = 13,
receive_pcs2.rate_match_empty_threshold = 5,
receive_pcs2.rate_match_fifo_mode = "true",
receive_pcs2.rate_match_full_threshold = 20,
receive_pcs2.rate_match_insert_threshold = 11,
receive_pcs2.rate_match_ordered_set_based = "false",
receive_pcs2.rate_match_pattern1 = "11010000111010000011",
receive_pcs2.rate_match_pattern2 = "00101111000101111100",
receive_pcs2.rate_match_pattern_size = 20,
receive_pcs2.rate_match_pipe_enable = "true",
receive_pcs2.rate_match_reset_enable = "false",
receive_pcs2.rate_match_skip_set_based = "true",
receive_pcs2.rate_match_start_threshold = 7,
receive_pcs2.rd_clk_mux_select = "int clock",
receive_pcs2.recovered_clk_mux_select = "recovered clock",
receive_pcs2.run_length = 40,
receive_pcs2.run_length_enable = "true",
receive_pcs2.rx_detect_bypass = "false",
receive_pcs2.rx_phfifo_wait_cnt = 32,
receive_pcs2.rxstatus_error_report_mode = 1,
receive_pcs2.self_test_mode = "incremental",
receive_pcs2.use_alignment_state_machine = "true",
receive_pcs2.use_deserializer_double_data_mode = "false",
receive_pcs2.use_deskew_fifo = "false",
receive_pcs2.use_double_data_mode = "false",
receive_pcs2.use_parallel_loopback = "false",
receive_pcs2.use_rising_edge_triggered_pattern_align = "false",
receive_pcs2.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs3
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs3_autospdrateswitchout),
.autospdspdchgout(),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[11:9]),
.autospdxnspdchg(int_rx_autospdxnspdchg[11:9]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs3_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs3_cdrctrllocktorefclkout),
.clkout(),
.coreclkout(wire_receive_pcs3_coreclkout),
.ctrldetect(),
.datain(rx_pma_recoverdataout_wire[79:60]),
.dataout(),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[3]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[1599:1200]),
.dprioout(wire_receive_pcs3_dprioout),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[3]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hip8b10binvpolarity(pipe8b10binvpolarity[3]),
.hipdataout(wire_receive_pcs3_hipdataout),
.hipdatavalid(wire_receive_pcs3_hipdatavalid),
.hipelecidle(wire_receive_pcs3_hipelecidle),
.hipelecidleinfersel({3{1'b0}}),
.hipphydonestatus(wire_receive_pcs3_hipphydonestatus),
.hippowerdown(powerdn[7:6]),
.hiprateswitch(rateswitch[0]),
.hipstatus(wire_receive_pcs3_hipstatus),
.invpol(1'b0),
.iqpphfifobyteselout(),
.iqpphfifoptrsresetout(),
.iqpphfifordenableout(),
.iqpphfifowrclkout(),
.iqpphfifowrenableout(),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs3_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs3_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[3]),
.phfifordenableout(wire_receive_pcs3_phfifordenableout),
.phfiforeset(rx_phfiforeset[3]),
.phfiforesetout(wire_receive_pcs3_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[3]),
.phfifowrdisableout(wire_receive_pcs3_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[11:9]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[11:9]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[11:9]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[11:9]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[11:9]),
.pipebufferstat(),
.pipedatavalid(),
.pipeelecidle(),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[3]),
.pipephydonestatus(),
.pipepowerdown(tx_pipepowerdownout[7:6]),
.pipepowerstate(tx_pipepowerstateout[15:12]),
.pipestatetransdoneout(wire_receive_pcs3_pipestatetransdoneout),
.pipestatus(),
.prbscidenable(rx_prbscidenable[3]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(wire_receive_pcs3_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[3]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs3_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[3]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[3]),
.rxfound(rx_pcs_rxfound_wire[7:6]),
.signaldetect(wire_receive_pcs3_signaldetect),
.signaldetected(rx_signaldetect_wire[3]),
.syncstatus(),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.coreclk(1'b0),
.elecidleinfersel({3{1'b0}}),
.grayelecidleinferselfromtx({3{1'b0}}),
.iqpautospdxnspgchg({2{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnptrsreset({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrclk({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pipe8b10binvpolarity(1'b0),
.pmatestbusin({8{1'b0}}),
.powerdn({2{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs3.align_pattern = "0101111100",
receive_pcs3.align_pattern_length = 10,
receive_pcs3.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs3.allow_align_polarity_inversion = "false",
receive_pcs3.allow_pipe_polarity_inversion = "true",
receive_pcs3.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs3.auto_spd_phystatus_notify_count = 14,
receive_pcs3.auto_spd_self_switch_enable = "false",
receive_pcs3.bit_slip_enable = "false",
receive_pcs3.byte_order_double_data_mode_mask_enable = "false",
receive_pcs3.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs3.byte_order_mode = "none",
receive_pcs3.byte_order_pad_pattern = "0",
receive_pcs3.byte_order_pattern = "0",
receive_pcs3.byte_order_pld_ctrl_enable = "false",
receive_pcs3.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs3.cdrctrl_cid_mode_enable = "true",
receive_pcs3.cdrctrl_enable = "true",
receive_pcs3.cdrctrl_rxvalid_mask = "true",
receive_pcs3.channel_bonding = "x4",
receive_pcs3.channel_number = ((starting_channel_number + 3) % 4),
receive_pcs3.channel_width = 8,
receive_pcs3.clk1_mux_select = "recovered clock",
receive_pcs3.clk2_mux_select = "digital reference clock",
receive_pcs3.core_clock_0ppm = "false",
receive_pcs3.datapath_low_latency_mode = "false",
receive_pcs3.datapath_protocol = "pipe",
receive_pcs3.dec_8b_10b_compatibility_mode = "true",
receive_pcs3.dec_8b_10b_mode = "normal",
receive_pcs3.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs3.deskew_pattern = "0",
receive_pcs3.disable_auto_idle_insertion = "false",
receive_pcs3.disable_running_disp_in_word_align = "false",
receive_pcs3.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs3.dprio_config_mode = 6'h01,
receive_pcs3.elec_idle_gen1_sigdet_enable = "true",
receive_pcs3.elec_idle_infer_enable = "false",
receive_pcs3.elec_idle_num_com_detect = 3,
receive_pcs3.enable_bit_reversal = "false",
receive_pcs3.enable_deep_align = "false",
receive_pcs3.enable_deep_align_byte_swap = "false",
receive_pcs3.enable_self_test_mode = "false",
receive_pcs3.enable_true_complement_match_in_word_align = "false",
receive_pcs3.force_signal_detect_dig = "true",
receive_pcs3.hip_enable = "true",
receive_pcs3.infiniband_invalid_code = 0,
receive_pcs3.insert_pad_on_underflow = "false",
receive_pcs3.logical_channel_address = (starting_channel_number + 3),
receive_pcs3.num_align_code_groups_in_ordered_set = 0,
receive_pcs3.num_align_cons_good_data = 16,
receive_pcs3.num_align_cons_pat = 4,
receive_pcs3.num_align_loss_sync_error = 17,
receive_pcs3.ph_fifo_low_latency_enable = "true",
receive_pcs3.ph_fifo_reg_mode = "true",
receive_pcs3.ph_fifo_xn_mapping0 = "none",
receive_pcs3.ph_fifo_xn_mapping1 = "none",
receive_pcs3.ph_fifo_xn_mapping2 = "central",
receive_pcs3.ph_fifo_xn_select = 2,
receive_pcs3.pipe_auto_speed_nego_enable = "true",
receive_pcs3.pipe_freq_scale_mode = "Frequency",
receive_pcs3.pma_done_count = 249950,
receive_pcs3.protocol_hint = "pcie2",
receive_pcs3.rate_match_almost_empty_threshold = 11,
receive_pcs3.rate_match_almost_full_threshold = 13,
receive_pcs3.rate_match_back_to_back = "false",
receive_pcs3.rate_match_delete_threshold = 13,
receive_pcs3.rate_match_empty_threshold = 5,
receive_pcs3.rate_match_fifo_mode = "true",
receive_pcs3.rate_match_full_threshold = 20,
receive_pcs3.rate_match_insert_threshold = 11,
receive_pcs3.rate_match_ordered_set_based = "false",
receive_pcs3.rate_match_pattern1 = "11010000111010000011",
receive_pcs3.rate_match_pattern2 = "00101111000101111100",
receive_pcs3.rate_match_pattern_size = 20,
receive_pcs3.rate_match_pipe_enable = "true",
receive_pcs3.rate_match_reset_enable = "false",
receive_pcs3.rate_match_skip_set_based = "true",
receive_pcs3.rate_match_start_threshold = 7,
receive_pcs3.rd_clk_mux_select = "int clock",
receive_pcs3.recovered_clk_mux_select = "recovered clock",
receive_pcs3.run_length = 40,
receive_pcs3.run_length_enable = "true",
receive_pcs3.rx_detect_bypass = "false",
receive_pcs3.rx_phfifo_wait_cnt = 32,
receive_pcs3.rxstatus_error_report_mode = 1,
receive_pcs3.self_test_mode = "incremental",
receive_pcs3.use_alignment_state_machine = "true",
receive_pcs3.use_deserializer_double_data_mode = "false",
receive_pcs3.use_deskew_fifo = "false",
receive_pcs3.use_double_data_mode = "false",
receive_pcs3.use_parallel_loopback = "false",
receive_pcs3.use_rising_edge_triggered_pattern_align = "false",
receive_pcs3.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pma receive_pma0
(
.adaptdone(),
.analogtestbus(wire_receive_pma0_analogtestbus),
.clockout(wire_receive_pma0_clockout),
.datain(rx_datain[0]),
.dataout(wire_receive_pma0_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[3:0]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[299:0]),
.dprioout(wire_receive_pma0_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[0]),
.locktoref(rx_locktorefclk_wire[0]),
.locktorefout(wire_receive_pma0_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[0]),
.powerdn(cent_unit_rxibpowerdn[0]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
.recoverdatain(pll_ch_dataout_wire[1:0]),
.recoverdataout(wire_receive_pma0_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[0]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma0_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma0.adaptive_equalization_mode = "none",
receive_pma0.allow_serial_loopback = "false",
receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
receive_pma0.channel_type = "auto",
receive_pma0.common_mode = "0.82V",
receive_pma0.deserialization_factor = 10,
receive_pma0.dprio_config_mode = 6'h01,
receive_pma0.enable_ltd = "false",
receive_pma0.enable_ltr = "true",
receive_pma0.eq_dc_gain = 3,
receive_pma0.eqa_ctrl = 0,
receive_pma0.eqb_ctrl = 0,
receive_pma0.eqc_ctrl = 0,
receive_pma0.eqd_ctrl = 0,
receive_pma0.eqv_ctrl = 0,
receive_pma0.eyemon_bandwidth = 0,
receive_pma0.force_signal_detect = "true",
receive_pma0.logical_channel_address = (starting_channel_number + 0),
receive_pma0.low_speed_test_select = 0,
receive_pma0.offset_cancellation = 1,
receive_pma0.ppmselect = 32,
receive_pma0.protocol_hint = "pcie2",
receive_pma0.send_direct_reverse_serial_loopback = "None",
receive_pma0.signal_detect_hysteresis = 4,
receive_pma0.signal_detect_hysteresis_valid_threshold = 14,
receive_pma0.signal_detect_loss_threshold = 3,
receive_pma0.termination = "OCT 100 Ohms",
receive_pma0.use_deser_double_data_width = "false",
receive_pma0.use_external_termination = "false",
receive_pma0.use_pma_direct = "false",
receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma1
(
.adaptdone(),
.analogtestbus(wire_receive_pma1_analogtestbus),
.clockout(wire_receive_pma1_clockout),
.datain(rx_datain[1]),
.dataout(wire_receive_pma1_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[7:4]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[599:300]),
.dprioout(wire_receive_pma1_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[1]),
.locktoref(rx_locktorefclk_wire[1]),
.locktorefout(wire_receive_pma1_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[1]),
.powerdn(cent_unit_rxibpowerdn[1]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
.recoverdatain(pll_ch_dataout_wire[3:2]),
.recoverdataout(wire_receive_pma1_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[1]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma1_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma1.adaptive_equalization_mode = "none",
receive_pma1.allow_serial_loopback = "false",
receive_pma1.channel_number = ((starting_channel_number + 1) % 4),
receive_pma1.channel_type = "auto",
receive_pma1.common_mode = "0.82V",
receive_pma1.deserialization_factor = 10,
receive_pma1.dprio_config_mode = 6'h01,
receive_pma1.enable_ltd = "false",
receive_pma1.enable_ltr = "true",
receive_pma1.eq_dc_gain = 3,
receive_pma1.eqa_ctrl = 0,
receive_pma1.eqb_ctrl = 0,
receive_pma1.eqc_ctrl = 0,
receive_pma1.eqd_ctrl = 0,
receive_pma1.eqv_ctrl = 0,
receive_pma1.eyemon_bandwidth = 0,
receive_pma1.force_signal_detect = "true",
receive_pma1.logical_channel_address = (starting_channel_number + 1),
receive_pma1.low_speed_test_select = 0,
receive_pma1.offset_cancellation = 1,
receive_pma1.ppmselect = 32,
receive_pma1.protocol_hint = "pcie2",
receive_pma1.send_direct_reverse_serial_loopback = "None",
receive_pma1.signal_detect_hysteresis = 4,
receive_pma1.signal_detect_hysteresis_valid_threshold = 14,
receive_pma1.signal_detect_loss_threshold = 3,
receive_pma1.termination = "OCT 100 Ohms",
receive_pma1.use_deser_double_data_width = "false",
receive_pma1.use_external_termination = "false",
receive_pma1.use_pma_direct = "false",
receive_pma1.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma2
(
.adaptdone(),
.analogtestbus(wire_receive_pma2_analogtestbus),
.clockout(wire_receive_pma2_clockout),
.datain(rx_datain[2]),
.dataout(wire_receive_pma2_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[11:8]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[899:600]),
.dprioout(wire_receive_pma2_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[2]),
.locktoref(rx_locktorefclk_wire[2]),
.locktorefout(wire_receive_pma2_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[2]),
.powerdn(cent_unit_rxibpowerdn[2]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[2]),
.recoverdatain(pll_ch_dataout_wire[5:4]),
.recoverdataout(wire_receive_pma2_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[2]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma2_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma2.adaptive_equalization_mode = "none",
receive_pma2.allow_serial_loopback = "false",
receive_pma2.channel_number = ((starting_channel_number + 2) % 4),
receive_pma2.channel_type = "auto",
receive_pma2.common_mode = "0.82V",
receive_pma2.deserialization_factor = 10,
receive_pma2.dprio_config_mode = 6'h01,
receive_pma2.enable_ltd = "false",
receive_pma2.enable_ltr = "true",
receive_pma2.eq_dc_gain = 3,
receive_pma2.eqa_ctrl = 0,
receive_pma2.eqb_ctrl = 0,
receive_pma2.eqc_ctrl = 0,
receive_pma2.eqd_ctrl = 0,
receive_pma2.eqv_ctrl = 0,
receive_pma2.eyemon_bandwidth = 0,
receive_pma2.force_signal_detect = "true",
receive_pma2.logical_channel_address = (starting_channel_number + 2),
receive_pma2.low_speed_test_select = 0,
receive_pma2.offset_cancellation = 1,
receive_pma2.ppmselect = 32,
receive_pma2.protocol_hint = "pcie2",
receive_pma2.send_direct_reverse_serial_loopback = "None",
receive_pma2.signal_detect_hysteresis = 4,
receive_pma2.signal_detect_hysteresis_valid_threshold = 14,
receive_pma2.signal_detect_loss_threshold = 3,
receive_pma2.termination = "OCT 100 Ohms",
receive_pma2.use_deser_double_data_width = "false",
receive_pma2.use_external_termination = "false",
receive_pma2.use_pma_direct = "false",
receive_pma2.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma3
(
.adaptdone(),
.analogtestbus(wire_receive_pma3_analogtestbus),
.clockout(wire_receive_pma3_clockout),
.datain(rx_datain[3]),
.dataout(wire_receive_pma3_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[15:12]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[1199:900]),
.dprioout(wire_receive_pma3_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[3]),
.locktoref(rx_locktorefclk_wire[3]),
.locktorefout(wire_receive_pma3_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[3]),
.powerdn(cent_unit_rxibpowerdn[3]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[3]),
.recoverdatain(pll_ch_dataout_wire[7:6]),
.recoverdataout(wire_receive_pma3_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[3]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma3_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma3.adaptive_equalization_mode = "none",
receive_pma3.allow_serial_loopback = "false",
receive_pma3.channel_number = ((starting_channel_number + 3) % 4),
receive_pma3.channel_type = "auto",
receive_pma3.common_mode = "0.82V",
receive_pma3.deserialization_factor = 10,
receive_pma3.dprio_config_mode = 6'h01,
receive_pma3.enable_ltd = "false",
receive_pma3.enable_ltr = "true",
receive_pma3.eq_dc_gain = 3,
receive_pma3.eqa_ctrl = 0,
receive_pma3.eqb_ctrl = 0,
receive_pma3.eqc_ctrl = 0,
receive_pma3.eqd_ctrl = 0,
receive_pma3.eqv_ctrl = 0,
receive_pma3.eyemon_bandwidth = 0,
receive_pma3.force_signal_detect = "true",
receive_pma3.logical_channel_address = (starting_channel_number + 3),
receive_pma3.low_speed_test_select = 0,
receive_pma3.offset_cancellation = 1,
receive_pma3.ppmselect = 32,
receive_pma3.protocol_hint = "pcie2",
receive_pma3.send_direct_reverse_serial_loopback = "None",
receive_pma3.signal_detect_hysteresis = 4,
receive_pma3.signal_detect_hysteresis_valid_threshold = 14,
receive_pma3.signal_detect_loss_threshold = 3,
receive_pma3.termination = "OCT 100 Ohms",
receive_pma3.use_deser_double_data_width = "false",
receive_pma3.use_external_termination = "false",
receive_pma3.use_pma_direct = "false",
receive_pma3.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_tx_pcs transmit_pcs0
(
.clkout(),
.coreclkout(wire_transmit_pcs0_coreclkout),
.ctrlenable({{3{1'b0}}, 1'b0}),
.datainfull({44{1'b0}}),
.dataout(wire_transmit_pcs0_dataout),
.digitalreset(tx_digitalreset_out[0]),
.dispval({{3{1'b0}}, 1'b0}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[149:0]),
.dprioout(wire_transmit_pcs0_dprioout),
.enrevparallellpbk(tx_revparallellpbken[0]),
.forcedisp({{3{1'b0}}, 1'b0}),
.forcedispcompliance(1'b0),
.forceelecidleout(wire_transmit_pcs0_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
.hipdatain({tx_forcedispcompliance[0], tx_ctrlenable[0], tx_datain_wire[7:0]}),
.hipdetectrxloop(tx_detectrxloop[0]),
.hipelecidleinfersel(rx_elecidleinfersel[2:0]),
.hipforceelecidle(tx_forceelecidle[0]),
.hippowerdn(powerdn[1:0]),
.hiptxclkout(),
.hiptxdeemph(tx_pipedeemph[0]),
.hiptxmargin(tx_pipemargin[2:0]),
.invpol(tx_invpolarity[0]),
.iqpphfifobyteselout(),
.iqpphfifordclkout(),
.iqpphfifordenableout(),
.iqpphfifowrenableout(),
.localrefclk(tx_localrefclk[0]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[0]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[0]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[0]),
.phfiforesetout(wire_transmit_pcs0_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[2:0]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[2:0]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[2:0]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[2:0]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[2:0]),
.pipeenrevparallellpbkout(wire_transmit_pcs0_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[0]),
.pipetxswing(tx_pipeswing[0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[19:0]),
.txdetectrx(wire_transmit_pcs0_txdetectrx),
.xgmctrl(cent_unit_txctrlout[0]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[7:0]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.coreclk(1'b0),
.datain({40{1'b0}}),
.detectrxloop(1'b0),
.elecidleinfersel({3{1'b0}}),
.forceelecidle(1'b0),
.freezptr(1'b0),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnrdclk({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.pipetxdeemph(1'b0),
.pipetxmargin({3{1'b0}}),
.powerdn({2{1'b0}}),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs0.allow_polarity_inversion = "false",
transmit_pcs0.auto_spd_self_switch_enable = "false",
transmit_pcs0.bitslip_enable = "false",
transmit_pcs0.channel_bonding = "x4",
transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pcs0.channel_width = 8,
transmit_pcs0.core_clock_0ppm = "false",
transmit_pcs0.datapath_low_latency_mode = "false",
transmit_pcs0.datapath_protocol = "pipe",
transmit_pcs0.disable_ph_low_latency_mode = "false",
transmit_pcs0.disparity_mode = "new",
transmit_pcs0.dprio_config_mode = 6'h01,
transmit_pcs0.elec_idle_delay = 6,
transmit_pcs0.enable_bit_reversal = "false",
transmit_pcs0.enable_idle_selection = "false",
transmit_pcs0.enable_reverse_parallel_loopback = "true",
transmit_pcs0.enable_self_test_mode = "false",
transmit_pcs0.enable_symbol_swap = "false",
transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
transmit_pcs0.enc_8b_10b_mode = "normal",
transmit_pcs0.force_echar = "false",
transmit_pcs0.force_kchar = "false",
transmit_pcs0.hip_enable = "true",
transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
transmit_pcs0.ph_fifo_reg_mode = "true",
transmit_pcs0.ph_fifo_xn_mapping0 = "none",
transmit_pcs0.ph_fifo_xn_mapping1 = "none",
transmit_pcs0.ph_fifo_xn_mapping2 = "central",
transmit_pcs0.ph_fifo_xn_select = 2,
transmit_pcs0.pipe_auto_speed_nego_enable = "true",
transmit_pcs0.pipe_freq_scale_mode = "Frequency",
transmit_pcs0.pipe_voltage_swing_control = "false",
transmit_pcs0.prbs_cid_pattern = "false",
transmit_pcs0.protocol_hint = "pcie2",
transmit_pcs0.refclk_select = "cmu_clock_divider",
transmit_pcs0.self_test_mode = "incremental",
transmit_pcs0.use_double_data_mode = "false",
transmit_pcs0.use_serializer_double_data_mode = "false",
transmit_pcs0.wr_clk_mux_select = "int_clk",
transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs1
(
.clkout(),
.coreclkout(wire_transmit_pcs1_coreclkout),
.ctrlenable({{3{1'b0}}, 1'b0}),
.datainfull({44{1'b0}}),
.dataout(wire_transmit_pcs1_dataout),
.digitalreset(tx_digitalreset_out[1]),
.dispval({{3{1'b0}}, 1'b0}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[299:150]),
.dprioout(wire_transmit_pcs1_dprioout),
.enrevparallellpbk(tx_revparallellpbken[1]),
.forcedisp({{3{1'b0}}, 1'b0}),
.forcedispcompliance(1'b0),
.forceelecidleout(wire_transmit_pcs1_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs1_grayelecidleinferselout),
.hipdatain({tx_forcedispcompliance[1], tx_ctrlenable[1], tx_datain_wire[15:8]}),
.hipdetectrxloop(tx_detectrxloop[1]),
.hipelecidleinfersel(rx_elecidleinfersel[5:3]),
.hipforceelecidle(tx_forceelecidle[1]),
.hippowerdn(powerdn[3:2]),
.hiptxclkout(),
.hiptxdeemph(tx_pipedeemph[1]),
.hiptxmargin(tx_pipemargin[5:3]),
.invpol(tx_invpolarity[1]),
.iqpphfifobyteselout(),
.iqpphfifordclkout(),
.iqpphfifordenableout(),
.iqpphfifowrenableout(),
.localrefclk(tx_localrefclk[1]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[1]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[1]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[1]),
.phfiforesetout(wire_transmit_pcs1_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[5:3]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[5:3]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[5:3]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[5:3]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[5:3]),
.pipeenrevparallellpbkout(wire_transmit_pcs1_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs1_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs1_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[1]),
.pipetxswing(tx_pipeswing[1]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[39:20]),
.txdetectrx(wire_transmit_pcs1_txdetectrx),
.xgmctrl(cent_unit_txctrlout[1]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[15:8]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.coreclk(1'b0),
.datain({40{1'b0}}),
.detectrxloop(1'b0),
.elecidleinfersel({3{1'b0}}),
.forceelecidle(1'b0),
.freezptr(1'b0),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnrdclk({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.pipetxdeemph(1'b0),
.pipetxmargin({3{1'b0}}),
.powerdn({2{1'b0}}),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs1.allow_polarity_inversion = "false",
transmit_pcs1.auto_spd_self_switch_enable = "false",
transmit_pcs1.bitslip_enable = "false",
transmit_pcs1.channel_bonding = "x4",
transmit_pcs1.channel_number = ((starting_channel_number + 1) % 4),
transmit_pcs1.channel_width = 8,
transmit_pcs1.core_clock_0ppm = "false",
transmit_pcs1.datapath_low_latency_mode = "false",
transmit_pcs1.datapath_protocol = "pipe",
transmit_pcs1.disable_ph_low_latency_mode = "false",
transmit_pcs1.disparity_mode = "new",
transmit_pcs1.dprio_config_mode = 6'h01,
transmit_pcs1.elec_idle_delay = 6,
transmit_pcs1.enable_bit_reversal = "false",
transmit_pcs1.enable_idle_selection = "false",
transmit_pcs1.enable_reverse_parallel_loopback = "true",
transmit_pcs1.enable_self_test_mode = "false",
transmit_pcs1.enable_symbol_swap = "false",
transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
transmit_pcs1.enc_8b_10b_mode = "normal",
transmit_pcs1.force_echar = "false",
transmit_pcs1.force_kchar = "false",
transmit_pcs1.hip_enable = "true",
transmit_pcs1.logical_channel_address = (starting_channel_number + 1),
transmit_pcs1.ph_fifo_reg_mode = "true",
transmit_pcs1.ph_fifo_xn_mapping0 = "none",
transmit_pcs1.ph_fifo_xn_mapping1 = "none",
transmit_pcs1.ph_fifo_xn_mapping2 = "central",
transmit_pcs1.ph_fifo_xn_select = 2,
transmit_pcs1.pipe_auto_speed_nego_enable = "true",
transmit_pcs1.pipe_freq_scale_mode = "Frequency",
transmit_pcs1.pipe_voltage_swing_control = "false",
transmit_pcs1.prbs_cid_pattern = "false",
transmit_pcs1.protocol_hint = "pcie2",
transmit_pcs1.refclk_select = "cmu_clock_divider",
transmit_pcs1.self_test_mode = "incremental",
transmit_pcs1.use_double_data_mode = "false",
transmit_pcs1.use_serializer_double_data_mode = "false",
transmit_pcs1.wr_clk_mux_select = "int_clk",
transmit_pcs1.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs2
(
.clkout(),
.coreclkout(wire_transmit_pcs2_coreclkout),
.ctrlenable({{3{1'b0}}, 1'b0}),
.datainfull({44{1'b0}}),
.dataout(wire_transmit_pcs2_dataout),
.digitalreset(tx_digitalreset_out[2]),
.dispval({{3{1'b0}}, 1'b0}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[449:300]),
.dprioout(wire_transmit_pcs2_dprioout),
.enrevparallellpbk(tx_revparallellpbken[2]),
.forcedisp({{3{1'b0}}, 1'b0}),
.forcedispcompliance(1'b0),
.forceelecidleout(wire_transmit_pcs2_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs2_grayelecidleinferselout),
.hipdatain({tx_forcedispcompliance[2], tx_ctrlenable[2], tx_datain_wire[23:16]}),
.hipdetectrxloop(tx_detectrxloop[2]),
.hipelecidleinfersel(rx_elecidleinfersel[8:6]),
.hipforceelecidle(tx_forceelecidle[2]),
.hippowerdn(powerdn[5:4]),
.hiptxclkout(),
.hiptxdeemph(tx_pipedeemph[2]),
.hiptxmargin(tx_pipemargin[8:6]),
.invpol(tx_invpolarity[2]),
.iqpphfifobyteselout(),
.iqpphfifordclkout(),
.iqpphfifordenableout(),
.iqpphfifowrenableout(),
.localrefclk(tx_localrefclk[2]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[2]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[2]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs2_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[2]),
.phfiforesetout(wire_transmit_pcs2_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs2_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[8:6]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[8:6]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[8:6]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[8:6]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[8:6]),
.pipeenrevparallellpbkout(wire_transmit_pcs2_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs2_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs2_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[2]),
.pipetxswing(tx_pipeswing[2]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[59:40]),
.txdetectrx(wire_transmit_pcs2_txdetectrx),
.xgmctrl(cent_unit_txctrlout[2]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[23:16]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.coreclk(1'b0),
.datain({40{1'b0}}),
.detectrxloop(1'b0),
.elecidleinfersel({3{1'b0}}),
.forceelecidle(1'b0),
.freezptr(1'b0),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnrdclk({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.pipetxdeemph(1'b0),
.pipetxmargin({3{1'b0}}),
.powerdn({2{1'b0}}),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs2.allow_polarity_inversion = "false",
transmit_pcs2.auto_spd_self_switch_enable = "false",
transmit_pcs2.bitslip_enable = "false",
transmit_pcs2.channel_bonding = "x4",
transmit_pcs2.channel_number = ((starting_channel_number + 2) % 4),
transmit_pcs2.channel_width = 8,
transmit_pcs2.core_clock_0ppm = "false",
transmit_pcs2.datapath_low_latency_mode = "false",
transmit_pcs2.datapath_protocol = "pipe",
transmit_pcs2.disable_ph_low_latency_mode = "false",
transmit_pcs2.disparity_mode = "new",
transmit_pcs2.dprio_config_mode = 6'h01,
transmit_pcs2.elec_idle_delay = 6,
transmit_pcs2.enable_bit_reversal = "false",
transmit_pcs2.enable_idle_selection = "false",
transmit_pcs2.enable_reverse_parallel_loopback = "true",
transmit_pcs2.enable_self_test_mode = "false",
transmit_pcs2.enable_symbol_swap = "false",
transmit_pcs2.enc_8b_10b_compatibility_mode = "true",
transmit_pcs2.enc_8b_10b_mode = "normal",
transmit_pcs2.force_echar = "false",
transmit_pcs2.force_kchar = "false",
transmit_pcs2.hip_enable = "true",
transmit_pcs2.logical_channel_address = (starting_channel_number + 2),
transmit_pcs2.ph_fifo_reg_mode = "true",
transmit_pcs2.ph_fifo_xn_mapping0 = "none",
transmit_pcs2.ph_fifo_xn_mapping1 = "none",
transmit_pcs2.ph_fifo_xn_mapping2 = "central",
transmit_pcs2.ph_fifo_xn_select = 2,
transmit_pcs2.pipe_auto_speed_nego_enable = "true",
transmit_pcs2.pipe_freq_scale_mode = "Frequency",
transmit_pcs2.pipe_voltage_swing_control = "false",
transmit_pcs2.prbs_cid_pattern = "false",
transmit_pcs2.protocol_hint = "pcie2",
transmit_pcs2.refclk_select = "cmu_clock_divider",
transmit_pcs2.self_test_mode = "incremental",
transmit_pcs2.use_double_data_mode = "false",
transmit_pcs2.use_serializer_double_data_mode = "false",
transmit_pcs2.wr_clk_mux_select = "int_clk",
transmit_pcs2.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs3
(
.clkout(),
.coreclkout(wire_transmit_pcs3_coreclkout),
.ctrlenable({{3{1'b0}}, 1'b0}),
.datainfull({44{1'b0}}),
.dataout(wire_transmit_pcs3_dataout),
.digitalreset(tx_digitalreset_out[3]),
.dispval({{3{1'b0}}, 1'b0}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[599:450]),
.dprioout(wire_transmit_pcs3_dprioout),
.enrevparallellpbk(tx_revparallellpbken[3]),
.forcedisp({{3{1'b0}}, 1'b0}),
.forcedispcompliance(1'b0),
.forceelecidleout(wire_transmit_pcs3_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs3_grayelecidleinferselout),
.hipdatain({tx_forcedispcompliance[3], tx_ctrlenable[3], tx_datain_wire[31:24]}),
.hipdetectrxloop(tx_detectrxloop[3]),
.hipelecidleinfersel(rx_elecidleinfersel[11:9]),
.hipforceelecidle(tx_forceelecidle[3]),
.hippowerdn(powerdn[7:6]),
.hiptxclkout(),
.hiptxdeemph(tx_pipedeemph[3]),
.hiptxmargin(tx_pipemargin[11:9]),
.invpol(tx_invpolarity[3]),
.iqpphfifobyteselout(),
.iqpphfifordclkout(),
.iqpphfifordenableout(),
.iqpphfifowrenableout(),
.localrefclk(tx_localrefclk[3]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[3]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[3]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs3_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[3]),
.phfiforesetout(wire_transmit_pcs3_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs3_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[11:9]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[11:9]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[11:9]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[11:9]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[11:9]),
.pipeenrevparallellpbkout(wire_transmit_pcs3_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs3_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs3_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[3]),
.pipetxswing(tx_pipeswing[3]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[79:60]),
.txdetectrx(wire_transmit_pcs3_txdetectrx),
.xgmctrl(cent_unit_txctrlout[3]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[31:24]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.coreclk(1'b0),
.datain({40{1'b0}}),
.detectrxloop(1'b0),
.elecidleinfersel({3{1'b0}}),
.forceelecidle(1'b0),
.freezptr(1'b0),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnrdclk({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.pipetxdeemph(1'b0),
.pipetxmargin({3{1'b0}}),
.powerdn({2{1'b0}}),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs3.allow_polarity_inversion = "false",
transmit_pcs3.auto_spd_self_switch_enable = "false",
transmit_pcs3.bitslip_enable = "false",
transmit_pcs3.channel_bonding = "x4",
transmit_pcs3.channel_number = ((starting_channel_number + 3) % 4),
transmit_pcs3.channel_width = 8,
transmit_pcs3.core_clock_0ppm = "false",
transmit_pcs3.datapath_low_latency_mode = "false",
transmit_pcs3.datapath_protocol = "pipe",
transmit_pcs3.disable_ph_low_latency_mode = "false",
transmit_pcs3.disparity_mode = "new",
transmit_pcs3.dprio_config_mode = 6'h01,
transmit_pcs3.elec_idle_delay = 6,
transmit_pcs3.enable_bit_reversal = "false",
transmit_pcs3.enable_idle_selection = "false",
transmit_pcs3.enable_reverse_parallel_loopback = "true",
transmit_pcs3.enable_self_test_mode = "false",
transmit_pcs3.enable_symbol_swap = "false",
transmit_pcs3.enc_8b_10b_compatibility_mode = "true",
transmit_pcs3.enc_8b_10b_mode = "normal",
transmit_pcs3.force_echar = "false",
transmit_pcs3.force_kchar = "false",
transmit_pcs3.hip_enable = "true",
transmit_pcs3.logical_channel_address = (starting_channel_number + 3),
transmit_pcs3.ph_fifo_reg_mode = "true",
transmit_pcs3.ph_fifo_xn_mapping0 = "none",
transmit_pcs3.ph_fifo_xn_mapping1 = "none",
transmit_pcs3.ph_fifo_xn_mapping2 = "central",
transmit_pcs3.ph_fifo_xn_select = 2,
transmit_pcs3.pipe_auto_speed_nego_enable = "true",
transmit_pcs3.pipe_freq_scale_mode = "Frequency",
transmit_pcs3.pipe_voltage_swing_control = "false",
transmit_pcs3.prbs_cid_pattern = "false",
transmit_pcs3.protocol_hint = "pcie2",
transmit_pcs3.refclk_select = "cmu_clock_divider",
transmit_pcs3.self_test_mode = "incremental",
transmit_pcs3.use_double_data_mode = "false",
transmit_pcs3.use_serializer_double_data_mode = "false",
transmit_pcs3.wr_clk_mux_select = "int_clk",
transmit_pcs3.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pma transmit_pma0
(
.clockout(wire_transmit_pma0_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[19:0]}),
.dataout(wire_transmit_pma0_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[299:0]),
.dprioout(wire_transmit_pma0_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[0]),
.powerdn(cent_unit_txobpowerdn[0]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[0]),
.rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
.rxfoundout(wire_transmit_pma0_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma0.analog_power = "auto",
transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pma0.channel_type = "auto",
transmit_pma0.clkin_select = 1,
transmit_pma0.clkmux_delay = "false",
transmit_pma0.common_mode = "0.65V",
transmit_pma0.dprio_config_mode = 6'h01,
transmit_pma0.enable_reverse_serial_loopback = "false",
transmit_pma0.logical_channel_address = (starting_channel_number + 0),
transmit_pma0.logical_protocol_hint_0 = "pcie2",
transmit_pma0.low_speed_test_select = 0,
transmit_pma0.physical_clkin1_mapping = "x4",
transmit_pma0.preemp_pretap = 0,
transmit_pma0.preemp_pretap_inv = "false",
transmit_pma0.preemp_tap_1 = 0,
transmit_pma0.preemp_tap_1_a = 28,
transmit_pma0.preemp_tap_1_b = 22,
transmit_pma0.preemp_tap_1_c = 7,
transmit_pma0.preemp_tap_2 = 0,
transmit_pma0.preemp_tap_2_inv = "false",
transmit_pma0.protocol_hint = "pcie2",
transmit_pma0.rx_detect = 0,
transmit_pma0.serialization_factor = 10,
transmit_pma0.slew_rate = "off",
transmit_pma0.termination = "OCT 100 Ohms",
transmit_pma0.use_external_termination = "false",
transmit_pma0.use_pma_direct = "false",
transmit_pma0.use_ser_double_data_mode = "false",
transmit_pma0.vod_selection = 3,
transmit_pma0.vod_selection_a = 6,
transmit_pma0.vod_selection_c = 1,
transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma1
(
.clockout(wire_transmit_pma1_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[39:20]}),
.dataout(wire_transmit_pma1_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[599:300]),
.dprioout(wire_transmit_pma1_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[1]),
.powerdn(cent_unit_txobpowerdn[1]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[1]),
.rxdetectvalidout(wire_transmit_pma1_rxdetectvalidout),
.rxfoundout(wire_transmit_pma1_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[1])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma1.analog_power = "auto",
transmit_pma1.channel_number = ((starting_channel_number + 1) % 4),
transmit_pma1.channel_type = "auto",
transmit_pma1.clkin_select = 1,
transmit_pma1.clkmux_delay = "false",
transmit_pma1.common_mode = "0.65V",
transmit_pma1.dprio_config_mode = 6'h01,
transmit_pma1.enable_reverse_serial_loopback = "false",
transmit_pma1.logical_channel_address = (starting_channel_number + 1),
transmit_pma1.logical_protocol_hint_0 = "pcie2",
transmit_pma1.low_speed_test_select = 0,
transmit_pma1.physical_clkin1_mapping = "x4",
transmit_pma1.preemp_pretap = 0,
transmit_pma1.preemp_pretap_inv = "false",
transmit_pma1.preemp_tap_1 = 0,
transmit_pma1.preemp_tap_1_a = 28,
transmit_pma1.preemp_tap_1_b = 22,
transmit_pma1.preemp_tap_1_c = 7,
transmit_pma1.preemp_tap_2 = 0,
transmit_pma1.preemp_tap_2_inv = "false",
transmit_pma1.protocol_hint = "pcie2",
transmit_pma1.rx_detect = 0,
transmit_pma1.serialization_factor = 10,
transmit_pma1.slew_rate = "off",
transmit_pma1.termination = "OCT 100 Ohms",
transmit_pma1.use_external_termination = "false",
transmit_pma1.use_pma_direct = "false",
transmit_pma1.use_ser_double_data_mode = "false",
transmit_pma1.vod_selection = 3,
transmit_pma1.vod_selection_a = 6,
transmit_pma1.vod_selection_c = 1,
transmit_pma1.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma2
(
.clockout(wire_transmit_pma2_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[59:40]}),
.dataout(wire_transmit_pma2_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[2]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[899:600]),
.dprioout(wire_transmit_pma2_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[2]),
.powerdn(cent_unit_txobpowerdn[2]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[2]),
.rxdetectvalidout(wire_transmit_pma2_rxdetectvalidout),
.rxfoundout(wire_transmit_pma2_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[2])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma2.analog_power = "auto",
transmit_pma2.channel_number = ((starting_channel_number + 2) % 4),
transmit_pma2.channel_type = "auto",
transmit_pma2.clkin_select = 1,
transmit_pma2.clkmux_delay = "false",
transmit_pma2.common_mode = "0.65V",
transmit_pma2.dprio_config_mode = 6'h01,
transmit_pma2.enable_reverse_serial_loopback = "false",
transmit_pma2.logical_channel_address = (starting_channel_number + 2),
transmit_pma2.logical_protocol_hint_0 = "pcie2",
transmit_pma2.low_speed_test_select = 0,
transmit_pma2.physical_clkin1_mapping = "x4",
transmit_pma2.preemp_pretap = 0,
transmit_pma2.preemp_pretap_inv = "false",
transmit_pma2.preemp_tap_1 = 0,
transmit_pma2.preemp_tap_1_a = 28,
transmit_pma2.preemp_tap_1_b = 22,
transmit_pma2.preemp_tap_1_c = 7,
transmit_pma2.preemp_tap_2 = 0,
transmit_pma2.preemp_tap_2_inv = "false",
transmit_pma2.protocol_hint = "pcie2",
transmit_pma2.rx_detect = 0,
transmit_pma2.serialization_factor = 10,
transmit_pma2.slew_rate = "off",
transmit_pma2.termination = "OCT 100 Ohms",
transmit_pma2.use_external_termination = "false",
transmit_pma2.use_pma_direct = "false",
transmit_pma2.use_ser_double_data_mode = "false",
transmit_pma2.vod_selection = 3,
transmit_pma2.vod_selection_a = 6,
transmit_pma2.vod_selection_c = 1,
transmit_pma2.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma3
(
.clockout(wire_transmit_pma3_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[79:60]}),
.dataout(wire_transmit_pma3_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[3]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[1199:900]),
.dprioout(wire_transmit_pma3_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[3]),
.powerdn(cent_unit_txobpowerdn[3]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[3]),
.rxdetectvalidout(wire_transmit_pma3_rxdetectvalidout),
.rxfoundout(wire_transmit_pma3_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[3])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma3.analog_power = "auto",
transmit_pma3.channel_number = ((starting_channel_number + 3) % 4),
transmit_pma3.channel_type = "auto",
transmit_pma3.clkin_select = 1,
transmit_pma3.clkmux_delay = "false",
transmit_pma3.common_mode = "0.65V",
transmit_pma3.dprio_config_mode = 6'h01,
transmit_pma3.enable_reverse_serial_loopback = "false",
transmit_pma3.logical_channel_address = (starting_channel_number + 3),
transmit_pma3.logical_protocol_hint_0 = "pcie2",
transmit_pma3.low_speed_test_select = 0,
transmit_pma3.physical_clkin1_mapping = "x4",
transmit_pma3.preemp_pretap = 0,
transmit_pma3.preemp_pretap_inv = "false",
transmit_pma3.preemp_tap_1 = 0,
transmit_pma3.preemp_tap_1_a = 28,
transmit_pma3.preemp_tap_1_b = 22,
transmit_pma3.preemp_tap_1_c = 7,
transmit_pma3.preemp_tap_2 = 0,
transmit_pma3.preemp_tap_2_inv = "false",
transmit_pma3.protocol_hint = "pcie2",
transmit_pma3.rx_detect = 0,
transmit_pma3.serialization_factor = 10,
transmit_pma3.slew_rate = "off",
transmit_pma3.termination = "OCT 100 Ohms",
transmit_pma3.use_external_termination = "false",
transmit_pma3.use_pma_direct = "false",
transmit_pma3.use_ser_double_data_mode = "false",
transmit_pma3.vod_selection = 3,
transmit_pma3.vod_selection_a = 6,
transmit_pma3.vod_selection_c = 1,
transmit_pma3.lpm_type = "stratixiv_hssi_tx_pma";
assign
cal_blk_powerdown = 1'b0,
cent_unit_clkdivpowerdn = {wire_cent_unit0_clkdivpowerdn[0]},
cent_unit_cmudividerdprioout = {wire_cent_unit0_cmudividerdprioout},
cent_unit_cmuplldprioout = {wire_cent_unit0_cmuplldprioout},
cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
cent_unit_rxpcsdprioin = {rx_pcsdprioout[1599:0]},
cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[1599:0]},
cent_unit_rxpmadprioin = {{2{{300{1'b0}}}}, rx_pmadprioout[1199:0]},
cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[1799:0]},
cent_unit_tx_dprioin = {{600{1'b0}}, tx_txdprioout[599:0]},
cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout[31:0]},
cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[5:0]},
cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[599:0]},
cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
cent_unit_txpmadprioin = {{2{{300{1'b0}}}}, tx_pmadprioout[1199:0]},
cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[1799:0]},
clk_div_clk0in = {pll0_out[3:0]},
clk_div_cmudividerdprioin = {{100{1'b0}}, wire_central_clk_div0_dprioout, {400{1'b0}}},
cmu_analogfastrefclkout = {wire_central_clk_div0_analogfastrefclkout},
cmu_analogrefclkout = {wire_central_clk_div0_analogrefclkout},
cmu_analogrefclkpulse = {wire_central_clk_div0_analogrefclkpulse},
coreclkout = {coreclkout_wire[0]},
coreclkout_wire = {wire_central_clk_div0_coreclkout},
fixedclk_div_in = {fixedclk_div5quad0c, fixedclk_div4quad0c, fixedclk_div3quad0c, fixedclk_div2quad0c, fixedclk_div1quad0c, fixedclk_div0quad0c},
fixedclk_enable = reconfig_togxb_busy_reg[0],
fixedclk_fast = {6{1'b1}},
fixedclk_in = {{2{1'b0}}, {4{fixedclk}}},
fixedclk_sel = reconfig_togxb_busy_reg[1],
fixedclk_to_cmu = {((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[5]) & fixedclk_div_in[5]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[5])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[4]) & fixedclk_div_in[4]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[4])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[3]) & fixedclk_div_in[3]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[3])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[2]) & fixedclk_div_in[2]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[2])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[1]) & fixedclk_div_in[1]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[1])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[0]) & fixedclk_div_in[0]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[0]))},
hip_tx_clkout = {{3{1'b0}}, wire_central_clk_div0_refclkout},
int_autospdx4configsel = {wire_cent_unit0_autospdx4configsel},
int_autospdx4rateswitchout = {wire_cent_unit0_autospdx4rateswitchout},
int_autospdx4spdchg = {wire_cent_unit0_autospdx4spdchg},
int_hipautospdrateswitchout = {wire_receive_pcs3_autospdrateswitchout, wire_receive_pcs2_autospdrateswitchout, wire_receive_pcs1_autospdrateswitchout, wire_receive_pcs0_autospdrateswitchout},
int_hiprateswtichdone = {wire_central_clk_div0_rateswitchdone},
int_phfifiox4ptrsreset = {wire_cent_unit0_phfifiox4ptrsreset},
int_pipeenrevparallellpbkfromtx = {wire_transmit_pcs3_pipeenrevparallellpbkout, wire_transmit_pcs2_pipeenrevparallellpbkout, wire_transmit_pcs1_pipeenrevparallellpbkout, wire_transmit_pcs0_pipeenrevparallellpbkout},
int_rateswitch = {int_rx_rateswitchout[0]},
int_rx_autospdxnconfigsel = {int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}},
int_rx_autospdxnspdchg = {int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}},
int_rx_coreclkout = {wire_receive_pcs3_coreclkout, wire_receive_pcs2_coreclkout, wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
int_rx_digitalreset_reg = {rx_digitalreset_reg0c[2]},
int_rx_phfifioxnptrsreset = {int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}},
int_rx_phfifobyteserdisable = {wire_receive_pcs3_phfifobyteserdisableout, wire_receive_pcs2_phfifobyteserdisableout, wire_receive_pcs1_phfifobyteserdisableout, wire_receive_pcs0_phfifobyteserdisableout},
int_rx_phfifoptrsresetout = {wire_receive_pcs3_phfifoptrsresetout, wire_receive_pcs2_phfifoptrsresetout, wire_receive_pcs1_phfifoptrsresetout, wire_receive_pcs0_phfifoptrsresetout},
int_rx_phfifordenableout = {wire_receive_pcs3_phfifordenableout, wire_receive_pcs2_phfifordenableout, wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
int_rx_phfiforesetout = {wire_receive_pcs3_phfiforesetout, wire_receive_pcs2_phfiforesetout, wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
int_rx_phfifowrdisableout = {wire_receive_pcs3_phfifowrdisableout, wire_receive_pcs2_phfifowrdisableout, wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
int_rx_phfifoxnbytesel = {int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}},
int_rx_phfifoxnrdenable = {int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}},
int_rx_phfifoxnwrclk = {int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}},
int_rx_phfifoxnwrenable = {int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}},
int_rx_rateswitchout = {wire_receive_pcs3_rateswitchout, wire_receive_pcs2_rateswitchout, wire_receive_pcs1_rateswitchout, wire_receive_pcs0_rateswitchout},
int_rxcoreclk = {int_rx_coreclkout[0]},
int_rxpcs_cdrctrlearlyeios = {wire_receive_pcs3_cdrctrlearlyeios, wire_receive_pcs2_cdrctrlearlyeios, wire_receive_pcs1_cdrctrlearlyeios, wire_receive_pcs0_cdrctrlearlyeios},
int_rxphfifordenable = {int_rx_phfifordenableout[0]},
int_rxphfiforeset = {int_rx_phfiforesetout[0]},
int_rxphfifox4byteselout = {wire_cent_unit0_rxphfifox4byteselout},
int_rxphfifox4rdenableout = {wire_cent_unit0_rxphfifox4rdenableout},
int_rxphfifox4wrclkout = {wire_cent_unit0_rxphfifox4wrclkout},
int_rxphfifox4wrenableout = {wire_cent_unit0_rxphfifox4wrenableout},
int_tx_coreclkout = {wire_transmit_pcs3_coreclkout, wire_transmit_pcs2_coreclkout, wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
int_tx_digitalreset_reg = {tx_digitalreset_reg0c[2]},
int_tx_phfifioxnptrsreset = {int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}},
int_tx_phfiforddisableout = {wire_transmit_pcs3_phfiforddisableout, wire_transmit_pcs2_phfiforddisableout, wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
int_tx_phfiforesetout = {wire_transmit_pcs3_phfiforesetout, wire_transmit_pcs2_phfiforesetout, wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
int_tx_phfifowrenableout = {wire_transmit_pcs3_phfifowrenableout, wire_transmit_pcs2_phfifowrenableout, wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
int_tx_phfifoxnbytesel = {int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}},
int_tx_phfifoxnrdclk = {int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}},
int_tx_phfifoxnrdenable = {int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}},
int_tx_phfifoxnwrenable = {int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}},
int_txcoreclk = {int_tx_coreclkout[0]},
int_txphfiforddisable = {int_tx_phfiforddisableout[0]},
int_txphfiforeset = {int_tx_phfiforesetout[0]},
int_txphfifowrenable = {int_tx_phfifowrenableout[0]},
int_txphfifox4byteselout = {wire_cent_unit0_txphfifox4byteselout},
int_txphfifox4rdclkout = {wire_cent_unit0_txphfifox4rdclkout},
int_txphfifox4rdenableout = {wire_cent_unit0_txphfifox4rdenableout},
int_txphfifox4wrenableout = {wire_cent_unit0_txphfifox4wrenableout},
nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
pipedatavalid = {pipedatavalid_out[3:0]},
pipedatavalid_out = {wire_receive_pcs3_hipdatavalid, wire_receive_pcs2_hipdatavalid, wire_receive_pcs1_hipdatavalid, wire_receive_pcs0_hipdatavalid},
pipeelecidle = {pipeelecidle_out[3:0]},
pipeelecidle_out = {wire_receive_pcs3_hipelecidle, wire_receive_pcs2_hipelecidle, wire_receive_pcs1_hipelecidle, wire_receive_pcs0_hipelecidle},
pipephydonestatus = {wire_receive_pcs3_hipphydonestatus, wire_receive_pcs2_hipphydonestatus, wire_receive_pcs1_hipphydonestatus, wire_receive_pcs0_hipphydonestatus},
pipestatus = {wire_receive_pcs3_hipstatus, wire_receive_pcs2_hipstatus, wire_receive_pcs1_hipstatus, wire_receive_pcs0_hipstatus},
pll0_clkin = {{9{1'b0}}, pll_inclk_wire[0]},
pll0_dprioin = {cent_unit_cmuplldprioout[1499:1200]},
pll0_dprioout = {wire_tx_pll0_dprioout},
pll0_out = {wire_tx_pll0_clk[3:0]},
pll_ch_dataout_wire = {wire_rx_cdr_pll3_dataout, wire_rx_cdr_pll2_dataout, wire_rx_cdr_pll1_dataout, wire_rx_cdr_pll0_dataout},
pll_ch_dprioout = {wire_rx_cdr_pll3_dprioout, wire_rx_cdr_pll2_dprioout, wire_rx_cdr_pll1_dprioout, wire_rx_cdr_pll0_dprioout},
pll_cmuplldprioout = {{300{1'b0}}, pll0_dprioout[299:0], pll_ch_dprioout[1199:0]},
pll_inclk_wire = {pll_inclk},
pll_locked = {pll_locked_out[0]},
pll_locked_out = {wire_tx_pll0_locked},
pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
pllreset_in = {1'b0, cent_unit_pllresetout[0]},
rateswitchbaseclock = {wire_central_clk_div0_rateswitchbaseclock},
reconfig_fromgxb = {rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout},
reconfig_togxb_busy = reconfig_togxb[3],
reconfig_togxb_disable = reconfig_togxb[1],
reconfig_togxb_in = reconfig_togxb[0],
reconfig_togxb_load = reconfig_togxb[2],
refclk_pma = {wire_central_clk_div0_refclkout},
rx_analogreset_in = {{2{1'b0}}, {4{((~ reconfig_togxb_busy) & rx_analogreset[0])}}},
rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
rx_cruclk_in = {{9{1'b0}}, rx_pldcruclk_in[3], {9{1'b0}}, rx_pldcruclk_in[2], {9{1'b0}}, rx_pldcruclk_in[1], {9{1'b0}}, rx_pldcruclk_in[0]},
rx_ctrldetect = {wire_receive_pcs3_hipdataout[8], wire_receive_pcs2_hipdataout[8], wire_receive_pcs1_hipdataout[8], wire_receive_pcs0_hipdataout[8]},
rx_dataout = {rx_out_wire[31:0]},
rx_deserclock_in = {rx_pll_clkout[15:0]},
rx_digitalreset_in = {4{int_rx_digitalreset_reg[0]}},
rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]},
rx_enapatternalign = {4{1'b0}},
rx_freqlocked = {(rx_freqlocked_wire[3] & (~ rx_analogreset[0])), (rx_freqlocked_wire[2] & (~ rx_analogreset[0])), (rx_freqlocked_wire[1] & (~ rx_analogreset[0])), (rx_freqlocked_wire[0] & (~ rx_analogreset[0]))},
rx_freqlocked_wire = {wire_rx_cdr_pll3_freqlocked, wire_rx_cdr_pll2_freqlocked, wire_rx_cdr_pll1_freqlocked, wire_rx_cdr_pll0_freqlocked},
rx_locktodata = {4{1'b0}},
rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[3]), ((~ reconfig_togxb_busy) & rx_locktodata[2]), ((~ reconfig_togxb_busy) & rx_locktodata[1]), ((~ reconfig_togxb_busy) & rx_locktodata[0])},
rx_locktorefclk_wire = {wire_receive_pcs3_cdrctrllocktorefclkout, wire_receive_pcs2_cdrctrllocktorefclkout, wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
rx_out_wire = {wire_receive_pcs3_hipdataout[7:0], wire_receive_pcs2_hipdataout[7:0], wire_receive_pcs1_hipdataout[7:0], wire_receive_pcs0_hipdataout[7:0]},
rx_pcs_rxfound_wire = {txdetectrxout[3], tx_rxfoundout[3], txdetectrxout[2], tx_rxfoundout[2], txdetectrxout[1], tx_rxfoundout[1], txdetectrxout[0], tx_rxfoundout[0]},
rx_pcsdprioin_wire = {cent_unit_rxpcsdprioout[1599:0]},
rx_pcsdprioout = {wire_receive_pcs3_dprioout, wire_receive_pcs2_dprioout, wire_receive_pcs1_dprioout, wire_receive_pcs0_dprioout},
rx_phfifordenable = {4{1'b1}},
rx_phfiforeset = {4{1'b0}},
rx_phfifowrdisable = {4{1'b0}},
rx_pipestatetransdoneout = {wire_receive_pcs3_pipestatetransdoneout, wire_receive_pcs2_pipestatetransdoneout, wire_receive_pcs1_pipestatetransdoneout, wire_receive_pcs0_pipestatetransdoneout},
rx_pldcruclk_in = {rx_cruclk[3:0]},
rx_pll_clkout = {wire_rx_cdr_pll3_clk, wire_rx_cdr_pll2_clk, wire_rx_cdr_pll1_clk, wire_rx_cdr_pll0_clk},
rx_pll_locked = {(rx_plllocked_wire[3] & (~ rx_analogreset[0])), (rx_plllocked_wire[2] & (~ rx_analogreset[0])), (rx_plllocked_wire[1] & (~ rx_analogreset[0])), (rx_plllocked_wire[0] & (~ rx_analogreset[0]))},
rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll3_pfdrefclkout, wire_rx_cdr_pll2_pfdrefclkout, wire_rx_cdr_pll1_pfdrefclkout, wire_rx_cdr_pll0_pfdrefclkout},
rx_plllocked_wire = {wire_rx_cdr_pll3_locked, wire_rx_cdr_pll2_locked, wire_rx_cdr_pll1_locked, wire_rx_cdr_pll0_locked},
rx_pma_analogtestbus = {{51{1'b0}}, wire_receive_pma3_analogtestbus[5:2], wire_receive_pma2_analogtestbus[5:2], wire_receive_pma1_analogtestbus[5:2], wire_receive_pma0_analogtestbus[5:2], 1'b0},
rx_pma_clockout = {wire_receive_pma3_clockout, wire_receive_pma2_clockout, wire_receive_pma1_clockout, wire_receive_pma0_clockout},
rx_pma_dataout = {wire_receive_pma3_dataout, wire_receive_pma2_dataout, wire_receive_pma1_dataout, wire_receive_pma0_dataout},
rx_pma_locktorefout = {wire_receive_pma3_locktorefout, wire_receive_pma2_locktorefout, wire_receive_pma1_locktorefout, wire_receive_pma0_locktorefout},
rx_pma_recoverdataout_wire = {wire_receive_pma3_recoverdataout[19:0], wire_receive_pma2_recoverdataout[19:0], wire_receive_pma1_recoverdataout[19:0], wire_receive_pma0_recoverdataout[19:0]},
rx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_rxpmadprioout[1199:0]},
rx_pmadprioout = {{2{{300{1'b0}}}}, wire_receive_pma3_dprioout, wire_receive_pma2_dprioout, wire_receive_pma1_dprioout, wire_receive_pma0_dprioout},
rx_powerdown = {4{1'b0}},
rx_powerdown_in = {{2{1'b0}}, rx_powerdown[3:0]},
rx_prbscidenable = {4{1'b0}},
rx_revparallelfdbkdata = {wire_receive_pcs3_revparallelfdbkdata, wire_receive_pcs2_revparallelfdbkdata, wire_receive_pcs1_revparallelfdbkdata, wire_receive_pcs0_revparallelfdbkdata},
rx_rmfiforeset = {4{1'b0}},
rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
rx_signaldetect = {rx_signaldetectout_wire[3:0]},
rx_signaldetect_wire = {wire_receive_pma3_signaldetect, wire_receive_pma2_signaldetect, wire_receive_pma1_signaldetect, wire_receive_pma0_signaldetect},
rx_signaldetectout_wire = {wire_receive_pcs3_signaldetect, wire_receive_pcs2_signaldetect, wire_receive_pcs1_signaldetect, wire_receive_pcs0_signaldetect},
rxphfifowrdisable = {int_rx_phfifowrdisableout[0]},
rxpll_dprioin = {{2{{300{1'b0}}}}, cent_unit_cmuplldprioout[1199:0]},
tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
tx_datain_wire = {tx_datain[31:0]},
tx_dataout = {wire_transmit_pma3_dataout, wire_transmit_pma2_dataout, wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
tx_dataout_pcs_to_pma = {wire_transmit_pcs3_dataout, wire_transmit_pcs2_dataout, wire_transmit_pcs1_dataout, wire_transmit_pcs0_dataout},
tx_digitalreset_in = {4{int_tx_digitalreset_reg[0]}},
tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]},
tx_dprioin_wire = {{600{1'b0}}, cent_unit_txdprioout[599:0]},
tx_invpolarity = {4{1'b0}},
tx_localrefclk = {wire_transmit_pma3_clockout, wire_transmit_pma2_clockout, wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
tx_pcs_forceelecidleout = {wire_transmit_pcs3_forceelecidleout, wire_transmit_pcs2_forceelecidleout, wire_transmit_pcs1_forceelecidleout, wire_transmit_pcs0_forceelecidleout},
tx_phfiforeset = {4{1'b0}},
tx_pipepowerdownout = {wire_transmit_pcs3_pipepowerdownout, wire_transmit_pcs2_pipepowerdownout, wire_transmit_pcs1_pipepowerdownout, wire_transmit_pcs0_pipepowerdownout},
tx_pipepowerstateout = {wire_transmit_pcs3_pipepowerstateout, wire_transmit_pcs2_pipepowerstateout, wire_transmit_pcs1_pipepowerstateout, wire_transmit_pcs0_pipepowerstateout},
tx_pipeswing = {4{1'b0}},
tx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_txpmadprioout[1199:0]},
tx_pmadprioout = {{2{{300{1'b0}}}}, wire_transmit_pma3_dprioout, wire_transmit_pma2_dprioout, wire_transmit_pma1_dprioout, wire_transmit_pma0_dprioout},
tx_revparallellpbken = {4{1'b0}},
tx_rxdetectvalidout = {wire_transmit_pma3_rxdetectvalidout, wire_transmit_pma2_rxdetectvalidout, wire_transmit_pma1_rxdetectvalidout, wire_transmit_pma0_rxdetectvalidout},
tx_rxfoundout = {wire_transmit_pma3_rxfoundout, wire_transmit_pma2_rxfoundout, wire_transmit_pma1_rxfoundout, wire_transmit_pma0_rxfoundout},
tx_txdprioout = {wire_transmit_pcs3_dprioout, wire_transmit_pcs2_dprioout, wire_transmit_pcs1_dprioout, wire_transmit_pcs0_dprioout},
txdetectrxout = {wire_transmit_pcs3_txdetectrx, wire_transmit_pcs2_txdetectrx, wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx},
w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
endmodule //pcie_hip_s4gx_gen2_x4_128_serdes_alt4gxb_svoa
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pcie_hip_s4gx_gen2_x4_128_serdes (
cal_blk_clk,
fixedclk,
gxb_powerdown,
pipe8b10binvpolarity,
pll_inclk,
pll_powerdown,
powerdn,
rateswitch,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
rx_elecidleinfersel,
tx_ctrlenable,
tx_datain,
tx_detectrxloop,
tx_digitalreset,
tx_forcedispcompliance,
tx_forceelecidle,
tx_pipedeemph,
tx_pipemargin,
coreclkout,
hip_tx_clkout,
pipedatavalid,
pipeelecidle,
pipephydonestatus,
pipestatus,
pll_locked,
rateswitchbaseclock,
reconfig_fromgxb,
rx_ctrldetect,
rx_dataout,
rx_freqlocked,
rx_patterndetect,
rx_pll_locked,
rx_signaldetect,
rx_syncstatus,
tx_dataout)/* synthesis synthesis_clearbox = 2 */;
input cal_blk_clk;
input fixedclk;
input [0:0] gxb_powerdown;
input [3:0] pipe8b10binvpolarity;
input pll_inclk;
input [0:0] pll_powerdown;
input [7:0] powerdn;
input [0:0] rateswitch;
input reconfig_clk;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [3:0] rx_cruclk;
input [3:0] rx_datain;
input [0:0] rx_digitalreset;
input [11:0] rx_elecidleinfersel;
input [3:0] tx_ctrlenable;
input [31:0] tx_datain;
input [3:0] tx_detectrxloop;
input [0:0] tx_digitalreset;
input [3:0] tx_forcedispcompliance;
input [3:0] tx_forceelecidle;
input [3:0] tx_pipedeemph;
input [11:0] tx_pipemargin;
output [0:0] coreclkout;
output [3:0] hip_tx_clkout;
output [3:0] pipedatavalid;
output [3:0] pipeelecidle;
output [3:0] pipephydonestatus;
output [11:0] pipestatus;
output [0:0] pll_locked;
output [0:0] rateswitchbaseclock;
output [16:0] reconfig_fromgxb;
output [3:0] rx_ctrldetect;
output [31:0] rx_dataout;
output [3:0] rx_freqlocked;
output [3:0] rx_patterndetect;
output [3:0] rx_pll_locked;
output [3:0] rx_signaldetect;
output [3:0] rx_syncstatus;
output [3:0] tx_dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [3:0] rx_cruclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
wire [3:0] sub_wire0;
wire [3:0] sub_wire1;
wire [16:0] sub_wire2;
wire [11:0] sub_wire3;
wire [3:0] sub_wire4;
wire [3:0] sub_wire5;
wire [0:0] sub_wire6;
wire [31:0] sub_wire7;
wire [3:0] sub_wire8;
wire [3:0] sub_wire9;
wire [0:0] sub_wire10;
wire [3:0] sub_wire11;
wire [3:0] sub_wire12;
wire [3:0] sub_wire13;
wire [3:0] sub_wire14;
wire [0:0] sub_wire15;
wire [3:0] sub_wire16;
wire [3:0] rx_patterndetect = sub_wire0[3:0];
wire [3:0] rx_signaldetect = sub_wire1[3:0];
wire [16:0] reconfig_fromgxb = sub_wire2[16:0];
wire [11:0] pipestatus = sub_wire3[11:0];
wire [3:0] rx_pll_locked = sub_wire4[3:0];
wire [3:0] rx_syncstatus = sub_wire5[3:0];
wire [0:0] coreclkout = sub_wire6[0:0];
wire [31:0] rx_dataout = sub_wire7[31:0];
wire [3:0] hip_tx_clkout = sub_wire8[3:0];
wire [3:0] pipeelecidle = sub_wire9[3:0];
wire [0:0] rateswitchbaseclock = sub_wire10[0:0];
wire [3:0] tx_dataout = sub_wire11[3:0];
wire [3:0] rx_ctrldetect = sub_wire12[3:0];
wire [3:0] pipedatavalid = sub_wire13[3:0];
wire [3:0] pipephydonestatus = sub_wire14[3:0];
wire [0:0] pll_locked = sub_wire15[0:0];
wire [3:0] rx_freqlocked = sub_wire16[3:0];
pcie_hip_s4gx_gen2_x4_128_serdes_alt4gxb_svoa pcie_hip_s4gx_gen2_x4_128_serdes_alt4gxb_svoa_component (
.reconfig_togxb (reconfig_togxb),
.cal_blk_clk (cal_blk_clk),
.tx_forceelecidle (tx_forceelecidle),
.fixedclk (fixedclk),
.rx_datain (rx_datain),
.rx_digitalreset (rx_digitalreset),
.pipe8b10binvpolarity (pipe8b10binvpolarity),
.pll_powerdown (pll_powerdown),
.tx_datain (tx_datain),
.tx_digitalreset (tx_digitalreset),
.tx_pipedeemph (tx_pipedeemph),
.gxb_powerdown (gxb_powerdown),
.rx_cruclk (rx_cruclk),
.tx_forcedispcompliance (tx_forcedispcompliance),
.rateswitch (rateswitch),
.reconfig_clk (reconfig_clk),
.rx_analogreset (rx_analogreset),
.powerdn (powerdn),
.tx_ctrlenable (tx_ctrlenable),
.tx_pipemargin (tx_pipemargin),
.pll_inclk (pll_inclk),
.rx_elecidleinfersel (rx_elecidleinfersel),
.tx_detectrxloop (tx_detectrxloop),
.rx_patterndetect (sub_wire0),
.rx_signaldetect (sub_wire1),
.reconfig_fromgxb (sub_wire2),
.pipestatus (sub_wire3),
.rx_pll_locked (sub_wire4),
.rx_syncstatus (sub_wire5),
.coreclkout (sub_wire6),
.rx_dataout (sub_wire7),
.hip_tx_clkout (sub_wire8),
.pipeelecidle (sub_wire9),
.rateswitchbaseclock (sub_wire10),
.tx_dataout (sub_wire11),
.rx_ctrldetect (sub_wire12),
.pipedatavalid (sub_wire13),
.pipephydonestatus (sub_wire14),
.pll_locked (sub_wire15),
.rx_freqlocked (sub_wire16))/* synthesis synthesis_clearbox=2
clearbox_macroname = alt4gxb
clearbox_defparam = "effective_data_rate=5000 Mbps;enable_lc_tx_pll=false;equalizer_ctrl_a_setting=0;equalizer_ctrl_b_setting=0;equalizer_ctrl_c_setting=0;equalizer_ctrl_d_setting=0;equalizer_ctrl_v_setting=0;equalizer_dcgain_setting=1;gen_reconfig_pll=false;gxb_analog_power=AUTO;gx_channel_type=AUTO;input_clock_frequency=100.0 MHz;intended_device_family=Stratix IV;intended_device_speed_grade=2;intended_device_variant=GX;loopback_mode=none;lpm_type=alt4gxb;number_of_channels=4;operation_mode=duplex;pll_control_width=1;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=0;protocol=pcie2;receiver_termination=oct_100_ohms;reconfig_dprio_mode=1;rx_8b_10b_mode=normal;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=true;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_bonding=x4;rx_channel_width=8;rx_common_mode=0.82v;rx_cru_bandwidth_type=Auto;rx_cru_inclock0_period=10000;rx_datapath_protocol=pipe;rx_data_rate=5000;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=true;rx_ppmselect=32;rx_rate_match_fifo_mode=normal;rx_rate_match_pattern1=11010000111010000011;rx_rate_match_pattern2=00101111000101111100;rx_rate_match_pattern_size=20;rx_run_length=40;rx_run_length_enable=true;rx_signal_detect_threshold=4;rx_use_align_state_machine=true;
rx_use_clkout=false;rx_use_coreclk=false;rx_use_cruclk=true;rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=false;rx_use_pipe8b10binvpolarity=true;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_analog_power=AUTO;tx_channel_bonding=x4;tx_channel_width=8;tx_clkout_width=4;tx_common_mode=0.65v;tx_data_rate=5000;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=High;tx_pll_inclk0_period=10000;tx_pll_type=CMU;tx_slew_rate=off;tx_transmit_protocol=pipe;tx_use_coreclk=false;tx_use_double_data_mode=false;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=3;coreclkout_control_width=1;elec_idle_infer_enable=false;enable_0ppm=false;gxb_powerdown_width=1;hip_enable=true;number_of_quads=1;rateswitch_control_width=1;reconfig_calibration=true;reconfig_fromgxb_port_width=17;reconfig_togxb_port_width=4;rx_cdrctrl_enable=true;rx_cru_m_divider=0;rx_cru_n_divider=1;rx_cru_vco_post_scale_divider=1;rx_dwidth_factor=1;rx_signal_detect_loss_threshold=3;rx_signal_detect_valid_threshold=14;rx_use_external_termination=false;rx_word_aligner_num_byte=1;tx_dwidth_factor=1;tx_pll_clock_post_divider=1;tx_pll_m_divider=0;tx_pll_n_divider=1;tx_pll_vco_post_scale_divider=1;tx_use_external_termination=false;" */;
defparam
pcie_hip_s4gx_gen2_x4_128_serdes_alt4gxb_svoa_component.starting_channel_number = starting_channel_number;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: IP_MODE STRING "PCIE_HIP_8"
// Retrieval info: PRIVATE: LOCKDOWN_EXCL STRING "PCIE"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "5000"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "5000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "5000"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 2-x4"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "5000 Mbps"
// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "AUTO"
// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100.0 MHz"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "2"
// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "GX"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PROTOCOL STRING "pcie2"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x4"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Auto"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "5000"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "4"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "AUTO"
// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x4"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "5000"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "off"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "3"
// Retrieval info: CONSTANT: coreclkout_control_width NUMERIC "1"
// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
// Retrieval info: CONSTANT: enable_0ppm STRING "false"
// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
// Retrieval info: CONSTANT: hip_enable STRING "true"
// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
// Retrieval info: CONSTANT: rateswitch_control_width NUMERIC "1"
// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "17"
// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "0"
// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1"
// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "1"
// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "3"
// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "0"
// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: hip_tx_clkout 0 0 4 0 OUTPUT NODEFVAL "hip_tx_clkout[3..0]"
// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 4 0 INPUT NODEFVAL "pipe8b10binvpolarity[3..0]"
// Retrieval info: USED_PORT: pipedatavalid 0 0 4 0 OUTPUT NODEFVAL "pipedatavalid[3..0]"
// Retrieval info: USED_PORT: pipeelecidle 0 0 4 0 OUTPUT NODEFVAL "pipeelecidle[3..0]"
// Retrieval info: USED_PORT: pipephydonestatus 0 0 4 0 OUTPUT NODEFVAL "pipephydonestatus[3..0]"
// Retrieval info: USED_PORT: pipestatus 0 0 12 0 OUTPUT NODEFVAL "pipestatus[11..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: pll_powerdown 0 0 1 0 INPUT NODEFVAL "pll_powerdown[0..0]"
// Retrieval info: USED_PORT: powerdn 0 0 8 0 INPUT NODEFVAL "powerdn[7..0]"
// Retrieval info: USED_PORT: rateswitch 0 0 1 0 INPUT NODEFVAL "rateswitch[0..0]"
// Retrieval info: USED_PORT: rateswitchbaseclock 0 0 1 0 OUTPUT NODEFVAL "rateswitchbaseclock[0..0]"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 OUTPUT NODEFVAL "reconfig_fromgxb[16..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_cruclk 0 0 4 0 INPUT GND "rx_cruclk[3..0]"
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 4 0 OUTPUT NODEFVAL "rx_ctrldetect[3..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 4 0 INPUT NODEFVAL "rx_datain[3..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 32 0 OUTPUT NODEFVAL "rx_dataout[31..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_elecidleinfersel 0 0 12 0 INPUT NODEFVAL "rx_elecidleinfersel[11..0]"
// Retrieval info: USED_PORT: rx_freqlocked 0 0 4 0 OUTPUT NODEFVAL "rx_freqlocked[3..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 4 0 OUTPUT NODEFVAL "rx_patterndetect[3..0]"
// Retrieval info: USED_PORT: rx_pll_locked 0 0 4 0 OUTPUT NODEFVAL "rx_pll_locked[3..0]"
// Retrieval info: USED_PORT: rx_signaldetect 0 0 4 0 OUTPUT NODEFVAL "rx_signaldetect[3..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 4 0 OUTPUT NODEFVAL "rx_syncstatus[3..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 4 0 INPUT NODEFVAL "tx_ctrlenable[3..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 32 0 INPUT NODEFVAL "tx_datain[31..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 4 0 OUTPUT NODEFVAL "tx_dataout[3..0]"
// Retrieval info: USED_PORT: tx_detectrxloop 0 0 4 0 INPUT NODEFVAL "tx_detectrxloop[3..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 4 0 INPUT NODEFVAL "tx_forcedispcompliance[3..0]"
// Retrieval info: USED_PORT: tx_forceelecidle 0 0 4 0 INPUT NODEFVAL "tx_forceelecidle[3..0]"
// Retrieval info: USED_PORT: tx_pipedeemph 0 0 4 0 INPUT NODEFVAL "tx_pipedeemph[3..0]"
// Retrieval info: USED_PORT: tx_pipemargin 0 0 12 0 INPUT NODEFVAL "tx_pipemargin[11..0]"
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 4 0 pipe8b10binvpolarity 0 0 4 0
// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
// Retrieval info: CONNECT: @pll_powerdown 0 0 1 0 pll_powerdown 0 0 1 0
// Retrieval info: CONNECT: @powerdn 0 0 8 0 powerdn 0 0 8 0
// Retrieval info: CONNECT: @rateswitch 0 0 1 0 rateswitch 0 0 1 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @rx_cruclk 0 0 4 0 rx_cruclk 0 0 4 0
// Retrieval info: CONNECT: @rx_datain 0 0 4 0 rx_datain 0 0 4 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @rx_elecidleinfersel 0 0 12 0 rx_elecidleinfersel 0 0 12 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 4 0 tx_ctrlenable 0 0 4 0
// Retrieval info: CONNECT: @tx_datain 0 0 32 0 tx_datain 0 0 32 0
// Retrieval info: CONNECT: @tx_detectrxloop 0 0 4 0 tx_detectrxloop 0 0 4 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 4 0 tx_forcedispcompliance 0 0 4 0
// Retrieval info: CONNECT: @tx_forceelecidle 0 0 4 0 tx_forceelecidle 0 0 4 0
// Retrieval info: CONNECT: @tx_pipedeemph 0 0 4 0 tx_pipedeemph 0 0 4 0
// Retrieval info: CONNECT: @tx_pipemargin 0 0 12 0 tx_pipemargin 0 0 12 0
// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
// Retrieval info: CONNECT: hip_tx_clkout 0 0 4 0 @hip_tx_clkout 0 0 4 0
// Retrieval info: CONNECT: pipedatavalid 0 0 4 0 @pipedatavalid 0 0 4 0
// Retrieval info: CONNECT: pipeelecidle 0 0 4 0 @pipeelecidle 0 0 4 0
// Retrieval info: CONNECT: pipephydonestatus 0 0 4 0 @pipephydonestatus 0 0 4 0
// Retrieval info: CONNECT: pipestatus 0 0 12 0 @pipestatus 0 0 12 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: rateswitchbaseclock 0 0 1 0 @rateswitchbaseclock 0 0 1 0
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 17 0 @reconfig_fromgxb 0 0 17 0
// Retrieval info: CONNECT: rx_ctrldetect 0 0 4 0 @rx_ctrldetect 0 0 4 0
// Retrieval info: CONNECT: rx_dataout 0 0 32 0 @rx_dataout 0 0 32 0
// Retrieval info: CONNECT: rx_freqlocked 0 0 4 0 @rx_freqlocked 0 0 4 0
// Retrieval info: CONNECT: rx_patterndetect 0 0 4 0 @rx_patterndetect 0 0 4 0
// Retrieval info: CONNECT: rx_pll_locked 0 0 4 0 @rx_pll_locked 0 0 4 0
// Retrieval info: CONNECT: rx_signaldetect 0 0 4 0 @rx_signaldetect 0 0 4 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 4 0 @rx_syncstatus 0 0 4 0
// Retrieval info: CONNECT: tx_dataout 0 0 4 0 @tx_dataout 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_hip_s4gx_gen2_x4_128_serdes.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_hip_s4gx_gen2_x4_128_serdes.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_hip_s4gx_gen2_x4_128_serdes.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_hip_s4gx_gen2_x4_128_serdes.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_hip_s4gx_gen2_x4_128_serdes.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_hip_s4gx_gen2_x4_128_serdes_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_hip_s4gx_gen2_x4_128_serdes_bb.v TRUE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_DIODE_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__FILL_DIODE_BEHAVIORAL_PP_V
/**
* fill_diode: Fill diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__fill_diode (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_DIODE_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__INV_16_V
`define SKY130_FD_SC_HD__INV_16_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__inv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__inv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__INV_16_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module daq3_spi (
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio,
spi_dir);
// 4 wire
input [ 2:0] spi_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_sdio;
output spi_dir;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_dir = ~spi_enable_s;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
IOBUF i_iobuf_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_miso),
.IO (spi_sdio));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_rgmii_module.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/MAC/mac/rgmii/altera_tse_rgmii_module.v,v $
//
// $Revision: #1 $
// $Date: 2014/02/16 $
// Check in by : $Author: swbranch $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description :
//
// Top level RGMII interface (receive and transmit) module.
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
module altera_tse_rgmii_module /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D103\"" */ ( // new ports to cater for mii with RGMII interface are added
// inputs
rgmii_in,
speed,
//data
gm_tx_d,
m_tx_d,
//control
gm_tx_en,
m_tx_en,
gm_tx_err,
m_tx_err,
reset_rx_clk,
reset_tx_clk,
rx_clk,
rx_control,
tx_clk,
// outputs:
rgmii_out,
gm_rx_d,
m_rx_d,
gm_rx_dv,
m_rx_en,
gm_rx_err,
m_rx_err,
m_rx_col,
m_rx_crs,
tx_control
);
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
output [ 3: 0] rgmii_out;
output [ 7: 0] gm_rx_d;
output [ 3: 0] m_rx_d;
output gm_rx_dv;
output m_rx_en;
output gm_rx_err;
output m_rx_err;
output m_rx_col;
output m_rx_crs;
output tx_control;
input [ 3: 0] rgmii_in;
input speed;
input [ 7: 0] gm_tx_d;
input [ 3: 0] m_tx_d;
input gm_tx_en;
input m_tx_en;
input gm_tx_err;
input m_tx_err;
input reset_rx_clk;
input reset_tx_clk;
input rx_clk;
input rx_control;
input tx_clk;
wire [ 3: 0] rgmii_out;
wire [ 7: 0] gm_rx_d;
wire gm_rx_dv;
wire m_rx_en;
wire gm_rx_err;
wire m_rx_err;
wire m_rx_col;
reg m_rx_col_reg;
reg m_rx_crs;
reg rx_dv;
reg rx_err;
wire tx_control;
//wire tx_err;
reg [ 7: 0] rgmii_out_4_wire;
reg rgmii_out_1_wire_inp1;
reg rgmii_out_1_wire_inp2;
wire [ 7:0 ] rgmii_in_4_wire;
reg [ 7:0 ] rgmii_in_4_reg;
reg [ 7:0 ] rgmii_in_4_temp_reg;
wire [ 1:0 ] rgmii_in_1_wire;
reg [ 1:0 ] rgmii_in_1_temp_reg;
wire speed_reg;
reg m_tx_en_reg1;
reg m_tx_en_reg2;
reg m_tx_en_reg3;
reg m_tx_en_reg4;
assign gm_rx_d = rgmii_in_4_reg;
assign m_rx_d = rgmii_in_4_reg[3:0]; // mii is only 4 bits, data are duplicated so we only take one nibble
altera_tse_rgmii_in4 the_rgmii_in4
(
.aclr (), //INPUT
.datain (rgmii_in), //INPUT
.dataout_h (rgmii_in_4_wire[7 : 4]), //OUTPUT
.dataout_l (rgmii_in_4_wire[3 : 0]), //OUTPUT
.inclock (rx_clk) //OUTPUT
);
altera_tse_rgmii_in1 the_rgmii_in1
(
.aclr (), //INPUT
.datain (rx_control), //INPUT
.dataout_h (rgmii_in_1_wire[1]), //INPUT rx_err
.dataout_l (rgmii_in_1_wire[0]), //OUTPUT rx_dv
.inclock (rx_clk) //OUTPUT
);
always @(posedge rx_clk or posedge reset_rx_clk)
begin
if (reset_rx_clk == 1'b1) begin
rgmii_in_4_temp_reg <= {8{1'b0}};
rgmii_in_1_temp_reg <= {2{1'b0}};
end
else begin
rgmii_in_4_temp_reg <= rgmii_in_4_wire;
rgmii_in_1_temp_reg <= rgmii_in_1_wire;
end
end
always @(posedge rx_clk or posedge reset_rx_clk)
begin
if (reset_rx_clk == 1'b1) begin
rgmii_in_4_reg <= {8{1'b0}};
rx_err <= 1'b0;
rx_dv <= 1'b0;
end
else begin
rgmii_in_4_reg <= {rgmii_in_4_wire[3:0], rgmii_in_4_temp_reg[7:4]};
rx_err <= rgmii_in_1_wire[0];
rx_dv <= rgmii_in_1_temp_reg[1];
end
end
always @(rx_dv or rx_err or rgmii_in_4_reg)
begin
m_rx_crs = 1'b0;
if ((rx_dv == 1'b1) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'hFF ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0E ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0F ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h1F ) )
begin
m_rx_crs = 1'b1; // read RGMII specification data sheet , table 4 for the conditions where CRS should go high
end
end
always @(posedge tx_clk or posedge reset_tx_clk)
begin
if(reset_tx_clk == 1'b1)
begin
m_tx_en_reg1 <= 1'b0;
m_tx_en_reg2 <= 1'b0;
m_tx_en_reg3 <= 1'b0;
m_tx_en_reg4 <= 1'b0;
end
else
begin
m_tx_en_reg1 <= m_tx_en;
m_tx_en_reg2 <= m_tx_en_reg1;
m_tx_en_reg3 <= m_tx_en_reg2;
m_tx_en_reg4 <= m_tx_en_reg3;
end
end
always @(m_tx_en_reg4 or m_rx_crs or rx_dv)
begin
m_rx_col_reg = 1'b0;
if ( m_tx_en_reg4 == 1'b1 & (m_rx_crs == 1'b1 | rx_dv == 1'b1))
begin
m_rx_col_reg = 1'b1;
end
end
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_1(
.clk(tx_clk), // INPUT
.reset_n(~reset_tx_clk), //INPUT
.din(m_rx_col_reg), //INPUT
.dout(m_rx_col));// OUTPUT
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_2(
.clk(tx_clk), // INPUT
.reset_n(~reset_tx_clk), //INPUT
.din(speed), //INPUT
.dout(speed_reg));// OUTPUT
assign gm_rx_err = rx_err ^ rx_dv;
assign gm_rx_dv = rx_dv;
assign m_rx_err = rx_err ^ rx_dv;
assign m_rx_en = rx_dv;
// mux for Out 4
always @(*)
begin
case (speed_reg)
1'b1: rgmii_out_4_wire = gm_tx_d;
1'b0: rgmii_out_4_wire = {m_tx_d,m_tx_d};
endcase
end
// mux for Out 1
always @(*)
begin
case (speed_reg)
1'b1:
begin
rgmii_out_1_wire_inp1 = gm_tx_en; // gigabit
rgmii_out_1_wire_inp2 = gm_tx_en ^ gm_tx_err;
end
1'b0:
begin
rgmii_out_1_wire_inp1 = m_tx_en;
rgmii_out_1_wire_inp2 = m_tx_en ^ m_tx_err;
end
endcase
end
altera_tse_rgmii_out4 the_rgmii_out4
(
.aclr (reset_tx_clk), //INPUT
.datain_h (rgmii_out_4_wire[3 : 0]), //INPUT
.datain_l (rgmii_out_4_wire[7 : 4]), //INPUT
.dataout (rgmii_out), //INPUT
.outclock (tx_clk) //OUTPUT
);
//assign tx_err = gm_tx_en ^ gm_tx_err;
altera_tse_rgmii_out1 the_rgmii_out1
(
.aclr (reset_tx_clk), //INPUT
.datain_h (rgmii_out_1_wire_inp1), //INPUT
.datain_l (rgmii_out_1_wire_inp2), //INPUT
.dataout (tx_control), //INPUT
.outclock (tx_clk) //OUTPUT
);
endmodule
|
module ultrasonido(input reset, input clk, input echo, output reg done, output reg trigger, output reg [15:0] distance);
//Período de la FPGA T=10nS (Código Alterno)
//Declaración de parámetros
//Estos parámetros se encuentran en nano segundos por el periodo de la FPGA
parameter divH = 1000;
parameter divL = 4000;
//Contadores
integer countF;
integer countEcho;
initial countF = 0;
//Trigger
always @(posedge clk) begin
if (reset)
begin
countF <= 0;
trigger <= 0;
end
else
begin
countF <= countF +1; //en caso de no funcionar probar con begin end en cada if
if (countF < divH+1)
trigger <= 1;
else
if (countF < divL+1)
trigger <= 0;
else
countF <= 0;
end
end
//echo
always @(posedge clk) begin
if (echo == 1) begin
countEcho <= countEcho +1;
done <= 0;
end
else
begin
if (echo == 0 & countEcho != 0)
distance <= (countEcho*340)/2000000;
//distance <= countEcho/58000;
countEcho <=0;
done <= 1;
end
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_1_V
`define SKY130_FD_SC_HVL__XOR2_1_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__xor2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__xor2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_1_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:52:26 09/08/2014
// Design Name: lab5dpath
// Module Name: C:/ece4743/projects/lab5_solution/tb_lab5dpath.v
// Project Name: lab5_solution
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: lab5dpath
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lab5dpath;
// Inputs
reg reset;
reg clk;
reg irdy;
reg [9:0] din;
// Outputs
wire ordy;
wire [9:0] dout;
// Instantiate the Unit Under Test (UUT)
lab5dpath uut (
.reset(reset),
.clk(clk),
.irdy(irdy),
.ordy(ordy),
.din(din),
.dout(dout)
);
reg[8*100:1] aline;
integer fd;
integer count,status;
integer i_a, i_b, i_c, i_result;
initial begin
clk = 0;
#100 //reset delay
forever #25 clk = ~clk;
end
initial begin
// Initialize Inputs
// Initialize Inputs
#1
reset = 1;
clk = 0;
irdy = 0;
din = 0;
count = 0;
fd = $fopen("multadd_vectors.txt","r");
// Wait 100 ns for global reset to finish
#100;
reset = 0;
@(negedge clk);
while ($fgets(aline,fd)) begin
status = $sscanf(aline,"%x %x %x %x",i_a, i_b, i_c, i_result);
count = count + 1;
din = i_a;
irdy = 1;
@(negedge clk);
irdy = 0;
din = i_b;
@(negedge clk);
din = i_c;
@(negedge clk);
@(negedge clk);
if (ordy != 1) begin
$display("FAIL: ORDY is not asserted\n");
end else begin
if (dout == i_result)
$display("%d PASS, a: %d, b: %d, c: %d, dout: %d\n",count,i_a,i_b,i_c,dout);
else
$display("%d FAIL, a: %d, b: %d, c: %d, y (actual): %d, dout (expected): %d\n",count,i_a,i_b,i_c,dout,i_result);
end
@(negedge clk);
//ensure output is still valid
if (ordy != 1) begin
$display("FAIL: ORDY is not asserted\n");
end else begin
if (dout == i_result)
$display("%d PASS, a: %d, b: %d, c: %d, dout: %d\n",count,i_a,i_b,i_c,dout);
else
$display("%d FAIL, a: %d, b: %d, c: %d, y (actual): %d, dout (expected): %d\n",count,i_a,i_b,i_c,dout,i_result);
end
@(negedge clk); //wait few clocks
if (ordy != 1) begin
$display("FAIL: ORDY is not asserted\n");
end else begin
if (dout == i_result)
$display("%d PASS, a: %d, b: %d, c: %d, dout: %d\n",count,i_a,i_b,i_c,dout);
else
$display("%d FAIL, a: %d, b: %d, c: %d, y (actual): %d, dout (expected): %d\n",count,i_a,i_b,i_c,dout,i_result);
end
end
end
endmodule
|
/*
* HIFIFO: Harmon Instruments PCI Express to FIFO
* Copyright (C) 2014 Harmon Instruments, LLC
* Author: Darrell Harmon
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*
* clock must be same as FPC FIFO and TPC FIFO
* reset is sync, active high
* fpc_ signals go to a from PC fifo
* tpc_ signals go to a to PC fifo
*
* User logic interface:
* wvalid: indicates valid write data is available on wdata and address
* rvalid: indicates a valid read request
* address: address for read and write. qualified by wvalid or rvalid
* wdata: write data. qualified by wvalid
* rdata: read data, present read data here RPIPE cycles after rvalid.
* status: inputs for wait condition instruction
*
* sequencer instructions:
* NOP: fpc_data[63:0] = 0
* WRITE: fpc_data[63:62] = 2
* fpc_data[ABITS-1:0] = address
* fpc_data[61] = increment
* fpc_data[47:32] = count
* fpc_data[31:0] = address
* READ:
* fpc_data[63:62] = 3
* fpc_data[61] = increment
* fpc_data[47:32] = count
* fpc_data[31:0] = address
* WAIT:
* fpc_data[63:62] = 1
* fpc_data[31:0] = timeout (clock cycles)
* fpc_data[39:32] = status bit
* fpc_data[41:40] = mode
* mode = 0: unconditional wait
* mode = 2: wait for status bit to be clear
* mode = 3: wait for status btt to be set
*/
module sequencer
(
input clock,
input reset,
// FPC FIFO
output fpc_read,
input fpc_valid,
input [63:0] fpc_data,
// TPC FIFO
input tpc_ready,
output tpc_write,
output [63:0] tpc_data,
// user logic interface
output reg rvalid = 0,
output reg wvalid = 0,
output reg [ABITS-1:0] address = 0,
output reg [DBITS-1:0] wdata = 0,
input [DBITS-1:0] rdata,
input [SBITS-1:0] status
);
parameter RPIPE = 2; // > 2
parameter ABITS = 16; // 1 to 32
parameter DBITS = 64; // 1 to 64
parameter SBITS = 16; // 1 to 64
parameter CBITS = 24; // 2 to 28
reg [CBITS-1:0] count = 32'hDEADBEEF;
reg [1:0] state = 0;
reg inc = 0;
wire rvalid_next = (state == 3) && tpc_ready;
wire wvalid_next = (state == 2) && fpc_read;
assign fpc_read = fpc_valid && ((state == 0) || (state == 2));
always @ (posedge clock)
begin
rvalid <= rvalid_next;
wvalid <= wvalid_next;
address <= (state == 0) ? fpc_data[ABITS-1:0] :
address + (inc && (rvalid || wvalid));
wdata <= fpc_data[DBITS-1:0];
inc <= (state == 0) ? fpc_data[61] : inc;
case(state)
0: count <= fpc_data[CBITS+31:32];
1: count <= count - 1'b1;
2: count <= count - wvalid_next;
3: count <= count - rvalid_next;
endcase
if(reset)
state <= 2'd0;
else
begin
case(state)
0: state <= fpc_read ? fpc_data[63:62] : 2'd0; // idle, nop
// wait, read, write
default: state <= (count[CBITS-1:1] == 0) ? 2'd0 : state;
endcase
end
end
// delay tpc_write RPIPE cycles from rvalid to allow for a read pipeline
delay_n #(.N(RPIPE)) delay_tpc_write
(.clock(clock), .in(rvalid), .out(tpc_write));
assign tpc_data = rdata;
endmodule
module delay_n
(
input clock,
input in,
output out
);
parameter N = 2;
reg [N-1:0] sreg = 0;
assign out = sreg[N-1];
always @ (posedge clock)
sreg <= {sreg[N-2:0],in};
endmodule
|
/*******************************************************
* File Name : hdl/ks26.v
* Module Name : Karatsuba Multiplier
* Author : Chester Rebeiro
* Institute : Indian Institute of Technology, Madras
* Creation Time :
* Comment : Automatically generated from ks.c
********************************************************/
//`include "ks13.v"
module Sks26(a, b, d);
input wire [25:0] a;
input wire [25:0] b;
output wire [50:0] d;
wire [24:0] m1;
wire [24:0] m2;
wire [24:0] m3;
wire [12:0] ahl;
wire [12:0] bhl;
Sks13 ksm1(a[12:0], b[12:0], m2);
Sks13 ksm2(a[25:13], b[25:13], m1);
assign ahl[12:0] = a[25:13] ^ a[12:0];
assign bhl[12:0] = b[25:13] ^ b[12:0];
Sks13 ksm3(ahl, bhl, m3);
assign d[00] = m2[00];
assign d[01] = m2[01];
assign d[02] = m2[02];
assign d[03] = m2[03];
assign d[04] = m2[04];
assign d[05] = m2[05];
assign d[06] = m2[06];
assign d[07] = m2[07];
assign d[08] = m2[08];
assign d[09] = m2[09];
assign d[10] = m2[10];
assign d[11] = m2[11];
assign d[12] = m2[12];
assign d[13] = m2[13] ^ m1[00] ^ m2[00] ^ m3[00];
assign d[14] = m2[14] ^ m1[01] ^ m2[01] ^ m3[01];
assign d[15] = m2[15] ^ m1[02] ^ m2[02] ^ m3[02];
assign d[16] = m2[16] ^ m1[03] ^ m2[03] ^ m3[03];
assign d[17] = m2[17] ^ m1[04] ^ m2[04] ^ m3[04];
assign d[18] = m2[18] ^ m1[05] ^ m2[05] ^ m3[05];
assign d[19] = m2[19] ^ m1[06] ^ m2[06] ^ m3[06];
assign d[20] = m2[20] ^ m1[07] ^ m2[07] ^ m3[07];
assign d[21] = m2[21] ^ m1[08] ^ m2[08] ^ m3[08];
assign d[22] = m2[22] ^ m1[09] ^ m2[09] ^ m3[09];
assign d[23] = m2[23] ^ m1[10] ^ m2[10] ^ m3[10];
assign d[24] = m2[24] ^ m1[11] ^ m2[11] ^ m3[11];
assign d[25] = m1[12] ^ m2[12] ^ m3[12];
assign d[26] = m1[13] ^ m2[13] ^ m3[13] ^ m1[00];
assign d[27] = m1[14] ^ m2[14] ^ m3[14] ^ m1[01];
assign d[28] = m1[15] ^ m2[15] ^ m3[15] ^ m1[02];
assign d[29] = m1[16] ^ m2[16] ^ m3[16] ^ m1[03];
assign d[30] = m1[17] ^ m2[17] ^ m3[17] ^ m1[04];
assign d[31] = m1[18] ^ m2[18] ^ m3[18] ^ m1[05];
assign d[32] = m1[19] ^ m2[19] ^ m3[19] ^ m1[06];
assign d[33] = m1[20] ^ m2[20] ^ m3[20] ^ m1[07];
assign d[34] = m1[21] ^ m2[21] ^ m3[21] ^ m1[08];
assign d[35] = m1[22] ^ m2[22] ^ m3[22] ^ m1[09];
assign d[36] = m1[23] ^ m2[23] ^ m3[23] ^ m1[10];
assign d[37] = m1[24] ^ m2[24] ^ m3[24] ^ m1[11];
assign d[38] = m1[12];
assign d[39] = m1[13];
assign d[40] = m1[14];
assign d[41] = m1[15];
assign d[42] = m1[16];
assign d[43] = m1[17];
assign d[44] = m1[18];
assign d[45] = m1[19];
assign d[46] = m1[20];
assign d[47] = m1[21];
assign d[48] = m1[22];
assign d[49] = m1[23];
assign d[50] = m1[24];
endmodule
|
/***********************************************************************
Logic Analyzer 1 (base module)
This file is part FPGA Libre project http://fpgalibre.sf.net/
Description:
Implements an internal logic analyzer of 8/16/32 channels using
the FT245 sync FIFO core.
Implements 1 stage trigger and supports independent clock.
This module is the logic analyzer itself (without support logic)
To Do:
-
Author:
- Salvador E. Tropea, salvador en inti.gob.ar
------------------------------------------------------------------------------
Copyright (c) 2017 Salvador E. Tropea <salvador en inti.gob.ar>
Copyright (c) 2017 Instituto Nacional de Tecnología Industrial
Distributed under the GPL v2 or newer license
------------------------------------------------------------------------------
Design unit: LA_1_Base(RTL) (Entity and architecture)
File name: la_1_base.v
Note: None
Limitations: None known
Errors: None known
Library: avr
Dependencies: IEEE.std_logic_1164
IEEE.numeric_std
utils.stdlib
mems.devices
Target FPGA: iCE40HX4K-TQ144
Language: Verilog
Wishbone: None
Synthesis tools: Lattice iCECube2 2017.01.27914
Simulation tools: GHDL [Sokcho edition] (0.2x)
Text editor: SETEdit 0.5.x
***********************************************************************/
reg start_r;
reg start_acq_r=0;
reg was_full;
wire next_data;
wire tx_wr;
wire [N_CH-1:0] acq_data;
reg [N_CH-1:0] acq_data_r;
// Triggers
reg [N_CH-1:0] trg_mask=0;
reg [N_CH-1:0] trg_value=0;
reg [N_CH-1:0] trg_edge=0;
wire [N_CH-1:0] acq_edge;
wire trigger;
reg [1:0] cnt_rx=2'b0;
reg [N_TX-1:0] cnt_tx=0;
wire [1:0] cnt_tx_sel;
reg [7:0] cnt_cdiv=7'b0;
// Config
reg cfg_src_r=1'b0; // Read from the config registers
wire [N_CH-1:0] cfg_data; // Data for the host
assign tx_data_o=cfg_src_r ? cfg_data : acq_data_r;
assign acq_data=chn_i;
generate
if (N_CH==8)
begin : cfg_8
assign cnt_tx_sel=cnt_tx[1:0];
assign cfg_data=cnt_tx_sel==2'd0 ? 8'h08 : ( // 8 channels
cnt_tx_sel==2'd1 ? N_FIFO[7:0] : ( // FIFO size
cnt_tx_sel==2'd2 ? CLK_DIV[7:0] : (// Clock divider
F_CLK[7:0]))); // Clock
end // cfg_8
else if (N_CH==16)
begin : cfg_16
assign cfg_data=cnt_tx[0]==1'b0 ? {N_FIFO[7:0], 8'h10} : // 16 channels/FIFO size
{F_CLK[7:0], CLK_DIV[7:0]}; // Clock divider/Clock
end // cfg_16
else if (N_CH==32)
begin : cfg_32
assign cfg_data={F_CLK[7:0], CLK_DIV[7:0], N_FIFO[7:0], 8'h20};
end // cfg_32
endgenerate
assign tx_wr=!tx_full_i && (start_acq_r || (start_r && trigger)) && cnt_cdiv==0;
assign tx_wr_o=tx_wr;
assign next_data=!tx_full_i && start_r && cnt_cdiv==0 && !cfg_src_r;
assign wr_o=next_data;
always @(posedge clk_i)
begin : do_clk_div
if (rst_i || (rx_rd_i && rx_data_i[0]))
cnt_cdiv <= 0;
else
begin
cnt_cdiv <= cnt_cdiv+1;
if (cnt_cdiv==CLK_DIV-1)
cnt_cdiv <= 0;
end
end // do_clk_div
always @(posedge clk_i)
begin : do_regs
if (rst_i)
begin
start_r <= 1'b0;
start_acq_r <= 1'b0;
cfg_src_r <= 1'b0;
was_full <= 1'b0;
cnt_tx <= {N_TX{1'b0}};
cnt_rx <= 2'b0;
trg_mask <= 8'b0;
trg_value <= 8'b0;
trg_edge <= 8'b0;
end
else
begin
if (tx_ft_full_i && start_r)
was_full <= 1'b1;
// Start writing
if (start_r && (trigger || cfg_src_r))
start_acq_r <= 1'b1;
// Stop after filling the FIFO once
if (tx_wr)
begin
cnt_tx <= cnt_tx+1;
if (cnt_tx==C_TX-1 ||
(cfg_src_r && cnt_tx[1:0]==2'b11 && N_CH==8) ||
(cfg_src_r && cnt_tx[0:0]==1'b1 && N_CH==16) ||
(cfg_src_r && N_CH==32))
begin
start_r <= 1'b0;
start_acq_r <= 1'b0;
end
end
// Registers
if (rx_rd_i)
begin
cnt_rx <= cnt_rx+1;
case (cnt_rx)
2'd0: trg_mask <= rx_data_i;
2'd1: trg_value <= rx_data_i;
2'd2: trg_edge <= rx_data_i;
2'd3:
begin
start_r <= rx_data_i[0];
cfg_src_r <= rx_data_i[1];
if (!start_r && rx_data_i[0])
begin
was_full <= 1'b0;
cnt_tx <= {N_TX{1'b0}};
// If we don't have a trigger start acq right now
if (trg_mask==8'b0)
start_acq_r <= 1'b1;
end
if (!rx_data_i[0])
start_acq_r <= 1'b0;
end
endcase
end
if (!rx_rd_i)
// Ensure we go back to 0 after a burst
cnt_rx <= 2'b0;
end
end // do_regs
////////////////////////////////
// 4 bits debug output (LEDs) //
////////////////////////////////
//assign dbg_o={1'b0,status_empty,was_full,start_r};
//assign dbg_o={2'b0,cnt_rx};
//assign dbg_o={ft_full,1'b0,cnt_rx2};
//assign dbg_o=dbg_fifo;
//assign dbg_o=trg_edge[3:0];
//assign dbg_o=trg_mask[3:0];
//assign dbg_o=trg_value[3:0];
assign dbg_o=4'b0;
///////////////////
// Trigger logic //
///////////////////
always @(posedge clk_i)
begin : do_acq_data_r
if (next_data)
acq_data_r <= acq_data;
end // do_acq_data_r
assign acq_edge=(acq_data_r ^ acq_data) &&
trg_edge; // Ignore edges on level triggers
assign trigger=trg_mask==8'b0 || // No mask, always triggered
((trg_value ~^ acq_data_r) & // Compare the data with the trigger value
(trg_edge ~^ acq_edge) & // Compare the data edge with the trigger edge
trg_mask)==trg_mask; // Apply the trigger mask
|
/*
* vgagraph_ctrl.v: ライン方向の fill address の制御
*/
module vgagraph_ctrl (
input CLK,
input load,
input fifofull,
input dispon,
input initiate,
input arready,
output hstart,
output done
);
`include "vgaparam.vh"
localparam dots = 640 * 480 / (2 * 16);
reg hstart_ff1 = 1'b0;
reg hstart_ff2 = 1'b0;
reg [8:0] cnt5 = 9'd0;
reg [22:0] cnt22 = 23'd0;
reg done_ff = 1'b0;
reg hvalid_ff = 1'b0;
reg vvalid_ff = 1'd0;
assign hstart = hstart_ff1 & (~hstart_ff2);
assign done = done_ff;
// バースト期間中アクティブになる信号
always @(posedge CLK) begin
if (initiate)
vvalid_ff <= 1'b1;
else if (arready && (cnt22 == dots - 1))
vvalid_ff <= 1'b0;
else
vvalid_ff <= vvalid_ff;
end
always @(posedge CLK) begin
if (load)
hvalid_ff <= 1'b1;
else if (initiate || cnt5 > 19 || ~vvalid_ff)
hvalid_ff <= 1'b0;
else
hvalid_ff <= hvalid_ff;
end
// iVCNT 有効かつ iHCNT == 0 の時、hstart = 1
always @(posedge CLK) begin
if (~hvalid_ff) begin
hstart_ff2 <= 1'b0;
hstart_ff1 <= 1'b0;
end
else if (fifofull) begin
hstart_ff2 <= hstart_ff2;
hstart_ff1 <= hstart_ff1;
end
else if (hvalid_ff && ~arready) begin
hstart_ff2 <= hstart_ff1;
hstart_ff1 <= dispon;
end
else begin
hstart_ff2 <= hstart_ff1;
hstart_ff1 <= 1'b0;
end
end
// ラインカウンタ(in burst block count)
always @(posedge CLK) begin
if (initiate)
cnt5 <= 5'd0;
else if (load && cnt5 > 19) begin
if (arready)
cnt5 <= 5'd1;
else
cnt5 <= 5'd0;
end
else if (hstart)
cnt5 <= cnt5 + 5'd1;
else
cnt5 <= cnt5;
end
// done: hstart でカウント開始、640 * 480 / 32 回カウントしたら1CLKだけアサートする
always @(posedge CLK) begin
if (initiate) begin
done_ff <= 1'b0;
cnt22 <= 23'd0;
end
else if (hstart) begin
if (cnt22 == dots - 1) begin
done_ff <= 1'b1;
cnt22 <= cnt22 + 23'd1;
end
else begin
done_ff <= 1'b0;
cnt22 <= cnt22 + 23'd1;
end
end
else begin
done_ff <= 1'b0;
cnt22 <= cnt22;
end
end
endmodule
|
`timescale 1ns/1ps
`include "cpu_constants.vh"
module dma_controller_tb;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire dma_status; // From dma of dma_controller.v
wire [23:0] dram_addr; // From dma of dma_controller.v
wire [31:0] dram_data_out; // From dma of dma_controller.v
wire dram_req_read; // From dma of dma_controller.v
wire dram_req_write; // From dma of dma_controller.v
wire [15:0] ram_addr; // From dma of dma_controller.v
wire [15:0] ram_data_out; // From dma of dma_controller.v
wire ram_we; // From dma of dma_controller.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg [15:0] addr; // To dma of dma_controller.v
reg clk; // To dma of dma_controller.v
reg [15:0] data_in; // To dma of dma_controller.v
reg [31:0] dram_data_in; // To dma of dma_controller.v
reg dram_data_valid; // To dma of dma_controller.v
reg dram_write_complete; // To dma of dma_controller.v
reg en; // To dma of dma_controller.v
reg [15:0] ram_data_in; // To dma of dma_controller.v
reg rst; // To dma of dma_controller.v
reg write_enable; // To dma of dma_controller.v
// End of automatics
dma_controller dma(/*AUTOINST*/
// Outputs
.dma_status (dma_status),
.ram_addr (ram_addr[15:0]),
.ram_data_out (ram_data_out[15:0]),
.ram_we (ram_we),
.dram_addr (dram_addr[23:0]),
.dram_data_out (dram_data_out[31:0]),
.dram_req_read (dram_req_read),
.dram_req_write (dram_req_write),
// Inputs
.clk (clk),
.rst (rst),
.en (en),
.addr (addr[15:0]),
.data_in (data_in[15:0]),
.write_enable (write_enable),
.ram_data_in (ram_data_in[15:0]),
.dram_data_in (dram_data_in[31:0]),
.dram_data_valid (dram_data_valid),
.dram_write_complete(dram_write_complete));
initial begin
clk = 0;
rst = 1;
en = 1;
addr = 0;
data_in = 0;
write_enable = 0;
ram_data_in = 16'habcd;
dram_data_in = 0;
dram_data_valid = 0;
dram_write_complete = 0;
end
always #5 clk <= ~clk;
initial begin
#20 rst <= 0;
addr = `DMA_COUNT_ADDR >> 1;
data_in = 16;
write_enable = 1;
@(posedge clk)
addr = `DMA_PERIPH_ADDR >> 1;
data_in = 16'hf00d;
@(posedge clk)
addr = `DMA_LOCAL_ADDR >> 1;
data_in = 16'hbeef;
@(posedge clk)
addr = `DMA_CONTROL_ADDR >> 1;
data_in = 0;
@(posedge clk)
write_enable = 0;
//test read
@(negedge dma_status)
#20
addr = `DMA_COUNT_ADDR >> 1;
data_in = 16;
write_enable = 1;
@(posedge clk);
addr = `DMA_PERIPH_ADDR >> 1;
data_in = 16'h00c0;
@(posedge clk)
addr = `DMA_LOCAL_ADDR >> 1;
data_in = 16'hfe00;
@(posedge clk);
addr = `DMA_CONTROL_ADDR >> 1;
data_in = 1;
@(posedge clk)
write_enable = 0;
end
reg busy = 0;
always @(posedge clk) begin
if(dram_req_write && !busy) begin
#30 dram_write_complete = 1;
busy <= 1;
end
if(dram_write_complete && busy) begin
dram_write_complete <= 0;
busy <= 0;
end
if(dram_req_read && !busy) begin
#80 dram_data_valid = 1;
busy <= 1;
end
if(dram_data_valid && busy) begin
dram_data_valid <= 0;
busy <= 0;
end
end
endmodule
|
module scaler_1d # (
parameter integer C_S_WIDTH = 12,
parameter integer C_M_WIDTH = 12,
parameter integer C_S_BMP = 4 ,
parameter integer C_S_BID = 2 ,
parameter integer C_S_IDX = 0 , /// C_S_WIDTH or 0
parameter integer C_SPLIT_ID_WIDTH = 2
) (
input wire clk,
input wire resetn,
input [C_S_WIDTH-1:0] s_nbr,
input [C_M_WIDTH-1:0] m_nbr,
output wire o_valid ,
input wire i_ready ,
output wire o_s_advance ,
output wire o_s_last ,
output wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] o_s_bmp_bid_idx0,
output wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] o_s_bmp_bid_idx1,
output wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] o_s_bmp_bid_idx2,
output wire o_m_advance ,
output wire o_m_first ,
output wire o_m_last ,
output wire o_a_last ,
output wire o_d_valid ,
output wire [C_SPLIT_ID_WIDTH : 0] o_split_id
);
///////////////////////////// row ////////////////////////////////////////////
wire sd_algo_enable ;
wire sd_core2split_o_valid ;
wire sd_core2split_s_advance ;
wire sd_core2split_s_last ;
wire [C_S_WIDTH + C_M_WIDTH : 0] sd_core2split_s_c ;
wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] sd_core2split_s_bmp_bid_idx0;
wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] sd_core2split_s_bmp_bid_idx1;
wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] sd_core2split_s_bmp_bid_idx2;
wire sd_core2split_m_advance ;
wire sd_core2split_m_first ;
wire sd_core2split_m_last ;
wire [C_S_WIDTH + C_M_WIDTH : 0] sd_core2split_m_c ;
wire sd_core2split_a_last ;
wire sd_core2split_d_valid ;
scaler_core # (
.C_S_WIDTH (C_S_WIDTH),
.C_M_WIDTH (C_M_WIDTH),
.C_S_BMP (C_S_BMP ),
.C_S_BID (C_S_BID ),
.C_S_IDX (C_S_IDX )
) sd_core (
.clk (clk ),
.resetn (resetn),
.s_nbr (s_nbr),
.m_nbr (m_nbr),
.enable (sd_algo_enable ),
.o_valid (sd_core2split_o_valid ),
.s_advance (sd_core2split_s_advance ),
.s_last (sd_core2split_s_last ),
.s_c (sd_core2split_s_c ),
.s_bmp_bid_idx0(sd_core2split_s_bmp_bid_idx0),
.s_bmp_bid_idx1(sd_core2split_s_bmp_bid_idx1),
.s_bmp_bid_idx2(sd_core2split_s_bmp_bid_idx2),
.m_advance (sd_core2split_m_advance ),
.m_first (sd_core2split_m_first ),
.m_last (sd_core2split_m_last ),
.m_c (sd_core2split_m_c ),
.a_last (sd_core2split_a_last ),
.d_valid (sd_core2split_d_valid )
);
wire sd_split2relay_valid ;
wire sd_split2relay_s_advance ;
wire sd_split2relay_s_last ;
wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] sd_split2relay_s_bmp_bid_idx0;
wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] sd_split2relay_s_bmp_bid_idx1;
wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] sd_split2relay_s_bmp_bid_idx2;
wire sd_split2relay_m_advance ;
wire sd_split2relay_m_first ;
wire sd_split2relay_m_last ;
wire sd_split2relay_a_last ;
wire sd_split2relay_d_valid ;
wire [C_SPLIT_ID_WIDTH : 0] sd_split2relay_split_id ;
scaler_spliter # (
.C_S_WIDTH (C_S_WIDTH ),
.C_M_WIDTH (C_M_WIDTH ),
.C_S_BMP (C_S_BMP ),
.C_S_BID (C_S_BID ),
.C_S_IDX (C_S_IDX ),
.C_SPLIT_ID_WIDTH (C_SPLIT_ID_WIDTH)
) sd_spliter (
.clk (clk ),
.resetn (resetn),
///.s_nbr (s_nbr),
.m_nbr (m_nbr),
.enable (sd_algo_enable ),
.i_valid (sd_core2split_o_valid ),
.i_s_advance (sd_core2split_s_advance ),
.i_s_last (sd_core2split_s_last ),
.i_s_c (sd_core2split_s_c ),
.i_s_bmp_bid_idx0(sd_core2split_s_bmp_bid_idx0 ),
.i_s_bmp_bid_idx1(sd_core2split_s_bmp_bid_idx1 ),
.i_s_bmp_bid_idx2(sd_core2split_s_bmp_bid_idx2 ),
.i_m_advance (sd_core2split_m_advance ),
.i_m_first (sd_core2split_m_first ),
.i_m_last (sd_core2split_m_last ),
.i_m_c (sd_core2split_m_c ),
.i_a_last (sd_core2split_a_last ),
.i_d_valid (sd_core2split_d_valid ),
.o_valid (sd_split2relay_valid ),
.o_s_advance (sd_split2relay_s_advance ),
.o_s_last (sd_split2relay_s_last ),
.o_s_bmp_bid_idx0(sd_split2relay_s_bmp_bid_idx0),
.o_s_bmp_bid_idx1(sd_split2relay_s_bmp_bid_idx1),
.o_s_bmp_bid_idx2(sd_split2relay_s_bmp_bid_idx2),
.o_m_advance (sd_split2relay_m_advance ),
.o_m_first (sd_split2relay_m_first ),
.o_m_last (sd_split2relay_m_last ),
.o_a_last (sd_split2relay_a_last ),
.o_d_valid (sd_split2relay_d_valid ),
.o_split_id (sd_split2relay_split_id )
);
localparam integer C_DATA_WIDTH = (7
+ (C_S_BMP + C_S_BID + C_S_IDX) * 3
+ (C_SPLIT_ID_WIDTH + 1));
scaler_relay # (
.C_DATA_WIDTH(C_DATA_WIDTH)
) relay (
.clk (clk ),
.resetn (resetn),
.s_valid(sd_split2relay_valid),
.s_data ({
sd_split2relay_s_advance ,
sd_split2relay_s_last ,
sd_split2relay_s_bmp_bid_idx0,
sd_split2relay_s_bmp_bid_idx1,
sd_split2relay_s_bmp_bid_idx2,
sd_split2relay_m_advance ,
sd_split2relay_m_first ,
sd_split2relay_m_last ,
sd_split2relay_a_last ,
sd_split2relay_d_valid ,
sd_split2relay_split_id
}),
.s_ready(sd_algo_enable),
.m_valid(o_valid),
.m_data ({
o_s_advance ,
o_s_last ,
o_s_bmp_bid_idx0,
o_s_bmp_bid_idx1,
o_s_bmp_bid_idx2,
o_m_advance ,
o_m_first ,
o_m_last ,
o_a_last ,
o_d_valid ,
o_split_id
}),
.m_ready(i_ready)
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
`define AUTOTB_DUT hls_macc
`define AUTOTB_DUT_INST AESL_inst_hls_macc
`define AUTOTB_TOP apatb_hls_macc_top
`define AUTOTB_LAT_RESULT_FILE "hls_macc.result.lat.rb"
`define AUTOTB_PER_RESULT_TRANS_FILE "hls_macc.performance.result.transaction.xml"
`define AUTOTB_TOP_INST AESL_inst_apatb_hls_macc_top
`define AUTOTB_MAX_ALLOW_LATENCY 15000000
`define AUTOTB_CLOCK_PERIOD_DIV2 2.00
`define AESL_DEPTH_a 1
`define AESL_DEPTH_b 1
`define AESL_DEPTH_accum 1
`define AESL_DEPTH_accum_clr 1
`define AUTOTB_TVIN_a "./c.hls_macc.autotvin_a.dat"
`define AUTOTB_TVIN_b "./c.hls_macc.autotvin_b.dat"
`define AUTOTB_TVIN_accum_clr "./c.hls_macc.autotvin_accum_clr.dat"
`define AUTOTB_TVIN_a_out_wrapc "./rtl.hls_macc.autotvin_a.dat"
`define AUTOTB_TVIN_b_out_wrapc "./rtl.hls_macc.autotvin_b.dat"
`define AUTOTB_TVIN_accum_clr_out_wrapc "./rtl.hls_macc.autotvin_accum_clr.dat"
`define AUTOTB_TVOUT_accum "./c.hls_macc.autotvout_accum.dat"
`define AUTOTB_TVOUT_accum_out_wrapc "./impl_rtl.hls_macc.autotvout_accum.dat"
module `AUTOTB_TOP;
parameter AUTOTB_TRANSACTION_NUM = 4383;
parameter PROGRESS_TIMEOUT = 10000000;
parameter LATENCY_ESTIMATION = 8;
parameter LENGTH_a = 1;
parameter LENGTH_b = 1;
parameter LENGTH_accum = 1;
parameter LENGTH_accum_clr = 1;
task read_token;
input integer fp;
output reg [287 : 0] token;
integer ret;
begin
token = "";
ret = 0;
ret = $fscanf(fp,"%s",token);
end
endtask
task post_check;
input integer fp1;
input integer fp2;
reg [287 : 0] token1;
reg [287 : 0] token2;
reg [287 : 0] golden;
reg [287 : 0] result;
integer ret;
begin
read_token(fp1, token1);
read_token(fp2, token2);
if (token1 != "[[[runtime]]]" || token2 != "[[[runtime]]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp1, token1);
read_token(fp2, token2);
while (token1 != "[[[/runtime]]]" && token2 != "[[[/runtime]]]") begin
if (token1 != "[[transaction]]" || token2 != "[[transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp1, token1); // skip transaction number
read_token(fp2, token2); // skip transaction number
read_token(fp1, token1);
read_token(fp2, token2);
while(token1 != "[[/transaction]]" && token2 != "[[/transaction]]") begin
ret = $sscanf(token1, "0x%x", golden);
if (ret != 1) begin
$display("Failed to parse token!");
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
ret = $sscanf(token2, "0x%x", result);
if (ret != 1) begin
$display("Failed to parse token!");
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
if(golden != result) begin
$display("%x (expected) vs. %x (actual) - mismatch", golden, result);
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp1, token1);
read_token(fp2, token2);
end
read_token(fp1, token1);
read_token(fp2, token2);
end
end
endtask
reg AESL_clock;
reg rst;
reg start;
reg ce;
reg tb_continue;
wire AESL_start;
wire AESL_reset;
wire AESL_ce;
wire AESL_ready;
wire AESL_idle;
wire AESL_continue;
wire AESL_done;
reg AESL_done_delay = 0;
reg AESL_done_delay2 = 0;
reg AESL_ready_delay = 0;
wire ready;
wire ready_wire;
wire [5 : 0] HLS_MACC_PERIPH_BUS_AWADDR;
wire HLS_MACC_PERIPH_BUS_AWVALID;
wire HLS_MACC_PERIPH_BUS_AWREADY;
wire HLS_MACC_PERIPH_BUS_WVALID;
wire HLS_MACC_PERIPH_BUS_WREADY;
wire [31 : 0] HLS_MACC_PERIPH_BUS_WDATA;
wire [3 : 0] HLS_MACC_PERIPH_BUS_WSTRB;
wire [5 : 0] HLS_MACC_PERIPH_BUS_ARADDR;
wire HLS_MACC_PERIPH_BUS_ARVALID;
wire HLS_MACC_PERIPH_BUS_ARREADY;
wire HLS_MACC_PERIPH_BUS_RVALID;
wire HLS_MACC_PERIPH_BUS_RREADY;
wire [31 : 0] HLS_MACC_PERIPH_BUS_RDATA;
wire [1 : 0] HLS_MACC_PERIPH_BUS_RRESP;
wire HLS_MACC_PERIPH_BUS_BVALID;
wire HLS_MACC_PERIPH_BUS_BREADY;
wire [1 : 0] HLS_MACC_PERIPH_BUS_BRESP;
wire HLS_MACC_PERIPH_BUS_INTERRUPT;
integer done_cnt = 0;
integer AESL_ready_cnt = 0;
integer ready_cnt = 0;
reg ready_initial;
reg ready_initial_n;
reg ready_last_n;
reg ready_delay_last_n;
reg done_delay_last_n;
reg interface_done = 0;
wire HLS_MACC_PERIPH_BUS_read_data_finish;
wire HLS_MACC_PERIPH_BUS_write_data_finish;
wire AESL_slave_start;
reg AESL_slave_start_lock = 0;
wire AESL_slave_write_start_in;
wire AESL_slave_write_start_finish;
reg AESL_slave_ready;
wire AESL_slave_output_done;
wire AESL_slave_done;
reg ready_rise = 0;
reg start_rise = 0;
reg slave_start_status = 0;
reg slave_done_status = 0;
reg ap_done_lock = 0;
wire ap_clk;
wire ap_rst_n;
wire ap_rst_n_n;
`AUTOTB_DUT `AUTOTB_DUT_INST(
.s_axi_HLS_MACC_PERIPH_BUS_AWADDR(HLS_MACC_PERIPH_BUS_AWADDR),
.s_axi_HLS_MACC_PERIPH_BUS_AWVALID(HLS_MACC_PERIPH_BUS_AWVALID),
.s_axi_HLS_MACC_PERIPH_BUS_AWREADY(HLS_MACC_PERIPH_BUS_AWREADY),
.s_axi_HLS_MACC_PERIPH_BUS_WVALID(HLS_MACC_PERIPH_BUS_WVALID),
.s_axi_HLS_MACC_PERIPH_BUS_WREADY(HLS_MACC_PERIPH_BUS_WREADY),
.s_axi_HLS_MACC_PERIPH_BUS_WDATA(HLS_MACC_PERIPH_BUS_WDATA),
.s_axi_HLS_MACC_PERIPH_BUS_WSTRB(HLS_MACC_PERIPH_BUS_WSTRB),
.s_axi_HLS_MACC_PERIPH_BUS_ARADDR(HLS_MACC_PERIPH_BUS_ARADDR),
.s_axi_HLS_MACC_PERIPH_BUS_ARVALID(HLS_MACC_PERIPH_BUS_ARVALID),
.s_axi_HLS_MACC_PERIPH_BUS_ARREADY(HLS_MACC_PERIPH_BUS_ARREADY),
.s_axi_HLS_MACC_PERIPH_BUS_RVALID(HLS_MACC_PERIPH_BUS_RVALID),
.s_axi_HLS_MACC_PERIPH_BUS_RREADY(HLS_MACC_PERIPH_BUS_RREADY),
.s_axi_HLS_MACC_PERIPH_BUS_RDATA(HLS_MACC_PERIPH_BUS_RDATA),
.s_axi_HLS_MACC_PERIPH_BUS_RRESP(HLS_MACC_PERIPH_BUS_RRESP),
.s_axi_HLS_MACC_PERIPH_BUS_BVALID(HLS_MACC_PERIPH_BUS_BVALID),
.s_axi_HLS_MACC_PERIPH_BUS_BREADY(HLS_MACC_PERIPH_BUS_BREADY),
.s_axi_HLS_MACC_PERIPH_BUS_BRESP(HLS_MACC_PERIPH_BUS_BRESP),
.interrupt(HLS_MACC_PERIPH_BUS_INTERRUPT),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n));
// Assignment for control signal
assign ap_clk = AESL_clock;
assign ap_rst_n = AESL_reset;
assign ap_rst_n_n = ~AESL_reset;
assign AESL_reset = rst;
assign AESL_start = start;
assign AESL_ce = ce;
assign AESL_continue = tb_continue;
assign AESL_slave_write_start_in = slave_start_status & HLS_MACC_PERIPH_BUS_write_data_finish;
assign AESL_slave_start = AESL_slave_write_start_finish;
assign AESL_done = slave_done_status & HLS_MACC_PERIPH_BUS_read_data_finish;
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
begin
slave_start_status <= 1;
end
else begin
if (AESL_start == 1 ) begin
start_rise = 1;
end
if (start_rise == 1 && AESL_done == 1 ) begin
slave_start_status <= 1;
end
if (AESL_slave_write_start_in == 1 && AESL_done == 0) begin
slave_start_status <= 0;
start_rise = 0;
end
end
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
begin
AESL_slave_ready <= 0;
ready_rise = 0;
end
else begin
if (AESL_ready == 1 ) begin
ready_rise = 1;
end
if (ready_rise == 1 && AESL_done_delay == 1 ) begin
AESL_slave_ready <= 1;
end
if (AESL_slave_ready == 1) begin
AESL_slave_ready <= 0;
ready_rise = 0;
end
end
end
always @ (posedge AESL_clock)
begin
if (AESL_done == 1) begin
slave_done_status <= 0;
end
else if (AESL_slave_output_done == 1 ) begin
slave_done_status <= 1;
end
end
AESL_axi_slave_HLS_MACC_PERIPH_BUS AESL_AXI_SLAVE_HLS_MACC_PERIPH_BUS(
.clk (AESL_clock),
.reset (AESL_reset),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_AWADDR (HLS_MACC_PERIPH_BUS_AWADDR),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_AWVALID (HLS_MACC_PERIPH_BUS_AWVALID),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_AWREADY (HLS_MACC_PERIPH_BUS_AWREADY),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_WVALID (HLS_MACC_PERIPH_BUS_WVALID),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_WREADY (HLS_MACC_PERIPH_BUS_WREADY),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_WDATA (HLS_MACC_PERIPH_BUS_WDATA),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_WSTRB (HLS_MACC_PERIPH_BUS_WSTRB),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_ARADDR (HLS_MACC_PERIPH_BUS_ARADDR),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_ARVALID (HLS_MACC_PERIPH_BUS_ARVALID),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_ARREADY (HLS_MACC_PERIPH_BUS_ARREADY),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_RVALID (HLS_MACC_PERIPH_BUS_RVALID),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_RREADY (HLS_MACC_PERIPH_BUS_RREADY),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_RDATA (HLS_MACC_PERIPH_BUS_RDATA),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_RRESP (HLS_MACC_PERIPH_BUS_RRESP),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_BVALID (HLS_MACC_PERIPH_BUS_BVALID),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_BREADY (HLS_MACC_PERIPH_BUS_BREADY),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_BRESP (HLS_MACC_PERIPH_BUS_BRESP),
.TRAN_HLS_MACC_PERIPH_BUS_interrupt (HLS_MACC_PERIPH_BUS_INTERRUPT),
.TRAN_HLS_MACC_PERIPH_BUS_read_data_finish(HLS_MACC_PERIPH_BUS_read_data_finish),
.TRAN_HLS_MACC_PERIPH_BUS_write_data_finish(HLS_MACC_PERIPH_BUS_write_data_finish),
.TRAN_HLS_MACC_PERIPH_BUS_ready_out (AESL_ready),
.TRAN_HLS_MACC_PERIPH_BUS_ready_in (AESL_slave_ready),
.TRAN_HLS_MACC_PERIPH_BUS_done_out (AESL_slave_output_done),
.TRAN_HLS_MACC_PERIPH_BUS_idle_out (AESL_idle),
.TRAN_HLS_MACC_PERIPH_BUS_write_start_in (AESL_slave_write_start_in),
.TRAN_HLS_MACC_PERIPH_BUS_write_start_finish (AESL_slave_write_start_finish),
.TRAN_HLS_MACC_PERIPH_BUS_transaction_done_in (AESL_done_delay),
.TRAN_HLS_MACC_PERIPH_BUS_start_in (AESL_slave_start)
);
initial begin : generate_AESL_ready_cnt_proc
AESL_ready_cnt = 0;
wait(AESL_reset === 1);
while(AESL_ready_cnt != AUTOTB_TRANSACTION_NUM) begin
while(AESL_ready !== 1) begin
@(posedge AESL_clock);
# 0.4;
end
@(negedge AESL_clock);
AESL_ready_cnt = AESL_ready_cnt + 1;
@(posedge AESL_clock);
# 0.4;
end
end
event next_trigger_ready_cnt;
initial begin : gen_ready_cnt
ready_cnt = 0;
wait (AESL_reset === 1);
forever begin
@ (posedge AESL_clock);
if (ready == 1) begin
if (ready_cnt < AUTOTB_TRANSACTION_NUM) begin
ready_cnt = ready_cnt + 1;
end
end
-> next_trigger_ready_cnt;
end
end
wire all_finish = (done_cnt == AUTOTB_TRANSACTION_NUM);
// done_cnt
always @ (posedge AESL_clock) begin
if (~AESL_reset) begin
done_cnt <= 0;
end else begin
if (AESL_done == 1) begin
if (done_cnt < AUTOTB_TRANSACTION_NUM) begin
done_cnt <= done_cnt + 1;
end
end
end
end
initial begin : finish_simulation
integer fp1;
integer fp2;
wait (all_finish == 1);
// last transaction is saved at negedge right after last done
@ (posedge AESL_clock);
@ (posedge AESL_clock);
@ (posedge AESL_clock);
@ (posedge AESL_clock);
$display("Simulation Passed.");
$finish;
end
initial begin
AESL_clock = 0;
forever #`AUTOTB_CLOCK_PERIOD_DIV2 AESL_clock = ~AESL_clock;
end
reg end_a;
reg [31:0] size_a;
reg [31:0] size_a_backup;
reg end_b;
reg [31:0] size_b;
reg [31:0] size_b_backup;
reg end_accum_clr;
reg [31:0] size_accum_clr;
reg [31:0] size_accum_clr_backup;
reg end_accum;
reg [31:0] size_accum;
reg [31:0] size_accum_backup;
initial begin : initial_process
integer proc_rand;
rst = 0;
# 100;
repeat(3) @ (posedge AESL_clock);
rst = 1;
end
initial begin : start_process
integer proc_rand;
reg [31:0] start_cnt;
ce = 1;
start = 0;
start_cnt = 0;
wait (AESL_reset === 1);
@ (posedge AESL_clock);
#0 start = 1;
start_cnt = start_cnt + 1;
forever begin
@ (posedge AESL_clock);
if (start_cnt >= AUTOTB_TRANSACTION_NUM) begin
// keep pushing garbage in
#0 start = 1;
end
if (AESL_ready) begin
start_cnt = start_cnt + 1;
end
end
end
always @(AESL_done)
begin
tb_continue = AESL_done;
end
initial begin : ready_initial_process
ready_initial = 0;
wait (AESL_start === 1);
ready_initial = 1;
@(posedge AESL_clock);
ready_initial = 0;
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
AESL_ready_delay = 0;
else
AESL_ready_delay = AESL_ready;
end
initial begin : ready_last_n_process
ready_last_n = 1;
wait(ready_cnt == AUTOTB_TRANSACTION_NUM)
@(posedge AESL_clock);
ready_last_n <= 0;
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
ready_delay_last_n = 0;
else
ready_delay_last_n <= ready_last_n;
end
assign ready = (ready_initial | AESL_ready_delay);
assign ready_wire = ready_initial | AESL_ready_delay;
initial begin : done_delay_last_n_process
done_delay_last_n = 1;
while(done_cnt < AUTOTB_TRANSACTION_NUM)
@(posedge AESL_clock);
# 0.1;
done_delay_last_n = 0;
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
begin
AESL_done_delay <= 0;
AESL_done_delay2 <= 0;
end
else begin
AESL_done_delay <= AESL_done & done_delay_last_n;
AESL_done_delay2 <= AESL_done_delay;
end
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
interface_done = 0;
else begin
# 0.01;
if(ready === 1 && ready_cnt > 0 && ready_cnt < AUTOTB_TRANSACTION_NUM)
interface_done = 1;
else if(AESL_done_delay === 1 && done_cnt == AUTOTB_TRANSACTION_NUM)
interface_done = 1;
else
interface_done = 0;
end
end
reg dump_tvout_finish_accum;
initial begin : dump_tvout_runtime_sign_accum
integer fp;
dump_tvout_finish_accum = 0;
fp = $fopen(`AUTOTB_TVOUT_accum_out_wrapc, "w");
if (fp == 0) begin
$display("Failed to open file \"%s\"!", `AUTOTB_TVOUT_accum_out_wrapc);
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
$fdisplay(fp,"[[[runtime]]]");
$fclose(fp);
wait (done_cnt == AUTOTB_TRANSACTION_NUM);
// last transaction is saved at negedge right after last done
@ (posedge AESL_clock);
@ (posedge AESL_clock);
@ (posedge AESL_clock);
fp = $fopen(`AUTOTB_TVOUT_accum_out_wrapc, "a");
if (fp == 0) begin
$display("Failed to open file \"%s\"!", `AUTOTB_TVOUT_accum_out_wrapc);
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
$fdisplay(fp,"[[[/runtime]]]");
$fclose(fp);
dump_tvout_finish_accum = 1;
end
////////////////////////////////////////////
// progress and performance
////////////////////////////////////////////
task wait_start();
while (~AESL_start) begin
@ (posedge AESL_clock);
end
endtask
reg [31:0] clk_cnt = 0;
reg AESL_ready_p1;
reg AESL_start_p1;
always @ (posedge AESL_clock) begin
clk_cnt <= clk_cnt + 1;
AESL_ready_p1 <= AESL_ready;
AESL_start_p1 <= AESL_start;
end
reg [31:0] start_timestamp [0:AUTOTB_TRANSACTION_NUM - 1];
reg [31:0] start_cnt;
reg [31:0] ready_timestamp [0:AUTOTB_TRANSACTION_NUM - 1];
reg [31:0] ap_ready_cnt;
reg [31:0] finish_timestamp [0:AUTOTB_TRANSACTION_NUM - 1];
reg [31:0] finish_cnt;
event report_progress;
initial begin
start_cnt = 0;
finish_cnt = 0;
ap_ready_cnt = 0;
wait (AESL_reset == 1);
wait_start();
start_timestamp[start_cnt] = clk_cnt;
start_cnt = start_cnt + 1;
if (AESL_done) begin
finish_timestamp[finish_cnt] = clk_cnt;
finish_cnt = finish_cnt + 1;
end
-> report_progress;
forever begin
@ (posedge AESL_clock);
if (start_cnt < AUTOTB_TRANSACTION_NUM) begin
if ((AESL_start && AESL_ready_p1)||(AESL_start && ~AESL_start_p1)) begin
start_timestamp[start_cnt] = clk_cnt;
start_cnt = start_cnt + 1;
end
end
if (ap_ready_cnt < AUTOTB_TRANSACTION_NUM) begin
if (AESL_start_p1 && AESL_ready_p1) begin
ready_timestamp[ap_ready_cnt] = clk_cnt;
ap_ready_cnt = ap_ready_cnt + 1;
end
end
if (finish_cnt < AUTOTB_TRANSACTION_NUM) begin
if (AESL_done) begin
finish_timestamp[finish_cnt] = clk_cnt;
finish_cnt = finish_cnt + 1;
end
end
-> report_progress;
end
end
reg [31:0] progress_timeout;
initial begin : simulation_progress
real intra_progress;
wait (AESL_reset == 1);
progress_timeout = PROGRESS_TIMEOUT;
$display("////////////////////////////////////////////////////////////////////////////////////");
$display("// Inter-Transaction Progress: Completed Transaction / Total Transaction");
$display("// Intra-Transaction Progress: Measured Latency / Latency Estimation * 100%%");
$display("//");
$display("// RTL Simulation : \"Inter-Transaction Progress\" [\"Intra-Transaction Progress\"] @ \"Simulation Time\"");
$display("////////////////////////////////////////////////////////////////////////////////////");
print_progress();
while (finish_cnt < AUTOTB_TRANSACTION_NUM) begin
@ (report_progress);
if (finish_cnt < AUTOTB_TRANSACTION_NUM) begin
if (AESL_done) begin
print_progress();
progress_timeout = PROGRESS_TIMEOUT;
end else begin
if (progress_timeout == 0) begin
print_progress();
progress_timeout = PROGRESS_TIMEOUT;
end else begin
progress_timeout = progress_timeout - 1;
end
end
end
end
print_progress();
$display("////////////////////////////////////////////////////////////////////////////////////");
calculate_performance();
end
task get_intra_progress(output real intra_progress);
begin
if (start_cnt > finish_cnt) begin
intra_progress = clk_cnt - start_timestamp[finish_cnt];
end else if(finish_cnt > 0) begin
intra_progress = LATENCY_ESTIMATION;
end else begin
intra_progress = 0;
end
intra_progress = intra_progress / LATENCY_ESTIMATION;
end
endtask
task print_progress();
real intra_progress;
begin
if (LATENCY_ESTIMATION > 0) begin
get_intra_progress(intra_progress);
$display("// RTL Simulation : %0d / %0d [%2.2f%%] @ \"%0t\"", finish_cnt, AUTOTB_TRANSACTION_NUM, intra_progress * 100, $time);
end else begin
$display("// RTL Simulation : %0d / %0d [n/a] @ \"%0t\"", finish_cnt, AUTOTB_TRANSACTION_NUM, $time);
end
end
endtask
task calculate_performance();
integer i;
integer fp;
reg [31:0] latency [0:AUTOTB_TRANSACTION_NUM - 1];
reg [31:0] latency_min;
reg [31:0] latency_max;
reg [31:0] latency_total;
reg [31:0] latency_average;
reg [31:0] interval [0:AUTOTB_TRANSACTION_NUM - 2];
reg [31:0] interval_min;
reg [31:0] interval_max;
reg [31:0] interval_total;
reg [31:0] interval_average;
begin
latency_min = -1;
latency_max = 0;
latency_total = 0;
interval_min = -1;
interval_max = 0;
interval_total = 0;
for (i = 0; i < AUTOTB_TRANSACTION_NUM; i = i + 1) begin
// calculate latency
latency[i] = finish_timestamp[i] - start_timestamp[i];
if (latency[i] > latency_max) latency_max = latency[i];
if (latency[i] < latency_min) latency_min = latency[i];
latency_total = latency_total + latency[i];
// calculate interval
if (AUTOTB_TRANSACTION_NUM == 1) begin
interval[i] = 0;
interval_max = 0;
interval_min = 0;
interval_total = 0;
end else if (i < AUTOTB_TRANSACTION_NUM - 1) begin
interval[i] = finish_timestamp[i] - start_timestamp[i]+1;
if (interval[i] > interval_max) interval_max = interval[i];
if (interval[i] < interval_min) interval_min = interval[i];
interval_total = interval_total + interval[i];
end
end
latency_average = latency_total / AUTOTB_TRANSACTION_NUM;
if (AUTOTB_TRANSACTION_NUM == 1) begin
interval_average = 0;
end else begin
interval_average = interval_total / (AUTOTB_TRANSACTION_NUM - 1);
end
fp = $fopen(`AUTOTB_LAT_RESULT_FILE, "w");
$fdisplay(fp, "$MAX_LATENCY = \"%0d\"", latency_max);
$fdisplay(fp, "$MIN_LATENCY = \"%0d\"", latency_min);
$fdisplay(fp, "$AVER_LATENCY = \"%0d\"", latency_average);
$fdisplay(fp, "$MAX_THROUGHPUT = \"%0d\"", interval_max);
$fdisplay(fp, "$MIN_THROUGHPUT = \"%0d\"", interval_min);
$fdisplay(fp, "$AVER_THROUGHPUT = \"%0d\"", interval_average);
$fclose(fp);
fp = $fopen(`AUTOTB_PER_RESULT_TRANS_FILE, "w");
$fdisplay(fp, "%20s%16s%16s", "", "latency", "interval");
if (AUTOTB_TRANSACTION_NUM == 1) begin
i = 0;
$fdisplay(fp, "transaction%8d:%16d%16d", i, latency[i], interval[i]);
end else begin
for (i = 0; i < AUTOTB_TRANSACTION_NUM; i = i + 1) begin
if (i < AUTOTB_TRANSACTION_NUM - 1) begin
$fdisplay(fp, "transaction%8d:%16d%16d", i, latency[i], interval[i]);
end else begin
$fdisplay(fp, "transaction%8d:%16d x", i, latency[i]);
end
end
end
$fclose(fp);
end
endtask
////////////////////////////////////////////
// Dependence Check
////////////////////////////////////////////
`ifndef POST_SYN
`endif
endmodule
|
module ppfifo_data_generator (
input clk,
input rst,
input i_enable,
//Ping Pong FIFO Interface
input [1:0] i_wr_rdy,
output reg [1:0] o_wr_act,
input [23:0] i_wr_size,
output reg o_wr_stb,
output reg [31:0] o_wr_data
);
//Local Parameters
//Registers/Wires
reg [23:0] r_count;
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wr_act <= 0;
o_wr_stb <= 0;
o_wr_data <= 0;
r_count <= 0;
end
else begin
//Reset strobe signals
o_wr_stb <= 0;
if (i_enable) begin
if ((i_wr_rdy > 0) && (o_wr_act == 0))begin
r_count <= 0;
if (i_wr_rdy[0]) begin
//Channel 0 is open
o_wr_act[0] <= 1;
end
else begin
//Channel 1 is open
o_wr_act[1] <= 1;
end
end
else if (o_wr_act > 0) begin
if (r_count < i_wr_size) begin
//More room left in the buffer
r_count <= r_count + 1;
o_wr_stb <= 1;
//put the count in the data
o_wr_data <= r_count;
end
else begin
//Filled up the buffer, release it
o_wr_act <= 0;
end
end
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111AI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O2111AI_FUNCTIONAL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2111ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
// Local signals
wire C1 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, B1, D1, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111AI_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:14:01 03/09/2017
// Design Name:
// Module Name: SimpleAI_TB
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SimpleAI_TB;
reg [8:0] X_state;
reg [8:0] O_state;
wire [8:0] AI_move;
integer i, j;
initial begin
#10;
// do stuff
/*X_state = 9'b000000000;
O_state = 9'b000000000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
// do stuff
X_state = 9'b000010000;
O_state = 9'b100000000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
// do stuff
X_state = 9'b000010001;
O_state = 9'b101000000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
// do stuff
X_state = 9'b010010001;
O_state = 9'b101100000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
*/
X_state = 9'b00010000;
O_state = 9'b01000000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
X_state = 9'b100000000;
O_state = 9'b000010000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
X_state = 9'b110000000;
O_state = 9'b000110000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
X_state = 9'b10001001;
O_state = 9'b001101000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#200;
$finish;
end
//always #5 clk = ~clk;
SimpleAI sa (
X_state,
O_state,
AI_move
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
(* rom_style = "block" *) module Loop_loop_height_fYi_rom (
addr0, ce0, q0, addr1, ce1, q1, addr2, ce2, q2, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input[AWIDTH-1:0] addr2;
input ce2;
output reg[DWIDTH-1:0] q2;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram0[0:MEM_SIZE-1];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram1[0:MEM_SIZE-1];
initial begin
$readmemh("./Loop_loop_height_fYi_rom.dat", ram0);
$readmemh("./Loop_loop_height_fYi_rom.dat", ram1);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram0[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram0[addr1];
end
end
always @(posedge clk)
begin
if (ce2)
begin
q2 <= ram1[addr2];
end
end
endmodule
`timescale 1 ns / 1 ps
module Loop_loop_height_fYi(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
input[AddressWidth - 1:0] address2;
input ce2;
output[DataWidth - 1:0] q2;
Loop_loop_height_fYi_rom Loop_loop_height_fYi_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ),
.addr2( address2 ),
.ce2( ce2 ),
.q2( q2 ));
endmodule
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// -- --
// -- Merges two Wishbone busses onto a single bus. One side can from the --
// -- instruction cache while the other from data cache. This module can --
// -- be used to connect any 2 generic Wishbone devices. --
// -- --
// -----------------------------------------------------------------------------
`default_nettype none
module zap_wb_merger (
// Clock and reset
input wire i_clk,
input wire i_reset,
// Wishbone bus 1
input wire i_c_wb_stb,
input wire i_c_wb_cyc,
input wire i_c_wb_wen,
input wire [3:0] i_c_wb_sel,
input wire [31:0] i_c_wb_dat,
input wire [31:0] i_c_wb_adr,
input wire [2:0] i_c_wb_cti,
output reg o_c_wb_ack,
// Wishbone bus 2
input wire i_d_wb_stb,
input wire i_d_wb_cyc,
input wire i_d_wb_wen,
input wire [3:0] i_d_wb_sel,
input wire [31:0] i_d_wb_dat,
input wire [31:0] i_d_wb_adr,
input wire [2:0] i_d_wb_cti,
output reg o_d_wb_ack,
// Common bus
output reg o_wb_cyc,
output reg o_wb_stb,
output reg o_wb_wen,
output reg [3:0] o_wb_sel,
output reg [31:0] o_wb_dat,
output reg [31:0] o_wb_adr,
output reg [2:0] o_wb_cti,
input wire i_wb_ack
);
`include "zap_defines.vh"
`include "zap_localparams.vh"
localparam CODE = 1'd0;
localparam DATA = 1'd1;
reg sel_ff, sel_nxt;
always @ (posedge i_clk)
begin
if ( i_reset )
sel_ff <= CODE;
else
sel_ff <= sel_nxt;
end
always @*
begin
if ( sel_ff == CODE )
begin
o_c_wb_ack = i_wb_ack;
o_d_wb_ack = 1'd0;
end
else
begin
o_d_wb_ack = i_wb_ack;
o_c_wb_ack = 1'd0;
end
end
always @*
begin
sel_nxt = sel_ff;
case(sel_ff)
CODE:
begin
if ( i_wb_ack && (o_wb_cti == CTI_CLASSIC || o_wb_cti == CTI_EOB) && i_d_wb_stb )
sel_nxt = DATA;
else if ( !i_c_wb_stb && i_d_wb_stb )
sel_nxt = DATA;
else
sel_nxt = sel_ff;
end
DATA:
begin
if ( i_wb_ack && (o_wb_cti == CTI_CLASSIC || o_wb_cti == CTI_EOB) && i_c_wb_stb )
sel_nxt = CODE;
else if ( i_c_wb_stb && !i_d_wb_stb )
sel_nxt = CODE;
else
sel_nxt = sel_ff;
end
endcase
end
always @ (posedge i_clk)
begin
if ( i_reset )
begin
o_wb_cyc <= 0;
o_wb_stb <= 0;
o_wb_wen <= 0;
o_wb_sel <= 0;
o_wb_dat <= 0;
o_wb_adr <= 0;
o_wb_cti <= 0;
end
else if ( sel_nxt == CODE )
begin
o_wb_cyc <= i_c_wb_cyc;
o_wb_stb <= i_c_wb_stb;
o_wb_wen <= i_c_wb_wen;
o_wb_sel <= i_c_wb_sel;
o_wb_dat <= i_c_wb_dat;
o_wb_adr <= i_c_wb_adr;
o_wb_cti <= i_c_wb_cti;
end
else
begin
o_wb_cyc <= i_d_wb_cyc;
o_wb_stb <= i_d_wb_stb;
o_wb_wen <= i_d_wb_wen;
o_wb_sel <= i_d_wb_sel;
o_wb_dat <= i_d_wb_dat;
o_wb_adr <= i_d_wb_adr;
o_wb_cti <= i_d_wb_cti;
end
end
endmodule
`default_nettype wire
// ----------------------------------------------------------------------------
// EOF
// ----------------------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRBP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SDFRBP_BEHAVIORAL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) & cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) & cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRBP_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2AI_4_V
`define SKY130_FD_SC_HD__O2BB2AI_4_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o2bb2ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2bb2ai_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2bb2ai_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2AI_4_V
|
/*------------------------------------------------------------------------------
Purpose
Arithmetic and logic unit.
------------------------------------------------------------------------------*/
module mips_alu (
input clk,
input rst,
input[2:0] mode,
input mode_acompl,
input mode_bcompl,
input mode_rinv_l,
input mode_div,
input mode_mult,
input[31:0] a,
input[31:0] b,
output reg[31:0] result,
output multdiv_ready,
output[31:0] quotient,
output[31:0] remainder,
output[63:0] product
);
wire[31:0] a_pos;
wire[31:0] b_pos;
wire[31:0] acompl;
wire[31:0] bcompl;
reg calc_isover;
wire[47:0] partproduct;
reg[1:0] state_multdiv;
reg[95:0] data_hold;
reg[3:0] counter;
localparam IDLE=2'd0,
DIV=2'd1,
MULT_L=2'd2,
MULT_H=2'd3;
/*------------------------------------------------------------------------------
All calculations without multiplication and division.
------------------------------------------------------------------------------*/
assign acompl= ~a+32'd1;
assign bcompl= ~b+32'd1;
assign a_pos= mode_acompl ? acompl : a;
assign b_pos= mode_bcompl ? bcompl : b;
always @*
begin
result=32'dx;
case(mode)
0:
begin
case({mode_acompl,mode_bcompl})
2'b00: result[31:0]= a+b;
2'b01: result[31:0]= a+bcompl;
2'b10: result[31:0]= acompl+b;
2'b11: result[31:0]= acompl+bcompl;
endcase
end
1:result[31:0]=b<<a[4:0];
2:result[31:0]=b>>a[4:0];
3:
begin
case(a[4:0])
5'd0:result[31:0]=b;
5'd1:result[31:0]={{1{b[31]}},b[31:1]};
5'd2:result[31:0]={{2{b[31]}},b[31:2]};
5'd3:result[31:0]={{3{b[31]}},b[31:3]};
5'd4:result[31:0]={{4{b[31]}},b[31:4]};
5'd5:result[31:0]={{5{b[31]}},b[31:5]};
5'd6:result[31:0]={{6{b[31]}},b[31:6]};
5'd7:result[31:0]={{7{b[31]}},b[31:7]};
5'd8:result[31:0]={{8{b[31]}},b[31:8]};
5'd9:result[31:0]={{9{b[31]}},b[31:9]};
5'd10:result[31:0]={{10{b[31]}},b[31:10]};
5'd11:result[31:0]={{11{b[31]}},b[31:11]};
5'd12:result[31:0]={{12{b[31]}},b[31:12]};
5'd13:result[31:0]={{13{b[31]}},b[31:13]};
5'd14:result[31:0]={{14{b[31]}},b[31:14]};
5'd15:result[31:0]={{15{b[31]}},b[31:15]};
5'd16:result[31:0]={{16{b[31]}},b[31:16]};
5'd17:result[31:0]={{17{b[31]}},b[31:17]};
5'd18:result[31:0]={{18{b[31]}},b[31:18]};
5'd19:result[31:0]={{19{b[31]}},b[31:19]};
5'd20:result[31:0]={{20{b[31]}},b[31:20]};
5'd21:result[31:0]={{21{b[31]}},b[31:21]};
5'd22:result[31:0]={{22{b[31]}},b[31:22]};
5'd23:result[31:0]={{23{b[31]}},b[31:23]};
5'd24:result[31:0]={{24{b[31]}},b[31:24]};
5'd25:result[31:0]={{25{b[31]}},b[31:25]};
5'd26:result[31:0]={{26{b[31]}},b[31:26]};
5'd27:result[31:0]={{27{b[31]}},b[31:27]};
5'd28:result[31:0]={{28{b[31]}},b[31:28]};
5'd29:result[31:0]={{29{b[31]}},b[31:29]};
5'd30:result[31:0]={{30{b[31]}},b[31:30]};
5'd31:result[31:0]={{31{b[31]}},b[31]};
endcase
end
4:result[31:0]=a&b;
5:result[31:0]=mode_rinv_l ? ~(a|b) : a|b;
6:result[31:0]=a^b;
endcase
end
/*------------------------------------------------------------------------------
Multiplication and division.
------------------------------------------------------------------------------*/
assign multdiv_ready= state_multdiv==IDLE ? ~(mode_div | mode_mult) :
calc_isover;
always @(posedge clk)
begin
if(rst)
begin
state_multdiv<= IDLE;
calc_isover<= 1'b0;
data_hold<= 96'd0;
counter<= 4'd0;
end
else
begin
case(state_multdiv)
IDLE:
begin
counter<= 4'd0;
data_hold<= {32'd0,a_pos,b_pos};
calc_isover<= 1'b0;
state_multdiv<= mode_div ? DIV :
mode_mult ? MULT_L : IDLE;
end
DIV:
begin
counter<= counter+1'b1;
data_hold[95:32]<= {remainder,quotient};
calc_isover<= counter==4'd14 ? 1'b1 : calc_isover;
state_multdiv<= calc_isover | !mode_div ? IDLE : DIV;
end
MULT_L:
begin
data_hold[47:32]<= data_hold[63:48];
data_hold[95:48]<= partproduct;
state_multdiv<= MULT_H;
end
MULT_H:
begin
counter<= counter+1'b1;
data_hold[47:0]<= partproduct;
calc_isover<= ~counter[0] ? 1'b1 : calc_isover;
state_multdiv<= calc_isover | !mode_mult ? IDLE : MULT_H;
end
endcase
end
end
mips_div
i_div (
.acompl(mode_acompl),
.bcompl(mode_bcompl),
.div_ready(calc_isover),
.a(data_hold[63:32]),
.b(data_hold[31:0]),
.remainder_in(data_hold[95:64]),
.quotient(quotient),
.remainder(remainder)
);
mips_mult
i_mult (
.acompl(mode_acompl),
.bcompl(mode_bcompl),
.a(data_hold[47:32]),
.b(data_hold[31:0]),
.partprod_h(data_hold[47:0]),
.partprod_l(data_hold[95:48]),
.partproduct(partproduct),
.product(product)
);
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:48:31 MST 2014
// Date : Wed Feb 11 13:39:15 2015
// Host : austin_workstation_1 running 64-bit Fedora release 20 (Heisenbug)
// Command : write_verilog -force -mode funcsim
// /home/luis/FIRMWARE/git/vhdl/ip_blocks/sip_check_data/src/async_fifo_align_64in_out/async_fifo_align_64in_out_funcsim.v
// Design : async_fifo_align_64in_out
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7vx485tffg1157-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v12_0,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "async_fifo_align_64in_out,fifo_generator_v12_0,{}" *)
(* core_generation_info = "async_fifo_align_64in_out,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=9,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=virtex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=510,C_PROG_FULL_THRESH_NEGATE_VAL=509,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=9,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=9,C_WR_DEPTH=512,C_WR_FREQ=1,C_WR_PNTR_WIDTH=9,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}" *)
(* NotValidForBitStream *)
module async_fifo_align_64in_out
(clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty,
valid);
input clk;
input rst;
input [63:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
output [63:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
output valid;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire valid;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [8:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [8:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [8:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "1" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "9" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "64" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "virtex7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "1" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "512x72" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "510" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "509" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "9" *)
(* C_RD_DEPTH = "512" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "9" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "9" *)
(* C_WR_DEPTH = "512" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "9" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
async_fifo_align_64in_out_fifo_generator_v12_0__parameterized0 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(clk),
.data_count(NLW_U0_data_count_UNCONNECTED[8:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(1'b0),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[8:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(valid),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(1'b0),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[8:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module async_fifo_align_64in_out_blk_mem_gen_generic_cstr
(dout,
tmp_ram_rd_en,
clk,
Q,
E,
O3,
I1,
din);
output [63:0]dout;
input tmp_ram_rd_en;
input clk;
input [0:0]Q;
input [0:0]E;
input [8:0]O3;
input [8:0]I1;
input [63:0]din;
wire [0:0]E;
wire [8:0]I1;
wire [8:0]O3;
wire [0:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire tmp_ram_rd_en;
async_fifo_align_64in_out_blk_mem_gen_prim_width \ramloop[0].ram.r
(.E(E),
.I1(I1),
.O3(O3),
.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module async_fifo_align_64in_out_blk_mem_gen_prim_width
(dout,
tmp_ram_rd_en,
clk,
Q,
E,
O3,
I1,
din);
output [63:0]dout;
input tmp_ram_rd_en;
input clk;
input [0:0]Q;
input [0:0]E;
input [8:0]O3;
input [8:0]I1;
input [63:0]din;
wire [0:0]E;
wire [8:0]I1;
wire [8:0]O3;
wire [0:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire tmp_ram_rd_en;
async_fifo_align_64in_out_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.E(E),
.I1(I1),
.O3(O3),
.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module async_fifo_align_64in_out_blk_mem_gen_prim_wrapper
(dout,
tmp_ram_rd_en,
clk,
Q,
E,
O3,
I1,
din);
output [63:0]dout;
input tmp_ram_rd_en;
input clk;
input [0:0]Q;
input [0:0]E;
input [8:0]O3;
input [8:0]I1;
input [63:0]din;
wire [0:0]E;
wire [8:0]I1;
wire [8:0]O3;
wire [0:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire \n_68_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire \n_69_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire \n_70_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire \n_71_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire \n_72_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire \n_73_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire \n_74_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire \n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("SDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(72),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(72))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram
(.ADDRARDADDR({1'b1,O3,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,I1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ),
.DIADI(din[31:0]),
.DIBDI(din[63:32]),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(dout[31:0]),
.DOBDO(dout[63:32]),
.DOPADOP({\n_68_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,\n_69_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,\n_70_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,\n_71_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram }),
.DOPBDOP({\n_72_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,\n_73_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,\n_74_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,\n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(tmp_ram_rd_en),
.ENBWREN(E),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(Q),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({E,E,E,E,E,E,E,E}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module async_fifo_align_64in_out_blk_mem_gen_top
(dout,
tmp_ram_rd_en,
clk,
Q,
E,
O3,
I1,
din);
output [63:0]dout;
input tmp_ram_rd_en;
input clk;
input [0:0]Q;
input [0:0]E;
input [8:0]O3;
input [8:0]I1;
input [63:0]din;
wire [0:0]E;
wire [8:0]I1;
wire [8:0]O3;
wire [0:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire tmp_ram_rd_en;
async_fifo_align_64in_out_blk_mem_gen_generic_cstr \valid.cstr
(.E(E),
.I1(I1),
.O3(O3),
.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2" *)
module async_fifo_align_64in_out_blk_mem_gen_v8_2__parameterized0
(dout,
tmp_ram_rd_en,
clk,
Q,
E,
O3,
I1,
din);
output [63:0]dout;
input tmp_ram_rd_en;
input clk;
input [0:0]Q;
input [0:0]E;
input [8:0]O3;
input [8:0]I1;
input [63:0]din;
wire [0:0]E;
wire [8:0]I1;
wire [8:0]O3;
wire [0:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire tmp_ram_rd_en;
async_fifo_align_64in_out_blk_mem_gen_v8_2_synth inst_blk_mem_gen
(.E(E),
.I1(I1),
.O3(O3),
.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *)
module async_fifo_align_64in_out_blk_mem_gen_v8_2_synth
(dout,
tmp_ram_rd_en,
clk,
Q,
E,
O3,
I1,
din);
output [63:0]dout;
input tmp_ram_rd_en;
input clk;
input [0:0]Q;
input [0:0]E;
input [8:0]O3;
input [8:0]I1;
input [63:0]din;
wire [0:0]E;
wire [8:0]I1;
wire [8:0]O3;
wire [0:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire tmp_ram_rd_en;
async_fifo_align_64in_out_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.E(E),
.I1(I1),
.O3(O3),
.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "compare" *)
module async_fifo_align_64in_out_compare
(comp0,
v1_reg_0,
I1);
output comp0;
input [3:0]v1_reg_0;
input I1;
wire I1;
wire comp0;
wire \n_0_gmux.gm[3].gms.ms ;
wire [3:0]v1_reg_0;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\n_0_gmux.gm[3].gms.ms ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\n_0_gmux.gm[3].gms.ms ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],I1}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module async_fifo_align_64in_out_compare_0
(comp1,
v1_reg_1,
I2);
output comp1;
input [3:0]v1_reg_1;
input I2;
wire I2;
wire comp1;
wire \n_0_gmux.gm[3].gms.ms ;
wire [3:0]v1_reg_1;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\n_0_gmux.gm[3].gms.ms ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_1));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\n_0_gmux.gm[3].gms.ms ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],I2}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module async_fifo_align_64in_out_compare_1
(comp0,
v1_reg,
I1);
output comp0;
input [3:0]v1_reg;
input I1;
wire I1;
wire comp0;
wire \n_0_gmux.gm[3].gms.ms ;
wire [3:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\n_0_gmux.gm[3].gms.ms ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\n_0_gmux.gm[3].gms.ms ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],I1}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module async_fifo_align_64in_out_compare_2
(comp1,
v1_reg_1,
I2);
output comp1;
input [3:0]v1_reg_1;
input I2;
wire I2;
wire comp1;
wire \n_0_gmux.gm[3].gms.ms ;
wire [3:0]v1_reg_1;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\n_0_gmux.gm[3].gms.ms ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_1));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\n_0_gmux.gm[3].gms.ms ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],I2}));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module async_fifo_align_64in_out_fifo_generator_ramfifo
(dout,
empty,
valid,
full,
clk,
din,
rst,
wr_en,
rd_en);
output [63:0]dout;
output empty;
output valid;
output full;
input clk;
input [63:0]din;
input rst;
input wr_en;
input rd_en;
wire RST;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire [3:0]\grss.rsts/c2/v1_reg ;
wire [3:0]\gwss.wsts/c0/v1_reg ;
wire [3:0]\gwss.wsts/c1/v1_reg ;
wire \n_11_gntv_or_sync_fifo.gl0.rd ;
wire \n_11_gntv_or_sync_fifo.gl0.wr ;
wire n_4_rstblk;
wire n_5_rstblk;
wire [8:0]p_10_out;
wire p_18_out;
wire p_1_out;
wire [8:0]p_20_out;
wire p_4_out;
wire [7:0]p_9_out;
wire rd_en;
wire [7:0]rd_pntr_plus1;
wire rst;
wire rst_d2;
wire rst_full_gen_i;
wire tmp_ram_rd_en;
wire valid;
wire wr_en;
async_fifo_align_64in_out_rd_logic \gntv_or_sync_fifo.gl0.rd
(.I1(\n_11_gntv_or_sync_fifo.gl0.wr ),
.I2(p_10_out),
.I3(p_9_out),
.O1(rd_pntr_plus1),
.O2(\n_11_gntv_or_sync_fifo.gl0.rd ),
.O3(p_20_out),
.Q(n_4_rstblk),
.clk(clk),
.empty(empty),
.p_18_out(p_18_out),
.p_1_out(p_1_out),
.rd_en(rd_en),
.v1_reg(\gwss.wsts/c0/v1_reg ),
.v1_reg_0(\gwss.wsts/c1/v1_reg ),
.v1_reg_1(\grss.rsts/c2/v1_reg ),
.valid(valid),
.wr_en(wr_en));
async_fifo_align_64in_out_wr_logic \gntv_or_sync_fifo.gl0.wr
(.AR(RST),
.E(p_4_out),
.I1(\n_11_gntv_or_sync_fifo.gl0.rd ),
.I2(rd_pntr_plus1),
.O1(\n_11_gntv_or_sync_fifo.gl0.wr ),
.O2(p_9_out),
.O3(p_20_out[8]),
.Q(p_10_out),
.clk(clk),
.full(full),
.p_1_out(p_1_out),
.rst_d2(rst_d2),
.rst_full_gen_i(rst_full_gen_i),
.v1_reg(\grss.rsts/c2/v1_reg ),
.v1_reg_0(\gwss.wsts/c0/v1_reg ),
.v1_reg_1(\gwss.wsts/c1/v1_reg ),
.wr_en(wr_en));
async_fifo_align_64in_out_memory \gntv_or_sync_fifo.mem
(.E(p_4_out),
.I1(p_10_out),
.O3(p_20_out),
.Q(n_5_rstblk),
.clk(clk),
.din(din),
.dout(dout),
.tmp_ram_rd_en(tmp_ram_rd_en));
async_fifo_align_64in_out_reset_blk_ramfifo rstblk
(.AR(RST),
.Q({n_4_rstblk,n_5_rstblk}),
.clk(clk),
.p_18_out(p_18_out),
.rd_en(rd_en),
.rst(rst),
.rst_d2(rst_d2),
.rst_full_gen_i(rst_full_gen_i),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module async_fifo_align_64in_out_fifo_generator_top
(dout,
empty,
valid,
full,
clk,
din,
rst,
wr_en,
rd_en);
output [63:0]dout;
output empty;
output valid;
output full;
input clk;
input [63:0]din;
input rst;
input wr_en;
input rd_en;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire valid;
wire wr_en;
async_fifo_align_64in_out_fifo_generator_ramfifo \grf.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.valid(valid),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v12_0" *) (* C_COMMON_CLOCK = "1" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "9" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "64" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "64" *) (* C_ENABLE_RLOCS = "0" *)
(* C_FAMILY = "virtex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_BACKUP = "0" *) (* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_INT_CLK = "0" *) (* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *) (* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "1" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *) (* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *)
(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "512x72" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "510" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "509" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "9" *) (* C_RD_DEPTH = "512" *) (* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "9" *) (* C_UNDERFLOW_LOW = "0" *) (* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *) (* C_USE_EMBEDDED_REG = "0" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_POWER_SAVING_MODE = "0" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_VALID_LOW = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "9" *)
(* C_WR_DEPTH = "512" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "9" *)
(* C_WR_RESPONSE_LATENCY = "1" *) (* C_MSGON_VAL = "1" *) (* C_ENABLE_RST_SYNC = "1" *)
(* C_ERROR_INJECTION_TYPE = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_INTERFACE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *) (* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_SLAVE_CE = "0" *) (* C_HAS_MASTER_CE = "0" *) (* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_AXI_ID_WIDTH = "1" *) (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_LEN_WIDTH = "8" *) (* C_AXI_LOCK_WIDTH = "1" *) (* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_RUSER = "0" *) (* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TDEST = "0" *) (* C_HAS_AXIS_TUSER = "1" *) (* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TLAST = "0" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TKEEP = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TSTRB_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_AXIS_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *) (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) (* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *) (* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) (* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_DIN_WIDTH_WACH = "32" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) (* C_DIN_WIDTH_AXIS = "1" *)
(* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) (* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *) (* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *) (* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_AXIS = "0" *)
module async_fifo_align_64in_out_fifo_generator_v12_0__parameterized0
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [63:0]din;
input wr_en;
input rd_en;
input [8:0]prog_empty_thresh;
input [8:0]prog_empty_thresh_assert;
input [8:0]prog_empty_thresh_negate;
input [8:0]prog_full_thresh;
input [8:0]prog_full_thresh_assert;
input [8:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [63:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [8:0]data_count;
output [8:0]rd_data_count;
output [8:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire axi_ar_injectdbiterr;
wire axi_ar_injectsbiterr;
wire [3:0]axi_ar_prog_empty_thresh;
wire [3:0]axi_ar_prog_full_thresh;
wire axi_aw_injectdbiterr;
wire axi_aw_injectsbiterr;
wire [3:0]axi_aw_prog_empty_thresh;
wire [3:0]axi_aw_prog_full_thresh;
wire axi_b_injectdbiterr;
wire axi_b_injectsbiterr;
wire [3:0]axi_b_prog_empty_thresh;
wire [3:0]axi_b_prog_full_thresh;
wire axi_r_injectdbiterr;
wire axi_r_injectsbiterr;
wire [9:0]axi_r_prog_empty_thresh;
wire [9:0]axi_r_prog_full_thresh;
wire axi_w_injectdbiterr;
wire axi_w_injectsbiterr;
wire [9:0]axi_w_prog_empty_thresh;
wire [9:0]axi_w_prog_full_thresh;
wire axis_injectdbiterr;
wire axis_injectsbiterr;
wire [9:0]axis_prog_empty_thresh;
wire [9:0]axis_prog_full_thresh;
wire backup;
wire backup_marker;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire injectdbiterr;
wire injectsbiterr;
wire int_clk;
wire m_aclk;
wire m_aclk_en;
wire m_axi_arready;
wire m_axi_awready;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]m_axi_buser;
wire m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_ruser;
wire m_axi_rvalid;
wire m_axi_wready;
wire m_axis_tready;
wire [8:0]prog_empty_thresh;
wire [8:0]prog_empty_thresh_assert;
wire [8:0]prog_empty_thresh_negate;
wire [8:0]prog_full_thresh;
wire [8:0]prog_full_thresh_assert;
wire [8:0]prog_full_thresh_negate;
wire rd_clk;
wire rd_en;
wire rd_rst;
wire rst;
wire s_aclk;
wire s_aclk_en;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_aruser;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awuser;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_rready;
wire [63:0]s_axi_wdata;
wire [0:0]s_axi_wid;
wire s_axi_wlast;
wire [7:0]s_axi_wstrb;
wire [0:0]s_axi_wuser;
wire s_axi_wvalid;
wire [7:0]s_axis_tdata;
wire [0:0]s_axis_tdest;
wire [0:0]s_axis_tid;
wire [0:0]s_axis_tkeep;
wire s_axis_tlast;
wire [0:0]s_axis_tstrb;
wire [3:0]s_axis_tuser;
wire s_axis_tvalid;
wire srst;
wire valid;
wire wr_clk;
wire wr_en;
wire wr_rst;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
async_fifo_align_64in_out_fifo_generator_v12_0_synth inst_fifo_gen
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.valid(valid),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v12_0_synth" *)
module async_fifo_align_64in_out_fifo_generator_v12_0_synth
(dout,
empty,
valid,
full,
clk,
din,
rst,
wr_en,
rd_en);
output [63:0]dout;
output empty;
output valid;
output full;
input clk;
input [63:0]din;
input rst;
input wr_en;
input rd_en;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire valid;
wire wr_en;
async_fifo_align_64in_out_fifo_generator_top \gconvfifo.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.valid(valid),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "memory" *)
module async_fifo_align_64in_out_memory
(dout,
tmp_ram_rd_en,
clk,
Q,
E,
O3,
I1,
din);
output [63:0]dout;
input tmp_ram_rd_en;
input clk;
input [0:0]Q;
input [0:0]E;
input [8:0]O3;
input [8:0]I1;
input [63:0]din;
wire [0:0]E;
wire [8:0]I1;
wire [8:0]O3;
wire [0:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire tmp_ram_rd_en;
async_fifo_align_64in_out_blk_mem_gen_v8_2__parameterized0 \gbm.gbmg.gbmga.ngecc.bmg
(.E(E),
.I1(I1),
.O3(O3),
.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module async_fifo_align_64in_out_rd_bin_cntr
(O1,
Q,
v1_reg,
O2,
v1_reg_1,
O3,
v1_reg_0,
I2,
comp1,
rd_en,
p_1_out,
wr_en,
comp0,
p_18_out,
I3,
E,
clk,
I1);
output O1;
output [7:0]Q;
output [3:0]v1_reg;
output [8:0]O2;
output [3:0]v1_reg_1;
output O3;
output [3:0]v1_reg_0;
input [8:0]I2;
input comp1;
input rd_en;
input p_1_out;
input wr_en;
input comp0;
input p_18_out;
input [7:0]I3;
input [0:0]E;
input clk;
input [0:0]I1;
wire [0:0]E;
wire [0:0]I1;
wire [8:0]I2;
wire [7:0]I3;
wire O1;
wire [8:0]O2;
wire O3;
wire [7:0]Q;
wire clk;
wire comp0;
wire comp1;
wire \n_0_gc0.count[8]_i_2 ;
wire p_18_out;
wire p_1_out;
wire [8:0]plusOp;
wire rd_en;
wire [8:8]rd_pntr_plus1;
wire [3:0]v1_reg;
wire [3:0]v1_reg_0;
wire [3:0]v1_reg_1;
wire wr_en;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h6A))
\gc0.count[2]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\gc0.count[4]_i_1
(.I0(Q[4]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[3]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gc0.count[5]_i_1
(.I0(Q[5]),
.I1(Q[3]),
.I2(Q[2]),
.I3(Q[0]),
.I4(Q[1]),
.I5(Q[4]),
.O(plusOp[5]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h6AAA))
\gc0.count[6]_i_1
(.I0(Q[6]),
.I1(Q[4]),
.I2(\n_0_gc0.count[8]_i_2 ),
.I3(Q[5]),
.O(plusOp[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\gc0.count[7]_i_1
(.I0(Q[7]),
.I1(Q[5]),
.I2(\n_0_gc0.count[8]_i_2 ),
.I3(Q[4]),
.I4(Q[6]),
.O(plusOp[7]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gc0.count[8]_i_1
(.I0(rd_pntr_plus1),
.I1(Q[6]),
.I2(Q[4]),
.I3(\n_0_gc0.count[8]_i_2 ),
.I4(Q[5]),
.I5(Q[7]),
.O(plusOp[8]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h8000))
\gc0.count[8]_i_2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.O(\n_0_gc0.count[8]_i_2 ));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.CLR(I1),
.D(Q[0]),
.Q(O2[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.CLR(I1),
.D(Q[1]),
.Q(O2[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.CLR(I1),
.D(Q[2]),
.Q(O2[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.CLR(I1),
.D(Q[3]),
.Q(O2[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(clk),
.CE(E),
.CLR(I1),
.D(Q[4]),
.Q(O2[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(clk),
.CE(E),
.CLR(I1),
.D(Q[5]),
.Q(O2[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(clk),
.CE(E),
.CLR(I1),
.D(Q[6]),
.Q(O2[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(clk),
.CE(E),
.CLR(I1),
.D(Q[7]),
.Q(O2[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(clk),
.CE(E),
.CLR(I1),
.D(rd_pntr_plus1),
.Q(O2[8]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(plusOp[0]),
.PRE(I1),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(clk),
.CE(E),
.CLR(I1),
.D(plusOp[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(clk),
.CE(E),
.CLR(I1),
.D(plusOp[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(clk),
.CE(E),
.CLR(I1),
.D(plusOp[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(clk),
.CE(E),
.CLR(I1),
.D(plusOp[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(clk),
.CE(E),
.CLR(I1),
.D(plusOp[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(clk),
.CE(E),
.CLR(I1),
.D(plusOp[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(clk),
.CE(E),
.CLR(I1),
.D(plusOp[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(clk),
.CE(E),
.CLR(I1),
.D(plusOp[8]),
.Q(rd_pntr_plus1));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(O2[1]),
.I1(I2[1]),
.I2(O2[0]),
.I3(I2[0]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(O2[1]),
.I1(I2[1]),
.I2(O2[0]),
.I3(I2[0]),
.O(v1_reg_1[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(O2[1]),
.I1(I3[1]),
.I2(O2[0]),
.I3(I3[0]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(O2[3]),
.I1(I2[3]),
.I2(O2[2]),
.I3(I2[2]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(O2[3]),
.I1(I2[3]),
.I2(O2[2]),
.I3(I2[2]),
.O(v1_reg_1[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(O2[3]),
.I1(I3[3]),
.I2(O2[2]),
.I3(I3[2]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(O2[5]),
.I1(I2[5]),
.I2(O2[4]),
.I3(I2[4]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(O2[5]),
.I1(I2[5]),
.I2(O2[4]),
.I3(I2[4]),
.O(v1_reg_1[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(O2[5]),
.I1(I3[5]),
.I2(O2[4]),
.I3(I3[4]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(O2[7]),
.I1(I2[7]),
.I2(O2[6]),
.I3(I2[6]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(O2[7]),
.I1(I2[7]),
.I2(O2[6]),
.I3(I2[6]),
.O(v1_reg_1[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(O2[7]),
.I1(I3[7]),
.I2(O2[6]),
.I3(I3[6]),
.O(v1_reg_0[3]));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1__0
(.I0(rd_pntr_plus1),
.I1(I2[8]),
.O(O1));
LUT6 #(
.INIT(64'hF0FFFFFF80888088))
ram_empty_i_i_1
(.I0(comp1),
.I1(rd_en),
.I2(p_1_out),
.I3(wr_en),
.I4(comp0),
.I5(p_18_out),
.O(O3));
endmodule
(* ORIG_REF_NAME = "rd_handshaking_flags" *)
module async_fifo_align_64in_out_rd_handshaking_flags
(valid,
ram_valid_i,
clk,
Q);
output valid;
input ram_valid_i;
input clk;
input [0:0]Q;
wire [0:0]Q;
wire clk;
wire ram_valid_i;
wire valid;
FDCE #(
.INIT(1'b0))
\gv.ram_valid_d1_reg
(.C(clk),
.CE(1'b1),
.CLR(Q),
.D(ram_valid_i),
.Q(valid));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module async_fifo_align_64in_out_rd_logic
(p_18_out,
empty,
valid,
O1,
O2,
v1_reg,
O3,
v1_reg_0,
I1,
v1_reg_1,
clk,
Q,
I2,
rd_en,
p_1_out,
wr_en,
I3);
output p_18_out;
output empty;
output valid;
output [7:0]O1;
output O2;
output [3:0]v1_reg;
output [8:0]O3;
output [3:0]v1_reg_0;
input I1;
input [3:0]v1_reg_1;
input clk;
input [0:0]Q;
input [8:0]I2;
input rd_en;
input p_1_out;
input wr_en;
input [7:0]I3;
wire I1;
wire [8:0]I2;
wire [7:0]I3;
wire [7:0]O1;
wire O2;
wire [8:0]O3;
wire [0:0]Q;
wire [3:0]\c1/v1_reg ;
wire clk;
wire comp0;
wire comp1;
wire empty;
wire n_0_rpntr;
wire n_26_rpntr;
wire p_14_out;
wire p_18_out;
wire p_1_out;
wire ram_valid_i;
wire rd_en;
wire [3:0]v1_reg;
wire [3:0]v1_reg_0;
wire [3:0]v1_reg_1;
wire valid;
wire wr_en;
async_fifo_align_64in_out_rd_handshaking_flags \grhf.rhf
(.Q(Q),
.clk(clk),
.ram_valid_i(ram_valid_i),
.valid(valid));
async_fifo_align_64in_out_rd_status_flags_ss \grss.rsts
(.E(p_14_out),
.I1(I1),
.I2(n_0_rpntr),
.I3(n_26_rpntr),
.O1(p_18_out),
.O2(O2),
.Q(Q),
.clk(clk),
.comp0(comp0),
.comp1(comp1),
.empty(empty),
.ram_valid_i(ram_valid_i),
.rd_en(rd_en),
.v1_reg(\c1/v1_reg ),
.v1_reg_1(v1_reg_1));
async_fifo_align_64in_out_rd_bin_cntr rpntr
(.E(p_14_out),
.I1(Q),
.I2(I2),
.I3(I3),
.O1(n_0_rpntr),
.O2(O3),
.O3(n_26_rpntr),
.Q(O1),
.clk(clk),
.comp0(comp0),
.comp1(comp1),
.p_18_out(p_18_out),
.p_1_out(p_1_out),
.rd_en(rd_en),
.v1_reg(v1_reg),
.v1_reg_0(v1_reg_0),
.v1_reg_1(\c1/v1_reg ),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_ss" *)
module async_fifo_align_64in_out_rd_status_flags_ss
(comp0,
comp1,
O1,
empty,
E,
O2,
ram_valid_i,
v1_reg,
I1,
v1_reg_1,
I2,
I3,
clk,
Q,
rd_en);
output comp0;
output comp1;
output O1;
output empty;
output [0:0]E;
output O2;
output ram_valid_i;
input [3:0]v1_reg;
input I1;
input [3:0]v1_reg_1;
input I2;
input I3;
input clk;
input [0:0]Q;
input rd_en;
wire [0:0]E;
wire I1;
wire I2;
wire I3;
wire O1;
wire O2;
wire [0:0]Q;
wire clk;
wire comp0;
wire comp1;
wire empty;
wire ram_valid_i;
wire rd_en;
wire [3:0]v1_reg;
wire [3:0]v1_reg_1;
async_fifo_align_64in_out_compare_1 c1
(.I1(I1),
.comp0(comp0),
.v1_reg(v1_reg));
async_fifo_align_64in_out_compare_2 c2
(.I2(I2),
.comp1(comp1),
.v1_reg_1(v1_reg_1));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[8]_i_1
(.I0(rd_en),
.I1(O1),
.O(E));
LUT2 #(
.INIT(4'h2))
\gv.ram_valid_d1_i_1
(.I0(rd_en),
.I1(empty),
.O(ram_valid_i));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(I3),
.PRE(Q),
.Q(O1));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(clk),
.CE(1'b1),
.D(I3),
.PRE(Q),
.Q(empty));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'hB))
ram_full_i_i_2
(.I0(O1),
.I1(rd_en),
.O(O2));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module async_fifo_align_64in_out_reset_blk_ramfifo
(rst_d2,
rst_full_gen_i,
AR,
tmp_ram_rd_en,
Q,
clk,
rst,
rd_en,
p_18_out);
output rst_d2;
output rst_full_gen_i;
output [0:0]AR;
output tmp_ram_rd_en;
output [1:0]Q;
input clk;
input rst;
input rd_en;
input p_18_out;
wire [0:0]AR;
wire [1:0]Q;
wire clk;
wire \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ;
wire \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1 ;
wire p_18_out;
wire rd_en;
wire rd_rst_asreg;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
wire rst;
wire rst_d1;
wire rst_d2;
wire rst_d3;
wire rst_full_gen_i;
wire tmp_ram_rd_en;
wire wr_rst_asreg;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
LUT3 #(
.INIT(8'hAE))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1
(.I0(Q[0]),
.I1(rd_en),
.I2(p_18_out),
.O(tmp_ram_rd_en));
FDCE #(
.INIT(1'b0))
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(rst_d3),
.Q(rst_full_gen_i));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_d1));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst),
.Q(rst_d2));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst),
.Q(rst_d3));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg
(.C(clk),
.CE(1'b1),
.D(rd_rst_asreg),
.Q(rd_rst_asreg_d1),
.R(1'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg
(.C(clk),
.CE(1'b1),
.D(rd_rst_asreg_d1),
.Q(rd_rst_asreg_d2),
.R(1'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(clk),
.CE(rd_rst_asreg_d1),
.D(1'b0),
.PRE(rst),
.Q(rd_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(rd_rst_asreg),
.I1(rd_rst_asreg_d2),
.O(\n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ),
.Q(Q[0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ),
.Q(Q[1]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg
(.C(clk),
.CE(1'b1),
.D(wr_rst_asreg),
.Q(wr_rst_asreg_d1),
.R(1'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg
(.C(clk),
.CE(1'b1),
.D(wr_rst_asreg_d1),
.Q(wr_rst_asreg_d2),
.R(1'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(clk),
.CE(wr_rst_asreg_d1),
.D(1'b0),
.PRE(rst),
.Q(wr_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1
(.I0(wr_rst_asreg),
.I1(wr_rst_asreg_d2),
.O(\n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1 ),
.Q(AR));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module async_fifo_align_64in_out_wr_bin_cntr
(O1,
Q,
O2,
O4,
O5,
ram_full_comb,
v1_reg,
O3,
comp0,
I1,
comp1,
p_1_out,
wr_en,
rst_full_gen_i,
I2,
E,
clk,
AR);
output O1;
output [8:0]Q;
output O2;
output O4;
output [7:0]O5;
output ram_full_comb;
output [3:0]v1_reg;
input [0:0]O3;
input comp0;
input I1;
input comp1;
input p_1_out;
input wr_en;
input rst_full_gen_i;
input [7:0]I2;
input [0:0]E;
input clk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire I1;
wire [7:0]I2;
wire O1;
wire O2;
wire [0:0]O3;
wire O4;
wire [7:0]O5;
wire [8:0]Q;
wire clk;
wire comp0;
wire comp1;
wire \n_0_gcc0.gc0.count[8]_i_2 ;
wire p_1_out;
wire [8:8]p_9_out;
wire [8:0]plusOp__0;
wire ram_full_comb;
wire rst_full_gen_i;
wire [3:0]v1_reg;
wire wr_en;
LUT1 #(
.INIT(2'h1))
\gcc0.gc0.count[0]_i_1
(.I0(O5[0]),
.O(plusOp__0[0]));
LUT2 #(
.INIT(4'h6))
\gcc0.gc0.count[1]_i_1
(.I0(O5[0]),
.I1(O5[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h6A))
\gcc0.gc0.count[2]_i_1
(.I0(O5[2]),
.I1(O5[0]),
.I2(O5[1]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\gcc0.gc0.count[3]_i_1
(.I0(O5[1]),
.I1(O5[0]),
.I2(O5[2]),
.I3(O5[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\gcc0.gc0.count[4]_i_1
(.I0(O5[4]),
.I1(O5[1]),
.I2(O5[0]),
.I3(O5[2]),
.I4(O5[3]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gcc0.gc0.count[5]_i_1
(.I0(O5[5]),
.I1(O5[3]),
.I2(O5[2]),
.I3(O5[0]),
.I4(O5[1]),
.I5(O5[4]),
.O(plusOp__0[5]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h6AAA))
\gcc0.gc0.count[6]_i_1
(.I0(O5[6]),
.I1(O5[4]),
.I2(\n_0_gcc0.gc0.count[8]_i_2 ),
.I3(O5[5]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\gcc0.gc0.count[7]_i_1
(.I0(O5[7]),
.I1(O5[5]),
.I2(\n_0_gcc0.gc0.count[8]_i_2 ),
.I3(O5[4]),
.I4(O5[6]),
.O(plusOp__0[7]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gcc0.gc0.count[8]_i_1
(.I0(p_9_out),
.I1(O5[6]),
.I2(O5[4]),
.I3(\n_0_gcc0.gc0.count[8]_i_2 ),
.I4(O5[5]),
.I5(O5[7]),
.O(plusOp__0[8]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h8000))
\gcc0.gc0.count[8]_i_2
(.I0(O5[3]),
.I1(O5[2]),
.I2(O5[0]),
.I3(O5[1]),
.O(\n_0_gcc0.gc0.count[8]_i_2 ));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.CLR(AR),
.D(O5[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(O5[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(O5[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(O5[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[4]
(.C(clk),
.CE(E),
.CLR(AR),
.D(O5[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[5]
(.C(clk),
.CE(E),
.CLR(AR),
.D(O5[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[6]
(.C(clk),
.CE(E),
.CLR(AR),
.D(O5[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[7]
(.C(clk),
.CE(E),
.CLR(AR),
.D(O5[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[8]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_9_out),
.Q(Q[8]));
FDPE #(
.INIT(1'b1))
\gcc0.gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(plusOp__0[0]),
.PRE(AR),
.Q(O5[0]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[1]),
.Q(O5[1]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[2]),
.Q(O5[2]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[3]),
.Q(O5[3]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[4]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[4]),
.Q(O5[4]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[5]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[5]),
.Q(O5[5]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[6]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[6]),
.Q(O5[6]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[7]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[7]),
.Q(O5[7]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[8]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[8]),
.Q(p_9_out));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(Q[1]),
.I1(I2[1]),
.I2(Q[0]),
.I3(I2[0]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(Q[3]),
.I1(I2[3]),
.I2(Q[2]),
.I3(I2[2]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(Q[5]),
.I1(I2[5]),
.I2(Q[4]),
.I3(I2[4]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(Q[7]),
.I1(I2[7]),
.I2(Q[6]),
.I3(I2[6]),
.O(v1_reg[3]));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1
(.I0(Q[8]),
.I1(O3),
.O(O1));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1__1
(.I0(Q[8]),
.I1(O3),
.O(O2));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1__2
(.I0(p_9_out),
.I1(O3),
.O(O4));
LUT6 #(
.INIT(64'h00C00000DDC0DD00))
ram_full_i_i_1
(.I0(comp0),
.I1(I1),
.I2(comp1),
.I3(p_1_out),
.I4(wr_en),
.I5(rst_full_gen_i),
.O(ram_full_comb));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module async_fifo_align_64in_out_wr_logic
(p_1_out,
full,
Q,
O1,
O2,
v1_reg,
E,
v1_reg_0,
v1_reg_1,
clk,
rst_d2,
O3,
I1,
wr_en,
rst_full_gen_i,
I2,
AR);
output p_1_out;
output full;
output [8:0]Q;
output O1;
output [7:0]O2;
output [3:0]v1_reg;
output [0:0]E;
input [3:0]v1_reg_0;
input [3:0]v1_reg_1;
input clk;
input rst_d2;
input [0:0]O3;
input I1;
input wr_en;
input rst_full_gen_i;
input [7:0]I2;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire I1;
wire [7:0]I2;
wire O1;
wire [7:0]O2;
wire [0:0]O3;
wire [8:0]Q;
wire clk;
wire comp0;
wire comp1;
wire full;
wire n_0_wpntr;
wire n_11_wpntr;
wire p_1_out;
wire ram_full_comb;
wire rst_d2;
wire rst_full_gen_i;
wire [3:0]v1_reg;
wire [3:0]v1_reg_0;
wire [3:0]v1_reg_1;
wire wr_en;
async_fifo_align_64in_out_wr_status_flags_ss \gwss.wsts
(.E(E),
.I1(n_0_wpntr),
.I2(n_11_wpntr),
.clk(clk),
.comp0(comp0),
.comp1(comp1),
.full(full),
.p_1_out(p_1_out),
.ram_full_comb(ram_full_comb),
.rst_d2(rst_d2),
.v1_reg_0(v1_reg_0),
.v1_reg_1(v1_reg_1),
.wr_en(wr_en));
async_fifo_align_64in_out_wr_bin_cntr wpntr
(.AR(AR),
.E(E),
.I1(I1),
.I2(I2),
.O1(n_0_wpntr),
.O2(O1),
.O3(O3),
.O4(n_11_wpntr),
.O5(O2),
.Q(Q),
.clk(clk),
.comp0(comp0),
.comp1(comp1),
.p_1_out(p_1_out),
.ram_full_comb(ram_full_comb),
.rst_full_gen_i(rst_full_gen_i),
.v1_reg(v1_reg),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_ss" *)
module async_fifo_align_64in_out_wr_status_flags_ss
(comp0,
comp1,
p_1_out,
full,
E,
v1_reg_0,
I1,
v1_reg_1,
I2,
ram_full_comb,
clk,
rst_d2,
wr_en);
output comp0;
output comp1;
output p_1_out;
output full;
output [0:0]E;
input [3:0]v1_reg_0;
input I1;
input [3:0]v1_reg_1;
input I2;
input ram_full_comb;
input clk;
input rst_d2;
input wr_en;
wire [0:0]E;
wire I1;
wire I2;
wire clk;
wire comp0;
wire comp1;
wire full;
wire p_1_out;
wire ram_full_comb;
wire rst_d2;
wire [3:0]v1_reg_0;
wire [3:0]v1_reg_1;
wire wr_en;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2
(.I0(wr_en),
.I1(p_1_out),
.O(E));
async_fifo_align_64in_out_compare c0
(.I1(I1),
.comp0(comp0),
.v1_reg_0(v1_reg_0));
async_fifo_align_64in_out_compare_0 c1
(.I2(I2),
.comp1(comp1),
.v1_reg_1(v1_reg_1));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_comb),
.PRE(rst_d2),
.Q(p_1_out));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_comb),
.PRE(rst_d2),
.Q(full));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module Computer_System (
expansion_jp1_export,
expansion_jp2_export,
hps_io_hps_io_emac1_inst_TX_CLK,
hps_io_hps_io_emac1_inst_TXD0,
hps_io_hps_io_emac1_inst_TXD1,
hps_io_hps_io_emac1_inst_TXD2,
hps_io_hps_io_emac1_inst_TXD3,
hps_io_hps_io_emac1_inst_RXD0,
hps_io_hps_io_emac1_inst_MDIO,
hps_io_hps_io_emac1_inst_MDC,
hps_io_hps_io_emac1_inst_RX_CTL,
hps_io_hps_io_emac1_inst_TX_CTL,
hps_io_hps_io_emac1_inst_RX_CLK,
hps_io_hps_io_emac1_inst_RXD1,
hps_io_hps_io_emac1_inst_RXD2,
hps_io_hps_io_emac1_inst_RXD3,
hps_io_hps_io_qspi_inst_IO0,
hps_io_hps_io_qspi_inst_IO1,
hps_io_hps_io_qspi_inst_IO2,
hps_io_hps_io_qspi_inst_IO3,
hps_io_hps_io_qspi_inst_SS0,
hps_io_hps_io_qspi_inst_CLK,
hps_io_hps_io_sdio_inst_CMD,
hps_io_hps_io_sdio_inst_D0,
hps_io_hps_io_sdio_inst_D1,
hps_io_hps_io_sdio_inst_CLK,
hps_io_hps_io_sdio_inst_D2,
hps_io_hps_io_sdio_inst_D3,
hps_io_hps_io_usb1_inst_D0,
hps_io_hps_io_usb1_inst_D1,
hps_io_hps_io_usb1_inst_D2,
hps_io_hps_io_usb1_inst_D3,
hps_io_hps_io_usb1_inst_D4,
hps_io_hps_io_usb1_inst_D5,
hps_io_hps_io_usb1_inst_D6,
hps_io_hps_io_usb1_inst_D7,
hps_io_hps_io_usb1_inst_CLK,
hps_io_hps_io_usb1_inst_STP,
hps_io_hps_io_usb1_inst_DIR,
hps_io_hps_io_usb1_inst_NXT,
hps_io_hps_io_spim1_inst_CLK,
hps_io_hps_io_spim1_inst_MOSI,
hps_io_hps_io_spim1_inst_MISO,
hps_io_hps_io_spim1_inst_SS0,
hps_io_hps_io_uart0_inst_RX,
hps_io_hps_io_uart0_inst_TX,
hps_io_hps_io_i2c0_inst_SDA,
hps_io_hps_io_i2c0_inst_SCL,
hps_io_hps_io_i2c1_inst_SDA,
hps_io_hps_io_i2c1_inst_SCL,
hps_io_hps_io_gpio_inst_GPIO09,
hps_io_hps_io_gpio_inst_GPIO35,
hps_io_hps_io_gpio_inst_GPIO40,
hps_io_hps_io_gpio_inst_GPIO41,
hps_io_hps_io_gpio_inst_GPIO48,
hps_io_hps_io_gpio_inst_GPIO53,
hps_io_hps_io_gpio_inst_GPIO54,
hps_io_hps_io_gpio_inst_GPIO61,
leds_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
pushbuttons_export,
sdram_addr,
sdram_ba,
sdram_cas_n,
sdram_cke,
sdram_cs_n,
sdram_dq,
sdram_dqm,
sdram_ras_n,
sdram_we_n,
sdram_clk_clk,
slider_switches_export,
system_pll_ref_clk_clk,
system_pll_ref_reset_reset,
vga_CLK,
vga_HS,
vga_VS,
vga_BLANK,
vga_SYNC,
vga_R,
vga_G,
vga_B,
vga_pll_ref_clk_clk,
vga_pll_ref_reset_reset,
video_in_TD_CLK27,
video_in_TD_DATA,
video_in_TD_HS,
video_in_TD_VS,
video_in_clk27_reset,
video_in_TD_RESET,
video_in_overflow_flag);
inout [31:0] expansion_jp1_export;
inout [31:0] expansion_jp2_export;
output hps_io_hps_io_emac1_inst_TX_CLK;
output hps_io_hps_io_emac1_inst_TXD0;
output hps_io_hps_io_emac1_inst_TXD1;
output hps_io_hps_io_emac1_inst_TXD2;
output hps_io_hps_io_emac1_inst_TXD3;
input hps_io_hps_io_emac1_inst_RXD0;
inout hps_io_hps_io_emac1_inst_MDIO;
output hps_io_hps_io_emac1_inst_MDC;
input hps_io_hps_io_emac1_inst_RX_CTL;
output hps_io_hps_io_emac1_inst_TX_CTL;
input hps_io_hps_io_emac1_inst_RX_CLK;
input hps_io_hps_io_emac1_inst_RXD1;
input hps_io_hps_io_emac1_inst_RXD2;
input hps_io_hps_io_emac1_inst_RXD3;
inout hps_io_hps_io_qspi_inst_IO0;
inout hps_io_hps_io_qspi_inst_IO1;
inout hps_io_hps_io_qspi_inst_IO2;
inout hps_io_hps_io_qspi_inst_IO3;
output hps_io_hps_io_qspi_inst_SS0;
output hps_io_hps_io_qspi_inst_CLK;
inout hps_io_hps_io_sdio_inst_CMD;
inout hps_io_hps_io_sdio_inst_D0;
inout hps_io_hps_io_sdio_inst_D1;
output hps_io_hps_io_sdio_inst_CLK;
inout hps_io_hps_io_sdio_inst_D2;
inout hps_io_hps_io_sdio_inst_D3;
inout hps_io_hps_io_usb1_inst_D0;
inout hps_io_hps_io_usb1_inst_D1;
inout hps_io_hps_io_usb1_inst_D2;
inout hps_io_hps_io_usb1_inst_D3;
inout hps_io_hps_io_usb1_inst_D4;
inout hps_io_hps_io_usb1_inst_D5;
inout hps_io_hps_io_usb1_inst_D6;
inout hps_io_hps_io_usb1_inst_D7;
input hps_io_hps_io_usb1_inst_CLK;
output hps_io_hps_io_usb1_inst_STP;
input hps_io_hps_io_usb1_inst_DIR;
input hps_io_hps_io_usb1_inst_NXT;
output hps_io_hps_io_spim1_inst_CLK;
output hps_io_hps_io_spim1_inst_MOSI;
input hps_io_hps_io_spim1_inst_MISO;
output hps_io_hps_io_spim1_inst_SS0;
input hps_io_hps_io_uart0_inst_RX;
output hps_io_hps_io_uart0_inst_TX;
inout hps_io_hps_io_i2c0_inst_SDA;
inout hps_io_hps_io_i2c0_inst_SCL;
inout hps_io_hps_io_i2c1_inst_SDA;
inout hps_io_hps_io_i2c1_inst_SCL;
inout hps_io_hps_io_gpio_inst_GPIO09;
inout hps_io_hps_io_gpio_inst_GPIO35;
inout hps_io_hps_io_gpio_inst_GPIO40;
inout hps_io_hps_io_gpio_inst_GPIO41;
inout hps_io_hps_io_gpio_inst_GPIO48;
inout hps_io_hps_io_gpio_inst_GPIO53;
inout hps_io_hps_io_gpio_inst_GPIO54;
inout hps_io_hps_io_gpio_inst_GPIO61;
output [9:0] leds_export;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input [3:0] pushbuttons_export;
output [12:0] sdram_addr;
output [1:0] sdram_ba;
output sdram_cas_n;
output sdram_cke;
output sdram_cs_n;
inout [15:0] sdram_dq;
output [1:0] sdram_dqm;
output sdram_ras_n;
output sdram_we_n;
output sdram_clk_clk;
input [9:0] slider_switches_export;
input system_pll_ref_clk_clk;
input system_pll_ref_reset_reset;
output vga_CLK;
output vga_HS;
output vga_VS;
output vga_BLANK;
output vga_SYNC;
output [7:0] vga_R;
output [7:0] vga_G;
output [7:0] vga_B;
input vga_pll_ref_clk_clk;
input vga_pll_ref_reset_reset;
input video_in_TD_CLK27;
input [7:0] video_in_TD_DATA;
input video_in_TD_HS;
input video_in_TD_VS;
input video_in_clk27_reset;
output video_in_TD_RESET;
output video_in_overflow_flag;
endmodule
|
//name : real_main
//tag : c components
//source_file : test.c
///=========
///
///*Created by C2CHIP*
// Register Allocation
// ===================
// Register Name Size
// 0 real_main return address 2
`timescale 1ns/1ps
module real_main;
integer file_count;
reg [15:0] timer;
reg [1:0] program_counter;
reg [15:0] address_2;
reg [15:0] data_out_2;
reg [15:0] data_in_2;
reg write_enable_2;
reg [15:0] address_4;
reg [31:0] data_out_4;
reg [31:0] data_in_4;
reg write_enable_4;
reg [15:0] register_0;
reg clk;
reg rst;
//////////////////////////////////////////////////////////////////////////////
// CLOCK AND RESET GENERATION
//
// This file was generated in test bench mode. In this mode, the verilog
// output file can be executed directly within a verilog simulator.
// In test bench mode, a simulated clock and reset signal are generated within
// the output file.
// Verilog files generated in testbecnch mode are not suitable for synthesis,
// or for instantiation within a larger design.
initial
begin
rst <= 1'b1;
#50 rst <= 1'b0;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
//////////////////////////////////////////////////////////////////////////////
// FSM IMPLEMENTAION OF C PROCESS
//
// This section of the file contains a Finite State Machine (FSM) implementing
// the C process. In general execution is sequential, but the compiler will
// attempt to execute instructions in parallel if the instruction dependencies
// allow. Further concurrency can be achieved by executing multiple C
// processes concurrently within the device.
always @(posedge clk)
begin
//implement timer
timer <= 16'h0000;
case(program_counter)
16'd0:
begin
program_counter <= 16'd1;
program_counter <= 16'd3;
register_0 <= 16'd1;
end
16'd1:
begin
program_counter <= 16'd3;
$finish;
program_counter <= program_counter;
end
16'd3:
begin
program_counter <= 16'd2;
program_counter <= register_0;
end
endcase
if (rst == 1'b1) begin
program_counter <= 0;
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 18 23:19:00 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/system_vga_color_test_0_0_stub.v
// Design : system_vga_color_test_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_color_test,Vivado 2016.4" *)
module system_vga_color_test_0_0(clk_25, xaddr, yaddr, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk_25,xaddr[9:0],yaddr[9:0],rgb[23:0]" */;
input clk_25;
input [9:0]xaddr;
input [9:0]yaddr;
output [23:0]rgb;
endmodule
|
`include "../../../rtl/verilog/gfx/gfx_cuvz.v"
module cuvz_bench();
parameter point_width = 16;
reg clk_i;
reg rst_i;
reg ack_i;
wire ack_o;
reg write_i;
reg [point_width-1:0] factor0_i;
reg [point_width-1:0] factor1_i;
reg [31:0] color0_i;
reg [31:0] color1_i;
reg [31:0] color2_i;
reg [1:0] color_depth_i;
wire [31:0] color_o;
reg [point_width-1:0] z0_i;
reg [point_width-1:0] z1_i;
reg [point_width-1:0] z2_i;
wire [point_width-1:0] z_o;
reg [7:0] a0_i;
reg [7:0] a1_i;
reg [7:0] a2_i;
wire [7:0] a_o;
reg [point_width-1:0] u0_i;
reg [point_width-1:0] u1_i;
reg [point_width-1:0] u2_i;
wire [point_width-1:0] u_o;
reg [point_width-1:0] v0_i;
reg [point_width-1:0] v1_i;
reg [point_width-1:0] v2_i;
wire [point_width-1:0] v_o;
reg [point_width-1:0] x_i;
reg [point_width-1:0] y_i;
wire [point_width-1:0] x_o;
wire [point_width-1:0] y_o;
// Write pixel output signal
wire write_o;
initial begin
$dumpfile("cuvz.vcd");
$dumpvars(0,cuvz_bench);
// init values
clk_i = 0;
rst_i = 1;
x_i = 1;
y_i = 2;
write_i = 0;
factor0_i = 35000;
factor1_i = 0;
color0_i = 255;
color1_i = 255 << 8;
color2_i = 255 << 16;
color_depth_i = 3; // 0 = 8 bits, 1 = 16 bits, 3 = 32 bits
z0_i = 150;
z1_i = 75;
z2_i = 0;
a0_i = 150;
a1_i = 75;
a2_i = 0;
u0_i = 0;
u1_i = 0;
u2_i = 0;
v0_i = 0;
v1_i = 0;
v2_i = 0;
//timing
#2 rst_i = 0;
write_i = 1;
#2 write_i = 0;
#4 write_i = 1;
factor1_i = 10000;
#2 write_i = 0;
// end sim
#2000 $finish;
end
always begin
#1 clk_i = ~clk_i;
end
always @(posedge clk_i)
#1 ack_i <= write_o;
gfx_cuvz cuvz(
.clk_i (clk_i),
.rst_i (rst_i),
.ack_i (ack_i),
.ack_o (ack_o),
.write_i (write_i),
// Variables needed for interpolation
.factor0_i (factor0_i),
.factor1_i (factor1_i),
// Color
.color0_i (color0_i),
.color1_i (color1_i),
.color2_i (color2_i),
.color_depth_i (color_depth_i),
.color_o (color_o),
// Depth
.z0_i (z0_i),
.z1_i (z1_i),
.z2_i (z2_i),
.z_o (z_o),
// Alpha
.a0_i (a0_i),
.a1_i (a1_i),
.a2_i (a2_i),
.a_o (a_o),
// Texture coordinates
.u0_i (u0_i),
.v0_i (v0_i),
.u1_i (u1_i),
.v1_i (v1_i),
.u2_i (u2_i),
.v2_i (v2_i),
.u_o (u_o),
.v_o (v_o),
// Raster position
.x_i (x_i),
.y_i (y_i),
.x_o (x_o),
.y_o (y_o),
.write_o (write_o)
);
defparam cuvz.point_width = point_width;
endmodule
|
/*************************************************************************************
*pwmfre = 50000000Hz/pwm frequency
*dutyratio = pwmfre * percent
*Example : 100Hz 50% dutyratio pwm output
pwmfre = 50000000Hz/100Hz
dutyratio = pwmfre * 50%
**************************************************************************************/
module pwm_out(rst_n, clk, enable, pha, phb, pwmfre, dutyratio);
input rst_n;
input clk;
input enable;
input[31:0] pwmfre;
input[31:0] dutyratio;
output pha;
output phb;
reg pwm_reg;
reg [31:0] count_reg;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
count_reg <= 0;
end
else if (enable)
begin
if (count_reg < pwmfre) begin
count_reg <= count_reg + 1;
end
else begin
count_reg <= 0;
end
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
pwm_reg <= 1'h0;
end
else if (enable)
begin
if (count_reg < dutyratio) begin
pwm_reg <= 1'h1;
end
else begin
pwm_reg <= 1'h0;
end
end
end
assign pha = pwm_reg;
assign phb = ~pwm_reg;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTN_4_V
`define SKY130_FD_SC_LP__DLXTN_4_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog wrapper for dlxtn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlxtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxtn_4 (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxtn_4 (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTN_4_V
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_slave_only_top.v
// Version : v1.0
// Description: Top level module for VIVADO.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_slave_only_top
#(
parameter C_FAMILY = "virtex7" ,
parameter C_BASEADDR = 32'hffffffff,
parameter C_HIGHADDR = 32'h00000000,
parameter C_ZERO_INVALID = 1 ,
parameter C_NO_EXCL = 0 ,
parameter C_S_AXI_DATA_WIDTH = 32 ,
parameter C_S_AXI_AWUSER_WIDTH = 8 ,
parameter C_S_AXI_ARUSER_WIDTH = 8 ,
parameter C_S_AXI_ID_WIDTH = 1 ,
parameter C_M_AXI_THREAD_ID_WIDTH = 1 ,
parameter C_M_AXI_DATA_WIDTH = 32 ,
parameter C_M_AXI_AWUSER_WIDTH = 8 ,
parameter C_M_AXI_ARUSER_WIDTH = 8 ,
parameter C_ATG_AXI4LITE = 0 ,
parameter C_ATG_BASIC_AXI4 = 1 ,
parameter C_RAMINIT_CMDRAM0_F = "NONE" ,
parameter C_RAMINIT_CMDRAM1_F = "NONE" ,
parameter C_RAMINIT_CMDRAM2_F = "NONE" ,
parameter C_RAMINIT_CMDRAM3_F = "NONE" ,
parameter C_RAMINIT_SRAM0_F = "NONE" ,
parameter C_RAMINIT_PARAMRAM0_F = "NONE"
) (
input s_axi_aclk ,
input s_axi_aresetn ,
input [C_S_AXI_ID_WIDTH-1:0] awid_s ,
input [31:0] awaddr_s ,
input [7:0] awlen_s ,
input [2:0] awsize_s ,
input [1:0] awburst_s ,
input [0:0] awlock_s ,
input [3:0] awcache_s ,
input [2:0] awprot_s ,
input [3:0] awqos_s ,
input [C_S_AXI_AWUSER_WIDTH-1:0] awuser_s ,
input awvalid_s ,
output awready_s ,
input wlast_s ,
input [C_S_AXI_DATA_WIDTH-1:0] wdata_s ,
input [C_S_AXI_DATA_WIDTH/8-1:0] wstrb_s ,
input wvalid_s ,
output wready_s ,
output [C_S_AXI_ID_WIDTH-1:0] bid_s ,
output [1:0] bresp_s ,
output bvalid_s ,
input bready_s ,
input [C_S_AXI_ID_WIDTH-1:0] arid_s ,
input [31:0] araddr_s ,
input [7:0] arlen_s ,
input [2:0] arsize_s ,
input [1:0] arburst_s ,
input [0:0] arlock_s ,
input [3:0] arcache_s ,
input [2:0] arprot_s ,
input [3:0] arqos_s ,
input [C_S_AXI_ARUSER_WIDTH-1:0] aruser_s ,
input arvalid_s ,
output arready_s ,
output [C_S_AXI_ID_WIDTH-1:0] rid_s ,
output rlast_s ,
output [C_S_AXI_DATA_WIDTH-1:0] rdata_s ,
output [1:0] rresp_s ,
output rvalid_s ,
input rready_s ,
input global_test_en_l
);
/* hierarchy structure
slave
|_ slave write
|_ slave read
*/
wire reg1_sgl_slv_wr ;
wire reg1_wrs_block_rds ;
wire [15:0] err_new_slv ;
wire [15:0] wr_reg_decode ;
wire [31:0] wr_reg_data ;
wire [71:0] slv_ex_info0_ff ;
wire [71:0] slv_ex_info1_ff ;
wire slv_ex_new_valid0 ;
wire slv_ex_new_valid1 ;
wire [15:0] ar_agen_addr ;
wire [C_S_AXI_DATA_WIDTH-1:0] slvram_rd_out ;
wire [63:0] sram_rd_data_a ;
wire [10:0] slvram_waddr_ff ;
wire [7:0] slvram_we_ff ;
wire [63:0] slvram_write_data_ff ;
wire [15:0] aw_agen_addr ;
wire [15:0] cmdram_we ;
wire [63:0] slvram_wr_data ;
wire awfifo_valid ;
wire [71:0] awfifo_out ;
wire [C_S_AXI_DATA_WIDTH*9/8+1-1:0] wfifo_out ;
wire slv_ex_valid0_ff ;
wire slv_ex_valid1_ff ;
wire reg0_m_enable_ff ;
wire [9:0] reg0_mw_ptr_ff ;
wire reg0_m_enable_cmdram_mrw ;
wire reg0_m_enable_cmdram_mrw_ff ;
wire reg0_m_enable_3ff ;
wire mw_done_ff ;
wire b_resp_unexp_ff ;
wire b_resp_bad_ff ;
wire [9:0] reg0_mw_ptr_update ;
wire param_cmdw_delayop_valid ;
wire [23:0] param_cmdw_count ;
wire param_cmdw_repeatfixedop_valid;
wire param_cmdw_disable_submitincr ;
wire [127:0] cmd_out_mw ;
wire cmdram_mw_regslice_id_stable ;
wire [C_M_AXI_DATA_WIDTH-1:0] mram_out ;
wire [15:0] maw_agen_addr ;
wire [8:0] mrd_complete_ptr_ff ;
wire [15:0] Maw_fifow_dbgout ;
wire [9:0] maw_ptr_new_ff ;
wire [9:0] maw_ptr_new_2ff ;
wire maw_fifo_push_ff ;
wire cmdram_mr_regslice_id_stable ;
wire [127:0] cmd_out_mr ;
wire param_cmdr_delayop_valid ;
wire [23:0] param_cmdr_count ;
wire param_cmdr_repeatfixedop_valid;
wire param_cmdr_disable_submitincr ;
wire [10:0] mram_waddr_ff ;
wire [C_M_AXI_DATA_WIDTH/8-1:0] mram_we_ff ;
wire [C_M_AXI_DATA_WIDTH-1:0] mram_write_data_ff ;
wire [9:0] reg0_mr_ptr_ff ;
wire mr_done_ff ;
wire mr_fifo_out_resp_bad ;
wire mr_bad_last_ff ;
wire mr_unexp ;
wire [9:0] reg0_mr_ptr_update ;
wire [8:0] mwr_complete_ptr_ff ;
wire [9:0] mar_ptr_new_ff ;
wire [9:0] mar_ptr_new_2ff ;
wire mar_fifo_push_ff ;
wire [19:0] param_cmdr_submitcnt_ff ;
wire [19:0] param_cmdw_submitcnt_ff ;
wire [127:0] cmd_out_mw_regslice ;
wire [127:0] cmd_out_mr_regslice ;
wire [127:0] cmd_out_mw_regslice_ff ;
wire [127:0] cmd_out_mr_regslice_ff ;
wire [71:0] slv_ex_info1 ;
wire slv_ex_toggle_ff ;
wire maw_fifow_notfull ;
wire [9:0] reg0_mr_ptr ;
wire [9:0] reg0_mw_ptr ;
wire maw_delay_ok_ff ;
wire maw_cnt_do_dec ;
wire maw_fifo_notfull ;
wire [3:0] mawtrk_free ;
wire maw_fifo0_notfull ;
wire maw_fifo1_notfull ;
wire maw_fifo2_notfull ;
wire maw_fifo3_notfull ;
wire maw_block_push_ff ;
wire b_resp_bad ;
wire b_complete_ff ;
wire [9:0] maw_ptr_new ;
wire maw_fifow_push ;
wire mar_complete_doinc ;
wire mar_done ;
wire mr_done ;
wire mw_done ;
wire maw_fifo0_user_disableincr ;
wire maw_disableincr ;
wire maw_disableincr_ff ;
wire [7:0] reg0_rev ;
wire maw_fifo1_pop ;
wire maw_agen_done ;
wire mw_fifo_valid ;
wire mw_fifo_pop ;
wire mw_fifo_notfull ;
wire maw_fifow_pop ;
wire maw_fifow_valid ;
wire maw_done ;
wire maw_valid ;
wire maw_fifo_push ;
wire [8:0] maw_complete_depth ;
wire [8:0] mwr_complete_ptr ;
wire [15:0] maw_complete_next2 ;
wire [15:0] maw_complete_vec_ff ;
wire maw_complete_doinc ;
wire [15:0] maw_complete_inc_exp ;
wire maw_agen_valid ;
wire mar_param_disableincr_ff ;
axi_traffic_gen_v2_0_7_s_w_channel # (
.C_BASEADDR (C_BASEADDR ),
.C_HIGHADDR (C_HIGHADDR ),
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH ),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH ),
.C_S_AXI_AWUSER_WIDTH(C_S_AXI_AWUSER_WIDTH),
.C_ZERO_INVALID (C_ZERO_INVALID ),
.C_NO_EXCL (C_NO_EXCL ),
.C_ATG_BASIC_AXI4 (C_ATG_BASIC_AXI4 ),
.C_ATG_AXI4LITE (C_ATG_AXI4LITE )
) slv_wr (
.Clk (s_axi_aclk ),
.rst_l (s_axi_aresetn ),
.awid_s (awid_s ),
.awaddr_s (awaddr_s ),
.awlen_s (awlen_s ),
.awsize_s (awsize_s ),
.awburst_s (awburst_s ),
.awlock_s (awlock_s ),
.awcache_s (awcache_s ),
.awprot_s (awprot_s ),
.awqos_s (awqos_s ),
.awuser_s (awuser_s ),
.awvalid_s (awvalid_s ),
.awready_s (awready_s ),
.wlast_s (wlast_s ),
.wdata_s (wdata_s ),
.wstrb_s (wstrb_s ),
.wvalid_s (wvalid_s ),
.wready_s (wready_s ),
.bid_s (bid_s ),
.bresp_s (bresp_s ),
.bvalid_s (bvalid_s ),
.bready_s (bready_s ),
.slv_ex_info0_ff (slv_ex_info0_ff ),
.slv_ex_valid0_ff (slv_ex_valid0_ff ),
.slv_ex_info1_ff (slv_ex_info1_ff ),
.slv_ex_valid1_ff (slv_ex_valid1_ff ),
.slv_ex_new_valid0 (slv_ex_new_valid0 ),
.slv_ex_new_valid1 (slv_ex_new_valid1 ),
.ar_agen_addr (ar_agen_addr ),
.slvram_rd_out (slvram_rd_out ),
.sram_rd_data_a (sram_rd_data_a ),
.slvram_waddr_ff (slvram_waddr_ff ),
.slvram_we_ff (slvram_we_ff ),
.slvram_write_data_ff (slvram_write_data_ff )
);
axi_traffic_gen_v2_0_7_s_r_channel #
(
.C_BASEADDR (C_BASEADDR ),
.C_HIGHADDR (C_HIGHADDR ),
.C_ZERO_INVALID (C_ZERO_INVALID ),
.C_NO_EXCL (C_NO_EXCL ),
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH ),
.C_S_AXI_ARUSER_WIDTH (C_S_AXI_ARUSER_WIDTH ),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH ),
.C_ATG_BASIC_AXI4 (C_ATG_BASIC_AXI4 ),
.C_ATG_AXI4LITE (C_ATG_AXI4LITE )
) slv_rd (
.Clk (s_axi_aclk ),
.rst_l (s_axi_aresetn ),
.arid_s (arid_s ),
.araddr_s (araddr_s ),
.arlen_s (arlen_s ),
.arsize_s (arsize_s ),
.arburst_s (arburst_s ),
.arlock_s (arlock_s ),
.arcache_s (arcache_s ),
.arprot_s (arprot_s ),
.arqos_s (arqos_s ),
.aruser_s (aruser_s ),
.arvalid_s (arvalid_s ),
.arready_s (arready_s ),
.rid_s (rid_s ),
.rlast_s (rlast_s ),
.rdata_s (rdata_s ),
.rresp_s (rresp_s ),
.rvalid_s (rvalid_s ),
.rready_s (rready_s ),
.slv_ex_info0_ff (slv_ex_info0_ff ),
.slv_ex_valid0_ff (slv_ex_valid0_ff ),
.slv_ex_info1_ff (slv_ex_info1_ff ),
.slv_ex_info1 (slv_ex_info1 ),
.slv_ex_valid1_ff (slv_ex_valid1_ff ),
.slv_ex_toggle_ff (slv_ex_toggle_ff ),
.slv_ex_new_valid0 (slv_ex_new_valid0 ),
.slv_ex_new_valid1 (slv_ex_new_valid1 ),
.ar_agen_addr (ar_agen_addr ),
.slvram_rd_out (slvram_rd_out )
);
assign mram_we_ff = {(C_M_AXI_DATA_WIDTH/8) {1'b0}};
assign mram_write_data_ff= { C_M_AXI_DATA_WIDTH {1'b0}};
assign maw_agen_addr = 16'h0;
axi_traffic_gen_v2_0_7_sharedram_wrap # (
.C_FAMILY (C_FAMILY ),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH ),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH ),
.C_RAMINIT_SRAM0_F (C_RAMINIT_SRAM0_F )
) sharedram_blk (
.Clk (s_axi_aclk ),
.rst_l (s_axi_aresetn ),
.mram_waddr_ff (11'h0 ),
.mram_we_ff (mram_we_ff ),
.mram_write_data_ff (mram_write_data_ff ),
.maw_agen_addr (maw_agen_addr ),
.slvram_waddr_ff (slvram_waddr_ff ),
.slvram_we_ff (slvram_we_ff ),
.slvram_write_data_ff (slvram_write_data_ff ),
.sram_rd_data_a (sram_rd_data_a ),
.ar_agen_addr (ar_agen_addr )
);
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Reset: Push button, active low
*/
input wire reset,
/*
* GPIO
*/
output wire hbm_cattrip,
/*
* Ethernet: QSFP28
*/
output wire qsfp0_tx1_p,
output wire qsfp0_tx1_n,
input wire qsfp0_rx1_p,
input wire qsfp0_rx1_n,
output wire qsfp0_tx2_p,
output wire qsfp0_tx2_n,
input wire qsfp0_rx2_p,
input wire qsfp0_rx2_n,
output wire qsfp0_tx3_p,
output wire qsfp0_tx3_n,
input wire qsfp0_rx3_p,
input wire qsfp0_rx3_n,
output wire qsfp0_tx4_p,
output wire qsfp0_tx4_n,
input wire qsfp0_rx4_p,
input wire qsfp0_rx4_n,
// input wire qsfp0_mgt_refclk_0_p,
// input wire qsfp0_mgt_refclk_0_n,
input wire qsfp0_mgt_refclk_1_p,
input wire qsfp0_mgt_refclk_1_n,
output wire qsfp0_refclk_oe_b,
output wire qsfp0_refclk_fs,
output wire qsfp1_tx1_p,
output wire qsfp1_tx1_n,
input wire qsfp1_rx1_p,
input wire qsfp1_rx1_n,
output wire qsfp1_tx2_p,
output wire qsfp1_tx2_n,
input wire qsfp1_rx2_p,
input wire qsfp1_rx2_n,
output wire qsfp1_tx3_p,
output wire qsfp1_tx3_n,
input wire qsfp1_rx3_p,
input wire qsfp1_rx3_n,
output wire qsfp1_tx4_p,
output wire qsfp1_tx4_n,
input wire qsfp1_rx4_p,
input wire qsfp1_rx4_n,
// input wire qsfp1_mgt_refclk_0_p,
// input wire qsfp1_mgt_refclk_0_n,
// input wire qsfp1_mgt_refclk_1_p,
// input wire qsfp1_mgt_refclk_1_n,
output wire qsfp1_refclk_oe_b,
output wire qsfp1_refclk_fs
);
// Clock and reset
wire clk_161mhz_ref_int;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst = ~reset;
wire mmcm_locked;
wire mmcm_clkfb;
// MMCM instance
// 161.13 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 800 MHz to 1600 MHz
// M = 64, D = 11 sets Fvco = 937.5 MHz (in range)
// Divide by 7.5 to get output frequency of 125 MHz
MMCME4_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(7.5),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(64),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(11),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(6.206),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_161mhz_ref_int),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
assign hbm_cattrip = 1'b0;
// XGMII 10G PHY
assign qsfp0_refclk_oe_b = 1'b0;
assign qsfp0_refclk_fs = 1'b1;
wire qsfp0_tx_clk_1_int;
wire qsfp0_tx_rst_1_int;
wire [63:0] qsfp0_txd_1_int;
wire [7:0] qsfp0_txc_1_int;
wire qsfp0_rx_clk_1_int;
wire qsfp0_rx_rst_1_int;
wire [63:0] qsfp0_rxd_1_int;
wire [7:0] qsfp0_rxc_1_int;
wire qsfp0_tx_clk_2_int;
wire qsfp0_tx_rst_2_int;
wire [63:0] qsfp0_txd_2_int;
wire [7:0] qsfp0_txc_2_int;
wire qsfp0_rx_clk_2_int;
wire qsfp0_rx_rst_2_int;
wire [63:0] qsfp0_rxd_2_int;
wire [7:0] qsfp0_rxc_2_int;
wire qsfp0_tx_clk_3_int;
wire qsfp0_tx_rst_3_int;
wire [63:0] qsfp0_txd_3_int;
wire [7:0] qsfp0_txc_3_int;
wire qsfp0_rx_clk_3_int;
wire qsfp0_rx_rst_3_int;
wire [63:0] qsfp0_rxd_3_int;
wire [7:0] qsfp0_rxc_3_int;
wire qsfp0_tx_clk_4_int;
wire qsfp0_tx_rst_4_int;
wire [63:0] qsfp0_txd_4_int;
wire [7:0] qsfp0_txc_4_int;
wire qsfp0_rx_clk_4_int;
wire qsfp0_rx_rst_4_int;
wire [63:0] qsfp0_rxd_4_int;
wire [7:0] qsfp0_rxc_4_int;
assign qsfp1_refclk_oe_b = 1'b0;
assign qsfp1_refclk_fs = 1'b1;
wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [63:0] qsfp1_txd_1_int;
wire [7:0] qsfp1_txc_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [63:0] qsfp1_rxd_1_int;
wire [7:0] qsfp1_rxc_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [63:0] qsfp1_txd_2_int;
wire [7:0] qsfp1_txc_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [63:0] qsfp1_rxd_2_int;
wire [7:0] qsfp1_rxc_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [63:0] qsfp1_txd_3_int;
wire [7:0] qsfp1_txc_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [63:0] qsfp1_rxd_3_int;
wire [7:0] qsfp1_rxc_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [63:0] qsfp1_txd_4_int;
wire [7:0] qsfp1_txc_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [63:0] qsfp1_rxd_4_int;
wire [7:0] qsfp1_rxc_4_int;
wire qsfp0_rx_block_lock_1;
wire qsfp0_rx_block_lock_2;
wire qsfp0_rx_block_lock_3;
wire qsfp0_rx_block_lock_4;
wire qsfp1_rx_block_lock_1;
wire qsfp1_rx_block_lock_2;
wire qsfp1_rx_block_lock_3;
wire qsfp1_rx_block_lock_4;
wire [7:0] qsfp_gtpowergood;
wire qsfp0_mgt_refclk_1;
wire qsfp0_mgt_refclk_1_int;
wire qsfp0_mgt_refclk_1_bufg;
assign clk_161mhz_ref_int = qsfp0_mgt_refclk_1_bufg;
wire [7:0] gt_txclkout;
wire gt_txusrclk;
wire [7:0] gt_rxclkout;
wire [7:0] gt_rxusrclk;
wire gt_reset_tx_done;
wire gt_reset_rx_done;
wire [7:0] gt_txprgdivresetdone;
wire [7:0] gt_txpmaresetdone;
wire [7:0] gt_rxprgdivresetdone;
wire [7:0] gt_rxpmaresetdone;
wire gt_tx_reset = ~((>_txprgdivresetdone) & (>_txpmaresetdone));
wire gt_rx_reset = ~>_rxpmaresetdone;
reg gt_userclk_tx_active = 1'b0;
reg [7:0] gt_userclk_rx_active = 1'b0;
IBUFDS_GTE4 ibufds_gte4_qsfp0_mgt_refclk_1_inst (
.I (qsfp0_mgt_refclk_1_p),
.IB (qsfp0_mgt_refclk_1_n),
.CEB (1'b0),
.O (qsfp0_mgt_refclk_1),
.ODIV2 (qsfp0_mgt_refclk_1_int)
);
BUFG_GT bufg_gt_refclk_inst (
.CE (&qsfp_gtpowergood),
.CEMASK (1'b1),
.CLR (1'b0),
.CLRMASK (1'b1),
.DIV (3'd0),
.I (qsfp0_mgt_refclk_1_int),
.O (qsfp0_mgt_refclk_1_bufg)
);
BUFG_GT bufg_gt_tx_usrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_tx_reset),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (gt_txclkout[0]),
.O (gt_txusrclk)
);
assign clk_156mhz_int = gt_txusrclk;
always @(posedge gt_txusrclk, posedge gt_tx_reset) begin
if (gt_tx_reset) begin
gt_userclk_tx_active <= 1'b0;
end else begin
gt_userclk_tx_active <= 1'b1;
end
end
genvar n;
generate
for (n = 0; n < 8; n = n + 1) begin
BUFG_GT bufg_gt_rx_usrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_rx_reset),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (gt_rxclkout[n]),
.O (gt_rxusrclk[n])
);
always @(posedge gt_rxusrclk[n], posedge gt_rx_reset) begin
if (gt_rx_reset) begin
gt_userclk_rx_active[n] <= 1'b0;
end else begin
gt_userclk_rx_active[n] <= 1'b1;
end
end
end
endgenerate
sync_reset #(
.N(4)
)
sync_reset_156mhz_inst (
.clk(clk_156mhz_int),
.rst(~gt_reset_tx_done),
.out(rst_156mhz_int)
);
wire [5:0] qsfp0_gt_txheader_1;
wire [63:0] qsfp0_gt_txdata_1;
wire qsfp0_gt_rxgearboxslip_1;
wire [5:0] qsfp0_gt_rxheader_1;
wire [1:0] qsfp0_gt_rxheadervalid_1;
wire [63:0] qsfp0_gt_rxdata_1;
wire [1:0] qsfp0_gt_rxdatavalid_1;
wire [5:0] qsfp0_gt_txheader_2;
wire [63:0] qsfp0_gt_txdata_2;
wire qsfp0_gt_rxgearboxslip_2;
wire [5:0] qsfp0_gt_rxheader_2;
wire [1:0] qsfp0_gt_rxheadervalid_2;
wire [63:0] qsfp0_gt_rxdata_2;
wire [1:0] qsfp0_gt_rxdatavalid_2;
wire [5:0] qsfp0_gt_txheader_3;
wire [63:0] qsfp0_gt_txdata_3;
wire qsfp0_gt_rxgearboxslip_3;
wire [5:0] qsfp0_gt_rxheader_3;
wire [1:0] qsfp0_gt_rxheadervalid_3;
wire [63:0] qsfp0_gt_rxdata_3;
wire [1:0] qsfp0_gt_rxdatavalid_3;
wire [5:0] qsfp0_gt_txheader_4;
wire [63:0] qsfp0_gt_txdata_4;
wire qsfp0_gt_rxgearboxslip_4;
wire [5:0] qsfp0_gt_rxheader_4;
wire [1:0] qsfp0_gt_rxheadervalid_4;
wire [63:0] qsfp0_gt_rxdata_4;
wire [1:0] qsfp0_gt_rxdatavalid_4;
wire [5:0] qsfp1_gt_txheader_1;
wire [63:0] qsfp1_gt_txdata_1;
wire qsfp1_gt_rxgearboxslip_1;
wire [5:0] qsfp1_gt_rxheader_1;
wire [1:0] qsfp1_gt_rxheadervalid_1;
wire [63:0] qsfp1_gt_rxdata_1;
wire [1:0] qsfp1_gt_rxdatavalid_1;
wire [5:0] qsfp1_gt_txheader_2;
wire [63:0] qsfp1_gt_txdata_2;
wire qsfp1_gt_rxgearboxslip_2;
wire [5:0] qsfp1_gt_rxheader_2;
wire [1:0] qsfp1_gt_rxheadervalid_2;
wire [63:0] qsfp1_gt_rxdata_2;
wire [1:0] qsfp1_gt_rxdatavalid_2;
wire [5:0] qsfp1_gt_txheader_3;
wire [63:0] qsfp1_gt_txdata_3;
wire qsfp1_gt_rxgearboxslip_3;
wire [5:0] qsfp1_gt_rxheader_3;
wire [1:0] qsfp1_gt_rxheadervalid_3;
wire [63:0] qsfp1_gt_rxdata_3;
wire [1:0] qsfp1_gt_rxdatavalid_3;
wire [5:0] qsfp1_gt_txheader_4;
wire [63:0] qsfp1_gt_txdata_4;
wire qsfp1_gt_rxgearboxslip_4;
wire [5:0] qsfp1_gt_rxheader_4;
wire [1:0] qsfp1_gt_rxheadervalid_4;
wire [63:0] qsfp1_gt_rxdata_4;
wire [1:0] qsfp1_gt_rxdatavalid_4;
gtwizard_ultrascale_0
qsfp_gty_inst (
.gtwiz_userclk_tx_active_in(>_userclk_tx_active),
.gtwiz_userclk_rx_active_in(>_userclk_rx_active),
.gtwiz_reset_clk_freerun_in(clk_125mhz_int),
.gtwiz_reset_all_in(rst_125mhz_int),
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
.gtwiz_reset_tx_datapath_in(1'b0),
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
.gtwiz_reset_rx_datapath_in(1'b0),
.gtwiz_reset_rx_cdr_stable_out(),
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
.gtrefclk00_in({2{qsfp0_mgt_refclk_1}}),
.qpll0outclk_out(),
.qpll0outrefclk_out(),
.gtyrxn_in({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n, qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n}),
.gtyrxp_in({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p, qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p}),
.rxusrclk_in(gt_rxusrclk),
.rxusrclk2_in(gt_rxusrclk),
.gtwiz_userdata_tx_in({qsfp1_gt_txdata_4, qsfp1_gt_txdata_3, qsfp1_gt_txdata_2, qsfp1_gt_txdata_1, qsfp0_gt_txdata_4, qsfp0_gt_txdata_3, qsfp0_gt_txdata_2, qsfp0_gt_txdata_1}),
.txheader_in({qsfp1_gt_txheader_4, qsfp1_gt_txheader_3, qsfp1_gt_txheader_2, qsfp1_gt_txheader_1, qsfp0_gt_txheader_4, qsfp0_gt_txheader_3, qsfp0_gt_txheader_2, qsfp0_gt_txheader_1}),
.txsequence_in({8{1'b0}}),
.txusrclk_in({8{gt_txusrclk}}),
.txusrclk2_in({8{gt_txusrclk}}),
.gtpowergood_out(qsfp_gtpowergood),
.gtytxn_out({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n, qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n}),
.gtytxp_out({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p, qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p}),
.rxgearboxslip_in({qsfp1_gt_rxgearboxslip_4, qsfp1_gt_rxgearboxslip_3, qsfp1_gt_rxgearboxslip_2, qsfp1_gt_rxgearboxslip_1, qsfp0_gt_rxgearboxslip_4, qsfp0_gt_rxgearboxslip_3, qsfp0_gt_rxgearboxslip_2, qsfp0_gt_rxgearboxslip_1}),
.gtwiz_userdata_rx_out({qsfp1_gt_rxdata_4, qsfp1_gt_rxdata_3, qsfp1_gt_rxdata_2, qsfp1_gt_rxdata_1, qsfp0_gt_rxdata_4, qsfp0_gt_rxdata_3, qsfp0_gt_rxdata_2, qsfp0_gt_rxdata_1}),
.rxdatavalid_out({qsfp1_gt_rxdatavalid_4, qsfp1_gt_rxdatavalid_3, qsfp1_gt_rxdatavalid_2, qsfp1_gt_rxdatavalid_1, qsfp0_gt_rxdatavalid_4, qsfp0_gt_rxdatavalid_3, qsfp0_gt_rxdatavalid_2, qsfp0_gt_rxdatavalid_1}),
.rxheader_out({qsfp1_gt_rxheader_4, qsfp1_gt_rxheader_3, qsfp1_gt_rxheader_2, qsfp1_gt_rxheader_1, qsfp0_gt_rxheader_4, qsfp0_gt_rxheader_3, qsfp0_gt_rxheader_2, qsfp0_gt_rxheader_1}),
.rxheadervalid_out({qsfp1_gt_rxheadervalid_4, qsfp1_gt_rxheadervalid_3, qsfp1_gt_rxheadervalid_2, qsfp1_gt_rxheadervalid_1, qsfp0_gt_rxheadervalid_4, qsfp0_gt_rxheadervalid_3, qsfp0_gt_rxheadervalid_2, qsfp0_gt_rxheadervalid_1}),
.rxoutclk_out(gt_rxclkout),
.rxpmaresetdone_out(gt_rxpmaresetdone),
.rxprgdivresetdone_out(gt_rxprgdivresetdone),
.rxstartofseq_out(),
.txoutclk_out(gt_txclkout),
.txpmaresetdone_out(gt_txpmaresetdone),
.txprgdivresetdone_out(gt_txprgdivresetdone)
);
assign qsfp0_tx_clk_1_int = clk_156mhz_int;
assign qsfp0_tx_rst_1_int = rst_156mhz_int;
assign qsfp0_rx_clk_1_int = gt_rxusrclk[0];
sync_reset #(
.N(4)
)
qsfp0_rx_rst_1_reset_sync_inst (
.clk(qsfp0_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.out(qsfp0_rx_rst_1_int)
);
eth_phy_10g #(
.BIT_REVERSE(1),
.PRBS31_ENABLE(1)
)
qsfp0_phy_1_inst (
.tx_clk(qsfp0_tx_clk_1_int),
.tx_rst(qsfp0_tx_rst_1_int),
.rx_clk(qsfp0_rx_clk_1_int),
.rx_rst(qsfp0_rx_rst_1_int),
.xgmii_txd(qsfp0_txd_1_int),
.xgmii_txc(qsfp0_txc_1_int),
.xgmii_rxd(qsfp0_rxd_1_int),
.xgmii_rxc(qsfp0_rxc_1_int),
.serdes_tx_data(qsfp0_gt_txdata_1),
.serdes_tx_hdr(qsfp0_gt_txheader_1),
.serdes_rx_data(qsfp0_gt_rxdata_1),
.serdes_rx_hdr(qsfp0_gt_rxheader_1),
.serdes_rx_bitslip(qsfp0_gt_rxgearboxslip_1),
.rx_error_count(qsfp0_rx_error_count_1_int),
.rx_block_lock(qsfp0_rx_block_lock_1),
.rx_high_ber(),
.tx_prbs31_enable(qsfp0_tx_prbs31_enable_1_int),
.rx_prbs31_enable(qsfp0_rx_prbs31_enable_1_int)
);
assign qsfp0_tx_clk_2_int = clk_156mhz_int;
assign qsfp0_tx_rst_2_int = rst_156mhz_int;
assign qsfp0_rx_clk_2_int = gt_rxusrclk[1];
sync_reset #(
.N(4)
)
qsfp0_rx_rst_2_reset_sync_inst (
.clk(qsfp0_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.out(qsfp0_rx_rst_2_int)
);
eth_phy_10g #(
.BIT_REVERSE(1),
.PRBS31_ENABLE(1)
)
qsfp0_phy_2_inst (
.tx_clk(qsfp0_tx_clk_2_int),
.tx_rst(qsfp0_tx_rst_2_int),
.rx_clk(qsfp0_rx_clk_2_int),
.rx_rst(qsfp0_rx_rst_2_int),
.xgmii_txd(qsfp0_txd_2_int),
.xgmii_txc(qsfp0_txc_2_int),
.xgmii_rxd(qsfp0_rxd_2_int),
.xgmii_rxc(qsfp0_rxc_2_int),
.serdes_tx_data(qsfp0_gt_txdata_2),
.serdes_tx_hdr(qsfp0_gt_txheader_2),
.serdes_rx_data(qsfp0_gt_rxdata_2),
.serdes_rx_hdr(qsfp0_gt_rxheader_2),
.serdes_rx_bitslip(qsfp0_gt_rxgearboxslip_2),
.rx_error_count(qsfp0_rx_error_count_2_int),
.rx_block_lock(qsfp0_rx_block_lock_2),
.rx_high_ber(),
.tx_prbs31_enable(qsfp0_tx_prbs31_enable_2_int),
.rx_prbs31_enable(qsfp0_rx_prbs31_enable_2_int)
);
assign qsfp0_tx_clk_3_int = clk_156mhz_int;
assign qsfp0_tx_rst_3_int = rst_156mhz_int;
assign qsfp0_rx_clk_3_int = gt_rxusrclk[2];
sync_reset #(
.N(4)
)
qsfp0_rx_rst_3_reset_sync_inst (
.clk(qsfp0_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.out(qsfp0_rx_rst_3_int)
);
eth_phy_10g #(
.BIT_REVERSE(1),
.PRBS31_ENABLE(1)
)
qsfp0_phy_3_inst (
.tx_clk(qsfp0_tx_clk_3_int),
.tx_rst(qsfp0_tx_rst_3_int),
.rx_clk(qsfp0_rx_clk_3_int),
.rx_rst(qsfp0_rx_rst_3_int),
.xgmii_txd(qsfp0_txd_3_int),
.xgmii_txc(qsfp0_txc_3_int),
.xgmii_rxd(qsfp0_rxd_3_int),
.xgmii_rxc(qsfp0_rxc_3_int),
.serdes_tx_data(qsfp0_gt_txdata_3),
.serdes_tx_hdr(qsfp0_gt_txheader_3),
.serdes_rx_data(qsfp0_gt_rxdata_3),
.serdes_rx_hdr(qsfp0_gt_rxheader_3),
.serdes_rx_bitslip(qsfp0_gt_rxgearboxslip_3),
.rx_error_count(qsfp0_rx_error_count_3_int),
.rx_block_lock(qsfp0_rx_block_lock_3),
.rx_high_ber(),
.tx_prbs31_enable(qsfp0_tx_prbs31_enable_3_int),
.rx_prbs31_enable(qsfp0_rx_prbs31_enable_3_int)
);
assign qsfp0_tx_clk_4_int = clk_156mhz_int;
assign qsfp0_tx_rst_4_int = rst_156mhz_int;
assign qsfp0_rx_clk_4_int = gt_rxusrclk[3];
sync_reset #(
.N(4)
)
qsfp0_rx_rst_4_reset_sync_inst (
.clk(qsfp0_rx_clk_4_int),
.rst(~gt_reset_rx_done),
.out(qsfp0_rx_rst_4_int)
);
eth_phy_10g #(
.BIT_REVERSE(1),
.PRBS31_ENABLE(1)
)
qsfp0_phy_4_inst (
.tx_clk(qsfp0_tx_clk_4_int),
.tx_rst(qsfp0_tx_rst_4_int),
.rx_clk(qsfp0_rx_clk_4_int),
.rx_rst(qsfp0_rx_rst_4_int),
.xgmii_txd(qsfp0_txd_4_int),
.xgmii_txc(qsfp0_txc_4_int),
.xgmii_rxd(qsfp0_rxd_4_int),
.xgmii_rxc(qsfp0_rxc_4_int),
.serdes_tx_data(qsfp0_gt_txdata_4),
.serdes_tx_hdr(qsfp0_gt_txheader_4),
.serdes_rx_data(qsfp0_gt_rxdata_4),
.serdes_rx_hdr(qsfp0_gt_rxheader_4),
.serdes_rx_bitslip(qsfp0_gt_rxgearboxslip_4),
.rx_error_count(qsfp0_rx_error_count_4_int),
.rx_block_lock(qsfp0_rx_block_lock_4),
.rx_high_ber(),
.tx_prbs31_enable(qsfp0_tx_prbs31_enable_4_int),
.rx_prbs31_enable(qsfp0_rx_prbs31_enable_4_int)
);
assign qsfp1_tx_clk_1_int = clk_156mhz_int;
assign qsfp1_tx_rst_1_int = rst_156mhz_int;
assign qsfp1_rx_clk_1_int = gt_rxusrclk[4];
sync_reset #(
.N(4)
)
qsfp1_rx_rst_1_reset_sync_inst (
.clk(qsfp1_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.out(qsfp1_rx_rst_1_int)
);
eth_phy_10g #(
.BIT_REVERSE(1),
.PRBS31_ENABLE(1)
)
qsfp1_phy_1_inst (
.tx_clk(qsfp1_tx_clk_1_int),
.tx_rst(qsfp1_tx_rst_1_int),
.rx_clk(qsfp1_rx_clk_1_int),
.rx_rst(qsfp1_rx_rst_1_int),
.xgmii_txd(qsfp1_txd_1_int),
.xgmii_txc(qsfp1_txc_1_int),
.xgmii_rxd(qsfp1_rxd_1_int),
.xgmii_rxc(qsfp1_rxc_1_int),
.serdes_tx_data(qsfp1_gt_txdata_1),
.serdes_tx_hdr(qsfp1_gt_txheader_1),
.serdes_rx_data(qsfp1_gt_rxdata_1),
.serdes_rx_hdr(qsfp1_gt_rxheader_1),
.serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_1),
.rx_error_count(qsfp1_rx_error_count_1_int),
.rx_block_lock(qsfp1_rx_block_lock_1),
.rx_high_ber(),
.tx_prbs31_enable(qsfp1_tx_prbs31_enable_1_int),
.rx_prbs31_enable(qsfp1_rx_prbs31_enable_1_int)
);
assign qsfp1_tx_clk_2_int = clk_156mhz_int;
assign qsfp1_tx_rst_2_int = rst_156mhz_int;
assign qsfp1_rx_clk_2_int = gt_rxusrclk[5];
sync_reset #(
.N(4)
)
qsfp1_rx_rst_2_reset_sync_inst (
.clk(qsfp1_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.out(qsfp1_rx_rst_2_int)
);
eth_phy_10g #(
.BIT_REVERSE(1),
.PRBS31_ENABLE(1)
)
qsfp1_phy_2_inst (
.tx_clk(qsfp1_tx_clk_2_int),
.tx_rst(qsfp1_tx_rst_2_int),
.rx_clk(qsfp1_rx_clk_2_int),
.rx_rst(qsfp1_rx_rst_2_int),
.xgmii_txd(qsfp1_txd_2_int),
.xgmii_txc(qsfp1_txc_2_int),
.xgmii_rxd(qsfp1_rxd_2_int),
.xgmii_rxc(qsfp1_rxc_2_int),
.serdes_tx_data(qsfp1_gt_txdata_2),
.serdes_tx_hdr(qsfp1_gt_txheader_2),
.serdes_rx_data(qsfp1_gt_rxdata_2),
.serdes_rx_hdr(qsfp1_gt_rxheader_2),
.serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_2),
.rx_error_count(qsfp1_rx_error_count_2_int),
.rx_block_lock(qsfp1_rx_block_lock_2),
.rx_high_ber(),
.tx_prbs31_enable(qsfp1_tx_prbs31_enable_2_int),
.rx_prbs31_enable(qsfp1_rx_prbs31_enable_2_int)
);
assign qsfp1_tx_clk_3_int = clk_156mhz_int;
assign qsfp1_tx_rst_3_int = rst_156mhz_int;
assign qsfp1_rx_clk_3_int = gt_rxusrclk[6];
sync_reset #(
.N(4)
)
qsfp1_rx_rst_3_reset_sync_inst (
.clk(qsfp1_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.out(qsfp1_rx_rst_3_int)
);
eth_phy_10g #(
.BIT_REVERSE(1),
.PRBS31_ENABLE(1)
)
qsfp1_phy_3_inst (
.tx_clk(qsfp1_tx_clk_3_int),
.tx_rst(qsfp1_tx_rst_3_int),
.rx_clk(qsfp1_rx_clk_3_int),
.rx_rst(qsfp1_rx_rst_3_int),
.xgmii_txd(qsfp1_txd_3_int),
.xgmii_txc(qsfp1_txc_3_int),
.xgmii_rxd(qsfp1_rxd_3_int),
.xgmii_rxc(qsfp1_rxc_3_int),
.serdes_tx_data(qsfp1_gt_txdata_3),
.serdes_tx_hdr(qsfp1_gt_txheader_3),
.serdes_rx_data(qsfp1_gt_rxdata_3),
.serdes_rx_hdr(qsfp1_gt_rxheader_3),
.serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_3),
.rx_error_count(qsfp1_rx_error_count_3_int),
.rx_block_lock(qsfp1_rx_block_lock_3),
.rx_high_ber(),
.tx_prbs31_enable(qsfp1_tx_prbs31_enable_3_int),
.rx_prbs31_enable(qsfp1_rx_prbs31_enable_3_int)
);
assign qsfp1_tx_clk_4_int = clk_156mhz_int;
assign qsfp1_tx_rst_4_int = rst_156mhz_int;
assign qsfp1_rx_clk_4_int = gt_rxusrclk[7];
sync_reset #(
.N(4)
)
qsfp1_rx_rst_4_reset_sync_inst (
.clk(qsfp1_rx_clk_4_int),
.rst(~gt_reset_rx_done),
.out(qsfp1_rx_rst_4_int)
);
eth_phy_10g #(
.BIT_REVERSE(1),
.PRBS31_ENABLE(1)
)
qsfp1_phy_4_inst (
.tx_clk(qsfp1_tx_clk_4_int),
.tx_rst(qsfp1_tx_rst_4_int),
.rx_clk(qsfp1_rx_clk_4_int),
.rx_rst(qsfp1_rx_rst_4_int),
.xgmii_txd(qsfp1_txd_4_int),
.xgmii_txc(qsfp1_txc_4_int),
.xgmii_rxd(qsfp1_rxd_4_int),
.xgmii_rxc(qsfp1_rxc_4_int),
.serdes_tx_data(qsfp1_gt_txdata_4),
.serdes_tx_hdr(qsfp1_gt_txheader_4),
.serdes_rx_data(qsfp1_gt_rxdata_4),
.serdes_rx_hdr(qsfp1_gt_rxheader_4),
.serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_4),
.rx_error_count(qsfp1_rx_error_count_4_int),
.rx_block_lock(qsfp1_rx_block_lock_4),
.rx_high_ber(),
.tx_prbs31_enable(qsfp1_tx_prbs31_enable_4_int),
.rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int)
);
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* Ethernet: QSFP28
*/
.qsfp0_tx_clk_1(qsfp0_tx_clk_1_int),
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
.qsfp0_txd_1(qsfp0_txd_1_int),
.qsfp0_txc_1(qsfp0_txc_1_int),
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
.qsfp0_rxd_1(qsfp0_rxd_1_int),
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
.qsfp0_txc_2(qsfp0_txc_2_int),
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
.qsfp0_rxd_2(qsfp0_rxd_2_int),
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
.qsfp0_txc_3(qsfp0_txc_3_int),
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
.qsfp0_rxd_3(qsfp0_rxd_3_int),
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
.qsfp0_txc_4(qsfp0_txc_4_int),
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
.qsfp0_rxd_4(qsfp0_rxd_4_int),
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp1_tx_clk_1(qsfp1_tx_clk_1_int),
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_8_V
`define SKY130_FD_SC_HVL__BUF_8_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_8_V
|
/*
* regm - register memory
*
* A 32-bit register memory. Two registers can be read at once. The
* variables `read1` and `read2` specifiy which registers to read. The
* output is placed in `data1` and `data2`.
*
* If `regwrite` is high, the value in `wrdata` will be written to the
* register in `wrreg`.
*
* The register at address $zero is treated special, it ignores
* assignment and the value read is always zero.
*
* If the register being read is the same as that being written, the
* value being written will be available immediately without a one
* cycle delay.
*
*/
`ifndef _regm
`define _regm
`ifndef DEBUG_CPU_REG
`define DEBUG_CPU_REG 0
`endif
module regm(
input wire clk,
input wire rst,
input wire [4:0] read1, read2,
output wire [31:0] data1, data2,
input wire regwrite,
input wire [4:0] wrreg,
input wire [31:0] wrdata);
reg [31:0] mem [0:31]; // 32-bit memory with 32 entries
reg [31:0] _data1, _data2;
integer i;
initial begin
if (`DEBUG_CPU_REG) begin
$display(" $v0, $v1, $t0, $t1, $t2, $t3, $t4, $t5, $t6, $t7");
$monitor("%x, %x, %x, %x, %x, %x, %x, %x, %x, %x",
mem[2][31:0], /* $v0 */
mem[3][31:0], /* $v1 */
mem[8][31:0], /* $t0 */
mem[9][31:0], /* $t1 */
mem[10][31:0], /* $t2 */
mem[11][31:0], /* $t3 */
mem[12][31:0], /* $t4 */
mem[13][31:0], /* $t5 */
mem[14][31:0], /* $t6 */
mem[15][31:0], /* $t7 */
);
end
end
always @(*) begin
if (read1 == 5'd0)
_data1 = 32'd0;
else if ((read1 == wrreg) && regwrite)
_data1 = wrdata;
else
_data1 = mem[read1][31:0];
end
always @(*) begin
if (read2 == 5'd0)
_data2 = 32'd0;
else if ((read2 == wrreg) && regwrite)
_data2 = wrdata;
else
_data2 = mem[read2][31:0];
end
assign data1 = _data1;
assign data2 = _data2;
always @(posedge clk, negedge rst) begin
if (!rst) begin
for (i = 0; i < 32; i=i+1) begin
mem[i] <= 32'h0;
end
#1 mem[2] <= 1;
end
else if (regwrite && wrreg != 5'd0) begin
// write a non $zero register
mem[wrreg] <= wrdata;
end
end
endmodule
`endif
|
`timescale 1ns/10ps
`include "pipeconnect.h"
module bus_ctrl(input wire clk,
input wire rst,
// Master connections
input wire `REQ master1_req,
output wire `RES master1_res,
input wire `REQ master2_req,
output wire `RES master2_res,
input wire `REQ master3_req,
output wire `RES master3_res,
// Target connections
output wire `REQ target1_req,
input wire `RES target1_res,
output wire `REQ target2_req,
input wire `RES target2_res
);
parameter debug = 0;
wire master1_target1 = (master1_req`A & 'hFFF0_0000) == 'h4000_0000;
wire master2_target1 = (master2_req`A & 'hFFF0_0000) == 'h4000_0000;
wire master3_target1 = (master3_req`A & 'hFFF0_0000) == 'h4000_0000;
wire master1_target2 = (master1_req`A & 'hFFF0_0000) == 'hFF00_0000;
wire master2_target2 = (master2_req`A & 'hFFF0_0000) == 'hFF00_0000;
wire master3_target2 = (master3_req`A & 'hFFF0_0000) == 'hFF00_0000;
/*
* Dummy target the returns all memory as 0. XXX xbar3x2 is cheaper
* so we might drop this dummy target in future.
*/
wire `REQ target3_req;
wire `RES target3_res = 0;
xbar3x3 xbar3x3(clk,
master1_target1, master1_target2, master1_req, master1_res,
master2_target1, master2_target2, master2_req, master2_res,
master3_target1, master3_target2, master3_req, master3_res,
target1_req, target1_res,
target2_req, target2_res,
target3_req, target3_res);
pipechecker check1("bus_ctrl_i", clk, master1_req, master1_res);
pipechecker check2("master2", clk, master2_req, master2_res);
pipechecker check3("master3", clk, master3_req, master3_res);
pipechecker check4("bus_ctrl sram", clk, target1_req, target1_res);
pipechecker check5("bus_ctrl peri", clk, target2_req, target2_res);
pipechecker check6("target3", clk, target3_req, target3_res);
reg r1_ = 0, r2_ = 0, r3_ = 0;
always @(posedge clk) if (debug) begin
r1_ <= master1_req`R;
r2_ <= master2_req`R;
r3_ <= master3_req`R;
if (master1_req`R) $display("%5d BUS_CTRL1: vga [%x]", $time, master1_req`A);
if (master1_res`HOLD) $display("%5d BUS_CTRL1: Stall 1", $time);
if (r1_) $display("%5d BUS_CTRL1: vga -> %x", $time, master1_res`RD);
if (master1_req`W) $display("%5d BUS_CTRL1: store# %x->[%x] (bytena %x)",
$time, master1_req`WD, master1_req`A, master1_req`WBE);
if (master2_req`R) $display("%5d BUS_CTRL2: fetc [%x]", $time, master2_req`A);
if (master2_res`HOLD) $display("%5d BUS_CTRL2: Stall 2", $time);
if (r2_) $display("%5d BUS_CTRL2: fetc -> %x", $time, master2_res`RD);
if (master2_req`W) $display("%5d BUS_CTRL2: store? %x->[%x] (bytena %x)",
$time, master2_req`WD, master2_req`A, master2_req`WBE);
if (master3_req`R) $display("%5d BUS_CTRL3: load [%x]", $time, master3_req`A);
if (master3_res`HOLD) $display("%5d BUS_CTRL3: Stall 3", $time);
if (r3_) $display("%5d BUS_CTRL3: load -> %x", $time, master3_res`RD);
if (master3_req`W) $display("%5d BUS_CTRL3: store %x->[%x] (bytena %x)",
$time, master3_req`WD, master3_req`A, master3_req`WBE);
end
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//
//Burst adapter parameters:
//adapter is mastered by: pcie_compiler_0/Rx_Interface
//adapter masters: ethernet_port_interface_0/avalon_slave_1
//asp_debug: 0
//byteaddr_width: 31
//ceil_data_width: 32
//data_width: 32
//dbs_shift: 1
//dbs_upstream_burstcount_width: 11
//downstream_addr_shift: 2
//downstream_burstcount_width: 1
//downstream_max_burstcount: 1
//downstream_pipeline: 0
//dynamic_slave: 1
//master_always_burst_max_burst: 0
//master_burst_on_burst_boundaries_only: 0
//master_data_width: 64
//master_interleave: 0
//master_linewrap_bursts: 0
//nativeaddr_width: 29
//slave_always_burst_max_burst: 0
//slave_burst_on_burst_boundaries_only: 0
//slave_interleave: 0
//slave_linewrap_bursts: 0
//upstream_burstcount: upstream_burstcount
//upstream_burstcount_width: 10
//upstream_max_burstcount: 512
//zero_address_width: 0
module DE4_SOPC_burst_1 (
// inputs:
clk,
downstream_readdata,
downstream_readdatavalid,
downstream_waitrequest,
reset_n,
upstream_address,
upstream_burstcount,
upstream_byteenable,
upstream_debugaccess,
upstream_nativeaddress,
upstream_read,
upstream_write,
upstream_writedata,
// outputs:
downstream_address,
downstream_arbitrationshare,
downstream_burstcount,
downstream_byteenable,
downstream_debugaccess,
downstream_nativeaddress,
downstream_read,
downstream_write,
downstream_writedata,
upstream_readdata,
upstream_readdatavalid,
upstream_waitrequest
)
;
output [ 28: 0] downstream_address;
output [ 10: 0] downstream_arbitrationshare;
output downstream_burstcount;
output [ 3: 0] downstream_byteenable;
output downstream_debugaccess;
output [ 28: 0] downstream_nativeaddress;
output downstream_read;
output downstream_write;
output [ 31: 0] downstream_writedata;
output [ 31: 0] upstream_readdata;
output upstream_readdatavalid;
output upstream_waitrequest;
input clk;
input [ 31: 0] downstream_readdata;
input downstream_readdatavalid;
input downstream_waitrequest;
input reset_n;
input [ 30: 0] upstream_address;
input [ 9: 0] upstream_burstcount;
input [ 3: 0] upstream_byteenable;
input upstream_debugaccess;
input [ 28: 0] upstream_nativeaddress;
input upstream_read;
input upstream_write;
input [ 31: 0] upstream_writedata;
wire [ 9: 0] address_offset;
reg atomic_counter;
wire [ 30: 0] current_upstream_address;
wire [ 9: 0] current_upstream_burstcount;
wire current_upstream_read;
wire current_upstream_write;
reg [ 10: 0] data_counter;
wire [ 10: 0] dbs_adjusted_upstream_burstcount;
wire [ 28: 0] downstream_address;
wire [ 30: 0] downstream_address_base;
wire [ 10: 0] downstream_arbitrationshare;
wire downstream_burstcount;
wire downstream_burstdone;
wire [ 3: 0] downstream_byteenable;
wire downstream_debugaccess;
wire [ 28: 0] downstream_nativeaddress;
reg downstream_read;
wire downstream_write;
reg downstream_write_reg;
wire [ 31: 0] downstream_writedata;
wire enable_state_change;
wire fifo_empty;
wire max_burst_size;
wire p1_atomic_counter;
wire p1_fifo_empty;
wire p1_state_busy;
wire p1_state_idle;
wire pending_register_enable;
wire pending_upstream_read;
reg pending_upstream_read_reg;
wire pending_upstream_write;
reg pending_upstream_write_reg;
reg [ 9: 0] read_address_offset;
wire read_update_count;
wire [ 10: 0] read_write_dbs_adjusted_upstream_burstcount;
reg [ 10: 0] registered_read_write_dbs_adjusted_upstream_burstcount;
reg [ 30: 0] registered_upstream_address;
reg [ 9: 0] registered_upstream_burstcount;
reg [ 3: 0] registered_upstream_byteenable;
reg [ 28: 0] registered_upstream_nativeaddress;
reg registered_upstream_read;
reg registered_upstream_write;
reg state_busy;
reg state_idle;
wire sync_nativeaddress;
wire [ 10: 0] transactions_remaining;
reg [ 10: 0] transactions_remaining_reg;
wire update_count;
wire upstream_burstdone;
wire upstream_read_run;
wire [ 31: 0] upstream_readdata;
wire upstream_readdatavalid;
wire upstream_waitrequest;
wire upstream_write_run;
reg [ 9: 0] write_address_offset;
wire write_update_count;
assign sync_nativeaddress = |upstream_nativeaddress;
//downstream, which is an e_avalon_master
//upstream, which is an e_avalon_slave
assign upstream_burstdone = current_upstream_read ? (transactions_remaining == downstream_burstcount) & downstream_read & ~downstream_waitrequest : (transactions_remaining == (atomic_counter + 1)) & downstream_write & ~downstream_waitrequest;
assign p1_atomic_counter = atomic_counter + (downstream_read ? downstream_burstcount : 1);
assign downstream_burstdone = (downstream_read | downstream_write) & ~downstream_waitrequest & (p1_atomic_counter == downstream_burstcount);
assign dbs_adjusted_upstream_burstcount = pending_register_enable ? read_write_dbs_adjusted_upstream_burstcount : registered_read_write_dbs_adjusted_upstream_burstcount;
assign read_write_dbs_adjusted_upstream_burstcount = {upstream_burstcount,
1'b0};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
registered_read_write_dbs_adjusted_upstream_burstcount <= 0;
else if (pending_register_enable)
registered_read_write_dbs_adjusted_upstream_burstcount <= read_write_dbs_adjusted_upstream_burstcount;
end
assign p1_state_idle = state_idle & ~upstream_read & ~upstream_write | state_busy & (data_counter == 0) & p1_fifo_empty & ~pending_upstream_read & ~pending_upstream_write;
assign p1_state_busy = state_idle & (upstream_read | upstream_write) | state_busy & (~(data_counter == 0) | ~p1_fifo_empty | pending_upstream_read | pending_upstream_write);
assign enable_state_change = ~(downstream_read | downstream_write) | ~downstream_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
pending_upstream_read_reg <= 0;
else if (upstream_read & state_idle)
pending_upstream_read_reg <= -1;
else if (upstream_burstdone)
pending_upstream_read_reg <= 0;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
pending_upstream_write_reg <= 0;
else if (upstream_burstdone)
pending_upstream_write_reg <= 0;
else if (upstream_write & (state_idle | ~upstream_waitrequest))
pending_upstream_write_reg <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
state_idle <= 1;
else if (enable_state_change)
state_idle <= p1_state_idle;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
state_busy <= 0;
else if (enable_state_change)
state_busy <= p1_state_busy;
end
assign pending_upstream_read = pending_upstream_read_reg;
assign pending_upstream_write = pending_upstream_write_reg & ~upstream_burstdone;
assign pending_register_enable = state_idle | ((upstream_read | upstream_write) & ~upstream_waitrequest);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
registered_upstream_read <= 0;
else if (pending_register_enable)
registered_upstream_read <= upstream_read;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
registered_upstream_write <= 0;
else if (pending_register_enable)
registered_upstream_write <= upstream_write;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
registered_upstream_burstcount <= 0;
else if (pending_register_enable)
registered_upstream_burstcount <= upstream_burstcount;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
registered_upstream_address <= 0;
else if (pending_register_enable)
registered_upstream_address <= upstream_address;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
registered_upstream_nativeaddress <= 0;
else if (pending_register_enable)
registered_upstream_nativeaddress <= upstream_nativeaddress;
end
assign current_upstream_read = registered_upstream_read & !downstream_write;
assign current_upstream_write = registered_upstream_write;
assign current_upstream_address = registered_upstream_address;
assign current_upstream_burstcount = pending_register_enable ? upstream_burstcount : registered_upstream_burstcount;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
atomic_counter <= 0;
else if ((downstream_read | downstream_write) & ~downstream_waitrequest)
atomic_counter <= downstream_burstdone ? 0 : p1_atomic_counter;
end
assign read_update_count = current_upstream_read & ~downstream_waitrequest;
assign write_update_count = current_upstream_write & downstream_write & downstream_burstdone;
assign update_count = read_update_count | write_update_count;
assign transactions_remaining = (state_idle & (upstream_read | upstream_write)) ? dbs_adjusted_upstream_burstcount : transactions_remaining_reg;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
transactions_remaining_reg <= 0;
else
transactions_remaining_reg <= (state_idle & (upstream_read | upstream_write)) ? dbs_adjusted_upstream_burstcount : update_count ? transactions_remaining_reg - downstream_burstcount : transactions_remaining_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_counter <= 0;
else
data_counter <= state_idle & upstream_read & ~upstream_waitrequest ? dbs_adjusted_upstream_burstcount : downstream_readdatavalid ? data_counter - 1 : data_counter;
end
assign max_burst_size = 1;
assign downstream_burstcount = (transactions_remaining > max_burst_size) ? max_burst_size : transactions_remaining;
assign downstream_arbitrationshare = current_upstream_read ? (dbs_adjusted_upstream_burstcount) : dbs_adjusted_upstream_burstcount;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
write_address_offset <= 0;
else
write_address_offset <= state_idle & upstream_write ? 0 : ((downstream_write & ~downstream_waitrequest & downstream_burstdone)) ? write_address_offset + downstream_burstcount : write_address_offset;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
read_address_offset <= 0;
else
read_address_offset <= state_idle & upstream_read ? 0 : (downstream_read & ~downstream_waitrequest) ? read_address_offset + downstream_burstcount : read_address_offset;
end
assign downstream_nativeaddress = registered_upstream_nativeaddress >> 3;
assign address_offset = current_upstream_read ? read_address_offset : write_address_offset;
assign downstream_address_base = {current_upstream_address[30 : 3], 3'b000};
assign downstream_address = downstream_address_base + {address_offset, 2'b00};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
downstream_read <= 0;
else if (~downstream_read | ~downstream_waitrequest)
downstream_read <= state_idle & upstream_read ? 1 : (transactions_remaining == downstream_burstcount) ? 0 : downstream_read;
end
assign upstream_readdatavalid = downstream_readdatavalid;
assign upstream_readdata = downstream_readdata;
assign fifo_empty = 1;
assign p1_fifo_empty = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
downstream_write_reg <= 0;
else if (~downstream_write_reg | ~downstream_waitrequest)
downstream_write_reg <= state_idle & upstream_write ? 1 : ((transactions_remaining == downstream_burstcount) & downstream_burstdone) ? 0 : downstream_write_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
registered_upstream_byteenable <= 4'b1111;
else if (pending_register_enable)
registered_upstream_byteenable <= upstream_byteenable;
end
assign downstream_write = downstream_write_reg & upstream_write & !downstream_read;
assign downstream_byteenable = downstream_write_reg ? upstream_byteenable : registered_upstream_byteenable;
assign downstream_writedata = upstream_writedata;
assign upstream_read_run = state_idle & upstream_read;
assign upstream_write_run = state_busy & upstream_write & ~downstream_waitrequest & !downstream_read;
assign upstream_waitrequest = (upstream_read | current_upstream_read) ? ~upstream_read_run : current_upstream_write ? ~upstream_write_run : 1;
assign downstream_debugaccess = upstream_debugaccess;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_SYMBOL_V
/**
* udp_dff$PE_pp$PG: Positive edge triggered enabled D flip-flop
* (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PE_pp$PG (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input DATA_EN,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_SYMBOL_V
|
/*
--------------------------------------------------------------------------
Pegasus - Copyright (C) 2012 Gregory Matthew James.
This file is part of Pegasus.
Pegasus is free; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
Pegasus is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------
*/
/*
--------------------------------------------------------------------------
-- Project Code : pegasus
-- Module Name : gry_cntr
-- Author : mammenx
-- Associated modules:
-- Function : A parameterized gray code counter.
--------------------------------------------------------------------------
*/
`timescale 1ns / 10ps
module gry_cntr #(WIDTH = 8)
(
//--------------------- Misc Ports (Logic) -----------
clk,
rst_n,
rst_val,
en,
gry_cnt,
gry_cnt_nxt
//--------------------- Interfaces --------------------
);
//----------------------- Global parameters Declarations ------------------
//----------------------- Input Declarations ------------------------------
input clk;
input rst_n;
input [WIDTH-1:0] rst_val;
input en;
//----------------------- Inout Declarations ------------------------------
//----------------------- Output Declarations -----------------------------
output [WIDTH-1:0] gry_cnt;
output [WIDTH-1:0] gry_cnt_nxt;
//----------------------- Output Register Declaration ---------------------
reg [WIDTH-1:0] gry_cnt;
reg [WIDTH-1:0] gry_cnt_nxt;
//----------------------- Internal Register Declarations ------------------
reg [WIDTH-1:0] bin_cnt_f;
//----------------------- Internal Wire Declarations ----------------------
reg [WIDTH-1:0] rst_val2bin_c;
reg [WIDTH-1:0] bin_cnt_nxt_c;
genvar i;
//----------------------- Internal Interface Declarations -----------------
//----------------------- FSM Declarations --------------------------------
//----------------------- Start of Code -----------------------------------
//Convert to binary
generate
for(i=WIDTH-1; i>=0; i--)
begin : RST_VAL2BIN
assign rst_val2bin_c[i] = ^rst_val[WIDTH-1:i];
end
endgenerate
always@(posedge clk, negedge rst_n)
begin
if(~rst_n)
begin
bin_cnt_f <= rst_val2bin_c;
gry_cnt <= rst_val;
end
else
begin
bin_cnt_f <= bin_cnt_nxt_c;
gry_cnt <= gry_cnt_nxt;
end
end
assign bin_cnt_nxt_c = bin_cnt_f + en;
assign gry_cnt_nxt = bin_cnt_nxt_c ^ {1'b0,bin_cnt_nxt_c[WIDTH-1:1]};
endmodule // gry_cntr
/*
--------------------------------------------------------------------------
-- <Header>
-- <Log>
[28-06-2014 03:30:07 PM][mammenx] Moved to Verilog
[08-06-2014 02:07:20 PM][mammenx] Brought out gry_cnt_nxt port
[08-06-2014 12:46:15 PM][mammenx] Modified rest load
[07-06-2014 09:55:48 PM][mammenx] Initial version
[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file
--------------------------------------------------------------------------
*/
|
(* Copyright (c) 2011-2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import List Omega.
Require Import CpdtTactics.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* end hide *)
(** %\part{Proof Engineering}
\chapter{Proof Search by Logic Programming}% *)
(** The Curry-Howard correspondence tells us that proving is "just" programming, but the pragmatics of the two activities are very different. Generally we care about properties of a program besides its type, but the same is not true about proofs. Any proof of a theorem will do just as well. As a result, automated proof search is conceptually simpler than automated programming.
The paradigm of %\index{logic programming}%logic programming%~\cite{LogicProgramming}%, as embodied in languages like %\index{Prolog}%Prolog%~\cite{Prolog}%, is a good match for proof search in higher-order logic. This chapter introduces the details, attempting to avoid any dependence on past logic programming experience. *)
(** * Introducing Logic Programming *)
(** Recall the definition of addition from the standard library. *)
Print plus.
(** %\vspace{-.15in}%[[
plus =
fix plus (n m : nat) : nat := match n with
| 0 => m
| S p => S (plus p m)
end
]]
This is a recursive definition, in the style of functional programming. We might also follow the style of logic programming, which corresponds to the inductive relations we have defined in previous chapters. *)
Inductive plusR : nat -> nat -> nat -> Prop :=
| PlusO : forall m, plusR O m m
| PlusS : forall n m r, plusR n m r
-> plusR (S n) m (S r).
(** Intuitively, a fact [plusR n m r] only holds when [plus n m = r]. It is not hard to prove this correspondence formally. *)
(* begin thide *)
Hint Constructors plusR.
(* end thide *)
Theorem plus_plusR : forall n m,
plusR n m (n + m).
(* begin thide *)
induction n; crush.
Qed.
(* end thide *)
Theorem plusR_plus : forall n m r,
plusR n m r
-> r = n + m.
(* begin thide *)
induction 1; crush.
Qed.
(* end thide *)
(** With the functional definition of [plus], simple equalities about arithmetic follow by computation. *)
Example four_plus_three : 4 + 3 = 7.
(* begin thide *)
reflexivity.
Qed.
(* end thide *)
(* begin hide *)
(* begin thide *)
Definition er := @eq_refl.
(* end thide *)
(* end hide *)
Print four_plus_three.
(** %\vspace{-.15in}%[[
four_plus_three = eq_refl
]]
With the relational definition, the same equalities take more steps to prove, but the process is completely mechanical. For example, consider this simple-minded manual proof search strategy. The steps with error messages shown afterward will be omitted from the final script.
*)
Example four_plus_three' : plusR 4 3 7.
(* begin thide *)
(** %\vspace{-.2in}%[[
apply PlusO.
]]
%\vspace{-.2in}%
<<
Error: Impossible to unify "plusR 0 ?24 ?24" with "plusR 4 3 7".
>> *)
apply PlusS.
(** %\vspace{-.2in}%[[
apply PlusO.
]]
%\vspace{-.2in}%
<<
Error: Impossible to unify "plusR 0 ?25 ?25" with "plusR 3 3 6".
>> *)
apply PlusS.
(** %\vspace{-.2in}%[[
apply PlusO.
]]
%\vspace{-.2in}%
<<
Error: Impossible to unify "plusR 0 ?26 ?26" with "plusR 2 3 5".
>> *)
apply PlusS.
(** %\vspace{-.2in}%[[
apply PlusO.
]]
%\vspace{-.2in}%
<<
Error: Impossible to unify "plusR 0 ?27 ?27" with "plusR 1 3 4".
>> *)
apply PlusS.
apply PlusO.
(** At this point the proof is completed. It is no doubt clear that a simple procedure could find all proofs of this kind for us. We are just exploring all possible proof trees, built from the two candidate steps [apply PlusO] and [apply PlusS]. The built-in tactic %\index{tactics!auto}%[auto] follows exactly this strategy, since above we used %\index{Vernacular commands!Hint Constructors}%[Hint Constructors] to register the two candidate proof steps as hints. *)
Restart.
auto.
Qed.
(* end thide *)
Print four_plus_three'.
(** %\vspace{-.15in}%[[
four_plus_three' = PlusS (PlusS (PlusS (PlusS (PlusO 3))))
]]
*)
(** Let us try the same approach on a slightly more complex goal. *)
Example five_plus_three : plusR 5 3 8.
(* begin thide *)
auto.
(** This time, [auto] is not enough to make any progress. Since even a single candidate step may lead to an infinite space of possible proof trees, [auto] is parameterized on the maximum depth of trees to consider. The default depth is 5, and it turns out that we need depth 6 to prove the goal. *)
auto 6.
(** Sometimes it is useful to see a description of the proof tree that [auto] finds, with the %\index{tactics!info}%[info] tactical. (This tactical is not available in Coq 8.4 as of this writing, but I hope it reappears soon. The special case %\index{tactics!info\_auto}%[info_auto] tactic is provided as a chatty replacement for [auto].) *)
Restart.
info auto 6.
(** %\vspace{-.15in}%[[
== apply PlusS; apply PlusS; apply PlusS; apply PlusS;
apply PlusS; apply PlusO.
]]
*)
Qed.
(* end thide *)
(** The two key components of logic programming are%\index{backtracking}% _backtracking_ and%\index{unification}% _unification_. To see these techniques in action, consider this further silly example. Here our candidate proof steps will be reflexivity and quantifier instantiation. *)
Example seven_minus_three : exists x, x + 3 = 7.
(* begin thide *)
(** For explanatory purposes, let us simulate a user with minimal understanding of arithmetic. We start by choosing an instantiation for the quantifier. Recall that [ex_intro] is the constructor for existentially quantified formulas. *)
apply ex_intro with 0.
(** %\vspace{-.2in}%[[
reflexivity.
]]
%\vspace{-.2in}%
<<
Error: Impossible to unify "7" with "0 + 3".
>>
This seems to be a dead end. Let us _backtrack_ to the point where we ran [apply] and make a better alternate choice.
*)
Restart.
apply ex_intro with 4.
reflexivity.
Qed.
(* end thide *)
(** The above was a fairly tame example of backtracking. In general, any node in an under-construction proof tree may be the destination of backtracking an arbitrarily large number of times, as different candidate proof steps are found not to lead to full proof trees, within the depth bound passed to [auto].
Next we demonstrate unification, which will be easier when we switch to the relational formulation of addition. *)
Example seven_minus_three' : exists x, plusR x 3 7.
(* begin thide *)
(** We could attempt to guess the quantifier instantiation manually as before, but here there is no need. Instead of [apply], we use %\index{tactics!eapply}%[eapply], which proceeds with placeholder%\index{unification variable}% _unification variables_ standing in for those parameters we wish to postpone guessing. *)
eapply ex_intro.
(** [[
1 subgoal
============================
plusR ?70 3 7
]]
Now we can finish the proof with the right applications of [plusR]'s constructors. Note that new unification variables are being generated to stand for new unknowns. *)
apply PlusS.
(** [[
============================
plusR ?71 3 6
]]
*)
apply PlusS. apply PlusS. apply PlusS.
(** [[
============================
plusR ?74 3 3
]]
*)
apply PlusO.
(** The [auto] tactic will not perform these sorts of steps that introduce unification variables, but the %\index{tactics!eauto}%[eauto] tactic will. It is helpful to work with two separate tactics, because proof search in the [eauto] style can uncover many more potential proof trees and hence take much longer to run. *)
Restart.
info eauto 6.
(** %\vspace{-.15in}%[[
== eapply ex_intro; apply PlusS; apply PlusS;
apply PlusS; apply PlusS; apply PlusO.
]]
*)
Qed.
(* end thide *)
(** This proof gives us our first example where logic programming simplifies proof search compared to functional programming. In general, functional programs are only meant to be run in a single direction; a function has disjoint sets of inputs and outputs. In the last example, we effectively ran a logic program backwards, deducing an input that gives rise to a certain output. The same works for deducing an unknown value of the other input. *)
Example seven_minus_four' : exists x, plusR 4 x 7.
(* begin thide *)
eauto 6.
Qed.
(* end thide *)
(** By proving the right auxiliary facts, we can reason about specific functional programs in the same way as we did above for a logic program. Let us prove that the constructors of [plusR] have natural interpretations as lemmas about [plus]. We can find the first such lemma already proved in the standard library, using the %\index{Vernacular commands!SearchRewrite}%[SearchRewrite] command to find a library function proving an equality whose lefthand or righthand side matches a pattern with wildcards. *)
(* begin thide *)
SearchRewrite (O + _).
(** %\vspace{-.15in}%[[
plus_O_n: forall n : nat, 0 + n = n
]]
The command %\index{Vernacular commands!Hint Immediate}%[Hint Immediate] asks [auto] and [eauto] to consider this lemma as a candidate step for any leaf of a proof tree. *)
Hint Immediate plus_O_n.
(** The counterpart to [PlusS] we will prove ourselves. *)
Lemma plusS : forall n m r,
n + m = r
-> S n + m = S r.
crush.
Qed.
(** The command %\index{Vernacular commands!Hint Resolve}%[Hint Resolve] adds a new candidate proof step, to be attempted at any level of a proof tree, not just at leaves. *)
Hint Resolve plusS.
(* end thide *)
(** Now that we have registered the proper hints, we can replicate our previous examples with the normal, functional addition [plus]. *)
Example seven_minus_three'' : exists x, x + 3 = 7.
(* begin thide *)
eauto 6.
Qed.
(* end thide *)
Example seven_minus_four : exists x, 4 + x = 7.
(* begin thide *)
eauto 6.
Qed.
(* end thide *)
(** This new hint database is far from a complete decision procedure, as we see in a further example that [eauto] does not finish. *)
Example seven_minus_four_zero : exists x, 4 + x + 0 = 7.
(* begin thide *)
eauto 6.
Abort.
(* end thide *)
(** A further lemma will be helpful. *)
(* begin thide *)
Lemma plusO : forall n m,
n = m
-> n + 0 = m.
crush.
Qed.
Hint Resolve plusO.
(* end thide *)
(** Note that, if we consider the inputs to [plus] as the inputs of a corresponding logic program, the new rule [plusO] introduces an ambiguity. For instance, a sum [0 + 0] would match both of [plus_O_n] and [plusO], depending on which operand we focus on. This ambiguity may increase the number of potential search trees, slowing proof search, but semantically it presents no problems, and in fact it leads to an automated proof of the present example. *)
Example seven_minus_four_zero : exists x, 4 + x + 0 = 7.
(* begin thide *)
eauto 7.
Qed.
(* end thide *)
(** Just how much damage can be done by adding hints that grow the space of possible proof trees? A classic gotcha comes from unrestricted use of transitivity, as embodied in this library theorem about equality: *)
Check eq_trans.
(** %\vspace{-.15in}%[[
eq_trans
: forall (A : Type) (x y z : A), x = y -> y = z -> x = z
]]
*)
(** Hints are scoped over sections, so let us enter a section to contain the effects of an unfortunate hint choice. *)
Section slow.
Hint Resolve eq_trans.
(** The following fact is false, but that does not stop [eauto] from taking a very long time to search for proofs of it. We use the handy %\index{Vernacular commands!Time}%[Time] command to measure how long a proof step takes to run. None of the following steps make any progress. *)
Example zero_minus_one : exists x, 1 + x = 0.
Time eauto 1.
(** %\vspace{-.15in}%
<<
Finished transaction in 0. secs (0.u,0.s)
>>
*)
Time eauto 2.
(** %\vspace{-.15in}%
<<
Finished transaction in 0. secs (0.u,0.s)
>>
*)
Time eauto 3.
(** %\vspace{-.15in}%
<<
Finished transaction in 0. secs (0.008u,0.s)
>>
*)
Time eauto 4.
(** %\vspace{-.15in}%
<<
Finished transaction in 0. secs (0.068005u,0.004s)
>>
*)
Time eauto 5.
(** %\vspace{-.15in}%
<<
Finished transaction in 2. secs (1.92012u,0.044003s)
>>
*)
(** We see worrying exponential growth in running time, and the %\index{tactics!debug}%[debug] tactical helps us see where [eauto] is wasting its time, outputting a trace of every proof step that is attempted. The rule [eq_trans] applies at every node of a proof tree, and [eauto] tries all such positions. *)
(* begin hide *)
(* begin thide *)
Definition syms := (eq_sym, plus_n_O, eq_add_S, f_equal2).
(* end thide *)
(* end hide *)
debug eauto 3.
(** [[
1 depth=3
1.1 depth=2 eapply ex_intro
1.1.1 depth=1 apply plusO
1.1.1.1 depth=0 eapply eq_trans
1.1.2 depth=1 eapply eq_trans
1.1.2.1 depth=1 apply plus_n_O
1.1.2.1.1 depth=0 apply plusO
1.1.2.1.2 depth=0 eapply eq_trans
1.1.2.2 depth=1 apply @eq_refl
1.1.2.2.1 depth=0 apply plusO
1.1.2.2.2 depth=0 eapply eq_trans
1.1.2.3 depth=1 apply eq_add_S ; trivial
1.1.2.3.1 depth=0 apply plusO
1.1.2.3.2 depth=0 eapply eq_trans
1.1.2.4 depth=1 apply eq_sym ; trivial
1.1.2.4.1 depth=0 eapply eq_trans
1.1.2.5 depth=0 apply plusO
1.1.2.6 depth=0 apply plusS
1.1.2.7 depth=0 apply f_equal (A:=nat)
1.1.2.8 depth=0 apply f_equal2 (A1:=nat) (A2:=nat)
1.1.2.9 depth=0 eapply eq_trans
]]
*)
Abort.
End slow.
(** Sometimes, though, transitivity is just what is needed to get a proof to go through automatically with [eauto]. For those cases, we can use named%\index{hint databases}% _hint databases_ to segregate hints into different groups that may be called on as needed. Here we put [eq_trans] into the database [slow]. *)
(* begin thide *)
Hint Resolve eq_trans : slow.
(* end thide *)
Example three_minus_four_zero : exists x, 1 + x = 0.
(* begin thide *)
Time eauto.
(** %\vspace{-.15in}%
<<
Finished transaction in 0. secs (0.004u,0.s)
>>
This [eauto] fails to prove the goal, but at least it takes substantially less than the 2 seconds required above! *)
Abort.
(* end thide *)
(** One simple example from before runs in the same amount of time, avoiding pollution by transitivity. *)
Example seven_minus_three_again : exists x, x + 3 = 7.
(* begin thide *)
Time eauto 6.
(** %\vspace{-.15in}%
<<
Finished transaction in 0. secs (0.004001u,0.s)
>>
%\vspace{-.2in}% *)
Qed.
(* end thide *)
(** When we _do_ need transitivity, we ask for it explicitly. *)
Example needs_trans : forall x y, 1 + x = y
-> y = 2
-> exists z, z + x = 3.
(* begin thide *)
info eauto with slow.
(** %\vspace{-.2in}%[[
== intro x; intro y; intro H; intro H0; simple eapply ex_intro;
apply plusS; simple eapply eq_trans.
exact H.
exact H0.
]]
*)
Qed.
(* end thide *)
(** The [info] trace shows that [eq_trans] was used in just the position where it is needed to complete the proof. We also see that [auto] and [eauto] always perform [intro] steps without counting them toward the bound on proof tree depth. *)
(** * Searching for Underconstrained Values *)
(** Recall the definition of the list length function. *)
Print length.
(** %\vspace{-.15in}%[[
length =
fun A : Type =>
fix length (l : list A) : nat :=
match l with
| nil => 0
| _ :: l' => S (length l')
end
]]
This function is easy to reason about in the forward direction, computing output from input. *)
Example length_1_2 : length (1 :: 2 :: nil) = 2.
auto.
Qed.
Print length_1_2.
(** %\vspace{-.15in}%[[
length_1_2 = eq_refl
]]
As in the last section, we will prove some lemmas to recast [length] in logic programming style, to help us compute inputs from outputs. *)
(* begin thide *)
Theorem length_O : forall A, length (nil (A := A)) = O.
crush.
Qed.
Theorem length_S : forall A (h : A) t n,
length t = n
-> length (h :: t) = S n.
crush.
Qed.
Hint Resolve length_O length_S.
(* end thide *)
(** Let us apply these hints to prove that a [list nat] of length 2 exists. (Here we register [length_O] with [Hint Resolve] instead of [Hint Immediate] merely as a convenience to use the same command as for [length_S]; [Resolve] and [Immediate] have the same meaning for a premise-free hint.) *)
Example length_is_2 : exists ls : list nat, length ls = 2.
(* begin thide *)
eauto.
(** <<
No more subgoals but non-instantiated existential variables:
Existential 1 = ?20249 : [ |- nat]
Existential 2 = ?20252 : [ |- nat]
>>
Coq complains that we finished the proof without determining the values of some unification variables created during proof search. The error message may seem a bit silly, since _any_ value of type [nat] (for instance, 0) can be plugged in for either variable! However, for more complex types, finding their inhabitants may be as complex as theorem-proving in general.
The %\index{Vernacular commands!Show Proof}%[Show Proof] command shows exactly which proof term [eauto] has found, with the undetermined unification variables appearing explicitly where they are used. *)
Show Proof.
(** <<
Proof: ex_intro (fun ls : list nat => length ls = 2)
(?20249 :: ?20252 :: nil)
(length_S ?20249 (?20252 :: nil)
(length_S ?20252 nil (length_O nat)))
>>
%\vspace{-.2in}% *)
Abort.
(* end thide *)
(** We see that the two unification variables stand for the two elements of the list. Indeed, list length is independent of data values. Paradoxically, we can make the proof search process easier by constraining the list further, so that proof search naturally locates appropriate data elements by unification. The library predicate [Forall] will be helpful. *)
(* begin hide *)
(* begin thide *)
Definition Forall_c := (@Forall_nil, @Forall_cons).
(* end thide *)
(* end hide *)
Print Forall.
(** %\vspace{-.15in}%[[
Inductive Forall (A : Type) (P : A -> Prop) : list A -> Prop :=
Forall_nil : Forall P nil
| Forall_cons : forall (x : A) (l : list A),
P x -> Forall P l -> Forall P (x :: l)
]]
*)
Example length_is_2 : exists ls : list nat, length ls = 2
/\ Forall (fun n => n >= 1) ls.
(* begin thide *)
eauto 9.
Qed.
(* end thide *)
(** We can see which list [eauto] found by printing the proof term. *)
(* begin hide *)
(* begin thide *)
Definition conj' := (conj, le_n).
(* end thide *)
(* end hide *)
Print length_is_2.
(** %\vspace{-.15in}%[[
length_is_2 =
ex_intro
(fun ls : list nat => length ls = 2 /\ Forall (fun n : nat => n >= 1) ls)
(1 :: 1 :: nil)
(conj (length_S 1 (1 :: nil) (length_S 1 nil (length_O nat)))
(Forall_cons 1 (le_n 1)
(Forall_cons 1 (le_n 1) (Forall_nil (fun n : nat => n >= 1)))))
]]
*)
(** Let us try one more, fancier example. First, we use a standard higher-order function to define a function for summing all data elements of a list. *)
Definition sum := fold_right plus O.
(** Another basic lemma will be helpful to guide proof search. *)
(* begin thide *)
Lemma plusO' : forall n m,
n = m
-> 0 + n = m.
crush.
Qed.
Hint Resolve plusO'.
(** Finally, we meet %\index{Vernacular commands!Hint Extern}%[Hint Extern], the command to register a custom hint. That is, we provide a pattern to match against goals during proof search. Whenever the pattern matches, a tactic (given to the right of an arrow [=>]) is attempted. Below, the number [1] gives a priority for this step. Lower priorities are tried before higher priorities, which can have a significant effect on proof search time. *)
Hint Extern 1 (sum _ = _) => simpl.
(* end thide *)
(** Now we can find a length-2 list whose sum is 0. *)
Example length_and_sum : exists ls : list nat, length ls = 2
/\ sum ls = O.
(* begin thide *)
eauto 7.
Qed.
(* end thide *)
(* begin hide *)
Print length_and_sum.
(* end hide *)
(** Printing the proof term shows the unsurprising list that is found. Here is an example where it is less obvious which list will be used. Can you guess which list [eauto] will choose? *)
Example length_and_sum' : exists ls : list nat, length ls = 5
/\ sum ls = 42.
(* begin thide *)
eauto 15.
Qed.
(* end thide *)
(* begin hide *)
Print length_and_sum'.
(* end hide *)
(** We will give away part of the answer and say that the above list is less interesting than we would like, because it contains too many zeroes. A further constraint forces a different solution for a smaller instance of the problem. *)
Example length_and_sum'' : exists ls : list nat, length ls = 2
/\ sum ls = 3
/\ Forall (fun n => n <> 0) ls.
(* begin thide *)
eauto 11.
Qed.
(* end thide *)
(* begin hide *)
Print length_and_sum''.
(* end hide *)
(** We could continue through exercises of this kind, but even more interesting than finding lists automatically is finding _programs_ automatically. *)
(** * Synthesizing Programs *)
(** Here is a simple syntax type for arithmetic expressions, similar to those we have used several times before in the book. In this case, we allow expressions to mention exactly one distinguished variable. *)
Inductive exp : Set :=
| Const : nat -> exp
| Var : exp
| Plus : exp -> exp -> exp.
(** An inductive relation specifies the semantics of an expression, relating a variable value and an expression to the expression value. *)
Inductive eval (var : nat) : exp -> nat -> Prop :=
| EvalConst : forall n, eval var (Const n) n
| EvalVar : eval var Var var
| EvalPlus : forall e1 e2 n1 n2, eval var e1 n1
-> eval var e2 n2
-> eval var (Plus e1 e2) (n1 + n2).
(* begin thide *)
Hint Constructors eval.
(* end thide *)
(** We can use [auto] to execute the semantics for specific expressions. *)
Example eval1 : forall var, eval var (Plus Var (Plus (Const 8) Var)) (var + (8 + var)).
(* begin thide *)
auto.
Qed.
(* end thide *)
(** Unfortunately, just the constructors of [eval] are not enough to prove theorems like the following, which depends on an arithmetic identity. *)
Example eval1' : forall var, eval var (Plus Var (Plus (Const 8) Var)) (2 * var + 8).
(* begin thide *)
eauto.
Abort.
(* end thide *)
(** To help prove [eval1'], we prove an alternate version of [EvalPlus] that inserts an extra equality premise. This sort of staging is helpful to get around limitations of [eauto]'s unification: [EvalPlus] as a direct hint will only match goals whose results are already expressed as additions, rather than as constants. With the alternate version below, to prove the first two premises, [eauto] is given free reign in deciding the values of [n1] and [n2], while the third premise can then be proved by [reflexivity], no matter how each of its sides is decomposed as a tree of additions. *)
(* begin thide *)
Theorem EvalPlus' : forall var e1 e2 n1 n2 n, eval var e1 n1
-> eval var e2 n2
-> n1 + n2 = n
-> eval var (Plus e1 e2) n.
crush.
Qed.
Hint Resolve EvalPlus'.
(** Further, we instruct [eauto] to apply %\index{tactics!omega}%[omega], a standard tactic that provides a complete decision procedure for quantifier-free linear arithmetic. Via [Hint Extern], we ask for use of [omega] on any equality goal. The [abstract] tactical generates a new lemma for every such successful proof, so that, in the final proof term, the lemma may be referenced in place of dropping in the full proof of the arithmetic equality. *)
Hint Extern 1 (_ = _) => abstract omega.
(* end thide *)
(** Now we can return to [eval1'] and prove it automatically. *)
Example eval1' : forall var, eval var (Plus Var (Plus (Const 8) Var)) (2 * var + 8).
(* begin thide *)
eauto.
Qed.
(* end thide *)
Print eval1'.
(** %\vspace{-.15in}%[[
eval1' =
fun var : nat =>
EvalPlus' (EvalVar var) (EvalPlus (EvalConst var 8) (EvalVar var))
(eval1'_subproof var)
: forall var : nat,
eval var (Plus Var (Plus (Const 8) Var)) (2 * var + 8)
]]
*)
(** The lemma [eval1'_subproof] was generated by [abstract omega].
Now we are ready to take advantage of logic programming's flexibility by searching for a program (arithmetic expression) that always evaluates to a particular symbolic value. *)
Example synthesize1 : exists e, forall var, eval var e (var + 7).
(* begin thide *)
eauto.
Qed.
(* end thide *)
Print synthesize1.
(** %\vspace{-.15in}%[[
synthesize1 =
ex_intro (fun e : exp => forall var : nat, eval var e (var + 7))
(Plus Var (Const 7))
(fun var : nat => EvalPlus (EvalVar var) (EvalConst var 7))
]]
*)
(** Here are two more examples showing off our program synthesis abilities. *)
Example synthesize2 : exists e, forall var, eval var e (2 * var + 8).
(* begin thide *)
eauto.
Qed.
(* end thide *)
(* begin hide *)
Print synthesize2.
(* end hide *)
Example synthesize3 : exists e, forall var, eval var e (3 * var + 42).
(* begin thide *)
eauto.
Qed.
(* end thide *)
(* begin hide *)
Print synthesize3.
(* end hide *)
(** These examples show linear expressions over the variable [var]. Any such expression is equivalent to [k * var + n] for some [k] and [n]. It is probably not so surprising that we can prove that any expression's semantics is equivalent to some such linear expression, but it is tedious to prove such a fact manually. To finish this section, we will use [eauto] to complete the proof, finding [k] and [n] values automatically.
We prove a series of lemmas and add them as hints. We have alternate [eval] constructor lemmas and some facts about arithmetic. *)
(* begin thide *)
Theorem EvalConst' : forall var n m, n = m
-> eval var (Const n) m.
crush.
Qed.
Hint Resolve EvalConst'.
Theorem zero_times : forall n m r,
r = m
-> r = 0 * n + m.
crush.
Qed.
Hint Resolve zero_times.
Theorem EvalVar' : forall var n,
var = n
-> eval var Var n.
crush.
Qed.
Hint Resolve EvalVar'.
Theorem plus_0 : forall n r,
r = n
-> r = n + 0.
crush.
Qed.
Theorem times_1 : forall n, n = 1 * n.
crush.
Qed.
Hint Resolve plus_0 times_1.
(** We finish with one more arithmetic lemma that is particularly specialized to this theorem. This fact happens to follow by the axioms of the _ring_ algebraic structure, so, since the naturals form a ring, we can use the built-in tactic %\index{tactics!ring}%[ring]. *)
Require Import Arith Ring.
Theorem combine : forall x k1 k2 n1 n2,
(k1 * x + n1) + (k2 * x + n2) = (k1 + k2) * x + (n1 + n2).
intros; ring.
Qed.
Hint Resolve combine.
(** Our choice of hints is cheating, to an extent, by telegraphing the procedure for choosing values of [k] and [n]. Nonetheless, with these lemmas in place, we achieve an automated proof without explicitly orchestrating the lemmas' composition. *)
Theorem linear : forall e, exists k, exists n,
forall var, eval var e (k * var + n).
induction e; crush; eauto.
Qed.
(* begin hide *)
Print linear.
(* end hide *)
(* end thide *)
(** By printing the proof term, it is possible to see the procedure that is used to choose the constants for each input term. *)
(** * More on [auto] Hints *)
(** Let us stop at this point and take stock of the possibilities for [auto] and [eauto] hints. Hints are contained within _hint databases_, which we have seen extended in many examples so far. When no hint database is specified, a default database is used. Hints in the default database are always used by [auto] or [eauto]. The chance to extend hint databases imperatively is important, because, in Ltac programming, we cannot create "global variables" whose values can be extended seamlessly by different modules in different source files. We have seen the advantages of hints so far, where [crush] can be defined once and for all, while still automatically applying the hints we add throughout developments. In fact, [crush] is defined in terms of [auto], which explains how we achieve this extensibility. Other user-defined tactics can take similar advantage of [auto] and [eauto].
The basic hints for [auto] and [eauto] are: %\index{Vernacular commands!Hint Immediate}%[Hint Immediate lemma], asking to try solving a goal immediately by applying a lemma and discharging any hypotheses with a single proof step each; %\index{Vernacular commands!Hint Resolve}%[Resolve lemma], which does the same but may add new premises that are themselves to be subjects of nested proof search; %\index{Vernacular commands!Hint Constructors}%[Constructors type], which acts like [Resolve] applied to every constructor of an inductive type; and %\index{Vernacular commands!Hint Unfold}%[Unfold ident], which tries unfolding [ident] when it appears at the head of a proof goal. Each of these [Hint] commands may be used with a suffix, as in [Hint Resolve lemma : my_db], to add the hint only to the specified database, so that it would only be used by, for instance, [auto with my_db]. An additional argument to [auto] specifies the maximum depth of proof trees to search in depth-first order, as in [auto 8] or [auto 8 with my_db]. The default depth is 5.
All of these [Hint] commands can be expressed with a more primitive hint kind, [Extern]. A few more examples of [Hint Extern] should illustrate more of the possibilities. *)
Theorem bool_neq : true <> false.
(* begin thide *)
auto.
(** A call to [crush] would have discharged this goal, but the default hint database for [auto] contains no hint that applies. *)
Abort.
(* begin hide *)
(* begin thide *)
Definition boool := bool.
(* end thide *)
(* end hide *)
(** It is hard to come up with a [bool]-specific hint that is not just a restatement of the theorem we mean to prove. Luckily, a simpler form suffices, by appealing to the built-in tactic %\index{tactics!congruence}%[congruence], a complete procedure for the theory of equality, uninterpreted functions, and datatype constructors. *)
Hint Extern 1 (_ <> _) => congruence.
Theorem bool_neq : true <> false.
auto.
Qed.
(* end thide *)
(** A [Hint Extern] may be implemented with the full Ltac language. This example shows a case where a hint uses a [match]. *)
Section forall_and.
Variable A : Set.
Variables P Q : A -> Prop.
Hypothesis both : forall x, P x /\ Q x.
Theorem forall_and : forall z, P z.
(* begin thide *)
crush.
(** The [crush] invocation makes no progress beyond what [intros] would have accomplished. An [auto] invocation will not apply the hypothesis [both] to prove the goal, because the conclusion of [both] does not unify with the conclusion of the goal. However, we can teach [auto] to handle this kind of goal. *)
Hint Extern 1 (P ?X) =>
match goal with
| [ H : forall x, P x /\ _ |- _ ] => apply (proj1 (H X))
end.
auto.
Qed.
(* end thide *)
(** We see that an [Extern] pattern may bind unification variables that we use in the associated tactic. The function [proj1] is from the standard library, for extracting a proof of [U] from a proof of [U /\ V]. *)
End forall_and.
(* begin hide *)
(* begin thide *)
Definition noot := (not, @eq).
(* end thide *)
(* end hide *)
(** After our success on this example, we might get more ambitious and seek to generalize the hint to all possible predicates [P].
[[
Hint Extern 1 (?P ?X) =>
match goal with
| [ H : forall x, P x /\ _ |- _ ] => apply (proj1 (H X))
end.
]]
<<
User error: Bound head variable
>>
Coq's [auto] hint databases work as tables mapping%\index{head symbol}% _head symbols_ to lists of tactics to try. Because of this, the constant head of an [Extern] pattern must be determinable statically. In our first [Extern] hint, the head symbol was [not], since [x <> y] desugars to [not (eq x y)]; and, in the second example, the head symbol was [P].
Fortunately, a more basic form of [Hint Extern] also applies. We may simply leave out the pattern to the left of the [=>], incorporating the corresponding logic into the Ltac script. *)
Hint Extern 1 =>
match goal with
| [ H : forall x, ?P x /\ _ |- ?P ?X ] => apply (proj1 (H X))
end.
(** Be forewarned that a [Hint Extern] of this kind will be applied at _every_ node of a proof tree, so an expensive Ltac script may slow proof search significantly. *)
(** * Rewrite Hints *)
(** Another dimension of extensibility with hints is rewriting with quantified equalities. We have used the associated command %\index{Vernacular commands!Hint Rewrite}%[Hint Rewrite] in many examples so far. The [crush] tactic uses these hints by calling the built-in tactic %\index{tactics!autorewrite}%[autorewrite]. Our rewrite hints have taken the form [Hint Rewrite lemma], which by default adds them to the default hint database [core]; but alternate hint databases may also be specified just as with, e.g., [Hint Resolve].
The next example shows a direct use of [autorewrite]. Note that, while [Hint Rewrite] uses a default database, [autorewrite] requires that a database be named. *)
Section autorewrite.
Variable A : Set.
Variable f : A -> A.
Hypothesis f_f : forall x, f (f x) = f x.
Hint Rewrite f_f.
Lemma f_f_f : forall x, f (f (f x)) = f x.
intros; autorewrite with core; reflexivity.
Qed.
(** There are a few ways in which [autorewrite] can lead to trouble when insufficient care is taken in choosing hints. First, the set of hints may define a nonterminating rewrite system, in which case invocations to [autorewrite] may not terminate. Second, we may add hints that "lead [autorewrite] down the wrong path." For instance: *)
Section garden_path.
Variable g : A -> A.
Hypothesis f_g : forall x, f x = g x.
Hint Rewrite f_g.
Lemma f_f_f' : forall x, f (f (f x)) = f x.
intros; autorewrite with core.
(** [[
============================
g (g (g x)) = g x
]]
*)
Abort.
(** Our new hint was used to rewrite the goal into a form where the old hint could no longer be applied. This "non-monotonicity" of rewrite hints contrasts with the situation for [auto], where new hints may slow down proof search but can never "break" old proofs. The key difference is that [auto] either solves a goal or makes no changes to it, while [autorewrite] may change goals without solving them. The situation for [eauto] is slightly more complicated, as changes to hint databases may change the proof found for a particular goal, and that proof may influence the settings of unification variables that appear elsewhere in the proof state. *)
Reset garden_path.
(** The [autorewrite] tactic also works with quantified equalities that include additional premises, but we must be careful to avoid similar incorrect rewritings. *)
Section garden_path.
Variable P : A -> Prop.
Variable g : A -> A.
Hypothesis f_g : forall x, P x -> f x = g x.
Hint Rewrite f_g.
Lemma f_f_f' : forall x, f (f (f x)) = f x.
intros; autorewrite with core.
(** [[
============================
g (g (g x)) = g x
subgoal 2 is:
P x
subgoal 3 is:
P (f x)
subgoal 4 is:
P (f x)
]]
*)
Abort.
(** The inappropriate rule fired the same three times as before, even though we know we will not be able to prove the premises. *)
Reset garden_path.
(** Our final, successful, attempt uses an extra argument to [Hint Rewrite] that specifies a tactic to apply to generated premises. Such a hint is only used when the tactic succeeds for all premises, possibly leaving further subgoals for some premises. *)
Section garden_path.
Variable P : A -> Prop.
Variable g : A -> A.
Hypothesis f_g : forall x, P x -> f x = g x.
(* begin thide *)
Hint Rewrite f_g using assumption.
(* end thide *)
Lemma f_f_f' : forall x, f (f (f x)) = f x.
(* begin thide *)
intros; autorewrite with core; reflexivity.
Qed.
(* end thide *)
(** We may still use [autorewrite] to apply [f_g] when the generated premise is among our assumptions. *)
Lemma f_f_f_g : forall x, P x -> f (f x) = g x.
(* begin thide *)
intros; autorewrite with core; reflexivity.
(* end thide *)
Qed.
End garden_path.
(** It can also be useful to apply the [autorewrite with db in *] form, which does rewriting in hypotheses, as well as in the conclusion. *)
Lemma in_star : forall x y, f (f (f (f x))) = f (f y)
-> f x = f (f (f y)).
(* begin thide *)
intros; autorewrite with core in *; assumption.
(* end thide *)
Qed.
End autorewrite.
(** Many proofs can be automated in pleasantly modular ways with deft combinations of [auto] and [autorewrite]. *)
|
`timescale 1ns/10ps
module soc_system_sdram_pll(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("100.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("143.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("143.000000 MHz"),
.phase_shift1("-3758 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
//
// Paul Gao 02/2021
//
// This is an input SDR PHY
//
// clk_i is center-aligned to data_i
// Waveform below shows the detailed behavior of the module
//
/****************************************************************************
+---+ +---+ +---+ +---+ +---+ +---+ +--+
clk_i/clk_o | | | | | | | | | | | | |
+------------+ +---+ +---+ +---+ +---+ +---+ +---+
-----------------+-------+-------+-------+-------+-------+-------
data_i D00 | D01 | D02 | D03 | D04 | D05 | D06
-----------------------------------------------------------------
-----------------------------------------------------------------
data_o D00 | D01 | D02 | D03 | D04 |
------------------------------+-------+-------+-------+-------+--
****************************************************************************/
module bsg_link_isdr_phy
#(parameter `BSG_INV_PARAM(width_p ))
(input clk_i
,output clk_o
,input [width_p-1:0] data_i
,output [width_p-1:0] data_o
);
assign clk_o = clk_i;
bsg_dff #(.width_p(width_p)) data_ff
(.clk_i(clk_i),.data_i(data_i),.data_o(data_o));
endmodule
`BSG_ABSTRACT_MODULE(bsg_link_isdr_phy)
|
`timescale 1ns/1ps
module tb;
`include "useful_tasks.v" // some helper tasks
reg rst_async_n; // asynchronous reset
reg r1,r2;
wire a0;
wire a1,a2,r0;
task handshake_4ph_port1;
input [31:0] delay;
begin
wait(a1 === 1'b0);
r1 = 1'b1;
wait(a1 === 1'b1);
#(delay);
r1 = 1'b0;
wait(a1 === 1'b0);
end
endtask
task handshake_4ph_port2;
input [31:0] delay;
begin
wait( a2 === 1'b0);
r2 = 1'b1;
wait( a2 === 1'b1);
#(delay);
r2 = 1'b0;
wait( a2 === 1'b0);
end
endtask
task handshake_4ph;
output r;
input a;
input [31:0] delay;
begin
wait( a === 1'b0);
r = 1'b1;
wait( a === 1'b1);
#(delay);
r = 1'b0;
wait( a === 1'b0);
end
endtask
task stimuli_port1;
integer i;
begin
$display("start 1");
for(i=0;i<100;i=i+1) begin
handshake_4ph_port1(($unsigned($random) % 200) + 20);
#($unsigned($random) % 200);
end
$display("stop1 ");
end
endtask
task stimuli_port2;
integer i;
begin
$display("start 2");
for(i=0;i<100;i=i+1) begin
handshake_4ph_port2(($unsigned($random) % 200) + 20);
#($unsigned($random) % 200);
end
$display("stop 2");
end
endtask
arbitrer_r1_4ph U_ARBITER(
.a1(a1),
.a2(a2),
.r1(r1),
.r2(r2),
.a0(a0),
.r0(r0),
.rstn(rst_async_n)
);
assign #12 a0 = r0;
// Dump all nets to a vcd file called tb.vcd
event dbg_finish;
reg clk;
initial clk = 0;
always
#100 clk = ~clk;
initial
begin
$dumpfile("tb.vcd");
$dumpvars(0,tb);
end
// Start by pulsing the reset low for some nanoseconds
initial begin
rst_async_n = 1'b0;
r1 <= 0;
r2 <= 0;
#5;
rst_async_n = 1'b1;
$display("-I- Reset is released");
#10;
$display("-I- step 1");
r1 <= 1;
@(posedge a1);
r1 <= 0;
@(negedge a1);
#10;
$display("-I- step 2");
r2 <= 1;
@(posedge a2);
r2 <= 0;
@(negedge a2);
#10;
$display("-I- step 3");
#10 handshake_4ph_port2(300);
#200;
#10 handshake_4ph_port1(100);
#200;
$display("-I- step 5");
handshake_4ph_port2(20);
#10;
-> dbg_finish;
fork
stimuli_port1();
stimuli_port2();
join
$display("-I- Done !");
$finish;
end
four_phase_assertion U_CHECKER0(.req(r0),.ack(a0),.rstn(rst_async_n));
four_phase_assertion U_CHECKER1(.req(r1),.ack(a1),.rstn(rst_async_n));
four_phase_assertion U_CHECKER2(.req(r2),.ack(a2),.rstn(rst_async_n));
endmodule // tb
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// ALTERA Confidential and Proprietary
// Copyright 2007 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
`timescale 1ps/1ps
module altera_tse_fake_master(
// Clock and reset
input clk,
input reset,
// Avalon MM master interface
output [8:0] phy_mgmt_address,
output phy_mgmt_read,
input [31:0] phy_mgmt_readdata,
output phy_mgmt_write,
output reg [31:0] phy_mgmt_writedata,
input phy_mgmt_waitrequest,
// Serial data loopback control
input sd_loopback
);
//////////////////////////////////internal registers and paramaters//////////////////////////////////
reg [1:0] state;
reg [1:0] next_state;
reg sd_loopback_r1, sd_loopback_r2;
reg bit_event;
localparam IDLE = 2'b0 ;
localparam WRITE_DATA = 2'b1;
////////////////////to detect the toggled data from sd_loopback //////////
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
sd_loopback_r1 <= 1'b0;
sd_loopback_r2 <= 1'b0;
end
else
begin
sd_loopback_r2 <= sd_loopback_r1;
sd_loopback_r1 <= sd_loopback;
end
end
// bit_event is the bit to remember there is an event happening at the sd_loopback
// and used to trigger IDLE -> WRITE_DATA state transition
// This bit is only cleared during WRITE_DATA -> IDLE transition and make sure that
// phy_mgmt_writedata[0] value is equal to sd_loopback data
// This is to ensure that our Avalon MM write transaction is always in sync with sd_loopback value
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bit_event <= 0;
end
else
begin
if ( sd_loopback_r1 != sd_loopback_r2)
begin
bit_event <= 1'b1;
end
else
begin
if (next_state == IDLE && state == WRITE_DATA && phy_mgmt_writedata[0] == sd_loopback)
begin
bit_event <= 1'b0;
end
end
end
end
// State machine
always @ (posedge clk or posedge reset)
begin
if (reset)
state <= IDLE;
else
state <= next_state;
end
// next_state logic
always @ (*)
begin
case (state)
IDLE:
begin
if (bit_event)
next_state = WRITE_DATA;
else
next_state = IDLE;
end
WRITE_DATA:
begin
if (!phy_mgmt_waitrequest)
next_state = IDLE;
else
next_state = WRITE_DATA;
end
default : next_state = IDLE;
endcase
end
// Connection to PHYIP (Avalon MM master signals)
assign phy_mgmt_write = (state == WRITE_DATA)? 1'b1 : 1'b0;
assign phy_mgmt_read = 1'b0;
assign phy_mgmt_address = (state == WRITE_DATA) ? 9'h61 : 9'h0;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
phy_mgmt_writedata <= 32'b0;
end
else
begin
if (state == IDLE && next_state == WRITE_DATA)
begin
phy_mgmt_writedata <= {31'b0, sd_loopback};
end
else if (state == WRITE_DATA && next_state == IDLE)
begin
phy_mgmt_writedata <= 32'b0;
end
end
end
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_CH0_YN1_U (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 13: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 13: 0] d1_data_in;
reg [ 13: 0] d2_data_in;
wire [ 13: 0] data_in;
reg [ 13: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 13: 0] edge_detect;
wire [ 13: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({14 {(address == 0)}} & data_in) |
({14 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[4] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[4] <= 0;
else if (edge_detect[4])
edge_capture[4] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[5] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[5] <= 0;
else if (edge_detect[5])
edge_capture[5] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[6] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[6] <= 0;
else if (edge_detect[6])
edge_capture[6] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[7] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[7] <= 0;
else if (edge_detect[7])
edge_capture[7] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[8] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[8] <= 0;
else if (edge_detect[8])
edge_capture[8] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[9] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[9] <= 0;
else if (edge_detect[9])
edge_capture[9] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[10] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[10] <= 0;
else if (edge_detect[10])
edge_capture[10] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[11] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[11] <= 0;
else if (edge_detect[11])
edge_capture[11] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[12] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[12] <= 0;
else if (edge_detect[12])
edge_capture[12] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[13] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[13] <= 0;
else if (edge_detect[13])
edge_capture[13] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in & ~d2_data_in;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:01:00 04/23/2015
// Design Name:
// Module Name: modBigNumbers
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module modBigNumbers(input reset, input clk, input [63:0] exponent, input [31:0] number,
output reg [31:0] result, output reg isDone
);
reg [31:0] nextResult;
reg [31:0] dividend;
reg nextIsDone;
reg [12:0] bitIndex;
reg [12:0] nextBitIndex;
reg [31:0] nextDividend;
wire [31:0] remainder;
wire [31:0] quotient;
wire [31:0] memMod;
wire rfd;
initial begin
nextIsDone = 0;
isDone = 0;
bitIndex = 0;
nextBitIndex = 0;
dividend = 1;
nextDividend = 1;
result = 0;
nextResult = 0;
end
div_gen_v3_0 dviderModule (.clk(clk),.rfd(rfd),.dividend(dividend),.divisor(number), .quotient(quotient), .fractional(remainder));
always @(posedge clk) begin
result <= nextResult;
isDone <= nextIsDone;
bitIndex <= nextBitIndex;
dividend <= nextDividend;
end
always @(*) begin
if (rfd == 1) begin
nextBitIndex = bitIndex < 64 ? bitIndex + 1 : bitIndex;
if (bitIndex == 64) begin
if (reset == 1) begin
nextIsDone = 0;
nextBitIndex = 0;
nextDividend = 1;
nextResult = 0;
end
else begin
nextIsDone = 1;
nextDividend = dividend;
nextResult = remainder;
end
end
else begin
nextResult = result;
nextIsDone = 0;
if (exponent[bitIndex] == 1) begin
nextDividend = remainder * memMod;
end
else begin
nextDividend = dividend;
end
end
end
else begin
nextBitIndex = bitIndex;
nextDividend = dividend;
nextResult = result;
nextIsDone = isDone;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_MUX_4TO2_BLACKBOX_V
`define SKY130_FD_SC_HDLL__UDP_MUX_4TO2_BLACKBOX_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_mux_4to2 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_MUX_4TO2_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 27.11.2014 14:15:43
// Design Name:
// Module Name:
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ([email protected])
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
module red_pitaya_iq_demodulator_block #(
parameter INBITS = 14,
parameter OUTBITS = 18,
parameter SINBITS = 14,
parameter SHIFTBITS = 1
// why SHIFTBITS SHOULD ALWAYS BE 1:
// the sin from fgen ranges from -2**(SINBITS-1)+1 to 2**(SINBITS-1)-1
// i.e. the strange number is excluded by definition. Including the
// strange number -2**(SINBITS-1), the product signal_i * sin / cos
// would be maximally
// 2**(SINBITS+INBITS-1-1). That is, including the sign bit it would
// occupy SINBITS+INBITS-1 bits. Excluding the strange number of the sin
// factor makes the maximum less than that, i.e. we can safely represent
// the product with SINBITS+INBITS-2 bits, including the sign bit.
// That makes SHIFTBITS = -1 (see below). OUTBITS only determines how many
// LSB's we cut off.
)
(
input clk_i,
input signed [SINBITS-1:0] sin,
input signed [SINBITS-1:0] cos,
input signed [INBITS-1:0] signal_i,
output signed [OUTBITS-1:0] signal1_o,
output signed [OUTBITS-1:0] signal2_o
);
reg signed [INBITS-1:0] firstproduct_reg;
always @(posedge clk_i) begin
firstproduct_reg <= signal_i;
end
reg signed [SINBITS+INBITS-1:0] product1;
reg signed [SINBITS+INBITS-1:0] product2;
// soft implementation of symmetric rounding
//wire signed [SINBITS+INBITS-1:0] product1_unrounded;
//wire signed [SINBITS+INBITS-1:0] product2_unrounded;
//assign product1_unrounded = firstproduct_reg * sin;
//assign product2_unrounded = firstproduct_reg * cos;
//wire signed [SINBITS+INBITS-1:0] product1_roundoffset;
//wire signed [SINBITS+INBITS-1:0] product2_roundoffset;
//assign product1_roundoffset = (product1_unrounded[SINBITS+INBITS-1]) ? {{(OUTBITS+SHIFTBITS+1){1'b0}},{1'b1},{(SINBITS+INBITS-OUTBITS-SHIFTBITS-2){1'b0}}}
// : {{(OUTBITS+SHIFTBITS+1){1'b0}},{1'b0},{(SINBITS+INBITS-OUTBITS-SHIFTBITS-2){1'b1}}};
//
//assign product2_roundoffset = (product2_unrounded[SINBITS+INBITS-1]) ? {{(OUTBITS+SHIFTBITS+1){1'b0}},{1'b1},{(SINBITS+INBITS-OUTBITS-SHIFTBITS-2){1'b0}}}
// : {{(OUTBITS+SHIFTBITS+1){1'b0}},{1'b0},{(SINBITS+INBITS-OUTBITS-SHIFTBITS-2){1'b1}}};
// after some problems, we choose asymmetric rounding for now - at least
// some rounding
always @(posedge clk_i) begin
// product1 <= product1_unrounded + product1_roundoffset;
// product2 <= product2_unrounded + product2_roundoffset;
product1 <= firstproduct_reg * sin + $signed(1 << (SINBITS+INBITS-OUTBITS-SHIFTBITS-1));
product2 <= firstproduct_reg * cos + $signed(1 << (SINBITS+INBITS-OUTBITS-SHIFTBITS-1));
end
assign signal1_o = product1[SINBITS+INBITS-1-SHIFTBITS:SINBITS+INBITS-OUTBITS-SHIFTBITS];
assign signal2_o = product2[SINBITS+INBITS-1-SHIFTBITS:SINBITS+INBITS-OUTBITS-SHIFTBITS];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD2_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DLYGATE4SD2_FUNCTIONAL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__dlygate4sd2 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD2_FUNCTIONAL_V |
module voice(clk, gate, note, pitch, lfo_sig, lfo_depth, lfo_depth_fine, wave_form, signal_out);
input wire clk;
input wire gate;
input wire [6:0] note;
input wire [7:0] lfo_sig;
input wire [6:0] lfo_depth;
input wire [6:0] lfo_depth_fine;
input wire [13:0] pitch;
output wire [7:0] signal_out;
//input wire [31:0] adder;
input wire [2:0] wave_form;
// wave_forms
parameter SAW = 3'b000;
parameter SQUARE = 3'b001; //with PWM
parameter TRIANGLE = 3'b010;
parameter SINE = 3'b011;
parameter RAMP = 3'b100;
parameter SAW_TRI = 3'b101;
parameter NOISE = 3'b110;
parameter UNDEF = 3'b111;
wire [31:0] adder_center;
note_pitch2dds transl1(.clk(clk), .note(note), .pitch(pitch), .lfo_sig(lfo_sig), .lfo_depth(lfo_depth), .lfo_depth_fine(lfo_depth_fine), .adder(adder_center));
wire [31:0] vco_out;
dds #(.WIDTH(32)) vco(.clk(clk), .adder(adder_center), .signal_out(vco_out));
wire [7:0] saw_out = vco_out[31:31-7];
wire [7:0] square_out = (vco_out[31:31-7] > 127) ? 8'b11111111 : 1'b00000000;
wire [7:0] tri_out = (saw_out>8'd191) ? 7'd127 + ((saw_out << 1) - 9'd511) :
(saw_out>8'd063) ? 8'd255 - ((saw_out << 1) - 7'd127) : 7'd127 + (saw_out << 1);
//SINE table
wire [7:0] sine_out;
sine sine_rom(.address(vco_out[31:31-7]),
.q(sine_out),
.clock(clk));
wire [7:0] ramp_out = -saw_out;
wire [7:0] saw_tri_out = (saw_out > 7'd127) ? -saw_out : 8'd127 + saw_out;
//noise
reg [7:0] noise_reg;
wire [7:0] noise_out = noise_reg;
wire [7:0] noise_sig;
//16000 hz GENERATOR
wire clk16000;
frq1divmod1 divider1(clk, 25'd1563, clk16000); //50000000 / 16000 / 2 = 1563
reg [1:0] clk16000_prev=2'b00;
always @(posedge clk) clk16000_prev <= {clk16000_prev[0], clk16000};
wire clk16000_posege = (clk16000_prev==2'b01);
rndx #(.WIDTH(8)) random8(.clk(clk), .signal_out(noise_sig));
always @(posedge clk) begin
if (clk16000_posege) begin
noise_reg <= noise_sig;
end
end
//signal_out
assign signal_out = (wave_form == SAW) ? saw_out :
(wave_form == SQUARE) ? square_out :
(wave_form == TRIANGLE) ? tri_out :
(wave_form == SINE) ? sine_out :
(wave_form == RAMP) ? ramp_out :
(wave_form == SAW_TRI) ? saw_tri_out :
(wave_form == NOISE) ? noise_out : 8'd127;
endmodule
|
/*
########################################################################
MASTER ENABLE, CLOCKS, CHIP-ID
########################################################################
*/
`include "elink_regmap.v"
module ecfg_elink (/*AUTOARG*/
// Outputs
txwr_gated_access, etx_soft_reset, erx_soft_reset, clk_config,
chipid,
// Inputs
clk, por_reset, txwr_access, txwr_packet
);
parameter RFAW = 6; // 32 registers for now
parameter PW = 104; // 32 registers for now
parameter ID = 12'h000;
parameter DEFAULT_CHIPID = 12'h808;
/******************************/
/*Clock/reset */
/******************************/
input clk;
input por_reset; // POR "hard reset"
/******************************/
/*REGISTER ACCESS */
/******************************/
input txwr_access;
input [PW-1:0] txwr_packet;
/******************************/
/*FILTERED WRITE FOR TX FIFO */
/******************************/
output txwr_gated_access;
/******************************/
/*Outputs */
/******************************/
output etx_soft_reset; // tx soft reset (level)
output erx_soft_reset; // rx soft reset (level)
output [15:0] clk_config; // clock settings (for pll)
output [11:0] chipid; // chip-id for Epiphany
/*------------------------CODE BODY---------------------------------------*/
//registers
reg [1:0] ecfg_reset_reg;
reg [15:0] ecfg_clk_reg;
reg [11:0] ecfg_chipid_reg;
reg [31:0] mi_dout;
//wires
wire ecfg_read;
wire ecfg_write;
wire ecfg_clk_write;
wire ecfg_chipid_write;
wire ecfg_reset_write;
wire mi_en;
wire [31:0] mi_addr;
wire [31:0] mi_din;
packet2emesh pe2 (
// Outputs
.access_out (),
.write_out (mi_we),
.datamode_out (),
.ctrlmode_out (),
.dstaddr_out (mi_addr[31:0]),
.data_out (mi_din[31:0]),
.srcaddr_out (),
// Inputs
.packet_in (txwr_packet[PW-1:0])
);
/*****************************/
/*ADDRESS DECODE LOGIC */
/*****************************/
assign mi_en = txwr_access &
(mi_addr[31:20]==ID) &
(mi_addr[10:8]==3'h2);
//read/write decode
assign ecfg_write = mi_en & mi_we;
assign ecfg_read = mi_en & ~mi_we;
//Config write enables
assign ecfg_reset_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_RESET);
assign ecfg_clk_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_CLK);
assign ecfg_chipid_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_CHIPID);
/*****************************/
/*FILTER ACCESS */
/*****************************/
assign txwr_gated_access = txwr_access & ~(ecfg_reset_write |
ecfg_clk_write |
ecfg_chipid_write);
//###########################
//# RESET REG (ASYNC)
//###########################
always @ (posedge clk or posedge por_reset)
if(por_reset)
ecfg_reset_reg[1:0] <= 'b0;
else if (ecfg_reset_write)
ecfg_reset_reg[1:0] <= mi_din[1:0];
assign etx_soft_reset = ecfg_reset_reg[0];
assign erx_soft_reset = ecfg_reset_reg[1];
//###########################
//# CCLK/LCLK (PLL)
//###########################
//TODO: implement!
always @ (posedge clk or posedge por_reset)
if(por_reset)
ecfg_clk_reg[15:0] <= 16'h573;//all clocks on at lowest speed
else if (ecfg_clk_write)
ecfg_clk_reg[15:0] <= mi_din[15:0];
assign clk_config[15:0] = ecfg_clk_reg[15:0];
//###########################
//# CHIPID
//###########################
always @ (posedge clk or posedge por_reset)
if(por_reset)
ecfg_chipid_reg[11:0] <= DEFAULT_CHIPID;
else if (ecfg_chipid_write)
ecfg_chipid_reg[11:0] <= mi_din[11:0];
assign chipid[11:0]=ecfg_chipid_reg[5:2];
endmodule // ecfg_elink
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
//-----------------------------------------------------------------------------------
//--RAM.v----------------------------------------------------------------------------
//--By Kyle Williams, 11/20/2012-----------------------------------------------------
//--MODULE DESCRIPTION---------------------------------------------------------------
//----------------Simple Dual Port Ram used to store data--------------------------
//----------------reset is not required ram can be filled with useless data----------
module Ram
#(
parameter ADDR_WIDTH = 4,
parameter DATA_WIDTH = 8,
parameter MEM_DEPTH = 64
)(
//------------Input Ports------------
input clk,
input[ADDR_WIDTH-1:0] addrA,
input[ADDR_WIDTH-1:0] addrB,
input wr_enaA,
input wr_enaB,
input[DATA_WIDTH-1:0] ram_inA,
input[DATA_WIDTH-1:0] ram_inB,
//------------Output Ports-----------
output reg[DATA_WIDTH-1:0] ram_outA,
output reg[DATA_WIDTH-1:0] ram_outB
);
//------------Reg/ Wires-------------
reg [DATA_WIDTH-1:0] mem [0:MEM_DEPTH-1];
always@(posedge clk)
begin:Port_One
if(wr_enaA == 1'b1)
begin:MEM_WRITE
mem[addrA] <= ram_inA;
end
//MEM_READ
ram_outA <= mem[addrA];
end
always@(posedge clk)
begin:Port_Two
if(wr_enaB == 1'b1)
begin:MEM_WRITE
mem[addrB] <= ram_inB;
end
//MEM_READ
ram_outB <= mem[addrB];
end
endmodule |
(** * Types: Type Systems *)
Require Export Smallstep.
Hint Constructors multi.
(** Our next major topic is _type systems_ -- static program
analyses that classify expressions according to the "shapes" of
their results. We'll begin with a typed version of a very simple
language with just booleans and numbers, to introduce the basic
ideas of types, typing rules, and the fundamental theorems about
type systems: _type preservation_ and _progress_. Then we'll move
on to the _simply typed lambda-calculus_, which lives at the core
of every modern functional programming language (including
Coq). *)
(* ###################################################################### *)
(** * Typed Arithmetic Expressions *)
(** To motivate the discussion of type systems, let's begin as
usual with an extremely simple toy language. We want it to have
the potential for programs "going wrong" because of runtime type
errors, so we need something a tiny bit more complex than the
language of constants and addition that we used in chapter
[Smallstep]: a single kind of data (just numbers) is too simple,
but just two kinds (numbers and booleans) already gives us enough
material to tell an interesting story.
The language definition is completely routine. *)
(* ###################################################################### *)
(** ** Syntax *)
(** Informally:
t ::= true
| false
| if t then t else t
| 0
| succ t
| pred t
| iszero t
Formally:
*)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm
| tzero : tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tiszero : tm -> tm.
(** _Values_ are [true], [false], and numeric values... *)
Inductive bvalue : tm -> Prop :=
| bv_true : bvalue ttrue
| bv_false : bvalue tfalse.
Inductive nvalue : tm -> Prop :=
| nv_zero : nvalue tzero
| nv_succ : forall t, nvalue t -> nvalue (tsucc t).
Definition value (t:tm) := bvalue t \/ nvalue t.
Hint Constructors bvalue nvalue.
Hint Unfold value.
Hint Unfold extend.
(* ###################################################################### *)
(** ** Operational Semantics *)
(** Informally: *)
(**
------------------------------ (ST_IfTrue)
if true then t1 else t2 ==> t1
------------------------------- (ST_IfFalse)
if false then t1 else t2 ==> t2
t1 ==> t1'
------------------------- (ST_If)
if t1 then t2 else t3 ==>
if t1' then t2 else t3
t1 ==> t1'
-------------------- (ST_Succ)
succ t1 ==> succ t1'
------------ (ST_PredZero)
pred 0 ==> 0
numeric value v1
--------------------- (ST_PredSucc)
pred (succ v1) ==> v1
t1 ==> t1'
-------------------- (ST_Pred)
pred t1 ==> pred t1'
----------------- (ST_IszeroZero)
iszero 0 ==> true
numeric value v1
-------------------------- (ST_IszeroSucc)
iszero (succ v1) ==> false
t1 ==> t1'
------------------------ (ST_Iszero)
iszero t1 ==> iszero t1'
*)
(** Formally: *)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
| ST_Succ : forall t1 t1',
t1 ==> t1' ->
(tsucc t1) ==> (tsucc t1')
| ST_PredZero :
(tpred tzero) ==> tzero
| ST_PredSucc : forall t1,
nvalue t1 ->
(tpred (tsucc t1)) ==> t1
| ST_Pred : forall t1 t1',
t1 ==> t1' ->
(tpred t1) ==> (tpred t1')
| ST_IszeroZero :
(tiszero tzero) ==> ttrue
| ST_IszeroSucc : forall t1,
nvalue t1 ->
(tiszero (tsucc t1)) ==> tfalse
| ST_Iszero : forall t1 t1',
t1 ==> t1' ->
(tiszero t1) ==> (tiszero t1')
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If"
| Case_aux c "ST_Succ" | Case_aux c "ST_PredZero"
| Case_aux c "ST_PredSucc" | Case_aux c "ST_Pred"
| Case_aux c "ST_IszeroZero" | Case_aux c "ST_IszeroSucc"
| Case_aux c "ST_Iszero" ].
Hint Constructors step.
(** Notice that the [step] relation doesn't care about whether
expressions make global sense -- it just checks that the operation
in the _next_ reduction step is being applied to the right kinds
of operands.
For example, the term [succ true] (i.e., [tsucc ttrue] in the
formal syntax) cannot take a step, but the almost as obviously
nonsensical term
succ (if true then true else true)
can take a step (once, before becoming stuck). *)
(* ###################################################################### *)
(** ** Normal Forms and Values *)
(** The first interesting thing about the [step] relation in this
language is that the strong progress theorem from the Smallstep
chapter fails! That is, there are terms that are normal
forms (they can't take a step) but not values (because we have not
included them in our definition of possible "results of
evaluation"). Such terms are _stuck_. *)
Notation step_normal_form := (normal_form step).
Definition stuck (t:tm) : Prop :=
step_normal_form t /\ ~ value t.
Hint Unfold stuck.
(** **** Exercise: 2 stars (some_term_is_stuck) *)
Example some_term_is_stuck :
exists t, stuck t.
Proof.
exists (tiszero ttrue).
unfold stuck; split.
Case "In normal form".
unfold normal_form.
unfold not; intros.
solve by inversion 3.
Case "Not a value".
unfold not; intros.
inversion H; solve by inversion.
Qed.
(** [] *)
(** However, although values and normal forms are not the same in this
language, the former set is included in the latter. This is
important because it shows we did not accidentally define things
so that some value could still take a step. *)
(** **** Exercise: 3 stars, advanced (value_is_nf) *)
(** Hint: You will reach a point in this proof where you need to
use an induction to reason about a term that is known to be a
numeric value. This induction can be performed either over the
term itself or over the evidence that it is a numeric value. The
proof goes through in either case, but you will find that one way
is quite a bit shorter than the other. For the sake of the
exercise, try to complete the proof both ways. *)
Lemma value_is_nf : forall t,
value t -> step_normal_form t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (step_deterministic) *)
(** Using [value_is_nf], we can show that the [step] relation is
also deterministic... *)
Theorem step_deterministic:
deterministic step.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Typing *)
(** The next critical observation about this language is that,
although there are stuck terms, they are all "nonsensical", mixing
booleans and numbers in a way that we don't even _want_ to have a
meaning. We can easily exclude such ill-typed terms by defining a
_typing relation_ that relates terms to the types (either numeric
or boolean) of their final results. *)
Inductive ty : Type :=
| TBool : ty
| TNat : ty.
(** In informal notation, the typing relation is often written
[|- t \in T], pronounced "[t] has type [T]." The [|-] symbol is
called a "turnstile". (Below, we're going to see richer typing
relations where an additional "context" argument is written to the
left of the turnstile. Here, the context is always empty.) *)
(**
---------------- (T_True)
|- true \in Bool
----------------- (T_False)
|- false \in Bool
|- t1 \in Bool |- t2 \in T |- t3 \in T
-------------------------------------------- (T_If)
|- if t1 then t2 else t3 \in T
------------ (T_Zero)
|- 0 \in Nat
|- t1 \in Nat
------------------ (T_Succ)
|- succ t1 \in Nat
|- t1 \in Nat
------------------ (T_Pred)
|- pred t1 \in Nat
|- t1 \in Nat
--------------------- (T_IsZero)
|- iszero t1 \in Bool
*)
Reserved Notation "'|-' t '\in' T" (at level 40).
Inductive has_type : tm -> ty -> Prop :=
| T_True :
|- ttrue \in TBool
| T_False :
|- tfalse \in TBool
| T_If : forall t1 t2 t3 T,
|- t1 \in TBool ->
|- t2 \in T ->
|- t3 \in T ->
|- tif t1 t2 t3 \in T
| T_Zero :
|- tzero \in TNat
| T_Succ : forall t1,
|- t1 \in TNat ->
|- tsucc t1 \in TNat
| T_Pred : forall t1,
|- t1 \in TNat ->
|- tpred t1 \in TNat
| T_Iszero : forall t1,
|- t1 \in TNat ->
|- tiszero t1 \in TBool
where "'|-' t '\in' T" := (has_type t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_True" | Case_aux c "T_False" | Case_aux c "T_If"
| Case_aux c "T_Zero" | Case_aux c "T_Succ" | Case_aux c "T_Pred"
| Case_aux c "T_Iszero" ].
Hint Constructors has_type.
(* ###################################################################### *)
(** *** Examples *)
(** It's important to realize that the typing relation is a
_conservative_ (or _static_) approximation: it does not calculate
the type of the normal form of a term. *)
Example has_type_1 :
|- tif tfalse tzero (tsucc tzero) \in TNat.
Proof.
apply T_If.
apply T_False.
apply T_Zero.
apply T_Succ.
apply T_Zero.
Qed.
(** (Since we've included all the constructors of the typing relation
in the hint database, the [auto] tactic can actually find this
proof automatically.) *)
Example has_type_not :
~ (|- tif tfalse tzero ttrue \in TBool).
Proof.
intros Contra. solve by inversion 2. Qed.
(** **** Exercise: 1 star, optional (succ_hastype_nat__hastype_nat) *)
Example succ_hastype_nat__hastype_nat : forall t,
|- tsucc t \in TNat ->
|- t \in TNat.
Proof.
intros.
inversion H. assumption.
Qed.
(** [] *)
(* ###################################################################### *)
(** ** Canonical forms *)
(** The following two lemmas capture the basic property that defines
the shape of well-typed values. They say that the definition of value
and the typing relation agree. *)
Lemma bool_canonical : forall t,
|- t \in TBool -> value t -> bvalue t.
Proof.
intros t HT HV.
inversion HV; auto.
induction H; inversion HT; auto.
Qed.
Lemma nat_canonical : forall t,
|- t \in TNat -> value t -> nvalue t.
Proof.
intros t HT HV.
inversion HV.
inversion H; subst; inversion HT.
auto.
Qed.
(* ###################################################################### *)
(** ** Progress *)
(** The typing relation enjoys two critical properties. The first is
that well-typed normal forms are values (i.e., not stuck). *)
Theorem progress : forall t T,
|- t \in T ->
value t \/ exists t', t ==> t'.
(** **** Exercise: 3 stars (finish_progress) *)
(** Complete the formal proof of the [progress] property. (Make sure
you understand the informal proof fragment in the following
exercise before starting -- this will save you a lot of time.) *)
Proof with auto.
intros t T HT.
has_type_cases (induction HT) Case...
(* The cases that were obviously values, like T_True and
T_False, were eliminated immediately by auto *)
Case "T_If".
right. inversion IHHT1; clear IHHT1.
SCase "t1 is a value".
apply (bool_canonical t1 HT1) in H.
inversion H; subst; clear H.
exists t2...
exists t3...
SCase "t1 can take a step".
inversion H as [t1' H1].
exists (tif t1' t2 t3)...
Case "T_Succ".
inversion IHHT as [Ht1Value | Ht1Step].
SCase "t1 is a value".
left.
apply (nat_canonical t1 HT) in Ht1Value.
unfold value. right.
apply nv_succ. assumption.
SCase "t1 can take a step".
right.
inversion Ht1Step.
exists (tsucc x).
apply ST_Succ. assumption.
Case "T_Pred".
inversion IHHT as [Ht1Value | Ht1Step].
SCase "t1 is a value".
left.
apply (nat_canonical t1 HT) in Ht1Value.
unfold value. right.
inversion Ht1Value.
admit. admit.
SCase "t1 can take a step".
right.
inversion Ht1Step.
exists (tpred x).
apply ST_Pred. assumption.
Case "T_Iszero".
inversion IHHT as [Ht1Value | Ht1Step].
SCase "t1 is a value".
left.
unfold value. left.
apply (nat_canonical t1 HT) in Ht1Value.
inversion Ht1Value.
admit. admit.
SCase "t1 can take a step".
right.
inversion Ht1Step.
exists (tiszero x).
apply ST_Iszero. assumption.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (finish_progress_informal) *)
(** Complete the corresponding informal proof: *)
(** _Theorem_: If [|- t \in T], then either [t] is a value or else
[t ==> t'] for some [t']. *)
(** _Proof_: By induction on a derivation of [|- t \in T].
- If the last rule in the derivation is [T_If], then [t = if t1
then t2 else t3], with [|- t1 \in Bool], [|- t2 \in T] and [|- t3
\in T]. By the IH, either [t1] is a value or else [t1] can step
to some [t1'].
- If [t1] is a value, then by the canonical forms lemmas
and the fact that [|- t1 \in Bool] we have that [t1]
is a [bvalue] -- i.e., it is either [true] or [false].
If [t1 = true], then [t] steps to [t2] by [ST_IfTrue],
while if [t1 = false], then [t] steps to [t3] by
[ST_IfFalse]. Either way, [t] can step, which is what
we wanted to show.
- If [t1] itself can take a step, then, by [ST_If], so can
[t].
(* FILL IN HERE *)
[] *)
(** This is more interesting than the strong progress theorem that we
saw in the Smallstep chapter, where _all_ normal forms were
values. Here, a term can be stuck, but only if it is ill
typed. *)
(** **** Exercise: 1 star (step_review) *)
(** Quick review. Answer _true_ or _false_. In this language...
- Every well-typed normal form is a value. True
- Every value is a normal form. True
- The single-step evaluation relation is
a partial function (i.e., it is deterministic). True
- The single-step evaluation relation is a _total_ function. False
*)
(** [] *)
(* ###################################################################### *)
(** ** Type Preservation *)
(** The second critical property of typing is that, when a well-typed
term takes a step, the result is also a well-typed term.
This theorem is often called the _subject reduction_ property,
because it tells us what happens when the "subject" of the typing
relation is reduced. This terminology comes from thinking of
typing statements as sentences, where the term is the subject and
the type is the predicate. *)
Theorem preservation : forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T.
(** **** Exercise: 2 stars (finish_preservation) *)
(** Complete the formal proof of the [preservation] property. (Again,
make sure you understand the informal proof fragment in the
following exercise first.) *)
Proof with auto.
intros t t' T HT HE.
generalize dependent t'.
has_type_cases (induction HT) Case;
(* every case needs to introduce a couple of things *)
intros t' HE;
(* and we can deal with several impossible
cases all at once *)
try (solve by inversion).
Case "T_If". inversion HE; subst; clear HE.
SCase "ST_IFTrue". assumption.
SCase "ST_IfFalse". assumption.
SCase "ST_If". apply T_If; try assumption.
apply IHHT1; assumption.
Case "T_Succ". inversion HE; subst.
apply T_Succ. apply IHHT in H0. assumption.
Case "T_Pred". inversion HE; subst.
SCase "ST_PredZero". apply T_Zero.
SCase "ST_PredSucc". admit.
SCase "ST_Pred".
apply IHHT in H0.
apply T_Pred.
assumption.
Case "T_Iszero".
Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (finish_preservation_informal) *)
(** Complete the following proof: *)
(** _Theorem_: If [|- t \in T] and [t ==> t'], then [|- t' \in T]. *)
(** _Proof_: By induction on a derivation of [|- t \in T].
- If the last rule in the derivation is [T_If], then [t = if t1
then t2 else t3], with [|- t1 \in Bool], [|- t2 \in T] and [|- t3
\in T].
Inspecting the rules for the small-step reduction relation and
remembering that [t] has the form [if ...], we see that the
only ones that could have been used to prove [t ==> t'] are
[ST_IfTrue], [ST_IfFalse], or [ST_If].
- If the last rule was [ST_IfTrue], then [t' = t2]. But we
know that [|- t2 \in T], so we are done.
- If the last rule was [ST_IfFalse], then [t' = t3]. But we
know that [|- t3 \in T], so we are done.
- If the last rule was [ST_If], then [t' = if t1' then t2
else t3], where [t1 ==> t1']. We know [|- t1 \in Bool] so,
by the IH, [|- t1' \in Bool]. The [T_If] rule then gives us
[|- if t1' then t2 else t3 \in T], as required.
(* FILL IN HERE *)
[] *)
(** **** Exercise: 3 stars (preservation_alternate_proof) *)
(** Now prove the same property again by induction on the
_evaluation_ derivation instead of on the typing derivation.
Begin by carefully reading and thinking about the first few
lines of the above proof to make sure you understand what
each one is doing. The set-up for this proof is similar, but
not exactly the same. *)
Theorem preservation' : forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Type Soundness *)
(** Putting progress and preservation together, we can see that a
well-typed term can _never_ reach a stuck state. *)
Definition multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Corollary soundness : forall t t' T,
|- t \in T ->
t ==>* t' ->
~(stuck t').
Proof.
intros t t' T HT P. induction P; intros [R S].
destruct (progress x T HT); auto.
apply IHP. apply (preservation x y T HT H).
unfold stuck. split; auto. Qed.
(* ###################################################################### *)
(** * Aside: the [normalize] Tactic *)
(** When experimenting with definitions of programming languages in
Coq, we often want to see what a particular concrete term steps
to -- i.e., we want to find proofs for goals of the form [t ==>*
t'], where [t] is a completely concrete term and [t'] is unknown.
These proofs are simple but repetitive to do by hand. Consider for
example reducing an arithmetic expression using the small-step
relation [astep]. *)
Definition amultistep st := multi (astep st).
Notation " t '/' st '==>a*' t' " := (amultistep st t t')
(at level 40, st at level 39).
Example astep_example1 :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
apply multi_step with (APlus (ANum 3) (ANum 12)).
apply AS_Plus2.
apply av_num.
apply AS_Mult.
apply multi_step with (ANum 15).
apply AS_Plus.
apply multi_refl.
Qed.
(** We repeatedly apply [multi_step] until we get to a normal
form. The proofs that the intermediate steps are possible are
simple enough that [auto], with appropriate hints, can solve
them. *)
Hint Constructors astep aval.
Example astep_example1' :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
eapply multi_step. auto. simpl.
eapply multi_step. auto. simpl.
apply multi_refl.
Qed.
(** The following custom [Tactic Notation] definition captures this
pattern. In addition, before each [multi_step] we print out the
current goal, so that the user can follow how the term is being
evaluated. *)
Tactic Notation "print_goal" := match goal with |- ?x => idtac x end.
Tactic Notation "normalize" :=
repeat (print_goal; eapply multi_step ;
[ (eauto 10; fail) | (instantiate; simpl)]);
apply multi_refl.
Example astep_example1'' :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
normalize.
(* At this point in the proof script, the Coq response shows
a trace of how the expression evaluated.
(APlus (ANum 3) (AMult (ANum 3) (ANum 4)) / empty_state ==>a* ANum 15)
(multi (astep empty_state) (APlus (ANum 3) (ANum 12)) (ANum 15))
(multi (astep empty_state) (ANum 15) (ANum 15))
*)
Qed.
(** The [normalize] tactic also provides a simple way to calculate
what the normal form of a term is, by proving a goal with an
existential variable in it. *)
Example astep_example1''' : exists e',
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* e'.
Proof.
eapply ex_intro. normalize.
(* This time, the trace will be:
(APlus (ANum 3) (AMult (ANum 3) (ANum 4)) / empty_state ==>a* ??)
(multi (astep empty_state) (APlus (ANum 3) (ANum 12)) ??)
(multi (astep empty_state) (ANum 15) ??)
where ?? is the variable ``guessed'' by eapply.
*)
Qed.
(** **** Exercise: 1 star (normalize_ex) *)
Theorem normalize_ex : exists e',
(AMult (ANum 3) (AMult (ANum 2) (ANum 1))) / empty_state
==>a* e'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (normalize_ex') *)
(** For comparison, prove it using [apply] instead of [eapply]. *)
Theorem normalize_ex' : exists e',
(AMult (ANum 3) (AMult (ANum 2) (ANum 1))) / empty_state
==>a* e'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 2 stars (subject_expansion) *)
(** Having seen the subject reduction property, it is reasonable to
wonder whether the opposity property -- subject _expansion_ --
also holds. That is, is it always the case that, if [t ==> t']
and [|- t' \in T], then [|- t \in T]? If so, prove it. If
not, give a counter-example. (You do not need to prove your
counter-example in Coq, but feel free to do so if you like.)
(* FILL IN HERE *)
[] *)
(** **** Exercise: 2 stars (variation1) *)
(** Suppose, that we add this new rule to the typing relation:
| T_SuccBool : forall t,
|- t \in TBool ->
|- tsucc t \in TBool
Which of the following properties remain true in the presence of
this rule? For each one, write either "remains true" or
else "becomes false." If a property becomes false, give a
counterexample.
- Determinism of [step]
- Progress
- Preservation
[] *)
(** **** Exercise: 2 stars (variation2) *)
(** Suppose, instead, that we add this new rule to the [step] relation:
| ST_Funny1 : forall t2 t3,
(tif ttrue t2 t3) ==> t3
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[] *)
(** **** Exercise: 2 stars, optional (variation3) *)
(** Suppose instead that we add this rule:
| ST_Funny2 : forall t1 t2 t2' t3,
t2 ==> t2' ->
(tif t1 t2 t3) ==> (tif t1 t2' t3)
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[] *)
(** **** Exercise: 2 stars, optional (variation4) *)
(** Suppose instead that we add this rule:
| ST_Funny3 :
(tpred tfalse) ==> (tpred (tpred tfalse))
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[] *)
(** **** Exercise: 2 stars, optional (variation5) *)
(** Suppose instead that we add this rule:
| T_Funny4 :
|- tzero \in TBool
]]
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[] *)
(** **** Exercise: 2 stars, optional (variation6) *)
(** Suppose instead that we add this rule:
| T_Funny5 :
|- tpred tzero \in TBool
]]
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[] *)
(** **** Exercise: 3 stars, optional (more_variations) *)
(** Make up some exercises of your own along the same lines as
the ones above. Try to find ways of selectively breaking
properties -- i.e., ways of changing the definitions that
break just one of the properties and leave the others alone.
[] *)
(** **** Exercise: 1 star (remove_predzero) *)
(** The evaluation rule [E_PredZero] is a bit counter-intuitive: we
might feel that it makes more sense for the predecessor of zero to
be undefined, rather than being defined to be zero. Can we
achieve this simply by removing the rule from the definition of
[step]? Would doing so create any problems elsewhere?
(* FILL IN HERE *)
[] *)
(** **** Exercise: 4 stars, advanced (prog_pres_bigstep) *)
(** Suppose our evaluation relation is defined in the big-step style.
What are the appropriate analogs of the progress and preservation
properties?
(* FILL IN HERE *)
[] *)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__NAND3_PP_BLACKBOX_V
/**
* nand3: 3-input NAND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_21_V
`define SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_21_V
/**
* sleep_sergate_plv: connect vpr to virtpwr when not in sleep mode.
*
* Verilog wrapper for sleep_sergate_plv with size of 21 units
* (invalid?).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sleep_sergate_plv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_sergate_plv_21 (
VIRTPWR,
SLEEP ,
VPWR ,
VPB ,
VNB
);
output VIRTPWR;
input SLEEP ;
input VPWR ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sleep_sergate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP),
.VPWR(VPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_sergate_plv_21 (
VIRTPWR,
SLEEP
);
output VIRTPWR;
input SLEEP ;
// Voltage supply signals
supply1 VPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sleep_sergate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_21_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// Xilinx ip cores are not fifo friendly and require a hard stop on the interface
// valid & data can not change, if ready is deasserted (if they do you will have to
// roll it back).
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axis_inf (
// adi interface
clk,
rst,
valid,
last,
data,
// xilinx interface
inf_valid,
inf_last,
inf_data,
inf_ready);
// parameter for data width
parameter DATA_WIDTH = 16;
localparam DW = DATA_WIDTH - 1;
// adi interface
input clk;
input rst;
input valid;
input last;
input [DW:0] data;
// xil interface
output inf_valid;
output inf_last;
output [DW:0] inf_data;
input inf_ready;
// internal registers
reg [ 2:0] wcnt = 'd0;
reg wlast_0 = 'd0;
reg [DW:0] wdata_0 = 'd0;
reg wlast_1 = 'd0;
reg [DW:0] wdata_1 = 'd0;
reg wlast_2 = 'd0;
reg [DW:0] wdata_2 = 'd0;
reg wlast_3 = 'd0;
reg [DW:0] wdata_3 = 'd0;
reg wlast_4 = 'd0;
reg [DW:0] wdata_4 = 'd0;
reg wlast_5 = 'd0;
reg [DW:0] wdata_5 = 'd0;
reg wlast_6 = 'd0;
reg [DW:0] wdata_6 = 'd0;
reg wlast_7 = 'd0;
reg [DW:0] wdata_7 = 'd0;
reg [ 2:0] rcnt = 'd0;
reg inf_valid = 'd0;
reg inf_last = 'd0;
reg [DW:0] inf_data = 'd0;
// write interface
always @(posedge clk) begin
if (rst == 1'b1) begin
wcnt <= 'd0;
end else if (valid == 1'b1) begin
wcnt <= wcnt + 1'b1;
end
if ((wcnt == 3'd0) && (valid == 1'b1)) begin
wlast_0 <= last;
wdata_0 <= data;
end
if ((wcnt == 3'd1) && (valid == 1'b1)) begin
wlast_1 <= last;
wdata_1 <= data;
end
if ((wcnt == 3'd2) && (valid == 1'b1)) begin
wlast_2 <= last;
wdata_2 <= data;
end
if ((wcnt == 3'd3) && (valid == 1'b1)) begin
wlast_3 <= last;
wdata_3 <= data;
end
if ((wcnt == 3'd4) && (valid == 1'b1)) begin
wlast_4 <= last;
wdata_4 <= data;
end
if ((wcnt == 3'd5) && (valid == 1'b1)) begin
wlast_5 <= last;
wdata_5 <= data;
end
if ((wcnt == 3'd6) && (valid == 1'b1)) begin
wlast_6 <= last;
wdata_6 <= data;
end
if ((wcnt == 3'd7) && (valid == 1'b1)) begin
wlast_7 <= last;
wdata_7 <= data;
end
end
// read interface
always @(posedge clk) begin
if (rst == 1'b1) begin
rcnt <= 'd0;
inf_valid <= 'd0;
inf_last <= 'b0;
inf_data <= 'd0;
end else if ((inf_ready == 1'b1) || (inf_valid == 1'b0)) begin
if (rcnt == wcnt) begin
rcnt <= rcnt;
inf_valid <= 1'd0;
inf_last <= 1'b0;
inf_data <= 'd0;
end else begin
rcnt <= rcnt + 1'b1;
inf_valid <= 1'b1;
case (rcnt)
3'd0: begin
inf_last <= wlast_0;
inf_data <= wdata_0;
end
3'd1: begin
inf_last <= wlast_1;
inf_data <= wdata_1;
end
3'd2: begin
inf_last <= wlast_2;
inf_data <= wdata_2;
end
3'd3: begin
inf_last <= wlast_3;
inf_data <= wdata_3;
end
3'd4: begin
inf_last <= wlast_4;
inf_data <= wdata_4;
end
3'd5: begin
inf_last <= wlast_5;
inf_data <= wdata_5;
end
3'd6: begin
inf_last <= wlast_6;
inf_data <= wdata_6;
end
default: begin
inf_last <= wlast_7;
inf_data <= wdata_7;
end
endcase
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO1P_BLACKBOX_V
`define SKY130_FD_SC_LP__LSBUFISO1P_BLACKBOX_V
/**
* lsbufiso1p: ????.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__lsbufiso1p (
X ,
A ,
SLEEP
);
output X ;
input A ;
input SLEEP;
// Voltage supply signals
supply1 DESTPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 DESTVPB;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO1P_BLACKBOX_V
|
// ctorng 2/22/2017
//
// 1 read-port, 1 write-port ram
//
// reads are synchronous
//
// Ports for tsmc16_2rw (sram_2p_uhde)
//
// CLK // in
// AA // in
// CENA // active low
// QA // out
//
// AB // in
// DB // in
// CENB // active low
// WENB // active low
//
// STOVAB// 1'b0 (is really a don't care, but we drive it)
// STOV // 1'b0 default
// EMA // 3'd2 default
// EMAW // 2'd1 default
// EMAS // 1'b0 default
// EMAP // 1'b0 default
// RET1N // 1'b1, active low, 1'b1 is disabled (retention mode)
//
`define bsg_mem_1r1w_sync_mask_write_bit_macro(words,bits,lgEls) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc16_1r1w_lg``lgEls``_w``bits``_bit mem ( \
.CLK (clk_i) \
,.AA (r_addr_i) \
,.CENA (~r_v_i) \
,.QA (r_data_o) \
\
,.AB (w_addr_i) \
,.DB (w_data_i) \
,.CENB (~w_v_i) \
,.WENB (~w_mask_i) \
\
,.STOV (1'd0 ) \
,.STOVAB(1'd0 ) \
,.EMA (3'd3 ) \
,.EMAW (2'd1 ) \
,.EMAS (1'b0 ) \
,.EMAP (1'b0 ) \
,.RET1N (1'b1 ) \
); \
end
`define bsg_mem_1r1w_sync_mask_write_bit_macro_rf(words,bits,lgEls) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc16_1r1w_rf_lg``lgEls``_w``bits``_bit mem ( \
.CLKA (clk_i) \
,.AA (r_addr_i) \
,.CENA (~r_v_i) \
,.QA (r_data_o) \
\
,.CLKB (clk_i) \
,.AB (w_addr_i) \
,.DB (w_data_i) \
,.CENB (~w_v_i) \
,.WENB (~w_mask_i) \
\
,.STOV (1'd0 ) \
,.EMAA (3'd3 ) \
,.EMAB (3'd3 ) \
,.EMASA (1'd1 ) \
,.RET1N (1'b1 ) \
); \
end
module bsg_mem_1r1w_sync_mask_write_bit #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=1
)
( input clk_i
, input reset_i
, input w_v_i
, input [width_p-1:0] w_mask_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
// currently unused
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [width_p-1:0] r_data_o
);
`bsg_mem_1r1w_sync_mask_write_bit_macro(64,88,6) else
`bsg_mem_1r1w_sync_mask_write_bit_macro(256,128,8) else
bsg_mem_1r1w_sync_mask_write_bit_synth
#(.width_p(width_p)
,.els_p (els_p )
,.read_write_same_addr_p(read_write_same_addr_p)
,.harden_p(harden_p)
) synth
(.*);
//synopsys translate_off
always_ff @(posedge clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p))
else
begin
//$error("%m: Attempt to read and write same address (reset_i %b, %x <= %x (mask %x) old_val %x",reset_i, w_addr_i,w_data_i,w_mask_i,mem[r_addr_i]);
$error("%m: Attempt to read and write same address (reset_i %b, %x <= %x (mask %x)",reset_i, w_addr_i,w_data_i,w_mask_i);
//$finish();
end
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p, harden_p);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_sync_mask_write_bit)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BA_2_V
`define SKY130_FD_SC_LP__O21BA_2_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ba_2 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ba_2 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BA_2_V
|
/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */
(* src = "../../verilog/max6682mean.v:1" *)
module MAX6682Mean(Reset_n_i, Clk_i, Enable_i, CpuIntr_o, MAX6682CS_n_o, SPI_Data_i, SPI_Write_o, SPI_ReadNext_o, SPI_Data_o, SPI_FIFOFull_i, SPI_FIFOEmpty_i, SPI_Transmission_i, PauseCounterPreset_i, PeriodCounterPresetH_i, PeriodCounterPresetL_i, SensorValue_o, Threshold_i, SPI_CPOL_o, SPI_CPHA_o, SPI_LSBFE_o);
(* src = "../../verilog/max6682mean.v:287" *)
wire [15:0] \$0\Accumulator[15:0] ;
(* src = "../../verilog/max6682mean.v:287" *)
wire [15:0] \$0\LastValue[15:0] ;
(* src = "../../verilog/max6682mean.v:231" *)
wire [15:0] \$0\PauseTimer[15:0] ;
(* src = "../../verilog/max6682mean.v:256" *)
wire [31:0] \$0\SensorFSM_Timer[31:0] ;
(* src = "../../verilog/max6682mean.v:112" *)
wire \$2\PauseTimerPreset[0:0] ;
(* src = "../../verilog/max6682mean.v:112" *)
wire \$2\SPI_FSM_Start[0:0] ;
(* src = "../../verilog/max6682mean.v:112" *)
wire \$2\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/max6682mean.v:303" *)
wire [15:0] \$add$../../verilog/max6682mean.v:303$35_Y ;
wire \$auto$opt_reduce.cc:126:opt_mux$2097 ;
wire \$auto$opt_reduce.cc:126:opt_mux$2103 ;
wire \$auto$opt_reduce.cc:126:opt_mux$2109 ;
wire \$procmux$1019_CMP ;
wire \$procmux$1024_CMP ;
wire \$procmux$1027_CMP ;
wire \$procmux$1121_CMP ;
wire \$procmux$1188_CMP ;
wire \$procmux$1325_CMP ;
wire \$procmux$1392_CMP ;
wire \$procmux$1529_CMP ;
wire \$procmux$1596_CMP ;
wire \$procmux$1663_CMP ;
wire [15:0] \$procmux$1729_Y ;
wire [31:0] \$procmux$1735_Y ;
wire [15:0] \$procmux$1741_Y ;
(* src = "../../verilog/max6682mean.v:245" *)
wire [15:0] \$sub$../../verilog/max6682mean.v:245$25_Y ;
(* src = "../../verilog/max6682mean.v:270" *)
wire [31:0] \$sub$../../verilog/max6682mean.v:270$30_Y ;
(* src = "../../verilog/max6682mean.v:283" *)
wire [15:0] AbsDiffResult;
(* src = "../../verilog/max6682mean.v:281" *)
wire [15:0] Accumulator;
(* src = "../../verilog/max6682mean.v:54" *)
wire [7:0] Byte0;
(* src = "../../verilog/max6682mean.v:55" *)
wire [7:0] Byte1;
(* intersynth_port = "Clk_i" *)
(* src = "../../verilog/max6682mean.v:5" *)
input Clk_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIRQs_s" *)
(* src = "../../verilog/max6682mean.v:9" *)
output CpuIntr_o;
(* src = "../../verilog/max6682mean.v:313" *)
wire [16:0] DiffAB;
(* src = "../../verilog/max6682mean.v:314" *)
wire [15:0] DiffBA;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIn_s" *)
(* src = "../../verilog/max6682mean.v:7" *)
input Enable_i;
(* src = "../../verilog/max6682mean.v:282" *)
wire [15:0] LastValue;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "Outputs_o" *)
(* src = "../../verilog/max6682mean.v:11" *)
output MAX6682CS_n_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PauseCounterPreset_i" *)
(* src = "../../verilog/max6682mean.v:27" *)
input [15:0] PauseCounterPreset_i;
(* src = "../../verilog/max6682mean.v:229" *)
wire [15:0] PauseTimer;
(* src = "../../verilog/max6682mean.v:89" *)
wire PauseTimerEnable;
(* src = "../../verilog/max6682mean.v:90" *)
wire PauseTimerOvfl;
(* src = "../../verilog/max6682mean.v:88" *)
wire PauseTimerPreset;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPresetH_i" *)
(* src = "../../verilog/max6682mean.v:29" *)
input [15:0] PeriodCounterPresetH_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPresetL_i" *)
(* src = "../../verilog/max6682mean.v:31" *)
input [15:0] PeriodCounterPresetL_i;
(* intersynth_port = "Reset_n_i" *)
(* src = "../../verilog/max6682mean.v:3" *)
input Reset_n_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_CPHA" *)
(* src = "../../verilog/max6682mean.v:39" *)
output SPI_CPHA_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_CPOL" *)
(* src = "../../verilog/max6682mean.v:37" *)
output SPI_CPOL_o;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "SPI_DataOut" *)
(* src = "../../verilog/max6682mean.v:13" *)
input [7:0] SPI_Data_i;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "SPI_DataIn" *)
(* src = "../../verilog/max6682mean.v:19" *)
output [7:0] SPI_Data_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_FIFOEmpty" *)
(* src = "../../verilog/max6682mean.v:23" *)
input SPI_FIFOEmpty_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_FIFOFull" *)
(* src = "../../verilog/max6682mean.v:21" *)
input SPI_FIFOFull_i;
(* src = "../../verilog/max6682mean.v:53" *)
wire SPI_FSM_Done;
(* src = "../../verilog/max6682mean.v:52" *)
wire SPI_FSM_Start;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_LSBFE" *)
(* src = "../../verilog/max6682mean.v:41" *)
output SPI_LSBFE_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_ReadNext" *)
(* src = "../../verilog/max6682mean.v:17" *)
output SPI_ReadNext_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_Transmission" *)
(* src = "../../verilog/max6682mean.v:25" *)
input SPI_Transmission_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_Write" *)
(* src = "../../verilog/max6682mean.v:15" *)
output SPI_Write_o;
(* src = "../../verilog/max6682mean.v:96" *)
wire SensorFSM_AddValue;
(* src = "../../verilog/max6682mean.v:94" *)
wire SensorFSM_DiffTooLarge;
(* src = "../../verilog/max6682mean.v:97" *)
wire SensorFSM_StoreNewValue;
(* src = "../../verilog/max6682mean.v:95" *)
wire SensorFSM_StoreValue;
(* src = "../../verilog/max6682mean.v:254" *)
wire [31:0] SensorFSM_Timer;
(* src = "../../verilog/max6682mean.v:93" *)
wire SensorFSM_TimerEnable;
(* src = "../../verilog/max6682mean.v:91" *)
wire SensorFSM_TimerOvfl;
(* src = "../../verilog/max6682mean.v:92" *)
wire SensorFSM_TimerPreset;
(* src = "../../verilog/max6682mean.v:280" *)
wire [15:0] SensorValue;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "SensorValue_o" *)
(* src = "../../verilog/max6682mean.v:33" *)
output [15:0] SensorValue_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "Threshold_i" *)
(* src = "../../verilog/max6682mean.v:35" *)
input [15:0] Threshold_i;
(* src = "../../verilog/max6682mean.v:303" *)
\$add #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$add$../../verilog/max6682mean.v:303$35 (
.A(Accumulator),
.B({ 5'b00000, Byte1, Byte0[7:5] }),
.Y(\$add$../../verilog/max6682mean.v:303$35_Y )
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2098 (
.A({ \$procmux$1529_CMP , \$procmux$1325_CMP , \$procmux$1121_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2097 )
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2104 (
.A({ \$procmux$1392_CMP , \$procmux$1188_CMP , \$procmux$1019_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2103 )
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2110 (
.A({ \$procmux$1596_CMP , \$procmux$1392_CMP , \$procmux$1188_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2109 )
);
(* src = "../../verilog/max6682mean.v:250" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$eq$../../verilog/max6682mean.v:250$26 (
.A(PauseTimer),
.B(16'b0000000000000000),
.Y(PauseTimerOvfl)
);
(* src = "../../verilog/max6682mean.v:275" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000100000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$eq$../../verilog/max6682mean.v:275$31 (
.A(SensorFSM_Timer),
.B(0),
.Y(SensorFSM_TimerOvfl)
);
(* fsm_encoding = "auto" *)
(* src = "../../verilog/max6682mean.v:86" *)
\$fsm #(
.ARST_POLARITY(1'b0),
.CLK_POLARITY(1'b1),
.CTRL_IN_WIDTH(32'b00000000000000000000000000000100),
.CTRL_OUT_WIDTH(32'b00000000000000000000000000001010),
.NAME("\\SensorFSM_State"),
.STATE_BITS(32'b00000000000000000000000000000100),
.STATE_NUM(32'b00000000000000000000000000001010),
.STATE_NUM_LOG2(32'b00000000000000000000000000000100),
.STATE_RST(32'b00000000000000000000000000000000),
.STATE_TABLE(40'b0111001101011001000101100010010010000000),
.TRANS_NUM(32'b00000000000000000000000000010100),
.TRANS_TABLE(440'b1001zz0z100100100000001001zz1z000100100000001000zz0z100000000010001000zz1z001000000010000111zz0z011100001000000111zz1z010000001000000110zzzz0101100000000001010zz10101000000001001011zz1001100000000100101zzz0000000000000100100z1zz100100010000000100z0zz010000010000000011z1zz100000000000010011z0zz001100000000010010z1zz011100000100000010z0zz001000000100000001z1zz011001000000000001z0zz000101000000000000zzz1010100000001000000zzz000000000000100)
) \$fsm$\SensorFSM_State$2115 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.CTRL_IN({ SensorFSM_TimerOvfl, SPI_FSM_Done, PauseTimerOvfl, Enable_i }),
.CTRL_OUT({ \$procmux$1663_CMP , \$procmux$1596_CMP , \$procmux$1529_CMP , \$procmux$1392_CMP , \$procmux$1325_CMP , \$procmux$1188_CMP , \$procmux$1121_CMP , \$procmux$1027_CMP , \$procmux$1024_CMP , \$procmux$1019_CMP })
);
(* src = "../../verilog/max6682mean.v:319" *)
\$gt #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$gt$../../verilog/max6682mean.v:319$39 (
.A(AbsDiffResult),
.B(Threshold_i),
.Y(SensorFSM_DiffTooLarge)
);
(* src = "../../verilog/max6682mean.v:231" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000010000)
) \$procdff$2089 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\PauseTimer[15:0] ),
.Q(PauseTimer)
);
(* src = "../../verilog/max6682mean.v:256" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(32'b00000000000000000000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000100000)
) \$procdff$2090 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\SensorFSM_Timer[31:0] ),
.Q(SensorFSM_Timer)
);
(* src = "../../verilog/max6682mean.v:287" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000010000)
) \$procdff$2091 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Accumulator[15:0] ),
.Q(Accumulator)
);
(* src = "../../verilog/max6682mean.v:287" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000010000)
) \$procdff$2092 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\LastValue[15:0] ),
.Q(LastValue)
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1051 (
.A(SPI_FSM_Done),
.Y(\$2\PauseTimerPreset[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$1729 (
.A(PauseTimer),
.B(\$sub$../../verilog/max6682mean.v:245$25_Y ),
.S(PauseTimerEnable),
.Y(\$procmux$1729_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$1732 (
.A(\$procmux$1729_Y ),
.B(PauseCounterPreset_i),
.S(PauseTimerPreset),
.Y(\$0\PauseTimer[15:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100000)
) \$procmux$1735 (
.A(SensorFSM_Timer),
.B(\$sub$../../verilog/max6682mean.v:270$30_Y ),
.S(SensorFSM_TimerEnable),
.Y(\$procmux$1735_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100000)
) \$procmux$1738 (
.A(\$procmux$1735_Y ),
.B({ PeriodCounterPresetH_i, PeriodCounterPresetL_i }),
.S(SensorFSM_TimerPreset),
.Y(\$0\SensorFSM_Timer[31:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$1741 (
.A(Accumulator),
.B(\$add$../../verilog/max6682mean.v:303$35_Y ),
.S(SensorFSM_AddValue),
.Y(\$procmux$1741_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$1744 (
.A(\$procmux$1741_Y ),
.B({ 5'b00000, Byte1, Byte0[7:5] }),
.S(SensorFSM_StoreValue),
.Y(\$0\Accumulator[15:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$1753 (
.A(LastValue),
.B(Accumulator),
.S(CpuIntr_o),
.Y(\$0\LastValue[15:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$374 (
.A(\$procmux$1663_CMP ),
.B(SensorFSM_DiffTooLarge),
.Y(CpuIntr_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$414 (
.A(1'b0),
.B({ SPI_FSM_Done, 1'b1 }),
.S({ \$auto$opt_reduce.cc:126:opt_mux$2103 , \$auto$opt_reduce.cc:126:opt_mux$2097 }),
.Y(PauseTimerEnable)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$448 (
.A(1'b1),
.B({ \$2\PauseTimerPreset[0:0] , 1'b0 }),
.S({ \$auto$opt_reduce.cc:126:opt_mux$2103 , \$auto$opt_reduce.cc:126:opt_mux$2097 }),
.Y(PauseTimerPreset)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$482 (
.A(1'b0),
.B({ \$2\SPI_FSM_Start[0:0] , PauseTimerOvfl }),
.S({ \$procmux$1024_CMP , \$auto$opt_reduce.cc:126:opt_mux$2097 }),
.Y(SPI_FSM_Start)
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$513 (
.A(\$auto$opt_reduce.cc:126:opt_mux$2109 ),
.B(SPI_FSM_Done),
.Y(SensorFSM_AddValue)
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$599 (
.A(\$procmux$1019_CMP ),
.B(SPI_FSM_Done),
.Y(SensorFSM_StoreValue)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$672 (
.A(1'b0),
.B({ Enable_i, 1'b1 }),
.S({ \$procmux$1027_CMP , \$procmux$1024_CMP }),
.Y(SensorFSM_TimerEnable)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$706 (
.A(1'b1),
.B({ \$2\SensorFSM_TimerPreset[0:0] , 1'b0 }),
.S({ \$procmux$1027_CMP , \$procmux$1024_CMP }),
.Y(SensorFSM_TimerPreset)
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$777 (
.A(Enable_i),
.Y(\$2\SensorFSM_TimerPreset[0:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$844 (
.A(Enable_i),
.B(SensorFSM_TimerOvfl),
.Y(\$2\SPI_FSM_Start[0:0] )
);
(* src = "../../verilog/max6682mean.v:245" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$sub$../../verilog/max6682mean.v:245$25 (
.A(PauseTimer),
.B(1'b1),
.Y(\$sub$../../verilog/max6682mean.v:245$25_Y )
);
(* src = "../../verilog/max6682mean.v:270" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000100000)
) \$sub$../../verilog/max6682mean.v:270$30 (
.A(SensorFSM_Timer),
.B(1'b1),
.Y(\$sub$../../verilog/max6682mean.v:270$30_Y )
);
(* src = "../../verilog/max6682mean.v:315" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010001),
.Y_WIDTH(32'b00000000000000000000000000010001)
) \$sub$../../verilog/max6682mean.v:315$36 (
.A({ 1'b0, LastValue }),
.B({ 1'b0, Accumulator }),
.Y(DiffAB)
);
(* src = "../../verilog/max6682mean.v:316" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$sub$../../verilog/max6682mean.v:316$37 (
.A(Accumulator),
.B(LastValue),
.Y(DiffBA)
);
(* src = "../../verilog/max6682mean.v:317" *)
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$ternary$../../verilog/max6682mean.v:317$38 (
.A(DiffAB[15:0]),
.B(DiffBA),
.S(DiffAB[16]),
.Y(AbsDiffResult)
);
(* src = "../../verilog/max6682mean.v:57" *)
SPI_FSM SPI_FSM_1 (
.Byte0(Byte0),
.Byte1(Byte1),
.Clk_i(Clk_i),
.MAX6682CS_n_o(MAX6682CS_n_o),
.Reset_n_i(Reset_n_i),
.SPI_Data_i(SPI_Data_i),
.SPI_FSM_Done(SPI_FSM_Done),
.SPI_FSM_Start(SPI_FSM_Start),
.SPI_ReadNext_o(SPI_ReadNext_o),
.SPI_Transmission_i(SPI_Transmission_i),
.SPI_Write_o(SPI_Write_o)
);
assign SPI_CPHA_o = 1'b0;
assign SPI_CPOL_o = 1'b0;
assign SPI_Data_o = 8'b00000000;
assign SPI_LSBFE_o = 1'b0;
assign SensorFSM_StoreNewValue = CpuIntr_o;
assign SensorValue = { 5'b00000, Byte1, Byte0[7:5] };
assign SensorValue_o = LastValue;
endmodule
(* src = "../../verilog/spifsm.v:1" *)
module SPI_FSM(Reset_n_i, Clk_i, SPI_FSM_Start, SPI_Transmission_i, MAX6682CS_n_o, SPI_Write_o, SPI_ReadNext_o, SPI_FSM_Done, SPI_Data_i, Byte0, Byte1);
(* src = "../../verilog/spifsm.v:117" *)
wire [7:0] \$0\Byte0[7:0] ;
(* src = "../../verilog/spifsm.v:117" *)
wire [7:0] \$0\Byte1[7:0] ;
(* src = "../../verilog/spifsm.v:50" *)
wire \$2\MAX6682CS_n_o[0:0] ;
(* src = "../../verilog/spifsm.v:50" *)
wire \$2\SPI_FSM_Wr1[0:0] ;
wire \$auto$opt_reduce.cc:126:opt_mux$2101 ;
wire \$auto$opt_reduce.cc:126:opt_mux$2111 ;
wire \$procmux$1864_CMP ;
wire \$procmux$1865_CMP ;
wire \$procmux$1866_CMP ;
wire \$procmux$1869_CMP ;
(* src = "../../verilog/spifsm.v:11" *)
output [7:0] Byte0;
(* src = "../../verilog/spifsm.v:12" *)
output [7:0] Byte1;
(* src = "../../verilog/spifsm.v:3" *)
input Clk_i;
(* src = "../../verilog/spifsm.v:6" *)
output MAX6682CS_n_o;
(* src = "../../verilog/spifsm.v:2" *)
input Reset_n_i;
(* src = "../../verilog/spifsm.v:10" *)
input [7:0] SPI_Data_i;
(* src = "../../verilog/spifsm.v:9" *)
output SPI_FSM_Done;
(* src = "../../verilog/spifsm.v:4" *)
input SPI_FSM_Start;
(* src = "../../verilog/spifsm.v:24" *)
wire SPI_FSM_Wr0;
(* src = "../../verilog/spifsm.v:23" *)
wire SPI_FSM_Wr1;
(* src = "../../verilog/spifsm.v:8" *)
output SPI_ReadNext_o;
(* src = "../../verilog/spifsm.v:5" *)
input SPI_Transmission_i;
(* src = "../../verilog/spifsm.v:7" *)
output SPI_Write_o;
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2102 (
.A({ SPI_FSM_Wr0, \$procmux$1866_CMP , \$procmux$1865_CMP , \$procmux$1864_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2101 )
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000010),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2112 (
.A({ SPI_FSM_Done, \$procmux$1869_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2111 )
);
(* fsm_encoding = "auto" *)
(* src = "../../verilog/spifsm.v:21" *)
\$fsm #(
.ARST_POLARITY(1'b0),
.CLK_POLARITY(1'b1),
.CTRL_IN_WIDTH(32'b00000000000000000000000000000010),
.CTRL_OUT_WIDTH(32'b00000000000000000000000000000110),
.NAME("\\SPI_FSM_State"),
.STATE_BITS(32'b00000000000000000000000000000011),
.STATE_NUM(32'b00000000000000000000000000000110),
.STATE_NUM_LOG2(32'b00000000000000000000000000000011),
.STATE_RST(32'b00000000000000000000000000000000),
.STATE_TABLE(18'b011101001010100000),
.TRANS_NUM(32'b00000000000000000000000000001001),
.TRANS_TABLE(126'b1011z1010000011010z001000001100z1011010000100z0000010000011zz010000100010zz101000010001zz100100000000z1011001000000z0000001000)
) \$fsm$\SPI_FSM_State$2127 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.CTRL_IN({ SPI_Transmission_i, SPI_FSM_Start }),
.CTRL_OUT({ SPI_FSM_Wr0, SPI_FSM_Done, \$procmux$1869_CMP , \$procmux$1866_CMP , \$procmux$1865_CMP , \$procmux$1864_CMP })
);
(* src = "../../verilog/spifsm.v:117" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000001000)
) \$procdff$2094 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Byte0[7:0] ),
.Q(Byte0)
);
(* src = "../../verilog/spifsm.v:117" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000001000)
) \$procdff$2095 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Byte1[7:0] ),
.Q(Byte1)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$1756 (
.A(Byte0),
.B(SPI_Data_i),
.S(SPI_FSM_Wr0),
.Y(\$0\Byte0[7:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$1763 (
.A(Byte1),
.B(SPI_Data_i),
.S(SPI_FSM_Wr1),
.Y(\$0\Byte1[7:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1891 (
.A(\$procmux$1864_CMP ),
.B(\$2\SPI_FSM_Wr1[0:0] ),
.Y(SPI_FSM_Wr1)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1902 (
.A(1'b0),
.B({ \$2\SPI_FSM_Wr1[0:0] , 1'b1 }),
.S({ \$procmux$1864_CMP , SPI_FSM_Wr0 }),
.Y(SPI_ReadNext_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1915 (
.A(1'b1),
.B({ 1'b0, \$2\MAX6682CS_n_o[0:0] }),
.S({ \$auto$opt_reduce.cc:126:opt_mux$2101 , \$auto$opt_reduce.cc:126:opt_mux$2111 }),
.Y(MAX6682CS_n_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1943 (
.A(1'b0),
.B({ 1'b1, SPI_FSM_Start }),
.S({ \$procmux$1866_CMP , \$auto$opt_reduce.cc:126:opt_mux$2111 }),
.Y(SPI_Write_o)
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1980 (
.A(SPI_FSM_Start),
.Y(\$2\MAX6682CS_n_o[0:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$2020 (
.A(SPI_Transmission_i),
.Y(\$2\SPI_FSM_Wr1[0:0] )
);
endmodule
|
/////////////////////////////
//LAB01 29/05 - Atividade 1//
/////////////////////////////
module Mod_Teste(
input CLOCK_27,
input CLOCK_50,
input [3:0] KEY,
input [17:0] SW,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7,
output [8:0] LEDG,
output [17:0] LEDR
);
// Ligacoes na placa
//{SW[17],SW[16],SW[15],SW[14],SW[13],SW[12],SW[11],SW[10],SW[9],SW[8],SW[7],SW[6],SW[5],SW[4],SW[3],SW[2],SW[1],SW[0]}
//{DA[2], DA[1], DA[0], AA[2], AA[1], AA[0], BA[2], BA[1], BA[0],MB, FS[3],FS[2],FS[1],FS[0],MD[2],RW, D_in, CONST_in}
parameter WORD_WIDTH = 16;
wire [WORD_WIDTH-1:0] B2HEXA_in, B2HEXB_in;
// Conversores Binario->7 Segmentos Hexadecimal
Decoder_Binary2HexSevenSegments B2HEXA(HEX0, B2HEXA_in);
Decoder_Binary2HexSevenSegments B2HEXB(HEX1, B2HEXB_in);
// Leds da Placa ligados ao barramento para monitoramento da atividade
assign LEDR[7:0] = {B2HEXA_in, B2HEXB_in};
// Instancia do Datapath
Datapath DP(
.FLAG_out(LEDR[17:13]),
.A_bus(B2HEXA_in),
.D_bus(B2HEXB_in),
.D_in({WORD_WIDTH{SW[1]}}),
.CNTRL_in(SW[17:2]),
.CONST_in({{(WORD_WIDTH-3){1'b0}},SW[1:0]}),
.CLK(KEY[3]),
);
defparam DP.WORD_WIDTH = WORD_WIDTH;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__SDFRBP_FUNCTIONAL_PP_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRBP_FUNCTIONAL_PP_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_clockgen.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_clockgen.v,v $
// Revision 1.2 2005/12/13 12:54:49 maverickist
// first simulation passed
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
// Revision 1.2 2005/04/27 15:58:45 Administrator
// no message
//
// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
// no message
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:55 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
//parameter Tp=1;
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
output Mdc; // Output clock
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
reg Mdc;
reg [7:0] Counter;
wire CountEq0;
wire [7:0] CounterPreset;
wire [7:0] TempDivider;
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are counting half of period
// Counter counts half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Counter[7:0] <= 8'h1;
else
begin
if(CountEq0)
begin
Counter[7:0] <= CounterPreset[7:0];
end
else
Counter[7:0] <= Counter - 8'h1;
end
end
// Mdc is asserted every other half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Mdc <= 1'b0;
else
begin
if(CountEq0)
Mdc <= ~Mdc;
end
end
assign CountEq0 = Counter == 8'h0;
assign MdcEn = CountEq0 & ~Mdc;
assign MdcEn_n = CountEq0 & Mdc;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DLATCH_LP_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HD__UDP_DLATCH_LP_PP_PG_N_BLACKBOX_V
/**
* udp_dlatch$lP_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N (
Q ,
D ,
GATE ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DLATCH_LP_PP_PG_N_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module flt_mult
(
input clk,
input rstn,
input [31:0] afl,
input [31:0] bfl,
output reg [31:0] fl
);
reg [47:0] mfl_0; // Mantisa of the Float
reg sfl_0; // Sign of the Float
reg [7:0] efl_0; // Exponent of the Float
reg zero_out_0;
reg sfl_1; // Sign of the Float
reg [7:0] efl_1; // Exponent of the Float
reg zero_out_1;
reg mfl47_1; // Mantisa of the Float
reg [24:0] nmfl_1; // Normalized Mantisa of the Float
reg not_mfl_47;
always @* not_mfl_47 = (~mfl47_1 & ~nmfl_1[24]);
always @(posedge clk, negedge rstn) begin
if(!rstn) begin
mfl_0 <= 48'h0;
sfl_0 <= 1'b0;
efl_0 <= 8'h0;
zero_out_0 <= 1'b0;
efl_1 <= 8'h0;
sfl_1 <= 1'b0;
zero_out_1 <= 1'b0;
mfl47_1 <= 1'b0;
nmfl_1 <= 25'h0;
fl <= 32'h0;
end
else begin
// Pipe 0.
// Multiply the mantisa.
mfl_0 <= {1'b1,afl[22:0]} * {1'b1,bfl[22:0]};
// Calulate the Sign.
sfl_0 <= afl[31] ^ bfl[31];
efl_0 <= afl[30:23] + bfl[30:23] - 8'h7E;
// If a or b equals zero, return zero.
if((afl[30:0] == 0) || (bfl[30:0] == 0))zero_out_0 <= 1'b1;
else zero_out_0 <= 1'b0;
// Pipe 1.
efl_1 <= efl_0;
sfl_1 <= sfl_0;
zero_out_1 <= zero_out_0;
mfl47_1 <= mfl_0[47];
if(mfl_0[47]) nmfl_1 <= mfl_0[47:24] + mfl_0[23];
else nmfl_1 <= mfl_0[47:23] + mfl_0[22];
// Pipe 2.
if(zero_out_1) fl <= 32'h0;
else fl <= {sfl_1,(efl_1 - not_mfl_47),nmfl_1[22:0]};
end
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zqynq_lab_1_design_xlconcat_0_1 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
`timescale 1ns / 1ps
module alu_min( RST, CLK, ENA, RGA, RGB, RGZ, KEY, OPT);
input RST, CLK, ENA;
input [7:0]OPT;
input [7:0]RGA;
input [7:0]RGB;
output [7:0]RGZ;
input [1:0]KEY;
reg [7:0]RGZ;
reg [11:0]tmp;
/**********************************************************************
* PROTECTION CELLS *
*********************************************************************/
always@(posedge CLK)begin
if(RST) RGZ = 0;
else begin
case(OPT)
8'b00000001: RGZ = 0;
8'b00000010: RGZ <= RGA + RGB;
8'b00000011: RGZ <= RGA - RGB;
8'b00000011: RGZ <= RGA^RGB;
8'b00000100: RGZ <= RGA&RGB;
8'b00000101: RGZ <= RGA|RGB;
8'b00000110: RGZ <= RGA&&RGB;
8'b00000111: RGZ <= RGA||RGB;
8'b00001000: RGZ <= RGA+1;
8'b00001001: RGZ <= RGA-1;
8'b00001010: RGZ <= RGA<<1;
8'b00001011: RGZ <= RGA>>1;
8'b00001100: RGZ <= !RGA;
8'b00001101: RGZ <= ~RGA;
8'b00001110: RGZ <= RGA+RGA;
8'b00001111: RGZ <= RGA-RGA;
8'b00010000: RGZ <= RGB+RGZ;
8'b00010001: RGZ <= RGB-RGZ;
8'b00010011: RGZ <= RGB^RGZ;
8'b00010100: RGZ <= RGB&RGZ;
8'b00010101: RGZ <= RGB|RGZ;
8'b00010110: RGZ <= RGB&&RGZ;
8'b00010111: RGZ <= RGB||RGZ;
8'b00111000: RGZ <= RGZ+1;
8'b00111001: RGZ <= RGZ-1;
8'b00111010: RGZ <= RGZ<<1;
8'b00111011: RGZ <= RGZ>>1;
8'b00111100: RGZ <= !RGZ;
8'b00111101: RGZ <= ~RGZ;
8'b00111110: RGZ <= RGB+RGZ;
8'b00111111: RGZ <= RGB-RGZ;
8'b00100000: RGZ <= RGA+RGB;
8'b00100001: RGZ <= RGA-RGB;
8'b00100011: RGZ <= RGA^RGB;
8'b00100100: RGZ <= RGA&RGB;
8'b00100101: RGZ <= RGA|RGB;
8'b00100110: RGZ <= RGA&&RGB;
8'b00100111: RGZ <= RGA||RGB;
8'b00101000: RGZ <= RGA+1;
8'b00101001: RGZ <= RGA-1;
8'b00101010: RGZ <= RGA<<1;
8'b00101011: RGZ <= RGA>>1;
8'b00101100: RGZ <= !RGA;
8'b00101101: RGZ <= ~RGA;
8'b00101110: RGZ <= RGA+RGA;
8'b00101111: RGZ <= RGA-RGA;
8'b00110000: RGZ <= RGZ+RGA;
8'b00110001: RGZ <= RGZ-RGA;
8'b00111000: RGZ <= RGZ+1;
8'b00111001: RGZ <= RGZ-1;
8'b00111010: RGZ <= RGZ<<1;
8'b00111011: RGZ <= RGZ>>1;
8'b00111100: RGZ <= !RGZ;
8'b00111101: RGZ <= ~RGZ;
8'b00111110: RGZ <= RGZ+RGB;
8'b00111111: RGZ <= RGZ-RGB;
/////////////////////////////////////////////////////
8'b01000000: RGZ=RGA+RGB;
8'b01000001: RGZ=RGA-RGB;
8'b01000010: RGZ=RGB-1;
8'b01000100: RGZ=RGA&&RGB;
8'b01000101: RGZ=RGA||RGB;
8'b01000110: RGZ=!RGA;
8'b01000111: RGZ=~RGA;
8'b01001000: RGZ=RGA&RGB;
8'b01001001: RGZ=RGA|RGB;
8'b01001010: RGZ=RGA^RGB;
8'b01001011: RGZ=RGA<<1;
8'b01001100: RGZ=RGA>>1;
8'b01001101: RGZ=RGA+1;
8'b01001110: RGZ=RGA-1;
8'b01001111: RGZ=RGA-1;
8'b01010000: RGZ=RGA+RGB;
8'b01010001: RGZ=RGA-RGB;
8'b01010010: RGZ=RGB-1;
8'b01010011: RGZ=RGA*RGB;
8'b01010100: RGZ=RGA&&RGB;
8'b01010101: RGZ=RGA||RGB;
8'b01010110: RGZ=!RGA;
8'b01010111: RGZ=~RGA;
8'b01011000: RGZ=RGA&RGB;
8'b01011001: RGZ=RGA|RGB;
8'b01011010: RGZ=RGA^RGB;
8'b01011011: RGZ=RGA<<1;
8'b01011100: RGZ=RGA>>1;
8'b01011101: RGZ=RGA+1;
8'b01011110: RGZ=RGA-1;
8'b01011111: RGZ=RGA-1;
8'b01100000: RGZ=RGA+RGB;
8'b01100001: RGZ=RGA-RGB;
8'b01100010: RGZ=RGB-1;
8'b01100100: RGZ=RGA&&RGB;
8'b01100101: RGZ=RGA||RGB;
8'b01100110: RGZ=!RGA;
8'b01100111: RGZ=~RGA;
8'b01101000: RGZ=RGA&RGB;
8'b01101001: RGZ=RGA|RGB;
8'b01101010: RGZ=RGA^RGB;
8'b01101011: RGZ=RGA<<1;
8'b01101100: RGZ=RGA>>1;
8'b01101101: RGZ=RGA+1;
8'b01101110: RGZ=RGA-1;
8'b01101111: RGZ=RGA-1;
8'b01110000: RGZ=RGA+RGB;
8'b01110001: RGZ=RGA-RGB;
8'b01110010: RGZ=RGB-1;
8'b01110011: RGZ=RGA*RGB;
8'b01110100: RGZ=RGA&&RGB;
8'b01110101: RGZ=RGA||RGB;
8'b01110110: RGZ=!RGA;
8'b01110111: RGZ=~RGA;
8'b01111000: RGZ=RGA&RGB;
8'b01111001: RGZ=RGA|RGB;
8'b01111010: RGZ=RGA^RGB;
8'b01111011: RGZ=RGA<<1;
8'b01111100: RGZ=RGA>>1;
8'b01111101: RGZ=RGA+1;
8'b01111110: RGZ=RGA-1;
8'b01111111: RGZ=RGA-1;
8'b10000000: RGZ=RGA+RGB;
8'b10000001: RGZ=RGA-RGB;
8'b10000010: RGZ=RGB-1;
8'b10000100: RGZ=RGA&&RGB;
8'b10000101: RGZ=RGA||RGB;
8'b10000110: RGZ=!RGA;
8'b10000111: RGZ=~RGA;
8'b10001000: RGZ=RGA&RGB;
8'b10001001: RGZ=RGA|RGB;
8'b10001010: RGZ=RGA^RGB;
8'b10001011: RGZ=RGA<<1;
8'b10001100: RGZ=RGA>>1;
8'b10001101: RGZ=RGA+1;
8'b10001110: RGZ=RGA-1;
8'b10001111: RGZ=RGA-1;
8'b10010000: RGZ=RGA+RGB;
8'b10010001: RGZ=RGA-RGB;
8'b10010010: RGZ=RGB-1;
8'b10010100: RGZ=RGA&&RGB;
8'b10010101: RGZ=RGA||RGB;
8'b10010110: RGZ=!RGA;
8'b10010111: RGZ=~RGA;
8'b10011000: RGZ=RGA&RGB;
8'b10011001: RGZ=RGA|RGB;
8'b10011010: RGZ=RGA^RGB;
8'b10011011: RGZ=RGA<<1;
8'b10011100: RGZ=RGA>>1;
8'b10011101: RGZ=RGA+1;
8'b10011110: RGZ=RGA-1;
8'b10011111: RGZ=RGA-1;
8'b10100000: RGZ=RGA+RGB;
8'b10100001: RGZ=RGA-RGB;
8'b10100010: RGZ=RGB-1;
8'b10100011: RGZ=RGA*RGB;
8'b10100100: RGZ=RGA&&RGB;
8'b10100101: RGZ=RGA||RGB;
8'b10100110: RGZ=!RGA;
8'b10100111: RGZ=~RGA;
8'b10101000: RGZ=RGA&RGB;
8'b10101001: RGZ=RGA|RGB;
8'b10101010: RGZ=RGA^RGB;
8'b10101011: RGZ=RGA<<1;
8'b10101100: RGZ=RGA>>1;
8'b10101101: RGZ=RGA+1;
8'b10101110: RGZ=RGA-1;
8'b10101111: RGZ=RGA-1;
8'b10110000: RGZ=RGA+RGB;
8'b10110001: RGZ=RGA-RGB;
8'b10110010: RGZ=RGB-1;
8'b10110011: RGZ=RGA*RGB;
8'b10110100: RGZ=RGA&&RGB;
8'b10110101: RGZ=RGA||RGB;
8'b10110110: RGZ=!RGA;
8'b10110111: RGZ=~RGA;
8'b10111000: RGZ=RGA&RGB;
8'b10111001: RGZ=RGA|RGB;
8'b10111010: RGZ=RGA^RGB;
8'b10111011: RGZ=RGA<<1;
8'b10111100: RGZ=RGA>>1;
8'b10111101: RGZ=RGA+1;
8'b10111110: RGZ=RGA-1;
8'b10111111: RGZ=RGA-1;
8'b11000000: RGZ=RGA+RGB;
8'b11000001: RGZ=RGA-RGB;
8'b11000010: RGZ=RGB-1;
8'b11000011: RGZ=RGA*RGB;
8'b11000100: RGZ=RGA&&RGB;
8'b11000101: RGZ=RGA||RGB;
8'b11000110: RGZ=!RGA;
8'b11000111: RGZ=~RGA;
8'b11001000: RGZ=RGA&RGB;
8'b11001001: RGZ=RGA|RGB;
8'b11001010: RGZ=RGA^RGB;
8'b11001011: RGZ=RGA<<1;
8'b11001100: RGZ=RGA>>1;
8'b11001101: RGZ=RGA+1;
8'b11001110: RGZ=RGA-1;
8'b11001111: RGZ=RGA-1;
8'b11010000: RGZ=RGA+RGB;
8'b11010001: RGZ=RGA-RGB;
8'b11010010: RGZ=RGB-1;
8'b11010011: RGZ=RGA*RGB;
8'b11010100: RGZ=RGA&&RGB;
8'b11010101: RGZ=RGA||RGB;
8'b11010110: RGZ=!RGA;
8'b11010111: RGZ=~RGA;
8'b11011000: RGZ=RGA&RGB;
8'b11011001: RGZ=RGA|RGB;
8'b11011010: RGZ=RGA^RGB;
8'b11011011: RGZ=RGA<<1;
8'b11011100: RGZ=RGA>>1;
8'b11011101: RGZ=RGA+1;
8'b11011110: RGZ=RGA-1;
8'b11011111: RGZ=RGA-1;
8'b11100000: RGZ=RGA+RGB;
8'b11100001: RGZ=RGA-RGB;
8'b11100010: RGZ=RGB-1;
8'b11100011: RGZ=RGA*RGB;
8'b11100100: RGZ=RGA&&RGB;
8'b11100101: RGZ=RGA||RGB;
8'b11100110: RGZ=!RGA;
8'b11100111: RGZ=~RGA;
8'b11101000: RGZ=RGA&RGB;
8'b11101001: RGZ=RGA|RGB;
8'b11101010: RGZ=RGA^RGB;
8'b11101011: RGZ=RGA<<1;
8'b11101100: RGZ=RGA>>1;
8'b11101101: RGZ=RGA+1;
8'b11101110: RGZ=RGA-1;
8'b11101111: RGZ=RGA-1;
8'b11110000: RGZ=RGA+RGB;
8'b11110001: RGZ=RGA-RGB;
8'b11110010: RGZ=RGB-1;
8'b11110011: RGZ=RGA*RGB;
8'b11110100: RGZ=RGA&&RGB;
8'b11110101: RGZ=RGA||RGB;
8'b11110110: RGZ=!RGA;
8'b11110111: RGZ=~RGA;
8'b11111000: RGZ=RGA&RGB;
8'b11111001: RGZ=RGA|RGB;
8'b11111010: RGZ=RGA^RGB;
8'b11111011: RGZ=RGA<<1;
8'b11111100: RGZ=RGA>>1;
8'b11111101: RGZ=RGA+1;
8'b11111110: RGZ=RGA-1;
8'b11111111: RGZ=RGA-1;
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BOI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A21BOI_PP_SYMBOL_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a21boi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BOI_PP_SYMBOL_V
|
/*
* main - main loop for grey_counter
*
* This section includes the grey counter and
* adds all necessary support for clocks and resets.
*
* This code was derived from the Demo program provided
* for the Lattice MachX) 2280 Breakout Board which
* blinks the LED's.
* [www.latticesemi.com/breakoutboards]
*
* Due to the hardware configuration the LEDs are
* inverted from what is expected. For example an
* LED that is on actually indicates a 0 instead of a 1.
* This is why the grey code, starting at all zeros,
* has all the LED's on.
*
*/
`include "grey_counter.v"
// 4 bit oscillating LED pattern
module main(rstn, osc_clk, led, clk );
input rstn ;
output osc_clk ;
output wire [7:0] led ;
output clk ;
reg [22:0]c_delay ;
// Reset occurs when argument is active low.
GSR GSR_INST (.GSR(rstn));
OSCC OSCC_1 (.OSC(osc_clk)) ;
grey_counter gc1(clk, led);
// The c_delay counter is used to slow down the internal oscillator (OSC) output
// to a rate of approximately 0.5 Hz
always @(posedge osc_clk or negedge rstn)
begin
if (~rstn)
c_delay <= 32'h0000 ;
else
c_delay <= c_delay + 1 ;
end
assign clk = c_delay[22] ;
endmodule
|
`timescale 1ns/1ns
module spi_slave_rx
(input clk,
input cs,
input sclk,
input mosi,
output miso,
output [7:0] rxd,
output rxdv,
output rxe); // rx end
assign miso = 1'b0; // for now, this thing is just an RX machine
wire sclk_sync, mosi_sync, cs_sync;
sync #(3, 3) in_sync
(.clk(clk), .in({sclk, mosi, ~cs}), .out({sclk_sync, mosi_sync, cs_sync}));
wire cs_sync_d1;
r cs_sync_d1_r(.c(clk), .rst(1'b0), .en(1'b1), .d(cs_sync), .q(cs_sync_d1));
wire sclk_sync_d1;
r sclk_sync_d1_r(.c(clk), .rst(1'b0), .en(1'b1),
.d(sclk_sync), .q(sclk_sync_d1));
wire mosi_sync_d1;
r mosi_sync_d1_r(.c(clk), .rst(1'b0), .en(1'b1),
.d(mosi_sync), .q(mosi_sync_d1));
localparam SW = 3;
localparam ST_IDLE = 3'd0;
localparam ST_CS_LO = 3'd1;
localparam ST_SCLK_LO = 3'd2;
localparam ST_SCLK_HI = 3'd3;
localparam ST_CS_HI = 3'd4;
localparam CW = 4;
reg [SW+CW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r(clk, next_state, 1'b0, 1'b1, state);
wire bit_cnt_rst, bit_cnt_en;
wire [2:0] bit_cnt;
r #(3) bit_cnt_r(.c(clk), .rst(bit_cnt_rst), .en(bit_cnt_en),
.d(bit_cnt+1'b1), .q(bit_cnt));
always @* begin
case (state)
ST_IDLE:
if (cs_sync) ctrl = { ST_CS_LO , 4'b0001 };
else ctrl = { ST_IDLE , 4'b0000 };
ST_CS_LO:
if (~sclk_sync) ctrl = { ST_SCLK_LO, 4'b0000 };
else ctrl = { ST_CS_LO , 4'b0000 };
ST_SCLK_LO:
if (sclk_sync) ctrl = { ST_SCLK_HI, 4'b0010 };
else ctrl = { ST_SCLK_LO, 4'b0000 };
ST_SCLK_HI:
if (~cs_sync) ctrl = { ST_CS_HI , 4'b0100 };
else if (~sclk_sync) ctrl = { ST_SCLK_LO, 4'b0100 };
else ctrl = { ST_SCLK_HI, 4'b0000 };
ST_CS_HI: ctrl = { ST_IDLE , 4'b0000 };
default: ctrl = { ST_IDLE , 4'b0000 };
endcase
end
assign bit_cnt_rst = ctrl[0];
assign bit_cnt_en = ctrl[1];
wire sclk_hi_done = ctrl[2];
r #(8) rxd_r(.c(clk), .rst(1'b0), .en(bit_cnt_en),
.d({rxd[6:0], mosi_sync_d1}), .q(rxd));
assign rxdv = bit_cnt == 3'b0 & sclk_hi_done; //state == ST_SCLK_HI;
assign rxe = state == ST_CS_HI;
endmodule
|
/* verilator lint_off UNUSED */
/* verilator lint_off CASEX */
/* verilator lint_off PINNOCONNECT */
/* verilator lint_off PINMISSING */
/* verilator lint_off IMPLICIT */
/* verilator lint_off WIDTH */
/* verilator lint_off UNDRIVEN */
// `define EMC
`define PSRAM
`define etherlite
//`define MIG_ARTY7
module TOP_SYS(
clk100,rstn,gpio_in,
// uart
TXD,RXD,
// psram
extA,extDB,extWEN,extUB,extLB,extCSN,extWAIT,
extOE,extCLK,extADV,extCRE,
// spi flash
sdin,sdout,sdwp,sdhld,sdcs,sdreset,
// gpio it87xx
//gpioA,gpioB,
// ethernet
PhyMdc,
PhyMdio,
PhyRstn,
PhyCrs,
PhyRxErr,
PhyRxd,
PhyTxEn,
PhyTxd,
PhyClk50Mhz,
PhyIntn,
// tiny spi
miso,
mosi,
sclk,
acl_sel,
debug
);
input clk100;
input rstn;
output TXD;
input [6:0] gpio_in;
output extCLK,extCRE;
output extADV,extUB,extLB,extWEN,extCSN,extOE;
input RXD;
output sdout,sdwp,sdhld,sdcs;
input sdin;
//inout [7:0] gpioA,gpioB;
wire [7:0] gpioA,gpioB;
input extWAIT;
output reg sdreset;
output reg acl_sel;
// tiny spi
output mosi;
input miso;
output sclk;
output [11:0] debug;
// external mem I/F
inout [15:0] extDB;
output [23:0] extA;
output PhyMdc;
inout PhyMdio;
output PhyRstn;
output PhyCrs;
input PhyRxErr;
input [1:0] PhyRxd;
output PhyTxEn;
output [1:0] PhyTxd;
output reg PhyClk50Mhz;
output reg PhyIntn;
// ethernet
wire PhyMdio_t;
wire PhyMdio_o;
wire [11:0] debug_int2;
assign debug = debug_v586;
// axi cpu bus
wire [31:0] M_AXI_AW, M_AXI_AR;
wire M_AXI_AWVALID,M_AXI_ARVALID,M_AXI_WVALID,M_AXI_RREADY;
wire M_AXI_AWREADY,M_AXI_ARREADY,M_AXI_WREADY,M_AXI_RVALID,M_AXI_RLAST,M_AXI_WLAST;
wire [31:0] M_AXI_R;
wire [31:0] M_AXI_W;
wire [3:0] M_AXI_WSTRB;
wire [1:0] M_AXI_ARBURST;
wire [7:0] M_AXI_ARLEN;
wire [2:0] M_AXI_ARSIZE;
wire [1:0] M_AXI_AWBURST;
wire [7:0] M_AXI_AWLEN;
wire [2:0] M_AXI_AWSIZE;
// axi ram bus
wire [31:0] S_AXI_AW_ram, S_AXI_AR_ram;
wire S_AXI_AWVALID_ram,S_AXI_ARVALID_ram,S_AXI_WVALID_ram,S_AXI_RREADY_ram;
wire S_AXI_AWREADY_ram,S_AXI_ARREADY_ram,S_AXI_WREADY_ram,S_AXI_RVALID_ram,S_AXI_RLAST_ram,S_AXI_WLAST_ram;
wire [31:0] S_AXI_R_ram;
wire [31:0] S_AXI_W_ram;
wire [3:0] S_AXI_WSTRB_ram;
wire [1:0] S_AXI_ARBURST_ram;
wire [7:0] S_AXI_ARLEN_ram;
wire [2:0] S_AXI_ARSIZE_ram;
wire [1:0] S_AXI_AWBURST_ram;
wire [7:0] S_AXI_AWLEN_ram;
wire [2:0] S_AXI_AWSIZE_ram;
// axi rom bus
wire [31:0] S_AXI_AW_rom, S_AXI_AR_rom;
wire S_AXI_AWVALID_rom,S_AXI_ARVALID_rom,S_AXI_WVALID_rom,S_AXI_RREADY_rom;
wire S_AXI_AWREADY_rom,S_AXI_ARREADY_rom,S_AXI_WREADY_rom,S_AXI_RVALID_rom,S_AXI_RLAST_rom,S_AXI_WLAST_rom;
wire [31:0] S_AXI_R_rom;
wire [31:0] S_AXI_W_rom;
wire [3:0] S_AXI_WSTRB_rom;
wire [1:0] S_AXI_ARBURST_rom;
wire [7:0] S_AXI_ARLEN_rom;
wire [2:0] S_AXI_ARSIZE_rom;
wire [1:0] S_AXI_AWBURST_rom;
wire [7:0] S_AXI_AWLEN_rom;
wire [2:0] S_AXI_AWSIZE_rom;
// axi net bus
wire [31:0] S_AXI_AW_net, S_AXI_AR_net;
wire S_AXI_AWVALID_net,S_AXI_ARVALID_net,S_AXI_WVALID_net,S_AXI_RREADY_net;
wire S_AXI_AWREADY_net,S_AXI_ARREADY_net,S_AXI_WREADY_net,S_AXI_RVALID_net,S_AXI_RLAST_net,S_AXI_WLAST_net;
wire [31:0] S_AXI_R_net;
wire [31:0] S_AXI_W_net;
wire [3:0] S_AXI_WSTRB_net;
wire [1:0] S_AXI_ARBURST_net;
wire [7:0] S_AXI_ARLEN_net;
wire [2:0] S_AXI_ARSIZE_net;
wire [1:0] S_AXI_AWBURST_net;
wire [7:0] S_AXI_AWLEN_net;
wire [2:0] S_AXI_AWSIZE_net;
// axi io bus
wire [31:0] M_IO_AXI_AW, M_IO_AXI_AR;
wire M_IO_AXI_AWVALID,M_IO_AXI_ARVALID,M_IO_AXI_WVALID,M_IO_AXI_RREADY;
wire M_IO_AXI_AWREADY,M_IO_AXI_ARREADY,M_IO_AXI_WREADY,M_IO_AXI_RVALID,M_IO_AXI_RLAST,M_IO_AXI_WLAST;
wire [31:0] M_IO_AXI_R;
wire [31:0] M_IO_AXI_W;
wire [3:0] M_IO_AXI_WSTRB;
wire [1:0] M_IO_AXI_ARBURST;
wire [3:0] M_IO_AXI_ARLEN;
wire [2:0] M_IO_AXI_ARSIZE;
wire [1:0] M_IO_AXI_AWBURST;
wire [7:0] M_IO_AXI_AWLEN;
wire [2:0] M_IO_AXI_AWSIZE;
wire [15:0] extDBo,extDBt;
wire [7:0] gpioA_dir,gpioB_dir,gpioA_out,gpioB_out;
wire [31:0] romA,romQ;
wire int_pic,iack;
wire [7:0] ivect;
wire clk;
wire [11:0] debug_v586;
//PULLUP i_PULLUP ( .O(extWAIT) );
//clk_wiz_v3_6 clk_wiz_v3_6 (.CLK_IN1(clk100) , .CLK_OUT1(clk) );
assign clk = clk100;
STARTUPE2 #(
.PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams.
.SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation.
)
STARTUPE2_inst (
.CFGCLK(), // 1-bit output: Configuration main clock output
.CFGMCLK(), // 1-bit output: Configuration internal oscillator clock output
.EOS(), // 1-bit output: Active high output signal indicating the End Of Startup.
.PREQ(), // 1-bit output: PROGRAM request to fabric output
.CLK(1'b0), // 1-bit input: User start-up clock input
.GSR(1'b0), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
.GTS(1'b0), // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
.KEYCLEARB(1'b0), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
.PACK(1'b0), // 1-bit input: PROGRAM acknowledge input
.USRCCLKO(sdclk), // 1-bit input: User CCLK input
.USRCCLKTS(1'b0), // 1-bit input: User CCLK 3-state enable input
.USRDONEO(1'b1), // 1-bit input: User DONE pin output control
.USRDONETS(1'b1) // 1-bit input: User DONE 3-state enable output
);
v586 v586 (
.m00_AXI_RSTN(rstn&psram_rdy),.m00_AXI_CLK(clk),
// axi interface 32bit
.m00_AXI_AWADDR(M_AXI_AW), .m00_AXI_AWVALID(M_AXI_AWVALID), .m00_AXI_AWREADY(M_AXI_AWREADY),
.m00_AXI_AWBURST(M_AXI_AWBURST), .m00_AXI_AWLEN(M_AXI_AWLEN), .m00_AXI_AWSIZE(M_AXI_AWSIZE),
.m00_AXI_WDATA(M_AXI_W), .m00_AXI_WVALID(M_AXI_WVALID), .m00_AXI_WREADY(M_AXI_WREADY), .m00_AXI_WSTRB(M_AXI_WSTRB), .m00_AXI_WLAST(M_AXI_WLAST),
.m00_AXI_ARADDR(M_AXI_AR), .m00_AXI_ARVALID(M_AXI_ARVALID), .m00_AXI_ARREADY(M_AXI_ARREADY),
.m00_AXI_ARBURST(M_AXI_ARBURST), .m00_AXI_ARLEN(M_AXI_ARLEN), .m00_AXI_ARSIZE(M_AXI_ARSIZE),
.m00_AXI_RDATA(M_AXI_R), .m00_AXI_RVALID(M_AXI_RVALID), .m00_AXI_RREADY(M_AXI_RREADY), .m00_AXI_RLAST(M_AXI_RLAST),
.m00_AXI_BVALID(1'b1),.m00_AXI_BREADY(M_AXI_BREADY),
// axi io interface 32bit
.m01_AXI_AWADDR(M_IO_AXI_AW), .m01_AXI_AWVALID(M_IO_AXI_AWVALID), .m01_AXI_AWREADY(M_IO_AXI_AWREADY),
.m01_AXI_AWBURST(M_IO_AXI_AWBURST), .m01_AXI_AWLEN(M_IO_AXI_AWLEN), .m01_AXI_AWSIZE(M_IO_AXI_AWSIZE),
.m01_AXI_WDATA(M_IO_AXI_W), .m01_AXI_WVALID(M_IO_AXI_WVALID), .m01_AXI_WREADY(M_IO_AXI_WREADY), .m01_AXI_WSTRB(M_IO_AXI_WSTRB), .m01_AXI_WLAST(M_IO_AXI_WLAST),
.m01_AXI_ARADDR(M_IO_AXI_AR), .m01_AXI_ARVALID(M_IO_AXI_ARVALID), .m01_AXI_ARREADY(M_IO_AXI_ARREADY),
.m01_AXI_ARBURST(M_IO_AXI_ARBURST), .m01_AXI_ARLEN(M_IO_AXI_ARLEN), .m01_AXI_ARSIZE(M_IO_AXI_ARSIZE),
.m01_AXI_RDATA(M_IO_AXI_R), .m01_AXI_RVALID(M_IO_AXI_RVALID), .m01_AXI_RREADY(M_IO_AXI_RREADY), .m01_AXI_RLAST(M_IO_AXI_RLAST),
.m01_AXI_BVALID(1'b1),.m01_AXI_BREADY(M_IO_AXI_BREADY),
// interrupts
.int_pic(int_pic),.ivect(ivect),.iack(iack),
.debug(debug_v586)
);
psram_axi_sync psram_axi_sync(
// MEM
.mem_addr(extA[23:1]),
.mem_cen(extCSN),
.mem_oen(extOE),
.mem_wen(extWEN),
.mem_ben({extUB,extLB}),
.mem_adv(extADV),
.mem_cre(extCRE),
.mem_data_i(extDB),
.mem_data_o(extDBo),
.mem_data_t(extDBt),
.mem_clk(extCLK),
.mem_wait(extWAIT),
.debug(debug_int2),
// CTRL
.clk(clk),
.rstn(rstn),
.controller_ready(psram_rdy),
// AXI
// AW CHANNEL
.s00_axi_awaddr(S_AXI_AW_ram),
.s00_axi_awlen(S_AXI_AWLEN_ram),
.s00_axi_awsize(S_AXI_AWSIZE_ram),
.s00_axi_awburst(S_AXI_AWBURST_ram),
.s00_axi_awvalid(S_AXI_AWVALID_ram),
.s00_axi_awready(S_AXI_AWREADY_ram),
// W CHANNEL
.s00_axi_wdata(S_AXI_W_ram),
.s00_axi_wstrb(S_AXI_WSTRB_ram),
.s00_axi_wlast(S_AXI_WLAST_ram),
.s00_axi_wvalid(S_AXI_WVALID_ram),
.s00_axi_wready(S_AXI_WREADY_ram),
// B CHANNEL
.s00_axi_bvalid(),
.s00_axi_bready(1'b1),
// AR CHANNEL
.s00_axi_araddr(S_AXI_AR_ram[23:0]),
.s00_axi_arlen(S_AXI_ARLEN_ram),
.s00_axi_arsize(S_AXI_ARSIZE_ram),
.s00_axi_arburst(S_AXI_ARBURST_ram),
.s00_axi_arvalid(S_AXI_ARVALID_ram),
.s00_axi_arready(S_AXI_ARREADY_ram),
// R CHANNEL
.s00_axi_rdata(S_AXI_R_ram),
.s00_axi_rlast(S_AXI_RLAST_ram),
.s00_axi_rvalid(S_AXI_RVALID_ram),
.s00_axi_rready(S_AXI_RREADY_ram)
);
axi_rom bootrom (
.clk(clk),
.rstn(rstn&psram_rdy),
.axi_ARVALID(S_AXI_ARVALID_rom),
.axi_ARREADY(S_AXI_ARREADY_rom),
.axi_AR(S_AXI_AR_rom),
.axi_ARBURST(S_AXI_ARBURST_rom),
.axi_ARLEN(S_AXI_ARLEN_rom),
.axi_RLAST(S_AXI_RLAST_rom),
.axi_R(S_AXI_R_rom),
.axi_RVALID(S_AXI_RVALID_rom),
.axi_RREADY(S_AXI_RREADY_rom)
);
`ifdef etherlite
axi_ethernetlite_0 i_etherlite (
.s_axi_aclk(clk),
.s_axi_aresetn(rstn&psram_rdy),
.ip2intc_irpt(),
.s_axi_awid(4'b000),
.s_axi_awaddr(S_AXI_AW_net[12:0]),
.s_axi_awlen(S_AXI_AWLEN_net),
.s_axi_awsize(S_AXI_AWSIZE_net),
.s_axi_awburst(S_AXI_AWBURST_net),
.s_axi_awcache(4'b0000),
.s_axi_awvalid(S_AXI_AWVALID_net),
.s_axi_awready(S_AXI_AWREADY_net),
.s_axi_wdata(S_AXI_W_net),
.s_axi_wstrb(S_AXI_WSTRB_net),
.s_axi_wlast(S_AXI_WLAST_net),
.s_axi_wvalid(S_AXI_WVALID_net),
.s_axi_wready(S_AXI_WREADY_net),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'b1),
.s_axi_arid(4'b0),
.s_axi_araddr(S_AXI_AR_net[12:0]),
.s_axi_arlen(S_AXI_ARLEN_net),
.s_axi_arsize(S_AXI_ARSIZE_net),
.s_axi_arburst(S_AXI_ARBURST_net),
.s_axi_arcache(4'b0),
.s_axi_arvalid(S_AXI_ARVALID_net),
.s_axi_arready(S_AXI_ARREADY_net),
.s_axi_rid(),
.s_axi_rdata(S_AXI_R_net),
.s_axi_rresp(),
.s_axi_rlast(S_AXI_RLAST_net),
.s_axi_rvalid(S_AXI_RVALID_net),
.s_axi_rready(S_AXI_RREADY_net),
.phy_tx_clk(clk),
.phy_rx_clk(clk),
.phy_crs(PhyCrs),
.phy_dv(1'b0),
.phy_rx_data({PhyRxd,2'b00}),
.phy_col(1'b0),
.phy_rx_er(PhyRxErr),
.phy_rst_n(PhyRstn),
.phy_tx_en(PhyTxEn),
//.phy_tx_data(PhyTxd),
.phy_mdio_i(PhyMdio),
.phy_mdio_o(PhyMdio_o),
.phy_mdio_t(PhyMdio_t),
.phy_mdc(PhyMdc)
);
assign PhyMdio = (PhyMdio_t) ? 1'bz : PhyMdio_o;
`endif
`ifndef etherlite
assign S_AXI_AWREADY_net = 1'b1;
assign S_AXI_WREADY_net = 1'b1;
assign S_AXI_ARREADY_net = 1'b1;
assign S_AXI_RVALID_net = 1'b1;
assign S_AXI_RLAST_net = 1'b1;
assign S_AXI_R_net = 32'h0;
`endif
axi_crossbar_0 i_axi_crossbar_0 (
.aclk(clk),
.aresetn(rstn&psram_rdy),
.m_axi_awaddr({S_AXI_AW_net,S_AXI_AW_rom,S_AXI_AW_ram}),
.m_axi_awlen({S_AXI_AWLEN_net,S_AXI_AWLEN_rom,S_AXI_AWLEN_ram}),
.m_axi_awsize({S_AXI_AWSIZE_net,S_AXI_AWSIZE_rom,S_AXI_AWSIZE_ram}),
.m_axi_awburst({S_AXI_AWBURST_net,S_AXI_AWBURST_rom,S_AXI_AWBURST_ram}),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid({S_AXI_AWVALID_net,S_AXI_AWVALID_rom,S_AXI_AWVALID_ram}),
.m_axi_awready({1'b1,1'b1,S_AXI_AWREADY_ram}), // rely on B channel
.m_axi_wdata({S_AXI_W_net,S_AXI_W_rom,S_AXI_W_ram}),
.m_axi_wstrb({S_AXI_WSTRB_net,S_AXI_WSTRB_rom,S_AXI_WSTRB_ram}),
.m_axi_wlast({S_AXI_WLAST_net,S_AXI_WLAST_rom,S_AXI_WLAST_ram}),
.m_axi_wuser(),
.m_axi_wvalid({S_AXI_WVALID_net,S_AXI_WVALID_rom,S_AXI_WVALID_ram}),
.m_axi_wready({1'b1,1'b1,S_AXI_WREADY_ram}), // rely on B channel
.m_axi_bresp(0),
.m_axi_buser(0),
.m_axi_bvalid(3'b111),
.m_axi_bready(),
.m_axi_araddr({S_AXI_AR_net,S_AXI_AR_rom,S_AXI_AR_ram}),
.m_axi_arlen({S_AXI_ARLEN_net,S_AXI_ARLEN_rom,S_AXI_ARLEN_ram}),
.m_axi_arsize({S_AXI_ARSIZE_net,S_AXI_ARSIZE_rom,S_AXI_ARSIZE_ram}),
.m_axi_arburst({S_AXI_ARBURST_net,S_AXI_ARBURST_rom,S_AXI_ARBURST_ram}),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid({S_AXI_ARVALID_net,S_AXI_ARVALID_rom,S_AXI_ARVALID_ram}),
.m_axi_arready({1'b0 ,S_AXI_ARREADY_rom,S_AXI_ARREADY_ram}), // rely on B channel
.m_axi_rdata({S_AXI_R_net,S_AXI_R_rom,S_AXI_R_ram}),
.m_axi_rresp(6'b0),
.m_axi_rlast({S_AXI_RLAST_net,S_AXI_RLAST_rom,S_AXI_RLAST_ram}),
.m_axi_ruser(12'b0),
.m_axi_rvalid({S_AXI_RVALID_net,S_AXI_RVALID_rom,S_AXI_RVALID_ram}),
.m_axi_rready({S_AXI_RREADY_net,S_AXI_RREADY_rom,S_AXI_RREADY_ram}),
.s_axi_awaddr(M_AXI_AW), .s_axi_awvalid(M_AXI_AWVALID), .s_axi_awready(M_AXI_AWREADY),
.s_axi_awburst(M_AXI_AWBURST), .s_axi_awlen(M_AXI_AWLEN), .s_axi_awsize(M_AXI_AWSIZE),
.s_axi_wdata(M_AXI_W), .s_axi_wvalid(M_AXI_WVALID), .s_axi_wready(M_AXI_WREADY), .s_axi_wstrb(M_AXI_WSTRB), .s_axi_wlast(M_AXI_WLAST),
.s_axi_araddr(M_AXI_AR), .s_axi_arvalid(M_AXI_ARVALID), .s_axi_arready(M_AXI_ARREADY),
.s_axi_arburst(M_AXI_ARBURST), .s_axi_arlen(M_AXI_ARLEN), .s_axi_arsize(M_AXI_ARSIZE),
.s_axi_rdata(M_AXI_R), .s_axi_rvalid(M_AXI_RVALID), .s_axi_rready(M_AXI_RREADY), .s_axi_rlast(M_AXI_RLAST),
.s_axi_bvalid(),.s_axi_bready(1'b1),
.s_axi_arlock(0), .s_axi_arcache(0),.s_axi_arprot(0), .s_axi_arqos(0), .s_axi_aruser(0),
.s_axi_awlock(0), .s_axi_awcache(0),.s_axi_awprot(0), .s_axi_awqos(0), .s_axi_awuser(0),
.s_axi_wuser(0)
);
always @(posedge clk) if (rstn == 0) sdreset <=1; else sdreset <=0;
always @(posedge clk) if (rstn == 0) acl_sel <=1; else acl_sel <=0;
always @(posedge clk) if (rstn == 0) PhyClk50Mhz <=0; else PhyClk50Mhz <=~PhyClk50Mhz;
assign extDB[0] = extDBt[0] ? extDBo[0] : 32'bz ;
assign extDB[1] = extDBt[1] ? extDBo[1] : 32'bz ;
assign extDB[2] = extDBt[2] ? extDBo[2] : 32'bz ;
assign extDB[3] = extDBt[3] ? extDBo[3] : 32'bz ;
assign extDB[4] = extDBt[4] ? extDBo[4] : 32'bz ;
assign extDB[5] = extDBt[5] ? extDBo[5] : 32'bz ;
assign extDB[6] = extDBt[6] ? extDBo[6] : 32'bz ;
assign extDB[7] = extDBt[7] ? extDBo[7] : 32'bz ;
assign extDB[8] = extDBt[8] ? extDBo[8] : 32'bz ;
assign extDB[9] = extDBt[9] ? extDBo[9] : 32'bz ;
assign extDB[10] = extDBt[10] ? extDBo[10] : 32'bz ;
assign extDB[11] = extDBt[11] ? extDBo[11] : 32'bz ;
assign extDB[12] = extDBt[12] ? extDBo[12] : 32'bz ;
assign extDB[13] = extDBt[13] ? extDBo[13] : 32'bz ;
assign extDB[14] = extDBt[14] ? extDBo[14] : 32'bz ;
assign extDB[15] = extDBt[15] ? extDBo[15] : 32'bz ;
/*
assign gpioA[0] = (gpioA_dir[0] == 0) ? 1'bz : gpioA_out[0];
assign gpioA[1] = (gpioA_dir[1] == 0) ? 1'bz : gpioA_out[1];
assign gpioA[2] = (gpioA_dir[2] == 0) ? 1'bz : gpioA_out[2];
assign gpioA[3] = (gpioA_dir[3] == 0) ? 1'bz : gpioA_out[3];
assign gpioA[4] = (gpioA_dir[4] == 0) ? 1'bz : gpioA_out[4];
assign gpioA[5] = (gpioA_dir[5] == 0) ? 1'bz : gpioA_out[5];
assign gpioA[6] = (gpioA_dir[6] == 0) ? 1'bz : gpioA_out[6];
assign gpioA[7] = (gpioA_dir[7] == 0) ? 1'bz : gpioA_out[7];
assign gpioB[0] = (gpioB_dir[0] == 0) ? 1'bz : gpioB_out[0];
assign gpioB[1] = (gpioB_dir[1] == 0) ? 1'bz : gpioB_out[1];
assign gpioB[2] = (gpioB_dir[2] == 0) ? 1'bz : gpioB_out[2];
assign gpioB[3] = (gpioB_dir[3] == 0) ? 1'bz : gpioB_out[3];
assign gpioB[4] = (gpioB_dir[4] == 0) ? 1'bz : gpioB_out[4];
assign gpioB[5] = (gpioB_dir[5] == 0) ? 1'bz : gpioB_out[5];
assign gpioB[6] = (gpioB_dir[6] == 0) ? 1'bz : gpioB_out[6];
assign gpioB[7] = (gpioB_dir[7] == 0) ? 1'bz : gpioB_out[7];
*/
assign sdwp = 1'b1;
assign sdhld = 1'b1;
periph i_periph (
.s00_AXI_RSTN(rstn&psram_rdy),
.s00_AXI_CLK(clk),
.cfg(gpio_in[6:0]),
// spi
.spi_mosi(sdout),
.spi_miso(sdin),
.spi_clk(sdclk),
.spi_cs(sdcs),
// tiny spi
.mosi(mosi),
.miso(miso),
.sclk(sclk),
// interrupts
.int_pic(int_pic),
.iack(iack),
.ivect(ivect),
// gpio
.gpioA_in(gpioA),.gpioB_in(gpioB),
.gpioA_out(gpioA_out),.gpioB_out(gpioB_out),
.gpioA_dir(gpioA_dir),.gpioB_dir(gpioB_dir),
//uart
.RXD(RXD),
.TXD(TXD),
// AXI4 IO 32 BIT BUS
.s00_AXI_AWADDR(M_IO_AXI_AW),
.s00_AXI_AWVALID(M_IO_AXI_AWVALID),
.s00_AXI_AWREADY(M_IO_AXI_AWREADY),
.s00_AXI_AWBURST(M_IO_AXI_AWBURST),
.s00_AXI_AWLEN(M_IO_AXI_AWLEN),
.s00_AXI_AWSIZE(M_IO_AXI_AWSIZE),
.s00_AXI_ARADDR(M_IO_AXI_AR),
.s00_AXI_ARVALID(M_IO_AXI_ARVALID),
.s00_AXI_ARREADY(M_IO_AXI_ARREADY),
.s00_AXI_ARBURST(M_IO_AXI_ARBURST),
.s00_AXI_ARLEN(M_IO_AXI_ARLEN),
.s00_AXI_ARSIZE(M_IO_AXI_ARSIZE),
.s00_AXI_WDATA(M_IO_AXI_W),
.s00_AXI_WVALID(M_IO_AXI_WVALID),
.s00_AXI_WREADY(M_IO_AXI_WREADY),
.s00_AXI_WSTRB(M_IO_AXI_WSTRB),
.s00_AXI_WLAST(M_IO_AXI_WLAST),
.s00_AXI_RDATA(M_IO_AXI_R),
.s00_AXI_RVALID(M_IO_AXI_RVALID),
.s00_AXI_RREADY(M_IO_AXI_RREADY),
.s00_AXI_RLAST(M_IO_AXI_RLAST),
.s00_AXI_BVALID(),
.s00_AXI_BREADY(1'b1)
);
endmodule
|
module cameraReader_sim
(
input clk,
input reset_n,
output refclk,
input pclk,
input [7:0] data,
input vsync,
input hsync,
output [15:0] data_out,
output wire wrreq,
output wire wrclk
);
reg wrclk1 = 0;
always@(negedge clk)
wrclk1 <= ~wrclk1;
reg [19:0] pixel_counter;
reg [9:0] wait_counter_hs;
reg [19:0] wait_counter_vs;
reg [1:0] state = 0;
assign wrclk = clk;
assign wrreq = state == 2'b01 ? wrclk1 : 1'b0;
assign data_out = pixel_counter % 640;
always@(posedge wrclk1)
begin
if(reset_n == 1'b0)
begin
pixel_counter <= 0;
wait_counter_vs <= 0;
wait_counter_hs <= 0;
end
else
begin
case(state)
2'b00:
begin
if(wait_counter_vs == 15679)
begin
wait_counter_vs <= 0;
state <= 2'b01;
pixel_counter <= pixel_counter + 1;
end
else
wait_counter_vs <= wait_counter_vs + 1;
end
2'b01:
begin
if(pixel_counter % 640 == 0)
begin
if(pixel_counter == 640*480)
begin
pixel_counter <= 0;
state <= 2'b11; //vs wait
end
else
state <= 2'b10; // hs wait
end
else
pixel_counter <= pixel_counter + 1;
end
2'b10:
begin
if(wait_counter_hs == 144)
begin
wait_counter_hs <= 0;
state <= 2'b01;
pixel_counter <= pixel_counter + 1;
end
else
wait_counter_hs <= wait_counter_hs + 1;
end
2'b11:
begin
if(wait_counter_vs == 7839)
begin
wait_counter_vs <= 0;
state <= 2'b00;
end
else
wait_counter_vs <= wait_counter_vs + 1;
end
endcase
end
end
endmodule |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Dec 25 17:16:48 2016
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// d:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/ball_small/ball_small_stub.v
// Design : ball_small
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module ball_small(clka, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[9:0],dina[11:0],douta[11:0]" */;
input clka;
input [0:0]wea;
input [9:0]addra;
input [11:0]dina;
output [11:0]douta;
endmodule
|
//
// Every HW component class has to be derived from :class:`hwt.synthesizer.unit.Unit` class
//
// .. hwt-autodoc::
//
module Showcase0 (
input wire[31:0] a,
input wire signed[31:0] b,
output reg[31:0] c,
input wire clk,
output reg cmp_0,
output reg cmp_1,
output reg cmp_2,
output reg cmp_3,
output reg cmp_4,
output reg cmp_5,
output reg[31:0] contOut,
input wire[31:0] d,
input wire e,
output wire f,
output reg[15:0] fitted,
output reg[7:0] g,
output reg[7:0] h,
input wire[1:0] i,
output reg[7:0] j,
output reg[31:0] k,
output wire out,
output wire output_0,
input wire rst_n,
output reg[7:0] sc_signal
);
localparam [31:0] const_private_signal = 32'h0000007b;
reg signed[7:0] fallingEdgeRam[0:3];
reg r = 1'b0;
reg[1:0] r_0 = 2'b00;
reg[1:0] r_1 = 2'b00;
reg r_next;
wire[1:0] r_next_0;
wire[1:0] r_next_1;
reg[7:0] rom[0:3];
always @(a, b) begin: assig_process_c
c = a + $signed(b);
end
always @(a) begin: assig_process_cmp_0
cmp_0 = a < 32'h00000004;
end
always @(a) begin: assig_process_cmp_1
cmp_1 = a > 32'h00000004;
end
always @(b) begin: assig_process_cmp_2
cmp_2 = b <= $signed(32'h00000004);
end
always @(b) begin: assig_process_cmp_3
cmp_3 = b >= $signed(32'h00000004);
end
always @(b) begin: assig_process_cmp_4
cmp_4 = b != $signed(32'h00000004);
end
always @(b) begin: assig_process_cmp_5
cmp_5 = b == $signed(32'h00000004);
end
always @(*) begin: assig_process_contOut
contOut = const_private_signal;
end
assign f = r;
always @(negedge clk) begin: assig_process_fallingEdgeRam
fallingEdgeRam[r_1] <= $unsigned(a[7:0]);
k <= {24'h000000, $signed(fallingEdgeRam[r_1])};
end
always @(a) begin: assig_process_fitted
fitted = a[15:0];
end
always @(a, b) begin: assig_process_g
g = {{a[1] & b[1], a[0] ^ b[0] | a[1]}, a[5:0]};
end
always @(a, r) begin: assig_process_h
if (a[2])
if (r)
h = 8'h00;
else if (a[1])
h = 8'h01;
else
h = 8'h02;
end
always @(posedge clk) begin: assig_process_j
j <= rom[r_1];
end
assign out = 1'b0;
assign output_0 = 1'bx;
always @(posedge clk) begin: assig_process_r
if (rst_n == 1'b0) begin
r_1 <= 2'b00;
r_0 <= 2'b00;
r <= 1'b0;
end else begin
r_1 <= r_next_1;
r_0 <= r_next_0;
r <= r_next;
end
end
assign r_next_0 = i;
assign r_next_1 = r_0;
always @(e, r) begin: assig_process_r_next_1
if (~r)
r_next = e;
else
r_next = r;
end
always @(a) begin: assig_process_sc_signal
case(a)
32'h00000001:
sc_signal = 8'h00;
32'h00000002:
sc_signal = 8'h01;
32'h00000003:
sc_signal = 8'h03;
default:
sc_signal = 8'h04;
endcase
end
initial begin
rom[0] = 0;
rom[1] = 1;
rom[2] = 2;
rom[3] = 3;
end
endmodule
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// -- --
// -- The pre-decode block. Does partial instruction decoding and sequencing --
// -- before passing the instruction onto the next stage. --
// -- --
// -----------------------------------------------------------------------------
`default_nettype none
module zap_predecode_main #(
//
// For several reasons, we need more architectural registers than
// what ARM specifies. We also need more physical registers.
//
parameter ARCH_REGS = 32,
//
// Although ARM mentions only 16 ALU operations, the processor
// internally performs many more operations.
//
parameter ALU_OPS = 32,
//
// Apart from the 4 specified by ARM, an undocumented RORI is present
// to help deal with immediate rotates.
//
parameter SHIFT_OPS = 5,
// Number of physical registers.
parameter PHY_REGS = 46,
// Coprocessor IF enable.
parameter COPROCESSOR_INTERFACE_ENABLE = 1,
// Compressed ISA support.
parameter COMPRESSED_EN = 1
)
///////////////////////////////////////////////////////////////////////////////
(
// Clock and reset.
input wire i_clk,
input wire i_reset,
// Branch state.
input wire [1:0] i_taken,
input wire i_force32,
input wire i_und,
// Clear and stall signals. From high to low priority.
input wire i_clear_from_writeback, // |Pri
input wire i_data_stall, // |
input wire i_clear_from_alu, // |
input wire i_stall_from_shifter, // |
input wire i_stall_from_issue, // V
// Interrupt events.
input wire i_irq,
input wire i_fiq,
input wire i_abt,
// Is 0 if all pipeline is invalid. Used for coprocessor.
input wire i_pipeline_dav,
// Coprocessor done.
input wire i_copro_done,
// PC input.
input wire [31:0] i_pc_ff,
input wire [31:0] i_pc_plus_8_ff,
// CPU mode. Taken from CPSR in the ALU.
input wire i_cpu_mode_t, // T mode.
input wire [4:0] i_cpu_mode_mode, // CPU mode.
// Instruction input.
input wire [34:0] i_instruction,
input wire i_instruction_valid,
// Instruction output
output reg [39:0] o_instruction_ff,
output reg o_instruction_valid_ff,
// Stall of PC and fetch.
output reg o_stall_from_decode,
// PC output.
output reg [31:0] o_pc_plus_8_ff,
output reg [31:0] o_pc_ff,
// Interrupts.
output reg o_irq_ff,
output reg o_fiq_ff,
output reg o_abt_ff,
output reg o_und_ff,
// Force 32-bit alignment on memory accesses.
output reg o_force32align_ff,
// Coprocessor interface.
output wire o_copro_dav_ff,
output wire [31:0] o_copro_word_ff,
// Branch.
output reg [1:0] o_taken_ff,
// Clear from decode.
output reg o_clear_from_decode,
output reg [31:0] o_pc_from_decode
);
`include "zap_defines.vh"
`include "zap_localparams.vh"
`include "zap_functions.vh"
///////////////////////////////////////////////////////////////////////////////
// Branch states.
localparam SNT = 0; // Strongly Not Taken.
localparam WNT = 1; // Weakly Not Taken.
localparam WT = 2; // Weakly Taken.
localparam ST = 3; // Strongly Taken.
///////////////////////////////////////////////////////////////////////////////
wire [39:0] o_instruction_nxt;
wire o_instruction_valid_nxt;
wire mem_fetch_stall;
wire arm_irq;
wire arm_fiq;
wire [34:0] arm_instruction;
wire arm_instruction_valid;
wire cp_stall;
wire [34:0] cp_instruction;
wire cp_instruction_valid;
wire cp_irq;
wire cp_fiq;
wire o_irq_nxt;
wire o_fiq_nxt;
reg [1:0] taken_nxt;
///////////////////////////////////////////////////////////////////////////////
// Flop the outputs to break the pipeline at this point.
always @ (posedge i_clk)
begin
if ( i_reset )
begin
reset;
clear;
end
else if ( i_clear_from_writeback )
begin
clear;
end
else if ( i_data_stall )
begin
// Preserve state.
end
else if ( i_clear_from_alu )
begin
clear;
end
else if ( i_stall_from_shifter )
begin
// Preserve state.
end
else if ( i_stall_from_issue )
begin
// Preserve state.
end
// If no stall, only then update...
else
begin
// Do not pass IRQ and FIQ if mask is 1.
o_irq_ff <= i_irq;
o_fiq_ff <= i_fiq;
o_abt_ff <= i_abt;
o_und_ff <= i_und && i_instruction_valid;
o_pc_plus_8_ff <= i_pc_plus_8_ff;
o_pc_ff <= i_pc_ff;
o_force32align_ff <= i_force32;
o_taken_ff <= taken_nxt;
o_instruction_ff <= o_instruction_nxt;
o_instruction_valid_ff <= o_instruction_valid_nxt;
end
end
task reset;
begin
o_irq_ff <= 0;
o_fiq_ff <= 0;
o_abt_ff <= 0;
o_und_ff <= 0;
o_pc_plus_8_ff <= 0;
o_pc_ff <= 0;
o_force32align_ff <= 0;
o_taken_ff <= 0;
o_instruction_ff <= 0;
o_instruction_valid_ff <= 0;
end
endtask
task clear;
begin
o_irq_ff <= 0;
o_fiq_ff <= 0;
o_abt_ff <= 0;
o_und_ff <= 0;
o_taken_ff <= 0;
o_instruction_valid_ff <= 0;
end
endtask
always @*
begin
o_stall_from_decode = mem_fetch_stall || cp_stall;
end
///////////////////////////////////////////////////////////////////////////////
// This unit handles coprocessor stuff.
zap_predecode_coproc
#(
.PHY_REGS(PHY_REGS)
)
u_zap_decode_coproc
(
// Inputs from outside world.
.i_clk(i_clk),
.i_reset(i_reset),
.i_irq(i_irq),
.i_fiq(i_fiq),
.i_instruction(i_instruction_valid ? i_instruction : 32'd0),
.i_valid(i_instruction_valid),
.i_cpsr_ff_t(i_cpu_mode_t),
.i_cpsr_ff_mode(i_cpu_mode_mode),
// Clear and stall signals.
.i_clear_from_writeback(i_clear_from_writeback),
.i_data_stall(i_data_stall),
.i_clear_from_alu(i_clear_from_alu),
.i_stall_from_issue(i_stall_from_issue),
.i_stall_from_shifter(i_stall_from_shifter),
// Valid signals.
.i_pipeline_dav (i_pipeline_dav),
// Coprocessor
.i_copro_done(i_copro_done),
// Output to next block.
.o_instruction(cp_instruction),
.o_valid(cp_instruction_valid),
.o_irq(cp_irq),
.o_fiq(cp_fiq),
// Stall.
.o_stall_from_decode(cp_stall),
// Coprocessor interface.
.o_copro_dav_ff(o_copro_dav_ff),
.o_copro_word_ff(o_copro_word_ff)
);
///////////////////////////////////////////////////////////////////////////////
assign arm_instruction = cp_instruction;
assign arm_instruction_valid = cp_instruction_valid;
assign arm_irq = cp_irq;
assign arm_fiq = cp_fiq;
///////////////////////////////////////////////////////////////////////////////
always @*
begin:bprblk1
reg [31:0] addr;
reg [31:0] addr_final;
o_clear_from_decode = 1'd0;
o_pc_from_decode = 32'd0;
taken_nxt = i_taken;
addr = $signed(arm_instruction[23:0]);
if ( arm_instruction[34] ) // Indicates a shift of 1.
addr_final = addr << 1;
else
addr_final = addr << 2;
//
// Perform actions as mentioned by the predictor unit in the fetch
// stage.
//
if ( arm_instruction[27:25] == 3'b101 && arm_instruction_valid )
begin
if ( i_taken[1] || arm_instruction[31:28] == AL )
// Taken or Strongly Taken or Always taken.
begin
// Take the branch. Clear pre-fetched instruction.
o_clear_from_decode = 1'd1;
// Predict new PC.
o_pc_from_decode = i_pc_plus_8_ff + addr_final;
if ( arm_instruction[31:28] == AL )
taken_nxt = ST;
end
else // Not Taken or Weakly Not Taken.
begin
// Else dont take the branch since pre-fetched
// instruction is correct.
o_clear_from_decode = 1'd0;
o_pc_from_decode = 32'd0;
end
end
end
///////////////////////////////////////////////////////////////////////////////
// This FSM handles LDM/STM/SWAP/SWAPB/BL/LMULT
zap_predecode_mem_fsm u_zap_mem_fsm (
.i_clk(i_clk),
.i_reset(i_reset),
.i_instruction(arm_instruction),
.i_instruction_valid(arm_instruction_valid),
.i_fiq(arm_fiq),
.i_irq(arm_irq),
.i_cpsr_t(i_cpu_mode_t),
.i_clear_from_writeback(i_clear_from_writeback),
.i_data_stall(i_data_stall),
.i_clear_from_alu(i_clear_from_alu),
.i_issue_stall(i_stall_from_issue),
.i_stall_from_shifter(i_stall_from_shifter),
.o_irq(o_irq_nxt),
.o_fiq(o_fiq_nxt),
.o_instruction(o_instruction_nxt), // 40-bit, upper 4 bits RESERVED.
.o_instruction_valid(o_instruction_valid_nxt),
.o_stall_from_decode(mem_fetch_stall)
);
///////////////////////////////////////////////////////////////////////////////
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A221O_FUNCTIONAL_PP_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a221o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
// Local signals
wire B2 and0_out ;
wire B2 and1_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out, C1);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221O_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21AI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__O21AI_PP_BLACKBOX_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21AI_PP_BLACKBOX_V
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Wishbone wrapper for MCB interface
*/
module wb_mcb_32
(
input wire clk,
input wire rst,
/*
* Wishbone interface
*/
input wire [31:0] wb_adr_i, // ADR_I() address input
input wire [31:0] wb_dat_i, // DAT_I() data in
output wire [31:0] wb_dat_o, // DAT_O() data out
input wire wb_we_i, // WE_I write enable input
input wire [3:0] wb_sel_i, // SEL_I() select input
input wire wb_stb_i, // STB_I strobe input
output wire wb_ack_o, // ACK_O acknowledge output
input wire wb_cyc_i, // CYC_I cycle input
/*
* MCB interface
*/
output wire mcb_cmd_clk,
output wire mcb_cmd_en,
output wire [2:0] mcb_cmd_instr,
output wire [5:0] mcb_cmd_bl,
output wire [31:0] mcb_cmd_byte_addr,
input wire mcb_cmd_empty,
input wire mcb_cmd_full,
output wire mcb_wr_clk,
output wire mcb_wr_en,
output wire [3:0] mcb_wr_mask,
output wire [31:0] mcb_wr_data,
input wire mcb_wr_empty,
input wire mcb_wr_full,
input wire mcb_wr_underrun,
input wire [6:0] mcb_wr_count,
input wire mcb_wr_error,
output wire mcb_rd_clk,
output wire mcb_rd_en,
input wire [31:0] mcb_rd_data,
input wire mcb_rd_empty,
input wire mcb_rd_full,
input wire mcb_rd_overflow,
input wire [6:0] mcb_rd_count,
input wire mcb_rd_error
);
reg cycle_reg = 0;
reg [31:0] wb_dat_reg = 0;
reg wb_ack_reg = 0;
reg mcb_cmd_en_reg = 0;
reg mcb_cmd_instr_reg = 0;
reg mcb_wr_en_reg = 0;
reg [3:0] mcb_wr_mask_reg = 0;
assign wb_dat_o = wb_dat_reg;
assign wb_ack_o = wb_ack_reg;
assign mcb_cmd_clk = clk;
assign mcb_cmd_en = mcb_cmd_en_reg;
assign mcb_cmd_instr = mcb_cmd_instr_reg;
assign mcb_cmd_bl = 0;
assign mcb_cmd_byte_addr = wb_adr_i;
assign mcb_wr_clk = clk;
assign mcb_wr_en = mcb_wr_en_reg;
assign mcb_wr_mask = mcb_wr_mask_reg;
assign mcb_wr_data = wb_dat_i;
assign mcb_rd_clk = clk;
assign mcb_rd_en = 1;
always @(posedge clk) begin
if (rst) begin
cycle_reg <= 0;
mcb_cmd_en_reg <= 0;
mcb_cmd_instr_reg <= 0;
mcb_wr_en_reg <= 0;
end else begin
wb_ack_reg <= 0;
mcb_cmd_en_reg <= 0;
mcb_cmd_instr_reg <= 0;
mcb_wr_en_reg <= 0;
if (cycle_reg) begin
if (~mcb_rd_empty) begin
cycle_reg <= 0;
wb_dat_reg <= mcb_rd_data;
wb_ack_reg <= 1;
end
end else if (wb_cyc_i & wb_stb_i & ~wb_ack_o) begin
if (wb_we_i) begin
mcb_cmd_instr_reg <= 3'b000;
mcb_cmd_en_reg <= 1;
mcb_wr_en_reg <= 1;
mcb_wr_mask_reg <= ~wb_sel_i;
wb_ack_reg <= 1;
end else begin
mcb_cmd_instr_reg <= 3'b001;
mcb_cmd_en_reg <= 1;
cycle_reg <= 1;
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_TB_V
`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_TB_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_pwrgood_pp_g.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VGND;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VGND = 1'bX;
#20 UDP_IN = 1'b0;
#40 VGND = 1'b0;
#60 UDP_IN = 1'b1;
#80 VGND = 1'b1;
#100 UDP_IN = 1'b0;
#120 VGND = 1'b0;
#140 VGND = 1'b1;
#160 UDP_IN = 1'b1;
#180 VGND = 1'bx;
#200 UDP_IN = 1'bx;
end
sky130_fd_sc_ls__udp_pwrgood_pp$G dut (.UDP_IN(UDP_IN), .VGND(VGND), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_TB_V
|
`timescale 1 ns / 1 ps
module column_counter(
input reset,
input clk,
input push_in,
output push_out,
input [31:0] in_col_index,
output [31:0] out_col_index,
output [4:0] out_count
);
//TODO: fix counter bug
reg r_push_out;
reg [31:0] col_index;
reg [4:0] counter;
reg [5:0] timer;
reg [4:0] r_out_count;
reg [31:0] col_out_index;
always @(posedge clk) begin
if(reset) begin
timer <= 0;
r_push_out <= 0;
end else begin
r_push_out <= 0;
if(timer == 0) begin
if(push_in) begin
col_index <= in_col_index;
timer <= 1;
counter <= 0;
end
end else begin
timer <= timer + 1;
if(push_in) begin
if(col_index == in_col_index) begin
counter <= counter + 1;
timer <= timer;
end else begin
counter <= 0;
r_push_out <= 1;
r_out_count <= counter;
col_out_index <= col_index;
timer <= 1;
col_index <= in_col_index;
end
end else if(timer == 6'H3F) begin
counter <= 0;
r_push_out <= 1;
r_out_count <= counter;
col_out_index <= col_index;
timer <= 0;
end
end
end
end
assign push_out = r_push_out;
assign out_col_index = col_out_index; //TODO: questionable name
assign out_count = r_out_count;
endmodule
|
/*
* Copyright (c) 2015, Arch Laboratory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/* ----- Do not change ----- */
`define DRAM_CMD_WRITE 3'b000
`define DRAM_CMD_READ 3'b001
`define DDR2_DATA 15:0
`define DDR2_ADDR 12:0
`define DDR2_CMD 2:0
// `define APPADDR_WIDTH 29
`define APPADDR_WIDTH 27
`define APPDATA_WIDTH 128
`define APPMASK_WIDTH (`APPDATA_WIDTH / 8)
module DRAMCON(input wire CLK200M,
input wire RST_IN,
output wire CLK_OUT,
output wire RST_OUT,
// User logic interface ports
input wire [`APPADDR_WIDTH-1:0] D_ADDR,
input wire [`APPDATA_WIDTH-1:0] D_DIN,
input wire D_WE,
input wire D_RE,
output reg [`APPDATA_WIDTH-1:0] D_DOUT,
output reg D_DOUTEN,
output wire D_BUSY,
// Memory interface ports
inout wire [`DDR2_DATA] DDR2DQ,
inout wire [1:0] DDR2DQS_N,
inout wire [1:0] DDR2DQS_P,
output wire [`DDR2_ADDR] DDR2ADDR,
output wire [2:0] DDR2BA,
output wire DDR2RAS_N,
output wire DDR2CAS_N,
output wire DDR2WE_N,
output wire [0:0] DDR2CK_P,
output wire [0:0] DDR2CK_N,
output wire [0:0] DDR2CKE,
output wire [0:0] DDR2CS_N,
output wire [1:0] DDR2DM,
output wire [0:0] DDR2ODT);
// inputs of u_dram
reg [`APPADDR_WIDTH-1:0] app_addr;
reg [`DDR2_CMD] app_cmd;
reg app_en;
reg [`APPDATA_WIDTH-1:0] app_wdf_data;
reg app_wdf_end;
reg [`APPMASK_WIDTH-1:0] app_wdf_mask;
reg app_wdf_wren;
wire app_sr_req = 0; // no used
wire app_ref_req = 0; // no used
wire app_zq_req = 0; // no used
// outputs of u_dram
wire [`APPDATA_WIDTH-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid;
wire app_rdy;
wire app_wdf_rdy;
wire app_sr_active; // no used
wire app_ref_ack; // no used
wire app_zq_ack; // no used
wire ui_clk;
wire ui_clk_sync_rst;
wire init_calib_complete;
mig
u_mig (
// Memory interface ports
.ddr2_dq (DDR2DQ),
.ddr2_dqs_n (DDR2DQS_N),
.ddr2_dqs_p (DDR2DQS_P),
.ddr2_addr (DDR2ADDR),
.ddr2_ba (DDR2BA),
.ddr2_ras_n (DDR2RAS_N),
.ddr2_cas_n (DDR2CAS_N),
.ddr2_we_n (DDR2WE_N),
.ddr2_ck_p (DDR2CK_P),
.ddr2_ck_n (DDR2CK_N),
.ddr2_cke (DDR2CKE),
.ddr2_cs_n (DDR2CS_N),
.ddr2_dm (DDR2DM),
.ddr2_odt (DDR2ODT),
// Clock input ports
.sys_clk_i (CLK200M),
// Application interface ports
.app_addr (app_addr),
.app_cmd (app_cmd),
.app_en (app_en),
.app_wdf_data (app_wdf_data),
.app_wdf_end (app_wdf_end),
.app_wdf_mask (app_wdf_mask),
.app_wdf_wren (app_wdf_wren),
.app_rd_data (app_rd_data),
.app_rd_data_end (app_rd_data_end),
.app_rd_data_valid (app_rd_data_valid),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
.app_sr_req (app_sr_req),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.app_zq_ack (app_zq_ack),
.ui_clk (ui_clk),
.ui_clk_sync_rst (ui_clk_sync_rst),
.init_calib_complete (init_calib_complete),
.sys_rst (RST_IN)
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
assign D_BUSY = (mode != WAIT_REQ);
assign CLK_OUT = ui_clk;
assign RST_OUT = (ui_clk_sync_rst || ~init_calib_complete); // High Active
///// READ & WRITE PORT CONTROL (begin) //////////////////////////////////////
localparam INIT = 0; // INIT must be 0
localparam WAIT_REQ = 1;
localparam WRITE = 2;
localparam READ = 3;
reg [1:0] mode;
reg [1:0] state;
reg [3:0] cnt;
reg [`APPDATA_WIDTH-1:0] app_wdf_data_buf;
reg write_finish;
reg error_reg;
always @(posedge ui_clk) begin
if (ui_clk_sync_rst) begin
mode <= INIT;
state <= 0;
app_addr <= 0;
app_cmd <= 0;
app_en <= 0;
app_wdf_data <= 0;
app_wdf_wren <= 0;
app_wdf_mask <= 0;
app_wdf_end <= 0;
cnt <= 0;
D_DOUT <= 0;
D_DOUTEN <= 0;
write_finish <= 0;
error_reg <= 0;
end else begin
case (mode)
INIT: begin // initialize
if (init_calib_complete) mode <= WAIT_REQ;
end
WAIT_REQ: begin // wait request
app_addr <= D_ADDR;
app_en <= 0;
app_wdf_data_buf <= D_DIN;
app_wdf_mask <= {`APPMASK_WIDTH{1'b0}};
if (D_WE) mode <= WRITE;
else if (D_RE) mode <= READ;
end
WRITE: begin
case (state)
0: begin
app_cmd <= `DRAM_CMD_WRITE;
app_en <= 1;
state <= 1;
cnt <= 0;
end
1: begin
if (app_rdy) begin
app_en <= 0;
end
if (app_wdf_rdy) begin
cnt <= cnt + 1;
if (cnt == 1) begin
app_wdf_wren <= 0;
app_wdf_end <= 0;
write_finish <= 1;
end else if (cnt == 0) begin
app_wdf_data <= app_wdf_data_buf;
app_wdf_wren <= 1;
app_wdf_end <= 1;
end
end
if (!app_en && write_finish) begin
mode <= WAIT_REQ;
state <= 0;
cnt <= 0;
write_finish <= 0;
end
end
endcase
end
READ: begin
case (state)
0: begin
app_cmd <= `DRAM_CMD_READ;
app_en <= 1;
state <= 1;
cnt <= 0;
end
1: begin
if (app_rdy) app_en <= 0;
if (app_rd_data_valid) begin
if (app_rd_data_end) cnt <= 1;
D_DOUT <= app_rd_data;
end
if (!app_en && cnt) begin
state <= 2;
D_DOUTEN <= 1;
end
end
2: begin
D_DOUTEN <= 0;
mode <= WAIT_REQ;
state <= 0;
cnt <= 0;
end
endcase
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
`default_nettype wire
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_b_e
//
// Generated
// by: wig
// on: Wed Jun 7 16:54:20 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_b_e.v,v 1.4 2006/06/22 07:19:59 wig Exp $
// $Date: 2006/06/22 07:19:59 $
// $Log: inst_b_e.v,v $
// Revision 1.4 2006/06/22 07:19:59 wig
// Updated testcases and extended MixTest.pl to also verify number of created files.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
//
// Generator: mix_0.pl Revision: 1.45 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_b_e
//
// No user `defines in this module
module inst_b_e
//
// Generated Module inst_b
//
(
port_b_1
);
// Generated Module Inputs:
input port_b_1;
// Generated Wires:
wire port_b_1;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_ba
ent_ba inst_ba (
);
// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb (
);
// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of inst_b_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module bram_fifo_core #(
parameter DEPTH = 32'h8000,
parameter FIFO_ALMOST_FULL_THRESHOLD = 95, // in percent
parameter FIFO_ALMOST_EMPTY_THRESHOLD = 5, // in percent
parameter ABUSWIDTH = 32
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
input wire BUS_RD,
input wire BUS_WR,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RD_DATA,
output reg [31:0] BUS_DATA_OUT_DATA,
input wire BUS_WR_DATA,
input wire [31:0] BUS_DATA_IN_DATA,
output wire FIFO_READ_NEXT_OUT,
input wire FIFO_EMPTY_IN,
input wire [31:0] FIFO_DATA,
output wire FIFO_NOT_EMPTY,
output wire FIFO_FULL,
output reg FIFO_NEAR_FULL,
output wire FIFO_READ_ERROR
);
localparam VERSION = 2;
wire SOFT_RST; //0
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
reg [7:0] status_regs[7:0];
// reg 0 for SOFT_RST
wire [7:0] FIFO_ALMOST_FULL_VALUE;
assign FIFO_ALMOST_FULL_VALUE = status_regs[1];
wire [7:0] FIFO_ALMOST_EMPTY_VALUE;
assign FIFO_ALMOST_EMPTY_VALUE = status_regs[2];
always @(posedge BUS_CLK)
begin
if(RST)
begin
status_regs[0] <= 8'b0;
status_regs[1] <= 255*FIFO_ALMOST_FULL_THRESHOLD/100;
status_regs[2] <= 255*FIFO_ALMOST_EMPTY_THRESHOLD/100;
status_regs[3] <= 8'b0;
status_regs[4] <= 8'b0;
status_regs[5] <= 8'b0;
status_regs[6] <= 8'b0;
status_regs[7] <= 8'b0;
end
else if(BUS_WR && BUS_ADD < 8)
begin
status_regs[BUS_ADD[2:0]] <= BUS_DATA_IN;
end
end
// read reg
wire [31:0] CONF_SIZE_BYTE; // write data count, 1 - 2 - 3, in units of byte
reg [31:0] CONF_SIZE_BYTE_BUF;
reg [7:0] CONF_READ_ERROR; // read error count (read attempts when FIFO is empty), 4
wire [31:0] CONF_SIZE; // in units of int
assign CONF_SIZE_BYTE = CONF_SIZE * 4;
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT <= FIFO_ALMOST_FULL_VALUE;
else if(BUS_ADD == 2)
BUS_DATA_OUT <= FIFO_ALMOST_EMPTY_VALUE;
else if(BUS_ADD == 3)
BUS_DATA_OUT <= CONF_READ_ERROR;
else if(BUS_ADD == 4)
BUS_DATA_OUT <= CONF_SIZE_BYTE[7:0]; // in units of bytes
else if(BUS_ADD == 5)
BUS_DATA_OUT <= CONF_SIZE_BYTE_BUF[15:8];
else if(BUS_ADD == 6)
BUS_DATA_OUT <= CONF_SIZE_BYTE_BUF[23:16];
else if(BUS_ADD == 7)
BUS_DATA_OUT <= CONF_SIZE_BYTE_BUF[31:24];
else
BUS_DATA_OUT <= 8'b0;
end
end
always @(posedge BUS_CLK)
begin
if (BUS_ADD == 4 && BUS_RD)
CONF_SIZE_BYTE_BUF <= CONF_SIZE_BYTE;
end
//reg FIFO_READ_NEXT_OUT_BUF;
wire FIFO_EMPTY_IN_BUF;
wire [31:0] FIFO_DATA_BUF;
wire FULL_BUF;
assign FIFO_READ_NEXT_OUT = !FULL_BUF;
`include "../includes/log2func.v"
localparam POINTER_SIZE = `CLOG2(DEPTH);
gerneric_fifo #(
.DATA_SIZE(32),
.DEPTH(DEPTH)
) i_buf_fifo (
.clk(BUS_CLK),
.reset(RST),
.write(!FIFO_EMPTY_IN || BUS_WR_DATA),
.read(BUS_RD_DATA),
.data_in(BUS_WR_DATA ? BUS_DATA_IN_DATA : FIFO_DATA),
.full(FULL_BUF),
.empty(FIFO_EMPTY_IN_BUF),
.data_out(FIFO_DATA_BUF[31:0]),
.size(CONF_SIZE[POINTER_SIZE-1:0])
);
assign CONF_SIZE[31:POINTER_SIZE] = 0;
always @(posedge BUS_CLK)
BUS_DATA_OUT_DATA <= FIFO_DATA_BUF;
assign FIFO_NOT_EMPTY = !FIFO_EMPTY_IN_BUF;
assign FIFO_FULL = FULL_BUF;
assign FIFO_READ_ERROR = (CONF_READ_ERROR != 0);
always @(posedge BUS_CLK) begin
if(RST)
CONF_READ_ERROR <= 0;
else if(FIFO_EMPTY_IN_BUF && BUS_RD_DATA && CONF_READ_ERROR != 8'hff)
CONF_READ_ERROR <= CONF_READ_ERROR +1;
end
always @(posedge BUS_CLK) begin
/* verilator lint_off UNSIGNED */
if(RST)
FIFO_NEAR_FULL <= 1'b0;
else if (((((FIFO_ALMOST_FULL_VALUE+1)*DEPTH)>>8) <= CONF_SIZE) || (FIFO_ALMOST_FULL_VALUE == 8'b0 && CONF_SIZE >= 0))
FIFO_NEAR_FULL <= 1'b1;
else if (((((FIFO_ALMOST_EMPTY_VALUE+1)*DEPTH)>>8) >= CONF_SIZE && FIFO_ALMOST_EMPTY_VALUE != 8'b0) || CONF_SIZE == 0)
FIFO_NEAR_FULL <= 1'b0;
/* verilator lint_on UNSIGNED */
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:06:01 08/27/2015
// Design Name:
// Module Name: FPU_Add_Subtract_Function
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FPU_Add_Subtract_Function
//Add/Subtract Function Parameters
/*#(parameter W = 32, parameter EW = 8, parameter SW = 23,
parameter SWR=26, parameter EWR = 5) //Single Precision */
#(parameter W = 64, parameter EW = 11, parameter SW = 52,
parameter SWR = 55, parameter EWR = 6) //-- Double Precision */
(
//FSM Signals
input wire clk,
input wire rst,
input wire beg_FSM,
input wire ack_FSM,
//Oper_Start_in signals
input wire [W-1:0] Data_X,
input wire [W-1:0] Data_Y,
input wire add_subt,
//Round signals signals
input wire [1:0] r_mode,
//OUTPUT SIGNALS
output wire overflow_flag,
output wire underflow_flag,
output wire ready,
output wire [W-1:0] final_result_ieee
);
////////////op_start_in///////////////
wire FSM_op_start_in_load_a,FSM_op_start_in_load_b;
wire [W-2:0] DMP, DmP;
wire real_op;
wire sign_final_result;
///////////Mux S-> exp_operation OPER_A_i//////////
wire FSM_selector_A;
//D0=DMP_o[W-2:W-EW-1]
//D1=exp_oper_result
wire [EW-1:0] S_Oper_A_exp;
///////////Mux S-> exp_operation OPER_B_i//////////
wire [1:0] FSM_selector_B;
//D0=DmP_o[W-2:W-9/W-12]
//D1=LZA_output
wire [EW-1:0] S_Oper_B_exp;
///////////exp_operation///////////////////////////
wire FSM_exp_operation_load_diff, FSM_exp_operation_load_OU ,FSM_exp_operation_A_S;
//oper_A= S_Oper_A_exp
//oper_B= S_Oper_B_exp
wire [EW-1:0] exp_oper_result;
///////////Mux S-> Barrel shifter shift_Value//////
//ctrl = FSM_selector_B;
//D0=exp_oper_result
//D1=LZA_output
wire [EWR-1:0] S_Shift_Value;
///////////Mux S-> Barrel shifter Data_in//////
wire FSM_selector_C;
//D0={1'b1,DmP [SW-1:0], 2'b0}
//D1={Add_Subt_Data_output}
wire [SWR-1:0]S_Data_Shift;
///////////Barrel_Shifter//////////////////////////
wire FSM_barrel_shifter_load, FSM_barrel_shifter_L_R, FSM_barrel_shifter_B_S;
//Shift_Value=S_Shift_Value
//Data_in=S_Data_Shift
wire [SWR-1:0] Sgf_normalized_result;
//////////Mux S-> Add_Subt_Sgf op//////////////////
wire FSM_selector_D;
//D0=real_op
//D1= 1'b0
wire S_A_S_op;
//////////Mux S-> Add_Subt_Sgf OPER A//////////////////
//wire FSM_selector_D
//D0={1'b1, DMP[SW-1:0], 2'b00}
//D1= Norm_Shift_Data
wire [SWR-1:0] S_A_S_Oper_A;
//////////Mux S-> Add_Subt_Sgf OPER B//////////////////
//wire FSM_selector_D
//D0= Norm_Shift_Data
//D1= SWR'd1;
wire [SWR-1:0] S_A_S_Oper_B;
/////////ADD_Subt_sgf///////////////////////////////////
wire FSM_Add_Subt_Sgf_load, add_overflow_flag;
//Add_Subt_i=S_A_S_op
//Oper_A_i=S_A_S_Oper_A
//Oper_B_i=S_A_S_Oper_B
wire [SWR-1:0] Add_Subt_result;
wire [SWR-1:0] A_S_P;
wire [SWR-1:1] A_S_C;
//FSM_C_o=add_overflow_flag
//////////LZA///////////////////////////////////////////
wire FSM_LZA_load;
//P_i=A_S_P
//C_i=A_S_C
//A_S_op_i=S_A_S_op
wire [EWR-1:0] LZA_output;
/////////Deco_round///////////////////////////////////////
//Data_i=Sgf_normalized_result
//Round_Type=r_mode
//Sign_Result_i=sign_final_result
wire round_flag;
////////Final_result//////////////////////////////////////
wire FSM_Final_Result_load;
///////////////////////////////////////////////////////////////////////////////////
wire rst_int;
//////////////////////////////////////////////////////////////////////////////////
wire selector_A;
wire [1:0] selector_B;
wire load_b;
wire selector_C;
wire selector_D;
///////////////////////////////////////FSM/////////////////////////////////////////
FSM_Add_Subtract FS_Module(
.clk(clk), //
.rst(rst), //
.rst_FSM(ack_FSM), //
.beg_FSM(beg_FSM), //
.zero_flag_i(zero_flag), //
.norm_iteration_i(FSM_selector_C), //
.add_overflow_i(add_overflow_flag), //
.round_i(round_flag), //
.load_1_o(FSM_op_start_in_load_a), //
.load_2_o(FSM_op_start_in_load_b), //
.load_3_o(FSM_exp_operation_load_diff), //
.load_8_o(FSM_exp_operation_load_OU),
.A_S_op_o(FSM_exp_operation_A_S), //
.load_4_o(FSM_barrel_shifter_load), //
.left_right_o(FSM_barrel_shifter_L_R), //
.bit_shift_o(FSM_barrel_shifter_B_S), //
.load_5_o(FSM_Add_Subt_Sgf_load), //
.load_6_o(FSM_LZA_load), //
.load_7_o(FSM_Final_Result_load), //
.ctrl_a_o(selector_A), //
.ctrl_b_o(selector_B), //
.ctrl_b_load_o(load_b),
.ctrl_c_o(selector_C), //
.ctrl_d_o(selector_D), //
.rst_int(rst_int), //
.ready(ready) //
);
/////////////////////////////Selector's registers//////////////////////////////
RegisterAdd #(.W(1)) Sel_A ( //Selector_A register
.clk(clk),
.rst(rst_int),
.load(selector_A),
.D(1'b1),
.Q(FSM_selector_A)
);
RegisterAdd #(.W(1)) Sel_C ( //Selector_C register
.clk(clk),
.rst(rst_int),
.load(selector_C),
.D(1'b1),
.Q(FSM_selector_C)
);
RegisterAdd #(.W(1)) Sel_D ( //Selector_D register
.clk(clk),
.rst(rst_int),
.load(selector_D),
.D(1'b1),
.Q(FSM_selector_D)
);
RegisterAdd #(.W(2)) Sel_B ( //Selector_B register
.clk(clk),
.rst(rst_int),
.load(load_b),
.D(selector_B),
.Q(FSM_selector_B)
);
////////////////////////////////////////////////////////
//MODULES///////////////////////////
////////////////////Oper_Start_in//////////////////7
//This Module classify both operands
//in bigger and smaller magnitude, Calculate the result' Sign bit and calculate the real
//operation for the execution///////////////////////////////
Oper_Start_In #(.W(W)) Oper_Start_in_module (
.clk(clk),
.rst(rst_int),
.load_a_i(FSM_op_start_in_load_a),
.load_b_i(FSM_op_start_in_load_b),
.add_subt_i(add_subt),
.Data_X_i(Data_X),
.Data_Y_i(Data_Y),
.DMP_o(DMP),
.DmP_o(DmP),
.zero_flag_o(zero_flag),
.real_op_o(real_op),
.sign_final_result_o(sign_final_result)
);
///////////////////////////////////////////////////////////
///////////Mux exp_operation OPER_A_i//////////
Multiplexer_AC #(.W(EW)) Exp_Oper_A_mux(
.ctrl(FSM_selector_A),
.D0 (DMP[W-2:W-EW-1]),
.D1 (exp_oper_result),
.S (S_Oper_A_exp)
);
///////////Mux exp_operation OPER_B_i//////////
wire [EW-EWR-1:0] Exp_oper_B_D1;
wire [EW-1:0] Exp_oper_B_D2;
Mux_3x1 #(.W(EW)) Exp_Oper_B_mux(
.ctrl(FSM_selector_B),
.D0 (DmP[W-2:W-EW-1]),
.D1 ({Exp_oper_B_D1,LZA_output}),
.D2 (Exp_oper_B_D2),
.S(S_Oper_B_exp)
);
generate
case(EW)
8:begin
assign Exp_oper_B_D1 =3'd0;
assign Exp_oper_B_D2 = 8'd1;
end
default:begin
assign Exp_oper_B_D1 =5'd0;
assign Exp_oper_B_D2 = 11'd1;
end
endcase
endgenerate
///////////exp_operation///////////////////////////
Exp_Operation #(.EW(EW)) Exp_Operation_Module(
.clk(clk),
.rst(rst_int),
.load_a_i(FSM_exp_operation_load_diff),
.load_b_i(FSM_exp_operation_load_OU),
.Data_A_i(S_Oper_A_exp),
.Data_B_i(S_Oper_B_exp),
.Add_Subt_i(FSM_exp_operation_A_S),
.Data_Result_o(exp_oper_result),
.Overflow_flag_o(overflow_flag),
.Underflow_flag_o(underflow_flag)
);
//////////Mux Barrel shifter shift_Value/////////////////
wire [EWR-1:0] Barrel_Shifter_S_V_D2;
Mux_3x1 #(.W(EWR)) Barrel_Shifter_S_V_mux(
.ctrl(FSM_selector_B),
.D0 (exp_oper_result[EWR-1:0]),
.D1 (LZA_output),
.D2 (Barrel_Shifter_S_V_D2),
.S (S_Shift_Value)
);
generate
case(EW)
8:begin
assign Barrel_Shifter_S_V_D2 = 5'd1;
end
default:begin
assign Barrel_Shifter_S_V_D2 = 6'd1;
end
endcase
endgenerate
///////////Mux Barrel shifter Data_in//////
Multiplexer_AC #(.W(SWR)) Barrel_Shifter_D_I_mux(
.ctrl(FSM_selector_C),
.D0 ({1'b1,DmP[SW-1:0],2'b00}),
.D1 (Add_Subt_result),
.S (S_Data_Shift)
);
///////////Barrel_Shifter//////////////////////////
Barrel_Shifter #(.SWR(SWR),.EWR(EWR)) Barrel_Shifter_module (
.clk(clk),
.rst(rst_int),
.load_i(FSM_barrel_shifter_load),
.Shift_Value_i(S_Shift_Value),
.Shift_Data_i(S_Data_Shift),
.Left_Right_i(FSM_barrel_shifter_L_R),
.Bit_Shift_i(FSM_barrel_shifter_B_S),
.N_mant_o(Sgf_normalized_result)
);
//////////Mux Add_Subt_Sgf op//////////////////
Multiplexer_AC #(.W(1)) Add_Sub_Sgf_op_mux(
.ctrl(FSM_selector_D),
.D0 (real_op),
.D1 (1'b0),
.S (S_A_S_op)
);
//////////Mux Add_Subt_Sgf oper A//////////////////
Multiplexer_AC #(.W(SWR)) Add_Sub_Sgf_Oper_A_mux(
.ctrl(FSM_selector_D),
.D0 ({1'b1,DMP[SW-1:0],2'b00}),
.D1 (Sgf_normalized_result),
.S (S_A_S_Oper_A)
);
//////////Mux Add_Subt_Sgf oper B//////////////////
wire [SWR-1:0] Add_Sub_Sgf_Oper_A_D1;
Multiplexer_AC #(.W(SWR)) Add_Sub_Sgf_Oper_B_mux(
.ctrl(FSM_selector_D),
.D0 (Sgf_normalized_result),
.D1 (Add_Sub_Sgf_Oper_A_D1),
.S (S_A_S_Oper_B)
);
generate
case (W)
32:begin
assign Add_Sub_Sgf_Oper_A_D1 = 26'd4;
end
default:begin
assign Add_Sub_Sgf_Oper_A_D1 =55'd4;
end
endcase
endgenerate
/////////ADD_Subt_sgf///////////////////////////////////
Add_Subt #(.SWR(SWR)) Add_Subt_Sgf_module(
.clk(clk),
.rst(rst_int),
.load_i(FSM_Add_Subt_Sgf_load),
.Add_Sub_op_i(S_A_S_op),
.Data_A_i(S_A_S_Oper_A),
.PreData_B_i(S_A_S_Oper_B),
.Data_Result_o(Add_Subt_result),
//.P_o(A_S_P),
//.Cn_o(A_S_C),
.FSM_C_o(add_overflow_flag)
);
/*
//Test Comb LZA//
Test_comb_LZA #(.SWR(SWR)) comb(
.clk(clk),
.rst(rst),
.Op_A_i(S_A_S_Oper_A),
.Pre_Op_B_i(S_A_S_Oper_B),
.op(S_A_S_op), //Carry in
.Cn_o(A_S_C),
.P_o(A_S_P) //Propagate (for LZA)
);
//////////LZA///////////////////////////////////////////
LZA #(.SWR(SWR),.EWR(EWR)) Leading_Zero_Anticipator_Module (
.clk(clk),
.rst(rst_int),
.load_i(FSM_LZA_load),
.P_i(A_S_P),
.C_i(A_S_C),
.A_S_op_i(S_A_S_op),
.Shift_Value_o(LZA_output)
);
*/
wire [SWR-1:0] Add_Subt_LZD;
assign Add_Subt_LZD = ~Add_Subt_result;
LZD #(.SWR(SWR),.EWR(EWR)) Leading_Zero_Detector_Module (
.clk(clk),
.rst(rst_int),
.load_i(FSM_LZA_load),
.Add_subt_result_i(Add_Subt_LZD),
.Shift_Value_o(LZA_output)
);
/////////Deco_round///////////////////////////////////////
Round_Sgf_Dec Rounding_Decoder(
.Data_i(Sgf_normalized_result[1:0]),
.Round_Type_i(r_mode),
.Sign_Result_i(sign_final_result),
.Round_Flag_o(round_flag)
);
////////Final_result//////////////////////////////////////
Tenth_Phase #(.W(W),.EW(EW),.SW(SW)) final_result_ieee_Module(
.clk(clk),
.rst(rst_int),
.load_i(FSM_Final_Result_load),
.sel_a_i(overflow_flag),
.sel_b_i(underflow_flag),
.sign_i(sign_final_result),
.exp_ieee_i(exp_oper_result),
.sgf_ieee_i(Sgf_normalized_result[SWR-2:2]),
.final_result_ieee_o(final_result_ieee)
);
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 4
(* X_CORE_INFO = "axi_protocol_converter_v2_1_axi_protocol_converter,Vivado 2014.4.1" *)
(* CHECK_LICENSE_TYPE = "tutorial_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "tutorial_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=1,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module tutorial_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [0 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [63 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [7 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [0 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [0 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [0 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [63 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [3 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WID" *)
output wire [0 : 0] m_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [3 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [1 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(1),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(m_axi_wid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
`default_nettype none
module serial_wb_mcu(
// System signals
clk_i, rst_i,
// Program memory address, instruction from program memory
pm_addr_o, pm_insn_i,
// Data port 0 and 1 (out)
port0_o,
port1_o,
strobe1_o,
// Data port 0 and 1 (in)
port2_i,
strobe2_o
);
input clk_i;
input rst_i;
output [9:0] pm_addr_o;
input [15:0] pm_insn_i;
output reg [7:0] port0_o;
output reg [7:0] port1_o;
output strobe1_o;
input wire [7:0] port2_i;
output strobe2_o;
wire clk_i;
wire rst_i;
reg [9:0] pm_addr_o;
wire [15:0] pm_insn_i;
reg strobe1_o;
reg strobe2_o;
reg [7:0] port2_r;
reg [15:0] insnreg;
// Internal registers and wires:
//
// Register file (16x8 bit registers)
reg [7:0] regfile[15:0];
reg [7:0] rf_op_a;
reg [7:0] rf_op_b;
reg rf_w; // Writeback enable
reg [7:0] rf_result; // Writeback input
reg [3:0] rf_index_r; // Writeback register
// ALU
reg [8:0] alu_result;
reg alu_flag_z;
reg alu_flag_c;
// Program counter
reg [8:0] pc;
// 2 slot stack for PC
reg [8:0] returnpc_0; // Return address from a jsr
reg [8:0] next_returnpc_0;
reg [8:0] returnpc_1; // Return address from a jsr
reg [8:0] next_returnpc_1;
// Instructions ( *tested means that it is tested in the testbench)
// Register modification group
// 0x0000ddddssssSSSS Rd = Rs + RS (set flags)
// 0x0001ddddssssSSSS Rd = Rs ^ RS (set flags)
// 0x0010ddddssssSSSS Rd = Rs & RS (set flags)
// 0x0011ddddssssSSSS Rd = Rs | RS (set flags)
// 0x0100ddddiiiiiiii Rd = immediate
// 0x0101dddd00000000 Rd = Port 2
// 0x0110dddd00000000 Rd = Address[port0+768]
// 0x0111ddddssss0000 Rd = Swap nibbles(Rs)
// Jump/misc group
// 0x1000000aaaaaaaaa Jump to address a
// 0x1000001aaaaaaaaa Jump to address a if zero
// 0x1000010aaaaaaaaa Jump to address a if carry
// 0x1000011aaaaaaaaa Jump to subroutine
// 0x1000100000000000 Return from subroutine
// 0x10010000ssss0000 Port 0 = Rs
// 0x10010001ssss0000 Port 1 = Rs
always @(posedge clk_i) begin
port2_r <= port2_i;
end
reg [7:0] from_pm_r;
always @(posedge clk_i) begin
if(!rf_op_b[0]) begin
from_pm_r <= pm_insn_i[15:8];
end else begin
from_pm_r <= pm_insn_i[7:0];
end
end
// Writeback
always @(posedge clk_i)
if(rst_i) begin
end else begin
if(rf_w)
regfile[rf_index_r] <= rf_result;
end
wire [7:0] rf_output;
// Decode operands
assign rf_output = regfile[rf_index_r];
localparam [1:0] FETCH = 2'd0; // Fetch INSN && Writeback
localparam [1:0] DECODE1 = 2'd1; // Fetch OP1
localparam [1:0] DECODE2 = 2'd2; // Fetch OP2
localparam [1:0] EXECUTE = 2'd3; // Execute
reg [1:0] state_r;
always @(posedge clk_i)
if(rst_i) begin
$display("In reset");
state_r <= FETCH;
end else begin
case(state_r)
FETCH: state_r <= DECODE1;
DECODE1: state_r <= DECODE2;
DECODE2: state_r <= EXECUTE;
EXECUTE: state_r <= FETCH;
endcase // case(state_r)
end
always @(posedge clk_i)
if(rst_i) begin
insnreg <= 16'hffff;
end else begin
if(state_r == FETCH) begin
insnreg <= pm_insn_i;
if(pm_insn_i == 16'hfffe) begin
$display("Breakpoint!");
$stop;
end
end
end
always @*
case(state_r)
FETCH: rf_index_r = insnreg[11:8];
DECODE1: rf_index_r = insnreg[7:4];
DECODE2: rf_index_r = insnreg[3:0];
default: rf_index_r = insnreg[3:0];
endcase // case(state_r)
always @(posedge clk_i) begin
if(state_r == DECODE1) rf_op_a <= rf_output;
if(state_r == DECODE2) rf_op_b <= rf_output;
end
always @* begin
if(state_r == DECODE1) begin
pm_addr_o = {rf_op_a[2:0],rf_op_b[7:1]};
// pm_addr_o = {2'b11, port0_o[7:1]};
end else begin
pm_addr_o = pc;
end
end // UNMATCHED !!
always @(posedge clk_i)
if(rst_i) begin
pc <= 0;
returnpc_0 <= 0;
returnpc_1 <= 0;
end else begin
if(state_r == FETCH) begin
pc <= pc + 1;
end else if(state_r == DECODE1) begin
if(insnreg[15:12] == 4'b1000) begin
case(insnreg[11:9])
3'b000:
pc <= insnreg[8:0];
3'b001:
if(alu_flag_z)
pc <= insnreg[8:0];
3'b010:
if(alu_flag_c)
pc <= insnreg[8:0];
3'b011: begin
pc <= insnreg[8:0];
returnpc_0 <= pc;
returnpc_1 <= returnpc_0;
end
default: begin
pc <= returnpc_0;
returnpc_0 <= returnpc_1;
end
endcase // case(insnreg[11:9])
end // if (insnreg[15:12] == 4'b1000)
end
end // else: !if(rst_i)
// Output ports:
always @(posedge clk_i)
if(rst_i) begin
port0_o <= 0;
port1_o <= 0;
strobe1_o <= 0;
end else begin
strobe1_o <= 0;
if(state_r == EXECUTE) begin
if(insnreg[15:12] == 4'b1001) begin
if(insnreg[8] == 0) begin
port0_o <= rf_op_a;
end else begin
strobe1_o <= 1;
port1_o <= rf_op_a;
end
end
end
end // else: !if(rst_i)
reg [7:0] alu_result_r;
// ALU
always @*
case(insnreg[13:12])
2'b00: alu_result = { 1'b0 , rf_op_a} + {1'b0, rf_op_b};
2'b01: alu_result = rf_op_a ^ rf_op_b;
2'b10: alu_result = rf_op_a & rf_op_b;
default: alu_result = rf_op_a | rf_op_b;
endcase // case(pm_insn[13:12])
// Flag generation
always @(posedge clk_i)
if(rst_i) begin
alu_result_r <= 8'b0;
end else begin
alu_result_r <= alu_result;
// Check to see if it is an ALU op
end // else: !if(rst_i)
always @(posedge clk_i)
if(rst_i) begin
alu_flag_c <= 0;
alu_flag_z <= 0;
strobe2_o <= 1'b0;
rf_w <= 0;
end else begin
strobe2_o <= 1'b0;
rf_w <= 0;
if(state_r == DECODE1) begin
if(insnreg[15:12] == 4'b0101) begin
strobe2_o <= 1'b1;
end
end else if(state_r == EXECUTE) begin
case(insnreg[15:14])
2'b00: begin // ALU operation
rf_result <= alu_result;
rf_w <= 1;
alu_flag_c <= alu_result[8];
if(alu_result[7:0] == 0) // Don't need ALU_flags just now...
alu_flag_z <= 1;
else
alu_flag_z <= 0;
end
2'b01: begin
rf_w <= 1;
case(insnreg[13:12])
2'b00: begin
rf_result <= insnreg[7:0];
end
2'b01: begin
rf_result <= port2_r;
end
2'b10: begin
rf_result <= from_pm_r;
end
default: begin
rf_result <= {rf_op_a[3:0], rf_op_a[7:4]};
end
endcase // case(insnreg[13:12])
end
default: begin
rf_w <= 0;
end
endcase // case(insnreg[15:14])
end
end
endmodule // mcu
|
/*
* University of Illinois/NCSA
* Open Source License
*
* Copyright (c) 2007-2014,The Board of Trustees of the University of
* Illinois. All rights reserved.
*
* Copyright (c) 2014 Matthew Hicks
*
* Developed by:
*
* Matthew Hicks in the Department of Computer Science
* The University of Illinois at Urbana-Champaign
* http://www.impedimentToProgress.com
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated
* documentation files (the "Software"), to deal with the
* Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimers.
*
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimers in the documentation and/or other
* materials provided with the distribution.
*
* Neither the names of Sam King, the University of Illinois,
* nor the names of its contributors may be used to endorse
* or promote products derived from this Software without
* specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS WITH THE SOFTWARE.
*/
`ifdef SMV
`include "../or1200/or1200_defines.v"
`else
`include "or1200_defines.v"
`endif
module ovl_combo_wrapped(
clk,
rst,
enable,
num_cks,
start_event,
test_expr,
select,
prevConfigInvalid,
out,
out_delayed,
configInvalid
);
parameter num_cks_max = 7;
parameter num_cks_width = 3;
input clk;
input rst;
input enable;
input [num_cks_width-1:0] num_cks;
input start_event;
input test_expr;
input [1:0] select;
input prevConfigInvalid;
output out;
output out_delayed;
output configInvalid;
reg out_delayed;
wire [2:0] result_3bit_comb;
`ifdef SMV
ovl_combo ovl_combo (.num_cks_max(7),
.num_cks_width(3),
.clock(clk),
.reset(rst),
.enable(enable),
.num_cks(num_cks),
.start_event(start_event),
.test_expr(test_expr),
.select(select),
.fire_comb(result_3bit_comb)
);
`else // !`ifdef SMV
ovl_combo #(
.num_cks_max(7),
.num_cks_width(3)
) ovl_combo(
.clock(clk),
.reset(rst),
.enable(enable),
.num_cks(num_cks),
.start_event(start_event),
.test_expr(test_expr),
.select(select),
.fire_comb(result_3bit_comb)
);
`endif // !`ifdef SMV
always @(posedge clk)
if(rst == `OR1200_RST_VALUE)
out_delayed <= 1'b0;
else if(enable)
out_delayed <= result_3bit_comb[0];
// It is invalid if num_cks == 0 and next or on edge format selected
//(CKS) Fixed a bug! was prevConfigInvalid & ...
assign configInvalid = prevConfigInvalid | (~|num_cks & ~select[1]);
//(CKS) I added the &configInvalid
assign out = result_3bit_comb[0];
endmodule
|
`include "logfunc.h"
// dense 1 port SRAM:
//
// dense means 2 cycle read/write
//
// Max total bits is 32Kbytes (Size*Width)
//
// Size must be between 32 and 1024
module ram_1port_dense #(parameter Width = 64, Size=128, Forward=0)(
input clk
,input reset
,input req_valid
,output req_retry
,input req_we
,input [`log2(Size)-1:0] req_pos
,input [Width-1:0] req_data
,output ack_valid
,input ack_retry
,output [Width-1:0] ack_data
);
logic [Width-1:0] ack_data_next;
async_ram_1port
#(.Width(Width), .Size(Size))
ram (
.p0_pos (req_pos)
,.p0_enable (req_valid & req_we)
,.p0_in_data (req_data)
,.p0_out_data (ack_data_next)
);
logic last_busy;
logic req_retry_next;
always_comb begin
// If it is a write, the retry has no effect. We can write one per cycle
// (token consumed)
req_retry = (req_retry_next & !req_we) | last_busy;
end
logic [Width-1:0] ack_n1_data;
logic ack_n1_valid;
logic ack_n1_retry;
always @(posedge clk) begin
if (reset) begin
last_busy <= 0;
end else begin
if (last_busy) begin
last_busy <= 0;
end else begin
last_busy <= req_valid;
end
end
end
fflop #(.Size(Width)) f1 (
.clk (clk),
.reset (reset),
.din (ack_data_next),
.dinValid ((req_valid & ~req_we) & ~last_busy),
.dinRetry (req_retry_next),
.q (ack_n1_data),
.qValid (ack_n1_valid),
.qRetry (ack_n1_retry)
);
fflop #(.Size(Width)) f2 (
.clk (clk),
.reset (reset),
.din (ack_n1_data),
.dinValid (ack_n1_valid),
.dinRetry (ack_n1_retry),
.q (ack_data),
.qValid (ack_valid),
.qRetry (ack_retry)
);
endmodule
|
// Driver for an LCD TFT display. Specifically, this was written to drive
// the AdaFruit YX700WV03, which is an 800x480 7" display. It's driven
// like a VGA monitor, but with digital color values, a data enable signal,
// and a clock.
module LCD_control(
input wire clock, // System clock.
input wire tick, // LCD clock (synchronous with system clock).
input wire reset_n, // Asynchronous reset, active low.
output reg [9:0] x, // On-screen X pixel location.
output reg [9:0] y, // On-screen Y pixel location.
output reg next_frame, // 1 when between frames (one clock).
output reg hs_n, // Horizontal sync, active low.
output reg vs_n, // Vertical sync, active low.
output reg data_enable // Whether we need a pixel right now.
);
// There are two internal registers, h and v. They are 0-based.
// The h value has these ranges:
//
// h hs_n
// [0, H_FRONT) 1 (front porch)
// [H_FRONT, H_FRONT + H_SYNC) 0 (sync pulse)
// [H_FRONT + H_SYNC, H_BLANK) 1 (back porch)
// [H_BLANK, H_TOTAL) 1 (pixels are visible)
//
// The v value has these ranges:
//
// v vs_n
// [0, V_FRONT) 1 (front porch)
// [V_FRONT, V_FRONT + V_SYNC) 0 (sync pulse)
// [V_FRONT + V_SYNC, V_BLANK) 1 (back porch)
// [V_BLANK, V_TOTAL) 1 (pixels are visible)
//
// next_frame is on the second pixel of the first row.
// Video parameters.
parameter H_FRONT = 24;
parameter H_SYNC = 72;
parameter H_BACK = 96;
parameter H_ACT = 800;
parameter H_BLANK = H_FRONT + H_SYNC + H_BACK;
parameter H_TOTAL = H_FRONT + H_SYNC + H_BACK + H_ACT;
parameter V_FRONT = 3;
parameter V_SYNC = 10;
parameter V_BACK = 7;
parameter V_ACT = 480;
parameter V_BLANK = V_FRONT + V_SYNC + V_BACK;
parameter V_TOTAL = V_FRONT + V_SYNC + V_BACK + V_ACT;
reg [10:0] h;
reg [10:0] v;
wire h_visible = h >= H_BLANK;
/* verilator lint_off UNSIGNED */
wire v_visible = v >= V_BLANK;
/* verilator lint_on UNSIGNED */
/* verilator lint_off UNUSED */
wire [10:0] h_normalized = h - H_BLANK;
wire [10:0] v_normalized = v - V_BLANK;
/* verilator lint_on UNUSED */
// Latch the next_frame register. This will be true for one (tick) clock
// a few rows after the last visible pixel.
always @(posedge clock) begin
if (tick) begin
// Don't do it right away after the end of the previous frame,
// that might cause problems if some logic isn't quite done
// dealing with the color. Wait a few rows.
next_frame <= h == 0 && v == V_FRONT;
end
end
// Walk through screen.
always @(posedge clock or negedge reset_n) begin
if (!reset_n) begin
h <= 0;
v <= 0;
hs_n <= 1;
vs_n <= 1;
x <= 0;
y <= 0;
data_enable <= 0;
end else if (tick) begin
// Advance pixel.
if (h < H_TOTAL - 1) begin
h <= h + 1'b1;
end else begin
// Next line.
h <= 0;
if (v < V_TOTAL - 1) begin
v <= v + 1'b1;
end else begin
v <= 0;
end
// Vertical sync.
if (v == V_FRONT - 1) begin
// Front porch end, sync pulse start.
vs_n <= 1'b0;
end
if (v == V_FRONT + V_SYNC - 1) begin
// Sync pulse end, back porch start.
vs_n <= 1'b1;
end
end
// Horizontal sync.
if (h == H_FRONT - 1) begin
// Front porch end, sync pulse start.
hs_n <= 1'b0;
end
if (h == H_FRONT + H_SYNC - 1) begin
// Sync pulse end, back porch start.
hs_n <= 1'b1;
end
// Latch output registers. These are delayed from the h and
// v values.
x <= h_visible ? h_normalized[9:0] : 10'h0;
y <= v_visible ? v_normalized[9:0] : 10'h0;
data_enable <= h_visible && v_visible;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__MUX2_PP_BLACKBOX_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2_PP_BLACKBOX_V
|
//
// usb 3.0 endpoint 0
//
// Copyright (c) 2013 Marshall H.
// All rights reserved.
// This code is released under the terms of the simplified BSD license.
// See LICENSE.TXT for details.
//
module usb3_ep0 (
input wire slow_clk,
input wire local_clk,
input wire reset_n,
input wire [8:0] buf_in_addr,
input wire [31:0] buf_in_data,
input wire buf_in_wren,
output wire buf_in_ready,
input wire buf_in_commit,
input wire [10:0] buf_in_commit_len,
output wire buf_in_commit_ack,
input wire [8:0] buf_out_addr,
output wire [31:0] buf_out_q,
output wire [10:0] buf_out_len,
output wire buf_out_hasdata,
input wire buf_out_arm,
output wire buf_out_arm_ack,
output reg vend_req_act,
output reg [7:0] vend_req_request,
output reg [15:0] vend_req_val,
output reg [15:0] vend_req_index,
//output reg [15:0] vend_req_len,
output reg [6:0] dev_addr,
output reg configured,
output reg reset_dp_seq,
output reg err_setup_pkt
);
`include "usb3_const.v"
`include "usb_descrip.v"
reg buf_in_commit_1, buf_in_commit_2;
reg buf_out_arm_1, buf_out_arm_2;
reg [63:0] packet_setup;
wire [7:0] packet_setup_reqtype = packet_setup[63:56];
wire packet_setup_dir = packet_setup_reqtype[7];
parameter SETUP_DIR_HOSTTODEV = 1'b0,
SETUP_DIR_DEVTOHOST = 1'b1;
wire [1:0] packet_setup_type = packet_setup_reqtype[6:5];
parameter [1:0] SETUP_TYPE_STANDARD = 2'h0,
SETUP_TYPE_CLASS = 2'h1,
SETUP_TYPE_VENDOR = 2'h2,
SETUP_TYPE_RESVD = 2'h3;
wire [4:0] packet_setup_recpt = packet_setup_reqtype[4:0];
parameter [4:0] SETUP_RECPT_DEVICE = 5'h0,
SETUP_RECPT_IFACE = 5'h1,
SETUP_RECPT_ENDP = 5'h2,
SETUP_RECPT_OTHER = 5'h3;
wire [7:0] packet_setup_req = packet_setup[55:48];
parameter [7:0] REQ_GET_STATUS = 8'h0,
REQ_CLEAR_FEAT = 8'h1,
REQ_SET_FEAT = 8'h3,
REQ_SET_ADDR = 8'h5,
REQ_GET_DESCR = 8'h6,
REQ_SET_DESCR = 8'h7,
REQ_GET_CONFIG = 8'h8,
REQ_SET_CONFIG = 8'h9,
REQ_SET_INTERFACE = 8'hB,
REQ_SYNCH_FRAME = 8'h12,
REQ_SET_SEL = 8'h30;
wire [15:0] packet_setup_wval = {packet_setup[39:32], packet_setup[47:40]};
wire [15:0] packet_setup_widx = {packet_setup[23:16], packet_setup[31:24]};
wire [15:0] packet_setup_wlen = {packet_setup[7:0], packet_setup[15:8]};
reg [10:0] desired_out_len;
reg [10:0] packet_out_len;
reg [3:0] dev_config;
reg ptr_in;
reg ptr_out;
reg [10:0] len_in;
reg ready_in;
assign buf_in_ready = ready_in;
assign buf_in_commit_ack = (state_in == ST_IN_COMMIT);
reg [10:0] len_out;
reg hasdata_out;
assign buf_out_len = len_out;
assign buf_out_hasdata = hasdata_out;
assign buf_out_arm_ack = (state_out == ST_OUT_ARM);
reg [6:0] dc;
reg [5:0] state_in;
parameter [5:0] ST_RST_0 = 6'd0,
ST_RST_1 = 6'd1,
ST_IDLE = 6'd10,
ST_IN_COMMIT = 6'd11,
ST_IN_SWAP = 6'd20,
ST_IN_PARSE_0 = 6'd21,
ST_IN_PARSE_1 = 6'd22,
ST_REQ_DESCR = 6'd30,
ST_RDLEN_0 = 6'd31,
ST_RDLEN_1 = 6'd32,
ST_RDLEN_2 = 6'd33,
ST_RDLEN_3 = 6'd34,
ST_REQ_GETCONFIG = 6'd35,
ST_REQ_SETCONFIG = 6'd36,
ST_REQ_SETINTERFACE = 6'd37,
ST_REQ_SETADDR = 6'd38,
ST_REQ_VENDOR = 6'd39,
ST_REQ_SETSEL = 6'd40,
ST_REQ_SETFEAT = 6'd41,
ST_REQ_CLRFEAT = 6'd42;
reg [5:0] state_out;
parameter [5:0] ST_OUT_ARM = 6'd11,
ST_OUT_SWAP = 6'd20;
always @(posedge local_clk) begin
{buf_in_commit_2, buf_in_commit_1} <= {buf_in_commit_1, buf_in_commit};
{buf_out_arm_2, buf_out_arm_1} <= {buf_out_arm_1, buf_out_arm};
configured <= dev_config ? 1'b1 : 1'b0;
reset_dp_seq <= 0;
`INC(dc);
// clear act strobe after 4 cycles
if(dc == 3) vend_req_act <= 1'b0;
// main fsm
case(state_in)
ST_RST_0: begin
len_out <= 0;
desired_out_len <= 0;
dev_addr <= 0;
dev_config <= 0;
err_setup_pkt <= 0;
ready_in <= 1;
state_in <= ST_RST_1;
end
ST_RST_1: begin
state_in <= ST_IDLE;
end
ST_IDLE: begin
// idle state
if(buf_in_commit_1 & ~buf_in_commit_2) begin
// link/protocol layer has written to this endpoint
len_in <= buf_in_commit_len;
ready_in <= 0;
dc <= 0;
state_in <= ST_IN_COMMIT;
end
end
ST_IN_COMMIT: begin
// generate ACK pulse
if(dc == 3) begin
dc <= 0;
buf_in_rdaddr <= 0;
state_in <= ST_IN_PARSE_0;
end
end
ST_IN_PARSE_0: begin
// parse setup packet
`INC(buf_in_rdaddr);
packet_setup <= {packet_setup[31:0], buf_in_q[31:0]};
if(dc == (2+2-1)) state_in <= ST_IN_PARSE_1;
end
ST_IN_PARSE_1: begin
// parse setup packet
packet_out_len <= packet_setup_wlen;
// confirm this is going in the right direction
//if(packet_setup_dir != SETUP_DIR_DEVTOHOST) begin
// err_setup_pkt <= 1;
// state <= 10;
//end else begin
if(packet_setup_type == SETUP_TYPE_VENDOR) begin
// parse vendor request
state_in <= ST_REQ_VENDOR;
end else begin
// proceed with parsing
case(packet_setup_req)
REQ_GET_DESCR: begin
state_in <= ST_REQ_DESCR;
end
REQ_GET_CONFIG: begin
state_in <= ST_REQ_GETCONFIG;
end
REQ_SET_CONFIG: begin
state_in <= ST_REQ_SETCONFIG;
end
REQ_SET_INTERFACE: begin
state_in <= ST_REQ_SETINTERFACE;
end
REQ_SET_ADDR: begin
state_in <= ST_REQ_SETADDR;
end
REQ_SET_FEAT: begin
state_in <= ST_REQ_SETFEAT;
end
REQ_CLEAR_FEAT: begin
state_in <= ST_REQ_CLRFEAT;
end
REQ_SET_SEL: begin
state_in <= ST_REQ_SETSEL;
end
default: begin
ready_in <= 1;
state_in <= ST_IDLE;
end
endcase
end
end
ST_REQ_DESCR: begin
state_in <= ST_RDLEN_0;
// GET_DESCRIPTOR
case(packet_setup_wval)
16'h0100: begin
// device descriptor
descrip_addr_offset <= DESCR_USB3_DEVICE;
end
16'h0200: begin
// config descriptor
descrip_addr_offset <= DESCR_USB3_CONFIG;
desired_out_len <= DESCR_USB3_CONFIG_LEN;
state_in <= ST_RDLEN_3;
end
16'h0300: begin
// string: languages
descrip_addr_offset <= DESCR_USB3_STRING0;
end
16'h0301: begin
// string: manufacturer
descrip_addr_offset <= DESCR_USB3_STRING1;
end
16'h0302: begin
// string: product name
descrip_addr_offset <= DESCR_USB3_STRING2;
end
16'h0303: begin
// string: serial number
descrip_addr_offset <= DESCR_USB3_STRING3;
end
//16'h0600: begin
// device qualifier descriptor
//descrip_addr_offset <= DESCR_OFF_DEVQUAL;
//end
16'h0f00: begin
// BOS #0
descrip_addr_offset <= DESCR_USB3_BOS;
desired_out_len <= DESCR_USB3_BOS_LEN;
state_in <= ST_RDLEN_3;
end
default: begin
packet_out_len <= 0;
end
endcase
end
ST_RDLEN_0: begin
// wait cycle if descriptor BRAM has a buffered output
state_in <= ST_RDLEN_1;
end
ST_RDLEN_1: begin
// wait cycle if descriptor BRAM has a buffered output
state_in <= ST_RDLEN_2;
end
ST_RDLEN_2: begin
// pick off the first byte at the pointer
desired_out_len <= buf_out_q[31:24];
state_in <= ST_RDLEN_3;
end
ST_RDLEN_3: begin
// pick smaller of the setup packet's wanted length and the stored length
len_out <= packet_out_len < desired_out_len ? packet_out_len : desired_out_len;
// send response
ready_in <= 1;
hasdata_out <= 1;
state_in <= ST_IDLE;
end
ST_REQ_GETCONFIG: begin
// GET DEVICE CONFIGURATION
// send 1byte response
len_out <= 1;
ready_in <= 1;
hasdata_out <= 1;
descrip_addr_offset <= dev_config ? DESCR_USB3_CONFSET : DESCR_USB3_CONFUNSET;
state_in <= ST_IDLE;
end
ST_REQ_SETCONFIG: begin
// SET DEVICE CONFIGURATION
dev_config <= packet_setup_wval[6:0];
reset_dp_seq <= 1;
// send 0byte response
len_out <= 0;
ready_in <= 1;
hasdata_out <= 1;
state_in <= ST_IDLE;
end
ST_REQ_SETINTERFACE: begin
// SET INTERFACE
//dev_config <= packet_setup_wval[6:0];
reset_dp_seq <= 1;
// send 0byte response
len_out <= 0;
ready_in <= 1;
hasdata_out <= 1;
state_in <= ST_IDLE;
end
ST_REQ_SETADDR: begin
// SET DEVICE ADDRESS
dev_addr <= packet_setup_wval[6:0];
// send 0byte response
len_out <= 0;
ready_in <= 1;
hasdata_out <= 1;
state_in <= ST_IDLE;
end
ST_REQ_VENDOR: begin
// VENDOR REQUEST
vend_req_request <= packet_setup_req;
vend_req_val <= packet_setup_wval;
vend_req_index <= packet_setup_widx;
// optional data stage for bidir control transfers
// would require additional unsupported code in this endpoint
//vend_req_len <= packet_setup_wlen;
// signal to external interface there was a vend_req
vend_req_act <= 1'b1;
dc <= 0;
// send 0byte response
len_out <= 0;
ready_in <= 1;
hasdata_out <= 1;
state_in <= ST_IDLE;
end
ST_REQ_SETSEL: begin
// send 0byte response
len_out <= 0;
ready_in <= 1;
hasdata_out <= 1;
state_in <= ST_IDLE;
end
ST_REQ_SETFEAT: begin
// U1/U2 Enable; parse wValue TODO
len_out <= 0;
ready_in <= 1;
hasdata_out <= 1;
state_in <= ST_IDLE;
end
ST_REQ_CLRFEAT: begin
reset_dp_seq <= 1;
len_out <= 0;
ready_in <= 1;
hasdata_out <= 1;
state_in <= ST_IDLE;
end
default: state_in <= ST_RST_0;
endcase
// output FSM
//
case(state_out)
ST_RST_0: begin
hasdata_out <= 0;
// configure default state
state_out <= ST_RST_1;
end
ST_RST_1: begin
state_out <= ST_IDLE;
end
ST_IDLE: begin
// idle state
if(buf_out_arm_1 & ~buf_out_arm_2) begin
// free up this endpoint
dc <= 0;
state_out <= ST_OUT_ARM;
end
end
ST_OUT_ARM: begin
// generate ARM_ACK pulse, several cycles for compat with slower FSMs
if(dc == 3) begin
state_out <= ST_OUT_SWAP;
end
end
ST_OUT_SWAP: begin
// this endpoint is not double buffered!
// current buffer is now ready for data
ready_in <= 1;
// update hasdata status
hasdata_out <= 0;
state_out <= ST_IDLE;
end
default: state_out <= ST_RST_0;
endcase
if(~reset_n) begin
// reset
state_in <= ST_RST_0;
state_out <= ST_RST_0;
end
end
reg [3:0] buf_in_rdaddr;
wire [31:0] buf_in_q;
usb3_ep0in_ram iu3ep0i (
.clk ( local_clk ),
.wr_dat_w ( buf_in_data ),
.rd_adr ( buf_in_rdaddr ),
.wr_adr ( buf_in_addr ),
.wr_we ( buf_in_wren ),
.rd_dat_r ( buf_in_q )
);
reg [7:0] descrip_addr_offset;
usb3_descrip_rom iu3d (
.clk ( local_clk ),
.adr ( buf_out_addr + descrip_addr_offset),
.dat_r ( buf_out_q )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31A_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O31A_BEHAVIORAL_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o31a (
X ,
A1,
A2,
A3,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31A_BEHAVIORAL_V |
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email: [email protected]
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module top
(
// Clocking & Reset
input clk_i,
input rst_i,
// Fault Output
output fault_o,
// Break Output
output break_o,
// Interrupt Input
input intr_i
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter CLK_KHZ = 8192;
parameter BOOT_VECTOR = 32'h10000000;
parameter ISR_VECTOR = 32'h10000000;
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire [31:0] soc_addr;
wire [31:0] soc_data_w;
wire [31:0] soc_data_r;
wire soc_we;
wire soc_stb;
wire soc_ack;
wire soc_irq;
wire[31:0] dmem_address;
wire[31:0] dmem_data_w;
wire[31:0] dmem_data_r;
wire[3:0] dmem_sel;
wire[2:0] dmem_cti;
wire dmem_we;
wire dmem_stb;
wire dmem_cyc;
wire dmem_stall;
wire dmem_ack;
wire[31:0] imem_addr;
wire[31:0] imem_data;
wire[3:0] imem_sel;
wire imem_stb;
wire imem_cyc;
wire[2:0] imem_cti;
wire imem_stall;
wire imem_ack;
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
ram
u_ram
(
.clka_i(clk_i),
.rsta_i(rst_i),
.stba_i(imem_stb),
.wea_i(1'b0),
.sela_i(imem_sel),
.addra_i(imem_addr[31:2]),
.dataa_i(32'b0),
.dataa_o(imem_data),
.acka_o(imem_ack),
.clkb_i(clk_i),
.rstb_i(rst_i),
.stbb_i(dmem_stb),
.web_i(dmem_we),
.selb_i(dmem_sel),
.addrb_i(dmem_address[31:2]),
.datab_i(dmem_data_w),
.datab_o(dmem_data_r),
.ackb_o(dmem_ack)
);
cpu_if
#(
.CLK_KHZ(CLK_KHZ),
.BOOT_VECTOR(32'h10000000),
.ISR_VECTOR(32'h10000000),
.ENABLE_ICACHE(`ICACHE_ENABLED),
.ENABLE_DCACHE(`DCACHE_ENABLED),
.REGISTER_FILE_TYPE("SIMULATION")
)
u_cpu
(
// General - clocking & reset
.clk_i(clk_i),
.rst_i(rst_i),
.fault_o(fault_o),
.break_o(break_o),
.nmi_i(1'b0),
.intr_i(soc_irq),
// Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
.imem0_addr_o(imem_addr),
.imem0_data_i(imem_data),
.imem0_sel_o(imem_sel),
.imem0_cti_o(imem_cti),
.imem0_cyc_o(imem_cyc),
.imem0_stb_o(imem_stb),
.imem0_stall_i(1'b0),
.imem0_ack_i(imem_ack),
// Data Memory 0 (0x10000000 - 0x10FFFFFF)
.dmem0_addr_o(dmem_address),
.dmem0_data_o(dmem_data_w),
.dmem0_data_i(dmem_data_r),
.dmem0_sel_o(dmem_sel),
.dmem0_cti_o(dmem_cti),
.dmem0_cyc_o(dmem_cyc),
.dmem0_we_o(dmem_we),
.dmem0_stb_o(dmem_stb),
.dmem0_stall_i(1'b0),
.dmem0_ack_i(dmem_ack),
// Data Memory 1 (0x11000000 - 0x11FFFFFF)
.dmem1_addr_o(/*open*/),
.dmem1_data_o(/*open*/),
.dmem1_data_i(32'b0),
.dmem1_sel_o(/*open*/),
.dmem1_we_o(/*open*/),
.dmem1_stb_o(/*open*/),
.dmem1_cyc_o(/*open*/),
.dmem1_cti_o(/*open*/),
.dmem1_stall_i(1'b0),
.dmem1_ack_i(1'b1),
// Data Memory 2 (0x12000000 - 0x12FFFFFF)
.dmem2_addr_o(soc_addr),
.dmem2_data_o(soc_data_w),
.dmem2_data_i(soc_data_r),
.dmem2_sel_o(/*open*/),
.dmem2_we_o(soc_we),
.dmem2_stb_o(soc_stb),
.dmem2_cyc_o(/*open*/),
.dmem2_cti_o(/*open*/),
.dmem2_stall_i(1'b0),
.dmem2_ack_i(soc_ack)
);
// CPU SOC
soc
#(
.CLK_KHZ(CLK_KHZ),
.ENABLE_SYSTICK_TIMER("ENABLED"),
.ENABLE_HIGHRES_TIMER("ENABLED"),
.EXTERNAL_INTERRUPTS(1)
)
u_soc
(
// General - clocking & reset
.clk_i(clk_i),
.rst_i(rst_i),
.ext_intr_i(1'b0),
.intr_o(soc_irq),
.uart_tx_o(),
.uart_rx_i(1'b0),
// Memory Port
.io_addr_i(soc_addr),
.io_data_i(soc_data_w),
.io_data_o(soc_data_r),
.io_we_i(soc_we),
.io_stb_i(soc_stb),
.io_ack_o(soc_ack)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Module: ip_checksum_ttl.v
// Project: NF2.1 reference router
// Description: Check the IP checksum over the IP header, and
// generate a new one assuming that the TTL gets decremented.
// Check if the TTL is valid, and generate the new TTL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module ip_checksum_ttl
#(parameter DATA_WIDTH = 64)
(
//--- datapath interface
input [DATA_WIDTH-1:0] in_data,
input in_wr,
//--- interface to preprocess
input word_ETH_IP_VER,
input word_IP_LEN_ID,
input word_IP_FRAG_TTL_PROTO,
input word_IP_CHECKSUM_SRC_HI,
input word_IP_SRC_DST,
input word_IP_DST_LO,
// --- interface to process
output ip_checksum_vld,
output ip_checksum_is_good,
output ip_hdr_has_options,
output ip_ttl_is_good,
output [7:0] ip_new_ttl,
output [15:0] ip_new_checksum, // new checksum assuming decremented TTL
input rd_checksum,
// misc
input reset,
input clk
);
//---------------------- Wires and regs---------------------------
reg [19:0] checksum_word_0, checksum_word_1;
reg [19:0] in_word_0_0, in_word_0_1, in_word_0_2;
reg [19:0] in_word_1_0, in_word_1_1, in_word_1_2;
wire [19:0] next_sum_0, next_sum_1;
reg [16:0] adjusted_checksum;
reg checksum_done;
wire empty;
reg [7:0] ttl_new;
reg ttl_good;
reg hdr_has_options;
reg add_carry_1, add_carry_2;
//------------------------- Modules-------------------------------
fallthrough_small_fifo #(.WIDTH(27), .MAX_DEPTH_BITS(2))
arp_fifo
(.din ({&checksum_word_0[15:0], adjusted_checksum[15:0], ttl_good, ttl_new, hdr_has_options}), // {IP good, new checksum}
.wr_en (checksum_done), // Write enable
.rd_en (rd_checksum), // Read the next word
.dout ({ip_checksum_is_good, ip_new_checksum, ip_ttl_is_good, ip_new_ttl, ip_hdr_has_options}),
.full (),
.nearly_full (),
.prog_full (),
.empty (empty),
.reset (reset),
.clk (clk)
);
//------------------------- Logic -------------------------------
assign ip_checksum_vld = !empty;
/* MUX the additions to save adder logic */
assign next_sum_0 = in_word_0_0 + in_word_0_1 + in_word_0_2;
assign next_sum_1 = in_word_1_0 + in_word_1_1 + in_word_1_2;
always @(*) begin
in_word_0_0 = {4'h0, in_data[31:16]};
in_word_0_1 = {4'h0, in_data[15:0]};
in_word_0_2 = checksum_word_0;
in_word_1_0 = {4'h0, in_data[DATA_WIDTH-1:DATA_WIDTH-16]};
in_word_1_1 = {4'h0, in_data[DATA_WIDTH-17:DATA_WIDTH-32]};
in_word_1_2 = checksum_word_1;
if(word_ETH_IP_VER) begin
in_word_0_0 = 20'h0;
in_word_0_2 = 20'h0;
end
if(word_IP_DST_LO) begin
in_word_0_0 = {4'h0, in_data[DATA_WIDTH-1:DATA_WIDTH-16]};
in_word_0_1 = checksum_word_1;
end
if(add_carry_1 | add_carry_2) begin
in_word_0_0 = 20'h0;
in_word_0_1 = {16'h0, checksum_word_0[19:16]};
in_word_0_2 = {4'h0, checksum_word_0[15:0]};
end
if(word_IP_LEN_ID) begin
in_word_1_2 = 20'h0;
end
end // always @ (*)
// checksum logic. 16bit 1's complement over the IP header.
// --- see RFC1936 for guidance.
// 1's compl add: do a 2's compl add and then add the carry out
// as if it were a carry in.
// Final checksum (computed over the whole header incl checksum)
// is in checksum_a and valid when IP_checksum_valid is 1
// If checksum is good then it should be 0xffff
always @(posedge clk) begin
if(reset) begin
checksum_word_0 <= 20'h0; // does the addition for the low 32 bits
checksum_word_1 <= 20'h0; // does the addition for the high 32 bits
adjusted_checksum <= 17'h0; // calculates the new chksum
checksum_done <= 0;
add_carry_1 <= 0;
add_carry_2 <= 0;
ttl_new <= 0;
ttl_good <= 0;
hdr_has_options <= 0;
end
else begin
/* make sure the version is correct and there are no options */
if(word_ETH_IP_VER) begin
hdr_has_options <= (in_data[15:8]!=8'h45);
end
if(word_IP_FRAG_TTL_PROTO) begin
ttl_new <= (in_data[15:8]==8'h0) ? 8'h0 : in_data[15:8] - 1'b1;
ttl_good <= (in_data[15:8] > 8'h1);
end
if(word_ETH_IP_VER | word_IP_FRAG_TTL_PROTO | word_IP_SRC_DST |
word_IP_DST_LO | add_carry_1 | add_carry_2) begin
checksum_word_0 <= next_sum_0;
end
if(word_IP_LEN_ID | word_IP_CHECKSUM_SRC_HI) begin
checksum_word_1 <= next_sum_1;
end
// see RFC 1141
if(word_IP_CHECKSUM_SRC_HI) begin
adjusted_checksum <= {1'h0, in_data[DATA_WIDTH-1:DATA_WIDTH-16]} + 17'h0100; // adjust for the decrement in TTL
end
if(word_IP_DST_LO) begin
adjusted_checksum <= {1'h0, adjusted_checksum[15:0]} + adjusted_checksum[16];
add_carry_1 <= 1;
end
else begin
add_carry_1 <= 0;
end
if(add_carry_1) begin
add_carry_2 <= 1;
end
else begin
add_carry_2 <= 0;
end
if(add_carry_2) begin
checksum_done <= 1;
end
else begin
checksum_done <= 0;
end
// synthesis translate_off
// If we have any carry left in top 4 bits then algorithm is wrong
if (checksum_done && checksum_word_0[19:16] != 4'h0) begin
$display("%t %m ERROR: top 4 bits of checksum_word_0 not zero - algo wrong???",
$time);
#100 $stop;
end
// synthesis translate_on
end // else: !if(reset)
end // always @ (posedge clk)
endmodule // IP_checksum
|
`timescale 1 ns / 1 ps
//////////////////////////////////////////////////////////////////////////////////
// Company: TAMUQ University
// Engineers: Ali Aljaani
// part of this work was contributed by Ryan Kim,and Josh Sackos as a demo for the PmodOLED/Nexys3 board By Digilent Inc.
//
//
// Create Date: 06:13:25 08/18/2014
// Module Name: ZedboardOLED_v1_0_S00_AXI
// Project Name: ZedboardOLED
// Target Devices: Zynq
// Tool versions: Vivado 14.2 (64-bits)
// Description: The core is a slave AXI peripheral with 17 software-accessed registers.
// registers 0-16 are used for data, register 17 is the control register
//
// Revision: 1.0 - ZedboardOLED_v1_0_S00_AXI completed
// Revision 0.01 - File Created
//
//////////////////////////////////////////////////////////////////////////////////
module ZedboardOLED
(
//SPI Data In (MOSI)
output SDIN,
//SPI Clock
output SCLK,
//Data_Command Control
output DC,
//Power Reset
output RES,
//Battery Voltage Control - connected to field-effect transistors-active low
output VBAT,
// Logic Voltage Control - connected to field-effect transistors-active low
output VDD,
input wire CLK,
input wire [127:0] s1,
input wire [127:0] s2,
input wire [127:0] s3,
input wire [127:0] s4,
input wire clear,
input wire refresh
);
//Current overall state of the state machine
reg [143:0] current_state;
//State to go to after the SPI transmission is finished
reg [111:0] after_state;
//State to go to after the set page sequence
reg [142:0] after_page_state;
//State to go to after sending the character sequence
reg [95:0] after_char_state;
//State to go to after the UpdateScreen is finished
reg [39:0] after_update_state;
//Variable that contains what the screen will be after the next UpdateScreen state
reg [7:0] current_screen[0:3][0:15];
//Variable assigned to the SSD1306 interface
reg temp_dc = 1'b0;
reg temp_res = 1'b1;
reg temp_vbat = 1'b1;
reg temp_vdd = 1'b1;
assign DC = temp_dc;
assign RES = temp_res;
assign VBAT = temp_vbat;
assign VDD = temp_vdd;
//-------------- Variables used in the Delay Controller Block --------------
wire [11:0] temp_delay_ms; //amount of ms to delay
reg temp_delay_en = 1'b0; //Enable signal for the delay block
wire temp_delay_fin; //Finish signal for the delay block
assign temp_delay_ms = (after_state == "DispContrast1") ? 12'h074 : 12'h014;
//-------------- Variables used in the SPI controller block ----------------
reg temp_spi_en = 1'b0; //Enable signal for the SPI block
reg [7:0] temp_spi_data = 8'h00; //Data to be sent out on SPI
wire temp_spi_fin; //Finish signal for the SPI block
//-------------- Variables used in the characters libtray ----------------
reg [7:0] temp_char; //Contains ASCII value for character
reg [10:0] temp_addr; //Contains address to BYTE needed in memory
wire [7:0] temp_dout; //Contains byte outputted from memory
reg [1:0] temp_page; //Current page
reg [3:0] temp_index; //Current character on page
//-------------- Variables used in the reset and synchronization circuitry ----------------
reg init_first_r = 1'b1; // Initilaize only one time
reg clear_screen_i = 1'b1; // Clear the screen on start up
reg ready = 1'b0; // Ready flag
reg RST_internal =1'b1;
reg[11:0] count =12'h000;
wire RST_IN;
wire RST=1'b0; // dummy wire - can be connected as a port to provide external reset to the circuit
integer i = 0;
integer j = 0;
assign RST_IN = (RST || RST_internal);
//-------------- Core commands assignments start ----------------
reg Clear_c = 1'b0;
reg Display_c = 1'b0;
always @(posedge CLK) begin
Clear_c <= clear;
Display_c <= refresh;
end
//-------------- Core commands assignments end ----------------
// ===========================================================================
// Implementation
// ===========================================================================
SpiCtrl SPI_COMP(
.CLK(CLK),
.RST(RST_IN),
.SPI_EN(temp_spi_en),
.SPI_DATA(temp_spi_data),
.SDO(SDIN),
.SCLK(SCLK),
.SPI_FIN(temp_spi_fin)
);
Delay DELAY_COMP(
.CLK(CLK),
.RST(RST_IN),
.DELAY_MS(temp_delay_ms),
.DELAY_EN(temp_delay_en),
.DELAY_FIN(temp_delay_fin)
);
charLib CHAR_LIB_COMP(
.clka(CLK),
.addra(temp_addr),
.douta(temp_dout)
);
// State Machine
always @(posedge CLK) begin
if(RST_IN == 1'b1) begin
current_state <= "Idle";
temp_res <= 1'b0;
end
else begin
temp_res <= 1'b1;
case(current_state)
// Idle State
"Idle" : begin
if(init_first_r == 1'b1) begin
temp_dc <= 1'b0; // DC= 0 "Commands" , DC=1 "Data"
current_state <= "VddOn";
init_first_r <= 1'b0; // Don't go over the initialization more than once
end
else begin
current_state <="WaitRequest";
end
end
// Initialization Sequence
// This should be done only one time when Zedboard starts
"VddOn" : begin // turn the power on the logic of the display
temp_vdd <= 1'b0; // remember the power FET transistor for VDD is active low
current_state <= "Wait1";
end
// 3
"Wait1" : begin
after_state <= "DispOff";
current_state <= "Transition3";
end
// 4
"DispOff" : begin
temp_spi_data <= 8'hAE; // 0xAE= Set Display OFF
after_state <= "SetClockDiv1";
current_state <= "Transition1";
end
// 5
"SetClockDiv1" : begin
temp_spi_data <= 8'hD5; //0xD5
after_state <= "SetClockDiv2";
current_state <= "Transition1";
end
// 6
"SetClockDiv2" : begin
temp_spi_data <= 8'h80; // 0x80
after_state <= "MultiPlex1";
current_state <= "Transition1";
end
// 7
"MultiPlex1" : begin
temp_spi_data <= 8'hA8; //0xA8
after_state <= "MultiPlex2";
current_state <= "Transition1";
end
// 8
"MultiPlex2" : begin
temp_spi_data <= 8'h1F; // 0x1F
after_state <= "ChargePump1";
current_state <= "Transition1";
end
// 9
"ChargePump1" : begin // Access Charge Pump Setting
temp_spi_data <= 8'h8D; //0x8D
after_state <= "ChargePump2";
current_state <= "Transition1";
end
// 10
"ChargePump2" : begin // Enable Charge Pump
temp_spi_data <= 8'h14; // 0x14
after_state <= "PreCharge1";
current_state <= "Transition1";
end
// 11
"PreCharge1" : begin // Access Pre-charge Period Setting
temp_spi_data <= 8'hD9; // 0xD9
after_state <= "PreCharge2";
current_state <= "Transition1";
end
// 12
"PreCharge2" : begin //Set the Pre-charge Period
temp_spi_data <= 8'hFF; // 0xF1
after_state <= "VCOMH1";
current_state <= "Transition1";
end
// 13
"VCOMH1" : begin //Set the Pre-charge Period
temp_spi_data <= 8'hDB; // 0xF1
after_state <= "VCOMH2";
current_state <= "Transition1";
end
// 14
"VCOMH2" : begin //Set the Pre-charge Period
temp_spi_data <= 8'h40; // 0xF1
after_state <= "DispContrast1";
current_state <= "Transition1";
end
// 15
"DispContrast1" : begin //Set Contrast Control for BANK0
temp_spi_data <= 8'h81; // 0x81
after_state <= "DispContrast2";
current_state <= "Transition1";
end
// 16
"DispContrast2" : begin
temp_spi_data <= 8'hF1; // 0x0F
after_state <= "InvertDisp1";
current_state <= "Transition1";
end
// 17
"InvertDisp1" : begin
temp_spi_data <= 8'hA0; // 0xA1
after_state <= "InvertDisp2";
current_state <= "Transition1";
end
// 18
"InvertDisp2" : begin
temp_spi_data <= 8'hC0; // 0xC0
after_state <= "ComConfig1";
current_state <= "Transition1";
end
// 19
"ComConfig1" : begin
temp_spi_data <= 8'hDA; // 0xDA
after_state <= "ComConfig2";
current_state <= "Transition1";
end
// 20
"ComConfig2" : begin
temp_spi_data <= 8'h02; // 0x02
after_state <= "VbatOn";
current_state <= "Transition1";
end
// 21
"VbatOn" : begin
temp_vbat <= 1'b0;
current_state <= "Wait3";
end
// 22
"Wait3" : begin
after_state <= "ResetOn";
current_state <= "Transition3";
end
// 23
"ResetOn" : begin
temp_res <= 1'b0;
current_state <= "Wait2";
end
// 24
"Wait2" : begin
after_state <= "ResetOff";
current_state <= "Transition3";
end
// 25
"ResetOff" : begin
temp_res <= 1'b1;
current_state <= "WaitRequest";
end
// ************ END Initialization sequence but without turnning the dispay on ************
// Main state
"WaitRequest" : begin
if(Display_c == 1'b1) begin
current_state <= "ClearDC";
after_page_state <= "ReadRegisters";
temp_page <= 2'b00;
end
else if ((Clear_c==1'b1) || (clear_screen_i == 1'b1)) begin
current_state <= "ClearDC";
after_page_state <= "ClearScreen";
temp_page <= 2'b00;
end
else begin
current_state<="WaitRequest"; // keep looping in the WaitRequest state untill you receive a command
if ((clear_screen_i == 1'b0) && (ready ==1'b0)) begin // this part is only executed once, on start-up
temp_spi_data <= 8'hAF; // 0xAF // Dispaly ON
after_state <= "WaitRequest";
current_state <= "Transition1";
temp_dc<=1'b0;
ready <= 1'b1;
//Display_c <= 1'b1;
end
end
end
//Update Page states
//1. Sets DC to command mode
//2. Sends the SetPage Command
//3. Sends the Page to be set to
//4. Sets the start pixel to the left column
//5. Sets DC to data mode
"ClearDC" : begin
temp_dc <= 1'b0;
current_state <= "SetPage";
end
"SetPage" : begin
temp_spi_data <= 8'b00100010;
after_state <= "PageNum";
current_state <= "Transition1";
end
"PageNum" : begin
temp_spi_data <= {6'b000000,temp_page};
after_state <= "LeftColumn1";
current_state <= "Transition1";
end
"LeftColumn1" : begin
temp_spi_data <= 8'b00000000;
after_state <= "LeftColumn2";
current_state <= "Transition1";
end
"LeftColumn2" : begin
temp_spi_data <= 8'b00010000;
after_state <= "SetDC";
current_state <= "Transition1";
end
"SetDC" : begin
temp_dc <= 1'b1;
current_state <= after_page_state;
end
"ClearScreen" : begin
for(i = 0; i <= 3 ; i=i+1) begin
for(j = 0; j <= 15 ; j=j+1) begin
current_screen[i][j] <= 8'h20;
end
end
after_update_state <= "WaitRequest";
current_state <= "UpdateScreen";
end
"ReadRegisters" : begin
// Page0
current_screen[0][15]<=s1[7:0];
current_screen[0][14]<=s1[15:8];
current_screen[0][13]<=s1[23:16];
current_screen[0][12]<=s1[31:24];
current_screen[0][11]<=s1[39:32];
current_screen[0][10]<=s1[47:40];
current_screen[0][9]<=s1[55:48];
current_screen[0][8]<=s1[63:56];
current_screen[0][7]<=s1[71:64];
current_screen[0][6]<=s1[79:72];
current_screen[0][5]<=s1[87:80];
current_screen[0][4]<=s1[95:88];
current_screen[0][3]<=s1[103:96];
current_screen[0][2]<=s1[111:104];
current_screen[0][1]<=s1[119:112];
current_screen[0][0]<=s1[127:120];
current_screen[1][15]<=s2[7:0];
current_screen[1][14]<=s2[15:8];
current_screen[1][13]<=s2[23:16];
current_screen[1][12]<=s2[31:24];
current_screen[1][11]<=s2[39:32];
current_screen[1][10]<=s2[47:40];
current_screen[1][9]<=s2[55:48];
current_screen[1][8]<=s2[63:56];
current_screen[1][7]<=s2[71:64];
current_screen[1][6]<=s2[79:72];
current_screen[1][5]<=s2[87:80];
current_screen[1][4]<=s2[95:88];
current_screen[1][3]<=s2[103:96];
current_screen[1][2]<=s2[111:104];
current_screen[1][1]<=s2[119:112];
current_screen[1][0]<=s2[127:120];
current_screen[2][15]<=s3[7:0];
current_screen[2][14]<=s3[15:8];
current_screen[2][13]<=s3[23:16];
current_screen[2][12]<=s3[31:24];
current_screen[2][11]<=s3[39:32];
current_screen[2][10]<=s3[47:40];
current_screen[2][9]<=s3[55:48];
current_screen[2][8]<=s3[63:56];
current_screen[2][7]<=s3[71:64];
current_screen[2][6]<=s3[79:72];
current_screen[2][5]<=s3[87:80];
current_screen[2][4]<=s3[95:88];
current_screen[2][3]<=s3[103:96];
current_screen[2][2]<=s3[111:104];
current_screen[2][1]<=s3[119:112];
current_screen[2][0]<=s3[127:120];
current_screen[3][15]<=s4[7:0];
current_screen[3][14]<=s4[15:8];
current_screen[3][13]<=s4[23:16];
current_screen[3][12]<=s4[31:24];
current_screen[3][11]<=s4[39:32];
current_screen[3][10]<=s4[47:40];
current_screen[3][9]<=s4[55:48];
current_screen[3][8]<=s4[63:56];
current_screen[3][7]<=s4[71:64];
current_screen[3][6]<=s4[79:72];
current_screen[3][5]<=s4[87:80];
current_screen[3][4]<=s4[95:88];
current_screen[3][3]<=s4[103:96];
current_screen[3][2]<=s4[111:104];
current_screen[3][1]<=s4[119:112];
current_screen[3][0]<=s4[127:120];
after_update_state <= "WaitRequest";
current_state <= "UpdateScreen";
end
//UpdateScreen State
//1. Gets ASCII value from current_screen at the current page and the current spot of the page
//2. If on the last character of the page transition update the page number, if on the last page(3)
// then the updateScreen go to "after_update_state" after
"UpdateScreen" : begin
temp_char <= current_screen[temp_page][temp_index];
if(temp_index == 'd15) begin
temp_index <= 'd0;
temp_page <= temp_page + 1'b1;
after_char_state <= "ClearDC";
if(temp_page == 2'b11) begin
after_page_state <= after_update_state;
clear_screen_i<=1'b0;
end
else begin
after_page_state <= "UpdateScreen";
end
end
else begin
temp_index <= temp_index + 1'b1;
after_char_state <= "UpdateScreen";
end
current_state <= "SendChar1";
end
//Send Character States
//1. Sets the Address to ASCII value of char with the counter appended to the end
//2. Waits a clock for the data to get ready by going to ReadMem and ReadMem2 states
//3. Send the byte of data given by the block Ram
//4. Repeat 7 more times for the rest of the character bytes
"SendChar1" : begin
temp_addr <= {temp_char, 3'b000};
after_state <= "SendChar2";
current_state <= "ReadMem";
end
"SendChar2" : begin
temp_addr <= {temp_char, 3'b001};
after_state <= "SendChar3";
current_state <= "ReadMem";
end
"SendChar3" : begin
temp_addr <= {temp_char, 3'b010};
after_state <= "SendChar4";
current_state <= "ReadMem";
end
"SendChar4" : begin
temp_addr <= {temp_char, 3'b011};
after_state <= "SendChar5";
current_state <= "ReadMem";
end
"SendChar5" : begin
temp_addr <= {temp_char, 3'b100};
after_state <= "SendChar6";
current_state <= "ReadMem";
end
"SendChar6" : begin
temp_addr <= {temp_char, 3'b101};
after_state <= "SendChar7";
current_state <= "ReadMem";
end
"SendChar7" : begin
temp_addr <= {temp_char, 3'b110};
after_state <= "SendChar8";
current_state <= "ReadMem";
end
"SendChar8" : begin
temp_addr <= {temp_char, 3'b111};
after_state <= after_char_state;
current_state <= "ReadMem";
end
"ReadMem" : begin
current_state <= "ReadMem2";
end
"ReadMem2" : begin
temp_spi_data <= temp_dout;
current_state <= "Transition1";
end
// SPI transitions
// 1. Set SPI_EN to 1
// 2. Waits for SpiCtrl to finish
// 3. Goes to clear state (Transition5)
"Transition1" : begin
temp_spi_en <= 1'b1;
current_state <= "Transition2";
end
"Transition2" : begin
if(temp_spi_fin == 1'b1) begin
current_state <= "Transition5";
end
end
// Delay Transitions
// 1. Set DELAY_EN to 1
// 2. Waits for Delay to finish
// 3. Goes to Clear state (Transition5)
"Transition3" : begin
temp_delay_en <= 1'b1;
current_state <= "Transition4";
end
"Transition4" : begin
if(temp_delay_fin == 1'b1) begin
current_state <= "Transition5";
end
end
// Clear transition
// 1. Sets both DELAY_EN and SPI_EN to 0
// 2. Go to after state
"Transition5" : begin
temp_spi_en <= 1'b0;
temp_delay_en <= 1'b0;
current_state <= after_state;
end
default : current_state <= "Idle";
endcase
end
end
// Internal reset generator
always @(posedge CLK) begin
if (RST_IN == 1'b1)
count<=count+1'b1;
if (count == 12'hFFF) begin
RST_internal <=1'b0;
end
end
endmodule
|
// megafunction wizard: %ROM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: jump_ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module jump_ram (
address_a,
address_b,
clock,
rden_a,
rden_b,
q_a,
q_b);
input [4:0] address_a;
input [4:0] address_b;
input clock;
input rden_a;
input rden_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden_a;
tri1 rden_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "jump_ram.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INIT_FILE STRING "jump_ram.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 5 0 INPUT NODEFVAL "address_a[4..0]"
// Retrieval info: USED_PORT: address_b 0 0 5 0 INPUT NODEFVAL "address_b[4..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
// Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a"
// Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b"
// Retrieval info: CONNECT: @address_a 0 0 5 0 address_a 0 0 5 0
// Retrieval info: CONNECT: @address_b 0 0 5 0 address_b 0 0 5 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 GND 0 0 16 0
// Retrieval info: CONNECT: @data_b 0 0 16 0 GND 0 0 16 0
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0
// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL jump_ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL jump_ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL jump_ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL jump_ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL jump_ram_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL jump_ram_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_1_V
`define SKY130_FD_SC_LP__A2BB2O_1_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2bb2o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2o_1 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2o_1 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_1_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_pcie_bram_top_7x.v
// Version : 1.11
// Description : bram wrapper for Tx and Rx
// given the pcie block attributes calculate the number of brams
// and pipeline stages and instantiate the brams
//
// Hierarchy:
// pcie_bram_top top level
// pcie_brams pcie_bram instantiations,
// pipeline stages (if any),
// address decode logic (if any),
// datapath muxing (if any)
// pcie_bram bram library cell wrapper
// the pcie_bram module can have a paramter that
// specifies the family (V6, V5, V4)
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
module PCIEBus_pcie_bram_top_7x
#(
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0, // MPS Supported : 0 - 128 B, 1 - 256 B, 2 - 512 B, 3 - 1024 B
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter VC0_TX_LASTPACKET = 31, // Number of Packets in Transmit
parameter TLM_TX_OVERHEAD = 24, // Overhead Bytes for Packets (Transmit)
parameter TL_TX_RAM_RADDR_LATENCY = 1, // BRAM Read Address Latency (Transmit)
parameter TL_TX_RAM_RDATA_LATENCY = 2, // BRAM Read Data Latency (Transmit)
parameter TL_TX_RAM_WRITE_LATENCY = 1, // BRAM Write Latency (Transmit)
parameter VC0_RX_RAM_LIMIT = 'h1FFF, // RAM Size (Receive)
parameter TL_RX_RAM_RADDR_LATENCY = 1, // BRAM Read Address Latency (Receive)
parameter TL_RX_RAM_RDATA_LATENCY = 2, // BRAM Read Data Latency (Receive)
parameter TL_RX_RAM_WRITE_LATENCY = 1 // BRAM Write Latency (Receive)
)
(
input user_clk_i, // Clock input
input reset_i, // Reset input
input mim_tx_wen, // Write Enable for Transmit path BRAM
input [12:0] mim_tx_waddr, // Write Address for Transmit path BRAM
input [71:0] mim_tx_wdata, // Write Data for Transmit path BRAM
input mim_tx_ren, // Read Enable for Transmit path BRAM
input mim_tx_rce, // Read Output Register Clock Enable for Transmit path BRAM
input [12:0] mim_tx_raddr, // Read Address for Transmit path BRAM
output [71:0] mim_tx_rdata, // Read Data for Transmit path BRAM
input mim_rx_wen, // Write Enable for Receive path BRAM
input [12:0] mim_rx_waddr, // Write Enable for Receive path BRAM
input [71:0] mim_rx_wdata, // Write Enable for Receive path BRAM
input mim_rx_ren, // Read Enable for Receive path BRAM
input mim_rx_rce, // Read Output Register Clock Enable for Receive path BRAM
input [12:0] mim_rx_raddr, // Read Address for Receive path BRAM
output [71:0] mim_rx_rdata // Read Data for Receive path BRAM
);
// TX calculations
localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 2) ? 512 :
1024 );
localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD);
localparam ROWS_TX = 1;
localparam COLS_TX = ((BYTES_TX <= 4096) ? 1 :
(BYTES_TX <= 8192) ? 2 :
(BYTES_TX <= 16384) ? 4 :
(BYTES_TX <= 32768) ? 8 :
18
);
// RX calculations
localparam ROWS_RX = 1;
localparam COLS_RX = ((VC0_RX_RAM_LIMIT < 'h0200) ? 1 :
(VC0_RX_RAM_LIMIT < 'h0400) ? 2 :
(VC0_RX_RAM_LIMIT < 'h0800) ? 4 :
(VC0_RX_RAM_LIMIT < 'h1000) ? 8 :
18
);
initial begin
$display("[%t] %m ROWS_TX %0d COLS_TX %0d", $time, ROWS_TX, COLS_TX);
$display("[%t] %m ROWS_RX %0d COLS_RX %0d", $time, ROWS_RX, COLS_RX);
end
PCIEBus_pcie_brams_7x #(
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.IMPL_TARGET ( IMPL_TARGET ),
.NUM_BRAMS ( COLS_TX ),
.RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY )
)
pcie_brams_tx (
.user_clk_i ( user_clk_i ),
.reset_i ( reset_i ),
.waddr ( mim_tx_waddr ),
.wen ( mim_tx_wen ),
.ren ( mim_tx_ren ),
.rce ( mim_tx_rce ),
.wdata ( mim_tx_wdata ),
.raddr ( mim_tx_raddr ),
.rdata ( mim_tx_rdata )
);
PCIEBus_pcie_brams_7x #(
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.IMPL_TARGET ( IMPL_TARGET ),
.NUM_BRAMS ( COLS_RX ),
.RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY )
) pcie_brams_rx (
.user_clk_i ( user_clk_i ),
.reset_i ( reset_i ),
.waddr ( mim_rx_waddr ),
.wen ( mim_rx_wen ),
.ren ( mim_rx_ren ),
.rce ( mim_rx_rce ),
.wdata ( mim_rx_wdata ),
.raddr ( mim_rx_raddr ),
.rdata ( mim_rx_rdata )
);
endmodule // pcie_bram_top
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD1_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DLYGATE4SD1_BEHAVIORAL_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlygate4sd1 (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD1_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTN_4_V
`define SKY130_FD_SC_HDLL__DLRTN_4_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlrtn_4 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlrtn_4 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTN_4_V
|
Require Export ZArith.
Require Export Arith.
Require Export Bool.
Open Scope Z_scope.
Check 100104.
Locate "_ * _".
Print Scope Z_scope.
Check 33%nat.
Check 0%nat.
Check O.
Open Scope nat_scope.
Check 33.
Check 0.
Check 33%Z.
Check (-12)%Z.
Open Scope Z_scope.
Check (-12).
Check (33%nat).
Check true.
Check false.
Check plus.
Check Zplus.
Check negb.
Check orb.
Check (negb true).
Check (negb (negb true)).
Check (((ifb (negb false)) true) false).
Open Scope nat_scope.
Check (S (S (S O))).
Check (mult (mult 5 (minus 5 4)) 7).
Check (5*(5-4)*7).
Check (S 3).
Check ((mult (mult (S (S (S (S (S O)))))
(minus (S (S (S (S (S O)))))(S (S (S (S O))))))
(S (S (S (S (S (S (S O))))))))).
Open Scope Z_scope.
Check (Zopp (Zmult 3 (Zminus (-5)(-8)))).
Check ((-4)*(7-7)).
Open Scope nat_scope.
Check (plus 3).
Check (Zmult (-5)).
Check Zabs_nat.
Check (5 + Zabs_nat (5-19)).
Check (fun n:nat => fun p:nat => fun z:Z => (Z_of_nat(n+p)+z)%Z).
Check (fun n p:nat => fun z:Z => (Z_of_nat(n+p)+z)%Z).
Check (fun (n p:nat)(z:Z) => (Z_of_nat(n+p)+z)%Z).
Check (fun a b c:Z => (b*b-4*a*c)%Z).
Check (fun (f g:nat->nat)(n:nat) => g (f n)).
Check (fun n (z:Z) f => (n+(Zabs_nat (f z)))%nat).
Check (fun n _:nat => n).
Check (fun n p:nat => p).
Check (fun n p : nat =>
(let diff := n-p in
let square := diff*diff in
square * (square+n))%nat).
Definition t1 :=
fun n:nat => let s := plus n (S n) in mult n (mult s s).
Check (fun i : nat =>
let sum := plus i (S i) in mult i (mult sum sum)).
Check (fun n : nat =>
let n := plus n (S n) in mult n (mult n n)).
Parameter max_int : Z.
Open Scope Z_scope.
Definition min_int := 1-max_int.
Print min_int.
Definition cube := fun z:Z => z*z*z.
Reset cube.
Definition cube (z:Z) : Z := z*z*z.
Print cube.
Definition Z_thrice (f:Z->Z)(z:Z) := f (f (f z)).
Definition plus9 := Z_thrice (Z_thrice (fun z:Z => z+1)).
Section binomial_def.
Variables a b:Z.
Definition binomial z:Z := a*z + b.
Section trinomial_def.
Variable c : Z.
Definition trinomial z:Z := (binomial z)*z + c.
End trinomial_def.
End binomial_def.
Print binomial.
Print trinomial.
Definition p1 : Z->Z := binomial 5 (-3).
Definition p2 : Z->Z := trinomial 1 0 (-1).
Definition p3 := trinomial 1 (-2) 1.
Section mab.
Variables m a b:Z.
Definition f := m*a*m.
Definition g := m*(a+b).
End mab.
Print f.
Print g.
Section h_def.
Variables a b:Z.
Let s:Z := a+b.
Let d:Z := a-b.
Definition h : Z := s*s + d*d.
End h_def.
Print h.
Definition Zsqr (z:Z) : Z := z*z.
Definition my_fun (f:Z->Z)(z:Z) : Z := f (f z).
Eval cbv delta [my_fun Zsqr] in (my_fun Zsqr).
Eval cbv delta [my_fun] in (my_fun Zsqr).
Check ((fun (f:Z->Z)(z:Z) => f (f z))(fun (z:Z) => z*z)).
Check ( fun z:Z =>
(fun z1:Z => z1*z1)((fun z0:Z => z0*z0) z)).
Check( fun z:Z => (fun z1:Z => z1*z1)(z*z)).
Check ( fun z:Z => z*z*(z*z)).
Eval cbv beta delta [my_fun Zsqr] in (my_fun Zsqr).
Eval cbv beta delta [h] in (h 56 78).
Eval cbv beta zeta delta [h] in (h 56 78).
Eval compute in (h 56 78).
Eval compute in (my_fun Zsqr 3).
Check Z.
Check ((Z->Z)->nat->nat).
Check Set.
Check Type.
Definition Z_bin : Set := Z->Z->Z.
Check (fun z0 z1:Z => let d := z0-z1 in d*d).
Definition Zdist2 (z z0:Z) := let d := z-z0 in d*d.
Check (nat->nat).
Check (nat->nat:Type).
Section realization.
Variables (A B :Set).
Let spec : Set := (((A->B)->B)->B)->A->B.
Let realization : spec
:= fun (f:((A->B)->B)->B) a => f (fun g => g a).
End realization.
Definition nat_fun_to_Z_fun : Set := (nat->nat)->Z->Z.
Definition absolute_fun : nat_fun_to_Z_fun :=
fun f z => Z_of_nat (f (Zabs_nat z)).
Definition always_0 : nat_fun_to_Z_fun :=
fun _ _ => 0%Z.
Definition to_marignan : nat_fun_to_Z_fun :=
fun _ _ => 1515%Z.
Definition ignore_f : nat_fun_to_Z_fun :=
fun _ z => z.
Definition from_marignan : nat_fun_to_Z_fun :=
fun f _ => Z_of_nat (f 1515%nat).
Check and.
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